CCVPX-16AI32SSC1M
32-Channel, Differential, 16-Bit Simultaneous Sampling;
Conduction-Cooled VPX Analog Input Board
With 1.0MSPS Sample Rate per Channel,Time-tagging, Low-latency access,and Front-Panel I/O 32 Differential analog inputs with dedicated 1.0MSPS 16-Bit ADC per channel
 Sampling rates to 1.0MSPS per channel
 Simultaneous sampling of all inputs; Minimum data skew
 Software-Selectable Input ranges: ±10V, ±5V, ±2.5V or ±1.25V
 Standard conduction-cooled 3U VPX form Factor
 Front-Panel system I/O access Sync and clock I/O support external control and multiboard configurations
 Time Tagging attaches time information to each input data value
 Low Latency provides 32 registers that duplicate the most recent samples from all channels
 Increased throughput capacity with local data packing
 Continuous, burst and single-sample clocking modes Hardware sync I/O for multiboard operation
 1 MByte FIFO data buffer; 512 K-Samples in packed-data mode.
 2-Channel DMA engine
 Conforms to PCI Express Specification revision 1.0a; x1 Link operating at 2.5Gbps
 Sample rate controlled by internal rate generators, by software triggering, or externally On-Demand internal Autocalibration of all channels

High-Density Analog Inputs
Analog Event CaptureIndustrial Robotics
Crash AnalysisAcoustic Sensor Arrays
Dynamic Test Systems--- PRELIMINARY --Rev: 012617

8302A Whitesburg Drive · Huntsville, AL 35802
Phone: (256) 880-8787 or (800) 653-9970 FAX: (256) 880-8788 Email: Solutions@GeneralStandards.com

CCVPX-16AI32SSC1M Preliminary

The conduction-cooled CCVPX-16AI32SSC1M analog input board provides 32 precision
16-Bit analog input channels on a standard 3U VPX module. All 32 inputs can be sampled
simultaneously at rates from zero to 1MSPS, and the input range can be software-selected
as ±10V, ±5V, ±2.5V or ±1.25V. Each channel contains a dedicated 16-Bit sampling ADC, adifferential input amplifier, and selftest input switches. Converted input data is available tothe host bus through a 1-MByte FIFO buffer. The 32-Bit local data path supports full D32
local-bus data packing, or data can be accessed through low-latency data registers.
Selectable Time Tagging attaches time information to each input data value. The board
supports standard conduction-cooling.
Inputs can be sampled in groups of 2, 4, 8, 16 or 32 channels; or any contiguous channelgroup can be selected for sampling. Triggered bursts are supported. The sample clock canbe generated from an internal rate generator, or by software, or by external hardware.
On-demand autocalibration determines offset and gain correction values for each input
channel, and applies the corrections subsequently during acquisition. A selftest switching
network routes calibration reference signals to each channel through internal selftest
switches, and permits board integrity to be verified by the host.

Input
Conn

Channel-00: One of 32 Identical Input Channels
Input
Vref

32 Diff
Analog Inputs

Selftest
SwitchDiff Amp

16-BitADC

Input Channels 01-31

Ext Sync
Local
Controller

Host Conn(PCI Express)+3.3VDC+12VDCPower
Conversion

Regulated
Power Voltages
Data
BufferVref

PCI Express
Interface
Adapter

Local Bus

Figure 1. CCVPX-16AI32SSC1M; Functional Organization
This product conforms to the VPX baseline standard ANSI/VITA 46.0-2007 (R2013).
Systemconnections are made at the front panel through a high-density front-panel I/O connector. Powerrequirements consist of +12VDC and +3.3VDC in compliance with the VPX specification, and operation
over the specified temperature range is achieved with standard conduction cooling.
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CCVPX-16AI32SSC1M Preliminary

At +25 OC, with specified operating conditions, and with differential processing deselected

Input Characteristics:
Configuration:

32 differential analog input channels. 16-Channel version available.

Voltage Ranges:

Software configurable as ±10V, ±5V, ±2.5V or ±1.25V fullscale

Input Impedance:

2.0 Megohms typical, line-line. 1.0 Megohms line-ground..

Bias Current:

100nA maximum.

Common Mode Rejection:

80dB on ±10V range; 85dB on ±1.25V range; typical, DC-50kHz

Min/Max Input Levels
for rated performance:±11V

Crosstalk Rejection:

85dB typical, DC-50kHz

Input Noise:

0.4mVRMS, ±10V Range; 0.15mVRMS, ±2.5V Range; typical, 0.01-250kHz

Overvoltage Protection:

Sustained ±15 Volts with power removed; ±30V with power applied

Transfer Characteristics:
Conversion Resolution:

16 Bits (0.0015 percent of FSR)

Sample Rate:

Zero to 1,000 KSPS per channel

Input Bandwidth (-3dB):

DC to 400 kHz typical

Channels per Sample:

1-32

DC Accuracy:(Maximum composite error
after autocalibration)

Range
±10V
±5V
±2.5V
±1.25V

Integral Nonlinearity:±0.008 percent of FSR, maximum

Differential Nonlinearity:±0.004 percent of FSR, maximum

Zero-Input± 1.5mv± 1.4mv± 1.1mv± 0.9mv

Fullscale± 2.8mv± 2.5mv± 1.8mv± 1.6mv

Analog Input Operating Modes and Controls
Input Data Buffer:

Sample Clock Sources:
Rate Generator:

External TTL Sync, Clock:
Input Data Format:

Data Format:
Low Latency:
Time Tagging:

FIFO; 1 Megabyte. 256 K-Samples in normal (16-Bit) mode; 512 K-samples inpacked-data mode. A 'Low-Latency' array of 32 data registers is available inaddition to the FIFO buffer.
Internal rate generator; External Hardware Sync I/O, Software clock. Continuous,Burst and Single-Sample Clocking Modes.
Two rate generators provide sample rates from 0.016-1,000,000 sample clocks per
second, by dividing the local master clock to the sample rate. (The standard masterclock frequency is 64MHz. See ordering information for custom frequencies.)
Bidirectional TTL lines; available through the I/O connector, or through a 6-pin SyncI/O connector located on the back of the board.
Nonpacked Mode: 16-Bit data word plus single-bit Channel-00 tag.
Packed Mode:
Lword sync code followed by packed channel data.
Even-numbered channels occupy lower word (D00-15), odd
channels occupy upper word (D16-31).
Selectable as offset binary or two's complement.
In addition to the FIFO buffer, 32 data registers are directly accessible for minimum
latency.
48-Bit 1-microsecond time stamping ('tagging') and windowed burst triggering.

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CCVPX-16AI32SSC1M Preliminary

Host Bus Compatibility:
Conforms to VPX VITA 46.0.
Also conforms to PCI Express Specification revision 1.0a; x1 Link operating at 2.5Gbps.
DMA transfers as bus master with two DMA channels.

Power Requirements:+3.3VDC ±0.2 VDC, 1.4 Amps typical, 1.6 Amp maximum.
+12VDC ±0.4 VDC, 0.5 Amps typical, 0.6 Amps maximum
Total power consumption:10.0 Watts typical, 12.5 Watts maximum.

Mechanical Characteristics
Height:18.8mm (0.74 in)
Depth:
170.6 mm (6.717 in)
Width:
100.0 mm (3.937 in)Shield:Side-1 is protected by an EMI shield.
Thermal transfer rails are provided for conduction cooling.

Environmental Specifications
Ambient Temperature Range:

Operating: 0 to +80 Degrees Celsius inlet airStorage: -40 to +85 Degrees Celsius

Relative Humidity:

Operating and Storage: 0 to 95%, non-condensing

Altitude:Operation to 10,000 ft.

Cooling:Standard conduction cooling thermal interfaces.

Specify the basic product model number followed by an option suffix "-A-B-C", as indicated below.
For example, model number CCVPX-16AI32SSC1M-32-64M-0 describes a board with 32 input channels, astandard 64.000MHz master clock frequency, and no custom features.
All versions provide time-tagging and low-latency functions as standard features.
Optional Parameter
Number of Input Channels

Master Clock Frequency:

Custom Feature

Value

Specify Option As:

32 Channels

A = 3216 Channels

A = 1664.000 MHz (Standard)

B = 64M

Specify custom frequency; 64-66 MHz *B = (Custom frequency)M

No custom features

C=0* Frequencies other than the standard frequency will cause proportionate variations in the sample rate.

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CCVPX-16AI32SSC1M Preliminary

Table 1. System I/O Connector Pin Functions
PinSignal

Pin

434241403938
37363534333231302928272625242322212019
18
1716151413
12111098765432

INPUT RTN
INPUT RTN
INP 00 LO
INP 01 LO
INP 02 LO
INP 03 LO
INP 04 LO
INP 05 LO
INP 06 LO
INP 07 LO
INPUT RTN
INP 08 LO
INP 09 LO
INP 10 LO
INP 11 LO
INP 12 LO
INP 13 LO
INP 14 LO
INP 15 LO
INPUT RTN
INP 16 LO
INP 17 LO
INP 18 LO
INP 19 LO
INP 20 LO
INP 21 LO
INP 22 LO
INP 23 LO
INPUT RTN
INP 24 LO
INP 25 LO
INP 26 LO
INP 27 LO
INP 28 LO
INP 29 LO
INP 30 LO
INP 31 LO
INPUT RTN
DIG RTNDIG RTNDIG RTNDIG RTN--8584838281807978777675747372717069686766656463626160595857565554535251504948474645112

DIG RTN

44Signal--INPUT RTN
INP 00 HI
INP 01 HI
INP 02 HI
INP 03 HI
INP 04 HI
INP 05 HI
INP 06 HI
INP 07 HI
INPUT RTN
INP 08 HI
INP 09 HI
INP 10 HI
INP 11 HI
INP 12 HI
INP 13 HI
INP 14 HI
INP 15 HI
INPUT RTN
INP 16 HI
INP 17 HI
INP 18 HI
INP 19 HI
INP 20 HI
INP 21 HI
INP 22 HI
INP 23 HI
INPUT RTN
INP 24 HI
INP 25 HI
INP 26 HI
INP 27 HI
INP 28 HI
INP 29 HI
INP 30 HI
INP 31 HI
INPUT RTN
DIG RTN
CLOCK RST INPREF CLK INP
1SYNC I/O or SAMP CLK OUTDefault configuration. Not software-configured for time tagging.
If software-configured for time tagging.

PIN 44

PIN 43PWB

PIN 85

Panel Pin-view

Figure 2. System I/O Connector

System I/O Mating Connector:
Omnetics # MNPO-85-DD-N-EJS-C,
dual-row, straight tail.
(Assembled cables available)

Table
2. 2.Sync-I/O
Pin
Functions
Table
Sync-I/O
Pin
Functions
SYNC-I/O
Conn Pin
1SignalDIG RTN2AUX CLOCK3

DIG RTN24

AUX SYNC

25

DIG RTN

6Reserved. Connect to
INPUT RTN or leavedisconnected.

CLOCK I/O or SAMP CLK INP1PIN 1

Recommended Sync-I/O mating
connector: Molex# 51146-0600.

General Standards Corporation assumes no responsibility for the use of any circuits in this product. No circuit patent licenses are implied.
Information included herein supersedes previously published specifications on this product and is subject to change without notice.

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