DATASHEETVP460

6U VPX Direct RF Processing System with Xilinx Zynq Ultrascale+ RFSoC
The VP460 is a 6U VPX RF processing system
featuring the transformational Xilinx® Zynq®
Ultrascale+™ RF system-on-chip technology(RFSoC) and the latest Xilinx Virtex™ Ultrascale+High Bandwidth Memory (HBM) FPGA device. The
RFSoC ZU29DR device used on the VP460 includes
16 integrated analog-to-digital converters at 2GSPS,
16 digital-to-analog converters at 6.4 GSPS, a userprogrammable FPGA fabric, and multi-core Zynq
ARM® processing subsystem. The HBM VU37P
device features the speed and capabilities of an
UltraScale+ FPGA plus integrated DRAM in the FPGA
package capable of up to 460GB/s data transfer rates
on -chip.

Reduce RF Signal Chain Complexity
RF systems with multiple channels suffer from acost- and complexity challenge. More channels
means more expensive and large RF signal up/down
conversion and signal conditioning. As a solution,
the VP460 enables direct RF sampling which can be
implemented in the digital domain, bringing greater
flexibility to the signal processing chain. Additionally,
simplified integration with RF sampling devices
removes the complexity of JESD204B high speed
serial interfaces.

Maximize Input/Output Channel Density
The VP460 is one of the densest 6U VPX analog
FPGA carrier boards available with the ability tosynchronize all 16 channels as well as multiple boards
for even larger system applications. In previous

generations of technology, this combination would
have taken four times as many boards.

Revolutionary processing capability
The VP460 is a revolution in COTS RF and FPGA
processing, perfectly balancing the need for highperformance FPGA processing, the ease of ahardened embedded processor and the ultralow latency of integrated analog interfaces. The
revolutionary RF and DSP technology enables a user
to create the most advanced multi-channel electronic
warfare systems, radar, and SDR applications today.

Offload Data More Efficiently
The VP460 has a traditonal VPX data plane interface,allowing a x8 PCIe™ Gen3 connection to a hostcomputer. With 16 ADCs sampling at rates up to2GSPS with two bytes per sample, even the modern
PCIe Gen 3 high speed data connection is too slowfor a direct transfer. To overcome this challenge, theVP460 includes – in addition to the PCIe Gen3 data
plane - up to 48 high speed serial lanes to the Xilinx
Virtex Ultrascale+ HBM device supporting protocols
such as PCIe Gen3, 10G Ethernet, Aurora, etc.
The VP460 is designed to be air-cooled. When pairedwith Abaco’s extensive portfolio of multi-architecture
processing boards including SBCs and GPGPUs, thestate-of-the-art VP460 enables systems to be built
from leading edge, interoperable components.

FEATURES:• Dual FPGA Architecture:-- Zynq UltraScale+ RFSoC-- Virtex UltraScale+ HBM• ADC 16 channels 2 GSPS 12-bit• DAC 16 channel 6.4 GSPS 14-bit• Independent clock generation
circuit for the ADC and DAC frontends• Application Processing Unit-- Quad-core ARM Cortex-A53• Real-Time Processing Unit-- Dual-core ARM Cortex-R5• Up to 8 GB DDR4 memory
available to the RFSoC• Up to 12 GB DDR4 memory
available to the Virtex
UltraScale+-- 8 GB integrated on the device-- Up to 460 GB/s transfer rates
with integrated DRAM
• VITA 57.4 FMC+ site available tothe Virtex UltraScale+ HBM• PCIe Gen3 x 16 from HBM tothe backplane and x8 from theRFSoC• Low latency, high bandwidthparallel data bus between theZynq UltraScale+ RFSoC andVirtex UltraScale+ HBM devices• User I/O to backplane RTM-- DisplayPort™ 1.2a-- SATA 3.1-- USB 3.0-- Gigabit Ethernet• Linux® and Windows® BSP
available• SOSA Backplane Option

DATASHEETVP460 6U VPX Direct RF Processing System with Xilinx Zynq Ultrascale+ RFSoC ﻿Specifications

Block diagram

Processing/FPGA• Xilinx ZU29DUR Zynq UltraScale+ RFSoC• Xilinx VU37P Virtex UltraScale+ w/HBMMemory• Two 64-bit 4GBytes DDR4 (8GB total)
memory blocks to RFSoC. Up to 2400
Mb/s.
• Single 64-bit 4GBytes DDR4 memory
block to Virtex Ultrascale+. Up to 2400
Mb/s.
• 8GB on-chip HBM blocks inside Virtex
Ultrascale+• Block RAM and UltraRAM available inside
the FPGA devices
ADC and DAC• ADC: 16-channels, 12-bit, 2GSPS with DDC• DAC: 16-channels, 14-bit, 6.4GSPS withDUC
Programmable FPGA Logic
RFSoC• 930k System Logic Cells• 425k CLB LUTs
• 4,272 DSP Slices
Virtex Ultrascale+• 2,852k System Logic Cells• 1,304k CLB LUTs• 9,024 DSP Slices
Application Processing Unit
• Quad-core ARM Cortex-A53 MPCore• Up to 1.5GHz
Real-time Processing Unit
• Dual-core ARM Cortex-R5 MPCore• Up to 533MHz
Backplane Connectivity• X16 PCIe to Virtex Ultrascale+• X8 PCIe to RFSoC• X16 GTY to P5• X16 GTY to P6 and P3 each (Depopulatedfor SOSA aligned backplane)
Software Support• Linux• Windows• VxWorks® (contact factory)
Environment• Convection Cooled• Operating Temperature: 0 oC to + 70oC

WE INNOVATE. WE DELIVER. YOU SUCCEED.
Americas: 866-OK-ABACO or +1-866-652-2226

Asia & Oceania: +81-3-5544-3973

Europe, Africa, & Middle East: +44 (0) 1327-359444
Locate an Abaco Systems Sales Representative visit: abaco.com/products/sales

abaco.com@AbacoSys©2019 Abaco Systems. All Rights Reserved. Xilinx and Zynq are registered trademarks, and Ultrascale+,and Virtex
are trademarks, of Xilinx, Inc. VxWorks is a registered trademark of Wind River Systems. Linux is the registeredtrademark of Linus Torvalds. Windows is a registered trademark of Microsoft Corporation. ARM is a registeredtrademark of ARM Limited. PCIe is a trademark of PCI-SIG. DisplayPort is a trademark of the Video Electronics
Standards Association (VESA). All other trademarks are the property of their respective owners. Specifications are
subject to change without notice.
06/19 A-DS-5200