TECHNICAL DATA SHEET

Onyx 52720
3-channel 200 MHz A/D, 2-channel 800 MHz D/A
3U VPX board with Virtex-7 FPGA

Complete radar andsoftware radio
interface solution▪ Radar and communication receiver andtransmitter▪ Wideband data acquisition▪ Electronic Warfare transponder▪ Sensor interfaces▪ Remote monitoring▪ Waveform signal generator

The 52720 is a multichannel, high-speed data converter, suitablefor connection to HF or IF ports of a communications or radarsystem. Its built-in data capture and playback features offer an ideal
turnkey solution.
The 52720 includes three A/Ds, one upconverter, two D/As and four banks of memory. Itfeatures built-in support for PCI Express over the 3U VPX backplane.

FEATURES▪ Supports Xilinx® Virtex®-7 VXT FPGA
▪ GateXpress® supports dynamic FPGA reconfiguration across PCIe
▪ Three 200 MHz 16-bit A/Ds
▪ One DUC (digital upconverter)▪ Two 800 MHz 16-bit D/As
▪ 4 GB of DDR3 SDRAM▪ Sample clock synchronization to an external system reference▪ LVPECL clock/sync bus for multiboard synchronization▪ PCI Express (Gen. 1, 2 & 3) interface up to x4▪ Optional user-configurable gigabit serial interface▪ Optional LVDS connections to the Xilinx® Virtex®-7 FPGA for custom I/O▪ 3U VPX form factor provides a compact, rugged platform▪ Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65(OpenVPX™ System Specification)▪ Ruggedized and conduction-cooled versions available

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Onyx 52720

52720 BLOCK DIAGRAMS

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Onyx 52720

THE ONYX ARCHITECTURE

A/D ACQUISITION IP MODULES

Based on the proven design of the Mercury Cobalt family, Onyx
raises the processing performance with the new flagship familyof Virtex-7 FPGAs from Xilinx. As the central feature of theboard architecture, the FPGA has access to all data and control
paths, enabling factory-installed functions including data
multiplexing, channel selection, data packing, gating, triggeringand memory control. The Onyx Architecture organizes the FPGA
as a container for data processing applications where eachfunction exists as an intellectual property (IP) module.

The 52720 features three A/D Acquisition IP Modules for easily
capturing and moving data. Each module can receive data fromany of the three A/Ds, a test signal generator or from the D/A
Waveform Playback IP Module in loopback mode.

Each member of the Onyx family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The 52720 factory-installed functions include three
A/D acquisition and a D/A waveform playback IP modules for
simplifying data capture and data transfer. IP modules for DDR3
SDRAM memories, a controller for all data clocking andsynchronization functions, a test signal generator, and a PCIeinterface complete the factory-installed functions and enable
the 52720 to operate as a complete turnkey solution, without
the need to develop any FPGA IP.

These powerful linked-list DMA engines are capable of a unique
Acquisition Gate Driven mode. In this mode, the length of atransfer performed by a link definition need not be known prior
to data acquisition; rather, it is governed by the length of theacquisition gate. This is extremely useful in applications where
an external gate drives acquisition and the exact length of thatgate is not known or is likely to vary.

EXTENDABLE IP DESIGNFor applications that require specialized functions, users can install
their own custom IP for data processing. The GateFlow FPGA
Design Kits include all of the factory-installed modules as document
source code. Developers can integrate their own IP with thefactory-installed functions or use the GateFlow kit to completely
replace the IP with their own.

XILINX VIRTEX-7 FPGAThe Xilinx Virtex-7 FPGA site can be populated with one of two FPGAs
to match the specific requirements of the processing task. Supported
FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1
slices and is ideal for modulation/demodulation, encoding/decoding,encryption/decryption, and channelization of the signals between
transmission and reception. For applications not requiring large DSP
resources or logic, the lower-cost VX330T can be installed.

A/D CONVERTER STAGE
The board's analog interface accepts three full-scale analog HF
or IF inputs on front panel SSMC connectors at +8 dBm into 50
ohms with transformer coupling into three Texas Instruments
ADS5485 200 MHz, 16-bit A/D converters. The digital outputs aredelivered into the Xilinx® Virtex®-7 FPGA for signal processing,data capture or routing to other board resources.

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Each IP module has an associated memory bank for buffering
data in FIFO mode or for storing data in transient capture mode.
All memory banks are supported with DMA engines for easily
moving A/D data through the PCIe interface.

For each transfer, the DMA engine can automatically construct
metadata packets containing A/D channel ID, a sample-accurate
time stamp and data length information. These actions simplify
the host processor’s job of identifying and executing on thedata.

D/A WAVEFORM PLAYBACK IP MODULE
The 52720 factory-installed functions include a sophisticated
D/A Waveform Playback IP module. A linked-list controller
allows users to easily play back to the dual D/As waveforms
stored in either on-board memory or off-board host memory.
Parameters including length of waveform, delay from playback
trigger, waveform repetition, etc. can be programmed for eachwaveform. Up to 64 individual link entries can be chained
together to create complex waveforms with a minimum ofprogramming.

DIGITAL UPCONVERTER AND D/A STAGE
A Texas Instruments DAC5688 DUC (digital upconverter) and D/A
accepts a baseband real or complex data stream from the FPGA
and provides that input to the upconvert, interpolate and dual
D/A stages. When operating as a DUC, it interpolates andtranslates real or complex baseband input signals to any IF
center frequency up to 360 MHz. It delivers real or quadrature(I+Q) analog outputs to the dual 16-bit D/A converter. Analog
output is through a pair of front panel SSMC connectors.
If translation is disabled, the DAC5688 acts as a dual
interpolating 16-bit D/A with output sampling rates up to 800

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MHz. In both modes the DAC5688 provides interpolation factorsof 2x, 4x and 8x.

CLOCKING AND SYNCHRONIZATION
Two internal timing buses provide either a single clock or two
different clock rates to the A/D and D/A signal paths. Eachtiming bus includes a clock, sync and a gate or trigger signal. An
on-board clock generator receives an external sample clockfrom the front panel SSMC connector. This clock can be useddirectly for either the A/D or D/A sections or can be divided by abuilt-in clock synthesizer circuit to provide different A/D and
D/A clocks.
In an alternate mode, the sample clock can be sourced from an
on-board programmable VCXO (Voltage-Controlled Crystal
Oscillator). In this mode, the front panel SSMC connector can beused to provide a 10 MHz reference clock for synchronizing theinternal oscillator.
A front panel 26-pin LVPECL Clock/Sync connector allows multiple
boards to be synchronized. In the slave mode, it accepts LVPECL
inputs that drive the clock, sync and gate signals. In the mastermode, the LVPECL bus can drive the timing signals forsynchronizing multiple boards.

MEMORY RESOURCES
The 52720 architecture supports four independent DDR3 SDRAM
memory banks. Each bank is 1 GB deep and is an integral partof the module’s DMA capabilities, providing FIFO memory spacefor creating DMA packets. Built-in memory functions include an
A/D data transient capture mode and D/A waveform playbackmode.

The board’s configuration FLASH can hold four FPGA images.
Images can be factory-installed IP or custom IP created by the user,
and programmed into the FLASH via JTAG using Xilinx iMPACT or
through the board’s PCIe interface. At power up the user canchoose which image will load based on a hardware switch setting.
Once booted, GateXpress allows the user three options for
dynamically reconfiguring the FPGA with a new IP image:▪ The first is the option to load an alternate image from
FLASH through software control. The user selects thedesired image and issues a reload command.
▪ The second option is for applications where the FPGA
image must be loaded directly through the PCIe interface.
This is important in security situations where there can be
no latent user image left in nonvolatile memory whenpower is removed. In applications where the FPGA IP may
need to change many times during the course of a
mission, images can be stored on the host computer andloaded through PCIe as needed.
▪ The third option, typically used during development,
allows the user to directly load the FPGA through JTAG
using Xilinx iMPACT.
In all three FPGA loading scenarios, GateXpress handles the
hardware negotiation simplifying and streamlining the loadingtask. In addition, GateXpress preserves the PCIe configuration
space allowing dynamic FPGA reconfiguration without a hostcomputer reset to rediscover the board. After the reload, thehost simply continues to see the board with the expected
device ID.

PCI EXPRESS INTERFACEThe 52720 includes an industry-standard interface fullycompliant with PCI Express Gen. 1 & 2 bus specifications.
Supporting PCIe links up to x4, the interface includes multiple
DMA controllers for efficient transfers to and from the board.

GATEXPRESS FOR FPGA CONFIGURATIONThe Onyx architecture includes GateXpress®, a sophisticated
FPGA-PCIe configuration manager for loading and reloading the
FPGA. At power up, GateXpress immediately presents a PCIetarget for the host computer to discover, effectively giving the
FPGA time to load from FLASH. This is especially important forlarger FPGAs where the loading times can exceed the PCIe
discovery window, typically 100 msec on most PCs.

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Onyx 52720

READYFLOW
Mercury provides ReadyFlow® BSPs (Board Support Packages) for
all Cobalt, Onyx, and Flexor products. Available for both Linux andWindows, these packages:▪ Provide a path for quick start-up through application
completion▪ Allow programming at high, intermediate and low levels tomeet various needs▪ Are illustrated with numerous examples▪ Include complete documentation and definitions of all
functions▪ Include library and example source code.
ReadyFlow BSPs contain C-language examples that can be used
to demonstrate the capabilities of Cobalt, Onyx, and Flexor
products. These programming examples will help you get an
immediate start on writing your own application. They provide
sample code that is known to work, giving you a means ofverifying that your board set is operational.

COMMAND LINE INTERFACEThe Command Line Interface provides access to pre-compiled
executable examples that operate the hardware right out of thebox, without the need to write any code. Board-specific hardware

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operating arguments can be entered in the command line tocontrol parameters: number of channels to enable, sample
clock frequency, data transfer size, reference clock frequency,
reference clock source, etc.
The Command Line Interface can be used to call an example
application from within a larger user application to control the
hardware, and parameter arguments are passed to theapplication for execution. Functions that control dataacquisition automatically save captured data to a pre-named
host file or are routed to the Signal Analyzer example function
for display.

SIGNAL ANALYZER
When used with the Command Line Interface, the Signal
Analyzer allows users to immediately start acquiring anddisplaying A/D data. A full-featured analysis tool, the Signal
Analyzer displays data in time and frequency domains. Built-in
measurement functions display 2nd and 3rd harmonics, THD,
and SINAD. Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals.

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GATEFLOWThe User Application Container

The GateFlow® FPGA Design Kit (FDK) allows the user to modify,

Shown below is the FPGA block diagram of a typical Cobalt,
Onyx or Flexor module. The User Application Container holds acollection of different installed IP modules connected to thevarious interfaces through the standard ports surrounding thecontainer. The specific IP modules for each product aredescribed in further detail in the datasheet of that product.

replace and extend the standard installed functions in the FPGA
to incorporate special modes of operation, new control
structures, and specialized signal-processing algorithms.
The Cobalt (Virtex-6), Onyx (Virtex-7), and Flexor (Virtex-7)
architectures configure the FPGA with standard factory-suppliedinterfaces including memory controllers, DMA engines, A/D and
D/A interfaces, timing and synchronization structures, triggeringand gating logic, time stamping and header tagging, data
formatting engines, and the PCIe interface. These resources areconnected to the User Application Container using well-defined
ports that present easy-to-use data and control signals,
effectively abstracting the lower-level details of the hardware.

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The GateFlow FDK provides a complete Xilinx's ISE or Vivado
project folder containing all the files necessary for the FPGA
developer to recompile the entire project with or without any
required changes. VHDL source code for each IP module
provides excellent examples of how the IP modules work, how
they might be modified, and how they might be replaced withcustom IP to implement a specific function.

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A/D PERFORMANCE

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Spurious Free Dynamic Range

Spurious Pick-up

fin = 70 MHz, fs = 200 MHz, Internal Clockfs = 200 MHz, Internal Clock

Two-Tone SFDR

Two-Tone SFDR

f1 = 30 MHz, f2 = 70 MHz, fs = 200 MHz

f1 = 69 MHz, f2 = 71 MHz, fs = 200 MHz

Adjacent Channel Crosstalk

Input Frequency Response

fin Ch2 = 70 MHz, fs = 200 MHz, Ch 1 shown

fs = 200 MHz, Internal Clock

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Onyx 52720

D/A PERFORMANCE

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Spurious Free Dynamic Range

Spurious Free Dynamic Range

fout = 70 MHz, fs = 800 MHz, Interpolation = 4,
Internal Clockfout = 100 MHz, fs = 800 MHz, Interpolation = 4,
Internal Clock

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Onyx 52720

FRONT PANEL CONNECTIONSThe XMC front panel includes six SSMC coaxial connectors and a
26-pin Sync Bus connector for input/output of timing andanalog signals. The front panel also includes ten LEDs.
▪ Sync Bus Connector: The 26-pin Sync
Bus front panel connector, labeled
SYNC/GATE, provides clock, sync, andgate input/output pins for the LVPECL
Sync Bus.

Analog Input Connectors: Three SSMC coaxial
connectors, labeled IN 1, IN 2, and IN 3: one for each
ADS5485 input channel.
▪ A/D Overload LEDs: There are three red OV (overload)
LEDs: one for each A/D input. Each LED indicates either
an analog input overload in the associated ADS5485, or an
A/D FIFO overrun.

SPECIFICATIONS
Front Panel Analog Signal Inputs▪ Link LED: The green LNK LED blinks
when a valid link has been establishedover the PCIe interface.

Input Type: Transformer-coupled, front panel female SSMC
connectors▪ User LED: The green USR LED is foruser applications.

Full Scale Input: +8 dBm into 50 ohms

▪ Master LED: The yellow MAS LED
illuminates when the model is the Sync
Bus Master. When only a single model isused, it must be a Master.
▪ PPS LED: The green PPS LED
illuminates when a valid PPS signal isdetected. The LED will blink at the rate of
the PPS signal.
▪ Over Temperature LED: The red TMP
LED illuminates when an overtemperature or over-voltage condition isindicated by any of thetemperature/voltage sensors on the PCB.
▪ Clock LED: The green CLK LED
illuminates when a valid sample clock
signal is detected. If the LED is notilluminated, no clock has been detected
and no data from the input stream can beprocessed.
▪ Clock Input Connector: One SSMC coaxial connector,
labeled CLK, for input of an external sample clock.

Transformer Type: Coil Craft WBC4-6TLB
3 dB Passband: 300 kHz to 700 MHz

A/D Converters
Type: Texas Instruments ADS5485
Sampling Rate: 10 MHz to 200 MHz
Resolution: 16 bits

D/A Converters
Type: Texas Instruments DAC5688
Input Data Rate: 250 MHz max.
Output IF: DC to 400 MHz max.
Output Signal: 2-channel real or 1-channel with frequency
translation
Output Sampling Rate: 800 MHz max. with interpolation
Resolution: 16 bits

Front Panel Analog Signal Outputs
Output Type: Transformer-coupled, front panel female SSMC
connectors
Transformer Type: Coil Craft WBC4-6TLB
Full Scale Output: +4 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz▪ Analog Output Connectors: Two SSMC coaxial
connectors, labeled OUT 1 and 2: one for each DAC5688
output.

Sample Clock Sources▪ D/A Underrun LED: There is one red UR (underrun) LED
for the D/A output. This LED illuminates when the
DAC5688 FIFO is out of data.

Clock Synthesizer

On-board clock synthesizer generates two clocks: one A/Dclock and one D/A clock
Clock Source: Selectable from on-board programmable VCXO
(10 to 810 MHz), front panel external clock or LVPECL timing
bus
Synchronization: VCXO can be locked to an external 4 to 180
MHz PLL system reference, typically 10 MHz

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Onyx 52720

Clock Dividers: External clock or VCXO can be divided by 1, 2,
4, 8, or 16 for the A/D clock

External Clock
Type: Front panel female SSMC connector, sine wave, 0 to
+10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz
sample clock or PLL system reference

Timing Bus
26-pin connector LVPECL bus includes, clock/sync/gate/PPS
inputs and outputs; TTL signal for gate/trigger and sync/PPS
inputsField Programmable Gate Array▪ Standard: Xilinx Virtex-7 XC7VX330T-2▪ Optional: Xilinx Virtex-7 XC7VX690T-2

Custom I/O▪ Option -104: Provides 24 pairs of LVDS connections
between the FPGA and the VPX P2 connector for custom
I/O.
▪ Option -105: Provides one 8X or two 4X gigabit links
between the FPGA and the VPX P1 connector to support
serial protocols.

MemoryPhysicalDimensions: 3U VPX▪ Depth: 170.6 mm (6.717 in.)▪ Height: 100 mm (3.937 in.)
Weight▪ VPX Carrier: 110 grams (3.9 oz.);▪ XMC Module: Approximately 400 grams (14 oz.) with 2-slotheatsink

ORDERING INFORMATION
Model

Description

52720

3-Channel 200 MHz A/D and 2-Channel 800 MHz D/Awith Virtex-7 FPGA 3U VPX

Options

Description-073

XC7VX330T-2 FPGA

-076

XC7VX690T-2 FPGA-104

LVDS FPGA I/O to VPX P2-105

Gigabit serial FPGA I/O to VPX P1

Type: DDR3 SDRAM-702

Air-cooled, Level 2

Size: Four banks, 1 GB each

-763

Conduction-cooled, Level 3

Speed: 800 MHz (1600 MHz DDR)

Contact Mercury for compatible option combinations.

PCI-Express Interface
PCI Express Bus: Gen. 1 or Gen. 2: x4

Environmental

ACCESSORY PRODUCTS
Model

Description

2171

Cable Kit: SSMC to SMA

Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing
Option -702: L2 (air-cooled)▪ Operating Temp: -20° to 65° C▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing
Option -763: L3 (conduction-cooled)▪ Operating Temp: -40° to 70° C▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

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Onyx 52720

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR ONYX PRODUCTS

Mercury offers development systems for Onyx products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system that
ensures optimum performance of Onyx boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORS
Onyx products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Onyx Model 71720 XMC (3Channel 200 MHz A/D with DDC and 2-Channel 800 MHz D/A with
Kintex UltraScale FPGA) has the following variants:
Model
52720

3U VPX board (single XMC)

57720

6U VPX board (single XMC)

58720

6U VPX board (dual XMC)

71720

XMC module

78720

PCIe board (single XMC)

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Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
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For technical details, contact:mrcy.com/go/CF52720

Visit: mrcy.com/go/MP52720+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Cobalt, Flexor, Onyx, GateXpress, GateFlow, and ReadyFlow. Other marks used herein may be trademarks or registered trademarks of theirrespective holders. Mercury believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The
information contained herein is subject to change without notice.
© 2022 Mercury Systems, Inc. 1-0-112322-DS-O52720

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