TECHNICAL DATA SHEET

Onyx 52751
2-channel 500 MHz A/D with DDC, DUC with 2-channel 800 MHz D/A
3U VPX board with Virtex-7 FPGA

Complete radar andsoftware radio
interface solution▪ Radar and communication receiver andtransmitter▪ Wideband data acquisition▪ Electronic Warfare transponder▪ Sensor interfaces▪ Remote monitoring▪ Waveform signal generator

The 52751 is a two-channel, high-speed data converter with aprogrammable DDC, suitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture andplayback features offer an ideal turnkey solution.
The 52751 includes two A/Ds, two D/As and four banks of memory. It features built-in
support for PCI Express over the 3U VPX backplane.

FEATURES▪ Supports Xilinx® Virtex®-7 VXT FPGA
▪ GateXpress® supports dynamic FPGA reconfiguration across PCIe
▪ Two 500 MHz 12-bit A/Ds and optional 400 MHz 14-bit A/Ds
▪ Two multiband DDCs (digital downconverters)▪ One DUC (digital upconverter)▪ Two 800 MHz 16-bit D/As
▪ 4 GB of DDR3 SDRAM▪ Sample clock synchronization to an external system reference▪ LVPECL clock/sync bus for multiboard synchronization▪ PCI Express (Gen. 1, 2 & 3) interface up to x4▪ Optional user-configurable gigabit serial interface▪ Optional LVDS connections to the Xilinx® Virtex®-7 FPGA for custom I/O▪ 3U VPX form factor provides a compact, rugged platform▪ Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65(OpenVPX™ System Specification)

mrcy.com

TECHNICAL DATA SHEET
Onyx 52751

52751 BLOCK DIAGRAMS

mrcy.com

2

TECHNICAL DATA SHEET
Onyx 52751

THE ONYX ARCHITECTURE
Each member of the Onyx family isdelivered with factory-installed
applications ideally matched to theboard’s analog interfaces. The 52751
factory installed functions include two
A/D acquisition and a D/A waveform
playback IP modules. Each of the two
acquisition IP modules contains a
powerful, programmable DDC IP core.
The waveform playback IP module
contains an interpolation IP core, ideal
for matching playback rates to the data
and decimation rates of the acquisition
modules. IP modules for DDR3
memories, a controller for all data
clocking and synchronization functions,a test signal generator, and a PCIeinterface complete the factory-installed
functions and enable the 52751 tooperate as a complete turnkey solution,
without the need to develop any FPGA IP.

XILINX VIRTEX-7 FPGAThe Xilinx Virtex-7 FPGA site can be
populated with one of two FPGAs to matchthe specific requirements of the processing
task. Supported FPGAs are VX330T or
VX690T. The VX690T features 3600 DSP48E1
slices and is ideal formodulation/demodulation,
encoding/decoding, encryption/decryption,and channelization of the signals between
transmission and reception. For applications
not requiring large DSP resources or logic,
the lower-cost VX330T can be installed.

processing, data capture and for routing
to other board resources.

A/D ACQUISITION IP MODULES
The 52751 features two A/D Acquisition
IP Modules for easily capturing andmoving data. Each module can receive
data from either of the two A/Ds, a test
signal generator or from the D/A
Waveform Playback IP Module inloopback mode. Each IP module has an
associated memory bank for buffering
data in FIFO mode or for storing data intransient capture mode. All memorybanks are supported with DMA engines
for easily moving A/D data through the
PCIe interface.
These powerful linked-list DMA engines
are capable of a unique Acquisition Gate
Driven mode. In this mode, the length ofa transfer performed by a link definitionneed not be known prior to dataacquisition; rather, it is governed by thelength of the acquisition gate. This isextremely useful in applications where
an external gate drives acquisition andthe exact length of that gate is notknown or is likely to vary.
For each transfer, the DMA engine can
automatically construct metadata
packets containing A/D channel ID, asample-accurate time stamp and data
length information. These actions
simplify the host processor’s job ofidentifying and executing on the data.

A/D CONVERTER STAGE

DDC IP CORES

The board's analog interface accepts two
analog HF or IF inputs on front panel
SSMC connectors with transformer
coupling into two Texas Instruments
ADS5463 500 MHz, 12-bit A/D converters.
Optionally, a Texas Instruments ADS5474
400 MHz, 14-bit A/D may be installed.

Within each A/D Acquisition IP Module isa powerful DDC IP core. Because of theflexible input routing of the A/D
Acquisition IP Modules, many different
configurations can be achieved including
one A/D driving both DDCs or each of the
two A/Ds driving its own DDC.

The digital outputs are delivered into the
Xilinx® Virtex®-7 FPGA for signal

Each DDC has an independent 32-bit
tuning frequency setting that ranges

mrcy.comfrom DC to ƒs, where ƒs is the A/D
sampling frequency. Each DDC can haveits own unique decimation setting,supporting as many as two different
output bandwidths for the board.
Decimations can be programmed from 2
to 131,072 providing a wide range tosatisfy most applications.
The decimating filter for each DDC
accepts a unique set of user-supplied 16bit coefficients. The 80% default filtersdeliver an output bandwidth of 0.8*ƒs/N,
where N is the decimation setting. The
rejection of adjacent-band components
within the 80% output bandwidth isbetter than 100 dB. Each DDC delivers acomplex output stream consisting of 24bit I + 24-bit Q or16-bit I + 16-bit Q
samples at a rate of ƒs/N.

D/A WAVEFORM PLAYBACK IP
MODULE
The Model 52751 factory-installed
functions include a sophisticated D/A
Waveform Playback IP module. A linkedlist controller allows users to easily playback to the dual D/As waveforms storedin either on-board memory or off- board
host memory.
Parameters including length ofwaveform, delay from playback trigger,
waveform repetition, etc. can be
programmed for each waveform. Up to
64 individual link entries can be chained
together to create complex waveforms
with a minimum of programming.

DIGITAL UPCONVERTER AND D/ASTAGE
A Texas Instruments DAC5688 DUC (digital
upconverter) and D/A accepts a baseband
real or complex data stream from the FPGA
and provides that input to the upconvert,
interpolate and dual D/A stages.
When operating as a DUC, it interpolates
and translates real or complex baseband

3

TECHNICAL DATA SHEET
Onyx 52751

input signals to any IF center frequency up
to 360 MHz. It delivers real or quadrature(I+Q) analog outputs to the dual 16-bit D/Aconverter. Analog output is through a pairof front panel SSMC connectors.
If translation is disabled, the DAC5688 acts
as a dual interpolating 16-bit D/A with
output sampling rates up to 800 MHz. In
both modes the DAC5688 provides
interpolation factors of 2x, 4x and 8x. In
addition to the DAC5688, an FPGA-based
interpolator core provides additional
interpolation from 2x to 65,536x. The twointerpolators can be combined to create a
total range from 2x to 524,288x.

CLOCKING AND SYNCHRONIZATION
Two internal timing buses provide eithera single clock or two different clock
rates to the A/D and D/A signal paths.
Each timing bus includes a clock, sync
and a gate or trigger signal. An on-board
clock generator receives an external
sample clock from the front panel SSMC
connector. This clock can be useddirectly for either the A/D or D/Asections or can be divided by a built-in
clock synthesizer circuit to provide
different A/D and D/A clocks. In an
alternate mode, the sample clock can besourced from an on-board programmable
VCXO (Voltage-Controlled Crystal
Oscillator). In this mode, the front panel
SSMC connector can be used to provide
a 10 MHz reference clock forsynchronizing the internal oscillator.
A front panel 26-pin LVPECL Clock/Sync
connector allows multiple modules to besynchronized. In the slave mode, it
accepts LVPECL inputs that drive theclock, sync and gate signals. In themaster mode, the LVPECL bus can drive
the timing signals for synchronizing
multiple boards.
Multiple 52751’s can be driven from the
LVPECL bus master, supporting

mrcy.comsynchronous sampling and sync
functions across all connected boards.

MEMORY RESOURCES
The 52751 architecture supports four
independent DDR3 SDRAM memorybanks. Each bank is 1 GB deep and is an
integral part of the module’s DMA
capabilities, providing FIFO memory
space for creating DMA packets. Built-in
memory functions include multichannel
A/D data capture, tagging and streaming.
In addition to the factory-installed
functions, custom user-installed IP
within the FPGA can take advantage ofthe memories for many other purposes.

PCI EXPRESS INTERFACEThe Model 52751 includes an industrystandard interface fully compliant withPCI Express Gen. 1, 2 and 3* bus
specifications. Supporting PCIe links up
to x4, the interface includes multiple
DMA controllers for efficient transfers toand from the board.
*Gen 3 requires a compatible backplane and SBC

GATEXPRESS FOR FPGACONFIGURATIONThe Onyx architecture includes
GateXpress®, a sophisticated FPGA-PCIeconfiguration manager for loading andreloading the FPGA. At power up,
GateXpress immediately presents a PCIetarget for the host computer to discover,effectively giving the FPGA time to loadfrom FLASH. This is especially important
for larger FPGAs where the loading
times can exceed the PCIe discovery
window, typically 100 msec on most PCs.

user can choose which image will load
based on a hardware switch setting. Oncebooted, GateXpress allows the user three
options for dynamically reconfiguring the
FPGA with a new IP image:▪ The first is the option to load analternate image from FLASH
through software control. The user
selects the desired image andissues a reload command.
▪ The second option is forapplications where the FPGA
image must be loaded directly
through the PCIe interface. This isimportant in security situations
where there can be no latent user
image left in nonvolatile memory
when power is removed. In
applications where the FPGA IP
may need to change many times
during the course of a mission,
images can be stored on the hostcomputer and loaded through PCIeas needed.
▪ The third option, typically usedduring development, allows theuser to directly load the FPGA
through JTAG using Xilinx iMPACT.
In all three FPGA loading scenarios,
GateXpress handles the hardware
negotiation simplifying and streamlining
the loading task. In addition, GateXpresspreserves the PCIe configuration space
allowing dynamic FPGA reconfiguration
without a host computer reset torediscover the board. After the reload,
the host simply continues to see theboard with the expected device ID.

The board’s configuration FLASH can holdfour FPGA images. Images can be factoryinstalled IP or custom IP created by theuser, and programmed into the FLASH via
JTAG using Xilinx iMPACT or through theboard’s PCIe interface. At power up the4

TECHNICAL DATA SHEET
Onyx 52751

READYFLOW
Mercury provides ReadyFlow® BSPs (Board Support Packages) for
all Cobalt, Onyx, and Flexor products. Available for both Linux andWindows, these packages:▪ Provide a path for quick start-up through application
completion▪ Allow programming at high, intermediate and low levels tomeet various needs▪ Are illustrated with numerous examples▪ Include complete documentation and definitions of all
functions▪ Include library and example source code.
ReadyFlow BSPs contain C-language examples that can be used
to demonstrate the capabilities of Cobalt, Onyx, and Flexor
products. These programming examples will help you get an
immediate start on writing your own application. They provide
sample code that is known to work, giving you a means ofverifying that your board set is operational.

COMMAND LINE INTERFACEThe Command Line Interface provides access to pre-compiled
executable examples that operate the hardware right out of thebox, without the need to write any code. Board-specific hardware

mrcy.com

operating arguments can be entered in the command line tocontrol parameters: number of channels to enable, sample
clock frequency, data transfer size, reference clock frequency,
reference clock source, etc.
The Command Line Interface can be used to call an example
application from within a larger user application to control the
hardware, and parameter arguments are passed to theapplication for execution. Functions that control dataacquisition automatically save captured data to a pre-named
host file or are routed to the Signal Analyzer example function
for display.

SIGNAL ANALYZER
When used with the Command Line Interface, the Signal
Analyzer allows users to immediately start acquiring anddisplaying A/D data. A full-featured analysis tool, the Signal
Analyzer displays data in time and frequency domains. Built-in
measurement functions display 2nd and 3rd harmonics, THD,
and SINAD. Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals.

5

TECHNICAL DATA SHEET
Onyx 52751

GATEFLOWThe User Application Container

The GateFlow® FPGA Design Kit (FDK) allows the user to modify,

Shown below is the FPGA block diagram of a typical Cobalt,
Onyx or Flexor module. The User Application Container holds acollection of different installed IP modules connected to thevarious interfaces through the standard ports surrounding thecontainer. The specific IP modules for each product aredescribed in further detail in the datasheet of that product.

replace and extend the standard installed functions in the FPGA
to incorporate special modes of operation, new control
structures, and specialized signal-processing algorithms.
The Cobalt (Virtex-6), Onyx (Virtex-7), and Flexor (Virtex-7)
architectures configure the FPGA with standard factory-suppliedinterfaces including memory controllers, DMA engines, A/D and
D/A interfaces, timing and synchronization structures, triggeringand gating logic, time stamping and header tagging, data
formatting engines, and the PCIe interface. These resources areconnected to the User Application Container using well-defined
ports that present easy-to-use data and control signals,
effectively abstracting the lower-level details of the hardware.

mrcy.com

The GateFlow FDK provides a complete Xilinx's ISE or Vivado
project folder containing all the files necessary for the FPGA
developer to recompile the entire project with or without any
required changes. VHDL source code for each IP module
provides excellent examples of how the IP modules work, how
they might be modified, and how they might be replaced withcustom IP to implement a specific function.

6

TECHNICAL DATA SHEET
Onyx 52751

FRONT PANEL CONNECTIONSThe XMC front panel includes six SSMC
coaxial connectors and a 26-pin Sync
Bus connector for input/output of timing
and analog signals. The front panel also
includes nine LEDs.
▪ Sync Bus
Connector: The
19-pin Sync Bus
front panel
connector, labeled
SYNC/GATE,
provides clock,sync, and gate
input/output pins
for the Sync Bus.
▪ Link LED: The
green LNK LED
blinks when a valid
link has been
established overthe PCIe interface.
▪ User LED: The
green USR LED is
for userapplications.
▪ MAS LED: The
yellow MAS
LED illuminates
when this model isthe Sync Bus
Master.
▪ PPS LED: The
green PPS LED
illuminates when a valid PPS signal
is detected. The LED will blink at
the rate of the PPS signal.
▪ Over Temperature LED: The red
TMP LED illuminates when an
over-temperature or over-voltage
condition is indicated by any of thetemperature/voltage sensors on
the Model PCB.
▪ Clock Input Connector: One
SSMC coaxial connector, labeled
CLK, for input of an external
sample clock.

mrcy.com▪ Trigger Input Connector: The
SSMC coaxial connector labeled
TRIG is for input of an external
trigger. The signal must be a
LVTTL signal.

Phase Offset Resolution: 32 bits, 0 to
360 degrees▪ Analog Output Connectors: Two
SSMC coaxial connectors foranalog signal outputs are labeled
OUT 1 and 2 for each DAC5688
output.

Default Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dB
stopband attenuation▪ DAC Underrun LED: The red UR
underrun LED illuminates when the
DAC5688 FIFO is out of data.
▪ Analog Input Connectors: Two
SSMC coaxial connectors, labeled
IN 1 and IN 2 are for each
ADC12D1800 input channel.
▪ ADC Overload LED: Two red OV(overload) LEDs for each A/D input.

SPECIFICATIONS
Front Panel Analog Signal Inputs
Input Type: Transformer-coupled,
front panel female SSMC connectors
Transformer Type:
Coil Craft WBC4-6TLB
Full Scale Input: +5 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz

A/D Converters (standard)

FIR Filter: 16-bit coefficients, 24-bit
output, with user programmablecoefficients

D/A Converters
Type: Texas Instruments DAC5688
Input Data Rate: 250 MHz max.
Output IF: DC to 400 MHz max.
Output Signal: 2-channel real or
1-channel with frequency translation
Output Sampling Rate: 800 MHz max.
with 2x, 4x or 8x interpolation
Resolution: 16 bits

Digital Interpolator
Interpolation Range: 2x to 65,536x in
two stages of 2x to 256x

Total Interpolator Range (D/A and
Digital Combined)
2x to 524,288x

Front Panel Analog Signal Outputs
Output Type: Transformer-coupled,
front panel female SSMC connectors
Transformer Type:
Coil Craft WBC4-6TLB

Type: Texas Instruments ADS5463

Full Scale Output: +4 dBm into
50 ohms

Sampling Rate: 20 MHz to 500 MHz

3 dB Passband: 300 kHz to 700 MHz

Resolution: 12 bits

A/D Converters (option -014)
Type: Texas Instruments ADS5474
Sampling Rate: 20 MHz to 400 MHz
Resolution: 14 bits

Digital Downconverters
Quantity: Two channels
Decimation Range: 2x to 131,072x in
two programmable stages of 2x to
256x and one fixed 2x stage
LO Tuning Freq. Resolution: 32 bits,
0 to ƒs
LO SFDR: >120 dB

Sample Clock Sources
On-board clock synthesizer generates
two clocks: one A/D clock and one D/Aclock

Clock Synthesizer
Clock Source: Selectable from onboard programmable VCXO (10 to 810
MHz), front panel external clock or
LVPECL timing bus
Synchronization: VCXO can be locked
to an external 4 to 180 MHz PLL
system reference, typically 10 MHz
Clock Dividers: External clock or VCXO
can be divided by 1, 2, 4, 8, or 16,
independently for the A/D clock andD/A clock
7

TECHNICAL DATA SHEET
Onyx 52751

External Clock
Type: Front panel female SSMC
connector, sine wave, 0 to +10 dBm,
AC-coupled, 50 ohms, accepts 10 to
800 MHz sample clock or PLL systemreference

Timing Bus
26-pin connector LVPECL bus
includes, clock/sync/gate/PPS inputs
and outputs; TTL signal forgate/trigger and sync/PPS inputs

Field Programmable Gate Array▪ Standard: Xilinx Virtex-7
XC7VX330T-2▪ Optional: Xilinx Virtex-7
XC7VX690T-2

Custom I/O▪ Option -104: Installs the PMC P14
connector with 24 LVDS pairs to
the FPGA▪ Option -105: Provides one 8X or
two 4X gigabit links between the
FPGA and VPX P1 connector to
support serial protocols.

MemoryType: DDR3 SDRAM
Size: Four banks, 1 GB each
Speed: 800 MHz (1600 MHz DDR)

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C

ORDERING INFORMATION
Model

Description

52751

2-Channel 500 MHz A/D with
DDC, DUC with 2-Channel 800
MHz D/A, and a Virtex-7 FPGA 3U
VPX▪ Relative Humidity: 0 to 95%,
non-condensing
Option -702: L2 (air-cooled)▪ Operating Temp: -20° to 65° C▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%,
non-condensing
Option -763: L3 (conduction-cooled)▪ Operating Temp: -40° to 70° C▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%,
non-condensing

PhysicalDimensions: Form Factor: VPX▪ Depth: 149 mm (5.87 in.)▪ Height: 74 mm (2.91 in.)
Weight▪ VPX Carrier: 110 grams (3.9 oz.);▪ XMC Module: approximately 400
grams (14 oz.) with 2-slotheatsink

Options

Description-014

400 MHz, 14-bit A/Ds

-073

XC7VX330T-2 FPGA

-076

XC7VX690T-2 FPGA-104

LVDS FPGA I/O to VPX P2-105

Gigabit serial FPGA I/O to VPX
P1

-702

Air-cooled, Level 2-763

Conduction-cooled, Level 3

Contact Mercury for compatible option
combinations.

ACCESSORY PRODUCTS
Model

Description

2171

Cable Kit: SSMC to SMA

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 or x8

mrcy.com

8

TECHNICAL DATA SHEET
Onyx 52751

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR ONYX PRODUCTS

Mercury offers development systems for Onyx products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system that
ensures optimum performance of Onyx boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORS
Onyx products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Onyx Model 71751 XMC (2Channel 500 MHz A/D with DDC and 2-Channel 800 MHz D/A with
DUC, Virtex-7 FPGA) has the following variants:
Model
52751

3U VPX board (single XMC)

57751

6U VPX board (single XMC)

58751

6U VPX board (dual XMC)

71751

XMC module

78751

PCIe board (single XMC)

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF52751

Visit: mrcy.com/go/MP52751+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Cobalt, Flexor, Onyx, GateXpress, GateFlow, and ReadyFlow. Other marks used herein may be trademarks or registered trademarks of theirrespective holders. Mercury believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The
information contained herein is subject to change without notice.
© 2022 Mercury Systems, Inc. 1-0-112322-DS-O52751

mrcy.com9