TECHNICAL DATA SHEETJade 78865
2-channel 200 MHz 16-bit A/D channelizer,
762 narrowband DDCs, 4 wideband DDCs
PCIe board with Kintex UltraScale FPGA

Complete radarand software radiointerface solution▪ Radar and software radio receiver▪ Wideband data acquisition▪ Communications receiver▪ Remote monitoring▪ Analog signal interface fordata recording▪ Sensor interfaces

The Jade® 78865 is a two-channel data converter with a total of766 programmable DDCs (digital downconverters). It is suitable forconnection to HF or IF ports of a communications or radar system. Itsbuilt-in data capture feature offers an ideal turnkey solution for extremely
high-channel-count systems.
It includes two A/Ds, a complete multiboard clock and sync section, eight banks ofchannelizer-based DDCs and resampling filters. The PCIe Gen.3 x8 interface is capable ofsustained data transfers to system memory of over 6 GB/sec.

FEATURES▪ Uses Xilinx® Kintex® UltraScale KU035 FPGA
▪ Two 200 MHz 16-bit A/Ds
▪ Four wideband DDCs (digital downconverters)▪ Up to 762 narrowband DDCs
▪ Sample clock generation and synchronization to an external system reference▪ PCI Express interface (Gen. 1, 2 & 3) up to x8▪ Ruggedized and conduction-cooled versions▪ Navigator Design Suite for software and custom IP development

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TECHNICAL DATA SHEETJade 78865

78865 BLOCK DIAGRAM

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TECHNICAL DATA SHEETJade 78865

THE JADE ARCHITECTURE
Evolved from the proven designs of Mercury’s Cobalt® and Onyx®
families, Jade® raises the processing performance while lowering
the overall power requirements by building on the Xilinx family ofKintex UltraScale FPGAs. As the central feature of the board
architecture, the FPGA has access to all data and control paths,
enabling factory-installed functions as well as providing an ideal
platform for user-created intellectual property (IP).
Each member of the Jade family is delivered with factoryinstalled applications ideally matched to the board’s analoginterfaces. The 78865 factory-installed functions include twoA/D acquisition IP modules for simplifying data capture andtransfer.
Each acquisition IP module contains a powerful, programmable
DDC IP core and a controller for all data clocking, triggering, andsynchronization functions. From each of the two acquisition
modules, A/D sample data flows into identical IP modules
consisting of banks of wideband and narrowband DDCs. Finally,
data is delivered to four DMA controllers and then to the PCIe
Gen. 3 x8 interface.
These complete the factory-installed functions and enable the78865 to operate as a complete turnkey solution for many
applications, thereby saving the cost and time of custom IPdevelopment.

XILINX KINTEX ULTRASCALE FPGAThe Kintex UltraScale KU035 FPGA handles all of the control,
timing, data formatting, and DSP operations for the channelizedDDCs and is highly optimized to maximize resource utilization andreduce power dissipation. Because of its extremely advanced
FPGA design, no Navigator FDK is offered for the 78865 forcustomers to modify the FPGA IP.

A/D CONVERTERS
The board's analog interface accepts two analog HF or IF inputs
on front panel SSMC connectors with transformer-coupling into
two Texas Instruments ADS5485 200 MHz, 16-bit A/Dconverters. The digital outputs are delivered into the Kintex
UltraScale FPGA for signal-processing or routing to other boardresources.

A/D ACQUISITION IP MODULES
The 78865 features two A/D Acquisition IP Modules for easily
capturing and moving data.

Each IP module has an associated DMA engine for easily moving
DDC data through the PCIe interface. These powerful linked-list
DMA engines are capable of a unique Acquisition Gate Drivenmode. In this mode, the length of a transfer performed by a link
definition need not be known prior to data acquisition; rather, it
is governed by the length of the acquisition gate.
For each transfer, the DMA engine can automatically construct
metadata packets containing A/D channel ID, a sample-accurate
time stamp and data length information. These actions simplify
the host processor’s job of identifying and executing on thedata.

DDC RESOURCES
Samples from the two A/D converters flow into two identical
blocks, each containing one bank of two wideband DDCs andthree banks of narrowband DDCs, as shown in the block diagram
below.
Wideband DDCs
The four wideband DDCs can be set for decimation values
between 8 and 128 in steps of 4, providing usable output
bandwidths from 1.25 MHz to 20 MHz for a sample rate, ƒs, of200 MHz. Because all four wideband DDCs within the 71865 feed
the same DMA controller #1, all wideband DDCs must use thesame decimation factor.
Each DDC delivers an output stream consisting of 16-bit I + 16bit Q complex samples at a rate of ƒs/N. Four samples, one fromeach of the wideband DDCs, are interleaved in the output
stream. All four wideband DDCs can be independently tuned
across the range from 0 Hz to ƒs with 32 bits of resolution.
Narrowband DDCs
Each of the six narrowband DDC banks can be configured tooperate in three different modes, where each mode provides adifferent quantity of DDC channels and range of decimations.
These modes are summarized in the following table:
ModeChannels

Dec Range

Steps

132

128 - 2048

64

264

256 - 4096

128

3127

512 - 8192

256

All six narrowband DDC banks must operate in the same mode.
The 80% default filters deliver an output bandwidth of 0.8*ƒs/N,
where N is the decimation setting. The rejection of adjacent-mrcy.com

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TECHNICAL DATA SHEETJade 78865

band components within the 80% output bandwidth is better
than 100 dB.
Each DDC delivers an output stream at a rate of ƒs/N, and is
programmable for either 16-bit I + 16-bit Q, or 24-bit I + 24-bit Qcomplex samples.
Because each pair of narrowband DDC banks feed a common
DMA controller, the decimation setting for each DDC must bethe same. Nevertheless, each pair can have a different
decimation setting from the other pairs.

RESAMPLING FILTERS
Three multiplexers allow outputs from each of the three
narrowband DDC pairs to feed the associated DMA controller orfeed the input of a resampling filter.
Each of the three resampling filters is an FIR low-pass filter thataccepts DDC input samples at one sample rate and delivers
output samples at another rate. Resampling filters are often
used for better symbol recovery of signals using digitalmodulation schemes. The output rate is usually higher to create
oversampling at a multiple of 2x, 4x, 8x, or 16x the symbol rate.
The resampling filter combines the operations of an FIRinterpolation filter followed by a decimator. The overall
resampling ratio is equal to the interpolation factor divided by
the decimation factor, both of which are programmableparameters.
Note that each of the three resampling filters can be
programmed independently. Some limitations on the DDC
output data rates and subsequent resampling ratios may be
imposed because of maximum PCIe transfer rates.

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CLOCKING AND SYNCHRONIZATION
An internal timing bus provides all timing and synchronization
required by the A/D converters. It includes a clock, two sync
and two gate or trigger signals. An on-board clock generator
receives an external sample clock from the front panel SSMC
connector. This clock can be used directly by the A/D or divided
by a built-in clock synthesizer circuit.
In an alternate mode, the sample clock can be sourced from an
on-board programmable voltage-controlled crystal oscillator. In
this mode, the front panel SSMC connector can be used toprovide a 10 MHz reference clock for synchronizing the internal
oscillator.
A front panel 26-pin LVPECL Clock/Sync connector allows
multiple boards to be synchronized. In the slave mode, it
accepts LVPECL inputs that drive the clock, sync and gatesignals. In the master mode, the LVPECL bus can drive thetiming signals for synchronizing multiple boards.
Multiple boards can be driven from the LVPECL bus master,
supporting synchronous sampling and sync functions across allconnected boards. For systems requiring high channel counts,
the Model 7893 System Synchronization and Distribution board
can synchronize up to eight 78865s.

PCI EXPRESS INTERFACEThe 78865 includes an industry-standard interface fullycompliant with PCI Express Gen. 1, 2 and 3 bus specifications.
Supporting PCIe links up to x8, the interface includes multiple
DMA controllers for efficient transfers to and from the board.

4TECHNICAL DATA SHEETJade 78865

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IPcores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installed
FPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jadedesign. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of all
hardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSP
components. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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5TECHNICAL DATA SHEETJade 78865

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade boardand Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEETJade 78865

A/D PERFORMANCE

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Spurious Free Dynamic Range

Spurious Pick-up

fin = 70 MHz, fs = 200 MHz, Internal Clockfs = 200 MHz, Internal Clock

Two-Tone SFDR

Two-Tone SFDR

f1 = 30 MHz, f2 = 70 MHz, fs = 200 MHz

f1 = 69 MHz, f2 = 71 MHz, fs = 200 MHz

Adjacent Channel Crosstalk

Input Frequency Response

fin Ch2 = 70 MHz, fs = 200 MHz, Ch 1 shown

fs = 200 MHz, Internal Clock

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TECHNICAL DATA SHEETJade 78865

FRONT PANEL CONNECTIONS
The front panel includes four SSMC coaxial connectors for clock,
trigger, and analog input signals, and a 26-pin Sync Bus
input/output connector. The front panel also includes eight LEDindicators.

▪ ADC Overload LEDs: There are two red OV (overload)
LEDs: one for each A/D input. Each LED indicates either anoverload in the associated ADS5485 or an ADC FIFO overrun.

SPECIFICATIONS
Front Panel Analog Signal Inputs▪ Sync Bus Connector: The 26-pin µSync
front panel connector, labeled SYNC/GATE,provides clock, sync, and gate input/output
pins for the Low-Voltage Positive EmitterCoupled Logic (LVPECL) Sync Bus.
▪ Link LED: The green LNK LED indicates thelink speed when a valid link has beenestablished over the PCIe interface, asfollows: Gen 1 - LED blinks slowly (less thanonce per second); Gen 2 - LED blinks about
once per second; Gen 3 - LED will beconstantly on.
▪ User LED: The green USR LED is for userapplications.
▪ Master LED: The yellow MAS LED
illuminates when this 71865 is the Sync BusMaster. When only a single 71865 is used, it
must be a Master.
▪ PPS LED: The green PPS LED illuminates
when a valid PPS signal is detected. The LED
will blink at the rate of the PPS signal.
▪

Over Temperature LED: The red TMP LEDilluminates when an over-temperature or over-voltage
condition is indicated by any of the temperature/voltage
sensors on the 71865 PCB.

▪ Clock LED: The green CLK LED illuminates when a valid
sample clock signal is detected. If the LED is not illuminated,no clock has been detected and no data from the input
stream can be processed.
▪ Clock Input Connector: One SSMC coaxial connector,
labeled CLK, for input of an external sample clock.
▪ Trigger Input Connector: One SSMC coaxial connector,
labeled TRIG, for input of an external trigger.
▪ Analog Input Connectors: Two SSMC coaxial connectors,labeled IN 1 and IN 2: one for each ADS5485 A/D converter.
▪ DAC Underrun LED: One red underrun UR LED for the
D/A output. This LED illuminates when the DAC5688 FIFO isout of data.

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Input Type: Transformer-coupled, front panel female SSMC
connectors
Transformer Type: Coil Craft WBC4-6TLB
Full Scale Input: +8 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz

A/D Converters
Type: Texas Instruments ADS5485Sampling Rate: 10 MHz to 200 GHz
Resolution: 16 bits

Wideband Digital Downconverters
Quantity: Four
Decimation Range: 8 to 128 in steps of 4, common to all fourDDCs
LO Tuning Freq. Resolution: 32 bits, 0 to ƒs
LO SFDR: >120 dB
Phase Offset Resolution: 32 bits, 0 to 360 degrees
FIR Filter: 24-bit coefficients, 24-bit output
FIR Filter Performance: 80% bandwidth <0.3 dB passband
ripple, >100 dB stopband attenuation

Narrowband Digital Downconverters
Quantity: Six banks
DDC Bank Modes:
Mode 1: 32 DDCs, Dec = 128 to 2048, in steps of 64
Mode 2: 64 DDCs, Dec = 256 to 4096, steps of 128
Mode 3: 127 DDCs, Dec = 512 to 8192, steps of 256
LO Tuning Freq. Resolution: 32 bits, 0 to ƒs, withindependent tuning for each channel
LO SFDR: >120 dB
Default Filter Set: 80% bandwidth, <0.3 dB passband ripple,>100 dB stopband attenuation

Sample Clock Sources
On-board clock synthesizer

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TECHNICAL DATA SHEETJade 78865

Clock Synthesizer

ORDERING INFORMATIONClock Source: Selectable from on-board programmable VCXO
(10 to 810 MHz), front panel external clock or LVPECL timingbusModelDescriptionSynchronization: VCXO can be locked to an external 4 to 180
MHz PLL system reference, typically 10 MHz

78865

2-channel 200 MHz A/D with 4 WB DDCs, 762 NB DDCs,
Kintex UltraScale FPGA - x8 PCIe

Clock Dividers: External clock or VCXO can be divided by 1, 2,3, 4, 6, 8, or 16 for the A/D clock

External Clock
Type: Front panel female SSMC connector, sine wave, 0 to+10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider
input clock or PLL system reference

Options:-702

Air-cooled, Level 2Contact Mercury for compatible option combinations and complete
specifications of rugged and conduction-cooled versions. Options maychange, so be sure to contact Mercury for the latest information.

Timing Bus
26-pin connector LVPECL bus includes, clock/sync/gate/PPS
inputs and outputs; TTL signal for gate/trigger and sync/PPS
inputsExternal Trigger Input
Type: Front panel female SSMC connector, LVTTL
Function: Programmable functions include: trigger, gate,
sync and PPSACCESSORY PRODUCTS
Model

Description

2171

Cable Kit: SSMC to SMA

7893

System Synchronizer and Distribution Board – PCIe

Field Programmable Gate Array
Standard: Xilinx Kintex UltraScale XCKU035-2

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 or x8

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing
Option -702: L2 (air-cooled)▪ Operating Temp: -20° to 65° C▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: PCIe card
▪ Depth: 181.10 mm (7.13 in)▪ Height: 111.25 mm (4.38 in)
Weight: Approximately 14 oz (400 grams)

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TECHNICAL DATA SHEETJade 78865

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR JADE PRODUCTS

Mercury offers development systems for Jade products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system that
ensures optimum performance of Jade boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORSJade products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Jade Model 71865 XMC (4Channel 200 MHz A/D with 766 DDCs, Kintex UltraScale FPGA)
has the following variants:
Model52865

3U VPX board (single XMC)

57865

6U VPX board (single XMC)

58865

6U VPX board (dual XMC)

71865

XMC module

78865

PCIe board (single XMC)

Corporate Headquarters
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Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, SwitzerlandFor technical details, contact:mrcy.com/go/CF78865

Visit: mrcy.com/go/MP78865+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Jade and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2022 Mercury Systems, Inc. 1-0-112922-DS-J78865

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