TECHNICAL DATA SHEET

Quartz 5553
3U VPX SOSA aligned 8-channel A/D and D/A board
with Xilinx Zynq UltraScale+ RFSoC - Gen 3

Developed in alignment
with the SOSA TechnicalStandard▪ High-bandwidth data streaming▪ Waveform signal generator▪ Analog I/O for digital recording andplayback▪ Communication receiver and transmitter▪ Sensor interfaces▪ Electronic Warfare transponder

The Quartz® 5553 is a high-performance, SOSA™ aligned 3U
OpenVPX board based on the Xilinx Zynq UltraScale+ RFSoC. The
RFSoC integrates eight RF class A/D and D/A converters into the Zynq’s
multiprocessor architecture, creating a multichannel data conversion
and processing solution on a single chip. The 5553 brings RFSoC
performance to 3U VPX with a complete system on a board.
Complementing the RFSoC’s on-chip resources are the 5553’s sophisticated clocking section
for single board and multiboard synchronization, a low-noise front end for RF input andoutput, 16 GBytes of DDR4, a 10 GigE interface, a 40 GigE interface, a gigabit serial opticalinterface capable of supporting dual 100 GigE connections and general purpose serial andparallel signal paths to the FPGA.

BOARD ARCHITECTURE
The 5553 board design places the RFSoC as the cornerstone of the architecture. All
control and data paths are accessible by the RFSoC’s programmable logic and processing
system. A full suite of Mercury-developed IP and software functions utilize thisarchitecture to provide data capture, timing, and interface solutions for many of the mostcommon application requirements.

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TECHNICAL DATA SHEET
Quartz 5553

FEATURES

EXTENDABLE IP DESIGN▪ Developed in alignment with the SOSA™ Technical Standard

For applications that require specialized functions, users caninstall their own custom IP for data processing. The Navigator
FPGA Design Kit (FDK) includes the board’s entire FPGA design
as a block diagram that can be edited in Xilinx’s Vivado® IP
Integrator. In addition to the IP Integrator block diagrams, allsource code and complete IP core documentation is included.
Developers can integrate their own IP along with the factoryinstalled functions or use the Navigator kit to completely
replace the IP provided by Mercury with their own.

▪ Incorporates Xilinx® Zynq® UltraScale+™ RFSoC▪ 16 GB of DDR4 SDRAM▪ On-board GPS receiver▪ 10 GigE Interface▪ 40 GigE Interface▪ Optional VITA 67.3C optical interface for backplane gigabit
serial communication▪ Dual 100 GigE UDP interface▪ Compatible with several VITA standards including: VITA 46,
VITA 48, VITA 67.3C, and VITA 65 (OpenVPX™ System
Specification)▪ Ruggedized and conduction-cooled▪ Unique QuartzXM eXpress Module enables migration to otherform factors▪ Navigator® BSP for software development▪ Navigator® FDK for custom IP development▪ Free lifetime applications support

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The Navigator Board Support Package (BSP), the companion
product to the Navigator FDK, provides a complete C-callable
library for control of the 5553’s hardware and IP. The Navigator
FDK and BSP libraries mirror each other where each IP function
is controlled by a matching software function, simplifying thejob of keeping IP and software development synchronized.
The Navigator BSP includes support for Xilinx's PetaLinux runningon the ARM Cortex-A53 processors. When running under
PetaLinux, the Navigator BSP libraries enable complete control of
the 5553 either from applications running locally or on the ARMs,
or using the Navigator API control and command from remotesystem computers.

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Balun

Balun

Balun

Balun

RF Out 6

RF Out 7

RF Out 8

JTAG

Antenna InBalun

RF Out 5Balun

RF In 8

RF Out 4Balun

RF In 7

Balun

Balun

RF In 6

RF Out 3Balun

RF In 5

Balun

Balun

RF In 4

RF Out 1

Balun

RF In 3

RF Out 2Balun

RF In 2

Balun

Balun

Timing Bus
Generator

RF In 1Gate / Trigger

Reference Sync

Reference Clk

Sample Clk

Frequency
Synthesizer

RF Out 2
through 7

RF In 2through 7

SysRef

D/A Clocks

A/D Clocks

GPS

D/A Output
1 -8

A/D Input
1 -8

Programmable
Logic

ZYNQ
UltraScale+
RFSoC FPGA

64

DDR4
SDRAM
4/8 GB

GTY

LVDS

GTY

GTY

Processing
System

GTR

GTR

GTR

GTR

JTAG

POWER
Battery
MANAGEMENTManagement

Model 5553 Quartz 3U VPXVPX VBAT

Battery

JTAG

VPX
P2

VPX
P1

VPX
P2
(1/2)

VPX
P0

X8 25 Gb/sec Optical
Transceiver(Optional)

3U VPX
Backplane

RF In
VITA
X8
RF Out67.3C
Dual X8
100 GigE

Reference Clk
Gate / Trigger

Sample Clk
GPS Antenna

LVDS

40 GigE

10 GigE

VPX VBAT

1 GigE

Sync Bus

12 V

VPX RefClk

VPX AuxClk

X8

Config
FLASH

DDR4
SDRAM
4/8 GB

12 V

IPMC
VITA 46.11

X10

X4

X1

64

1 GigEPowerManagement

Model 6003 QuartzXM eXpress Module9.85 GHz
14-BIT
D/A & DUC
Channels
1-8

5 GHz
14-bitA/D & DDC
Channels
1-8

RF Signal
Chain

Clock
Management

SD
Card

TECHNICAL DATA SHEET
Quartz 5553

5553 BLOCK DIAGRAM

Click on a block for more information.

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TECHNICAL DATA SHEET
Quartz 5553

A/D CONVERTER STAGE
The analog interface accepts analog IF or RF inputs on eight coax
connectors located within a VITA 67.3C connector. These inputs aretransformer-coupling into the RF signal chain of the RFSoC. Inside
the RFSoC, the analog signals are routed to eight 5 GSPS, 14-bit A/Dconverters. Each converter has built-in digital downconverters with
programmable 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, or 40x
decimation and independent tuning.
The A/D digital outputs are delivered into the Zynq’s programmable
logic and processor system for signal processing, data capture or forrouting to other resources. In addition to the A/D’s built-in
decimation, an additional stage of IP-based decimation provides
another 16x stage of data reduction, ideal for applications that needto stream data from all eight A/Ds.

D/A CONVERTER STAGE
The RFSoC’s eight D/A converters accept baseband real or complex
data streams from the FPGA’s programmable logic. Each 9.85 GSPS,
14-bit D/A includes a digital upconverter with independent tuning
and interpolations of 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x,
or 40x. Each D/A output is transformer coupled to a coax
connection located within a VITA 67.3C connector.

CLOCKING AND SYNCHRONIZATION
An on-board timing bus generator uses a programmable frequency
synthesizer to generate the sample clock and all required timing
signals. the on-board sample clock can also be locked to areference clock received through one of the VITA 67.3C connectors.
A multifunction gate/trigger input is also available on one of the
VITA 67.3C connectors for external control of data acquisition andplayback. For larger systems requiring multiboard synchronization,a multisignal sync bus interface is provided on the VPX P1
connector. These signals include the sample clock and all requiredcomplementary timing signals to provide single sample accurate
synchronization across multiple boards. The Model 5503 HighSpeed Synchronizer and Distribution 3U VPX Board is available as aprogrammable clocking and sync source for these high channel
count Quartz® systems.

MEMORY RESOURCES
The 5553 architecture supports 8 GBytes of DDR4 SDRAM
memory accessible from the Programmable Logic. Userinstalled IP, which, along with the Mercury-supplied DDR4
controller core within the FPGA can take advantage of thememory for custom applications. An additional 8 GByte bank ofmrcy.com

DDR4 SDRAM is available to the Processing System as program
memory and storage.

1, 10 AND 40 GIGE INTERFACEThe 5553 includes 1, 10 and 40 GigE interfaces for control anddata transfers. These interfaces are independent of the optical
100 GigE interfaces. The 1 GigE interface provides a directconnection to the Processing System. The 10 and 40 GigE
interfaces respond to Ethernet ARP requests and are available
for custom implementations in SOSA sensor systems.

GPS
A GPS receiver provides time and position information to the
FPGA and ARM processors. This information can be used for
precise data tagging. The GPS provides a 1 PPS and a reference
clock to the FPGA.

EXPANDABLE I/O
The 5553 supports eight 25 Gb/sec full duplex optical lanes tothe VITA 67.3C connector. With the built-in 100 GigE UDP
interface or installation of a user provided serial protocol, this
optical interface enables a high-speed gigabit data streaming
path between boards.

INTELLIGENT PLATFORM MANAGEMENT CONTROLLER
The 5553 uses Crossfield Technology LLC’s Intelligent Platform
Management Controller (IPMC) to provide a fully compliant andflexible management solution for Field Replaceable Units (FRU) that
support the VITA 46.11 standard required by HOST and SOSA
architectures. The IPMC provides a standardized implementation of
FRU management interfaces, control signals, and sensor monitoring.
The IPMC provides the Chassis Manager and higher-level System
Management Software (SMS) access to FRU information, FRU control
signals, and sensor monitoring functions so that they can identify,
activate/deactivate, reset, and monitor health of the card and takeappropriate system control actions.
The IPMC also provides a low-level path for configuration
management and FRU maintenance through both IPMI messages anda Maintenance Port (MP) serial interface. The maintenance port
provides a terminal mode command-line interface and supports
monitoring, data uploads, and FRU level troubleshooting.

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TECHNICAL DATA SHEET
Quartz 5553

OPTIMIZED IP
capturing and storing this much raw data is not feasible, theA/Ds built-in digital downconverters can reduce this data
throughput in many applications to a rate reasonable for thedata streaming and storage components downstream in thesystem.

Xilinx has created an integrated processing solution in the RFSoC
that is unprecedented. The key to unlocking the potential of the
RFSoC is efficient operation using optimized IP and application
software. Mercury helps streamline the process from development
to deployed application by providing a full suite of built-in functions.
These address the data flow and basic processing needed for someof the most common applications.

In some applications capturing the raw, full bandwidth data is
crucial. The 5553’s dual 100 GigE UDP engine provides a highbandwidth path for moving data off of the board. Along withthe built-in data acquisition IP, the 5953 can stream raw datafrom two A/D channels running at 4 GSPS over optical cable toa downstream storage or processing subsystem.

EXAMPLE 1 - HIGH BANDWIDTH DATA STREAMING
The RFSoC’s eight A/Ds are capable of producing an aggregate
data rate of 80 GB/sec when all channels are enabled. While

DDR
SDRAM
RF In

A/Ds
Data
Acquisition
IP Block

1 GigE
VPX

10 GigE
40 GigE

Dual
100 GigE
UDP
IP Block

D/As
Zync UltraScale+ RFSoC

8x 25 Gb/sec
OpticalTransceivers

VITA
66.4

Dual
100 GigE
Out

Model 5553

EXAMPLE 2 - WAVEFORM GENERATOR
The 5553’s IP supports multiple D/A signal source options. A simple
loopback path allows samples received by the A/Ds to be output
through the D/As. A CW signal generator produces a sine output
with programmable frequency. A chirp generator, ideal for radar

RF In

applications, outputs sweep signals with programmablefrequency, ramp, phase offset, gain offset and length. The
generators also include flexible trigger options with both internaland external triggering.

DDR
SDRAM

CW Signal
Generator
IP Block

A/Ds

1 GigE
VPX

10 GigE
40 GigE

RF Out

D/As

M
U
X

Chirp
Generator
IP Block
VITA
66.4

Zync UltraScale+ RFSoC
Model 5553
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TECHNICAL DATA SHEET
Quartz 5553

EXAMPLE 3 - MULTIMODE DATA ACQUISITION SYSTEM
In some applications multiple data acquisition modes may need
to be operated at the same time. A required dataflow could be
full bandwidth streaming of a single A/D channel over 100 GigE toa data recorder while another channel of A/D data is stored assnapshots in the boards DDR4 SDRAM and read by the ARM

RF In

processor for analysis or transfer over the 1 GigE interface toan external processor. The 5553 provides these modes withbuilt-in IP supporting complex data streaming scenarios
without the need for creating custom IP.

DDR SDRAM
Memory Control
IP Block

A/Ds

DDR
SDRAM

1 GigE
VPX

Data
Acquisition
IP Block

10 GigE
40 GigE

D/As
Dual 100 GigE
UDP IP Block

Zync UltraScale+ RFSoC

8x 25 Gb/sec
OpticalTransceivers

VITA
66.4

Dual
100 GigE
Out

Model 5553

FLEXIBLE MODULAR DESIGN
While the Quartz 5553 follows the form factor of a standard 3U
OpenVPX board, the unique modular design of Model 6003
QuartzXM eXpress Module provides the flexibility to deploy thissolution in many different situations. The heart of the QuartzXM
is a system on module containing all of the key components
including the RFSoC FPGA, DDR4 SDRAM, and power and clock
management.
In the case of the 5553, the QuartzXM is mounted on a 3U OpenVPX
carrier which complements the design with a timing bus generator,
analog signal conditioning, a GPS receiver and an 8x 28 Gbps opticaltransceiver. As a module and carrier board set, the 5553 becomes acomplete, ready to deploy 3U OpenVPX solution available for a range

of operating environments from commercial to rugged andconduction-cooled.
The Model 6003 QuartzXM can also be mounted on othercarriers available from Mercury to support standard form
factors; or for applications that require a non-standard
footprint, Mercury supports the module with a design kit forusers to engineer and build their own custom carrier. As acomplete and tested module, the QuartzXM encapsulates bestin-class electrical and mechanical design, eliminating some of
the most challenging aspects of embedded circuit design andallowing the user to focus on the application specific carrier
design.

QuartzXM eXpress Module

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TECHNICAL DATA SHEET
Quartz 5553

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.
The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design
Suite includes the complete Vivado project folder for each Jade
product with all design files for the factory-installed FPGA IP.
Vivado’s IP Integrator is a graphical design entry tool that visuallypresents the complete block diagram of all IP blocks so thedeveloper can access every component of the Jade design.
Developers can quickly import, delete, and modify IP blocks andchange interconnection paths using simple mouse operations.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on the
powerful AXI4 standard. multilevel documentation for each IP coreis a mouse click away, and fully consistent with Xilinx IP cores.
The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational
control of all hardware functions on the board and IP functionsin the FPGA. The BSP structure is designed to complement thefunctions of the FDK by maintaining a one-to-one relationshipbetween FDK and BSP components. For each IP block found in
the FDK library, a matching software module can be found in
the BSP. This organization simplifies the creation and editingof software to support new IP functions and modifications toexisting IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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TECHNICAL DATA SHEET
Quartz 5553

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEET
Quartz 5553

SPECIFICATIONS

D/A Converters

Field Programmable Gate Array▪ Quantity: 8

Type: (standard) Xilinx Zynq UltraScale+ RFSoC XCZU47DR▪ Option -048: Xilinx Zynq UltraScale+ RFSoC XCZU48DR▪ Sampling Rate: (standard) 8.92 GHz▪ With -2 speed grade (option -002): 9.85 GHz

Speed: (standard) -1 speed grade▪ Resolution: 14 bits

▪ Option -002: -2 speed grade

Digital Upconverters

RFSoC RF Signal Chain
Analog Inputs▪ Quantity▪ Option -113: 4▪ Option -114: 8▪ Connector▪ Option -113: VITA 67.3D▪ Option -114: VITA 67.3C▪ Quantity: 1 per D/A▪ Interpolation Range: 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x,
20x, 24x, and 40x (not all interpolations are supported bydefault IP)▪ LO Tuning Freq. Resolution: 48 bits
▪ Filter: 80% pass band, 89 dB stop-band attenuation
Sample Clock▪ Source: On-board programmable clock source or external
clock source▪ Input Type: Transformer-coupled▪ Connector Type: VITA 67.3C (for external source)▪ Transformer Type: Mini-Circuits TCM1-83X+▪ Level: -10 dBm to +10 dBm▪ Full Scale Input: +10 dBm into 50 ohms

Reference Clock

A/D Converters▪ Source: On-board oscillator, on- board GPS, or externalsource▪ Quantity: 8▪ Sampling Rate: 5.0 GHz▪ Resolution: 14 bits
Digital Downconverters▪ Quantity: 1 per A/D▪ Decimation Range: 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x,
20x, 24x, and 40x (not all decimations are supported bydefault IP)▪ LO Tuning Freq. Resolution: 48 bits, 0 to ƒs▪ Filter: 80% pass band, 89 dB stop-band attenuation
Analog Outputs▪ Quantity▪ Option -113: 4▪ Option -114: 8▪ Quantity▪ Option -113: VITA 67.3D▪ Option -114: VITA 67.3C▪ Input Type: Transformer-coupled▪ Transformer Type: Mini-Circuits TCM1-83X+▪ Full Scale Output: +0 dBm into 50 ohms

mrcy.com▪ Connector Type: VITA 67.3C or VITA 67.3D (for externalsource)▪ Level: -10 dBm to +24 dBm
Gate/Trigger:▪ Source: Programmable through software or externalsource▪ Connector Type: VITA 67.3C or VITA 67.3D (for externalsource)▪ Level: TTL
Sync Bus▪ Signals: Sample Clock, Reference Clock, Reference Sync,
Gate/Trigger▪ Location: VPX-P1

RFSoC Processing System
ARM Cortex-A53:▪ Quantity: 4▪ Speed: 1.5 GHz
ARM Cortex-R5:▪ Quantity: 2▪ Speed: 600 MHz

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TECHNICAL DATA SHEET
Quartz 5553

Processor I/O:

FPGA Configuration FLASH:▪ Interface: 1 GigE

▪ Type: QSPI NOR Flash▪ Location: VPX-P1▪ Size: 2 x 1 Gbit

FPGA I/O

Environmental

Interface: GPIO

Option -763: L3 (conduction-cooled)▪ Quantity: 10 Pairs▪ Operating Temp: –40° to 70° C▪ Type: LVDS

▪ Storage Temp: –50° to 100° C▪ Location: VPX-P1▪ Relative Humidity: 0 to 95%, non-condensing

Interface: 10 GigE

Physical▪ Location: VPX-P1

Dimensions: VPX board

Interface: 40 GigE

▪ Depth: 170.61 mm (6.717 in)▪ Location: VPX-P1▪ Height: 100 mm (3.937 in)Interface: Optical▪ Weight: Approximately 14 oz (400 grams)▪ Quantity▪ Option -107: 4 full duplex lanes▪ Option -108: 8 full duplex lanes▪ Connector

OpenVPX Compatibility
The 5553 is compatible with the following module profile, as
defined by the VITA 65 OpenVPX Specification:
SLT3-PAY-1F1U1S1S1U2F1H-14.6.11-12▪ Option -107: VITA 67.3D▪ Option -108: VITA 67.3C▪ Speed: 25 Gb/sec▪ Laser: 850 nm▪ Protocol: Factory-installed dual 100 GigE UDP IP coresprovides greater than 24 GB/sec data transfers, otherprotocols supported with user installed IP

GPSSource: On-board
Antenna Connector Location: VITA 67.3C

JTAG
Location: VPX-P0

MemoryProcessing System:▪ Type: DDR4 SDRAM▪ Size: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)
Programmable Logic:▪ Type: DDR4 SDRAM▪ Size: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)

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TECHNICAL DATA SHEET
Quartz 5553

ORDERING INFORMATIONACCESSORY PRODUCTS

Model

Description

Model

Description

5553

3U VPX SOSA aligned 8-channel A/D board with Xilinx
Zynq UltraScale+ RFSoC - Gen 35503

3U VPX SOSA aligned high-speed synchronizer anddistribution board

Options

Description

OptionDescription-002-2 FPGA speed grade, -1 standard-048

XCZU48DR FPGA (XCZU47DR is standard)

8256

SOSA Aligned 3U VPX Development Chassis-107

VITA 67.3D 4X optical interface-108

VITA 67.3C 8X optical interface-113

VITA 67.3D with 4 A/D, 4 D/A, External Reference andTrigger connections installed-114

VITA 67.3C with 8 A/D, 8 D/A, External Reference,
Trigger, GPS Antenna and External Clock connections
installed-151

8 Gb processor system memory, 8 Gb programmable
logic memory-214

Alternate RF pin-out configuration-220

Extended A/D sample rate*-763

Conduction-cooled, Level L3

LIFETIME SUPPORT FOR QUARTZ PRODUCTS
Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

*Limited availability, contact Mercury.
Contact Mercury for compatible option combinations and complete
specifications.

Corporate Headquarters
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Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF5553

Visit: mrcy.com/go/MP5553+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Quartz and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2022 Mercury Systems, Inc. 1-1-102822-DS-Q5553

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