TECHNICAL DATA SHEETJade 5585
3U VPX SOSA aligned 8-channel 250 MHz A/D board
with Virtex UltraScale+ HBM FPGA

Complete radar andsoftware radio interface▪ Wideband data acquisition▪ Multichannel, multiboard synchronization
for high channel count systems▪ High-bandwidth memory, FPGA logic
and DSP density make this board asingle-slot 3U VPX processingpowerhouse

The 5585 SOSA aligned 3U OpenVPX board is an 8-channel, highspeed data converter with programmable DDCs (digital downconverters). It is suitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture featureoffers an ideal turnkey solution as well as a platform for developing anddeploying custom FPGA-processing IP.
Ample data transfer bandwidth and flexibility are provided by a range of board interfaces
including 1 GigE, 10 GigE, 40 GigE, dual 100 GigE and PCIe with installation of Mercury oruser-supplied IP. The Virtex UltraScale+ HBM’s on-chip high-bandwidth memory coupledwith the FPGA’s logic and DSP density enable the 5585 to be a single-slot SOSA aligned 3U
VPX data acquisition and processing powerhouse.

FEATURES▪ Exceptional dynamic range and analog signal integrity▪ Features Xilinx Virtex UltraScale+ HBM FPGAs▪ Eight 250 MHz 16-bit A/Ds
▪ 10 GigE Interface▪ 40 GigE Interface▪ Dual 100 GigE UDP interface▪ Optional VITA 67.3C optical interface for backplane gigabit serial communication▪ Compatible with several VITA standards including: VITA 46, VITA 48.11, VITA 67.3C andVITA 65 (OpenVPX™ System Specification)▪ Navigator Design Suite for software and custom IP development

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TECHNICAL DATA SHEETJade 5585

5585 BLOCK DIAGRAMClick on a block for more information.

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TECHNICAL DATA SHEETJade 5585

BOARD ARCHITECTURE

A/D CONVERTER STAGE

The 5585 board design places the Virtex UltraScale+ FPGA as
the cornerstone of the architecture. The FPGA has access to alldata and control paths, enabling factory-installed functions
including data multiplexing, channel selection, data packing,gating, triggering and memory control. The Jade architectureorganizes the FPGA as a container for data-processing
applications where each function exists as an intellectual
property (IP) module.

The front end accepts eight analog HF or IF inputs from theVITA 67.3 C connector with transformer coupling into four Texas
Instruments ADS42LB69 dual 250 MHz, 16- bit A/D converters.
The digital outputs are delivered into the Virtex UltraScale+
HBM FPGA for signal processing or routing to other module
resources.

Each member of the Jade family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The 5585 factory-installed functions include eight
A/D acquisition IP modules for simplifying data capture andtransfer.

The 5585 features eight A/D Acquisition IP Modules for easily
capturing and transferring data. Each module can receive datafrom any of the eight A/Ds, or a test signal generator and movethe acquired data off board over 10 GigE, 40 GigE or PCIe.

Each of the eight acquisition IP modules contains a powerful,programmable DDC IP core; a controller for all data clocking andsynchronization functions; a test signal generator; andinterfaces to PCIe, 10 and 40 GigE. An optional 8-lane opticalinterface is also available and provides a dual 100 GigE interface
with an IP core included with the Navigator FPGA Design Kit andinstalled by the user. These complete the factory-installedfunctions and enable the 5585 to operate as a complete turnkey
solution for many applications, thereby saving the cost and timeof custom IP development.

EXTENDABLE IP DESIGNFor applications that require specialized functions, users caninstall their own custom IP for data processing. The Navigator
FPGA Design Kits include all of the factory-installed modules as
documented source code. Developers can integrate their own IPwith the factory-installed functions or use the Navigator kit tocompletely replace the Mercury IP with their own.

XILINX VIRTEX ULTRASCALE+ HBM FPGAThe 5585 features the VU37P Virtex UltraScale+ HBM. The
FPGA’s 8 GB of on-chip HBM SDRAM supports memory
bandwidth of up to 460 GB/s. This represents better than a 20X
throughput increase over traditional, external DDR4 SDRAM.
This increased performance addresses the ever-accelerating
memory requirements of high bandwidth, high computation
applications. Additional resources include 9024 DSP slices, 2.8
million system logic cells and 32.7 Gb/s GTY gigabit serialtransceivers.

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A/D ACQUISITION IP MODULES

For each transfer, the acquisition module can automaticallyconstruct metadata packets containing A/D channel ID, asample-accurate time stamp, and data length information.
These actions simplify the host processor’s job of identifying
and executing on the data.

DDC IP CORES
Within each A/D Acquisition IP Module is a powerful DDC IP
core. Because of the flexible input routing of the A/DAcquisition IP Modules, many different configurations can beachieved, including one A/D driving all DDCs or each of the A/Ds
driving its own DDC.
Each DDC has an independent 32-bit tuning frequency settingthat ranges from DC to ƒs, where ƒs is the A/D sampling
frequency. Each DDC can have its own unique decimation
setting, supporting as many as three different output
bandwidths for the board. Decimations can be programmed
from 2 to 32,768, providing a wide range to satisfy mostapplications.
The decimating filter for each DDC accepts a unique set ofuser-supplied 18-bit coefficients. The 80% default filters deliver
an output bandwidth of 0.8*ƒs/N, where N is the decimation
setting. The rejection of adjacent-band components within the80% output bandwidth is better than 100 dB. Each DDC delivers
a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of ƒs/N.

CLOCKING AND SYNCHRONIZATION
An on-board timing bus generator uses a programmablefrequency synthesizer to generate the sample clock and all
required timing signals, enabling the board to operate with noadditional clocks required. For applications that require anexternal sample clock, the 5585 can receive the full rate sample

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TECHNICAL DATA SHEETJade 5585

clock through one of the VITA 67.3C connections, or in analternate mode, a reference clock can be received on thisconnection and used to lock the on-board sample clock to ahouse reference. A multifunction gate/trigger input is alsoavailable on one of the VITA 67.3C connections for external
control of data acquisition as well as a sync input signal forresetting counters and clocks on the board.
For larger systems requiring multi-board synchronization, amultisignal sync bus interface is provided on the VPX P1
connector. This interface includes the reference clock, thegate/trigger input, and the sync signal The Model 5503 HighSpeed Synchronizer and Distribution 3U VPX Board is available
as a programmable clocking and sync source for these highchannel-count systems.

ARM PROCESSOR
The 5585's on-board ARM processor provides a path toreprogram the FPGA through 1 GigE. This is ideal forapplications that might need to dynamically change FPGA
functionality during deployment. The processor runs Linux.

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INTEGRATED PLATFORM MANAGEMENT CONTROLLER
The 5585 uses an Integrated Platform Management Controller(IPMC) to provide a fully compliant and flexible management solution
for Field Replaceable Units (FRU) that support the VITA 46.11
standard required by HOST and SOSA architectures. The IPMC
provides a standardized implementation of FRU management
interfaces, control signals and sensor monitoring.
The IPMC provides the Chassis Manager and higher-level System
Management Software (SMS) access to FRU information, FRU
control signals and sensor monitoring functions so that they
can identify, activate/de-activate, reset and monitor the healthof the card and take appropriate system control actions.
The IPMC also provides a low-level path for configuration
management and FRU maintenance through both IPMI
messages and a Maintenance Port (MP) serial interface. The
maintenance port provides a terminal mode command-line
interface and supports monitoring, data uploads and FRU-leveltroubleshooting.

4TECHNICAL DATA SHEETJade 5585

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IPcores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installedFPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jade
design. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of all
hardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSP
components. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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TECHNICAL DATA SHEETJade 5585

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade boardand Navigator BSP and start viewing analog signals immediately.

6TECHNICAL DATA SHEETJade 5585

SPECIFICATIONS
Analog Inputs
Quantity: 8Connector: VITA 67.3C

Gate/Trigger In
Connector: VITA 67.3C

Option -763: L3a (conduction-cooled)

Level: LVTTL▪ Operating Temp: 0° to 70° C▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, noncondensing

Sync In

Input Type: Transformer-coupled

Connector: VITA 67.3C

Transformer Type: Coil Craft WBC46TLB

Level: TTL

Full Scale Input: +4 dBm into 50 ohms
3 dB Passband: 300 MHz to 700 MHz

A/D Converters
Type: Texas Instruments ADS42LB69
Sampling Rate: 10 MHz to 250 MHz

Environmental

ARM Processor
Type: 64-bit Cortex-A53 core
Speed: 800 MHz
Memory: 4 Gb DDR3L SDRAM
Ethernet: 1 GigE on VPX-P1

Field Programmable Gate Array

PhysicalDimensions: VPX board▪ Depth: 170.61 mm (6.717 in)▪ Height: 100 mm (3.937 in)
Weight: TBD

OpenVPX Compatibility

Type: Xilinx Virtex UltraScale+ HBM
XCVU37P

The 5585 is compatible with thefollowing module profile, as defined bythe VITA 65 OpenVPX Specification:Quantity: Eight channels

Speed: (standard) -1 speed grade

SLT3-PAY-1F1U1S1S1U2F1H-14.6.11-12

Decimation Range: 2x to 32,768x inthree stages of 2x to 32x▪ Option -002: -2 speed grade

Resolution: 16 bits

Digital Downconverters (FPGA IP)

LO Tuning Freq. Resolution: 32 bits, 0to ƒs
LO SFDR: >108 dB
Phase Offset Resolution: 32 bits, 0 to360 degrees
FIR Filter: 18-bit coefficients, 24-bit
output, user-programmablecoefficients
Default Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dB
stopband attenuation

Sample Clock Source
On-board clock synthesizer

Clock Synthesizer
Clock Source: Selectable from onboard programmable VCXO (10 to 810MHz) or LVPECL timing bus
Synchronization: VCXO can be locked
to an external 4 to 180 MHz PLL
system reference, typically 10 MHz,
received through the VITA 67.3C
connector
Clock Dividers: External clock or VCXO
can be divided by 1, 2, 4, 8, or 16 for
the A/D clock

System Logic Cells: 2,852k
HBM DRAM: 8 GBytes
Total Block RAM: 70.9 Mb
UltraRAM: 270.0 Mb
DSP Slices: 9,024

FPGA I/O
Interface: GPIO
▪ Quantity: 2 pairs▪ Type: LVDS
▪ Location: VPX-P1
Interface: 10 GigE
▪ Location: VPX-P1
Interface: 40 GigE
▪ Location: VPX-P1
Interface: Optical (Option -108)▪ Quantity: 8 full duplex lanes▪ Speed: 28 Gb/sec▪ Laser: 850 nm▪ Location: VITA 67.3C (VPX-P2)
Interface: PCI-Express▪ Type: Gen 1, 2, or 3: x4▪ Location: VPX-P1
FPGA Configuration FLASH:
2x 1 Gbit QSPI

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TECHNICAL DATA SHEETJade 5585

ORDERING INFORMATION
Model5585

LIFETIME SUPPORT FOR JADE PRODUCTS

Description
8-channel 250 MHz A/D SOSA aligned 3U VPX board withVirtex UltraScale+ HBM FPGAOptions:-002-2 FPGA speed grade,-1 standard-089

XCVU37P FPGA-108

VITA 67.3C 8X optical interface-114

VITA 67.3C with 8 A/D, External Clock/Reference, Trigger,
Sync connections installed-214

Alternate RF pin-out configuration-763

Conduction-cooled, Level L3

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reducedcosts, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

Contact Mercury for compatible option combinations and complete
specifications of rugged and conduction-cooled versions.

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn moreAvenue Eugène-Lance, 38PO Box 584
CH-1212 Grand-Lancy 1Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF5585

Visit: mrcy.com/go/MP5585+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Jade and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2023 Mercury Systems, Inc. 1-0-022723-DS-J5585

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