TECHNICAL DATA SHEETJade 54810
LVDS digital I/O
3U VPX board with Kintex UltraScale FPGAHigh-performance
offload co-processor▪ Fully customizable I/O signal status andcontrol interface▪ 38 pairs of Configurable LVDS
Digital I/O▪ Meets needs from low cost to highperformance▪ Choice of FPGA resources

The Jade® 54810 is designed to work with the Navigator® Design
Suite of tools. The combination of Jade and Navigator offers
users an efficient path to developing and deploying FPGA-based
data processing IP.
In addition to supporting PCI Express Gen. 3 as a native interface, the 54810 includes
optional high-bandwidth serial and parallel connections to the Kintex UltraScale FPGA forcustom digital I/O.

FEATURES▪ Supports Xilinx® Kintex® UltraScale™ FPGA
▪ Front panel digital I/O can be used as a status and control or data interface▪ PCI Express interface (Gen. 1, 2 & 3) up to x8▪ Compatible with VITA-46, VITA-48 and VITA-65 (OpenVPX™ Specification)▪ Optional LVDS and gigabit serial connections for custom FPGA I/O

THE JADE ARCHITECTURE
Evolved from the proven designs of Mercury’s Cobalt® and Onyx® families, Jade® raises theprocessing performance while lowering the overall power requirements by building on the Xilinx
family of Kintex UltraScale FPGAs. As the central feature of the board architecture, the FPGA
has access to all data and control paths, enabling factory-installed functions as well as
providing an ideal platform for user-created intellectual property (IP).

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TECHNICAL DATA SHEETJade 54810

54810 BLOCK DIAGRAM (STANDARD CONFIGURATION AND OPTION -109 SHOWN.)

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TECHNICAL DATA SHEETJade 54810

54810 BLOCK DIAGRAM (OPTIONS -111 AND -112 SHOWN.)

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XILINX KINTEX ULTRASCALE FPGASVPX-P2 INTERFACE OPTIONS

Depending on the requirements of the processing task, the Kintex
Ultrascale can be selected from a range of FPGAs: KU035 through
KU115. The KU115 features 5520 DSP48E2 slices and is ideal formodulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals betweentransmission and reception. For applications not requiring large
DSP resources or logic, a lower-cost FPGA can be installed.

When purchased with option -110, the 54810 supports theemerging VITA 66.5 standard and provides four optical duplex
lanes to a mating VITA 66.5 backplane connector. With theinstallation of a serial protocol like 10 or 40 Gigabit Ethernet inthe FPGA, the VITA 66.5 interface enables high bandwidthcommunications between boards or chassis independent of thePCIe interface.

FRONT PANEL DIGITAL I/O INTERFACE

Options -111 and -112 provide analog signal routing through theVPX backplane. Both options replace front panel connectors for
RF In, RF Out, Sample Clock/ Reference Clock In andGate/Trigger/ Sync/PPS In with coax signals that pass throughthe backplane for connections to other boards or chassis.
Option -111 is compatible with VITA 67.2 and option -112 iscompatible with VITA 67.3C.

The 54810 includes an 80-pin front panel connector thatprovides 38 LVDS pairs connected to the FPGA. With user IP,
these can be utilized for a control and status interface to othercomponents of the system or as a data path.

MEMORY RESOURCES
The 54810 architecture supports a 5 GB bank of DDR4 SDRAM
memory. User-installed IP along with the Mercury-suppliedDDR4 controller core within the FPGA can take advantage of thememory for custom applications.

PCI EXPRESS INTERFACEThe 54810 includes an industry standard interface fully compliant
with PCI Express Gen. 1, 2, and 3 bus specifications. Supporting PCIe
links up to x8, the interface includes multiple DMA controllers for
efficient transfers to and from the module.

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NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processingpower of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IPcores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installed
FPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jade
design. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of all
hardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSP
components. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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Because all Jade boards are shipped with a full suite of built-inIP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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FRONT PANEL CONNECTIONSThe XMC front panel includes a 80-pin digital input/output
connector. The front panel also includes two LED indicators.
▪ User LEDs: The two yellow USR 1 and USR 2
LEDs indicate Input/Output operating status.
▪ Digital I/O Connector: The 80-pin
connector provides 32 digital input/output
Data bits, Clock, Data Valid, and Data suspend
signals. Three pairs of spare pins areavailable for user applications.

Custom I/O▪ Option -104: provides 24 pairs of LVDS connections
etween the FPGA and the VPX P2 connector for custom
I/O (not available with options -111 and -112)▪ Option -105: provides an 8X gigabit link between the FPGA
and the VPX P1 connector to support serial protocols
gigabit link to 4X when combined with option -110).
▪ Option -110: VITA 66.5 interface provides optical 4X duplexlanes▪ Option -111: VITA 67.2: digital input/output data bits,clock, data valid, and data suspend▪ Option -112: VITA 67.3C: digital input/output data bits,clock, data valid, and data suspend

MemoryType: DDR4 SDRAM
Size: 5 GB
Speed: 1200 MHz (2400 MHz DDR)

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 or x8

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing

SPECIFICATIONS
Front Panel Digital I/OConnector Type: 80-pin connector, mates to a ribbon cableconnector

Option -702: L2 (air-cooled)▪ Operating Temp: -20° to 65° C▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

Signal Quantity: 38 pairs

Option -713: L3 (conduction-cooled)

Signal Type: LVDS

▪ Operating Temp: -40° to 70° C

Field Programmable Gate Array▪ Standard: Xilinx Kintex UltraScale XCKU035-2▪ Option -084: Xilinx Kintex UltraScale XCKU060-2▪ Option -087: Xilinx Kintex UltraScale XCKU115-2▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: 3U VPX board▪ Depth: 170.61 mm (6.717 in)▪ Height: 100 mm (3.937 in)
Weight: Approximately 14 oz (400 grams)

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ORDERING INFORMATION
Model

Description

associated with building and testing a development system thatensures optimum performance of Jade boards. Please contact
Mercury to configure a system that matches your requirements.

54810

LVDS Digital I/O 3U VPX with Kintex UltraScale FPGAFORM FACTORS-084

XCKU060-2 FPGAJade products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Jade Model 71810 XMC(LVDS Digital I/O with Kintex UltraScale FPGA) has the following
variants:-087

XCKU115-2 FPGA-104

LVDS FPGA I/O through P14 connector-105

Gigabit serial FPGA I/O

54810

3U VPX board (single XMC with optical/backplane RF)-110

VITA 66.5 interface provides optical 4X duplex lanes

57810

6U VPX board (single XMC)

-111

VITA 67.2: digital input/output data bits, clock, data valid,and data suspend

58810

6U VPX board (dual XMC)

-112

VITA 67.3C: digital input/output data bits, clock, data valid,and data suspend

71810

XMC module-702

Air-cooled, Level 2-763

Conduction-cooled, Level 3

Options:

Contact Mercury for compatible option combinations and complete
specifications of rugged and conduction-cooled versions. Options maychange, so be sure to contact Mercury for the latest information.

DEVELOPMENT SYSTEMS
Mercury offers development systems for Jade products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense

Corporate Headquarters
50 Minuteman RoadAndover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

Model

LIFETIME SUPPORT FOR JADE PRODUCTS
Mercury offers worldwide customers shorter development time,reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF54810

Visit: mrcy.com/go/MP54810+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation ThatMatters, Jade and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2023 Mercury Systems, Inc. 1-0-011023-DS-J54810

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