TECHNICAL DATA SHEET

Onyx 52741
1-channel 3.6 GHz or 2-channel 1.8 GHz,
12-bit A/D with wideband DDC
3U VPX board with Virtex-7 FPGA

Complete radarand software radio
interface solution▪ Radar and software radio receiver▪ Remote monitoring▪ Communications receiver▪ Sensor interfaces▪ Analog signal interface for data recording▪ Wideband data acquisition

The 52741 is a high-speed data converter with a programmable
DDC, suitable for connection to HF or IF ports of a communications
or radar system. Its built-in data capture features offer an ideal turnkey
solution.
The 52741 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition
to supporting PCI Express Gen. 3 as a native interface, the 52741 includes an optional
connection to the Virtex-7 FPGA for custom I/O.

FEATURES▪ Supports Xilinx® Virtex®-7 VXT FPGA
▪ GateXpress® supports dynamic FPGA reconfiguration across PCIe
▪ One-channel mode with 3.6 GHz, 12-bit A/D▪ Two-channel mode with 1.8 GHz, 12-bit A/Ds
▪ Programmable one- or two-channel DDC (Digital Downconverter)▪ 4 GB of DDR3 SDRAM▪ µSync clock/sync bus for multiboard synchronization▪ PCI Express (Gen. 1, 2 & 3) interface up to x4▪ Optional user-configurable gigabit serial interface▪ Optional LVDS connections to the Xilinx® Virtex®-7 FPGA for custom I/O▪ Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65(OpenVPX™ System Specification

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TECHNICAL DATA SHEET
Onyx 52741

52741 BLOCK DIAGRAMS

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Onyx 52741

THE ONYX ARCHITECTURE
Based on the proven design of the Mercury Cobalt family, Onyx
raises the processing performance with the new flagship familyof Virtex-7 FPGAs from Xilinx. As the central feature of theboard architecture, the FPGA has access to all data and control
paths, enabling factory-installed functions including data
multiplexing, channel selection, data packing, gating, triggeringand memory control. The Onyx Architecture organizes the FPGA
as a container for data processing applications where eachfunction exists as an intellectual property (IP) module.
Each member of the Onyx family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The 52741 factory-installed functions include an A/D
acquisition IP module and a programmable digital
downconverter. In addition, IP modules for DDR3 SDRAM
memories, a controller for all data clocking and synchronization
functions, a test signal generator and a PCIe interface complete
the factory-installed functions and enable the 52741 to operate
as a complete turnkey solution, without the need to develop any
FPGA IP.

EXTENDABLE IP DESIGNFor applications that require specialized functions, users can install
their own custom IP for data processing. The GateFlow FPGA
Design Kits include all of the factory-installed modules as document
source code. Developers can integrate their own IP with thefactory-installed functions or use the GateFlow kit to completely
replace the IP with their own.

XILINX VIRTEX-7 FPGAThe Xilinx Virtex-7 FPGA site can be populated with one of two FPGAs
to match the specific requirements of the processing task. Supported
FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1
slices and is ideal for modulation/demodulation, encoding/decoding,encryption/decryption, and channelization of the signals between
transmission and reception. For applications not requiring large DSP
resources or logic, the lower-cost VX330T can be installed.

The ADC12D1800 provides a programmable 15-bit gain
adjustment allowing the 71741 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSync feature supports A/D
synchronization across multiple boards.
The A/D digital outputs are delivered into the Xilinx® Virtex®-7
FPGA for signal processing, data capture or for routing to otherboard resources.

A/D ACQUISITION IP MODULES
The 52741 features an A/D Acquisition IP Module for easy
capture and data moving. The IP module can receive data fromthe A/D, or a test signal generator. The IP module has
associated memory banks for buffering data in FIFO mode or forstoring data in transient capture mode. In single-channel mode,
all four banks are used to store the single-channel of input data.
In dual-channel mode, memory banks 1 and 2 store data from
input channel 1 and memory banks 3 and 4 store data from input
channel 2. In both modes, continuous, full-rate transient
capture of 12-bit data is supported.
The memory banks are supported with a DMA engine for moving
A/D data through the PCIe interface. This powerful linked-list
DMA engine is capable of a unique Acquisition Gate Driven
mode. In this mode, the length of a transfer performed by a link
definition need not be known prior to data acquisition; rather, it
is governed by the length of the acquisition gate. This isextremely useful in applications where an external gate drives
acquisition and the exact length of that gate is not known or is
likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing a sample-accurate time stampand data length information. These actions simplify the hostprocessor’s job of identifying and executing on the data.

A/D CONVERTER STAGE
The board's analog interface accepts analog HF or IF inputs on apair of front panel SSMC connectors with transformer coupling
into a Texas Instruments ADC12D1800 12-bit A/D. The converter
operates in single-channel interleaved mode with a sampling
rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dualchannel mode with a sampling rate of 1.8 GHz and input
bandwidth of 2.8 GHz.

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Onyx 52741

DDC IP CORESGATEXPRESS FOR FPGA CONFIGURATION

Within the FPGA is a powerful DDC IP core. The core supports asingle-channel mode, accepting data samples from the A/D atthe full 3.6 GHz rate. Additionally, a dual-channel mode supports
the A/Ds 1.8 GHz two-channel operation.

The Onyx architecture includes GateXpress®, a sophisticated
FPGA-PCIe configuration manager for loading and reloading the
FPGA. At power up, GateXpress immediately presents a PCIetarget for the host computer to discover, effectively giving the
FPGA time to load from FLASH. This is especially important forlarger FPGAs where the loading times can exceed the PCIe
discovery window, typically 100 msec on most PCs.

In dual-channel mode, each DDC has an independent 32-bit
tuning frequency setting that ranges from DC to ƒs, where ƒs is
the A/D sampling frequency. In single-channel mode,decimation can be programmed to 8x, 16x or 32x. In dualchannel mode, both channels share the same decimation rate,
programmable to 4x, 8x or 16x.
In single-channel mode, decimation can be programmed to 8x,
16x or 32x. In dual-channel mode, both channels share the same
decimation rate, programmable to 4x, 8x or 16x.
The decimating filter for each DDC accepts a unique set ofuser-supplied 18-bit coefficients. The 80% default filters deliver
an output bandwidth of 0.8*ƒs/N, where N is the decimation
setting. The rejection of adjacent-band components within the
80% output bandwidth is better than 100 dB. Each DDC delivers
a complex output stream consisting of 24-bit I + 24-bit Q or16bit I + 16-bit Q samples at a rate of ƒs/N.

CLOCKING AND SYNCHRONIZATION
The 52741 accepts a 1.8 GHz dual-edge sample clock via a front
panel SSMC connector. A second front panel SSMC accepts a
TTL signal that can function as Gate, PPS or Sync.
A front panel µSync bus connector allows multiple boards to besynchronized, ideal for multichannel systems. The µSync bus
includes gate, reset, and in and out reference clock signals. Two
52741s can be synchronized with a simple cable. For larger
systems, multiple 52741s can be synchronized using the Model
5292 high-speed sync board to drive the sync bus.

MEMORY RESOURCES
The 52741 architecture supports four independent DDR3 SDRAM
memory banks. Each bank is 1 GB deep and is an integral part ofthe module’s DMA capabilities, providing FIFO memory space forcreating DMA packets. Built-in memory functions include
multichannel A/D data capture, tagging and streaming.

The board’s configuration FLASH can hold four FPGA images.
Images can be factory-installed IP or custom IP created by the user,
and programmed into the FLASH via JTAG using Xilinx iMPACT or
through the board’s PCIe interface. At power up the user canchoose which image will load based on a hardware switch setting.
Once booted, GateXpress allows the user three options for
dynamically reconfiguring the FPGA with a new IP image:▪ The first is the option to load an alternate image from
FLASH through software control. The user selects thedesired image and issues a reload command.
▪ The second option is for applications where the FPGA
image must be loaded directly through the PCIe interface.
This is important in security situations where there can be
no latent user image left in nonvolatile memory whenpower is removed. In applications where the FPGA IP may
need to change many times during the course of a
mission, images can be stored on the host computer andloaded through PCIe as needed.
▪ The third option, typically used during development,
allows the user to directly load the FPGA through JTAG
using Xilinx iMPACT.
In all three FPGA loading scenarios, GateXpress handles the
hardware negotiation simplifying and streamlining the loadingtask. In addition, GateXpress preserves the PCIe configuration
space allowing dynamic FPGA reconfiguration without a hostcomputer reset to rediscover the board. After the reload, thehost simply continues to see the board with the expected
device ID.

PCI EXPRESS INTERFACEThe Model 52741 includes an industry-standard interface fullycompliant with PCI Express Gen. 1, 2 and 3 bus specifications.
Supporting PCIe links up to x8, the interface includes multiple
DMA controllers for efficient transfers to and from the board.

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Onyx 52741

READYFLOW
Mercury provides ReadyFlow® BSPs (Board Support Packages) for
all Cobalt, Onyx, and Flexor products. Available for both Linux andWindows, these packages:▪ Provide a path for quick start-up through application
completion▪ Allow programming at high, intermediate and low levels tomeet various needs▪ Are illustrated with numerous examples▪ Include complete documentation and definitions of all
functions▪ Include library and example source code.
ReadyFlow BSPs contain C-language examples that can be used
to demonstrate the capabilities of Cobalt, Onyx, and Flexor
products. These programming examples will help you get an
immediate start on writing your own application. They provide
sample code that is known to work, giving you a means ofverifying that your board set is operational.

COMMAND LINE INTERFACEThe Command Line Interface provides access to pre-compiled
executable examples that operate the hardware right out of thebox, without the need to write any code. Board-specific hardware

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operating arguments can be entered in the command line tocontrol parameters: number of channels to enable, sample
clock frequency, data transfer size, reference clock frequency,
reference clock source, etc.
The Command Line Interface can be used to call an example
application from within a larger user application to control the
hardware, and parameter arguments are passed to theapplication for execution. Functions that control dataacquisition automatically save captured data to a pre-named
host file or are routed to the Signal Analyzer example function
for display.

SIGNAL ANALYZER
When used with the Command Line Interface, the Signal
Analyzer allows users to immediately start acquiring anddisplaying A/D data. A full-featured analysis tool, the Signal
Analyzer displays data in time and frequency domains. Built-in
measurement functions display 2nd and 3rd harmonics, THD,
and SINAD. Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals.

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Onyx 52741

GATEFLOWThe User Application Container

The GateFlow® FPGA Design Kit (FDK) allows the user to modify,

Shown below is the FPGA block diagram of a typical Cobalt,
Onyx or Flexor module. The User Application Container holds acollection of different installed IP modules connected to thevarious interfaces through the standard ports surrounding thecontainer. The specific IP modules for each product aredescribed in further detail in the datasheet of that product.

replace and extend the standard installed functions in the FPGA
to incorporate special modes of operation, new control
structures, and specialized signal-processing algorithms.
The Cobalt (Virtex-6), Onyx (Virtex-7), and Flexor (Virtex-7)
architectures configure the FPGA with standard factory-suppliedinterfaces including memory controllers, DMA engines, A/D and
D/A interfaces, timing and synchronization structures, triggeringand gating logic, time stamping and header tagging, data
formatting engines, and the PCIe interface. These resources areconnected to the User Application Container using well-defined
ports that present easy-to-use data and control signals,
effectively abstracting the lower-level details of the hardware.

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The GateFlow FDK provides a complete Xilinx's ISE or Vivado
project folder containing all the files necessary for the FPGA
developer to recompile the entire project with or without any
required changes. VHDL source code for each IP module
provides excellent examples of how the IP modules work, how
they might be modified, and how they might be replaced withcustom IP to implement a specific function.

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Onyx 52741

FRONT PANEL CONNECTIONSSPECIFICATIONSThe XMC front panel includes four SSMC coaxial connectors anda 19-pin Sync Bus connector for input/output of timing andanalog signals. The front panel also includes five LEDs.

Front Panel Analog Signal Inputs
Input Type: Transformer-coupled, front panel female SSMC
connectors

A/D Converter▪ PPS LED: The green PPS LED
illuminates when a valid PPS signal isdetected. The LED will blink at the rateof the PPS signal.
▪ PPS Input Connector: The
SSMC coaxial connector, labeled
PPS IN is for input of an external PPS or
Gate signal.
▪ Sync Bus Connector: The 19-pin Sync
Bus front panel connector, labeled
SYNC/GATE, provides clock, sync, andgate input/output pins for the Sync Bus.
▪ Over Temperature LED: The red TMP
LED illuminates when an overtemperature or over-voltage condition isindicated by any of thetemperature/voltage sensors on the
PCB.
▪ Link LED: The green LNK LED blinks
when a valid link has been establishedover the PCIe interface.
▪ Analog Input Connectors: Two SSMC
coaxial connectors, labeled IN 1 and IN
2 are for each ADC12D1800 input
channel.
▪ A/D Overload LED: There is one red
OV (overload) LED for the A/D input. It
indicates either an analog input overload in the associated
ADC12D1800, or an ADC FIFO overrun.
▪ Clock LED: The green CLK LED illuminates when a valid
sample clock signal is detected. If the LED is notilluminated, no clock has been detected and no data fromthe input stream can be processed.
▪ Clock Input Connector: One SSMC coaxial connector,
labeled EXT CLK IN, for input of an external sample
clock.

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Type: Texas Instruments ADC12D1800
Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz;
dual-channel mode: 150 MHz to 1.8 GHz
Resolution: 12 bits
Input Bandwidth: single-channel mode: 1.75 GHz; dualchannel mode: 2.8 GHz
Full Scale Input: +2 dBm to +4 dBm, programmable

Digital Downconverters
Modes: One or two channels, programmable
Supported Sample Rate: One-channel mode: 3.6 GHz, twochannel mode: 1.8 GHz
Decimation Range: One-channel mode: 8x, 16x or 32x, twochannel mode: 4x, 8x, or 16x
LO Tuning Freq. Resolution: 32 bits, 0 to ƒs
LO SFDR: >120 dB
Phase Offset Resolution: 32 bits, 0 to 360 degrees
FIR Filter: User-programmable 18-bit coefficients
Default Filter Set: 80% bandwidth, <0.3 dB passband ripple,>100 dB stopband attenuation

Sample Clock Source
Front panel SSMC connector

Timing Bus
19-pin µSync bus connector includes sync and gate/trigger
inputs, CML

External Trigger Input
Type: Front panel female SSMC connector, LVTTL
Function: Programmable functions include: trigger, gate,
sync and PPS

Field Programmable Gate Array▪ Standard: Xilinx Virtex-7 XC7VX330T-2▪ Optional: Xilinx Virtex-7 XC7VX690T-2

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Onyx 52741

Custom I/O▪ Option -104: Provides 20 pairs of LVDS connections
between the FPGA and the VPX P2 connector for custom
I/O

ORDERING INFORMATION
Model

Description

52741

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D with
Wideband DDC, Virtex-7 FPGA - 3U VPX

Options

Description

Type: DDR3 SDRAM-073

XC7VX330T-2 FPGA

Size: Four banks, 1 GB each-076

XC7VX690T-2 FPGA

Speed: 800 MHz (1600 MHz DDR)

-104

LVDS FPGA I/O to VPX P2-105

Gigabit serial FPGA I/O to VPX P1-702

Air-cooled, Level 2-763

Conduction-cooled, Level 3▪ Option -105: Provides one 8X or two 4X gigabit links
between the FPGA and the VPX P1 connector to support
serial protocols

MemoryPCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C

Contact Mercury for compatible option combinations.

ACCESSORY PRODUCTS▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing

Model

Description

Option -702: L2 (air-cooled)5292

High-Speed Synchronizer and Distribution Board▪ Operating Temp: -20° to 65° C

9192

Rackmount High-Speed System Synchronizer▪ Storage Temp: -40° to 100° C

5294

High-Speed Clock Generator▪ Relative Humidity: 0 to 95%, non-condensing
Option -763: L3 (conduction-cooled)▪ Operating Temp: -40° to 70° C▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: Form Factor: 3U VPX▪ Depth: 170.6 mm (6.717 in.)▪ Height: 100 mm (3.937 in.)
Weight▪ VPX Carrier: 110 grams (3.9 oz.);▪ XMC Module: approximately 400 grams (14 oz.) with 2-slotheatsink

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Onyx 52741

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR ONYX PRODUCTS

Mercury offers development systems for Onyx products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system that
ensures optimum performance of Onyx boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORS
Onyx products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Onyx Model 71741 XMC (1Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D with DDC with
Virtex-7 FPGA) has the following variants:
Model
52741

3U VPX board (single XMC)

57741

6U VPX board (single XMC)

58741

6U VPX board (dual XMC)

71741

XMC module

78741

PCIe board (single XMC)

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For technical details, contact:mrcy.com/go/CF52741

Visit: mrcy.com/go/MP52741+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Cobalt, Flexor, Onyx, GateXpress, GateFlow, and ReadyFlow. Other marks used herein may be trademarks or registered trademarks of theirrespective holders. Mercury believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The
information contained herein is subject to change without notice.
© 2022 Mercury Systems, Inc. 1-0-112322-DS-O52741

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