12AIO
12-Bit Analog Input/Output Board
With 32 Input Channels, 4 Output Channels, a 16-Bit Digital I/O Portand 1.5 MSPS Input Conversion Rate
Available in PMC, PCI, cPCI and PC104-Plus and PCI Express form factors as:
PMC-12AIO:
PMC, Single-width
PCI-12AIO:

PCI, short lengthcPCI-12AIO:

cPCI, 3U

PC104P-12AIO:

PC104-Plus

PCIe-12AIO:

PCI Express

PCIe104-12AIO:

PCIe, one-lane on PC/104 form factor

See Ordering Information for details.
Call for availability of other form factors, such as XMC, CCPMC, etc.

Features:


32 Single-Ended or 16 Differential 12-Bit Scanned Analog Input Channels
4 Analog Output Channels, 12-Bit D/A Converter per Channel
16-Bit Bi-directional Digital Port with Two Auxiliary I/O Lines
Software-Selectable Analog Input/Output Ranges of ±10V, ±5V or ±2.5V
Independent 32K-Sample Analog Input and Output FIFO Buffers
1.5 MSPS Conversion Rate in Single-Channel Mode;
1.0 MSPS in Multichannel Scan Mode; (1.5 MSPS with Accelerated Scanning option)
Low Crosstalk, Noise and Input Bias Current; Buffer Amplifiers on all Analog Input Lines
1.2 MSPS (Megasamples per Second) Aggregate Analog Output Clocking Rate (0.3 MSPS/Chan)(1.6 MSPS aggregate; 0.4MSPS/Chan with optional Accelerated Scanning)
Supports Waveform and Arbitrary Function Generation; Continuous and One-shot Modes
Internal Rate Generator Controls Input Sampling, Output Sampling, or Both Simultaneously
Supports Multiboard Synchronization of Analog Inputs and Outputs
Internal Auto calibration of Analog Input and Output Channels
Continuous and Burst (One-Shot) Input and Output Modes
DMA Engine Minimizes Host I/O Overhead

Applications Include: Acoustics Analysis
 Analog Inputs
 Data Acquisition Systems

 Voltage Measurement
 Process Monitoring Industrial Robotics

 Automatic Test Equipment
 Audio Waveform Analysis
 Environmental Test Systems092513

Functional Description:
The PMC-12AIO board provides cost effective high-speed 12-bit analog input/output resources on astandard single-width PMC module. Four analog output channels can be updated either
synchronously or asynchronously, and support waveform generation. Internal autocalibration
networks permit calibration to be performed without removing the board from the system.
Software-controlled test configurations include a loopback mode for monitoring all analog output
channels. Gain and offset correction of the analog input and output channels is performed bycalibration DAC's that are loaded with channel correction values during autocalibration. A digital
I/O port provides 16 bidirectional data lines and two auxiliary I/O lines.
The analog inputs are software-configurable either as 32 single-ended channels or as 16 differential
signal pairs. Buffer amplifiers on all input lines eliminate multiplexer input switching noise, andminimize crosstalk and input bias currents. Analog input data accumulates in a 32K-sample buffer
until retrieved by the PCI bus. Each of the four analog output channels contains a dedicated 12-bit
D/A converter and an output range control network. The board receives analog output data from thePCI bus through a 32K-sample FIFO buffer.

I/O
ConnAnalog
Inputs32 S.E.,
16 Diff

Input
BufferAmps
Selftest
Switches

Analog
Mux

Input
Range
Control

12-BIT ADC

Loopback
Voltage
Reference

Vtest OutInput
Sync I/O

8-Bit
Calibration
DAC’SAIBuffer
AO
Buffer

PCI
Conn
PCI
Interface
Adapter

LocalController

12-BitOutput
DAC’s(4)I/O
Conn
AnalogOutputs
4 S.E.

Local Bus

Figure 1. PMC-12AIO; Functional Organization
This product is functionally compatible with the IEEE PCI local bus specification Revision 2.3, and supports
the "plug-n-play" initialization concept. System input/output connections are made at the panel bracket
through a high-density 68-pin connector. Power requirements consist of +5 VDC, in compliance with thePCI specification, and operation over the specified temperature range is achieved with conventionalconvection cooling.

ELECTRICAL SPECIFICATIONSO

At +25 C, with specified operating voltages

ANALOG INPUT CHANNELS
 Input Characteristics:
Configuration:

32 input lines, configurable as 32 single-ended or 16 differential channels

Voltage Ranges:

Software configurable as ±10, ±5 or ±2.5 Volts

Input Impedance:
Bias Current:

1.0 Megohms line-to-ground, 2.0 Megohms line-to-line, in parallel with 100Pfd.
Independent of scan rate.
80 nanoamps maximum

Noise:

0.7 LSB-RMS typical

Common Mode Rejection:

60 dB typical, DC-60 Hz, differential input mode

Common Mode Range:±10 Volts; differential input configuration

Overvoltage Protection:

Standard: ±30 Volts with power applied; ±15 Volts with power removed

 Transfer Characteristics:
Resolution:

12 Bits; 0.0244 percent of FSR

Maximum Conversion Rate:

1500K conversions per second, minimum in single-channel mode,
1000K in multichannel modes (1500K with 'Accelerated Scanning' factory option).

Channels per scan:2, 4, 8, 16, or 32 Channels per scan (32 channels available only in single-ended mode)

Maximum Scan Rate:

1500K scans/sec in single-channel mode. 31K-500K scans per second in scanningmodes (47K-750K scans per second with Accelerated Scanning option).
Scan rate equals the conversion rate divided by the number of channels per scan.

Minimum Scan Rate:

458 scans per second, using a single internal rate generator; 0.007SPS using bothgenerators. Zero, using a software sync flag or an externally supplied sync input.

DC Accuracy:(Maximum composite error,referred to inputs)

Range
±10V
±5V
±2.5V

Crosstalk Rejection:

75dB, DC-10kHz

Integral Nonlinearity:±0.024 percent of FSR, maximumDifferential Nonlinearity:±0.024 percent of FSR, maximum

Midscale Accuracy±4.2mV±3.5mV±2.5mV±Fullscale Accuracy±8.4mV
±5.2mV
±4.0mV Analog Input Operating Modes and Controls
Analog Input Modes:

Single Scan:

A software or hardware sync initiates a single scan of all active
channels at the maximum conversion rate. As many as threetarget boards can be synchronized to a single initiator board.

Continuous Scan:

Inputs are scanned continuously at the selected scan rate.

Selftest:

Reference and loopback tests; autocalibration

Analog Input Modes (Cont.):

Input Data Buffer:

Multiple-Channel:

2, 4, 8, 16 or 32 channels per scanSingle-Channel:

Any single-channel can be selected for digitizing at themaximum conversion rate.

32K-sample FIFO with 0000h-7FFEh adjustable threshold flag; DMA is supported

ANALOG OUTPUT CHANNELS Output Characteristics:
Configuration:

Four single-ended output channels. (Ordering option)

Voltage Ranges:

Same as selected for analog inputs; ±10, ±5 or ±2.5 Volts

Output Resistance:

1.0 Ohm, maximum

Output protection:

Withstands sustained short-circuiting to ground

Load Current:

Zero to ±3ma per channel

Load Capacitance:

Stable with zero to 2000 pF shunt capacitance

Noise:

2.0mV-RMS, 10Hz-100KHz typical

Glitch Impulse:

5 nV-Sec typical, ±2.5V range

 Transfer Characteristics:
Resolution:

12 Bits (0.0244 percent of FSR)

Output Sample Rate:

Software adjustable from 458SPS to 400KSPS per channel with optional accelerated
scanning; 366SPS to 300KSPS standard; 0.007SPS to 400KSPS (300KSPS standard)using both internal rate generators. DC to 400KSPS (DC-300KSPS standard) withhardware or software sync.
Range
Midscale Accuracy±Fullscale Accuracy±10V±4.0mV
±7.5mV±5V±3.1mV±4.7mV±2.5V±2.0mV±3.5mV

DC Accuracy:(Max error, no-load)Settling Time:

8us to 1LSB, typical with 50-percent fullscale step

Crosstalk Rejection:

65 dB minimum, DC-1000Hz

Integral Nonlinearity:±0.025 percent of FSR, maximum

Differential Nonlinearity:±0.015 percent of FSR, maximum

 Analog Output Operating Modes and Controls
Clocking Modes:

Simultaneous Continuous Mode: Channel values in a designated channel group arestored in an intermediate buffer, and then are transferred to the output DAC's when anoutput clock occurs. The clock can be generated either by the internal rate generator,
by a software flag, or by an external hardware trigger. As many as three target boards
can be clock-synchronized to a single initiator board.
Simultaneous Burst Mode: A single function (i.e.: burst) is initiated by a software orhardware sync. During a burst, channel values in a designated channel group are stored
in a transfer buffer, and then are transferred to the output DAC's each time a clock
pulse is generated by the internal rate generator. The burst terminates when a Burst
End flag is encountered.

Clocking Modes (Cont.):

Channel-Sequential Modes: Same as simultaneous modes, but each value in the data
buffer is written immediately to the associated output DAC. The group-end flag isignored in this mode.

Channel Assignment:

A 2-bit field in the output buffer assigns the associated data field to a specific output
channel.

Group End:A single bit in the output buffer indicates the last value in a channel group.

Burst End:A single bit in the output buffer indicates the last value in an output burst sequence.

Output Data Buffer:

32K-sample FIFO with 0000h-7FFEh adjustable threshold flag; DMA is supported

RATE GENERATORS
Analog outputs and inputs can be clocked from either of two independent rate generators, or both inputs and outputs
can be synchronized to a single generator. Each rate generator uses a 16-bit adjustable frequency divider, and thetwo generators can be operated in series to provide very low clocking rates.

DIGITAL I/O PORTThe digital I/O port consists of 16 bidirectional data lines, one auxiliary input line and one auxiliary output line. Aninterrupt request can be generated in response to the auxiliary input. The data lines are organized as two data bytes,
each of which can be configured independently as either an input or output byte. Standard TTL logic levels apply,with 20 ma current-sink capability per output line.

PCI INTERFACE
 Compatibility:

Conforms to PCI Specification 2.3, with D32 read/write transactions.
Supports "plug-n-play" initialization.
Provides one multifunction interrupt.
Supports DMA transfers as bus master.

MECHANICAL AND ENVIRONMENTAL SPECIFICATIONS Power Requirements+5VDC ±0.2 VDC at 1.3 Amps, maximum
Maximum Power Dissipation: 5.5 Watts, Side 1;

1.0 Watt, Side 2 Physical Characteristics (PMC Form Factor)
Height:Depth:
Width:
Shield:13.5 mm (0.53 in)
149.0 mm (5.87 in)
74.0 mm (2.91 in)
Optional EMI shield available for Side 1.

 Environmental Specifications
Ambient Temperature Range:

Operating: 0 to +65 degrees Celsius inlet airStorage: -40 to +85 degrees CelsiusRelative Humidity:

Operating: 0 to 80%, non-condensing
Storage: 0 to 95%, non-condensing
Operation to 10,000 ft.
Conventional convection cooling.

Altitude:Cooling:ORDERING INFORMATION
Specify the basic product model number followed by an option suffix "-ABCD", as indicated below. For example,
model number PMC-12AIO-41A describes a board with 4 output channels, a bezel and EMI shield, accelerated
scanning, and no custom features.

Basic Model Number

Form Factor

PMC-12AIO

PMC (Native)

PCI-12AIO 1

PCI, short lengthcPCI-12AIO

1cPCI, 3U

PCIe-12AIO

1cPCI, 3U
PC104-Plus

PC104P-12AIO
PCIe104-12AIO
121,2PCIe, one-lane on PC/104 form factor

Module installed and tested on an adapter, with mechanical and functional equivalency.
Contact factory for availability in native form factors.
PCIe104 supports only the PCIe bus.
Optional Parameter

Value

Number of Analog Outputs

No Output Channels

A=0

4 Output Channels

A=4EMI Shield (Recommended

No bezel or shield

B=0

in high-noise environments)

Bezel & shield installed

B=1

Accelerated Scanning

No acceleration

C=0Accelerated Scanning

C=A---D*Custom FeatureSpecify Option As:* Numeric code, determined by specific feature. Zero (0) if no custom feature applies.

SYSTEM I/O CONNECTIONS
Table 1. System Connector Pin Functions
P5 ROW-APIN

SIGNALP5 ROW-B
PIN

SIGNAL

ROW A

ROW B

34

ANA INP00 HI

34

ANA OUT00

33

ANA INP00 LO *33

OUTPUT RTN

323130ANA INP02 HI
ANA INP02 LO
ANA INP04 HI

323130ANA OUT01
OUTPUT RTN
ANA OUT0229

ANA INP04 LO

29

OUTPUT RTN

282726ANA INP06 HI
ANA INP06 LO
ANA INP08 HI

282726ANA OUT03
OUTPUT RTNVTEST

25ANA INP08 LO

25VTEST RTN

242322ANA INP10 HI
ANA INP10 LO
ANA INP12 HI

242322

DIGITAL RTN
AUX DIGITAL IN
AUX DIGITAL OUT

21ANA INP12 LO

21

DIG IO 00

2019181716

ANA INP14 HI
ANA INP14 LO
INPUT RTN
INPUT RTN
ANA INP16 HI

2019181716

DIG IO 01
DIG IO 02
DIG IO 03
DIG IO 04
DIG IO 05

15ANA INP16 LO

15

DIG IO 06

141312ANA INP18 HI
ANA INP18 LO
ANA INP20 HI

141312DIG IO 07
DIG IO 08
DIG IO 09Panel Pin-view

11ANA INP20 LO11DIG IO 10Figure 2. System Input/Output Connector

1098ANA INP22 HI
ANA INP22 LO
ANA INP24 HI

1098DIG IO 11
DIG IO 12
DIG IO 137ANA INP24 LO

7DIG IO 14654ANA INP26 HI
ANA INP26 LO
ANA INP28 HI

654DIG IO 15
DIGITAL RTN
SYNC OUTPUT

3ANA INP28 LO

3DIGITAL RTN

21ANA INP30 HI
ANA INP30 LO

21SYNC INPUTDIGITAL RTN

PIN 34
P5CONNPWB

PIN 1System Mating Connector:
68-Pin 2-row 0.050" dual-ribbon cable
socket connector: Robinson Nugent#P50E-068-SEA, or equivalent.
Contact factory for availability of the68-pin AMP SCSI-3 connector.

* Analog inputs are shown for the differential input mode. In singleended mode, LO inputs become consecutive odd-numberedchannels, beginning with ANA INP 01 replacing ANA INP 00 LO.

General Standards Corp.
General Standards Corporation assumes no responsibility for the use of any circuits in this product. No circuit patent licenses are implied. Information included hereinsupersedes previously published specifications on this product and is subject to change without notice.