TECHNICAL DATA SHEETJade 78861
4-channel 200 MHz A/D with DDCs
PCIe board with Kintex UltraScale FPGA

Complete radarand software radiointerface solution▪ Radar and software radio receiver▪ Remote monitoring▪ Communications receiver▪ Sensor interfaces▪ Analog signal interface for data recording▪ Wideband data acquisition

The Jade® 78861 is a multichannel, high-speed data converter with
programmable DDCs (digital downconverters). It is suitable forconnection to HF or IF ports of a communications or radar system. Its
built-in data capture feature offers an ideal turnkey solution as well as aplatform for developing and deploying custom FPGA-processing IP.
It includes four A/Ds, a complete multiboard clock and sync section and a large DDR4memory. In addition to supporting PCI Express Gen. 3 as a native interface, the 78861
includes optional high-bandwidth connections to the Kintex UltraScale FPGA for custom
digital I/O.

FEATURES▪ Exceptional dynamic range and analog signal integrity▪ Xilinx® Kintex® UltraScale™ FPGA
▪ Four 200 MHz 16-bit A/Ds
▪ Four multiband DDCs (digital downconverters)▪ 5 GB of 2400 MHz DDR4 SDRAM▪ Sample clock synchronization to an an external reference▪ Programmable frequency synthesized sample clock generator▪ PCI Express interface (Gen. 1, 2 & 3) up to x8▪ Powerful DMA controllers for moving data
▪ Multichannel, multiboard synchronization with clock/sync bus▪ Optional clock/sync generator for multiboard systems▪ Optional LVDS port and gigabit serial connections for custom FPGA I/O▪ Navigator Design Suite for software and custom IP development

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TECHNICAL DATA SHEETJade 78861

78861 BLOCK DIAGRAM
Click on a block for more information.

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THE JADE ARCHITECTURE
Evolved from the proven designs of Mercury’s Cobalt® and Onyx®
families, Jade® raises the processing performance while lowering
the overall power requirements by building on the Xilinx family ofKintex UltraScale FPGAs. As the central feature of the board
architecture, the FPGA has access to all data and control paths,
enabling factory-installed functions as well as providing an ideal
platform for user-created intellectual property (IP).
Each member of the Jade family is delivered with factory-installed
applications ideally matched to the board’s analog interfaces. The
78861 factory installed functions include four A/D acquisition
modules for simplifying data capture and tagging, and a set of
specialized DMA engines for efficient data transfers between theboard and a host computer.
Additional IP includes: four powerful, programmable DDC IP
cores; a controller for all data clocking and synchronization
functions; a test signal generator; and a PCIe interface. These
factory-installed applications enable the 78861 to operate as acomplete turnkey solution for many applications, thereby saving
the cost and time of custom IP development.

XILINX KINTEX ULTRASCALE FPGAS

definition need not be known prior to data acquisition; rather, it
is governed by the length of the acquisition gate. This isextremely useful in applications where an external gate drives
acquisition and the exact length of that gate is not known or is
likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing A/D channel ID, a sample-accurate
time stamp and data length information. These actions simplify
the host processor’s job of identifying and executing on the data.

DDC IP CORES
Within each A/D Acquisition IP Module is a powerful DDC IPcore. Because of the flexible input routing of the A/DAcquisition IP Modules, many different configurations can beachieved including one A/D driving all four DDCs or each of thefour A/Ds driving its own DDC.
Each DDC has an independent 32-bit tuning frequency settingthat ranges from DC to ƒs, where ƒs is the A/D sampling
frequency. Each DDC can have its own unique decimation
setting, supporting as many as four different output bandwidths
for the board. Decimations can be programmed from 2 to 32,768
providing a wide range to satisfy most applications.

Depending on the requirements of the processing task, the Kintex
Ultrascale can be selected from a range of FPGAs: KU035 through
KU115. The KU115 features 5520 DSP48E2 slices and is ideal formodulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between
transmission and reception. For applications not requiring large
DSP resources or logic, a lower-cost FPGA can be installed.

The decimating filter for each DDC accepts a unique set ofuser-supplied 18-bit coefficients. The 80% default filters deliver
an output bandwidth of 0.8*ƒs/N, where N is the decimation
setting. The rejection of adjacent-band components within the
80% output bandwidth is better than 100 dB. Each DDC delivers
a complex output stream consisting of 24-bit I + 24-bit Q or16bit I + 16-bit Q samples at a rate of ƒs/N.

A/D CONVERTER STAGE

CLOCKING AND SYNCHRONIZATIONThe board's analog interface accepts four analog HF or IF inputs
on front panel SSMC connectors with transformer coupling into
four Texas Instruments ADS5485 200 MHz, 16-bit A/Dconverters. The digital outputs are delivered into the Kintex
UltraScale FPGA for signal-processing or routing to other boardresources.

An internal timing bus provides all timing and synchronization
required by the A/D converters. It includes a clock, two sync and two
gate or trigger signals. An on-board clock generator receives anexternal sample clock from the front panel SSMC connector. This
clock can be used directly by the A/D or divided by a built-in clock
synthesizer circuit.

A/D ACQUISITION IP MODULES

In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode,the front panel SSMC connector can be used to provide a 10 MHz
reference clock for synchronizing the internal oscillator.

The 78861 features four A/D Acquisition IP Modules for easily
capturing and moving data. Each IP module can receive datafrom any of the four A/Ds or a test signal generator.
Each IP module has an associated DMA engine for easily moving
A/D data through the PCIe interface. These powerful linked-list
DMA engines are capable of a unique Acquisition Gate Drivenmode. In this mode, the length of a transfer performed by a linkmrcy.com

A front panel 26-pin LVPECL Clock/Sync connector allows
multiple boards to be synchronized. In the slave mode, it
accepts LVPECL inputs that drive the clock, sync and gate

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TECHNICAL DATA SHEETJade 78861

signals. In the master mode, the LVPECL bus can drive thetiming signals for synchronizing multiple boards.
For systems requiring high channel counts, the Model 7893 System
Synchronization and Distribution board can synchronize up to eight78861s.

MEMORY RESOURCES
The 78861 architecture includes a 5 GB bank of DDR4 SDRAM
memory. This resource is used by the board's built-in functions
for data storage and buffering, but can also be used for custom
applications. The Navigator FDK provides a memory controller
as well as guidance on the most efficient use of the memory
when creating IP functions.

PCI EXPRESS INTERFACEThe 78861 includes an industry standard interface fully compliant withPCI Express Gen. 1, 2, and 3 bus specifications. Supporting PCIe linksup to x8, the interface includes multiple DMA controllers for efficienttransfers to and from the module.

FRONT PANEL CONNECTIONS
The front panel includes six SSMC coaxial connectors for clock,
trigger, and analog input signals, and a 26-pin Sync Bus
input/output connector. The front panel also includes ten LEDs.
▪ Sync Bus Connector: The 26-pin µSync
front panel connector, labeled SYNC/GATE,
provides clock, sync, and gate input/output
pins for the LVPECL Sync Bus.
▪ Link LED: The green LNK LED indicates thelink speed when a valid link has been
established over the PCIe interface, as follows:
Gen 1 - LED blinks slowly (less than once persecond); Gen 2 - LED blinks about once persecond; Gen 3 - LED will be constantly on.
▪ User LED: The green USR LED is for user
applications.
▪ Master LED: The yellow MAS LED
illuminates when this 71861 is the Sync BusMaster. When only a single 71861 is used, it
must be a Master.
▪ PPS LED: The green PPS LED illuminates
when a valid PPS signal is detected. The LED
will blink at the rate of the PPS signal.
▪ Over Temperature LED: The red TMP LEDilluminates when an over-temperature orover-voltage condition is indicated by any of
the temperature/voltage sensors on the 71861 PCB.
▪ Clock LED: The green CLK LED illuminates when a valid
sample clock signal is detected. If the LED is not illuminated,no clock has been detected and no data from the input
stream can be processed.
▪ Clock Input Connector: One SSMC coaxial connector,
labeled CLK, for input of an external sample clock.
▪ Trigger Input Connector: One SSMC coaxial connector,
labeled TRIG, for input of an external trigger.
▪ Analog Input Connectors: Four SSMC coaxial connectors,labeled IN 1, IN 2, IN 3, and IN 4: one for each ADS5485
input channel.
▪ A/D Overload LEDs: There are four red OV (overload)
LEDs: one for each A/D input. Each LED indicates either ananalog input overload in the associated ADS5485, or an A/D
FIFO overrun.

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TECHNICAL DATA SHEETJade 78861

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, dataformatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IPcores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installed
FPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jade
design. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of allhardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSP
components. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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5TECHNICAL DATA SHEETJade 78861

Because all Jade boards are shipped with a full suite of built-inIP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade boardand Navigator BSP and start viewing analog signals immediately.

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A/D PERFORMANCE

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Spurious Free Dynamic Range

Spurious Pick-up

fin = 70 MHz, fs = 200 MHz, Internal Clockfs = 200 MHz, Internal Clock

Two-Tone SFDR

Two-Tone SFDR

f1 = 30 MHz, f2 = 70 MHz, fs = 200 MHz

f1 = 69 MHz, f2 = 71 MHz, fs = 200 MHz

Adjacent Channel Crosstalk

Input Frequency Response

fin Ch2 = 70 MHz, fs = 200 MHz, Ch 1 shown

fs = 200 MHz, Internal Clock

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TECHNICAL DATA SHEETJade 78861

SPECIFICATIONS
Front Panel Analog Signal Inputs
Input Type: Transformer-coupled,
front panel female SSMC connectors
Transformer Type: Coil Craft WBC46TLB
Full Scale Input: +8 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz

A/D Converters
Type: Texas Instruments ADS5485
Sampling Rate: 10 MHz to 200 MHz
Resolution: 16 bits

Digital Downconverters
Quantity: Four channels
Decimation Range: 2x to 32,768x in
three stages of 2x to 32x
LO Tuning Freq. Resolution: 32 bits, 0to ƒsExternal Clock
Type: Front panel female SSMC
connector, sine wave, 0 to +10 dBm,
AC-coupled, 50 ohms, accepts 10 to800 MHz divider input clock or PLL
system reference

Timing Bus
26-pin connector LVPECL bus includes,
clock/sync/gate/PPS inputs andoutputs; TTL signal for gate/trigger andsync/PPS inputs

External Trigger Input
Type: Front panel female SSMC
connector, LVTTL
Function: Programmable functions
include: trigger, gate, sync and PPS

Field Programmable Gate Array
Standard: Xilinx Kintex UltraScaleXCKU035-2

LO SFDR: >108 dB

Option -084: Xilinx Kintex UltraScaleXCKU060-2

Phase Offset Resolution: 32 bits, 0 to360 degrees

Option -087: Xilinx Kintex UltraScaleXCKU115-2

FIR Filter: 18-bit coefficients, 24-bit
output, user-programmablecoefficients
Default Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dB
stopband attenuation

Sample Clock Sources
On-board clock synthesizer

Clock Synthesizer
Clock Source: Selectable from onboard programmable VCXO (10 to 810MHz), front panel external clock or
LVPECL timing bus
Synchronization: VCXO can be locked
to an external 4 to 180 MHz PLL
system reference, typically 10 MHz
Clock Dividers: External clock or VCXO
can be divided by 1, 2, 3, 4, 6, 8, or 16for the A/D clock

Custom I/O
Option -104: installs 24 pairs of LVDS
connections from the FPGA to a 68pin header for custom I/O.
Option -105: provides an 8X gigabit
link between the FPGA and a serial
connector to support serial protocols.

MemoryType: DDR4 SDRAM
Size: 5 GBSpeed: 1200 MHz (2400 MHz DDR)

Option -702: L2 (air-cooled)▪ Operating Temp: -20° to 65° C▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%, noncondensing

PhysicalDimensions: PCIe card
▪ Depth: 181.10 mm (7.13 in)▪ Height: 111.25 mm (4.38 in)
Weight: Approximately 14 oz (400grams)

ORDERING INFORMATION
Model

Description

78861

4-channel 200 MHz A/D with
DDCs and Kintex UltraScale
FPGA - x8 PCIe

Options:-084

XCKU060-2 FPGA-087

XCKU115-2 FPGA-104

LVDS FPGA I/O through 68-pinribbon cable connector-105

Gigabit serial FPGA I/O throughserial connector-702

Air-cooled, Level 2

Contact Mercury for compatible option
combinations and complete specifications ofrugged and conduction-cooled versions.
Options may change, so be sure to contact
Mercury for the latest information.

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 orx8

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, noncondensing

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TECHNICAL DATA SHEETJade 78861ACCESSORY PRODUCTS

FORM FACTORSJade products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Jade Model 71861 XMC (4Channel 200 MHz A/D with Multiband DDCs, Kintex UltraScale
FPGA) has the following variants:

Model

Description

2171

Cable Kit: SSMC to SMA

7893

System Synchronizer and Distribution Board – PCIeModel

DEVELOPMENT SYSTEMS
Mercury offers development systems for Jade products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system thatensures optimum performance of Jade boards. Please contact
Mercury to configure a system that matches your requirements.

52861

3U VPX board (single XMC)

54861

3U VPX board (single XMC with optical/backplane RF)

57861

6U VPX board (single XMC)

58861

6U VPX board (dual XMC)

71861

XMC module

78861

PCIe board (single XMC)

LIFETIME SUPPORT FOR JADE PRODUCTS
Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reducedcosts, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,EW, and data acquisition MIL-Aero solutions worldwide.

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF78861

Visit: mrcy.com/go/MP78861+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Jade and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2023 Mercury Systems, Inc. 1-0-022223-DS-J78861

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