TECHNICAL DATA SHEET

Model 5560
3U VPX SOSA aligned processor boardwith Versal HBM ACAP

Co-processor
for distributed ACAP
processing tasks▪ High-Bandwidth Memory (HBM) delivers
8x more memory bandwidth than
traditional DDR5 solutions▪ High-bandwidth memory, ACAP logic,and DSP density provide robust
processing in a single slot

▪ Board interfaces: 1 GigE, 10 GigE,40 GigE, 100 GigE, and PCIe

▪ Expansion mezzanine interface for data
converter or digital I/O boards

The 5560 is a high-performance, SOSA aligned 3U OpenVPX coprocessor board based on the Xilinx Versal HBM ACAP (AdaptiveCompute Acceleration Platform). It serves as an ideal stand-alone
processor or as a co-processor for distributed ACAP processing tasks.
Ample data transfer bandwidth and flexibility are provided by a range of board interfaces
including 1 GigE, 10 GigE, 40 GigE, 100 GigE, and PCIe with installation of Mercury or usersupplied IP. The Versal HBM’s on-chip high-bandwidth memory coupled with the ACAP’s
logic and DSP density enable the 5560 to provide robust processing in a single 3U VPXslot.

FEATURES▪ Features Xilinx Versal HBM ACAP▪ 10 GigE Interface and 40 GigE Interface▪ Optional VITA 67.3C optical interface for backplane gigabit serial communication▪ Up to 4 100 GigE UDP Interfaces▪ Compatible with several VITA standards including: VITA 46.11, VITA 48, VITA 67.3C andVITA 65 (OpenVPX™ System Specification)▪ Ruggedized and conduction-cooled▪ Navigator Design Suite for software and custom IP development▪ Expansion mezzanine interface for data converter or digital I/O boards

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Model 5560

5560 BLOCK DIAGRAM

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Model 5560

BOARD ARCHITECTURE
The 5560 board design places the Versal
HBM ACAP as the cornerstone of thearchitecture. All control and data paths
are accessible by the ACAP. IP andsoftware are provided to access allboard interfaces including PCIe, 10 and
40 GigE. Optional 4-lane opticalinterfaces are also available and eachprovides a 100 GigE UDP interface withan IP core included with the Navigator
FPGA Design Kit.

EXTENDABLE IP DESIGNFor applications that require specialized
functions, users can install their own
custom IP for data processing. Mercury’sNavigator FPGA Design Kits (FDKs)
include the board’s FPGA design as ablock diagram that can be edited in
Xilinx’s Vivado IP Integrator. In addition
to the IP Integrator block diagrams, allsource code and complete IP core
documentation is included. Developers
can integrate their own IP along with theMercury factory-installed functions or
use the Navigator kit to completely
replace the Mercury IP with their own.
The Navigator Board Support Package(BSP), the companion product to theNavigator FDK, provides a complete Ccallable library for control of the 5560’s
hardware and IP. The Navigator FDK andBSP libraries mirror each other whereeach IP function is controlled by amatching software function, simplifying
the job of keeping IP and softwaredevelopment synchronized.

XILINX VERSAL HBM ACAPThe 5560 features the Versal HBM ACAP.
The ACAP provides 16 GB of on-chip HBM
SDRAM and supports memory bandwidthof up to 820 GB/s. This represents better
than an 8X throughput increase overtraditional, external DDR5 SDRAM. This
increased performance addresses theever-accelerating memory requirements

mrcy.comof high bandwidth, high computationapplications. Additional resources
include 7392 DSP slices, 3.8 million
system logic cells and 32.7 Gb/s GTYP
gigabit serial transceivers.

INTEGRATED PLATFORM
MANAGEMENT CONTROLLER
The 5560 uses an Integrated Platform
Management Controller (IPMC) to provide afully compliant and flexible management
solution for Field Replaceable Units (FRU)
that support the VITA 46.11 standard
required by HOST and SOSA architectures.
The IPMC provides a standardized
implementation of FRU management
interfaces, control signals and sensor
monitoring.
The IPMC provides the Chassis Manager
and higher-level System ManagementSoftware (SMS) access to FRU
information, FRU control signals andsensor monitoring functions so that they
can identify, activate/de-activate, resetand monitor the health of the card andtake appropriate system control actions.
The IPMC also provides a low-level pathfor configuration management and FRU
maintenance through both IPMI
messages and a Maintenance Port (MP)serial interface. The maintenance port
provides a terminal mode command-line
interface and supports monitoring, data
uploads and FRU-level troubleshooting.

EXPANSION MEZZANINEThe 5560 features an expansion
mezzanine to host analog data
converters or additional optical or digitalinterfaces. The mezzanine connectors
provide 24 gigabit serial lanes at 32
Gb/sec ideal for supporting highbandwidth A/Ds and D/As. Additionalsignals including 32 LVDS pairs and clock
and sync signals provide flexibility tosupport a range of different converters
and architectures.

SPECIFICATIONS
Adaptive Compute Acceleration
Platform (ACAP)
Type: Xilinx/AMD Versal HBM VH1542
Adaptable Engines: 3,837 k System
Logic Cells
Intelligent Engines: 7,392 DSP slices
Scalar Engines:▪ Dual-core ARM Cortex-A72▪ Dual-core ARM Cortex-R5F
HBM DRAM: 16 GBytes
Total Block RAM: 89 Mb
UltraRAM: 366 Mb

ACAP I/OInterface: GPIO
▪ Quantity: 4 pairs▪ Type: LVDS
▪ Location: VPX-P1
Interface: 1 GigE
▪ Location: VPX-P1
Interface: 10 GigE
▪ Location: VPX-P1
Interface: 40 GigE
▪ Location: VPX-P1
Interface: PCI-Express▪ Type: Gen 1, 2, 3, or 4: x4▪ Location: VPX-P1
Interface: Optical▪ Quantity: 16 full duplex lanes▪ Speed: 25 Gb/sec▪ Laser: 850 nm▪ Location: VITA 67.3C (VPX-P2)

MemoryECCM: 64 GBytes
SDRAM: DDR4, 8 GBytes
Configuration FLASH: 2x 1 Gbit QSPI3TECHNICAL DATA SHEET
Model 5560

ORDERING INFORMATION

EnvironmentalOption -763:L3a (conduction-cooled)▪ Operating Temp: 0° to 70° C▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

Model

Description

5560

SOSA aligned 3U VPX co-processor, Versal HBM ACAP

PhysicalDimensions: VPX board▪ Depth: 170.61 mm (6.717 in)▪ Height: 100 mm (3.937 in)
Weight: TBD

OpenVPX Compatibility
The 5560 is compatible with the following module profile, asdefined by the VITA 65 OpenVPX Specification:
SLT3-PAY-1F1U1S1S1U2F1H-14.6.11-12

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For technical details, contact:mrcy.com/go/CF5560

Visit: mrcy.com/go/MP5560+41 22 884 5100 tel

The Mercury Systems logo is a registered trademark of Mercury Systems, Inc. Other marks used herein may be trademarks or registered trademarksof their respective holders. Mercury products identified in this document conform with the specifications and standards described herein.
Conformance to any such standards is based solely on Mercury’s internal processes and methods. The information contained in this document issubject to change at any time without notice.
© 2023 Mercury Systems, Inc. 1-0-060623-DS-5560

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