DATASHEETFMC134 FPGA Mezzanine Card
Direct RF conversion module ﻿
The FMC134 provides customers with ahigh bandwidth and high channel countI/O solution that is ideal for multi-channel
receivers in a wide range of applications.
With four 12-bit analog-to-digital channels
up to 3.2GSPS or two analog channels up to6.4GSPS, the FMC134’s design is based on
the Texas Instruments™ ADC12DJ3200 andis mechanically and electrically compliant
with the FMC+ standard (VITA 57.4), the next
generation of small form factor expansion I/Ofor high performance FPGA-based systems.
The A/D JESD204B data interface connects
to an FPGA using 16 of the 24 high speed
serial lanes available on an FMC+ high serial
pin count (HSPC) connector. The unused
eight high speed serial lanes are passed tothe top of the board, enabling the potential for
FMC stacking.
The sample clock can be supplied externallythrough a coax connection or supplied by aninternal clock source (optionally locked to an
external reference) for multi-board and multichannel synchronization.

The board also includes an external trigger
input and two reference outputs that can beenabled for multi-board synchronization.
The front panel I/O can optionally be
populated with MMCX or SSMC coaxialconnectors. Analog I/O is AC-coupled.
When paired with the latest FPGA carriercards with FMC+ sites - such as the Abaco
VP880 or the VP868 with Xilinx® Ultrascale™
technology - customers can implement highperformance algorithms on an industry
standard platform.

FEATURES:• Two operational modes-- 4 channels, 12-bit, 3.2GSPS
data rate-- 2 channels, 12-bit, 6.4GSPS
data rate• VITA 57.4 HSPC FMC+ siterequired• 16 JESD204B lanes at
12.8GBPS• 8 JESD204B lanes passed toboard topside for FMC stacking

Applications include:• Optional FMC+e connection for
additional stacked serial lanes• Traditional radar• Conduction cooled
configuration available• Bi-static radar• Multi-channel radar• Wideband receivers• Wireless communication SDR applications• Signals intelligence receiver• AC-coupled analog input• 9 front panel SSMC or MMCXconnectors• Internal or external clock• MIL-I-46058c conformal
coating (optional)• 2Kbit EEPROM (M24C02-WDW)
accessible from the host via
I2C bus• Full-featured board support
package.
-- Open source VHDL
reference design-- Open source C/C++ reference
examples. Windows® andLinux® support.
-- JESD204B core included-- Simplified IP integration withStellarIP

DATASHEETFMC134 FPGA Mezzanine Card Direct RF conversion module ﻿Block diagram

Ref Sync

Ref Out 1

Board
Monitoring

Clock / Sync Tree
Ref Out 0

Board
Control

Ext.Clock/ Ref Input
Level

BALUN

ADC 1

BALUN

ADC 2
ADC 3

LVDS Sync [1]
LVDS Clock [4]
LVDS Trigger [1]A/D: ADC12DJ3200[DP0..7](ADC 0)BALUN

A/D: ADC12DJ3200
12 Bit Dual / Single
Channel @3.2 / 6.4 GSPSLVDS / JESD204B

ADC 0A/D: ADC12DJ3200
12 Bit Dual / Single
Channel @3.2 / 6.4 GSPS

I2C

A/D: ADC12DJ3200[DP8..15]

FMC Plus HSPC Connector

Trigger In

Status & Control

EEPROM(ADC 1)BALUN
JESD204B [8 x 12.8 Gbps][DP24..31]

LVDS Clock [2](optional)

JESD204B [8 x 12.8 Gbps][DP24..31]

HSPCe Connector
JESD204B(optional)

Firefly(optional)

FMC Plus Stacking Connector

LVDS Clock [2]Status & Control

WE INNOVATE. WE DELIVER. YOU SUCCEED.
Americas: 866-OK-ABACO or +1-866-652-2226

Asia & Oceania: +81-3-5544-3973

Europe, Africa, & Middle East: +44 (0) 1327-359444
Locate an Abaco Systems Sales Representative visit: abaco.com/products/sales

abaco.com@AbacoSys©2017 Abaco Systems. All Rights Reserved. All other brands, names or trademarks are propertyof their respective owners. Specifications are subject to change without notice.
05/17 A-DS-5183