M471V/M471K/M471C Series

NuMicro® FamilyArm® Cortex® -M4-based Microcontroller

M471V/M471K/M471C Series
Datasheet

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller andmicroprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

Dec. 22, 2022

Page 1 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETThe information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

M471V/M471K/M471C Series
TABLE OF CONTENTS
1

GENERAL DESCRIPTION ............................................................................ 9

2

FEATURES .................................................................................................. 10
2.1 NuMicro® M471V/M471K/M471C Features ............................................................. 10

3

PARTS INFORMATION ............................................................................... 16
3.1 Package Type .............................................................................................................. 16
3.2 M471V/M471K/M471C Series Naming Rule ........................................................... 17
3.3 M471V/M471K/M471C Series Selection Guide ...................................................... 18

4

PIN CONFIGURATION ................................................................................ 19
4.1 Pin Configuration ......................................................................................................... 19
4.1.1 Pin Diagram..................................................................................................................... 19
4.1.2 Multi-function Pin Diagram ............................................................................................ 22

4.2 Pin Mapping ................................................................................................................. 24
4.3 Pin Functional Description ......................................................................................... 29
4.3.1 Multi-function Summary Table ...................................................................................... 29
4.3.2 Multi-function Summary Table Sorted by GPIO ......................................................... 46

5

BLOCK DIAGRAM ...................................................................................... 67
5.1 NuMicro® M471V/M471K/M471C Block Diagram .................................................. 67

M471V/M471K/M471C SERIES DATASHEET6FUNCTIONAL DESCRIPTION..................................................................... 68
6.1 Arm® Cortex®-M4 Core ............................................................................................... 68
6.2 System Manager.......................................................................................................... 71
6.2.1 Overview .......................................................................................................................... 71
6.2.2 System Reset .................................................................................................................. 71
6.2.3 System Power Distribution ............................................................................................ 77
6.2.4 Power Modes and Wake-up Sources .......................................................................... 78
6.2.5 Power Modes and Power Level Transition ................................................................. 81
6.2.6 System Memory Map ..................................................................................................... 81
6.2.7 SRAM Memory Orginization ......................................................................................... 83
6.2.8 Bus Matrix ........................................................................................................................ 85
6.2.9 HIRC Auto Trim ............................................................................................................... 85
6.2.10 Internal VREF .................................................................................................................... 85
6.2.11 UART0_TXD Modulation with EPWM ......................................................................... 87
6.2.12 Register Lock Control .................................................................................................... 87
6.2.13 System Timer (SysTick) ................................................................................................. 91
6.2.14 Nested Vectored Interrupt Controller (NVIC) .............................................................. 92

6.3 Clock Controller ........................................................................................................... 97
6.3.1 Overview .......................................................................................................................... 97
6.3.2 Clock Generator.............................................................................................................. 98

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6.3.3 System Clock and SysTick Clock............................................................................... 100
6.3.4 Peripherals Clock ......................................................................................................... 102
6.3.5 Power-down Mode Clock ............................................................................................ 102
6.3.6 Clock Output.................................................................................................................. 102

6.4 Flash Memeory Controller (FMC) ........................................................................... 103
6.4.1 Overview ........................................................................................................................ 103
6.4.2 Features ......................................................................................................................... 103

6.5 Data Flash Memory Controller (DFMC) ................................................................. 104
6.5.1 Overview ........................................................................................................................ 104
6.5.2 Features ......................................................................................................................... 104

6.6 General Purpose I/O (GPIO) ................................................................................... 105
6.6.1 Overview ........................................................................................................................ 105
6.6.2 Features ......................................................................................................................... 105

6.7 PDMA Controller (PDMA) ......................................................................................... 106
6.7.1 Overview ........................................................................................................................ 106
6.7.2 Features ......................................................................................................................... 106

6.8 Timer Controller (TMR) ............................................................................................. 107
6.8.1 Overview ........................................................................................................................ 107
6.8.2 Features ......................................................................................................................... 107

6.9 Watchdog Timer (WDT) ............................................................................................ 109
6.9.1 Overview ........................................................................................................................ 109

6.10

Window Watchdog Timer (WWDT) ................................................................... 110

6.10.1 Overview ........................................................................................................................ 110
6.10.2 Features ......................................................................................................................... 110

6.11

Real Time Clock (RTC) ....................................................................................... 111

6.11.1 Overview ........................................................................................................................ 111
6.11.2 Features ......................................................................................................................... 111

6.12

EPWM Generator and Capture Timer (EPWM) .............................................. 112

6.12.1 Overview ........................................................................................................................ 112
6.12.2 Features ......................................................................................................................... 112

6.13

Basic PWM Generator and Capture Timer (BPWM) ...................................... 114

6.13.1 Overview ........................................................................................................................ 114
6.13.2 Features ......................................................................................................................... 114

6.14

UART Interface Controller (UART).................................................................... 115

6.14.1 Overview ........................................................................................................................ 115
6.14.2 Features ......................................................................................................................... 115

6.15

Serial Peripheral Interface (SPI)........................................................................ 117

6.15.1 Overview ........................................................................................................................ 117

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6.9.2 Features ......................................................................................................................... 109

M471V/M471K/M471C Series
6.15.2 Features ......................................................................................................................... 117

6.16

I2C Serial Interface Controller (I2C) ................................................................... 118

6.16.1 Overview ........................................................................................................................ 118
6.16.2 Features ......................................................................................................................... 118

6.17

Customize IR Receiver (CIR) ............................................................................ 119

6.17.1 Overview ........................................................................................................................ 119
6.17.2 Features ......................................................................................................................... 119

6.18

CRC Controller (CRC) ........................................................................................ 120

6.18.1 Overview ........................................................................................................................ 120
6.18.2 Features ......................................................................................................................... 120

6.19

Pseudo Random Number Generator (PRNG) ................................................ 121

6.19.1 Overview ........................................................................................................................ 121
6.19.2 Features ......................................................................................................................... 121

6.20

Enhanced 12-bit Analog-to-Digital Converter (EADC) ................................... 122

6.20.1 Overview ........................................................................................................................ 122
6.20.2 Features ......................................................................................................................... 122

6.21

Digital to Analog Converter (DAC) .................................................................... 123

6.21.1 Overview ........................................................................................................................ 123
6.21.2 Features ......................................................................................................................... 123

6.22

Analog Comparator Controller (ACMP)............................................................ 124

M471V/M471K/M471C SERIES DATASHEET

6.22.1 Overview ........................................................................................................................ 124
6.22.2 Features ......................................................................................................................... 124

7

APPLICATION CIRCUIT............................................................................ 125
7.1 Power Supply Scheme ............................................................................................. 125
7.2 Peripheral Application Scheme ............................................................................... 126

8

ELECTRICAL CHARACTERISTICS ......................................................... 127
8.1 Absolute Maximum Ratings ..................................................................................... 127
8.1.1 Voltage Characteristics ................................................................................................ 127
8.1.2 Current Characteristics ................................................................................................ 128
8.1.3 Thermal Characteristics............................................................................................... 129
8.1.4 EMC Characteristics .................................................................................................... 130
8.1.5 Package Moisture Sensitivity (MSL) .......................................................................... 131
8.1.6 Soldering Profile ........................................................................................................... 132

8.2 General Operating Conditions ................................................................................. 133
8.3 DC Electrical Characteristics ................................................................................... 134
8.3.1 Supply Current Characteristics................................................................................... 134
8.3.2 On-Chip Peripheral Current Consumption ................................................................ 138
8.3.3 Wakeup Time from Low-Power Modes ..................................................................... 139
8.3.4 I/O Current Injection Characteristics.......................................................................... 140

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8.3.5 I/O DC Characteristics ................................................................................................. 140

8.4 AC Electrical Characteristics ................................................................................... 143
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC) ................................................. 143
8.4.1 38.4 kHz Internal Low Speed RC Oscillator (LIRC) ................................................ 144
8.4.2 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT)
Characteristics ......................................................................................................................... 145
8.4.3 External 4~24 MHz High Speed Clock Input Signal Characteristics .................... 149
8.4.4 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT)
Characteristics ......................................................................................................................... 150
8.4.5 External 32.768 kHz Low Speed Clock Input Signal Characteristics ................... 152
8.4.6 PLL Characteristics ...................................................................................................... 153
8.4.7 I/O AC Characteristics ................................................................................................. 154

8.5 Analog Characteristics .............................................................................................. 156
8.5.1 LDO ................................................................................................................................ 156
8.5.2 Reset and Power Control Block Characteristics ...................................................... 156
8.5.3 12-bit SAR Analog To Digital Converter (ADC) ........................................................ 157
8.5.4 Digital to Analog Converter (DAC) ............................................................................. 159
8.5.5 Analog Comparator Controller (ACMP)..................................................................... 161
8.5.6 Internal Voltage Reference ......................................................................................... 162
8.5.7 Temperature Sensor .................................................................................................... 163

8.6 Communications Characteristics............................................................................. 164
8.6.1 SPI Dynamic Characteristics ...................................................................................... 164
8.6.3 I2C Dynamic Characteristics ....................................................................................... 169

8.7 Flash DC Electrical Characteristics ........................................................................ 170
8.8 Data Flash DC Electrical Characteristics ............................................................... 171

9

PACKAGE DIMENSIONS .......................................................................... 172
9.1 LQFP 100L (14x14x1.4 mm3 footprint 2.0 mm) .................................................... 172
9.2 LQFP 128L (14x14x1.4 mm3 footprint 2.0 mm) .................................................... 173
9.3 WLCSP100 (4.4648x 4.4480x 0.58 mm3 , ball pitch 0.4 mm) ............................ 174

10 ABBREVIATIONS ...................................................................................... 175
10.1

Abbreviations ........................................................................................................ 175

11 REVISION HISTORY ................................................................................. 177

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8.6.2 SPI - I2S Dynamic Characteristics ............................................................................. 167

M471V/M471K/M471C Series
LIST OF FIGURES
Figure 4.1-1 LQFP 100-pin Diagram .............................................................................................. 19
Figure 4.1-2 LQFP 128-pin Diagram .............................................................................................. 20
Figure 4.1-3 WLCSP 100-pin Diagram .......................................................................................... 21
Figure 4.1-4 LQFP 100-pin Multi-function Pin Diagram ................................................................. 22
Figure 4.1-5 LQFP 128-pin Multi-function Pin Diagram ................................................................. 23
Figure 5.1-1 NuMicro® M471V/M471K/M471C Block Diagram...................................................... 67
Figure 6.1-1 Cortex® -M4 Block Diagram ........................................................................................ 68
Figure 6.2-1 System Reset Sources .............................................................................................. 72
Figure 6.2-2 nRESET Reset Waveform ......................................................................................... 74
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 74
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 75
Figure 6.2-5 Brown-out Detector (BOD) Waveform ....................................................................... 76
Figure 6.2-6 NuMicro® M471V/M471K/M471C Power Distribution Diagram ................................. 77
Figure 6.2-7 Power Mode State Machine ...................................................................................... 79
Figure 6.2-8 NuMicro® M471V/M471K/M471C Power Distribution Diagram ................................. 81
Figure 6.2-9 SRAM Block Diagram ................................................................................................ 83
Figure 6.2-10 SRAM Memory Organization ................................................................................... 84
Figure 6.2-11 NuMicro® M471V/M471K/M471C Bus Matrix Diagram ........................................... 85

M471V/M471K/M471C SERIES DATASHEET

Figure 6.2-12 NuMicro® M471V/M471K/M471C VREF Diagram ..................................................... 86
Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 98
Figure 6.3-2 Clock Generator Block Diagram ................................................................................ 99
Figure 6.3-3 System Clock Block Diagrams ................................................................................ 100
Figure 6.3-4 HXT Stop Protect Procedure ................................................................................... 101
Figure 6.3-5 SysTick Clock Control Block Diagram ..................................................................... 101
Figure 6.3-6 Clock Output Block Diagram ................................................................................... 102
Figure 8.1-1 Soldering profile from J-STD-020C ......................................................................... 132
Figure 8.4-1 Typical Crystal Application Circuit ........................................................................... 148
Figure 8.4-2 Typical 32.768 kHz Crystal Application Circuit ........................................................ 151
Figure 8.5-1 Power Ramp Up/Down Condition ............................................................................ 157
Figure 8.5-2 Typical connection with internal voltage reference.................................................. 162
Figure 8.6-1 SPI Master Mode Timing Diagram .......................................................................... 164
Figure 8.6-2 SPI Slave Mode Timing Diagram ............................................................................ 166
Figure 8.6-3 I2S Master Mode Timing Diagram............................................................................ 167
Figure 8.6-4 I2S Slave Mode Timing Diagram.............................................................................. 168
Figure 8.6-5 I2C Timing Diagram ................................................................................................. 169

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M471V/M471K/M471C Series
List of Tables
Table 1-1 NuMicro® M471V/M471K/M471C Series Key Features Support Table ........................... 9
Table 4.3-1 GPIO Multi-function Table........................................................................................... 66
Table 6.2-1 Reset Value of Registers ............................................................................................ 73
Table 6.2-2 Power Mode Table ...................................................................................................... 78
Table 6.2-3 Power Mode Difference Table .................................................................................... 78
Table 6.2-4 Power Mode Definition Table ...................................................................................... 78
Table 6.2-5 Clocks in Power Modes .............................................................................................. 79
Table 6.2-6 Re-Entering Power-down Mode Condition ................................................................. 80
Table 6.2-7 Address Space Assignments for On-Chip Controllers................................................ 83
Table 6.2-8 Exception Model ......................................................................................................... 93
Table 6.2-9 Interrupt Number Table ............................................................................................... 96
Table 6.5-1 FMC Features Comparison Table at Different Chip ................................................. 104
Table 6.13-1 BPWM Features Comparison Table ....................................................................... 114
Table 6.14-1 M471V/M471K/M471C series UART Features ....................................................... 116
Table 8.1-1 Voltage Characteristics ............................................................................................. 127
Table 8.1-2 Current Characteristics ............................................................................................. 128
Table 8.1-3 Thermal Characteristics ............................................................................................ 129
Table 8.1-4 EMC Characteristics ................................................................................................. 130
Table 8.1-5 Package Moisture Sensitivity (MSL) ......................................................................... 131

Table 8.2-1 General operating conditions .................................................................................... 133
Table 8.3-1 Current consumption in Normal Run mode .............................................................. 135
Table 8.3-2 Current consumption in Idle mode ............................................................................ 136
Table 8.3-3 Chip Current Consumption in Power-down mode .................................................... 137
Table 8.3-4 Peripheral Current Consumption .............................................................................. 139
Table 8.3-5 Low-power mode wakeup timings ............................................................................ 139
Table 8.3-6 I/O current injection characteristics........................................................................... 140
Table 8.3-7 I/O input Characteristics............................................................................................ 140
Table 8.3-8 I/O output Characteristics ......................................................................................... 141
Table 8.3-9 nRESET Input Characteristics .................................................................................. 142
Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics .......................... 143
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics .......................... 144
Table 8.4-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator ........................................ 146
Table 8.4-4 External 4~24 MHz High Speed Crystal Characteristics .......................................... 147
Table 8.4-5 External 4~24 MHz High Speed Clock Input Signal ................................................. 149
Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator ........................................ 150

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Table 8.1-6 Soldering Profile........................................................................................................ 132

M471V/M471K/M471C Series
Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics ......................................... 150
Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal ................................................ 152
Table 8.4-9 PLL Characteristics ................................................................................................... 153
Table 8.4-10 I/O AC Characteristics ............................................................................................ 155
Table 8.5-1 Reset and Power Control Unit .................................................................................. 157
Table 8.5-2 ACMP Characteristics ............................................................................................... 161
Table 8.6-1 SPI Master Mode Characteristics ............................................................................. 164
Table 8.6-2 SPI Slave Mode Characteristics ............................................................................... 165
Table 8.6-3 I2S Characteristics .................................................................................................... 167
Table 8.6-4 I2C Characteristics .................................................................................................... 169
Table 10.1-1 List of Abbreviations................................................................................................ 176

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
1

GENERAL DESCRIPTIONThe NuMicro® M471V/M471K/M471C series is a 32-bit microcontroller based on Arm® Cortex® -M4F
core, with DSP instruction set and single-precision floating-point unit (FPU), targeted for smart home
appliance applications. For the growing requirement of the safety functions on the home appliance, theM471V/M471K/M471C series provides certified Software Test Library (STL) and an application notefor IEC60730-1 Class B Annex H. This certified STL can significantly reduce the development timeand efforts to pass IEC60730-1 Class B certification for home appliances. The M471V/M471K/M471C
series runs up to 120 MHz, and features 2.5V to 5.5V wide operating voltage, -40°C to 105°C wide
operating temperature, a variety of packages with wide pin pitch, and excellent high immunity
characteristics by ESD HBM 8 KV and EFT 4.4 KV, which greatly meet the rigid requirements forstability, reliability and safety of home appliance systems.
As the new smart function added on home appliances, the M471V/M471K/M471C series provides up
to 512 KB dual-bank of Flash memory for code storage, 64 KB SRAM for run time operation and 32
KB independent Data Flash for parameters. The dual bank design of 512 KB Flash memory supports
the Firmware update through the Over-The-Air (FOTA) process. Additionally, in response to the code
security requirements, the M471V/M471K/M471C series supports Execute-Only Memory (XOM)
function to protect confidential program code information from stealing in the run-time. Finally, the 32
KB independent data Flash provides a 256 Bytes page erasing unit to make the parameter data
update and access more efficiently. In order to reduce the data access overhead of CPU core to
peripherals, a peripheral direct memory access (PDMA) is provided.
The M471V/M471K/M471C series supports plenty of peripherals, including a Customize IR receiver(CIR) for remote controller, up to 24 channels of 16-bit PWM, 6 sets of UART, 2 sets of SPI/I2S, 2 setsof I²C, and a real-time clock (RTC).
The M471V/M471K/M471C series also provides rich analog peripherals including 2 sets of analog
comparators, up to 24 channels of 12-bit SAR ADC, and 1 channel of 8-bit DAC. The
M471V/M471K/M471C series also integrates a pseudo random number generator (PRNG) to support
the requirement for encryption and decryption of smart home appliances.

Core
Product Line

Timer
PDMA

CRC

(MHz)
M471V/M471K/M471C
Series

120

PWM

UART

I2C

(32-bit)
√

√

4

QSPI/
ADC

ACMP

DAC

CIR

PRNG

24

2

1

√

√

SPI
24

6

2

SPI x2

Table 1-1 NuMicro® M471V/M471K/M471C Series Key Features Support Table
This series supports three package choices which are designed for home appliance PCB demands.


LQFP100: 14 mm x 14 mm, pin pitch 0.5 mm



LQFP128: 14 mm x 14 mm, pin pitch 0.4 mm



WLCSP100: 4.4648x 4.4480x 0.58 mm, ball pitch 0.4 mm

The NuMicro® M471V/M471K/M471C series is suitable for a wide range of applications such as:Washing MachineRefrigerator

Air conditioner



Air Purifier

Other home appliances

Dec. 22, 2022

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M471V/M471K/M471C SERIES DATASHEETFor the development, Nuvoton provides the NuMaker-M471KI evaluation board, and Nuvoton Nu-Link
debugger. The 3rd Party IDE such as Keil MDK, IAR EWARM, Eclippse IDE with GNU GCC compilers
are also supported.

M471V/M471K/M471C Series

2
2.1

FEATURES
NuMicro® M471V/M471K/M471C Features

Core and System
 Arm® Cortex® -M4 processor, running up to 120 MHz Built-in Memory Protection Unit (MPU) Built-in Nested Vectored Interrupt Controller (NVIC)
 Hardware IEEE 754 compliant Floating-point Unit (FPU)
Arm® Cortex® -M4

 DSP extension with hardware divider and single-cycle 32-bit
hardware multiplier 24-bit system tick timer
 Programmble and maskable interrupt
 Low Power Sleep mode by WFI and WFE instructions

Brown-out Detector (BOD) Four-level BOD with brown-out interrupt and reset option(4.4V/3.7V/2.7V/2.4V)

Low Voltage Reset (LVR)

 LVR with 2.35V threshold voltage level

Security

 96-bit Unique ID (UID).
 128-bit Unique Customer ID (UCID).

M471V/M471K/M471C SERIES DATASHEETMemories Two bank 512 KB on-chip Application ROM (APROM)
 Supports FOTA function
 4 KB on-chip Flash for user-defined loader (LDROM) 32 Kbytes data Flash which is rewritable in parallel with instruction
execution
 All on-chip Flash expect data Flash supporting 2048-byte page
erase
Flash

 Data Flash supporting 256-byte page erase
 Fast Flash programming verification with CRC
 On-chip Flash programming with In-Chip Programming (ICP), InSystem Programming (ISP) and In-Application Programming (IAP)
capabilities Configurable boot up sources user-defined loader (LDROM) or
Application ROM (APROM)
 2-wired ICP Flash updating through SWD interface
 32-bit/64-bit and multi-word Flash programming function

SRAM

Dec. 22, 2022

 Up to 64 KB on-chip SRAM includes:

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M471V/M471K/M471C Series
 Byte-, half-word- and word-access 32 KB with hardware parity check Supports PDMA operation
 Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials
 Programmable initial value and seed value Programmable order reverse setting and one’s complement setting
for input data and CRC checksum
Cyclic Redundancy
Calculation (CRC) 8-bit, 16-bit, and 32-bit data width
 8-bit write mode with 1-AHB clock cycle operation
 16-bit write mode with 2-AHB clock cycle operation
 32-bit write mode with 4-AHB clock cycle operation
 Uses PDMA to write data with performing CRC operation
 Six independent and configurable channels for automatic datatransfer between memories and peripherals Basic and Scatter-Gather transfer modes

Peripheral DMA (PDMA) Each channel supports circular buffer management using ScatterGather Transfer mode
 Fixed-priority and Round-robin priorities modes Single and burst transfer types
 Byte-, half-word- and word tranfer unit with count up to 65536
 Incremental or fixed source and destination address Supports 64 bits, 128 bits, 192 bits, and 256 bits random number
generation.

Clocks 4~24 MHz High-speed eXternal crystal oscillator (HXT) for precise
timing operation
External Clock Source 32.768 kHz Low-speed eXternal crystal oscillator (LXT) for RTC
function and low-power system operation
 Supports clock failure detection for external crystal oscillators andexception generatation (NMI) 38 kHz Low-speed Internal RC oscillator (LIRC) for watchdog timer
and wakeup operation

Internal Clock Source 48 MHz High-speed Internal RC oscillator (HIRC) trimmed to 1%
accuracy at -20 to 85°C
 Up to 120 MHz on-chip PLL, sourced from HIRC or HXT, allowing
CPU operation up to the maximum CPU frequency without the needfor a high-frequency crystal

Real-Time Clock (RTC)

Dec. 22, 2022

 The RTC clock source is from Low-speed external crystal
 Able to wake up CPU from any reduced power mode

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Pseudo Random Number
Generator (PRNG)

M471V/M471K/M471C Series
 Supports ±5 ppm within 5 seconds software clock accuracy
compensation
 Supports Alarm registers (second, minute, hour, day, month, year) Supports RTC Time Tick and Alarm Match interrupt
 Automatic leap year recognition
 Supports 1 Hz clock output for calibration

Timers
TIMER
 4 sets of 32-bit timers with 24-bit up counters and 8-bit prescalecounters
 Independent clock source for each timer
 One-shot, Periodic, Toggle and Continuous Counting operationmodes
 Event counting function to count the event from external pin
 Input capture function to capture or reset counter value External capture pin event for interval measurement
 External capture pin event to reset 24-bit up counter
32-bit Timer Chip wake-up from Idle/Power-down mode if a timer interrupt signal
is generated
 Timer interrupt flag or external capture interrupt flag to trigger
BPWM, EPWM, EADC, DAC and PDMA

M471V/M471K/M471C SERIES DATASHEET Internal capture triggered source from ACMP output
 Inter-Timer trigger capture mode
PWM
 16-bit compare register and period register Double buffer for period register and compare register Supports inverse in PWM output
 PWM interrupt wake-up from system Power-down mode 16-bit counters with 12-bit clock presacle supporting 12 PWM
output channels
 Up to 12 independent input capture channels with 16-bit resolution
counter Supports dead time with maximum divided 12-bit prescale Up, down or up-down PWM counter type
Enhanced PWM (EPWM)

 Supports complementary mode for 3 complementary paired PWM
output channels
 Synchronous function for phase control
 Counter synchronous start function
 Brake function with auto recovery mechanism
 Mask function and tri-state output for each PWM channel
 Trigger EADC or DAC to start conversion immediately

Dec. 22, 2022

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M471V/M471K/M471C Series Trigger EADC to start conversion after a short delay Hardware short-circuit output check 16-bit counters with 12-bit clock presacle supporting 12 PWM
output channels
 Up to 12 independent input capture channels with 16-bit resolution
counter Up, down or up-down PWM counter type
Basic PWM (BPWM)

 Counter synchronous start function
 Complementary mode for 6 complementary paired PWM output
channels
 Mask function and tri-state output for each PWM channel
 Able to trigger EADC to start conversion
 18-bit free running up counter for WDT time-out interval Supports multiple clock sources from LIRC (default selection),
HCLK/2048 and LXT with 8 selectable time-out period

Watchdog Able to wake up system from Power-down or Idle mode Time-out event to trigger interrupt or reset system
 Supports four WDT reset delay periods, including 1026, 130, 18 or
3 WDT_CLK reset delay period
 Configured to force WDT enabled on chip power-on or reset Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit
counter with 11-bit prescale Suspended in Idle/Power-down mode

Analog Interfaces One 12-bit, 24-ch 1.895 MSPS SAR EADC with up to 24 singleended input channels or 1 differential input pair
 Three internal channels for band-gap VBG input, Temperature
sensor input and DAC input
Enhanced Analog-toDigital Converter (EADC)

 Supports external VREF pin or internal reference voltage
 Analog-to-Digital conversion can be triggered by software enable,
external pin, Timer 0~3 overflow pulse trigger or PWM trigger
 Configurable EADC sampling time Double data buffers for sample module 0~3
 Supports PDMA operation
 One 8-bit, 200 KSPS voltage type DAC without buffer

Digital-to-Analog
Converter (DAC) Reference voltage can be switched from AVDD, VREF pin and Internalreference voltage
 The trigger of the DAC conversion can be done by the software,
external triggers or timer0 to timer3, EPWM0 Available for monitoring by the ACMP

Dec. 22, 2022

Page 13 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETWindow Watchdog

M471V/M471K/M471C Series PDMA operation
 Two Analog Comparators
 Supports four multiplexed I/O pins at positive input

Analog Comparator(ACMP)

 Supports one I/O pin, band-gap voltage, DAC voltage output,
internal voltage reference, and 16-level voltage divider from AVDD or
VREF at negative input
 Supports wake up from Power-down by interrput
 Supports triggers for brake events and cycle-by-cycle control for
PWM
 Supports window compare mode and window latch mode Supports programmable hysteresis window: 20 mV and 40 mV
 One Internal reference voltage with 2.048V, 2.560V, 3.072V,
4.096V Can be configured to supply a reference voltage to the following:

Internal reference voltage

 ADC reference Voltage
 DAC reference Voltage
 Comparator negative input

Temperature sensor

 One built-in temperature sensor with 1°C resolution

Communication Interfaces
M471V/M471K/M471C SERIES DATASHEET Six Low-power UARTs with up to 2 MHz baud rate
 Auto-Baud Rate measurement and baud rate compensation
function Supports low power UART (LPUART): baud rate clock from
LXT(32.768 kHz) with 9600bps in Power-down mode even system
clock is stopped
 UART0/UART1 supporting 16-byte FIFOs with programmable level
trigger UART2/UART3/UART4/UART5 supporting 1-byte FIFOs with
programmable level trigger
 Auto flow control ( nCTS and nRTS)
Low-power UART Supports IrDA (SIR) function on UART0/UART1
 Supports LIN function on UART0/UART1
 Supports RS-485 9-bit mode and direction control
 Supports nCTS, incoming data, Received Data FIFO reachedthreshold and RS-485 Address Match (AAD mode) wake-up
function in idle mode Supports hardware or software enabled to program nRTS pin tocontrol RS-485 transmission direction
 Supports wake-up function
 8-bit receiver FIFO time-out detection function
 Supports break error, frame error, parity error and receive/transmit

Dec. 22, 2022

Page 14 of 178

Rev 1.40

M471V/M471K/M471C Series
FIFO overflow detection function
 PDMA operation
 Two sets of I2C devices with Master/Slave mode Supports Standard mode (100 kbps), Fast mode (400 kbps), Fastmode plus (1 Mbps)
 Programmable clocks allowing for versatile rate control
I2C

 Supports multiple address recognition (four slave address withmask option)
 Supports SMBus and PMBus
 Supports multi-address power-down wake-up function
 PDMA operation
 Two SPI/I2S controllers with Master/Slave mode
 SPI/I2S provides separate 4-level of 32-bit (or 8-level of 16-bit)transmit and receive FIFO buffers
SPI
 Up to 24 MHz in Master mode Configurable bit length of a transfer word from 8 to 32-bit
 MSB first or LSB first transfer sequence Byte reorder function

SPI/I2S

 Supports Byte or Word Suspend mode Supports one data channel half-duplex transfer
I2S
 Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit
audio data sizes
 Supports PCM mode A, PCM mode B, I2S and MSB justified data
format PDMA operation
 1 channel

Customize IR Receiver(CIR) Four pattern matching (header, data 0, data 1, and special datadetection)
 8-byte receive buffer per unit Supports four I/O modes: Quasi bi-direction, Push-Pull output,
Open-Drain output and Input only with high impendence mode
 Selectable TTL/Schmitt trigger input

GPIO Configured as interrupt source with edge/level trigger setting
 Supports independent pull-up control
 Supports high driver and high sink current I/O Supports software selectable slew rate control

Dec. 22, 2022

Page 15 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET Supports receive-only modeM471V/M471K/M471C Series
3

PARTS INFORMATION

Package is Halogen-free, RoHS-compliant and TSCA-compliant.

3.1

Package TypeWLCSP100

LQFP100

LQFP128

M471CI8AE

M471VI8AE

M471KI8AE

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 16 of 178

Rev 1.40

M471V/M471K/M471C Series

3.2

M471V/M471K/M471C Series Naming Rule

M4

71

K

I

8

A

E

Core

SeriesPackage

Flash Size

SRAM Size

Revision

Temperature

Cortex® M4F

71: Base

V: LQFP100(14x14 mm)
K: LQFP128(14x14 mm)
C: WLCSP100(4.4648x4.448mm)

G: 256 KB
I: 512 KB

7: 48 KB
8: 64 KB

E:-40°C ~ 105°C

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 17 of 178

Rev 1.40

M471V/M471K/M471C Series

3.3

M471V/M471K/M471C Series Selection Guide
M471
PART NUMBER

Flash (KB)
SRAM (KB)

KI8AE

CI8AE

512
(dual bank)64(32 KB hardware parity
check)

512(dual bank)64(32 KB hardware parity
check)

512(dual bank)64(32 KB hardware parity
check)

Data Flash (KB)

32

LDROM (KB)

4XOM (regions)

4

System Frequency (MHz)

120

I/O

91

119

Connectivity

M471V/M471K/M471C SERIES DATASHEET

32-bit Timer

4

Customize IR Receiver

√

UART

6

SPI/I2S

2

I2C

2

16-bit EPWM

1216-bit BPWM

12

PMDA

6-ch

RTC

√

12-bit ADC

23

24

8-bit DAC

1

Analog Comparator

2

PRNG

√

PackageDec. 22, 2022

VI8AE

83

24

LQFP 100

LQFP 128

C: WLCSP100(14x14mm)(14x14mm)(4.4648x4.448mm)

Page 18 of 178

Rev 1.40

M471V/M471K/M471C Series
4

PIN CONFIGURATION

Users can find pin configuaration information in the Multi-function Pin Diagram section or by using
NuTool - PinConfig. The NuTool - PinConfig contains all Nuvoton NuMicro® Family chip series with allpart number, and helps users configure GPIO multi-function correctly and handily.

4.1

Pin Configuration

4.1.1

Pin Diagram
LQFP100 Pin Diagram

PD.9

PF.1

PF.0

53

52

51

PC.5

PD.8

55

54

PC.3

PC.4

57

56

PC.1

PC.2

59

58

PI.2

PC.0

61

60

PD.7

PI.3

63

62

PD.5

PD.6

65

64

PD.3

PD.4

67

66

PD.1

PD.2

69

68

PD.13

PD.0

71

70

PA.13

PA.12

73

72

PA.15

PA.14

75

74

Corresponding Part Number: M471VI8AE

7650

nRESET

PE.6

77

49

PE.15

PE.5

78

48

PE.14

PE.4

79

47

PF.15

PE.3

80

46

PA.0

PE.2

81

45

PA.1

PE.1

82

44

PA.2

PE.0

83

43

PA.3

VSS

84

42

PA.4

LDO_CAP

85

41

PA.5

VDD

86

40

PD.15

PC.14

87

39

PF.13

PB.15

88

38

PF.12

PB.14

89

37

PA.6

PB.13

90

36

PA.7

PB.12

91

35

PC.6

AVDD

92

34

PC.7

VREF

93

33

PC.8

AVSS

94

32

PE.13

PB.11

95

31

PE.12

PB.10

96

30

PE.9

PB.9

97

29

PE.8

PB.8

98

28

VDD

PB.7

99

27

VSS

PB.6

100

26

PF.2

23

24

25

PF.5

PF.14

PF.14

21

22

PF.6

PF.14

19

20

PF.8

PF.7

17

18

PD.11

PD.10

15

16

PA.8

PA.9

PD.12

13

14

PA.10

11

12

PI.1

PA.11

9

10

PB.1

PI.0

7

8

PC.10

PB.0

5

6

PC.12

PC.11

3

4

PB.3

PB.2

1

2

PB.5

PB.4

LQFP100

M471V/M471K/M471C SERIES DATASHEET

PE.7

Figure 4.1-1 LQFP 100-pin Diagram

Dec. 22, 2022

Page 19 of 178

Rev 1.40

M471V/M471K/M471C Series
LQFP128 Pin Diagram

PD.8

PD.9

PF.1

PF.0

68

67

66

65

PC.4

PC.5

70

69

PC.2

PC.3

72

71

PC.0

PC.1

74

73

PI.3

PI.2

76

75

PG.10

PG.9

78

77

PG.12

PG.11

80

79

PG.14

PG.13

82

81

PD.7

PG.15

84

83

PD.5

PD.6

86

85

PD.3

PD.4

88

87

PD.1

PD.2

90

89

PD.13

PD.0

92

91

PA.13

PA.12

94

93

PA.15

PA.14

96

95

Corresponding Part Number: M471KI8AE

97

64

nRESET

PE.6

98

63

PE.15

PE.5

99

62

PE.14

PE.4

100

61

PF.15

PE.3

101

60

PA.0

PE.2

102

59

PA.1

PI.4

103

58

PA.2

PI.5

104

57

PA.3

PE.1

105

56

PA.4

PE.0

106

55

PA.5

PH.8

107

54

PD.15

PH.9

108

53

PF.13

PH.10

109

52

PF.12

PH.11

110

51

PA.6

PD.14

111

50

PA.7

VSS

112

49

PC.6

LDO_CAP

113

48

PC.7

VDD

114

47

PC.8

PC.14

115

46

PE.13

PB.15

116

45

PE.12

PB.14

117

44

PE.11

PB.13

118

43

PE.10

PB.12

119

42

PE.9

AVDD

120

41

PE.8

VREF

121

40

VDD

AVSS

122

39

VSS

PB.11

123

38

PF.2

PB.10

124

37

PF.3

PB.9

125

36

PH.7

PB.8

126

35

PH.6

PB.7

127

34

PH.5

PB.6

128

33

PH.4

29

30

31

32

PF.5

PF.4

PF.8

PF.7

PF.6

27

28

PF.9

PF.14

25

26

PF.10

23

24

PG.4

21

22

PG.2

PG.3

PF.11

19

20

PD.11

PD.10

17

18

PC.13

PD.12

15

16

PA.9

PA.8

13

14

PA.11

PA.10

11

12

PI.0

PI.1

9

10

PB.1

PC.9

PB.0

7

8

PC.10

5

6

PC.12

PC.11

3

4

PB.3

PB.2

1

2

PB.5

LQFP128

PB.4

M471V/M471K/M471C SERIES DATASHEET

PE.7

Figure 4.1-2 LQFP 128-pin Diagram

Dec. 22, 2022

Page 20 of 178

Rev 1.40

M471V/M471K/M471C Series
WLCSP100 Pin Diagram

Corresponding Part Number: M471CI8AE
Top transparent view
B

C

D

E

F

G

H

J

K

10

PF.4

PF.2

PE.8

PC.8

PA.7

VSS

VDD

PA.3

PF.15

PF.0

9

PF.5

PF.3

PE.9

PE.13

PA.6

PD.15

PA.2

PE.14

nRES
ET

PC.5

8

PF.6

PF.14

PE.12

PC.7

PC.6

PA.5

PE.15

PD.8

PC.4

PC.1

7

PF.8

PF.7

VSS

VDD

PA.4

PA.0

PD.9

PC.2

PC.0

VSS

6

PD.11

PD.12

PC.13

PD.10

PA.1

PF.1

PC.3

PD.5

PD.6

PD.7

5

PA.8

PA.9

PA.10

AVSS

PB.12

VSS

VDD

PD.2

PD.3

PD.4

4

PA.11

VDD

PB.1

PB.2

PB.4

PB.14

PA.15

PD.13

PD.1

PD.0

3

VSS

PB.0

PC.11

PB.7

PB.9

PB.15

PE.2

PA.14

PA.13

PA.12

2

PC.12

PB.3

PB.6

PB.10

VREF

VDD

VDD

PE.3

PE.5

PE.7

1

PB.5

PB.8

PB.11

AVDD

PB.13

PC.14

LDO_
CAP

VSS

PE.4

PE.6

M471V/M471K/M471C SERIES DATASHEETAWLCSP100

Figure 4.1-3 WLCSP 100-pin Diagram

Dec. 22, 2022

Page 21 of 178

Rev 1.40

M471V/M471K/M471C Series
4.1.2

Multi-function Pin Diagram
LQFP-100 Pin Multi-function Pin Diagram

PC.5 / UART2_TXD / I2C1_SCL / UART4_TXD / EPWM1_CH0

PD.8 / UART2_nRTS

PD.9 / UART2_nCTS

PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK

PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT

55

54

53

52

51

PC.1 / SPI1_CLK / UART2_TXD / I2C0_SCL / EPWM1_CH4 / ACMP0_O / EADC0_ST

PC.2 / SPI1_MOSI / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / EPWM1_CH3

PC.3 / SPI1_MISO / UART2_nRTS / I2C0_SMBAL / UART3_TXD / EPWM1_CH2

PC.4 / SPI1_I2SMCLK / UART2_RXD / I2C1_SDA / UART4_RXD / EPWM1_CH1

59

58

57

60

56

PD.7 / UART1_TXD / I2C0_SCL / SPI1_MISO

PI.3 / UART1_RXD / I2C0_SDA / UART5_RXD / I2C1_SDA / UART4_RXD / BPWM0_CH4

PI.2 / UART1_TXD / I2C0_SCL / UART5_TXD / I2C1_SCL / UART4_TXD / BPWM0_CH5 / EADC0_ST

PC.0 / SPI1_SS / UART2_RXD / I2C0_SDA / EPWM1_CH5 / ACMP1_O

63

62

61

PD.3 / SPI0_SS / UART3_nRTS / UART0_TXD

PD.4 / I2C1_SDA / SPI1_SS

PD.5 / I2C1_SCL / SPI1_CLK

PD.6 / UART1_RXD / I2C0_SDA / SPI1_MOSI

67

66

65

64

PD.13 / SPI0_I2SMCLK / SPI1_I2SMCLK

PD.0 / SPI0_MOSI / UART3_RXD / TM2

PD.1 / SPI0_MISO / UART3_TXD

PD.2 / SPI0_CLK / UART3_nCTS / UART0_RXD

71

70

69

68

PA.15 / UART0_RXD / BPWM1_CH5 / EPWM0_SYNC_IN

PA.14 / UART0_TXD / BPWM1_CH4

PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3

PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2

75

74

73

72

Corresponding Part Number: M471VI8AE

PE.7 / UART5_TXD / EPWM0_CH0 / BPWM0_CH576

50

nRESET

PE.6 / UART5_RXD / EPWM0_CH1 / BPWM0_CH4

77

49

PE.15 / UART2_RXD

PE.5 / EPWM0_CH2 / BPWM0_CH3

78

48

PE.14 / UART2_TXD

PE.4 / EPWM0_CH3 / BPWM0_CH2

79

47

PF.15 / EPWM0_BRAKE0 / EPWM0_CH1 / TM2 / CLKO / INT4

PE.3 / EPWM0_CH4 / BPWM0_CH1

80

46

PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / EPWM0_CH5 / DAC0_ST

PE.2 / EPWM0_CH5 / BPWM0_CH081

45PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / EPWM0_CH4

PE.1 / SPI1_MISO / UART3_TXD / I2C1_SCL / UART4_nCTS

82

44PA.2 / SPI0_CLK / UART4_RXD / UART1_RXD / I2C1_SDA / I2C0_SMBSUS / BPWM0_CH2 / EPWM0_CH3 / CIR0_RXD

PE.0 / SPI1_MOSI / UART3_RXD / I2C1_SDA / UART4_nRTS

83

43

PA.3 / SPI0_SS / UART4_TXD / UART1_TXD / I2C1_SCL / I2C0_SMBAL / CLKO / BPWM0_CH3 / EPWM0_CH2 / EPWM1_BRAKE1

VSS

84

42

PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART5_RXD / I2C0_SDA / UART0_RXD / BPWM0_CH4 / EPWM0_CH1

LDO_CAP85

41

PA.5 / SPI1_I2SMCLK / UART0_nCTS / UART5_TXD / I2C0_SCL / UART0_TXD / BPWM0_CH5 / EPWM0_CH0

VDD

86

40

PD.15 / EPWM0_CH5 / TRACE_CLK / TM3 / INT1

39

PF.13 / I2C0_SDA / UART5_RXD / UART3_RXD / UART1_RXD / I2C1_SDA / EPWM0_CH3 / BPWM0_CH1 / TRACE_DATA038

PF.12 / I2C0_SCL / UART5_TXD / UART3_TXD / UART1_TXD / I2C1_SCL / EPWM0_CH2 / BPWM0_CH0 / TRACE_DATA1 / CIR0_RXD

PC.14 / SPI0_I2SMCLK / CIR0_RXD / EPWM0_SYNC_IN / TM1

87

PB.15 / EADC0_CH15 / SPI0_SS / UART0_nCTS / UART3_TXD / EPWM0_BRAKE1 / EPWM1_CH0 / TM0_EXT

88

PB.14 / EADC0_CH14 / SPI0_CLK / UART0_nRTS / UART3_RXD / EPWM1_CH1 / TM1_EXT / CLKO89

37

PA.6 / SPI1_SS / UART0_RXD / I2C1_SDA / EPWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0

PB.13 / EADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / UART0_TXD / UART3_nRTS / EPWM1_CH2 / TM2_EXT

9036PA.7 / SPI1_CLK / UART0_TXD / I2C1_SCL / EPWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1

PB.12 / EADC0_CH12 / DAC0_OUT / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / UART0_RXD / UART3_nCTS / EPWM1_CH3 / TM3_EXT

9135

PC.6 / SPI1_MOSI / UART4_RXD / UART0_nRTS / I2C1_SMBSUS / EPWM1_CH3 / BPWM1_CH1 / TRACE_DATA2 / TM1 / INT2

AVDD

92

34

PC.7 / SPI1_MISO / UART4_TXD / UART0_nCTS / I2C1_SMBAL / EPWM1_CH2 / BPWM1_CH0 / TRACE_DATA3 / TM0 / INT3

VREF

93

33

PC.8 / I2C0_SDA / UART4_nCTS / UART1_RXD / EPWM1_CH1 / BPWM1_CH4

AVSS

94

32

PE.13 / I2C0_SCL / UART4_nRTS / UART1_TXD / EPWM0_CH5 / EPWM1_CH0 / BPWM1_CH5

PB.11 / EADC0_CH11 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0

95

31

PE.12 / UART1_nRTS / EPWM0_CH4 / TRACE_CLK

PB.10 / EADC0_CH10 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1

9630

PE.9 / UART2_RXD / EPWM0_CH1 / EPWM0_BRAKE1 / TRACE_DATA2

PB.9 / EADC0_CH9 / UART0_TXD / UART1_nCTS / I2C1_SMBAL / I2C0_SCL / BPWM1_CH2 / INT7

97

29

PE.8 / UART2_TXD / EPWM0_CH0 / EPWM0_BRAKE0 / TRACE_DATA3

PB.8 / EADC0_CH8 / UART0_RXD / UART1_nRTS / I2C1_SMBSUS / I2C0_SDA / BPWM1_CH3 / INT6

98

28

VDD

PB.7 / EADC0_CH7 / UART1_TXD / BPWM1_CH4 / EPWM1_BRAKE0 / EPWM1_CH4 / INT5 / ACMP0_O

99

27

VSS

PB.6 / EADC0_CH6 / UART1_RXD / BPWM1_CH5 / EPWM1_BRAKE1 / EPWM1_CH5 / INT4 / ACMP1_O

100

26

PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT / BPWM1_CH1

21

22

23

24

25

PF.6 / SPI0_MOSI / UART4_RXD

PF.14 / EPWM1_BRAKE0 / EPWM0_BRAKE0 / EPWM0_CH4 / CLKO / TM3 / INT5

PF.4 / UART2_TXD / UART2_nRTS / EPWM0_CH1 / BPWM0_CH5 / X32_OUT

PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0

PF.8 / SPI0_CLK / UART5_nCTS

PF.7 / SPI0_MISO / UART4_TXD

PF.5 / UART2_RXD / UART2_nCTS / EPWM0_CH0 / BPWM0_CH4 / EPWM0_SYNC_OUT / X32_IN / EADC0_ST

17

18

19

20

PD.11 / EADC0_CH17 / UART1_TXD / INT6

16

PD.12 / EADC0_CH18 / UART2_RXD / BPWM0_CH5 / CLKO / EADC0_ST / INT5

PD.10 / EADC0_CH16 / UART1_RXD / INT7

13

14

15

PA.9 / EADC0_CH21 / UART1_TXD / BPWM0_CH2 / TM2_EXT

PA.8 / EADC0_CH20 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4

PA.11 / EADC0_CH23 / ACMP0_P0 / BPWM0_CH0 / EPWM0_SYNC_OUT / TM0_EXT

PA.10 / EADC0_CH22 / ACMP1_P0 / BPWM0_CH1 / TM1_EXT / DAC0_ST

9

10

11

12

PB.0 / EADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / EPWM0_CH5 / EPWM1_CH5 / EPWM0_BRAKE1

PI.0 / UART0_TXD / I2C0_SCL / UART5_TXD / UART2_TXD / I2C1_SCL / EPWM0_CH4 / EPWM1_CH0 / ACMP0_O

PI.1 / UART0_RXD / I2C0_SDA / UART5_RXD / UART2_RXD / I2C1_SDA / EPWM0_CH5 / EPWM1_CH1 / ACMP1_O

5

6

7

8

PC.10 / UART3_TXD / EPWM1_CH2

PC.12 / UART0_TXD / I2C0_SCL / EPWM1_CH0 / ACMP0_O

PC.11 / UART0_RXD / I2C0_SDA / EPWM1_CH1 / ACMP1_O

PB.2 / EADC0_CH2 / ACMP0_P1 / SPI1_SS / UART1_RXD / UART5_nCTS / EPWM0_CH3 / I2C1_SDA / TM3 / INT3

PB.1 / EADC0_CH1 / SPI1_I2SMCLK / UART2_TXD / I2C1_SCL / EPWM0_CH4 / EPWM1_CH4 / EPWM0_BRAKE0

1

2

3

4

PB.5 / EADC0_CH5 / ACMP1_N / SPI1_MISO / I2C0_SCL / UART5_TXD / EPWM0_CH0 / UART2_TXD / TM0 / INT0

PB.4 / EADC0_CH4 / ACMP1_P1 / SPI1_MOSI / I2C0_SDA / UART5_RXD / EPWM0_CH1 / UART2_RXD / TM1 / INT1

M471V/M471K/M471C SERIES DATASHEETPB.3 / EADC0_CH3 / ACMP0_N / SPI1_CLK / UART1_TXD / UART5_nRTS / EPWM0_CH2 / I2C1_SCL / EPWM0_BRAKE0 / TM2 / INT2

LQFP100

Figure 4.1-4 LQFP 100-pin Multi-function Pin Diagram

Dec. 22, 2022

Page 22 of 178

Rev 1.40

M471V/M471K/M471C Series
LQFP-128 Pin Multi-function Pin Diagram

PD.8 / UART2_nRTS

PD.9 / UART2_nCTS

PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK

PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT

68

67

66

65

PC.2 / SPI1_MOSI / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / EPWM1_CH3

PC.3 / SPI1_MISO / UART2_nRTS / I2C0_SMBAL / UART3_TXD / EPWM1_CH2

PC.4 / SPI1_I2SMCLK / UART2_RXD / I2C1_SDA / UART4_RXD / EPWM1_CH1

PC.5 / UART2_TXD / I2C1_SCL / UART4_TXD / EPWM1_CH0

72

71

70

69

PI.3 / UART1_RXD / I2C0_SDA / UART5_RXD / I2C1_SDA / UART4_RXD / BPWM0_CH4

PI.2 / UART1_TXD / I2C0_SCL / UART5_TXD / I2C1_SCL / UART4_TXD / BPWM0_CH5 / EADC0_ST

PC.0 / SPI1_SS / UART2_RXD / I2C0_SDA / EPWM1_CH5 / ACMP1_O

PC.1 / SPI1_CLK / UART2_TXD / I2C0_SCL / EPWM1_CH4 / ACMP0_O / EADC0_ST

76

75

74

73

PG.12 / BPWM0_CH2

PG.11 / BPWM0_CH3

PG.10 / BPWM0_CH4

PG.9 / BPWM0_CH5

80

79

78

77

PD.7 / UART1_TXD / I2C0_SCL / SPI1_MISO

PG.15 / CLKO / EADC0_ST

PG.14 / BPWM0_CH0

PG.13 / BPWM0_CH1

84

83

82

81

PD.3 / SPI0_SS / UART3_nRTS / UART0_TXD

PD.4 / I2C1_SDA / SPI1_SS

PD.5 / I2C1_SCL / SPI1_CLK

PD.6 / UART1_RXD / I2C0_SDA / SPI1_MOSI

88

87

86

85

PD.13 / SPI0_I2SMCLK / SPI1_I2SMCLK

PD.0 / SPI0_MOSI / UART3_RXD / TM2

PD.1 / SPI0_MISO / UART3_TXD

PD.2 / SPI0_CLK / UART3_nCTS / UART0_RXD

92

91

90

89

PA.15 / UART0_RXD / BPWM1_CH5 / EPWM0_SYNC_IN

PA.14 / UART0_TXD / BPWM1_CH4

PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3

PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2

96

95

94

93

Corresponding Part Number: M471KI8AE

PE.7 / UART5_TXD / EPWM0_CH0 / BPWM0_CH5

9764

nRESET

PE.6 / UART5_RXD / EPWM0_CH1 / BPWM0_CH4

98

63PE.15 / UART2_RXD

PE.5 / EPWM0_CH2 / BPWM0_CH3

99

62

PE.14 / UART2_TXD

PE.4 / EPWM0_CH3 / BPWM0_CH2

100

61

PF.15 / EPWM0_BRAKE0 / EPWM0_CH1 / TM2 / CLKO / INT4

PE.3 / EPWM0_CH4 / BPWM0_CH1

101

60

PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / EPWM0_CH5 / DAC0_ST

PE.2 / EPWM0_CH5 / BPWM0_CH0

102

59

PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / EPWM0_CH4

PI.4 / UART4_TXD / UART0_TXD / UART1_TXD / EPWM0_CH5 / CIR0_RXD / ACMP0_O

103

58

PA.2 / SPI0_CLK / UART4_RXD / UART1_RXD / I2C1_SDA / I2C0_SMBSUS / BPWM0_CH2 / EPWM0_CH3 / CIR0_RXD

PI.5 / UART4_RXD / UART0_RXD / UART1_RXD / EPWM0_CH4 / ACMP1_O

104

57

PA.3 / SPI0_SS / UART4_TXD / UART1_TXD / I2C1_SCL / I2C0_SMBAL / CLKO / BPWM0_CH3 / EPWM0_CH2 / EPWM1_BRAKE1

PE.1 / SPI1_MISO / UART3_TXD / I2C1_SCL / UART4_nCTS

105

56

PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART5_RXD / I2C0_SDA / UART0_RXD / BPWM0_CH4 / EPWM0_CH1

PE.0 / SPI1_MOSI / UART3_RXD / I2C1_SDA / UART4_nRTS

106

55

PA.5 / SPI1_I2SMCLK / UART0_nCTS / UART5_TXD / I2C0_SCL / UART0_TXD / BPWM0_CH5 / EPWM0_CH0

PH.8 / SPI1_CLK / UART3_nRTS / I2C1_SMBAL / UART1_TXD

107

54

PD.15 / EPWM0_CH5 / TRACE_CLK / TM3 / INT1

PH.9 / SPI1_SS / UART3_nCTS / I2C1_SMBSUS / UART1_RXD

108

53

PF.13 / I2C0_SDA / UART5_RXD / UART3_RXD / UART1_RXD / I2C1_SDA / EPWM0_CH3 / BPWM0_CH1 / TRACE_DATA0

PH.10 / SPI1_I2SMCLK / UART4_TXD / UART0_TXD

109

52

PF.12 / I2C0_SCL / UART5_TXD / UART3_TXD / UART1_TXD / I2C1_SCL / EPWM0_CH2 / BPWM0_CH0 / TRACE_DATA1 / CIR0_RXD

PH.11 / UART4_RXD / UART0_RXD / EPWM0_CH5

110

51

PA.6 / SPI1_SS / UART0_RXD / I2C1_SDA / EPWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0

PD.14 / SPI0_I2SMCLK / EPWM0_CH4

111

50

PA.7 / SPI1_CLK / UART0_TXD / I2C1_SCL / EPWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1

VSS

112

49

PC.6 / SPI1_MOSI / UART4_RXD / UART0_nRTS / I2C1_SMBSUS / EPWM1_CH3 / BPWM1_CH1 / TRACE_DATA2 / TM1 / INT2

LDO_CAP

113

48

PC.7 / SPI1_MISO / UART4_TXD / UART0_nCTS / I2C1_SMBAL / EPWM1_CH2 / BPWM1_CH0 / TRACE_DATA3 / TM0 / INT3

VDD

114

47

PC.8 / I2C0_SDA / UART4_nCTS / UART1_RXD / EPWM1_CH1 / BPWM1_CH4

PC.14 / SPI0_I2SMCLK / CIR0_RXD / EPWM0_SYNC_IN / TM1

115

46

PE.13 / I2C0_SCL / UART4_nRTS / UART1_TXD / EPWM0_CH5 / EPWM1_CH0 / BPWM1_CH5

PB.15 / EADC0_CH15 / SPI0_SS / UART0_nCTS / UART3_TXD / EPWM0_BRAKE1 / EPWM1_CH0 / TM0_EXT

116

45

PE.12 / UART1_nRTS / EPWM0_CH4 / TRACE_CLK

PB.14 / EADC0_CH14 / SPI0_CLK / UART0_nRTS / UART3_RXD / EPWM1_CH1 / TM1_EXT / CLKO

117

44

PE.11 / UART3_RXD / UART1_nCTS / EPWM0_CH3 / EPWM1_BRAKE1 / TRACE_DATA0

PB.13 / EADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / UART0_TXD / UART3_nRTS / EPWM1_CH2 / TM2_EXT

118

43

PE.10 / UART3_TXD / EPWM0_CH2 / EPWM1_BRAKE0 / TRACE_DATA1

PB.12 / EADC0_CH12 / DAC0_OUT / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / UART0_RXD / UART3_nCTS / EPWM1_CH3 /TM3_EXT

119

42

PE.9 / UART2_RXD / EPWM0_CH1 / EPWM0_BRAKE1 / TRACE_DATA2

AVDD

120

41

PE.8 / UART2_TXD / EPWM0_CH0 / EPWM0_BRAKE0 / TRACE_DATA3

VREF

121

40

VDD

AVSS

122

39

VSS

PB.11 / EADC0_CH11 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0

123

38

PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT / BPWM1_CH1

PB.10 / EADC0_CH10 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1

124

37

PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0

PB.9 / EADC0_CH9 / UART0_TXD / UART1_nCTS / I2C1_SMBAL / I2C0_SCL / BPWM1_CH2 / INT7

125

36

PH.7 / SPI1_SS

PB.8 / EADC0_CH8 / UART0_RXD / UART1_nRTS / I2C1_SMBSUS / I2C0_SDA / BPWM1_CH3 / INT6

126

35

PH.6 / SPI1_CLK

PB.7 / EADC0_CH7 / UART1_TXD / BPWM1_CH4 / EPWM1_BRAKE0 / EPWM1_CH4 / INT5 / ACMP0_O

127

34

PH.5 / SPI1_MOSI

PB.6 / EADC0_CH6 / UART1_RXD / BPWM1_CH5 / EPWM1_BRAKE1 / EPWM1_CH5 / INT4 / ACMP1_O

128

33

PH.4 / SPI1_MISO

29

30

31

32

PF.6 / SPI0_MOSI / UART4_RXD

PF.14 / EPWM1_BRAKE0 / EPWM0_BRAKE0 / EPWM0_CH4 / CLKO / TM3 / INT5

PF.5 / UART2_RXD / UART2_nCTS / EPWM0_CH0 / BPWM0_CH4 / EPWM0_SYNC_OUT / X32_IN / EADC0_ST

PF.4 / UART2_TXD / UART2_nRTS / EPWM0_CH1 / BPWM0_CH5 / X32_OUT

25

26

27

28

PF.9 / SPI0_SS / UART5_nRTS

PF.8 / SPI0_CLK / UART5_nCTS

PF.7 / SPI0_MISO / UART4_TXD

PG.4 / TM2

PF.11 / UART5_TXD / TM3

PF.10 / SPI0_I2SMCLK / UART5_RXD

21

22

23

24

PG.2 / I2C0_SMBAL / I2C1_SCL / TM0

PG.3 / I2C0_SMBSUS / I2C1_SDA / TM1

17

18

19

20

PD.11 / EADC0_CH17 / UART1_TXD / INT6

PD.10 / EADC0_CH16 / UART1_RXD / INT7

PA.9 / EADC0_CH21 / UART1_TXD / BPWM0_CH2 / TM2_EXT

PA.8 / EADC0_CH20 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4

PC.13 / EADC0_CH19 / UART2_TXD / BPWM0_CH4 / CLKO / EADC0_ST

PA.10 / EADC0_CH22 / ACMP1_P0 / BPWM0_CH1 / TM1_EXT / DAC0_ST

PD.12 / EADC0_CH18 / UART2_RXD / BPWM0_CH5 / CLKO / EADC0_ST / INT5

13

14

15

16

PA.11 / EADC0_CH23 / ACMP0_P0 / BPWM0_CH0 / EPWM0_SYNC_OUT / TM0_EXT

9

10

11

12

PB.1 / EADC0_CH1 / SPI1_I2SMCLK / UART2_TXD / I2C1_SCL / EPWM0_CH4 / EPWM1_CH4 / EPWM0_BRAKE0

PB.0 / EADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / EPWM0_CH5 / EPWM1_CH5 / EPWM0_BRAKE1

PC.9 / UART3_RXD / EPWM1_CH3

PI.0 / UART0_TXD / I2C0_SCL / UART5_TXD / UART2_TXD / I2C1_SCL / EPWM0_CH4 / EPWM1_CH0 / ACMP0_O

PC.10 / UART3_TXD / EPWM1_CH2

PI.1 / UART0_RXD / I2C0_SDA / UART5_RXD / UART2_RXD / I2C1_SDA / EPWM0_CH5 / EPWM1_CH1 / ACMP1_O

5

6

7

8

PC.12 / UART0_TXD / I2C0_SCL / EPWM1_CH0 / ACMP0_O

PB.2 / EADC0_CH2 / ACMP0_P1 / SPI1_SS / UART1_RXD / UART5_nCTS / EPWM0_CH3 / I2C1_SDA / TM3 / INT3

PC.11 / UART0_RXD / I2C0_SDA / EPWM1_CH1 / ACMP1_O

1

2

3

4

PB.5 / EADC0_CH5 / ACMP1_N / SPI1_MISO / I2C0_SCL / UART5_TXD / EPWM0_CH0 / UART2_TXD / TM0 / INT0

PB.4 / EADC0_CH4 / ACMP1_P1 / SPI1_MOSI / I2C0_SDA / UART5_RXD / EPWM0_CH1 / UART2_RXD / TM1 / INT1

M471V/M471K/M471C SERIES DATASHEETPB.3 / EADC0_CH3 / ACMP0_N / SPI1_CLK / UART1_TXD / UART5_nRTS / EPWM0_CH2 / I2C1_SCL / EPWM0_BRAKE0 / TM2 / INT2

LQFP128

Figure 4.1-5 LQFP 128-pin Multi-function Pin Diagram

Dec. 22, 2022

Page 23 of 178

Rev 1.40

M471V/M471K/M471C Series
4.2

Pin Mapping

Different part number with same package might has different function. Please refer to the selection
guide in section 3.3, Pin Configuration in section 4.1 or NuTool - PinConfig.

Corresponding Part Number: M471VI8AE, M471KI8AE, M471CI8AE
M471
Pin Name

100 Pin

128 PinWLCSP 100 Pin

PB.5

1

1

A1

PB.4

2

2

E4

PB.3

3

3

B2

PB.2

4

4

D4

PC.12

5

5

A2

PC.11

6

6

C3

PC.10

7

7

PC.9

8

PB.1

8

9

C4

PB.0

9

10

B3

PI.0

10

11

M471V/M471K/M471C SERIES DATASHEET

VSS

A3

VDD

B4

PI.1

11

12

PA.11

12

13

A4

PA.10

13

14

C5

PA.9

14

15

B5

PA.8

15

16

A5

17

C6

PC.13
PD.12

16

18

B6

PD.11

17

19

A6

PD.10

18

20

D6

PG.2

21

PG.3

22

PG.4

23

PF.11

24

PF.10

25

PF.9

26

PF.8

Dec. 22, 2022

19

27

Page 24 of 178

A7

Rev 1.40

M471V/M471K/M471C Series
PF.7

20

28

B7

PF.6

21

29

A8

PF.14

22

30

B8

PF.5

23

31

A9

PF.4

24

32

A10

PH.4

33

PH.5

34

PH.6

35

PH.7

36

PF.3

25

37

B9

PF.2

26

38

B10

VSS

27

39

C7

VDD

28

40

D7

PE.8

29

41

C10

PE.9

30

42

C9

PE.10

43

PE.11

44
31

45

C8

PE.13

32

46

D9

PC.8

33

47

D10

PC.7

34

48

D8

PC.6

35

49

E8

PA.7

36

50

E10

PA.6

37

51

E9

PF.12

38

52

VSS

F10

VDD

G10

PF.13

39

53

PD.15

40

54

F9

PA.5

41

55

F8

PA.4

42

56

E7

PA.3

43

57

H10

PA.2

44

58

G9

PA.1

45

59

E6

PA.0

46

60

F7

Dec. 22, 2022

Page 25 of 178

M471V/M471K/M471C SERIES DATASHEET

PE.12

Rev 1.40

M471V/M471K/M471C Series
PF.15

47

61

J10

PE.14

48

62

H9

PE.15

49

63

G8

nRESET

50

64

J9

PF.0

51

65

K10

PF.1

52

66

F6

PD.9

53

67

G7

PD.8

54

68

H8

PC.5

55

69

K9

PC.4

56

70

J8

PC.3

57

71

G6

PC.2

58

72

H7

PC.1

59

73

K8

PC.0

60

74

J7

PI.2

61

75

VSS

K7

VDD

G5

PI.3

62

76

M471V/M471K/M471C SERIES DATASHEET

PG.9

77

PG.10

78

PG.11

79

PG.12

80

PG.13

81

PG.14

82

PG.15

83

PD.7

63

84

K6

PD.6

64

85

J6

PD.5

65

86

H6

PD.4

66

87

K5

PD.3

67

88

J5

PD.2

68

89

H5

PD.1

69

90

J4

PD.0

70

91

K4

PD.13

71

92

H4

PA.12

72

93

K3

Dec. 22, 2022

Page 26 of 178

Rev 1.40

M471V/M471K/M471C Series
PA.13

73

94

J3

PA.14

74

95

H3

PA.15

75

96

G4

PE.7

76

97

K2

PE.6

77

98

K1

PE.5

78

99

J2

PE.4

79

100

J1

PE.3

80

101

H2

PE.2

81

102

G3

VSS

H1

VDD

G2

PI.4

103

PI.5

104

PE.1

82

105

PE.0

83

106
107

PH.9

108

PH.10

109

PH.11

110

PD.14

111

VSS

84

112

F5

LDO_CAP

85

113

G1

VDD

86

114

F2

PC.14

87

115

F1

PB.15

88

116

F3

PB.14

89

117

F4

PB.13

90

118

E1

PB.12

91

119

E5

AVDD

92

120

D1

VREF

93

121

E2

AVSS

94

122

D5

PB.11

95

123

C1

PB.10

96

124

D2

PB.9

97

125

E3

PB.8

98

126

B1

Dec. 22, 2022

Page 27 of 178

M471V/M471K/M471C SERIES DATASHEET

PH.8

Rev 1.40

M471V/M471K/M471C Series
PB.7

99

127

D3

PB.6

100

128

C2

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 28 of 178

Rev 1.40

M471V/M471K/M471C Series
4.3

Pin Functional Description

Corresponding Part Number: M471VI8AE, M471KI8AE, M471CI8AE
4.3.1
Group

Multi-function Summary Table
Pin Name

GPIO

MFP

Type

ACMP0_N

PB.3

MFP1

A

PC.12

MFP14

O

PI.0

MFP14

O

PC.1

MFP14

O

PI.4

MFP15

O

PB.7

MFP15

O

ACMP0_P0

PA.11

MFP1

A

Analog comparator 0 positive input 0 pin.

ACMP0_P1

PB.2

MFP1

A

Analog comparator 0 positive input 1 pin.

ACMP0_P2

PB.12

MFP1

A

Analog comparator 0 positive input 2 pin.

ACMP0_P3

PB.13

MFP1

A

Analog comparator 0 positive input 3 pin.

ACMP0_WLAT

PA.7

MFP13

I

Analog comparator 0 window latch input
pin

ACMP1_N

PB.5

MFP1

A

Analog comparator 1 negative input pin.

PC.11

MFP14

O

PI.1

MFP14

O

PC.0

MFP14

O

PI.5

MFP15

O

PB.6

MFP15

O

ACMP1_P0

PA.10

MFP1

A

Analog comparator 1 positive input 0 pin.

ACMP1_P1

PB.4

MFP1

A

Analog comparator 1 positive input 1 pin.

ACMP1_P2

PB.12

MFP1

A

Analog comparator 1 positive input 2 pin.

ACMP1_P3

PB.13

MFP1

A

Analog comparator 1 positive input 3 pin.

ACMP1_WLAT

PA.6

MFP13

I

Analog comparator 1 window latch input
pin

PA.11

MFP9

I/O

PF.12

MFP11

I/O

PA.0

MFP12

I/O

PG.14

MFP12

I/O

PE.2

MFP13

I/O

ACMP0_O

ACMP0

ACMP1

BPWM0

BPWM0_CH0

Dec. 22, 2022

Page 29 of 178

Analog comparator 0 negative input pin.

Analog comparator 0 output pin.

Analog comparator 1 output pin.

BPWM0 channel 0 output/capture input.

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETACMP1_O

Description

M471V/M471K/M471C SeriesGroup

Pin Name

BPWM0_CH1

GPIO

MFP

Type

PA.10

MFP9

I/O

PF.13

MFP11

I/O

PA.1

MFP12

I/O

PG.13

MFP12

I/O

PE.3

MFP13

I/O

PA.9

MFP9

I/O

PA.2

MFP12

I/O

PG.12

MFP12

I/O

PE.4

MFP13

I/O

PA.8

MFP9

I/O

PA.3

MFP12

I/O

PG.11

MFP12

I/O

PE.5

MFP13

I/O

PC.13

MFP9

I/O

PF.5

MFP8

I/O

PA.4

MFP12

I/O

PI.3

MFP12

I/O

PG.10

MFP12

I/O

PE.6

MFP13

I/O

PD.12

MFP9

I/O

PF.4

MFP8

I/O

PA.5

MFP12

I/O

PI.2

MFP12

I/O

PG.9

MFP12

I/O

PE.7

MFP13

I/O

PF.3

MFP11

I/O

PC.7

MFP12

I/O

PF.0

MFP12

I/O

PB.11

MFP10

I/O

PF.2

MFP11

I/O

PC.6

MFP12

I/O

PF.1

MFP12

I/O

BPWM0_CH2

BPWM0 channel 3 output/capture input.

BPWM0_CH4

BPWM0 channel 4 output/capture input.

M471V/M471K/M471C SERIES DATASHEETBPWM0_CH5

BPWM0 channel 5 output/capture input.

BPWM1_CH0

BPWM1_CH1

Dec. 22, 2022

BPWM0 channel 1 output/capture input.

BPWM0 channel 2 output/capture input.

BPWM0_CH3

BPWM1

Description

BPWM1 channel 0 output/capture input.

Page 30 of 178

BPWM1 channel 1 output/capture input.

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

PB.10

MFP10

I/O

PA.7

MFP12

I/O

PA.12

MFP11

I/O

PB.9

MFP10

I/O

PA.6

MFP12

I/O

PA.13

MFP11

I/O

PB.8

MFP10

I/O

PC.8

MFP12

I/O

PA.14

MFP11

I/O

PB.7

MFP10

I/O

PE.13

MFP12

I/O

PA.15

MFP11

I/O

PB.6

MFP10

I/O

PF.12

MFP15

I

PA.2

MFP15

I

PI.4

MFP14

I

PC.14

MFP10

I

PC.13

MFP13

O

PD.12

MFP13

O

PF.14

MFP13

O

PA.3

MFP11

O

PF.15

MFP14

O

PG.15

MFP14

O

PB.14

MFP14

O

PB.12

MFP1

A

PA.10

MFP14

I

PA.0

MFP15

I

EADC0_CH0

PB.0

MFP1

A

EADC0 channel 0 analog input.

EADC0_CH1

PB.1

MFP1

A

EADC0 channel 1 analog input.

EADC0_CH2

PB.2

MFP1

A

EADC0 channel 2 analog input.

EADC0_CH3

PB.3

MFP1

A

EADC0 channel 3 analog input.

EADC0_CH4

PB.4

MFP1

A

EADC0 channel 4 analog input.

BPWM1_CH2

BPWM1_CH3

BPWM1_CH4

BPWM1_CH5

CIR0

CLKO

DAC0_OUT
DAC0

Dec. 22, 2022

BPWM1 channel 3 output/capture input.

BPWM1 channel 4 output/capture input.

BPWM1 channel 5 output/capture input.

CIR0 data receiver input pin.

DAC0_ST

EADC0

BPWM1 channel 2 output/capture input.

M471V/M471K/M471C SERIES DATASHEETCLKO

CIR0_RXD

Description

Clock Out

DAC0 channel analog output.
DAC0 external trigger input.

Page 31 of 178

Rev 1.40

M471V/M471K/M471C SeriesGroup

M471V/M471K/M471C SERIES DATASHEETPin Name

GPIO

MFP

Type

EADC0_CH5

PB.5

MFP1

A

EADC0 channel 5 analog input.

EADC0_CH6

PB.6

MFP1

A

EADC0 channel 6 analog input.

EADC0_CH7

PB.7

MFP1

A

EADC0 channel 7 analog input.

EADC0_CH8

PB.8

MFP1

A

EADC0 channel 8 analog input.

EADC0_CH9

PB.9

MFP1

A

EADC0 channel 9 analog input.

EADC0_CH10

PB.10

MFP1

A

EADC0 channel 10 analog input.

EADC0_CH11

PB.11

MFP1

A

EADC0 channel 11 analog input.

EADC0_CH12

PB.12

MFP1

A

EADC0 channel 12 analog input.

EADC0_CH13

PB.13

MFP1

A

EADC0 channel 13 analog input.

EADC0_CH14

PB.14

MFP1

A

EADC0 channel 14 analog input.

EADC0_CH15

PB.15

MFP1

A

EADC0 channel 15 analog input.

EADC0_CH16

PD.10

MFP1

A

EADC0 channel 16 analog input.

EADC0_CH17

PD.11

MFP1

A

EADC0 channel 17 analog input.

EADC0_CH18

PD.12

MFP1

A

EADC0 channel 18 analog input.

EADC0_CH19

PC.13

MFP1

A

EADC0 channel 19 analog input.

EADC0_CH20

PA.8

MFP1

A

EADC0 channel 20 analog input.

EADC0_CH21

PA.9

MFP1

A

EADC0 channel 21 analog input.

EADC0_CH22

PA.10

MFP1

A

EADC0 channel 22 analog input.

EADC0_CH23

PA.11

MFP1

A

EADC0 channel 23 analog input.

PC.13

MFP14

I

PD.12

MFP14

I

PF.5

MFP11

I

PC.1

MFP15

I

PI.2

MFP15

I

PG.15

MFP15

I

PB.3

MFP13

I

PB.1

MFP13

I

PF.14

MFP10

I

PE.8

MFP11

I

PF.15

MFP11

I

PB.0

MFP13

I

PE.9

MFP11

I

EADC0_ST

EPWM0_BRAKE0
EPWM0

EADC0 external trigger input.

EPWM0_BRAKE1

Dec. 22, 2022

Description

EPWM0 Brake 0 input pin.

EPWM0 Brake 1 input pin.

Page 32 of 178

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

EPWM0_CH0

GPIO

MFP

Type

PB.15

MFP10

I

PB.5

MFP11

I/O

PF.5

MFP7

I/O

PE.8

MFP10

I/O

PA.5

MFP13

I/O

PE.7

MFP12

I/O

PB.4

MFP11

I/O

PF.4

MFP7

I/O

PE.9

MFP10

I/O

PA.4

MFP13

I/O

PF.15

MFP12

I/O

PE.6

MFP12

I/O

PB.3

MFP11

I/O

PE.10

MFP10

I/O

PF.12

MFP10

I/O

PA.3

MFP13

I/O

PE.5

MFP12

I/O

PB.2

MFP11

I/O

PE.11

MFP10

I/O

PF.13

MFP10

I/O

PA.2

MFP13

I/O

PE.4

MFP12

I/O

PB.1

MFP11

I/O

PI.0

MFP11

I/O

PF.14

MFP12

I/O

PE.12

MFP10

I/O

PA.1

MFP13

I/O

PE.3

MFP12

I/O

PI.5

MFP11

I/O

PD.14

MFP11

I/O

PB.0

MFP11

I/O

PI.1

MFP11

I/O

EPWM0_CH1

EPWM0_CH2

EPWM0 channel 1 output/capture input.

EPWM0_CH4

EPWM0 channel 2 output/capture input.

EPWM0 channel 3 output/capture input.

EPWM0 channel 4 output/capture input.

EPWM0_CH5

Dec. 22, 2022

EPWM0 channel 0 output/capture input.

EPWM0 channel 5 output/capture input.

Page 33 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETEPWM0_CH3

Description

M471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

PE.13

MFP10

I/O

PD.15

MFP12

I/O

PA.0

MFP13

I/O

PE.2

MFP12

I/O

PI.4

MFP11

I/O

PH.11

MFP11

I/O

PA.15

MFP12

I

PC.14

MFP11

I

PA.11

MFP10

O

PF.5

MFP9

O

PF.14

MFP9

I

PE.10

MFP11

I

PB.7

MFP11

I

PE.11

MFP11

I

PA.3

MFP15

I

PB.6

MFP11

I

PC.12

MFP12

I/O

PI.0

MFP12

I/O

PE.13

MFP11

I/O

PC.5

MFP12

I/O

PB.15

MFP11

I/O

PC.11

MFP12

I/O

PI.1

MFP12

I/O

PC.8

MFP11

I/O

PC.4

MFP12

I/O

PB.14

MFP11

I/O

PC.10

MFP12

I/O

PC.7

MFP11

I/O

PC.3

MFP12

I/O

PB.13

MFP11

I/O

PC.9

MFP12

I/O

PC.6

MFP11

I/O

EPWM0_SYNC_IN

EPWM0_SYNC_OU
T

EPWM1_BRAKE0

EPWM1_BRAKE1

M471V/M471K/M471C SERIES DATASHEETEPWM1_CH0

Description

EPWM0 counter
input pin.

synchronous

trigger

EPWM0 counter
output pin.

synchronous

trigger

EPWM1 Brake 0 input pin.

EPWM1 Brake 1 input pin.

EPWM1 channel 0 output/capture input.

EPWM1

EPWM1_CH1

EPWM1_CH2

EPWM1 channel 2 output/capture input.

EPWM1_CH3

Dec. 22, 2022

EPWM1 channel 1 output/capture input.

EPWM1 channel 3 output/capture input.

Page 34 of 178

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

PC.2

MFP12

I/O

PB.12

MFP11

I/O

PB.1

MFP12

I/O

PA.7

MFP11

I/O

PC.1

MFP12

I/O

PB.7

MFP12

I/O

PB.0

MFP12

I/O

PA.6

MFP11

I/O

PC.0

MFP12

I/O

PB.6

MFP12

I/O

PB.5

MFP6

I/O

PC.12

MFP4

I/O

PI.0

MFP4

I/O

PF.3

MFP4

I/O

PE.13

MFP4

I/O

PF.12

MFP4

I/O

PA.5

MFP9

I/O

PC.1

MFP9

I/O

PI.2

MFP4

I/O

PD.7

MFP4

I/O

PB.9

MFP9

I/O

PB.4

MFP6

I/O

PC.11

MFP4

I/O

PI.1

MFP4

I/O

PF.2

MFP4

I/O

PC.8

MFP4

I/O

PF.13

MFP4

I/O

PA.4

MFP9

I/O

PC.0

MFP9

I/O

PI.3

MFP4

I/O

PD.6

MFP4

I/O

PB.8

MFP9

I/O

EPWM1_CH4

EPWM1 channel 4 output/capture input.

EPWM1_CH5

I2C0_SCL

Description

EPWM1 channel 5 output/capture input.

I2C0 clock pin.

M471V/M471K/M471C SERIES DATASHEET

I2C0

I2C0_SDA

Dec. 22, 2022

Page 35 of 178

I2C0 data input/output pin.

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

I2C0_SMBAL

I2C0_SMBSUS

GPIO

MFP

Type

PG.2

MFP4

O

PA.3

MFP10

O

PC.3

MFP9

O

PG.3

MFP4

O

PA.2

MFP10

O

PC.2

MFP9

O

PB.3

MFP12

I/O

PB.1

MFP9

I/O

PI.0

MFP9

I/O

PG.2

MFP5

I/O

PA.7

MFP8

I/O

PF.12

MFP9

I/O

PA.3

MFP9

I/O

PF.0

MFP3

I/O

PC.5

MFP9

I/O

PI.2

MFP9

I/O

PD.5

MFP4

I/O

PA.12

MFP4

I/O

PE.1

MFP8

I/O

PB.11

MFP7

I/O

PB.2

MFP12

I/O

PB.0

MFP9

I/O

PI.1

MFP9

I/O

PG.3

MFP5

I/O

PA.6

MFP8

I/O

PF.13

MFP9

I/O

Description

I2C0 SMBus SMBALTER pin

I2C0 SMBus SMBSUS
CONTROL pin)

pin

(PMBusI2C1 clock pin.

I2C1_SCL

M471V/M471K/M471C SERIES DATASHEETI2C1

I2C1 data input/output pin.

I2C1_SDA

Dec. 22, 2022

PA.2

MFP9

I/O

PF.1

MFP3

I/O

PC.4

MFP9

I/O

PI.3

MFP9

I/O

PD.4

MFP4

I/O

PA.13

MFP4

I/O

Page 36 of 178

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

I2C1_SMBAL

I2C1_SMBSUS

GPIO

MFP

Type

PE.0

MFP8

I/O

PB.10

MFP7

I/O

PC.7

MFP8

O

PH.8

MFP8

O

PB.9

MFP7

O

PC.6

MFP8

O

PH.9

MFP8

O

PB.8

MFP7

O

PF.1

MFP14

I

Description

I2C1 SMBus SMBALTER pin

I2C1 SMBus SMBSUS
CONTROL pin)

pin

(PMBusSerial wired debugger clock pin.
ICE_CLK

Note: It is recommended to use 100 kΩ
pull-up resistor on ICE_CLK pin.

ICE
Serial wired debugger data pin.
ICE_DAT

INT0

INT1

INT3

INT4

INT5

INT6

INT7

MFP14

I/O

PB.5

MFP15

I

PA.6

MFP15

I

PB.4

MFP15

I

PA.7

MFP15

I

PD.15

MFP15

I

PB.3

MFP15

I

PC.6

MFP15

I

PB.2

MFP15

I

PC.7

MFP15

I

PA.8

MFP15

I

PF.15

MFP15

I

PB.6

MFP13

I

PD.12

MFP15

I

PF.14

MFP15

I

PB.7

MFP13

I

PD.11

MFP15

I

PB.8

MFP13

I

PD.10

MFP15

I

PB.9

MFP13

I

INT0

INT1

External interrupt 0 input pin.

INT2

INT5

External interrupt 3 input pin.

INT6

External interrupt 4 input pin.

External interrupt 5 input pin.

External interrupt 6 input pin.

INT7

Dec. 22, 2022

External interrupt 1 input pin.

External interrupt 2 input pin.

INT3

INT4

Note: It is recommended to use 100 kΩ
pull-up resistor on ICE_DAT pin.

M471V/M471K/M471C SERIES DATASHEET

INT2

PF.0

External interrupt 7 input pin.

Page 37 of 178

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

PF.8

MFP5

I/O

PA.2

MFP4

I/O

PD.2

MFP4

I/O

PB.14

MFP4

I/O

PB.0

MFP8

I/O

PF.10

MFP5

I/O

PA.4

MFP4

I/O

PD.13

MFP4

I/O

PD.14

MFP5

I/O

PC.14

MFP4

I/O

PB.11

MFP9

I/O

PF.7

MFP5

I/O

PA.1

MFP4

I/O

PD.1

MFP4

I/O

PB.13

MFP4

I/O

PF.6

MFP5

I/O

PA.0

MFP4

I/O

PD.0

MFP4

I/O

PB.12

MFP4

I/O

PF.9

MFP5

I/O

PA.3

MFP4

I/O

PD.3

MFP4

I/O

PB.15

MFP4

I/O

PB.3

MFP5

I/O

PH.6

MFP3

I/O

PA.7

MFP4

I/O

PC.1

MFP7

I/O

PD.5

MFP5

I/O

PH.8

MFP6

I/O

PB.1

MFP5

I/O

PA.5

MFP4

I/O

PC.4

MFP7

I/O

SPI0_CLK

SPI0_I2SMCLKSPI0

SPI0 serial clock pin.

SPI0_MISO

M471V/M471K/M471C SERIES DATASHEETSPI0 MOSI (Master Out, Slave In) pin.

SPI0_SSSPI0 slave select pin.

SPI1_CLK

SPI1_I2SMCLK

Dec. 22, 2022

SPI0 I2S master clock output pin

SPI0 MISO (Master In, Slave Out) pin.

SPI0_MOSISPI1Description

SPI1 serial clock pin.

Page 38 of 178

SPI1 I2S master clock output pin

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

PD.13

MFP5

I/O

PH.10

MFP6

I/O

PB.5

MFP5

I/O

PH.4

MFP3

I/O

PC.7

MFP4

I/O

PC.3

MFP7

I/O

PD.7

MFP5

I/O

PE.1

MFP6

I/O

PB.4

MFP5

I/O

PH.5

MFP3

I/O

PC.6

MFP4

I/O

PC.2

MFP7

I/O

PD.6

MFP5

I/O

PE.0

MFP6

I/O

PB.2

MFP5

I/O

PH.7

MFP3

I/O

PA.6

MFP4

I/O

PC.0

MFP7

I/O

PD.4

MFP5

I/O

PH.9

MFP6

I/O

PB.5

MFP14

I/O

PG.2

MFP13

I/O

PC.7

MFP14

I/O

PA.11

MFP13

I/O

PB.15

MFP13

I/O

PB.4

MFP14

I/O

PG.3

MFP13

I/O

PC.6

MFP14

I/O

PC.14

MFP13

I/O

PA.10

MFP13

I/O

PB.14

MFP13

I/O

PB.3

MFP14

I/O

Timer2 event counter input/toggle output

Page 39 of 178

Rev 1.40

SPI1_MISOSPI1 MISO (Master In, Slave Out) pin.

SPI1_MOSISPI1 MOSI (Master Out, Slave In) pin.

TM0

SPI1 slave select pin.

TM0_EXT

TM1

Timer0 event counter input/toggle output
pin.

Timer0 external
output pin.

captureinput/toggle

Timer1 event counter input/toggle output
pin.

TM1

TM1_EXT
TM2

TM2

Dec. 22, 2022

Timer1 external
output pin.

captureinput/toggle

M471V/M471K/M471C SERIES DATASHEETSPI1_SS

TM0

Description

M471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

Description

PG.4

MFP13

I/O

pin.

PA.7

MFP14

I/O

PF.15

MFP13

I/O

PD.0

MFP14

I/O

PA.9

MFP13

I/O

PB.13

MFP13

I/O

PB.2

MFP14

I/O

PF.11

MFP13

I/O

PF.14

MFP14

I/O

PA.6

MFP14

I/O

PD.15

MFP14

I/O

PA.8

MFP13

I/O

PB.12

MFP13

I/O

PE.12

MFP14

O

PD.15

MFP13

O

PE.11

MFP14

O

PF.13

MFP13

O

PE.10

MFP14

O

PF.12

MFP13

O

PE.9

MFP14

O

PC.6

MFP13

O

PE.8

MFP14

O

PC.7

MFP13

O

PC.11

MFP3

I

PI.1

MFP3

I

PF.2

MFP3

I

PA.6

MFP7

I

PA.4

MFP11

I

PA.0

MFP7

I

PF.1

MFP4

I

PD.2

MFP9

I

PA.15

MFP3

I

TM2_EXT

TM3
TM3

TM3_EXTTRACE_CLK

M471V/M471K/M471C SERIES DATASHEETTRACE_DATA1

Dec. 22, 2022

Timer3 event counter input/toggle output
pin.

Timer3 external
output pin.

captureinput/toggle

ETM Trace Data 1 output pin

ETM Trace Data 2 output pin

TRACE_DATA3UART0_RXD

input/toggle

ETM Trace Data 0 output pin

TRACE_DATA2

UART0

captureETM Trace Clock output pin

TRACE_DATA0TRACETimer2 external
output pin.

ETM Trace Data 3 output pin

Page 40 of 178

UART0 data receiver input pin.

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

UART0_TXD

MFP

Type

PI.5

MFP8

I

PH.11

MFP8

I

PB.12

MFP6

I

PB.8

MFP5

I

PC.12

MFP3

O

PI.0

MFP3

O

PF.3

MFP3

O

PA.7

MFP7

O

PA.5

MFP11

O

PA.1

MFP7

O

PF.0

MFP4

O

PD.3

MFP9

O

PA.14

MFP3

O

PI.4

MFP8

O

PH.10

MFP8

O

PB.13

MFP6

O

PB.9

MFP5

O

PC.7

MFP7

I

PA.5

MFP7

I

PB.15

MFP6

I

PB.11

MFP5

I

PC.6

MFP7

O

PA.4

MFP7

O

PB.14

MFP6

O

PB.10

MFP5

O

PB.2

MFP6

I

PA.8

MFP7

I

PD.10

MFP3

I

PC.8

MFP8

I

PF.13

MFP8

I

PA.2

MFP8

I

PF.1

MFP2

I

UART0_nCTS

UART1_RXD

Dec. 22, 2022

UART0 data transmitter output pin.

UART0 clear to Send input pin.

UART0_nRTS

UART1

Description

UART0 request to Send output pin.

Page 41 of 178

UART1 data receiver input pin.

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETGPIOM471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

PI.3

MFP3

I

PD.6

MFP3

I

PI.5

MFP10

I

PH.9

MFP10

I

PB.6

MFP6

I

PB.3

MFP6

O

PA.9

MFP7

O

PD.11

MFP3

O

PE.13

MFP8

O

PF.12

MFP8

O

PA.3

MFP8

O

PF.0

MFP2

O

PI.2

MFP3

O

PD.7

MFP3

O

PI.4

MFP10

O

PH.8

MFP10

O

PB.7

MFP6

O

PE.11

MFP8

I

PA.1

MFP8

I

PB.9

MFP6

I

PE.12

MFP8

O

PA.0

MFP8

O

PB.8

MFP6

O

PB.4

MFP12

I

PB.0

MFP7

I

PI.1

MFP7

I

PD.12

MFP7

I

PF.5

MFP2

I

PE.9

MFP7

I

PE.15

MFP3

I

PC.4

MFP8

I

PC.0

MFP8

I

UART1_TXD

M471V/M471K/M471C SERIES DATASHEETUART1_nCTS

UART1_nRTS

UART2

UART2_RXD

Dec. 22, 2022

Description

UART1 data transmitter output pin.

Page 42 of 178

UART1 clear to Send input pin.

UART1 request to Send output pin.

UART2 data receiver input pin.

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

UART2_TXD

UART2_nCTS

UART2_nRTS

UART3

UART3_TXD

UART3_nCTS

Dec. 22, 2022

MFP

Type

PB.5

MFP12

O

PB.1

MFP7

O

PI.0

MFP7

O

PC.13

MFP7

O

PF.4

MFP2

O

PE.8

MFP7

O

PE.14

MFP3

O

PC.5

MFP8

O

PC.1

MFP8

O

PF.5

MFP4

I

PD.9

MFP4

I

PC.2

MFP8

I

PF.4

MFP4

O

PD.8

MFP4

O

PC.3

MFP8

O

PC.9

MFP7

I

PE.11

MFP7

I

PF.13

MFP7

I

PC.2

MFP11

I

PD.0

MFP5

I

PE.0

MFP7

I

PB.14

MFP7

I

PC.10

MFP7

O

PE.10

MFP7

O

PF.12

MFP7

O

PC.3

MFP11

O

PD.1

MFP5

O

PE.1

MFP7

O

PB.15

MFP7

O

PD.2

MFP5

I

PH.9

MFP7

I

PB.12

MFP7

I

Page 43 of 178

Description

UART2 data transmitter output pin.

UART2 clear to Send input pin.

UART2 request to Send output pin.

UART3 data receiver input pin.

UART3 data transmitter output pin.

UART3 clear to Send input pin.

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETUART3_RXD

GPIO

M471V/M471K/M471C SeriesGroup

Pin Name

UART3_nRTS

UART4_RXD

GPIO

MFP

Type

PD.3

MFP5

O

PH.8

MFP7

O

PB.13

MFP7

O

PF.6

MFP6

I

PC.6

MFP5

I

PA.2

MFP7

I

PC.4

MFP11

I

PI.3

MFP11

I

PA.13

MFP3

I

PI.5

MFP7

I

PH.11

MFP7

I

PB.10

MFP6

I

PF.7

MFP6

O

PC.7

MFP5

O

PA.3

MFP7

O

PC.5

MFP11

O

PI.2

MFP11

O

PA.12

MFP3

O

PI.4

MFP7

O

PH.10

MFP7

O

PB.11

MFP6

O

PC.8

MFP5

I

PE.1

MFP9

I

PE.13

MFP5

O

PE.0

MFP9

O

PB.4

MFP7

I

PI.1

MFP6

I

PF.10

MFP6

I

PF.13

MFP6

I

PA.4

MFP8

I

PI.3

MFP6

I

PE.6

MFP8

I

Description

UART3 request to Send output pin.

UART4 data receiver input pin.

UART4

M471V/M471K/M471C SERIES DATASHEETUART4_TXD

UART4_nCTS

UART4 clear to Send input pin.

UART4_nRTS

UART5

UART5_RXD

Dec. 22, 2022

UART4 data transmitter output pin.

UART4 request to Send output pin.

Page 44 of 178

UART5 data receiver input pin.

Rev 1.40

M471V/M471K/M471C SeriesGroup

Pin Name

GPIO

MFP

Type

PB.5

MFP7

O

PI.0

MFP6

O

PF.11

MFP6

O

PF.12

MFP6

O

PA.5

MFP8

O

PI.2

MFP6

O

PE.7

MFP8

O

PB.2

MFP7

I

PF.8

MFP6

I

PB.3

MFP7

O

PF.9

MFP6

O

X32_IN

PF.5

MFP10

I

External 32.768 kHz crystal input pin.

X32_OUT

PF.4

MFP10

O

External 32.768 kHz crystal output pin.

XT1_IN

PF.3

MFP10

I

External 4~24 MHz (high speed) crystal
input pin.

XT1_OUT

PF.2

MFP10

O

External 4~24 MHz (high speed) crystal
output pin.

Page 45 of 178

Rev 1.40

UART5_TXD

UART5_nCTS

Description

UART5 data transmitter output pin.

UART5 clear to Send input pin.

UART5_nRTS

UART5 request to Send output pin.

X32

XT1

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

M471V/M471K/M471C Series
4.3.2

Multi-function Summary Table Sorted by GPIO
Pin Name

Type

MFP

Description

PA.0

I/O

MFP0

General purpose digital I/O pin.

SPI0_MOSI

I/O

MFP4

SPI0 MOSI (Master Out, Slave In) pin.

UART0_RXDI

MFP7

UART0 data receiver input pin.

PA.0 UART1_nRTS

O

MFP8

UART1 request to Send output pin.

BPWM0_CH0

I/O

MFP12

BPWM0 channel 0 output/capture input.

EPWM0_CH5

I/O

MFP13

EPWM0 channel 5 output/capture input.

DAC0_STI

MFP15

DAC0 external trigger input.

PA.1

I/O

MFP0

General purpose digital I/O pin.

SPI0_MISO

I/O

MFP4

SPI0 MISO (Master In, Slave Out) pin.

UART0_TXD

O

MFP7

UART0 data transmitter output pin.

UART1_nCTS

I

MFP8

UART1 clear to Send input pin.

BPWM0_CH1

I/O

MFP12

BPWM0 channel 1 output/capture input.

EPWM0_CH4

I/O

MFP13

EPWM0 channel 4 output/capture input.

PA.2

I/O

MFP0

General purpose digital I/O pin.

SPI0_CLK

I/O

MFP4

SPI0 serial clock pin.

UART4_RXDI

MFP7

UART4 data receiver input pin.

UART1_RXDI

MFP8

UART1 data receiver input pin.

I/O

MFP9

I2C1 data input/output pin.

I2C0_SMBSUS

O

MFP10

I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)

BPWM0_CH2

I/O

MFP12

BPWM0 channel 2 output/capture input.

EPWM0_CH3

I/O

MFP13

EPWM0 channel 3 output/capture input.

CIR0_RXDI

MFP15

CIR0 data receiver input pin.

PA.3

I/O

MFP0

General purpose digital I/O pin.

SPI0_SSI/O

MFP4

SPI0 slave select pin.

UART4_TXD

O

MFP7

UART4 data transmitter output pin.

UART1_TXDO

MFP8UART1 data transmitter output pin.

I/O

MFP9

I2C1 clock pin.

I2C0_SMBAL

O

MFP10

I2C0 SMBus SMBALTER pin

CLKO

O

MFP11

Clock OutBPWM0_CH3

I/O

MFP12

BPWM0 channel 3 output/capture input.

EPWM0_CH2

I/O

MFP13

EPWM0 channel 2 output/capture input.

PA.1

M471V/M471K/M471C SERIES DATASHEET

PA.2 I2C1_SDA

PA.3 I2C1_SCL

Dec. 22, 2022

Page 46 of 178

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

EPWM1_BRAKE1

I

MFP15

EPWM1 Brake 1 input pin.

PA.4

I/O

MFP0

General purpose digital I/O pin.

SPI0_I2SMCLK

I/O

MFP4

SPI0 I2S master clock output pin

UART0_nRTS

O

MFP7

UART0 request to Send output pin.

UART5_RXDI

MFP8

UART5 data receiver input pin.

I2C0_SDA

I/O

MFP9

I2C0 data input/output pin.

UART0_RXD

I

MFP11

UART0 data receiver input pin.

BPWM0_CH4

I/O

MFP12

BPWM0 channel 4 output/capture input.

EPWM0_CH1

I/O

MFP13

EPWM0 channel 1 output/capture input.

PA.5

I/O

MFP0

General purpose digital I/O pin.

SPI1_I2SMCLK

I/O

MFP4

SPI1 I2S master clock output pin

UART0_nCTS

I

MFP7

UART0 clear to Send input pin.

UART5_TXD

O

MFP8

UART5 data transmitter output pin.

I2C0_SCL

I/O

MFP9

I2C0 clock pin.

UART0_TXD

O

MFP11

UART0 data transmitter output pin.

BPWM0_CH5

I/O

MFP12

BPWM0 channel 5 output/capture input.

EPWM0_CH0

I/O

MFP13

EPWM0 channel 0 output/capture input.

PA.6

I/O

MFP0

General purpose digital I/O pin.

SPI1_SSI/O

MFP4

SPI1 slave select pin.

UART0_RXDI

MFP7

UART0 data receiver input pin.

I2C1_SDA

I/O

MFP8

I2C1 data input/output pin.

PA.6 EPWM1_CH5

I/O

MFP11

EPWM1 channel 5 output/capture input.

BPWM1_CH3

I/O

MFP12

BPWM1 channel 3 output/capture input.

ACMP1_WLAT

I

MFP13

Analog comparator 1 window latch input pin

TM3

I/O

MFP14

Timer3 event counter input/toggle output pin.

INT0

I

MFP15

External interrupt 0 input pin.

PA.7

I/O

MFP0

General purpose digital I/O pin.

SPI1_CLK

I/O

MFP4

SPI1 serial clock pin.

UART0_TXD

O

MFP7

UART0 data transmitter output pin.

I2C1_SCL

I/O

MFP8

I2C1 clock pin.

EPWM1_CH4

I/O

MFP11

EPWM1 channel 4 output/capture input.

BPWM1_CH2

I/O

MFP12

BPWM1 channel 2 output/capture input.

PA.4

PA.5

Dec. 22, 2022

Page 47 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

PA.7

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

ACMP0_WLAT

I

MFP13

Analog comparator 0 window latch input pin

TM2

I/O

MFP14

Timer2 event counter input/toggle output pin.

INT1

I

MFP15

External interrupt 1 input pin.

PA.8

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH20

A

MFP1

EADC0 channel 20 analog input.

UART1_RXDI

MFP7

UART1 data receiver input pin.

BPWM0_CH3

I/O

MFP9

BPWM0 channel 3 output/capture input.

TM3_EXT

I/O

MFP13

Timer3 external capture input/toggle output pin.

INT4

I

MFP15

External interrupt 4 input pin.

PA.9

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH21

A

MFP1

EADC0 channel 21 analog input.

PA.9 UART1_TXD

O

MFP7

UART1 data transmitter output pin.

BPWM0_CH2

I/O

MFP9

BPWM0 channel 2 output/capture input.

TM2_EXT

I/O

MFP13

Timer2 external capture input/toggle output pin.

PA.10

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH22

A

MFP1

EADC0 channel 22 analog input.

ACMP1_P0

A

MFP1

Analog comparator 1 positive input 0 pin.

BPWM0_CH1

I/O

MFP9

BPWM0 channel 1 output/capture input.

TM1_EXT

I/O

MFP13

Timer1 external capture input/toggle output pin.

DAC0_STI

MFP14

DAC0 external trigger input.

PA.11

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH23

A

MFP1

EADC0 channel 23 analog input.

ACMP0_P0

A

MFP1

Analog comparator 0 positive input 0 pin.

BPWM0_CH0

I/O

MFP9

BPWM0 channel 0 output/capture input.

EPWM0_SYNC_OUT

O

MFP10

EPWM0 counter synchronous trigger output pin.

TM0_EXT

I/O

MFP13

Timer0 external capture input/toggle output pin.

PA.12

I/O

MFP0

General purpose digital I/O pin.

UART4_TXD

O

MFP3

UART4 data transmitter output pin.

I2C1_SCL

I/O

MFP4

I2C1 clock pin.

BPWM1_CH2

I/O

MFP11

BPWM1 channel 2 output/capture input.

PA.13

I/O

MFP0

General purpose digital I/O pin.

UART4_RXDI

MFP3

UART4 data receiver input pin.

PA.8

M471V/M471K/M471C SERIES DATASHEET

PA.10

PA.11

PA.12

PA.13

Dec. 22, 2022

Page 48 of 178

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

I2C1_SDA

I/O

MFP4

I2C1 data input/output pin.

BPWM1_CH3

I/O

MFP11

BPWM1 channel 3 output/capture input.

PA.14

I/O

MFP0

General purpose digital I/O pin.

PA.14 UART0_TXD

O

MFP3

UART0 data transmitter output pin.

BPWM1_CH4

I/O

MFP11

BPWM1 channel 4 output/capture input.

PA.15

I/O

MFP0

General purpose digital I/O pin.

UART0_RXDI

MFP3

UART0 data receiver input pin.

BPWM1_CH5

I/O

MFP11

BPWM1 channel 5 output/capture input.

EPWM0_SYNC_IN

I

MFP12

EPWM0 counter synchronous trigger input pin.

PB.0

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH0

A

MFP1

EADC0 channel 0 analog input.

UART2_RXDI

MFP7

UART2 data receiver input pin.

SPI0_I2SMCLK

I/O

MFP8

SPI0 I2S master clock output pin

I2C1_SDA

I/O

MFP9

I2C1 data input/output pin.

EPWM0_CH5

I/O

MFP11

EPWM0 channel 5 output/capture input.

EPWM1_CH5

I/O

MFP12

EPWM1 channel 5 output/capture input.

EPWM0_BRAKE1

I

MFP13

EPWM0 Brake 1 input pin.

PB.1

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH1

A

MFP1

EADC0 channel 1 analog input.

SPI1_I2SMCLK

I/O

MFP5

SPI1 I2S master clock output pin

UART2_TXD

O

MFP7

UART2 data transmitter output pin.

I2C1_SCL

I/O

MFP9

I2C1 clock pin.

EPWM0_CH4

I/O

MFP11

EPWM0 channel 4 output/capture input.

EPWM1_CH4

I/O

MFP12

EPWM1 channel 4 output/capture input.

EPWM0_BRAKE0

I

MFP13

EPWM0 Brake 0 input pin.

PB.2

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH2

A

MFP1

EADC0 channel 2 analog input.

ACMP0_P1

A

MFP1

Analog comparator 0 positive input 1 pin.

I/O

MFP5

SPI1 slave select pin.

UART1_RXDI

MFP6

UART1 data receiver input pin.

UART5_nCTS

I

MFP7

UART5 clear to Send input pin.

EPWM0_CH3

I/O

MFP11

EPWM0 channel 3 output/capture input.

PA.15

PB.0

M471V/M471K/M471C SERIES DATASHEET

PB.1

PB.2 SPI1_SS

Dec. 22, 2022

Page 49 of 178

Rev 1.40

M471V/M471K/M471C Series

M471V/M471K/M471C SERIES DATASHEETPin Name

Type

MFP

Description

I2C1_SDA

I/O

MFP12

I2C1 data input/output pin.

TM3

I/O

MFP14

Timer3 event counter input/toggle output pin.

INT3

I

MFP15

External interrupt 3 input pin.

PB.3

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH3

A

MFP1

EADC0 channel 3 analog input.

ACMP0_NA

MFP1

Analog comparator 0 negative input pin.

SPI1_CLK

I/O

MFP5

SPI1 serial clock pin.

UART1_TXD

O

MFP6

UART1 data transmitter output pin.

PB.3 UART5_nRTS

O

MFP7

UART5 request to Send output pin.

EPWM0_CH2

I/O

MFP11

EPWM0 channel 2 output/capture input.

I2C1_SCL

I/O

MFP12

I2C1 clock pin.

EPWM0_BRAKE0

I

MFP13

EPWM0 Brake 0 input pin.

TM2

I/O

MFP14

Timer2 event counter input/toggle output pin.

INT2

I

MFP15

External interrupt 2 input pin.

PB.4

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH4

A

MFP1

EADC0 channel 4 analog input.

ACMP1_P1

A

MFP1

Analog comparator 1 positive input 1 pin.

SPI1_MOSI

I/O

MFP5

SPI1 MOSI (Master Out, Slave In) pin.

I2C0_SDA

I/O

MFP6

I2C0 data input/output pin.

UART5_RXDI

MFP7

UART5 data receiver input pin.

EPWM0_CH1

I/O

MFP11

EPWM0 channel 1 output/capture input.

UART2_RXD

I

MFP12

UART2 data receiver input pin.

TM1

I/O

MFP14

Timer1 event counter input/toggle output pin.

INT1

I

MFP15

External interrupt 1 input pin.

PB.5

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH5

A

MFP1

EADC0 channel 5 analog input.

ACMP1_NA

MFP1

Analog comparator 1 negative input pin.

SPI1_MISO

I/O

MFP5

SPI1 MISO (Master In, Slave Out) pin.

I2C0_SCL

I/O

MFP6

I2C0 clock pin.

UART5_TXD

O

MFP7

UART5 data transmitter output pin.

EPWM0_CH0

I/O

MFP11

EPWM0 channel 0 output/capture input.

UART2_TXD

O

MFP12

UART2 data transmitter output pin.

PB.4

PB.5

Dec. 22, 2022

Page 50 of 178

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

TM0

I/O

MFP14

Timer0 event counter input/toggle output pin.

INT0

I

MFP15

External interrupt 0 input pin.

PB.6

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH6

A

MFP1

EADC0 channel 6 analog input.

UART1_RXDI

MFP6

UART1 data receiver input pin.

BPWM1_CH5

I/O

MFP10

BPWM1 channel 5 output/capture input.

EPWM1_BRAKE1

I

MFP11

EPWM1 Brake 1 input pin.

EPWM1_CH5

I/O

MFP12

EPWM1 channel 5 output/capture input.

INT4

I

MFP13

External interrupt 4 input pin.

ACMP1_OO

MFP15

Analog comparator 1 output pin.

PB.7

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH7

A

MFP1

EADC0 channel 7 analog input.

UART1_TXD

O

MFP6

UART1 data transmitter output pin.

BPWM1_CH4

I/O

MFP10

BPWM1 channel 4 output/capture input.

EPWM1_BRAKE0

I

MFP11

EPWM1 Brake 0 input pin.

EPWM1_CH4

I/O

MFP12

EPWM1 channel 4 output/capture input.

INT5

I

MFP13

External interrupt 5 input pin.

ACMP0_OO

MFP15

Analog comparator 0 output pin.

PB.8

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH8

A

MFP1

EADC0 channel 8 analog input.

UART0_RXDI

MFP5

UART0 data receiver input pin.

UART1_nRTS

O

MFP6

UART1 request to Send output pin.

I2C1_SMBSUS

O

MFP7

I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)

I2C0_SDA

I/O

MFP9

I2C0 data input/output pin.

BPWM1_CH3

I/O

MFP10

BPWM1 channel 3 output/capture input.

INT6

I

MFP13

External interrupt 6 input pin.

PB.9

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH9

A

MFP1

EADC0 channel 9 analog input.

UART0_TXD

O

MFP5

UART0 data transmitter output pin.

UART1_nCTS

I

MFP6

UART1 clear to Send input pin.

I2C1_SMBAL

O

MFP7

I2C1 SMBus SMBALTER pin

I2C0_SCL

I/O

MFP9

I2C0 clock pin.

PB.6

PB.7

PB.9

Dec. 22, 2022

Page 51 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

PB.8

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

BPWM1_CH2

I/O

MFP10

BPWM1 channel 2 output/capture input.

INT7

I

MFP13

External interrupt 7 input pin.

PB.10

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH10

A

MFP1

EADC0 channel 10 analog input.

UART0_nRTS

O

MFP5

UART0 request to Send output pin.

UART4_RXDI

MFP6

UART4 data receiver input pin.

I2C1_SDA

I/O

MFP7

I2C1 data input/output pin.

BPWM1_CH1

I/O

MFP10

BPWM1 channel 1 output/capture input.

PB.11

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH11

A

MFP1

EADC0 channel 11 analog input.

UART0_nCTS

I

MFP5

UART0 clear to Send input pin.

PB.11 UART4_TXD

O

MFP6

UART4 data transmitter output pin.

I2C1_SCL

I/O

MFP7

I2C1 clock pin.

SPI0_I2SMCLK

I/O

MFP9

SPI0 I2S master clock output pin

BPWM1_CH0

I/O

MFP10

BPWM1 channel 0 output/capture input.

PB.12

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH12

A

MFP1

EADC0 channel 12 analog input.

DAC0_OUTA

MFP1

DAC0 channel analog output.

ACMP0_P2

A

MFP1

Analog comparator 0 positive input 2 pin.

ACMP1_P2

A

MFP1

Analog comparator 1 positive input 2 pin.

SPI0_MOSI

I/O

MFP4

SPI0 MOSI (Master Out, Slave In) pin.

UART0_RXDI

MFP6

UART0 data receiver input pin.

UART3_nCTS

I

MFP7

UART3 clear to Send input pin.

EPWM1_CH3

I/O

MFP11

EPWM1 channel 3 output/capture input.

TM3_EXT

I/O

MFP13

Timer3 external capture input/toggle output pin.

PB.13

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH13

A

MFP1

EADC0 channel 13 analog input.

ACMP0_P3

A

MFP1

Analog comparator 0 positive input 3 pin.

PB.13 ACMP1_P3

A

MFP1

Analog comparator 1 positive input 3 pin.

SPI0_MISO

I/O

MFP4

SPI0 MISO (Master In, Slave Out) pin.

UART0_TXD

O

MFP6

UART0 data transmitter output pin.

UART3_nRTS

O

MFP7

UART3 request to Send output pin.

PB.10

M471V/M471K/M471C SERIES DATASHEET

PB.12

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M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

EPWM1_CH2

I/O

MFP11

EPWM1 channel 2 output/capture input.

TM2_EXT

I/O

MFP13

Timer2 external capture input/toggle output pin.

PB.14

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH14

A

MFP1

EADC0 channel 14 analog input.

SPI0_CLK

I/O

MFP4

SPI0 serial clock pin.

UART0_nRTS

O

MFP6

UART0 request to Send output pin.

UART3_RXDI

MFP7

UART3 data receiver input pin.

EPWM1_CH1

I/O

MFP11

EPWM1 channel 1 output/capture input.

TM1_EXT

I/O

MFP13

Timer1 external capture input/toggle output pin.

CLKO

O

MFP14

Clock Out

PB.15

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH15

A

MFP1

EADC0 channel 15 analog input.

SPI0_SSI/O

MFP4

SPI0 slave select pin.

UART0_nCTS

I

MFP6

UART0 clear to Send input pin.

UART3_TXD

O

MFP7

UART3 data transmitter output pin.

EPWM0_BRAKE1

I

MFP10

EPWM0 Brake 1 input pin.

EPWM1_CH0

I/O

MFP11

EPWM1 channel 0 output/capture input.

TM0_EXT

I/O

MFP13

Timer0 external capture input/toggle output pin.

PC.0

I/O

MFP0

General purpose digital I/O pin.

SPI1_SSI/O

MFP7

SPI1 slave select pin.

UART2_RXDI

MFP8

UART2 data receiver input pin.

I2C0_SDA

I/O

MFP9

I2C0 data input/output pin.

EPWM1_CH5

I/O

MFP12

EPWM1 channel 5 output/capture input.

ACMP1_OO

MFP14

Analog comparator 1 output pin.

PC.1

I/O

MFP0

General purpose digital I/O pin.

SPI1_CLK

I/O

MFP7

SPI1 serial clock pin.

UART2_TXDO

MFP8UART2 data transmitter output pin.

I/O

MFP9

I2C0 clock pin.

EPWM1_CH4

I/O

MFP12

EPWM1 channel 4 output/capture input.

ACMP0_OO

MFP14

Analog comparator 0 output pin.

EADC0_STI

MFP15

EADC0 external trigger input.

I/O

MFP0

General purpose digital I/O pin.

PB.14

PB.15

PC.1 I2C0_SCL

PC.2 PC.2

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M471V/M471K/M471C SERIES DATASHEET

PC.0

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

SPI1_MOSI

I/O

MFP7

SPI1 MOSI (Master Out, Slave In) pin.

UART2_nCTS

I

MFP8

UART2 clear to Send input pin.

I2C0_SMBSUS

O

MFP9

I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)

UART3_RXD

I

MFP11

UART3 data receiver input pin.

EPWM1_CH3

I/O

MFP12

EPWM1 channel 3 output/capture input.

PC.3

I/O

MFP0

General purpose digital I/O pin.

SPI1_MISO

I/O

MFP7

SPI1 MISO (Master In, Slave Out) pin.

UART2_nRTS

O

MFP8

UART2 request to Send output pin.

I2C0_SMBAL

O

MFP9

I2C0 SMBus SMBALTER pin

UART3_TXD

O

MFP11

UART3 data transmitter output pin.

EPWM1_CH2

I/O

MFP12

EPWM1 channel 2 output/capture input.

PC.4

I/O

MFP0

General purpose digital I/O pin.

SPI1_I2SMCLK

I/O

MFP7

SPI1 I2S master clock output pin

UART2_RXDI

MFP8

UART2 data receiver input pin.

I2C1_SDA

I/O

MFP9

I2C1 data input/output pin.

UART4_RXD

I

MFP11

UART4 data receiver input pin.

EPWM1_CH1

I/O

MFP12

EPWM1 channel 1 output/capture input.

PC.5

I/O

MFP0

General purpose digital I/O pin.

UART2_TXDO

MFP8UART2 data transmitter output pin.

I/O

MFP9

I2C1 clock pin.

UART4_TXD

O

MFP11

UART4 data transmitter output pin.

EPWM1_CH0

I/O

MFP12

EPWM1 channel 0 output/capture input.

PC.6

I/O

MFP0

General purpose digital I/O pin.

SPI1_MOSI

I/O

MFP4

SPI1 MOSI (Master Out, Slave In) pin.

UART4_RXDI

MFP5

UART4 data receiver input pin.

UART0_nRTS

O

MFP7

UART0 request to Send output pin.

I2C1_SMBSUS

O

MFP8

I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)

EPWM1_CH3

I/O

MFP11

EPWM1 channel 3 output/capture input.

BPWM1_CH1

I/O

MFP12

BPWM1 channel 1 output/capture input.

TRACE_DATA2

O

MFP13

ETM Trace Data 2 output pin

TM1

I/O

MFP14

Timer1 event counter input/toggle output pin.

INT2

I

MFP15

External interrupt 2 input pin.

PC.3

PC.4

M471V/M471K/M471C SERIES DATASHEET

PC.5 I2C1_SCL

PC.6

Dec. 22, 2022

Page 54 of 178

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

PC.7

I/O

MFP0

General purpose digital I/O pin.

SPI1_MISO

I/O

MFP4

SPI1 MISO (Master In, Slave Out) pin.

UART4_TXD

O

MFP5

UART4 data transmitter output pin.

UART0_nCTS

I

MFP7

UART0 clear to Send input pin.

I2C1_SMBAL

O

MFP8

I2C1 SMBus SMBALTER pin

EPWM1_CH2

I/O

MFP11

EPWM1 channel 2 output/capture input.

BPWM1_CH0

I/O

MFP12

BPWM1 channel 0 output/capture input.

TRACE_DATA3

O

MFP13

ETM Trace Data 3 output pin

TM0

I/O

MFP14

Timer0 event counter input/toggle output pin.

INT3

I

MFP15

External interrupt 3 input pin.

PC.8

I/O

MFP0

General purpose digital I/O pin.

I2C0_SDA

I/O

MFP4

I2C0 data input/output pin.

UART4_nCTS

I

MFP5

UART4 clear to Send input pin.

UART1_RXDI

MFP8

UART1 data receiver input pin.

EPWM1_CH1

I/O

MFP11

EPWM1 channel 1 output/capture input.

BPWM1_CH4

I/O

MFP12

BPWM1 channel 4 output/capture input.

PC.9

I/O

MFP0

General purpose digital I/O pin.

PC.9 UART3_RXD

I

MFP7

UART3 data receiver input pin.

EPWM1_CH3

I/O

MFP12

EPWM1 channel 3 output/capture input.

PC.10

I/O

MFP0

General purpose digital I/O pin.

PC.10 UART3_TXD

O

MFP7

UART3 data transmitter output pin.

EPWM1_CH2

I/O

MFP12

EPWM1 channel 2 output/capture input.

PC.11

I/O

MFP0

General purpose digital I/O pin.

UART0_RXDI

MFP3

UART0 data receiver input pin.

I/O

MFP4

I2C0 data input/output pin.

EPWM1_CH1

I/O

MFP12

EPWM1 channel 1 output/capture input.

ACMP1_OO

MFP14

Analog comparator 1 output pin.

PC.12

I/O

MFP0

General purpose digital I/O pin.

UART0_TXD

O

MFP3

UART0 data transmitter output pin.

I/O

MFP4

I2C0 clock pin.

EPWM1_CH0

I/O

MFP12

EPWM1 channel 0 output/capture input.

ACMP0_OO

MFP14

Analog comparator 0 output pin.

PC.7

PC.8

PC.12 I2C0_SCL

Dec. 22, 2022

Page 55 of 178

M471V/M471K/M471C SERIES DATASHEET

PC.11 I2C0_SDA

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

PC.13

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH19

A

MFP1

EADC0 channel 19 analog input.

UART2_TXD

O

MFP7

UART2 data transmitter output pin.

BPWM0_CH4

I/O

MFP9

BPWM0 channel 4 output/capture input.

CLKO

O

MFP13

Clock Out

EADC0_STI

MFP14

EADC0 external trigger input.

PC.14

I/O

MFP0

General purpose digital I/O pin.

SPI0_I2SMCLK

I/O

MFP4

SPI0 I2S master clock output pin

I

MFP10

CIR0 data receiver input pin.

EPWM0_SYNC_IN

I

MFP11

EPWM0 counter synchronous trigger input pin.

TM1

I/O

MFP13

Timer1 event counter input/toggle output pin.

PD.0

I/O

MFP0

General purpose digital I/O pin.

SPI0_MOSI

I/O

MFP4

SPI0 MOSI (Master Out, Slave In) pin.

UART3_RXDI

MFP5

UART3 data receiver input pin.

TM2

I/O

MFP14

Timer2 event counter input/toggle output pin.

PD.1

I/O

MFP0

General purpose digital I/O pin.

PD.1 SPI0_MISO

I/O

MFP4

SPI0 MISO (Master In, Slave Out) pin.

UART3_TXD

O

MFP5

UART3 data transmitter output pin.

PD.2

I/O

MFP0

General purpose digital I/O pin.

SPI0_CLK

I/O

MFP4

SPI0 serial clock pin.

UART3_nCTS

I

MFP5

UART3 clear to Send input pin.

UART0_RXDI

MFP9

UART0 data receiver input pin.

PD.3

I/O

MFP0

General purpose digital I/O pin.

SPI0_SSI/O

MFP4

SPI0 slave select pin.

UART3_nRTS

O

MFP5

UART3 request to Send output pin.

UART0_TXD

O

MFP9

UART0 data transmitter output pin.

PD.4

I/O

MFP0

General purpose digital I/O pin.

PD.4 I2C1_SDA

I/O

MFP4

I2C1 data input/output pin.

SPI1_SSI/O

MFP5

SPI1 slave select pin.

PD.5

I/O

MFP0

General purpose digital I/O pin.

PD.5 I2C1_SCL

I/O

MFP4

I2C1 clock pin.

SPI1_CLK

I/O

MFP5

SPI1 serial clock pin.

PC.13

PC.14 CIR0_RXD

PD.0

M471V/M471K/M471C SERIES DATASHEET

PD.2

PD.3

Dec. 22, 2022

Page 56 of 178

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

PD.6

I/O

MFP0

General purpose digital I/O pin.

UART1_RXDI

MFP3

UART1 data receiver input pin.

I2C0_SDA

I/O

MFP4

I2C0 data input/output pin.

SPI1_MOSI

I/O

MFP5

SPI1 MOSI (Master Out, Slave In) pin.

PD.7

I/O

MFP0

General purpose digital I/O pin.

UART1_TXD

O

MFP3

UART1 data transmitter output pin.

I2C0_SCL

I/O

MFP4

I2C0 clock pin.

SPI1_MISO

I/O

MFP5

SPI1 MISO (Master In, Slave Out) pin.

PD.8

I/O

MFP0

General purpose digital I/O pin.

UART2_nRTS

O

MFP4

UART2 request to Send output pin.

PD.9

I/O

MFP0

General purpose digital I/O pin.

UART2_nCTS

I

MFP4

UART2 clear to Send input pin.

PD.10

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH16

A

MFP1

EADC0 channel 16 analog input.

UART1_RXDI

MFP3

UART1 data receiver input pin.

INT7

I

MFP15

External interrupt 7 input pin.

PD.11

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH17

A

MFP1

EADC0 channel 17 analog input.

UART1_TXD

O

MFP3

UART1 data transmitter output pin.

INT6

I

MFP15

External interrupt 6 input pin.

PD.12

I/O

MFP0

General purpose digital I/O pin.

EADC0_CH18

A

MFP1

EADC0 channel 18 analog input.

UART2_RXDI

MFP7

UART2 data receiver input pin.

PD.12 BPWM0_CH5

I/O

MFP9

BPWM0 channel 5 output/capture input.

CLKO

O

MFP13

Clock Out

EADC0_STI

MFP14

EADC0 external trigger input.

INT5

I

MFP15

External interrupt 5 input pin.

PD.13

I/O

MFP0

General purpose digital I/O pin.

PD.13 SPI0_I2SMCLK

I/O

MFP4

SPI0 I2S master clock output pin

SPI1_I2SMCLK

I/O

MFP5

SPI1 I2S master clock output pin

PD.14

I/O

MFP0

General purpose digital I/O pin.

SPI0_I2SMCLK

I/O

MFP5

SPI0 I2S master clock output pin

PD.6

PD.7

PD.8

PD.9

PD.10

M471V/M471K/M471C SERIES DATASHEET

PD.11

PD.14

Dec. 22, 2022

Page 57 of 178

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M471V/M471K/M471C Series

M471V/M471K/M471C SERIES DATASHEETPin Name

Type

MFP

Description

EPWM0_CH4

I/O

MFP11

EPWM0 channel 4 output/capture input.

PD.15

I/O

MFP0

General purpose digital I/O pin.

EPWM0_CH5

I/O

MFP12

EPWM0 channel 5 output/capture input.

PD.15 TRACE_CLK

O

MFP13

ETM Trace Clock output pin

TM3

I/O

MFP14

Timer3 event counter input/toggle output pin.

INT1

I

MFP15

External interrupt 1 input pin.

PE.0

I/O

MFP0

General purpose digital I/O pin.

SPI1_MOSI

I/O

MFP6

SPI1 MOSI (Master Out, Slave In) pin.

PE.0 UART3_RXD

I

MFP7

UART3 data receiver input pin.

I2C1_SDA

I/O

MFP8

I2C1 data input/output pin.

UART4_nRTS

O

MFP9

UART4 request to Send output pin.

PE.1

I/O

MFP0

General purpose digital I/O pin.

SPI1_MISO

I/O

MFP6

SPI1 MISO (Master In, Slave Out) pin.

PE.1 UART3_TXD

O

MFP7

UART3 data transmitter output pin.

I2C1_SCL

I/O

MFP8

I2C1 clock pin.

UART4_nCTS

I

MFP9

UART4 clear to Send input pin.

PE.2

I/O

MFP0

General purpose digital I/O pin.

PE.2 EPWM0_CH5

I/O

MFP12

EPWM0 channel 5 output/capture input.

BPWM0_CH0

I/O

MFP13

BPWM0 channel 0 output/capture input.

PE.3

I/O

MFP0

General purpose digital I/O pin.

PE.3 EPWM0_CH4

I/O

MFP12

EPWM0 channel 4 output/capture input.

BPWM0_CH1

I/O

MFP13

BPWM0 channel 1 output/capture input.

PE.4

I/O

MFP0

General purpose digital I/O pin.

PE.4 EPWM0_CH3

I/O

MFP12

EPWM0 channel 3 output/capture input.

BPWM0_CH2

I/O

MFP13

BPWM0 channel 2 output/capture input.

PE.5

I/O

MFP0

General purpose digital I/O pin.

PE.5 EPWM0_CH2

I/O

MFP12

EPWM0 channel 2 output/capture input.

BPWM0_CH3

I/O

MFP13

BPWM0 channel 3 output/capture input.

PE.6

I/O

MFP0

General purpose digital I/O pin.

UART5_RXDI

MFP8

UART5 data receiver input pin.

EPWM0_CH1

I/O

MFP12

EPWM0 channel 1 output/capture input.

BPWM0_CH4

I/O

MFP13

BPWM0 channel 4 output/capture input.

PE.6

Dec. 22, 2022

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Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

PE.7

I/O

MFP0

General purpose digital I/O pin.

UART5_TXD

O

MFP8

UART5 data transmitter output pin.

EPWM0_CH0

I/O

MFP12

EPWM0 channel 0 output/capture input.

BPWM0_CH5

I/O

MFP13

BPWM0 channel 5 output/capture input.

PE.8

I/O

MFP0

General purpose digital I/O pin.

UART2_TXD

O

MFP7

UART2 data transmitter output pin.

PE.8 EPWM0_CH0

I/O

MFP10

EPWM0 channel 0 output/capture input.

EPWM0_BRAKE0

I

MFP11

EPWM0 Brake 0 input pin.

TRACE_DATA3

O

MFP14

ETM Trace Data 3 output pin

PE.9

I/O

MFP0

General purpose digital I/O pin.

UART2_RXDI

MFP7

UART2 data receiver input pin.

PE.9 EPWM0_CH1

I/O

MFP10

EPWM0 channel 1 output/capture input.

EPWM0_BRAKE1

I

MFP11

EPWM0 Brake 1 input pin.

TRACE_DATA2

O

MFP14

ETM Trace Data 2 output pin

PE.10

I/O

MFP0

General purpose digital I/O pin.

UART3_TXD

O

MFP7

UART3 data transmitter output pin.

PE.10 EPWM0_CH2

I/O

MFP10

EPWM0 channel 2 output/capture input.

EPWM1_BRAKE0

I

MFP11

EPWM1 Brake 0 input pin.

TRACE_DATA1

O

MFP14

ETM Trace Data 1 output pin

PE.11

I/O

MFP0

General purpose digital I/O pin.

UART3_RXDI

MFP7

UART3 data receiver input pin.

UART1_nCTS

I

MFP8

UART1 clear to Send input pin.

EPWM0_CH3

I/O

MFP10

EPWM0 channel 3 output/capture input.

EPWM1_BRAKE1

I

MFP11

EPWM1 Brake 1 input pin.

TRACE_DATA0

O

MFP14

ETM Trace Data 0 output pin

PE.12

I/O

MFP0

General purpose digital I/O pin.

UART1_nRTS

O

MFP8

UART1 request to Send output pin.

EPWM0_CH4

I/O

MFP10

EPWM0 channel 4 output/capture input.

TRACE_CLK

O

MFP14

ETM Trace Clock output pin

PE.13

I/O

MFP0

General purpose digital I/O pin.

I/O

MFP4

I2C0 clock pin.

O

MFP5

UART4 request to Send output pin.

PE.7

M471V/M471K/M471C SERIES DATASHEET

PE.11

PE.12

PE.13 I2C0_SCL
UART4_nRTS

Dec. 22, 2022

Page 59 of 178

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

UART1_TXDO

MFP8UART1 data transmitter output pin.

EPWM0_CH5

I/O

MFP10

EPWM0 channel 5 output/capture input.

EPWM1_CH0

I/O

MFP11

EPWM1 channel 0 output/capture input.

BPWM1_CH5

I/O

MFP12

BPWM1 channel 5 output/capture input.

PE.14

I/O

MFP0

General purpose digital I/O pin.

UART2_TXD

O

MFP3

UART2 data transmitter output pin.

PE.15

I/O

MFP0

General purpose digital I/O pin.

UART2_RXDI

MFP3

UART2 data receiver input pin.

PF.0

I/O

MFP0

General purpose digital I/O pin.

UART1_TXD

O

MFP2

UART1 data transmitter output pin.

I2C1_SCL

I/O

MFP3

I2C1 clock pin.

UART0_TXD

O

MFP4

UART0 data transmitter output pin.

BPWM1_CH0

I/O

MFP12

BPWM1 channel 0 output/capture input.

ICE_DAT

I/O

MFP14

Serial wired debugger data pin.

PE.14

PE.15

PF.0

Note: It is recommended to use 100 kΩ pull-up
resistor on ICE_DAT pin.

M471V/M471K/M471C SERIES DATASHEET

PF.1

PF.1

I/O

MFP0

General purpose digital I/O pin.

UART1_RXDI

MFP2

UART1 data receiver input pin.

I2C1_SDA

I/O

MFP3

I2C1 data input/output pin.

UART0_RXDI

MFP4

UART0 data receiver input pin.

BPWM1_CH1

I/O

MFP12

BPWM1 channel 1 output/capture input.

ICE_CLKI

MFP14

Serial wired debugger clock pin.
Note: It is recommended to use 100 kΩ pull-up
resistor on ICE_CLK pin.

PF.2

PF.2

I/O

MFP0

General purpose digital I/O pin.

UART0_RXDI

MFP3

UART0 data receiver input pin.

I2C0_SDA

I/O

MFP4

I2C0 data input/output pin.

XT1_OUTO

MFP10External 4~24 MHz (high speed) crystal output pin.

BPWM1_CH1

I/O

MFP11

BPWM1 channel 1 output/capture input.

PF.3

I/O

MFP0

General purpose digital I/O pin.

UART0_TXD

O

MFP3

UART0 data transmitter output pin.

I2C0_SCL

I/O

MFP4

I2C0 clock pin.

XT1_INI

MFP10External 4~24 MHz (high speed) crystal input pin.

PF.3

Dec. 22, 2022

Page 60 of 178

Rev 1.40

M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

BPWM1_CH0

I/O

MFP11

BPWM1 channel 0 output/capture input.

PF.4

I/O

MFP0

General purpose digital I/O pin.

UART2_TXD

O

MFP2

UART2 data transmitter output pin.

UART2_nRTS

O

MFP4

UART2 request to Send output pin.

EPWM0_CH1

I/O

MFP7

EPWM0 channel 1 output/capture input.

BPWM0_CH5

I/O

MFP8

BPWM0 channel 5 output/capture input.

X32_OUTO

MFP10External 32.768 kHz crystal output pin.

PF.5

I/O

MFP0

General purpose digital I/O pin.

UART2_RXDI

MFP2

UART2 data receiver input pin.

UART2_nCTS

I

MFP4

UART2 clear to Send input pin.

EPWM0_CH0

I/O

MFP7

EPWM0 channel 0 output/capture input.

BPWM0_CH4

I/O

MFP8

BPWM0 channel 4 output/capture input.

EPWM0_SYNC_OUT

O

MFP9

EPWM0 counter synchronous trigger output pin.

X32_INI

MFP10External 32.768 kHz crystal input pin.

EADC0_STI

MFP11

EADC0 external trigger input.

PF.6

I/O

MFP0

General purpose digital I/O pin.

SPI0_MOSI

I/O

MFP5

SPI0 MOSI (Master Out, Slave In) pin.

UART4_RXDI

MFP6

UART4 data receiver input pin.

PF.7

I/O

MFP0

General purpose digital I/O pin.

SPI0_MISO

I/O

MFP5

SPI0 MISO (Master In, Slave Out) pin.

UART4_TXD

O

MFP6

UART4 data transmitter output pin.

PF.8

I/O

MFP0

General purpose digital I/O pin.

SPI0_CLK

I/O

MFP5

SPI0 serial clock pin.

UART5_nCTS

I

MFP6

UART5 clear to Send input pin.

PF.9

I/O

MFP0

General purpose digital I/O pin.

SPI0_SSI/O

MFP5

SPI0 slave select pin.

UART5_nRTS

O

MFP6

UART5 request to Send output pin.

PF.10

I/O

MFP0

General purpose digital I/O pin.

PF.10 SPI0_I2SMCLK

I/O

MFP5

SPI0 I2S master clock output pin

UART5_RXDI

MFP6

UART5 data receiver input pin.

PF.11

I/O

MFP0

General purpose digital I/O pin.

UART5_TXD

O

MFP6

UART5 data transmitter output pin.

PF.4

PF.5

PF.7

PF.8

PF.9

M471V/M471K/M471C SERIES DATASHEET

PF.6

PF.11

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M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

TM3

I/O

MFP13

Timer3 event counter input/toggle output pin.

PF.12

I/O

MFP0

General purpose digital I/O pin.

I2C0_SCL

I/O

MFP4

I2C0 clock pin.

UART5_TXD

O

MFP6

UART5 data transmitter output pin.

UART3_TXD

O

MFP7

UART3 data transmitter output pin.

UART1_TXDO

MFP8UART1 data transmitter output pin.

I2C1_SCL

I/O

MFP9

I2C1 clock pin.

EPWM0_CH2

I/O

MFP10

EPWM0 channel 2 output/capture input.

BPWM0_CH0

I/O

MFP11

BPWM0 channel 0 output/capture input.

TRACE_DATA1

O

MFP13

ETM Trace Data 1 output pin

CIR0_RXDI

MFP15

CIR0 data receiver input pin.

PF.13

I/O

MFP0

General purpose digital I/O pin.

I2C0_SDA

I/O

MFP4

I2C0 data input/output pin.

UART5_RXDI

MFP6

UART5 data receiver input pin.

UART3_RXDI

MFP7

UART3 data receiver input pin.

PF.13 UART1_RXD

I

MFP8

UART1 data receiver input pin.

I2C1_SDA

I/O

MFP9

I2C1 data input/output pin.

EPWM0_CH3

I/O

MFP10

EPWM0 channel 3 output/capture input.

BPWM0_CH1

I/O

MFP11

BPWM0 channel 1 output/capture input.

TRACE_DATA0

O

MFP13

ETM Trace Data 0 output pin

PF.14

I/O

MFP0

General purpose digital I/O pin.

EPWM1_BRAKE0

I

MFP9

EPWM1 Brake 0 input pin.

EPWM0_BRAKE0

I

MFP10

EPWM0 Brake 0 input pin.

PF.14 EPWM0_CH4

I/O

MFP12

EPWM0 channel 4 output/capture input.

CLKO

O

MFP13

Clock Out

TM3

I/O

MFP14

Timer3 event counter input/toggle output pin.

INT5

I

MFP15

External interrupt 5 input pin.

PF.15

I/O

MFP0

General purpose digital I/O pin.

EPWM0_BRAKE0

I

MFP11

EPWM0 Brake 0 input pin.

PF.15 EPWM0_CH1

I/O

MFP12

EPWM0 channel 1 output/capture input.

TM2

I/O

MFP13

Timer2 event counter input/toggle output pin.

CLKO

O

MFP14

Clock OutPF.12

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

INT4

I

MFP15

External interrupt 4 input pin.

PG.2

I/O

MFP0

General purpose digital I/O pin.

I2C0_SMBAL

O

MFP4

I2C0 SMBus SMBALTER pin

I2C1_SCL

I/O

MFP5

I2C1 clock pin.

TM0

I/O

MFP13

Timer0 event counter input/toggle output pin.

PG.3

I/O

MFP0

General purpose digital I/O pin.

I2C0_SMBSUS

O

MFP4

I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)

I2C1_SDA

I/O

MFP5

I2C1 data input/output pin.

TM1

I/O

MFP13

Timer1 event counter input/toggle output pin.

PG.4

I/O

MFP0

General purpose digital I/O pin.

TM2

I/O

MFP13

Timer2 event counter input/toggle output pin.

PG.9

I/O

MFP0

General purpose digital I/O pin.

BPWM0_CH5

I/O

MFP12

BPWM0 channel 5 output/capture input.

PG.10

I/O

MFP0

General purpose digital I/O pin.

BPWM0_CH4

I/O

MFP12

BPWM0 channel 4 output/capture input.

PG.11

I/O

MFP0

General purpose digital I/O pin.

BPWM0_CH3

I/O

MFP12

BPWM0 channel 3 output/capture input.

PG.12

I/O

MFP0

General purpose digital I/O pin.

BPWM0_CH2

I/O

MFP12

BPWM0 channel 2 output/capture input.

PG.13

I/O

MFP0

General purpose digital I/O pin.

BPWM0_CH1

I/O

MFP12

BPWM0 channel 1 output/capture input.

PG.14

I/O

MFP0

General purpose digital I/O pin.

BPWM0_CH0

I/O

MFP12

BPWM0 channel 0 output/capture input.

PG.15

I/O

MFP0

General purpose digital I/O pin.

PG.15 CLKO

O

MFP14

Clock Out

EADC0_STI

MFP15

EADC0 external trigger input.

PH.4

I/O

MFP0

General purpose digital I/O pin.

SPI1_MISO

I/O

MFP3

SPI1 MISO (Master In, Slave Out) pin.

PH.5

I/O

MFP0

General purpose digital I/O pin.

SPI1_MOSI

I/O

MFP3

SPI1 MOSI (Master Out, Slave In) pin.

PH.6

I/O

MFP0

General purpose digital I/O pin.

SPI1_CLK

I/O

MFP3

SPI1 serial clock pin.

PG.2

PG.3

PG.4

PG.9

PG.10

PG.11

M471V/M471K/M471C SERIES DATASHEET

PG.12

PG.13

PG.14

PH.4

PH.5

PH.6

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M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

PH.7

I/O

MFP0

General purpose digital I/O pin.

SPI1_SSI/O

MFP3

SPI1 slave select pin.

PH.8

I/O

MFP0

General purpose digital I/O pin.

SPI1_CLK

I/O

MFP6

SPI1 serial clock pin.

PH.8 UART3_nRTS

O

MFP7

UART3 request to Send output pin.

I2C1_SMBAL

O

MFP8

I2C1 SMBus SMBALTER pin

UART1_TXD

O

MFP10

UART1 data transmitter output pin.

PH.9

I/O

MFP0

General purpose digital I/O pin.

SPI1_SSI/O

MFP6

SPI1 slave select pin.

PH.9 UART3_nCTS

I

MFP7

UART3 clear to Send input pin.

I2C1_SMBSUS

O

MFP8

I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)

UART1_RXD

I

MFP10

UART1 data receiver input pin.

PH.10

I/O

MFP0

General purpose digital I/O pin.

SPI1_I2SMCLK

I/O

MFP6

SPI1 I2S master clock output pin

UART4_TXD

O

MFP7

UART4 data transmitter output pin.

UART0_TXD

O

MFP8

UART0 data transmitter output pin.

PH.11

I/O

MFP0

General purpose digital I/O pin.

UART4_RXDI

MFP7

UART4 data receiver input pin.

UART0_RXDI

MFP8

UART0 data receiver input pin.

EPWM0_CH5

I/O

MFP11

EPWM0 channel 5 output/capture input.

PI.0

I/O

MFP0

General purpose digital I/O pin.

UART0_TXD

O

MFP3

UART0 data transmitter output pin.

I2C0_SCL

I/O

MFP4

I2C0 clock pin.

UART5_TXD

O

MFP6

UART5 data transmitter output pin.

UART2_TXD

O

MFP7

UART2 data transmitter output pin.

I2C1_SCL

I/O

MFP9

I2C1 clock pin.

EPWM0_CH4

I/O

MFP11

EPWM0 channel 4 output/capture input.

EPWM1_CH0

I/O

MFP12

EPWM1 channel 0 output/capture input.

ACMP0_OO

MFP14

Analog comparator 0 output pin.

PI.1

I/O

MFP0

General purpose digital I/O pin.

UART0_RXDI

MFP3

UART0 data receiver input pin.

I2C0_SDA

I/O

MFP4

I2C0 data input/output pin.

PH.7

PH.10

M471V/M471K/M471C SERIES DATASHEET

PH.11

PI.0

PI.1

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M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

UART5_RXDI

MFP6

UART5 data receiver input pin.

UART2_RXDI

MFP7

UART2 data receiver input pin.

I2C1_SDA

I/O

MFP9

I2C1 data input/output pin.

EPWM0_CH5

I/O

MFP11

EPWM0 channel 5 output/capture input.

EPWM1_CH1

I/O

MFP12

EPWM1 channel 1 output/capture input.

ACMP1_OO

MFP14

Analog comparator 1 output pin.

PI.2

I/O

MFP0

General purpose digital I/O pin.

UART1_TXD

O

MFP3

UART1 data transmitter output pin.

I2C0_SCL

I/O

MFP4

I2C0 clock pin.

UART5_TXD

O

MFP6

UART5 data transmitter output pin.

I2C1_SCL

I/O

MFP9

I2C1 clock pin.

UART4_TXD

O

MFP11

UART4 data transmitter output pin.

BPWM0_CH5

I/O

MFP12

BPWM0 channel 5 output/capture input.

EADC0_STI

MFP15

EADC0 external trigger input.

PI.3

I/O

MFP0

General purpose digital I/O pin.

UART1_RXDI

MFP3

UART1 data receiver input pin.

I2C0_SDA

I/O

MFP4

I2C0 data input/output pin.

UART5_RXDI

MFP6

UART5 data receiver input pin.

I2C1_SDA

I/O

MFP9

I2C1 data input/output pin.

UART4_RXD

I

MFP11

UART4 data receiver input pin.

BPWM0_CH4

I/O

MFP12

BPWM0 channel 4 output/capture input.

PI.4

I/O

MFP0

General purpose digital I/O pin.

UART4_TXD

O

MFP7

UART4 data transmitter output pin.

UART0_TXD

O

MFP8

UART0 data transmitter output pin.

UART1_TXD

O

MFP10

UART1 data transmitter output pin.

EPWM0_CH5

I/O

MFP11

EPWM0 channel 5 output/capture input.

CIR0_RXDI

MFP14

CIR0 data receiver input pin.

ACMP0_OO

MFP15

Analog comparator 0 output pin.

PI.5

I/O

MFP0

General purpose digital I/O pin.

UART4_RXDI

MFP7

UART4 data receiver input pin.

UART0_RXDI

MFP8

UART0 data receiver input pin.

UART1_RXD

I

MFP10

UART1 data receiver input pin.

PI.2

PI.4

M471V/M471K/M471C SERIES DATASHEET

PI.3

PI.5

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M471V/M471K/M471C Series
Pin Name

Type

MFP

Description

EPWM0_CH4

I/O

MFP11

EPWM0 channel 4 output/capture input.

ACMP1_OO

MFP15

Analog comparator 1 output pin.

Table 4.3-1 GPIO Multi-function Table

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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Rev 1.40

M471V/M471K/M471C Series
5
5.1

BLOCK DIAGRAM
NuMicro® M471V/M471K/M471C Block Diagram

M471V/M471K/M471C SERIES DATASHEET

Figure 5.1-1 NuMicro® M471V/M471K/M471C Block Diagram

Dec. 22, 2022

Page 67 of 178

Rev 1.40

M471V/M471K/M471C Series
6

FUNCTIONAL DESCRIPTION

6.1

Arm® Cortex® -M4 Core

The Cortex® -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA AHBLite interfaces for best parallel performance and includes an NVIC component. The processor with
optional hardware debug functionality can execute Thumb code and is compatible with other Cortex® M profile processors. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler mode.
Thread mode is entered on Reset, and can be entered as a result of an exception return. The Cortex® M4F is a processor with the same capability as the Cortex® -M4 processor and includes floating point
arithmetic functionality. The NuMicro® M471V/M471K/M471C series is embedded with Cortex® -M4F
processor. Throughout this document, the name Cortex® -M4 refers to both Cortex® -M4 and Cortex® M4F processors. Figure 6.1-1 shows the functional controller of the processor.

M471V/M471K/M471C SERIES DATASHEET

Figure 6.1-1 Cortex® -M4 Block Diagram
Cortex® -M4 processor features:
 A low gate count processor core, with low latency interrupt processing that has:–

A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual–

Banked Stack Pointer (SP)–

Hardware integer divide instructions, SDIV and UDIV–

Handler and Thread modes

Dec. 22, 2022

Page 68 of 178

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M471V/M471K/M471C Series







Thumb and Debug states–

Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low
interrupt latency–

Automatic processor state saving and restoration for low latency Interrupt Service
Routine (ISR) entry and exit–

Support for ARMv6 big-endian byte-invariant or little-endian accesses–

Support for ARMv6 unaligned accesses

Floating Point Unit (FPU) in the Cortex® -M4F processor providing:–

32-bit instructions for single-precision (C float) data-processing operations–

Combined Multiply and Accumulate instructions for increased precision (Fused MAC)–

Hardware support for conversion, addition, subtraction, multiplication with optional
accumulate, division, and square-root–

Hardware support for denormals and all IEEE rounding modes–

32 dedicated 32-bit single precision registers, also addressable as 16 double-wordregisters–

Decoupled three stage pipeline

Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core toachieve low latency interrupt processing. Features include:–

External interrupts. Configurable from 1 to 240 (the NuMicro® M471V/M471K/M471C
series configured with 64 interrupts)–

Bits of priority, configurable from 3 to 8–

Dynamic reprioritization of interrupts–

Priority grouping which enables selection of preempting interrupt levels andnonpreempting interrupt levels–

Support for tril-chaining and late arrival of interrupts, which enables back-to-backinterrupt processing without the overhead of state saving and restoration between
interrupts.

–

Processor state automatically saved on interrupt entry, and restored on interrupt exit
with on instruction overhead–

Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode

Memory Protection Unit (MPU). An optional MPU for memory protection, including:–

Eight memory regions–

Sub Region Disable (SRD), enabling efficient use of memory regions–

The ability to enable a background region that implements the default memory map
attributes

Low-cost debug solution that features:–

Debug access to all memory and registers in the system, including access to memory
mapped devices, access to internal core registers when the core is halted, and accessto debug control registers even while SYSRESETn is asserted.

–

Serial Wire Debug Port(SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug
access–

Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints andDec. 22, 2022

Page 69 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET–M471V/M471K/M471C Series
code patches–

Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data
tracing, and system profiling–

Optional Instrumentation Trace Macrocell (ITM) for support of printf() style debugging–

Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA),
including Single Wire Output (SWO) mode–

Optional Embedded Trace Macrocell (ETM) for instruction trace.

Bus interfaces:–

Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode, andSystem bus interfaces–

Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface–

Bit-band support that includes atomic bit-band write and read operations.

–

Memory access alignment–

Write buffer for buffering of write data–

Exclusive access transfers for multiprocessor systems

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 70 of 178

Rev 1.40

M471V/M471K/M471C Series
6.2 System Manager
6.2.1

Overview

System management includes the following sections:

6.2.2



System Reset

System Power Distribution

SRAM Memory Orginization



System Timer (SysTick)

Nested Vectored Interrupt Controller (NVIC)

System Control register

System Reset

The system reset can be issued by one of the events listed below. These reset event flags can beread from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are fromperipheral signals. Software reset can trigger reset through setting control registers.
–Power-on Reset–

Low level on the nRESET pin–

Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)–

Low Voltage Reset (LVR)–

Brown-out Detector Reset (BOD Reset)–

CPU Lockup Reset

Software Reset Sources–

CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])–MCU Reset to reboot but keeping the booting setting from APROM or LDROM bywriting 1 to SYSRESETREQ (AIRCR[2])–

CPU Reset for Cortex® -M4 core only by writing 1 to CPURST (SYS_IPRST0[1])Dec. 22, 2022

Page 71 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETHardware Reset Sources

M471V/M471K/M471C Series
Glitch Filter
32 us

nRESET~50k ohm
@3.3v

VDD

POROFF(SYS_PORCTL[15:0])

Power-onReset
LVREN(SYS_BODCTL[7])AVDD

Reset Pulse Width~3.2msLow Voltage
Reset
BODRSTEN(SYS_BODCTL[3])Brown-out
Reset
WDT/WWDT
Reset

Reset Pulse Width
64 WDT clocks

CPU Lockup
Reset

Reset Pulse Width
2 system clocks

System ResetCHIP Reset
CHIPRST(SYS_IPRST0[0])MCU Reset
SYSRSTREQ(AIRCR[2])Software Reset

Reset Pulse Width
2 system clocks

CPU Reset
CPURST(SYS_IPRST0[1])Figure 6.2-1 System Reset Sources

M471V/M471K/M471C SERIES DATASHEET

There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M4 only; the other reset sources will reset Cortex® -M4 and all peripherals. However, there aresmall differences between each reset source and they are listed in Table 6.2-1
Reset Sources
Register
SYS_RSTSTS
CHIPRST(SYS_IPRST0[0])POR

NRESET

WDT

LVR

BOD

Lockup

CHIP

MCU

CPU

Bit 0 = 1

Bit 1 = 1

Bit 2 = 1

Bit 3 = 1

Bit 4 = 1

Bit 8 = 1

Bit 0 = 1

Bit 5 = 1

Bit 7 = 1

0x0

-

-

-

-

-

-

-

-

BODEN
(SYS_BODCTL[0])BODVL(SYS_BODCTL[2:1])

ReloadReloadReloadReload
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0-

ReloadReloadReload
from
from
from
CONFIG0 CONFIG0 CONFIG0-BODRSTEN(SYS_BODCTL[3])HXTEN(CLK_PWRCTL[0])
LXTEN(CLK_PWRCTL[1])
WDTCKEN(CLK_APBCLK0[0])HCLKSEL

Dec. 22, 2022

ReloadReloadReloadReloadReloadReloadReloadReload
from
from
from
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
0x0

-

-

-

-

-

-

-

-

0x1

-

0x1

-

-

-

0x1

-

-

Reloadfrom

Reloadfrom

Reloadfrom

Reloadfrom

Reloadfrom

Reloadfrom

Reloadfrom

Reloadfrom-Page 72 of 178

Rev 1.40

M471V/M471K/M471C Series(CLK_CLKSEL0[2:0])
WDTSELCONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
0x3

0x3

-

-

-

-

-

-

-

0x0

-

-

-

-

-

-

-

-

0x0

-

-

-

-

-

-

-

-

0x0

-

-

-

-

-

-

-

-

0x0

-

-

-

-

-

-

-

-

0x0

0x0

-

-

-

-

-

-

-

ReloadReloadReloadReloadReload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadfrom
CONFIG0--0x07000x07000x07000x07000x0700-0x0700--

WDT_ALTCTL

0x00000x00000x00000x00000x0000-0x0000--

WWDT_RLDCNT

0x00000x00000x00000x00000x0000-0x0000--

WWDT_CTL

0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800-

0x3F0800--

WWDT_STATUS

0x00000x00000x00000x00000x0000-0x0000--

WWDT_CNT

0x3F

0x3F

0x3F

0x3F

0x3F

-

0x3F

-

-

ReloadReloadReloadReloadReload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadfrom
CONFIG0--

ReloadReloadReloadReloadReload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadfrom
CONFIG0--

ReloadReloadReloadReloadReloadbase onbase onbase onbase onbase onCONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadbase onCONFIG0--(CLK_CLKSEL1[1:0])
HXTSTB(CLK_STATUS[0])LXTSTB(CLK_STATUS[1])PLLSTB(CLK_STATUS[2])HIRCSTB(CLK_STATUS[4])CLKSFAIL(CLK_STATUS[7])RSTEN(WDT_CTL[1])WDTEN(WDT_CTL[7])
WDT_CTL
except bit 1 and bit 7.

(FMC_ISPCTL[1])BL(FMC_ISPCTL[16])CBS(FMC_ISPSTS[2:1))

VECMAP(FMC_ISPSTS[23:9])
Other Peripheral
Registers

Reset ValueFMC Registers

Reset Value-

Note: ‘-‘ means that the value of register keeps original setting.

Table 6.2-1 Reset Value of Registers
nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an

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asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and thestate keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if theprevious reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset waveform.

nRESET
0.7 VDD

32 us

0.2 VDD

32 us
nRESET Reset

Figure 6.2-2 nRESET Reset Waveform
Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system tobe reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, thePOR module will detect the rising voltage and generate reset signal to system until the voltage isready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there
is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3
shows the power-on reset waveform.

M471V/M471K/M471C SERIES DATASHEET

VPOR

0.1V
VDD
Power-onReset

Figure 6.2-3 Power-on Reset (POR) Waveform
Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function
will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage islower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the
AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL(SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.2-4 shows the Low Voltage Reset waveform.

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M471V/M471K/M471C Series

AVDD

VLVR

T1
( < LVRDGSEL)

T2( =LVRDGSEL)
T3( =LVRDGSEL)

Low Voltage Reset
200 usDelay for LVR stable

LVREN

Figure 6.2-4 Low Voltage Reset (LVR) Waveform
Brown-out Detector Reset (BOD Reset)

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M471V/M471K/M471C SERIES DATASHEET

If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL(SYS_BODCTL[17:16]) and the state keeps longer than De-glitch time set by BODDGSEL(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the
AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The
default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user
configuration
register
CBODEN(CONFIG0[19]),
CBOV(CONFIG0[22:21])and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.2-5 shows the Brown-out Detector waveform.

M471V/M471K/M471C Series
AVDD
VBODH
VBODL

Hysteresis

T1(< BODDGSEL)

T2(= BODDGSEL)BODOUT
T3(= BODDGSEL)BODRSTEN

Brown-out
Reset

Figure 6.2-5 Brown-out Detector (BOD) Waveform

M471V/M471K/M471C SERIES DATASHEET

Watchdog Timer Reset (WDT)In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used
to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system andtake action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is awatchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.

CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M4 core is reset and all other peripherals remain the same status
after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset andBS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or

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M471V/M471K/M471C Series
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.

6.2.3

System Power Distribution

In this chip, power distribution is divided into two segments:


Analog power from AVDD and AVSS provides the power for analog components operation.



Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.

VREF

The outputs of internal voltage regulators (LDO) require an external capacitor which should be locatedclose to the corresponding pin. Analog power (AVDD) should be the same voltage level of the digital
power (VDD). Figure 6.2-6 shows the NuMicro® M471V/M471K/M471C power distribution.

12-bit ADC

8-bit DACInternal Reference
VoltageTemp. Sensor

AnalogComparator

LVDR(Low Voltage Reset,
Brown-out Detector)

AVDD
AVSS

Digital Logic
LDO_CAP

SRAM

Flash

Data Flash

1.8V/1.9V

PF.2
PF.3

PLL

POR18

48 MHz HIRC
Oscillator

4~24 MHz
crystaloscillator

POR50

Power
On
Control

5.0V à
1.8V/1.9V
LDO

M471V/M471K/M471C SERIES DATASHEET

1uF
38.4 kHz
LIRC
Oscillator

IO Cell

GPIO

VSS

VDD

M471 Power Distribution

Figure 6.2-6 NuMicro® M471V/M471K/M471C Power Distribution Diagram

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6.2.4

Power Modes and Wake-up Sources

The NuMicro® M471V/M471K/M471C series has power manager unit to support several operating
modes for saving power. Table 6.2-2 lists all power modes in the M471V/M471K/M471C series.
Mode

CPU Operating Maximum
Speed

LDO_CAP Clock Disable(V)( MHz)
Normal mode

96

1.80

All clocks are disabled by control register.

Turbo mode

120

1.90

All clocks are disabled by control register.

Idle mode

CPU enter Sleep mode

Normal Power-down mode

1.80/1.90 Only CPU clock is disabled.

CPU enters Deep Sleep mode

(NPD)

1.80/1.90 Most clocks are disabled except LIRC/LXT, andonly RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.

Table 6.2-2 Power Mode Table
There are different power mode entry settings for each power mode. They have different entry setting
and leaving condition. Table 6.2-3 shows the entry setting for each power mode. When chip power-on,
chip is running at normal mode. User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN
(CLK_PWRCTL[7]) and PDMSEL (CLK_PMUCTL[2:0]) and execute WFI instruction.
Register/Instruction

SLEEPDEEPPDEN

PDMSELCPU Run WFI Instruction

Mode(SCR[2])(CLK_PWRCTL[7]) (CLK_PMUCTL[2:0])

M471V/M471K/M471C SERIES DATASHEET

Normal mode

0

0

0

NO

Idle mode

0

0

0

YES

Normal Power-down mode

1

1

0

YES

Table 6.2-3 Power Mode Difference Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-4 lists theavailable clocks for each power mode.
Power Mode

Normal Mode

Idle Mode

Power-Down Mode

Definition

CPU is in active state

CPU is in sleep state

CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.

Entry Condition

Chip is in normal mode after
system reset released

CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable andexecutes WFI instruction.

Wake-Up Sources

N/A

All interrupts

RTC, WDT, I²C, Timer, UART,
GPIO, EINT, ACMP, CIR0 and
BOD.

Available Clocks

All

All except CPU clock

LXT and LIRC

After Wake-Up

N/A

CPU back to normal mode

CPU back to normal mode

Table 6.2-4 Power Mode Definition Table

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M471V/M471K/M471C Series

System reset released

Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ONCPU executes WFIInterrupts occur

1. SLEEPDEEP(SCR[2]) = 1
2. PDEN(CLK_PWRCTL[7]) = 1
3. CPU executes WFIWake-up events occur

Power-down Mode
CPU Clock OFF
HXT, HIRC, PCLK OFF
LXT, LIRC ON
Flash Halt

Idle Mode
CPU Clock OFF
HXT, HIRC, PCLK ON
LXT, LIRC ON
Flash Halt

Figure 6.2-7 Power Mode State Machine
NPD

HXT

ON

Halt

HIRC

ON

Halt

LXT

ON

ON/OFF1LIRC

ON

ON/OFF2

PLL

ON

Halt

HCLK/PCLK

ON

Halt

CPU

Halt

Halt

SRAM retention

ON

ON

FLASH

ON

Halt

TIMER

ON

ON/OFF3

WDT

ON

ON/OFF4

RTC

ON

ON/OFF5

UART

ON

ON/OFF6

CIR0

ON

ON/OFF7

OthersON

Halt

M471V/M471K/M471C SERIES DATASHEET

Idle Mode

Table 6.2-5 Clocks in Power Modes
Note:
1. LXT ON or OFF depends on SOFTWARE setting in normal mode.
2. LIRC ON or OFF depends on SOFTWARE setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.

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M471V/M471K/M471C Series
5. If RTC clock source is selected as LXT and LXT is on.
6. If UART clock source is selected as LXT and LXT is on.
7. If CIR0 clock source is selected as LIRC/LXT and LIRC/LXT is on.

Wake-up sources in Normal Power-down mode (NPD):
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.2-6 lists the condition about how to enter Power-down mode again for each peripheral.
User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Power-Down Mode
Wake-Up
SourceWake-Up Condition

Re-Entering Power-Down Mode Condition
NPD

BOD

Brown-Out Detector
Reset / Interrupt

V

After software writes 1 to clear BODIF (SYS_BODCTL[4]).

LVR

LVR Reset

V

After software writes 1 to clear LVRF (SYS_RSTSTS[3])POR

POR Reset

V

After software writes 1 to clear PORF (SYS_RSTSTS[0])EINT

External Interrupt

V

After software write 1 to clear the Px_INTSRC[n] bit.

GPIO

GPIO Interrupt

V

After software write 1 to clear the Px_INTSRC[n] bit.

Timer Interrupt

V

After software writes 1 to clear TWKF (TIMERx_INTSTS[1])and TIF (TIMERx_INTSTS[0]).

WDT Interrupt

V

After software writes 1 to clear WKF (WDT_CTL[5]) (Write
Protect).

Alarm Interrupt

V

After software writes 1 to clear ALMIF (RTC_INTSTS[0]).

Time Tick Interrupt

V

After software writes 1 to clear TICKIF (RTC_INTSTS[1]).

nCTS Wake-Up

V

After
softwarewrites(UARTx_WKSTS[0]).

1

to

clear

CTSWKFRX Data Wake-Up

V

After
softwarewrites(UARTx_WKSTS[1]).

1

to

clear

DATWKF

Received FIFO
Threshold Wake-Up

V

After
softwarewrites(UARTx_WKSTS[2]).

1

to

clear

RFRTWKF

RS-485 AAD Mode
Wake-UpV

After
softwarewrites(UARTx_WKSTS[3]).

1

to

clear

RS485WKF

Received FIFO
Threshold Time-out
Wake-UpV

After
softwarewrites(UARTx_WKSTS[4]).

1

to

clear

TOUTWKF

Address match WakeUp

V

After
softwarewrites1
to(I2C_WKSTS[1]). Then software
WKIF(I2C_WKSTS[0]).

clear
writes

WKAKDONE
1 to clear

ACMP

Comparator PowerDown Wake-Up Interrupt

V

After software writes 1 to clear WKIF0 (ACMP_STATUS[8])and WKIF1 (ACMP_STATUS[9]).

CIR0

CIR0 receive patternmatch Wake-Up

V

After software writes 1 to clear PDWKF (CIR_STATUS[10]).

TIMER

WDT

M471V/M471K/M471C SERIES DATASHEET

RTC

UART

I2C

Table 6.2-6 Re-Entering Power-down Mode Condition

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M471V/M471K/M471C Series
6.2.5

Power Modes and Power Level Transition

NPD

POR Reset
nReset pin
WDT reset
CHIP reset
LVR
BOD reset
Lockup reset
System reset

Power Level PL0

Power Level changing

Run modePower Level PL1

Power Level PL1

Power Level PL0

Figure 6.2-8 NuMicro® M471V/M471K/M471C Power Distribution Diagram

6.2.6

System Memory Map

The NuMicro® M471V/M471K/M471C series provides 4G-byte addressing space. The memory
locations assigned to each on-chip controllers are shown in Table 6.2-7. The detailed register
definition, memory space, and programming will be described in the following sections for each onchip peripheral. The NuMicro® M471V/M471K/M471C series only supports little-endian data format.
Address Space

Token

Controllers

Flash and SRAM Memory Space
0x0000_0000 – 0x0007_FFFF

FLASH_BA

FLASH Memory Space (512 Kbytes)

0x0040_0000 – 0x0040_7FFF

DFLASH_BA

Data FLASH Memory Space (32 Kbytes)

0x2000_0000 – 0x2000_7FFF

SRAM0_BA

SRAM Memory Space (32 Kbytes)

0x2000_8000 – 0x2000_FFFF

SRAM1_BA

SRAM Memory Space (32 Kbytes)

Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)

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Idle modeM471V/M471K/M471C Series
0x4000_0000 – 0x4000_01FF

SYS_BA

System Control Registers

0x4000_0200 – 0x4000_02FF

CLK_BA

Clock Control Registers

0x4000_0300 – 0x4000_03FF

NMI_BANMI Control Registers

0x4000_4000 – 0x4000_4FFF

GPIO_BAGPIO Control Registers

0x4000_8000 – 0x4000_8FFF

PDMA_BA

Peripheral DMA Control Registers

0x4000_C000 – 0x4000_CFFF

FMC_BA

Flash Memory Control Registers

0x4000_F000 – 0x4000_FFFF

DFMC_BA

Data Flash Memory Control Registers

0x4003_1000 – 0x4003_1FFF

CRC_BA

CRC Generator Registers

APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)

M471V/M471K/M471C SERIES DATASHEET

0x4004_0000 – 0x4004_00FF

WDT_BA

Watchdog Timer Control Registers

0x4004_0100 – 0x4004_0FFF

WWDT_BA

Window Watchdog Timer Control Registers

0x4004_1000 – 0x4004_1FFF

RTC_BA

Real Time Clock (RTC) Control Register

0x4004_3000 – 0x4004_3FFF

EADC0_BA

Enhanced Analog-Digital-Converter 0 (EADC0) Control Registers

0x4004_5000 – 0x4004_5FFF

ACMP01_BA

Analog Comparator 0/ 1 Control Registers

0x4004_7000 – 0x4004_7FFF

DAC_BADAC Control Registers

0x4005_0000 – 0x4005_0FFF

TMR01_BA

Timer0/Timer1 Control Registers

0x4005_1000 – 0x4005_1FFF

TMR23_BA

Timer2/Timer3 Control Registers

0x4005_8000 – 0x4005_8FFF

EPWM0_BA

EPWM0 Control Registers

0x4005_9000 – 0x4005_9FFF

EPWM1_BA

EPWM1 Control Registers

0x4005_A000 – 0x4005_AFFF

BPWM0_BA

BPWM0 Control Registers

0x4005_B000 – 0x4005_BFFF

BPWM1_BA

BPWM1 Control Registers

0x4005_F000 – 0x4005_FFFF

CIR0_BA

Custermize IR Control Registers

0x4006_1000 – 0x4006_1FFF

SPI0_BASPI0 Control Registers

0x4006_2000 – 0x4006_2FFF

SPI1_BASPI1 Control Registers

0x4007_0000 – 0x4007_0FFF

UART0_BA

UART0 Control Registers

0x4007_1000 – 0x4007_1FFF

UART1_BA

UART1 Control Registers

0x4007_2000 – 0x4007_2FFF

UART2_BA

UART2 Control Registers

0x4007_3000 – 0x4007_3FFF

UART3_BA

UART3 Control Registers

0x4007_4000 – 0x4007_4FFF

UART4_BA

UART4 Control Registers

0x4007_5000 – 0x4007_5FFF

UART5_BA

UART5 Control Registers

0x4008_0000 – 0x4008_0FFF

I2C0_BA

I2C0 Control Registers

0x4008_1000 – 0x4008_1FFF

I2C1_BAI2C1 Control Registers

0x400B_A000 – 0x400B_AFFF

PRNG_BAPRNG Control Registers

System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF

Dec. 22, 2022

SCS_BA

System Timer Control Registers

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M471V/M471K/M471C Series
0xE000_E100 – 0xE000_ECFF

SCS_BA

External Interrupt Controller Control Registers

0xE000_ED00 – 0xE000_ED8F

SCS_BA

System Control Registers

Table 6.2-7 Address Space Assignments for On-Chip Controllers

6.2.7

SRAM Memory Orginization

The M471V/M471K/M471C supports embedded SRAM with total 64 Kbytes size and the SRAM
organization is separated to two banks: SRAM bank0 and SRAM bank1. The first bank has 32 Kbytes
address space, the second bank has 32 Kbyte address space. These two banks address space canbe accessed simultaneously. The SRAM bank0 supports parity error check to make sure chip
operating more stable.
Supports total 64 Kbytes SRAM

Supports byte / half word / word writeSupports fixed 32 Kbytes SRAM bank0 for independent access

Supports parity error check function for SRAM bank0Supports oversize response errorSupports remap address to 0x1000_0000

AHB interface
controller

SRAM decoder

SRAM bank0

AHB interface
controller

SRAM decoder

SRAM bank1

Figure 6.2-9 SRAM Block Diagram
Figure 6.2-9 shows the SRAM organization of M471. There are two SRAM banks in M471. The bank0
is addressed to 32 Kbytes and the bank1 is addressed to 32 Kbytes. The bank0 address space is from
0x2000_0000 to 0x2000_7FFF. The bank1 address space is from 0x2000_8000 to 0x2000_FFFF. The
address between 0x2001_0000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault
if CPU accesses these illegal memory addresses.
The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can access SRAM
bank0 through 0x2000_0000 to 0x2000_7FFF or 0x1000_0000 to 0x1000_7FFF, and access SRAM
bank1 through 0x2000_8000 to 0x2000_FFFF or 0x1000_8000 to 0x1000_FFFF.

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M471V/M471K/M471C SERIES DATASHEETAHB BusM471V/M471K/M471C Series

0x3FFF_FFFF

512MB

Reserved

0x2001_0000
0x1000_FFFF

0x2000_FFFF
remapping

32K byte
SRAM bank1

32K byte
SRAM bank1

0x2000_8000

0x1000_8000

0x2000_7FFF

0x1000_7FFF

M471V/M471K/M471C SERIES DATASHEET

32K byte
SRAM bank0

32K byte
SRAM bank0

remapping

0x2000_0000

0x1000_0000
64K byte device

64K byte device

Figure 6.2-10 SRAM Memory Organization
SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the parity
error checking mechanism is dynamic operating. As parity error occured, the PERRIF(SYS_SRAM_STATUS[0]) will be asserted to 1 and the SYS_SRAM_ERRADDR register will recode
the address with parity error. Chip will enter interrupt when SRAM parity error occurred if PERRIEN(SYS_SRAM_INTCTL[0]) is set to 1. When SRAM parity error occured, chip will stop detecting SRAM
parity error until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit.

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M471V/M471K/M471C Series
6.2.8

Bus Matrix

The M471V/M471K/M471C supports Bus Matrix to manage the access arbitration between masters.
The access arbitration can be selected by INTACTEN (SYS_AHBMCTL[0]) to use round-robinalgorithm or set Cortex® -M4 CPU as the highest bus priority.

PDMA

M4-SBUS

M4-DBUS

M4-IBUS

M3

M2

M1

M0
S0

S1

S2

FLASH

SRAM1
(32K)

SRAM2
(32K)

S3

APB1

S4

APB2

S5

DFLASHS6
AHB(ctrl)

Figure 6.2-11 NuMicro® M471V/M471K/M471C Bus Matrix Diagram

6.2.9

HIRC Auto Trim

This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate
LXT (32.768 kHz crystal oscillator), automatically gets accurate HIRC output frequency, 0.25 %deviation within all temperature ranges.

6.2.10Internal VREF

This chip supports internal VREF function, depend on setting of VREFCTL(SYS_VREFCTL[4:0]) togenerate different reference voltage for ADC/DAC/ACMP. User has to enable PRELOADEN(SYS_VREFCTL[6]) to fit the Tstable when VREFCTL(SYS_VREFCTL[4:0]) change setting (except
set to 00000) to make sure that VREF works well. Tstable depends on different situations has different
requirement, please refer to the relative Datasheet.

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M471V/M471K/M471C SERIES DATASHEETFor instance, the system needs an accurate 48 MHz clock. In such case, if neither using PLL as thesystem clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL(SYS_IRCTCTL[10] reference clock selection) to “1”, set FREQSEL (SYS_IRCTCTL[1:0] trim
frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK(SYS_IRCTISTS[0] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate
within 0.25% deviation.

M471V/M471K/M471C Series

Internal Reference
Voltage

Analog Comparator
1
CRV0
0
CRV0SSEL(ACMP_VREF[6])1CRV1

VREFEN0

PRELOADCRV1SSEL(ACMP_VREF[22])VREF OUT

VREF

Tstable1

8-bit DAC0SELVREF(DAC0_CTL[4])M471V/M471K/M471C SERIES DATASHEET

1

12-bit EADC
AVDD

0REFSEL(EADC0_VREF[1])Figure 6.2-12 NuMicro® M471V/M471K/M471C VREF Diagram

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M471V/M471K/M471C Series
6.2.11

UART0_TXD Modulation with EPWM

This chip supports UART0_TXD to modulate with EPWM channel. User can set
MODPWMSEL(SYS_MODCTL[7:4]) to choose which EPWM0 channel to modulate with UART0_TXD
and set MODEN(SYS_MODCTL[0]) to enable modulation function. User can set
TXDINV(UART_LINE[8]) to inverse UART0_TXD before modulating with EPWM.

EPWM0_CHx

UART0_TXD

TXDINV = 0 & MODH = 0

TXDINV = 0 & MODH = 1

TXDINV = 1 & MODH = 0

Figure 6.2-11 UART0_TXD Modulated with EPWM Channel

6.2.12

Register Lock Control

Some of the system control registers need to be protected to avoid inadvertent write and disturb thechip operation. These system control registers are protected after the power-on reset till user disables
register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence iswriting the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence.
SYS_IPRST0

Address 0x4000_0008

SYS_ALTCTL

address 0x4000_0014

SYS_BODCTL

address 0x4000_0018

SYS_PORCTL

address 0x4000_0024

SYS_VREFCTL

address 0x4000_0028

SYS_SRAM_BISTCTL

address 0x4000_00D0

SYS_SRAM_PARITY

address 0x4000_00D8

SYS_RCADJ

address 0x4000_0110

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M471V/M471K/M471C Series

M471V/M471K/M471C SERIES DATASHEETSYS_HIRC2TCTL

address 0x4000_018C

SYS_HXTTCTL

address 0x4000_0190

SYS_ACMPTCTL

address 0x4000_0194

SYS_PORDISAN

address 0x4000_01EC

SYS_PLCTL

address 0x4000_01F8

CLK_PWRCTL

address 0x4000_0200

CLK_APBCLK0

address 0x4000_0208

CLK_CLKSEL0

address 0x4000_0210

CLK_CLKSEL1

address 0x4000_0214

CLK_PLLCTL

address 0x4000_0240

CLK_PLL2CTL

address 0x4000_0244

CLK_PLLTEST

address 0x4000_0248

CLK_PMUCTL

address 0x4000_0290

NMIEN

address 0x4000_0300

AHBMCTL

address 0x4000_0400

FMC_FTCTL

address 0x4000_5018

FMC_ICPCMD

address 0x4000_501C

FMC_ISPCTL

address 0x4000_C000

FMC_ISPTRG

address 0x4000_C010

FMC_FTCTL

address 0x4000_C018

FMC_ICPCTL

address 0x4000_C01C

FMC_ISPSTS

address 0x4000_C040

FMC_CYCCTL

address 0x4000_C04C

FMC_KPKEYTRG

address 0x4000_C05C

FMC_KPKEYSTS

address 0x4000_C060

WDT_CTL

address 0x4004_0000

WDT_ALTCTL

address 0x4004_0004

EADC_TEST

address 0x4004_3200

ACMP_TEST

address 0x4004_5FF8

DAC0_TEST

address 0x4004_7FF0

DAC1_TEST

address 0x4004_7FF8

TIMER0_CTL

address 0x4005_0000

TIMER1_CTL

address 0x4005_0100

TIMER2_CTL

address 0x4005_1000

TIMER3_CTL

address 0x4005_1100

Dec. 22, 2022

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M471V/M471K/M471C Series
address 0x4005_0040

TIMER1_PWMCTL

address 0x4005_0140

TIMER2_PWMCTL

address 0x4005_1040

TIMER3_PWMCTL

address 0x4005_1140

TIMER0_PWMDTCTL

address 0x4005_0058

TIMER1_PWMDTCTL

address 0x4005_0158

TIMER2_PWMDTCTL

address 0x4005_1058

TIMER3_PWMDTCTL

address 0x4005_1158

TIMER0_PWMBRKCTL

address 0x4005_0070

TIMER1_PWMBRKCTL

address 0x4005_0170

TIMER2_PWMBRKCTL

address 0x4005_1070

TIMER3_PWMBRKCTL

address 0x4005_1170

TIMER0_PWMSWBRK

address 0x4005_007C

TIMER1_PWMSWBRK

address 0x4005_017C

TIMER2_PWMSWBRK

address 0x4005_107C

TIMER3_PWMSWBRK

address 0x4005_117C

TIMER0_PWMINTEN1

address 0x4005_0084

TIMER1_PWMINTEN1

address 0x4005_0184

TIMER2_PWMINTEN1

address 0x4005_1084

TIMER3_PWMINTEN1

address 0x4005_1184

TIMER0_PWMINTSTS1

address 0x4005_008C

TIMER1_PWMINTSTS1

address 0x4005_018C

TIMER2_PWMINTSTS1

address 0x4005_108C

TIMER3_PWMINTSTS1

address 0x4005_118C

EPWM_CTL0

address 0x4005_8000/0x4005_9000

EPWM_CTL1

address 0x4005_8000/0x4005_9000

EPWM_DTCTL0_1

address 0x4005_8070/0x4005_9070

EPWM_DTCTL2_3

address 0x4005_8074/0x4005_9074

EPWM_DTCTL4_5

address 0x4005_8078/0x4005_9078

EPWM_BRKCTL0_1

address 0x4005_80C8/0x4005_90C8

EPWM_BRKCTL2_3

address 0x4005_80CC/0x4005_90CC

EPWM_BRKCTL4_5

address 0x4005_80D0/0x4005_90D0

EPWM_SWBRK

address 0x4005_80DC/0x4005_90DC

EPWM_INTEN1

address 0x4005_80E4/0x4005_90E4

EPWM_INTSTS1

address 0x4005_80EC/0x4005_90EC

Dec. 22, 2022

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M471V/M471K/M471C SERIES DATASHEETTIMER0_PWMCTL

Rev 1.40

M471V/M471K/M471C Series
address 0x4005_8300/0x4005_9300

BPWM_CTL0

address 0x4005_A000/0x4005_B000

BPWM_SELFTEST

address 0x4005_A030/0x4005_B030

SYST_VAL

address 0xE000_E018

Dec. 22, 2022

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M471V/M471K/M471C SERIES DATASHEETEPWM_SELFTEST

Rev 1.40

M471V/M471K/M471C Series

6.2.13

System Timer (SysTick)

The Cortex® -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clearon-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can beused as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the countertransitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather thanan arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloadedwith this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M4 Technical Reference Manual” and“Arm® v6-M Architecture Reference Manual”.

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
6.2.14

Nested Vectored Interrupt Controller (NVIC)

The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of thestacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC
from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable
the Configuration and Control Register. Any other user mode access causes a bus fault. You canaccess all NVIC registers using byte, halfword, and word accesses unless otherwise stated. NVIC
registers are located within the SCS (System Control Space). All NVIC registers and system debug
registers are little-endian regardless of the endianness state of the processor.
The NVIC supports:An implementation-defined number of interrupts, in the range 1-240 interrupts.



A programmable priority level of 0-16 for each interrupt; a higher level corresponds to alower priority, so level 0 is the highest interrupt priority.



Level and pulse detection of interrupt signals.

Dynamic reprioritization of interrupts.

Grouping of priority values into group priority and subpriority fields.

Interrupt tail-chaining.

An external Non Maskable Interrupt (NMI)

WIC with Ultra-low Power Sleep mode support

The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling.
Exception Model and System Interrupt Map

M471V/M471K/M471C SERIES DATASHEET

Table 6.2-8 lists the exception model supported by M471V/M471K/M471C series. Software can set 16
levels of priority on some of these exceptions as well as on all interrupts. The highest userconfigurable priority is denoted as “0x00” and the lowest priority is denoted as “0xF0” (The 4-LSB
always 0). The default priority of all the user-configurable interrupts is “0x00”. Note that priority “0” istreated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “HardFault”.
When any interrupts is accepted, the processor will automatically fetch the starting address of theinterrupt service routine (ISR) from a vector table in memory. On system reset, the vector table is fixedat address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start
address to a different memory location, in the range 0x00000080 to 0x3FFFFF80,
The vector table contains the initialization value for the stack pointer on reset, and the entry point
addresses for all exception handlers. The vector number on previous page defines the order of entries
in the vector table associated with exception handler entry as illustrated in previous section.
Exception Type

Vector Number

Vector Address

PriorityReset

1

0x00000004

-3

NMI

2

0x00000008-2

Hard Fault

30x0000000C-1

Memory Manager Fault

40x00000010

Configurable

Bus Fault

50x00000014

Configurable

Usage Fault

60x00000018

Configurable

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M471V/M471K/M471C Series
Reserved

7 ~ 10Reserved

SVCall110x0000002C

Configurable

Debug Monitor

120x00000030

Configurable

Reserved

13

PendSV140x00000038

Configurable

SysTick

15

0x0000003C

Configurable

Interrupt (IRQ0 ~ IRQ)

16 ~ 111

Reserved

0x00000000 +(Vector Number)*4

Configurable

Table 6.2-8 Exception Model

VectorNumberInterrupt Number(BitinRegisters)

Interrupt Interrupt Name

Interrupt Description--

System exceptions

16

0

BODOUT

Brown-Out low voltage detected interrupt

17

1

IRC_INTIRC TRIM interrupt

18

2

PWRWU_INTClock controller interrupt for chip wake-up from power-down state

193

SRAM_PERR

SRAM parity check error interrupt

20

4

CLKFAIL

Clock fail detected interrupt

21

5

FMC_INTFMC ISP interrupt

22

6

RTC_INTReal time clock interrupt

23

7

TAMP_INT

Tamper interrupt

24

8

WDT_INT

Watchdog Timer interrupt

25

9

WWDT_INT

Window Watchdog Timer interrupt

26

10

EINT0

External interrupt from PA.6 or PB.5 pins

27

11

EINT1

External interrupt from PA.7, PB.4 or PD.15pins

28

12

EINT2

External interrupt from PB.3 or PC.6 pin

29

13

EINT3

External interrupt from PB.2 or PC.7 pin

30

14

EINT4

External interrupt from PA.8, PB.6 or PF.15 pin

31

15

EINT5

External interrupt from PB.7, PD.12 or PF.14 pin

32

16

GPA_INT

External interrupt from PA[15:0] pin

33

17

GPB_INT

External interrupt from PB[15:0] pin

34

18

GPC_INT

External interrupt from PC[15:0] pin

35

19

GPD_INT

External interrupt from PD[15:0] pin

36

20

GPE_INT

External interrupt from PE[15:0] pin

37

21

GPF_INT

External interrupt from PF[15:0] pin

Dec. 22, 2022

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M471V/M471K/M471C SERIES DATASHEET

0 ~ 15

Rev 1.40

M471V/M471K/M471C Series

M471V/M471K/M471C SERIES DATASHEET

38

22

Reserved

Reserved

39

23

SPI0_INT

SPI0 interrupt

40

24

BRAKE0_INT

EPWM0 brake interrupt

41

25

EPWM0_P0_INT

EPWM0 pair 0 interrupt

42

26

EPWM0_P1_INT

EPWM0 pair 1 interrupt

43

27

EPWM0_P2_INT

EPWM0 pair 2 interrupt

44

28

BRAKE1_INT

EPWM1 brake interrupt

45

29

EPWM1_P0_INT

EPWM1 pair 0 interrupt

46

30

EPWM1_P1_INT

EPWM1 pair 1 interrupt

47

31

EPWM1_P2_INT

EPWM1 pair 2 interrupt

48

32

TMR0_INT

Timer 0 interrupt

49

33

TMR1_INT

Timer 1 interrupt

50

34

TMR2_INT

Timer 2 interrupt

51

35

TMR3_INT

Timer 3 interrupt

52

36

UART0_INT

UART0 interrupt

53

37

UART1_INTUART1 interrupt

54

38

I2C0_INT

I2C0 interrupt

55

39

I2C1_INT

I2C1 interrupt

56

40

PDMA_INTPDMA interrupt

57

41

DAC_INTDAC interrupt

58

42

EADC0_INT0

EADC0 interrupt source 0

59

43

EADC0_INT1

EADC0 interrupt source 1

60

44

ACMP01_INT

ACMP0 and ACMP1 interrupt

61

45

Reserved

Reserved

62

46

EADC0_INT2

EADC0 interrupt source 2

63

47

EADC0_INT3

EADC0 interrupt source 3

64

48

UART2_INTUART2 interrupt

65

49

UART3_INTUART3 interrupt

66

50

Reserved

Reserved

67

51

SPI1_INT

SPI1 interrupt

68

52

Reserved

Reserved

69

53

Reserved

Reserved

70

54

Reserved

Reserved

71

55

Reserved

Reserved

72

56

Reserved

Reserved

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M471V/M471K/M471C Series
57

Reserved

Reserved

74

58

Reserved

Reserved

75

59

Reserved

Reserved

76

60

Reserved

Reserved

77

61

Reserved

Reserved

78

62

Reserved

Reserved

80

64

Reserved

Reserved

81

65

Reserved

Reserved

82

66

Reserved

Reserved

83

67

Reserved

Reserved

84

68

Reserved

Reserved

85

69

Reserved

Reserved

86

70

Reserved

Reserved

8771

PRNG_INTPRNG interrupt

88

72

GPG_INT

External interrupt from PG[15:0] pin

89

73

EINT6

External interrupt from PB.8 or PD.11 pin

90

74

UART4_INTUART4 interrupt

91

75

UART5_INTUART5 interrupt

92

76

Reserved

Reserved

93

77

Reserved

Reserved

94

78

BPWM0_INTBPWM0 interrupt

95

79

BPWM1_INTBPWM1 interrupt

96

80

Reserved

Reserved

97

81

Reserved

Reserved

98

82

Reserved

Reserved

99

83

Reserved

Reserved

100

84

Reserved

Reserved

101

85

Reserved

Reserved

102

86

Reserved

Reserved

103

87

Reserved

Reserved

105

88

GPH_INT

External interrupt from PH[11:0] pin

105

89

EINT7

External interrupt from PB.9 or PD.10 pin

106

90

Reserved

Reserved

107

91

Reserved

Reserved

108

92

Reserved

Reserved

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M471V/M471K/M471C Series
109

93

Reserved

Reserved

110

94

Reserved

Reserved

111

95

Reserved

Reserved

112

96

Reserved

Reserved

113

97

Reserved

Reserved

114

98

Reserved

Reserved

115

99

Reserved

Reserved

116

100

Reserved

Reserved

117

101

Reserved

Reserved

118

102

Reserved

Reserved

119

103

Reserved

Reserved

120

104

Reserved

Reserved

121

105

Reserved

Reserved

122

106

Reserved

Reserved

123

107

Reserved

Reserved

124

108

Reserved

Reserved

125

109

Reserved

Reserved

126

110

GPI_INT

External interrupt from PI[5:0] pin

127

111

CIR0_INT

CIR0 interrupt

M471V/M471K/M471C SERIES DATASHEET

Table 6.2-9 Interrupt Number Table
Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable orInterrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When aninterrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, theinterrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until
cleared by reset or an exception return. Clearing the enable bit prevents new activations of theassociated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used toenable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has noeffect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.

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M471V/M471K/M471C Series
6.3 Clock Controller
6.3.1

Overview

The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex® -M4 core executes
the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~24
MHz external high speed crystal (HXT) and 48 MHz internal high speed RC oscillator (HIRC) to
reduce the overall system power consumption. Figure 6.3-1 shows the clock generator and theoverview of the clock source control.

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series

HIRC
48MHz

HXT
4~24MHz

LXT
32.768 kHz

LIRC
38.4 kHzEADC

HIRC/4

1

PLLFOUTPLL FOUT

HXT/1,/2,/4,/8,/16

PCLK0

0

CLK_PLLCTL[19]

HIRC
LIRC
PLLFOUT
LXT

I2C1

PCLK1

EPWM1

SPI1

SPI0

CPU

BPWM0

BPWM1

CRC

TMR0

TMR2

FMC

TMR1

TMR3

111

PDMA

UR0

UR1

011

GPIO

UR2

SRAM

UR4

UR5

WDG

RTC

010

1/(HCLKDIV+1)

HCLK

001

HXT

I2C0
EPWM0

UR3

DAC

000

ACMP

CLK_CLKSEL0[2:0]

LIRC
HCLK

11

1/2048

10

LXT

01

/1,/2,/4,/8,/16
WDT

CLK_CLKSEL1[1:0]

HIRC

11

LXT
LIRC

11
WWDT

HCLK

1/2048

HIRC
HCLK

1/2

111

1/2

011

1/2

010

01

HXT

10

00

CLK_CLKSEL1[25:24]
CLK_CLKSEL1[27:26]
CLK_CLKSEL3[25:24]
CLK_CLKSEL3[27:26]
CLK_CLKSEL3[29:28]
CLK_CLKSEL3[31:30]

CLK_CLKSEL1[31:30]

CPUCLK

UART0
UART1
UART2
UART3
UART4
UART5

1/(UART0DIV+1)
1/(UART1DIV+1)
1/(UART2DIV+1)
1/(UART3DIV+1)
1/(UART4DIV+1)
1/(UART5DIV+1)

10

PLLFOUT

1
SysTick

HXT
LXT

001

HXT

0
SYST_CTRL[2]000

CLK_CLKSEL0[5:3]

PCLK1

1/(EADCDIV+1)

LIRC
LXT

EADC

1
RTC
0

DIV1EN(CLK_CLKOCTL[5])

HIRC

11

HCLK

RTC_LXTCTL[7]

10

LXT

LIRC

M471V/M471K/M471C SERIES DATASHEET

TM0
LXT
HXT

CLK1HZEN(CLK_CLKOCTL[6])

0
0

01

HXT
HIRC

/2(CLK_CLKOCTL[3:0]+1)

1

00

CLKO

1

100
CLK_CLKSEL1[29:28]

011
010

CIR0

LXT

001

LIRC

000

RTCCKSEL(RTC_LXTCTL[7])/32768
(LXT)
or
38912
(LIRC)

0
1

1 Hz clock from RTC

CLK_CLKSEL2[26:24]
HIRC
PCLK1
PLLFOUT
HXT

HIRC

11

PCLK0

10
01

PLLFOUT

SPI0

HXT

00

CLK_CLKSEL2[5:4]

PCLK0
HCLK

LIRC
TM0/TM1

1
0

LXT
HXT

01

SPI1

00

PCLK1
EPWM 0BPWM 0HCLK

10EPWM 1
BPWM 1

CLK_CLKSEL2[1]CLK_CLKSEL2[9]

HIRC

111

LIRC

101
011

PCLK0

10

CLK_CLKSEL2[7:6]

CLK_CLKSEL2[0]CLK_CLKSEL2[8]

HIRC

11

010

TMR0
TMR1

PCLK1
LXT

001

HXT

000

111
101
011

TM2/TM3

010

TMR2
TMR3

001
000

CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]

CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]

Figure 6.3-1 Clock Generator Global View Diagram

6.3.2

Clock Generator

The clock generator consists of 5 clock sources, which are listed below:32.768 kHz external low speed crystal oscillator (LXT)

4~24 MHz external high speed crystal oscillator (HXT)

Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from

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M471V/M471K/M471C Series
external 4~24 MHz external high speed crystal (HXT) or 48 MHz internal high speed
oscillator divided by 4 (HIRC/4)


48 MHz internal high speed RC oscillator (HIRC)



38.4 kHz internal low speed RC oscillator (LIRC)LXTEN (CLK_PWRCTL[1])
X32_IN

X32_OU
T
XT1_I
N

XT1_OUT

External
32.768 kHz
Crystal (LXT)

LXT

HXTEN (CLK_PWRCTL[0])External
4~24 MHz
Crystal (HXT)

PLLSRC(CLK_PLLCTL[19])0HIRCEN (CLK_PWRCTL[2])Internal 48
MHz
Oscillator

HXT

1

PLL

PLL FOUT

1/4

HIRC

LIRCEN (CLK_PWRCTL[3])M471V/M471K/M471C SERIES DATASHEETInternal 38.4
kHz Oscillator(LIRC)

LIRC

Figure 6.3-2 Clock Generator Block Diagram

Dec. 22, 2022

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M471V/M471K/M471C Series
6.3.3

System Clock and SysTick Clock

The system clock has 5 clock sources, which were generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shownin Figure 6.3-3.

HCLKSEL(CLK_CLKSEL0[2:0])
HIRC
LIRC
PLLFOUT
LXT
HXT

111

CPUCLK

011

1/(HCLK_N+1)
1/(HCLKDIV+1)
HCLKDIV(CLK_CLKDIV0[3:0])

010
001
000

CPU in Power Down Mode

HCLK
PCLK0
PCLK1

CPU
AHB
APB0
APB1

Figure 6.3-3 System Clock Block Diagrams
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.

M471V/M471K/M471C SERIES DATASHEETWhen HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIEN (CLK_CLKDCTL[5]) is
set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the clock
stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after
re-enable action and user can switch system clock to HXT again.
Figure 6.3-4 shows The HXT clock stops detection and system clock switches to HIRC procedure

Dec. 22, 2022

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M471V/M471K/M471C Series

Set HXTFDEN To enable
HXT clock detectorNO

HXTFIF = 1?

YES

System clock source =“HXT” or “PLL with
HXT” ?

System clock keep
original clock

NO

YES

Switch system clock to
HIRC

Figure 6.3-4 HXT Stop Protect Procedure

HIRC_period * 2048 < HXT_period * UPERBDHIRC_period* 2048 > HXT_period* LOWERBD

The clock source of SysTick in Cortex® -M4 core can use CPU clock or external clock(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock
source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block
diagram is shown in Figure 6.3-5.
STCLKSEL(CLK_CLKSEL0[5:3])
HIRC
HCLK
HXT
LXT
HXT

1/2

111

1/2

011

1/2

010

STCLK
001
000

Figure 6.3-5 SysTick Clock Control Block Diagram

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M471V/M471K/M471C SERIES DATASHEETThe formula of UPERBD and LOWERBD as below

M471V/M471K/M471C Series
6.3.4

Peripherals Clock

Each peripheral clock has its own clock source selection. Refer to the CLK_CLKSEL1, CLK_CLKSEL2
and CLK_CLKSEL3 register.

6.3.5

Power-down Mode Clock

When entering Power-down mode, system clocks, some clock sources and some peripheral clocks
are disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:




6.3.6

Clock Generator–

38.4 kHz internal low speed RC oscillator (LIRC) clock–32.768 kHz external low speed crystal oscillator (LXT) clock

Peripherals Clock (When the modules adopt LXT or LIRC as clock source)

Clock Output

This device is equipped with a power-of-2 frequency divider which is composed of 16 chained divideby-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer isreflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with thefrequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0
to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low
state and stays in low state.

M471V/M471K/M471C SERIES DATASHEETCLKOEN(CLK_CLKOCTL[4])Enabledivide-by-2 counter

1/2

HIRC
HCLK
LXT
HXT

1/22

FREQSEL(CLK_CLKOCTL[3:0])

16 chained
divide-by-2 counter
1/23

…...

1/215

DIV1EN(CLK_CLKOCTL[5])

1/216
0000
0001
:
:
1110
1111

11
10

CLK1HZEN(CLK_CLKOCTL[6])16 to 1
MUX

0
0
1

CLKO

1

01
00
RTCCKSEL(RTC_LXTCTL[7])CLKOSEL (CLK_CLKSEL1[29:28])
LXT

0

LIRC
1

/32768(LXT)
Or/38912(LIRC)

1 Hz clock from RTC

Figure 6.3-6 Clock Output Block Diagram

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6.4 Flash Memeory Controller (FMC)
6.4.1

Overview

The FMC is equipped with 256/512 Kbytes on-chip embedded Flash for application and configurable
Data Flash to store some application dependent data. Thus, the total size of application rom (APROM)
is 256/512 Kbytes. A User Configuration block provides for system initiation. A 4 Kbytes loader ROM(LDROM) is used for In-System-Programming (ISP) function. A 4 Kbytes cache with zero wait cycle isused to improve Flash access performance. This chip also supports In-Application-Programming (IAP)
function. User switches the code executing without chip reset after the embedded Flash is updated.

6.4.2

Features
Supports dual-bank Flash macro for safe firmware upgradeSupports 256/512 Kbytes application ROM (APROM)

Supports 4 Kbytes loader ROM (LDROM)Supports 4 XOM (eXecution Only Memory) regions to conceal user program in APROM.

Supports 16 bytes User Configuration block to control system initiation

Supports 2 Kbytes page erase for all embedded FlashSupports bank erase for APROM, except for XOM regionsSupports 32-bit/64-bit and multi-word Flash programming functionSupports fast Flash programming verification functionSupports CRC32 checksum calculation functionSupports Flash all one verification functionSupports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memorySupports cache memory to improve Flash access performance and reduce power
consumption (4K cache 1 way)

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6.5 Data Flash Memory Controller (DFMC)
6.5.1

Overview

The DFMC is equipped with 32 Kbytes on-chip Data Flash to store some application dependent data.

6.5.2

FeaturesSupports 32 Kbytes application Data FlashSupports 256 bytes page erase for all embedded FlashSupports CRC32 checksum calculation functionSupports Data Flash all one verification functionSupports In-System-Programming (ISP) to update embedded Data Flash memory

FMC Features

M471

32 KB Data ROM●

256 B page erase●

Mass erase for Data Flash.

●

CRC32 checksum calculation function●

hardware Writer mode and In-Circuit-Programming (ICP)●smart entry detection on Writer mode and ICP●

M471V/M471K/M471C SERIES DATASHEET

Table 6.5-1 FMC Features Comparison Table at Different Chip

Dec. 22, 2022

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M471V/M471K/M471C Series
6.6 General Purpose I/O (GPIO)
6.6.1

Overview

This chip has up to 119 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 119 pins are arranged in 9 ports named as PA, PB, PC, PD, PE, PF,
PG, PH and PI. PA, PB, PD, PE and PF has 16 pins on port. PC has 15 pins on port. PG has 10 pins
on port. PH has 8 pins on port. PI has 6 pins on port. Each of the 119 pins is independent and has thecorresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]).

6.6.2

Features

Four I/O modes:–

Quasi-bidirectional mode–

Push-Pull Output mode–

Open-Drain Output mode–

Input only with high impendence mode

TTL/Schmitt trigger input selectable

I/O pin can be configured as interrupt source with edge/level setting

Supports High Drive and High Slew Rate I/O modeConfigurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset–

CIOINI = 1, all GPIO pins in input mode after chip resetSupport independent pull-up control

Enabling the pin interrupt function will also enable the wake-up function

Dec. 22, 2022

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M471V/M471K/M471C Series
6.7

PDMA Controller (PDMA)

6.7.1

Overview

The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. Thishas the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
The PDMA controller has a total of 6 channels and each channel can perform transfer between
memory and peripherals or between memory and memory.

6.7.2

FeaturesSupports 6 independently configurable channels

Selectable 2 level of priority (fixed priority or round-robin priority)Supports transfer data width of 8, 16, and 32 bits



Supports source and destination address increment size can be byte, half-word, word or
no increment

Supports software and UART, SPI, EPWM, TIMER, EADC, DAC, ACMP and I2C request

Supports Scatter-Gather mode to perform sophisticated transfer through the use of thedescriptor link list tableSupports single and burst transfer typeSupports time-out function on channel 0 and channel1

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
6.8 Timer Controller (TMR)
6.8.1

Overview

The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement atimer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement byexternal capture pins.
The timer controller also provides four PWM generators. Each PWM generator supports one PWM
output and two selectable PWM output channels (TMx or TMx_EXT). The output state of PWM output
pin can be control by polarity control, output enable control and output channel select.

6.8.2

Features
Timer Function Features
Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescalecounter

Independent clock source for each timer

Provides one-shot, periodic, toggle-output and continuous counting operation modes

24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])

Supports event counting function

24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])

Supports external capture pin (TMx_EXT) event for interval measurement

Supports external capture pin (TMx_EXT) event to reset 24-bit up counterSupports internal clock (HIRC, LIRC) and external clock (HXT, LXT) for capture eventSupports chip wake-up from Idle/Power-down mode if a timer interrupt signal isgeneratedSupport Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
BPWM, EPWM, EADC, DAC and PDMA functionSupports internal capture triggered while internal ACMP output signal transitionSupports Inter-Timer trigger mode
PWM Function FeaturesSupports PWM generator with two selectable output channels

Supports 16-bit PWM counter–Up count operation type–One-shot or auto-reload counter operation modeSupports 8-bit prescale from 1 to 256

Supports 16-bit compare register and period register and double buffer for period registerand compare registerSupports tri-state enable and polarity control for each PWM selectable output channels

Supports interrupt on the following events:–



PWM period point, up-count compared point events

Supports wake-up when interrupt occurs when clock source is LXT or LIRC

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M471V/M471K/M471C SERIES DATASHEETM471V/M471K/M471C Series

PWM can generator output in Power-down modeSupports trigger EADC, PDMA, and DAC on the following events:–

PWM period point and up-count compared point events

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
6.9 Watchdog Timer (WDT)
6.9.1

Overview

The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timersupports the function to wake up system from Idle/Power-down mode.

6.9.2

Features

20-bit free running up counter for WDT time-out intervalSelectable time-out interval (24 ~ 220) and the time-out interval is 0.416 ms ~ 27.306 s if
WDT_CLK = 38.4 kHz.



System kept in reset state for a period of (1 / WDT_CLK) * 63Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay periodSupports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]in Config0 registerSupports WDT time-out wake-up function only if WDT clock source is selected as 38.4
kHz or LXT.

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
6.10

Window Watchdog Timer (WWDT)

6.10.1

Overview

The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software running to uncontrollable status by any unpredictable condition.

6.10.2Features

6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexibleSupports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter

WWDT counter suspends in Idle/Power-down mode

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
6.11

Real Time Clock (RTC)

6.11.1

Overview

The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers
programmable time tick and alarm match interrupts. The data format of time and calendar messages
are expressed in BCD format. A digital frequency compensation feature is available to compensate
external crystal oscillator frequency accuracy.

6.11.2Features
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check.

Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM.

Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable
in RTC_TAMSK and RTC_CAMSK.



Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register.

Supports Leap Year indication in RTC_LEAPYEAR register.

Supports Day of the Week counter in RTC_WEEKDAY register.



Frequency of RTC clock source compensate by RTC_FREQADJ register.

All time and calendar message expressed in BCD format.

Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64,
1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.



Supports RTC Time Tick and Alarm Match interrupt.

Supports 1 Hz clock output.

Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal isgenerated.

Supports Daylight Saving Time software control in RTC_DSTCTL.

Dec. 22, 2022

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M471V/M471K/M471C SERIES DATASHEETM471V/M471K/M471C Series
6.12

EPWM Generator and Capture Timer (EPWM)

6.12.1

Overview

The chip provides two EPWM generators － EPWM0 and EPWM1. Each EPWM supports 6 channelsof EPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
EPWM counter with 16-bit comparator. The EPWM counter supports up, down and up-down countertypes. EPWM uses comparator compared with counter to generate events. These events use to
generate EPWM pulse, interrupt and trigger signal for EADC/DAC to start conversion.
The EPWM generator supports two standard EPWM output modes: Independent mode andComplementary mode, they have difference architecture. There are two output functions based onstandard output modes: Group function and Synchronous function. Group function can be enabled
under Independent mode or complementary mode. Synchronous function only enabled undercomplementary mode. Complementary mode has two comparators to generate various EPWM pulse
with 12-bit dead-time generator and another free trigger comparator to generate trigger signal for
EADC. For EPWM output control unit, it supports polarity output, independent pin mask and brakefunctions.
The EPWM generator also supports input capture function. It supports latch EPWM counter value tocorresponding register when input channel has a rising transition, falling transition or both transition ishappened. Capture function also support PDMA to transfer captured data to memory.

6.12.2Features
EPWM Function Features

M471V/M471K/M471C SERIES DATASHEETSupports maximum clock frequency up to maximum PLL frequency

Supports up to two EPWM modules, each module provides 6 output channels

Supports independent mode for EPWM output/Capture input channelSupports complementary mode for 3 complementary paired EPWM output channel–

Dead-time insertion independent control with 12-bit resolution–

Synchronous function for phase control–

Two compared values during one periodSupports 12-bit prescaler from 1 to 4096

Supports 16-bit resolution EPWM counter–Up, down and up/down counter operation typeSupports one-shot or auto-reload counter operation modeSupports group functionSupports synchronous functionSupports mask function and tri-state enable for each EPWM pinSupports brake function–

Brake source from pin, analog comparator and system safety events (clock failed,
SRAM parity error, Brown-out detection and CPU lockup).

–

Noise filter for brake source from pin–

Leading edge blanking (LEB) function for brake source from analog comparator–

Edge detect brake source to control brake state until brake interrupt cleared–

Level detect brake source to auto recover function after brake condition removed

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M471V/M471K/M471C SeriesSupports interrupt on the following events:–

EPWM counter matches 0, period value or compared value–

Brake condition happened

Supports trigger EADC/DAC on the following events:–

EPWM counter matches 0, period value or compared value–

EPWM counter match free trigger comparator compared value (only for EADC)–

Support EPWM trigger EADC event prescaler featureSupports PDMA transfer for Interrupt Flag Accumulator functionSupports EPWM output accumulator stop counter modeSupports Fault Detect Function.

Supports External Pin Trigger function
Capture Function FeaturesSupports 3-bit capture input noise filterSupports up to 12 capture input channels with 16-bit resolutionSupports rising or falling capture conditionSupports input rising/falling capture interrupt

Supports rising/falling capture with counter reload optionSupports PDMA transfer function for EPWM all channels

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series

6.13

Basic PWM Generator and Capture Timer (BPWM)

6.13.1

Overview

The chip provides two BPWM generators － BPWM0 and BPWM1. Each BPWM supports 6 channelsof BPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
BPWM counter with 16-bit comparator. The BPWM counter supports up, down and up-down countertypes, all 6 channels share one counter. BPWM uses the comparator compared with counter togenerate events. These events are used to generate BPWM pulse, interrupt and trigger signal for
EADC0 to start conversion. For BPWM output control unit, it supports polarity output, independent pin
mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value tocorresponding register when input channel has a rising transition, falling transition or both transition ishappened.

6.13.2Features
BPWM Function FeaturesSupports maximum clock frequency up to maximum PLL frequency.

Supports up to two BPWM modules; each module provides 6 output channels

Supports independent mode for BPWM output/Capture input channelSupports 12-bit prescalar from 1 to 4096

Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter–Up, down and up/down counter operation type

M471V/M471K/M471C SERIES DATASHEETSupports mask function and tri-state enable for each BPWM pinSupports interrupt in the following events:–



BPWM counter matches 0, period value or compared value

Supports trigger EADC0 in the following events:–

BPWM counter matches 0, period value or compared value

Capture Function FeaturesSupports up to 12 capture input channels with 16-bit resolutionSupports rising or falling capture conditionSupports input rising/falling capture interrupt

Supports rising/falling capture with counter reload option
M471

Trigger numbers for EADC

1

Table 6.13-1 BPWM Features Comparison Table

Dec. 22, 2022

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M471V/M471K/M471C Series
6.14

UART Interface Controller (UART)

6.14.1

Overview

The chip provides six channels of Universal Asynchronous Receiver/Transmitters (UART). The UART
controller performs serial-to-parallel conversion on data received from the peripheral and parallel-toserial conversion on data transmitted from the CPU. Each UART controller channel supports eleventypes of interrupts. The UART controller supports flow control function. The UART controller also
supports IrDA SIR, LIN, RS-485 and Single-wire function modes and auto-baud rate measuringfunction.

6.14.2FeaturesFull-duplex asynchronous communications

Separates receive and transmit 16/16 bytes or 1/1 byte entry FIFO for data payloads

Supports hardware auto-flow control

Programmable receiver buffer trigger levelSupports programmable baud rate generator for each channel individuallySupports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up functionSupports 8-bit receiver buffer time-out detection functionProgrammable transmitting data delay time between the last stop and the next START bit
by setting DLY (UART_TOUT[15:8])

Supports Auto-Baud Rate measurement and baud rate compensation function–

9600 bps for UART_CLK is selected LXT.

Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function

Fully programmable serial-interface characteristics

–Programmable number of data bit, 5-, 6-, 7-, 8- bit character–

Programmable PARITY bit, even, odd, no parity or stick PARITY bit generation anddetection–

Programmable STOP bit, 1, 1.5, or 2 STOP bit generation

Supports IrDA SIR function mode–

3/16 bit duration for normal mode

Supports LIN function mode (Only UART0/UART1 with LIN function)–

LIN master/slave mode–

Programmable break generation function for transmitter–

Break detection function for receiver

Supports RS-485 function mode–

RS-485 9-bit mode–

Hardware or software enables to program nRTS pin to control RS-485 transmission
directionSupports PDMA transfer functionSupports Single-wire function mode

Dec. 22, 2022

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M471V/M471K/M471C SERIES DATASHEETM471V/M471K/M471C Series

Supports baud rate compensation function
UART Feature

UART0/ UART1

UART2 ~ UART5

FIFO

16 Bytes

1 Bytes

Auto Flow Control (CTS/RTS)

√

√

IrDA

√

√

LIN

√

-

RS-485 Function Mode√√nCTS Wake-up√√

Incoming Data Wake-up

√

√

√

-

RS-485 Address Match (AAD mode)√
Wake-up-

Auto-Baud Rate Measurement√√

STOP bit Length

1, 1.5, 2 bit

1, 1.5, 2 bit

Word Length

5, 6, 7, 8 bits

5, 6, 7, 8 bits

Even / Odd Parity√√

Stick Bit√√

Baud Rate Compensation√-

ReceivedDatathreshold Wake-up

FIFO

reached

M471V/M471K/M471C SERIES DATASHEET

Table 6.14-1 M471V/M471K/M471C series UART Features

Dec. 22, 2022

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M471V/M471K/M471C Series
6.15

Serial Peripheral Interface (SPI)

6.15.1

Overview

The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains up to two sets of SPI controllers performing a serial-to-parallel conversion on data
received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device. Each SPI controller can be configured as a master or a slave device and supports
the PDMA function to access the data buffer. Each SPI controller also supports I2S mode to connect
external audio CODEC.

6.15.2Features–

Up to two sets of SPI controllers–

Supports Master or Slave mode operation–

Master mode up to 24 MHz–

Slave mode up to 24 MHz when SPI master device supports adjustment function of
RX data sampling clock–

Slave mode up to 18 MHz when SPI master device does not support adjustment
function of RX data sampling clock–

Configurable bit length of a transaction word from 4 to 32-bit–

Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO
buffers which depends on SPI setting of data width–

Supports MSB first or LSB first transfer sequence–

Supports Byte Reorder function–

Supports Byte or Word Suspend mode–

Supports PDMA transfer–

Supports 3-Wire, no slave selection signal, bi-direction interface–

Supports one data channel half-duplex transfer–

Supports receive-only mode

2

I S Mode–

Supports Master or Slave–

Capable of handling 8-, 16-, 24- and 32-bit word sizes–

Each provides two 4-level FIFO data buffers, one for transmitting and the other forreceiving–Supports monaural and stereo audio data–

Supports PCM mode A, PCM mode B, I2S and MSB justified data format–

Supports two PDMA requests, one for transmitting and the other for receiving

Dec. 22, 2022

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M471V/M471K/M471C SERIES DATASHEETSPI ModeM471V/M471K/M471C Series
6.16

I2C Serial Interface Controller (I2C)

6.16.1

Overview

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection andarbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are two sets of I2C controllers which support Power-down wake-up function.

6.16.2Features

2

The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to thebus. The main features of the I2C bus include:

M471V/M471K/M471C SERIES DATASHEETSupports up to two I2C ports



Master/Slave modeBidirectional data transfer between masters and slaves

Multi-master bus (no central master)Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1
Mbps)



Arbitration between simultaneously transmitting masters without corruption of serial dataon the bus

Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus



Serial clock synchronization used as a handshake mechanism to suspend and resumeserial transfer

Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up andtimer-out counter overflow

Programmable clocks allow for versatile rate control

Supports 7-bit addressing and 10-bit addressing modeSupports multiple address recognition ( four slave address with mask option)Supports Power-down wake-up functionSupports PDMA with one buffer capabilitySupports setup/hold time programmableSupports Bus Management (SM/PM compatible) function

Dec. 22, 2022

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M471V/M471K/M471C Series
6.17

Customize IR Receiver (CIR)

6.17.1

Overview

The CIR controller supports to receive data from the output pin of IR receiver. The received data will
be stored in registers and wait for further analysis.

6.17.2FeaturesSupports one channel CIR control signal receiver.

Supports 5 clock sources with 3-bit prescale for vary bit rate sampling.

Supports a digital filter to be used to filter out noise.

Supports observeing the noise filter output signal.

Supports input signal inversion.

Supports two 32-bit data registers and receive buffer full flag.

Supports Header, Data0, Data1, End and Special patterns.

Supports to receive data in Power-down mode and be woken up by specified first 8 bits
data pattern. (User needs to switch clock source to LIRC before entering Power-down
mode.)



Offers 11 different kinds of interrupt options and flags.



Supports receive error detection.

Supports three receive formats for the CIR control signal waveform.



Clock PCLK frequency must be faster than CIR internal clock CIR0_CLK frequency.

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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M471V/M471K/M471C Series
6.18

CRC Controller (CRC)

6.18.1

Overview

The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.

6.18.2FeaturesSupports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32–

CRC-CCITT: X16 + X12 + X5 + 1–

CRC-8: X8 + X2 + X + 1–

CRC-16: X16 + X15 + X2 + 1–

CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

Programmable seed valueSupports programmable order reverse setting for input data and CRC checksumSupports programmable 1’s complement setting for input data and CRC checksumSupports 8/16/32-bit of data width–

8-bit write mode: 1-AHB clock cycle operation–

16-bit write mode: 2-AHB clock cycle operation–

32-bit write mode: 4-AHB clock cycle operation

Supports using PDMA to write data to perform CRC operation

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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M471V/M471K/M471C Series
6.19

Pseudo Random Number Generator (PRNG)

6.19.1

Overview

The PRNG core supports 64, 128, 192 and 256 bits random number generation.

6.19.2Features

PRNG–

Supports 64, 128, 192 and 256 bits random number generation

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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M471V/M471K/M471C Series
6.20

Enhanced 12-bit Analog-to-Digital Converter (EADC)

6.20.1

Overview

The chip contains one 12-bit successive approximation analog-to-digital converter (SAR EADC
converter) with 24 external input channels and 3 internal channels. The EADC converter can bestarted by software trigger, EPWM0/1 triggers, BPWM0/1 triggers, timer0~3 overflow pulse triggers,
ADINT0 interrupt EOC (End of conversion) and ADINT1 interrupt EOC pulse trigger and external pin(EADC0_ST) input signal.

6.20.2Features

M471V/M471K/M471C SERIES DATASHEET

Analog input voltage range: 0~ VREF (Max to 5.5V)

Reference voltage from VREF pin or AVDD

12-bit resolutionUp to 24 single-end analog external input channels or 1 pair differential analog input
channelsUp to 3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP) ,and DAC0 output

Four EADC interrupts (ADINT0~3) with individual interrupt vector addresses for EADC



Maximum EADC clock frequency is 36 MHz for EADCUp to 1.895 MSPS conversion rate for EADC



Supports calibration function and calibration interrupt

Supports internal reference voltage VREF: 2.048V, 2.56V, 3.072V, and 4.096V.

Supports power-down mode and ultra low frequency modeUp to 27 sample modules–

Sample modules0~23 is configurable for EADC converter channel (EADC_CH0~23)
and trigger source for each EADC–

Sample module 24~26 is fixed for channel 24, 25, 26 input sources as band-gap
voltage, temperature sensor, and DAC output–

Double buffer for sample control logic module 0~3–

Configurable sampling time for each sample module–

Conversion results are held in 27 data registers with valid and overrun indicators.



Averaging (2n times, n=0~8) to support up to 12-bit result and over-sampling, or called
Accumulation, (2n times, n=0~8) to support up to 16-bit result

Any EADC conversion of each EADC can be started by:–Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~26)–

External pin EADC0_ST–

Timer0~3 overflow pulse triggers–

ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers–

EPWM/BPWM triggers

Supports PDMA transferConversion Result Monitor by Compare Mode

Dec. 22, 2022

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M471V/M471K/M471C Series
6.21

Digital to Analog Converter (DAC)

6.21.1

Overview

The DAC module is a 8-bit, voltage output digital-to-analog converter. It can be configured to used inconjunction with the PDMA controller. The DAC integrates a voltage output buffer that can be used toreduce output impendence and drive external loads directly without having to add an external
operational amplifier.

6.21.2Features

Analog output voltage range: 0~AVDD.

Supports 8-bit output mode.

Rail to rail settle time 5us.

Supports up to one 8-bit 200 KSPS voltage type DAC without buffer.



Reference voltage from internal reference voltage (INT_VREF), VREF pin.

Supports software and hardware trigger, including Timer0~3, EPWM0, EPWM1, andexternal trigger pin to start DAC conversion.

Supports PDMA mode.

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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M471V/M471K/M471C Series
6.22

Analog Comparator Controller (ACMP)

6.22.1

Overview

The chip provides two comparators. The comparator output is logic 1 when positive input is greaterthan negative input; otherwise, the output is 0. Each comparator can be configured to generate aninterrupt when the comparator output value changes.

6.22.2Features

Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)Up to two rail-to-rail analog comparatorsSupports hysteresis function–

Supports programmable hysteresis window: 0mV, 10mV, 20mV, 30mV, 40mV, 50mVSupports wake-up function

Selectable input sources of positive input and negative input



ACMP0 supports:–

4 multiplexed I/O pins at positive sources:–

M471V/M471K/M471C SERIES DATASHEETACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3

4 negative sources:

ACMP0_N

Supports Comparator Reference Voltage (CRV)Internal band-gap voltage (VBG)

DAC0 output (DAC0_OUT)

ACMP1 supports:–

4 multiplexed I/O pins at positive sources:–

ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3

4 negative sources:

ACMP1_N

Supports Comparator Reference Voltage (CRV)Internal band-gap voltage (VBG)

DAC0 output (DAC0_OUT)Shares one ACMP interrupt vector for all comparators

Interrupts generated when compare results change (Interrupt event condition isprogrammable)

Supports triggers for break events and cycle-by-cycle control for EPWM

Supports window compare mode and window latch modeSupports offset calibration

Dec. 22, 2022

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M471V/M471K/M471C Series
7

APPLICATION CIRCUIT

7.1

Power Supply Scheme
as close to AVDD as possible
L=30Z

EXT_PWR
AVDD

1uF+0.1uF+0.01uF

AVSS

L=30Z

10uF+0.1uF
as close to the
EXT_PWR as possible
VREF

2.2uF+1uF+470pF

L=30Z
as close to VREF as possible

LDO_CAPVSS

1uF
as close to LDO as possible
VDD

M471V/M471K/M471C SERIES DATASHEETVSS

EXT_VSS

0.1uF*Nas close to VDD/VDDIO/VBAT as possible

Dec. 22, 2022

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M471V/M471K/M471C Series
7.2

Peripheral Application Scheme
DVCC

VDDIO

100K

100K

VBAT

VDD
ICE_DAT

SWD
Interface

ICE_CLKnRESET
VSS

20pF
XT1_IN

DVCC

4~24 MHz
crystal

20pF

XT1_OUT

Crystal

20pF

SPI_SSSPI_CLKSPI_MISO
SPI_MOSI

CS

VDD

CLK
MISO
MOSI

VSS

SPI Device

X32_IN32.768 kHz
crystal

20pF

DVCC

X32_OUT

M471 Series

DVCC

Reset
Circuit

DVCC

10K

4.7K

4.7K

I2C_SCL

CLK

VDD

I2C_SDADIOVSSI2C Device

nRST

10 uF

M471V/M471K/M471C SERIES DATASHEETLDO_CAPLDO

RS 232 Transceiver PC COM Port

2.2 uF
UART_RXD

ROUT

RIN

UART_TXD

TIN

TOUT

UART

Audio codec

Line InI2S

NUC8822

Line Out

Dec. 22, 2022

Page 126 of 178

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M471V/M471K/M471C Series
8

ELECTRICAL CHARACTERISTICS

8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is notguaranteed.

8.1.1

Voltage Characteristics

Symbol

Min

Max

Unit

DC power supply

-0.3

6.5

V

ΔVDD

Variations between different VDD power pins

-

50

mV

|VDD –AVDD|

Allowed voltage difference for VDD and AVDD

-

50

mV

Variations between different ground pins

-

50

mV

Allowed voltage difference for VSS and AVSS

-

50

mV

VSS-0.3

6.5

V

VDD-V

[*1]
SS

ΔVSS
|VSS - AVSS|
VIN

Description

Input voltage on any other pin[*2]Notes:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Refer to Table 8.1-2 for the values of the maximum allowed injected current

Table 8.1-1 Voltage Characteristics

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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M471V/M471K/M471C Series
8.1.2

Current Characteristics
SymbolDescription

Min

Max

ΣIDD[*1]

Maximum current into VDD

-

200

ΣISS

Maximum current out of VSS-

100

Maximum current sunk by a I/O Pin-

20

Maximum current sourced by a I/O Pin-

20

Maximum current sunk by total I/O Pins[*2]-100Maximum current sourced by total I/O Pins[*2]-100

IINJ(PIN) [*3]

Maximum injected current by a I/O Pin-±5

ΣIINJ(PIN) [*3]

Maximum injected current by total I/O Pins

-

±25

IIO

Unit

mA

Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.

Table 8.1-2 Current Characteristics

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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M471V/M471K/M471C Series
8.1.3

Thermal Characteristics

The average junction temperature can be calculated by using the following equation:
TJ = TA + (PD x θJA )

TA = ambient temperature (℃)

θJA = thermal resistance junction-ambient (℃/Watt)

PD

Symbol= sum of internal and I/O power dissipation
Description

Min

Typ

Max

TA

Operating ambient temperature

-40

-

105

TJ

Operating junction temperature

-40

-

125

TST

Storage temperature

-65

-

150

-

58

-

℃/Watt-46-℃/Watt-38.5-℃/Watt

Thermal resistance junction-ambient
64-pin LQFP(7x7 mm)
θJA[*1]

Thermal resistance junction-ambient
100-pin LQFP(14x14 mm)
Thermal resistance junction-ambient
128-pin LQFP(14x14 mm)

Unit

℃

Note:
1.

Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions

Table 8.1-3 Thermal Characteristics

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M471V/M471K/M471C Series
8.1.4

EMC Characteristics

8.1.4.1

Electrostatic discharge (ESD)

For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.1.4.2

Static latchup

Two complementary static tests are required on six parts to assess the latchup
performance:A supply overvoltage is applied to each power supply pinA current injection is applied to each input, output and configurable I/O pin

8.1.4.3

Electrical fast transients (EFT)

In some application circuit compoment will produce fast and narrow high-frequency trasnients burstsof narrow high-frequency transients on the power distribution system..
Inductive loads:–

Relays, switch contactors–

Heavy-duty motors when de-energized etc.

The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 byInternational ElectrotechnicalCommission (IEC).
SymbolDescription

Min

Typ

Max

Unit

M471V/M471K/M471C SERIES DATASHEETVHBM[*1]

Electrostatic discharge,human body mode

-8K

-

8K

VCDM[*2]

Electrostatic discharge,charge device model

-1K

-

1K

VMM[*]

Electrostatic discharge,machine model

-400

-

400

Pin current for latch-up[*3]

-350

-

350

mA

Fast transient voltage burst

-4.4

-

+4.4

kV

LU

[*3]

VEFT[*4] [*5]V

Notes:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.

Table 8.1-4 EMC Characteristics

Dec. 22, 2022

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Rev 1.40

M471V/M471K/M471C Series
8.1.5

Package Moisture Sensitivity (MSL)The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.

64-pin LQFP(7x7 mm)

Pacakge

MSL

[*1]

MSL 3

100-pin LQFP(14x14 mm) [*1]

MSL 3

[*1]

MSL 3

128-pin LQFP(14x14 mm)
Note:

1. Determined according to IPC/JEDEC J-STD-020

Table 8.1-5 Package Moisture Sensitivity (MSL)

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

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Rev 1.40

M471V/M471K/M471C Series
8.1.6

Soldering Profile

Figure 8.1-1 Soldering profile from J-STD-020C

M471V/M471K/M471C SERIES DATASHEET

Porfile Feature

Pb Free Package

Average ramp-up rate (217℃ to peak)

3℃/sec. max

Preheat temperature 150℃ ~200℃

60 sec. to 120 sec.

Temperature maintained above 217℃

60 sec. to 150 sec.
> 30 sec.

Time with 5℃ of actual peak temperature
Peak temperature range

260℃

Ramp-down rate

6℃/sec ax.

Time 25℃ to peak temperature

8 min. max

Note:
1.

Determined according to J-STD-020C

Table 8.1-6 Soldering Profile

Dec. 22, 2022

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Rev 1.40

M471V/M471K/M471C Series
8.2 General Operating Conditions(VDD-VSS = 2.5 ~ 5.5V, TA = 25C, HCLK = 48 MHz unless otherwise specified.)
SymbolParameter

Min

Typ

Max

Unit

TA

Temperature

-40

-

105

℃

fHCLK

Internal AHB clock frequency

-

-

120

MHz

VDD

Operation voltage

2.5

-

5.5

AVDD[*1]

Analog operation voltage

VREF

Analog reference voltage

2.5

-

AVDD

VLDO

LDO output voltage

-

1.8

-

VBG

Band-gap voltage

1.18

1.21

1.245

V

TVBG_ADC[*3]

ADC sampling time when reading
the band-gap voltage

10

-

-

S

CLDO[*2]

LDO output capacitor on each pin

RESR[*3]

ESR of CLDO output capacitor

-

-

0.5

Ω

IRUSH[*3]InRush current on voltage
regulator power-on (POR or
wakeup from Standby)

-

100

400

mA

ERUSH[*3]InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)

-

1.8

-

µC

Test Conditions

VDD
V

1

µF

VDD = 1.8 V, TA = 105 °C,
IRUSH = 90 mA for 80µs

1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2. To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and theclosest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
3. Guaranteed by design, not tested in production

Table 8.2-1 General operating conditions

Dec. 22, 2022

Page 133 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETNote:M471V/M471K/M471C Series
8.3 DC Electrical Characteristics
8.3.1

Supply Current Characteristics

The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.


All GPIO pins are in push pull mode and output high.



The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature(TA), and the typical values for TA= 25 °C and VDD = 2.5 ~ 5.5 V unless otherwise
specified.



VDD = AVDDWhen the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK.



Program run CoreMark® code in Flash.
Typ [*1]

SymbolConditions

Max[*1][*2]

FHCLK

Unit
TA = 25 °C

TA = 25 °C

TA = 85 °C

TA = 105 °C

120 MHz

43.93

51.25

52.50

53.80

100 MHz

35.37

39.06

40.40

41.75

96 MHz

35.02

38.66

40.05

41.40

72 MHz

26.82

30.47

31.72

32.98

60 MHz

22.72

26.38

27.54

28.78

48 MHz

16.23

16.82

17.67

18.74

24 MHz

8.68

9.01

9.84

10.87

12 MHz

4.85

5.06

5.86

6.89

4 MHz

2.30

2.41

3.22

4.22

24 MHz

9.41

13.05

14.02

15.15

12 MHz

5.64

9.27

10.18

11.27

4 MHz

3.10

6.75

7.60

8.67

Normal run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals disable

38.4 kHz

0.106

0.147

0.930

1.923

HCLK is set as LIRC or LXT
clock

32 kHz

0.103

0.150

0.934

1.937

Normal run mode with PL0(PLSEL = 00), executed from
Flash, all peripherals enable

120 MHz

63.63

72.69

74.42

76.14

100 MHz

58.82

62.99

64.98

66.59

Normal run mode with PL0(PLSEL = 00), executed from
Flash, all peripherals disable
HCLK is set as PLL clock(fPCLK0, 1 = 1/2 fHCLK.)

M471V/M471K/M471C SERIES DATASHEET

Normal run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals disable
HCLK is set as PLL clock

IDD_RUN

Normal run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals disable
HCLK is set as HIRC, HXT
clock

mA

HCLK is set as PLL clock(fPCLK0,
1=
1/2 fHCLK.)
Normalrun
modewith PL1

Dec. 22, 2022

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Rev 1.40

M471V/M471K/M471C Series(PLSEL = 01), executed from
Flash, all peripherals enable

96 MHz

57.57

61.66

63.67

65.30

HCLK is set as PLL clock

72 MHz

43.86

47.86

49.59

51.08

60 MHz

36.99

40.94

42.53

43.95

48 MHz

25.82

26.94

27.96

29.09

24 MHz

16.30

17.04

18.01

19.09

12 MHz

10.15

10.65

11.54

12.60

4 MHz

6.05

6.37

7.24

8.26

24 MHz

15.19

18.93

20.10

21.30

12 MHz

9.09

12.79

13.80

14.96

4 MHz

5.01

8.70

9.60

10.70

Normal run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals enable

38.4 kHz

0.113

0.151

0.936

1.930

HCLK is set as LIRC or LXT
clock

32 kHz

0.111

0.158

0.944

1.943

Normal run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals enable
HCLK is set as HIRC, HXT
clock

Notes:
1. When analog peripheral blocks such as DAC, ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional
power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.

Table 8.3-1 Current consumption in Normal Run mode
Typ [*1]
SymbolConditions

FHCLK

Unit
TA = 25 °C

TA = 25 °C

TA = 85 °C

TA = 105 °C

120 MHz

11.46

16.37

17.35

18.53

100 MHz

9.67

13.44

14.40

15.52

96 MHz

10.34

14.05

15.07

16.21

72 MHz

8.26

11.97

12.91

14.02

60 MHz

7.23

10.93

11.84

12.95

48 MHz

3.77

3.97

4.79

5.81

24 MHz

2.43

2.57

3.38

4.39

12 MHz

1.73

1.84

2.64

3.64

4 MHz

1.26

1.35

2.13

3.14

24 MHz

3.20

6.87

7.71

8.78

12 MHz

2.53

6.19

7.03

8.10

4 MHz

2.07

5.72

6.55

7.60

38.4 kHz

0.096

0.140

0.922

1.915

HCLK is set as PLL clock(fPCLK0, 1 = 1/2 fHCLK.)
Idle run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals disable
HCLK is set as PLL clock

IDD_IDLE

Idle run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals disable
HCLK is set as HIRC, HXT
clock

Idle run mode with PL1(PLSEL = 01), executed from

Dec. 22, 2022

Page 135 of 178

mA

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

Idle run mode with PL0(PLSEL = 00), executed from
Flash, all peripherals disable

Max[*1][*2]M471V/M471K/M471C Series
Flash, all peripherals disable
32 kHz

0.095

0.141

0.924

1.923

120 MHz

32.72

40.27

41.68

43.05

100 MHz

34.40

38.64

40.34

41.79

96 MHz

34.10

38.25

39.99

41.46

72 MHz

26.16

30.20

31.70

33.06

60 MHz

22.20

26.18

27.56

28.87

48 MHz

13.80

14.54

15.55

16.66

24 MHz

10.23

10.77

11.71

12.80

12 MHz

7.07

7.46

8.35

9.41

4 MHz

4.97

5.25

6.10

7.14

24 MHz

9.22

12.98

14.04

15.21

12 MHz

6.12

9.83

10.80

11.92

4 MHz

4.03

7.70

8.61

9.69

Idle run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals enable

38.4 kHz

0.104

0.144

0.927

1.93

HCLK is set as LIRC or LXT
clock

32 kHz

0.103

0.150

0.933

1.941

HCLK is set as LIRC or LXT
clock
Idle run mode with PL0(PLSEL = 00), executed from
Flash, all peripherals enable
HCLK is set as PLL clock(fPCLK0, 1 = 1/2 fHCLK.)
Idle run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals enable
HCLK is set as PLL clock

Idle run mode with PL1(PLSEL = 01), executed from
Flash, all peripherals enable
HCLK is set as HIRC, HXT
clock

Notes:

M471V/M471K/M471C SERIES DATASHEET

1.

When analog peripheral blocks such as DAC, ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.

2.

Based on characterization, not tested in production unless otherwise specified.

Table 8.3-2 Current consumption in Idle mode

Dec. 22, 2022

Page 136 of 178

Rev 1.40

M471V/M471K/M471C Series
LIRC LXT[*1]
SymbolTest Conditions

Power-down mode,
all peripherals disable

Power-down mode,
WDT/Timer/UART/RTC enable and run

Typ[*2]38.4 32.768
kHz
kHz TA = 25 °C

Max[*3][*4]TA = 25 °C

TA = 85 °C

TA = 105°C--

24.348

62

903

2015

-

V

26.066

65

913

2027

V

-

26.236

65

913

2027

V

V

27.469

67

919

2037

IDD_PD

UnitµA
Power-down mode,
WDT/Timer/UART enable and run

Power-down mode,
WDT/Timer/UART/RTC enable and run,
WDT use LIRC, UART/Timer/RTC use LXT

Notes:
2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as DAC, ADC and ACMP are ON, an additional power consumption should beconsidered.
5. Based on characterization, tested in production.

Table 8.3-3 Chip Current Consumption in Power-down mode

Dec. 22, 2022

Page 137 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

1. Crystal used: AURUM XF66RU000032C0 with a CL of 12.5 pF for L2 gain level.

M471V/M471K/M471C Series
8.3.2

On-Chip Peripheral Current Consumption


The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.



All GPIO pins are set as output high of push pull mode without multi-function.



HCLK is the system clock, fHCLK = 120 MHz, fPCLK0, 1 = 1/2 fHCLK.



The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
IDD[*1]

PDMA0_ON

1038

ISP_ON~0STCLK_ON

418

CRC_ON144

FMCIDLE_ON

1738

GPICK_ON

204

GPACK_ON

201

GPBCK_ON

211

GPCCK_ON203

GPDCK_ON203

GPECK_ON

201

GPFCK_ON

211

GPGCK_ON

200

GPHCK_ON

216

WDT_ON552

RTC_ON104

TMR0_ON

607

TMR1_ON

602

TMR2_ON

616

TMR3_ON

621

CLKO_ON610

ACMP01_ON

524

I2C0_ON230

I2C1_ON

195

SPI0_ON

1571

SPI1_ON

1595

UART0_ON

1014

UART1_ON1267

M471V/M471K/M471C SERIES DATASHEET

Peripheral

Unit

µA

Dec. 22, 2022

Page 138 of 178

Rev 1.40

M471V/M471K/M471C Series
UART2_ON996

UART3_ON984

UART4_ON957

UART5_ON956

ADC_ON1344

DAC0_ON69

CIR0_ON

242

EPWM0_ON967

EPWM1_ON925

BPWM0_ON

227

BPWM1_ON194

PRNG_ON

154

Notes:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
4. When the DAC is turned on, add an additional power consumption per DAC for the analog part.

Table 8.3-4 Peripheral Current Consumption

8.3.3

Wakeup Time from Low-Power Modes

Symbol

Typ

Max

Unit

Wakeup from IDLE mode

5

6cyclesWakeup from normal Power-down mode

15.2

18

uS

tET_IDLEEnter to IDLE mode

1

1cyclestET_NPDEnter to normal Power-down mode

10

13cyclestWU_IDLEtWU_NPD[*1][*2]Parameter

Notes:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
instruction.

Table 8.3-5 Low-power mode wakeup timings

Dec. 22, 2022

Page 139 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETThe wakeup times given in Table 8.2-1 is measured on a wakeup phase with a 48 MHz HIRC
oscillator.

M471V/M471K/M471C Series
8.3.4

I/O Current Injection Characteristics

In general, I/O current injection due to external voltages below VSS or above VDD should be avoided
during normal product operation. However, the analog compoenent of the MCU is most likely to beaffected by the injection current , but it is not easily clarified when abnormal injection accidentally
happens. It is recommended to add a Schottky diode (pin to ground or pin to VDD) to pins that include
analog function which may potentially injection currents.

SymbolParameter

IINJ(PIN) Injected current by a I/O Pin

Negative
injection

Positive
injection-00Injected current on nReset pins

-00Injected current on PF2~PF5, PA10,mA PA11 and PB0~PB15 for analog
input function-5+5Injected current on any other I/O
except analog input pin

Unit

Test Condition

Table 8.3-6 I/O current injection characteristics

8.3.5

I/O DC Characteristics

8.3.5.1

PIN Input Characteristics

SymbolParameter
Input low voltage (Schmitt trigger)

Min

Typ

Max

0

-

0.3*VDD

0

-

0.8

VIL

M471V/M471K/M471C SERIES DATASHEET

Input high voltage (Schmitt trigger)-

0.7

VDD = 2.7 V

0

-

0.5

VDD = 2.5 V

0.7*VDD

-

VDD

2

-

VDD

VDD = 5.5 V
V

Input high voltage (TTL trigger)

Hysteresis voltage of schmitt input

1.5

-

VDD

VDD = 3.3 V

1.1

-

VDD

VDD = 2.5 V-

0.2*VDD

-

-1

-

1

V
VSS < VIN < VDD,
Open-drain or input only mode
A

Input leakage current-1

RPU[*1]

VDD = 4.5 V

0

VIH

ILK[*2]

Test Conditions

V
Input low voltage (TTL trigger)

VHY[*1]

Unit

Pull up resistor

-

1

77

VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pinskΩ VDD =5.5V

Notes:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.

Table 8.3-7 I/O input Characteristics

Dec. 22, 2022

Page 140 of 178

Rev 1.40

M471V/M471K/M471C Series
8.3.5.2

I/O Output Characteristics

SymbolParameter

Source current for quasibidirectional mode andhigh level

Min (sim)

Typ

Max (sim)

Unit-70.99

-110

-

µA

-41.71-67-37.73-61-µA-5.696

-8.12

-

mA

-3.349

-4.87

-

mA

-3.032

-4.40

-

mA

9.486

14.07

-

mA

5.648

8.75

-

mA

5.147

8.05

-

mA

-

5

-

pF

-

µA

Test Conditions
VDD = 4.5 V
VIN=(VDD-0.4) V
VDD = 2.7 V
VIN=(VDD-0.4) V
VDD = 2.5 V
VIN=(VDD-0.4) V

ISR[*1] [*2]

Source current for pushpull mode and high level

ISK[*1] [*2]

CIO[*1]

Sinkcurrent for push-pullmode and low level

I/O pin capacitanceVDD = 4.5 V
VIN=(VDD-0.4) V
VDD = 2.7 V
VIN=(VDD-0.4) V
VDD = 2.5 V
VIN=(VDD-0.4) V
VDD = 4.5 V
VIN= 0.4 V
VDD = 2.7 V
VIN= 0.4 V
VDD = 2.5 V
VIN= 0.4 V

1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must notexceed ΣIDD and ΣISS.

Table 8.3-8 I/O output Characteristics

8.3.5.3

nRESET Input Characteristics

SymbolParameter

Min

Typ

Max

Unit

Test Conditions

VILR

Negative going threshold, nRESET--

0.3*VDDV

VIHR

Positive going threshold, nRESET

0.7*VDD--V

RRST[*1]

Internal nRESET pull up resistor

30

50

190

kΩ VDD=5.5V

-

20

-

26

-

38

tFR[*1]nRESET input filtered pulse time

Normal run and Idle modeµS
Power-down mode

Notes:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.

Dec. 22, 2022

Page 141 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

Notes:

M471V/M471K/M471C Series
Table 8.3-9 nRESET Input Characteristics

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 142 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4 AC Electrical Characteristics
8.4.1

48 MHz Internal High Speed RC Oscillator (HIRC)

The 48 MHz RC oscillator is calibrated in production.
Symbol.
VDD

Parameter

Min

Typ

Max

Unit

Operating voltage

2.5

-

5.5

V

Oscillator frequnecy

47.52

48

48.48

MHz

-1

-

1

%

-2[*1]

-

2[*1]

%

-

400

700

µA

11

20

µS

fHRC
Frequency drift over temperarure andvolatge

IHRC[*1]

Operating current

TS[*2]

Stable time

Test Conditions

TA = 25 °C,
VDD = 2.5 ~ 5.5V
TA = 25 °C,
VDD = 2.5 ~ 5.5V
TA = -40C ~ +105 °C,
VDD = 2.5 ~ 5.5V

TA = -40C ~ +105 °C,
VDD = 2.5 ~ 5.5V

Notes:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.

Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 143 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4.1

38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Min [*1]

TypMax [*1]

Unit

Operating voltage

2.5

-

5.5

V

Oscillator frequnecy

-

38.4

-

kHz

-2

-

2

%

-15

-

15

%

Symbol
VDD

Parameter

FLRC [*2]Frequency drift over temperarureand volatge

Test Conditions

TA = 25 °C,
VDD = 2.5V~5.5V
TA = 25 °C,
VDD = 2.5V~5.5V
TA=-40~105°C
VDD=2.5V~5.5V
Without software calibration

ILRC

Operating current

-

1

1.6

µA

TS

Stable time

-

200

500

μS

VDD = 3.3V
TA=-40~105°C
VDD=2.5V~5.5V

Notes:
1.

Guaranteed by characterization, not tested in production.

2.

The 38.4 kHz low speed RC oscillator can be calibrated by user.

3.

Guaranteed by design.

Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 144 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4.2

External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) Characteristics

The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained withtypical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in orderto minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
SymbolParameter

Min[*1]

Typ

Max[*1]

Unit

Test Conditions

VDD

Operating voltage

2.5

-

5.5

V

Rf

Internal feedback resister

-

250

-

kΩ

fHXT

Oscillator frequency

4

-

24

MHz

-

0.3

1

4 MHz, Gain = L0, CL = 12.5
pF

-

1

4

12 MHz, Gain = L1, CL = 12.5
pF

-

1.5

6.7

16 MHz, Gain = L2, CL = 12.5
pF

-

2.2

9

24 MHz, Gain = L3, CL = 12.5
pF

-

0.45

2

4 MHz, Gain = L0, CL = 30 pF

-

0.8

3.2

12 MHz, Gain = L1, CL = 20
pF

-

1.5

8

16 MHz, Gain = L2, CL = 10
pF

-

2

9

24 MHz, Gain = L3, CL = 10
pF

-

4.5

8.5

4 MHz, Gain = L0, CL = 12.5
pF

-

3

3.5

12 MHz, Gain = L1, CL = 12.5
pF

-

2.5

2.8

16 MHz, Gain = L2, CL = 12.5
pF

-

1.5

2

24 MHz, Gain = L3, CL = 12.5
pF

-

1.04

1.1

4 MHz, Gain = L0, CL = 30 pF

-

0.35

0.4

12 MHz, Gain = L1, CL = 20
pF

-

0.26

0.3

16 MHz, Gain = L2, CL = 10
pF

-

0.21

0.25

24 MHz, Gain = L3, CL = 10
pF

40

-

60

%

0.7*VDDV

Current consumption
IHXT

mA(Crystal type)

Current consumption
IHXT

mA(Resonator type)TS

mS(Crystal type)

Stable timeTS

mS
(Resonator type)

DuHXT

Duty cycle

Vpp

Peak-to-peak amplitude

Dec. 22, 2022

0.3*VDD 0.5*VDD

Page 145 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

Stable timeM471V/M471K/M471C Series
SymbolParameter

Min[*1]

Typ

Max[*1]

Unit

Test Conditions

Notes:
1. Guaranteed by characterization, not tested in production.

Table 8.4-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 146 of 178

Rev 1.40

M471V/M471K/M471C Series
SymbolRs

Parameter

Min [*1]

TypMax [*1]

-

-

150

Crystal @4 MHz, CL = 12.5 pF,
Gain = L0

-

-

120

Crystal @12 MHz, CL = 12.5
pF, Gain = L1

-

-

100

Crystal @16 MHz, CL = 12.5
pF, Gain = L2

-

-

80

Crystal @24 MHz, CL = 12.5
pF, Gain = L3

Unit

Test Conditions

ΩEquivalent series resisotr(ESR)
-

-

40

Ceramic Resonator @4 MHz,
CL = 30 pF, Gain = L0

-

-

20

Ceramic Resonator @12 MHz,
CL = 20 pF, Gain = L1

-

-

60

Ceramic Resonator @16 MHz,
CL = 10 pF, Gain = L2

-

-

60

Ceramic Resonator @24 MHz,
CL = 10 pF, Gain = L3

Notes:
1.

Guaranteed by characterization, not tested in production.

2.

Safety factor (Sf) must be higher than 5 for HXT to determine the oscillator safe operation during the application life. If
Safety factor isn’t enough, the HXT gain need be changed to higher driving level.
𝑆𝑓 =−𝑅
𝐶𝑟𝑦𝑠𝑡𝑎𝑙 𝐸𝑆𝑅=

𝑅𝐴𝐷𝐷 + 𝑅𝑆
𝑅𝑆

RADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is onlyused to measure Safety factor (Sf) of crystal in engineer stage, not for mass produciton.

XT1_IN

RADD
C2

C1

Table 8.4-4 External 4~24 MHz High Speed Crystal Characteristics
8.4.2.1

Typical Crystal Application Circuits

For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 20 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as arough estimate of the combined pin and board capacitance) when sizing C1 and C2.

CRYSTAL

C1

C2

R1

4 MHz ~ 24 MHz

10 ~ 20 pF

10 ~ 20 pF

without

Dec. 22, 2022

Page 147 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETXT1_OUTM471V/M471K/M471C Series

XT1_OUTC2

XT1_IN

R1

C1

Figure 8.4-1 Typical Crystal Application Circuit

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 148 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4.3

External 4~24 MHz High Speed Clock Input Signal Characteristics

For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.

SymbolfHXT_ext

Parameter
External user clock source
frequency

Min [*1]

TypMax [*1]

Unit

1

-

24

MHz

Test Conditions

tCHCX

Clock high time

16

-

-

nS

tCLCX

Clock low time

16

-

-

nS

tCLCH

Clock rise time

-

-

10

nS

Low (10%) to high level (90%)
rise timetCHCL

Clock fall time

-

-

10

nS

High (90%) to low level (10%)
fall time

DuE_HXT

Duty cycle

40

-

60

%

VIH

Input high voltage

0.7*VDD

-

VDD

V

VIL

Input low voltage

VSS-

0.3*VDDV

External
clock source

XT1_IN should be set as
Schmitt Trigger Mode

XT1_IN

M471V/M471K/M471C SERIES DATASHEET

tCLCL
tCLCH
VIH
VIL

90%

tCLCX
10%

tCHCL

tCHCX

Notes:
1.

Guaranteed by characterization, not tested in production.

Table 8.4-5 External 4~24 MHz High Speed Clock Input Signal

Dec. 22, 2022

Page 149 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4.4

External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics

The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained withtypical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices inorder to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
SymbolParameter

Min [*1]

TypMax [*1]

Unit

VDD

Operation voltage

2.5

-

5.5

V

TLXT

Temperature range

-40

-

105

C

Rf

Internal feedback resistor

-

6

-

MΩ

FLXT

Oscillator frequency

ILXT

32.768

Test ConditionskHz

M471V/M471K/M471C SERIES DATASHEET

0.3

0.55

4.4

ESR=35 kΩ, CL = 12.5 pF, Gain =
L0

0.3

0.65

4.6

ESR=35 kΩ, CL = 12.5 pF, Gain =
L1

0.4

0.72

4.8

ESR=35 kΩ, CL = 12.5 pF, Gain =
L2

0.55

0.9

5.2

ESR=70 kΩ, CL = 12.5 pF, Gain =
L3

0.57

1

5.4

ESR=70 kΩ, CL = 12.5 pF, Gain =
L4

0.62

1.1

5.6

ESR=70 kΩ, CL = 12.5 pF, Gain =
L5

0.75

1.3

6

ESR=90 kΩ, CL = 12.5 pF, Gain =
L6

0.92

1.6

6.6

ESR=90 kΩ, CL = 12.5 pF, Gain =L7

ACurrent consumption

TsLXT

Stable time

-

1

2

S

DuLXT

Duty cycle

30

-

70

%

Vpp

Peak-to-peak amplitude

-

0.5

-

V

Notes:
1. Guaranteed by characterization, not tested in production.

Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
SymbolRs

Parameter
Equivalnet Series Resisotr(ESR)

Min

Typ

Max

Unit

Test Conditions

-

35

70

kΩ

Crystal @32.768 kHz

Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics
8.4.4.1

Typical Crystal Application Circuits
CRYSTAL

32.768 kHz, ESR < 70 KΩ

Dec. 22, 2022

C1

C2

R1

5 ~ 20 pF

5 ~ 20 pF

without

Page 150 of 178

Rev 1.40

M471V/M471K/M471C Series

X32_OUTC2

X32_IN

R1

C1

Figure 8.4-2 Typical 32.768 kHz Crystal Application Circuit

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 151 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4.5

External 32.768 kHz Low Speed Clock Input Signal Characteristics

For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
SymbolParameter

Min [*1]

TypMax [*1]

Unit

Test Conditions

fLXT_ext

External clock source frequency-

32.768

-

kHz

tCHCX

Clock high time

450

-

-

nS

tCLCX

Clock low time

450

-

-

nS

tCLCH

Clock rise time

-

-

50

nS

Low (10%) to high level (90%)
rise timetCHCL

Clock fall time

-

-

50

nS

High (90%) to low level (10%) falltime

DuE_LXT

Duty cycle

30

-

70

%

VIH

LXT input pin input high voltage

0.7*VDD

-

VDD

V

VIL

LXT input pin input low voltage

VSS-

0.3*VDDV

External
clock source

X32_IN should be set as Schmitt
Trigger Mode

X32_INtCLCL

M471V/M471K/M471C SERIES DATASHEET

tCLCH

VIH

90%

tCLCX
10%

VIL
tCHCL

tCHCX

Notes:
1.

Guaranteed by design, not tested in production

Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal

Dec. 22, 2022

Page 152 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4.6

PLL Characteristics

SymbolParameter

Min[*1]

Typ

Max[*1]

Unit

fPLL_in

PLL input clock

4

-

24

MHz

fPLL_OUT

PLL multiplier output clock

16

-

120

MHz

fPLL_REF

PLL reference clock

4

-

8

MHz

fPLL_VCO

PLL voltage controlled oscillator

64

-

120

MHz

TL

PLL locking time

-

-

100

µS

Jitter[*2]Cycle-to-cycle Jitter

-

-

500

pS

IDD

Power consumption

-

1

2

mA

Test Conditions

VDD=5.5V @ fPLL_VCO = 100
MHz

Notes:
1.

Guaranteed by characterization, not tested in production

2.

Guaranteed by design, not tested in production

Table 8.4-9 PLL Characteristics

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 153 of 178

Rev 1.40

M471V/M471K/M471C Series
8.4.7

I/O AC Characteristics

SymbolParameter

Output high (90%) to low level (10%) fall time

Typ.

Max[*1].

7.06

11.745CL = 30 pF, VDD >= 4.5 V

4.85

8.807

CL = 10 pF, VDD >= 4.5 V

11.44

19.96

CL = 30 pF, VDD >= 2.7 V

8.53

14.399CL = 10 pF, VDD >= 2.7 V

13.33

21.921

CL = 30 pF, VDD >= 2.5 V

9.69

15.932

4.46

7.785

CL = 30 pF, VDD >= 4.5 V

2.81

4.76

CL = 10 pF, VDD >= 4.5 V

6.79

12.257

CL = 30 pF, VDD >= 2.7 V

4.42

7.817

CL = 10 pF, VDD >= 2.7 V

7.51

13.287

CL = 30 pF, VDD >= 2.5 V

5

8.569

CL = 10 pF, VDD >= 2.5 V

6.57

11.88

CL = 30 pF, VDD >= 4.5 V

4.04

7.742

CL = 10 pF, VDD >= 4.5 V

10.96

19.128CL = 30 pF, VDD >= 2.7 V

6.83

12.18

12.2

21.363CL = 30 pF, VDD >= 2.5 V

7.76

13.352CL = 10 pF, VDD >= 2.5 V

5.17

9.151

CL = 30 pF, VDD >= 4.5 V

2.77

5.109

CL = 10 pF, VDD >= 4.5 V

8.3

14.602CL = 30 pF, VDD >= 2.7 V

4.66

7.891

9.42

15.941

CL = 30 pF, VDD >= 2.5 V

5.24

8.617

CL = 10 pF, VDD >= 2.5 V

Typ.

Min[*1].

Unit

Test Conditions[*2](Normal Slew Rate)tf(IO)outnS

CL = 10 pF, VDD >= 2.5 V

Output high (90%) to low level (10%) fall time(High Slew Rate)

M471V/M471K/M471C SERIES DATASHEET

Output low (10%) to high level (90%) rise time
(Normal Slew Rate)tr(IO)out

Output low (10%) to high level (90%) rise time(High Slew Rate)

SymbolDec. 22, 2022

Parameter

Page 154 of 178

nS

nS

Unit

CL = 10 pF, VDD >= 2.7 V

CL = 10 pF, VDD >= 2.7 V

Test Conditions[*2]

Rev 1.40

M471V/M471K/M471C Series

I/O maximum frequency

48.91

28.2

CL = 30 pF, VDD >= 4.5 V

74.99

40.3

CL = 10 pF, VDD >= 4.5 V

29.76

17.1

CL = 30 pF, VDD >= 2.7 V

43.4

25.1

MHz CL = 10 pF, VDD >= 2.7 V

26.11

15.4

CL = 30 pF, VDD >= 2.5 V

38.2

22.8

CL = 10 pF, VDD >= 2.5 V

69.23

39.4

CL = 30 pF, VDD >= 4.5 V

119.47

67.6

CL = 10 pF, VDD >= 4.5 V

44.18

24.8

CL = 30 pF, VDD >= 2.7 V

73.42

42.4

MHz CL = 10 pF, VDD >= 2.7 V

39.38

22.8

CL = 30 pF, VDD >= 2.5 V

65.10

38.8

CL = 10 pF, VDD >= 2.5 V

2.77

-

1.19

-

(Normal Slew Rate)fmax(IO)out[*3]

I/O maximum frequency(High Slew Rate)

I/O dynamic current consumptionf(IO)out = 24 MHz
CL = 10 pF, VDD = 3.3 V,f(IO)out = 24 MHz
mA

0.69

-

0.3

-

CL = 30 pF, VDD = 3.3 V,f(IO)out = 6 MHz
CL = 10 pF, VDD = 3.3 V,f(IO)out = 6 MHz

Notes:
1.

Guaranteed by characterization result, not tested in production.

2.

CL is a external capacitive load to simulate PCB and device loading.

3.

The maximum frequency is defined by 𝑓𝑚𝑎𝑥 =4.

The I/O dynamic current consumption is defined by 𝐼𝐷𝐼𝑂 = 𝑉𝐷𝐷 × 𝑓𝐼𝑂 × (𝐶𝐼𝑂 + 𝐶𝐿 )2
3 × (𝑡𝑓 +𝑡𝑟 ).

Table 8.4-10 I/O AC Characteristics

Dec. 22, 2022

Page 155 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

IDIO

[*4]

CL = 30 pF, VDD = 3.3 V,

M471V/M471K/M471C Series
8.5 Analog Characteristics
8.5.1

LDO

SymbolParameter

Min

Typ

Max

Unit

VDD

Power supply

2.5

-

5.5

V

VLDO

Output voltage

-

1.8

-

V

TA

Temperature

-40

-

105

℃

Test Condition

Notes:
It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.

1.

2. For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest V SS pin of
the device.
3.

VLDO is only used to supply internal power.

8.5.2

Reset and Power Control Block Characteristics

The parameters in below table are derived from tests performed under ambient temperature.
SymbolParameter

Min

Typ

Max

Unit

IPOR[*1]

POR operating current

-

10

20

µA

[*1]

LVR operating current

-

1

4.5

AVDD = 3.3V

IBOD[*1]

BOD operating current

-

10

25.2

AVDD = 3,3V, Normal
mode

-

1

2.4

AVDD = 3.3V, Low
Power mode

POR reset voltage(Falling edge)

2.10

2.20

2.30

POR reset voltage(Rising edge)

2.15

2.25

2.35

LVR reset voltage(Falling edge)

2.25

2.35

2.45

LVR reset voltage(Rising edge)

2.30

2.40

2.50

BOD brown-out detect voltage

2.30

2.40

2.50

BODVL = 0

(Falling edge)

2.60

2.70

2.80

BODVL = 1

3.60

3.70

3.80

BODVL = 2

4.20

4.40

4.60

BODVL = 3

BOD brown-out detect voltage

2.38

2.48

2.58

BODVL = 0

(Rising edge)

2.68

2.78

2.88

BODVL = 1

3.68

3.78

3.88

BODVL = 2

4.28

4.48

4.68

BODVL = 3

ILVR

M471V/M471K/M471C SERIES DATASHEET

VPOR

VLVR

VBOD

Test Conditions
AVDD = 3.3V

V

TLVR_SU[*1]

LVR startup time

-

50

65

TLVR_RE[*1]

LVR respond time

-

2

5

-

[*1]

BOD startup time

-

260.4

306.4

-

BOD respond time

-

2

2.5

Normal mode

TBOD_SUTBOD_RE[*1]

Dec. 22, 2022

Page 156 of 178µS-

Rev 1.40

M471V/M471K/M471C Series
-

-

3862

Low Power modeRVDDR[*1]

VDD rise time rate

10

-

-

[*1]

VDD fall time rate

10

-

-

POR Enabled

100

-

-

LVR Enabled

10

-

-

BOD Enabled, Normal
mode

RVDDF

µS/V

POR Enabled

Notes:
1.

Guaranteed by characterization, not tested in production.

2.

Design for specified applcaiton.

Table 8.5-1 Reset and Power Control Unit

VDD

RVDDR

RVDDF

VBOD
VLVR
VPOR

Figure 8.5-1 Power Ramp Up/Down Condition

8.5.3

12-bit SAR Analog To Digital Converter (ADC)

SymbolParameter

Min

Typ

Max

Unit

Test Conditions

TA

Temperature

-40

-

105

℃

AVDD

Analog operating voltage

2.5

-

5.5

V

VDD = AVDD

VREF

Reference voltage

2.5

-

AVDD

V

AVDD-VREF < 2.5V

VIN

ADC channel input voltage

0

-

VREF

V
AVDD = VDD = VREF = 5.0 V

IADC[*1]

ADC Operating current (AVDD +VREF current)

FADC = 36 MHz
-

168

TBD

µA

TCONV = 19 * TADC
25℃

NR
FADC[*1]
1/TADC

Resolution
ADC Clock frequency

Dec. 22, 2022

12
4

-

Page 157 of 178

Bit
36

MHz

2.7V < AVDD < 5.5V

Rev 1.40

M471V/M471K/M471C SERIES DATASHEETTime

M471V/M471K/M471C Series
SymbolParameter

Min

Typ

Max

Unit

Test Conditions
TSMP =

TSMP

Sampling Time

1

-

256

1/FADC(EXTSMPT(EADC_SCTLx[31:24]) + 1) * TADC

TCONVConversion time

19

-

274

1/FADCTCONV = TSMP + 18 * TADCFSPS[*1]

Sampling Rate

TBD

-

1895

kSPS

FSPS = FADC / TCONV

TEN

Enable to ready time

1

-

-

1/ FADC

INL[*1]

Integral Non-Linearity Error

-3.7

-

3.3

LSB

VREF = AVDDDNL[*1]

Differential Non-Linearity Error

-1

-

3.8

LSB

VREF = AVDD

EG[*1]

Gain error

-4

-

4

LSB

VREF = AVDD

EO[*1]T

Offset error

-4

-

4

LSB

VREF = AVDD

EA[*1]

Absolute Error

-4

-

4

LSB

VREF = AVDDENOB[*1]

Effective number of bits

-

10

-

bits

FADC = 36 MHz

SINAD[*1]Signal-to-noise
ratio

-

62.02

-

and

distortion

AVDD = VDD = VREF = 3.3 V
Input Frequency = 20 kHz
dB

SNR[*1]Signal-to-noise ratio

-

62.12

-

THD[*1]

Total harmonic distortion--74.63-

CIN[*1]

Internal Capacitance

-

3.6

-

pF

RIN[*1]

Internal Switch Resistance

-

-

0.85

kΩ

External input impedance

-

-

TBD

kΩ

REX

[*1]

TA = 25 °C

M471V/M471K/M471C SERIES DATASHEET

Notes:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad andis combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
𝑅𝐸𝑋 =

𝑘
− 𝑅𝐼𝑁
𝑓𝐴𝐷𝐶 × 𝐶𝐼𝑁 × ln(2𝑁+2 )

VDD

REX
VEX

EADC_CHx

RIN

12-bitConverter

CIN

CEX

Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins

Dec. 22, 2022

Page 158 of 178

Rev 1.40

M471V/M471K/M471C Series
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.

EF (Full scale error) = EO + EG
Gain Error
EG

Offset Error
EO

4095
4094
4093
4092

Ideal transfer curve

7
6ADC
outputcode

5

Actual transfer curve

4
3
2

DNL
1 LSB

Offset Error
EO

4095

Analog input voltage(LSB)

Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset andgain error from the actual transfer curve.

8.5.4

Digital to Analog Converter (DAC)

The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and thetypical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
SymbolParameter

Min

Typ

Max

Unit

2.5

-

5.5

V

Test Condition

AVDD

Analog supply voltage

NR

Resolution

VREF

Reference supply voltage

2.4

-

AVDD

V

VREF ≤ AVDDDNL[*2]Differential non-linearity error

-

±0.4

-

LSB

No Loading

INL[*2]Integral non-linearity error

-

±0.5

-

LSB

No Loading

Dec. 22, 2022

8

Page 159 of 178

bit

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

1

M471V/M471K/M471C Series
OE[*2]

Offset Error

-

±0.5

-

LSB

No LoadingGE[*2]

Gain Error

-

±0.5

-

LSB

No Loading

-

-

±1

LSB

No Loading

-

-

±2

LSB

AVDD = VREF = 3.072 ~ 5.5V andRLOAD = 4M ohm

-

-

±3

LSB

AVDD = VREF = 3.072 ~ 5.5V andRLOAD = 2M ohm

Absolute Error

AE[*2]-

Monotonic

8-bit guaranteed

-

1*LSB

-

VREF 1*LSB

V

5

-

-

kΩ

-

6.4

-

kΩ

CLOAD[*2] [*4] Capacitive load

-

-

35

pF

IDAC_AVDD[*2] DAC operating current on AVDD supply

-

10

-

A

AVDD = 5.5V, no load

IDAC_VREF[*2] DAC operating current on VREF supply

-

-

1000

A

AVDD = 5.5V, no loadVO[*1]

Output Voltage

RLOAD[*2] [*3] Resistive load
RO[*2]

Output impedance

TB[*2]

Settling Time

-

4

4.5

μS

-

Full scale: for a 8-bit input codetransition between the lowest and thehighest input codes when DAC_OUT
reaches final value +/-1 LSB,
CLOAD ≤ 35pF, No RLOAD

M471V/M471K/M471C SERIES DATASHEET

Note:
1.
2.
3.
4.

Guaranteed by design, not tested in production
Guaranteed by characteristic, not tested in production.
Resistive load between DACOUT and AVSS.
Capacitive load at DACOUT pin.

Dec. 22, 2022

Page 160 of 178

Rev 1.40

M471V/M471K/M471C Series
8.5.5

Analog Comparator Controller (ACMP)

The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and thetypical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
SymbolParameter

Min

Typ

Max

Unit

Test Conditions

AVDD

Analog supply voltage

2.5

-

5.5

V

TA

Temperature

-40

-

105

℃

IACMP[*2]

ACMP operating current

-

75

150

A

VCM[*2]

Input common mode voltage range

0

1/2
AVDD

AVDD

VDI[*2]Differential input voltage sensitivity

30

-

-

mV (20mV+10mV offset)

Voffset[*2]Input offset voltage

-

±10

±20

mV

-

0

-

HYSSEL = 000

10

20

40

mV HYSSEL = 010

20

40

70

HYSSEL = 100

Vhys[*2]

Hysteresis window

Av[*1]

DC voltage Gain

43

70

-

dB

Td[*2]

Propagation delay

-

120

200

nS

TSetup[*2]

Setup time

-

-

5

μS

CRV output voltage

-1.6

-

1.6

%

Operating current

-

50

100

A

A

[*2]
CRV

IDD_CRV[*2]VDD = AVDD

AVDD x (CRVCTL/63)

M471V/M471K/M471C SERIES DATASHEET

Notes:
1.

Guaranteed by design, not tested in production

2.

Guaranteed by characteristic, not tested in production

Table 8.5-2 ACMP Characteristics

Dec. 22, 2022

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M471V/M471K/M471C Series
8.5.6

Internal Voltage Reference

The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and thetypical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol

VREF_INT

Ts[*1]

IVREF_INT[*1]

Parameter

Min

Typ

Max

2.017

2.048

2.079

2.521

2.560

2.599

Internal reference voltage

Unit

Test Conditions
AVDD >= 2.5 V
AVDD >= 2.9 V

V
3.026

3.072

3.118

AVDD >= 3.4 V

4.034

4.096

4.158

AVDD >= 4.5 V

-

0.5

0.8

CL =4.7 uF, VREF initial=0, Preload ismS enabled.

-

9.3

13

CL =4.7 uF, VREF initial=5.5, Preload ismS enabled.

-

24

180

CL =1 uF, VREF initial=0, Preload ismS enabled.

-

2

2.6

CL =1 uF, VREF initial=5.5, Preload ismS enabled.

-

-

1

mA

-

-

1.5

mA

Stable time

VREF_INT operating current

IVREF_LOAD[*1] VREF_INT output loading current
Note:

1. Guaranteed by characterization, not tested in production

M471V/M471K/M471C SERIES DATASHEET

VREF

1uF

Note: VREF_INT is only supported while package includes VREF pin with external capacitor.

Figure 8.5-2 Typical connection with internal voltage reference

Dec. 22, 2022

Page 162 of 178

Rev 1.40

M471V/M471K/M471C Series
8.5.7

Temperature Sensor

The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and thetypical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
SymbolParameter

Min

Typ

Max

Unit

VTEMP_OS[*1]Temperature sensor offset voltage

735

749

755

mV TA = 0°C

TC[*1]

Temperature Coefficient-1.55-1.698

-1.75

mV/°C

TS[*2]

Stable time

-

-

2

S

TTEMP_ADC[*1]

ADC sampling time when reading thetemperature

-

10

15

S

ITEMP[*1]Temperature sensor operating current

-

16

30

A

Test Conditions

Note:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
3. VTEMP (mV) = TC (mV/°C) x Temperature (°C) + VTEMP_OS (mV)

M471V/M471K/M471C SERIES DATASHEET

Dec. 22, 2022

Page 163 of 178

Rev 1.40

M471V/M471K/M471C Series

8.6

Communications Characteristics

8.6.1

SPI Dynamic Characteristics
Specificaitons[*1]SymbolFSPICLK
1/ TSPICLK

Test Conditions

Parameter

SPI clock frequency

Min

Typ

Max

-

-

32

-

-

25

-

-

25

Unit
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
MHz

2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF

tCLKH

Clock output High time

TSPICLK / 2

nS

tCLKL

Clock output Low time

TSPICLK / 2

nS

tDS

Data input setup time

0

-

-

nS

tDH

Data input hold time

4.7

-

-

nS

-

-

2

nS

4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF

-

-

2

nS

2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF

-

-

2

nS

2.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF

tV

Data output valid time

Note:

1. Guaranteed by design.

M471V/M471K/M471C SERIES DATASHEET

Table 8.6-1 SPI Master Mode Characteristics

tCLKH

tCLKL

CLKP=0SPICLK
CLKP=1tV
MOSI

Data Valid

Data Valid

tDS
MISO

Data Valid

CLKP=0, TX_NEG=1, RX_NEG=0or
CLKP=1, TX_NEG=0, RX_NEG=1tDH
Data ValidtV
Data Valid

MOSI
tDS
MISO

Data Valid

CLKP=0, TX_NEG=0, RX_NEG=1or
CLKP=1, TX_NEG=1, RX_NEG=0tDH
Data Valid

Data Valid

Figure 8.6-1 SPI Master Mode Timing Diagram

Dec. 22, 2022

Page 164 of 178

Rev 1.40

M471V/M471K/M471C SeriesSpecificaitons[*1]SymbolFSPICLK
1/ TSPICLK

Test Conditions

Parameter

SPI clock frequency

Min

Typ

Max

-

-

18

-

-

15

-

-

14

Unit
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
MHz

2.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF

tCLKH

Clock output High time

TSPICLK / 2

nS

tCLKL

Clock output Low time

TSPICLK / 2

nS

tSS

Slave select setup time

1
TSPICLK
+ 2ns

-

-

1
TSPICLK
+ 3ns

-

-

1
TSPICLK
+ 3ns

-

-

4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF

nS

Slave select hold time

1
TSPICLK

-

-

nS

tDS

Data input setup time

1

-

-

nS

tDH

Data input hold time

6

-

-

nS

-

-

26

-

-

32

-

-

34

4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
nS

2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF

Note:

1. Guaranteed by design.

Table 8.6-2 SPI Slave Mode Characteristics

Dec. 22, 2022

Page 165 of 178

Rev 1.40

M471V/M471K/M471C SERIES DATASHEET

Data output valid time

2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF

2.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF

tSH

tV

2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF

M471V/M471K/M471C Series

SSACTPOL=1

SPI SStSStSH

SSACTPOL=0tCLKH

CLKPOL=0
TXNEG=1
RXNEG=0tCLKL

SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1

tV

SPI data output(SPI_MISO)

Data Valid

Data ValidtDS

SPI data input(SPI_MOSI)

Data Valid

SSACTPOL=1

SPI SStDH
Data Valid

tSS

tSH

SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1

tCLKH

tCLKL

SPI Clock

M471V/M471K/M471C SERIES DATASHEETCLKPOL=1
TXNEG=1
RXNEG=0tV

SPI data output(SPI_MISO)

Data ValidtDS
SPI data input(SPI_MOSI)

Data ValidtDH
Data Valid

Data Valid

Figure 8.6-2 SPI Slave Mode Timing Diagram

Dec. 22, 2022

Page 166 of 178

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M471V/M471K/M471C Series
SPI - I2S Dynamic Characteristics

8.6.2
SymbolParameter

Min [*1]

Max [*1]

Unit

Test Conditions

tw(CKH)I2S clock high time80-

tw(CKL)I2S clock low time80-

tv(WS)

WS valid time0

6th(WS)

WS hold time0-

Master modetsu(WS)

WS setup time

16-

Slave modeth(WS)

WS hold time0-

Slave mode

DuCy(SCK)I2S slave input clock duty
cycle

35

65

2

-

Master receiver

0-

Slave receiver

5-

Master receiver

6-

Master fPCLK = 48 MHz, data: 24 bits, audio
frequency = 128 kHz
Master modenS

tsu(SD_MR)

Slave mode

Data input setup timetsu(SD_SR)
th(SD_MR)%

Data input hold timeth(SD_SR)

Slave receivernS

tv(SD_ST)

Data output valid time-

30

Slave transmitter (after enable edge)th(SD_ST)

Data output hold time4-

Slave transmitter (after enable edge)tv(SD_MT)

Data output valid time-

4

Master transmitter (after enable edge)th(SD_MT)

Data output hold time0-

Master transmitter (after enable edge)

Note:

CK output

Table 8.6-3 I2S Characteristics

CPOL = 0tw(CKH)
CPOL = 1
tw(CKL)tv(WS)th(WS)

WS outputtv(SD_ST)
SDtransmit

LSB transmit(2)MSB transmit

tsu(SD_MR)
SDreceive

LSB receive(2)Bitn transmit

th(SD_ST)
LSB transmit

th(SD_MR)
MSB receive

Bitn receive

LSB receive

Figure 8.6-3 I2S Master Mode Timing Diagram

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1. Guaranteed by design.

M471V/M471K/M471C Series

CK Input

CPOL = 0

CPOL = 1
tw(CKH)

tw(CKL)th(WS)

WS inputtv(SD_ST)tsu(WS)
SDtransmit

LSB transmit(2)MSB transmit

tsu(SD_SR)
SDreceive

LSB receive(2)Bitn transmit

th(SD_ST)
LSB transmit

th(SD_SR)
MSB receive

Bitn receive

LSB receive

Figure 8.6-4 I2S Slave Mode Timing Diagram

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M471V/M471K/M471C Series
8.6.3

I2C Dynamic Characteristics

SymbolParameter

Standard Mode[1][2]Fast Mode[1][2]

Min

Max

Min

Max

Unit

tLOW

SCL low period

4.7

-

1.3

-

µS

tHIGH

SCL high period

4

-

0.6

-

µS

tSU; STA

Repeated START condition setup time

4.7

-

0.6

-

µS

tHD; STASTART condition hold time

4

-

0.6

-

µS

tSU; STOSTOP condition setup time

4

-

0.6

-

µS

tBUF

Bus free time

4.7[3]-

1.2[3]-µS

tSU;DAT

Data setup time

250

-

100

-

nS

tHD;DAT

Data hold time0[4]3.45[5]0[4]0.8[5]µStr

SCL/SDA rise time

-

1000

20+0.1Cb

300

nS

tf

SCL/SDA fall time

-

300

-

300

nS

Cb

Capacitive load for each bus line

-

400

-

400

pF

Notes:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.

Table 8.6-4 I2C Characteristics
STOP

Repeated
START

START

STOP

SDA
tBUF

tLOW
tr

SCL
tHD;STA

tf

tHIGH
tHD;DATtSU;DATtSU;STAtSU;STO

Figure 8.6-5 I2C Timing Diagram

Dec. 22, 2022

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3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.

M471V/M471K/M471C Series
8.7 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
SymbolParameter

Min[3]

Typ

Max

Unit

VFLA[1]

Supply voltage

-

1.8

-

V

TERASE

Page erase time

-

25

-

mS

TMASS ERASE

Mass erase time

-

127

-

mS

TBANK ERASEBank erase time

-

127

-

mS

TPROG

Program time

-

98

-

μS

IDD2

Program current

-

10

-

mA

IDD3

Erase current

-

12

-

mA

20,000--cycles[2]

65

-

-

10

-

-

4

-

-

NENDUR

TRET

Cycling Endurance

Data retention

Test Condition

TA = 25℃

TJ = -40℃~125℃
20 kcycle[2] , TJ = 55℃

year

20 kcycle[2] , TJ = 85℃
20 kcycle[2] , TJ = 125℃

Notes:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles. The flash data can only be programmed once at the same address after flash
erase.
3. Guaranteed by design.

M471V/M471K/M471C SERIES DATASHEET

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M471V/M471K/M471C Series
8.8 Data Flash DC Electrical Characteristics
The devices are shipped to customers with the Data Flash memory erased.
SymbolParameter

Min[3]

Typ

Max

Unit

VFLA[1]

Supply voltage

-

1.8

-

V

TERASE

Page erase time

-

21

-

mS

TMASS ERASE

Mass erase time

-

23

-

mS

TPROG

Program time

-

150

-

μS

IDD2

Program current

-

8

-

mA

IDD3

Erase current

-

12

-

mA

20,000--cycles[2]

65

-

-

10

-

-

4

-

-

NENDUR

TRET

Cycling Endurance

Data retention

Test Condition

TA = 25℃

TJ = -40℃~125℃
20 kcycle[2] , TJ = 55℃

year

20 kcycle[2] , TJ = 85℃
20 kcycle[2] , TJ = 125℃

Notes:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles. The flash data can only be programmed once at the same address after flash
erase.
3. Guaranteed by design.

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M471V/M471K/M471C Series
9

PACKAGE DIMENSIONS

Package is Halogen-free, RoHS-compliant and TSCA-compliant.

9.1

LQFP 100L (14x14x1.4 mm3 footprint 2.0 mm)

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M471V/M471K/M471C Series
9.2

LQFP 128L (14x14x1.4 mm3 footprint 2.0 mm)

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M471V/M471K/M471C Series
9.3

WLCSP100 (4.4648x 4.4480x 0.58 mm3 , ball pitch 0.4 mm)

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M471V/M471K/M471C Series
10 ABBREVIATIONS
10.1

Abbreviations
Description

ACMP

Analog Comparator Controller

ADC

Analog-to-Digital Converter

AES

Advanced Encryption Standard

APB

Advanced Peripheral Bus

AHB

Advanced High-Performance Bus

BOD

Brown-out Detection

CAN

Controller Area Network

CCAP

Camera Capture Interface

DAP

Debug Access Port

DES

Data Encryption Standard

EADC

Enhanced Analog-to-Digital Converter

EBI

External Bus Interface

EMAC

Ethernet MAC Controller

EPWM

Enhanced Pulse Width Modulation

FIFOFirst In, First Out

FMC

Flash Memory Controller

FPU

Floating-point Unit

GPIO

General-Purpose Input/Output

HCLK

The Clock of Advanced High-Performance Bus

HIRC

12 MHz Internal High Speed RC Oscillator

HXT

4~24 MHz External High Speed Crystal Oscillator

IAP

In Application Programming

ICP

In Circuit Programming

ISP

In System ProgrammingLDO

Low Dropout Regulator

LIN

Local Interconnect Network

LIRC

10 kHz internal low speed RC oscillator (LIRC)

MPU

Memory Protection Unit

NVIC

Nested Vectored Interrupt Controller

PCLK

The Clock of Advanced Peripheral Bus

PDMA

Peripheral Direct Memory Access

PLL

Phase-Locked Loop

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M471V/M471K/M471C SERIES DATASHEET

Acronym

Rev 1.40

M471V/M471K/M471C Series
PWM

Pulse Width Modulation

QEI

Quadrature Encoder Interface

SD

Secure Digital

SPI

Serial Peripheral Interface

SPS

Samples per Second

TDES

Triple Data Encryption Standard

TK

Touch Key

TMR

Timer Controller

UART

Universal Asynchronous Receiver/Transmitter

UCID

Unique Customer ID

USB

Universal Serial Bus

WDT

Watchdog Timer

WWDTWindow Watchdog Timer

Table 10.1-1 List of Abbreviations

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M471V/M471K/M471C Series
11 REVISION HISTORY
Date

Revision

Description

2020.09.15

1.00

1. Initial version.

2021.05.15

1.10

1. Added section 6.7 PDMA Controller (PDMA).
1. Updated cover page.
2. Updated chapter 1 GENERAL DESCRIPTION.

2021.06.15

1.20

3. Updated section 3.3 M471V/M471K/M471C Series Selection Guide.
4. Updated section 3.2 M471V/M471K/M471C Series Naming Rule.
5. Updated section 5.1 NuMicro® M471V/M471K/M471C Block Diagram.

2021.12.22

1.30

2022.12.22

1.40

1. Updated program time to 150 μS in section 8.8 Data Flash DC Electrical
Characteristics
1. Added new part number M471CI8AE.
2. Added “Package is Halogen-free, RoHS-compliant and TSCA-compliant.” in Chapter
3 and 9.

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M471V/M471K/M471C Series

M471V/M471K/M471C SERIES DATASHEET

Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, alltypes of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify thedamages and liabilities thus incurred by Nuvoton.

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