Also presented at International Symposium on Detector Development, SLAC, Stanford Univ., April 3-6, 2006

First Results of
0.15μm CMOS SOI Pixel Detector
SLAC Exp. Seminar, Apr. 4, 2006
Yasuo Arai (KEK)KEK Detector Technology Project :[SOIPIX Group]
Y. Arai、Y. Ikegami、H. Ushiroda、
Y. Unno、O. Tajima、T. Tsuboyama、
S. Terada、M. Hazumi、H. IkedaA、K. HaraB、H. IshinoC、T. KawasakiD、Gary VarnerE, Elena MartinE, Hiro TajimaF
KEK、JAXAA、U. TsukubaB、TITC、Niigata U.D、U. HawaiiE, SLACF
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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OUTLINE
1. Introduction
What is Silicon-On-Insulator?
2. SOI Pixel Development at KEK
3. Specific Issues on SOI Pixel
TCAD Simulation
4. Test Results
5. Summary

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)2

1. IntroductionzzWhat is Silicon-On-Insulator?

A thin layer (50nm ~ 100μm) of
Si layered on SiO2
Higher speed (up to 15%) andLower power (up to 20%) over
Bulk CMOS.

1μm

Transistor

OKI Electric Industry Co., Ltd.
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

3Feature of SOI-CMOS Devices• Full Dielectric Isolation : Latchup Free, Small Area
• Low Junction Capacitance : High Speed, Low Power• Low Leakage, Low Vth Shift : High Temp. (~300 ºC) Application• High Soft Error Immunity : Rad-Hard application
Bulk CMOS

SOI CMOS(Ref. 'SOI Technology' by Jean-Pierre Colinge, Springer)
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)4

PD vs. FD

IBM PowerPC, AMD Athlon,
Sony Cell …
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

OKI Radio ControlledWrist Watch (CASIO)

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SOI Wafer Fabrication（UNIBONDTM, SOITEC）

microbubbles

hydrophilicbonding~500oC

CMOS(Low R)

Sensor(High R)
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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Previous Activity

Processed inLab. with ~3μmtechnology.
Ended at 2004?
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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２．SOI Pixel Development at KEK
Last spring, New Detector R&D projects were called at KEK, and we
proposed Development of SOI (Silicon-On-Insulator) Pixel Detector.
Main members consist of Belle and ATLAS silicon detector group.

Hybrid Pixel Detector(need many bump bondings)

SOI Pixel Detector
Monolithic Detector withSensor(Hi-R) andElectronics(Low-R)
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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Feature of Our SOI Pixel Detector• Using Commercial 0.15μm FD-SOI process (OKI Elec. Ind.).
• SOI Wafer (SOITEC Hi-R, 150 mmφ)
Top Si : Cz, ~18 Ω-cm, p-type, 50 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz、Hi-R >1k Ω-cm (No type assignment bysupplier), 650 μm thick (thinned after process <350μm)• Multi Project Wafer (Masks are shared with other design)+ additional process step.
• Add only 3 mask layers to create sensor (p+, n+, andcontact to substrate).
• Back side is plated with Al (200 nm).
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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History• ’05. 6: OKI agreed on SOIPIX development with us.
• ’05.10: 3 x 2（for p/n substrate) + 3 chips (total 9 chips) submitted.
（32x32 small pixel, 4x4 large pixel, Short strip, Tr TEG ...)
• ’05.12: Test of contact fabrication.
• ’06. 2: Test of p-n junction fabrication.
• ’06.3 middle : Process ends.
• ’06.3.30 Bare Chip Delivered.
(-> so the present results are very preliminary and limited)

Electronics

contactp-n junction

TOP Si~50nm
BOX(Buried Oxide)
200nm

p+n+350um

Sensor (High Resistivity)
Al (2000A)

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

pixel

pixel
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SOI Pixel Process step flow
① After Gate stack formation
SOI
Box
650um

Handling wafer② Box Window photo lithography and etching

Handling wafer③ Source/Drain Implantation followed by S/D annealing and Salicidation
n+p+Handling wafer④ 1st ILD (interlayer dielectrics) filling and CMP planarization

Handling wafer
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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⑤ Contact etching

Handling wafer⑥ Contact plug filling and 1st Metal formation

650um

Handling wafer⑦ 3 ~ 5Metal formation followed by Backside polishing and Al coating

n+p+250~350um

Handling waferAl
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

12Side View

n+ on p--p+ on n--2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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Small Pixel TEG

CMOS Active Pixel
Sensor Type
20 μm x 20 μm32 x 32 pixels

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

14IHXCP (Imaging Hard X-Ray Compton Polarimeter) TEG+

set baseline

Vbase−

U of Hawaii &SLAC

Row enable

VDD
threshold

8−12DAC

ThreshVDD

Collection electrode−Row hit+

VIsrc

Hold sample
AnalogbufferTarget Specification
Column Hit

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

Sel Column

200 x 200 μm
2.1 x 2.1 cm<=10 e500 Hz
10? mili-Hz
0.5 keV1-2 μs200 μW/pixel
12 bits

Analog sample (bussed)

Pixel Size
Pixel Array (Detector) Size
Noise
Global Trigger Rate
Single Pixel Rate
Trigger Threshold
Trigger Latency
PowerADC precision

4 x 4 pixels

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3. Specific Issues on SOI Pixel• n+, p+ implantÆ Formed with Tr Source/Drain not to increase number of masks.
• ThinningÆ Wafer is thinned from 650um to 350um. Further thinning is possible.
• Back Side process
Æ No implant on back side. Just add Al (2000 A) Plating.
• Thermal Donor generation
Type of the high-R wafer may change by TD generation during process.
Æ We prepared both p & n substrate designs.
• Back Gate Effect to SOI Tr
Substrate works as back gate, so the voltage must be low under Tr.
Æ All Tr are placed within Guard Ring, and body is tied to VDD/VSS.

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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3D Process/Device Simulator ENEXSS• Developed by SELETE (Japan Consortium)( http://www.selete.co.jp/ )• Full 3D simulation
α particle
injection

SOI NMOSs o u rcegate

BOXdrain

Useful to get¾ Field Map¾ Device Characteristics
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)¾ Signal generated by particle, etc.

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Back Bias Simulation
ＴＣＡＤ: ENEXSSNMOSＢＯＸ
handle wafer

Threshold voltage (V)

0.5
0.4
0.3
0.2
0.1
0V

-0.1
-0.2
-0.3
-0.4

backbias supplied here

-20
-100+10 +20-20 -14 -8 -2 4 10 16
Backbias (V)VB (V)

With |back bias| > 8V, NMOS or PMOS become always ON.
Voltage of substrate under Tr must be kept low.
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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4．Test Results

MPW Wafer
6 inchφ2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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2.5 mmTEG Chip Layout

4 electrods/pixelCenter of pixel isopen for Light Test
2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

20 μm

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n+ contact

Contact & Sheet
Resistance

Hi-R (> 1k Ωcm)
Std. wafer(p+, ~13 Ωcm)

p+ contact

Hi-R (> 1k Ωcm)
Std. wafer(p+, ~13 Ωcm)

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)[Sheet R]
n+ : 33 Ω/squarep+ : 136 Ω/square[Contact](0.16x0.16um2)
n+ : 87 Ω
p+ : 218 Ω21

p-n junctionI-V characteristics

p+(center) - n+(guard)

p+(center) - n+ (guard) &n+(center) - p+(guard)

n+(center) - p+(guard)

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)22n+ / p+ --- backI-V characteristics

p+ - backn+ - backn+(center) – back is Ohmic
Æ Substrate is n-type2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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Substrate Resistivity

Very Preliminary!

[before process]No type assign, > 1 kΩcm

[after process] (4-points measurement)n-type, ρ ~700 Ωcm (->NB~6x1012 cm-3)
1010I-V Characteristic
I[A]1010um x 460um strip
I<1nA @V=56 V
Depletion ~ 100 μm ?

10-6-7-8-9-1010-1110-12100102030

405060Vdet[V]2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)

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5．Summary• We have started development of Monolithic SOI Pixel Detector.
• The detector has sensor in high-resistive Si and CMOS circuit in lowresistive Si.
• We are using commercial (OKI 0.15 μm SOI) process with commercialwafer (SOITEC Hi-R) with only adding 3 masks.
• 3-D TCAD simulations for sensor/device study are being done withENEXSS。
• Good substrate contact and p-n junction are confirmed with the firstrun wafer.
• We found type of handle wafer is ‘n’, and have enough resistivity.
• 9 kinds of TEG chips are received at the end of March, and showing
promising results. Detailed tests will be done soon.
• We would like to apply this technique to Super-B, SLHC, ILC and Xray detectors.

2006.4.4 yasuo.arai@kek.jp (SLAC Exp. Seminar)25