Motivation 1/2
Test Application Time Reduction witha Dynamic Reconfigurable Scan Tree
Architecture

Telecommunication
Security

HomeY. Bonhomme T. Yoneda H. Fujiwara P. Girard

TEST

MedicalComputerComputer Design
Design andand Test
Test Laboratory
Laboratory

Robotics

Informatics

Transport…

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Motivation 2/2

OutlineIntroduction

Scan Technique
From the circuit

From the circuit

Test
control
input

To reduce the test generation
complexity
To increase the test quality

Scan tree generation

EfficientReliable
ProvenStandardized

Experimental results

To the circuitNew solution

Different optimizations

To the circuit

Testobservation
outputPrevious solution

Fanout

Test power
Test time

AreaArea-overhead

Conclusion and future work
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Introduction 2/3

Scan tree architecture [Miyase03] [Yotsuyanagi03]
Scan input

Scan tree architecture
Scan output

Test time reduction
No additional test pin

Shift time for 1 test pattern: 9
Scan input

High dependence between the scan tree design
and the test sequence
Test sequence updating is no guaranty

MISRIt is not possible to provide a scan treearchitecture in any case
Scan output

Dynamic reconfigurable scan treearchitecture [Bonhomme04]

Shift time for 1 test pattern: 4COE
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Scan tree architecture generation

Introduction 3/3

1/4

The proposed architecture

Previous scan tree generation method 1/2
Incompatibility

Scan input

Scan tree mode

MISR
Pattern
Recognition

Single scan modeTP1 1 0 X X X 0
TP2 1 0 X X X 1236541MISRMISRColoring graphrepresentation

L1L2
L2 > L1 TP2 increases the constraint on the scan tree architecture

Scan output

Scan enable

Testsequence

TestSequence
for scantree
generation

Test sequence
reduction

Sort by# incompatibilities

Which part of the test sequence for each mode?

Equivalent test patterns:
Scan treearchitecture

TP1,TP2COE
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Scan tree architecture generation

Scan tree architecture generation

2/4

3/4

Previous scan tree generation method 2/2
Test sequence for scan treearchitecture generation
TP11 XXX 1 X
0 1 XX 1 X
0XX1 1 1
1 0 1X0 010 010X
11 0101

TP2TP3TP4TP5TP6TP1

New scan tree generation method 1/2Standard
scan tree architecture# clock cycles

TP1max=48

Complexity: O(m²O(m².n²)

TP2(1x1) + (5x6)

TP3TP4TP5TP2TP3TP4TP5TP3TP4TP5TP6TP4TP5TP5TP62
TP1TP2MISRMIS
R

TP3341652341

TP6TP6TP6TP6Minimal test time

Coloring graph

1 XXX 1 X
0 1 XX 1 X
0XX1 1 1
1 0 1X0 0
10 010X11 0101

6523416TP4TP5TP62365236523654141415

Coloring graphrepresentation

Greedy Algorithm
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Scan tree architecture generation
4/4

Experimental environment

New scan tree generation method 2/2
2 23 32
3Complexity:
O(m.n²O(m.n²)
TP3P2

H=2
H=2TP4TP3

1652233

TT
P1,2
P1,2,34 4
1 1
6 6 5 54411TP11 ,2 ,3 ,4, 5, 665365Justsort H=4the graph
H=3# clock cycles
2342
3
H=4
H=6
No5 graph Tcoloring
solved461T
2TP1TP1,241

Benchmark sets:

ISCAS’ISCAS’89 (scan version)

Test parameters:

Deterministic patterns
TestGen by Synopsys

max=48

P5P4T
TP5P641

H=7
H=66622

5533

66

55

44

11Simulation:

C codePIV 2.8GHz and 1Go

Minimal test time:
time: solution 1, 2, 3, 4…
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Experimental results 1/3

Experimental results 2/3

Benchmark setUncompacted test sequence

# FFs

# TPs

# TPs

(uncompacted)(compacted)

s5378

179

166

125

98,7%

s5378

72,70%

1172,70%5s9234

211

341

228

93,16%

s9234

58,30%

97

57,20%

29

Computation
Computation
Shift test
Shift test
time reduction* time (in seconds) time reduction* time (in seconds)

FC

s13207

669

540

347

98,32%

s1320787,80%

548

87,90%

222

s35932

1728

2835

XX

s35932

99,51%

3940

99%

511

s38584

1426

1275

XX

s3858486,90%

14525

86,80%

399

Previous technique

Proposed technique* Compared to the uncompacted test sequence applied in standard scan architecture
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Experimental results 3/3

Different optimizations 1/4

Compacted test sequence

Fanout Optimization 1/2
Uncompacted
test sequence(for the proposedarchitecture)

Shift test
Shift test
time reduction* time reduction*mm

s5378

68,21%

67,91%

s9234

46,25%

42,06%

Fault simulation

s13207

83,99%

83,79%

Test pattern droppings35932

90,05%

91,41%

s38584

XX

Previoustechnique

Proposedtechniquenmmnmm
Compactedtest sequence≈ Cn_out + 4Cm_in≈ Cn_out + 2Cm_in(for the proposedarchitecture)

Performance degradation* Compared to the compacted test sequence applied in standard scan
scan architecture
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Different optimizations 3/4

Fanout Optimization 2/2 – Fixed limitation: Fanout maximum =2
Fanoutaverage

Fanoutmaximum

Fanoutaverage

Fanoutmaximum

s5378

1,42

12,5

1,13

1,93s9234

1,08

4,77

1,052s13207

1,3

5,4

1,212s35932

6,29

27,111,22s38584

1,12,121,05

2

Before optimization

AreaArea-overhead Optimization 1/2

MIS
RM
IS
RAfter optimization

Minimization of the delaydelay-overhead
Critical path can be safe
No modification of the shift test time reduction
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M
I
S
R:6

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M
I
S
R:4

3

Different optimizations 4/4Conclusion

AreaArea-overhead Optimization 2/2
Reduction

s5378# Mux.

Size ofthe MISR

# Mux.

Size ofthe MISR

7475

5693,2%92,0%Size of# Mux. the MISR

s9234

42438981,0%79,1%

s13207

350

351

23

23

93,4%

93,4%

s35932

725

726

346

347

52,3%

52,2%

s38584

561

562

21

2296,3%

96,1%

Before optimization

Test time reduction up to 99%
No additional test pins
Flexibility
Test sequence updating is possible
Optimization Fanout / AreaArea-overhead

After optimization

No modification of the shift test time reduction
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Future work
Include test power optimization
Include design constraint:
Scan
Scan Input

MISRMI
S
R

M
IS
R

M
I
S
R

M
I
S
R

M
I
S
R

M
I
S
R

M
I
S
R

M
I
S
R

M
I
S
R

M
I
S
R

M
I
S
R

Scan
Scan Output

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