Simplifying complexity

A Safe and Secure ROS 2 Multi-Domain
Architecture for AMD Embedded
Heterogeneous Platforms
Alessandro Biondi, Accelerat SRL & Scuola Superiore Sant’Anna
Tomas Thoresen, AMD© 2023 Accelerat Srl

1

Mixed-Criticality Software for Robotics
Multimedia
Third-Party
Network

Low-level
Control

Perception
High-level
Control
MachineLearning

Monitoring

Collision
avoidance
Planning

Field
Network

Localization© 2023 Accelerat Srl

Public2Mixed-Criticality Software for Robotics
Multimedia
Third-Party
Network

Low-level
Control

Perception
High-level
Control
MachineLearning

Monitoring

Collision
avoidance
Planning

FieldNetworkLocalization

All in one platform to contain space, weight, wiring, power, and cost (SWaP-C)!

AMD Kria™
KR260
Robotics© 2023 Accelerat Srl

Public3

Cyber-Security Threats
Multimedia
Third-Party
Network

Low-level
Control

Perception
High-level
Control
MachineLearning

Monitoring

Collision
avoidance
Planning

Field
Network

Localization

Cyber-attacks starting from low-criticality software can compromise the missionof the system
AMD Kria™
KR260
Robotics© 2023 Accelerat Srl

Public4

Safety Issues
Multimedia
Third-Party
Network

Low-level
Control

Perception
High-level
Control
MachineLearning

Monitoring

Collision
avoidance
Planning

Field
Network

Localization

Safety issues that interest complex, mid-criticality software can propagate tosafety-critical software
AMD Kria™
KR260
Robotics© 2023 Accelerat Srl

Public5

Time-Predictability/Determinism Issues
Multimedia
Third-Party
Network

Low-level
Control

Perception
High-level
Control
MachineLearning

Monitoring

Collision
avoidance
Planning

Field
Network

Localization

The temporal properties of safety-critical software can be disrupted bycomplex, mid-criticality software due to on-chip interference
AMD Kria™
KR260
Robotics© 2023 Accelerat Srl

Public6

Multi-Domain ArchitectureCriticality

Criticality

Multimedia
Third-Party
NetworkX

Criticality

Perception

Planning

High-level
Control

Localization

Low-level
Control

Monitoring

FieldNetworkCollision
avoidance

MachineLearning

Strong isolation boundary© 2023 Accelerat SrlPublic7

The CLARE Software Stack
Safe and secure islandson the same chip
Strong isolation between islands(next-gen Hypervisor technology pioneered with research activities)

Automatic optimizations

Intelligent machine verification(Design Rule Checking for avoiding mistakes in the configuration)

The expert is CLARE-Toolkit

CLARE-Toolkit(no need for experts in system-level software and hardware)

Automatic
optimization ofconfiguration© 2023 Accelerat Srl

System monitoring

AMD Kria
KR260TM
Public< 1 hour for the whole configuration

8

The CLARE Architecture
Computervision

Signalprocessing

Machine learning

Controlalgorithms

User interaction

Apps
Safe
fallbacks

User requirements

Monitoring

Remoteupdating

Networking

Schedulers

Physicalactuation

CLARE-Middleware(optional)

QoS regulators
Resource partitioning

Rich OS 0Middleware

RTOS

Rich OS 1

Domains

Bare-metal
runtime

CLARE
Basic
Firmware

Domains

CLARE-Hypervisor

Applicationclass cores

Microcontrollerclass Cores

ProgrammablelogicGPU

Platform
CLARE
Third-party

DSPs

XMMU

QoS control
mechanisms

Platform
managementcores

Hardware© 2023 Accelerat Srl

Public9CLARE for Multi-Domain ROS
Mid-criticality domain
Perception
High-level
Control

Planning

High-criticality domain
Low-level
Control

MachineLearning

Localization

Field
Network

Collision
avoidance

Monitoring

CLARE-Middleware (includes virtualized DDS)
FreeRTOS

Real-time Linux

CLARE-Hypervisor
CameraSensors

Programmable Logic

Health & Security
Monitoring
Actuators

Custom Peripherals

AI Accelerator(s)Collision
Avoid. Sensors© 2023 Accelerat Srl

Public10CLARE-Middleware
Unified and simplified API to access CLARE and platform services

Main features relevant to Multi-Domain ROS2:
 Transparent, virtualized publisher/subscriber data
distribution service
 Uses CLARE’s built-in time-predictable, safe androbust inter-domain communication
 Signaling for health and security monitoring© 2023 Accelerat Srl

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CLARE-Hypervisor

HARD
REAL-TIMESECURITY

Fixed-priority and EDF scheduling

Address-Space Layout Randomization

Totally static

Bounded latency for event dispatching

Control-Flow Integrity

MISRA compliancy

Super low-latency FastBoot

Secure boot for VMs

Off-line auto-generated configuration

Secure cache partitioning

TrustZone support

Ongoing SIL4/ASIL-D certification

Bank-aware memory allocation

Strong VM space separation~ 8K LoC

Memory bandwidth reservation

Robust to denial-of-service and side-channelattacks

VM-level health-monitoring© 2023 Accelerat Srl

PublicSAFETY

12Strong Isolation
CLARE-Hypervisor implements advanced mechanisms for strong isolation, which can be optimally andautomatically configured from CLARE-Toolkit
Memory bandwidth reservation
Budgeting the number of transactions that can beissued by each core and each I/O peripheral over timeCountermeasure formemory-related inter-domain
DoS attacks

Peripheral

Countermeasure forcache-related inter-domainside-channel attacks© 2023 Accelerat SrlCoreL1CoreL1CoreL1Core

L1

BUS

Peripheral

Bank 0Bank-aware partitioning

DRAM

L2

Allocating domains to different DRAM
banks to control memory contention

Bank 1

Bank nSecure cache partitioning

Countermeasure for
DRAM-related inter-domainside-channel attacks(e.g., Row Hammer)

Partitioning the shared levels of cache tocontrol inter-core interference
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CLARE-Toolkit

Automatic optimization of thedeployment and configuration ofcomplex mixed-criticality
applications

Configuration of the entire
CLARE Software Stack withavailability of a rich template
library

CLARE-Toolkit

CLARE-Toolkit
GUIFront- end
orStand- alone
Back- end
with support for scripting

Platform-awareness for
low-level isolation
mechanisms

Designed to be integrated
with Chip Vendor
Ecosystems

Chip Vendor
2 Options:
Ecos ys tem
1.
2.

© 2023 Accelerat Srl

PublicBrowser-based on an Accelerat Cloud (SaaS)
On-premise

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CLARE-Toolkit
Performance estimations:
Bandwidth, Latencies, …
Low-level configuration:••

High-level requirements:-Criticalities and isolation capabilities
Amounts of memory
Desired bandwidths
Security features
Etc.

•Spatial and temporal isolation settings
Optimized distribution of the entire
memory to comply with the requested
configuration
Etc.
CLARE-Hypervisor
configuration

CLARE-Middleware
configuration

Vendor-specificsettings

Optimization

Configuration and binary
generation
Design Rule
Checking© 2023 Accelerat Srl

PublicHardware15

Scalable AMD Kria™ Portfolio
Choose the Starter Kit

Select the right Production SOM

KD240 DRIVES

Develop your Custom Carrier Card
K24

KRIA™ K24 SOM

For Drives and Motor
Control Systems•••

K26

Half the size of a credit
cardPower efficient
ECC support

KV260 VISION AI
For Vision AI
Cameras and Systems

KRIA K26 SOM•••

VCU and larger DPU
55% more I/OsTransceivers

K24

KR260 ROBOTICS
K26

For Robotics andMachine Vision Systems© 2023 Accelerat Srl

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Safety Certifications for AMD
˃ Functional Safety Certifications
ISO 26262
IEC 61508
ISO 13849
˃ Certified
Vitis/Vivado Developer Tools
MicroBlaze compiler
Zynq Ultrascale+ MPSoC© 2023 Accelerat Srl

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Target Applications for Embedded Developers© 2023 Accelerat Srl

Public18Simplifying complexity

THANK YOUSee more at accelerat.eu and amd.com© 2023 Accelerat Srl

Simplifying complexity

All content and information on this presentation is for informational and educational purposes only. Although we strive to provide accurate general
information, the information presented here is not a substitute for any kid of professional advice, and you should not rely solely on this information.
Always consult a professional in the area for your particular needs a circumstances prior to making a professional, legal, instructional and financial decisions.

© 2023 Accelerat Srl