ProductFolder

Order
Now

Technical
Documents

参考資料

Support &Community

Tools &
Software

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018

ISO722x デュアル・チャネルのデジタル・アイソレータ
1 特長

3 概要

•

ISO7220xおよびISO7221xファミリのデバイスは、デュア
ル・チャネルのデジタル・アイソレータです。PCBレイアウト
を行いやすくするため、チャネルはISO7220xでは同じ方向、ISO7221xでは反対方向に配置されています。これらのデバイスにはロジック入力および出力バッファがあり、TIの二酸化シリコン(SiO2)絶縁バリアによって分離され、VDE準拠で最高4000VPKのガルバニック絶縁を実現します。これらのデバイスを絶縁型電源と組み合わせて使用すると、高電圧がブロックされ、グランドが絶縁されます。また、データ・バスや他の回路で発生したノイズ電流がロー
カル・グランドに入り込み、ノイズに敏感な回路に干渉または損傷を与えることを防止できます。

1

•
•
•
•
•
•

•

1、5、25、150Mbpsの信号速度オプション– チャネル間の出力スキューが低い:
最大値1ns– 低いパルス幅歪み(PWD): 最大値1ns– 低いジッタ成分: 150Mbpsで標準値1ns
50kV/μsの標準過渡電圧耐性
2.8V (Cグレード)、3.3V、5Vの電源で動作
4kVのESD保護
高い電磁気耐性
動作温度範囲: -40℃～+125℃
定格電圧で標準寿命28年(『ISO72xファミリのデジタル・アイソレータの高電圧寿命』および「絶縁コンデンサの予測寿命」を参照)
安全関連の認定– VDE基本絶縁、DIN VDE V 0884-11:2017-01
およびDIN EN 61010-1 (VDE 0411-1)に従い4000VPK VIOTM、560VPK VIORM– UL 1577に従い2500VRMS絶縁– IEC 60950-1およびIEC 62368-1についてCSA
承認済み

2 アプリケーション
•

•
•
•

産業用フィールドバス– Modbus– Profibus™
– DeviceNet™データバス
コンピュータ・ペリフェラル・インターフェイス
サーボ制御インターフェイス
データ収集

バイナリ入力信号がコンディショニングされ、バランスされた信号に変換されてから、容量性絶縁バリアによって差動化されます。絶縁バリアを通過して、差動コンパレータがロジック変換情報を受け取り、それに応じてフリップフロップ
および出力回路を設定またはリセットします。バリアを通して周期的に更新パルスが送信され、出力が正しいDCレベルであることを保証します。このDC更新パルスが4μsごとに受信されない場合、入力に電力が供給されていない、またはアクティブに駆動されていないと見なされ、フェイル
セーフ回路により出力が論理HIGH状態に駆動されます。
製品情報(1)
型番

パッケージ

ISO7220x

SOIC (8)ISO7221x

本体サイズ（公称）4.90mm×3.91mm(1) 提供されているすべてのパッケージについては、巻末の注文情報を参照してください。

概略回路図
VCCI

Isolation
Capacitor

VCCO

INx

OUTx

GNDI

GNDO

VCCIおよびGNDIは、それぞれ入力チャネルの電源およびグランド接続です。
VCCOおよびGNDOは、それぞれ出力チャネルの電源およびグランド接続です。

1

英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。
English Data Sheet: SLLS755

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.tij.co.jp

目次
1
2
3
4
5
6
7

特長 .......................................................................... 1
アプリケーション ......................................................... 1
概要 .......................................................................... 1
改訂履歴................................................................... 2
说明（续）................................................................... 6
Pin Configuration and Functions ......................... 7
Specifications......................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9

Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Power Ratings........................................................... 8
Insulation Specifications............................................ 9
Safety-Related Certifications................................... 10
Safety Limiting Values ............................................ 10
Electrical Characteristics—5-V VCC1 and V CC2Supplies ................................................................... 11
7.10 Electrical Characteristics—5-V VCC1 and 3.3-V VCC2
Supply ...................................................................... 12
7.11 Electrical Characteristics—3.3-V VCC1 and 5-V VCC2
Supply ..................................................................... 13
7.12 Electrical Characteristics—3.3-V VCC1 and VCC2
Supplies ................................................................... 14
7.13 Electrical Characteristics—2.8-V VCC1 and VCC2
Supplies ................................................................... 14
7.14 Switching Characteristics—5-V VCC1 and VCC2
Supplies ................................................................... 15
7.15 Switching Characteristics—5-V VCC1 and 3.3-V
VCC2 Supply ............................................................. 16
7.16 Switching Characteristics—3.3-V CC1 and 5-V VCC2
Supplies ................................................................... 17

7.17 Switching Characteristics—3.3-V VCC1 and VCC2
Supplies ................................................................... 18
7.18 Switching Characteristics—2.8-V VCC1 and VCC2
Supplies ................................................................... 18
7.19 Insulation Characteristics Curves ......................... 19
7.20 Typical Characteristics .......................................... 20

8
9Parameter Measurement Information ................ 22
Detailed Description ............................................ 24
9.1
9.2
9.3
9.4

Overview ................................................................. 24
Functional Block Diagram ....................................... 24
Feature Description................................................. 25
Device Functional Modes........................................ 25

10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ................................................ 26

11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 28

13 デバイスおよびドキュメントのサポート ....................... 29
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8

デバイス・サポート ................................................... 29
ドキュメントのサポート .............................................. 29
関連リンク ............................................................... 29
ドキュメントの更新通知を受け取る方法..................... 29
コミュニティ・リソース ................................................ 29
商標 ....................................................................... 30
静電気放電に関する注意事項 ................................ 30
Glossary ................................................................ 30

14 メカニカル、パッケージ、および注文情報 ................. 30

4 改訂履歴
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
Revision O (April 2017) から Revision P に変更

Page

•

ドキュメント全体を通して「(VDE V 0884-10):2006-12」を「DIN VDE V 0884-11:2017-01」に 変更 ............................................. 1•

ドキュメント全体を通して「部品受領通知5AおよびIEC 60950-1についてCSA承認済み」を「IEC 60950-1およびIEC 623681についてCSA承認済み」に 変更 ............................................................................................................................................. 1•

Added the basic insulation working voltage for CSA in the Safety-Related Certifications table .......................................... 10•

Changed the VDE certification number from 40016131 to 40047657 in the Safety-Related Certifications table ................ 10•

Changed the maximum propagation delay and pulse-width distortion in each Switching Characteristics table ................. 15•

Added ± 10% for the VCC1 and VCC2 voltages in the condition statement of the Switching Characteristics—5-V VCC1
and VCC2 Supplies table ....................................................................................................................................................... 15•

Changed ISO722x to ISO7220 for all part numbers for the Channel-to-channel output skew parameter in each
Switching Characteristic table .............................................................................................................................................. 15

Revision N (September 2015) から Revision O に変更

Page

•

Changed the Dissipation Characteristics table to Power Ratings. Combined the DIN V VDE V 0884-10 (VDE V
0884-10):2006-12 Insulation Characteristics table IEC Package Characteristics, and IEC 60664-1 Ratings Table in
the Insulation Specifications table. Changed the Regulatory Information table to Safety-Related Certifications .................. 8•

Deleted the maximum surge voltage, 4000 VPK for VDE in the Safety-Related Certifications table.................................... 10

2

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.tij.co.jp

JAJS331P – JULY 2006 – REVISED AUGUST 2018•

Changed the CSA information in the Safety-Related Certifications table ............................................................................ 10•

追加 「ドキュメントの更新通知を受け取る方法」セクション.......................................................................................................... 29•

変更 「静電気放電に関する注意事項」セクション...................................................................................................................... 29

Revision M (October 2014) から Revision N に変更

Page

•

ドキュメント全体を通してVDE認定を「DIN EN 60747-5-5 (VDE 0884-5)」から「DIN V VDE V 0884-10 (VDE V 088410):2006-12」に 変更 ............................................................................................................................................................... 1•「概略回路図」を高品質のバージョンに更新............................................................................................................................... 1•

Changed the max value of the IN and OUT voltage from 6 to VCC + 0.5 in the Absolute Maximum Ratings table............... 7•

Changed L(I01) MIN value from 4.8 to 4 in the IEC Package Characteristics table. ............................................................. 9•

Added the JEDEC package dimensions note in the IEC Package Characteristics table....................................................... 9•

Changed L(I01) MIN value from 4.8 to 4 in the IEC Package Characteristics table. ............................................................. 9•

Added the DTI parameter to the IEC Package Characteristics table. .................................................................................... 9•

Changed the DTI test condition From: IEC 60112 / VDE 0303 Part 1 To: DIN EN 60112 (VDE 0303-11); IEC 60112 ........ 9•

Added = 150°C to insulation resistance test condition in the DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Insulation Characteristics table. ............................................................................................................................................. 9•

Added table row with input side VCC = X to the ISO7220x or ISO7221x Function table...................................................... 25

Revision L (January 2012) から Revision M に変更

Page

•

データシートのタイトルを「ISO722x デュアル・チャネルのデジタル・アイソレータ」に 変更 ............................................................ 1•「熱に関する情報」表を変更、「ピン構成と機能」セクション、「取り扱い定格」表、「放熱定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクショ
ン、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを 追加 .................... 1•「特長」セクションを更新 ............................................................................................................................................................ 1•「概要」の2番目の文に「VDE準拠で最高4000VPK」を 追加 ........................................................................................................ 1•

Updated the Regulatory Information Table............................................................................................................................. 7•

Added the min and max values to the Storage temperature parameter in the Absolute Maximum Ratings table. ............... 7•

Changed in ROC table Max col, VIH row from VCC to 5.5 .................................................................................................... 8•

Changed the L(I01) parameter name to external clearance (CLR) and L(I02) to external creepage (CPG). Alsochanged the input-to-output test voltage (VPR) parameter name to apparent charge (qpd) ................................................... 9•

Changed the Device Options table, Input Threshold column from ≠ symbol to ~ symbol 6 places .................................... 25•

変更 『絶縁の用語集』............................................................................................................................................................. 29

Revision K (January 2010) から Revision L に変更

Page

•

「特長」を「3.3Vまたは5Vの電源で動作」から「2.8V (Cグレード)、3.3V、5Vの電源で動作」に変更................................................ 1•「特長」を「4000Vpeak絶縁、560Vpeak VIORM」から、「IEC 60747-5-2 (VDE 0884, Rev2)に従い4000VPK VIOTM、560VPK
VIORM」に変更........................................................................................................................................................................... 1•

Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table ................................................... 8•

Changed Note: (1) in the RECOMMENDED OPERATING CONDITIONS table ................................................................... 8•

Changed the CTI MIN value From: ≥175 V To: ≥400 V ......................................................................................................... 9•Updated the Regulatory Information table............................................................................................................................ 10•

Changed ICC1 and ICC2 test conditions in the 5-V table......................................................................................................... 11•

Changed Table Note: (1) ...................................................................................................................................................... 11•

Changed ICC1 and ICC2 test conditions in the VCC1 at 5 V, VCC2 at 3.3 V table...................................................................... 12•

Changed Table Note: (1) ...................................................................................................................................................... 12•

Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3 V, VCC2 at 5 V table...................................................................... 13

Copyright © 2006–2018, Texas Instruments Incorporated

3

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.tij.co.jp•

Changed Table Note (1) ....................................................................................................................................................... 13•

Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table .......................................................................... 14•

Changed Table Note (1) ....................................................................................................................................................... 14•

Added ELECTRICAL and Switching CHARACTERISTICS table for VCC1 and VCC2 at 2.8 V (ISO722xC-Only) ................. 14•

Changed VCC Undervoltage Threshold vs Free-Air Temperature ........................................................................................ 20•

Changed Failsafe Delay Time Test Circuit and Voltage Waveforms ................................................................................... 22

Revision J (May 2009) から Revision K に変更

Page

•

Changed the RECOMMENDED OPERATING CONDITIONS so that Note (2) is associated with all device options in
the Input pulse width and Signaling rate ................................................................................................................................ 8•

Changed Note (2) From: Typical signaling rate under ideal conditions at 25°C. To: Typical signaling rate and Input
pulse width are measured at ideal conditions at 25°C. .......................................................................................................... 8•

Changed column 2 of the AVAILABLE OPTIONS table From: Signaling Rate To: Max Signaling Rate ............................. 25

Revision I (December 2008) から Revision J に変更•

Changed ISO7221C Marked As column From: TI7221C To: I7221C in the AVAILABLE OPTIONS table ......................... 25

Revision H (May 2008) から Revision I に変更
•

Page

Page

「特長」のUL 1577の箇条書き項目に「IEC 61010-1、IEC 60950-1、およびCSA承認済み」を 追加 ............................................ 1

Revision G (March 2008) から Revision H に変更

Page

•

Added Note: (1) to the RECOMMENDED OPERATING CONDITIONS table ....................................................................... 8•

Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table.................................................... 11•

Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V table ............................................ 12•

Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V table ............................................ 13•

Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V.......................................................... 14

Revision F (August 2007) から Revision G に変更

Page

•

データシートに型番ISO7220BおよびISO7221Bを 追加............................................................................................................ 1•「特長」一覧に5Mbpsの信号速度を 追加 .................................................................................................................................. 1•

Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table . 11•

Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3
V table................................................................................................................................................................................... 12•

Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5
V table................................................................................................................................................................................... 13•

Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V ....... 14•

Added PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xB, Propagation Delay vs Free-Air
Temperature, ISO722xB....................................................................................................................................................... 20•

Added Part Numbers ISO7220B and ISO7221B to the AVAILABLE OPTIONS table......................................................... 25

Revision E (July 2007) から Revision F に変更

Page

•

Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table ....................... 15•

Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table......................... 15•

Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table................ 16

4

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.tij.co.jp

JAJS331P – JULY 2006 – REVISED AUGUST 2018•

Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ................. 16•

Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION table................ 17•

Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION table ................. 17•

Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS table................................................................................. 18•

Changed 3.3-VRMS Supply Current vs Signaling Rate - Re-scaled the Y-axis ..................................................................... 20•

Changed 5-VRMS Supply Current vs Signaling Rate - New Curves...................................................................................... 20

Revision D (June 2007) から Revision E に変更

Page

•

Changed 3.3-VRMS Supply Current vs Signaling Rate - New Curves................................................................................... 20•

Changed 5-VRMS Supply Current vs Signaling Rate - Re-scaled the Y-axis ....................................................................... 20

Revision C (May 2007) から Revision D に変更•

Page

Changed Typical ISO7220x Circuit Hook-Up - Pin 2 (INA) label From: OUTPUT to INPUT ............................................... 27

Revision B (May 2007) から Revision C に変更

Page

•

Added the Signaling rate values to the RECOMMENDED OPERATING CONDITIONS table.............................................. 8•

Changed the IEC 60664-1 RATINGS TABLE - Specification I-III test conditions From: Rated mains voltage ≤150
VRMS To: Rated mains voltage ≤300 VRMS. Added a row for the I-II specifications........................................................... 9•

Added ISO722xM Jitter vs Signaling Rate cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING
CHARACTERISTICS table ................................................................................................................................................... 15•

Added Time-Dependent Dielectric Breakdown Test Results ............................................................................................... 27

Revision A (August 2006) から Revision B に変更

Page

•

Added the TYPICAL CHARACTERISTIC CURVES to the data sheet. ............................................................................... 20•

Added the PARAMETER MEASUREMENT INFORMATION to the data sheet .................................................................. 22•

Added the APPLICATION INFORMATION section to the data sheet.................................................................................. 26•

追加 データシートに『絶縁の用語集』セクション........................................................................................................................ 29

2006年
年7月
月発行のものから更新

Page

•

「特長」のUL 1577の箇条書き項目から「およびCSA承認済み」を 削除....................................................................................... 1•

Added option A to the AVAILABLE OPTIONS table ............................................................................................................ 25

Copyright © 2006–2018, Texas Instruments Incorporated

5

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

5 说明（续）容量が小さく、その結果として時定数も小さいため、高速な動作が可能で、0Mbps (DC)から150Mbpsまでの信号速度に対応できます(ラインの信号速度は、1秒あたりの電圧遷移回数で、bps単位で表されます)。Aオプション、Bオプション、C
オプションのデバイスは、入力にTTL入力しきい値とノイズ・フィルタが存在し、遷移パルスがデバイスの出力に渡されることを防止します。MオプションのデバイスにはCMOS VCC/2入力しきい値が存在し、入力ノイズ・フィルタが存在しないため、追加の伝搬遅延が発生しません。
ISO7220xおよびISO7221xファミリのデバイスは2.8V (Cグレード)、3.3V、5V、またはいずれかの組み合わせの2つの電源電圧を必要とします。2.8Vまたは3.3V電源で動作するとき、すべての入力は5V許容で、すべての出力は4mA CMOSです。
ISO7220xおよびISO7221xファミリのデバイスは、-40℃～+125℃の周囲温度範囲で動作が規定されています。

6

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

Pin Configuration and Functions
ISO7220x D Package
8-Pin SOICTop View

INA 2
INB 3

ISOLATION

VCC1 1

GND1 4

ISO7221x D Package
8-Pin SOICTop View

8 VCC2

VCC1 1

7 OUTAOUTA 26 OUTBINB 3

5 GND2

GND1 48 VCC2

ISOLATION

6

JAJS331P – JULY 2006 – REVISED AUGUST 2018

7 INA
6 OUTB
5 GND2

Pin Functions
PIN

I/O

DESCRIPTION

NAME

ISO7220x

ISO7221x

INA

2

7

I

Input, channel A

INB

3

3

I

Input, channel B

GND1

4

4

—

Ground connection for VCC1

GND2

5

5

—

Ground connection for VCC2

OUTA

7

2

O

Output, channel A

OUTB

6

6

O

Output, channel B

VCC1

1

1

—

Power supply, VCC1

VCC2

8

8

—

Power supply, VCC2

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN

MAX

UNIT

VCC

Supply voltage (2), VCC1, VCC2

–0.5

6

V

VI

Voltage at IN, OUT–0.5

VCC + 0.5 (3)V

IO

Output current

–15

15

mA

TJ

Maximum junction temperature

170

°C

Tstg

Storage temperature

150

°C

(1)
(2)
(3)

–65

Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These ratings are stressratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground pin and are peak voltage values.
Maximum voltage must not exceed 6 V.

7.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)(1)(2)

Electrostatic
discharge

(1)

VALUE

UNIT

±4000

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)

±1000

V

Machine Model, ANSI/ESDS5.2-1996

±200

V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Copyright © 2006–2018, Texas Instruments Incorporated

7

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

7.3 Recommended Operating Conditions
MIN
VCC

Supply voltage (1), VCC1, VCC2

IOH

High-level output current

IOL

Low-level output current

tui

Input pulse width

ISO722xA, ISO722xB, ISO722xM
ISO722xC

MAX
5.5

2.8

5.5

–4

(2)

UNIT
V
mA

4

Signaling rate (2)

1/tui

NOM

3

ISO722xA

1

0.67

ISO722xB

200

100

ISO722xC

40

33ISO722xM

6.67

5ISO722xA

0

1500

1000

ISO722xB0

10

5ISO722xC

0

30

25

ISO722xM

0

200

150

mA
μs

ns

kbps

Mbps

VIH

High-level input voltage

ISO722xA, ISO722xB, ISO722xC

2

5.5

V

VIL

Low-level input voltage

ISO722xA, ISO722xB, ISO722xC

0

0.8

V

VIH

High-level input voltage

ISO722xM

0.7 VCC

VCC

V

VIL

Low-level input voltage

ISO722xM

0

0.3 VCC

V

TJ

Junction temperature

–40

150

°C

H

External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification

1000

A/m

(1)

For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8 V.
Typical signaling rate and Input pulse width are measured at ideal conditions at 25°C.

(2)

7.4 Thermal Information
ISO7220x
ISO7221x

THERMAL METRIC (1)UNIT

D (SOIC)
8 PINS

Low-K Thermal Resistance (2)212

High-K Thermal Resistance

122

RθJA

Junction-to-ambient thermal resistanceRθJC(top)

Junction-to-case (top) thermal resistance

69.1

°C/W

RθJB

Junction-to-board thermal resistance

47.7

°C/W

ψJT

Junction-to-top characterization parameter

15.2

°C/W

ψJB

Junction-to-board characterization parameter

47.2

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

—

°C/W

(1)
(2)

°C/W

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.

7.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 150 Mbps 50% duty cycle square wave
PARAMETER
PD

8Device power dissipation, ISO722xM

TEST CONDITIONSMINTYP MAX

UNIT

390

mW

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 2018

7.6 Insulation Specifications
PARAMETERTEST CONDITIONS

VALUE

UNIT

GENERAL
External clearance (1)Shortest terminal-to-terminal distance through air

4

mm

CPG

External creepage (1)Shortest terminal-to-terminal distance across the
package surface

4

mm

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

0.008

mm

CTI

Comparative tracking index

DIN EN 60112 (VDE 0303-11); IEC 60112

400

V

Rated mains voltage ≤150 VRMS

I-IV

Rated mains voltage ≤300 VRMS

I-III

Rated mains voltage ≤400 VRMS

I-II

CLR

Material group
Overvoltage category

II

DIN VDE V 0884-11:2017-01 (2)
VIORM
VIOTM

Maximum repetitive peak isolation voltage AC voltage (bipolar)
Maximum transient isolation voltage

Apparent charge (3)qpd

Barrier capacitance, input to output (4)CIO

Isolation resistance, input to output (4)

RIO

560

VPK

VTEST = VIOTM
t = 60 s (qualification), t = 1 s (100% production)

4000

VPK

Method a: After I/O safety test subgroup 2/3, Vini =VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s

≤5

Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.3 × VIORM, tm =
10 s

≤5

Method b1: At routine test (100% production) andpreconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.5 × VIORM, tm = 1 s≤5

VIO = 0.4 sin (4E6πt)1

VIO = 500 V, TA = 25°C

>1012

VIO = 500 V, 100°C ≤ TA ≤ 125°C>1011

VIO = 500 V at TS = 150°C>109

Pollution degree

2

Climatic category

40/125/21

pC

pF
Ω

UL 1577
VISO
(1)

(2)
(3)
(4)

Withstand isolation voltage

VTEST = VISO = 2500 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100%production)

2500

VRMS

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Careshould be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shallbe ensured by means of suitable protective circuits.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device

Copyright © 2006–2018, Texas Instruments Incorporated

9

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

7.7 Safety-Related Certifications
VDE

CSA

UL

Certified according to DIN VDE V 088411:2017-01 and DIN EN 61010-1 (VDE
0411-1):2011-07

Certified according to IEC 60950-1 and IEC 62368- Recognized under UL 1577
1
Component Recognition Program

Basic Insulation
Maximum Transient Overvoltage, 4000 VPK;
Maximum Repetitive Peak Isolation Voltage,
560 VPK

2000 VRMS Isolation rating
400 VRMS Basic insulation and 148 VRMS
Reinforced insulation working voltage per CSA
60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.
+A1+A2.
300 VRMS Basic insulation working voltage per
CSA 62369-1-14 and IEC 62368-1:2014 Ed. 2.

Single protection, 2500 VRMS

Certificate number: 40047657

Master contract number: 220991

File number: E181974

7.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failureof the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER

IS

TS

Safety input, output, or supply
current
Safety temperature

TEST CONDITIONS

MIN

TYP

MAX

RθJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C,
see Figure 1

124

RθJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C,
see Figure 1

190

UNIT

mA

150

°C

(1)

The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mountpackages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.

10

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 2018

7.9 Electrical Characteristics—5-V VCC1 and V CC2 Supplies
VCC1 and V CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER

ICC1

ICC2

VCC1 supply current

VCC2 supply current

VOH

High-level output voltage

VOL

Low-level output voltage

TEST CONDITIONS

MIN

TYP

MAX

ISO7220x quiescent, VI = VCC or 0 V, no load

12

ISO7221 quiescent, VI = VCC or 0 V, no load

8.5

17

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz
input clock signal, no load

2

3

ISO7221A, ISO7221B 1 Mbps, 0.5-MHz input
clock signal, no load

1018

ISO7220C, ISO7220M 25 Mbps, 12.5-MHz
input clock signal, no load

49ISO7221C and ISO7221M 25 Mbps, 12.5-MHz
input clock signal, no load

1222ISO7220x quiescent, VI = VCC or 0 V, no load

16

31

ISO7221x quiescent, VI = VCC or 0 V, no load

8.5

17

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz
input clock signal, no load

17

32

ISO7221A, ISO7221B 1 Mbps, 0.5-MHz input
clock signal, no load

1018

ISO7220C, ISO7220M 25 Mbps, 12.5-MHz
input clock signal, no load

20

34

ISO7221C and ISO7221M 25 Mbps, 12.5-MHz
input clock signal, no load

12

22

mA

mA

VCC – 0.8

4.6

VCC – 0.1

5V

IOL = 4 mA, See Figure 14

0.2

0.4

IOL = 20 μA, See Figure 140

0.1

VI(HYS) Input voltage hysteresis

150

High-level input current

IN from 0 V to VCC

Low-level input current

IN from 0 V to VCC

CI

Input capacitance to ground

IN at VCC, VI = 0.4 sin (4E6πt)

CMTI

Common-mode transient immunity

VI = VCC or 0 V, See Figure 16

Copyright © 2006–2018, Texas Instruments Incorporated

mA

mA

IOH = –20 μA, See Figure 14

IIL

mA

mA

IOH = –4 mA, See Figure 14

IIH

UNIT

mV
10

–10
25

V

μA
μA

1

pF

50

kV/μs

11

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

7.10 Electrical Characteristics—5-V VCC1 and 3.3-V VCC2 Supply
VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER

ICC1

ICC2

VOH

VCC1 supply current

VCC2 supply current

High-level output voltage

TYP

MAX

ISO7220x quiescent, VI = VCC or 0 V, no load

TEST CONDITIONS

1

2

ISO7221x quiescent, VI = VCC or 0 V, no load

8.5

17

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input
clock signal, no load

2

3

ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input
clock signal, no load

1018

ISO7220C and ISO7220M 25 Mbps, 12.5-MHz
input clock signal, no load

49ISO7221C and ISO7221M 25 Mbps, 12.5-MHz
input clock signal, no load

12

22

8

18

4.3

9.5

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input
clock signal, no load

919ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input
clock signal, no load

511ISO7220C and ISO7220M 25 Mbps, 12.5-MHz
input clock signal, no load

1020

ISO7221C and ISO7221M 25 Mbps, 12.5-MHz
input clock signal, no load

6

12

mA

VCC – 0.4

ISO7221x (5-V side), IOH = –4 mA, See Figure 14

VCC – 0.8

All devices, IOH = –20 μA, See Figure 14

VCC – 0.1

V

IOL = 4 mA, See Figure 14

0.4

IOL = 20 μA, See Figure 14

0.1

Input voltage hysteresis

IIH

High-level input current

IN from 0 V to VCC

IIL

Low-level input current

IN from 0 V to VCC

CI

Input capacitance to ground

IN at VCC, VI = 0.4 sin (4E6πt)

CMTI

Common-mode transient immunity

VI = VCC or 0 V, See Figure 16

mA

mA

ISO7220x, ISO7221x (3.3-V side), IOH = –4 mA,
See Figure 14

VI(HYS)

mA

mA

ISO7221x quiescent, VI = VCC or 0 V, no load

Low-level output voltage

UNIT

mA

ISO7220x quiescent, VI = VCC or 0 V, no load

VOL

12

MIN

150

mV
10

–10

15

V

μA
μA

1

pF

40

kV/μs

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 20187.11 Electrical Characteristics—3.3-V VCC1 and 5-V VCC2 Supply
VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER

ICC1

ICC2

VOH

VCC1 supply current

VCC2 supply current

High-level output voltage

TYP

MAX

ISO7220x quiescent, VI = VCC or 0 V, no load

TEST CONDITIONS

MIN

0.6

1

ISO7221x quiescent, VI = VCC or 0 V, no load

4.3

9.5

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal,
no load1

2ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal,
no load5

11

ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock
signal, no load

2

4ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock
signal, no load

6

12ISO7220x quiescent, VI = VCC or 0 V, no load

16

31

ISO7221x quiescent, VI = VCC or 0 V, no load

8.5

17

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal,
no load

18

32

ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal,
no load10

18

ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock
signal, no load

20

34

ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock
signal, no load

12

22

mA

mA

ISO7221x (3.3-V side), IOH = –4 mA, See Figure 14

VCC – 0.4

All devices, IOH = –20 μA, See Figure 14

VCC – 0.1

V

IOL = 4 mA, See Figure 14

VI(HYS)

Input threshold voltage hysteresis

IIH

High-level input current

IN from 0 V or VCC

IIL

Low-level input current

IN from 0 V or VCC

CI

Input capacitance to ground

IN at VCC, VI = 0.4 sin (4E6πt)

CMTI

Common-mode transient immunity

VI = VCC or 0 V, See Figure 16

0.4

IOL = 20 μA, See Figure 14

0

0.1

150

Copyright © 2006–2018, Texas Instruments Incorporated

mA

mA

VCC – 0.8

Low-level output voltage

mA

mA

ISO7220x and ISO7221x (5-V side), IOH = –4 mA, See
Figure 14

VOL

UNIT

mV
10

–10

15

μA
μA

1

pF

40

kV/μs

13

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

7.12 Electrical Characteristics—3.3-V VCC1 and VCC2 Supplies
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) (1)
PARAMETER

ICC1

VCC2 supply current

ICC2

VCC2 supply current

TYP

MAX

ISO7220x quiescent, VI = VCC or 0 V, no load

TEST CONDITIONS

0.6

1

ISO7221x quiescent, VI = VCC or 0 V, no load

4.3

9.5

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal,
no load1

2ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal,
no load5

11

ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock
signal, no load

2

4ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock
signal, no load

6

12

8

18

4.3

9.5

ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal,
no load

919ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal,
no load5

11

ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock
signal, no load

1020

ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock
signal, no load

6

12

mA

VCC – 0.4

3

IOH = –20 μA, See Figure 14

VCC – 0.1

3.3

Low-level output voltage

VI(HYS)

Input voltage hysteresis

IIH

High-level input current

IN from 0 V or VCC

IIL

Low-level input current

IN from 0 V or VCC

CI

Input capacitance to ground

IN at VCC, VI = 0.4 sin (4E6πt)

CMTI

Common-mode transient immunity

VI = VCC or 0 V, See Figure 16

mA

mA

IOH = –4 mA, See Figure 14

VOL

mA

mA

ISO7221x quiescent, VI = VCC or 0 V, no load

High-level output voltage

UNIT

mA

ISO7220x quiescent, VI = VCC or 0 V, no load

VOH

(1)

MIN

IOL = 4 mA, See Figure 14
IOL = 20 μA, See Figure 14

0.2

0.4

0

0.1

150

mV
10

–10

15

V

μA
μA

1

pF

40

kV/μs

For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.

7.13 Electrical Characteristics—2.8-V VCC1 and VCC2 Supplies
VCC1 and VCC2 at 2.8 V (over recommended operating conditions unless otherwise noted.) 2.8-V operation is only specified forISO722xC with production screening starting in January 2012. The first two digits of the Lot Trace Code (YMSLLLLG4)
written on top of each device can be used to identify year and month of production respectively.
PARAMETER

ICC1

ICC2

VOH

VCC1 supply current

VCC2 supply current

High-level output voltage

TYP

MAX

ISO7220C quiescent, VI = VCC or 0 V, no load

TEST CONDITIONS

0.4

0.9

ISO7221C quiescent, VI = VCC or 0 V, no load

3.7

7.5

ISO7220C 25 Mbps, 12.5-MHz input clock signal, no load

1.5

3.5

ISO7221C 25 Mbps, 12.5-MHz input clock signal, no load

4.5

10

ISO7220C quiescent, VI = VCC or 0 V, no load

6.8

15

ISO7221C quiescent, VI = VCC or 0 V, no load

3.7

7.5

ISO7220C 25 Mbps, 12.5-MHz input clock signal, no load

917ISO7221C 25 Mbps, 12.5-MHz input clock signal, no load

4.5

10

IOH = –4 mA, See Figure 14

VCC – 0.6

IOH = –20 μA, See Figure 14

VCC – 0.1

IOL = 4 mA, See Figure 14

VOL

Low-level output voltage

VI(HYS)

Input voltage hysteresis

IIH

High-level input current

IN from 0 V or VCC

IIL

Low-level input current

IN from 0 V or VCC

CI

Input capacitance to ground

IN at VCC, VI = 0.4 sin (4E6πt)

CMTI

Common-mode transient immunity

VI = VCC or 0 V, See Figure 16

14

MIN

IOL = 20 μA, See Figure 14

mA

mA

mA

mA

2.55
2.8
0.25

0.6

0

0.1

150

–10

V

mV
10

10

UNIT

μA
μA

1

pF

30

kV/μs

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 20187.14 Switching Characteristics—5-V VCC1 and VCC2 Supplies
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETERtPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tsk(pp)Part-to-part skew (2)TEST CONDITIONS
ISO722xA, see Figure 14

ISO722xB, see Figure 14

ISO722xC, see Figure 14

ISO722xM, see Figure 14

MIN

TYP

MAX

UNIT

280

405

600

ns

1

18

ns

55

70

ns

1

3

ns

32

42

ns

1

2

ns

10

16

ns

0.5

1

ns

42

22

6

ISO722xA

180

ISO722xB

17

ISO722xC

10ISO722xM

tsk(o)

Channel-to-channel output skew (3)trOutput signal rise timetf

Output signal fall time

tfs

Failsafe output delay time from input powerlosstjit(pp)

Peak-to-peak eye-pattern jitter

(1)
(2)
(3)

ns

3

ISO7220A

3

15

ISO7220B

0.6

3

ISO7220C, ISO7220M

0.2

1

ns

1

ns

1

ns

See Figure 15

3μs

ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max samepolarity input, both channels, See Figure 17, Figure 13

1

ISO722xM, 150 Mbps unrestricted bit run length data
input, both channels, See Figure 17

2

See Figure 14

ns

Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.

Copyright © 2006–2018, Texas Instruments Incorporated

15

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

7.15 Switching Characteristics—5-V VCC1 and 3.3-V VCC2 Supply
VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETERtPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tsk(pp)Part-to-part skew (2)TEST CONDITIONS
ISO722xA, see Figure 14

MIN

TYP

MAX

UNIT

285

410

585

ns

1

18

ns

58

75

ns

1

3

ns

36

48

ns

1

2

ns

12

20

ns

0.5

1

ns

45

ISO722xB, see Figure 14

25

ISO722xC, see Figure 14

7

ISO722xM, see Figure 14
ISO722xA

180

ISO722xB

17

ISO722xC

10ISO722xM

tsk(o)

Channel-to-channel output skew (3)trOutput signal rise timetf

Output signal fall time

tfs

Failsafe output delay time from input powerlosstjit(pp)

Peak-to-peak eye-pattern jitter

(1)
(2)
(3)

16

ns

5

ISO7220A

3

15

ISO7220B

0.6

3

ISO7220C, ISO7220M

0.2

1

ns

2

ns

2

ns

See Figure 15

3μs

ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max samepolarity input, both channels, See Figure 17, Figure 13

1

ISO722xM, 150 Mbps unrestricted bit run length data
input, both channels, See Figure 17

2

See Figure 14

ns

Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 20187.16 Switching Characteristics—3.3-V CC1 and 5-V VCC2 Supplies
VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETERtPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tsk(pp)Part-to-part skew (2)TEST CONDITIONS
ISO722xA, see Figure 14

ISO722xB, see Figure 14

ISO722xC, see Figure 14

ISO722xM, see Figure 14

MIN

TYP

MAX

UNIT

285

395

605

ns

1

22

ns

58

75

ns

1

4

ns

36

48

ns

1

3

ns

12

21

ns

0.5

1

ns

45

25

7

ISO722xA

190

ISO722xB

17

ISO722xC

10ISO722xM

tsk(o)

Channel-to-channel output skew (3)trOutput signal rise timetf

Output signal fall time

tfs

Failsafe output delay time from input powerlosstjit(pp)

Peak-to-peak eye-pattern jitter

(1)
(2)
(3)

ns

5

ISO7220A

3

15

ISO7220B

0.6

3

ISO7220C, ISO7220M

0.2

1

ns

1

ns

1

ns

See Figure 15

3μs

ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max samepolarity input, both channels, see Figure 17, Figure 13

1

ISO722xM, 150 Mbps unrestricted bit run length data
input, both channels, see Figure 17

2

See Figure 14

ns

Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.

Copyright © 2006–2018, Texas Instruments Incorporated

17

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

7.17 Switching Characteristics—3.3-V VCC1 and VCC2 Supplies
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETERtPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tsk(pp)Part-to-part skew (2)TEST CONDITIONS
ISO722xA, see Figure 14

MIN

TYP

MAX

UNIT

290

400

610

ns

1

22

ns

62

78

ns

1

4

ns

40

52

ns

1

3

ns

16

25

ns

0.5

1

ns

46

ISO722xB, see Figure 14

26

ISO722xC, see Figure 14

8

ISO722xM, see Figure 14
ISO722xA

190

ISO722xB

17

ISO722xC

10ISO722xM
Channel-to-channel output skew (3)tsk(o)
tr

Output signal rise timetf

Output signal fall time

tfs

Failsafe output delay time from input powerlosstjit(pp)

Peak-to-peak eye-pattern jitter

(1)
(2)
(3)

ns

5

ISO7220A

3

15

ISO7220B

0.6

3

ISO7220C, ISO7220M

0.2

1

ns

2

ns

2

ns

See Figure 15

3μs

ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max samepolarity input, both channels, See Figure 17, Figure 13

1

ISO722xM, 150 Mbps unrestricted bit run length data
input, both channels, See Figure 17

2

See Figure 14

ns

Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.

7.18 Switching Characteristics—2.8-V VCC1 and VCC2 Supplies
VCC1 and VCC2 at 2.8 V (over recommended operating conditions unless otherwise noted.)
PARAMETERTEST CONDITIONStPLH, tPHL

Propagation delay

PWD

Pulse-width distortion |tPHL – tPLH| (1)tsk(pp)Part-to-part skew (2)ISO722xC

tsk(o)

Channel-to-channel output skew (3)ISO7220C

tr

Output signal rise timetf

Output signal fall time

tfs

Failsafe output delay time from input power
loss

(1)
(2)
(3)

18

ISO722xC, see Figure 14

See Figure 14
See Figure 15

MIN

TYP

MAX

UNIT

26

45

65

ns

1.5

5

ns

12

ns

5

ns

0.2
2

ns

2

ns

4.6

μs

Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 20187.19 Insulation Characteristics Curves
250

Safety Limiting Current - mA

225
VCC1,2 at 3.6 V

200
175
150
125

VCC1,2 at 5.5 V

100
75
50
25
0
0

50

100
150
TC - Case Temperature - °C

200

Figure 1. Thermal Derating Curve for Limiting Current per VDE

Copyright © 2006–2018, Texas Instruments Incorporated

19

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

7.20 Typical Characteristics
20

30
TA = 25°C,
15 pF Load

18

26

16

ISO7220x ICC2

24

14

ICC - Supply Current - mA

ICC - Supply Current - mA

TA = 25°C,
15 pF Load28

ISO7220x ICC21210ISO7221x ICC1&2

8
6
4

ISO7220x ICC12220ISO7221x ICC1&2

18
16
14
12
10

ISO7220x ICC1

8
6
4

2

2
0

0
0

25

50

75

100

Signaling Rate - Mbps

5075
Signaling Rate - Mbps

Figure 2. 3.3-VRMS Supply Current vs Signaling Rate
(Mbps)

Figure 3. 5-VRMS Supply Current vs Signaling Rate
(Mbps)

450

25

100

70
TA = 25°C,
15 pF Load

15 pF Load

440

65

Propagation Delay - ns

430

Propagation Delay - ns

0420

VCC = 3.3 V
410

tpLH & tpHL

400

VCC = 5 V
390

tpLH & tpHL
380
370

tPLH & tPHL

VCC = 3.3 V
60

VCC = 5 V

55

tPLH & tPHL

50

360
350
-40

-15

10

35

60

85

45
-40

110 125

Temperature - °C

25
Temperature - °C

Figure 4. Propagation Delay vs Free-Air Temperature,
ISO722xA

Figure 5. Propagation Delay vs Free-Air Temperature,
ISO722xB

30

20

VCC = 3.3 V

25

VCC = 3.3 V

tpLH & tpHL

15

Propagation Delay - ns

Propagation Delay - ns

125

20

15

tpLH & tpHL

VCC = 5 V

10

tpLH & tpHL

10

tpLH & tpHL

VCC = 5 V

5
5

0
-40

20

15 pF Load

-15

10

35

60

85

110 125

15 pF Load

0
-40

-15

10

35

60

85

110 125

Temperature - °C

Temperature - °C

Figure 6. Propagation Delay vs Free-Air Temperature,
ISO722xC

Figure 7. Propagation Delay vs Free-Air Temperature,
ISO722xM

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 2018

Typical Characteristics (continued)
2.5

1.4

2.4

5-V Vth+

1.35

5-V Vth+1.3

Input Voltage Threshold - V

Input Voltage Threshold - V

2.3

3.3-V Vth+

1.25

15 pF Load

1.2

1.15

5-V Vth1.1

2.2

5-V Vth-

2.1
2

15 pF Load
1.9
1.8

3.3-V Vth+

1.7
1.6

1.05

1.5

3.3-V Vth-40 -25 -10

5

20

35

50

65

80

95

3.3-V Vth-

1.4
-40 -25 -101

110 125

5

20

35

50

65

80

95

110 125

Temperature - °C

Temperature - °C

Figure 8. ISO722xA, ISO722xB and ISO722xC Input Voltage
Low-to-High Switching Threshold vs Free-Air Temperature

Figure 9. ISO722xM Input Voltage High-to-Low
vs Free-Air Temperature-80
15 pF Load
TA = 25°C

-70
2.64

-60
VCC = 5 V

VCC Rising
-50

2.6

IOUT - mA

Power Supply Undervoltage Threshold - V

2.68

2.56

-40
-30

VCC Falling

VCC = 3.3 V

-20
2.52

-10
2.48
-40 -25 -10

0
5

20

35

50

65

80

95

110 125

0

2

4

6

Free-Air Temperature - °C

VOUT - V

Figure 10. VCC Undervoltage Threshold vs Free-Air
Temperature

Figure 11. High-Level Output Current vs High-Level Output
Voltage70

2000
15 pF Load
TA = 25°C

60

VCC = 5 V

1600

50

1400
1200

40

Jitter − ps

IOUT - mA

15 pF Load
TA = 25°C

1800

VCC = 3.3 V
30

VCC1 = VCC2 = 5 V

1000
800
600

20

VCC1 = VCC2 = 3.3 V
400

10
200
0

0
0

1

2

3

4

5

0

50

100

150

200

VOUT - V

Signaling Rate - Mbps

Figure 12. Low-Level Output Current vs Low-Level Output
Voltage

Figure 13. ISO722xM Jitter vs Signaling Rate

Copyright © 2006–2018, Texas Instruments Incorporated

21

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

ISOLATION BARRIER

8 Parameter Measurement Information

IN
Input
Generator

VI

50 W

NOTE A

VCC
VI

VCC/2

VCC/2

OUT

0V
tPHL

tPLH
CL
NOTE B

VO

VO

VOH

90%

50%

50%

10%
tr

tf

A.

The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.

B.

CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%.

VOL

Figure 14. Switching Characteristic Test Circuit and Voltage Waveforms
VI
ISOLATION BARRIER

VCC

IN = 0 V

A.

VCC
OUT

VI

2.7 V

VO

0V
VOH

tfs

CL
NOTE AVO

50%

FAILSAFE HIGH
VOL

CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%.

Figure 15. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCCO

VCCI

S1

Isolation Barrier

C = 0.1 µF ±1%

IN

C = 0.1 µF ±1%
Pass-fail criteria:
The output mustremain stable.
OUT
+
EN

VOH or VOL

CL
See Note A

GNDI

+

VCM ±

±

GNDO

Copyright © 2016, Texas Instruments Incorporated

A.

CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%.

Figure 16. Common-Mode Transient Immunity Test Circuit

22

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 2018

Parameter Measurement Information (continued)
VCC

DUT
Tektronix
HFS9009

IN

OUT

0V

Tektronix
784D

PATTERN
GENERATOR

VCC/2

Jitter

NOTE: PRBS bit pattern run length is 2

16

– 1. Transition time is 800 ps.

Figure 17. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform

Copyright © 2006–2018, Texas Instruments Incorporated

23

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

9 Detailed Description
9.1 Overview
The isolator in theFunctional Block Diagram is based on a capacitive isolation barrier technique. The I/O channelof the ISO7220x and ISO7221x family of devices consists of two internal data channels, a high-frequency
channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering therange from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a
differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate thesignal into transients, which then are converted into differential pulses by two comparators. The comparator
outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving
output of the flip-flop measures the durations between signal transients. If the duration between two consecutive
transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the outputmultiplexer to switch from the high-frequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, thesesignals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating asufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-passfilter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.

9.2 Functional Block Diagram
Isolation Barrier

OSC
LPF
Low t Frequency
Channel(DC...100 kbps)

PWM

VREF
0
OUT
1 S

IN

DCL
High t Frequency
Channel(100 kbps...150 Mbps)

VREF

Copyright © 2016, Texas Instruments Incorporated

24

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 2018

9.3 Feature Description
Table 1 provides an overview of the device features.
Table 1. Device Features
PART NUMBER

MAXIMUM SIGNALING
RATE

INPUT
THRESHOLDCHANNEL
DIRECTION

ISO7220A

1 Mbps≈ 1.5 V (TTL)(CMOS compatible)

ISO7220B

5 Mbps≈ 1.5 V (TTL)(CMOS compatible

ISO7220C

25 Mbps≈ 1.5 V (TTL)(CMOS compatible)

ISO7220M

150 Mbps

VCC/ 2 (CMOS)

ISO7221A

1 Mbps≈ 1.5 V (TTL)(CMOS compatible)

ISO7221B

5 Mbps≈ 1.5 V (TTL)(CMOS compatible)

ISO7221C

25 Mbps≈ 1.5 V (TTL)(CMOS compatible)

ISO7221M

150 Mbps

VCC/ 2 (CMOS)

Same direction

Opposite directions

9.4 Device Functional Modes
The ISO7220x and ISO7221x family of devices functional modes are listed in Table 2.
Table 2. ISO7220x or ISO7221x Function Table (1)(1)

INPUT SIDE VCC

OUTPUT SIDE VCC

PU

PU

INPUT (IN)

OUTPUT (OUT)

H

H

L

L

Open

H

PD

PU

X

H

X

PD

X

Undetermined

PU = Powered Up (VCC ≥ 3.0 V), PD = Powered Down (VCC ≤ 2.5 V), X = Irrelevant, H = High Level,
L = Low Level
Input
VCC1

VCC1

VCC1

Output
VCC2

750 kW
IN

8W

500 W

OUT
13 W

Figure 18. Device I/O Schematics

Copyright © 2006–2018, Texas Instruments Incorporated

25

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.ti.com

10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information
The ISO7220x and ISO7221x family devices use single-ended TTL or CMOS-logic switching technology. The
supply voltage range is from 3 V (2.8 V for C-grade) to 5.5 V for both supplies, VCC1 and VCC2. When designingwith digital isolators, because of the single-ended design structure, digital isolators do not conform to any specificinterface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator
is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver,regardless of the interface type or standard.

10.2 Typical Application
The ISO7221x family of devices can be used with Texas Instruments' mixed signal micro-controller, digital-toanalog converter, transformer driver, and voltage regulator to create an isolated 4- to 20-mA current loop.
VS
3.3 V

0.1 F

2

1:1.33

VCC D2 3

MBR0520L
1

SN650110 F

GND D1

0.1 F

IN

OUT

3.3VISO

5

10 F

TPS76333
3

1

EN

GND

2

10 F
MBR0520L

4, 5

0.1 F

ISO-BARRIER

0.1 F

20

LOOP+

0.1 F

0.1 F

15

0.1 F
10
1

8

2
5
6

DVCC
XOUT
XIN

MSP430
G2132

8

P3.0 11
12
P3.1

VCC1

VCC2

2 OUTA

INA
ISO7221

3 INB

OUTB

DVSS

GND1

GND2

4

4

5

7

5

6

4

3
VA

VD

LOW

BASE

ERRLVL16
0.1 F

DAC161P997
22

DBACK
DIN

C1

14
3 × 22 nF

1 F

C2C3 COMA

13

12

1

OUT
COMD

9
LOOP±

2

Figure 19. Isolated 4- to 20-mA Current Loop
10.2.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias (or limit current),
the ISO7220x and ISO7221x devices require only two external bypass capacitors to operate.

26

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com

JAJS331P – JULY 2006 – REVISED AUGUST 2018

Typical Application (continued)
10.2.2 Detailed Design Procedure
Figure 20 and Figure 21 show the hookup of a typical ISO7220x and ISO7221x circuit. The only external
components are two bypass capacitors.
V CC1

V CC 2

0.1mF

2 mm
max .
from
Vcc 1

INPUT

1
INA 2
INB

INPUT

3
4

8
OUTA
7
OUTB
6
5

2 mm
max .
from
Vcc 2

0.1mF
OUTPUTOUTPUT

ISO7220

GND 1

GND 2

Figure 20. Typical ISO7220x Circuit Hook-Up
V CC1

V CC2

0.1mF

2 mm
max .
from
Vcc1

OUTPUT

1
OUTA
2
INB

INPUT

3
4

8
INA
7
OUTB
6
5

2 mm
max .
from
Vcc 2

0.1mF
INPUT
OUTPUT

ISO7221

GND 1

GND 2

Figure 21. Typical ISO7221x Circuit Hook-Up
10.2.3 Application Curve
At maximum working voltage, the isolation barrier of the ISO7220x and ISO7221x family of devices has morethan 28 years of life.

Working Life (Years)

100

VIORM at 560 VPK

28

10
0

120

250

500

750

880

1000

Working Voltage, VIORM (VPK)

Figure 22. Time-Dependent Dielectric Breakdown Test Results

Copyright © 2006–2018, Texas Instruments Incorporated

27

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.tij.co.jp

11 Power Supply Recommendations
To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor isrecommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the
supply pins as possible. If only a single primary-side power supply is available in an application, isolated power
can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments
SN6501 device. For such applications, detailed power supply design and transformer selection recommendations
are available in SN6501 Transformer Driver for Isolated Power Supplies.

12 Layout12.1 Layout Guidelines
A minimum of four layers are required to accomplish a low EMI PCB design (see Figure 23). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer.
• Route the high-speed traces on the top layer to avoid the use of vias (and the introduction of the inductances)
and allow for clean interconnects between the isolator and the transmitter and receiver circuits of the datalink.
• Place a solid ground plane next to the high-speed signal layer to establish controlled impedance fortransmission line interconnects and provide an excellent low-inductance path for the return current flow.
• Place the power plane next to the ground plane to create additional high-frequency bypass capacitance ofapproximately 100 pF/in2.
• Route the slower speed control signals on the bottom layer to allow for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system tothe stack to keep it symmetrical. Adding a second plane system to the stack makes the stack mechanicallystable and prevents it from warping. The power and ground plane of each power system can be placed closer
together, thus increasing the high-frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength andstiffness, and the self-extinguishing flammability-characteristics.

12.2 Layout Example
High-speed traces
10 mils

Ground plane

40 mils

Keep this space
free from planes,
traces, pads, and
vias

FR-4
0r ~ 4.5

Power plane
10 mils

Low-speed traces

Figure 23. Recommended Layer Stack

28

Copyright © 2006–2018, Texas Instruments Incorporated

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.tij.co.jp

JAJS331P – JULY 2006 – REVISED AUGUST 2018

13 デバイスおよびドキュメントのサポート
13.1 デバイス・サポート
13.1.1 開発サポート
開発サポートについては、次の資料を参照してください。
• DALI DMX512 と電力線通信を使用したAC電源LEDライティングのリファレンス・デザイン• 産業用サーボ・ドライブとACインバータ・ドライブのリファレンス・デザイン• 低コスト単相/二相絶縁電気測定回路のリファレンス・デザイン• ノイズ耐性のある静電容量式タッチHMIのリファレンス・デザイン• Type 2 PoE PSE、6kVの雷サージのリファレンス・デザイン

13.2 ドキュメントのサポート
13.2.1 関連資料
関連資料については、以下を参照してください。
• テキサス・インスツルメンツ、『DAC161P997 シングル・ワイヤの4～20mAループ用16ビットDAC』データシート• テキサス・インスツルメンツ、『デジタル・アイソレータ設計ガイド』• テキサス・インスツルメンツ、『ISO72xファミリのデジタル・アイソレータの高電圧寿命』アプリケーション・レポート• テキサス・インスツルメンツ、『絶縁の用語集』• テキサス・インスツルメンツ、『MSP430G2x32 ミクスト・シグナル・マイクロコントローラ』データシート• テキサス・インスツルメンツ、『SN6501 絶縁電源用の変圧器ドライバ』データシート• テキサス・インスツルメンツ、『TPS763xx 低消費電力、150mA、低ドロップアウトのリニア・レギュレータ』データシート

13.3 関連リンク
次の表に、クイック・アクセス・リンクを示します。カテゴリには、技術資料、サポートおよびコミュニティ・リソース、ツールとソフ
トウェア、およびサンプル注文またはご購入へのクイック・アクセスが含まれます。
表 3. 関連リンク
製品

プロダクト・フォルダ

ご注文はこちら

技術資料

ツールとソフトウェア

サポートとコミュニティ

ISO7220A

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ISO7220B

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ISO7220C

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ISO7220M

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ISO7221A

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ISO7221B

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ISO7221C

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ISO7221M

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

13.4 ドキュメントの更新通知を受け取る方法
ドキュメントの更新についての通知を受け取るには、ti.comのデバイス製品フォルダを開いてください。右上の隅にある「通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。

13.5 コミュニティ・リソース
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™オオンライン・コミュニティ TIのE2E（Engineer-to-Engineer）コミュニティ。エンジニア間の共同作業を促進するために開設されたものです。e2e.ti.comでは、他のエンジニアに質問し、知識を共有
し、アイディアを検討して、問題解決に役立てることができます。
Copyright © 2006–2018, Texas Instruments Incorporated

29

ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
JAJS331P – JULY 2006 – REVISED AUGUST 2018www.tij.co.jp

コミュニティ・リソース (continued)
設計サポート TIの設計サポート 役に立つE2Eフォーラムや、設計サポート・ツールをすばやく見つけることができます。技術サポート用の連絡先情報も参照できます。

13.6 商標
E2E is a trademark of Texas Instruments.
DeviceNet is a trademark of Open DeviceNet Vendors Association.
Profibus is a trademark of Profibus.
All other trademarks are the property of their respective owners.

13.7 静電気放電に関する注意事項
すべての集積回路は、適切なESD保護方法を用いて、取扱いと保存を行うようにして下さい。
静電気放電はわずかな性能の低下から完全なデバイスの故障に至るまで、様々な損傷を与えます。高精度の集積回路は、損傷に対して敏感であり、極めてわずかなパラメータの変化により、デバイスに規定された仕様に適合しなくなる場合があります。

13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 メカニカル、パッケージ、および注文情報
以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。この情報は、そのデバイスについて利用可能な最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。

30

Copyright © 2006–2018, Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM
www.ti.com

2-Oct-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

ISO7220ADOBSOLETE

SOIC

D

8

TBD

Call TI

Call TI-40 to 125

I7220A

ISO7220ADR

ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7220A

Samples

ISO7220ADRG4ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7220A

Samples

TBD

Call TI

Call TI-40 to 125

I7220B

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7220B

TBD

Call TI

Call TI-40 to 125

I7220C

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7220C

TBD

Call TI

Call TI-40 to 125

I7220M

ISO7220BD

OBSOLETE

SOIC

D

8

ISO7220BDR

ACTIVE

SOIC

D

8

Samples

ISO7220CD

OBSOLETE

SOIC

D

8

ISO7220CDR

ACTIVESOIC

D

8ISO7220MDOBSOLETE

SOIC

D

8

ISO7220MDR

ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7220M

Samples

ISO7220MDRG4ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7220M

Samples

ISO7221ADR

ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7221A

Samples

ISO7221ADRG4ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7221A

Samples

ISO7221BDR

ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7221B

Samples

ISO7221BDRG4ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7221B

Samples

Samples

ISO7221CD

OBSOLETE

SOIC

D

8

TBD

Call TI

Call TI-40 to 125

I7221CISO7221CDR

ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7221C

Samples

ISO7221CDRG4ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7221C

Samples

ISO7221MD

OBSOLETE

SOIC

D

8

TBD

Call TI

Call TI-40 to 125

I7221M

ISO7221MDR

ACTIVESOIC

D

8RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 125

I7221M

2500(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM
www.ti.com

2-Oct-2024

OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7220A, ISO7221A, ISO7221C :• Automotive : ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1
NOTE: Qualified Version Definitions:• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

ISO7220ADR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO7220BDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO7220CDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO7220MDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO7221ADR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO7221BDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO7221CDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO7221MDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)ISO7220ADR

SOIC

D

8

2500

350.0

350.0

43.0

ISO7220BDR

SOIC

D

8

2500

350.0

350.0

43.0

ISO7220CDR

SOIC

D

8

2500

350.0

350.0

43.0

ISO7220MDR

SOIC

D

8

2500

350.0

350.0

43.0

ISO7221ADR

SOIC

D

8

2500

350.0

350.0

43.0

ISO7221BDR

SOIC

D

8

2500

350.0

350.0

43.0

ISO7221CDR

SOIC

D

8

2500

350.0

350.0

43.0

ISO7221MDR

SOIC

D

8

2500

350.0

350.0

43.0

Pack Materials-Page 2

PACKAGE OUTLINE

D0008ASOIC - 1.75 mm max height
SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUITCSEATING PLANE.228-.244 TYP[5.80-6.19]
A.004 [0.1] C

PIN 1 ID AREA
6X .050[1.27]
8

1

2X
.150
[3.81].189-.197[4.81-5.00]
NOTE 3

4X (0 -15 )4
5
B

8X .012-.020[0.31-0.51].010 [0.25]
C A B.150-.157[3.81-3.98]
NOTE 4.069 MAX[1.75].005-.010 TYP[0.13-0.25]

4X (0 -15 )SEE DETAIL A.010[0.25].004-.010[0.11-0.25]

0 -8.016-.050[0.41-1.27]

DETAIL A(.041)[1.04]TYPICAL

4214825/C 02/2019

NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM

SEE
DETAILS

1
8
8X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X

METAL

SOLDER MASKOPENINGEXPOSED
METAL.0028 MAX
[0.07]ALL AROUNDSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSED
METAL.0028 MIN
[0.07]ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM
1
88X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCILSCALE:8X

4214825/C 02/2019

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要なお知らせと免責事項
TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。
これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した
TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。
上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプ
リケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TIは一切の責任を拒否します。
TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。
お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE
郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated