Jasper Li

TI Designs: PMP9773 Reference Guide

USB Power Supply Using TPS61088 to Support Quick
Charge 2.0

TI Designs

Circuit Description

TI Designs are analog solutions created by TI’s
analog experts. Reference designs offer the theory,component selection, and simulation of useful circuits.
Circuit modifications that help to meet alternate
design goals are also discussed.

This Reference-Design is to power the USB port thataims to support Quick Charge 2.0 from Lithium-ion
battery or a voltage supply between 2.7 V and 4.4 V.
The Reference-Design includes a boost converter
TPS61088 to boost the input voltage up to 12 V, a 12V E-fuse TPS2592AA with 2-A to 3.7-A adjustablecurrent limit for short circuit protection and a QC2.0
interface IC CHY100 to adjust output voltage
according to the Quick Charge 2.0 standard. This
Reference-Design can support 5V&3A, 9V&2A and12V&1.5A output power.

Design Resources
Design Page

All Design files

TPS61088

Datasheet

TPS2592AA

Datasheet

Ask The Analog Experts
WEBENCH® Design Center

Boost Converter TPS61088

eFuse TPS2592AA

USB Port
VBUS
5V, 9V, 12V

Input Voltage
2.7V to 4.4V
Output Voltage
Setting

Charger Interface
IC

D+
D-

15mm

38mm
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters andother important disclaimers and information.
TINA-TI is a trademark of Texas Instruments
WEBENCH is a registered trademark of Texas Instruments
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Contents
1
2

3
4

5

2

Introduction .................................................................................................................................. 4
Design Description ...................................................................................................................... 4
2.1 Boost Converter Solution........................................................................................................ 5
2.1.1 Frequency, Inductor and capacitor selection ............................................................... 5
2.1.2 Compensation Capacitor and Resistor ........................................................................ 6
2.1.3 Output Voltage Setting ................................................................................................ 6
2.2 E-fuse and Interface ............................................................................................................... 6
A method to Enter QC2.0 ............................................................................................................. 6
Test Result.................................................................................................................................... 7
4.1 Efficiency ................................................................................................................................ 7
4.2 Thermal Performance ............................................................................................................. 8
4.3 VBUS Voltage Transition .......................................................................................................... 9
4.4 Load Transient ..................................................................................................................... 11
4.5 Short Circuit Protection......................................................................................................... 12
4.6 Mobile phone Charging ........................................................................................................ 12
Schematic, Bill of Materials and PCB Layout ........................................................................... 14
5.1 Schematic ............................................................................................................................ 14
5.2 Bill of Materials ..................................................................................................................... 15
5.3 PCB Layout .......................................................................................................................... 16

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List of Figure
Figure 1: Block Diagram of the Reference-Design ............................................................................ 4
Figure 2 TPS61088 Boost Converter Schematic ................................................................................ 5
Figure 3 Interface-Circuit to Enter Quick Charge 2.0 ........................................................................ 7
Figure 4 Efficiency of the Reference Design...................................................................................... 8
Figure 5 Thermal Performance at VIN=3.6V ........................................................................................ 9
Figure 6 VBUS Transits from 5V to 9V at VIN=3.6V ............................................................................. 10
Figure 7 VBUS Transits from 9V to 12V at VIN=3.6V ........................................................................... 10
Figure 8 VBUS Transits from 5V to 12V at VIN=3.6V ........................................................................... 10
Figure 9 Falling-Time at VIN=3.6V&IOUT=0A...................................................................................... 11
Figure 10 Load Transient Waveform ................................................................................................ 12
Figure 11 Short Circuit Protection .................................................................................................... 12
Figure 12 Setup to Charge a Mobile Phone...................................................................................... 13
Figure 13 Waveform of Charging a Mobile Phone ........................................................................... 13
Figure 14 PMP9773 Schematic ......................................................................................................... 14
Figure 15 PMP9773 Top Overlay, Top Layer and Top Paste ........................................................... 16
Figure 16 PMP9773 Bottom Overlay and Bottom Layer .................................................................. 16

List of Table
Table 1 Performance Specification Summary.................................................................................... 4
Table 2 PMP9775 Output Effective Capacitance and Ripple ............................................................. 6
Table 3 Quick Charge 2.0 Lookup Table ............................................................................................ 7
Table 4 Temperature-Rise at VBUS=9V................................................................................................. 9
Table 5 Over/undershoot of Load Transient .................................................................................... 12
Table 6 PMP9773 Bill of Material....................................................................................................... 15

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1 Introduction
The Reference-Design (RD) builds a power circuit for USB port that supports Quick Charge 2.0 (QC2.0) class A.
The input and output capability of this design is shown in Table 1 . By using a charger interface IC, the output
voltage VBUS can be one of the three voltages, 5V, 9V or 12V, based on the signal on D+ and D- pin of the USB
port. The maximum output power of the RD is 18W.
Table 1 Performance Specification Summary
specification

Test Condition

Min

Input Voltage

Output Voltage

typical2.7

Output Current lower than the maximum value

Output Current

Max

Unit

4.4

V

5.0

V

9.0

V

12.0

V

VBUS = 5V

03

A

VBUS = 9V

02

A

VBUS = 12V

0

1.5

A

The following chapters describe the operation principle, schematic, PCB layout, output characteristics and thermal
performance of the RD.

2 Design Description
The RD’s block diagram is shown in Figure 1. The primary input power is Lithium-ion battery, the voltage of whichis from 3 V to 4.35 V. According the QC2.0 standard class A, the voltage for the USB power output is 5 V, 9 V or
12 V. So the TPS61088 is used to boost the low input voltage to the target voltage.
The TPS2592AA is a 12-V e-Fuse with adjustable 2-A to 3.7-A current limit. It is to protest the battery and the
TPS61088 in case of short circuit happening in the USB output port.
Boost Converter TPS61088

eFuse TPS2592AA

USB Port
VBUS
5V, 9V, 12V

Input Voltage
2.7V to 4.4V
Output Voltage
Setting

Charger Interface
IC

D+
D-

Figure 1: Block Diagram of the Reference-Design
The Charger interface IC communicates with the portable device being charged to identify if the portable device
supports QC2.0. If yes, it changes the boost converter’s output voltage by changing the feedback resistor
according to the requirement of the portable device. If not, the boost converter keeps the default output voltage of
5 V.

4USB Power Supply Using TPS61088 to Support Quick Charge 2.0
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2.1

Boost Converter Solution

The schematic of the boost converter solution based on the TPS61088 is shown in Figure 2. The detail operating
principle, pin functions and electrical characteristics of the TPS61088 are described in its datasheet(SLVSCM8A).
L1
1.5µH

U1
VIN

2.7~4.4V

9
1

C1
22µF

VIN

BOOT

VCC
SW
SW
SW
SW

C3
2.2µF
EN_B

GND

2

EN

GND
18
R1
4.7k

19
10

C2
0.01µF

R3
100k

13
C4
0.047uF

FSW
COMP
VOUT
VOUT
VOUT

ILIM

C5
0.1uF
R7
332k

3
14
15
16
R5
316k

FB
AGND

GND

PGND

GND

GND

GND

GND

GND

C8
22µF

C9
22µF

GND

GND

20
21
R6
100k

R8
95.3k

R9
127k
V2

NC
NC

C7
22µF

17

MODE

TPS61088RHLR
GND

C6
1µF

V1

11
12

4
5
6
7

SS

R4

1

8

GND

GND

Figure 2 TPS61088 Boost Converter Schematic

2.1.1 Frequency, Inductor and capacitor selection
The switching frequency of a boost converter impacts its inductor value, input and output capacitor value and theefficiency. High frequency benefits small inductor and capacitor value, and also small solution size, but is adverse
to efficiency; while low frequency benefits high efficiency but causes large solution size. The switching frequencyof the TPS61088 is set by a resistor between its SW pin and FSW pin. The frequency at this design is set toapproximate 500 KHz.
The average input current of a boost converter is defined by equation (1), where η is the efficiency and VOUT is theoutput voltage of the boost converter (the output voltage of the RD is represented by VBUS). Given VIN=3V, η=0.9,
VOUT=9V, IOUT=2A, the average input current IAVE=6.7A.

IAVE 

VVOUT  IOUT
VIN  η(1)

The inductor value is determined by the current ripple, normally 20% to 40% of the average input current. Then
inductor value can be calculated by equation (2), where IPP is the peak to peak current ripple, fs is 500 KHz.

L

1
1
1
IPP  (
)  fsVOUT  VIN VIN(2)

A 1.5-µH inductor is selected in the RD considering the efficiency of the RD and package of the inductor.
Low-ESR ceramic capacitor is used for this high switching frequency boost converter. So the output voltage ripple
is primarily determined by the equation (3), in which COUT is the effective capacitance.

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VRIP 

(VBST  VIN )  IOUT
COUT  VBST  fs

(3)

Three 22-µF,0805 package capacitors in parallel are used in the RD. The effective capacitance of ceramic
capacitor is largely impacted by its bias voltage. The total effective capacitance and output ripple at VIN=3.6V
based on equation (3) are shown in Table 2.
Table 2 PMP9775 Output Effective Capacitance and Ripple
VOUT
Effective Cap.
VRIP

5V
33 µF
51 mV

9V
16.5 µF
145 mV

12 V
13.2 µF
159 mV

2.1.2 Compensation Capacitor and Resistor
The converter must be stable under 5 V, 9 V and 12 V with the same compensation capacitor and resistor, which
are C2 and R1 in Figure 2. The C2 and R1 are designed based on 5-V output condition, because the right handpanel zero of the boost converter is smallest at 5-V condition. Refer to the TPS61088 datasheet for the detailabout the small signal model.
In real board, the stability and phase margin of the converter can be estimated using the load transient waveform,
as described in the page 5, 6 of the application-note “Optimizing Transient Response of Internally Compensateddc-dc Converters With Feedforward Capacitor” (SLVA289).

2.1.3 Output Voltage Setting
The output voltage of the boost converter is set by the interface IC through changing the TPS61088 feedback
resistor. As shown in Figure 2, when R8 and R9 are opened, the VVOUT can be calculated by equation (4). The RD
output VBUS is approximately equal to VOUT when the e-fuse is enabled.

VOUT 

R5  R6
 VREF  5V
R6

(4)

When R8 is shorted to GND and R9 keeps opened, the output voltage can be calculated by equation (5)VOUT 

R5   R6  R8   R6  R8
 VREF  9V
R6  R8(5)

When R8 and R9 are both shorted to GND, the output voltage can be calculated by the equation (6)VOUT 

2.2

R5   R6  R8  R8  R9  R6  R9   R6  R8  R9
 VREF  12V
R6  R8  R9

(6)

E-fuse and Interface

The external components for the E-fuse TPS2592AA and the interface control IC CHY100 are easy to design
following the suggestion in their datasheets.

3 A method to Enter QC2.0
According the description in the CHY100 datasheet, the processes to enter QC2.0 are:
− Apply a voltage between 0.325 V and 2 V to D+ for at least 1.25 seconds− Discharge the D- voltage below 0.325 V for at least 1ms while keep the D+ voltage above 0.325 V− Apply the voltage levels in Table 3 to set the output voltage. (must keep the D+ voltage above 0.325 V)

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USB Power Supply Using TPS61088 to Support Quick Charge 2.0
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Table 3 Quick Charge 2.0 Lookup Table
D+
0.325 V – 2 V>2 V
0.325 V – 2 V

D0.325 V – 2 V
0.325 V – 2 V
GND

Output Voltage
12 V
9V
5 V(default)

Figure 3(a) shows an interface-circuit that can help the RD to enter QC2.0 for evaluation. Following lists the steps
to connect the interface-circuit to the reference-design and the D+/D- voltage, and the VBUS voltage in each step isshown in Figure 3(b):S1 Connect a power-supply between 2.7 V and 4.4 V to the RD, and connect a 3V power-supply to theinterface-circuit (the VBUS ramps up to approx. 5V after this step).
S2 Close the Jumper J1, connect V1 to the D+ pin and keep the D- floating, then wait at least 2 seconds. Two
actions happen during this 2 seconds:− The D+ and D- voltage equal to 1.5V for 1.25 seconds. (because the D+ and D- pins connect
together inside the CHY100)− Then the D+ keeps at 1.5V and the D- voltage decrease to zero. (because the D+ and D- pins
disconnect and a resistor inside the CHY100 discharges the D-)
S3 Open the J1, and then connect the D- to V2. The VBUS jumps to 9V. (because the D+ voltage is above 3Vand the D- voltage is between 2V and 0.325V)
S4 While keep the D- connection with V2, close the Jumper J1. The VBUS jumps to 12V. (because the D+ andD- voltage are between 2V and 0.325V)
S5 Disconnect the D+ with V1. VBUS jumps to 5V (Because the RD quits the QC2.0 and VBUS goes to thedefault value 5V. start from S1 when needing to enter QC2.0 again)

2K

16K

V1

V2

2K

5.6K

3V
+
–

12V
9V
5V

VOUT
1.25s

2V
D+

.325V
2V

Jumper
J1

D-

.325V
S1

(a)QC2.0 Interface-Circuit

S2

S3

S4

(b) D+/D- and VBUS Waveform

Figure 3 An Interface-Circuit to Enter Quick Charge 2.0

4 Test Result
4.1

Efficiency

Figure 4 shows the efficiency of the RD at VBUS = 5 V, 9 V and 12 V from 0.1A to full load (Refer the TPS61088
datasheet for more efficiency data of the TPS61088). The efficiency does not just depend on the IC, but also
depends on the inductor and the PCB layout. A small DCR inductor and PCB power tracks with small resistancecan help to improve the efficiency.

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100

100

98

98

96

96

94

94

Efficiency [%]Efficiency [%]www.ti.com

92
90
88

92
90
88

86

86

84

84

82

3.0

3.6

82

4.2

3.0

80

80
0.10

0.50

0.90

1.30

1.70
Iout [A]

2.10

2.50

0.10

2.90

0.30

0.50

0.70

(a) VBUS=5V

0.90

1.10
Iout [A]

1.30

1.50

1.70

3.6

4.2

1.90

(b) VBUS=9V

100
98
96

Efficiency [%]

94
92
90
88
86

84
82

3.0

80
0.10

0.30

0.50

0.70
0.90
Iout [A]

1.10

3.6

4.2

1.30

1.50

(c) VBUS=12V
Figure 4 Efficiency of the Reference Design

4.2

Thermal Performance

Figure 5 shows the thermal performance at full output power condition when VIN=3.6V. The ambient temperature
TA is 23ºC and highest temperature point is at the inductor or TPS61088. The worst case happens at VBUS=12V
because of lowest efficiency.

51.9 oC(a) VBUS=5V, IOUT=3A

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69.1 oC

67.4 oC(b) VBUS=9V, IOUT=2A

79.8 oC

76.8 oC(c) VBUS=12V, IOUT=1.5A
Figure 5 Thermal Performance at VIN=3.6V
Table 4 summarize the temperature-rise at VBUS=9V and TA=23ºC.
Table 4 Temperature-Rise at VBUS=9V

IOUT=2A

VIN=3.6V

4.3

Different Input Voltage Conditions
VIN=3.3Vo51.8 C
Different Output Current Conditions
IOUT=1A
IOUT=1.5Aoo
24.2 C33.5 C
VIN=3Vo59.6 C

VIN=3.6Vo46.1 CIOUT=2Ao
46.1 CVBUS Voltage Transition

The voltage’s rising up waveforms from 5V to 9V, 9V to 12V and 5V to 12V are shown in Figure 6, Figure 7, andFigure 8 respectively. The waveforms are measured by changing the D+ and D- voltage level.
There is output voltage overshoot at no load condition. The worst case is 5V to 12V, at which the output voltage
could reach 13.2V for a short period. It is caused by the fast transition of VBUS and the power save mode enabled.
Make sure the device powered by the circuit can tolerate the voltage overshoot, or apply some load during thetransition, or disable the power save mode of the TPS61088 by shorting its MODE pin to ground.

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IIN,2A/div
IIN,2A/div
VBUS,2V/div

VBUS,2V/div(a) IOUT = 0A(b) IOUT = 1.5A

Figure 6 VBUS Transits from 5V to 9V at VIN=3.6V

IIN,2A/div
VBUS,2V/div
VBUS,2V/div
IIN,2A/div(a) IOUT = 0A(b) IOUT = 1.5A

Figure 7 VBUS Transits from 9V to 12V at VIN=3.6V

IIN,2A/div
IIN,2A/div
VBUS,2V/div

VBUS,2V/div(a) IOUT = 0A(b) IOUT = 1.5A

Figure 8 VBUS Transits from 5V to 12V at VIN=3.6V
The falling-time from 9 V to 5 V, 12 V to 9 V and 12 V to 5 V at no load condition are shown in Figure 9, thelongest falling-time happens at 12-V to 5-V transition which lasts about 120 ms.

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VBUS,2V/div
VBUS,2V/div

IOUT,2A/div

IOUT,2A/div(a) VBUS from 9 V to 5 V(b) VBUS from 12 V to 9 V

VBUS,2V/div
IOUT,2A/div(c) VBUS from 12 V to 5 V
Figure 9 Falling-Time at VIN=3.6V&IOUT=0A

4.4

Load Transient

The load transient waveform at 5-V, 9-V and 12-V output voltage are shown in Figure 10 (a), (b) and (c)respectively. The test condition is 25% to 75% to 25% of full load with current slew rate of 0.5A/µs. The loadtransient waveforms indicate that the designed circuit is stable at the three output voltage condition with enoughphase margins.

ILOAD,1A/div
VBUS (AC),500mV/div

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ILOAD,1A/div

VBUS (AC),500mV/div

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www.ti.com(a) VBUS=5V IOUT=0.75~2.25A(b) VBUS=9V IOUT=0. 5~1.5A

ILOAD,1A/div

VBUS (AC),500mV/div(c) VBUS=12V IOUT=0.38~1.13A
Figure 10 Load Transient Waveform
The overshoot and undershoot of the load transient are summarized in Table 5. More output capacitors can help
to reduce the overshoot and undershoot but result in high cost.
Table 5 Over/undershoot of Load Transient
VBUS
Overshootundershoot

4.5

5V
550 mV
650 mV

9V
1V
1V

12 V
1.2 V
1.2 V

Short Circuit Protection

The short circuit protection waveform is shown in Figure 11, where VBST is the output voltage of the boost
converter. When the VBUS is short to ground, the E-fuse protects the TPS61088 from damage during the shortcircuit. The output voltage recovers when the short circuit is removed.

ILOAD,2A/div

VOUT,2V/div
VBUS,2V/div

Figure 11 Short Circuit Protection

4.6

Mobile phone Charging

The setup to charge a mobile phone that supports Quick Charger 2.0 is shown in Figure 12. A cable with a microB type male connector is used to link the mobile phone (Samsung Note 4) and the RD. A current probe and a
voltage probe are to measure the output current and voltage respectively. The EN pins of the TPS61088 and the
TPS2592AA are connected together.

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Figure 12 Setup to Charge a Mobile Phone
Figure 13 shows the waveforms of output voltage and current after enabling the RD:− Firstly, the circuit ramps up to 5V;− Then, the VBUS keeps at 5V for approx. 1.6s. The mobile phone needs this period to enter QC2.0− And then the VBUS jumps to 9V. No overshoot happens at VBUS. The load current is not constant because
the phone is active.
− Finally the phone is inactive (screen turns off), the charge-power keeps at 9V&1.5A.
VBUS=5V QC2.0
Communication Timefor approx. 1.6s

ILOAD
0.5A/div
Enable the RD

VBUS=9V
The phone is active & screen is on
The load current is not constant

VBUS=9V
The phone screen is off
The load current is 1.5A

VOUT
2V/div

Figure 13 Waveform of Charging a Mobile PhoneTIDU917-May 2015

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5 Schematic, Bill of Materials and PCB Layout
5.1

Schematic

Figure 14 shows the schematic of the RD.
L1
1.5µH

U1
VIN

2.7~4.4V

9
1

C1
22µF

VIN

BOOT

VCC
SW
SW
SW
SW

C3
2.2µF
EN_B

GND

2

EN

GND
18
R1
4.7k

19
10

C2
0.01µF

R3
100k

13
C4
0.047uF

FSW
COMP
VOUT
VOUT
VOUT

ILIM

FB

R7
332k

EN_F

14
15
16
R5
316k

AGND
PGND

GND

GND

GND

C7
22µF

C8
22µF

C9
22µF

OUT
OUT
OUT

GND

GND

GND

2

6
7
8

VBUS 5V, 9V, 12V

BFET

C12
1µF

1

9

EN/UVLO
ILIM

R11
1.00M

DV/DT

PAD

10

GND
R13
100k

11

C11
100pF TPS2592AADRC

17
GND

20
21
R6
100k

R8
95.3k

R9
127k
V2

GND

C6
1µF

MODE
NC
NC

VIN
VIN
VIN

3

TPS61088RHLR
GND

U2
3
4
5

V1

11
12

C5
0.1uF

4
5
6
7

SS

R4

1

8

GND
R10
3.01k

GND

GND

U3

GND

8
C10
0.22µF

4
V2

3

V1

2

GND

BP

D+

V3

D-

V2

R

V1

GND

6

D+

5

D-

7
1

R12
127k

R14
390k

CHY100
GND
VIN
EN_B
EN_F
R2
1.00M

VBUS

1
2
3
4

DD+
J1

1
2
3
4

GND

GND

GND

J2
GND
1

No Installed

GND

Figure 14 PMP9773 Schematic

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5.2

Bill of Materials

The bill of materials in the reference design is shown in Table 6
Table 6 PMP9773 Bill of Material
Designator

Quantity

C1

1

22uF

CAP, CERM, 22 µF, 10 V, +/20%, X5R, 0603

0603

GRM188R61A226ME15D

MuRataC2

1

0.01uF

CAP, CERM, 0.01 µF, 50 V, +/10%, X7R, 0402

0402

GRM155R71H103KA88D

MuRata

C3

1

2.2uF

CAP, CERM, 2.2 µF, 25 V, +/10%, X5R, 0402

0402

GRM155R61E225KE11D

MuRataC4

1

0.047uF

CAP, CERM, 0.047uF, 10V, +/10%, X5R, 0402

0402

GRM155R61A473KA01D

MuRata

C5

1

0.1uF

CAP, CERM, 0.1uF, 16V, +/-10%,
X5R, 0402

0402

GRM155R61C104KA88D

MuRataC6, C122

1uF

CAP, CERM, 1 µF, 25 V, +/- 10%,
X5R, 0603

0603

GRM188R61E105KA12D

MuRataC7, C8, C9

3

22uF

CAP, CERM, 22 µF, 25 V, +/20%, X5R, 0805

0805

GRM21BR61E226ME44

MuRataC10

1

0.22uF

CAP, CERM, 0.22 µF, 10 V, +/10%, X5R, 0402

0402

GRM155R61A224KE19D

MuRata

C11

1

100pF

CAP, CERM, 100 pF, 50 V, +/5%, C0G/NP0, 0402

0402

GRM1535C1H101JDD5D

MuRata

L1

1

1.5uH

WE-HC4744311150

R1

1

4.7k

Inductor, Shielded Drum Core,
Superflux, 1.5 µH, 11 A, 0.0078
ohm, SMD
RES, 4.7 k, 5%, 0.063 W, 0402

0402

CRCW04024K70JNED

Wurth
Elektronik
eiSos
Vishay-Dale

R2, R112

1.00Meg

RES, 1.00 M, 1%, 0.063 W, 0402

0402

CRCW04021M00FKED

Vishay-Dale

R3, R13

2

100k

0402

CRCW0402100KFKED

Vishay-Dale

R5

1

316k

RES, 100k ohm, 1%, 0.063W,
0402
RES, 316 k, 1%, 0.063 W, 0402

0402

CRCW0402316KFKED

Vishay-Dale

R6

1

100k

RES, 100 k, 1%, 0.063 W, 0402

0402

CRCW0402100KFKED

Vishay-Dale

R7

1

332k

RES, 332 k, 1%, 0.063 W, 0402

0402

CRCW0402332KFKED

Vishay-Dale

R8

1

95.3k

RES, 95.3 k, 1%, 0.063 W, 0402

0402

CRCW040295K3FKED

Vishay-Dale

R9, R122

127k

RES, 127 k, 1%, 0.063 W, 0402

0402

CRCW0402127KFKED

Vishay-Dale

R10

1

3.01k

RES, 3.01 k, 1%, 0.063 W, 0402

0402

CRCW04023K01FKED

Vishay-Dale

R14

1

390k

RES, 390 k, 5%, 0.063 W, 0402

0402

CRCW0402390KJNEDVishay-Dale

U1

1

RHL0020A

TPS61088RHLR

Texas
InstrumentsU2

1

13.2-V Output, Synchronous
Boost Converter with 10-A Switch,
RHL0020A
12V eFuse with Integrated
Blocking FET Driver, Auto Retry,
DRC0010J

DRC0010J

TPS2592AADRC

Texas
Instruments

U3

1

CHY100Power
Integrations

TIDU917-May 2015

Value

Description

PackagePart Number

Manufacturer

USB Power Supply Using TPS61088 to Support Quick Charge 2.0
Copyright © 2015, Texas Instruments Incorporated15

www.ti.com

5.3

PCB Layout

Figure 15 and Figure 16 show the layout of the reference design. The bulk output capacitor is far away from the
TPS61088, so a small package output capacitor C6 is placed near the IC and connected with short track to
reduce the voltage spike at SW pin. The copper for the thermal pad of the TPS61088 should be as large as
possible to reduce the temperature-rise caused by the power loss.

Figure 15 PMP9773 Top Overlay, Top Layer and Top Paste

Figure 16 PMP9773 Bottom Overlay and Bottom Layer

16

USB Power Supply Using TPS61088 to Support Quick Charge 2.0
Copyright © 2015, Texas Instruments Incorporated

TIDU917-May 2015

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