M029G/M030G/M031G Series

NuMicro® FamilyArm® Cortex®-M0-based Microcontroller

M029G/M030G/M031G Series
Datasheet

Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller andmicroprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

Mar. 31, 2023

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M029G/M030G/M031G SERIES DATASHEETThe information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

M029G/M030G/M031G Series
TABLE OF CONTENTS
1 GENERAL DESCRIPTION............................................................................... 9
1.1 Key Feature And Application........................................................................................ 9

2 FEATURES .................................................................................................... 10
2.1 M029G/M030G/M031G Features ............................................................................. 10

3 PARTS INFORMATION ................................................................................. 15
3.1 Package Type .............................................................................................................. 15
3.2 M029G/M030G/M031G Series Naming Rule .......................................................... 16
3.3 M029G/M030G/M031G Series Selection Guide..................................................... 17

4 PIN CONFIGURATION .................................................................................. 18
4.1 Pin Configuration ......................................................................................................... 18
4.1.1 M029G/M030G/M031G Series Pin Diagram .............................................................. 18
4.1.2 M029G Series Multi-function Pin Diagram ................................................................. 20
4.1.3 M030G Series Multi-function Pin Diagram ................................................................. 22
4.1.4 M031G Series Multi-function Pin Diagram ................................................................. 26

4.2 Pin Mapping ................................................................................................................. 30
4.3 Pin Functional Description ......................................................................................... 32

5 BLOCK DIAGRAM ......................................................................................... 36
M029G/M030G/M031G SERIES DATASHEET

5.1 M029G Block Diagram................................................................................................ 36
5.2 M030G/M031G Block Diagram ................................................................................. 36

6 FUNCTIONAL DESCRIPTION ....................................................................... 37
6.1 Arm® Cortex®-M0 Core ............................................................................................... 37
6.2 System Manager.......................................................................................................... 39
6.2.1 Overview .......................................................................................................................... 39
6.2.2 System Reset .................................................................................................................. 39
6.2.3 System Power Distribution ............................................................................................ 45
6.2.4 Power Modes and Wake-up Sources .......................................................................... 47
6.2.5 System Memory Map ..................................................................................................... 49
6.2.6 SRAM Memory Organization ........................................................................................ 51
6.2.7 Chip Bus Matrix .............................................................................................................. 51
6.2.8 Temperature Sensor....................................................................................................... 52
6.2.9 Internal Voltage Reference (INT_VREF)..................................................................... 53
6.2.10 MANCH_TXD Modulation with BPWM1 ..................................................................... 53
6.2.11 Register Lock Control .................................................................................................... 54
6.2.12 System Timer (SysTick) ................................................................................................. 55
6.2.13 Nested Vectored Interrupt Controller (NVIC) .............................................................. 56

6.3 Clock Controller ........................................................................................................... 60

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6.3.1 Overview .......................................................................................................................... 60
6.3.2 Clock Generator.............................................................................................................. 61
6.3.3 System Clock and SysTick Clock ................................................................................. 62
6.3.4 Peripherals Clock ........................................................................................................... 63
6.3.5 Power-down Mode Clock .............................................................................................. 63
6.3.6 Clock Output.................................................................................................................... 63

6.4 Flash Memory Controller (FMC)................................................................................ 64
6.4.1 Overview .......................................................................................................................... 64
6.4.2 Features ........................................................................................................................... 64

6.5 General Purpose I/O (GPIO) ..................................................................................... 65
6.5.1 Overview .......................................................................................................................... 65
6.5.2 Features ........................................................................................................................... 65

6.6 PDMA Controller (PDMA) ........................................................................................... 66
6.6.1 Overview .......................................................................................................................... 66
6.6.2 Features ........................................................................................................................... 66

6.7 Timer Controller (TMR) ............................................................................................... 67
6.7.1 Overview .......................................................................................................................... 67
6.7.2 Features ........................................................................................................................... 67

6.8 Watchdog Timer (WDT) .............................................................................................. 68
6.8.1 Overview .......................................................................................................................... 68
6.8.2 Features ........................................................................................................................... 68
6.9.1 Overview .......................................................................................................................... 69
6.9.2 Features ........................................................................................................................... 69

6.10

Basic PWM Generator and Capture Timer (BPWM) ........................................ 70

6.10.1 Overview .......................................................................................................................... 70
6.10.2 Features ........................................................................................................................... 70

6.11

UART Interface Controller (UART)...................................................................... 71

6.11.1 Overview .......................................................................................................................... 71
6.11.2 Features ........................................................................................................................... 71

6.12

Serial Peripheral Interface (SPI).......................................................................... 73

6.12.1 Overview .......................................................................................................................... 73
6.12.2 Features ........................................................................................................................... 73

6.13

I2C Serial Interface Controller (I2C) ..................................................................... 74

6.13.1 Overview .......................................................................................................................... 74
6.13.2 Features ........................................................................................................................... 74

6.14

CRC Controller (CRC) .......................................................................................... 75

6.14.1 Overview .......................................................................................................................... 75
6.14.2 Features ........................................................................................................................... 75

6.15

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CRC Controller (CRC) - Configurable ................................................................ 76

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6.9 Window Watchdog Timer (WWDT) ........................................................................... 69

M029G/M030G/M031G Series
6.15.1 Overview .......................................................................................................................... 76
6.15.2 Features ........................................................................................................................... 76

6.16

Manchester Controller (MANCH) ........................................................................ 77

6.16.1 Overview .......................................................................................................................... 77
6.16.2 Features ........................................................................................................................... 77

6.17

Analog-to-Digital Converter (ADC)...................................................................... 78

6.17.1 Overview .......................................................................................................................... 78
6.17.2 Features ........................................................................................................................... 78

6.18

Digital to Analog Converter (DAC) ...................................................................... 80

6.18.1 Overview .......................................................................................................................... 80
6.18.2 Features ........................................................................................................................... 80

6.19

Peripherals Interconnection ................................................................................. 81

6.19.1 Overview .......................................................................................................................... 81
6.19.2 Peripherals Interconnect Matrix table .......................................................................... 81

7 APPLICATION CIRCUIT ................................................................................ 82
7.1 Power Supply Scheme ............................................................................................... 82
7.2 Peripheral Application Scheme ................................................................................. 83

8 ELECTRICAL CHARACTERISTICS .............................................................. 84
8.1 Absolute Maximum Ratings ....................................................................................... 84
8.1.1 Voltage Characteristics .................................................................................................. 84
M029G/M030G/M031G SERIES DATASHEET

8.1.2 Current Characteristics .................................................................................................. 84
8.1.3 Thermal Characteristics................................................................................................. 85
8.1.4 EMC Characteristics ...................................................................................................... 86
8.1.5 Package Moisture Sensitivity(MSL) ............................................................................. 86
8.1.6 Soldering Profile ............................................................................................................. 88

8.2 General Operating Conditions ................................................................................... 89
8.3 DC Electrical Characteristics ..................................................................................... 90
8.3.1 Supply Current Characteristics ..................................................................................... 90
8.3.2 On-Chip Peripheral Current Consumption .................................................................. 93
8.3.3 Wakeup Time from Low-Power Modes ....................................................................... 94
8.3.4 I/O Current Injection Characteristics ............................................................................ 95
8.3.5 I/O DC Characteristics ................................................................................................... 95

8.4 AC Electrical Characteristics ..................................................................................... 97
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC) ................................................... 97
8.4.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) .................................................. 99
8.4.3 PLL Characteristics ........................................................................................................ 99
8.4.4 I/O AC Characteristics ................................................................................................... 99

8.5 Analog Characteristics .............................................................................................. 101
8.5.1 Reset and Power Control Block Characteristics ......................................................101

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8.5.2 12-bit SAR ADC ............................................................................................................103
8.5.3 Digital to Analog Converter (DAC) .............................................................................105
8.5.4 Internal Voltage Reference for M029G/M030G........................................................106
8.5.5 Internal Voltage Reference for M031G ......................................................................1088.5.6 Temperature Sensor.....................................................................................................108

8.6 Communications Characteristics ............................................................................ 110
8.6.1 SPI Dynamic Characteristics ......................................................................................110
8.6.2 I2C Dynamic Characteristics .......................................................................................113

8.7 Flash DC Electrical Characteristics ........................................................................ 114

9 PACKAGE DIMENSIONS ............................................................................ 115
9.1 QFN 24L (3x3x0.9 mm Pitch:0.40 mm).................................................................. 115
9.2 QFN 33L (4x4x0.8 mm Pitch:0.40 mm).................................................................. 116

10 ABBREVIATIONS ........................................................................................ 117
10.1

Abbreviations ........................................................................................................ 117

11 REVISION HISTORY ................................................................................... 119

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M029G/M030G/M031G Series
LIST OF FIGURES
Figure 4.1-1 M029G/M030G/M031G Series QFN 24-pin Diagram ................................................ 18
Figure 4.1-2 M030G/M031G Series QFN 33-pin Diagram............................................................. 19
Figure 4.1-3 M029G Series QFN 24-pin Multi-function Pin Diagram ............................................. 20
Figure 4.1-4 M030G Series QFN 24-pin Multi-function Pin Diagram ............................................. 22
Figure 4.1-5 M030GTC1AE and M030GTD1AE Multi-function Pin Diagram ................................ 24
Figure 4.1-6 M031G Series QFN 24-pin Multi-function Pin Diagram ............................................. 26
Figure 4.1-7 M031GTD2AE and M031GTC2AE Multi-function Pin Diagram ................................ 28
Figure 5-1 NuMicro M029G Block Diagram ................................................................................... 36
Figure 5-2 NuMicro M030G/M031G Block Diagram ...................................................................... 36
Figure 6.1-1 Functional Block Diagram .......................................................................................... 37
Figure 6.2-1 System Reset Sources .............................................................................................. 40
Figure 6.2-2 nRESET Reset Waveform ......................................................................................... 42
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 43
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 43
Figure 6.2-5 Brown-out Detector (BOD) Waveform ....................................................................... 44
Figure 6.2-6 NuMicro® M029G/M030G/M031G Power Distribution Diagram ................................ 46
Figure 6.2-7 Power Mode State Machine ...................................................................................... 48
Figure 6.2-8 SRAM Memory Organization ..................................................................................... 51
M029G/M030G/M031G SERIES DATASHEET

Figure 6.2-9 NuMicro® M029G/M030G/M031G Bus Matrix Diagram ............................................ 51
Figure 6.2-10 Temperature Sensor Conversion Waveform ........................................................... 52
Figure 6.2-11 MANCH_TXD Modulated with BPWM1_CHn ......................................................... 54
Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 61
Figure 6.3-2 Clock Generator Block Diagram ................................................................................ 62
Figure 6.3-3 System Clock Block Diagram .................................................................................... 62
Figure 6.3-4 SysTick Clock Control Block Diagram ....................................................................... 63
Figure 6.3-5 Clock Output Block Diagram ..................................................................................... 63
Figure 8.1-1 Soldering Profile from J-STD-020C ........................................................................... 88
Figure 8.4-1 HIRC vs. Temperature ............................................................................................... 98
Figure 8.5-1 Power Ramp Up/Down Condition ............................................................................ 102
Figure 8.5-2 Typical connection with internal voltage reference.................................................. 107
Figure 8.5-3 Typical connection with internal voltage reference.................................................. 108
Figure 8.6-1 SPI Master Mode Timing Diagram .......................................................................... 110
Figure 8.6-2 SPI Slave Mode Timing Diagram ............................................................................ 112
Figure 8.6-3 I2C Timing Diagram ................................................................................................. 113

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M029G/M030G/M031G Series
List of Tables
Table 1.1-1 NuMicro M029G/M030G/M031G Series Key Features Support Table ........................ 9
Table 4.1-1 M029GGC0AE Multi-function Pin Table ..................................................................... 21
Table 4.1-2 M030GGC1AE and M030GGD1AE Multi-function Pin Table ..................................... 23
Table 4.1-3 M030GTC1AE and M030GTD1AE Pin Multi-function Pin Table ................................ 25
Table 4.1-4 M031GGD2AE and M031GGC2AE Multi-function Pin Table ..................................... 27
Table 4.1-5 M031GTD2AE and M031GTC2AE Pin Multi-function Pin Table ................................ 29
Table 6.2-1 Reset Value of Registers ............................................................................................ 41
Table 6.2-2 DAC Reset Retention Value of Registers ................................................................... 42
Table 6.2-3 GPIO Reset Retention Value of Registers.................................................................. 42
Table 6.2-4 Power Mode Table ...................................................................................................... 47
Table 6.2-5 Power Mode Entry Setting Table ................................................................................ 47
Table 6.2-6 Power Mode Difference Table .................................................................................... 47
Table 6.2-7 Clocks in Power Modes .............................................................................................. 48
Table 6.2-8 Condition of Entering Power-down Mode Again ......................................................... 49
Table 6.2-9 Address Space Assignments for On-Chip Controllers ................................................ 50
Table 6.2-10 Temperature Data Truth Table ................................................................................. 53
Table 6.2-11 Exception Model ....................................................................................................... 57
Table 6.2-12 Interrupt Number Table ............................................................................................. 58

Table 6.11-1 UART Features ......................................................................................................... 72
Table 6.19-1 Peripherals Interconnect Matrix table ....................................................................... 81
Table 8.1-1 Voltage Characteristics ............................................................................................... 84
Table 8.1-2 Current Characteristics ............................................................................................... 84
Table 8.1-3 Thermal Characteristics .............................................................................................. 85
Table 8.1-4 EMC Characteristics ................................................................................................... 86
Table 8.1-5 Package Moisture Sensitivity (MSL) ........................................................................... 87
Table 8.1-6 Soldering Profile.......................................................................................................... 88
Table 8.2-1 General Operating Conditions .................................................................................... 89
Table 8.3-1 Current Consumption in Normal Run Mode................................................................ 90
Table 8.3-2 Current Consumption in Idle Mode ............................................................................. 91
Table 8.3-3 Chip Current Consumption in Power-down Mode ...................................................... 92
Table 8.3-4 Peripheral Current Consumption ................................................................................ 93
Table 8.3-5 Low-power Mode Wakeup Timings ............................................................................ 94
Table 8.3-6 I/O Current Injection Characteristics ........................................................................... 95
Table 8.3-7 I/O Input Characteristics ............................................................................................. 95
Table 8.3-8 I/O Output Characteristics........................................................................................... 96

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Table 6.2-13 Vector Figure Format ................................................................................................ 58

M029G/M030G/M031G Series
Table 8.3-9 nRESET Input Characteristics .................................................................................... 96
Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics ............................ 97
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics ............................ 99
Table 8.4-3 PLL characteristics...................................................................................................... 99
Table 8.4-4 I/O AC Characteristics .............................................................................................. 100
Table 8.5-1 Reset and Power Control Unit .................................................................................. 101
Table 8.6-1 SPI Master Mode Characteristics ............................................................................. 110
Table 8.6-2 SPI Slave Mode Characteristics ............................................................................... 111
Table 8.6-3 I2C Characteristics .................................................................................................... 113
Table 8.7-1 Flash DC Electrical Characteristics .......................................................................... 114
Table 10.1-1 List of Abbreviations................................................................................................ 118

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M029G/M030G/M031G Series
1

GENERAL DESCRIPTIONThe NuMicro M029G/M030G/M031G series 32-bit microcontroller is designed for Optical Transceiver
Module applications. All of these series have a built-in temperature sensor with ±1.6°C deviation from
0°C to 70°C and ±2°C deviation from -40°C to 105°C. Especially, the M031G series supports “Pilot Tone
Modulation” to realize the required Operations, Administration, and Management (OAM) functions for
optical path network. Therefore, the M031G series is equipped with a high flexibility programmable
Hardware Manchester Codec with CRC to encode and decode low-frequency dither signal and 1 set of
DAC with “Auto Data Generation” function to generate the smooth sine waveform up to 500 kHz for the
Pilot Tone Modulation of optical path network.
The M029G/M030G/M031G series is based on Arm Cortex-M0 core with 32-bit hardware
multiplier/divider. It runs up to 48/72 MHz and features 32 Kbytes and 64 Kbytes Flash memory, 2Kbyte,
4 Kbytes and 8 Kbytes SRAM, 2.7V ~ 3.6V operating voltage, 5V I/O tolerance, and -40°C to +105°C
operating temperature.
The M029G/M030G/M031G series provides plenty of peripherals including up to 6 sets of 32-bit timers,
1 set of UART with RS485 and One-wire mode, 1 set of SPI, 2 sets of I2C supporting 400 kHz or 1 MHz
Slave mode, and up to 7 channels of PDMA to offload CPU loading. Furthermore, all of these series
support I2C bootloader for Optical Transceiver Module applications to program application code into the
M029G/M030/M031G series through the I2C interface.
The M029G/M030G/M031G series also provides rich analog peripherals including internal voltage
reference that can output 2.5V, up to 16 channels of 2 MSPS 12-bit SAR ADC and up to 4 sets of 12bit DAC. In addition, 1 set of DAC in the M031G series supports the Auto Data Generation function.
To fit the small form factor requirement of the optical module, the M029G/M030G/M031G series provides
the QFN 24-pin (3x3 mm) and QFN 33-pin (4x4 mm) small form factor package by pin-compatible acrossthese series to make the system design and change parts easily.

For the development system, Nuvoton provides the NuMaker evaluation board and Nuvoton Nu-Link
debugger. The 3rd Party IDE such as Keil MDK, IAR EWARM, and Eclippse IDE with GNU GCC
compilers are also supported.

1.1

Key Feature And Application* 1 set of DAC with Auto Data Generation function
Temp. Internal MANCH
Sensor VREF
Codec

Product Line

UART

I2C

SPI/ I2S

Timer

BPWM

PDMA

ADC

DAC

M029G

1

2

1

2

6

5

16

2

√

√

-

√

M030G

1

2

1

2

6

5

16

4

√

√

-

√

M031G

1

2

1

6

6

7

16

4*

√

√

√

√

CRC

Table 1.1-1 NuMicro M029G/M030G/M031G Series Key Features Support Table

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M029G/M030G/M031G SERIES DATASHEETTo support user who needs I2C bootloader for Optical Transceiver Module applications,
M029G/M030G/M031G series provides pre-programming service based on user’s requirements. There
are two built-in I2C bootloader versions separated by I2C pin selection.

M029G/M030G/M031G Series
2

FEATURES

2.1 M029G/M030G/M031G Features
Core and System
 Arm® Cortex®-M0 core, running up to 72 MHz Built-in Nested Vectored Interrupt Controller (NVIC)®

®

Arm Cortex -M0

 24-bit system tick timer
 Programmble and maskable interrupt
 Low Power Sleep mode by WFI and WFE instructions

Brown-out Detector(BOD)

 Two-level BOD with brown-out interrupt and reset option(2.7V/2.5V)

Low Voltage Reset (LVR)

 LVR with 2.3V threshold voltage level

Security

 96-bit Unique ID (UID) 128-bit Unique Customer ID (UCID)

Memories Up to 64/32 KB on-chip Application ROM (APROM)
 Up to 2 KB on-chip Flash for user-defined loader (LDROM)
M029G/M030G/M031G SERIES DATASHEET Up to 512 bytes non-readable Security Protection ROM (SPROM)
 All on-chip Flash support 512 bytes page eraseFlash Fast Flash programming verification with CRC-32 checksum
calculation
 On-chip Flash programming with In-Chip Programming (ICP), InSystem Programming (ISP) and In-Application Programming (IAP)
capabilities
 2-wired ICP Flash updating through SWD/ICE interface
 Up to 8 KB on-chip SRAMSRAM Byte-, half-word- and word-access PDMA operation
 Supports 8-bits, 16-bits and 32-bits configurable polynomials
 Programmable initial value and seed value

Cyclic Redundancy
Calculation (CRC) Configurable

 Programmable order reverse setting and one’s complement setting
for input data and CRC checksum
 8-bit, 16-bit, and 32-bit data width
 8-bit write mode with 1-AHB clock cycle operation
 16-bit write mode with 2-AHB clock cycle operation
 32-bit write mode with 4-AHB clock cycle operation

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M029G/M030G/M031G Series
 Uses DMA to write data with performing CRC operation
 Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials
 Programmable initial value and seed value Programmable order reverse setting and one’s complement setting
for input data and CRC checksum
Cyclic Redundancy
Calculation (CRC) 8-bit, 16-bit, and 32-bit data width
 8-bit write mode with 1-AHB clock cycle operation
 16-bit write mode with 2-AHB clock cycle operation
 32-bit write mode with 4-AHB clock cycle operation
 Uses DMA to write data with performing CRC operation
 Up to 7 independent and configurable channels for automatic datatransfer between memories and peripherals Basic and Scatter-Gather transfer modes

Peripheral DMA (PDMA) Each channel supports circular buffer management using ScatterGather Transfer mode
 Fixed-priority and Round-robin priorities modes Single and burst transfer types
 Byte-, half-word- and word tranfer unit with count up to 65536
 Incremental or fixed source and destination address

ClocksInternal Clock Source 38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog
timer and wake-up operation
 Up to 144 MHz on-chip PLL, allows CPU operation up to the
maximim CPU frequency without the need for a high-frequency
crystalTimers Up to 6 sets of 32-bit timers with 24-bit up counter and one 8-bit
pre-scale counter from independent clock source One-shot, Periodic, Toggle and Continuous Counting operationmodes
32-bit Timer Supports event counting function to count the event from externalpins Supports external capture pin for interval measurement andresetting 24-bit up counter Supports chip wake-up function, if a timer interrupt signal isgenerated

Basic PWM (BPWM)

 16-bit counters with 12-bit clock pre-scale for 144 MHz PWM output
channels Up to 6 independent input capture channels with 16-bit resolution

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M029G/M030G/M031G SERIES DATASHEET 48 MHz High-speed Internal RC oscillator (HIRC)

M029G/M030G/M031G Series
counter Up, down or up-down PWM counter type
 Mask function and tri-state output for each PWM channel
 Able to trigger ADC to start conversion
 Able to trigger DAC to start conversion
 20-bit free running up counter for WDT time-out interval Supports multiple clock sources from LIRC (default selection),
HCLK/2048 with 9 selectable time-out period
Watchdog Able to wake up system from Power-down or Idle mode Time-out event to trigger interrupt or reset system
 Supports four WDT reset delay periods, including 1026, 130, 18 or
3 WDT_CLK reset delay period
 Configured to force WDT enabled on chip power-on or reset

Window Watchdog

 Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit
counter with 11-bit prescale Suspended in Idle/Power-down mode

Analog Interfaces

Voltage Reference Internal built-in reference has 2.048V and 2.5V two voltage levelselection for ADC, DAC or external devices

M029G/M030G/M031G SERIES DATASHEET Supports ADC and DAC references voltage from internal built-in
reference voltage, or external VREF pin
 Analog input voltage range: 0 ~ AVDD One 12-bit, up to 1.4 MSPS (M029G/M030G) or 2 MSPS (M031G)
SAR ADC with up to 16 single-ended input channels or 8 differential
input pairs; 10-bit accuracy is guaranteed Internal channels for band-gap VBG input
 Supports external VREF pin or internal built-in reference voltage
 Supports calibration capability

ADC Four operation modes: Single mode, Burst mode, Single-cycle
Scan mode and Continuous Scan mode
 Analog-to-Digital conversion can be triggered by software (ADST),
external pin (STADC), Timer 0~1 overflow pulse trigger, andBPWM1 trigger
 Each conversion result is held in data register of each channel withvalid and overrun indicators
 Supports conversion result monitor by compare mode function
 Configurable ADC external sampling time
 PDMA operation
 Supports floating detect function

DAC

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 Analog input voltage range: 0 ~ AVDD

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M029G/M030G/M031G Series
 Supports four 12-bit, 1 MSPS voltage type DAC
 Supports 12- or 8-bit output mode Supports external VREF pin or internal built-in reference voltage
 Digital-to-Analog conversion can be triggered by software(SWTRG), Timer 0~5 overflow pulse trigger, and BPWM1 trigger
 Supports PDMA mode Supports group mode of synchronized update capability for two
DACs
 Supports DAC output retention when system reset 1 set of DAC Supports Auto Data Generation function in M031G
series Built-in calibrated temperature sensor
Temperature Sensor

 Supported temperature range: –40°C to 105°C
 Precision: ±2 °C

Communication Interfaces
 Low-power UARTs with up to 7.2 MHz baud rate
 Auto-Baud Rate measurement function
 Supports low power UART (LPUART): baud rate clock from LIRC
(38.4 kHz) with 9600bps in Power-down mode even system clock
is stopped
 Auto flow control (nCTS and nRTS)
 Supports IrDA (SIR) function
Low-power UART Supports RS-485 9-bit mode and direction control
 Supports nCTS and incoming data wake-up function in idle mode Supports hardware or software enables to program nRTS pin tocontrol RS-485 transmission direction
 Supports wake-up function
 8-bit receiver FIFO time-out detection function
 Supports break error, frame error, parity error and receive/transmit
FIFO overflow detection functions
 PDMA operation
 Supports Single-wire function mode Supports two sets of I2C devices with Master/Slave mode

I2C

 Supports Standard mode (100 kbps), Fast mode (400 kbps)
 Supports Fast mode plus (1 Mbps) (M030G/M031G)
 Supports 7 bits mode

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M029G/M030G/M031G SERIES DATASHEET 1-byte FIFOs with programmable level trigger

M029G/M030G/M031G Series
 Programmable clocks allowing for versatile rate control
 Supports multiple address recognition (four slave address withmask option)
 Supports multi-address power-down wake-up function
 PDMA operation
 Supports receiving continuous data bytes in none stretch mode Supports built-in I2C bootloader
 Up to 36 MHz in Master mode and up to 16 MHz in Slave mode at
2.7V~3.6V system voltage
 Configurable bit length of a transfer word from 8 to 32-bit
 Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit andreceive FIFO buffers
SPI

 MSB first or LSB first transfer sequence Byte reorder function
 Supports Byte or Word Suspend mode Supports one data channel half-duplex transfer
 Supports receive-only mode
 PDMA operation

M029G/M030G/M031G SERIES DATASHEET Supports four I/O modes: Quasi bi-direction, Push-Pull output,
Open-Drain output and Input only with high impendence mode Configured as interrupt source with edge/level trigger setting
GPIO Supports 5V-tolerance function except analog I/O (PA.0 ~ PA.3,
PB.0~PB.15, PF0)
 Enabling the pin interrupt function will also enable the wake-up
function Input schmitt trigger function
 Supports independent pull-up control
 Supports encode/decode Manchester code Supports different modulation signal format

Manchester Codec–

Programmable Idle pattern–

Programmable preamble style and its transmitted number–

Programmable data size in a frame Supports configurable Manchester bit rate Supports selectable deglitch time function
 Supports PDMA for receiving/transmitting
 Supports Manchester encoded edge function to trigger Timer
Controller

Mar. 31, 2023

Page 14 of 120

Rev 1.02

M029G/M030G/M031G Series
3

PARTS INFORMATION

3.1 Package Type
Package is Halogen-free, RoHS-compliant and TSCA-compliant.
QFN24

QFN33

M029GGC0AE

M030GTC1AE

M030GGC1AE

M030GTD1AE

M030GGD1AE

M031GTC2AE

M031GGC2AE

M031GTD2AE

M031GGD2AE

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

Page 15 of 120

Rev 1.02

M029G/M030G/M031G Series
3.2

M029G/M030G/M031G Series Naming Rule
M0

30G

T

D

1

A

E

Core

Line

Package

Flash

SRAM

Reserve

Temperature

Cortex-M0

29: Entry

G: QFN24

C: 32 KB

0: 2 KB

30: Base(3x3x0.9 mm)

D: 64 KB

1: 4 KB

31: with
Manchester
encode/decode

T: QFN33

E:-40°C ~ 105°C

2: 8 KB(4x4x0.8 mm)

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

Page 16 of 120

Rev 1.02

M029G/M030G/M031G Series
3.3 M029G/M030G/M031G Series Selection Guide
M029G

M030G

M031G

Part Number
GC0AE

GC1AE GD1AE TC1AE TD1AE GC2AE GD2AE TC2AE TD2AE

32

SRAM (KB)

248

LDROM (KB)

2

2

2

SPROM (Bytes)

512

512

512

System Frequency (MHz)

48

48

72

PLL (MHz)

-

-

144

I/O

19

32-bit Timer

2

2

6

UART

1

1

1

SPI/I2S

1

1

1

I²C/SMBus2

2

2

Manchester

-

-

√

BPWM

6

6

6

PDMA

5

5

7

CRC

√

√

-

CRC- Configurable

-

-

√

12-bit SAR ADC

1112-bit DAC

2

4

4*

Temperature Sensor

√

√

√

Internal Voltage
Reference√√√

Connectivity

Flash (KB)

64

32

19

28

11

QFN24

QFN24

64

16

QFN33

32

64

32

19

28

11

QFN24

64

16

QFN33

DAC*: 1 set supports Auto Data Generation function

Mar. 31, 2023

Page 17 of 120

Rev 1.02

M029G/M030G/M031G SERIES DATASHEET

Package32

M029G/M030G/M031G Series
4

PIN CONFIGURATION

Users can find pin configuration information in the M029G/M030G/M031G Multi-function Pin diagram
sections or by using NuTool - PinConfigure. The NuTool - PinConfigure contains all NuMicro® Family
chip series with all part number, and helps users configure GPIO multi-function correctly and handily.

4.1 Pin Configuration
4.1.1

M029G/M030G/M031G Series Pin Diagram
M029G/M030G/M031G Series QFN 24-Pin Diagram

PB.4

PB.7

PB.8

VSS

PF.2

PF.3

16

15

14

13

PB.6
18

17

PB.5
19

Corresponding Part Number: M029GGC0AE, M030GGC1AE, M030GGD1AE, M031GGD2AE,
M031GGC2AE

20

12

PB.11

11

PB.12

10

PA.0

Top transparent view
21

PB.2

22

PC.1

23

9

PA.1

PB.1

24

8

PA.2

3

4

5

6

7

VDD

nRESET/ICE_CLK

PF.0

PA.3

2

VREF

VSS

1

QFN24

PB.0

M029G/M030G/M031G SERIES DATASHEET

PB.3

Figure 4.1-1 M029G/M030G/M031G Series QFN 24-pin Diagram

Mar. 31, 2023

Page 18 of 120

Rev 1.02

M029G/M030G/M031G Series
M030G/M031G Series QFN 33-Pin Diagram

PB.3

PB.4

PB.5

PB.6

PB.7

PB.8

PB.9

PB.10

PF.2

24

23

22

21

20

19

18

17

Corresponding Part Number: M030GTC1AE, M030GTD1AE, M031GTD2AE, M031GTC2AE

25

16

PF.3

Top transparent view

PB.2

26

15

PB.11

PC.1

27

14

PB.12

PB.1

28

13

PB.13

PA.14

29

12

PB.14

PA.12

30

11

PB.15

PA.13

31

10

PA.0

PB.0

32

9

PA.1

QFN33

1

2

3

4

5

6

7

8

VDD

AVDD

nRESET/ICE_CLK

PF.0

PA.15

PA.3

PA.2

M029G/M030G/M031G SERIES DATASHEETVREF

33 EPAD

Figure 4.1-2 M030G/M031G Series QFN 33-pin Diagram

Mar. 31, 2023

Page 19 of 120

Rev 1.02

M029G/M030G/M031G Series
4.1.2

M029G Series Multi-function Pin Diagram
M029G Series QFN 24-Pin Multi-function Pin Diagram

VSS

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

14

13

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

15

PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5

16

PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4
18

17

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0
19

Corresponding Part Number: M029GGC0AE

12

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0

11

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT

10PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD

23

9PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD

24

8PA.2 / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA

INT1 / TM1 / I2C0_SDA / ADC0_CH4 / PB.4

20

INT2 / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3

21

INT3 / TM1 / BPWM1_CH3 / I2C1_SDA / ADC0_CH2 / PB.2

22

ADC0_ST / I2C0_SCL / PC.1
BPWM1_CH4 / I2C1_SCL / UART0_RXD / ADC0_CH1 / PB.1

2

3

4

5

6

7

VSS

VDD

nRESET/ICE_CLK

ICE_DAT / PF.0

CLKO / I2C1_SCL / I2C0_SMBAL / SPI0_SS / PA.3

QFN24

VREF

M029G/M030G/M031G SERIES DATASHEETI2C1_SDA / ADC0_CH0 / PB.0

1

Top transparent view

Figure 4.1-3 M029G Series QFN 24-pin Multi-function Pin Diagram
Pin

Pin Function

1

PB.0 / ADC0_CH0 / I2C1_SDA

2

VREF

3

VSS

4

VDD

5

nRESET/ICE_CLK

6

PF.0 / ICE_DAT

7

PA.3 / SPI0_SS / I2C0_SMBAL / I2C1_SCL / CLKO

Mar. 31, 2023

Page 20 of 120

Rev 1.02

M029G/M030G/M031G Series
Pin

Pin Function

8

PA.2 / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA

9

PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD

11

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT

12

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0

13

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

14

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

15

VSS

16

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

17

PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5

18

PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4

19

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT020

PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1

21

PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / INT2

22

PB.2 / ADC0_CH2 / I2C1_SDA / BPWM1_CH3 / TM1 / INT3

23

PC.1 / I2C0_SCL / ADC0_ST

24

PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SCL / BPWM1_CH4

Mar. 31, 2023

Page 21 of 120

M029G/M030G/M031G SERIES DATASHEET

Table 4.1-1 M029GGC0AE Multi-function Pin Table

Rev 1.02

M029G/M030G/M031G Series
4.1.3

M030G Series Multi-function Pin Diagram
M030G Series QFN 24-Pin Multi-function Pin Diagram20
21

INT3 / TM1 / BPWM1_CH3 / I2C1_SDA / ADC0_CH2 / PB.2

22

ADC0_ST / I2C0_SCL / PC.1

23

BPWM1_CH4 / I2C1_SCL / UART0_RXD / ADC0_CH1 / PB.1

24

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

VSS

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

15

14

13

PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5

16

18

INT1 / TM1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3

17

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0

PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4

19

Corresponding Part Number: M030GGC1AE, M030GGD1AE

12

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0

11

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT

10PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD

9PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD

8PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA

5nRESET/ICE_CLK

7

4

6

3

VSS

VDD

ICE_DAT / PF.0

2

VREF

QFN24

CLKO / I2C1_SCL / I2C0_SMBAL / SPI0_SS / DAC3_OUT / PA.3

M029G/M030G/M031G SERIES DATASHEETI2C1_SDA / ADC0_CH0 / PB.0

1

Top transparent view

Figure 4.1-4 M030G Series QFN 24-pin Multi-function Pin Diagram
Pin

Pin Function

1

PB.0 / ADC0_CH0 / I2C1_SDA

2

VREF

3

VSS

4

VDD

5

nRESET/ICE_CLK

6

PF.0 / ICE_DAT

7

PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / CLKO

Mar. 31, 2023

Page 22 of 120

Rev 1.02

M029G/M030G/M031G Series
Pin

Pin Function

8

PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA

9

PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD

11

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT

12

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0

13

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

14

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

15

VSS

16

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

17

PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5

18

PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4

19

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT020

PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1

21

PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / INT2

22

PB.2 / ADC0_CH2 / I2C1_SDA / BPWM1_CH3 / TM1 / INT3

23

PC.1 / I2C0_SCL / ADC0_ST

24

PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SCL / BPWM1_CH4

Mar. 31, 2023

Page 23 of 120

M029G/M030G/M031G SERIES DATASHEET

Table 4.1-2 M030GGC1AE and M030GGD1AE Multi-function Pin Table

Rev 1.02

M029G/M030G/M031G Series
M030G Series QFN 33-Pin Multi-function Pin Diagram

PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0

PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4

PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

PB.9 / ADC0_CH9 / UART0_TXD / BPWM1_CH2

PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA / BPWM1_CH1

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

24

23

22

21

20

19

18

17

Corresponding Part Number: M030GTC1AE, M030GTD1AE

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

INT2 / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3

25

INT3 / TM1 / BPWM1_CH3 / I2C1_SDA / ADC0_CH2 / PB.2

26

15

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0

ADC0_ST / I2C0_SCL / PC.1

27

14

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT

BPWM1_CH4 / I2C1_SCL / UART0_RXD / ADC0_CH1 / PB.1

28

13

PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM0_EXT

BPWM1_CH4 / UART0_TXD / PA.14

29

12

PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO

BPWM1_CH2 / I2C1_SCL / PA.1230

11PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT

BPWM1_CH3 / I2C1_SDA / PA.13

31

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD

9PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD

QFN33

33 EPAD

1

2

3

4

5

6

7

8

AVDD

nRESET/ICE_CLK

ICE_DAT / PF.0

BPWM1_CH5 / UART0_RXD / PA.15

CLKO / I2C1_SCL / I2C0_SMBAL / SPI0_SS / DAC3_OUT / PA.3

I2C1_SDA / I2C0_SMBSUS / SPI0_CLK / DAC2_OUT / PA.2

M029G/M030G/M031G SERIES DATASHEET

VDD

32

VREF

I2C1_SDA / ADC0_CH0 / PB.0

16
Top transparent view

Figure 4.1-5 M030GTC1AE and M030GTD1AE Multi-function Pin Diagram
Pin

Pin Function

1

VREF

2

VDD

3

AVDD

4

nRESET/ICE_CLK

5

PF.0 / ICE_DAT

6

PA.15 / UART0_RXD / BPWM1_CH5

Mar. 31, 2023

Page 24 of 120

Rev 1.02

M029G/M030G/M031G Series
Pin Function

7

PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / CLKO8

PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA

9

PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD

11

PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT

12

PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO13

PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM0_EXT

14

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT

15

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0

16

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

17

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

18

PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA / BPWM1_CH1

19

PB.9 / ADC0_CH9 / UART0_TXD / BPWM1_CH2

20

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

21

PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5

22

PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4

23

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT024

PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1

25

PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / INT2

26

PB.2 / ADC0_CH2 / I2C1_SDA / BPWM1_CH3 / TM1 / INT3

27

PC.1 / I2C0_SCL / ADC0_ST

28

PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SCL / BPWM1_CH4

29

PA.14 / UART0_TXD / BPWM1_CH430

PA.12 / I2C1_SCL / BPWM1_CH2

31

PA.13 / I2C1_SDA / BPWM1_CH3

32

PB.0 / ADC0_CH0 / I2C1_SDA

33

EPAD

M029G/M030G/M031G SERIES DATASHEET

Pin

Table 4.1-3 M030GTC1AE and M030GTD1AE Pin Multi-function Pin Table

Mar. 31, 2023

Page 25 of 120

Rev 1.02

M029G/M030G/M031G Series
4.1.4

M031G Series Multi-function Pin Diagram
M031G Series QFN 24-Pin Multi-function Pin Diagram20
21

INT3 / TM3 / MANCH_RXD / TM1 / BPWM1_CH3 / I2C1_SCL / TM5 / I2C1_SDA / ADC0_CH2 / PB.2

22

ADC0_ST / I2C0_SCL / I2C1_SCL / PC.1

23

BPWM1_CH4 / I2C1_SCL / I2C1_SDA / UART0_RXD / ADC0_CH1 / PB.1

24

VSS

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

14

13

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

15

PB.7 / ADC0_CH7 / MANCH_TXD / BPWM1_CH4 / INT5

16

18

INT1 / TM1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / TM2 / MANCH_TXD / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3

17

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0

PB.6 / ADC0_CH6 / MANCH_RXD / BPWM1_CH5 / INT4

19

Corresponding Part Number: M031GGD2AE, M031GGC2AE

12

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD

11

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4

9PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD

8

PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA / BPWM1_CH2 / MANCH_TXD

Top transparent view

1

2

3

4

5

6

7

VREF

VSS

VDD

nRESET/ICE_CLK

ICE_DAT / PF.0

BPWM1_CH5 / CLKO / BPWM1_CH3 / I2C1_SCL / I2C0_SMBAL / SPI0_SS / DAC3_OUT / PA.3

M029G/M030G/M031G SERIES DATASHEETI2C1_SDA / ADC0_CH0 / PB.0

QFN24

Figure 4.1-6 M031G Series QFN 24-pin Multi-function Pin Diagram
Pin

Pin Function

1

PB.0 / ADC0_CH0 / I2C1_SDA

2

VREF

3

VSS

4

VDD

Mar. 31, 2023

Page 26 of 120

Rev 1.02

M029G/M030G/M031G Series
Pin

Pin Function
nRESET/ICE_CLK

6

PF.0 / ICE_DAT

7

PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / BPWM1_CH3 / CLKO / BPWM1_CH5

8

PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA / BPWM1_CH2 / MANCH_TXD

9PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4

11

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD

12

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD

13

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

14

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

15

VSS

16

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

17

PB.7 / ADC0_CH7 / MANCH_TXD / BPWM1_CH4 / INT5

18

PB.6 / ADC0_CH6 / MANCH_RXD / BPWM1_CH5 / INT4

19

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT020

PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1

21

PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / MANCH_TXD / TM2 / INT2

22

PB.2 / ADC0_CH2 / I2C1_SDA / TM5 / I2C1_SCL / BPWM1_CH3 / TM1 / MANCH_RXD / TM3 / INT3

23

PC.1 / I2C1_SCL / I2C0_SCL / ADC0_ST

24

PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SDA / I2C1_SCL / BPWM1_CH4

M029G/M030G/M031G SERIES DATASHEET

5

Table 4.1-4 M031GGD2AE and M031GGC2AE Multi-function Pin Table

Mar. 31, 2023

Page 27 of 120

Rev 1.02

M029G/M030G/M031G Series
M031G Series QFN 33-Pin Multi-function Pin Diagram

PB.9 / ADC0_CH9 / UART0_TXD / BPWM1_CH2

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3
20

17

PB.7 / ADC0_CH7 / MANCH_TXD / BPWM1_CH4 / INT5
21

PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA / BPWM1_CH1

PB.6 / ADC0_CH6 / MANCH_RXD / BPWM1_CH5 / INT4
22

18

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0
23

19

PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1
24

Corresponding Part Number: M031GTD2AE, M031GTC2AE

INT2 / TM2 / MANCH_TXD / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3

25

INT3 / TM3 / MANCH_RXD / TM1 / BPWM1_CH3 / I2C1_SCL / TM5 / I2C1_SDA / ADC0_CH2 / PB.2

26

15

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD

ADC0_ST / I2C0_SCL / I2C1_SCL / PC.1

27

14

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD

BPWM1_CH4 / I2C1_SCL / I2C1_SDA / UART0_RXD / ADC0_CH1 / PB.1

28

13

PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM4_EXT / TM2_EXT / TM0_EXT

TM4_EXT / BPWM1_CH4 / I2C1_SCL / UART0_TXD / PA.14

29

TM4 / BPWM1_CH2 / I2C1_SCL / PA.1230

11PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT

TM5 / BPWM1_CH3 / I2C1_SDA / PA.13

31

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4

I2C1_SDA / ADC0_CH0 / PB.0

32

9

PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD

16
Top transparent view

QFN33

12

2

3

4

5

6

7

8

nRESET/ICE_CLK

ICE_DAT / PF.0

TM5_EXT / BPWM1_CH5 / UART0_RXD / PA.15

BPWM1_CH5 / CLKO / BPWM1_CH3 / I2C1_SCL / I2C0_SMBAL / SPI0_SS / DAC3_OUT / PA.3

MANCH_TXD / BPWM1_CH2 / I2C1_SDA / I2C0_SMBSUS / SPI0_CLK / DAC2_OUT / PA.2

1

VDD

VREF

M029G/M030G/M031G SERIES DATASHEET

AVDD

33 EPAD

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO

Figure 4.1-7 M031GTD2AE and M031GTC2AE Multi-function Pin Diagram
Pin

Pin Function

1

VREF

2

VDD

3

AVDD

4

nRESET/ICE_CLK

5

PF.0 / ICE_DATMar. 31, 2023

Page 28 of 120

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M029G/M030G/M031G Series
Pin Function

6

PA.15 / UART0_RXD / BPWM1_CH5 / TM5_EXT

7PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / BPWM1_CH3 / CLKO / BPWM1_CH5

8

PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA / BPWM1_CH2 / MANCH_TXD

9PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD

10

PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4

11

PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT

12

PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO13

PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM4_EXT / TM2_EXT / TM0_EXT

14

PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD

15

PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD

16

PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0

17

PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1

18

PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA / BPWM1_CH1

19

PB.9 / ADC0_CH9 / UART0_TXD / BPWM1_CH2

20

PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3

21

PB.7 / ADC0_CH7 / MANCH_TXD / BPWM1_CH4 / INT5

22

PB.6 / ADC0_CH6 / MANCH_RXD / BPWM1_CH5 / INT4

23

PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT024

PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1

25

PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / MANCH_TXD / TM2 / INT2

26

PB.2 / ADC0_CH2 / I2C1_SDA / TM5 / I2C1_SCL / BPWM1_CH3 / TM1 / MANCH_RXD / TM3 / INT3

27

PC.1 / I2C1_SCL / I2C0_SCL / ADC0_ST

28

PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SDA / I2C1_SCL / BPWM1_CH4

29

PA.14 / UART0_TXD / I2C1_SCL / BPWM1_CH4 / TM4_EXT

30

PA.12 / I2C1_SCL / BPWM1_CH2 / TM4

31

PA.13 / I2C1_SDA / BPWM1_CH3 / TM532

PB.0 / ADC0_CH0 / I2C1_SDA

33

EPAD

M029G/M030G/M031G SERIES DATASHEET

Pin

Table 4.1-5 M031GTD2AE and M031GTC2AE Pin Multi-function Pin Table

Mar. 31, 2023

Page 29 of 120

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M029G/M030G/M031G Series
4.2 Pin Mapping
Different part number with same package might has different function. Please refer to the
M029G/M030G/M031G Series Selection Guide, Pin Configuration section or NuTool - PinConfig.
Corresponding Part Number: M029GxC, M030GxC, M030GxD, M031GxC, M031GxD series.

M029G/M030G/M031G Series
Pin Name

24 Pin33 Pin

VREF

2

1

VSS

3

VDD

4

AVDD

2
3

nRESET/ICE_CLK

5

4

PF.0

6

5

PA.15

6

PA.3

7

7

PA.2

8

8

PA.1

9

9

PA.0

10

10

M029G/M030G/M031G SERIES DATASHEET

PB.15

11

PB.14

12

PB.13

13

PB.12

11

14

PB.11

12

15

PF.3

13

16

PF.2

14

17

PB.10

18

PB.9

19

VSS

15

PB.8

16

20

PB.7

17

21

PB.6

18

22

PB.5

19

23

PB.4

20

24

PB.3

21

25

PB.2

22

26

PC.1

23

27

Mar. 31, 2023

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Rev 1.02

M029G/M030G/M031G Series
PB.1

24

28

PA.14

29

PA.12

30

PA.13

31

PB.0

1

EPAD

32
33

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

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M029G/M030G/M031G Series
4.3 Pin Functional Description
Corresponding Part Number: M029GxC, M030GxC, M030GxD, M031GxC, M031GxD series.

Group

Pin Name

ADC0

Type

Description

M029G/M030G/M031G SERIES DATASHEETADC0_CH0

A

ADC0 channel 0 analog input.

ADC0_CH1

A

ADC0 channel 1 analog input.

ADC0_CH2A

ADC0 channel 2 analog input.

ADC0_CH3A

ADC0 channel 3 analog input.

ADC0_CH4A

ADC0 channel 4 analog input.

ADC0_CH5A

ADC0 channel 5 analog input.

ADC0_CH6A

ADC0 channel 6 analog input.

ADC0_CH7A

ADC0 channel 7 analog input.

ADC0_CH8A

ADC0 channel 8 analog input.

ADC0_CH9A

ADC0 channel 9 analog input.

ADC0_CH10A

ADC0 channel 10 analog input.

ADC0_CH11A

ADC0 channel 11 analog input.

ADC0_CH12A

ADC0 channel 12 analog input.

ADC0_CH13A

ADC0 channel 13 analog input.

ADC0_CH14A

ADC0 channel 14 analog input.

ADC0_CH15A

ADC0 channel 15 analog input.

ADC0_STI

ADC0 external trigger input pin.

BPWM1_CH0

I/O

BPWM1 channel 0 output/capture input.

BPWM1_CH1

I/O

BPWM1 channel 1 output/capture input.

BPWM1

Mar. 31, 2023

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M029G/M030G/M031G SeriesGroup

Pin Name

Description

BPWM1_CH2

I/O

BPWM1 channel 2 output/capture input.

BPWM1_CH3

I/O

BPWM1 channel 3 output/capture input.

BPWM1_CH4

I/O

BPWM1 channel 4 output/capture input.

BPWM1_CH5

I/O

BPWM1 channel 5 output/capture input.

CLKO

CLKO

O

Clock OutDAC0

DAC0_OUTA

DAC0 channel analog output.

DAC1

DAC1_OUTA

DAC1 channel analog output.

DAC2

DAC2_OUTA

DAC2 channel analog output.

DAC3

DAC3_OUTA

DAC3 channel analog output.

I2C0_SCL

I/O

I2C0 clock pin.

I2C0_SDA

I/O

I2C0 data input/output pin.

I2C0_SMBALO

I2C0 SMBus SMBALTER pin

I2C0_SMBSUSO

I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)

I2C1_SCL

I/O

I2C1 clock pin.

I2C1_SDA

I/O

I2C1 data input/output pin.

ICE_CLKI

Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK
pin

I2C0

I2C1

Serial wired debugger clock pin

nRESET : External reset input, active LOW with an internal pull-up. Set
this pin low reset to initial state.

ICE
nRESET /ICE_DAT

I/O

ICE_DAT : Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT
pin.

INT0

INT0

I

External interrupt 0 input pin.

INT1

INT1

I

External interrupt 1 input pin.

INT2

INT2

I

External interrupt 2 input pin.

Mar. 31, 2023

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M029G/M030G/M031G SERIES DATASHEET

TypeM029G/M030G/M031G SeriesGroup

Pin Name

Type

Description

INT3

INT3

I

External interrupt 3 input pin.

INT4

INT4

I

External interrupt 4 input pin.

INT5

INT5

I

External interrupt 5 input pin.

MANCH_RXD

I

Manchester data receiver input pin.

MANCH_TXD

OManchester data transmitter output pin.

VDD

PPower supply for I/O ports and LDO source for internal PLL and digital
circuit.

VSSP

Ground pin for digital circuit.

AVDD

P

Power supply for internal analog circuit.

AVSS

P

Ground pin for analog circuit.

VREF

A

EPAD

P

Exposed pad served as ground pin (VSS).

SPI0_CLK

I/O

SPI0 serial clock pin.

SPI0_MISO

I/O

SPI0 MISO (Master In, Slave Out) pin.

SPI0_MOSI

I/O

SPI0 MOSI (Master Out, Slave In) pin.

SPI0_SS

I/O

SPI0 slave select pin.

TM0

I/O

Timer0 event counter input/toggle output pin.

TM0_EXT

I/O

Timer0 external capture input/toggle output pin.

TM1

I/O

Timer1 event counter input/toggle output pin.

TM1_EXT

I/O

Timer1 external capture input/toggle output pin.

MANCH

Power

ADC and DAC reference voltage input.
Note: This pin needs to be connected with a 1uF capacitor.

M029G/M030G/M031G SERIES DATASHEET

SPI0

TM0

TM1

TM2

I/O

Timer2 event counter input/toggle output pin.

TM2
TM2_EXT

Mar. 31, 2023

I/O

Timer2 external capture input/toggle output pin.

Page 34 of 120

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M029G/M030G/M031G SeriesGroup

Pin Name

Type
TM3

I/O

Description
Timer3 event counter input/toggle output pin.

TM3
TM3_EXT

TM4

I/O

I/O

Timer3 external capture input/toggle output pin.

Timer4 event counter input/toggle output pin.

TM4
TM4_EXT

TM5

I/O

I/O

Timer4 external capture input/toggle output pin.

Timer5 event counter input/toggle output pin.

TM5
TM5_EXT

I/O

Timer5 external capture input/toggle output pin.

UART0_RXDI

UART0 data receiver input pin.

UART0_TXDO

UART0 data transmitter output pin.

UART0_nCTS

I

UART0 clear to Send input pin.

UART0_nRTSO

UART0 request to Send output pin.

UART0

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

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M029G/M030G/M031G Series
5
5.1

BLOCK DIAGRAM
M029G Block Diagram

Figure 5-1 NuMicro M029G Block Diagram

5.2

M030G/M031G Block Diagram

M029G/M030G/M031G SERIES DATASHEET*Only in M031G Series** M031G Series is equipped with 1 set of DAC with Auto Data Generation function
Figure 5-2 NuMicro M030G/M031G Block Diagram

Mar. 31, 2023

Page 36 of 120

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M029G/M030G/M031G Series
6

FUNCTIONAL DESCRIPTION

6.1 Arm® Cortex®-M0 Core
The Cortex®-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality.
The processor can execute Thumb code and is compatible with other Cortex®-M profile processor. The
profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result ofan exception. An exception return can only be issued in Handler mode. Thread mode is entered on
Reset, and can be entered as a result of an exception return. Figure 6.1-1 shows the functional controller
of processor.

Cortex-M0 Components
Cortex-M0 Processor

Debug

NestedVectoredInterrupt
Controller(NVIC)

Interrupts

WakeupInterrupt
Controller(WIC)

Cortex-M0
Processor
Core

Breakpoint
andWatchpoint
Unit

Bus matrix

Debuggerinterface

AHB-Lite interface

Debug
Access Port
(DAP)

Serial Wire or
JTAG debug port

The implemented device provides:

A low gate count processor:–

Arm®6-M Thumb® instruction set–

Thumb-2 technology–Arm®6-M compliant 24-bit SysTick timer–

A 32-bit hardware multiplier–

System interface supported with little-endian data accesses–

Ability to have deterministic, fixed-latency, interrupt handling–

Load/store-multiples and multicycle-multiplies that can be abandoned and restarted tofacilitate rapid interrupt handling–

C Application Binary Interface compliant exception model. This is the Armv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the useof pure C functions as interrupt handlers–

Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event(WFE) instructions, or return from interrupt sleep-on-exit feature

NVIC:
–

Mar. 31, 2023

32 external interrupt inputs, each with four levels of priority

Page 37 of 120

Rev 1.02

M029G/M030G/M031G SERIES DATASHEET

Figure 6.1-1 Functional Block DiagramM029G/M030G/M031G Series





–

Dedicated Non-maskable Interrupt (NMI) input–

Supports for both level-sensitive and pulse-sensitive interrupt lines–

Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep
mode

Debug support:–

Four hardware breakpoints–

Two watchpoints–

Program Counter Sampling Register (PCSR) for non-intrusive code profiling–

Single step and vector catch capabilities

Bus interfaces:–

Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory–

Single 32-bit slave port that supports the DAP (Debug Access Port)

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

Page 38 of 120

Rev 1.02

M029G/M030G/M031G Series
6.2 System Manager
6.2.1

Overview

System management includes the following sections:

6.2.2



System Reset

System Power Distribution

SRAM Memory Orginization



System Timer (SysTick)

Nested Vectored Interrupt Controller (NVIC)

System Control register

System Reset

The system reset can be issued by one of the events listed below. These reset event flags can be readfrom SYS_RSTSTS register to determine the reset source. Hardware reset sources are from peripheral
signals. Software reset can trigger reset through setting control registers.
–Power-on Reset–

Low level on the nRESET pin–

Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)–

Low Voltage Reset (LVR)–

Brown-out Detector Reset (BOD Reset)–

CPU Lockup Reset

Software Reset Sources–

CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])–MCU Reset to reboot but keeping the booting setting from APROM or LDROM bywriting 1 to SYSRESETREQ (AIRCR[2])–

CPU Reset for Cortex®-M0 core only by writing 1 to CPURST (SYS_IPRST0[1])Mar. 31, 2023

Page 39 of 120

Rev 1.02

M029G/M030G/M031G SERIES DATASHEETHardware Reset Sources

M029G/M030G/M031G Series

Hardware Reset Sources
Glitch Filter
33 us

nRESET

VDD~50k ohm
POROFF(SYS_PORCTL[15:0])@3.3v
Power-onReset

NRESET Reset

Reset Pulse Width~3.2msPOR Reset

Reset Pulse Width~3.2msLVR Reset

Brown-out
Reset

Reset Pulse Width~3.2ms

BOD Reset

WDT/WWDT
Reset

Reset Pulse Width
64 WDT clocks

WDT Reset

CPU Lockup
Reset

Reset Pulse Width
2 system clocks

Lockup ResetCHIP Reset
CHIPRST(SYS_IPRST0[0])Reset Pulse Width
2 system clocks

CHIP ResetMCU Reset
SYSRSTREQ(AIRCR[2])Reset Pulse Width
2 system clocks

MCU Reset

CPU Reset
CPURST(SYS_IPRST0[1])Reset Pulse Width
2 system clocks

CPU Reset

LVREN(SYS_BODCTL[7])AVDD

Low Voltage
Reset
BODRSTEN(SYS_BODCTL[3])Software Reset Sources

M029G/M030G/M031G SERIES DATASHEET

Figure 6.2-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex®-M0 only; the other reset sources will reset Cortex®-M0 and all peripherals. However, there aresome registers with particularly different reset sources. Table 6.2-1 lists these differences.
Reset Sources
Register
SYS_RSTSTS
CHIPRST(SYS_IPRST0[0])BODEN(SYS_BODCTL[0])BODVL(SYS_BODCTL[16])BODRSTEN(SYS_BODCTL[3])WDTCKEN(CLK_APBCLK0[0])Mar. 31, 2023

POR

NRESET

WDT

LVR

BOD

Lockup

CHIP

MCU

CPU

Bit 0 = 1

Bit 1 = 1

Bit 2 = 1

Bit 3 = 1

Bit 4 = 1

Bit 8 = 1

Bit 0 = 1

Bit 5 = 1

Bit 7 = 1

0x0

-

-

-

-

-

-

-

-

0x0

0x1

0x1

0x1

-

0x1

0x1

0x1

-

0x0

0x0

0x0

0x0

-

0x0

0x0

0x0

-

0x1

0x1

0x1

0x1

-

0x1

0x1

0x1

-

0x1

-

0x1

-

-

-

0x1

-

-

Page 40 of 120

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M029G/M030G/M031G Series
HCLKSEL

0x7

0x7

0x7

0x7

0x7

0x7

0x7

0x7

-

0x3

0x3

-

-

-

-

-

-

-

0x0

-

-

-

-

-

-

-

-

ReloadReloadReloadReloadReload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadfrom
CONFIG0--0x08000x08000x08000x08000x0800-0x0800--

WDT_ALTCTL

0x00000x00000x00000x00000x0000-0x0000--

WWDT_RLDCNT

0x00000x00000x00000x00000x0000-0x0000--

WWDT_CTL

0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800-

0x3F0800--

WWDT_STATUS

0x00000x00000x00000x00000x0000-0x0000--

WWDT_CNT

0x3F

0x3F

0x3F

0x3F

0x3F

-

0x3F

-

-

ReloadReloadReloadReloadReload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadfrom
CONFIG0--

ReloadReloadReloadReloadReload
from
from
from
from
from
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1-

Reloadfrom
CONFIG1--

ReloadReloadReloadReloadReload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadfrom
CONFIG0--

ReloadReloadReloadReloadReloadbase on base on base on base on base on
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0-

Reloadbase onCONFIG0--(CLK_CLKSEL0[2:0])
WDTSEL(CLK_CLKSEL1[1:0])
HIRCSTB(CLK_STATUS[4])RSTEN(WDT_CTL[1])WDTEN(WDT_CTL[7])
WDT_CTL
except bit 1 and bit 7.

BS(FMC_ISPCTL[1])FMC_DFBA(FMC_ISPSTS[2:1))
VECMAP(FMC_ISPSTS[23:9])
DAC IP Registers(RETEN, DAC0_CTL[24]=1)
DAC IP Registers(RETEN, DAC0_CTL[24]=0)
GPIO IP Registers(RETEN (GPIO_RET[0]) = 1)
GPIO IP Registers

Refer to Table 6.2-2 for DAC Reset Retention source and reset value.

Reset Value-

Refer to Table 6.2-3 for GPIO Reset Retention source and reset value.

Reset Value-

Other Peripheral Registers

Reset Value-FMC Registers

Reset Value(RETEN (GPIO_RET[0]) = 0)

Note: ‘-‘ means that the value of register keeps original setting.

Table 6.2-1 Reset Value of Registers

Mar. 31, 2023

Page 41 of 120

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M029G/M030G/M031G SERIES DATASHEETCBS

M029G/M030G/M031G Series

Reset Sources
Register
DAC Registers
SCPDIS(SYS_VREFCTL[8])PRELOADEN(SYS_VREFCTL[6])VREFSEL(SYS_VREFCTL[1])
VREFEN(SYS_VREFCTL[0])TSBGEN(SYS_TSCTL[1])POR

NRESET

WDT

LVR

BOD

Lockup

CHIP

MCU

CPU

Reset
Value

-

-

Reset
Value

Reset
Value

Reset
Value

-

-

-

0x0

-

-

0x0

0x0

0x0

-

-

-

0x0

-

-

0x0

0x0

0x0

-

-

-

0x0

-

-

0x0

0x0

0x0

-

-

-

0x0

-

-

0x0

0x0

0x0

-

-

-

0x0

-

-

0x0

0x0

0x0

-

-

-

Table 6.2-2 DAC Reset Retention Value of Registers
Reset Sources
Register
GPIO Registers

POR

NRESET

WDT

LVR

BOD

Lockup

CHIP

MCU

CPU

Reset
Value

-

-

Reset
Value

Reset
Value

Reset
Value

-

-

-

M029G/M030G/M031G SERIES DATASHEET

Table 6.2-3 GPIO Reset Retention Value of Registers
nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is anasynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 33 us (glitch filter), chip will be reset. The nRESET
reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the statekeeps longer than 33 us (glitch filter). The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous reset
source is nRESET reset. Figure 6.2-2 shows the nRESET reset waveform.

nRESET
0.7 VDD

33 us

0.2 VDD

33 us
nRESET Reset

Figure 6.2-2 nRESET Reset Waveform

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M029G/M030G/M031G Series
Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system tobe reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, thePOR module will detect the rising voltage and generate reset signal to system until the voltage is readyfor MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a
POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3 shows
the power-on reset waveform.

VPOR

VDD

0.1V

Power-onReset

Figure 6.2-3 Power-on Reset (POR) Waveform
Low Voltage Reset (LVR)

AVDD

VLVR

T1
( < LVRDGSEL)

T2( =LVRDGSEL)

Low Voltage Reset
200 usT3( =LVRDGSEL)

Delay for LVR stable

LVREN

Figure 6.2-4 Low Voltage Reset (LVR) Waveform

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If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function will
be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is lower
than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL (SYS_BODCTL[14:12]),chip will be reset. The LVR reset will control the chip in reset state until the AVDD voltage rises above
VLVR and the state keeps longer than De-glitch time set by LVRDGSEL (SYS_BODCTL[14:12]). The
default setting of Low Voltage Reset is enabled without De-glitch function. Figure 6.2-4 shows the Low
Voltage Reset waveform.

M029G/M030G/M031G Series
Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL (SYS_BODCTL[16])and the state keeps longer than De-glitch time set by BODDGSEL (SYS_BODCTL[10:8]), chip will bereset. The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and thestate keeps longer than De-glitch time set by BODDGSEL. Figure 6.2-5 shows the Brown-out Detector
waveform.
AVDD
VBODH
VBODL

Hysteresis

T1(< BODDGSEL)

T2(= BODDGSEL)BODOUT
T3(= BODDGSEL)BODRSTEN

M029G/M030G/M031G SERIES DATASHEET

Brown-out
Reset

Figure 6.2-5 Brown-out Detector (BOD) Waveform
Watchdog Timer Reset (WDT)In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used tocheck if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog timeout. User may decide to enable system reset during watchdog time-out to recover the system and takeaction for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is awatchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.

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M029G/M030G/M031G Series
CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex®-M0 core is reset and all other peripherals remain the same status
after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset andBS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM orLDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.

6.2.3

System Power Distribution

In this chip, power distribution is divided into three segments:


Analog power from AVDD and AVSS provides the power for analog components operation.



Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8V power for digital operation and I/O pins.

M029G/M030G/M031G package connect AVSS and VSS together.

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

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VREF

M029G/M030G/M031G Series

AVDD

12-bit ADC

Internal
Reference
Voltage

12-bit DAC0~3

Low Voltage
Reset

Brown-out
Detector

Temperature
Sensor

AVSS

SRAM

Flash

Digital Logic

1.8V

VDD to 1.8V
LDO

Power On
Control

VDD

M029G/M030G/M031G SERIES DATASHEETPOR33

48 MHz
HIRC
Oscillator

POR18

38.4 kHz
LIRC
Oscillator

IO Cell

VSS / EPAD

PLL

Figure 6.2-6 NuMicro® M029G/M030G/M031G Power Distribution Diagram

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M029G/M030G/M031G Series
6.2.4

Power Modes and Wake-up Sources

This chip has a power manager unit to support several operating modes for saving power. Table 6.2-4
lists all power modes in the M029G/M030G/M031G series.
Mode

CPU Operating Maximum Speed ( MHz)LDO (V)

Clock Disable

Normal mode

72/48

1.8

All clocks are disabled by control register.

Idle mode

CPU enters Sleep mode

1.8

Only CPU clock is disabled.

1.8

All clocks are disabled, except LIRC. And only
WDT/Timer/UART peripheral clocks still enable
if their clock sources are selected as LIRC.

Power-down mode CPU enters Power-down mode

Table 6.2-4 Power Mode Table
There are different power mode entry settings and leaving condition for each power mode. Table 6.2-5
shows the entry setting for each power mode. When chip power-on, chip is running in normal mode.
User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCTL[7]) and execute
WFI instruction.
Register/Instruction

SLEEPDEEP

PDEN

Mode

(SCR[2])(CLK_PWRCTL[7])

0

0

NO

0

0

YES

1

1

YES

Normal mode
Idle mode(CPU enters Sleep mode)
Power-down mode
(CPU enters Deep Sleep mode)

CPU Run WFI Instruction

There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-6 lists the available
clocks for each power mode.
Normal Mode

Idle Mode

Power-Down Mode

Definition

CPU is in active state

CPU is in sleep state

CPU is in sleep state and all clocks stop
except LIRC. SRAM content retended.

Entry Condition

Chip is in normal mode
CPU executes WFIafter system reset released instruction.

CPU sets sleep mode enable and power
down enable and executes WFI
instruction.

Wake-up Sources

N/A

All interrupts

WDT, I²C, Timer, UART, BOD, GPIO
and EINT

Available Clocks

All

All except CPU clock

LIRC

After Wake-up

N/A

CPU back to normal mode

CPU back to normal mode

Table 6.2-6 Power Mode Difference Table

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Table 6.2-5 Power Mode Entry Setting TableM029G/M030G/M031G Series

System reset released

Normal Mode
CPU Clock ON
PLL, HIRC, LIRC, HCLK, PCLK ON
Flash ONCPU executes WFI

1. SLEEPDEEP (SCS_SCR[2]) = 1
2. PDEN (CLK_PWRCTL[7]) = 1 and
PDWKIF (CLK_PWRCTL[6]) = 1
3. CPU executes WFIInterrupts occur

Wake-up events
occurPower-down Mode
CPU Clock OFF
PLL, HIRC, HCLK, PCLK OFF
LIRC ON
Flash Halt

Idle Mode
CPU Clock OFF
PLL, HIRC, LIRC, HCLK, PCLK ON
Flash Halt

Figure 6.2-7 Power Mode State Machine

M029G/M030G/M031G SERIES DATASHEET

Normal Mode

Idle Mode

Power-Down Mode

HIRC48 (48 MHz OSC)

ON

ON

Halt

LIRC (38.4 kHz OSC)

ON

ON

ON

PLL

ON

ON

Halt

HCLK/PCLK

ON

ON

Halt

CPU

ON

Halt

Halt

SRAM retention

ON

ON

ON

FLASH

ON

ON

Halt

TIMER

ON

ON

ON/OFF1

WDT

ON

ON

ON/OFF2

UART

ON

ON

ON/OFF3

Others

ON

ON

Halt

Table 6.2-7 Clocks in Power Modes
Note:
1. If TIMER clock source is selected as LIRC.
2. If WDT clock source is selected as LIRC.
3. If UART clock source is selected as LIRC.
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, BOD and GPIO
After chip enters power down, the following wake-up sources can wake up chip to normal mode. Table
6.2-8 lists the condition about how to enter Power-down mode again for each peripheral.
User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.

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M029G/M030G/M031G Series
Wake-Up

Wake-Up Condition

Source
BOD

System Can Enter Power-Down Mode Again Condition

Brown-Out Detector Interrupt After software writes 1 to clear BODIF (SYS_BODCTL[4]).

INT

External Interrupt

After software write 1 to clear the Px_INTSRC[n] bit.

GPIO

GPIO Interrupt

After software write 1 to clear the Px_INTSRC[n] bit.

TIMER

Timer Interrupt

After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF(TIMERx_INTSTS[0]).

WDT

WDT Interrupt

After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).

nCTS wake-up

After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).

RX Data wake-up

After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).

Address match

After software writes 1 to clear WKIF (I2C_WKSTS[0]).

UART
I2C

Table 6.2-8 Condition of Entering Power-down Mode Again

6.2.5

System Memory Map

This chip provides 4G-byte addressing space. The memory locations assigned to each on-chip
controllers are shown in Table 6.2-9. The detailed register definition, memory space, and programming
will be described in the following sections for each on-chip peripheral. The M029G/M030G/M031G
series only supports little-endian data format.
Address Space

Token

Controllers

Flash and SRAM Memory SpaceFLASH_BA

FLASH Memory Space (64 Kbytes)

0x2000_0000 – 0x2000_1FFF

SRAM_BA

SRAM Memory Space (8 Kbytes)

M029G/M030G/M031G SERIES DATASHEET

0x0000_0000 – 0x0000_FFFF

Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF

SYS_BA

System Control Registers

0x4000_0200 – 0x4000_02FF

CLK_BA

Clock Control Registers

0x4000_0300 – 0x4000_03FF

NMI_BANMI Control Registers

0x4000_4000 – 0x4000_4FFF

GPIO_BAGPIO Control Registers

0x4000_8000 – 0x4000_8FFF

PDMA_BA

Peripheral DMA Control Registers

0x4000_C000 – 0x4000_CFFF

FMC_BA

Flash Memory Control Registers

0x4003_1000 – 0x4003_1FFF

CRC_BA

CRC Generator Registers

APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF

WDT_BA

Watchdog Timer Control Registers

0x4004_3000 – 0x4004_3FFF

ADC_BA

Analog-Digital-Converter (ADC) Control Registers

0x4004_7000 – 0x4004_7FFF

DAC01_BA

DAC01 Control Registers

0x4004_B000 – 0x400B_7FFF

DAC23_BA

DAC23 Control Registers

0x4005_0000 – 0x4005_0FFF

TMR01_BA

Timer0/Timer1 Control Registers

0x4005_1000 – 0x4005_1FFF

TMR23_BA

Timer2/Timer3 Control Registers

0x4005_2000 – 0x4005_2FFF

TMR45_BA

Timer4/Timer5 Control Registers

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M029G/M030G/M031G Series
0x4005_B000 – 0x4005_BFFF

BPWM1_BA

BPWM Control Registers

0x4006_1000 – 0x4006_1FFF

SPI0_BASPI0 Control Registers

0x4007_0000 – 0x4007_0FFF

UART_BA

UART0 Control Registers

0x4008_0000 – 0x4008_0FFF

I2C0_BA

I2C0 Control Registers

0x4008_1000 – 0x4008_1FFF

I2C1_BAI2C1 Control Registers

0x400B_C000 – 0x400B_CFFF

MANCH_BA

Manchester Codec Control Registers

System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF

SCS_BA

System Timer Control Registers

0xE000_E100 – 0xE000_ECFF

SCS_BA

External Interrupt Controller Control Registers

0xE000_ED00 – 0xE000_ED8F

SCS_BA

System Control Registers

Table 6.2-9 Address Space Assignments for On-Chip Controllers

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M029G/M030G/M031G Series
6.2.6

SRAM Memory Organization

This chip supports embedded 2/4/8 Kbytes size SRAM:
Supports 2/4/8 Kbytes SRAM

Supports byte / half word / word writeSupports oversize response error

Figure 6.2-8 shows the M029G/M030G/M031G series SRAM organization. The address between
0x2000_2000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses
these illegal memory addresses.

0x3FFF_FFFF

Reserved
Reserved
512MB

Reserved

0x2000_2000

8K byteSRAM bank00x2000_1000
0x2000_0800

2K byteSRAM bank0
2K byte device

4K byte device

8K byte device

Figure 6.2-8 SRAM Memory Organization

6.2.7

Chip Bus Matrix

This chip supports Bus Matrix to manage the access arbitration between masters. The access arbitration
uses round-robin algorithm as the bus priority.

PDMA

Cortex®-M0

M1

M0

S0

S1

S2

S3

FLASH

SRAM

APB0

APB1

S4
AHB
(ctrl)

Figure 6.2-9 NuMicro® M029G/M030G/M031G Bus Matrix Diagram

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4K byteSRAM bank00x2000_0000

M029G/M030G/M031G Series
6.2.8

Temperature Sensor

This chip is equipped with an on-chip temperature sensor. Temperature sensor control registers arelocated in SYS_TSCTL and SYS_TSDATA.
User should set both TSEN(SYS_TSCTL[0]) and TSBGEN(SYS_TSCTL[1]) bits to 1 to enable thetemperature sensor. User needs to wait 200us for temperatre sensor to be stable, and then set
TSST(SYS_TSCTL[2]) bit to 1 to start temperature sensor conversion.
After temperature sensor conversion is finished, TSEOC(SYS_TSDATA[0]) bit will be set to 1
automatically, and TSDATA(SYS_TSDATA[27:16]) will present the temperature sensor data. Figure
6.2-10 shows the timing waveform of temperature sensor conversion.

Tstartup

Tconversion

Tconversion( > 200 us)( < 100 ms)( < 100 ms)

TSEN(SYS_TSCTL[0])TSBGEN(SYS_TSCTL[1])1st conversion

2nd conversion
Clear byhardwareTSST(SYS_TSCTL[2])Clear byhardwareClear by software

TSEOC(SYS_TSDATA[0])TSDATA(SYS_TSDATA[27:16])

1st Temperature Data[11:0]

Clear by software

2nd Temperature Data[11:0]

M029G/M030G/M031G SERIES DATASHEET

Figure 6.2-10 Temperature Sensor Conversion Waveform
Table 6.2-10 is a reference table for the relationship between temperature and TSDATA. Negative
temperature is represented in TSDATA(SYS_TSDATA[27:16]) by twos complement format, and per
LSB difference is equivalent to 0.0625 ° C.

Mar. 31, 2023

Temperature (°C)

Temperature Data (TSDATA)

128

0x7FF

127.9375

0x7FF

100

0x640

80

0x500

75

0x4B0

50

0x320

25

0x190

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M029G/M030G/M031G Series
0.25

0x004

0

0x000

-0.25

0xFFC

-25

0xE70

-55

0xC90

Table 6.2-10 Temperature Data Truth Table

6.2.9

Internal Voltage Reference (INT_VREF)

This chip supports internal voltage reference (INT_VREF) to provide the voltage reference for ADC and
DACs. The INT_VREF routes to VREF pin. User can set VREFEN(SYS_VREFCTL[0]) to select ADC and
DACs reference voltage sourcing from external VREF pin supply or internal INT_VREF. If using external
VREF source, VREFEN needs to be set to 0, and INT_VREF will output floating.
When VREFEN is set to 1, INT_VREF will be enabled. In addition, user can select INT_VREF output
voltage level 2.048V or 2.5V by VREFSEL(SYS_VREFCTL[1]). However, VREFSEL must be decided
before VREFEN is set to 1.
When VREFEN is set to 1, PRELOADEN(SYS_VREFCTL[6]) will be set automatically to shorten VREF
discharge and stable time. User needs to disable PRELOADEN function after stable time, otherwise it
will affect the maximum load current that INT_VREF can provide.

6.2.10 MANCH_TXD Modulation with BPWM1Mar. 31, 2023

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M029G/M030G/M031G SERIES DATASHEETThis chip supports MANCH_TXD to modulate with BPWM1_CH0 ~ BPWM1_CH5. User can set
MANCHMODEN (SYS_MODCTL[21:16]) to enable modulation function with each BPWM1 channel andset MANCHMODL (SYS_MODCTL[29:24]) to select MANCH_TXD data high or low to modulate with
BPWM1 channels. The Manchester modulation example waveform is shown in Figure 6.2-11.

M029G/M030G/M031G Series

BPWM1_CHn

MANCH_TXD

Modulated MANCH_TXD :MANCHMODE[n] = 0 &MANCHMODL[n] = x

MANCHMODE[n] = 1 &MANCHMODH[n] = 0

MANCHMODE[n] = 1 &MANCHMODH[n] = 1

Note: n=0, 1 .. 5

Figure 6.2-11 MANCH_TXD Modulated with BPWM1_CHn

6.2.11 Register Lock Control

M029G/M030G/M031G SERIES DATASHEET

Some of the system control registers need to be protected to avoid inadvertent write and disturb thechip operation. These system control registers are protected after the power-on reset till user to disable
register protection. For user to program these protected registers, a register protection disable sequenceneeds to be followed by a special programming. The register protection disable sequence is writing thedata “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100 continuously. Any
different data value, different sequence or any other write to other address during these three data
writing will abort the whole sequence. All proteced control registers are noted “(Write Protect)” and add
an note “Note: This bit is write protected. Refer to the SYS_REGLCTL register “ in register description
field.

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M029G/M030G/M031G Series
6.2.12 System Timer (SysTick)
The Cortex®-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-onwrite, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used
as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the countertransitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather thanan arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloadedwith this value. This mechanism can be used to disable the feature independently from the timer enablebit.
For more detailed information, please refer to the “Arm® Cortex®-M0 Technical Reference Manual” and“Arm® v6-M Architecture Reference Manual”.

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M029G/M030G/M031G Series
6.2.13 Nested Vectored Interrupt Controller (NVIC)
The Cortex®-M0 provides an interrupt controller as an integral part of the exception mode, named as“Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core andprovides following features:

Nested and Vectored interrupt support



Automatic processor state saving and restoration

Reduced and deterministic interrupt latency

The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of
the interrupts and most of the system exceptions can be configured to different priority levels. When aninterrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s
priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will
override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched froma vector table in memory. There is no need to determine which interrupt is accepted and branch to thestarting address of the correlated ISR by software. While the starting address is fetched, NVIC will also
automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At
the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal
execution. Thus it will take less and deterministic time to process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without theoverhead of states saving and restoration and therefore reduces delay time in switching to pending ISR
at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of
concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute(at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one
without delay penalty. Thus it advances the real-time capability.
M029G/M030G/M031G SERIES DATASHEETFor more detailed information, please refer to the “Arm® Cortex®-M0 Technical Reference Manual” and“Arm® v6-M Architecture Reference Manual”.

Exception Model and System Interrupt Map
Table 6.2-11 lists the exception model supported by the M029G/M030G/M031G series. Software canset four levels of priority on some of these exceptions as well as on all interrupts. The highest userconfigurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all
the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system,
after three system exceptions “Reset”, “NMI” and “Hard Fault”.

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M029G/M030G/M031G Series
Exception Name

Vector Number

Priority

Reset

1

-3

NMI

2

-2

Hard Fault

3-1

Reserved

4 ~ 10Reserved

SVCall11

Configurable

Reserved

12 ~ 13

Reserved

PendSV

14

Configurable

SysTick

15

Configurable

Interrupt (IRQ0 ~ IRQ31)

16 ~ 47

Configurable

Table 6.2-11 Exception Model

VectorNumberInterrupt Number(Bit
In
Registers)

Interrupt Interrupt Name

Interrupt Description--

System exceptions

16

0

BODOUT

Brown-Out low voltage detected interrupt

17

1

WDT_INT

Watchdog Timer interrupt

182

EINT024

External interrupt fromEINT0,2,4.

19

3

EINT135

External interrupt fromEINT1.3.5

20

4

GPAB_INT

External interrupt from PA, PB pin

21

5

GPCF_INT

External interrupt from PC, PF pin

22

6

TMR4_INT

Timer 4 interrupt

23

7

TMR5_INT

Timer 5 interrupt

24

8

TMR0_INT

Timer 0 interrupt

25

9

TMR1_INT

Timer 1 interrupt

26

10

TMR2_INT

Timer 2 interrupt

27

11

TMR3_INT

Timer 3 interrupt

28

12

UART0_INT

UART0 interrupt

29

13

Reserved

Reserved

30

14

SPI0_INT

SPI0 interrupt

31

15

Reserved

Reserved

32

16

Reserved

Reserved

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M029G/M030G/M031G Series
33

17

MANCH_INTManchester Codec interrupt

34

18

I2C0_INT

I2C0 interrupt

35

19

I2C1_INT

I2C1 interrupt

36

20

Reserved

Reserved

37

21

BPWM_INT

BPWM interrupt

38

22

Reserved

Reserved

39

23

DAC01_INT

DAC0/1 device interrupt

40

24

DAC23_INT

DAC2/3 device interrupt

41

25

TEMP_INTTEMP interrupt

42

26

PDMA_INTPDMA interrupt

43

27

Reserved

Reserved

44

28

PWRWU_INTClock controller interrupt for chip wake-up from power-down state

4529

ADC_INTADC interrupt

46

30

Reserved

Reserved

47

31

Reserved

Reserved

Table 6.2-12 Interrupt Number Table
Vector Table

M029G/M030G/M031G SERIES DATASHEETWhen an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt
service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base address is fixed
at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and theentry point addresses for all exception handlers. The vector number on previous page defines the orderof entries in the vector table associated with exception handler entry as illustrated in previous section.
Vector Table Word Offset

Description0

SP_main – The Main stack pointerVector Number

Exception Entry Pointer using that Vector Number

Table 6.2-13 Vector Figure Format
Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable orInterrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy,
both registers reading back the current enabled state of the corresponding interrupts. When an interrupt
is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will
not be activated. If an interrupt is Active when it is disabled, it remains in its Active state until cleared byreset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used toenable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effecton the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting
four interrupts).

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M029G/M030G/M031G Series
The general registers associated with the NVIC are all accessible from a block of memory in the System
Control Space and will be described in next section.

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6.3 Clock Controller
6.3.1

Overview

The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex®-M0 core executes the
WFI instruction. After that, chip enters Power-down mode and waits for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 48 MHz
internal high speed RC oscillator (HIRC) and Programmable PLL output clock frequency (PLLFOUT) to
reduce the overall system power consumption. Figure 6.3-1 shows the clock generator and the overview
of the clock source control.

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M029G/M030G/M031G Series

LIRC
38.4 kHz

HIRC
48MHz

PCLK1

PCLK0
I2C0

ADC

TMR0

I2C1

/1,/2,/4,/8,/16
HIRC

PLL FOUT

1/4

HIRC

PLLFOUT

111
1/(HCLKDIV+1)

PLLFOUT

HCLK

010

CPU

TMR1

TMR2

CRC

TMR4

TMR3

FMC

TMR5

BPWM1

PDMA

UART0

DAC0/1SRAM

WDT

DAC2/3

Manchester

SPI0

CLK_CLKSEL0[2:0]/1,/2,/4,/8,/16

LIRC

LIRC

11
WDT

HCLK

11
WWDT

HCLK

10

1/204810

1/2048

CLK_CLKSEL1[3:2]
CLK_CLKSEL1[1:0]

CPUCLKPLLFOUT
LIRC
PCLK0

001

HIRC

101

HCLK

1/(UART0DIV+1)

100

HIRC

UART0

1/2

111

1/2

011

1
SysTick
0

SYST_CTRL[2]011
CLK_CLKSEL0[5:3]

CLK_CLKSEL1[26:24]

PLLFOUTHIRC

DIV1EN(CLK_CLKOCTL[5])110

PLLFOUT

101

LIRC

PCLK1
(CLK_CLKOCTL[3:0]+1)

/2

100

HIRC

011

HCLK

0

CLKO

HIRC

01
10

1/(ADCDIV + 1)

ADC

11

1

010

ADCSEL(CLKSEL2[21:20])

CLK_CLKSEL1[6:4]

TM0/TM1

HIRC
111
101
011

PCLK0

LIRC
TMR0
TMR1

TM2/TM3

LIRC
TM4/TM5

010

TMR2
TMR3

010

CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]

HIRC

111
101
011

PCLK0

101
011

PCLK1

CLK_CLKSEL1[10:8]
CLK_CLKSEL1[14:12]

HIRC

111

PCLK1

TMR4
TMR5

PLLFOUT

11
10

1/(SPI0_CLKDIV[8:0]+1)

SPI0

01

010
CLK_CLKSEL2[5:4]

CLK_CLKSEL2[14:12]
CLK_CLKSEL2[18:16]

PCLK1
PLLFOUT1

BPWM 10

CLK_CLKSEL2[9]Figure 6.3-1 Clock Generator Global View Diagram

6.3.2

Clock Generator

The clock generator consists of 2 clock sources, which are listed below:48 MHz internal high speed RC oscillator (HIRC)



Programmable PLL output clock frequency (PLLFOUT) – PLL source is selected from 48

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HIRC
LIRC

M029G/M030G/M031G Series
MHz internal high speed oscillator (HIRC/4)


HIRCEN (CLK_PWRCTL[2])

/4

PLL

Internal 48 MHz
Oscillator(HIRC)PLLFOUTHIRCInternal 38.4
kHz Oscillator(LIRC)

LIRC

Figure 6.3-2 Clock Generator Block Diagram

6.3.3

System Clock and SysTick Clock

The system clock has 2 clock sources generated from clock generator block The clock source switch
depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in Figure 6.3-3.

M029G/M030G/M031G SERIES DATASHEETHCLKSEL(CLK_CLKSEL0[2:0])
HIRC
PLLFOUTCPUCLK

111

1/(HCLKDIV+1)
1/(HCLK_N+1)
HCLKDIV(CLK_CLKDIV0[3:0])

010

HCLK
PCLK0
/1,/2,/4,/8,/16

CPU in Power Down Mode

PCLK1

CPU
AHB
APB0
APB1

APB0DIV(CLK_PCLKDIV[3:0])
APB1DIV(CLK_PCLKDIV[[6:4])

Figure 6.3-3 System Clock Block Diagram
The clock source of SysTick in Cortex®-M0 core can use CPU clock or external clock (SYST_CTRL[2]).
If using external clock, the SysTick clock (STCLK) has 2 clock sources. The clock source switch depends
on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block diagram is shown in Figure
6.3-4.

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M029G/M030G/M031G Series

CPUCLK
HIRC
HCLK

1/2

111

1/2

011

1
SysTick
0

SYST_CTRL[2]STCLKSEL
CLK_CLKSEL0[5:3]

Figure 6.3-4 SysTick Clock Control Block Diagram

6.3.4

Peripherals Clock

The peripherals clock has different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSELx register description.

6.3.5

Power-down Mode Clock

When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are
disabled. Some clock sources and peripherals clock are still active in Power-down mode.
The clock that is still kept active is listed below:


6.3.6

Peripherals Clock (when the modules adopt LIRC as clock source)

Clock Output

The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to
CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low stateand stays in low state.

CLKOEN(CLK_CLKOCTL[4])PLLFOUT
LIRC
HIRC
HCLK

110

Enabledivide-by-2 counter

1/2

1/22

FREQSEL(CLK_CLKOCTL[3:0])

16 chained
divide-by-2 counter
1/23

…...

1/215

DIV1EN(CLK_CLKOCTL[5])

1/216
0000
0001
:
:
1110
1111

100
011
010

16 to 1
MUX

0

CLKO

1

CLKOSEL (CLK_CLKSEL1[6:4])

Figure 6.3-5 Clock Output Block Diagram

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M029G/M030G/M031G SERIES DATASHEETThis device is equipped with a power-of-2 frequency divider composed by 16 chained divide-by-2 shift
registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to
CLKO function pin. Therefore, there are 16 options of power-of-2 divided clocks with the frequency from
Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.

M029G/M030G/M031G Series
6.4 Flash Memory Controller (FMC)
6.4.1

Overview

This chip is equipped with 32/64 Kbytes on-chip embedded Flash. A User Configuration block isprovided for system initialization. A loader ROM (LDROM) is used for In-System-Programming (ISP)
function. A security protection ROM (SPROM) can conceal user program. This chip also supports InApplication-Programming (IAP) function. User switches the code executing without the chip reset after
the embedded Flash is updated.

6.4.2

FeaturesSupports 32/64 Kbytes application ROM (APROM).



Supports 512 bytes page size for 32/64 Kbytes Flash.

Supports 2 Kbytes loader ROM (LDROM).



Supports configurable Data Flash size to share with APROM.

Supports 512 bytes security protection ROM (SPROM) to conceal user program.

Supports 12 bytes User Configuration block to control system initialization.

Supports 512 bytes page erase for all embedded Flash.

Supports CRC-32 checksum calculation function.

Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory.

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M029G/M030G/M031G Series
6.5 General Purpose I/O (GPIO)
6.5.1

Overview

This chip has up to 28 General Purpose I/O pins to be shared with other function pins depending on thechip configuration. These 28 pins are arranged in 4 ports named as PA, PB, PC, PF. PA has 8 pins on
port. PB has 16 pins on port. PC has 1 pin on port. PF has 3 pins on port. Each of the 28 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
dependent on CIOINI (CONFIG0[10]).

6.5.2

Features

Four I/O modes:–

Quasi-bidirectional mode–

Push-Pull Output mode–

Open-Drain Output mode–

Input only with high impendence modeI/O pin can be configured as interrupt source with edge/level setting

Input schmitt trigger function

Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting–

CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset–

CIOINI = 1, all GPIO pins in input mode after chip reset

I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O modeSupports independent pull-up control

Enabling the pin interrupt function will also enable the wake-up functionSupports 5V-tolerance function except analog I/O (PA0~PA3, PB0~15, PF0)GPIO output can be configured to retention when system reset

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M029G/M030G/M031G Series
6.6 PDMA Controller (PDMA)
6.6.1

Overview

The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This has
the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. The
PDMA controller has a total of 7 channels and each channel can perform transfer between memory andperipherals or between memory and memory.

6.6.2

FeaturesSupports 7 independently configurable channels

Selectable 2 level of priorities (fixed priority or round-robin priority)Supports transfer data width of 8, 16, and 32 bits



Supports source and destination address increment size to be byte, half-word, word or no
incrementSupports software and I2C, SPI, UART, ADC, DAC, MANCH and TIMER request

Supports Scatter-Gather mode to implement complex transmission by using descriptor
link list tableSupports single and burst transfer typeSupports time-out function on channel 0 and channel1

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M029G/M030G/M031G Series
6.7 Timer Controller (TMR)
6.7.1

Overview

The timer controller includes up to six 32-bit timers, Timer0 ~ Timer5, allowing user to easily implementa timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement byexternal capture pins.

6.7.2

Features
Timer Function Features
Up to six sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit
prescale counter

Independent clock source for each timer

Provides one-shot, periodic, toggle-output and continuous counting operation modes

24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])

Supports event counting function

24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])

Supports external capture pin event for interval measurement

Supports external capture pin event to reset 24-bit up counterSupports internal capture triggered while LIRC transitionSupports chip wake-up from Idle/Power-down mode if a timer interrupt signal isgeneratedSupport Timer0 ~ Timer5 time-out interrupt signal or capture interrupt signal to trigger
ADC, DAC, PDMA, BPWM functionSupports Inter-Timer trigger mode

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M029G/M030G/M031G SERIES DATASHEETM029G/M030G/M031G Series
6.8 Watchdog Timer (WDT)
6.8.1

Overview

The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer also
supports the function to wake up system from Idle/Power-down mode.

6.8.2

Features

20-bit free running up counter for WDT time-out intervalSelectable time-out interval (24 ~ 220) and the time-out interval is 416us ~ 27.3 s if
WDT_CLK = 38.4 kHz (LIRC)



System kept in reset state for a period of (1 / WDT_CLK) * 63Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay periodSupports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]in Config0 registerSupports WDT time-out wake-up function only if WDT clock source is selected as LIRC

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M029G/M030G/M031G Series
6.9 Window Watchdog Timer (WWDT)
6.9.1

Overview

The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.

6.9.2

Features

6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexibleSupports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter

WWDT counter suspends in Idle/Power-down mode

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M029G/M030G/M031G Series
6.10 Basic PWM Generator and Capture Timer (BPWM)
6.10.1 Overview
This chip provides one BPWM generator (BPWM1). BPWM supports 6 channels of BPWM output or
input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit BPWM counter with 16bit comparator. The BPWM counter supports up, down and up-down counter types, all 6 channels share
one counter. BPWM uses the comparator compared with counter to generate events. These events areused to generate BPWM pulse, interrupt and trigger signal for ADC, DAC to start conversion. For BPWM
output control unit, it supports polarity output, independent pin mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value tocorresponding register when input channel has a rising transition, falling transition or both transition ishappened.

6.10.2 Features
6.10.2.1 BPWM Function FeaturesSupports maximum clock frequency up to 144 MHz

Supports one BPWM modules and provides 6 output channels

Supports independent mode for BPWM output/Capture input channelSupports 12-bit prescalar from 1 to 4096

Supports 16-bit resolution BPWM counter, the module provides 1 BPWM counter–Up, down and up/down counter operation typeSupports mask function and tri-state enable for each BPWM pinSupports interrupt in the following events:

M029G/M030G/M031G SERIES DATASHEET–BPWM counter matches 0, period value or compared valueSupports trigger DAC

Supports trigger ADC in the following events:–

BPWM counter matches 0, period value or compared value

6.10.2.2 Capture Function FeaturesSupports up to 6 capture input channels with 16-bit resolutionSupports rising or falling capture conditionSupports input rising/falling capture interrupt

Supports rising/falling capture with counter reload option

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M029G/M030G/M031G Series
6.11 UART Interface Controller (UART)
6.11.1 Overview
The chip provides one channels of Universal Asynchronous Receiver/Transmitters (UART). The UART
controller performs serial-to-parallel conversion on data received from the peripheral and parallel-toserial conversion on data transmitted from the CPU. Each UART controller channel supports ten typesof interrupts. The UART controller supports flow control function. The UART controller also supports
IrDA SIR, RS-485, and Single-wire function modes and auto-baud rate measuring function.

6.11.2 FeaturesFull-duplex asynchronous communications

Separates receive and transmit 1/1 byte entry FIFO for data payloads

Supports hardware auto-flow control

Programmable receiver buffer trigger levelSupports programmable baud rate generator for each channel individuallySupports nCTS and incoming data wake-up functionSupports 8-bit receiver buffer time-out detection functionProgrammable transmitting data delay time between the last stop and the next start bit bysetting DLY (UART_TOUT[15:8])

Supports Auto-Baud Rate measurement functionSupports break error, frame error, parity error and receive/transmit buffer overflow
detection function

Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character–

Programmable parity bit, even, odd, no parity or stick parity bit generation anddetection–

Programmable stop bit, 1, 1.5, or 2 stop bit generation

Supports IrDA SIR function mode–Supports for 3/16 bit duration for normal mode

Supports RS-485 function mode–

Supports RS-485 9-bit mode–

Supports hardware or software enables to program nRTS pin to control RS-485
transmission directionSupports PDMA transfer functionSupport Single-wire function mode

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M029G/M030G/M031G SERIES DATASHEET–M029G/M030G/M031G Series
UART Feature

UART0

FIFO

1 Bytes

Auto Flow Control (CTS/RTS)

√

IrDA

√

LIN

-

RS-485 Function Mode√nCTS Wake-up√

Incoming Data Wake-up√

Received Data FIFO reached threshold
Wake-up
RS-485 Address Match (AAD mode)
Wake-up
Auto-Baud Rate Measurement√

STOP Bit Length

1, 1.5, 2 bit

Word Length

5, 6, 7, 8 bits

Even / Odd Parity√

Stick Bit√

Table 6.11-1 UART Features

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M029G/M030G/M031G Series
6.12 Serial Peripheral Interface (SPI)
6.12.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains one set of SPI controller performing a serial-to-parallel conversion on data received froma peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each
SPI controller can be configured as a master or a slave device and supports the PDMA function toaccess the data buffer.

6.12.2 Features

SPI Mode
Supports one set of SPI controller–

Supports Master or Slave mode operation–

Configurable bit length of a transaction word from 8 to 32-bit–

Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO
buffers which depends on SPI setting of data width–

Supports MSB first or LSB first transfer sequence–

Supports Byte Reorder function–

Supports Byte or Word Suspend mode–

Master mode up to 24 MHz and Slave mode up to 16 MHz (when chip works at VDD =1.8~3.6V)–

Supports one data channel half-duplex transfer–

Supports receive-only mode–

Supports PDMA transfer

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M029G/M030G/M031G Series
6.13 I2C Serial Interface Controller (I2C)
6.13.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and arbitrationthat prevents data corruption if two or more masters attempt to control the bus simultaneously.
There are two sets of I2C controllers that support Power-down wake-up function.

6.13.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to thebus. The main features of the I2C bus include:

M029G/M030G/M031G SERIES DATASHEETSupports up to two I2C ports



Master/Slave modeBidirectional data transfer between masters and slaves

Multi-master bus (no central master)Supports Standard mode (100 kbps), Fast mode (400 kbps)



Supports Fast mode plus (1 Mbps) (M030G/M031G)



Arbitration between simultaneously transmitting masters without corruption of serial dataon the bus

Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus

Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up andtimer-out counter overflowsProgrammable clocks allow for versatile rate control

Supports 7-bit addressingSupports multiple address recognition (four slave address with mask option)Supports Power-down wake-up functionSupports PDMA with one buffer capabilitySupports two-level buffer function (only supported in slave mode)Supports setup/hold time programmableSupports built-in I2C bootloader

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M029G/M030G/M031G Series
6.14 CRC Controller (CRC)
6.14.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.

6.14.2 FeaturesSupports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32–

CRC-CCITT: X16 + X12 + X5 + 1–

CRC-8: X8 + X2 + X + 1–

CRC-16: X16 + X15 + X2 + 1–

CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

Programmable seed valueSupports programmable order reverse setting for input data and CRC checksumSupports programmable 1’s complement setting for input data and CRC checksumSupports 8/16/32-bit of data width–

8-bit write mode: 1-AHB clock cycle operation–

16-bit write mode: 2-AHB clock cycle operation–

32-bit write mode: 4-AHB clock cycle operation

Supports using PDMA to write data to perform CRC operation
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M029G/M030G/M031G Series
6.15 CRC Controller (CRC) - Configurable
6.15.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with 8-bits, 16-bits and32-bits configurable polynomials.

6.15.2 FeaturesSupports 8-bits, 16-bits and 32-bits configurable polynomials

Programmable seed valueSupports programmable order reverse setting for input data and CRC checksumSupports programmable 1’s complement setting for input data and CRC checksumSupports 8/16/32-bit of data width–

8-bit write mode: 1-AHB clock cycle operation–

16-bit write mode: 2-AHB clock cycle operation–

32-bit write mode: 4-AHB clock cycle operation

Supports using PDMA to write data to perform CRC operation

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M029G/M030G/M031G Series
6.16 Manchester Controller (MANCH)
6.16.1 Overview
The Manchester code is used to transmit a plenty of continuous data in a single bus without synchronous
clock. In each encoded data bit, there is an edge transition in the middle to synchronize the internal
clock. Hence, the clock deviation between receiver and transmitter will not affect the communication.
The Manchester Controller supports encode and decode function with at least 2 modulation signal
formats (Mode 1 and Mode 2). The Manchester Controller also supports programmable format. The
format of the preamble of the data packet and the idle pattern of bus can be defined. The Manchester
Controller supports three 4-level FIFO for transmit, encoded and decoded data. To read/write the data
from/into FIFO, PDMA can be used and combined with other peripherals. The Manchester encodededge function can also trigger Timer Controller and interconnect with PDMA and DAC.

6.16.2 FeaturesSupports encode/decode Manchester codeSupports different modulation signal format–

Mode 1–Mode 2–

Programmable format
Programmable Idle patternProgrammable preamble style and its transmitted numberProgrammable data size in a frame

Supports configurable Manchester bit rateSupports selectable deglitch time functionSupports three 4-level FIFO for transmit, encoded and decoded dataSupports PDMA for data receiving/transmitting individuallySupports Manchester encoded edge function to trigger Timer ControllerSupports bit detect error, receive FIFO overflow, receive frame done and transmit frame
done interrupt

Mar. 31, 2023

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M029G/M030G/M031G SERIES DATASHEETM029G/M030G/M031G Series
6.17 Analog-to-Digital Converter (ADC)
6.17.1 Overview
The ADC contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter)with 16 input channels. The A/D converter supports four operation modes: Single, Burst, Single-cycle
Scan and Continuous Scan mode. The A/D converter can be started by software, external pin (STADC),
timer0~timer5 overflow pulse trigger or BPWM trigger.

6.17.2 Features

Operating voltage: 1.8V~3.6V.

Analog input voltage: 0 ~ AVDD.

Supports external reference voltage from VREF pin.

12-bit resolution and 10-bit accuracy is guaranteed.

Up to 16 single-end analog input channels or 8 differential analog input channels.

Maximum ADC peripheral clock frequency is 34 MHz.



Up to 1.4 MSPS (M029G/M030G) or 2 MSPS (M031G) sampling rate.



Scan on enabled channels

Threshold voltage detection

Four operation modes:

M029G/M030G/M031G SERIES DATASHEET–Single mode: A/D conversion is performed one time on a specified channel.

–

Burst mode: A/D converter samples and converts the specified single channel andsequentially stores the result in FIFO.

–

Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.

–

Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode
until software stops A/D conversion.

An A/D conversion can be started by:–

Software Write 1 to ADST bit–

External pin (STADC)–

Timer 0~timer5 overflow pulse trigger–

BPWM triggerEach conversion result is held in data register of each channel with valid and overrun
indicators.

Conversion result can be compared with specified value and user can select whether togenerate an interrupt when conversion result matches the compare register setting.

Supports extend sample time function (0~255 ADC clock).

One internal channel from band-gap voltage (VBG).



One internal channel from internal pull-up/down circuit.

Supports PDMA transfer mode.

Supports Calibration mode.

Supports Floating Detect Function

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M029G/M030G/M031G Series
Note1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
Note2: If the internal channel for band-gap voltage is active, the minimum time of sample stage should
be TVBG_ADC. Please refer to section 8.2 for detailed information.
Note3: The ADC Clock frequency must be slower than or equal to PCLK.

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M029G/M030G/M031G Series
6.18 Digital to Analog Converter (DAC)
6.18.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be configured to 12-or 8bit output mode and can be used in conjunction with the PDMA controller. The DAC integrates a voltage
output buffer that can be used to reduce output impendence and drive external loads directly without
having to add an external operational amplifier.

6.18.2 Features

M029G/M030G/M031G SERIES DATASHEET

Analog output voltage range: 0~AVDD.

Supports 12-or 8-bit output mode.

Rail to rail settle time 5us.

Supports up to two 12-bit 1 MSPS voltage type DAC (DAC0/DAC1). (M029G)

Supports up to four 12-bit 1 MSPS voltage type DAC (DAC0/DAC1/DAC2/DAC3).
(M030G/M031G)



Reference voltage from internal reference voltage (INT_VREF), VREF pin.



DAC maximum conversion updating rate 1 MSPS.

Supports voltage output buffer mode and bypass voltage output buffer mode.

Supports software and hardware trigger, including Timer0~5,BPWM1 trigger to start DAC
conversion.

Supports PDMA mode.

Supports group mode of synchronized update capability for two DACs.



DAC output can be configured to retention when system reset.

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M029G/M030G/M031G Series
6.19 Peripherals Interconnection
6.19.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous
action between peripherals without needing to involve the CPU. Peripherals interact without CPU saves
CPU resources, reduces power consumption, operates with no software latency and fast responds.

6.19.2 Peripherals Interconnect Matrix table
Please refer to the relative Technical Reference Manual for detailed functional description about the
peripherals interconnection.
Destination
Source
ADC

DAC

PWM

Timer

LIRC

-

-

-

√

BPWM

√

√

-

-

Timer

√

√

√

√

Manchester Codec√√

Table 6.19-1 Peripherals Interconnect Matrix table

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M029G/M030G/M031G Series
7

APPLICATION CIRCUIT

7.1 Power Supply Schemea s clos e to AVDD a s pos s ible
L=30Z

EXT_P WR
AVDD

AVS S

1uF+0.1uF+0.01uF
L=30Z

a s clos e to the
EXT_P WR a s pos s ible

10uF+0.1uF

VREF

2.2uF+1uF+470pF

L=30Z
a s clos e to VREF a s pos s ible

VDD

M029G/M030G/M031G SERIES DATASHEETVS S / EP AD

EXT_VS S

0.1uF*Na s clos e to VDD a s pos s ible

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M029G/M030G/M031G Series
7.2 Peripheral Application Scheme
DVCC

100K

SWD
Interface

DVCC

100K
VDD
ICE_DATnRESET/ICE_CLK
VSS/EPAD

CS
CLK
MISO
MOSI

SPI_SSSPI_CLKSPI_MISO
SPI_MOSIVDD

SPI Device

VSS

DVCC
DVCC

M030G/M031G Series
4.7
K

4.7
K

I2C_SCL

CLK

VDD

I2C_SDADIOVSSI2C Device

RS 232 Transceiver PC COM Port
UART_RXD

ROUT

RIN

UART_TXD

TIN

TOUT

UART

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M029G/M030G/M031G Series
8

ELECTRICAL CHARACTERISTICS

8.1

Absolute Maximum Ratings

Stresses above the absolute maximum ratings may cause permanent damage to the device. The limiting
values are stress ratings only and cannot be used to functional operation of the device. Exposure to theabsolute maximum ratings may affect device reliability and proper operation is not guaranteed.

8.1.1

Voltage Characteristics

Symbol

Min

Max

Unit

-0.3

4.0

V

Variations between different power pins

-

50

mV

Allowed voltage difference for VDD and AVDD

-

50

mV

ΔVSS

Variations between different ground pins

-

50

mV

|VSS - AVSS|

Allowed voltage difference for VSS and AVSS

-

50

mV

VSS-0.3

5.5

V

VSS-0.3

4.0

V

VDD-VSS[*1]ΔVDD|VDD –AVDD|

Description
DC power supply

Input voltage on 5V-tolerance I/O
VIN
[*2]

Input voltage on any other pin
Note:

1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Non 5V-tolerance I/O includes PA.0 ~ 3; PB.0 ~ 15; PF.0; nRESET pin. VIN maximum value must be respected to avoid
permanent damage. Refer to Table 8.1-2 for the values of the maximum allowed injected current

Table 8.1-1 Voltage Characteristics
M029G/M030G/M031G SERIES DATASHEET

8.1.2

Current Characteristics
SymbolMin

Max

Maximum current into VDD-

150

Maximum current out of VSS-

100

Maximum current sunk by a I/O Pin-

20

Maximum current sourced by a I/O Pin-

20

Maximum current sunk by total I/O Pins[*2]-100Maximum current sourced by total I/O Pins[*2]-100

IINJ(PIN) [*3]

Maximum injected current by a I/O Pin-±5

ΣIINJ(PIN) [*3]

Maximum injected current by total I/O Pins-

±25

ΣIDD[*1]
ΣISS

Description

Unit

mA

IIO

Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be exceeded.
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

Table 8.1-2 Current Characteristics

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M029G/M030G/M031G Series
8.1.3

Thermal Characteristics

The average junction temperature can be calculated by using the following equation:
TJ = TA + (PD x θJA )TA = ambient temperature (°C)θJA = thermal resistance junction-ambient (°C/Watt)
PD = sum of internal and I/O power dissipation

SymbolDescription

Min

Typ

Max

TA

Operating ambient temperature

-40

-

105

TJ

Operating junction temperature

-40

-

125

TST

Storage temperature

-65

-

150

-

68

-

°C/Watt

-

37.9

-

°C/Watt

Thermal resistance junction-ambientθJA[*1]24-pin QFN(3x3 mm)
Thermal resistance junction-ambient
33-pin QFN(4x4 mm)

Unit

°C

Note:
1. Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions

Table 8.1-3 Thermal Characteristics

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M029G/M030G/M031G Series
8.1.4

EMC Characteristics
Electrostatic discharge (ESD)

For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:

A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
Electrical fast transients (EFT)

In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts ofnarrow high-frequency transients on the power distribution system..
Inductive loads:
Relays, switch contactors
Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 byInternational ElectrotechnicalCommission (IEC).
––

SymbolDescription

Min

Typ

Max

Unit

VHBM[*1]

Electrostatic discharge,human body mode

-7000

-

+7000

VCDM[*2]

Electrostatic discharge,charge device model

-1000

-

+1000

LU[*3]

Pin current for latch-up[*3]

-400

-

+400

mA

VEFT[*4]

Fast transient voltage burst

-4.4

-

+4.4

kV

V

M029G/M030G/M031G SERIES DATASHEET

Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test, the performace cretia class is 4A.

Table 8.1-4 EMC Characteristics

8.1.5

Package Moisture Sensitivity(MSL)The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.

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M029G/M030G/M031G Series
PacakgeMSL

24-pin QFN(3x3 mm) [*1]MSL 333-pin QFN(4x4 mm) [*1]

MSL 3

Note:
1. Determined according to IPC/JEDEC J-STD-020

Table 8.1-5 Package Moisture Sensitivity (MSL)

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M029G/M030G/M031G Series
8.1.6

Soldering Profile

Figure 8.1-1 Soldering Profile from J-STD-020C
M029G/M030G/M031G SERIES DATASHEET

Porfile Feature

Pb Free Package

Average ramp-up rate (217°C to peak)

3°C/sec. max

Preheat temperature 150°C ~200°C

60 sec. to 120 sec.

Temperature maintained above 217°C

60 sec. to 150 sec.

Time with 5°C of actual peak temperature> 30 sec.

Peak temperature range

260°C

Ramp-down rate

6°C/sec ax.

Time 25°C to peak temperature

8 min. max

Note:
1. Determined according to J-STD-020C

Table 8.1-6 Soldering Profile

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M029G/M030G/M031G Series
8.2

General Operating Conditions(VDD-VSS = 2.7 ~ 3.6V, TA = 25°C, HCLK = 48/72 MHz unless otherwise specified.)
SymbolParameter

Min

Typ

Max

Unit

TA

Temperature

-40

-

105

°C

fHCLK

Internal AHB clock frequency

-

-

72

MHz

VDD

Operation voltage

2.7

-

3.6

AVDD[*1]

Analog operation voltage

Test Conditions

VDD = 2.7V~3.6V
VDD > BOD detect voltage
while chip power on [*4]VDD
VREF <= AVDD - 0.2V,
V

VREF

Analog reference voltage

2.048

-

AVDD

when VREFEN(SYS_VREFCTL[0]) =1’b1.
VREF <= AVDD,
when VREFEN(SYS_VREFCTL[0]) =1’b0.

VBG[*3]Band-gap voltage

1.16

1.23

1.31

ADC sampling time when reading
the band-gap voltage

20

-

-

µS

IRUSH[*2]

InRush current on voltage
regulator power-on (POR or
wakeup from Standby)

-

150

200

mA

ERUSH[*2]

InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)

-

2.25

3.00

µC

TVBG_ADC[*3]VDD = 2.7 V, TA = 105 °C,
IRUSH = 150 mA for 15 us

1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation.
2. Guaranteed by design, not tested in production
3. Based on characterization, not tested in production unless otherwise specified.
4. BOD brown-out detect function is default enabled and BODVL is set to 0. While chip power up, VDD and AVDD should
higher than BOD detect voltage, otherwise, chip will remain at reset stage.

Table 8.2-1 General Operating Conditions

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M029G/M030G/M031G SERIES DATASHEETNote:M029G/M030G/M031G Series
8.3

DC Electrical Characteristics

8.3.1

Supply Current Characteristics

The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.






All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature(TA), and the typical values for TA= 25 °C and VDD = 2.7V ~ 3.6 V unless otherwise
specified.
VDD = AVDD
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK.
Program run while(1) code in Flash.
Typ [*1]

SymbolConditions

Max[*1][*2]
Unit

FHCLK

M029G/M030G/M031G SERIES DATASHEETTA = 25 °C

TA = 25 °C

TA = 85 °C

TA = 105 °C

72 MHz

14.30

14.65

14.80

15.05

Normal run mode, executedfrom Flash, all peripherals
disable48 MHz

9.80

9.95

10.25

10.50

HIRC, PLL clock

24 MHz

6.40

6.50

6.80

7.00

12 MHz

4.70

4.75

5.00

5.20

4 MHz

3.50

3.55

3.75

3.95

72 MHz

22.65

23.05

23.50

23.85

48 MHz

15.45

15.75

16.20

16.45

24 MHz

9.35

9.55

9.85

10.10

12 MHz

6.25

6.35

6.65

6.85

4 MHz

4.15

4.20

4.45

4.65

IDD_RUN

Normal run mode, executedfrom Flash, all peripherals
enable
HIRC, PLL clock

mA

Note:
1. When analog peripheral blocks such as ADC, DAC, Temperature Sensor, INT_VREF, PLL, HIRC are ON, an
additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.

Table 8.3-1 Current Consumption in Normal Run ModeMar. 31, 2023

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M029G/M030G/M031G Series
Max[*1] [*2]TypSymbolConditions

Unit

FHCLK

Idle mode, all peripherals
disableHIRC, PLL clock

TA = 25 °C

TA = 25 °C

TA = 85 °C

TA = 105 °C

72 MHz

6.90

7.00

7.25

7.50

48 MHz

4.05

4.10

4.35

4.55

24 MHz

3.55

3.60

3.80

4.00

12 MHz

3.25

3.25

3.50

3.60

4 MHz

3.00

3.05

3.25

3.45

IDD_IDLE

mA

Idle mode, all peripherals
enable
HIRC, PLL clock

72 MHz

15.15

15.45

15.90

16.25

48 MHz

9.60

9.75

10.15

10.40

24 MHz

6.30

6.40

6.70

6.95

12 MHz

4.60

4.70

4.95

5.15

4 MHz

3.50

3.55

3.75

3.95

Note:
1. When analog peripheral blocks such as ADC, DAC, Temperature Sensor, INT_VREF, PLL, HIRC are ON, an additional
power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.

M029G/M030G/M031G SERIES DATASHEET

Table 8.3-2 Current Consumption in Idle ModeMar. 31, 2023

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M029G/M030G/M031G Series
Typ[*1]
SymbolMax[*2][*3]Unit

Test Conditions

Power-down mode, all peripherals disable,

TA = 25 °C

TA = 25 °C

TA = 85 °C

TA = 105 °C

1730[*4]

1820[*4]2080[*4]2350[*4]

230

320

580

850

and LDO Pre-load enable

Power-down mode, all peripherals disable,
and LDO Pre-load disable
IDD_PDµA
Power-down mode, UART/Timer/WDT use LIRC,

1730[*4]

1825[*4]2085[*4]2355[*4]

230

325

585

855

and LDO Pre-load enable

Power-down mode, UART/Timer/WDT use LIRC,
and LDO Pre-load disable
Note:

1. VDD = AVDD = 3.3V, LVR23 enabled, POR disabled and BOD disabled.
2. Based on characterization, not tested in production unless otherwise specified.
3. When analog peripheral blocks such as ADC, DAC, Temperature Sensor, INT_VREF, PLL, HIRC are ON, an additional
power consumption should be considered.
4. Based on characterization, tested in production.

M029G/M030G/M031G SERIES DATASHEET

Table 8.3-3 Chip Current Consumption in Power-down ModeMar. 31, 2023

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M029G/M030G/M031G Series
8.3.2

On-Chip Peripheral Current ConsumptionThe typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function.
HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
IDD[*1]

PDMA

305

ISP

0.1

CRC

44

WDT/WWDT

120

TMR0

270

TMR1

260

TMR2

315

TMR3

320

TMR4

290

TMR5

270

CLKO

75

I2C0

60

I2C1

55

SPI0

665

UART0

505

ADC[*2]

530

BPWM1

615

DAC0[*3]85

DAC1[*3]70

Manch. Codec

675

Temperature Sensor[*4]

0.1

Unit

uA

M029G/M030G/M031G SERIES DATASHEET

Peripheral

Note:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the DAC is turned on, add an additional power consumption per DAC for the analog part.
4. Temperature Sensor doesn’t have clock enable bit for this test item. When the Temperature Sensor is turned on, add
an additional power consumption per Temperature Sensor for the analog part.

Table 8.3-4 Peripheral Current Consumption

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M029G/M030G/M031G Series
8.3.3

Wakeup Time from Low-Power Modes

The wakeup times given in Table 8.3-5 is measured on a wakeup phase with a 48 MHz HIRC
oscillator.
SymboltWU_IDLEtWU_NPD[*1][*2]Parameter

Typ

Max

Unit

Wakeup from IDLE mode

5

6cyclesWakeup from normal power down mode

13

-

µs

Note:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
instruction.
3. Guaranteed by design.

Table 8.3-5 Low-power Mode Wakeup Timings

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M029G/M030G/M031G Series
8.3.4

I/O Current Injection Characteristics

In general, I/O current injection due to external voltages below VSS or above VDD except 5V-tolenece I/Oshould be avoided during normal product operation. However, the analog compoenent of the MCU ismost likely to be affected by the injection current , but it is not easily clarified when abnormal injection
accidentally happens. It is recommended to add a Schottky diode (pin to ground or pin to VDD) to pinsthat include analog function which may potentially injection currents.
SymbolParameter

IINJ(PIN) Injected current by a I/O Pin

Negative
injection

Positive
injection-00Injected current on nReset pins

-00Injected current on PA0~PA3 andmA PB0~PB15 for analog input function-5+5Injected current on any other 5Vtolerance I/O

Unit

Test Condition

Table 8.3-6 I/O Current Injection Characteristics

8.3.5

I/O DC Characteristics
PIN Input Characteristics

SymbolParameter

Min

Typ

Max

Unit

Input low voltage

0-0.3*VDD

V

VIH

Input high voltage

0.7*VDD-

VDD

V

VHY[*1]

Hysteresis voltage of schmitt input-

0.2*VDD

-

V

-1

-

1

ILK[*2]

RPU[*1]

VSS < VIN < VDD,
Open-drain or input only mode
µA

Input leakage current
-1

-

1

32

38

54

45

60

79

Pull up resistor

VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pinskΩ

VDD = 3.6 V, Input mode
VDD = 2.7 V, input mode

Note:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.

Table 8.3-7 I/O Input Characteristics

Mar. 31, 2023

Page 95 of 120

Rev 1.02

M029G/M030G/M031G SERIES DATASHEETVIL

Test Conditions

M029G/M030G/M031G Series
I/O Output Characteristics
SymbolParameter

Source current for quasibidirectional mode andhigh level

Min

Typ

Max

Unit

-25.5

-28

-32

µA

-18

-22

-24

µA

-8

-10

-15

mA

-6

-8

-13

mA

7.5

9

14.5

mA

6

7.5

13

mA

-

5

-

pF

Test Conditions
VDD = 3.3 V
VIN=(VDD-0.4) V

VDD = 2.7 V
VIN=(VDD-0.4) V

ISR[*1] [*2]

Source current for pushpull mode and high level

ISK[*1] [*2]

CIO[*1]

Sink current for push-pullmode and low level

I/O pin capacitanceVDD = 3.3 V
VIN=(VDD-0.4) V
VDD = 2.7 V
VIN=(VDD-0.4) V
VDD = 3.3 V
VIN= 0.4 V
VDD = 2.7 V
VIN= 0.4 V

Note:
1. Guaranteed by characterization result, not tested in production.
2.

The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must notexceed ΣIDD and ΣISS.

M029G/M030G/M031G SERIES DATASHEET

Table 8.3-8 I/O Output Characteristics
nRESET Input Characteristics
SymbolParameter

Min

Typ

Max

Unit

VILR

Negative going threshold, nRESET--

0.3*VDDV

VIHR

Positive going threshold, nRESET

0.7*VDD

-

-

V

32

38

54

RRST[*1]

Internal nRESET pull up resistor
45

60

79

-

32

-

31.36

-

32.64

tFR[*1]nRESET input filtered pulse timeKΩ

Test Conditions

VDD = 3.6 V
VDD = 2.7 V
Normal run and Idle modeµS 32us=3*512*HIRCPower down mode

Note:
1. Guaranteed by characterization result, not tested in production.

Table 8.3-9 nRESET Input Characteristics

Mar. 31, 2023

Page 96 of 120

Rev 1.02

M029G/M030G/M031G Series
8.4

AC Electrical Characteristics

8.4.1

48 MHz Internal High Speed RC Oscillator (HIRC)

The 48 MHz RC oscillator is calibrated in production.
Symbol.
VDD

Parameter

Min

Typ

Max

Unit

Operating voltage

2.7

3.3

3.6

V

Oscillator frequnecy

-

48

-

MHz

-0.5

-

+0.5

%

-0.7

-

+0.7

%

-1

-

+1

%

-2

-

+2

%

fHRC[*1]
Frequency drift over temperarure andvolatge

IHRC[*1]

Operating current

-

500

700

µA

TS[*2]

Stable time

-

-

20

µs

Test Conditions

TA = 25 °C,
VDD = 3.3V
TA = 25 °C,
VDD = 3.3V
TA = 0°C ~ +70 °C,
VDD = 3.3V
TA = -20°C ~ +105 °C,
VDD = 3.3V
TA = -40°C ~ +105 °C,
VDD = 2.7 ~ 3.6V

TA = -40°C ~ +105 °C,
VDD = 2.7 ~ 3.6V

Note:
1. Guaranteed by characterization result, not tested in production.

M029G/M030G/M031G SERIES DATASHEET

2. Guaranteed by design.

Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics

Frequency Drift Over Temperarure when VDD = 3.6 V
2.00%
1.50%

Percentage(%)

1.00%
0.50%
0.00%

Max

-0.50%

Min-1.00%-1.50%-2.00%

-40

-20

0

20

40

60

80

100

120

Temperature (°C)(a) Test Condition: VDD = 3.6 V, Temp. = -40 ~ 125 °C

Mar. 31, 2023

Page 97 of 120

Rev 1.02

M029G/M030G/M031G SeriesFrequency Drift Over Temperarure when VDD = 3.3 V
2.00%
1.50%

Percentage(%)

1.00%
0.50%
0.00%

Max

-0.50%

Min-1.00%-1.50%-2.00%

-40

-20

0

20

40

60

80

100

120

Temperature (°C)(b) Test Condition: VDD = 3.3 V, Temp. = -40 ~ 125 °C

Frequency Drift Over Temperarure when VDD = 2.5 V
2.00%
1.50%

Percentage(%)

M029G/M030G/M031G SERIES DATASHEET

1.00%
0.50%
0.00%

Max

-0.50%

Min-1.00%-1.50%-2.00%

-40

-20

0

20

40

60

80

100

120

Temperature (°C)(c) Test Condition: VDD = 2.5 V, Temp. = -40 ~ 125 °C
Note:
The graph is a statistical result using a limited number of samples. For the actual characetristic range, please refer toTable 8.4-1.

Figure 8.4-1 HIRC vs. Temperature

Mar. 31, 2023

Page 98 of 120

Rev 1.02

M029G/M030G/M031G Series
8.4.2

38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Min [*1]

TypMax [*1]

Unit

Operating voltage

2.7

3.3

3.6

V

Oscillator frequnecy

-

38.4

-

kHz

-

1

-

%

-50

-

+50

%

SymbolParameter

VDD

FLRC [*2]Frequency drift over temperarureand volatge

Test Conditions

TA = 25 °C,
VDD = 3.3V
TA=-40~105 °C
VDD=2.7V~3.6V
Without software calibration

ILRC

Operating current

-

1

1.1

µA

VDD = 3.3V

TS

Stable time

-

100

-

μs

TA=-40~105 °C
VDD=2.7V~3.6V

Note:
1. Guaranteed by characterization, not tested in production.
2. The 38.4 kHz low speed RC oscillator can be calibrated by user.

Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics

8.4.3

PLL Characteristics

SymbolParameter

Min[*1]

Typ

Max[*1]

Unit

Test Conditions

PLL input clock

3.2

-

32

MHz

fPLL_OUT

PLL multiplier output clock

50

-

144

MHz

fPLL_REF

PLL reference clock

0.8

-

8

MHz

fPLL_VCO

PLL voltage controlled oscillator

200

-

500

MHz

TL

PLL locking time

-

-

500

µS

Jitter[*2]Cycle-to-cycle Jitter

-

200

350

pS

IDD

Power consumption

-

5

9

mA

VDD =3.3V @ fPLL_OUT = 144
MHz

Unit

Test Conditions[*2]Notes:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
The fPLL_OUT must meet the restrictions of CPU and peripheral.

Table 8.4-3 PLL characteristics

8.4.4

I/O AC Characteristics

Symboltf(IO)outtr(IO)out

Parameter

Typ.

Max[*1].

-

6

Output high (90%) to low level (10%) fall time

Output low (10%) to high level (90%) rise timeMar. 31, 2023

CL = 30 pF, VDD >= 2.7 V
ns

-

3.5

-

6

Page 99 of 120

CL = 10 pF, VDD >= 2.7 V
ns

CL = 30 pF, VDD >= 2.7 V

Rev 1.02

M029G/M030G/M031G SERIES DATASHEETfPLL_inM029G/M030G/M031G Series

IDIO[*4]

-

3.5

-

2.77

I/O dynamic current consumption

CL = 10 pF, VDD >= 2.7 V
CL = 30 pF, VDD = 3.3 V,
mA

-

1.19

f(IO)out = 24 MHz
CL = 10 pF, VDD = 3.3 V,f(IO)out = 24 MHz

Note:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
3. The I/O dynamic current consumption is defined by 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷 × 𝑓𝑓𝐼𝐼𝐼𝐼 × (𝐶𝐶𝐼𝐼𝐼𝐼 + 𝐶𝐶𝐿𝐿 )Table 8.4-4 I/O AC Characteristics

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

Page 100 of 120

Rev 1.02

M029G/M030G/M031G Series
8.5

Analog Characteristics

8.5.1

Reset and Power Control Block Characteristics

The parameters in below table are derived from tests performed under ambient temperature.
SymbolParameter

Min

Typ

Max

Unit

IPOR[*1]

POR operating current

-

20

30

µA

ILVR[*1]

LVR operating current

-

2

3.6

AVDD = 3.6V

IBOD[*1]

BOD operating current

-

3

5.5

AVDD = 3.6V

VPOR

POR reset voltage

2

2.2

2.4

VLVR

LVR reset voltage

2.16

2.3

2.44

-

VBOD

BOD brown-out detect voltage

2.35

2.5

2.65

BODVL = 0

2.54

2.7

2.86

BODVL = 1

V

Test Conditions
AVDD = 3.6V-

TLVR_SU[*1]

LVR startup time

-

140

240

TLVR_RE[*1]

LVR respond time

-

9

12

-

TBOD_SU[*1]

BOD startup time

-

1000

1740

-

TBOD_RE[*1]

BOD respond time

-

100

165

-

RVDDR[*1]

VDD rise time rate

10

-

-

µs

µs/V

-

POR/LVR/BOD
Enabled(BODVL=0)

RVDDF

[*1]

VDD fall time rate--

POR Enabled

80

-

-

LVR Enabled

470

-

-

BOD 2.5V Enabled

305

-

-

BOD 2.7V Enabled

Note:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.

Table 8.5-1 Reset and Power Control Unit

Mar. 31, 2023

Page 101 of 120

Rev 1.02

M029G/M030G/M031G SERIES DATASHEET

10M029G/M030G/M031G Series

VDD

RVDDF

RVDDR
VBOD
VLVR
VPOR

Time
Figure 8.5-1 Power Ramp Up/Down Condition

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

Page 102 of 120

Rev 1.02

M029G/M030G/M031G Series
8.5.2

12-bit SAR ADC

SymbolParameter

Min

Typ

Max

Unit

Test Conditions

TA

Temperature

-40

-

125

°C

AVDD

Analog operating voltage

2.7

-

3.6

V

VREF

Reference voltage

2.048

-

AVDD

V

VIN

ADC channel input voltage

0

-

VREF

V

VCM

Common-Mode Input Range

VREF/2

V

Full differential input

IADC[*1]

Operating current (AVDD + VREF current) at
2 MSPS

550µA

AVDD = VDD = VREF = 3.3 V

NR

Resolution

12

Bit

VDD = AVDDADC Clock frequency (M029G/M030G)

4

-

24

MHz

1/TADCADC Clock frequency (M031G)

4

-

34

MHz

TSMP

Sampling Time

1

-

256

TSMP =
1/FADC (EXTSMPT(ADC_ESMPCTL[7:0])+ 1 ) * TADC

TCONVConversion time

17

-

272

1/FADC TCONV = TSMP + 16 * TADC

Sampling Rate (M029G/M030G)

-

-

1.4

MSPS FSPS = FADC / TCONV

Sampling Rate (M031G)

-

-

2

EXTSMPT(ADC_ESMPCTL[7:0])
MSPS = 0

Integral Non-Linearity Error

-2

-

2

LSB

VREF = AVDD

DNL

Differential Non-Linearity Error

-1

-

2

LSB

VREF = AVDD

EG[*1]

Gain error

-4

0.5

4

LSB

VREF = AVDD

EO[*1]T

Offset error

-4

0.5

4

LSB

VREF = AVDD

EA[*1]

Absolute Error

-4

0.5

4

LSB

VREF = AVDDENOB_1.4M[*1] Effective number of bits at 1.4 MSPS

-

9.3

-

bits

FADC = 24 MHz

SNR_1.4M[*1]

-

58

dB

Input Frequency = 10 kHz

FSPS[*1]

INL[*1][*1]

Signal-to-noise ratio at 1.4 MSPSAVDD = VDD = VREF = 3.6 V

THD_1.4M[*1]Total harmonic distortion at 1.4 MSPS

-

-77

-

ENOB_2M[*1]Effective number of bits at 2 MSPS

-

9.3

-

SNR_2M[*1]Signal-to-noise ratio at 2 MSPS

-

58

-

THD_2M[*1]Total harmonic distortion at 2 MSPS

-

-71

-

CIN[*1]

Internal Capacitance

-

2.9

-

pF

RIN[*1]

Internal Switch Resistance

-

0.95

2

kΩ

REX[*1]

External input impedance

-

-

50

kΩ

Mar. 31, 2023

TA = 25 °C
bits

AVDD = VDD = VREF = 3.6 V
dB

Page 103 of 120

FADC = 34 MHz
Input Frequency = 10 kHz
TA = 25 °C

Rev 1.02

M029G/M030G/M031G SERIES DATASHEETFADC[*1]

M029G/M030G/M031G Series
SymbolParameter

Min

Typ

Max

Unit

Test Conditions

Note:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad andis combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
𝑅𝑅𝐸𝐸𝐸𝐸 =𝑘𝑘− 𝑅𝑅𝐼𝐼𝐼𝐼
𝑓𝑓𝐴𝐴𝐴𝐴𝐴𝐴 × 𝐶𝐶𝐼𝐼𝐼𝐼 × ln(2𝑁𝑁+2 )

VDD

REX
VEX

EADC_CHx

RIN

12-bitConverter

CIN

CEX

M029G/M030G/M031G SERIES DATASHEET

Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.

Mar. 31, 2023

Page 104 of 120

Rev 1.02

M029G/M030G/M031G Series
EF (Full scale error) = EO + EG
Gain Error
EG

Offset Error
EO

4095
4094
4093
4092

Ideal transfer curve

7
6ADC
outputcode

5

Actual transfer curve

4
3
2

DNL

1

1 LSB

4095

Analog input voltage(LSB)

Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset andgain error from the actual transfer curve.

8.5.3

Digital to Analog Converter (DAC)

The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values
for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
SymbolParameter

AVDD

Analog supply voltage

NR

Resolution

VREF

Reference supply voltage

DNL[*2]Differential non-linearity error

INL[*2]Integral non-linearity error

OE[*2]

GE[*2]

Min

Typ

Max

Unit

2.7

3.3

3.6

V

12

bit

-

AVDD

V

VREF ≤ AVDD

±1

±3

LSB

12-bit mode

-

±2

±5

LSB

12-bit mode

-

-

±10

LSB

-

-

±5

LSB

-

-

±10

LSB

2.048

Offset Error

Gain Error

Mar. 31, 2023

Test Condition

Page 105 of 120

12-bit mode
DACOUT buffer ON
12-bit mode
DACOUT buffer OFF
12-bit mode
DACOUT buffer ON

Rev 1.02

M029G/M030G/M031G SERIES DATASHEET

Offset Error
EO

M029G/M030G/M031G SeriesAE[*2]

-

-

±5

LSB

-

-

±10

LSB

-

-

±4

LSB

Absolute Error-

Monotonic

VO[*1]

10-bit guaranteed12-bit mode
DACOUT buffer OFF
12-bit mode
DACOUT buffer ON
12-bit mode
DACOUT buffer OFF

-

-

0.2

-

AVDD 0.2

V

DACOUT buffer ON

1*LSB

-

VREF1*LSBVDACOUT buffer OFF

5

-

kΩ

DACOUT buffer ON

-

8

20

kΩ

DACOUT buffer OFF

-

-

20

pF

DACOUT buffer OFF

-

-

50

pF

DACOUT buffer ON

Output Voltage

RLOAD[*2] [*3] Resistive load
RO[*2]

Output impedance

CLOAD[*2] [*4] Capacitive load

AVDD = 3.6V, no load, DACOUTIDAC_AVDD[*2] DAC operating current on AVDD supply

-

250

360

µA

buffer ON, lowest code (0x000)
AVDD = 3.6V, no load, DACOUT
buffer ON, middle code (0x800)

IDAC_VREF[*2] DAC operating current on VREF supply

-

-

200

µA

VREF =2.5V, no load, worst case code
(0x800)

M029G/M030G/M031G SERIES DATASHEETTB[*2]

Settling Time

-

5

6

μS

Full scale: for a 12-bit input codetransition between the lowest and thehighest input codes when DAC_OUT
reaches final value +/-1 LSB,
CLOAD ≤ 50pF, RLOAD ≥ 5kΩ, Buffer
ON, VREF = 2.5V

FS

Update Rate

-

1

-

MSPS

Max. frequency for a correct
DAC_OUT change from core i to
i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 5kΩ

-

-60

-40

dB

No RLOAD, CLOAD = 50pF

PSRR[*1] Power Supply Rejection Ratio
Note:
1.
2.
3.
4.

8.5.4

Guaranteed by design, not tested in production
Guaranteed by characteristic, not tested in production.
Resistive load between DACOUT and AVSS.
Capacitive load at DACOUT pin.

Internal Voltage Reference for M029G/M030G

The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and thetypical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
VREF_INT

Ts[*1]

Parameter

Min

Typ

Max

2.017

2.048

2.079
V

Internal reference voltage
2.463

2.5

2.538

-

-

2

Stable timeMar. 31, 2023

Unit

Page 106 of 120

Test Conditions
AVDD >= 2.7 V
AVDD >= 2.7 V

CL =4.7 uF, VREF initial=0, Preload ismS enabled.

Rev 1.02

M029G/M030G/M031G Series
-

-

15

CL =4.7 uF, VREF initial=3.6, Preload ismS enabled.

-

-

480

CL =1 uF, VREF initial=0, Preload isµS enabled.

-

-

3000

CL =1 uF, VREF initial=3.6, Preload isµS enabled.

IREF_INT[*1]

VREF_INT operating current

-

160

220

µA

IREF_LOAD

VREF_INT output loading current

-

-

1.5

mA

Note:

1. Guaranteed by characterization, not tested in production

VREF
1uF

Note: VREF_INT is only supported while package includes VREF pin with external capacitor.

Mar. 31, 2023

Page 107 of 120

M029G/M030G/M031G SERIES DATASHEET

Figure 8.5-2 Typical connection with internal voltage reference

Rev 1.02

M029G/M030G/M031G Series
8.5.5

Internal Voltage Reference for M031G

The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and thetypical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
VREF_INT

Ts[*1]

Parameter

Min

Typ

Max

2.017

2.048

2.079

Unit
V

Internal reference voltage

Stable time

Test Conditions
AVDD >= 2.7 V

2.463

2.5

2.538

-

-

2

CL =4.7 uF, VREF initial=0, Preload ismS enabled.

-

-

15

CL =4.7 uF, VREF initial=3.6, Preload ismS enabled.

-

-

900

CL =2.2 uF, VREF initial=0, Preload isµS enabled.

-

-

6000

CL =2.2 uF, VREF initial=3.6, Preload isµS enabled.

AVDD >= 2.7 V

IREF_INT[*1]

VREF_INT operating current

-

300

360

µA

IREF_LOAD

VREF_INT output loading current

-

-

3

mA

Note:

1. Guaranteed by characterization, not tested in production

M029G/M030G/M031G SERIES DATASHEET

VREF
2.2uF

Note: VREF_INT is only supported while package includes VREF pin with external capacitor.

Figure 8.5-3 Typical connection with internal voltage reference

8.5.6

Temperature Sensor

The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and thetypical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol

Min

Typ

Max

Unit

AVDD

Analog supply voltage

Parameter

2.7

3.3

3.6

V

TA

Temperature

-40

-

105

°C

ITEMP

Temperature Sensor operating
current

-

200

-

µA

-1.6

-

+1.6

°C

-2

-

+2

°C

TTEMP_ERR[*1] Internal Temperature Deviation

Mar. 31, 2023

Page 108 of 120

Test Conditions

T = 0 °C to 70 °C
VDD = 3.3 V
T = -40 °C to 105 °C

Rev 1.02

M029G/M030G/M031G Series
VDD = 2.7 V to 3.6 V
TR

Temperature Resolution-

0.0625

-

°C

TCONV

Conversion Time

-

84

100

ms

Note:

1. Guaranteed by characterization, not tested in production

M029G/M030G/M031G SERIES DATASHEETMar. 31, 2023

Page 109 of 120

Rev 1.02

M029G/M030G/M031G Series
8.6

Communications Characteristics

8.6.1

SPI Dynamic Characteristics
Specificaitons[*1]SymbolFSPICLK
1/ TSPICLK

Test Conditions

Parameter

SPI clock frequency

Min

Typ

Max

Unit

-

-

24

MHz

tCLKH

Clock output High time

TSPICLK / 2

ns

tCLKL

Clock output Low time

TSPICLK / 2

ns

tDS

Data input setup time

2

-

-

ns

tDH

Data input hold time

4

-

-

ns

tV

Data output valid time

-

-

5

ns

2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF

2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF

Note:

1.

Guaranteed by design.

Table 8.6-1 SPI Master Mode Characteristics

tCLKH

tCLKL

CLKP=0SPICLK

M029G/M030G/M031G SERIES DATASHEETCLKP=1tV
MOSI

Data Valid

Data Valid

tDS
MISO

Data Valid

CLKP=0, TX_NEG=1, RX_NEG=0or
CLKP=1, TX_NEG=0, RX_NEG=1tDH
Data ValidtV
Data Valid

MOSI
tDS
MISO

Data Valid
CLKP=0, TX_NEG=0, RX_NEG=1or
CLKP=1, TX_NEG=1, RX_NEG=0tDH
Data Valid

Data Valid

Figure 8.6-1 SPI Master Mode Timing Diagram

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M029G/M030G/M031G SeriesSpecificaitons[*1]SymbolFSPICLK
1/ TSPICLK

Test Conditions

Parameter

SPI clock frequency

Min

Typ

Max

Unit

-

-

16

MHz

2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF

2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF

tCLKH

Clock output High time

TSPICLK / 2tCLKLClock output Low time

TSPICLK / 2

tSS

Slave select setup time

1
TSPICLK
+ 2ns

-

-

ns

tSH

Slave select hold time

1
TSPICLK

-

-

ns

tDS

Data input setup time

1.5

-

-

ns

tDH

Data input hold time

3.5

-

-

ns

tV

Data output valid time

-

-

17.5

ns

2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF

Note:

1.

Guaranteed by design.

Table 8.6-2 SPI Slave Mode Characteristics

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M029G/M030G/M031G Series

SSACTPOL=1tSS

SPI SStSH

SSACTPOL=0tCLKH

CLKPOL=0
TXNEG=1
RXNEG=0tCLKL

SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1

tV

SPI data output(SPI_MISO)

Data Valid

Data ValidtDS
SPI data input(SPI_MOSI)

Data Valid

SSACTPOL=1

tDH
Data ValidtSS

SPI SStSH

SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1

tCLKH

tCLKL

SPI Clock

M029G/M030G/M031G SERIES DATASHEETCLKPOL=1
TXNEG=1
RXNEG=0tV

SPI data output(SPI_MISO)

Data ValidtDS
SPI data input(SPI_MOSI)

Data ValidtDH
Data Valid

Data Valid

Figure 8.6-2 SPI Slave Mode Timing Diagram

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M029G/M030G/M031G Series
I2C Dynamic Characteristics

8.6.2
SymbolParameter

Standard Mode[1][2]Fast Mode[1][2]

Min

Max

Min

Max

Unit

tLOW

SCL low period

4.7

-

1.3

-

µs

tHIGH

SCL high period

4

-

0.6

-

µs

tSU; STA

Repeated START condition setup time

4.7

-

0.6

-

µs

tHD; STASTART condition hold time

4

-

0.6

-

µs

tSU; STOSTOP condition setup time

4

-

0.6

-

µs

tBUF

Bus free time

4.7[3]-

1.2[3]-µstSU;DAT

Data setup time

250

-

100

-

ns

tHD;DAT

Data hold time0[4]3.45[5]0[4]0.8[5]µstr

SCL/SDA rise time

-

1000

20+0.1Cb

300

ns

tf

SCL/SDA fall time

-

300

-

300

ns

Cb

Capacitive load for each bus line

-

400

-

400

pF

Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.

5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.

Table 8.6-3 I2C Characteristics
S TOP

Re pe a te dS TARTS TART

S TOP

S DA
tBUF
tLOW
tr

tf

S CL
tHIGH
tHD;S TAtHD;DATtS U;DATtS U;S TAtS U;S TO

Figure 8.6-3 I2C Timing Diagram

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M029G/M030G/M031G SERIES DATASHEET

3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.

M029G/M030G/M031G Series
8.7

Flash DC Electrical Characteristics

The devices are shipped to customers with the Flash memory erased.
Symbol

Min

Typ

Max

Unit

Supply voltage

1.62

1.8

1.98

V

TERASE

Page erase time

-

20

-

ms

TPROG

Program time

-

60

-

µs

IDD1

Read current

-

7

-

mA

IDD2

Program current

-

8

-

mA

IDD3

Erase current

-

12

-

mA

NENDUR

Endurance

20,000

-

10

-

2

-

VFLA[1]

Parameter

Test Condition

TA = 25°C

TRET

cycles[2]TJ = -40°C~125°C

-

year

20 kcycle[3] TJ = 85°C

-

year

20 kcycle[3] TJ = 105°C

Data retention

Note:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.

Table 8.7-1 Flash DC Electrical Characteristics

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M029G/M030G/M031G Series
9

PACKAGE DIMENSIONS

Package is Halogen-free, RoHS-compliant and TSCA-compliant.

9.1 QFN 24L (3x3x0.9 mm Pitch:0.40 mm)

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M029G/M030G/M031G Series
9.2 QFN 33L (4x4x0.8 mm Pitch:0.40 mm)

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M029G/M030G/M031G Series
10 ABBREVIATIONS
10.1 Abbreviations
Description

ACMP

Analog Comparator Controller

ADC

Analog-to-Digital Converter

AES

Advanced Encryption Standard

APB

Advanced Peripheral Bus

AHB

Advanced High-Performance Bus

BOD

Brown-out Detection

CAN

Controller Area Network

DAP

Debug Access Port

DES

Data Encryption Standard

EADC

Enhanced Analog-to-Digital Converter

EBI

External Bus Interface

EMAC

Ethernet MAC Controller

EPWM

Enhanced Pulse Width Modulation

FIFOFirst In, First Out

FMC

Flash Memory Controller

FPU

Floating-point Unit

GPIO

General-Purpose Input/Output

HCLK

The Clock of Advanced High-Performance Bus

HIRC

12 MHz Internal High Speed RC Oscillator

HXT

4~32 MHz External High Speed Crystal Oscillator

IAP

In Application Programming

ICP

In Circuit Programming

ISP

In System ProgrammingLDO

Low Dropout Regulator

LIN

Local Interconnect Network

LIRC

10 kHz internal low speed RC oscillator (LIRC)

MPU

Memory Protection Unit

NVIC

Nested Vectored Interrupt Controller

PCLK

The Clock of Advanced Peripheral Bus

PDMA

Peripheral Direct Memory Access

PLL

Phase-Locked Loop

PWM

Pulse Width Modulation

Mar. 31, 2023

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M029G/M030G/M031G SERIES DATASHEET

Acronym

Rev 1.02

M029G/M030G/M031G Series
QEI

Quadrature Encoder Interface

SD

Secure Digital

SPI

Serial Peripheral Interface

SPS

Samples per Second

TDES

Triple Data Encryption Standard

TK

Touch Key

TMR

Timer Controller

UART

Universal Asynchronous Receiver/Transmitter

UCID

Unique Customer ID

USB

Universal Serial Bus

WDT

Watchdog Timer

WWDTWindow Watchdog Timer

Table 10.1-1 List of Abbreviations

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M029G/M030G/M031G Series
11 REVISION HISTORY
Date

Revision

Description

2021.05.31

1.00

 Initial version.
 Added M029G series.
 Added built-in I2C bootloader information in chapter 1 and section
2.1 and 6.13.2.
 Added ADC 2 MSPS sampling rate in chapter 1 and section 2.1,
6.17.2 and 8.5.2.

2022.10.24

1.01

 Updated thermal resistance junction-ambient (θJA) value in section
8.1.3.
 Updated ADC characteristics in section 8.5.2.
 Changed the ADC note about using the internal channel for bandgap voltage in section 6.17.2.
 Added “Package is Halogen-free, RoHS-compliant and TSCAcompliant.” in chapter 3 and chapter 9.

2023.03.31

1.0.2



Updated IDD_PD value in Table 8.3-3.

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M029G/M030G/M031G Series

M029G/M030G/M031G SERIES DATASHEET

Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all typesof safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims
to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages
and liabilities thus incurred by Nuvoton.

Mar. 31, 2023

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