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IR LayerRelease™
Technology

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IR LayerRelease™ Technology
Wafer bonding and LayerRelease is the new lithography scaling
Introduction

Key Aspects

In semiconductor manufacturing, 3D integration – the manufacturing, vertical assemblyand packaging of multiple different dies into a single package – is increasingly importantin optimizing the Power, Performance, Area and Cost (PPAC) metric in semiconductor
design and manufacturing, as well as enabling roadmap continuation. At the same time,wafer bonding is a critical enabler for 3D integration. One can even argue that wafer
bonding is the new lithography scaling, because without temporary and permanent wafer
bonding one cannot vertically stack components and dies.

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In the past, 3D integration was driven primarily from a packaging perspective. In otherwords, different dies on interposers or fan-out wafers were connected to each other, withconsiderable performance increases. However, the dies were designed and manufactured
as classically 2D system on chip. Despite enormous efforts and successes in the area oflithography and transistor node reduction, performance increase has increasingly slowed
down and requires a rethink in the manufacture and design of future processors andmemories. Above all, there is no way around 3D integration and wafer bonding or layertransfer.

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Through-silicon IR laser
eliminates glass carriers
Ultra-thin film or layer releasewith nanometer precision
Fusion and hybrid bonding
compatible
Application independent –from FEOL to BEOL
Enabling next-generation
device architectures
First front-end compatible
debonding technology

Moving Beyond Glass Carriers
Carrier technologies utilizing glass substrates, coupled with organic adhesives and wafer bonding processes, have become anestablished method for building up device layers in 3D devices. The device wafer is temporarily bonded onto the glass carrier wafer
using the organic adhesive, where it is then thinned on the backside. Next, an ultraviolet (UV) wavelength laser is used to dissolve theadhesives and release the device layer, which is subsequently permanently bonded onto the final product wafer.
However, glass substrates are difficult to process with semiconductor fab equipment that have been designed primarily around silicon,
and that require costly upgrades to enable glass wafer processing. Simple things such as wafer edge detection and pre-aligners
can be upgraded to make established equipment carrier compatible. More fundamental issues with glass carriers are their electricaland thermal isolation properties, which demand new recipes for deposition or the deposition of extra layers on the wafer back side
to allow electrostatic chucking in deposition and etch equipment. In addition, organic adhesives are generally limited to processing
temperatures below 300°C, which limits their use to back-end processing.
EVG40NT2

EVG LayerRelease

EVG GEMINI FB XTEVG BONDSCALE

W2W, D2W and D2DOverlay Metrology fororganic and inorganic
Dies and wafers

Selective and full area
IR Laser releasethrough siliconHybrid Bonding oftwo FEOL
metallization circuits<100nm overlay

Combination ofwafer-to-wafer bonding
and EUV or Immersion
lithography

EVG320D2W
D2W Fusion and Hybrid
Bonding using CoD2W or
DPD2W flows

and packaging technolo3D IC Integration
gies in 2.5D and 3D

EVG Lithoscale
Fully digital maskless
Lithography for Adaptive
patterning, Rapid prototyping& fully traceable chiplets

Scaling, Device Scaling,Scaling Dimensional
Layout Scaling

EVG850 TB/DB

2D-SOC„Chiplet“ Partitioning

Temporary Bonding &Debonding for next FoWLP,
2.5D and 3Dprocesses

STCO System Technology Co Optimization
Figure 1: Key industry drivers for improved system performance by scaling, 3D Integration and System Technology Co Optimization.

IR LayerRelease™ Technology
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In a perfect world, fabs could utilize silicon carriers with inorganic release layers to avoid these temperature and glass carriercompatibility issues. Recently, a revolutionary layer transfer approach was introduced that eliminates the need for glass substrates foradvanced packaging. This avoids both temperature and glass carrier compatibility issues, and enables the ability to transfer ultra-thin(single micron and below) layers via carriers in front-end processing without changing the processes of record.

Revolutionary Infrared Laser Release Technology
This new layer release technology for silicon, called LayerRelease™, utilizes an infrared (IR) laser and specially formulated inorganic
release materials to enable laser debonding on silicon with nanometer precision. The backside of the silicon wafer is exposed with
the IR laser, which operates at a unique wavelength that silicon is transparent to. An inorganic release layer that is pre-built into thesilicon stack through standard deposition processes absorbs the IR light, resulting in the separation of the silicon at a predeterminedand precisely defined layer or area.
Utilizing inorganic release layers enables more precise and thinner release layers to be used in the range of a few nanometers versus
a few microns for organic adhesives. Subsequent stacking of such thin device layers enables higher bandwidth interconnects, andopens new opportunities to design and segment dies for next-generation high-performance systems. In addition, the inorganic releaselayers are compatible with high-temperature processing (up to 1000°C), enabling layer transfer for many new front-end applications,such as epitaxy, deposition and annealing, where organic adhesives are incompatible.
The nanometer-precision of the LayerRelease process supports advanced semiconductor device roadmaps calling for thinner device
layers and packages, increased 3D integration, and reduced processing costs through thin-layer transfer and the elimination of glass
substrates. At the same time, LayerRelease’s compatibility with high-temperature processes enables hybrid and fusion bonding evenof ultra-thin layers on silicon carriers, which in turn enables completely novel process flows for 3D IC and 3D sequential integration
applications.
For interposers, several improvements in integration and patterning density are on the industry roadmap for leading-edge applications
below 500nm line/space patterning resolution. Furthermore, integrated passive devices require high process temperatures for dielectric
deposition and etching of more than 300°C. This is generally unsuitable for adhesive-based carrier systems since the processing
temperatures of most thermoplastic and thermoset materials are limited to 270°C.
In addition, for Fan-out Wafer-level Packaging (FO-WLP), glass carriers are now standard and meet many requirements of today’s
packages and interconnect densities down to about 2µm linewidths. However, new concepts are needed to take FO-WLP further withlinewidths well below 1µm. This is very easy to realize with silicon carriers and IR debond, and allows seamless integration of copperand dual damascene.

Die-to-Wafer Hybrid Bonding
d D2WEnabling
Bonding
Reconstructed wafers circumvent the restriction of wafer-to-wafer (W2W) bonding by allowing tested good dies to be placed on acarrier substrate and then filling the gap between dies with a dielectric oxide filling process. In this way, a continuous wafer with oxidesurface serves as a base for further process steps. The following figure describes the process flow in detail.

Silicon carrier withIR release layers

EVG LayerRelease
IR Laser Release

ngWndrFigure 2: Reconstructed D2W integration combining die placement and processing and reconstruction of ultra-thin chiplets with high bandwidth W2W hybrid bonding

IR LayerRelease™ Technology
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One of the main reasons for this process flow is to eliminate traditional packaging materials and replace them with fab-clean andfab-standard materials. This shifts the standard packaging process from back-end-of-line processing to the fab front-end whereinterconnects are being processed. As a result, more and thinner layers of interconnects in chip processing can be achieved than everbefore.
LayerRelease is perfectly suited for enabling silicon as a starting carrier due to the following reasons:• It provides for a fusion bondable surface to attach chips top side up or bottom side down for mechanical attachment• It provides high-temperature capability for all standard fabrication processes at process temperatures of 450°C and higher• It combines with W2W hybrid bonding to enable layer transfer and uniform stacking of multiple thin wafers, enabling high bandwidthinterconnects• It enables the delamination of ultra-thin films in the sub µm range

Ultra-thin Layer Transfer and Stacking Using “Temporary” Fusion Bonding
Another significant application of LayerRelease is the combination of IR laser release technology with fusion bonding, which enables
fusion bonding to carriers and then area-selective detachment after processing. The IR laser release technology is based on front-end
compatible and available materials and deposition processes. This means that there are no limitations in process temperature, that therelease of the product wafer can be conducted without any adaptive process, and that integration flows do not need to be adapted
and requalified due to new materials in the line. Another key advantage of using inorganic release layers is their high film uniformity
in combination with fusion bonding. As the materials are highly uniform over the wafer and do not alter their properties during
processing, the LayerRelease carrier system enables a tremendous reduction in device thickness to sub-micron without damage
resulting from the carrier process.
Especially in hybrid bonded memory applications, such as SRAM or DRAM, carrier systems have a crucial role in wafer stacking.
To stack the same wafer layouts, without mirroring one of the devices, face-to-back stacking is needed where one device wafer ismounted, thinned and backside processed on a carrier used for hybrid bonding (Figure 3). By freeing any temperature restrictions andenabling ultra-thin silicon processing, through silicon vias of 50µm depth can become through silicon contacts of only a few microns,resulting in improved thermal, electrical, and better cost performance. As a result, LayerRelease carriers are a key enabler for using
IR LaserF2B wafers.
Hybrid Bonding
hybridbonding Releaseon ultra-thin|device

Si carrier

F2B Layer
Stacking

Si carrier

Si carrier

Silicon Release Carrier
deposition (including platinglayers, bonding layers andalignment marks)

Si carrier

Face Down Bonding to IR
release carrier wafer

Si carrier

Wafer thinning, TSV
etching, hybrid bond padpatterining, CMP

Base + 1 Stacking:
W2W Bonding andsubsequent IR Laser
Release (EVG Gemini FB &EVG LayerRelease)

Base + 2 Stacking:
W2W Bonding andsubsequent IR Laser
Release (EVG Gemini FB &EVG LayerRelease)

Figure 3: Face to back stacking of ultra-thin wafers on front-end compatible silicon carriers enabled by the LayerRelease process

Conclusion
Wafer bonding and layer transfer are critical enablers to 3D integration. Glass carriers and inorganic adhesives have traditionally been
21
Confidentialroadmap scaling requires a new approach to layer transfer
used for building up layers in 3D devices. However, continued
technology.
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A novel and universal IR release technology through silicon wafers, called LayerRelease, has been developed that provides precisely
controlled separation without IR transmission or risk to the device layer. The use of inorganic IR release layers enables nanometer200 µm
precision separation of layers and higher processing temperatures, thereby supporting front-end processing and enabling die andwafer processing with thicknesses even below 1 micron for improved PPAC. The LayerRelease technology is demo ready at EV
Group’s Heterogeneous Integration Competence Center™ (HICC) – the company’s innovation incubator for heterogeneous device
integration – located at its headquarters in Austria. Beyond today’s application, wafer bonding and LayerRelease can play a key role inupcoming device developments by providing a boost to lithography scaling for 3D sequential and even new transistor designs, suchas complementary FET (CFET). Further research into this is being investigated.
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Acknowledgement
Content in this white paper originally appeared in an article published in the 3DInCites Yearbook, Vol. 5, 2023, which can be found here:
https://media.3dincites.com/view/726845277/36-37/

IR LayerRelease™ Technology
EV Group - DI Erich Thallner Strasse 1 - 4782 St. Florian am Inn - Austria - Contact@EVGroup.com

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