HB206/D
Rev. 4, Feb-2002

Linear & Switching Voltage
Regulator Handbook
ON Semiconductor

ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application bycustomer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any otherapplication in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC
products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of
the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATIONGLOBAL Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center
4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031
Phone: 81-3-5740-2700
Email: r14525@onsemi.com

N. American Technical Support: 800-282-9855 Toll Free USA/Canada

For additional information, please contact your local Sales
Representative

ON Semiconductor Website: http://onsemi.com

HB206/DLinear & Switching Voltage Regulator Handbook

HB206/DRev. 4, Feb–2002

 SCILLC, 2002
Previous Edition  1989
“All Rights Reserved”

SWITCHMODE, POWERTAP and TMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).

All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

http://onsemi.com
2

Linear & Switching Voltage Regulator
Applications Information

In Brief . . .
PageIn most electronic systems, voltage regulation is requiredfor various functions. Today’s complex electronic systems are
requiring greater regulating performance, higher efficiency
and lower parts count. Present integrated circuit and power
package technology has produced IC voltage regulators
which can ease the task of regulated power supply design,
provide the performance required and remain cost effective.
Available in a growing variety, ON Semiconductor offers awide range of regulator products from fixed and adjustable
voltage types to special–function and switching regulator
control ICs.
This handbook describes ON Semiconductor’s voltage
regulator products and provides information on applying
these products. Basic Linear regulator theory and switchingregulator topologies have been included along with practicaldesign examples. Other relevant topics include trade–offs ofLinear versus switching regulators, series pass elements for
Linear regulators, switching regulator component design
considerations, heatsinking, construction and layout, power
supply supervision and protection, and reliability.

Basic Linear Regulator Theory . . . . . . . . . . . . . . . . . . . 6
Selecting a Linear IC Voltage Regulator . . . . . . . . . . . 15
Linear Regulator Circuit Configuration
and Design Considerations . . . . . . . . . . . . . . . . . . . . 18
Series Pass Element Considerations
for Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Linear Regulator Construction and Layout . . . . . . . . . 37
Linear Regulator Design Example . . . . . . . . . . . . . . . . 59
Linear Regulator Circuit Troubleshooting
Check List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Designing the Input Supply . . . . . . . . . . . . . . . . . . . . . . 63
An Introduction to Switching
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Switching Regulator Topologies . . . . . . . . . . . . . . . . . . 74
Switching Regulator Component
Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Basic Switching Power Supply
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Switching Regulator Design Examples . . . . . . . . . . . . 96
Power Supply Supervisory andProtection Considerations . . . . . . . . . . . . . . . . . . . . . 97
Heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

http://onsemi.com
3

TABLE OF CONTENTS
Section 1.

Basic Linear Regulator Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The “Regulator within a Regulator” Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page
6
6
6
10
13

Section 2.

Selecting a Linear IC Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting the Type of Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive versus Negative Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three–Terminal, Fixed Output Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three–Terminal, Adjustable Output Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting an IC Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15
15
15
15
17
17

Section 3.

Linear Regulator Circuit Configuration and Design Considerations . . . . . . . . . . . . . . . . . . . . . . .
Positive, Adjustable Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative, Adjustable Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive, Fixed Output Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative, Fixed Output Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18
18
22
22
25
27

Section 4.

Series Pass Element Considerations for Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series Pass Element Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series Pass Element Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Limiting Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constant Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Foldback Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Paralleling Series Pass Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29
29
30
31
31
34
36

Section 5.

Linear Regulator Construction and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Layout and Component Placement Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground Loops and Remote Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mounting Considerations for Power Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Insulation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fastener and Hardware Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal System Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A: Thermal Resistance Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix B: Measurement of Interface Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37
37
37
39
43
47
55
56
57

Section 6.

Linear Regulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC Regulator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Determination of Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Determination of Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection of Series Pass Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q1 Heatsink Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Construction Input Supply Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

59
59
59
59
60
60
61
61
61

Section 7.

Linear Regulator Circuit Troubleshooting Check List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

62

http://onsemi.com
4

TABLE OF CONTENTS (Continued)
Page
Section 8.

Designing the Input Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design of Capacitor–Input Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Surge Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

63
64
66
67
68

Section 9.

An Introduction to Switching Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison with Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69
69
70
72

Section 10.

Switching Regulator Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FET and Bipolar Drive Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Surge Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transformer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter Capacitor Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

74
74
76
77
79
79
81

Section 11.

Switching Regulator Component Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zener and Mosorb Transient Suppressors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

83
83
85
85

Section 12.

Basic Switching Power Supply Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flyback and Forward Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Push–Pull and Bridge Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Half and Full Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

88
88
91
94

Section 13.

Switching Regulator Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

96Section 14.

Power Supply Supervisory and Protection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Crowbar Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCR Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Sense and Drive Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC3425 Power Supply Supervisory Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC34064 and MC34164 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

97
97
98
99
103
105

Section 15.

Heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Thermal Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting a Heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commercial Heatsinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Heatsink Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heatsink Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Miniature IC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics of SOIC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOP–8 and SOP–16L Packaged Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics of DPAK and D2PAK Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

106
106
107
107
109
112
112
113
113
114

http://onsemi.com
5

SECTION 1
BASIC LINEAR REGULATOR THEORY
A. IC Voltage Regulator
The basic functional block diagram of an integrated circuit voltage regulator is shown in Figure 1–1.
It consists of a stable reference, whose output voltage is Vref, and a high gain error amplifier. The output
voltage (VO), is equal to or a multiple of Vref. The regulator will tend to keep VO constant by sensing any
changes in VO and trying to return it to its original value. Therefore, the ideal voltage regulator could beconsidered a voltage source with a constant output voltage. However, in practice the IC regulator is better
represented by the model shown in Figure 1–2.
In this figure, the regulator is modeled as a voltage source with a positive output impedance (ZO). The
value of the voltage source (V) is not constant; instead it varies with changes in supply voltage (VCC) andwith changes in IC junction temperature (TJ) induced by changes in ambient temperature and power
dissipation. Also, the regulator output voltage (VO) is affected by the voltage drop across ZO, caused by
the output current (IO). In the following text, the reference and amplifier sections will be described, and theircontributions to the changes in the output voltage analyzed.

B. Voltage Reference
Naturally, the major requirement for the reference is that it be stable; variations in supply voltage orjunction temperature should have little or no effect on the value of the reference voltage (Vref).

1. Zener Diode Reference
The simplest form of a voltage reference is shown in Figure 1–3a. It consists of a resistor and a zener
diode. The zener voltage (VZ) is used as the reference voltage. In order to determine VZ, consider Figure
1–3b. The zener diode (VR1) of Figure 1–3a has been replaced with its equivalent circuit model and thevalue of VZ is therefore given by (at a constant junction temperature):
VCC – VBZ
R + ZzVZ = VBZ + IZZZ = VBZ +where:ZZ(1)

VBZ = zener breakdown voltage
IZ = zener current
ZZ = zener impedance at IZ.

Note that changes in the supply voltage give rise to changes in the zener current, thereby changing thevalue of the reference voltage (VZ).

http://onsemi.com
6

Figure 1–1. Voltage Regulator Functional Block Diagram
VCC

Reference

Error
Amplifier

Vref

VO

+

Figure 1–2. Voltage Regulator Equivalent Circuit Model
VCC

ZO

IO
VO

V = f (VCC, Tj)

Figure 1–3. Zener Diode Reference
VCC
VCC
R
IZ

R

VZ
ZZ

VZ
VR1

VBZ

(a)

(b)

http://onsemi.com
7

2. Constant Current — Zener Reference
The effect of zener impedance can be minimized by driving the zener diode with a constant current asshown in Figure 1–4. The value of the zener current is largely independent of VCC and is given by:
IZ =

VBEQ1
RSC

(2)

where: VBEQ1 = base–emitter voltage of Q1.
This gives a reference voltage of:Vref = VZ + VBEQ1 = VBZ + IZZZ + VBEQ1(3)

where IZ is constant and given by Equation 2.
The reference voltage (about 7.0 V) of this configuration is therefore largely independent of supply voltage
variations. This configuration has the additional benefit of better temperature stability than that of a simple
resistor–zener reference.
Referring back to Figure 1–3a, it can be seen that the reference voltage temperature stability is equal
to that of the zener diode, VR1. The stability of zener diodes used in most integrated circuitry is about+ 2.2 mV/°C or  0.04%/°C (for a 6.2 V zener). If the junction temperature varies 100°C, the zener orreference voltage would vary 4%. A variation this large is usually unacceptable.
However, the circuit of Figure 1–4 does not have this drawback. Here the positive 2.2 mV/°C
temperature coefficient (TC) of the zener diode is offset by the negative 2.2 mV/°C TC of the VBE of Q1.
This results in a reference voltage with very stable temperature characteristics.

Figure 1–4. Constant Current (Zener Reference)
VCC

R
Q2

Vref
VZ

VR1
IZ

Q1
VBEQ1

RSC

http://onsemi.com
8

3. Bandgap Reference
Although very stable, the circuit of Figure 1–4 does have a disadvantage in that it requires a supply
voltage of 9.0 V or more. Another type of stable reference which requires only a few volts to operate wasdescribed by Widlar(1) and is shown in Figure 1–5. In this circuit Vref is given by:
Vref = VBEQ3 + I2R2
where:I2 =VBEQ1 – VBEQ2
R1(4)(neglecting base currents)

The change in Vref with junction temperature is given by:∆ Vref = ∆ VBE3 +∆VBEQ1 – ∆VBEQ2

R2

R1

(5)

It can be shown that,∆ VBEQ1 = ∆ TJK ln I1(6)and, ∆ VBEQ2 = ∆ TJK ln I2(7)where:

K = a constant∆ TJ = change in junction temperature

and,I1 > I2

Combining (5), (6), and (7)R2R1∆ Vref = ∆ VBEQ3 + ∆ TJK

ln

I1
I2

(8)

Since ∆ VBEQ3 is negative, and with I1 > I2, ln I1/I2 is positive, the net change in Vref with temperature
variations can be made to equal zero by appropriately selecting the values of I1, R1, and R2.
Figure 1–5. Bandgap Reference
VCC

Vref

I1

R3

R2

I2

Q3

VBEQ1

VBEQ3

Q2

Q1

VBEQ2

R1

http://onsemi.com
9C. The Error Amplifier
Given a stable reference, the error amplifier becomes the determining factor in integrated circuit
voltage regulator performance. Figure 1–6 shows a typical differential error amplifier in a voltage regulator
configuration. With a constant supply voltage (VCC) and junction temperature, the output voltage is
given by:
VO= AVOL υi – ZOL IO = AVOL {(Vref ± VIO) – VO β} – ZOL IO
where:(9)

AVOL = amplifier open loop gain
VIO = input offset voltage
ZOL = open loop output impedance
R1β== feedback ratio (β is always ≤1)
R1 + R2
IO = output current

υi= true differential input voltage
Manipulating Equation 9:
ZOL(Vref ± VIO) –
AVOL
VO =
1
β+
AVOL

IO
(10)

Note that if the amplifier open loop gain is infinite, this expression reduces to:VO =1(Vref ± VIO) = (Vref ± VIO)
β

1 

R2
R1

(11)

The output voltage can thus be set any value equal to or greater than (Vref ± VIO). Note also that if AVOL is not
infinite, with constant output current (a non–varying output load), the output voltage can still be“tweaked–in” by varying R1 and R2, even though VO will not exactly equal that given by Equation 11.
Assuming a stable reference and a finite value of AVOL, inaccuracy of the output voltage can be traced
to the following amplifier characteristics:

1. Amplifier Input Offset Voltage Drift
The input transistors of integrated circuit amplifiers are usually not perfectly matched. As in operational
amplifiers, this is expressed in terms of an input offset voltage (VIO). At a given temperature, this effect canbe nulled out of the desired output voltage by adjusting Vref or 1/β. However, VIO drifts with temperature,
typically ± 5.0 µV/°C to +15 µV/°C, causing a proportional change in the output voltage. Closer matching of
the internal amplifier input transistors minimizes this effect, as does selecting a feedback ratio (β) to beclose to unity.

2. Amplifier Power Supply Sensitivity
Changes in regulator output voltage due to power supply voltage variations can be attributed to two
amplifier performance parameters: power supply rejection ratio (PSRR) and common mode rejection ratio(CMRR). In modern integrated circuit regulator amplifiers, the utilization of constant current sources gives
such large values of PSRR that this effect on VO can usually be neglected. However, supply voltagechanges can affect the output voltage since these changes appear as common mode voltage changes, andthey are best measured by the CMRR.

http://onsemi.com
10Figure 1–6. Typical Voltage Regulator Configuration
VCC
(+)
+VIO

Vref

IO

ZOL

υi

VO
AVOLυi

(-)

R2

R1

The definition of common mode voltage (VCM), illustrated by Figure 1–7a, is:VCM where:(V–)
V1 2 V2 –  (V) 
2(12)

V1 = voltage on amplifier noninverting input
V2 = voltage on amplifier inverting input
V+ = positive supply voltage
V– = negative supply voltage

Figure 1–7. Definition of Common Mode Voltage Error
V+

V+
V1

+

V1

VCM

+

CMRR
VO

AVOLυi

υi

V2

V-

V2

V-

(a)

(b)
http://onsemi.com
11VOFigure 1–8. Common Mode Regulator Effects
VCC
(+)
VCM
Vref

CMRR

υi

VO
AVOLυi

(

)
R2

R1

In an ideal amplifier, only the differential input voltage (V1 – V2) has any effect on the output voltage; thevalue of VCM would not effect the output. In fact, VCM does influence the amplifier output voltage. This effectcan be modeled as an additional voltage offset at the amplifier input equal to VCM/CMRR as shown in
Figures 1–7b and 1–8. The latter figure is the same configuration as Figure 1–6, with amplifier input offset
voltage and output impedance deleted for clarity and common mode voltage effects added. The output
voltage of this configuration is given by:
VO= AVOL υi = AVOL
Manipulating,VO =where:and,VCM = Vref –VCM
Vref –
– VO
CMRR

VCM
Vref –
CMRR
β+

(13)

(14)

1
AVOL

VCC
2

(15)

CMRR = common mode rejection ratio

It can be seen from Equations (14) and (15) that the output can vary when VCC varies. This can be reduced
by designing the amplifier to have a high AVOL, a high CMRR, and by choosing the feedback ratio (β) to
be unity.

http://onsemi.com
12

3. Amplifier Output ImpedanceReferring back to Equation (9), it can be seen that the equivalent regulator output impedance (ZO) is
given by:
ZO =

ZOL
∆VO

∆IO
βAVOL

(16)

This impedance must be as low as possible, in order to minimize load current effects on the output voltage.
This can be accomplished by lowering ZOL, choosing an amplifier with high AVOL, and by selecting the
feedback ratio (β) to be unity.
A simple way of lowering the effective value of ZOL is to make an impedance transformation with anemitter follower, as shown in Figure 1–9. Given a change in output current (∆IO) the amplifier will see achange of only ∆IO/hFEQ1 in its output current (IO ). Therefore, (ZOL) in Equation (16) has been effectively
reduced to ZOL/hFEQ1, reducing the overall regulator output impedance (ZO).

D. The Regulator within a Regulator Approach
In the preceding text, we have analyzed the sections of an integrated circuit voltage regulator anddetermined how they contribute to its non–ideal performance characteristics. These are shown in Table
1–1 along with procedures which minimize their effects.
It can be seen that in all cases regulator performance can be improved by selecting AVOL as high as
possible and β = 1. Since a limit is soon approached in how much AVOL can be practically obtained in an
integrated circuit amplifier, selecting a feedback ratio (β) equal to unity is the only viable way of improving
total regulator performance, especially in reducing regulator output impedance. However, this method
presents a basic problem to the regulator designer. If the configuration of Figure 1–6 is used, the output
voltage cannot be adjusted to a value other than Vref. The solution is to utilize a different regulator
configuration known as the regulator within a regulator approach.(2) Its greatest benefit is in reducing total
regulator output impedance.
Figure 1–9. Emitter Follower Output
VCC

(+)
Vref

IO′

ZOL

Q1

IO
VO

(

)
R2

R1

http://onsemi.com
13

Table 1–1
VO Changes
Section

Effect Can Be
Induced By:

Minimized By Selecting:

VCC• Constant current–zener method• Bandgap reference

TJ• Bandgap reference• TC compensated zener method

VCC• High CMRR amplifier• High AVOL amplifier
•β=1

TJ

• Low VIO drift amplifier• High AVOL amplifier
•β=1

IO

• Low ZOL amplifier• High AVOL amplifier• Additional emitter follower output•β=1

Reference

AmplifierAs shown in Figure 1–10, amplifier A1 sets up a voltage (V1) given by:
V1  Vref

1 

R2
R1

(17)

V1 now serves as the reference voltage for amplifier A2, whose output voltage (VO) is given by:
VO  V1  Vref

1 

R2
R1

(18)

Note that the output impedance of A2, and therefore the regulator output impedance, has been minimized
by selecting A2’s feedback factor to be unity; and that output voltage can still be set at voltages greater thanVref by adjusting R1 and R2.
Figure 1–10. The “Regulator within a Regulator” Configuration

ZOL

Vref

A2

+
V1

VO

+

A1

R2

R1

(1)Widlar, R. J., New Developments in IC Voltage Regulators, IEEE Journal of Solid State Circuits, Feb.1971, Vol. SC–6, pgs. 2–7.
(2)Tom Fredericksen, IEEE Journal of Solid State Circuits, Vol. SC–3, Number 4, Dec. 1968, A Monolithic High Power Series Voltage Regulator.

http://onsemi.com
14

SECTION 2
SELECTING A LINEAR IC VOLTAGE REGULATOR
A. Selecting the Type of Regulator
There are five basic linear regulator types; positive, negative, fixed output, tracking and floating
regulators. Each has its own particular characteristics and best uses, and selection depends on thedesigner’s needs and trade–offs in performance and cost.

1. Positive Versus Negative Regulators
In most cases, a positive regulator is used to regulate positive voltages and a negative regulator
negative voltages. However, depending on the system’s grounding requirements, each regulator type may
be used to regulate the “opposite” voltage.
Figures 2–1a and 2–1b show the regulators used in the conventional and obvious mode. Note that the
ground reference for each (indicated by the heavy line) is continuous. Several positive regulators could
be used with the same input supply to deliver several voltages with common grounds; negative regulators
may be utilized in a similar manner.
If no other common supplies or system components operate off the input supply to the regulator, thecircuits of Figures 2–1c and 2–1d may be used to regulate positive voltages with a negative regulator andvice versa. In these configurations, the input supply is essentially floated, i.e., neither side of the input istied to the system ground.
There are methods of utilizing positive regulators to obtain negative output voltages without sacrificing
ground bus continuity. However, these methods are only possible at the expense of increased circuit
complexity and cost. An example of this technique is shown in Section 3.

2. Three–Terminal, Fixed Output Regulators
These regulators offer the designer a simple, inexpensive way to obtain a source of regulated voltage.
They are available in a variety of positive or negative output voltages and current ranges.
The advantages of these regulators are:a) Easy to use.
b) Internal overcurrent and thermal protection.
c) No circuit adjustments necessary.
d) Low cost.
Their disadvantages are:a) Output voltage cannot be precisely adjusted. (Methods for obtaining adjustable outputs are shownin Section 3).
b) Available only in certain output voltages and currents.
c) Obtaining greater current capability is more difficult than with other regulators. (Methods for
obtaining greater output currents are shown in Section 3.)

http://onsemi.com
15

Figure 2–1. Regulator Configurations+
Input
SupplyPositive
Regulator

Vin

+
VO

(a) Positive Output Using Positive Regulator

Input
Supply

+

+

Vin

VO
Negative
Regulator(b) Negative Output Using Negative Regulator

Input
Supply

+

+

Vin

VO
Negative
Regulator(c) Positive Output Using Negative Regulator+
Input
SupplyPositive
Regulator

+
VO

Vin

(d) Negative Output Using Positive Regulator

http://onsemi.com
16

3. Three–Terminal, Adjustable Output Regulators
Like the three–terminal fixed regulators, the three–terminal adjustable regulators are easy andinexpensive to use. These devices provide added flexibility with output voltage adjustable over a wide
range, from 1.2 V to nearly 40 V, by means of an external, two–resistor voltage divider. A variety of current
ranges from 100 mA to 3.0 A are available.

B. Selecting an IC Regulator
Once the type of regulator is decided upon, the next step is to choose a specific device. To provide
higher currents than are available from monolithic technologies, an IC regulator will often be used as adriver to a boost transistor. This complicates the selection and design task, as there are now several
overlapping solutions to many of the design problems.
Unfortunately, there is no exact step–by–step procedure that can be followed which will lead to theideal regulator and circuit configuration for a specific application. The regulating circuit that is finallyaccepted will be a compromise between such factors as performance, cost, size and complexity. Becauseof this, the following general design procedure is suggested:
1. Select the regulators which meet or exceed the requirements for line regulation, load regulation, TC of
the output voltage and operating ambient temperature range. At this point, do not be overly concerned withthe regulator capabilities in terms of output voltage, output current, SOA and special features.
2. Next, select application circuits from Section 3 which meet the requirements for output current, output
voltage, special features, etc. Preliminary designs using the chosen regulators and circuit configurations
are then possible. From these designs a judgement can be made by the designer as to which regulator
circuit configuration combination best meets his or her requirements in terms of cost, size and complexity.

http://onsemi.com
17

SECTION 3
LINEAR REGULATOR CIRCUIT CONFIGURATION
AND DESIGN CONSIDERATIONS
Once the IC regulators, which meet the designer’s performance requirements, have been selected,
the next step is to determine suitable circuit configurations. Initial designs are devised and compared todetermine the IC regulator/circuit configuration that best meets the designer’s requirements. In thissection, several circuit configurations and design equations are given for the various regulator ICs.
Additional circuit configurations can be found on the device data sheets. Organization is first by regulator
type and then by variants, such as current boost. Each circuit diagram has component values for aparticular voltage and current regulator design.
A. Positive, Adjustable
B. Negative, Adjustable
C. Positive, Fixed
D. Negative, Fixed
E. Tracking
F. Special
1. Obtaining Extended Output Voltage Range
2. Electronic Shutdown
G. General Design Considerations
It should be noted that all circuit configurations shown have constant current limiting. If foldback limiting
is desired, see Section 4C for techniques and design equations.

A. Positive, Adjustable Output IC Regulator Configurations
1. Basic Regulator Configurations
Positive Three–Terminal Adjustables
These adjustables, comprised of the LM317L, LM317, and LM350 series devices range in output
currents of 100 mA, 500 mA, 1.5 A, and 3.0 A respectively. All of these devices utilize the same basic circuit
configuration as shown in Figure 3–1A.
MC1723C
The basic circuit configurations for the MC1723C regulator are shown in Figures 3–2A and 3–3A. For
output voltages from  7.0 V to 37 V the configuration of Figure 3–2A can be used, while Figure 3–3A canbe used to obtain output voltages from 2.0 V to  7.0 V.

2. Output Current Boosting
If output currents greater than those available from the basic circuit configurations are desired, thecurrent boost circuits shown in this section can be used. The output currents which can be obtained withthis configurations are limited only by capabilities of the external pass element(s).

http://onsemi.com
18

Figure 3–1A. Basic Configuration for Positive, Adjustable Output
Three–Terminal Regulators
Vin

+ VO

Vout

LM317L
LM317
LM350

R1
240

IAdj

+C

Adjust

Cin
0.1µF

R2

O

1.0µF

CAdj
10µF

+

Cin: required if regulator is located an appreciable distance from power supply filter.
CO: improves transient response.
CAdj: improves Ripple Rejection.
R2+ IAdj R2
Vout = 1.25 V1 +R1Since IAdj is controlled to less than 100 µA, the error
associated with this term is negligible in most applications.

Figure 3–2A. MC1723C Basic Circuit Configuration for Vref ≤ VO ≤ 37 V
Vin
+ 20V

R3

12

10

11

2

6

3

VO

22Ω

+ 15V
ISC = 30 mA

MC1723C

5.1k
5

4
13

0.01µF

RSC

7

0.66 V; 10 kΩ < R1 + R2 < 100 kΩ
ISC

R3 ≅ R1 || R2 ; 0 ≤ Cref ≤ 0.1 µF
R2 =

Vref
VO

(R1 + R2) ≈7.0 V(R1 + R2)
VO

Values shown are for a 15 V, 30 mA regulator
using an MC1723CP for a TA(max) = 25°C.

http://onsemi.com
19

R1

10k

R2

100pF

Cref

RSC ≅

12k

Figure 3–3A. MC1723C Basic Circuit Configuration for 2.0 V ≤ VO ≤ Vref
Vin
+ 20V

12

10

11

2

7

RSC

VO

22Ω

+ 5.0VISC = 30 mA

3
MC1723C

5.1k
5

R1

3.6k

4

R3

13
Cref
0.01µF

13k

R2

1.0nF
7

0.66V
; 10 kΩ < R1 + R2 < 100 kΩ
ISC

RSC 
VO

R2 =

Vref

VO

(R1 + R2) 

7.0 V(R1 + R2)R3 = R1 || R2; 0 ≤ Cref ≤ 0.1 µF
Values shown are for a 5.0 V, 30 mA regulator using
an MC1723CP for a TA(max) = 70°C.

To obtain greater output currents with the MC1723C the configurations shown in Figures 3–4A and
3–5A can be used. Figure 3–4A uses an NPN external pass element, while a PNP is used in Figure 3–5A.
Figure 3–4A. MC1723C NPN Boost Configuration
Q1
+ Vin

2N3055or Equiv

12

+ 20V

11

10

RSC

VO

1.3Ω
1/2W

+ 15V
ISC = 0.5A

2
3
MC1723C

6

4

R3
5.1k

5

13

0.1µF

Cref

R2 =

12k

R2

10k

100pF

7

RSC ≅

R1

0.66 V; 10 kΩ < R1 + R2 < 100 kΩ
ISC

Vref
VO

(R1 + R2) ≅7.0 V(R1 + R2)VO

0 ≤ Cref ≤ 0.1 µF ; R3 ≅ R1 || R2
Selection of Q1 based on considerations of Section 4.
Values shown are for a 15 V, 500 mA regulator using an unheatsinked
MC1723CP and a 2N3055 on a 6°C/W heatsink for TA up to + 70°C.

http://onsemi.com
20

Figure 3–5A. MC1723C PNP Boost Configuration
2N3791or Equiv

Vin
+ 18V

R4
100

Q1
11

10

12

2

RSC

VO

0.91Ω
1/2W

+ 12V
ISC = 0.75 A

3MC1723C
R3
5.1k
0.1µF

6

4

5

13

R1

10k

100pF

Cref

R2

7

13k

0.66 V; 10 kΩ < R1 + R2 < 100 kΩ ; 0 ≤ Cref ≤ 0.1 µF
ISC
Vref
7.0 V
R2 =
(R1 + R2) ≅(R1 + R2)
VO
VO

RSC ≅

R3 = R1 || R2
0 < R4 ≤ VBE on (Q1) / 5.0 mA
Selection of Q1 based on considerations of Section 4.
Values shown are for a 12 V, 750 mA regulator using an unheatsinked
MC1723CP and a 2N3791 on a 4°C/W heatsink for TA up to + 70°C.

3. High Efficiency Regulator Configurations
When large output currents at voltages under approximately 9.0 V are desired, the configuration of
Figure 3–6A can be utilized to obtain increased operating efficiency. This is accomplished by providing aseparate low voltage input supply for the pass element. This method, however, usually necessitates that
separate short circuit protection be provided for the IC regulator and external pass element. Figure 3–6A
shows a high efficiency regulator configuration for the MC1723C.
Figure 3–6A. MC1723C High Efficiency Regulator Configuration
2N3055
Q1

Vin1+ 6.5V
Vin2

8

10

+ 10V

7

2

4

Cref

R1

2.0k
3

R2

5.1k

0.1µF

MC1723C

7

3

R = 15Ω
IB

RSC

VO

0.62Ω
1.0W

+5.0V
ISC = 1.0 A

MPS6512 orEquivalent

4

1.3k

13

R3

RSC ≅
R≅

0.66 V; 10 kΩ <R1 + R2 < 100 kΩ
Ib(max)

R2 =

VO
Vref

1.0nF

See Section 3F for general design considerations.
Selection of Q1 based on considerations of Section 4.
Values shown for a 5.0 V, 1.0 A regulator using an unheatsinked
MC1723CP and a 2N3055 on a 10°C/W heatsink for TA up to + 70°C.

http://onsemi.com
21

0.6 V
ISC

(R1 + R2) ≅0 ≤ Cref ≤ 0.1 µF
R3 ≅ R1 || R2

VO(R1 + R2)
7.0 V

B. Negative, Adjustable Output IC Regulator Configurations
1. Basic Regulator Configurations (MC1723C)
Although a positive regulator, the MC1723C can be used in a negative regulator circuit configuration.
This is done by using an external pass element and a zener level shifter as shown in Figure 3–1B. It should
be noted that for proper operation, the input supply must not vary over a wide range, since the correct value
for VZ depends directly on this voltage. In addition, it should be noted that this circuit will not operate witha shorted output.
Figure 3–1B. MC1723C Negative Regulator Configuration
10

12
11

R1

12k

4
MC1723C

6

+

100pF

5

13

R2

10k

7

VO = -15 V

VZ = 14 V
Q1

Vin = -20 V to -23 V

10mF

2N3055or Equiv

VO ≥ 10 V; 10 kΩ ≤ R1 + R2 ≤ 100 kΩ
R2 =

Vref
VO

(R1 + R2) ≅

7.0 V
VO

(R1 + R2)

VZ ≤Vin - VBE(Q1) - 3.0 V; VZ ≥ Vin - VO - VBE(Q1) + 6.0 V
Selection of Q1 based on considerations of Section 4.
Values shown are for a -15 V, 750 mA regulator using the MC1723CP with Q1
mounted on a 20°C/W heatsink at TA up to +70°C. Do not short circuit output.

C. Positive, Fixed Output IC Regulator Configurations
1. Basic Regulator Configuration
The basic current configuration for the positive three–terminal regulators is shown in Figure 3–1C.
Depending on which regulator type is used, this configuration can provide output currents in excess
of 3.0 A.

2. Output Current Boosting
Figure 3–2C illustrates a method for obtaining greater output currents with the three–terminal positive
regulators. Although any of these regulators may be used, usually it is most economical to use the 1.0 A
MC7800C in this configuration.

http://onsemi.com
22

Figure 3–1C. Basic Circuit Configuration for Positive, Fixed Output, Three–Terminal Regulators
1

Vin

Cin

0.33µF

2

IO
1.0 A
0.1 A
0.5 A
3.0 A

DeviceMC78XX
MC78LXX
MC78MXX
MC78TXXVO

CO

3

Cin: required if regulator is located more than a few (≈2 to 4) inches away
Cin: from input supply capacitor; for long input leads to regulator, up to 1.0 µF
Cin: may be needed for Cin. (Cin should be a high frequency type capacitor.)
CO: improves transient response.
XX: two digits of type number indicating nominal output voltage.
See Section 15 for heatsinking.

Figure 3–2C. Current Boost Configuration for Positive Three–Terminal Regulators
Vin

0.12Ω
5.0W

10V

RSC

MJ2955or Equiv
Q1
ISC(Q1)

2N6049or Equiv
R
50Ω

IC1
1

MC78XXC

1.0µF

3

2

ISCTOT

ISC(IC1)

VO
5.0V

XX:two digits of type number indicating nominal output voltage.
R:used to divert IC regulator bias current and determines at
what output current level Q1 begins conducting.
0<R≤

VBE on(Q1); RSC ≈
IBias (IC1)

0.6 V; ISCTOT = ISC(Q1) + ISC(IC1)ISC(Q1)

Selection of Q1 based on considerations of Section 4.
Values shown are for a 5.0 V, 5.0 A regulator using an MC7805CT on
a 2.5°C/W heatsink and Q1 on a 1°C/W heatsink for TA up to 70°C.

3. Obtaining an Adjustable Output Voltage
With the addition of an op amp, an adjustable output voltage supply can be obtained with the MC7805C.
Regulation characteristics of the three–terminal regulators are retained in this configuration, shown in
Figure 3–3C. If lower output currents are required, then an MC78M05C (0.5 A) could be used in place ofthe MC7805C.

4. Current Regulator
In addition to providing voltage regulation, the three–terminal positive regulators can also be used as
current regulators to provide a constant current source. Figure 3–4C shows this configuration. The output
current can be adjusted to any value from ≈ 8.0 mA (IQ, the regulator bias current) up to the available output
current of the regulator. Five–volt regulators should be used to obtain the greatest output voltage
compliance range for a given input voltage.
http://onsemi.com
23

Figure 3–3C. Adjustable Output Voltage Configuration
Using a Three–Terminal Positive Regulator

Vin

1

2

MC7805C

Figure 3–4C. Current Regulator ConfigurationVO

MC7805C
MC78MO5C
MC78L05A, C

1

Vin
0.33µF

VO′

3

3

R

VO
7
6

0.33µF

2

MC1741CP1

1.0k

IIB

2
0.1µF
3

IO =

10k

VO′
R

+ IIB

Current Reg ∆IO =4

IO

Constant Current
to Grounded Load

∆VO′R

+ ∆ IIBVO + VO′ + 2.0 V ≤ Vin ≤ 35 V

VO = 7.0 V to 33 V
Vin - VO ≥ 2.0 V
Vin ≥ 35 V

5. High Input Voltage
Occasionally, it may be necessary to power a three–terminal regulator from a supply voltage greaterthan Vin(max), 35 V or 40 V. In these cases a preregulator circuit, as shown in Figure 3–5C, may be used.

Figure 3–5C. Preregulator for Input Voltages Above Vin(max)
2N6569

Vin
60V
R1

IC1

1

MC78XXC

Q1
750Ω
2.0W

0.33µF

2VO

3

IN5363
30V, 5.0W

R1 = (

Vin - 30

1.5
VCEO(Q1) ≤ Vin) • hfe(Q1)

XX: two digits of type number indicating nominal output voltage.
Values shown for Vin = 60 V
Q1 should be mounted on a 2°C/W heatsink for operation at TA up to+70°C. IC1 should be appropriately heatsinked for the package type used.

6. High Output Voltage
If output voltages above 24 V are desired, the circuit configuration of Figure 3–6C may be used. Zener
diode (Z1) sets the output voltage, while Q1, Z2, and D1 assure that the MC7824C does not have morethan 30 V across it during short circuit conditions.
http://onsemi.com
24

Figure 3–6C. High Output Voltage Configuration for Three–Terminal Positive Regulators
IC1
2N6576

Vin

1

60V
R1

5.6k
1/2W

Q1

Z2

VO

2

MC7824CT

48V+

30.33µF

IN4751
30V,
1.0W

10µF
50V

IN4001D1IN474924V, 1.0W

Z1

VO = VZ1 + 24; R1 = (Vin - (VZ1 + VZ2)
1.5

) • hfe(Q2)

Values shown are for a 48 V, 1.0 A regulator
Q1 mounted on a 10°C/W heatsink
and IC1 mounted on a 2°C/W heatsink for TA up to +70°C.

D. Negative, Fixed Output IC Regulator Configurations
1. Basic Regulator Configurations
Figure 3–1D gives the basic circuit configuration for the MC79XX and MC79LXX three–terminal
negative regulators.

Figure 3–1D. Basic Circuit Configuration for Negative Three–Terminal Regulators
-Vin
Cin

3 or
Case

Device
MC79XX
MC79LXX

IO
1.0 A
0.1 A
1

0.33µF

2

0.1µF

-VO
CO

Cin:required if regulator is located more than a few (≈ 2 to 4) inches away from input supply
Cin:capacitor; for long input leads to regulator, up to 1.0 µF may be required. Cin should be a high frequency type
Cin:capacitor.
CO:improves stability and transient response.
XX:two digits of type number indicating nominal output voltage.
See Section 15 for heatsinking.

http://onsemi.com
25Output Current Boosting
In order to obtain increased output current capability from the negative three–terminal regulators, thecurrent boost configuration of Figure 3–2D may be used. Currents which can be obtained with thisconfiguration are limited only by the capabilities of the external pass transistor(s).
Figure 3–2D. Output Current Boost Configuration for Three–Terminal Negative Regulators-10V

ISC(Q1)

0.56, 1W

Vin

Q10.56, 1WVO

2N3055or Equiv

0.56, 1W
RSC

ISCTOT

ISC(IC1)

IC1

MJE200or Equiv

3

MC79XXC

R
5.6
+

Gnd

1

1.0µF

2

1.0µF

+

Gnd

XX:two digits of type number indicating output voltage. See Section 2 for available voltages.
R:used to divert regulator bias current and determine at what output current level Q1
R:begins conducting.
O<R≤

VBE on(Q1)
IBias(IC1)ISCTOT = ISC(Q1) + ISC(IC1)
RSC ≈

0.6 V
ISC(Q1)
Selection of Q1 based on considerations of Section 4.

Values shown are for a -5.0 V, +4.0 A regulator; using an MC7905CT on a 1.5°C/W heatsink
with Q1 mounted on a 1°C/W heatsink for TA up to +70°C.

2. Current Regulator
The three–terminal negative regulators may also be used to provide a constant current sink, as shownin Figure 3–3D. In order to obtain the greatest output voltage compliance range at a given input voltage,
the MC7905C or MC79L05C should be used in this configuration.
Figure 3–3D. Current Regulator Configuration for the Three–Terminal Negative Regulators
IO
Vin

3
1.0µF

MC7905C
or
MC79L05A,C

2

R

VO′

1

1.0µF

IIB
Vin ≥ - 35 V for MC7905C
Vin ≥ - 30 V for MC79L05C
Vin ≤ VO + VO - 2.0 V
IO =

VO′
R

+ IIB

Current regulation: ∆IO =∆VO′
R+ ∆IIB

http://onsemi.com
26

VO

Constant Current
from GroundedLoad

F. General Design Considerations
In addition to the design equations given in the regulator circuit configuration panels of Sections 3A–E,
there are a few general design considerations which apply to all regulator circuits. These considerations
are given below.

1. Regulator Voltages
For any circuit configuration, the worse–case voltages present on each pin of the IC regulator must bewithin the maximum and/or minimum limits specified on the device data sheets. These limits are
instantaneous values, not averages.
They include: a. Vin(min)b. Vin(max)c. (Vin – Vout) min
d. Vout(min)e. Vout(max)For example, the voltage between Pins 12 and 7 (Vin) of an MC1723CP must never fall below 9.5 V,
even instantaneously, or the regulator will not function properly, (see Figure 3–1B).

2. Regulator Power Dissipation, Junction Temperature and Safe Operating Area
The junction temperature, power dissipation output current or safe operating area limits of the IC
regulator must never be exceeded.

3. Operation with a Load Common to a Voltage of Opposite Polarity
In many cases, a regulator powers a load which is not connected to ground but instead is connected
to a voltage source of opposite polarity (e.g. op amps, level shifting circuits, etc.). In these cases, a clamp
diode should be connected to the regulator output as shown in Figure 3–1F. This protects the regulator,
during startup and short circuit operation, from output polarity reversals.
Figure 3–1F. Output Polarity Reversal Protection
+ Vin

+ VO

Positive
Regulator
1N4001or Equiv

Load
1N4001or Equiv- Vin

Negative
Regulator- VO

http://onsemi.com
27

4. Reverse Bias Protection
Occasionally, there exists the possibility that the input voltage to the regulator can collapse faster thanthe output voltage. This could occur, for example, if the input supply is “crowbarred” during an output
overvoltage condition. If the output voltage is greater ≈ 7.0 V, the emitter–base junction of the series passelement (internal or external) could break down and be damaged. To prevent this, a diode shunt can be
employed, as shown in Figure 3–2F.
Figure 3–3F shows a three–terminal positive–adjustable regulator with the recommended protection
diodes for output voltages in excess of 25 V, or high output capacitance values (CO > 25 µF, CAdj >10 µF).
Diode D1 prevents CO from discharging through the regulator during an input short circuit. Diode D2
protects against capacitor CAdj from discharging through the regulator during an output short circuit. The
combination of diodes D1 and D2 prevents CAdj from discharging through the regulator during an input
short circuit.
Figure 3–2F. Reverse Bias Protection

Figure 3–3F. Reverse Bias Protection for
Three–Terminal Adjustable Regulators
D1

Vin

Positive
Regulator+ VO

1N4002Vin

Cin

Positive
Adjustable
Regulator

Vout

R1

+ VO
D2
1N4002Adjust
R2

+

CO

CAdj
+ VO

http://onsemi.com
28

SECTION 4
SERIES PASS ELEMENT CONSIDERATIONSFOR LINEAR REGULATORS
Presently, most monolithic IC voltage regulators that are available have output current capabilities from
100 mA to 3.0 A. If greater current capability is required, or if the IC regulator does not possess sufficientsafe–operating–area (SOA), the addition of an external series pass element is necessary.
In this section, configurations, specifications and current limit techniques for external series passelements will be considered. For illustrative purposes, pass elements for only positive regulator types will
be discussed. However, the same considerations apply for pass elements used with negative regulators.

A. Series Pass Element Configurations
Using an NPN Type Transistor
If the IC regulator has an external sense lead, an NPN type series pass element may be used, as shownin Figure 4–1 A. This pass element could be a single transistor or multiple transistors arranged in
Darlington and/or paralleled configurations.
In this configuration, the IC regulator supplies the base current (IB) to the pass element (Q2) whichacts as a current amplifier and provides the increased output current (IO) capability.
Figure 4–1A. NPN Type Series Pass Element Configuration
External
Serial Pass Element
VCE(Q2)IC(Q2)

``C''

Vin1*

``E''
Q2

IO
VO

``B''

IB(Q2)IC Regulator (simplified)
Vin2

VO′

Q1

IBias
VS
Sense Lead

*Vin1 may or may not equal Vin2, depending on the application.

http://onsemi.com
29

Using a PNP Type Transistor
If the IC regulator does not have an external sense lead, as in the case of the three–terminal fixed output
regulators, the configuration of Figure 4–1B can be used. (Regulators which possess an external sense
lead may also be used with this configuration.) As before, the PNP type pass element can be a single
transistor or multiple transistors.
Figure 4–1B. PNP Type Series Pass Element Configuration
External
Series Pass Element
``E''

Vin1

R

VCE(Q2)IC(Q2)

``C''

Q2

``B''
IC Regulator (simplified)IB(Q2)

Q1

Vin1

IO
VO

IBias

This configuration functions in a similar manner to that of Figure 4–1A, in that the regulator supplies
base current to pass element. The resistor (R) serves to route the IC regulator bias current (IBias) awayfrom the base of Q2. If not included, regulation would be lost at low output currents. The value of R is low
enough to prevent Q2 from turning on when IBias flows through this resistor, and is given by:
0<R≤

VBEon(Q2 )
IBias

(4.0)

B. Series Pass Element Specifications
Independent of which configuration is utilized, the transistor or transistors that compose the passelement must have adequate ratings for IC(max), VCEO, hfe, power dissipation, and safe operating area.

1. IC(max) — for the pass element of Figure 4–1A, IC(max) is given by:
IC(max)(Q2) ≥ IO(max) – IB(max)(Q2) = IO(max) –≥ IO(max)IC(max)(Q2)
hfe(Q2)

(4.1)
(4.2)

For the configuration of Figure 4–1B:
IC(max)(Q2) ≥ IO(max) + IB(max)(Q2)≥ IO(max)

http://onsemi.com
30

(4.3)
(4.4)

2. VCEO — since VCE(Q2) is equal to Vin1(max) when the output is shorted or during start up:
VCEO(Q2) ≤ Vin1(max)(4.5)

3. hfe — the minimum DC current gain for Q2 in Figures 4–1A and 4–1B is given by:hfe(min)(Q2) ≥IC(max)(Q2)@ VCE = (Vin1(min) – VO)

IB(max)(Q2)(4.6)

4. Maximum Power Dissipation PD(max), and Safe Operating Area (SOA)
For any transistor there are certain combinations of IC and VCE at which it may safely be operated.
When plotted on a graph, whose axes are VCE and IC, a safe–operating region is formed.
As an example, the safe–operating–area (SOA) curve for the well known 2N3055 NPN silicon powertransistor is shown in Figure 4–2. The boundaries of the SOA curve are formed by IC(max), power
dissipation, second breakdown and VCEO ratings of the transistor. Notice that the power dissipationand second breakdown ratings are given for a case temperature of +25°C and must be derated at higher
case temperatures. (Derating factors may be found in the transistors’ data sheets.) These boundaries
must never be exceeded during operation, or destruction of the transistor(s) which constitute the passelement may result. (In addition, the maximum operating junction temperature must not be exceeded, see
Section 15.)

C. Current Limiting Techniques
In order to select a transistor or transistors with adequate SOA, the locus of pass element IC and VCE
operating points must be known. This locus of points is determined by the input voltage (Vin1, output voltage(VO), output current (IO) and the type of output current limiting technique employed.
In most cases, Vin1, VO, and the required output current are already known. All that is left to determine
is how the chosen current limit scheme affects required pass element SOA.
Note, since the external pass element is merely an extension of the IC regulator, the following
discussions apply equally well to IC regulators not using an external pass element.

1. Constant Current Limiting
This method is the simplest to implement and is extensively used, especially at the lower output current
levels. The basic circuit configuration is shown in Figure 4–3A, and operates in the following manner.
As the output current increases, the voltage drop across RSC increases, proportionately. When the
output current has increased to the point that the voltage drop across RSC is equal to the base–emitter ON
voltage of Q3 (VBEon(Q3)), Q3 conducts. This diverts base current (IDrive) away from Q1, the IC regulator’sinternal series pass element. Base drive (IB(Q2)) of Q2 is therefore reduced and its collector–emitter
voltage increases, thereby reducing the output voltage below its regulated value, Vout. The resulting output
voltage–current characteristic is shown in Figure 4–3B.
The value of ISC is given by:
ISC =VBEon(Q3)
RSC

http://onsemi.com
31

(4.7)

Figure 4–2. 2N3055 Safe Operating Area (SOA)
20

IC(max)10
PD(max) @ TC = 25°C
7.0

5.0

I C , COLLECTOR CURRENT, (A)2N3055
Safe-Operating-Area
3.0

2.0

1.0
Second Breakdown @ TC = 25°C
0.7

0.5

0.3

0.2

VCEO

0.1

3.0

4.0

5.0

7.0

10

20

VCE, COLLECTOR-TO-EMITTER VOLTAGE, (V)

http://onsemi.com
32

40

60

Figure 4–3. Constant Current Limiting

(a)

(b)

IC(Q2)Vin1

Q1
IDrive

Vout

IO

Q2

RSC

Ib(Q2)VBE(Q3)VO

VO, OUTPUT VOLTAGE

External
Pass Element
VCE(Q2)

Q3

IO, OUTPUT CURRENTISCIC Regulator

By using the base of Q1 in the IC regulator as a control point, this configuration has the added benefitof limiting the IC regulator output current (IB(Q2)) to Isc/hfe(Q2), as well as limiting the collector current of
Q2 to ISC. Of course, access to this point is necessary. Fortunately, it is usually available in the form ofa separate pin or as the regulator’s compensation terminal.(1)The required safe–operating–area for Q2 can be obtained by plotting the VCE and IC of Q2 given by:
VCE(Q2) = Vin1 – VO – IORSC  Vin1 – VO
IC(Q2)  IO

(4.8)
(4.9)

where, VO = Vout for 0 ≤ IO ≤ ISC(4.10)

and, IO = ISC for 0 ≤ VO ≤ Vout

(4.11)The resulting plot is shown in Figure 4–4. The transistor chosen for Q2 must have an SOA which encloses
this plot, see Figure 4–4. Note that the greatest demand on the transistor’s SOA capability occurs when the
output of the regulator is short circuited and the pass element must support the full input voltage and shortcircuit current simultaneously.
Figure 4–4. Constant Current Limit SOA Requirements(See Section 3 for Circuit Techniques)IC(Q2) , COLLECTOR CURRENT LOG

IC(max)Pass Element SOA

ISC

Vin1 - Vout
Vin1 VCEO
VCE(Q2), COLLECTOR-EMITTER VOLTAGE LOG(1)

The three–terminal regulators have internal current limiting and therefore do not provide
access to this point. If an external pass element is used with these regulators, constantcurrent limiting can still be accomplished by diverting pass element drive.

http://onsemi.com
33

2. Foldback Current Limiting
A disadvantage of the constant current limit technique is that in order to obtain sufficient SOA the passelement must have a much greater collector current capability than is actually needed. If the short circuitcurrent could be reduced, while still allowing full output current to be obtained during normal regulator
operation, more efficient utilization of the pass elements SOA capability would result. This can be doneby using a “foldback” current limiting technique instead of constant current limiting.
The basic circuit configuration for this method is shown in Figure 4–5(A). The circuit operates in amanner similar to that of the constant current limiting circuit, in that output current control is obtained bydiverting base drive away from Q1 with Q3.
At low output currents, VA approximately equals VO and VR2 is less than than VO. Q3 is therefore
non–conducting and the output voltage remains constant. As the output current increases, the voltage drop
across RSC increases until VA and VR2 are great enough to bias Q3 on. The output current at which thisoccurs is IK, the “knee” current.
Figure 4–5. Foldback Current Limiting

(a)

(b)

External Pass Element
VCE(Q2)
VA
Q2

Vin1

Ib(Q2)

Q1

IO

Vout

VO, OUTPUT VOLTAGE

IC(Q2)

VO

RSC

R1

IDriveISC

IO, OUTPUT CURRENT
Q3IC Regulator
VBE(Q3)

R2

VR2

Figure 4–6. Foldback Current Limit SOA Requirements

I C(Q2), COLLECTOR CURRENT LOG

IC(max)Pass Element

IK
Constant Current
Limiting
Foldback Current
Limiting

ISC

Vin1 VCEO

Vin1-Vout

VCE(Q2), COLLECTOR-EMITTER VOLTAGE LOG

http://onsemi.com
34

IK

The output voltage will now decrease. Less output current is now required to keep VA and VR2 at alevel sufficient to bias Q3 on since the voltage at its emitter has the tendency to decrease faster than thatat its base. The output current will continue to “foldback” as the output voltage decreases, until an output
short circuit current level (ISC) is reached when the output voltage is zero. The resulting output
current–voltage characteristic is shown in Figure 4–5B. The values for R1, R2, and RSC (neglecting basecurrent of Q3) are given by:
RSC =Vout/ISC
I
Vout
– K
1 
ISC
VBEon(Q3)
R2
V= BEon(Q3)
ISC RSC
R1 + R2

and, R1 + R2 ≤Vout
IDrive(4.12)(4.13)(4.14)

where: Vout = normal regulator output voltage
IK = knee current
ISC = short circuit current
IDrive = base drive to regulator’s internal pass element(s)A plot of Q2 operating points, which result when using this technique, is shown in Figure 4–6. Notethat the pass element is required to operate with a collector current of only ISC during short circuit
conditions, not the full output current, IK. This results in a more efficient utilization of the SOA of Q2 allowing
the use of a smaller transistor than if constant current limiting were used. Although foldback current limiting
allows use of smaller pass element transistors for a given regulator output current than does constantcurrent limiting, it does have a few disadvantages.
Referring to Equation (4.12), as the foldback ratio (IK/ISC) is increased, the required value of RSC
increases. This results in a greater input voltage at higher foldback ratios. In addition, it can be seen forEquation (4.12) that there exists an absolute limit to the foldback ratio equal to:
IK
ISC(max)

 1 

Vout
for RSC  
VBEon(Q3)(4.15)For these reasons, foldback ratios greater than 2:1 or 3:1 are not usually practical for the lower output
voltage regulators.

http://onsemi.com
35

D. Paralleling Pass Element Transistors
Occasionally, it will not be possible to obtain a transistor with sufficient safe–operating–area. In thesecases it is necessary to parallel two or more transistors. Even if a single transistor with sufficient capability
is available, it is possible that paralleling two smaller transistors is more economical.
In order to insure that the collector currents of the paralleled transistors are approximately equal, theconfiguration of Figure 4–7 can be used. Emitter–ballasting resistors are used to force collector–current
sharing between Q1 and Q2. The collector–current mismatch can be determined by considering thefollowing, from Figure 4–7,
VBE1 + V1 = VBE2 + V2

(4.16)

and, ∆VBE = ∆V

(4.17)

where: VBE = VBE1 – VBE2 and, ∆V = V2 – V1
Assuming IE1  IC1 and IE2  OC2, the collector–current mismatch is given by,
V2RE

IC2 – IC1
=
IC2

V1
RE

–
V2
RE

and, percent collector–current mismatch =

∆VBE
V2

=

V2 – V1
∆V
∆VBE
=
=
V2
V2
V2

(4.18)(4.19)

× 100%(4.20)

From Equation (4.20), the collector–current mismatch is dependent on ∆ VBE and V2. Since ∆VBE isusually acceptable, V2 should be 1.0 V to 0.5 V, respectively. RE is therefore given by:
RE =0.5 V to 1.0 V
0.5 V to 1.0 V
0.5 V to 1.0 V
=
=
IC1
IC2
IC/2

(4.21)

Figure 4–7. Paralleling Pass Element Transistors
IC

IC1

IC2

IB
Q1

Q2

VBEI

IE1
V1

QN

VBE2

RE

IE2
V2

http://onsemi.com
36

RE

SECTION 5
LINEAR REGULATOR CONSTRUCTION
AND LAYOUT
An important, and often neglected, aspect of the total regulator circuit design is the actual layout andcomponent placement of the circuit. In order to obtain excellent transient response performance, highfrequency transistors are used in modern integrated circuit voltage regulators. Proper attention to circuit
layout is therefore necessary to prevent regulator instability or oscillations, or degraded performance.
In this section, guidelines will be given on proper regulator layout and placement of circuit components.
In addition, topics such as remote voltage sensing, semiconductor mounting techniques, and thermal
system evaluations will also be discussed.

1. General Layout and Component Placement Considerations
As mentioned previously, modern integrated circuit regulators are necessarily high bandwidth devices
in order to obtain good transient response characteristics. To insure stable closed–loop operation, all thesedevices are frequency compensated, either internally or externally. This compensation can easily be upset
by unwanted stray circuit capacitances and lead inductances, resulting in spurious oscillations. Therefore,
it is important that the circuit lead lengths be short and the layout as tight as possible. Particular attention
should be paid to locating the compensation and bypass capacitors as close to the IC as possible. Lead
lengths associated with the external pass element(s), if used, should also be minimized.
Often overlooked is the stray inductance associated with the input leads to the regulator circuit. If thelead length from the input supply filter capacitor to the regulator input is more than a couple of inches, a0.01 µF to 1.0 µF high frequency type capacitor (tantalum, ceramic, etc.) should be used to bypass the
supply leads close to the regulator input pins.

2. Ground Loops and Remote Voltage Sensing
Ground Loops — Regulator performance can also suffer if ground loops in the circuit wiring are not
avoided. The most common ground loop problem occurs when the return lead of the input supply filter
capacitor is improperly located, as shown in Figure 5–1. If this return lead is physically connected between
the load return and the regulator circuit ground point (“B”), a ripple voltage component (60 Hz or 120 Hz)
can be induced on the load voltage (VL). This is due to the high peaks of the filter capacitor ripple current(Iripple) flowing through the lead resistance between the load and regulator. These peaks can be 5 to 15
times the value of load current. Since the regulator will only keep constant the voltage between its sense
lead and ground point, points “A” and “B” in Figure 5–1, this additional ripple voltage (Vlead), will appear at
the load.
This problem can be avoided by proper placement and connection of the filter capacitor return load asshown in Figure 5–2.
Remote Voltage Sensing — Closely related to the above ground loop problem is resistance in the current
carrying leads to the load. This can cause poorer than expected load regulation in cases where the load
currents are large or where the load is located some distance from the regulator. This is illustrated in Figure
5–3. As stated previously, the regulator circuit will keep the voltage present between its sense and groundpins constant. From Figure 5–3 we can see that any lead resistance between these points and the load willcause the load voltage (VL) to vary with varying load current, IL. This effectively lowers the load regulation of
the circuit.

http://onsemi.com
37

Figure 5–1. Filter Capacitor Ground Loop — WRONG!
A"Regulator
Circuit
+
C

B"

to
XFMR

Vout

VL

RL

VL

RL

RLead
IrippleVLead

Figure 5–2. Filter Capacitor Ground Loop — RIGHT!
A"

Regulator
Circuit
+

C

Vout

B"

to
XFMR

IrippleThis problem can be avoided by the use of remote Sense leads, as shown in Figure 5–4. The voltage
drops in the high current carrying leads now have no effect on the load voltage (V L). However, since theSense and Ground leads are usually rather long, care must be exercised that their associated lead
inductance is minimized, or loop instability may result. The Ground and Sense leads should be formed intoa twisted pair lead to minimize their lead inductance and noise pickup.
Figure 5–3. Effects of Resistance In Output Leads
OutputVin

RLead

Regulator
Circuit
Sense

+

Gnd

VL

Load

IL
RLead

Figure 5–4. Remote Voltage Sensing
OutputVin

RLead

Regulator
Circuit
Sense

+
Gnd

VL

RLead

http://onsemi.com
38

RL

IL

3. Mounting Considerations for Power Semiconductors
Current and power ratings of semiconductors are inseparably linked to their thermal environment.
Except for lead–mounted parts used at low currents, a heat exchanger is required to prevent the junction
temperature from exceeding its rated limit, thereby running the risk of a high failure rate. Furthermore, thesemiconductor industry’s field history indicated that the failure rate of most silicon semiconductors
decreases approximately by one–half for a decrease in junction temperature from 160° to 135°C.(1)Guidelines for designers of military power supplies impose a 110°C limit upon junction temperature.(2)Proper mounting minimizes the temperature gradient between the semiconductor case and theheat exchanger.
Most early life field failures of power semiconductors can be traced to faulty mounting procedures. With
metal packaged devices, faulty mounting generally causes unnecessarily high junction temperature,
resulting in reduced component lifetime, although mechanical damage has occurred on occasion from
improperly mounting to a warped surface. With the widespread use of various plastic packaged
semiconductors, the prospect of mechanical damage is very significant. Mechanical damage can impair
the case moisture resistance or crack the semiconductor die.
Figure 5–5 shows an example of doing nearly everything wrong. A tab mount TO–220 package isshown being used as a replacement for a TO–213AA (TO–66) part which was socket mounted. To use thesocket, the leads are bent — an operation which, if not properly done, can crack the package, break theinternal bonding wires, or crack the die. The package is fastened with a sheet metal screw through a 1/4″
hole containing a fiber–insulating sleeve. The force used to tighten the screw tends to pull the package into
the hole, possibly causing enough distortion to crack the die. In addition the contact area is small becauseof the area consumed by the large hole and the bowing of the package, the result is a much higher junction
temperature than expected. If a rough heatsink surface and/or burrs around the hole were displayed in theillustration, most but not all poor mounting practices would be covered.
Figure 5–5. Extreme Case of Improperly Mountinga Semiconductor (Distortion Exaggerated)
Plastic Body
Leads

Package Heatsink
Mica Washer

Equipment
Heatsink

Socket for
TO-213AA Package

Speed Nut(Part of Socket)
Sheet Metal Screw_________________________________(1) MIL–HANDBOOK — 2178, SECTION 2.2.
(2) Navy Power Supply Reliability — Design and Manufacturing Guidelines NAVMAT P4855–1,
Dec. 1982 NAVPUBFORCEN,
5801 Tabor Ave., Philadelphia, PA 19120.
Cho–Therm is a registered trademark of Chromerics, Inc.
Grafoil is a registered trademark of Union Carbide
Kapton is a registered trademark of E.I. Dupont
Rubber–Duc is a trademark of AAVID Engineering
Sil Pad is a trademark of Berquist
Sync–Nut is a trademark of ITW Shakeproof
Thermasil is a registered trademark and Thermafilm is a trademark of Thermalloy, Inc.
ICePAK, Full Pak, POWERTAP and Thermopad are trademarks of ON Semiconductor, Inc.

http://onsemi.com
39

In many situations the case of the semiconductor must be electrically isolated from its mounting
surface. The isolation material is, to some extent, a thermal isolator as well, which raises junction operating
temperatures. In addition, the possibility of arc–over problems is introduced if high voltages are present.
Various regulating agencies also impose creepage distance specifications which further complicatesdesign. Electrical isolation thus places additional demands upon the mounting procedure.
Proper mounting procedures usually necessitate orderly attention to the following:
1. Preparing the mounting surface
2. Applying a thermal grease (if required)
3. Installing the insulator (if electrical isolation is desired)
4. Fastening the assembly
5. Connecting the terminals to the circuit
In this note, mounting procedures are discussed in general terms for several generic classes of
packages. As newer packages are developed, it is probable that they will fit into the generic classes
discussed in this note. Unique requirements are given on data sheets pertaining to the particular package.
The following classes are defined:
Flange Mount
Tab Mount
Plastic Body Mount
Surface Mount
Appendix A contains a brief review of thermal resistance concepts.
Appendix B discusses measurement difficulties with interface thermal resistance tests.
Mounting Surface Preparation
In general, the heatsink mounting surface should have a flatness and finish comparable to that of thesemiconductor package. In lower power applications, the heatsink surface is satisfactory if it appears flat
against a straight edge and is free from deep scratches. In high power applications, a more detailed
examination of the surface is required. Mounting holes and surface treatment must also be considered.
Surface Flatness
Surface flatness is determined by comparing the variance in height (∆h) of the test specimen to thatof a reference standard as indicated in Figure 5–6. Flatness is normally specified as a fraction of the Total
Indicator Reading (TIR). The mounting surface flatness (i.e, ∆h/TIR) if less than 4 mils per inch, normal
for extruded aluminum, is satisfactory in most cases.

Figure 5–6. Surface Flatness Measurement
TIR = Total Indicator Reading
Sample
Piece
TIR

Reference
Piece

Device Mounting Area

http://onsemi.com
40∆hSurface Finish
Surface finish is the average of the deviations both above and below the mean value of surface height.
For minimum interface resistance, a finish in the range of 50 µin. to 60 µin. is satisfactory. A finer finish
is costly to achieve and does not significantly lower contact resistance. Tests conducted by Thermalloy
using a copper TO–204 (TO–3) package with a typical 32 µin. finish, showed that heatsink finishes between
16 µin. and 64 µin. caused less than ±2.5% difference in interface thermal resistance when the voids andscratches were filled with a thermal joint compound.(3) Most commercially available cast or extruded
heatsinks will require spotfacing when used in high power applications. In general, milled or machined
surfaces are satisfactory if prepared with tools in good working condition.
Mounting Holes
Mounting holes generally should only be large enough to allow clearance of the fastener. The larger
thick flange type packages having mounting holes removed from the semiconductor die location, such as
the TO–204AA, may successfully be used with larger holes to accommodate an insulating bushing, butmany plastic encapsulated packages are intolerant of this condition. For these packages, a smaller screw
size must be used such that the hole for the bushing does not exceed the hole in the package.
Punched mounting holes have been a source of trouble because if not properly done, the area arounda punched hole is depressed in the process. This “crater” in the heatsink around the mounting hole cancause two problems. The device can be damaged by distortion of the package as the mounting pressure
attempts to conform it to the shape of the heatsink indentation, or the device may only bridge the craterand leave a significant percentage of its heat–dissipating surface out of contact with the heatsink. The first
effect may often be detected immediately by visual cracks in the package (if plastic), but usually an
unnatural stress is imposed, which results in an early–life failure. The second effect results in hotter
operation and is not manifested until much later.
Although punched holes are seldom acceptable in the relatively thick material used for extruded
aluminum heatsinks, several manufacturers are capable of properly utilizing the capabilities inherent inboth fine–edge blanking or sheared–through holes when applied to sheet metal as commonly used forstamped heatsinks. The holes are pierced using Class A progressive dies mounted on four–post die sets
equipped with proper pressure pads and holding fixtures.
When mounting holes are drilled, a general practice with extruded aluminum, surface cleanup isimportant. Chamfers must be avoided because they reduce heat transfer surface and increase mounting
stress. However, the edges must be broken to remove burrs which cause poor contact between device andheatsink and may puncture isolation material.
Surface Treatment
Many aluminum heatsinks are black–anodized to improve radiation ability and prevent corrosion.
Anodizing results in significant electrical but negligible thermal insulation. It need only be removed fromthe mounting area when electrical contact is required. Heatsinks are also available which have a nickel
plated copper insert under the semiconductor mounting area. No treatment of this surface is necessary.
Another treated aluminum finish is iridite, or chromate–acid dip, which offers low resistance becauseof its thin surface, yet has good electrical properties because it resists oxidation. It need only be cleanedof the oils and films that collect in the manufacture and storage of the sinks, a practice which should beapplied to all heatsinks.
For economy, paint is sometimes used for sinks; removal of the paint where the semiconductor is
attached is usually required because of the paint’s high thermal resistance. However, when it is necessary
to insulate the semiconductor package from the heatsink, hard anodized or painted surfaces allow an easy
installation for low voltage applications. Some manufacturers will provide anodized or painted surfaces
meeting specific insulation voltage requirements, usually up to 400 V.
It is also necessary that the surface be free from all foreign material, film, and oxide (freshly bared
aluminum forms an oxide layer in a few seconds). Immediately prior to assembly, it is a good practice topolish the mounting area with No. 000 steel wool, followed by an acetone or alcohol rinse.
________________________________(3) Catalog #87–HS–9 (1987), page 8, Thermalloy, Inc., P.O. Box 810839, Dallas, Texas 75381–0839.

http://onsemi.com
41

Interface Decisions
When any significant amount of power is being dissipated, something must be done to fill the air voids
between mating surfaces in the thermal path. Otherwise, the interface thermal resistance will be
unnecessarily high and quite dependent upon the surface finishes.
For several years, thermal joint compounds, often called grease, have been used in the interface. They
have a resistivity of approximately 60°C/W/in whereas air has 1200°C/W/in. Since surfaces are highly
pockmarked with minute voids, use of a compound makes a significant reduction in the interface thermal
resistance of the joint. However, the grease causes a number of problems, as discussed in the following
section. To avoid using grease, manufacturers have developed dry conductive and insulating pads toreplace the more traditional materials. These pads are conformal and therefore partially fill voids when
under pressure.
Thermal Compounds (Grease)
Joint compounds are a formulation of fine zinc or other conductive particles in a silicone oil or othersynthetic base fluid which maintains a grease–like consistency with time and temperature. Since some ofthese compounds do not spread well, they should be evenly applied in a very thin layer using a spatulaor lintless brush, and wiped lightly to remove excess material. Some cyclic rotation of the package will help
the compound spread evenly over the entire contact area. Some experimentation is necessary to
determine the correct quantity; too little will not fill all the voids, while too much may permit some compoundto remain between well mated metal surfaces where it will substantially increase the thermal resistanceof the joint.
To determine the correct amount, several semiconductor samples and heatsinks should be assembled
with different amounts of grease applied evenly to one side of each mating surface. When the amount iscorrect, a very small amount of grease should appear around the perimeter of each mating surface as theassembly is slowly torqued to the recommended value. Examination of a dismantled assembly should
reveal even wetting across each mating surface. In production, assemblers should be trained to slowly
apply the specified torque even though an excessive amount of grease appears at the edges of mating
surfaces. Insufficient torque causes a significant increase in the thermal resistance of the interface.
To prevent accumulation of airborne particulate matter, excess compound should be wiped away using
a cloth moistened with acetone or alcohol. These solvents should not contact plastic–encapsulated
devices, as they may enter the package and cause a leakage path or carry in substances which might
attack the semiconductor chip.
Data showing the effect of compounds on several package types under different mounting conditions
is shown in Table 5–1. The rougher the surface, the more valuable the grease becomes in lowering contact
resistance; therefore, when mica insulating washers are used, use of grease is generally mandatory. The
joint compound also improves the breakdown rating of the insulator.
Table 5–1. Approximate Values for Interface Thermal Resistance Data
from Measurements Performed In ON Semiconductor Applications Engineering Laboratory
Dry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless otherwise
noted the case temperature is monitored by a thermocouple located directly under the die reached through a hole in the heatsink.
(See Appendix B for a discussion of Interface Thermal Resistance Measurements.)
Package Type and Data
JEDEC
Outlines

Description

Interface Thermal Resistance (°C/W)
Test
Torque
Torq
e
In–Lb

Dry

Lubed

Dry

Lubed

Type

See
Note

Metal–to–Metal

With Insulator

TO–204AA (TO–3)

Diamond Flange

6

0.5

0.1

1.3

0.36

3 mil Mica1

TO–220AB

Thermowatt

8

1.2

1.0

3.4

1.6

2 mil Mica

1, 2

NOTES: 1. See Figures 5–7 and 5–8 for additional data on TO–204AA and TO–220 packages.
2. Screw not insulated (see Figure 5–12).

http://onsemi.com
42

Conductive Pads
Because of the difficulty of assembly using grease and the evaporation problem, some equipment
manufacturers will not, or cannot, use grease. To minimize the need for grease, several vendors offer dry
conductive pads which approximate performance obtained with grease. Data for a greased bare joint anda joint using Grafoil, a dry graphite compound, is shown in the data of Figure 5–7. Grafoil is claimed to bea replacement for grease when no electrical isolation is required; the data indicates it does indeed perform
as well as grease. Another conductive pad available from AAVID is called KON–DUX. It is made with aunique, grain oriented, flake–like structure (patent pending). Highly compressible, it becomes formed tothe surface roughness of both the heatsink and semiconductor. Manufacturer’s data shows it to provide
an interface thermal resistance better than a metal interface with filled silicone grease. Similar dry
conductive pads are available from other manufacturers. They are a fairly recent development; long term
problems, if they exist, have not yet become evident.

Insulation Considerations
Since most power semiconductors use are vertical device construction it is common to manufacture
power semiconductors with the output electrode (anode, collector or drain) electrically common to thecase; the problem of isolating this terminal from ground is a common one. For lowest overall thermal
resistance, which is quite important when high power must be dissipated, it is best to isolate the entire
heatsink/semiconductor structure from ground, rather than to use an insulator between the semiconductor
and the heatsink. Heatsink isolation is not always possible, however, because of EMI requirements, safety
reasons, instances where a chassis serves as a heatsink or where a heatsink is common to several
non–isolated packages. In these situations insulators are used to isolate the individual components fromthe heatsink. Newer packages, such as the ON Semiconductor Full Pak and EMS modules, contain theelectrical isolation material within, thereby saving the equipment manufacturer the burden of addressing
theisolation problem.
Insulator Thermal Resistance
When an insulator is used, thermal grease is of greater importance than with a metal–to–metal contact,because two interfaces exist instead of one and some materials, such as mica, have a hard, markedly
uneven surface. With many isolation materials reduction of interface thermal resistance of between 2 to
1 and 3 to 1 are typical when grease is used.
Data obtained by Thermalloy, showing interface resistance for different insulators and torques applied
to TO–204 (TO–3) and TO–220 packages, is shown in Figure 5–7, for bare and greased surfaces. Similarmaterials to those shown are available from several manufacturers. It is obvious that with somearrangements, the interface thermal resistance exceeds that of the semiconductor (junction–to–case).
Referring to Figure 5–7, one may conclude that when high power is handled, beryllium oxide isunquestionably the best. However, it is an expensive choice. (It should not be cut or abraided, as the dust
is highly toxic.) Thermafilm is a filled polyimide material which is used for isolation (variation of Kapton).
It is a popular material for low power applications because of its low cost ability to withstand hightemperatures, and ease of handling in contrast to mica which chips and flakes easily.
A number of other insulating materials are also shown. They cover a wide range of insulation
resistance, thermal resistance and ease of handling. Mica has been widely used in the past because it
offers high break down voltage and fairly low thermal resistance at a low cost but it certainly should be usedwith grease.
Silicone rubber insulators have gained favor because they are somewhat conformal under pressure.
Their ability to fill in most of the metal voids at the interface reduces the need for thermal grease. When
first introduced, they suffered from cut–through after a few years in service. The ones presently available
have solved this problem by having imbedded pads of Kapton or fiberglass. By comparing Figures 5–7(c)and 5–7(d), it can be noted that Thermasil, a filled silicone rubber without grease, has about the sameinterface thermal resistance as greased mica for the TO–220 package.

http://onsemi.com
43

Figure 5–7. Interface Thermal Resistance Using Different Insulating
Materials as a Function of Mounting Screw Torque
1.0

1.6

(1)

1.4

(2)
(3)
(4)
(5)

1.2
1.0
0.8

(6)
(7)

0.6
0.4
0.2

(1) Thermalfilm, .002 (.05) thick(2) Mica, .003 (.08) thick(3) Mica, .002 (.05) thick(4) Hard anodized, .020 (.51) thick(5) Aluminum oxide, .062 (1.57) thick(6) Berylium oxide, .062 (1.57) thick(7) Bare joint no finish(8) Grafoil, .005 (.13) thick**Grafoil is not an insulating material

(8)

0

0.9
0.8
0.7
0.6
0.5

(1)

0.4

(2) (3)
(5)
(4)

0.3
0.2
0.1
0

72 145 217 290 362 435
INTERFACE PRESSURE (psi)

0

5
(1)
4
(2)
(3)
(4)

2
1

72 145 217 290 362 435
INTERFACE PRESSURE (psi)(b) TO–204AA (TO–3)
With Thermal Grease(5)(6) (7)(8)(1) Thermalfilm, .022 (.05) thick(2) Mica, .003 (.08) thick(3) Mica, .002 (.05) thick(4) Hard anodized, .020 (.51) thick(5) Thermalsil Il, .009 (.23) thick(6) Thermalsil Il, .006 (.15) thick(7) Bare joint no finish(8) Grafoil, .005 (.13) thick**Grafoil is not an insulating material0

R θCS , THERMAL RESISTANCE (° C/W)

R θCS , THERMAL RESISTANCE (° C/W)(a) TO–204AA (TO–3)
Without Thermal Grease

3

(6)
(7)

0
1
2
3 4
5
6
MOUNTING SCREW TORQUE (IN-LBS)

0
1
2
3
4
5
6
MOUNTING SCREW TORQUE (IN-LBS)
0

R θCS , THERMAL RESISTANCE (° C/W)

R θCS , THERMAL RESISTANCE (° C/W)

2.0

5
4
3
(1)

2

(2)
(3)
(4)
(7)

1

0
0
1
2
3
4
5
6
MOUNTING SCREW TORQUE (IN-LBS)

0
1
2
4
5 6
3
MOUNTING SCREW TORQUE (IN-LBS)(c) TO–220
Without Thermal Grease(d) TO–220
With Thermal Grease

Data Courtesy of Thermalloy

http://onsemi.com
44

A number of manufacturers offer silicone rubber insulators. Table 5–2 shows measured performanceof a number of these insulators under carefully controlled, nearly identical conditions. The interface thermal
resistance extremes are over 2:1 for the various materials. It is also clear that some of the insulators aremuch more tolerant than others of out–of–flat surfaces. Since the tests were performed, newer products
have been introduced. The Bergquist K–10 pad, for example, is described as having about 2/3 the interface
resistance of the Sil Pad 1000 which would place its performance close to the Chomerics 1671 pad. AAVID
also offers an isolated pad called Rubber–Duc, however it is only available vulcanized to a heatsink andtherefore was not included in the comparison. Published data from AAVID shows RθCS below 0.3°C/W forpressures above 500 psi. However, surface flatness and other details are not specified so a comparison
cannot be made with other data in this note.
Table 5–2. Thermal Resistance of Silicone Rubber Pads
Manufacturer

Product

RθCS @ 3 Mils*

RθCS @ 7.5 Mils*

Wakefield
Bergquist
Stockwell Rubber
Bergquist
Thermalloy
Shin–Etsu
Bergquist
Chomerics
Wakefield
Bergquist
Ablestik
Thermalloy
Chomerics

Delta Pad 173–7
Sil Pad K–4
1867
Sil Pad 400–9
Thermalsil II
TC–30AGSil Pad 400–7
1674
Delta Pad 174–9
Sil Pad 1000
Thermal Wafers
Thermalsil III
1671

0.790
0.752
0.742
0.735
0.680
0.664
0.633
0.592
0.574
0.529
0.500
0.440
0.367

1.175
1.470
1.015
1.205
1.045
1.260
1.060
1.190
0.755
0.935
0.990
1.035
0.655

*Test Fixture Deviation from flat Thermalloy EIR86–1010.

The thermal resistance of some silicone rubber insulators is sensitive to surface flatness when used
under a fairly rigid base package. Data for a TO–204AA (TO–3) package insulated with Thermasil is shown
on Figure 5–8. Observe that the “worst case” encountered (7.5 mils) yields results having about twice thethermal resistance of the “typical case” (3 mils), for the more conductive insulator. In order for Thermasil
III to exceed the performance of greased mica, total surface flatness must be under 2 mils, a situation that
requires spot finishing.
Figure 5–8. Effect of Total Surface Flatness on Interface
Resistance Using Silicon Rubber Insulators

INTERFACE THERMAL RESISTANCE (° C/W)

1.2

1.0

(1)
(2)

0.8

0.6

0.4
(1) Thermalsil Il, 0.009 inches (0.23 mm) thick.
(2) Thermalsil Il, 0.006 inches (0.15 mm) thick.

0.2

0Data Courtesy of Thermalloy

0

0.002

0.004

0.006

0.008

TOTAL JOINT DEVIATION FROM FLAT OVER
TO-3 HEADER SURFACE AREA (INCHES)

http://onsemi.com
45

0.01

Silicon rubber insulators have a number of unusual characteristics. Besides being affected by surface
flatness and initial contact pressure, time is a factor. For example, in a study of the Cho–Therm 1688 padthermal interface impedance dropped from 0.90°C/W to 0.70°C/W at the end of 1000 hours. Most of thechange occurred during the first 200 hours where RθCS measured 0.74°C/W. The torque on theconventional mounting hardware had decreased to 3 in–lb from an initial 6 in–lb. With non–conformalmaterials, a reduction in torque would have increased the interface thermal resistance.
Because of the difficulties in controlling all variables affecting tests of interface thermal resistance, datafrom different manufacturers is not in good agreement. Table 5–3 shows data obtained from two sources.
The relative performance is the same, except for mica which varies widely in thickness. Appendix B
discusses the variables which need to be controlled. At the time of this writing ASTM Committee D9 isdeveloping a standard for interface measurements.
The conclusions to be drawn from all this data is that some types of silicon rubber pads, mounted dry,will out perform the commonly used mica with grease. Cost may be a determining factor in making
a selection.
Table 5–3. Performance of Silicon Rubber Insulators Tested per MIL–I–49456
Measured Thermal Resistance (°C/W)
Material

Thermalloy Data(1)Bergquist Data(2)Bare Joint, greased
BeO, greased
Cho–Therm, 1617
Q Pad (non–insulated)
Sil–Pad, K–10
Thermasil III

0.033
0.082
0.233
—
0.263
0.267

0.008
—
—
0.009
0.200
—

Mica, greased
Sil–Pad 1000
Cho–therm 1674
Thermasil II
Sil–Pad 400
Sil–Pad K–4

0.329
0.400
0.433
0.500
0.533
0.583

0.400
0.300
—
—
0.440
0.440

(1) From Thermalloy EIR 87–1030(2) From Bergquist Data Sheet

Insulation Resistance
When using insulators, care must be taken to keep the mating surfaces clean. Small particles of foreign
matter can puncture the insulation, rendering it useless or seriously lowering its dielectric strength. In
addition, particularly when voltages higher than 300 V are encountered, problems with creepage may
occur. Dust and other foreign material can shorten creepage distances significantly, so having a clean
assembly area is important. Surface roughness and humidity also lower insulation resistance. Use ofthermal grease usually raises the withstand voltage of the insulation system but excess must be removed
to avoid collecting dust. Because of these factors, which are not amenable to analysis, hi–pot testingshould be done on prototypes and a large margin of safety employed.
Insulated Electrode Packages
Because of the nuisance of handling and installing the accessories needed for an insulated
semiconductor mounting, equipment manufacturers have longed for cost–effective insulated packages
since the 1950s. The first to appear were stud mount types which usually have a layer of beryllium oxide
between the stud hex and the can. Although effective, the assembly is costly and requires manual
mounting and lead wire soldering to terminals on top of the case. In the late eighties, a number of electricallyisolated parts became available from various semiconductor manufacturers. These offerings presently
consist of multiple chips and integrated circuits as well as the more conventional single chip devices.
The newer insulated packages can be grouped into two categories. The first has insulation between
the semiconductor chips and the mounting base; an exposed area of the mounting base is used to secure
the part. The second category contains parts which have a plastic overmold covering the metal mounting
base. The Full Pak (Case 221C) illustrated in Figure 5–13, is an example of parts in the second category.
http://onsemi.com
46

Parts in the first category — those with an exposed metal flange or tab — are mounted the same astheir non–insulated counterparts. However, as with any mounting system where pressure is bearing onplastic, the overmolded type should be used with a conical compression washer, described later inthis note.

Fastener and Hardware Characteristics
Characteristics of fasteners, associated hardware, and the tools to secure them determine theirsuitability for use in mounting the various packages. Since many problems have arisen because of
improper choices, the basic characteristics of several types of hardware are discussed next.
Compression Hardware
Normal split ring lock washers are not the best choice for mounting power semiconductors. A typical#6 washer flattens at about 50 pounds, whereas 150 to 300 pounds is needed for good heat transfer at
the interface. A very useful piece of hardware is the conical, sometimes called a Belleville washer,compression washer. As shown in Figure 5–9, it has the ability to maintain a fairly constant pressure overa wide range of its physical deflection — generally 20% to 80%. When installing, the assembler applies
torque until the washer depresses to half its original height. (Tests should be run prior to setting up theassembly line to determine the proper torque for the fastener used to achieve 50% deflection.) The washer
will absorb any cyclic expansion of the package, insulating washer or other materials caused bytemperature changes. Conical washers are the key to successful mounting of devices requiring strict
control of the mounting force or when plastic hardware is used in the mounting scheme. They are usedwith the large face contacting the packages. A new variation of the conical washer includes it as part ofa nut assembly. Called a Sync Nut, the patented device can be soldered to a PC board and thesemiconductor mounted with a 6–32 machine screw.(4)Figure 5–9. Characteristics of the Conical Compression Washers Designed
for Use with Plastic Body Mounted Semiconductors

PRESSURE ON PACKAGE (LBF)

280
240
200
160
120
80
40
0

0

20

40

60

80

DEFLECTION OF WASHER DURING MOUNTING (%)_________________________________(4) ITW Shakeproof, St. Charles Road, Elgin, IL 60120.

http://onsemi.com
47

100

ClipsFast assembly is accomplished with clips. When only a few watts are being dissipated, the smallboard–mounted or free–standing heat dissipators with an integral clip, offered by several manufacturers,
result in a low cost assembly. When higher power is being handled, a separate clip may be used with larger
heatsinks. In order to provide proper pressure, the clip must be specially designed for a particular heatsink
thickness and semiconductor package.
Clips are especially popular with plastic packages such as the TO–220 and TO–126. In addition to fast
assembly, the clip provides lower interface thermal resistance than other assembly methods when it isdesigned for proper pressure to bear on the top of the plastic over the die. The TO–220 package usuallyis lifted up under the die location when mounted with a single fastener through the hole in the tab becauseof the high pressure at one end.
Machine Screws
Machine screws, conical washers, and nuts (or Sync Nut) can form a trouble–free fastener system for
all types of packages which have mounting holes. However, proper torque is necessary. Torque ratings
apply when dry; therefore, care must be exercised when using thermal grease to prevent it from getting
on the threads as inconsistent torque readings result. Machine screw heads should not directly contact thesurface of plastic packages types as the screw heads are not sufficiently flat to provide properly distributed
force. Without a washer, cracking of the plastic case may occur.
Self–Tapping Screws
Under carefully controlled conditions, sheet metal screws are acceptable. However, during the tapping
process with a standard screw, a volcano–like protrusion will develop in the metal being threaded; anunacceptable surface that could increase the thermal resistance may result. When standard sheet metalscrews are used, they must be used in a clearance hole to engage a speed nut. If a self–tapping process
is desired, the screw type must be used which roll–forms machine screw threads.
RivetsRivets are not recommended fasteners for any of the plastic packages. When a rugged metal
flange–mount package is being mounted directly to a heatsink, rivets can be used provided press–rivetingis used. Crimping force must be applied slowly and evenly. Pop–riveting should never be used because
the high crimping force could cause deformation of most semiconductor packages. Aluminum rivets aremuch preferred over steel because less pressure is required to set the rivet and thermal conductivity
is improved.
The hollow rivet, or eyelet, is preferred over solid rivets. An adjustable, regulated pressure press is usedsuch that a gradually increasing pressure is used to pan the eyelet. Use of sharp blows could damage thesemiconductor die.
Solder
Until the advent of the surface mount assembly technique, solder was not considered a suitable
fastener for power semiconductors. However, user demand has led to the development of new packages
for this application. Acceptable soldering methods include conventional belt–furnace, irons, vapor–phase
reflow, and infrared reflow. It is important that the semiconductor temperature not exceed the specified
maximum (usually 260°C) or the die bond to the case could be damaged. A degraded die bond has
excessive thermal resistance which often leads to a failure under power cycling.

http://onsemi.com
48

Adhesives
Adhesives are available which have coefficients of expansion compatible with copper and aluminum.(5)Highly conductive types are available; a 10 mil layer has approximately 0.3°C/W interface thermal
resistance. Different types are offered: high strength types for non–field–serviceable systems or low
strength types for field–serviceable systems. Adhesive bonding is attractive when case mounted parts areused in wave soldering assembly because thermal greases are not compatible with the conformal coatings
used and the greases foul the solder process.
Plastic Hardware
Most plastic materials will flow, but differ widely in this characteristic. When plastic materials form partsof the fastening system, compression washers are highly valuable to assure that the assembly will not
loosen with time and temperature cycling. As previously discussed, loss of contact pressure will increaseinterface thermal resistance.
Fastening Techniques
Each of the various classes of packages in use requires different fastening techniques. Details
pertaining to each type are discussed in following sections. Some general considerations follow.
To prevent galvanic action from occurring when devices are used on aluminum heatsinks in a corrosive
atmosphere, many devices are nickel or gold–plated. Consequently, precautions must be taken not to mar
the finish.
Another factor to be considered is that when a copper based part is rigidly mounted to an aluminumheatsink, a bimetallic system results which will bend with temperature changes. Not only is the thermal
coefficient of expansion different for copper and aluminum, but the temperature gradient through eachmetal also causes each component to bend. If bending is excessive and the package is mounted by two
or more screws the semiconductor chip could be damaged. Bending can be minimized by:
1. Mounting the component parallel to the heatsink fins to provide increased stiffness.
2. Allowing the heatsink holes to be a bit oversized so that some slip between surfaces canoccur as temperature changes.
3. Using a highly conductive thermal grease or mounting pad between theheatsink and semiconductor to minimize the temperature gradient and allow for movement.
Flange Mount
Few known mounting difficulties exist with the smaller flange mount packages, such as the TO–204(TO–3). The rugged base and distance between die and mounting hose combine to make it extremely
difficult to cause any warpage unless mounted on a surface which is badly bowed or unless one side istightened excessively before the other screw is started. It is therefore good practice to alternate tighteningof the screws so that pressure is evenly applied. After the screws are finger–tight the hardware should betorqued to its final specification in at least two sequential steps. A typical mounting installation for a popularflange type part is shown in Figure 5–10. Machine screws (preferred), self–tapping screws, islets or rivets
may be used to secure the package using guidelines in the previous section, Fastener and Hardware
Characteristics.

___________________________________(5) Robert Batson, Elliot Fraunglass and James P. Moran, Heat Dissipation Through Thermalloy Conductive Adhesives, EMTAS ’83 Conference,
February 1–3, Phoenix, AZ; Society of Manufacturing Engineers, One SME Drive, P.O. Box 930, Dearborn, MI 48128.

http://onsemi.com
49

Figure 5–10. Hardware Used for a TO–204AA (TO–3) Flange Mount PartNo. 6 Sheet Metal Screw

Power
Transistor
Insulator

Insulating
Bushing
Heatsink

SocketTab Mount
The tab mount class is composed of a wide array of packages as illustrated in Figure 5–11. Mounting
considerations for all varieties are similar to that for the popular TO–220 package, whose suggested
mounting arrangements and hardware are shown in Figure 5–12. The rectangular washer shown in Figure
5–12a is used to minimize distortion of the mounting flange; excessive distortion could cause damage tothe semiconductor chip. Use of the washer is only important when the size of the mounting hole exceeds
0.140 inch (6–32 clearance). Larger holes are needed to accommodate the lower insulating bushing when
the screw is electrically connected to the case; however, the holes should not be larger than necessary
to provide hardware clearance and should never exceed a diameter of 0.250 inch. Flange distortion is also
possible if excessive torque is used during mounting. A maximum torque of 8 inch–pounds is suggested
when using a 6–32 screw.
Care should be exercised to assure that the tool used to drive the mounting screw never comes incontact with the plastic body during the driving operation. Such contact can result in damage to the plastic
body and internal device connections. To minimize this problem, ON Semiconductor TO–220 packages
have a chamfer on one end. TO–220 packages of other manufacturers may need a spacer or combination
spacer and isolation bushing to raise the screw head above the top surface of the plastic.

http://onsemi.com
50

The popular TO–220 package and others of similar construction lift off the mounting surface aspressure is applied to one end. (See Appendix B, Figure B1.) To counter this tendency, at least one
hardware manufacturer offers a hard plastic cantilever beam which applies more even pressure on thetab.(6) In addition, it separates the mounting screw from the metal tab. Tab mount parts may also be
effectively mounted with clips as shown in Figure 5–14(c). To obtain high pressure without cracking thecase, a pressure spreader bar should be used under the clip. Interface thermal resistance with thecantilever beam or clips can be lower than with screw mounting.
Figure 5–11. Several Types of Tab Mounted Parts

CASE 221A(TO–220AB)

CASE 314D

CASE 340(TO–218)

Figure 5–12. Mounting Arrangements for Tab Mount TO–220b)Alternate Arrangement for Isolated Mounting when Screwb)must be at Heatsink Potential. 4-40 Hardware is Used.

a)Preferred Arrangement for Isolated or Non-isolated Mounting. Screwa)is at Semiconductor Case Potential. 6-32 Hardware is Used.

Use Parts Listed Below.

Choose from Parts Listed Below.

4-40 Pan or Hex Head Screw
6-32 Hex
Head Screw
Flat Washer
Insulating Bushing(1) Rectangular Steel
WasherSemiconductor(Case 221, 221A)

Semiconductor(Case 221,221A)(2) Rectangular
Insulator
Heatsink

Rectangular
Insulator
Heatsink(2) Bushing(3) Flat Washer

Compression Washer(4) Conical Washer(1)Used with thin chassis and/or large hole.
(2)Used when isolation is required.
(3)Required when nylon bushing is used.

4-40 Hex Nut

6-32 Hex Nut___________________________________(6) Catalog, Edition 18, Richco Plastic Company, 5825 N. Tripp Ave., Chicago, IL 60546.

http://onsemi.com
51

Plastic Body Mount
The Full Pak plastic power packages shown in Figure 5–13 are typical of packages in this group. They
have been designed to feature minimum size with no compromise in thermal resistance.
The Full Pak (Case 221C) is similar to a TO–220 except that the tab is encased in plastic. Because
the mounting force is applied to plastic, the mounting procedure differs from a standard TO–220 and issimilar to that of the Thermopad.
Several types of fasteners may be used to secure these packages; machine screws, eyelets, or clips
are preferred. With screws or eyelets, a conical washer should be used which applies the proper force tothe package over a fairly wide range of deflection and distributes the force over a fairly large surface area.
Screws should not be tightened with any type of air–driven torque gun or equipment which may cause highimpact. Characteristics of a suitable conical washer is shown in Figure 5–9.
The Full Pak (Case 221C, 221D and 340B) permits the mounting procedure to be greatly simplified overthat of a standard TO–220. As shown in Figure 5–14(c), one properly chosen clip, inserted into two slottedholes in the heatsink, is all the hardware needed. Even though clip pressure is much lower than obtainedwith a screw, the thermal resistance is about the same for either method. This occurs because the clip
bears directly on top of the die and holds the package flat while the screw causes the package to lift up
somewhat under the die. (See Figure B1 of Appendix B.) The interface should consist of a layer of thermal
grease or a highly conductive thermal pad. Of course, screw mounting shown in Figure 5–14(b) may also
be used but a conical compression washer should be included. Both methods afford a major reduction in
hardware as compared to the conventional mounting method with a TO–220 package which is shown in
Figure 5–14(a).
Figure 5–13. Plastic Body Mounted Packages

CASE 221C(Full Pak)

CASE 221D(Full Pak)

CASE 340B(Full Pak)

Figure 5–14. Mounting Arrangements for the Full Pak
as Compared to a Conventional TO–220ÇÇÇ

4-40 Screw

Plain Washer
Insulating Bushing

Insulator
Heatsink
Threaded SideÇÇ
Ç

6-32 Screw
Plain Washer

Clip

Heatsink

Compression Washer

Compression Washer

Heatsink

NutNut(a) Screw Mounted
TO–220(b) Screw Mounted
Full Pak

http://onsemi.com
52(c) Clip Mounted
Full Pak

Surface Mount
Although many of the tab mount parts have been surface mounted, special small footprint packages
for mounting power semiconductors using surface mount assembly techniques have been developed. The
DPAK, shown in Figure 5–15, for example, will accommodate a die up to 112 mils × 112 mils, and has atypical thermal resistance around 2°C/W junction to case. The thermal resistance values of the solderinterface is well under 1°C/W. The printed circuit board also serves as the heatsink.
Standard glass–epoxy 2 oz. boards do not make very good heatsinks because the thin foil has a highthermal resistance. As Figure 5–16 shows, thermal resistance assymtotes to about 20°C/W at 10 square
inches of board area, although a point of diminishing returns occurs at about 3 square inches.
Boards are offered that have thick aluminum or copper substrates. A dielectric coating designed for
low thermal resistance is overlayed with one or two ounce copper foil for the preparation of printed
conductor traces. Tests run on such a product indicate that case to substrate thermal resistance is in thevicinity of 1°C/W, exact values depending upon board type.(7) The substrate may be an effective heatsink
itself, or it can be attached to a conventional finned heatsink for improved performance.
Since DPAK and other surface mount packages are designed to be compatible with surface mountassembly techniques, no special precautions are needed other than to insure that maximum
temperature/time profiles are not exceeded.
Figure 5–15. Surface Mounted DPAK Packages

CASE 369

CASE 369A

JUNCTIONTOAIR (° C/W)

R θ JA, THERMAL RESISTANCE

100
90

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ

80
Minimum
Size Pad

70
60

2.0

2.0 oz. Copper
L

1.6

L

1.2
0.8

50
40

2.4

PD(max) for TA = 50°C

Free Air
Mounted
Vertically

0.4

RθJA
0

5.0

10

15

20

25

30

PD, MAXIMUM POWER DISSIPATION (W)

Figure 5–16. Effect of Footprint Area on Thermal Resistanceof DPAK Mounted on a Glass–Epoxy Board

0

L, LENGTH OF COPPER (mm)___________________________________(7) Herb Fick, Thermal Management of Surface Mount Power Devices, Powerconversion and Intelligent Motion, August 1987.

http://onsemi.com
53

Free Air and Socket Mounting
In applications where average power dissipation is on the order of a watt or so, most power
semiconductors may be mounted with little or no heatsinking. The leads of the various metal power
packages are not designed to support the packages; their cases must be firmly supported to avoid thepossibility of cracked seals around the leads. Many plastic packages may be supported by their leads inapplications where high shock and vibration stresses are not encountered and where no heatsink is used.
The leads should be as short as possible to increase vibration resistance and reduce thermal resistance.
As a general practice however, it is better to support the package. A plastic support for the TO–220
Package and other similar types is offered by heatsink accessory vendors.
In certain situations, in particular where semiconductor testing is required or prototypes arebeing developed, sockets are desirable. Manufacturers have provided sockets for many of the
packages available from ON Semiconductor. The user is urged to consult manufacturers’ catalogs for
specific details. Sockets with Kelvin connections are necessary to obtain accurate voltage readings
across semiconductor terminals.
Connecting and Handling Terminals
Pins, leads, and tabs must be handled and connected properly to avoid undue mechanical stress which
could cause semiconductor failure. Change in mechanical dimensions as a result of thermal cycling over
operating temperature extremes must be considered. Standard metal, plastic, and RF stripline packages
each have some special considerations.
Metal Packages
The pins of metal packaged devices using glass to metal seals are not designed to handle any
significant bending or stress. If abused, the seals could crack. Wires may be attached using sockets, crimp
connectors or solder, provided the data sheet ratings are observed. When wires are attached directly tothe pins, flexible or braided leads are recommended in order to provide strain relief.
Plastic Packages
The leads of the plastic packages are somewhat flexible and can be reshaped although this is not arecommended procedure. In many cases, a heatsink can be chosen which makes lead–bending
unnecessary. Numerous lead and tab–forming options are available from ON Semiconductor on large
quantity orders. Preformed leads remove the users risk of device damage caused by bending.
If, however, lead–bending is done by the user, several basic considerations should be observed. Whenbending the lead, support must be placed between the point of bending and the package. For forming small
quantities of units, a pair of pliers may be used to clamp the leads at the case, while bending with the fingers
or another pair of pliers. For production quantities, a suitable fixture should be made.
The following rules should be observed to avoid damage to the package.
1. A leadbend radius greater than 1/32 inch for TO–220.
2. No twisting of leads should be done at the case.
3. No axial motion of the lead should be allowed with respect to the case.
The leads of plastic packages are not designed to withstand excessive axial pull. Force in this direction
greater than 4 pounds may result in permanent damage to the device. If the mounting arrangement
imposes axial stress on the leads, a condition which may be caused by thermal cycling, some method ofstrain relief should be devised. When wires are used for connections, care should be exercised to assurethat movement of the wire does not cause movement of the lead at the lead–to–plastic junctions. Highly
flexible or braided wires are good for providing strain relief.
Wire wrapping of the leads is permissible, provided that the lead is restrained between the plastic caseand the point of the wrapping. The leads may be soldered; the maximum soldering temperature, however,must not exceed 260°C and must be applied for not more than 5 seconds at a distance greater than 1/8
inch from the plastic case.

http://onsemi.com
54

Cleaning Circuit Boards
It is important that any solvents or cleaning chemicals used in the process of degreasing or flux removal
do not affect the reliability of the devices. Alcohol and unchlorinated freon solvents are generally
satisfactory for use with plastic devices, since they do not damage the package. Hydrocarbons such as
gasoline and chlorinated freon may cause the encapsulant to swell, possibly damaging the transistor die.
When using an ultrasonic cleaner for cleaning circuit boards, care should be taken with regard toultrasonic energy and time of application. This is particularly true if any packages are free–standing
without support.

Thermal System Evaluation
Assuming that a suitable method of mounting the semiconductor without incurring damage has beenachieved, it is important to ascertain whether the junction temperature is within bounds.
In applications where the power dissipated in the semiconductor consists of pulses at a low duty cycle,
the instantaneous or peak junction temperature, not average temperature, may be the limiting condition.
In this case, use must be made of transient thermal resistance data. For a full explanation of its use, see
ON Semiconductor Application Note, AN569.
Other applications, notably switches driving highly reactive loads, may create severe current crowding
conditions which render the traditional concepts of thermal resistance or transient thermal impedance
invalid. In this case, transistor safe operating area, thyristor di/dt limits, or equivalent ratings as applicable,
must be observed.
Fortunately, in many applications, a calculation of the average junction temperature is sufficient. It isbased on the concept of thermal resistance between the junction and a temperature reference point on
the case. (See Appendix A.) A fine wire thermocouple should be used, such as #36 AWG, to determine
case temperature. Average operating junction temperature can be computed from the following equation:
TJ = TC + RθJC × PD
where, TJ = junction temperature (°C),
TC = case temperature (°C),
RθJC = thermal resistance junction–to–case as specified on the data sheet (°C/W),
PD = power dissipated in the device (W).
The difficulty in applying the equation often lies in determining the power dissipation. Two commonlyused empirical methods are graphical integration and substitution.
Graphical Integration
Graphical integration may be performed by taking oscilloscope pictures of a complete cycle of thevoltage and current waveforms, using a limit device. The pictures should be taken with the temperaturestabilized. Corresponding points are then read from each photo at a suitable number of time increments.
Each pair of voltage and current values are multiplied together to give instantaneous values of power. The
results are plotted on linear graph paper, the number of squares within the curve counted, and the total
divided by the number of squares along the time axis. The quotient is the average power dissipation.
Oscilloscopes are available to perform these measurements and make the necessary calculations.
Substitution
This method is based upon substituting an easily measurable, smooth dc source for a complex
waveform. A switching arrangement is provided which allows operating the load with the device under test,
until it stabilizes in temperature. Case temperature is monitored. By throwing the switch to the “test”
position, the device under test is connected to a dc power supply, while another pole of the switch supplies
the normal power to the load to keep it operating at full power level. The dc supply is adjusted so that thesemiconductor case temperature remains approximately constant when the switch is thrown to eachposition for about 10 seconds. The dc voltage and current values are multiplied together to obtain average
power. It is generally necessary that a Kelvin connection be used for the device voltage measurement.

http://onsemi.com
55

Appendix A
Thermal Resistance Concepts
The basic equation for heat transfer under steady–state conditions is generally written as:
q = hA∆T(1)
where, q = rate of heat transfer or power dissipation (PD),h = heat transfer coefficient,
A = area involved in heat transfer,∆T = temperature difference between regions of heat transfer.
However, electrical engineers generally find it easier to work in terms of thermal resistance, definedas the ratio of temperature to power. From Equation 1, thermal resistance (Rθ) is(2)Rθ = ∆T/q = 1/hA
The coefficient (h) depends upon the heat transfer mechanism used and various factors involved in thatparticular mechanism.
An analogy between Equation 2 and Ohm’s Law is often made to form models of heat flow. Note that
T could be thought of as a voltage thermal resistance corresponds to electrical resistance (R); and, power(q) is analogous to current (I). This gives rise to a basic thermal resistance model for a semiconductor as
indicated by Figure A–1.
Figure A–1. Basic Thermal Resistance Model Showing Thermal
to Electrical Analogy for a Semiconductor(TJ) Junction TemperatureDie

ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉ
Insulators

Heatsink

Flat Washer

RθJC(TC) Case Temperature

PD

RθCS
(TS) Heatsink
Temperature
RθSA(TA) Ambient
Temperature

Solder Terminal
Nut

Reference Temperature

The equivalent electrical circuit may be analyzed by using Kirchoff’s Law and the following
equation results:(3)
TJ = PD(RθJC + RθCS + RθSA) + TA
where, TJ = junction temperature,
PD = power dissipation,
RθJC = semiconductor thermal resistance (junction–to–case),
RθCS = interface thermal resistance (case–to–heatsink),
RθSA = heatsink thermal resistance (heatsink–to–ambient),
TA = ambient temperature.
The thermal resistance junction–to–ambient is the sum of the individual components. Each component
must be minimized if the lowest junction temperature is to result.
The value for the interface thermal resistance (RθCS) may be significant compared to the other thermal
resistance terms. A proper mounting procedure can minimize RθCS.

http://onsemi.com
56

The thermal resistance of the heatsink is not absolutely constant; its thermal efficiency increases asambient temperature increases and it is also affected by orientation of the sink. The thermal resistance ofthe semiconductor is also variable; it is a function of biasing and temperature. Semiconductor thermal
resistance specifications are normally at conditions where current density is fairly uniform. In some
applications such as in RF power amplifiers and short–pulse applications, current density is not uniform
and localized heating in the semiconductor chip will be the controlling factor in determining power
handling ability.

Appendix B
Measurement of Interface Thermal Resistance
Measuring the interface thermal resistance RθCS appears deceptively simple. All that’s apparently
needed is a thermocouple on the semiconductor case, a thermocouple on the heatsink, and a means ofapplying and measuring dc power. However, RθCS is proportional to the amount of contact area between
the surfaces and consequently is affected by surface flatness and finish and the amount of pressure on
the surfaces. The fastening method may also be a factor. In addition, placement of the thermocouples canhave a significant influence upon the results. Consequently, values for interface thermal resistancepresented by different manufacturers are not in good agreement. Fastening methods and thermocouple
locations are considered in this Appendix.
When fastening the test package in place with screws, thermal conduction may take place through thescrews, for example, from the flange ear on a TO–204AA package directly to the heatsink. This shunt pathyields values which are artificially low for the insulation material and dependent upon screw head contact
area and screw material. MIL–I–49456 allows screws to be used in tests for interface thermal resistanceprobably because it can be argued that this is “application oriented”.
Thermalloy takes pains to insulate all possible shunt conduction paths in order to more accurately
evaluate insulation materials. The ON Semiconductor fixture uses an insulated clamp arrangement tosecure the package which also does not provide a conduction path.
As described previously, some packages, such as a TO–220, may be mounted with either a screw
through the tab or a clip bearing on the plastic body. These two methods often yield different values forinterface thermal resistance. Another discrepancy can occur if the top of the package is exposed to theambient air where radiation and convection can take place. To avoid this, the package should be covered
with insulating foam. It has been estimated that a 15% to 20% error in RθCS can be incurred fromthis source.
Another significant cause for measurement discrepancies is the placement of the thermocouple tomeasure the semiconductor case temperature. Consider the TO–220 package shown in Figure B–1. The
mounting pressure at one end causes the other end — where the die is located — to lift off the mounting
surface slightly. To improve contact, ON Semiconductor TO–220 Packages are slightly concave. Use ofa spreader bar under the screw lessens the lifting, but some is inevitable with a package of this structure.
B–1. JEDEC TO–220 Package Mounted to Heatsink Showing Various
Thermocouple Locations and Lifting Caused by Pressure at One End
Die

E.I.A.
ThermalloyÇÇÇÇÇÇÇÉÉ
ÉÉÉÉÉÉÉÉÇÇÇÇÇÇÇÉÉ ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉON Semiconductor

http://onsemi.com
57

Three thermocouple locations are shown.
a) The ON Semiconductor location is directly under the die reached through a hole in the heatsink. The
thermocouple is held in place by a spring which forces the thermocouple into intimate contact with thebottom of the semi’s case.
b) The JEDEC location is close to the die on the top surface of the package base reached through ablind hole drilled through the molded body. The thermocouple is swaged in place.
c) The Thermalloy location is on the top portion of the tab between the molded body and the mounting
screw. The thermocouple is soldered into position.
Temperatures at the three locations are generally not the same. Consider the situation depicted in
Figure B–1. Because the only area of direct contact is around the mounting screw, nearly all the heat travels
horizontally along the tab from the die to the contact area. Consequently, the temperature at the JEDEC
location is hotter than at the Thermalloy location and the ON Semiconductor location is even hotter. Since
junction–to–sink thermal resistance must be constant for a given test setup, the calculated
junction–to–case thermal resistance values decrease and case–to–sink values increase as the casetemperature thermocouple readings become warmer. Thus the choice of reference point for the casetemperature is quite important.
There are examples where the relationship between the thermocouple temperatures are different fromthe previous situation. If a mica washer with grease is installed between the semiconductor package andthe heatsink, tightening the screw will not bow the package; instead, the mica will be deformed. The primaryheat conduction path is from the die through the mica to the heatsink. In this case, a small temperaturedrop will exist across the vertical dimension of the package mounting base so that the thermocouple at the
EIA location will be the hottest. The thermocouple temperature at the Thermalloy location will be lower but
close to the temperature at the EIA location as the lateral heat flow is generally small. The ON
Semiconductor location will be coolest.
The EIA location is chosen to obtain the highest temperature on the case. It is of significance because
power ratings are supposed to be based on this reference point. Unfortunately, the placement of thethermocouple is tedious and leaves the semiconductor in a condition unfit for sale.
The ON Semiconductor location is chosen to obtain the highest temperature of the case at a point
where, hopefully, the case is making contact to the heatsink. Once the special heatsink to accommodate
the thermocouple has been fabricated, this method lends itself to production testing and does not markthe device. However, this location is not easily accessible to the user.
The Thermalloy location is convenient and is often chosen by equipment manufacturers. However, italso blemishes the case and may yield results differing up to 1°C/W for a TO–220 package mounted toa heatsink without thermal grease and no insulator. This error is small when compared to the thermal
resistance of heat dissipaters often used with this package, since power dissipation is usually a few watts.
When compared to the specified junction–to–case values of some of the higher power semiconductors
becoming available, however, the difference becomes significant and it is important that the semiconductor
manufacturer and equipment manufacturer use the same reference point.
Another EIA method of establishing reference temperatures utilizes a soft copper washer (thermal
grease is used) between the semiconductor package and the heatsink. The washer is flat to within
1.0 mil/inch, has a finish better than 63 µin., and has an imbedded thermocouple near its center. Thisreference includes the interface resistance under nearly ideal conditions and is therefore
application–oriented. It is also easy to use but has not become widely accepted.
A good way to improve confidence in the choice of case reference point is to also test forjunction–to–case thermal resistance while testing for interface thermal resistance. If the junction–to–casevalues remain relatively constant as insulators are changed, torque varied, etc., then the case reference
point is satisfactory.

http://onsemi.com
58

SECTION 6
LINEAR REGULATOR DESIGN EXAMPLEAs an illustration of the use of the material contained in the preceding sections, the following regulator
design example is given.
Regulator Performance Requirements:
Output Voltage, VO = +10 V ± 0.1 V
Output Current, IO = 1.0 A, current limited
Load Regulation, ≤ 0.1% for IO = 10 mA to 750 mA
Line Regulation, ≤ 0.1%
Output ripple, ≤ 2.0 mVpp
Max Ambient Temperature, TA ≤ +70°C
Supply will have common loads to a negative supply.

1. IC Regulator Selection
Study of the available regulators given in the selection guide reveals that the MC1723C would meetthe regulation performance requirements. This regulator must be current boosted to obtain the required
1.0 A output current. A rough cost estimate shows that an MC1723C series pass element combination is
the most economical approach.

2. Circuit Configuration
In Section 3, an appropriate circuit configuration is found. This is the MC1723C NPN boost
configuration of Figure 3–4A.

3. Determination of Component Values
Using the equations given in Figure 3–4A, the values of Cref, R1, R2, R3 and RSC are determined.
a) Cref is chosen to be 0.1 µF for low noise operation.
b) R1 + R2 is chosen to be ≈ 10 k.
c) R2 is then given by: R2 ≈7.0 V
(R1 + R2) = 0.7 (10 k) = 7.0 k
VOd) Since Vref can vary by as much as ± 5% for the MC1723C, R2 should be made variable by at leastthat much, so that VO can be set to the required value of +10 V ± 0.1 V. R2 is therefore chosen to
consist of a 62 k resistor and a 2.0 k trimpot.
e) R1 = 10 k – R2 = 10 k – 7.0 k = 3.0 kf) RSC ≈0.6 V 0.6 V= 0.6 Ω; 0.56 Ω, 1.0 W chosen for RSC.
=
ISC
1.0 A

g) R3 = R1 R2 ≅ 2.2 k

http://onsemi.com
59

4. Determination of Input Voltage (Vin)
There are two basic constraints on the input voltage: 1) the device limits for minimum and maximum
Vin and, 2) the minimum input–output voltage differential. These limits are found on the device data sheet
to be:
9.5 V ≤ Vin ≤ 40 V and (Vin – VO) ≥ 3.0 V
For the configuration of Figure 3–5A, (Vin – VO) is given by:(Vin – VO) = [Vin – (VO + 2φ)] ≥ 3.0 V, where φ = VBEon ≈ 0.6 V
Note that (Vin – VO) is defined on the device data sheet to be the differential between the input and output
pins. Since the base–emitter junction drops of Q1 and RSC have been added to the circuit, they must be
added to the minimum value of (Vin – VO). Therefore,
Vin ≥ VO + 2φ + 3.0 V = 10 + 1.2 + 3
Vin ≥ 14.2 V
This condition also satisfies the requirement for a minimum Vin of 9.5 V.
In order to simplify the design of the input supply (see Section 8), Vin is chosen to be 16 V average with
a 3.0 Vpp ripple at full load and up to 25 V at no load. This assures that the input voltage is always above
the required minimum value of 14.2 V. Now, the output ripple can be determined. The MC1723C has atypical ripple rejection ratio of –74 db, as given on its data sheet. With an input ripple of 3.0 Vpp, the output
ripple would be less than 1.0 mVpp, which meets the regulator output ripple requirements.

5. Selection of the Series Pass Element (Q1)
The transistor type chosen for Q1 must have the following characteristics (see Section 4):a) VCEO ≥ Vin(max)b) IC(max) ≥ ISC
ISC@ VCE = Vin – VO – φ, where φ = VBEon  0.6 Vc) hfe ≥ IOd) PD(max) ≥ Vin, × ISCe) θJC such to allow practical heatsinkingf) SOA such that it can withstand VCE = Vin @ IC = ISC
For this example: VCEO ≥ 25 V
IC(max) ≥ 1.0 A
hfe ≥ 25 @ VCE = 5.0 V @ IC = 1.0 A
PD(max) ≥ 16 W
θJC = 1.52°C/W
SOA = 1.0 A @ 16 V
A 2N3055 transistor is chosen as a suitable device for Q1 using the selection guide of Section 4 and thetransistor data sheets (available from the device manufacturer).

http://onsemi.com
60

6. Q1 Heatsink Calculation
TJ = TA + PD θJA
where, PD = Vin × ISC
θJA = θJC + θCS + θSA(Equation 15.1 from Section 15)(Equation 6.2)

Solving for θSA:

θSA =TJ –TA
PD– (θJC + θCS)

(6.2)

From the 2N3055 data sheet, TJ = 200°C and θJC = 1.52°C/W. The transistor will be mounted with thermal
grease directly to the heatsink. Therefore, θCS is found to be 0.1°C/W from Table 15–1.
Solving for Equation 6.2:
θSA =200°C – 70°C
– (1.52 + 0.1) °C/W
16 V × 1.0 A≤ 6.6°C/W

A commercial heatsink is now chosen from Table 15–2 or one custom designed using the methods given
in Section 15. For this example, a Thermalloy #6003 heatsink, having a θCS of 6.2°C/W, was used.

7. Clamp Diode
Since the regulator can power a load which is also connected to a negative supply, a 1N4001 diodeis connected to the output for protection. The complete circuit schematic is shown in Figure 6–1.
Figure 6–1. 10 V, 1.0 A Design Example
2N3055 on
Thermalloy #6003

2

MC1723CL
6

VBE

IO

11

R3
2.2k

VBE

10

12

VO = +10 V, 1.0 A
RSC

Q1
Vin = +16 V

0.56, 1.0W

3

θJA = 150°C/W

3.0k

4

R1

5
0.1µF

Cref

13

100pF

7

R2
2.0k
6.2k

8. Construction Input Supply Design
The input supply is now designed using the information contained in Section 8 and the regulator circuit
is constructed using the guidelines given in Section 5.

http://onsemi.com
61

SECTION 7
LINEAR REGULATOR CIRCUIT
TROUBLESHOOTING CHECKLIST
Occasionally, the designer’s prototype regulator circuit will not operate properly. If problems do occur,
the trouble can be traced to a design error in 99.9% of the cases. As a troubleshooting aid to the designer,
the following guide is presented.
Of course, it would be difficult, if not impossible, to devise a troubleshooting guide which would cover
all possible situations. However, the checklist provided will help the designer pinpoint the problem in the
majority of cases. To use the guide, first locate the problem’s symptom(s) and then carefully recheck theregulator design in the area indicated using the information contained in the referenced handbook section.
If, after carefully rechecking the circuit, the designer is not successful in resolving the problem, seek
assistance from the factory by contacting the nearest ON Semiconductor Sales office.
Symptoms

Design Area to Check

SectionRegulator oscillates

1. Layout
2. Compensation capacitor too small
3. Input leads not bypassed
4. External pass element parasitically oscillating

5
3
5
5

Loss of regulation at light loads

1. Emitter–base resistor in “PNP” type boost configuration too large
2. Absence of 1.0 mA ‘‘minimum’’ load.
(See load regulation test spec on device data sheet)
3. Improper circuit configuration

4

Loss of regulation at heavy loads

1. Input voltage too low [Vin(min), |Vin – VO|min]
2. External pass element gain too low
3. Current limit too low
4. Line resistance between sense points and load
5. Inadequate heatsinking

2, 3
4
3
5
15

IC regulator or pass element fails
after warm–up or at high TA.

1. Inadequate heatsinking
2. Input Voltage Transient Vin(max), VCEO

15
2, 4, 5

Pass element fails during shortcircuit.

1. Insufficient pass element ratings SOA, IC(max)
2. Inadequate heatsinking

415

IC regulator fails during shortcircuit.

1. IC current or SOA capability exceeded
2. Inadequate heatsinking

2

1. Input voltage transient Vin(max)22

IC regulator fails during power–up

2. IC current or SOA capability exceeded as load (capacitor)

3

is charged up.

IC regulator fails during
power–down.

1. Regulator reverse biased

3

Output voltage does not come up
during power–up or after
short circuit

1. Out polarity reversal
2. Load has ‘‘latched–up’’ in some manner.
(Usually seen with op amps, current sources, etc.)

3

Excessive 60 Hz or 120 Hz
output ripple

1. Input supply filter capacitor ground loop5

http://onsemi.com
62

SECTION 8
DESIGNING THE INPUT SUPPLY
Most input supplies used to power series pass regulator circuits consist of a 60 Hz, single phasestep–down transformer followed by a rectifier circuit whose output is smoothed by a choke or capacitor
input filter. The type of rectifier circuit used can be either a half–wave, full–wave, or full–wave bridge type,as shown in Figure 8–1. The half–wave circuit is used in low current applications, while the full–wave ispreferable in high–current, low output voltage cases. The full–wave bridge is usually used in all otherhigh–current applications.
Figure 8–1. Rectification Schemes(a) Half–Wave(b) Full–Wave or Full–Wave Center Tap(c) Full–Wave Bridge

In this section, specification of the filter capacitor, rectifier and transformer ratings will be discussed.
The specifications for the choke input filter will not be considered since the simpler capacitor input type ismore commonly used in series regulated circuits. A detailed description of this type of filter can be foundin the reference listed at the end of this section.

http://onsemi.com
63

1. Design of Capacitor–Input Filters
The best practical procedure for the design of capacitor–input filters still remains based on thegraphical data presented by Schade(1) in 1943. The curves shown in Figures 8–2 through 8–5 give all therequired design information for half–wave and full–wave rectifier circuits. Whereas Schade originally also
gave curves for the impedance of vacuum–tube rectifiers, the equivalent values for semiconductor diodes
must be substituted. However, the rectifier forward drop often assumes more significance than the dynamic
resistance in low–voltage supply applications, as the dynamic resistance can generally be neglected whencompared with the sum of the transformer secondary–winding resistance plus the reflectedprimary–winding resistance. The forward drop may be of considerable importance, however, since it isabout 1.0 V, which clearly cannot be ignored in supplies of 12 V or less.

Figure 8–2. Relation of Applied Alternating Peak Voltage to Direct Output Voltage
in Half–Wave Capacitor–Input Circuits
100

0.05
0.5
1
2

RS

90
VM

C

VC

RL

4

80

% VC(DC) / VM

60

20
25
30
35
40
50
60
70
80
90
100

50
40
30
20
10
0

0.1

1.0

10
ωCRL

ω = 2 π f, f = Line Frequency
C in Farads
RL in Ohms________________________________(1)From O. H. Schade, Proc. IRE, Vol. 31, p. 356, 1943.

http://onsemi.com
64

100

1000

% RS /R L

6
8
10
12.5
15

70

Figure 8–3. Relation of Applied Alternating Peak Voltage to
Direct Output Voltage in Full–Wave Capacitor–Input Circuits
0.05
0.1
0.5
1

100

90

VM

RS

VM

RS

Full-Wave
C VC

RL

2
4

Full-Wave
Bridge

6

80

8
12.5
15

70

20

60

25

% RS /R L% VC(DC) / VM

10

30
35
40

50

50
60
70

40

30

80
90
100

0.1

1.0

10
ωCRL (C IN FARADS, RL IN OHMS)

100

1000

ω = 2π f, f = Line Frequency

7

0.02
0.05
0.1
0.2
0.5
1.0
2.0
5.0
10
30
100

5
3
2

1
1.0

2.0

3.0

5.0

7.0

10

20

30
nωCRL

50

70

100

200

300

1000

40
I F(Peak) IF(AV) (PER DIODE)% RS /nR L

10

0.02

30

0.05
0.1

20

0.2
0.5

10

1.0

7

2.0
5.0

5

10
30

3

100

1.0

2.0

3.0

5.0

7.0

10

20

1 for Half-Wave Single-Phase Rectifier Circuits
2 for Full-Wave Single-Phase Rectifier Circuits
ω = 2 π f, where f = Line Frequency

30
nωCRL

50

n=

http://onsemi.com
65

70

100

200

300

500

C in Farads
RL in Ohms
RS = RMS Equivalent Source Resistance

700 1000% RS /nR L

F = IF(R ) I F(AV) (PER DIODE)S

Figure 8–4. Relation of RMS and Peak–to–Average Diode Current in Capacitor–Input Circuits

Figure 8–5. Root–Mean–Square Ripple Voltage for Capacitor–Input Circuits
100
70
50

CircuitAr f , RIPPLE FACTOR (%)

30
20

Half-Wave

Parameter
RS/RL (%)
A
0.1
1.0
10
30
0.1
1.0
10
30

Full-Wave

10
7.0
5.0

A

A

3.0
2.0
1.0
0.7
0.5
0.3
0.2
0.1
1.0

2.0

3.0

5.0

7.0

10

20

30

50

70

100

200

300

500

1000

ωCRL

ω = 2 π f, f = Line Frequency
C in Farads
RL in Ohms

Returning to the above curves, the full–wave circuit will be considered. Figure 8–3 shows that a circuit
must operate with ωCRL ≥ 10 in order to hold the voltage reduction to less than 10% and ωCRL ≥ 40 to obtainless than 2.0% reduction. However, it will also be seen that these voltage reduction figures require RS/RL,
where RS is now the total series resistance, to be about 0.1% which, if attainable, causes repetitivepeak–to–average current ratios from 10 to 17 respectively, as can be seen from Figure 8–4. These ratios
can be satisfied by many diodes; however, they may not be able to tolerate the turn–on surge current
generated when the input–filter capacitor is discharged and the transformer primary is energized at thepeak of the input waveform. The rectifier is then required to pass a surge current determined by the peaksecondary voltage less the rectifier forward drop and limited only by the series resistance R S. In order tocontrol this turn–on surge, additional resistance must often be provided in series with each rectifier. It
becomes evident, then, that a compromise must be made between voltage reduction on the one hand anddiode surge rating and hence average current–carrying capacity on the other hand. If small voltage
reduction, that is good voltage regulation, is required, a much larger diode is necessary than thatdemanded by the average current rating.
Surge Current
The capacitor–input filter allows a large surge to develop, because the reactance of the transformer
leakage inductance is rather small. The maximum instantaneous surge current is approximately VM/RS
and the capacitor charges with a time constant τ ≈ RS C1. As a rough — but conservative — check, thesurge will not damage the diode if VM/RS is less than the diode IFSM rating and τ is less than 8.3 ms. It is
wise to make RS as large as possible and not pursue tight voltage regulation; therefore, not only will thesurge be reduced but rectifier and transformer ratings will more nearly approach the DC power
requirements of the supply.

http://onsemi.com
66

2. Design ProcedureA) From the regulator circuit design (see Section 6), we know:
VC(DC) = the required full load average dc output voltage of the capacitor input filter
VRipple(pp) = the maximum no load peak–to–peak ripple voltage
Vm = the maximum no load output voltage
IO = the full–load filter output current
f = the input ac line frequencyB) From Figure 8–5, we can determine a range of minimum capacitor values to obtain sufficient ripple
attenuation. First determine rf:
VRipple(pp)× 100%
rf =(8.1)
2 √ 2 VC(DC)A range for ωCRL can now be found from Figure 8–5.
C) Next, determine the range of RS/RL from Figure 8–2 or 8–3 using VC(DC) and the values for ωCRL foundin part B. If the range of ωCRL values initially determined from Figure 8–5 is above 10, RS/RL can befound from Figures 8–2 and 8–3 using the lowest ωCRL value. Otherwise, several iterations between
Figures 8–2 or 8–3 and 8–5 may be necessary before an exact solution for RS/RLand ωCRL for a given
rf and VC(DC)/Vm can be found.
D) Once ωCRL is found, the value of the filter capacitor (C) can be determined from:ωCRL
C=
VC(DC)
2πf
IO

(8.2)

E) The rectifier requirements may now be determined:
1. Average current per diode;IF(avg) = IO for half–wave rectification(8.3)= IO/2 for full–wave rectification
2. RMS and Peak repetitive rectifier current ratings can be determined from Figure 8–4.
3. The rectifier PIV rating is 2 Vm for the half–wave and full–wave circuits, Vm for the fullwave bridge circuit. In addition, a minimum safety margin of 20% to 50% is advisable
due to the possibility of line transients.
4. Maximum surge current, Isurge = Vm/(RS + ESR)
(8.4)
where, ESR = minimum equivalent series resistance of filter capacitor from its data sheet.
F) Transformer Specification
1. Secondary leg RMS voltage, VS = {Vm + (n) 1.0}/ √ 2
where; n = 1 for half–wave and full–wave
n = 2 for full–wave bridge
2. Total resistance of secondary and any external resistors to be equal to RS found from
Figures 8–2, 8–3, and 8–4 (see Part C).
3. Secondary RMS current; half–wave = Irms
full–wave = Irms
full–wave bridge = √ 2 Irms
where, Irms = rms rectifier current (from part E.1 and E.2).
4. Transformer VA rating; half–wave = VS Irms
full–wave = 2 VS Irms
full–wave bridge = VS Irms (√ 2 )where, Irms = rms rectifier current (from part E.1 and E.2) and,
where, VS = secondary leg RMS voltage.

http://onsemi.com
67

(8.5)

(8.6)

(8.7)

3. Design Example
A) Find the values for the filter capacitor, transformer rectifier ratings, given
Full–Wave Bridge Rectification;
VC(DC) = 16 V
VRipple(pp) = 3.0 V
VM = 25 V
IO = 1.0 A
f = 60 Hz
B) Using Equation (8.1),
3
× 100% = 6.6%
2 √ 2 (16)rf =from Figure 8.5, ωCRL  7 to 15

C) Using ωCRL = 10, RS/RL is found from Figure 8–3 using,
VC(DC)
VM=

16= 0.64 = 64%
25

RS/RL = 20% or RS = 0.2 × RL = 0.2

VC(DC)= 0.2 (16)IO

RS = 3.2 ΩD) From Equation (8.2), the filter capacitor size is found:
10
ωCRL
=
= 1658 µF
C=
VC(DC)
2πf(60)16
2πf
IO
E) The rectifier ratings are now specified:
1. IF(avg) = IO/2 = 0.5 A from Equation (8.3)
2. IF(rms) = 2 × IF(AVG) = 1.0 A from Figure 8–4
3. IF(Peak) = 5.2 × IF(AVG) = 2.6 A from Figure 8–4
4. PIV = VM = 25 V (use 50 V for safety margin)
5. Isurge = VM/(RS + ESR)  25/3.2 = 7.8 A from Equation (8.4), neglecting capacitor ESR.
F) The transformer should have the following ratings:
1. VS = {VM + n(1.0)}/ √ 2 = (25 + 2)/ √ 2 = 19 VRMS {from Equation (8.5)}
2. Secondary Resistance should be 3.2 Ω
3. Secondary RMS current rating should be 1.4 A, (from Equation (8.6)).
4. From Equation (8.7), the transformer should have a 27 VA rating.
It should be noted that, in order to simplify the procedure, the above design does not allow forline voltage variations or component tolerances. The designer should take these factors into accountwhen designing his input supply. Typical tolerances would be: line voltage = +10% to –15% and filter
capacitors = +75% to –10%.

________________________________REFERENCES
1. O. H. Schade, Proc. IRE, Vol. 31, 1943.
2. ON Semiconductor Silicon Rectifier Manual, 1980.

http://onsemi.com
68

SECTION 9
AN INTRODUCTION TO SWITCHING
POWER SUPPLIESThe Switching Power Supply continues to increase in popularity and is one of the fastest growing
markets in the world of power conversion. Its performance and size advantages meet the needs of today’s
modern and compact electronic equipment and the increasing variety of components directed at theseapplications makes new designs even more practical.
This guide is intended to provide the designer with an overview of the more popular inverter circuits,
their basic theory of operation, and some of the subtle characteristics involved in selecting a circuit andthe appropriate components. Also included are valuable design tips on both the major passive and active
components needed for a successful design. Finally, a complete set of selector guides to ON
Semiconductor’s Switchmode components is provided which gives a detailed listing of the industry’s mostcomprehensive line of semiconductor products for switching power supplies.
Comparison with Linear Regulators
The primary advantages of a switching power supply are efficiency, size,and weight. It is also a more
complex design, cannot meet some of the performance capabilities of linear supplies and generates aconsiderable amount of electrical noise. However switchers are being accepted in the industry, particularly
where size and efficiency are of prime importance. Performance continues to improve and for mostapplications they are usually cost competitive down to the 20 W power level.
In the past the switcher’s advantage versus the linear regulator was in the high power arena where
passive components such as transformers and filters were small compared to the linear regulator at thesame power level. However, active component count was high and tended to make the switcher less costeffective at low power levels. In recent years, Switchers have been significantly cost reduced because
designers have been able to simplify the control circuits with new, cost effective integrated circuits and havefound even lower cost alternatives in the passive component area.
A performance comparison chart of switching versus linear supplies is shown in Table 9–1. Switcher
efficiencies run from 70% to 80% but occasionally fall to (60% to 65%) when linear post regulators are used
for the auxiliary outputs. Some linear power supplies on the other hand, are operated with up to 50%
efficiency but these are areas where line variations or hold–up time problems are minimal. Most linears
operate with typical efficiencies of only 30%. The overall size reduction of a 20 kHz switcher is about 4:1
and newer designs in the 100 kHz to 200 kHz region end up at about 8:1 (versus a linear). Other
characteristics such as static regulation specs are comparable, while ripple and load transient response
are usually worse. Output noise specs can be somewhat misleading. Very often a 500 mV switching spikeat the output may be attenuated considerably at the load itself due to the series inductance of theconnecting cables and the additional filter capacitors found in many logic circuits. In the future, the noise
generated at higher switching frequencies (100 kHz to 500 kHz) will probably be easier to filter and thetransient response will be faster. Hold–up time is greater for switchers because it is easier to store energy
in high voltage capacitors (200 V to 400 V) than in the lower voltage (20 V to 50 V) filter capacitors common
to linear power supplies. This is due to the fact that the physical size of a capacitor is dependent on its CV
product while energy storage is proportional to CV2.

http://onsemi.com
69

Table 9–1. 20 kHz Switcher versus Linear Performance
Parameter

SwitcherLinearEfficiency

75%

30%

Size

2.0 W/in3

0.5 W/in3

Weight40 W/lb

10 W/lb

Line and Load Regulation

0.1%

0.1%

Output Ripple Vpp

50 mV

5.0 mV

Noise Vpp

50 mV to 200 mV—

Transient Response

1.0 ms

20 µs

Hold–Up Time

20 ms to 30 ms

1.0 ms to 2.0 ms

Basic Configurations
A switching power supply is a relatively complex circuit as is shown by the four basic building blocks
of Figure 9–1. It is apparent here that the heart of the supply is really the high frequency inverter. It is herethat the work of chopping the rectified line at a high frequency (20 kHz to 200 kHz) is done. It is here alsothat the line voltage is transformed down to the correct output level for use by logic or other electronic
circuits. The remaining blocks support this basic function. The 60 Hz input line is rectified and filtered by
one block and after the inverter steps this voltage down, the output is again rectified and filtered by another.
The task of regulating the output voltage is left to the control circuit which closes the loop from the output
to the inverter. Most control circuits generate a fixed frequency internally and utilize pulse width modulation
techniques to implement the desired regulation. Basically, the on–time of the square wave drive to theinverter is controlled by the output voltage. As load is removed or input voltage increases,the slight risein output voltage will signal the control circuit to deliver shorter pulses to the inverter and conversely as
the load is increased or input voltage decreases, wider pulses will be fed to the inverter.
The inverter configurations used in today’s switchers actually evolved from the buck and boost circuits
shown in Figures 9–2a and 9–2b. In each case the regulating means and loop analysis will remain the same
but a transformer is added in order to provide electrical isolation between the line and load. The forward
converter family which includes the push–pull and half bridge circuits evolved from the buck regulator(Figure 9–2a). And the newest switcher, the flyback converter, actually evolved from the boost regulator.
The buck circuit interrupts the line and provides a variable pulse width square wave to a simple averaging
LC filter. In this case, the first order approximation of the output voltage is Vout = Vin × duty cycle andregulation is accomplished by simply varying the duty cycle. This is satisfactory for most analysis work andonly the transformer turns ratio will have to be adjusted slightly to compensate for IR drops, diode drops,
and transistor saturation voltages.
Operation of the boost circuit is more subtle in that it first stores energy in a choke and then delivers
this energy plus the input line to the load. However, the flyback regulators which evolved from thisconfiguration delivers only the energy stored in the choke to the load. This method of operation is actuallybased on the buck boost model shown in Figure 9–2c. Here, when the switch is opened, only the storedinductive energy is delivered to the load. The true boost circuit can also regulate by stepping up (orboosting) the input voltage whereas the buck–boost or flyback regulator can step the input voltage up or
down. Analysis of the boost regulator begins by dealing with the choke as an energy storage element which
delivers a fixed amount of power to the load: PO = 1/2 L IfO where, I = the peak choke current; fO = theoperating frequency; and, L = the inductance.
Because it delivers a fixed amount of power to the load regardless of load impedance (except for shortcircuits), the boost regulator is the designer’s first choice in photoflash and capacitive–discharge (CD)automotive ignition circuits to recharge the capacitive load. It also makes a good battery charger. For anelectronic circuit load, however, the load resistance must be known in order to determine theoutput voltage:
LfORL
where, RL = the load resistance.
PORL = IVO =2
In this case, the choke current is proportional to the on–time or duty cycle of the switch and regulation for
fixed loads simply involves varying the duty cycle as before. However, the output also depends on the load
which was not the case with buck regulators and results in a variation of loop gain with load.
http://onsemi.com
70

Figure 9–1. Functional Block Diagram — Switching Power Supply
50-60 Hz

20 to 25 kHz

DC

DCHigh Frequency
Inverter

OutputLine

Input Rectifierand Filter

Output Rectifierand Filter
Control Circuit

Note: Input to output isolation is not shown.

PWM

Comp

OSC

Ref

Figure 9–2. Nonisolated DC–DC Converters+ Vin+ Vout+ Vin

Vout ≤ Vin+ VoutVout > Vin(a) Buck (Step–Down)(b) Boost (Step–Up)- Vout+ Vin(c) Buck–Boost Regulator
which Resembles the Flyback Regulator(Step–Up or Down)

http://onsemi.com
71For both regulators, transient response or responses to step changes in load are very difficult toanalyze. They lead to what is termed a “load dump” problem. This requires that energy already stored in
the choke or filter be provided with a place to go when load is abruptly removed. Practical solutions to thisproblem include limiting the minimum load and using the right amount of filter capacitance to give theregulator time to respond to this change.
The Future
The future offers a lot of growth potential for switchers in general and low power switchers(20 W to 100 W) in particular. The latter are responding to the growth in microprocessor based equipment
as well as computer peripherals. Today’s configurations have already been challenged by the sine wave
inverter which reduces noise and improves transistor reliability but does effect a cost penalty. Also, a trend
to higher switching frequencies to reduce size and cost even further has begun. The latest bipolar designs
operate efficiently up to 100 kHz and the FET seems destined to own the 200 kHz to 500 kHz range.
At this time there are a lot of safety and noise specifications. Originally governed only by MIL specs
and the VDE in Europe, now both UL and the FCC have released a set of specifications that apply toelectronic systems which often include switchers (see Table 9–2). It seems probable, however, that systemengineers or power supply designers will be able to add the necessary line filters and EMI shields without
evoking a significant cost penalty in the design.
The most optimistic note concerning switchers is in the component area. Switching power supply
components have actually evolved from components used in similar applications. And it is very likely thatnewer and more mature products specifically for switchers will continue to appear over the next several
years. The ultimate effect of this evolution will be to further simplify, cost reduce and increase the reliabilityof these designs.
Table 9–2. SMPS Specifications
Specification

Area

UL 478, VDE 0730, VDE 0806

SafetyVDE 0871, VDE 0875
MIL–STD–217D
MIL–STD–461A
DOD–STD–1399
FCC Class A & B
CSA C22.2, IEC 380

EMI
Reliability
EMI
Harmonic Content
EMI
SafetyThe synchronous rectifier is one example of a new component developed specifically for low voltage
switchers. As requirements for 2.0 V and 3.0 V supplies emerge for use by fine geometry VLSI chips, theonly way to maintain decent conversion efficiency is to develop lower forward drop rectifiers. The
differences in 3.0 V and 5.0 V rectifier requirements are shown in Table 9–3. At this time, ON
Semiconductor offers low VF Schottky and area efficient TMOS III FETs for this task and is considering avariety of additional technology options. The direct approach involves using low VF Schottkys or pinch
rectifiers which will feature VFs of 0.3 V to 0.4 V. The indirect approach involves using FETs or bipolartransistors and slightly more complex circuitry like that shown in Figure 9–3. Both transistors will feature
VFs of 0.2 V and, in addition, the bipolar will have high EBOs (30 V) and high gain (100) with a recovery
time of 100 ns.
And for designers who are not satisfied with the relatively low frequency limitations of square wave
switchers, there is the SRPS. The series resonant power supply topology seems to offer the possibility ofworking in the 1.0 MHz region. If components like the relatively exotic power transformer can be cost
reduced, then it will be possible for this topology to become dominant in the market. The features generally
associated with this type of power supply are listed in Table 9–4 and a typical half bridge circuit is shownin Figure 9–4. In a design now being studied in ON Semiconductor’s advanced products laboratory,
standard FETs, Schottkys and ultrafast rectifiers all appear to work very well at 1.0 MHz.

http://onsemi.com
72

Figure 9–3. Synchronous Rectifiersfor 3.0 V Power Supplies

Table 9–3. Synchronous Rectifier
Requirements

G

OutputVoltage

Rectifier Characteristics
VF

VR

5.0 V

0.5 V–1.0 V

30 V–60 V

3.0 V

0.3 V–0.6 V

20 V–40 V

Primarily to reduce VF
also to reduce trr

S

D

S

D

VO

G
Note: The FET must be operated below VF of thediode in order to gain the trr advantage.

Table 9–4. SRPS Features
FeatureDescription

High Frequency

Today’s line operated designs use sine waves in the 500 kHz to 1.0 MHz range.

Small Size

The ferrite transformer and polypropylene coupling capacitor are smaller than thosefound in lower frequency square wave designs.

Low Noise

Switching occurs at zero crossings which reduces component stress and lowers EMI.

Efficient

Because switching losses are reduced, efficiency is high (typically 80%).

High Peak to Average
Current Ratios

Current ratings of the transistors and rectifiers are twice as high as similar flyback
designs.

Special Control Circuit

PDM (density) rather than PWM (width) control is used and requires a control IC
with a programmable VCO.

MarketThe SRPS is expected to own 15% of the power supply market by 1990.

Figure 9–4. SRPS Block Diagram
AC
Line

Input
Rectifierand Filter

1.0MHzFETInverter

SeriesResonant
Tank andTransformer

Schottky
Rectifiers

OutputFilterPDM
Control Circuit

60Hz

1.0 MHz Components

PDM
Controller

http://onsemi.com
73

20kHz

OutputSECTION 10
SWITCHING REGULATOR TOPOLOGIESFET and Bipolar Drive Considerations
There are probably as many base drive circuits for bipolars as there are designers. Ideally, thetransistor would like just enough forward drive (current) to stay in or near saturation and reverse drive thatvaries with the amount of stored base charge such as a low impedance reverse voltage. Many of today’scommon drive circuits are shown in Figure 10–1. The fixed drive circuits of Figure 10(a), (b) and (c) tend
to emphasize economy, while the Baker clamp and proportional drive circuits of Figure 10(d) and (e)emphasize performance over cost.
FET drive circuits are another alternative. The standard that has evolved at this time is shown in Figure
10–2A. This transformer coupled circuit will produce forward and reverse voltages applied to the FET gate
which vary with the duty cycle as shown. For this example, a VGS rating of 20 V would be adequate for the
worst case condition of high logic supply (12 V) and minimum duty cycle. And yet, minimum gate drive
levels of 10 V are still available with duty cycles up to 50%. If wide variations in duty cycle are anticipated,
it might be wise to consider using a semi–regulated logic supply for these situations. Finally, one point thatis not obvious when looking at the circuit is that FETs can be directly coupled to many ICs with only
100 mA of sink and source capability and still switch efficiently at 20 kHz. However, to achieve switchingefficiently at higher frequencies, 1.0 A to 2.0 A of drive may be required on a pulsed basis in order to quickly
charge and discharge the gate capacitances. A simple example will serve to illustrate this point and also
show that the Miller effect, produced by CDG, is the predominant speed limitation when switching highvoltages (see Figure 10–2B). A FET responds instantaneously to changes in gate voltage and will begin
to conduct when the threshold is reached (VGS = 2.0 V to 3.0 V) and be fully on with VGS = 7.0 V to 8.0 V.
Gate waveforms will show a porch at a point just above the threshold voltage which varies in duration
depending on the amount of drive current available and this determines both the rise and fall times for thedrain current.
Figure 10–1. Typical Bipolar Base Drive Circuits

12V
MC34060(a) Fixed Drive, Turn–Off
Energy Stored in Transformer

15Ω

9

MPS
U01

8

1.0k

MPS
U95

(d) Standard
Baker Clamp
50µF
+
105°C
Low ESR

MJE13005
22Ω(c) Direct Drive(e) Proportional
Base Drive(b) Fixed Drive, Turn–Off
Energy Stored in Capacitor

http://onsemi.com
74

Figure 10–2A. Typical Transformer Coupled FET Drive
12V
CDG

1:2

CGS

Wave Forms

ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ

VGS

50% Duty Cycle

10 V
0V- 10 V

ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ

20% Duty Cycle

16 V
0V
-4V

VGS Wave Forms

Figure 10–2B. FET Drive Current Requirements
10 V
8.0 V
2.0 V
0V

VGS
Drive
Circuit

100pF

CDG

500pF

CGS

1.0 A

IG + IM0A
1.0 A

2. Gate Cap Current for 30 ns:
IG = CGS dv/dt

1. Miller Current for 30 ns:
IM = CDG dv/dt= 100 pF ×

300 V
= 1.0 A
30 ns

= 500 pF ×

6.0 V
= 0.1 A
30 ns

To estimate drive current requirements, two simple calculations with gate capacitances can be made:1. IM = CDGdv/dt and,2. IG = CGSdv/dt
IM is the current required by the Miller Effect to charge the drain–to–gate capacitance at the rate it is desired
to move the drain voltage (and current). And IG is usually the lesser amount of current required to charge
the gate–to–source capacitance through the linear region (2.0 V to 8.0 V). As an example, if 30 ns
switching times are desired at 300 V, where CDG = 100 pF and CGS = 500 pF, then:
1. IM = 100 pF × 300 V/30 ns = 1.0 A and,2. IG = 500 pF × 6.0 V/30 ns = 0.1 A
This example shows the direct proportion of drive current capability to speed and also illustrates that formost devices, CDG will have the greatest effect on switching speed and that CGS is important only inestimating turn–on and turn–off delays.
Aside from its unique drive requirements, a FET is very similar to a bipolar transistor. Today’s 400 V
FETs compete with bipolar transistors in many switching applications. They are faster and easier to drive,
but do cost more and have higher saturation, or more accurately, “on” voltages. The performance orefficiency tradeoffs are analyzed using Figure 10–3, where typical power losses for switching transistors
versus frequency are shown. The FET (and bipolar) losses were calculated at 100°C rather than 25°C
because on resistance and switching times are highest here and 100°C is typical of many applications.
These curves are asymptotes of the actual device performance, but are useful in establishing the“breakpoint” of various devices, which is the point where saturation and switching losses are equal.

http://onsemi.com
75

TOTAL TRANSISTOR POWER LOSS (W)PT = Pon + P swt

Figure 10–3. Typical Switching Losses at 300 V and 5.0 A (TJ = 100°C)
100
30
10

Bipolartf = 100 ns

FET
tf = 20 ns

3.0
1.0
1.0

10

100
f, OPERATING FREQUENCY (Hz)

1.0

10

Control Circuits
Over the years, a variety of control ICs for SMPS have been introduced. The voltage mode controllers
diagramed in Table 10–1 still dominate this market. The basic regulating function is performed in the pulse
width modulator (PWM) section. Here, the dc feedback signal is compared to a fixed frequency sawtooth
waveform. The result is a variable duty cycle pulse train which, with suitable buffer or interface circuits, canbe used to drive the power switching transistor. Some ICs provide only a single output while others provide
a phase splitter or flip–flop to alternately pulse two output channels. Additionally, most ICs provide an error
amplifier and reference section shown as a means to process, compare and amplify the feedback signal.
Features required by a control IC vary to some extent because of the particular needs of a designer
and on the circuit configuration chosen. However, most of today’s current generation ICs have evolved withthe following capabilities or features:• Programmable (to 500 kHz) Fixed Frequency Oscillator• Linear PWM Section with Duty Cycle from 0% to 100%
• On Board Error Amplifiers• On Board Reference Regulator• Adjustable Deadtime• Under Voltage (low VCC) Inhibit• Good Output Drive (100 mA to 200 mA)• Option of Single or Dual Channel Output• Uncommitted Output Collector and Emitter or Totem Pole Drive Configuration• Soft–Start• Digital Current Limiting• Oscillator Sync Capability
It is primarily the cost differences in these parts that determine whether all or only part of these features
will be incorporated. Most of these are evident to the designer who has already started comparing
competitive device data sheets.
In addition to the control circuits listed in Table 10–2, ON Semiconductor also has two dc converter
control chips, the µA78S40 and the MC34063A. These chips feature an on–board 40 V, 2.0 A switchingtransistor and operate by dropping pulses from a fixed frequency, fixed duty cycle oscillator depending onload demand.
Today there is a demand for simple, low cost, single control ICs. These ICs, like ON Semiconductor’sMC34060A and MC34063A components, are used to run the low–power flyback type configurations andare usually part of a three chip rather than a single chip system. The differences in these two approaches
are illustrated in Figure 10–6.
When it is necessary to drive two or more power transistors, drive transformers are a practical interface
element and are driven by the conventional dual channel ICs. In the case of a single transistor converter,
however, it is usually more cost effective to directly drive the transistor from the IC. In this situation, an

http://onsemi.com
76

optocoupler is commonly used to couple the feedback signal from the output back to this control IC. And
the error amplifier in this case is nothing more than a programmable zener like ON Semiconductor’s TL431.
Overvoltage Protection
Linear and switching power supplies can be protected from overvoltage with a crowbar circuit. For
linear supplies, the pass transistor can fail shorted, allowing high line transformer voltage to the load. For
switching power supplies, a loose or disconnected remote sense lead can allow high voltage to the load.
Table 10–1. Basic SM Control ICs
ControlTechniqueType A
Voltage Mode

Type B
Voltage Mode w/Latch

Osc
Schematic

Osc
+

FB

R
Latch

+

FB

PWM

S

Type C
Current Mode
Osc

Latch
S
R
+

PWM

PWM

FB

Single Channel
Parts

MC34060A—

UC3842
MC34129

Dual Channel
Parts

TL494/594

SG3525A/27A
SG3526—

Features

Low Cost

Digital Current Limiting,Good Noise Immunity

Designed for Flyback,Inherent Feed Forward

PWM
Waveforms
OutputTable 10–2. Control Circuits
Overvoltage
Protection(OVP)
Standard
TL431

High
Performance
MC3423
TL431A

Over/Undervoltage
Protection(O/UVP)

Undervoltage
Sense MPU/MCU
Reset

MC3425
MC34161

MC34064–5
MC34164–3
MC34164–5

The list of available circuits is shown in Table 10–2 and a typical 0 V application is shown in Figure 10–4.
This crowbar circuit ignores noise spikes but will fire the SCR when a valid overvoltage condition isdetected. The SCR will discharge C2 and either blow the fuse or cause the power supply to shut down.
Figure 10–4. Crowbar Circuit

Power
SupplyC2

MC3423

http://onsemi.com
77

VOFor further information, see the MC3423 data sheet.

http://onsemi.com
78Surge Current Protection
Many high current PWM switching supplies operate directly off the ac line. They have very large
capacitive input filters with high inrush surge currents. The line circuit breaker and the rectifier bridge must
be protected during turn–on.
Surge current limiting can be accomplished by adding RS and an SCR short after charging C1, asshown in Figure 10–5, or by phase controlling the line voltage with a Triac.
Figure 10–5. Surge Current Limiting for a Switching Power Supply
RS
AC
Line

RectifierBridge

G

C1

RS
AC
Line

RectifierBridgeG

C1Transformer Design
With respect to transformer design, many of today’s designers would say don’t try it. They’d advise
using a consultant or winding house to perform this task and with good reason. It takes quite a bit of time
to develop a feel for this craft and be able to use both experience and intuition to find solutions to second
and third order problems. Because of these subtle problems, most designers find that after the first paper
design is done, as many as four or five lab iterations may be necessary before the transformer meets thedesign goals. However, there is a considerable design challenge in this area and a great deal of satisfaction
can be obtained by mastering it.
This component design, as do all others, begins by requesting all available literature from theappropriate manufacturers and then following this up with phone calls when specific questions arise. A
partial list of companies is shown in Table 10–3. Designs below 20 W generally use pot cores, but for
20 W and above, E cores are preferred. E cores expose the windings to air so that heat is not trapped insideand make it easier to bring out connections for several windings. Remember that flyback designs require
lower permeability cores than the others. The classic approach is to consult manufacturers charts like theone shown in Figure 10–8 and then to pick a core with the required power handling ability. Both E and EC(E cores with a round center leg) are popular now and they are available from several manufacturers. EC
cores offer a performance advantage (better coupling) but standard E cores cost less and are also usedin these applications. Another approach that seems to work equally well is to do a paper design of theestimated windings and turns required. Size the wire for 500 circular mils (CM) per amp and then find acore that has the required window area for this design. Now, before the windings are put on, it is a goodidea to modify the turns so that they fit on one layer or an integral number of layers on that bobbin. This
involves checking the turns per inch of the wire against the bobbin length. The primary generally goes on
first and then the secondaries. If the primary hangs over an extra half layer, try reducing the turns or thewire size. Conversely, if the secondary does not take up a full layer, try bifilar winding (parallel) using wire
half the size originally chosen (i.e., 3 wire sizes smaller, like 23 versus 20). This technique ultimately resultsin the use of foil for the higher current (20 A) low voltage windings. Most windings can be separated with
3 mil mylar (yellow) tape but for good isolation, cloth is recommended between primary and secondary.
Finally, once a mechanical fit has been obtained, it is time for the circuit tests. The isolation voltage
rating is strictly a mechanical problem and is one of the reasons why cloth is preferred over tape between
the primary and secondary. The inductance and saturating current level of the primary are inherent to thedesign, and should be checked in the circuit or other suitable test fixture. Such a fixture is shown in
Figure 10–7 where the transistor and diode are sized to handle the anticipated currents. The pulse
generator is run at a low enough duty cycle to allow the core to reset. Pulse width is increased until the startof saturation is observed (Isat). Inductance is found using L = E/(di/dt).
http://onsemi.com
79

Figure 10–6. Control Circuit Topologies
Rect &
FilterLine

Rect &
FilterOutputDual Channel
ControlIC(a) Single Chip System — Drive Transformer Isolation

Line

Rect &
FilterRect &
FilterOutputSingle Channel
ControlIC

Opto
CouplerError
Amp(b) Three Chip System — Opto Coupler Isolation

In forward converters, the transformer generally has no gap in order to minimize the magnetizing
current (IM). For these applications the core should be chosen large enough so that the resulting LI productinsures that IM at operating voltages is less than Isat. For flyback designs, a gap is necessary and the test
circuit is useful again to evaluate the effect of the gap. The gap will normally be quite large, Lg > > L m/u,
where, Lg= gap length
Lm = magnetic path length, andu= permeability.
Under this stipulation, the gap directly controls the LI parameters and doubling it will decrease L by two and increase Isat by two
until fringing effects occur. Gaps of 5 mils to 20 mils are common. Again, the anticipated switching currents must be less than Isat
when the core is gapped for the correct inductance.
Table 10–3. Partial List of Core (C) and Transformer (T) Manufacturers
Company

Location

CodeFerroxcube Inc.
Indiana General
Stackpole
TDK
Pulse Engineering
Coilcraft

Sauggerties, NY
Keasby, NJ
St. Marys, PA
El Segundo, CA
San Diego, CA
Cary, IL

C
C
C
C
T
T

Transformer tests in the actual supply are usually done with a high voltage dc power supply on the
primary and with a pulse generator or other manual control for the pulse width (such as using the control
IC in the open loop configuration). Here the designer must recheck three areas:
1. Core saturation
2. Correct amount of secondary voltage
3. Transformer heat rise
If problems are detected in any of these areas, the ultimate fix may be to redesign using the next larger
core size. However, if problems are minimal, or none exist, it is possible to stay with the same core or evenconsider using the next smaller size.

http://onsemi.com
80Figure 10–7. Simple Coil Tester
20V
DUT

Isat
IC

IC

Scope

Time

Current Transformer∆IC
L = V ∆t

Filter Capacitor Considerations
In today’s 20 kHz switchers, aluminum electrolytics still predominate. The good news is that most havebeen characterized, improved, and cost reduced for this application. The input filter requires a voltage
rating that depends on the peak line voltage; i.e., 400 V to 450 V for a 220 V switcher. If voltage is increased
beyond this point, the capacitor will begin to act like a zener and be thermally destroyed from high leakage
currents if the rating is exceeded for enough time. In doubler circuits, voltage sharing of the two capacitors
in series can be a problem. Here extra voltage capability may be needed to make up for the imbalances
caused by different values of capacitance and leakage current. A bleeder resistor is normally used here
not only for safety but to mask the differences in leakage current. The RMS current rating is also an
important consideration for input capacitors and is an example of improvements offered by today’s
manufacturers. Earlier “lytics” usually lacked this rating and often overheated. Large capacitors that were
not needed for performance were used just to reduce this heating. However, today’s devices offer lower
thermal resistance, improved connection to the foil and good RMS ratings. A partial list of manufacturersthat supply both high voltage input and the lower voltage output capacitors for switchers is shown in
Table 10–4. Most of the companies offer not only the standard 85°C components, but devices with up to
125°C ratings which are required because of the high ambient temperatures (55° to 85°C) that many
switchers have to operate in, many times without the benefit of fans.
Table 10–4. Partial List of Capacitor Companies
Company (U.S.)

Location

MEPCO/Electra

Columbia, SC

Cornell–Dublier

Sanford, NC

SangamoPickens, SC

Mallory

Indianapolis, IN

For output capacitors the buzz word is low ESR (equivalent series resistance). It turns out that for most
capacitors even in the so–called “low ESR” series, the output ripple depends more on this resistance thanon the capacitor value itself. Although typical and maximum ESR ratings are now available on most
capacitors designed for switchers, the lead inductance generally is not specified except for the ultra–highfrequency four terminal capacitors from some vendors. This parameter is responsible for the relatively highswitching spikes that appear at the output. However, at this point in time, most designers find it less costly
and more effective to add a high frequency noise filter rather than use a relatively expensive capacitor withlow equivalent series inductance (ESL).
These LC noise or spike filters are made using small powdered iron toroids (1/2″ to 1″ OD) with
distributed windings to minimize interwinding capacitance. And the output is bypassed using a small
0.1 µF ceramic or a 10 µF to 50 µF tantalum or both. Larger powered iron toroids are often used in themain LC output filter although the higher permeability ferrite EC and E cores with relatively large gaps canalso be used. Calculations for the size of this component should take into account the minimum load sothat the choke will not run “dry” as stated earlier.

http://onsemi.com
81

Figure 10–8. Core Selection for Bridge Configurations(Reprinted from Ferroxcube Design Manual)
2000
Pth
(W)
1000

500

200

100

50

20

10

5

2

1
10

20

30

40

Note: Power handling decreases by a factor of 2 in forward
Note: and by 4 in flyback configurations.

http://onsemi.com
82

50

SECTION 11
SWITCHING REGULATOR COMPONENTDESIGN TIPS
Transistors
The initial selection of a transistor for a switcher is basically a problem of finding the one with voltage
and current capabilities that are compatible with the application. For the final choice performance and cost
tradeoffs among devices from the same or several manufacturers have to be weighed. Before thesedevices can be put in the circuit, both protective and drive circuits will have to be designed.
ON Semiconductor’s first line of devices for switchers were trademarked “Switchmode” transistors andintroduced in the early 70’s with data sheets that provided all the information that a designer would needincluding reverse bias safe operating area (RBSOA) and performance at elevated temperature (100°C).
The first series was the 2N6542 through 2N6547, TO–204 (TO–3) and was followed by the MJE13002
through MJE13009 series in a plastic TO–220 package. Finally, high voltage (1.0 kV) requirements weremet by the metal MJ8500 thru MJ8505 series and the plastic MJE8500 series. The Switchmode II series
is an advanced version of Switchmode I that features faster switching. Switchmode III is a state of the art
bipolar with exceptional speed, RBSOA, and up to 1.5 kV blocking capacity. Here, device cost is somewhat
higher, but system costs may be lowered because of reduced snubber requirements and higher operating
frequencies. A similar argument applies to ON Semiconductor TMOS Power FETs. These devices makeit possible to switch efficiently at higher frequencies (200 kHz to 500 kHz) but the main selling point is thatthey are easier to drive. This latter point is the one most often made to show that systems savings are again
quite possible even though the initial device cost is higher.
Table 11–1. ON Semiconductor High Voltage Switching Transistor Technologies
Approximate
SwitchingFrequency

Typical
DeviceTypical FallTime

SWITCHMODE I

2N6545
MJE13005
MJE12007

200 nsto
500 ns

20 k

SWITCHMODE II

MJ13081

100 ns

100 k

SWITCHMODE III

MJ16010

50 ns

200 k

TMOS

MTP5N40

20 ns

500 k

FamilyTable 11–2 is a chart of the transistor voltage requirements for the various off–line converter circuits.
As illustrated, the most stringent requirement for single transistor circuits (flyback and forward) is theblocking or VCEV rating. Bridge circuits, on the other hand, turn on and off from the dc bus and their mostcritical voltage is the turn–on or VCEO(sus) rating.
Table 11–2. Power Transistor Voltage Chart
CircuitLine
Voltage220
120

Flyback, Forward or Push–Pull

Half or Full–Bridge

VCEV

VCEO(sus)

VCEO(sus)

VCEV

850 kV to 1.0 kV
450

450
250

450
250

450
250

http://onsemi.com
83

Most switchmode transistor load lines are inductive during turn–on and turn–off. Turn–on is generally
inductive because the short circuit created by output rectifier reverse recovery times is isolated by leakage
inductance in the transformer. This inductance effectively snubs most turn–on load lines so that the rectifier
recovery (or short circuit) current and the input voltage are not applied simultaneously to the transistor.
Sometimes primary interwinding capacitance presents a small current spike but usually turn–on transientsare not a problem. Turn–off transients due to this same leakage inductance, however, are almost always
a problem. In bridge circuits, clamp diodes can be used to limit these voltage spikes. If the resulting
inductive load line exceeds the transistor’s reverse bias switching capability (RBSOA) then an RC network
may also be added across the primary to absorb some of this transient energy. The time constant of thisnetwork should equal the anticipated switching time of the transistor (50 ns to 500 ns). Resistance valuesof 100 Ω to 1000 Ω in this RC network are generally appropriate. Trial and error will indicate how low theresistor has to be to provide the correct amount of snubbing. For single transistor converters, the circuits
shown in Figure 11–1 are generally used.
Here slightly different criteria are used to define the R and C snubber values:
It
C= f
V
where;
I = the peak switching current
tf = the transistor fall time
V = the peak switching voltage (Approximately twice the DC bus)
also,
R = ton/C (it is not necessary to completely discharge this capacitor
in order to obtain the desired effects of this circuit)
where,
ton = the minimum on–time or pulse width2
and,PR = CV f2
where, PR = the power rating of the resistor
and,f = the operating frequency.
In most of today’s designs snubber elements are small or nonexistent and voltage spikes from energy
left in the leakage inductance a more critical problem depending on how good the coupling is between the
primary and clamp windings and how fast the clamp diode turns on. FETs often have to be slowed down
to prevent self destruction from this spike.
Figure 11–1. Protection Circuits for Switching Transistors
VDD

Clamp
Winding

Zener
Clamp
Zener
Clamp

RC
Clamp

http://onsemi.com
84

RC
SnubberRC
NetworkZener and Mosorb Transient Suppressors
If necessary, protection from voltage spikes may be obtained by adding a zener and rectifier acrossthe primary as shown in Figure 11–1. Here ON Semiconductor’s 5.0 W zener lines with ratings up to 200
V, and 10 W TO–220 Mosorbs with ratings up to 250 V can provide the clamping or spike limiting function.
If the zener must handle most of the power, its size can be estimated using:LL I2fPZ =2
where,PZ = the zener power ratingand,
LL = the leakage inductance (measured with the clamp winding or secondary shorted)
I = peak collector current
f = operating frequency
Distinction is sometimes made between devices trademarked Mosorb (by ON Semiconductor, Inc.),
and standard zener/avalanche diodes used for reference, low–level regulation and low–level protection
purposes. It must be emphasized that Mosorb devices are, in fact, zener diodes. The basic semiconductor
technology and processing are identical. The primary difference is in the applications for which they
are designed. Mosorb devices are intended specifically for transient protection purposes and aredesigned, therefore, with a large effective junction area that provides high pulse power capability while
minimizing the total silicon use. Thus, Mosorb pulse power ratings begin at 600 W — well in excess of low
power conventional zener diodes which in many cases do not even include pulse power ratings among
their specifications.
MOVs, like Mosorbs, do have the pulse power capabilities for transient suppression. They are metaloxide varistors (not semiconductors) that exhibit bidirectional avalanche characteristics, similar to thoseof back–to–back connected zeners. The main attributes of such devices are low manufacturing cost, theability to absorb high energy surges (up to 600 joules) and symmetrical bidirectional “breakdown”
characteristics. Major disadvantages are: high clamping factor, an internal wear–out mechanism and an
absence of low–end voltage capability. These limitations restrict the use of MOVs primarily to the protectionof insensitive electronic components against high energy transients in applications above 20 V, whereas,
Mosorbs are best suited for precise protection of sensitive equipment even in the low voltage range thesame range covered by conventional zener diodes.
Rectifiers
Once components for the inverter section of a switcher have been chosen, it is time to determine how
to get power into and out of this section. This is where the all–important rectifier comes into play. (SeeFigure 11–2.) The input rectifier is generally a standard recovery bridge that operates off the ac line andinto a capacitive filter. For the output section, most designers use Schottkys for efficient rectification of
the low voltage, 5.0 V output windings and for the higher voltage, 12 V to 15 V outputs, the more economical
fast recovery or ultrafast diodes are used.
Figure 11–2. Switchmode Power Supply Flyback or Boost Design
D4
12V Output

D2
D5
D1
AC LineContIC

5V Output

D3
Q1

TMOS1
OC

http://onsemi.com
85

D1 — Bridge Rectifier — Line Voltage
D2 — Clamp Diode— HV/Fast–Ultrafast
D3 — Snubber Diode — HV/Fast–Ultrafast
D4 — Output Rectifier — Fast/Ultrafast
D5 — Output Rectifier — Schottky

For the process of choosing an input rectifier, it is useful to visualize the circuit shown in Figure 11–3.
To reduce cost, most earlier approaches of using choke input filters, soft start relays (Triacs), or SCRs to
bypass a large limiting resistor have been abandoned in favor of using small limiting resistors or thermistors
and a large bridge. The bridge must be able to withstand the surge currents that exist from repetitive starts
at peak line. The procedure for finding the right component and checking its fit is as follows:
1. Choose a rectifier with 2 to 5 times the average IO required.
2. Estimate the peak surge current (Ip) and time (t) using:
1.4 VinIp =t = RSCRS
Where Vin is the RMS input voltage; RS is the total series resistance; and C is the filter capacitor size.
Figure 11–3. Choosing Input Rectifiers
Filter
Cap

AC
Line

Bridge

RS

Load

C

3. Compare this current pulse to the sub cycle surge current rating (IS) of the diode itself. If the curveof IS versus time is not given on the data sheet, the approximate value for IS at a particular pulse
width (t) may be calculated knowing:• IFSM — the single cycle (8.3 ms) surge current rating and using.
• I2 √ t = K, which applies when the diode temperature rise is controlled by its
thermal response as well as power (i.e., T = K′P √ t for t < 8.0 ms).
This gives:
1/4
IS2 √ t = I2FSM √ 8.3 ms or, IS = IFSM ( 8.3 ms ) , t is in milliseconds.
t
4. If IS < IP, consider either increasing the limiting resistor (RS) or utilizing a larger diode.
In the output section where high frequency rectifiers are needed, there are several types available tothe designer. In addition to the Schottky (SBR) and fast recovery (FR), there is also an ultrafast recovery(UFR). Comparative performance for devices with similar current ratings is shown in Table 11–3. The
obvious point here is that lower forward voltage improves efficiency and lower recovery times reduce
turn–on losses in the switching transistors, but the tradeoff is higher cost. As stated earlier, Schottkys are
generally used for 5.0 V outputs and fast recovery and ultrafast devices for 12 V outputs and greater. The
ultrafast is competing both with the Schottky where higher breakdown is needed and with the fast recovery
in those applications where performance is more important than cost. Ten years ago Schottkys were veryfragile and could fail short from either excessive dv/dt (1.0 V to 5.0 V per nanosecond) or reverse
avalanche. Since that time, ON Semiconductor has incorporated a “guard ring” or internal zener which
minimizes these earlier problems and reduces the need for RC snubbers and other external protective
networks.
Table 11–3. ON Semiconductor Rectifier Product Portfolio
Schottky

Ultrafast

Fast
RecoveryStandard
Recovery

0.5 V to 0.6 V

0.9 V to 1.0 V

1.2 V to 1.4 V

1.2 V to 1.4 V

Reverse Recovery Time (trr)<10 ns

25 ns to 100 ns

150 ns1.0 µstrr Form

Soft

Soft

Soft

Soft

Parameter
Forward Voltage (VF)

http://onsemi.com
86DC Blocking Voltage (VR)Cost Ratio

20 V to 60 V

50 V to 1000 V

50 V to 1000 V

50 V to 1000 V

3:1

3:1

2:1

1:1

http://onsemi.com
87

SECTION 12
BASIC SWITCHING POWER SUPPLYCONFIGURATIONS
The implementation of switching power supplies by the non–specialist is becoming increasingly easy
due to the availability of power devices and control ICs especially developed for this purpose by thesemiconductor manufacturer.
This section is meant to help in the preliminary selection of the devices required for the implementationof the listed switching power supplies.
Flyback and Forward Converter Switching Power Supplies (50 W to 250 W)• Input line variation: Vin + 10%, – 20%• Converter efficiency: η = 80%• Output regulation by duty cycle (δ variation: δ(max) = 0.4)
• Maximum Transistor working current:

Iw =

=

2.0 Poutη  δ(max)  Vin(min)  √ 2Poutη  δ(max)  Vin(min)  √ 2==

5.5 PoutVin
2.25 Pout
Vin(Flyback)(Forward)• Maximum transistor working voltage: Vw = 2  Vin(max)  √ 2 + guardband• Working frequency: f = 20 kHz to 200 kHz

Basic Flyback Configuration
OutputRectifier
DC Output
Power
Inverter

Line
Input

Control
Circuitry

Input
Rectifier

http://onsemi.com
88

Table 12–1. Flyback and Forward Converter Semiconductor Selection Chart
Output Power

50 W

100 W

175 W

250 W

Input Line Voltage (Vin)

120 V

220 V
240 V

120 V

220 V
240 V

120 V

220 V
240 V

120 V

MOSFET Requirements:
Max Working Current (Iw)
Max Working Voltage (Vw)

2.25 A
380 V

1.2 A
750 V

4.0 A
380 V

2.5 A
750 V

8.0 A
380 V

4.4 A
750 V

11.4 A380 V

Power MOSFETs Recommended:
Metal (TO–204AA) (TO–3)
Plastic (TO–220AB)
Plastic (TO–218AC)

MTM4N45
MTP4N45—

MTM2N90
MTP2N90—

MTM4N45
MTP4N45—

MTM2N90
MTP2N90—

MTM7N45—
MTH7N45

MTM4N90——

MTM15N45——

Input Rectifiers:
Max Working Current (Iw)
Recommended Types

0.4 A
MDA104A

0.25 A
MDA106A

0.4 A
MDA206

0.5 A
MDA2102.35 A
MDA9701.25 A
MDA210

4.6 A
MDA3506

Output Rectifiers:
Recommended types for
Output Voltage of: 5.0 V
10 V
20 V
50 V
100 V
Recommended Control Circuits

MBR3035PT
MUR3010PT
MUR1615CT
MUR1615CT
MUR 440, MUR840A

MBR3035PT
MUR3010PT
MUR1615CT
MUR1615CT
MUR840A

MBR12035CT
MUR10010CT
MUR3015PT
MUR1615CT
MUR840A

MBR20035CT
MUR10010CT
MUR10015CT
MUR3015PT
MUR840A

SG1525A, SG1526, TL494 Inverter Control Circuit
MC3423 Overvoltage Detector
Error Amplifier: Single TL431; Dual–LM358
Quad MC3403, LM324, LM2902

Flyback and Forward Converters
To take advantage of the regulating techniques discussed earlier and also provide isolation, a total ofseven popular configurations have evolved and are listed below. Each circuit has a practical power range
or capability associated with it as follows:
Power Range

Parts Cost

DC Converter

Circuit

5.0 W$ 4.00Converter w/30 V Transformer

10 W

7.00

Blocking OSC

20 W

10.00

Flyback

50 W

15.00

Forward

100 W

20.00

Half–Bridge

200 W

30.00

Full–Bridge

500 W

75.00

First to be discussed will be the low power (20 W to 200 W) converters which are dominated by thesingle transistor circuits shown in Figure 12–1. All of these circuits operate the magnetic element in the
unipolar rather than bipolar mode. This means that transformer size is sacrificed for circuit simplicity.
The flyback (alternately known as the “ringing choke”) regulator stores energy in the primary winding
and dumps it into the secondary windings, see Figure 12–1(a). A clamp winding is usually present to allow
energy stored in the leakage reactance to return safely to the line instead of avalanching the switchingtransistor. The operating model for this circuit is the buck–boost discussed earlier. The flyback is the lowest
cost regulator because output filter chokes are not required since the output capacitors feed from a current
source rather than a voltage source. It does have higher output ripple than the forward converters becauseof this. However, it is an excellent choice when multiple output voltages are required and does tend toprovide better cross regulation than the other types. In other words changing the load on one winding will
have little effect on the output voltage of the others.

http://onsemi.com
89

Figure 12–1. Low Power Popular (20 to 200 W) Converter Configurations(a) Flyback (Clamp Winding is Optional)(b) Forward (Clamp Winding is Necessary)(c) Two Transistor Forward or Flyback(Clamp Winding is not Needed)

A 120/220 Vac flyback design requires transistors that block twice the peak line plus transients or about
1.0 kV. ON Semiconductor’s MJE13000 and 16000A series with ratings of 750 V to 1000 V are normallyused here. These bipolar devices are relatively fast (100 ns) and are typically used in the 20 kHz to 50 kHz
operating frequency range. The recent availability of 900 V and 1000 V TMOS FETs allows designers tooperate in the next higher range (50 kHz to 80 kHz) and some have even gone as high as 300 kHz withsquare wave designs and FETs. Faster 1.0 kV bipolar transistors are also planned in the future and will
provide another design alternative. The two transistor variations of this circuit, Figure 12–1(c), eliminate
the clamp winding and add a transistor and diode to effectively clamp peak transistor voltages to the line.
With this circuit a designer can use the faster 400 V to 500 V FET transistors and push operating
frequencies considerably higher. There is a cost penalty here over the single transistor circuit due to theextra transistor, diodes and gate drive circuitry.
A subtle variation in the method of operation can be Figure 12–2. Flyback Transistor Waveforms
applied to the flyback regulator. The difference is referred
800 V
to as operation in the discontinuous or continuous modeand the waveform diagrams are shown in Figure 12–2.
VCE
400 V VCEThe analysis given in the earlier section on boost
0V
regulators dealt strictly with the discontinuous mode
where all the energy is dumped from the choke before the
2.0 A
1.0 A
transistor turns on again. If the transistor is turned on whileIC
0 A ICenergy is still being dumped into the load, the circuit is
Discontinuous Mode
Continuous Modeoperating in the continuous mode. This is generally an
advantage for the transistor in that it needs to switch only
half as much peak current in order to deliver the same
power to the load. In many instances, the same transformer
transformer may be used with only the gap reduced to provide more inductance. Sometimes the core size
will need to be increased to support the higher LI product (2 to 4 times) now required because theinductance must increase by almost 10 times to effectively reduce the peak current by two. In dealing withthe continuous mode, it should also be noted that the transistor must now turn on from 500 V to 600 V rather
than 400 V level because there no longer is any deadtime to allow the flyback voltage to settle back downin the input voltage level. Generally, it is advisable to have VCEO(sus) ratings comparable to the turn–on
requirements except for SMIII where turn–on up to VCEV is permitted.
The flyback converter stands out from the others in its need for a low inductance, high current primary.
Conventional E and pot core ferrites are difficult to work with because their permeability is too high evenwith relatively large gaps (50 to 100 milli–inches). The industry needs something better that will provide
permeabilities of 60 to 120 instead of 2000 to 3000 for this application.

http://onsemi.com
90

The single transistor forward converter is shown in Figure 12–1(b). Although it initially appears very
similar to the flyback, it is not. The operating model for this circuit is actually the buck regulator discussed
earlier. Instead of storing energy in the transformer and then delivering it to the load, this circuit uses thetransformer in the active or forward mode and delivers power to the load while the transistor is on. The
additional output rectifier is used as a freewheeling diode for the LC filter and the third winding is actuallya reset winding. It generally has the same turns as the primary, (is usually bifilar wound) and does clamp
the reset voltage to twice the line. However, its main function is to return energy stored in the magnetizing
inductance to the line and thereby reset the core after each cycle of operation. Because it takes the sametime to set and reset the core, the duty cycle of this circuit cannot exceed 50%. This also is a very popular
low power converter and like the flyback is practically immune from transformer saturation problems.
Transistor waveforms shown in Figure 12–3 illustrate
Figure 12–3. Forward Converter
that the voltage requirements are identical to theTransistor Waveforms
flyback. For the single transistor versions, 400 V
turn–on and 1.0 kV blocking devices like the MJE13000
800 V
and MJE16000 transistors are required. The two
VCE
400 V
transistor circuit variations shown in Figure 12–1(b)again adds a cost penalty but allows a designer to use
0V
the faster 400 V to 500 V devices. With this circuit,
operation in the discontinuous mode refers to
1.0 A
the time when the load is reduced to a point where theICfilter choke runs “dry.” This means that choke current
0A
starts at and returns to zero during each cycle ofoperation. Most designers prefer to avoid this typeof mode because of higher ripple and noise even though there are no adverse effects on the components
themselves. Standard ferrite cores work fine here and in the high power converters as well. In theseapplications, no gap is used as the high permeability (3000) results in the desirable effect of very low
magnetizing current levels. And, zeners or RC clamps may be used to reset the core in lieu of the clamp
winding to lower the voltage stress on the switching transistors.

Figure 12–4. Push–Pull Converter(200 W to 1.0 kW)

Push–Pull and Bridge Converters

The high power circuits shown in Figures 12–4 to12–7 all operate the magnetic element in the bipolar or+ Vout+ Vinpush–pull mode and require 2 to 4 inverter transistors.
Because the transformers operate in this mode theytend to be almost half the size of the equivalent single
transistor converters and thereby provide a costadvantage over their counterparts at power levels of
200 kW to 1.0 kW.
The push–pull converter shown in Figure 12–4 isone of the oldest converter circuits around. Its early use
was in low voltage inverters such as the 12 Vdc to 120 Vdc power source for recreational vehicles and indc to dc converters. Because these converters are free running rather than driven and operate from low
voltages, transformer saturation problems are minimal. In the high voltage off–line switchers, saturation
problems are common and were difficult to solve. The transistors are also subjected to twice the peak line
voltage which requires the use of high voltage (1.0 kV) transistors. Both of these drawbacks have tended
to discourage designers of off–line switchers from using this configuration until current mode control ICs
were introduced. Now these circuits are being looked at with renewed interest.

http://onsemi.com
91

Push–Pull Switching Power Supplies (100 W to 500 W)• Input line variation: Vin + 10%, – 20%• Converter efficiency: η = 80%• Output regulation by duty cycle (δ) variation: δ(max) = 0.8• Maximum transistor working current:

Pout
1.4 Pout=Vinη  δ(max)  Vin(min)  √2
• Maximum transistor working voltage: Vw = 2  Vin(max)  √ 2 + guardband• Working frequency: f = 20 kHz to 200 kHz
Iw =Basic Push–Pull Configuration
OutputFilterOutputRectifier

DC Output

Line
Input

Control
CircuitryPower
Inverter

Input
Rectifier

Table 12–2. Push–Pull Semiconductor Selection Chart
Output Power

100 W

250 W

500 W

Input Line Voltage (Vin)

120 V

220 V
240 V

120 V

220 V
240 V

120 V

220 V
240 V

MOSFET Requirements:
Max Working Current (Iw)
Max Working Voltage (Vw)

1.2 A
380 V

0.6 A
750 A

2.9 A
380 V

1.6 A
750 V

5.7 A
380 V

3.1 A
750 V

Power MOSFETs Recommended:
Metal (TO–204AA) (TO–3)
Plastic (TO–220AB)
Plastic (TO–218AC)

MTM2N50
MTP2N45—

MTM2N90
MTP2N90—

MTM4N45
MTP4N45—

MTM2N90
MTP2N94—

MTM7N45—
MTH7N45

MTM4N90——

Input Rectifiers:
Max Working Current (Iw)
Recommended Types

0.9 A
MDA206

0.5 A
MDA2102.35 A
MDA970–5

1.25 A
MDA210

4.6 A
MDA3506

2.5 A
MDA3510Output Rectifiers:
Recommended types for
output voltages of: 5.0 V
10 V
20 V
50 V
100 V

MBR3035PT
MBR3045PT, MUR3010PT
MUR1615CT
MUR1615CT
MUR840A, MUR440

Recommended Control Circuits

MBR12035CT
MUR10010CT
MUR3015PT
MUR1615CT
MUR840A

SG1525A, SG1526, TL494 Inverter Control Circuit
MC3423 Overvoltage Detector
Error Amplifier: Single TL431; Dual–LM358
Quad MC3403, LM324, LM2902

http://onsemi.com
92

MBR20035CT
MUR10010CT
MUR10015CT
MUR3015PT
MUR840A

Half–Bridge/Full–Bridge Switching Power Supplies (100 W to 500 W/500 W to 1000 W)• Input line variation: Vin + 10%, – 20%• Converter efficiency: η = 80%• Output regulation by duty cycle (δ) variation: δ(max) = 0.8• Maximum working current:

2 PoutIw =η  δ(max)  Vin(min)  √ 2
Pout

=

=

=

2.8 Pout
Vin(Half–Bridge)

1.4 Pout(Full–Bridge)Vinη  δ(max)  Vin(min)  √ 2• Maximum transistor working voltage: Vw = Vin(max)  √ 2 + guardband• Working frequency: f = 20 kHz to 200 kHz
Basic Half–Bridge Configuration
OutputFilterOutputRectifier

Line
Input

DC Output

Control
CircuitryPower
Inverter
Input
Rectifier

Table 12–3. Half–Bridge Semiconductor Selection Chart
Output Power

100 W

350 W

500 W

Input Voltage (Vin)

120 V

220 V
240 V

120 V

220 V
240 V

120 V

220 V
240 V

MOSFET Requirements:
Max Working Current (Iw)
Max Working Voltage (Vw)

2.3 A
190 V

1.25 A
380 V

5.7 A
190 V

3.1 A
380 V

11.5 A
190 V

6.25 A380 V

Power MOSFETs Recommended:
Metal (TO–204AA) (TO–3)
Plastic (TO–220AB)
Plastic (TO–218AC)

MTM5N35
MTP3N40—

MTM2N45
MTP2N45—

MTM8N40—
MTH8N40

MTM4N45
MTP4N45—

MTM10N25
MTP10N25—

MTM7N45—
MTH7N45

Input Rectifiers:
Max Working Current (Iw)
Recommended Types

0.9 A
MDA206

0.5 A
MDA210

2.3 A
MDA970–5

1.25 A
MDA210

4.6 A
MDA3506

2.5 A
MDA3510Output Rectifiers:
Recommended types for
output voltage of: 5.0 V
10 V
20 V
50 V
100 V

MBR3035PT
MBR3045PT, MUR3010PT
MUR1615CT
MUR1615CT
MUR840A, MUR440

Recommended Control Circuits

MBR12035CT
MUR10010CT
MUR3015PT
MUR1615CT
MUR840A

SG1525A, SG1526, TL494 Inverter Control Circuit
MC3423 Overvoltage Detector
Error Amplifier: Single TL431; Dual–LM358
Quad MC3403, LM324, LM2902

http://onsemi.com
93

MBR20035CT
MUR10010CT
MUR10015CT
MUR3015PT
MUR840A

Half and Full–Bridge
The most popular high power converter is the half–bridge (Figure 12–6). It has two clear advantages
over the push–pull and became the favorite rather quickly. First, the transistors never see more than thepeak line voltage and the standard 400 V fast switchmode transistors that are readily available may be
used. And second, and probably even more important, transformer saturation problems are easily
minimized by use of a small coupling capacitor (about 2.0 µF to 5.0 µF) as shown above. Because theprimary winding is driven in both directions, a full–wave output filter, rather than half, is now used and thecore is actually utilized more effectively. Another more subtle advantage of this circuit is that the input filter
capacitors are placed in series across the rectified 220 V line which allows them to be used as the voltage
doubler elements on a 120 V line. This still allows the inverter transformer to operate from a nominal
320 V bus when the circuit is connected to either 120 V or 220 V. Finally, this topology allows diode clamps
across each transistor to contain destructive switching transients. The designer’s dream, of course, is forfast transistors that can handle a clamped inductive load line at rated current. And a few (like the MJE16000
series from ON Semiconductor) are beginning to appear on the market. With the improved RBSOA thatthese transistors feature, less snubbing is required and this improves both the cost and efficiency ofthese designs.

Figure 12–5. Half–Bridge Converterwith Split Windings

Figure 12–6. Half–Bridge Converter(200 W to 1.0 kW)
+ Vin

+ Vin

+ VoutCC+ VoutCC

Basic Full–Bridge Configuration
OutputFilterOutputRectifier

DC Output

Control
Circuitry
Line
Input

Power
Inverter
Input
Rectifier

http://onsemi.com
94

Table 12–4. Full–Bridge Semiconductor Selection Chart
Output Power

500 W

750 W

1000 W

Input Voltage (Vin)

120 V

220 V
240 V

120 V

220 V
240 V

120 V

220 V
240 V

MOSFET Requirements:
Max Working Curren (Iw)
Max Working Voltage (Vw)

5.7 A
190 V

3.1 A
380 V

8.6 A
190 V

4.7 A
380 V

11.5 A
190 V

6.25 A380 V

Power MOSFETs Recommended:
Metal (TO–204AA) (TO–3)
Plastic (TO–220AB)
Plastic (TO–218AC)

MTM8N20
MTP8N20—

MTM4N45
MTP4N45—

MTM10N25
MTP10N25—

MTM7N45
MTP4N45
MTH7N45

MTM15N20
MTP12N20
MTH15N20

MTM7N45—
MTH7N45

Input Rectifiers:
Max Working Current (Iw)
Recommended Types

4.6 A
MDA3506

2.5 A
MDA3510

7.0 A

3.8 A

9.25 A

5.0 A

Output Rectifiers:
Recommended types for
output voltage of: 5.0 V
10 V
20 V
50 V
100 V

MBR20035CT
MUR10010CT
MUR10015CT
MUR3015PT
MUR804PT

Recommended Control Circuits

MBR30035CT
MUR10010CT*
MUR10015CT
MUR3015PT*
MUR3040PT

MBR30035CT*
MUR10010CT*
MUR10015CT*
MUR10015CT
MUR3040PT

SG1525A, SG1526, TL494 Inverter Control Circuit
MC3423 Overvoltage Detector
Error Amplifier: Single TL431; Dual–LM358
Quad MC3403, LM324, LM2902*More than one device per leg, matched.

The effective current limit of today’s low cost TO–218 discrete transistors (250 mil die) is somewherein the 10 A to 20 A area. Once this limit is reached, the designer generally changes to the full–bridge
configurations shown in Figure 12–7. Because full line rather than half is applied to the primary winding,the power out can be almost double that of the half–bridge with the same switching transistors. Power
Darlington transistors are a logical choice for higher power control with current, voltage and speed
capabilities allowing very high performance and cost effective designs. Another variation of the half–bridgeis the split winding circuit, shown in Figure 12–5. A diode clamp can protect the lower transistor but asnubber or zener clamp must still be used to protect the top transistor from switching transients. Because
both emitters are at an ac ground point, expensive drive transformers can now be replaced by lower costcapacitively–coupled drive circuits.

Figure 12–7. Full–Bridge Converter(200 W to 1.0 kW)+ Vin+ VoutCC

http://onsemi.com
95

SECTION 13
SWITCHING REGULATOR DESIGN EXAMPLES
In addition to the application materials in this data book, ON Semiconductor publishes several
application notes which contain basic information on the design of power supplies using a variety of ON
Semiconductor Analog ICs. AN920 describes in detail the principles of operation of the MC34063A andµA78S40 Switching Regulator Subsystems. Several converter design examples and numerous
applications circuits with test data are included in this application note. The circuit techniques describedin this note are also applicable to the MC34163 and MC34165 Power Switching Regulators.
Operating details of the MC34129 Current Mode Switching Regulator Controller, and examples of its
use with ON Semiconductor SENSEFET products, are provided in AN976. The application note AN983
focuses on a 400 W half-bridge power supply design which uses the TL494 PWM control circuit. The TL594
can be used in this same application.
Essentially all of the data sheets for newer power supply control and supervisory circuits include
extensive applications information with test conditions and performance results. Many data sheets also
include printed circuit board layouts for some key applications so that the designer can evaluate theintegrated circuits in an actual power supply. This data book presents all data sheets in their entirety sothat the applications information is readily available for each device.

http://onsemi.com
96

SECTION 14
POWER SUPPLY SUPERVISORY
AND PROTECTION CONSIDERATIONSThe use of SCR crowbar overvoltage protection (OVP) circuits has been, for many years, a popularmethod of providing protection from accidental overvoltage stress for the load. In light of the recent
advances in LSI circuitry, this technique has taken on added importance. It is not uncommon to haveseveral hundred dollars worth of electronics supplied from a single low voltage supply. If this supply were
to fail due to component failure or other accidental shorting of higher voltage supply busses to the low
voltage bus, several hundred dollars worth of circuitry could literally go up in smoke. The small additional
investment in protection circuitry can easily be justified in such applications.

A. The Crowbar Technique
One of the simplest and most effective methods of obtaining overvoltage protection is to use a“crowbar” SCR placed across the equipment’s dc power supply bus. As the name implies, the SCR is usedmuch like a crowbar would be, to short the dc supply when an overvoltage condition is detected. Typicalcircuit configurations for this circuit are shown on Figure 14–1. This method is very effective in eliminating
the destructive overvoltage condition. However, the effectiveness is lost if the OVP circuitry is not reliable.

Figure 14–1. Typical Crowbar OVP Circuit Configurations

Vout

Vin
DC
Power
Supply

+
Cout

*

Vin
DC
Power
Supply

OV
Sense

Vout
Cout

+

OV
Sense

*Needed if supply not current–limited.

http://onsemi.com
97

Figure 14–2. Crowbar SCR Surge Current Waveform
I

Ipk

di
dt
Surge Due to
Output Capacitor

Current Limited
Supply Outputt

B. SCR Considerations
Referring to Figure 14–1, it can easily be seen that, when activated, the crowbar SCR is subjected toa large current surge from the filter and output capacitors. This large current surge, illustrated in Figure
14–2, can cause SCR failure or degradation by any one of three mechanisms: di/dt, peak surge current,or I2 t. In many instances the designer must empirically determine the SCR and circuit elements which will
result in reliable and effective OVP operation. To aid in the selection of devices for this application, ON
Semiconductor has characterized several devices specifically for crowbar applications. A summary ofthese specifications and a selection guide for this application is shown in Table 14–1. This significantly
reduces the amount of empirical testing that must be done by the designer. A good understanding of thefactors that influence the SCR’s di/dt and surge current capability will greatly simplify the total circuit designtask.
Table 14–1. Crowbar SCRs
Device Type**

Peak Discharge Current*

di/dt*

MCR67
MCR68
MCR69
MCR70
MCR71

300 A
300 A
750 A
850 A
1700 A

75 A/µs
75 A/µs
100 A/µs
100 A/µs
200 A/µs* tw = 1.0 µs, exponentially decaying** All devices available with 25, 50, and 100 V ratings

1. di/dt — As the gate region of the SCR is driven on, its area of conduction takes a finite amount of timeto grow, starting as a very small region and gradually spreading. Since the anode current flows throughthis turned–on gate region, very high current densities can occur in the gate region if high anode currents
appear quickly (di/dt). This can result in immediate destruction of the SCR or gradual degradation of its
forward blocking voltage capabilities, depending upon the severity of the occasion.
The value of di/dt that an SCR can safely handle is influenced by its construction and the characteristicsof the gate drive signal. A center–gate–fire SCR has more di/dt capability than a corner–gate–fire type, andheavily overdriving (3 to 5 times IGT) the SCR gate with a fast <1.0 µs rise time signal will maximize its di/dt
capability. A typical maximum di/dt in phase control SCRs of less than 50 A rms rating might be 200 A/µs,
assuming a gate current of five times IGT and <1.0 µs rise time. If having done this, a di/dt problem still
exists, the designer can also decrease the di/dt of the current saveform by adding inductance in series with

http://onsemi.com
98the SCR, as shown in Figure 14–3. Of course, this reduces the circuit’s ability to rapidly reduce the dc bus
voltage, and a tradeoff must be made between speedy voltage reduction and di/dt.
2. Surge Current — If the peak current and/or the duration of the surge is excessive, immediate
destruction due to device overheating will result. The surge capability of the SCR is directly proportional
to its die area. If the surge current cannot be reduced (by adding series resistance, see Figure 14–3) toa safe level which is consistent with the system’s requirements for speedy bus voltage reduction, thedesigner must use a higher current SCR. This may result in the average current capability of the SCR
exceeding the steady state current requirements imposed by the dc power supply.
Figure 14–3. Circuit Elements Affecting SCR Surge & di/dt

RLead
OutputCapacitor

ESR

LLead
R*
L*

ESL

*R and L
empiricallydetermined(For additional information on SCRs in crowbar applications refer to Characterizing the SCR for Crowbar Applications,
Al Pshaenich, ON Semiconductor AN789).

C. The Sense and Drive Circuit
In order to maximize the crowbar SCR’s di/dt capability, it should receive a fast rise timehigh–amplitude gate–drive signal. This must be one of the primary factors considered when selecting thesensing and drive circuitry. Also important is the sense circuitry’s noise immunity.
Noise immunity can be a major factor in the selection of the sense circuitry employed. If the sensing
circuit has low immunity and is operated in a noisy environment, nuisance tripping of the OVP circuit canoccur on short localized noise spikes, which would not normally damage
the load.
ThisZener
results
in excessive
Figure14–4. The
Sense
Circuitsystem down time. There are several types of sense circuits presently being used in OVP applications.
These can be classified into three types: zener, discrete, and “723.”
1. The Zener Sense Circuit — Figure 14–4 shows the use ofa zener to trigger the crowbar SCR. This method is NOT
recommended since it provides very poor gate drive and greatly
decreases the SCR’s di/dt handling capability, especially since
the SCR steals its own very necessary gate drive as it turns on.
Additionally, this method does not allow the trip point to be
adjusted except by zener replacement.

NO!

2. The Discrete Sense Circuit — A technique which canprovide adequate gate drive and an adjustable, lowtemperature coefficient trip point is shown in Figure 14–5.
While overcoming the disadvantages of the zener sense circuit, this technique requires many components
and is more costly. In addition, this method is not particularly noise immune and often suffers from nuisancetripping.

http://onsemi.com
99

3. The “723” Sense Circuit — By using an integrated circuit voltage regulator, such as the industry
standard “723” type, a considerable reduction in component count can be achieved. This is illustrated in
Figure 14–6. Unfortunately, this technique is not noise immune, and suffers an additional disadvantage inthat it must be operated at voltages above 9.5 V.
Figure 14–5. The Discrete Sense Circuit

Figure 14–6. The “723” Sense Circuit+

4. The MC3423 — To fill the need for a low cost, low complexity method of implementing crowbar
overvoltage protection which does not suffer the disadvantages of previous techniques, an IC has beendeveloped for use as an OVP sense and drive circuit, the MC3423.
The MC3423 was designed to provide output currents of up to 300 mA with a 400 mA/µs rise time inorder to maximize the di/dt capabilities of the crowbar SCR. In addition, its features include:
1. Operation off 4.5 V to 40 V supply voltages.
2. Adjustable low temperature coefficient trip point.
3. Adjustable minimum overvoltage duration before actuation to reduce nuisancetripping in noisy environments.
4. Remote activation input.
5. Indication output.
5. Block Diagram — The block diagram of the MC3423 is shown in Figure 14–7. It consists of a stable
2.6 V reference, two comparators and a high current output. This output, together with the indication output
transistor, is activated either by a voltage greater than 2.6 V on Pin 3 or by a TTL/5.0 V CMOS high logic
level on the remote activation input, Pin 5.
The circuit also has a comparator–controlled current source which can be used in conjunction with andexternal timing capacitor to set a minimum overvoltage duration (0.5 µs to 1.0 ms) before actuation occurs.
This feature allows the OVP circuit to operate in noisy environments without nuisance tripping.
Figure 14–7. MC3423 Block Diagram

http://onsemi.com
100

VCC

1

Current
Source42
Vsense 1

-

+

+

-

Vref
2.5 V

8
Output
7

3

5
RMT.
ACT.

Vsense 2

VEE

6
Indication
Out

6. Basic Circuit Configuration — The basic circuit configuration of the MC3423 OVP is shown in
Figure 14–8. In this circuit the voltage sensing inputs of both the internal amplifiers are tied together forsensing the overvoltage condition. The shortest possible propagation delay is thus obtained. The thresholdor trip voltage at which the MC3423 will trigger and supply gate drive to the crowbar SCR, Q1, is determinedby the selection of R1 and R2. Their values can be determined by the equations given in Figure 14–8 orby the graph shown in Figure 14–9. The switch (S1) shown in Figure 14–8 may be used to reset the SCR
crowbar. Otherwise, the power supply, across which the SCR is connected, must be shut down to resetthe crowbar. If a non current–limited supply is used a fuse or circuit breaker, F1, should be used to protect
the SCR and/or the load.
Figure 14–8. MC3423 Basic Circuit Configuration(+)*(+ Sense Lead)

F1
R1

1
2

Power
Supply3Q1
8MC3423

To
Load

RG

7

R2

S1*
(- Sense Lead)

R
R
Vtrip = Vref (1 + 1 ) ≈ 2.6 V (1 + 1 )
R2
R2

(-)

R2 ≤ 10 kΩ for minimum drift*Needed if supply is not current–limited

7. MC3423 Programmable Configuration — In many instances, MC3423 OVP will be used in a noisy
environment. To prevent false tripping of the OVP circuit by noise which would not normally harm the load,

http://onsemi.com
101

MC3423 has a programmable delay feature. To implement this feature, the circuit configuration of
Figure 14–10 is used.
Here a capacitor is connected from Pin 3 and Pin 4 to VEE. The value of this capacitor determines theminimum duration of the overvoltage condition (tD) which is necessary to trip the OVP. The value of CD canbe found from Figure 14–11. The circuit operates in the following manner: when VCC rises above the trip
point set by R1 and R2, the internal current source begins charging the capacitor, CD, connected to Pins
3 and 4. If the overvoltage condition remains present long enough for the capacitor voltage, VCD to reachVref, the output is activated. If the overvoltage condition disappears before this occurs, the capacitor isdischarged at a rate 10 times faster than the charging rate, resetting the timing feature until the next
overvoltage condition occurs.
8. Indication Output — An additional output for use as an indicator of OVP activation is provided by theMC3423. This output (Pin 6) is an open–collector transistor which saturates when the MC3423 OVP is
activated. It will remain in a saturated state until the SCR crowbar pulls the supply voltage, VCC, below
4.5 V as in Figure 14–10. This output can be used to clock an edge triggered flip–flop whose output inhibits
or shuts down the power supply when the OVP trips. This reduces or eliminates the heatsinking
requirements for the crowbar SCR.

http://onsemi.com
102

Figure 14–9. R1 versus Trip Voltage
for the MC3423 OVP(+)

30
R1, RESISTANCE (kΩ )Figure 14–10. MC3423 Configuration for
Programmable Minimum Duration of
Overvoltage Condition Before Tripping

Max

Typ

R2 = 2.7 k
20

R3

R1
Power
SupplyMin

1 6
2

MC3423
3

R2

10

8

RG

5

4

Indication
Out

7
CD

0

0

5.0

10
15
20
Vtrip, TRIP VOLTAGE (V)

25

(-)
-

30
R3 ≥

Vtrip
10 mA

9. Remote Activation Input — Another feature of the MC3423 is its Remote Activation Input, Pin 5. If thevoltage on this CMOS/TTL compatible input is held below 0.7 V, the MC3423 operates normally. However,
if it is raised to a voltage above 2.0 V, the OVP output is activated independent of whether or not an
overvoltage condition is present.
This feature can be used to accomplish an orderly and sequenced shutdown of system power supplies
during a system fault condition. In addition, the Indication Output of one MC3423 can be used to activate
another MC3423, if a single transistor inverter is used to interface the former’s Indication Output to thelatter’s Remote Activation Input.

D. MC3425 Power Supply Supervisory Circuit
In addition to the MC3423 a second IC, the MC3425 has been developed. Similar in many respects
to the MC3423, the MC3425 is a power supply supervisory circuit containing all the necessary functions
required to monitor over and undervoltage fault conditions. The block diagram is shown below in
Figure 14–12. The Overvoltage (OV) and Undervoltage (UV) Input Comparators are both referenced to
an internal 2.5 V regulator. The UV Input Comparator has a feedback activated 12.5 µA current sink (IH)
which is used for programming the input hysteresis voltage (VH). The source resistance feeding this input(RH) determines the amount of hysteresis voltage by VH = IHRH = 12.5 × 10–6 RH.
Figure 14–11. CD versus Minimum Overvoltage Duration, tD for The MC3423 OVP

C D, CAPACITANCE (µ F)

1.0

0.1

0.01

0.001

0.0001
0.001

0.01

0.1
tD, DELAY TIME (ms)http://onsemi.com
103

1.0

10

Separate Delay pins (OV DLY, UV DLY) are provided for each channel to independently delay the Drive
and Indicator outputs, thus providing greater input noise immunity. The two Delay pins are essentially theoutputs of the respective input comparators, and provide a constant current source, IDLY(source), of typically
200 µA when the noninverting input voltage is greater than the inverting input level. A capacitor connectedfrom these Delay pins to ground, will establish a predictable delay time (tDLY) for the Drive and Indicator
outputs. The Delay pins are internally connected to the non–inverting inputs of the OV and UV Output
Comparators, which are referenced to the internal 2.5 V regulator. Therefore, delay time (tDLY) is basedon the constant current source, IDLY(source), charging the external delay capacitor (CDLY) to 2.5 V.
Vref CDLY
2.5 CDLY
tDLY === 12500 CDLY
IDLY(source)
200 µA
Figure 14–13 provides CDLY values for a wide range of time delays. The Delay pins are pulled low when
the respective input comparator’s non–inverting input is less than the inverting input. The sink current
IDLY(sink) capability of the Delay pins is ≥1.8 mA and is much greater than the typical 200 µA source current,
thus enabling a relatively fast delay capacitor discharge time.
The Overvoltage Drive Output is a current–limited emitter–follower capable of sourcing 300 mA at aturn–on slew rate of 2.0 A/µs, ideal for driving crowbar SCRs. The Undervoltage Indicator Output is an
open–collector NPN transistor, capable of sinking 30 mA to provide sufficient drive for LEDs, small relays
or shutdown circuitry. These current capabilities apply to both channels operating simultaneously,
providing device power dissipation limits are not exceeded. The MC3425 has an internal 2.5 V bandgap
reference regulator with an accuracy of ± 4.0% for the basic devices.

Figure 14–12. Block Diagram
VCC
8
+

+

200µA
OV Sense

+

3

-

Input
Comp.
OV

+

+
Output
Comp.
OV
+
200µA

+

UV Sense

-

4

1

+
Output
Comp.
UV
-

Input
Comp.
UV

6
+

2.5V
Reference
Regulator

IH
12.5µA2

5
INPUT SECTIONUV OVDLY DLY

Note: All voltages and currents are nominal.

http://onsemi.com
104

7
Gnd
OUTPUT SECTIONOV Drive
UV IndicatorFigure 14–13. Output Delay Time versus Delay Capacitancet DLY , OUTPUT DELAY TIME (ms)100

VCC = 15 V
TA = 25°C

10
1.0
0.1

tDLY =
0.01

0.001
0.0001

2.5 CDLY
200 µA

0.001
0.01
0.1
1.0
CDLY, DELAY PIN CAPACITANCE (µF)

10.0

E. MC34064 and MC34164 Series
The MC34064 and MC34164 series are two families of undervoltage sensing circuits specificallydesigned for use as reset controllers in microprocessor–based systems. They offer the designer an
economical solution for low voltage detection with a single external resistor. Both parts feature a trimmed
bandgap reference, and a comparator with precise thresholds and built–in hysteresis to prevent erratic
reset operation.
The two families of undervoltage sensing circuits,taken together, cover the needs of the most
Input
2
commonly specified power supplies used in
1
MCU/MPU systems. Key parameter specifications ofReset
the MC34164 family were chosen to complement theMC34064 series. The table summarizes criticalparameters of both families. The MC34064 fulfills theneeds of a 5.0 V ± 5% system and features a tighter
hysteresis specification. The MC34164 series covers+
5.0 V ± 10% and 3.0 V ± 5% power supplies withsignificantly lower power consumption, making them
1.2 Vrefideal for applications where extended battery life
is required such as consumer products or hand
held equipment.
Gnd 3
Applications include direct monitoring of the 5.0 V
MPU/logic power supply used in appliance,= Sink Only Positive True Logic+
automotive, consumer, and industrial equipment.
The MC34164 is specifically designed for battery
powered applications where low bias current (1/25thof the MC34064’s) is an important characteristic.

________________________________REFERENCES
1. Characterizing the SCR for Crowbar Applications, Al Pshaenich, ON Semiconductor AN789. (Out of Print)
2. Semiconductor Considerations for DC Power Supply SCR Crowbar Circuits, Henry Wurzburg, Third National Sold–State Power Conversion
Conference, June 25, 1976.
3. Is a Crowbar Enough? Willis C. Pierce Jr., Hewlett–Packard, Electronic Design 20, Sept. 27, 1974.
4. Transient Thermal Response — General Data and Its Use, Bill Roehr and Brice Shiner, ON Semiconductor AN569. (Out of Print)

http://onsemi.com
105

SECTION 15
HEATSINKING
A. The Thermal Equation
A necessary and primary requirement for the safe operation of any semiconductor device, whether it
be an IC or a transistor, is that its junction temperature be kept below the specified maximum value given
on its data sheet. The operating junction temperature is given by:
TJ = TA + PD θJA
where:(15.1)

TJ = junction temperature (°C)
TA = ambient air temperature (°C)
PD = power dissipated by device (W)θJA = thermal resistance from junction–to–ambient air (°C/W)

The junction–to–ambient thermal resistance (θJA) in Equation (15.1), can be expressed as a sum ofthermal resistances as shown below:
θJA = θJC + θCS + θSA
where: θJC = junction–to–case thermal resistance(15.2)

θCS = case–to–heatsink thermal resistanceθSA = heatsink–to–ambient thermal resistance
Equation (15.2) applies only when an external heatsink is used. If no heatsink is used, θJA is equal to thedevice package θJA given on the data sheet.
θJC depends on the device and its package (case) type, while θSA is a property of the heatsink and θCS
depends on the type of package/heatsink interface employed. Values for θJC and θSA are found on thedevice and heatsink data sheets, while θCS is given in Table 15–1.
Table 15–1. θCS For Various Packages & Mounting Arrangements
θCS
Metal–to–Metal*

Using an Insulator*

Case

Dry

With Heatsink
CompoundWith Heatsink
CompoundType

TO–204

0.5°C/W

0.1°C/W

0.36°C/W
0.28°C/W

3 mil MICA
Anodized Aluminum

TO–2201.2°C/W

1.0°C/W

1.6°C/W

2 mil MICA

*Typical values; heatsink surface should be free of oxidation, paint, and anodization

Examples showing the use of Equations (15.1) and (15.2) in thermal calculations are as follows:
Example 1: Find required heatsink θSA for an MC7805CT, given:
TJ(max) (desired) = +125°C
TA(max) = +70°C
PD = 2.0 W
http://onsemi.com
106

Mounted directly to heatsink with silicon thermal grease at interface:
1. From MC7805CT data sheet, θJC = 5°C/W
2. From Table 15–1. θCS = 1.6°C/W
3. Using Equation (15.1) and (15.2), solve for θSA:
(TJ – TA)– θCS – θJC
PD(125 – 70)
θSA =– 5.0 – 1.6 (≤ 20.9°C/W required)
2

θSA =

Example 2: Find the maximum allowable TA for an unheatsinked MC78L15CT, given:
TJ(max) (desired) = +125°C
PD = 0.25 W
1. From MC78L15CT data sheet, θJA = 200°C/W
2. Using Equation (15.1), find TA:
TA = Tj – PD θJA= 125 – 0.25 (200)= +75°C

B. Selecting a Heatsink
Usually, the maximum ambient temperature, power being dissipated, the TJ(max), and θJC for thedevice being used are known. The required θSA for the heatsink is then determined using Equations (15.1)
and (15.2), as in Example 1. The designer may elect to use a commercially available heatsink, or if
packaging or economy demands it, design his own.

1. Commercial Heatsinks
As an aid in selecting a heatsink, a representative listing is shown in Table 15–2. This listing is by nomeans complete and is only included to give the designer an idea of what is available.
Table 15–2. Commercial Heatsink Selection Guide
TO–204AA (TO–3)

θSA*(°C/W)

Manufacturer/Series or Part Number

0.3–1.0

Thermalloy — 6441, 6443, 6450, 6470, 6560, 6590, 6660, 6690

1.0–3.0

Wakefield — 641
Thermalloy — 6123, 6135, 6169, 6306, 6401, 6403, 6421, 6423, 6427, 6442, 6463, 6500

3.0–5.0

Wakefield — 621, 623
Thermalloy — 6606, 6129, 6141, 6303
IERC — HP
Staver — V3–3–2

5.0–7.0

Wakefield — 690
Thermalloy — 6002, 6003, 6004, 6005, 6052, 6053, 6054, 6176, 6301
IERC — LB
Staver — V3–5–2

7.0–10Wakefield — 672
Thermalloy — 6001, 6016, 6051, 6105, 6601
IERC — LA µP
Staver — V1–3, V1–5, V3–3, V3–5, V3–7

10–25

Thermalloy — 6013, 6014, 6015, 6103, 6104, 6105, 6117

*All values are typical as given by the manufacturer or as determined from characteristic curves supplied by the manufacturer.

http://onsemi.com
107

Table 15–2. Commercial Heatsink Selection Guide (continued)
TO–204AA (TO–5)
θSA*(°C/W)

Manufacturer/Series or Part Number

12 to 20

Wakefield — 260
Thermalloy — 1101, 1103
Staver — V3A–5

20 to 30

Wakefield — 209
Thermalloy — 1116, 1121, 1123, 1130, 1131, 1132, 2227, 3005
IERC — LP
Staver — F5–5

30 to 50

Wakefield — 207
Thermalloy — 2212, 2215, 225, 2228, 2259, 2263, 2264
Staver — F5–5, F6–5
Wakefield — 204, 205, 208
Thermalloy — 1115, 1129, 2205, 2207, 2209, 2210, 2211, 2226, 2230, 2257, 2260, 2262
Staver — F1–5, F5–5

TO–204AB
θSA*(°C/W)

Manufacturer/Series or Part Number

5.0 to 10

IERC H P3 Series
Staver — V3–7–225, V3–7–96

10 to 15

Thermalloy — 6030, 6032, 6034
Staver — V4–3–192, V–5–1

20 to 30

Wakefield — 295
Thermalloy — 6025, 6107

15 to 20

Thermalloy — 6106
Staver — V4–3–128, V6–2

TO–226AA (TO–92)
θSA*(°C/W)
46
50
57
65
72
80 to 90
85

Manufacturer/Series or Part Number
Staver F5–7A, F5–8
IERC AUR
Staver F5–7D
IERC RU
Staver F1–8, F2–7
Wakefield 292
Thermalloy 2224
DUAL–IN–LINE–PACKAGE ICs

20
30
32
34
45
60

Thermalloy — 6007
Thermalloy — 6010
Thermalloy — 6011
Thermalloy — 6012
IERC — LIC
Wakefield — 650, 651*All values are typical as given by the manufacturer or as determined from characteristic curves supplied by the manufacturer.

Staver Co., Inc.: 41–51 N. Saxon Ave., Bay Shore, NY 11706
IERC: 135 W. Magnolia Blvd., Burbank, CA 91502
Thermalloy: P.O. Box 34829, 2021 W. Valley View Ln. Dallas, TX
Wakefield Engin Ind: Wakefield, MA 01880

http://onsemi.com
108

2. Custom Heatsink Design
Custom heatsinks are usually either forced air cooled or convection cooled. The design of forced aircooled heatsinks is usually done empirically, since it is difficult to obtain accurate air flow measurements.
On the other hand, convection cooled heatsinks can be designed with fairly predictable characteristics. It
must be emphasized, however, that any custom heatsink design should be thoroughly tested in the actual
equipment configuration to be certain of its performance. In the following sections, a design procedure forconvection cooled heatsinks is given.
Obviously, the basic goal of any heatsink design is to produce a heatsink with an adequately low
thermal resistance, θSA. Therefore, a means of determining θSA is necessary in the design. Unfortunately,a precise calculation method for θSA is beyond the scope of this book.* However, a first order approximation
can be calculated for a convection cooled heatsink if the following conditions are met:
1. The heatsink is a flat rectangular or circular plate whose thickness is smaller than its length or width.
2. The heatsink will not be located near other heat radiating surfaces.
3. The aspect ratio of a rectangular heatsink (length:width) is not greater than 2:1.
4. Unrestricted convective air flow.
For the above conditions, the heatsink thermal resistance can be approximated by:θSA 
where:

1(°C/W)Aη (Fchc + ∈Hr)

(15.3)

A = area of the heatsink surface
η = heatsink effectivenessFc = convective correction factor
hc = convection heat transfer coefficient∈ = emissivity
Hr = normalized radiation heat transfer coefficient

The convective heat transfer coefficient, hc, can be found from Figure 15–1. Note that it is a functionof the heatsink fin temperature rise (TS – TA) and the heatsink significant dimension (L). The fin temperaturerise (TS – TA) is given by:(15.4)
TS – TA = θSA PD
where:
TS = heatsink temperature
TA = ambient temperatureθSA = heatsink–to–ambient thermal resistance
PD = power dissipatedhc , CONVECTION COEFFICIENT(W/In 2 - °C) x 10 -3

Figure 15–1. Convection Coefficient (hc)
10
9.0
8.0
7.0
6.0

L = 1"

5.0

2"

4.0

4"
10"

3.0

2.0

*If greater precision is desired, ormore information on heat flow andheatsinking is sought, consult thereferences list at the end of thissection.

10

20
30
50
70
100
TS - TA, FIN TEMPERATURE RISE OF PLATE (°C)

http://onsemi.com
109

200

The significant heatsink dimension (L) is dependent on the heatsink shape and mounting place andis given in Table 15–3. The convective correction factor (Fc) is likewise dependent on shape and mounting
plane of the heatsink and is also given in Table 15–3.
Table 15–3. Significant Dimension (L) and Correction Factor (Fc)for Convection Thermal ResistanceSignificant Dimension L
Surface

Rectangular Plane

Position

L

VerticalCorrection Factor Fc
Position

Fc

Height (max 2 ft)

Vertical Plane

1.0

Horizontal

length × width
length + width

Horizontal Plane
both surfaces
exposed

1.35

Vertical

π / 1 × diameterTop only exposed

0.9

Circular Plane

The normalized radiation heat transfer coefficient (Hr) is dependent on the ambient temperature (TA) andthe heatsink temperature rise (TS – TA) given by Equation (15.4). Hr can be determined from Figure 15–2.

H r , NORMALIZED RADIATION COEFFICIENT(W/In 2 - °C) x 10 -2

Figure 15–2. Normalized Radiation Coefficient (Hr)
2.0
1.5

1.0
0.9
0.8
0.7

TA = 100°C
75°C
50°C

0.6
0.5
0.4

25°C
10

20
30
50
70
100
TS - TA, TEMPERATURE RISE OF PLATE (°C)

200

The emissivity (∈) can be found in Table 15–4 for various heatsink surfaces.
Table 15–4. Typical Emissivities of Common Surfaces
Surface

Emissivity (∈)

Alodine on Aluminum
Aluminum, Anodized
Aluminum, Polished
Copper, Polished
Copper, Oxidized
Rolled Sheet SteelAir Drying Enamel (any color)
Oil Paints (any color)
Varnishhttp://onsemi.com
110

0.15
0.7 to 0.9
0.05
0.07
0.70
0.66
0.85 to 0.91
0.92 to 0.96
0.89 to 0.93

Finally, the heatsink efficient (η) can be found from the nomograph of Figure 15–3. Use of thenomograph is as follows:a) Find hT = Fchc + ∈Hr from Figures 15–1, 15–2 and Tables 15–3 and 15–4,
and locate this point on the nomograph.
b) Draw a line from hT through chosen heatsink fin thickness (x) to find α.
c) Determine D for the heatsink shape as given in Figure 15–4 and draw a linefrom this point through α, which was found in (b), to determine η.
d) If power dissipating element is not located at heatsink’s center of symmetry,multiply η by 0.7 (for vertically mounted plates only).
Note that in order to calculate θSA from Equation (15.3), it is necessary to know the heatsink size.
Therefore, in order to arrive at a suitable heatsink design, a trial size is selected, its θSA evaluated, and theoriginal size reduced or enlarged as necessary. This process is iterated until the smallest heatsink is
obtained that has the required θSA. The following design example is given to illustrate this procedure.
Figure 15–3. Fin Effectiveness Nomogram for Symmetrical Flat, Uniformly Thick Fins
D

∝

4.0

0.05

3.0

Fin Thickness
For
Aluminum

0.1

2.0

For
Copper

0.2

0.8
0.7
0.6
0.5
0.4

2.0

0.3

3.0
4.0
5.0

0.2

1.0

1.0

1.0

0.1

0.1

1.0

η
Fin Effectiveness

10

10

10

0.3
0.4
0.5

1.0

hT = FChC+∈Hr

0.01

0.01

94

0.001

0.001

0.0001

85

84
80

82

0.01

75

Inches

70
65

10.0

Inches

90

88

0.1

60

0.001

55

W/In2/°C

50

45

40
35
%

Figure 15–4. Determination of D for Use in η Nomograph of Figure 15–3

a

b

D

d

s

√ abπ , if a,b  S & b ≤ 2aD

http://onsemi.com
111sd , if ds2

Heatsink Design Example
Design a flat rectangular heatsink for use with a horizontally mounted power device on a PC board,
given the following:
1. Heatsink θSA = 25°C/W
2. Power to be dissipated, PD = 2.0 W
3. Maximum ambient temperature, TA = 50°C
4. Heatsink to be constructed from 1/8″ (0.125″) thick anodized aluminum.
a) First, a trial heatsink is chosen: 2″ × 3″ (experience will simplify this selection andreduce the number of necessary iterations.)b) The factors in Equation (15.3) are evaluated by using the Figures and Tables given:
A = 2″ × 3″ = 6 sq. in.
L = 6/5″ = 1.2 in. (from Table 15–3)
TS – TA = 50°C (from Figure 15–4)
hc = 5.8 × 10–3 W/in2 – °C (from Figure 15–1)
Fc = 0.9 (from Table 15–3)
Hr = 6.1 × 10–3 W/in2 – °C (from Figure 15–2)∈ = 0.9 (from Table 15–4)
hT = Fchc + Hr∈ = 10.7 × 10–3 W/in2 – °C
α = 0.13 (from Figure 15–3)
D = 1.77 (from Figure 15–4)
η > 0.94 1 (from Figure 15–3)c) Using Equation (15.3), find θSA:θSA 

1
= 16.66°C/W < 25°C/W
Aη (Fchc + ∈Hr)d) Since 2″ × 3″ is too large, try 2″ × 2″. Following the same procedure, θSA is foundto be 25°C/W, which exactly meets the design requirements.

SOIC MINIATURE IC PLASTIC PACKAGE
Thermal Information
The maximum power consumption an integrated circuit can tolerate at a given operating ambient
temperature, can be found from the equation:
TJ(max) – TA
PD(T =
A)
RθJA (typ)where: PD(TA) = power dissipation allowable at a given operating ambient temperature,
TJ(max) = maximum operating junction temperature as listed in the maximum ratings section,
TA = desired operating ambient temperature,
RθJA (typ) = typical thermal resistance junction–to–ambient.
Maximum Ratings
RatingSymbol

Value

Unit

Operating Ambient Temperature RangeTA

0 to +70– 40 to +85°C

Operating Junction Temperature

TJ

150

°C

Storage Temperature Range

Tstg– 55 to +150

°C

http://onsemi.com
112

THERMAL CHARACTERISTICS OF SOIC PACKAGES
Measurement specimens are solder mounted on a Philips SO test board #7322–078, 80873 in still air.
No auxiliary thermal conduction aids are used. As thermal resistance varies inversely with die area, a given
package takes thermal resistance values between the max and min curves shown. These curves represent
the smallest (2000 square mils) and largest (8000 square mils) die areas expected to be assembled in the
SOIC package.
Figure 15–5. Thermal Resistance,
Junction–to–Ambient (°C/W)

Min. Die Size
2K Mils2

140 _
120

_

Max. Die Size
See Figure 15-6
8K Mils2
for Heatsink
Detail
||||SO-8
SOP-8*SO-14
SO-16
PACKAGE STYLE

100 _

3.2

150

JUNCTIONTOAIR (° C/W)

160_

R θ JA, THERMAL RESISTANCE

°C/W
θJA

170
_

130

2.4

110

Graph represents symmetrical layout

90

L

70

10

20

Several families of voltage regulators and power control ICs have been
introduced in surface mounted packages which were developed by the
Analog IC Division. The SOP–8 and SOP–16L packages have external
dimensions which are identical to the standard SO–8 and SO–16L surface
mount devices, but the center four leads of the packages are all connectedto the leadframe die flag. This internal modification decreases the package
thermal resistance and therefore increases its power dissipation capability.
This advantage is fully realized when the package is mounted on a printed
circuit board with a single pad for the four center leads. This large area ofcopper then acts as an external heat spreader, efficiently conducting heataway from the package.

JUNCTIONTOAIR (° C/W)

R θ JA, THERMAL RESISTANCE

80

2.4

ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ

Graph represents symmetrical layout

70
L

60

2.0 oz.
CopperL

50

3.0 mm

RθJA

40
30

2.8

PD(max) for TA = +50°C

0

10

2.0
1.6
1.2
0.8
0.4

20

30

40

0
50

L, LENGTH OF COPPER (mm)http://onsemi.com
113

PD, MAXIMUM POWER DISSIPATION (W)

Figure 15–7. SOP–16L Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length
90

30

L, LENGTH OF COPPER (mm)SOP–8 and SOP–16L Packaged Devices

100

3.0 mm

RθJA
0

2.0
1.6

2.0 oz.
CopperL

50
30

Data taken using Philips SO test board #7322-078, 80873*SOP-8 using standard SO-8 footprint minimum pad size

2.8

PD(max) for TA = +50°C

40

1.2
0.8
0.4
50

PD, MAXIMUM POWER DISSIPATION (W)

_

200
180

Figure 15–6. SOP–8 Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length

THERMAL CHARACTERISTICS OF DPAK AND D2PAK PACKAGE
The evaluation was performed using an active device (4900 square mils) mounted on 2.0 ounce copper
foil epoxied to a GIO type printed circuit board. Measurements were made in still air and no auxiliary
thermal conduction aids were used. The size of a square copper pad was varied, and all measurements
were made with the unit mounted as shown in Figure 15–8. The curve shown in Figure 15–8 is a plot ofjunction–to–air thermal resistance versus the length of the square copper pad in millimeters. This showsthat when the DPAK is mounted on a 10 mm × 10 mm square pad of 2.0 ounce copper it has a thermal
resistance which is comparable to a TO–220 device mounted vertically without additional heatsinking.

JUNCTIONTOAIR (° C/W)

R θ JA, THERMAL RESISTANCE

100
90

2.0

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ

80
Minimum
Size Pad

70
60
50
40

2.4

PD(max) for TA = +50°C

Free Air
Mounted
Vertically

2.0 oz. Copper
L

1.6

L

1.2

0.4

RθJA
0

5.0

10

15

0.8

20

25

30

0

PD, MAXIMUM POWER DISSIPATION (W)

Figure 15–8. DPAK Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length

L, LENGTH OF COPPER (mm)The thermal characteristics of the D2PAK are shown in Figure 15–9. The device was mounted on
2.0 oz. copper on an FR4–type P.C. board. The maximum power dissipation was measured with a junction
temperature of 150°C.

JUNCTIONTOAIR (° C/W)

R θ JA, THERMAL RESISTANCE

80
70

3.0

Free Air
Mounted
Vertically

60

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
2.0 oz. Copper
L

Minimum
Size Pad

50

2.5
2.0

L

1.5

40
RθJA
30

3.5

PD(max) for TA = +50°C

0

5.0

10

15

20

L, LENGTH OF COPPER (mm)http://onsemi.com
114

25

30

1.0

PD, MAXIMUM POWER DISSIPATION (W)

Figure 15–9. 3–Pin and 5–Pin D2PAK
Thermal Resistance and Maximum Power
Dissipation versus P.C.B. Copper LengthON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICESAND REPRESENTATIVESUNITED STATESALABAMA
Huntsville . . . . . . . . . . . . . . . . . . 256–774–1000

CALIFORNIA
Encino . . . . . . . . . . . . . . . . . . . . . 818–654–9040
Irvine . . . . . . . . . . . . . . . . . . . . . . 949–623–8485
Sacramento (Sales Rep) . . . . . . 916–652–0268
San Diego . . . . . . . . . . . . . . . . . 858–621–5100
Santa Clara (Sales Rep) . . . . . . . 408–350–4800

COLORADO
Littleton . . . . . . . . . . . . . . . . . . . . 303–256–5884

FLORIDA
Boca Raton . . . . . . . . . . . . . . . . 561–995–1466
Tampa . . . . . . . . . . . . . . . . . . . . . 813–286–6181

UNITED STATES (continued)
UTAH
Draper (Sales Rep) . . . . . . . . . . . 801–572–4010

Duluth . . . . . . . . . . . . . . . . . . . . . 888–793–3435
Chicago . . . . . . . . . . . . . . . . . . . 847–330–6959

INDIANA
Kokomo . . . . . . . . . . . . . . . . . . . 765–865–2085
Carmel (Sales Rep) . . . . . . . . . . . 317–848–9958

MASSACHUSETTS
Boston . . . . . . . . . . . . . . . . . . . . 781–376–4223

MICHIGAN
Livonia . . . . . . . . . . . . . . . . . . . . 734–953–6704

MINNESOTA
Plymouth . . . . . . . . . . . . . . . . . . 763–249–2360

NORTH CAROLINA
Raleigh . . . . . . . . . . . . . . . . . . . . 919–785–5025

PENNSYLVANIA
Philadelphia/Horsham . . . . . . . 215–997–4340

TEXAS
Dallas (Sales Rep) . . . . . . . . . . . . 972–680–2800

Herzelia . . . . . . . . . . . . . . 972 (0) 9–9609–111

ITALY

WASHINGTON
Seattle . . . . . . . . . . . . . . . . . . . . 425–646–7374

WASHINGTON, D.C.
. . . . . . . . . . . . . . . . . . . . . . . . . . . 410–884–4086

Milan . . . . . . . . . . . . . . . . . . 39 (0) 2–530–0951

JAPAN
Tokyo . . . . . . . . . . . . . . . . . . . 81–3–5740–2700

KOREA
Seoul . . . . . . . . . . . . . . . . . . . . . 82–2–528–2700

MALAYSIACANADAQUEBEC

Penang . . . . . . . . . . . . . . . . . . . 60–4–226–9368

Pointe Claire . . . . . . . . . . . . . . . 514–695–4599

ONTARIO
Toronto . . . . . . . . . . . . . . . . . . . . 905–812–0092

MEXICOGuadalajara . . . . . . . . . . . . . . . . 523–669–9100

PHILIPPINES
Muntinlupa City . . . . . . . . . . . . 63–2–842–7141

PUERTO RICOGEORGIAILLINOISINTERNATIONAL (continued)
ISRAELSan Juan . . . . . . . . . . . . . . . . . . 787–641–4100

INTERNATIONALBRAZILSINGAPORE

Sao Paulo . . . . . . . . . . . . . 55–011–3030–5244

CHINA
Beijing . . . . . . . . . . . . . . . . . 86–10–8518–2323
Chengdu . . . . . . . . . . . . . . . . . 86–28–678–4078
Shenzhen . . . . . . . . . . . . . . . 86–755–209–1128
Shanghai . . . . . . . . . . . . . . 86–21–6875–6677

CZECH REPUBLIC
Roznov . . . . . . . . . . . . . . 420 (0) 651–667–141

Singapore . . . . . . . . . . . . . . . . . . . 65–298–1768

SWEDEN
Solna . . . . . . . . . . . . . . . . . 46 (0) 8–5090–4680

TAIWAN
Taipei . . . . . . . . . . . . . . . . . 886–2–2718–9961

THAILAND
Bangkok . . . . . . . . . . . . . . . . . . 66–2–653–5031

UNITED KINGDOM
Aylesbury . . . . . . . . . . . . . 44 (0) 1296–610400

FINLAND
Vantaa . . . . . . . . . . . . . 358 (0) 9–85–666–460

FRANCE
Paris . . . . . . . . . . . . . . . 33 (0) 1–39–26–41–00

GERMANY
Munich . . . . . . . . . . . . . . 49 (0) 89–93–0808–0

HONG KONG
Hong Kong . . . . . . . . . . . . . . . . 852–2689–0088

http://onsemi.com
115

N. AMERICAN TECHNICAL SUPPORT
1–800–282–9855 Toll Free

ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONSDATA SHEET CLASSIFICATIONS
A Data Sheet is the fundamental publication for each individual product/device, or series of products/devices, containing detailed
parametric information and any other key information needed in using, designing–in or purchasing of the product(s)/device(s) it describes.
Below are the three classifications of Data Sheet: Product Preview; Advance Information; and Fully Released Technical Data
PRODUCT PREVIEWA Product Preview is a summary document for a product/device under consideration or in the early stages of development. The
Product Preview exists only until an “Advance Information” document is published that replaces it. The Product Preview is often
used as the first section or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer atthe bottom of the first page: “This document contains information on a product under development. ON Semiconductor reserves theright to change or discontinue this product without notice.”
ADVANCE INFORMATIONThe Advance Information document is for a device that is NOT fully qualified, but is in the final stages of the release process,and for which production is eminent. While the commitment has been made to produce the device, final characterization andqualification may not be complete. The Advance Information document is replaced with the “Fully Released Technical Data”
document once the device/part becomes fully qualified. The Advance Information document displays the following disclaimer atthe bottom of the first page: “This document contains information on a new product. Specifications and information herein are subject
to change without notice.”
FULLY RELEASED TECHNICAL DATAThe Fully Released Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces theAdvance Information document and represents a part that is fully qualified. The Fully Released Technical Data document is virtually
the same document as the Product Preview and the Advance Information document with the exception that it provides informationthat is unavailable for a product in the early phases of development, such as complete parametric characterization data. The Fully
Released Technical Data document is also a more comprehensive document than either of its earlier incarnations. This document
displays no disclaimer, and while it may be informally referred to as a “data sheet,” it is not labeled as such.
DATA BOOK
A Data Book is a publication that contains primarily a collection of Data Sheets, general family and/or parametric information,
Application Notes and any other information needed as reference or support material for the Data Sheets. It may also contain cross referenceor selector guide information, detailed quality and reliability information, packaging and case outline information, etc.
APPLICATION NOTEAn Application Note is a document that contains real–world application information about how a specific ON Semiconductor
device/product is used, or information that is pertinent to its use. It is designed to address a particular technical issue. Parts and/or softwaremust already exist and be available.
SELECTOR GUIDEA Selector Guide is a document published, generally at set intervals, that contains key line–item, device–specific information forparticular products or families. The Selector Guide is designed to be a quick reference tool that will assist a customer in determining theavailability of a particular device, along with its key parameters and available packaging options. In essence, it allows a customer to quickly“select” a device. For detailed design and parametric information, the customer would then refer to the device’s Data Sheet. The Master
Components Selector Guide (SG388/D) is a listing of ALL currently available ON Semiconductor devices.
REFERENCE MANUAL
A Reference Manual is a publication that contains a comprehensive system or device–specific descriptions of the structure and function(operation) of a particular part/system; used overwhelmingly to describe the functionality or application of a device, series of devices ordevice category. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).
HANDBOOKA Handbook is a publication that contains a collection of information on almost any give subject which does not fall into the Reference
Manual definition. The subject matter can consist of information ranging from a device specific design information, to system design, to
quality and reliability information.
ADDENDUM
A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in the
primary publication it supports. Individual addendum items are published cumulatively. The Addendum is destroyed upon the next revisionof the primary document.
http://onsemi.com
116

HB206/D
Rev. 4, Feb-2002

Linear & Switching Voltage
Regulator Handbook
ON Semiconductor

ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application bycustomer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any otherapplication in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC
products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of
the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATIONGLOBAL Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center
4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031
Phone: 81-3-5740-2700
Email: r14525@onsemi.com

N. American Technical Support: 800-282-9855 Toll Free USA/Canada

For additional information, please contact your local Sales
Representative

ON Semiconductor Website: http://onsemi.com

HB206/D