THE EUROPEAN APPROACH FOR EXSCALE AGES

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Cambrian explosion
Achieving performance through specialization

Copyright European Processor Initiative 20192/18/20

Courtesy Steve
Scott
2Cray CTO

TOP10 OVER THE LAST 10 YEARS
2009 – Nov.

2014 – Nov.

2019 – Nov.

(Post)Exascale

CPU only

9520

CPU + ACC.

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WHY? SOME OBVIOUS REASONS…

Linpack

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AI4

HPC BEFORE ARTIFICIAL INTELLIGENCE

Theoretical model

HPC Application

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Results

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HPC WITH ARTIFICIAL INTELLIGENCE
Theoretical model

HPC Application

Results

Results

Big Data

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AI

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HPC & AI AT EXASCALE: IT’S ALL ABOUT WORKFLOWS (1/2)
Edge
Computing

Edge
Computing

X86
Public Clouds

Realtime dataprocessing

Realtime dataprocessing

Theoritical modelSUMMITX86

HPC Application

FUGAKUsunway taihulight
Results

Results

Big Data

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

AI8

HPC & AI AT EXASCALE: IT’S ALL ABOUT WORKFLOWS (2/2)
Edge
Computing

Edge
ComputingRealtime dataprocessing

Europeanapproach?

Legacy X86

Public Clouds

Realtime dataprocessing

ü EU Architectureü EU HWü EU SWü Handle all complexity the others don’t know how to

RHEA (ARM)

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

RHEA +ACC.
(ARM+Risc-V)

RHEA + GPU(ARM+Nvidia/AMD)

RHEA + ***(ARM+Common Platform)
9HPC & AI AT EXASCALE: IT’S ALL ABOUT WORKFLOWS (2/2)
Edge
Computing

Edge
ComputingPublic Clouds

Realtime dataprocessing

Realtime dataprocessing

Europeanapproachü EU Architectureü EU HWü EU SWü Handle all complexity the others don’t know how toCompiler
CPUCPUCPU

Legacy X86

RHEA (ARM)

ACC. A

ACC. BRHEA +ACC(ARM+Risc-V)

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

ACC. CCPURHEA + GPU(ARM+Nvidia/AMD)

ACC. DCPURHEA + ***(ARM+Common Platform)

ACC. E

10THE DEVELOPER / USER STANDPOINT

Compiler (unified front-end)
OPENMP 5.0 / OpenCL / OPENACC / OPENAPI
Target A

Target B

Specific backend
Target C

RHEA

RHEA

RHEA

RHEA

RHEA

ACC. A

ACC. B

ACC. C

ACC. D

ACC. E

ACC. A
ACC. A
ACC. A

ACC. B
ACC. B
ACC. B

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

ACC. C
ACC. C
ACC. C

Target D

Target E

ACC. D
ACC. D
ACC. DACC. E
ACC. E
ACC. E
11EVIDENCE: INTEL OVERALL STRATEGY IN HPC, CLOUD, EDGEIntel own accelerator developments:

CPU - Accelerator interface:- GPU (Artic Sound)- CSA

Accelerator companies acquired by Intel orwith intel in their Capital, in the last years:- Altera- Habana- Mobileye- Untether AI* (Toronto, Ontario, Canada)- SambaNova Systems* (Palo Alto,California, U.S.)- Zhuhai EEasy Technology Co. Ltd.*(Zhuhai, China)- …

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18- CXL

X86User environment:- Intel Compiler- OneAPI

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LESSONS LEARNEDPROFILE FOR EXASCALE SOLUTIONS
Main changes- Holistic view of data from IoT to Supercomputers.
- Hybrid in-house / cloud- Workflow everywhere

The CPU has to be well balanced- peak performance is not important- Agility (FP64 for HPC, BF16 for deep learning) is crucial- Data transfer is crucial
è Cover day to day needs and for all compute not fitting well in ACC

Modularity is a must have. One does not fit all

Several accelerators, typically one per module

Performance comes from accelerators

Keep overall architecture simple
è one CPU to unify all accelerators

Keep end user life simple- 1 CPU only
- LLVM + GCC + OPENMP 5.0- Keep it open!

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TECHNOLOGY & ROADMAP

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COMMON PLATFORM VISION: FEDERATE ACCELERATORSInterposer function

Value proposition+60 potential ACC. (non exhaustive)

SIPEARL RHEA chip
Embedded memory (likeHBM)
HBMChiplet

Low cost chip from AI
start-ups
HBM
ChipletAIChiplet

AI Start-up
accelerator
Interposer for integration

CryptoAccelerator

Quantum or
photonics
accelerator

THE COMMON OPEN PLATFORM IS
THE EUROPEAN STANDARD FOR MANAGING EXTREME SPECIALIZATIONCopyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

CONCEPT OF COMMON PLATFORM : INTERPOSER & MULTI-CHIPLET

HBM

HBM

HBM

HBM

Chiplet #2
Chiplet #1

Silicon interposer (passive)

Package substrate

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CONCEPT OF COMMON PLATFORM : INTERPOSER & MULTI-CHIPLETCPUAccelerator(s)

HBM

HBM
HBM

Chiplet #1

Chiplet #2

HBM

Silicon interposer (passive)

Package substrate

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HETEROGENEOUS INTEGRATION
I/O coherent
Accelerators¡ Integrating customized

functions at different levels

Traditional GP-GPU, interconnect
and to the storage

PCIe/CXL
links
PCIe links¡ EPI accelerator IPs today are

Package substrate

DDR
memories

HBM
memorires

integrated in Rhea designinter-chiplet links
over substrate

EST CommonPlatform Design

Coherentchiplet

CCIX links via PCB

Coherent
accelerator
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Possible location
for User functions
Commerical FPGA chips
or CCIX enabled companions chips(accelerator, NIC or other EST chips)
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GENERAL PURPOSE PROCESSOR (GPP) AND COMMON OPEN ARCHITECTURE

PCIe gen5
links

externallinks

CCIX (RHEA)
CCIX & CXL (CRONOS)

Kalray

ZEUS
(ARM)

links
to adjacent chiplets
ZEUS
ZEUS
ZEUS
MPPA
ASICEPICommonPlatform
open vision
is to integrate most of EPI IP’s
ZEUS
ZEUS
EPAC
ASIC
ZEUS
eFPGA
development

Dedicated
cryptographic
IP

FPGA

HBM 2ememories

Menta(FR)¡DDR5memories

NoCARM¡¡¡¡¡¡

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

Network on Chip (NoC) – ARM
CPU – ARM – ZEUS
EPAC – EPI Accelerator (TITAN)
MPPA – Multi-Purpose Processing ArrayeFPGA – embedded FPGA
Cryptographic ASIC (EU Sovereignty)
Any other ASIC
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CPU (RHEA) DESIGNS¡ Multi-core Armv8.x processor for both computing and control flow
¡ Very high Byte/FLOP ratio¡ EPI Accelerators work in I/O coherent mode and share the same memory view
¡ Coherent NoC with system level cache to keep the data local¡ HBM2e, DDR5 and PCIe gen5
¡ High-speed links for SMP and for functional extensions¡ Low voltage to improve the energy efficiency / N6 process
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EPAC – RISC-V ACCELERATOR FOUNDATIONS

VPU

EPAC

Bridge to GPPSTXVRP
Bridge to GPP¡ EPAC – TITAN = EPI Accelerator¡ VPU – Vector Processing Unit¡ STX – Stencil/Tensor accelerator¡ VRP = Variable Real Precision

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ROADMAP

ZEUS Core
TITAN Acc.
5nm

Tape-out
ZEUS Core
N6

Test Platform

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

2022 – H2
EU Exascale Supercomputer
Edge-HPC (autonomous vehicle)
with CRONOS & TITAN
2021 – H2
E4 - PCIe board (WS compatible)
ATOS - BullxSequana Board
with RHEA β version 22

ARM WW HPCCPUmanufacturer,
2 servermanufacturers,“Astra” system atSandia,
upcoming system
at Stony Brook

Upcoming CPU
manufacturer,
Server manufacturer,
system at CEA, UK,
MontBlanc, EPI
CPU & server
manufacturer,
upcoming“Fugaku”
systemCPU & server
manufacturer[geopoliticalissues regarding
the license]

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CONCLUSION

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EUROPEAN APPROACH FOR (POST) EXASCALE CHALLENGES

TechnologyOpen¡ One CPU to rule all accelerators¡ ARM is the best choice: performances,openness, unique IoT to Supercomputer
ecosystem¡ Chiplet based approach

Ecosystem (holistic)¡ ARM from IoT to HPC¡ Common Open platform¡ GCC and LLVM

¡ Open programming model¡ OPENMP 5¡ Aim open hardware¡ OPENCL¡ Common Open Platform

Copyright © European Processor Initiative 2020. 2nd R-CCS Int'l workshop/Kobe/2020-02-18

¡ …

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Book the datest
1 EPI ForumthMarch, 16-17 , 2020

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THANK YOU FOR YOUR ATTENTION

w www.european-processor-initiative.eu@EuProcessor
European Processor Initiative
European Processor Initiative

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