PUMD9-Q

50 V, 100 mA NPN/PNP resistor-equipped double transistor;
R1 = 10 kΩ, R2 = 47 kΩ
7 October 2021

Product data sheet

1. General description
NPN/PNP Resistor-Equipped double Transistor (RET) in a very small SOT363 (SC-88) SurfaceMounted Device (SMD) plastic package.
NPN/NPN complement: PUMH9-Q
PNP/PNP complement: PUMB9-Q

2. Features and benefits
•
•
•
•
•
•

100 mA output current capability
Built-in bias resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
Qualified according to AEC-Q101 and recommended for use in automotive applications

3. Applications••••

Digital application in automotive and industrial segments
Cost-saving alternative for BC847-Q/BC857-Q series in digital applications
Controlling IC inputs
Switching loads

4. Quick reference data
Table 1. Quick reference data
SymbolParameter

Conditions

Min

Typ

Max

Unit

-

-

50

V

-

-

100

mA
kΩ

Per transistor, for the PNP transistor with negative polarity
VCEO

collector-emitter
voltage

IO

output current

R1

bias resistor 1

[1]

7

10

13

R2/R1

bias resistor ratio

[1]

3.7

4.7

5.7

[1]

open baseSee "Section 11: Test information" for resistor calculation and test conditions.

PUMD9-Q

Nexperia

50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

5. Pinning information
Table 2. Pinning information
Pin
SymbolDescription

Simplified outline

1

GND1

GND (emitter) TR1

2

I1

input (base) TR1

3

O2

output (collector) TR2

4

GND2

GND (emitter) TR2

5

I2

input (base) TR2

6

O1

output (collector) TR1

Graphic symbol
O1

6

5

4

I2

R1

GND2

R2
TR2

TR1

1

2

R2

3

R1

TSSOP6 (SOT363)
GND1

I1

O2

006aaa143

6. Ordering information
Table 3. Ordering information
Type number
Package
PUMD9-Q

Name

Description

TSSOP6plastic, surface-mounted package; 6 leads; 0.65 mm pitch; SOT363
2.1 mm x 1.25 mm x 0.95 mm bodyVersion

7. Marking
Table 4. Marking codes
Type number

Marking code[1]PUMD9-Q

D%9[1]% = placeholder for manufacturing site code

PUMD9-Q

Product data sheet

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
SymbolParameter

Conditions

Min

Max

Unit

Per transistor, for the PNP transistor with negative polarity
VCBO

collector-base voltage

open emitter

-

50

V

VCEO

collector-emitter voltage

open base

-

50

V

VEBO

emitter-base voltage

open collector

-

6

V

VI

input voltage

input voltage TR1

-

40

V

-

-6

V

-

6

V

-

-40

V

-

100

mA

input voltage TR2
IO

output current

Ptot

total power dissipation

Tamb ≤ 25 °C

[1]

-

200

mW

Ptot

total power dissipation

Tamb ≤ 25 °C

[1]

-

300

mW

Tj

junction temperature

-

150

°C

Tamb

ambient temperature

-65

150

°C

Tstg

storage temperature

-65

150

°C

Per device[1]

Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided, 35 μm copper, tin-plated and standard footprint.
006aac749

400
Ptot
(mW)
300

200

100

0
-75

-25

25

75

125
175
Tamb (°C)

FR4 PCB, single-sided, 35 μm copper, tin-plated and standard footprint
Fig. 1.

Per device: Power derating curve

PUMD9-Q

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

9. Thermal characteristics
Table 6. Thermal characteristics
SymbolParameter

Conditions

Min

Typ

Max

Unit

Per transistor
Rth(j-a)thermal resistance from in free air
junction to ambient

[1]

-

-

625

K/W

thermal resistance from in free air
junction to ambient

[1]

-

-

417

K/W

Per device
Rth(j-a)[1]

Device mounted on an FR4 PCB, single-sided, 35 μm copper, tin-plated and standard footprint.
103
Zth(j-a)(K/W)

006aac750

duty cycle = 1
0.75
0.33

0.5
0.2

102
0.1

0.05

10

0.02

0.01

0

1
10-5

10-4

10-3

10-2

10-1

1

10

102

tp (s)

103

FR4 PCB, single-sided, 35 µm copper, tin-plated and standard footprint
Fig. 2.

Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values

PUMD9-Q

Product data sheet

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

10. Characteristics
Table 7. Characteristics
SymbolParameter

Conditions

Min

Typ

Max

Unit

Per transistor, for the PNP transistor with negative polarity
V(BR)CBO

collector-basebreakdown voltage

IC = 100 µA; IE = 0 A; Tamb = 25 °C

50

-

-

V

V(BR)CEOcollector-emitter
breakdown voltage

IC = 2 mA; IB = 0 A; Tamb = 25 °C

50

-

-

V

ICBO

collector-base cut-off
current

VCB = 50 V; IE = 0 A; Tamb = 25 °C

-

-

100

nA

ICEO

collector-emitter cut-off VCE = 30 V; IB = 0 A; Tamb = 25 °C
current
VCE = 30 V; IB = 0 A; Tj = 150 °C

-

-

100

nA

-

-

5

µA

IEBO

emitter-base cut-off
current

VEB = 5 V; IC = 0 mA; Tamb = 25 °C

-

-

150

µA

hFE

DC current gain

VCE = 5 V; IC = 5 mA; Tamb = 25 °C

100

-

-

VCEsatcollector-emittersaturation voltage

IC = 5 mA; IB = 0.25 mA; Tamb = 25 °C

-

-

100

mV

VI(off)off-state input voltage

VCE = 5 V; IC = 100 µA; Tamb = 25 °C

-

0.7

0.5

V

VI(on)

on-state input voltage

VCE = 0.3 V; IC = 1 mA; Tamb = 25 °C

1.4

0.8

-

V

R1

bias resistor 1

[1]

7

10

13

kΩ

R2/R1

bias resistor ratio

[1]

3.7

4.7

5.7

-

-

2.5

pF

-

230

-

MHz

-

-

3

pF

-

180

-

MHz

TR1 (NPN)
Cc

collector capacitance

VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz;
Tamb = 25 °C

fTtransition frequency

VCE = 5 V; IC = 10 mA; f = 100 MHz;
Tamb = 25 °C

Cccollector capacitance

VCB = -10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C

fTtransition frequency

VCE = -5 V; IC = -10 mA; f = 100 MHz;
Tamb = 25 °C[2]

TR2 (PNP)

[1]
[2]

[2]

See "Section 11: Test information" for resistor calculation and test conditions.
Characteristics of built-in transistor

PUMD9-Q

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ
006aac784

1030.50 mA

IC
(A)

(1)

hFE

aaa-018582

0.1

(2)

0.45 mA
0.40 mA

0.08(3)0.35 mA
0.30 mA

102

0.25 mA

0.06

0.20 mA
0.04

0.15 mA

10

0.10 mA

0.02

IB = 0.05 mA
1
10-1

1

10

IC (mA)

0102

VCE = 5 V
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C
Fig. 3.

0

1

2

3

4

VCE (V)

5

Tamb = 25 °C
Fig. 4.

TR1 (NPN): Collector current as a function ofcollector-emitter voltage; typical values

TR1 (NPN): DC current gain as a function ofcollector current; typical values
aaa-018586

1006aac786

10

VCEsat(V)

VI(on)
(V)

10-1

1

(1)
(2)
(3)

(1)
(2)
(3)

10-2
10-1

Fig. 5.

1

10

IC (mA)

102

10-1
10-1

1

10

IC (mA)

102

IC/IB = 20
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C

VCE = 0.3 V(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C

TR1 (NPN): Collector-emitter saturation voltage Fig. 6.
as a function of collector current; typical values

TR1 (NPN): On-state input voltage as a functionof collector current; typical values

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ
006aac787

10006aac788

3
Cc
(pF)

VI(off)
(V)

2
(1)

1
(2)
(3)

10-1
10-1

1

1

IC (mA)

0

10

VCE = 5 V
(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C
Fig. 7.

0

10

20

30

40
50
VCB (V)f = 1 MHz
Tamb = 25 °C
Fig. 8.

TR1 (NPN): Collector capacitance as a functionof collector-base voltage; typical values

TR1 (NPN): Off-state input voltage as a functionof collector current; typical values
006aac757

103

006aac789

103
hFE

(1)
(2)

fT
(MHz)

(3)

102

102
10

10
10-1

1

10

IC (mA)

1
-10-1

102

f = 100 MHz
Tamb = 25 °C
VCE = 5 V
Fig. 9.

TR1 (NPN): Transition frequency as a functionof collector current; typical values of built-in
transistor

PUMD9-Q

Product data sheet

-1

-10

IC (mA)-102

VCE = -5 V
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C
Fig. 10. TR2 (PNP): DC current gain as a function ofcollector current; typical values

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ
aaa-018918-0.1-0.80 mAIC
(A)

aaa-018915-1-0.72 mA
-0.64 mA

-0.08

VCEsat(V)-0.56 mA
-0.48 mA
-0.40 mA

-0.06

-0.32 mA

-10-1

-0.24 mA

-0.04

(1)
(2)

-0.16 mA

(3)

-0.02
IB = -0.08 mA
0

0

-1

-2

-3

-4

VCE (V)

-10-2
-10-1

-5

Tamb = 25 °C

-1

-10

IC (mA)-102

IC/IB = 20
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C

Fig. 11. TR2 (PNP): Collector current as a function ofcollector-emitter voltage; typical values

Fig. 12. TR2 (PNP): Collector-emitter saturation voltage
as a function of collector current; typical values
006aac791-10

VI(on)(V)

006aac792-10

VI(off)
(V)
(1)

-1

(1)

-1

(2)

(2)

(3)

-10-1
-10-1

-1

(3)

-10

IC (mA)

-102

-10-1
-10-1

VCE = -0.3 V(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C-1

IC (mA)-10

VCE = -5 V
(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C

Fig. 13. TR2 (PNP): On-state input voltage as a function Fig. 14. TR2 (PNP): Off-state input voltage as a functionof collector current; typical valuesof collector current; typical values

PUMD9-Q

Product data sheet

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ
Cc(pF)

006aac793

7006aac763

103

6
fT
(MHz)

5
4

102
3
2
1
0

0

-10

-20

-30

10
-10-1

-40
-50
VCB (V)f = 1 MHz
Tamb = 25 °C
Fig. 15. TR2 (PNP): Collector capacitance as a functionof collector-base voltage; typical values

PUMD9-Q

Product data sheet

-1

-10

IC (mA)-102

f = 100 MHz
Tamb = 25 °C
VCE = -5 V
Fig. 16. TR2 (PNP): Transition frequency as a functionof collector current; typical values of built-in
transistor

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

11. Test information
Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC)
standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use inautomotive applications.

Resistor calculation•

Calculation of bias resistor 1 (R1)•

Calculation of bias resistor ratio (R2/R1)n.c.

II1; II2

R1

II3; II4
R2

GND
aaa-020082

Fig. 17. TR1 (NPN): Resistor test circuitn.c.

II1; II2

R1

II3; II4
R2

GND
aaa-020083

Fig. 18. TR2 (PNP): Resistor test circuit

Resistor test conditions
Table 8. Resistor test conditions
Type number

R1 (kΩ)R2 (kΩ)

Test conditions
II1

II2

II3

II4

90 μA

140 μA-55 μA-105 μA

Per transistor, for the PNP with negative polarity
PUMD9-Q

PUMD9-Q

Product data sheet

1047

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

12. Package outline
2.2
1.8
6

2.2 1.35
2.0 1.15

1.1
0.8
5

4

2

3

0.45
0.15

pin 1
index

1
0.65
1.3

0.3
0.2

0.25
0.10

Dimensions in mm

14-10-03

Fig. 19. Package outline TSSOP6 (SOT363)

PUMD9-Q

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

13. Soldering
2.65

solder lands
2.35 1.5

0.4 (2×)

0.6 0.5(4×) (4×)

solder resist
solder paste

0.5
(4×)

0.6
(2×)

occupied area

0.6
(4×)

Dimensions in mm
1.8

sot363_fr

Fig. 20. Reflow soldering footprint for TSSOP6 (SOT363)

1.5
solder lands
0.3 2.5

4.5

1.5

solder resist
occupied area
Dimensions in mm

1.3

preferred transport
direction during soldering

1.3
2.45
5.3

sot363_fw

Fig. 21. Wave soldering footprint for TSSOP6 (SOT363)

PUMD9-Q

Product data sheet

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

14. Revision history
Table 9. Revision history
Data sheet ID
Release date

Data sheet status

Change notice

Supersedes

PUMD9-Q v.2

20211007

Product data sheet-

PUMD9-Q v.1

Modification:

•
•
•
•
•
•
•
•
•
•
•

PUMD9-Q v.1

20210625

PUMD9-Q

Product data sheet

Complete rework
General description: added new lines at the end
Pinning: Graphic symbol replaced
Limiting values: deleted parameter ICM
Characteristics: ICEO max limit is updated to 100 nA
Characteristics: added new graphics
Characteristics: replaced the figure 006aac785 with aaa-aaa-018586
Characteristics: replaced the figure 006aac790 with aaa-018915
Characteristics: Updated the graphics conditions
Characteristics: V(BR)EBO values is removed
Test information: Included resistor calculation, resistor test circuit and resistor test condition
Product data sheet-

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death orsevere property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment orapplications and therefore such inclusion and/or use is at the customer's own
risk.

15. Legal information
Data sheet status
Document status[1][2]

Product
status [3]Definition

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.

Objective [short]data sheet

Development

This document contains data fromthe objective specification for
product development.

Preliminary [short]data sheet

Qualification

This document contains data fromthe preliminary specification.

Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.

Product [short]data sheet

Production

This document contains the productspecification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating orcompleting a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.

Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet isintended for quick reference only and should not be relied upon to containdetailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
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agreed otherwise in writing. In no event however, shall an agreement bevalid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
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In no event shall Nexperia be liable for any indirect, incidental, punitive,
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Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
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Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
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liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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sold subject to the general terms and conditions of commercial sale, as
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for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
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publication hereof.
Suitability for use in automotive applications — This Nexperia producthas been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted tobe suitable for use in life support, life-critical or safety-critical systems or

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50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 10 kΩ, R2 = 47 kΩ

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking.......................................................................... 2
8. Limiting values............................................................. 3
9. Thermal characteristics............................................... 4
10. Characteristics............................................................ 5
11. Test information........................................................ 10
12. Package outline........................................................ 11
13. Soldering................................................................... 12
14. Revision history........................................................13
15. Legal information......................................................14© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 7 October 2021

PUMD9-Q

Product data sheet

All information provided in this document is subject to legal disclaimers.

7 October 2021

© Nexperia B.V. 2021. All rights reserved

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