Freescale Semiconductor

Document Number: AN4815
Rev. 0, 02/2015

Application Notei.MX 6SoloX Migration Guide
Migrating from i.MX 6Solo to i.MX 6SoloX

1 Introduction
1.1 Purpose
This Application Note provides an introduction
to the i.MX 6SoloX architecture by highlighting
the differences with the i.MX 6 Series processor
upon which it is based, namely the i.MX 6Solo.
This document is intended to be a migration
guide for development teams that are porting
platforms from i.MX 6Solo to i.MX 6SoloX.

© Freescale Semiconductor, Inc., 2015. All rights reserved.

Contents1Introduction .............................................. 1
1.1

Purpose .............................................. 1

1.2

Scope ................................................. 2

1.3

Audience ............................................ 2

2Feature Change Summary ......................... 3

3

Revision History ....................................... 8

1.2 Scope
The i.MX 6SoloX was developed with extensive reuse of existing Freescale designs including:•••

Extensive reuse and alignment with i.MX 6Solo
Modules reused/modified from i.MX 6SoloLite
Modules reused/modified from Vybrid

Due to the close alignment with the i.MX 6Solo design, this white paper will be structured as a changesummary from the i.MX 6Solo features. In addition, references to modules that have been reused or
modified from i.MX 6SoloLite and Vybrid will be provided.
The i.MX 6SoloX architecture introduces new features that provide differentiation from other membersof the i.MX 6 Series. Some key differentiators include:•••

i.MX 6SoloX is the first i.MX 6 Series processor to provide asymmetric multiprocessing(AMP) by integrating Cortex-A9 and Cortex-M4 CPUs. Features that allow multiple
execution environments to communicate and safely share resources are supported inhardware.
Integrated Ethernet support has been upgraded to provide dual 1 Gigabit ports with AVB
support.
Analog integration has been enhanced by including general-purpose and video ADCinterfaces.

This white paper will highlight new features added to the i.MX 6SoloX design that require additional
consideration when porting designs based on i.MX 6Solo.

1.3 Audience
The content of this document is targeted towards system integrators and software developers migratingfrom platforms based on i.MX 6Solo.

i.MX 6SoloX Migration Guide Application Note, Rev. 0, 02/2015
2Freescale Semiconductor

2 Feature Change Summary
This section will summarize the architectural changes for i.MX 6SoloX with respect to i.MX 6Solo.

CategoryFeature

Change from i.MX 6Solo

CommentCortex-A9

L2 reduced from 512KB to 256KB.

i.MX 6Solo/6DualLite includes 512KB
to support SMP configurations withdual Cortex-A9 CPUs (i.MX 6DualLite).

L2 memory array (256 KB) can be
configured as OCRAM to extend theavailable on-chip memory.

This feature is supported on i.MX
6SoloLite.

Add Cortex-M4 platform:

Secondary processor for fast-boot,low-power processing, and robust CAN
message handling.

L2 Cache Size
Cortex-A9
L2 Cache as OCRAM
Cortex-M4Platform•

16KB I-Cache•

16KB D-Cache•

64KB TCM (tightly coupledmemory) divided into 32KB
lower (TCML) and 32KB
upper (TCMU) regions

CPUInterprocessor
Communication &Synchronization

SEMA4

1 instance of the SEMA4 module
added to support hardware-enforced
semaphores.

MU

1 instance of the MU (messagingunit) module added to support
interprocessor communication
between the Cortex-A9 and CortexM4

The Cortex-M4 platform from Vybrid isreused with the following changes:•

Add core MPU for additional
control of memory attributes•

Updated memory map to reflectalignment with i.MX6 family.

•

No interrupt routing. All IRQs are
mapped to Cortex-M4 and CortexA9 CPUs.

•

MU (messaging unit) provides
interprocessor interrupts.

•

Direct boot from Cortex-M4 is notsupported.

•

Boot vector will be in TCML andpopulated by Cortex-A9.

•

Exclusive access support(synchronization primitives
supported using LDREX andSTREX instructions)

SEMA4 module is reused from Vybrid.

i.MX 6SoloX Migration Guide Application Note, Rev. 0, 02/2015
Freescale Semiconductor

3

CategoryFeatureChange from i.MX 6Solo

RDC

Add RDC module (resource domaincontroller) to support domain-based
access control to shared resources.

SEMA42

Add 2 instances of SEMA42 module
to support safe access to shared
peripherals.

SEMA42 is similar to SEMA4 with thefollowing key differences:•SEMA42 increases the number ofaccess domains from 2 to 15•

SEMA42 does not have interrupt
to indicate semaphore release

RDC programming model supports theoption to require hardware semaphore
for peripherals shared between
domains. Signaling between theSEMA42 and RDC binds peripherals tosemaphore gates within SEMA42.

Multicore
Isolation/SharingTimers

Comment

AIPSTZ, SPBA

Updated to support domain-based
peripheral access control.

RDC programming model is used toconfigure peripheral access rights foreach domain.

DSEC, DEXSC

Updated to support domain-based
access control of memory regions.

RDC programming model is used toconfigure memory regions and accessrights for each domain.

WDOG

Increase WDOG instances from 2 to3.

Additional WDOG for Cortex-M4
usage.

OCRAM_S

Add 16KB on-chip memory in thealways-on power domain.

OCRAM_S can be used by software
for state retention of the CPU andother hardware blocks.

Secure RAM

Increase Secure RAM size from16KB to 32KB.

QSPI

2 instances of Quad SPI added.

RAW NAND

Upgrade BCH40 to BCH62 tosupport 62-bit ECC andrandomization.

Internal Memory

Each QSPI instance supports dualchannel and DDR capability. QSPI
module is reused from Vybrid.

External Memory

HABSecurity

HAB updates to improve secure boottimes

HAB will support a new fastauthentication option that reduces therequired signatures from 4 to 2 withoutcompromising the level of security.

i.MX 6SoloX Migration Guide Application Note, Rev. 0, 02/2015
4Freescale Semiconductor

CategoryFeature

Change from i.MX 6Solo

VPU

VPU removed.

Video encode/decode requires CortexA9 software.

VDOA

VDOA removed.

Not needed since VPU removed.

VADC

Video ADC added to support
NTSC/PAL analog video input.

Provides cost-effective support ofanalog rearview cameras. VADC
module is reused from Vybrid.

VDEC

Add composite video decoder toprovide NTSC/PAL decoding.

Decodes NTSC/PAL signals fromanalog camera into YUV. VDEC
module is reused from Vybrid.

HDMI

HDMI transmitter removed.

MIPI/CSI-2

MIPI/CSI-2 receiver removed.

MIPI/DSIMIPI/DSI transmitter removed.

VideoCamera, Display, &Graphics

CommentIPU

IPU removed.

IPU functionality replaced with CSI +PXP + LCDIF

CSI

2 parallel CSI ports added.

CSI module from i.MX 6SoloLite will bereused with the following modifications:•Support 24-bit YUV input•Support simple video deinterlacing•Support field input signal

PXP

PXP can be used to support CSC,compositing, rotation, and resize
operations previously supported byIPU.

PXP module from i.MX 6Solo will bereused.

GISGIS (General Interrupt Service)
module added.

GIS can be used to automate the flowof data from the camera to the display.

LCDIF

2 instances of LCDIF added.

LCDIF module from i.MX 6SoloLite will
be reused with the following
modifications:

LVDS

Reduced from 2 channels to 1.

GPU

GC880 and GC320 removed.
GC400T added.

EPDC

EPDC (Electrophoretic DisplayController) removed.

•Blending of overlay buffer withsame height and width as displaybuffer•Local/global alpha blending ofoverlay buffer

GC400T provides integrated 2D and3D support.

i.MX 6SoloX Migration Guide Application Note, Rev. 0, 02/2015
Freescale Semiconductor

5CategoryFeature

Change from i.MX 6Solo

CommentSAI

Add 2 SAI instances to increase thenumber of I2S audio interfaces from2 to 5 (3 SSI + 2 SAI).

Unlike the SSI, the SAI interfaces do
not flow through AUDMUX. The SAI
modules support increased FIFO depth(64x32-bit) over the SSI. The SAI
module is reused from Vybrid.

Audio

Note: The ESAI from i.MX 6Solo isalso available on i.MX 6SoloX.
ENET

MIPI_HSI

Increased ENET instances from 1 to
2. Both ENET instances support
AVB.

ENET module from i.MX 6Solo
updated with the following
modifications:•Dual 64-bit AXI bus interface•

Improved bus fabric priority control•

8K RX & TX FIFO size•

Unaligned buffer support•

Interrupt coalescing•

AVB support

MIPI_HSI removed.

Connectivity
MLBAnalog

MLB support for MOST150 removed.
DTCP cipher accelerator removed.

MLB module from i.MX 6Solo reusedwith the following modifications:•

Only MOST25, MOST50
supported.

•DTCP removed.

UART

Increase UART instances from 5 to
6.

PWM

Increase PWM instances from 4 to 8.

SPI

Increase SPI instances from 4 to 5.

ADC

2 instances of 12-bit ADC added.

ADC module from Vybrid is reused.

Temperature Sensor

Temperature sensor will be modified
to have three programmable trip
points (low, high, panic). The panic
trip point will be capable ofgenerating a system reset.

The changes to the sensor
functionality allow an interrupt to begenerated when temperatures falloutside of the programmed window.
The panic reset provides a hardware
failsafe when temperatures reach
dangerous levels.

i.MX 6SoloX Migration Guide Application Note, Rev. 0, 02/2015
6Freescale Semiconductor

CategoryFeature

Change from i.MX 6SoloComment

LDO_PULDO_PU removed. VDDPU_CAP
pins removed.

GPU will be powered from VDDSOC.
IPU and VPU modules powered by
LDO_PU on i.MX 6Solo are removed.

LDO_PCIE

LDO_PCIE added. LDO_PCIE
supply is VDD_SOC_IN andconnects to PCIE_VP/VPTX pads.

LDO_PCIE provides power for thePCIe PHY digital logic.

L2 Power Gating

Support L2 cache power gating.

L2 cache will support the following
power gating options:PowerSNVSDBGMON•L2 cache memory remains
powered and retains state during
Cortex-A9 power gating.

•L2 cache memory will be powered
down and lose state during
Cortex-A9 power gating.

ONOFF pin behavior updated toalign with Android requirements.
DBGMON added.

DBGMON is a real-time debug monitor
to record last AXI transaction before
system reset. DBGMON module fromi.MX 6SoloLite will be reused.

Debug Signals

Peripheral debug signals routed
based on RDC configuration.

RDC configuration will be used todetermine how a peripheral responds
when the Cortex-M4 and Cortex-A9
enter debug modes.

Memory Map

Cortex-A9 memory map updated toreflect IP changes.

Refer to Memory Map chapter in the
Reference Manual for full details.

IRQ Map

IRQ map updated to reflect IPchanges.

Refer to IRQ map chapter in the
Reference Manual for full details.

DMA Map

DMA map updated to reflect IPchanges.

Refer to DMA map chapter in the
Reference Manual for full details.

Fuse Map

Fuse map updated to reflect IPchanges.

Refer to Fuse map chapter in the
Reference Manual for full details.

CSU

CSU programming model updated toreflect IP changes.

Refer to Security Reference manual for
full details.

CCM

Clock tree updated to reflect IPchanges and optimize for low power.

CCM module from i.MX 6Solo reusedwith modifications including:

DebugSystem Integration•Dedicated clock roots for IP blocks
that have been removed will beremoved or connected to new IPblocks.

•24 MHz RC OSC option isavailable for use in low-power
modes with XTAL powered off.

•Audio/Video PLL will support onthe-fly changes to provide atunable media clock.

i.MX 6SoloX Migration Guide Application Note, Rev. 0, 02/2015
Freescale Semiconductor

73 Revision History
The following table provides a revision history for this white paper.
Document Revision History
Rev. NumberDateRevision

Rev. 002/2015

Initial release.

i.MX 6SoloX Migration Guide Application Note, Rev. 0, 02/2015
8Freescale Semiconductor

How to Reach Us:

Information in this document is provided solely to enable system and software

Home Page:
freescale.com

implementers to use Freescale products. There are no express or implied copyrightWeb Support:
freescale.com/support

information in this document.

licenses granted hereunder to design or fabricate any integrated circuits based on theFreescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding thesuitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/orspecifications can and do vary in different applications, and actual performance mayvary over time. All operating parameters, including “typicals,” must be validated foreach customer application by customer’s technical experts. Freescale does not convey
any license under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found at the following
address:

freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of theirrespective owners. ARM and Cortex are the registered trademarks of ARM Limited.

© 2015 Freescale Semiconductor, Inc.

Document Number: AN4815
Rev. 002/2015