PCAL6416A

2

Low-voltage translating 16-bit I C-bus/SMBus I/O expanderwith interrupt output, reset, and configuration registers
Rev. 7.1 — 30 August 2022

1

Product data sheet

General description
The PCAL6416A is a 16-bit general-purpose I/O expander that provides remote I/O
2
expansion for most microcontroller families via the I C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one
voltage level to I/O devices operating at a different (usually higher) voltage level. The
PCAL6416A has built-in level shifting feature that makes these devices extremely flexible
in mixed signal environments where communication between incompatible I/O voltages
is required. Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless
communications with next-generation low voltage microprocessors and microcontrollers
on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCAL6416A: VDD(I2C-bus) and VDD(P). VDD(I2Cbus) provides the supply voltage for the interface at the master side (for example, amicrocontroller) and the VDD(P) provides the supply for core circuits and Port P. The
bidirectional voltage level translation in the PCAL6416A is provided through VDD(I2C-bus).
VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates2
the VDD level of the I C-bus to the PCAL6416A, while the voltage level on Port P of the
PCAL6416A is determined by the VDD(P).
The PCAL6416A contains the PCA6416A register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers and additionally, the PCAL6416A
has Agile I/O, which are additional features specifically designed to enhance the I/
O. These additional features are: programmable output drive strength, latchable
inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status
register, programmable open-drain or push-pull outputs. The PCAL6416A is a pinto-pin replacement to the PCA6416A, however, the PCAL6416A powers up with all I/
O interrupts masked. This mask default allows for a board bring-up free of spurious
interrupts at power-up.
At power-on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data foreach input or output is kept in the corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity Inversion register, saving external
logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete
components.
The system master can reset the PCAL6416A in the event of a time-out or otherimproper operation by asserting a LOW in the RESET input. The power-on reset puts2
the registers in their default state and initializes the I C-bus/SMBus state machine. The
RESET pin causes the same reset/initialization to occur without depowering the part.

NXP Semiconductors
2

PCAL6416A

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
The PCAL6416A open-drain interrupt (INT) output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to thesystem master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data2
on its ports without having to communicate via the I C-bus. Thus, the PCAL6416A canremain a simple slave device. The input latch feature holds or latches the input pin state
and keeps the logic values that created the interrupt until the master can service theinterrupt. This minimizes the host’s interrupt service response for fast moving inputs.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while
consuming low device current.
2

One hardware pin (ADDR) can be used to program and vary the fixed I C-bus address2
and allow up to two devices to share the same I C-bus or SMBus.

2

Features and benefits
2• I C-bus to parallel port expander• Operating power supply voltage range of 1.65 V to 5.5 V• Allows bidirectional voltage-level translation and GPIO expansion between:– 1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P– 2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P– 3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P– 5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P• Low standby current consumption:– 1.5 μA typical at 5 V VDD– 1.0 μA typical at 3.3 V VDD• Schmitt trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs– Vhys = 0.18 V (typical) at 1.8 V– Vhys = 0.25 V (typical) at 2.5 V– Vhys = 0.33 V (typical) at 3.3 V– Vhys = 0.5 V (typical) at 5 V• 5 V tolerant I/O ports• Active LOW reset input (RESET)• Open-drain active LOW interrupt output (INT)
2• 400 kHz Fast-mode I C-bus• Internal power-on reset• Power-up with all channels configured as inputs• No glitch on power-up• Noise filter on SCL/SDA inputs• Latched outputs with 25 mA drive maximum capability for directly driving LEDs
• Latch-up performance exceeds 100 mA per JESD 78, Class II• ESD protection exceeds JESD 22– 2000 V Human-Body Model (A114-A)– 1000 V Charged-Device Model (C101)• Packages offered: TSSOP24, HWQFN24, VFBGA24, X2QFN24 (LGA, Land Grid
Array)
PCAL6416A

Product data sheet

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Rev. 7.1 — 30 August 2022

© 2022 NXP B.V. All rights reserved.

2 / 56

PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

2.1 Agile I/O features• Software backward compatible with PCA6416A with interrupts disabled at power-up• Pin-to-pin drop-in replacement with PCA6416A• Output port configuration: bank selectable push-pull or open-drain output stages• Interrupt status: read-only register identifies the source of an interrupt• Bit-wise I/O programming features:– Output drive strength: four programmable drive strengths to reduce rise and fall times
in low-capacitance applications– Input latch: Input Port register values changes are kept until the Input Port register isread– Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable– Pull-up/pull-down selection: 100 kΩ pull-up/pull-down resistor selection– Interrupt mask: mask prevents the generation of the interrupt when input changes
state to prevent spurious interrupts

3

Ordering information

Table 1. Ordering information
Type number

Topsidemark

Package
Name

Description

Version

PCAL6416AEV

L16A

VFBGA24plastic very thin fine-pitch ball grid array package; 24 balls;
body 3 × 3 × 0.85 mm

SOT1199-1

PCAL6416AEX1

16X

[1]

X2QFN24plastic, thermal enhanced super thin land grid array or quad SOT1895-1
flat package; no leads; 24 terminals; body 2.0 × 2.0 × 0.35mm

PCAL6416AHF

L16A

HWQFN24plastic thermal enhanced very very thin quad flat package;no leads; 24 terminals; body 4 × 4 × 0.75 mm

SOT994-1

PCAL6416APWPCAL6416A

TSSOP24plastic thin shrink small outline package; 24 leads; bodywidth 4.4 mm

SOT355-1[1]‘X’ rotates from 1 to 5 and indicates the work week of the indicated month

3.1 Ordering options
Table 2. Ordering options
Type number

Orderable partnumberPackage

Packing method

Minimum
order
quantity

Temperature range

PCAL6416AEVPCAL6416AEVJVFBGA24

Reel 13" Q1/T1*Standard mark SMD

6000

Tamb = -40 °C to +85 °C

PCAL6416AEX1PCAL6416AEX1Z

X2QFN24

Reel 7" Q2/T3*Standard mark SMD

5000

Tamb = -40 °C to +85 °C

PCAL6416AHF

PCAL6416AHF,128

HWQFN24

Reel 13" Q2/T3*Standard mark SMD

6000

Tamb = -40 °C to +85 °C

PCAL6416APWPCAL6416APW,118

TSSOP24

Reel 13" Q1/T1*Standard mark SMD

2500

Tamb = -40 °C to +85 °C

PCAL6416A

Product data sheet

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Rev. 7.1 — 30 August 2022

© 2022 NXP B.V. All rights reserved.

3 / 56

PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

4

Block diagram
PCAL6416A

INTERRUPTLOGIC

LP FILTER

INT

ADDR
SCL

I2C-BUSCONTROLINPUTFILTERSDA

VDD(I2C-bus)
VDD(P)

P0_0 to P0_7

I/O
PORT

16 BITS

P1_0 to P1_7

write pulse
read pulse
I/O control

POWER-ON
RESET

RESET

SHIFT
REGISTER

VSS
002aaf962

All I/Os are set to inputs at reset.
Figure 1. Block diagram of PCAL6416A (positive logic)

5

Pinning information
5.1 Pinning

RESET

22 SCLP0_0

4

21 ADDR

P0_1

5

20 P1_7

P0_2

6

P0_3

7

18 P1_5

P0_0

1

18 ADDR

P0_4

8

17 P1_4

P0_1

2

17 P1_7

P0_5

9

16 P1_3

P0_2

3

P0_6 10

15 P1_2

P0_3

4

P0_7 11

14 P1_1

P0_4

5

14 P1_4

VSS 12

13 P1_0

P0_5

6

13 P1_3

Figure 2. Pin configuration for TSSOP24

PCAL6416A

Product data sheet

P1_2 12

P1_1 11

P1_0 10

9VSS

16 P1_6
15 P1_5002aaf964

Transparent top view

Figure 3. Pin configuration for HWQFN24

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Rev. 7.1 — 30 August 2022

8

The exposed center pad, if used, must beconnected only as a secondary ground or mustbe left electrically open.

7002aaf963

PCAL6416AHF

P0_7

19 P1_6

P0_6

PCAL6416APW

terminal 1
index area

19 SCL23 SDA

3

21 VDD(P)20 SDA

24 VDD(P)223 VDD(I2C-bus)
22 INT1

24 RESETINT
VDD(I2C-bus)© 2022 NXP B.V. All rights reserved.

4 / 56

PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
ball A1
index area

PCAL6416AEV
1

2

3

4

5

A
B
C
D
E

002aaf966

Transparent top view

An empty cell indicates no ball is populated atthat grid point.
Figure 4. Pin configuration for VFBGA24 (3mm × 3 mm)

1

2

3

4

5

A

P0_0

RESET

INT

SDA

SCL

B

P0_2

VDD(I2C-bus) VDD(P)

ADDR

C

P0_3

P0_4

P0_1

P1_7

P1_6

D

P0_5

P0_7

P1_2

P1_4

P1_5

E

P0_6

VSS

P1_0

P1_1

P1_3
002aag244

Figure 5. Ball mapping for VFBGA24 (3 mm
× 3 mm) (transparent top view)

PCAL6416AEX1

terminal 1
index area

1

2

3

4

5

A
B

1

2

3

4

5

C

A

RESET VDD(I2C-bus) VDD(P)

SCL

ADDR

D

B

P0_0

INT

SDA

P1_7

C

P0_2

P0_3

P0_1

P1_6

P1_5

D

P0_4

P0_7

P1_0

P1_4

P1_3

E

P0_5

P0_6

VSS

P1_1

P1_2

E
aaa-026741

Transparent top view

An empty cell indicates no ball is populated atthat grid point.
Figure 6. Pin configuration for X2QFN24 (2mm × 2 mm); EX1 land grid array option

002aah145

Figure 7. Ball mapping for X2QFN24 (2 mm ×2 mm) (transparent top view)

5.2 Pin description
Table 3. Pin description
SymbolPin

Description

TSSOP24

HWQFN24VFBGA24

X2QFN24

INT

1

22

A3

B3

Interrupt output. Connect to VDD(I2C-bus) or VDD(P)through a pull-up resistor.

VDD(I2C-bus)

2

23

B3

A2

Supply voltage of I C-bus. Connect directly to the2
VDD of the external I C master. Provides voltage-leveltranslation.

PCAL6416A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7.1 — 30 August 2022

2

© 2022 NXP B.V. All rights reserved.

5 / 56

PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 3. Pin description...continued
SymbolPin

Description

TSSOP24

HWQFN24VFBGA24

X2QFN24

RESET

3

24

A2

A1

Active LOW reset input. Connect to VDD(I2C-bus)
through a pull-up resistor if no active connection is
used.

P0_0

[1]

4

1

A1

B1

Port 0 input/output 0

P0_1

[1]

5

2

C3

C3

Port 0 input/output 1

P0_2

[1]

6

3

B1

C1

Port 0 input/output 2

P0_3

[1]

7

4

C1

C2

Port 0 input/output 3

P0_4

[1]

8

5

C2

D1

Port 0 input/output 4

P0_5

[1]

9

6

D1

E1

Port 0 input/output 5

P0_6

[1]

10

7

E1

E2

Port 0 input/output 6

P0_7

[1]

11

8

D2

D2

Port 0 input/output 7

VSS

12

9

E2

E3

Ground

P1_0

[2]

13

10

E3

D3

Port 1 input/output 0

P1_1

[2]

14

11

E4

E4

Port 1 input/output 1

P1_2

[2]

15

12

D3

E5

Port 1 input/output 2

P1_3

[2]

16

13

E5

D5

Port 1 input/output 3

P1_4

[2]

17

14

D4

D4

Port 1 input/output 4

P1_5

[2]

18

15

D5

C5

Port 1 input/output 5

P1_6

[2]

19

16

C5

C4

Port 1 input/output 6

P1_7

[2]

20

17

C4

B5

Port 1 input/output 7

ADDR

21

18

B5

A5

Address input. Connect directly to VDD(P) or ground.

SCL

22

19

A5

A4

Serial clock bus. Connect to VDD(I2C-bus) through a pullup resistor.

SDA

23

20

A4

B4

Serial data bus. Connect to VDD(I2C-bus) through a pullup resistor.

VDD(P)

24

21

B4

A3

Supply voltage of PCAL6416A for Port P.

[1]
[2]

6

Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-on, all I/O are configured as input.
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-on, all I/O are configured as input.

Voltage translation
Table 4 shows how to set up VDD levels for the necessary voltage translation between the2
I C-bus and the PCAL6416A.
Table 4. Voltage translation

PCAL6416A

Product data sheet

2

VDD(I2C-bus) (SDA and SCL of I C master)

VDD(P) (Port P)

1.8 V

1.8 V

1.8 V

2.5 V

1.8 V

3.3 V
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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 4. Voltage translation...continued
2

7

VDD(I2C-bus) (SDA and SCL of I C master)

VDD(P) (Port P)

1.8 V

5V

2.5 V

1.8 V

2.5 V

2.5 V

2.5 V

3.3 V

2.5 V

5V

3.3 V

1.8 V

3.3 V

2.5 V

3.3 V

3.3 V

3.3 V

5V

5V

1.8 V

5V

2.5 V

5V

3.3 V

5V

5V

Functional description
Refer to Figure 1.

7.1 Device address
The address of the PCAL6416A is shown in Figure 8.
slave address
0

1

0

0

0

0

fixed

AD
R/W
DR
hardware selectable002aah045

Figure 8. PCAL6416A address

ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW(logic 0) to assign one of the two possible slave addresses. The last bit of the slave
address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1)
selects a read operation, while a LOW (logic 0) selects a write operation.

7.2 Interface definition
Table 5. Interface definition
Byte
2

Bit

I C-bus slave address
I/O data bus

PCAL6416A

Product data sheet

7 (MSB)

6

5

4

3

2

1

0 (LSB)

L

H

L

L

L

L

ADDR

R/W

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

7.3 Pointer register and command byte
Following the successful acknowledgment of the address byte, the bus master sends acommand byte, which is stored in the Pointer register in the PCAL6416A. The lower threebits of this data byte state the operation (read or write) and the internal registers (Input,
Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction withthe lower three bits of the Command byte are used to point to the extended features ofthe device (Agile IO). This register is write only.
B7

B6

B5

B4

B3

B2

B1

B0

002aaf540

Figure 9. Pointer register bits

Table 6. Command byte
Pointer register bits

Command byte Register(hexadecimal)

ProtocolPower-up
default

B7

B6

B5

B4

B3

B2

B1

B0

0

0

0

0

0

0

0

0

00h

Input port 0

read byte

xxxx xxxx

0

0

0

0

0

0

0

1

01h

Input port 1

read byte

xxxx xxxx

0

0

0

0

0

0

1

0

02h

Output port 0

read/write byte

1111 1111

0

0

0

0

0

0

1

1

03h

Output port 1

read/write byte

1111 1111

0

0

0

0

0

1

0

0

04h

Polarity Inversion port 0

read/write byte

0000 0000

0

0

0

0

0

1

0

1

05h

Polarity Inversion port 1

read/write byte

0000 0000

0

0

0

0

0

1

1

0

06h

Configuration port 0

read/write byte

1111 1111

0

0

0

0

0

1

1

1

07h

Configuration port 1

read/write byte

1111 1111

0

1

0

0

0

0

0

0

40h

Output drive strength
register 0

read/write byte

1111 1111

0

1

0

0

0

0

0

1

41h

Output drive strength
register 0

read/write byte

1111 1111

0

1

0

0

0

0

1

0

42h

Output drive strength
register 1

read/write byte

1111 1111

0

1

0

0

0

0

1

1

43h

Output drive strength
register 1

read/write byte

1111 1111

0

1

0

0

0

1

0

0

44h

Input latch register 0

read/write byte

0000 0000

0

1

0

0

0

1

0

1

45h

Input latch register 1

read/write byte

0000 0000

0

1

0

0

0

1

1

0

46h

Pull-up/pull-down enableregister 0

read/write byte

0000 0000

0

1

0

0

0

1

1

1

47h

Pull-up/pull-down enableregister 1

read/write byte

0000 0000

0

1

0

0

1

0

0

0

48h

Pull-up/pull-down
selection register 0

read/write byte

1111 1111

0

1

0

0

1

0

0

1

49h

Pull-up/pull-down
selection register 1

read/write byte

1111 1111

0

1

0

0

1

0

1

0

4Ah

Interrupt mask register 0

read/write byte

1111 1111

PCAL6416A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7.1 — 30 August 2022

[1]

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 6. Command byte...continued
Pointer register bits

Command byte Register(hexadecimal)

ProtocolPower-up
default

B7

B6

B5

B4

B3

B2

B1

B0

0

1

0

0

1

0

1

1

4Bh

Interrupt mask register 1

read/write byte

1111 1111

0

1

0

0

1

1

0

0

4Ch

Interrupt status register 0

read byte

0000 0000

0

1

0

0

1

1

0

1

4Dh

Interrupt status register 1

read byte

0000 0000

0

1

0

0

1

1

1

1

4Fh

Output port configuration
registerread/write byte

0000 0000[1]

Undefined.

7.4 Register descriptions
7.4.1 Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 8.2.
Table 7. Input port 0 register (address 00h)
Bit

7

6

5

4

3

2

1

0

Symbol

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

Default

X

X

X

X

X

X

X

X

Table 8. Input port 1 register (address 01h)
Bit

7

6

5

4

3

2

1

0

Symbol

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

Default

X

X

X

X

X

X

X

X

7.4.2 Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) shows the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have noeffect on pins defined as inputs. In turn, reads from these registers reflect the value thatwas written to these registers, not the actual pin value. A register pair write operation is
described in Section 8.1. A register pair read operation is described in Section 8.2.
Table 9. Output port 0 register (address 02h)
Bit

PCAL6416A

Product data sheet

7

6

5

4

3

2

1

0

Symbol

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

Default

1

1

1

1

1

1

1

1

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 10. Output port 1 register (address 03h)
Bit

7

6

5

4

3

2

1

0

Symbol

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

Default

1

1

1

1

1

1

1

1

7.4.3 Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with‘1’), the corresponding port pin’s polarity is inverted in the input register. If a bit in thisregister is cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A
register pair write operation is described in Section 8.1. A register pair read operation is
described in Section 8.2.
Table 11. Polarity inversion port 0 register (address 04h)
Bit

7

6

5

4

3

2

1

0

Symbol

N0.7

N0.6

N0.5

N0.4

N0.3

N0.2

N0.1

N0.0

Default

0

0

0

0

0

0

0

0

Table 12. Polarity inversion port 1 register (address 05h)
Bit

7

6

5

4

3

2

1

0

Symbol

N1.7

N1.6

N1.5

N1.4

N1.3

N1.2

N1.1

N1.0

Default

0

0

0

0

0

0

0

0

7.4.4 Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins.
If a bit in these registers is set to 1, the corresponding port pin is enabled as a highimpedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write operation is described in Section 8.1. A
register pair read operation is described in Section 8.2.
Table 13. Configuration port 0 register (address 06h)
Bit

7

6

5

4

3

2

1

0

Symbol

C0.7

C0.6

C0.5

C0.4

C0.3

C0.2

C0.1

C0.0

Default

1

1

1

1

1

1

1

1

Table 14. Configuration port 1 register (address 07h)
Bit

PCAL6416A

Product data sheet

7

6

5

4

3

2

1

0

Symbol

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Default

1

1

1

1

1

1

1

1

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

7.4.5 Output drive strength register pairs (40h, 41h, 42h, 43h)
The Output drive strength registers control the output drive level of the GPIO. Each
GPIO can be configured independently to a certain output current level by two register
control bits. For example Port 0.7 is controlled by register 41 CC0.7 (bits [7:6]), Port
0.6 is controlled by register 41 CC0.6 (bits [5:4]). The output drive level of the GPIO is
programmed 00b = 0.25×, 01b = 0.5×, 10b = 0.75× or 11b = 1× of the drive capability of
the I/O. See Section 9.2 for more details. A register pair write operation is described in
Section 8.1. A register pair read operation is described in Section 8.2.
Table 15. Current control port 0 register (address 40h)
Bit

7

SymbolDefault

6

5

CC0.3
1

4

3

CC0.2
1

1

2

1

CC0.1
1

0
CC0.0

1

1

1

1

3

2

1

0

Table 16. Current control port 0 register (address 41h)
Bit

7

SymbolDefault

6

5

CC0.7
1

4
CC0.6

1

1

CC0.5
1

CC0.4

1

1

1

1

3

2

1

0

Table 17. Current control port 1 register (address 42h)
Bit

7

SymbolDefault

6

5

CC1.3
1

4
CC1.2

1

1

CC1.1
1

CC1.0

1

1

1

1

3

2

1

0

Table 18. Current control port 1 register (address 43h)
Bit

7

SymbolDefault

6

5

CC1.7
1

4
CC1.6

1

1

CC1.5
1

1

CC1.4
1

1

1

7.4.6 Input latch register pair (44h, 45h)
The input latch registers (registers 44 and 45) enable and disable the input latch of the
I/O pins. These registers are effective only when the pin is configured as an input port.
When an input latch register bit is 0, the corresponding input pin state is not latched. A
state change in the corresponding input pin generates an interrupt. A read of the input
register clears the interrupt. If the input goes back to its initial logic state before the input
port register is read, then the interrupt is cleared.
When an input latch register bit is 1, the corresponding input pin state is latched. Achange of state of the input generates an interrupt and the input logic value is loaded
into the corresponding bit of the input port register (registers 0 and 1). A read of the input
port register clears the interrupt. If the input pin returns to its initial logic state before theinput port register is read, then the interrupt is not cleared and the corresponding bit of
the input port register keeps the logic value that initiated the interrupt. See Figure 16.
PCAL6416A

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PCAL6416A

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2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back tologic 0, the input port 0 register will capture this change and an interrupt is generated(if unmasked). When the read is performed on the input port 0 register, the interrupt iscleared, assuming there were no additional input(s) that have changed, and bit 4 of the
input port 0 register will read ‘1’. The next read of the input port register bit 4 registershould now read ‘0’.
An interrupt remains active when a non-latched input simultaneously switches state witha latched input and then returns to its original state. A read of the input register reflects
only the change of state of the latched input and also clears the interrupt. The interrupt is
not cleared if the input latch register changes from latched to non-latched configuration.
If the input pin is changed from latched to non-latched input, a read from the input
port register reflects the current port logic level. If the input pin is changed from nonlatched to latched input, the read from the input register reflects the latched logic level. A
register pair write operation is described in Section 8.1. A register pair read operation is
described in Section 8.2.
Table 19. Input latch port 0 register (address 44h)
Bit

7

6

5

4

3

2

1

0

Symbol

L0.7

L0.6

L0.5

L0.4

L0.3

L0.2

L0.1

L0.0

Default

0

0

0

0

0

0

0

0

Table 20. Input latch port 1 register (address 45h)
Bit

7

6

5

4

3

2

1

0

Symbol

L1.7

L1.6

L1.5

L1.4

L1.3

L1.2

L1.1

L1.0

Default

0

0

0

0

0

0

0

0

7.4.7 Pull-up/pull-down enable register pair (46h, 47h)
These registers allow the user to enable or disable pull-up/pull-down resistors on the I/O
pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting
the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, theresistors will be disconnected when the outputs are configured as open-drain outputs(see Section 7.4.11). Use the pull-up/pull-down registers to select either a pull-up or pulldown resistor. A register pair write operation is described in Section 8.1. A register pairread operation is described in Section 8.2.
Table 21. Pull-up/pull-down enable port 0 register (address 46h)
Bit

7

6

5

4

3

2

1

0

Symbol

PE0.7

PE0.6

PE0.5

PE0.4

PE0.3

PE0.2

PE0.1

PE0.0

Default

0

0

0

0

0

0

0

0

Table 22. Pull-up/pull-down enable port 1 register (address 47h)
Bit

PCAL6416A

Product data sheet

7

6

5

4

3

2

1

0

Symbol

PE1.7

PE1.6

PE1.5

PE1.4

PE1.3

PE1.2

PE1.1

PE1.0

Default

0

0

0

0

0

0

0

0

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PCAL6416A

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2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

7.4.8 Pull-up/pull-down selection register pair (48h, 49h)
The I/O port can be configured to have pull-up or pull-down resistor by programming
the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 kΩ pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 kΩ pull-down resistor forthat I/O pin. If the pull-up/down feature is disconnected, writing to this register will haveno effect on I/O pin. Typical value is 100 kΩ with minimum of 50 kΩ and maximum of
150 kΩ. A register pair write operation is described in Section 8.1. A register pair read
operation is described in Section 8.2.
Table 23. Pull-up/pull-down selection port 0 register (address 48h)
Bit

7

6

5

4

3

2

1

0

Symbol

PUD0.7

PUD0.6

PUD0.5

PUD0.4

PUD0.3

PUD0.2

PUD0.1

PUD0.0

Default

1

1

1

1

1

1

1

1

Table 24. Pull-up/pull-down selection port 1 register (address 49h)
Bit

7

6

5

4

3

2

1

0

SymbolPUD1.7

PUD1.6

PUD1.5

PUD1.4

PUD1.3

PUD1.2

PUD1.1

PUD1.0

Default

1

1

1

1

1

1

1

1

7.4.9 Interrupt mask register pair (4Ah, 4Bh)
Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts duringsystem start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0.
If an input changes state and the corresponding bit in the Interrupt mask register is set to1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding
bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bitis 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted.
If the interrupt mask bit of an input that is currently the source of an interrupt is set to1, the interrupt pin will be de-asserted. A register pair write operation is described in
Section 8.1. A register pair read operation is described in Section 8.2.
Table 25. Interrupt mask port 0 register (address 4Ah) bit description
Bit

7

6

5

4

3

2

1

0

Symbol

M0.7

M0.6

M0.5

M0.4

M0.3

M0.2

M0.1

M0.0

Default

1

1

1

1

1

1

1

1

Table 26. Interrupt mask port 1 register (address 4Bh) bit description
Bit

PCAL6416A

Product data sheet

7

6

5

4

3

2

1

0

Symbol

M1.7

M1.6

M1.5

M1.4

M1.3

M1.2

M1.1

M1.0

Default

1

1

1

1

1

1

1

1

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

7.4.10 Interrupt status register pair (4Ch, 4Dh)
These read-only registers are used to identify the source of an interrupt. When read, alogic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0
indicates that the input pin is not the source of an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt
status bit will return logic 0. A register pair write operation is described in Section 8.1. A
register pair read operation is described in Section 8.2.
Table 27. Interrupt status port 0 register (address 4Ch) bit description
Bit

7

6

5

4

3

2

1

0

Symbol

S0.7

S0.6

S0.5

S0.4

S0.3

S0.2

S0.1

S0.0

Default

0

0

0

0

0

0

0

0

Table 28. Interrupt status port 1 register (address 4Dh) bit description
Bit

7

6

5

4

3

2

1

0

Symbol

S1.7

S1.6

S1.5

S1.4

S1.3

S1.2

S1.1

S1.0

Default

0

0

0

0

0

0

0

0

7.4.11 Output port configuration register (4Fh)
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 10). A logic
1 configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended
command sequence is to program this register (4Fh) before the configuration register(06h and 07h) sets the port pins as outputs.
ODEN0 configures Port 0_x and ODEN1 configures Port 1_x.
Table 29. Output port configuration register (address 4Fh)
Bit

7

6

5

SymbolDefault432

reserved
0

0

0

0

0

0

1

0

ODEN1

ODEN0

0

0

7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a highimpedance input. The input voltage may be raised above VDD(P) to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin andeither VDD(P) or VSS. The external voltage applied to this I/O pin should not exceed therecommended levels for proper operation.

PCAL6416A

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
data fromshift register

output port
register data

configuration
registerdata fromshift register

D

write
configuration
pulse

CK

VDD(P)Q

Q1

ESD
protection
diode

Q2

ESD
protection
diode

FF
D

Q

Q
FF

write pulse

CK
output port
register

P0_0 to P0_7
P1_0 to P1_7

VSS
D

Q

input port
register dataFF
read pulse

CK

VDD(P)

PULL-UP/PULL-DOWN
CONTROL

INTERRUPT
MASK

input port
register

100 kD

input latch
registerdata fromshift register
write input
latch pulseD

to INT

Q

LATCH

Q

read pulseFF
polarity inversion
register

CK

data fromshift registerDwrite polarity
pulse

CK

EN
input port
latch

Q
FF
002aag971

On power-up or reset, all registers return to default values.
Figure 10. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)

7.6 Power-on reset
When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the
PCAL6416A in a reset condition until VDD(P) has reached VPOR. At that time, the reset2
condition is released and the PCAL6416A registers and I C-bus/SMBus state machine
initializes to their default states. After that, VDD(P) must be lowered to below VPOR andback up to the operating voltage for a power-reset cycle. See Section 9.3 "Power-on
reset requirements".

7.7 Reset input (RESET)The RESET input can be asserted to initialize the system while keeping the VDD(P) at
its operating level. A reset can be accomplished by holding the RESET pin LOW for a2
minimum of tw(rst). The PCAL6416A registers and I C-bus/SMBus state machine arechanged to their default state once RESET is LOW (0). When RESET is HIGH (1), theI/O levels at the P port can be changed externally or through the master. This input
requires a pull-up resistor to VDD(I2C-bus) if no active connection is used.

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NXP Semiconductors
2

PCAL6416A

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

7.8 Interrupt output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. The interrupt is reset when data on the portchanges back to the original value or when data is read from the port that generated
the interrupt (see Figure 16). Resetting occurs in the Read mode at the acknowledge(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interruptsthat occur during the ACK or NACK clock pulse can be lost (or be very short) due tothe resetting of the interrupt during this pulse. Any change of the I/Os after resetting is
detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match thecontents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VDD(P) or
VDD(I2C-bus), depending on the application. INT should be connected to the voltage sourceof the device that requires the interrupt information.
When using the input latch feature, the input pin state is latched. The interrupt is reset
only when data is read from the port that generated the interrupt. The reset occurs in theRead mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the risingedge of the SCL signal.

8

Bus transactions
2

The PCAL6416A is an I C-bus slave device. Data is exchanged between the master and2
PCAL6416A through write and read commands using I C-bus. The two communicationlines are a serial data line (SDA) and a serial clock line (SCL). Both lines must beconnected to a positive supply via a pull-up resistor when connected to the output stagesof a device. Data transfer may be initiated only when the bus is not busy.

8.1 Write commands
Data is transmitted to the PCAL6416A by sending the device address and setting the
Least Significant Bit (LSB) to a logic 0 (see Figure 8 for device address). The commandbyte is sent after the address and determines which register receives the data that
follows the command byte.
Twenty-two registers within the PCAL6416A are configured to operate as eleven registerpairs. The eleven pairs are input port, output port, polarity inversion, configuration, output
drive strength (two 16-bit registers), input latch, pull-up/pull-down enable, pull-up/pulldown selection, interrupt mask, and interrupt status registers. After sending data to one
register, the next data byte is sent to the other register in the pair (see Figure 11 andFigure 12). For example, if the first byte is sent to Output Port 1 (register 3), the next byte
is stored in Output Port 0 (register 2).
There is no limit on the number of data bytes sent in one write transmission. In this way,
the host can continuously update a register pair independently of the other registers.

PCAL6416A

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NXP Semiconductors

PCAL6416A

2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
SCL

1

2

3

4

5

6

7

8

9

slave address
SDA S

0

1

0

0

command byte
AD
0 DR 00START condition

R/W

A

0

0

0

0

0

data to port 001

acknowledge
from slave

0

A 0.7

STOP
condition

data to port 1

DATA 00.0 A 1.7

acknowledge
from slave

DATA 1

1.0 A

acknowledge
from slaveP

acknowledge
from slave

write to porttv(Q)data out from port 0

DATA 0 VALID
tv(Q)DATA 1 VALID

data out from port 1002aaf556

Figure 11. Write to Output port register
SCL

1

2

3

4

5

6

7

8

9

slave address
SDA S

0

1

0

0

START condition0command byte
0

AD
0
DR
R/W

A

0 1/0 0acknowledge
from slave

data to register0 1/0 1/0 1/0 1/0 A

DATA 0MSB
acknowledge
from slave

STOP
condition

data to register
A
LSB

MSB
acknowledge
from slave

DATA 1A

P

LSB
acknowledge
from slave002aag972

Figure 12. Write to device registers

PCAL6416A

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

8.2 Read commands
To read data from the PCAL6416A, the bus master must first send the PCAL6416A
address with the least significant bit set to a logic 0 (see Figure 8 for device address).
The command byte is sent after the address and determines which register is to beaccessed.
After a restart, the device address is sent again, but this time the least significant bit
is set to a logic 1. Data from the register defined by the command byte is sent by the
PCAL6416A (see Figure 13 and Figure 16). Data is clocked into the register on the risingedge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflects the information in the other register in the pair. For example, if Input
Port 1 is read, the next byte read is Input Port 0.There is no limit on the number of databytes received in one read transmission, but on the final byte received the bus mastermust not acknowledge the data.
After a subsequent restart, the command byte contains the value of the next registerto be read in the pair. For example, if Input Port 1 was read last before the restart, theregister that is read after the restart is the Input Port 0.
command byte

slave address
SDA S

0

1

0

0

0 AD 0DR

0START conditionA0 1/0 0R/W

acknowledge
from slaveacknowledge
from slave

data from lower orupper byte of registerslave address(cont.) S

0

1

0

0

(repeated)
START condition

0MSB
0 AD 1DR(cont.)

0 1/0 1/0 1/0 1/0 A

A

R/W
acknowledge
from slave

data from upper orlower byte of register
LSB

DATA (first byte)

MSB
A

acknowledge
from master

LSB
DATA (last byte)NAno acknowledge
from masterat this moment master-transmitter becomes master-receiverand slave-receiver becomes slave-transmitter

P
STOP
condition

002aah046

Figure 13. Read from device registers

PCAL6416A

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NXP Semiconductors

PCAL6416A

2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
data into port 0
data into port 1
INT
tv(INT)
SCL

1

2

3

4

trst(INT)
5

6slave address
SDA S

0

1

0

0

START condition

0

7

8

9

R/W
AD
0 DR 1

I0.x
A

acknowledge
from slave

7

6

5

4

I1.x

3

2

1

0

A

acknowledge
from master

7

6

5

4

3

I0.x
2

1

0

A

7

acknowledge
from master

6

5

4

3

STOP condition

I1.x
2

1

0

A

acknowledge
from master

7

6

5

4

3

2

1

0

1

P

non acknowledge
from masterread from port 0
read from port 1002aah143

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is
assumed that the command byte has previously been set to ‘00’ (read input port register).
This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 13).
Figure 14. Read input port register (non-latched), scenario 1

PCAL6416A

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NXP Semiconductors

PCAL6416A

2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
data into port 0

DATA 00

DATA 01

DATA 02th(D)data into port 1

DATA 03tsu(D)DATA 10DATA 11DATA 12th(D)tsu(D)

INT
tv(INT)
SCL

1

2

3

4

trst(INT)
5

6slave address
SDA S

0

1

0

0

START condition

0

7

8

9

R/W
AD
0 DR 1

I0.x
A

acknowledge
from slave

I1.x

DATA 00

A
acknowledge
from master

I0.x

DATA 10A
acknowledge
from master

DATA 03

I1.x
A
acknowledge
from master

DATA 12

STOP condition
1P

non acknowledge
from masterread from port 0
read from port 1002aah144

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is
assumed that the command byte has previously been set to ‘00’ (read input port register).
This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 13).
Figure 15. Read input port register (non-latched), scenario 2

PCAL6416A

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NXP Semiconductors

PCAL6416A

2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
data into port 0

DATA 01

DATA 02

DATA 01tsu(D)
data into port 1

DATA 10DATA 11DATA 10

I1.x

I0.x

th(D)
INT
tv(INT)
SCL

1

2

3

4

trst(INT)
5

6slave address
SDA S

0

1

0

0

START condition

0

7

8

9

R/W
AD
0 DR 1

I0.x
A

acknowledge
from slave

DATA 01A
acknowledge
from master

DATA 10A
acknowledge
from master

DATA 02

I1.x
A
acknowledge
from master

DATA 11

STOP condition
1P

non acknowledge
from masterread from port 0
read from port 1002aah054

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is
assumed that the command byte has previously been set to ‘00’ (read input port register).
This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 13).
Figure 16. Read input port register (latch enabled), scenario 3

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

9

Application design-in information
VDD(I2C-bus)

VDD(P)VDD(I2C-bus) = 1.8 V
10 k

VDD
MASTERCONTROLLER
SCL
SDA
INT
RESET

10 k

10 k

10 k

(×7)

ALARM(1)
SUBSYSTEM 1(e.g., alarm system)

10 k

VDD(I2C-bus)
SCL
SDA
INT
RESET

VDD(P)
P0_0
P0_1

A
controlledswitchenablePCAL6416A

B

P0_2
P0_3

GND

P0_4
P0_5
P0_6
P0_7
P1_0
P1_1

KEYPAD

P1_2
P1_3

ADDR

P1_4
P1_5
P1_6
GND

P1_7

002aaf965

Device address configured as 0100 000x for this example.
P0_0 and P0_2 through P1_0 are configured as inputs.
P0_1 and P1_1 through P1_7 are configured as outputs.
1. External resistors are required for inputs (on P port) that may float. Also, internal pull-up or pull-down may be used toeliminate the need for external components. If a driver to an input will never let the input float, a resistor is not needed.
If an output in the P port is configured as a push-pull output there is no need for external pull-up resistors. If an output
in the P port is configured as an open-drain output, external pull-up resistors are required.
Figure 17. Typical application

9.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 17. Since the LED acts as a diode, when the LED is off the I/
O VI is about 1.2 V less than VDD(P). The supply current, IDD(P), increases as VI becomes
lower than VDD(P).
Designs needing to minimize current consumption, such as battery power applications,should consider maintaining the I/O pins greater than or equal to VDD when the
LED is off. Figure 18 shows a high value resistor in parallel with the LED. Figure 19
shows VDD(P) less than the LED supply voltage by at least 1.2 V. Both of thesemethods maintain the I/O VI at or above VDD(P) and prevents additional supply current
consumption when the LED is off.

PCAL6416A

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
3.3 V

VDD

VDD(P)5V

VDD(P)

LED

Pn

LED

Pn

002aah278

Figure 18. High value resistor in parallelwith the LED

002aah279

Figure 19. Device supplied by a lower
voltage

9.2 Output drive strength control
The Output drive strength registers allow the user to control the output drive level of the
GPIO. Each GPIO can be configured independently to one of the four possible output
current levels. By programming these bits the user is changing the number of transistor
pairs or ‘fingers’ that drive the I/O pad.
Figure 20 shows a simplified output stage. The behavior of the pad is affected by theConfiguration register, the output port data, and the current control register. When the
Current Control register bits are programmed to 10b, then only two of the fingers areactive, reducing the current drive capability by 50 %.

PMOS_EN0

Current Control
register

DECODER

PMOS_EN[3:0]
NMOS_EN[3:0]

Configuration
register

VDD(P)

PMOS_EN1

PMOS_EN2

PMOS_EN3
P0_0 to P0_7
P1_0 to P1_7

Output port
register
NMOS_EN3

NMOS_EN2

NMOS_EN1

NMOS_EN0002aah053

Figure 20. Simplified output stage

Reducing the current drive capability may be desirable to reduce system noise. Whenthe output switches (transitions from H/L), there is a peak current that is a function of theoutput drive selection. This peak current runs through VDD and VSS package inductance
PCAL6416A

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
and will create noise (some radiated, but more critically Simultaneous Switching Noise(SSN)). In other words, switching many outputs at the same time will create groundand supply noise. The output drive strength control through the Output Drive Strength
registers allows the user to mitigate SSN issues without the need of additional external
components.

9.3 Power-on reset requirements
In the event of a glitch or data corruption, PCAL6416A can be reset to its default
conditions by using the power-on reset feature. Power-on reset requires that the device
go through a power cycle to be completely reset. This reset also happens when thedevice is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 21 and Figure 22.
VDD(P)
ramp-upramp-down

re-ramp-up
td(rst)(dV/dt)r(dV/dt)f

time to re-ramp
when VDD(P) drops
below 0.2 V or to VSS

time(dV/dt)r

002aag960

Figure 21. VDD(P) is lowered below 0.2 V or to 0 V and then ramped up to VDD(P)
VDD(P)
ramp-down

ramp-uptd(rst)VI drops below POR levels(dV/dt)f

time to re-ramp
when VDD(P) drops
to VPOR(min) - 50 mV

time(dV/dt)r

002aag961

Figure 22. VDD(P) is lowered below the POR threshold, then ramped back up to VDD(P)

Table 30 specifies the performance of the power-on reset feature for PCAL6416A for bothtypes of power-on reset.
Table 30. Recommended supply sequencing and ramp rates
Tamb = 25 °C (unless otherwise noted). Not tested; specified by design.
SymbolParameter

Condition

Min

Typ

Max

Unit

(dV/dt)ffall rate of change of voltage

Figure 21

0.1

-

2000

ms

(dV/dt)rrise rate of change of voltage

Figure 21

0.1

-

2000

ms

td(rst)reset delay time

Figure 21; re-ramp time when VDD(P)drops below 0.2 V or to VSS)

1

-

-

μs

Figure 22; re-ramp time when VDD(P)drops to VPOR(min) - 50 mV)

1

-

-

μs

ΔVDD(gl)glitch supply voltage difference

Figure 23

[1]

-

-

1.0

V

[2]

-

-

10

μs

0.7

-

-

V

tw(gl)VDD

supply voltage glitch pulse width

Figure 23

VPOR(trip)

power-on reset trip voltage

falling VDD(P)PCAL6416A

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 30. Recommended supply sequencing and ramp rates...continued
Tamb = 25 °C (unless otherwise noted). Not tested; specified by design.
Symbol[1][2]

Parameter

Condition

Min

Typ

Max

Unit

rising VDD(P)

-

-

1.4

V

Level that VDD(P) can glitch down to with a ramp rate = 0.4 μs/V, but not cause a functional disruption when tw(gl)VDD < 1 μs.
Glitch width that will not cause a functional disruption when ΔVDD(gl) = 0.5 × VDD(P).

Glitches in the power supply can also affect the power-on reset performance of thisdevice. The glitch width (tw(gl)VDD) and glitch height (ΔVDD(gl)) are dependent on eachother. The bypass capacitance, source impedance, and device impedance are factorsthat affect power-on reset performance. Figure 23 and Table 30 provide more information
on how to measure these specifications.
VDD(P)VDD(gl)tw(gl)VDD

time002aag962

Figure 23. Glitch width and glitch height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset2
condition is released and all the registers and the I C-bus/SMBus state machine are
initialized to their default states. The value of VPOR differs based on the VDD(P) being
lowered to or from 0 V. Figure 24 and Table 30 provide more details on this specification.
VDD(P)VPOR (rising VDD(P))
VPOR (falling VDD(P))
time
POR

time
002aag963

Figure 24. Power-on reset voltage (VPOR)

9.4 Device current consumption with internal pull-up and pull-downresistors
The PCAL6416A integrates programmable pull-up and pull-down resistors to eliminate
external components when pins are configured as inputs and pull-up or pull-downresistors are required (for example, nothing is driving the inputs to the power supply
rails. Since these pull-up and pull-down resistors are internal to the device itself, they
contribute to the current consumption of the device and must be considered in the overallsystem design.
The pull-up or pull-down function is selected in registers 48h and 49h, while the resistor
is connected by the enable registers 46h and 47h. The configuration of the resistors isshown in Figure 10.
PCAL6416A

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NXP Semiconductors
2

PCAL6416A

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow fromthe VDD(P) pin through the resistor to ground when the pin is held LOW. This current willappear as additional IDD upsetting any current consumption measurements.
In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH,
current will flow from the power supply through the pin to the VSS pin. While this current
will not be measured as part of IDD, one must be mindful of the 200 mA limiting value
through VSS.
The pull-up and pull-down resistors are simple resistors and the current is linear with
voltage. The resistance specification for these devices spans from 50 kΩ with a nominal
100 kΩ value. Any current flow through these resistors is additive by the number of pins
held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 28 for agraph of supply current versus the number of pull-up resistors.
2

9.5 I C-bus error recovery techniques
2

There are a number of techniques to recover from error conditions on the I C-bus. Slave2
devices like the PCAL6416A use a state machine to implement the I C protocol andexpect a certain sequence of events to occur to function properly. Unexpected events
2at the I C master can wreak havoc with the slaves connected on the bus. However, it isusually possible to recover deterministically to a known bus state with careful protocol
manipulation.
A hard slave reset, either through power-on reset or by activating the RESET pin, will set
the device back into the default state. Of course, this means the input/output pins andtheir configuration will be lost, which might cause some system issues.
A STOP condition, which is only initiated by the master, will reset the slave state machine
into a known condition where SDA is not driven LOW by the slave and logically, the slave
is waiting for a START condition. A STOP condition is defined as SDA transitioning from
LOW to HIGH while SCL is HIGH.
If the master is interrupted during a packet transmission, the slave may be sending data2
or performing an Acknowledge, driving the I C-bus SDA line LOW. Since SDA is LOW,
2
it effectively blocks any other I C-bus transaction. A deterministic method to clear thissituation, once the master recognizes a ‘stuck bus’ state, is for the master to blindlytransmit nine clocks on SCL. If the slave was transmitting data or acknowledging, nineor more clocks ensures the slave state machine returns to a known, idle state since theprotocol calls for eight data bits and one ACK bit. It does not matter when the slave statemachine finishes its transmission, extra clocks will be recognized as STOP conditions.
The PCAL6416A SCL pin is an input only. If SCL is stuck LOW, then only the bus masteror a slave performing a clock stretch operation can cause this condition.
2

With careful design of the bus master error recovery firmware, many I C-bus protocol
problems can be avoided.

10 Limiting values
Table 31. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
SymbolParameter

Min

Max

Unit

VDD(I2C-bus)

2

I C-bus supply voltage

-0.5

+6.5

V

VDD(P)

supply voltage port P

-0.5

+6.5

V

PCAL6416A

Product data sheet

Conditions

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 31. Limiting values...continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol

Min

Max

Unit

input voltage

[1]

-0.5

+6.5

V

VO

output voltage

[1]

-0.5

+6.5

V

IIK

input clamping current

ADDR, RESET, SCL; VI < 0 V

-

±20

mA

IOK

output clamping current

INT; VO < 0 V

-

±20

mA

IIOK

input/output clamping current

P port; VO < 0 V or VO > VDD(P)

-

±20

mA

SDA; VO < 0 V or VO > VDD(I2C-bus)

-

±20

mA

continuous; P port; VO = 0 V to VDD(P)

-

50

mA

continuous; SDA, INT;
VO = 0 V to VDD(I2C-bus)

-

25

mA

VI

IOL

Parameter

Conditions

LOW-level output current

IOH

HIGH-level output current

continuous; P port; VO = 0 V to VDD(P)

-

25

mA

IDD

supply current

continuous through VSS

-

200

mA

IDD(P)

supply current port P

continuous through VDD(P)

-

160

mA

IDD(I2C-bus)

2

I C-bus supply current

continuous through VDD(I2C-bus)

-

10

mA

Tstg

storage temperature

-65

+150

°C

Tj(max)maximum junction temperature

-

125

°C

[1]

The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

11 Recommended operating conditions
Table 32. Operating conditions
SymbolParameter

Min

Max

Unit

VDD(I2C-bus)

2

I C-bus supply voltage

1.65

5.5

V

VDD(P)

supply voltage port P

1.65

5.5

V

VIH

HIGH-level input voltage

SCL, SDA, RESET

0.7 × VDD(I2C-bus)

5.5

V

ADDR, P1_7 to P0_0

0.7 × VDD(P)

5.5

V

SCL, SDA, RESET-0.5

0.3 × VDD(I2C-bus)

V

ADDR, P1_7 to P0_0

-0.5

0.3 × VDD(P)V

VIL

Conditions

LOW-level input voltage

IOH

HIGH-level output current

P1_7 to P0_0

-

10

mA

IOL

LOW-level output current

P1_7 to P0_0

-

25

mA

Tamb

ambient temperature

operating in free air

-40

+85

°C

12 Thermal characteristics
Table 33. Thermal characteristics
SymbolZth(j-a)Parameter

Conditionstransient thermal impedance from junction toambient

PCAL6416A

Product data sheet

Max

Unit

TSSOP24 package

[1]

88

K/W

HWQFN24 package

[1]

66

K/W

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 33. Thermal characteristics...continued
SymbolParameter

Conditions[1]

VFBGA24 package
[1]

Max

Unit

171

K/W

The package thermal impedance is calculated in accordance with JESD 51-7.

13 Static characteristics
Table 34. Static characteristics
Tamb = -40 °C to +85 °C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
SymbolParameter

Conditions

Min

Typ

VIK

input clamping voltage

II = -18 mA

-1.2

VPOR

power-on reset voltage

VI = VDD(P) or VSS; IO = 0 mA

VOH

HIGH-level output[2]
voltage

P port; IOH = -8 mA; CCX.X = 11b

[1]

Max

Unit

-

-

V

-

1.1

1.4

V

VDD(P) = 1.65 V

1.2

-

-

V

VDD(P) = 2.3 V

1.8

-

-

V

VDD(P) = 3 V

2.6

-

-

V

VDD(P) = 4.5 V

4.1

-

-

V

VDD(P) = 1.65 V

1.1

-

-

V

VDD(P) = 2.3 V

1.7

-

-

V

VDD(P) = 3 V

2.5

-

-

V

VDD(P) = 4.5 V

4.0

-

-

V

VDD(P) = 1.65 V

-

-

0.45

V

VDD(P) = 2.3 V

-

-

0.25

V

VDD(P) = 3 V

-

-

0.25

V

VDD(P) = 4.5 V

-

-

0.2

V

VDD(P) = 1.65 V

-

-

0.5

V

VDD(P) = 2.3 V

-

-

0.3

V

VDD(P) = 3 V

-

-

0.25

V

VDD(P) = 4.5 V

-

-

0.2

V

3

-

-

mA

P port; IOH = -2.5 mA and CCX.X = 00b;
IOH = -5 mA and CCX.X = 01b;
IOH = -7.5 mA and CCX.X = 10b;
IOH = -10 mA and CCX.X = 11b;

VOL

LOW-level output[2]
voltage

P port; IOL = 8 mA; CCX.X = 11b

P port; IOL = 2.5 mA and CCX.X = 00b;
IOL = 5 mA and CCX.X = 01b;
IOL = 7.5 mA and CCX.X = 10b;
IOL = 10 mA and CCX.X = 11b;

IOL

LOW-level output[3]
current

PCAL6416A

Product data sheet

VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V
SDA

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 34. Static characteristics...continued
Tamb = -40 °C to +85 °C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
SymbolParameter

Conditions
INT

II

input current

Min

Typ

[1]

[4]

Max

Unit

-

mA

3

15

SCL, SDA, RESET; VI = VDD(I2C-bus) or VSS

-

-

±1

μA

ADDR; VI = VDD(P) or VSS

-

-

±1

μA

VDD(P) = 1.65 V to 5.5 V

IIH

HIGH-level input current P port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 V

-

-

1

μA

IIL

LOW-level input current

P port; VI = VSS; VDD(P) = 1.65 V to 5.5 V

-

-

1

μA

IDD

supply current

IDD(I2C-bus) + IDD(P);SDA, P port, ADDR, RESET;
VI on SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port and ADDR = VDD(P);IO = 0 mA; I/O = inputs; fSCL = 400 kHz
VDD(P) = 3.6 V to 5.5 V

-

10

25

μA

VDD(P) = 2.3 V to 3.6 V

-

6.5

15

μA

VDD(P) = 1.65 V to 2.3 V

-

4

9

μA

VDD(P) = 3.6 V to 5.5 V

-

1.5

7

μA

VDD(P) = 2.3 V to 3.6 V

-

1

3.2

μA

VDD(P) = 1.65 V to 2.3 V

-

0.5

1.7

μA

VDD(P) = 3.6 V to 5.5 V

-

60

125

μA

VDD(P) = 2.3 V to 3.6 V

-

40

75

μA

VDD(P) = 1.65 V to 2.3 V

-

20

45

μA

-

1.1

1.5

mA

IDD(I2C-bus) + IDD(P);SCL, SDA, P port, ADDR, RESET;
VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port and ADDR = VDD(P);IO = 0 mA; I/O = inputs; fSCL = 0 kHz

Active mode; IDD(I2C-bus) + IDD(P);P port, ADDR, RESET;
VI on RESET = VDD(I2C-bus);
VI on P port and ADDR = VDD(P);IO = 0 mA; I/O = inputs;
fSCL = 400 kHz, continuous register readwith pull-ups enabled (PCAL6416A only);
IDD(I2C-bus) + IDD(P); P port, ADDR, RESET;
VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port = VSS;
VI on ADDR = VDD(I2C-bus) or VSS;
IO = 0 mA; I/O = inputs with pull-up enabled;
fSCL = 0 kHz
VDD(P) = 1.65 V to 5.5 V

PCAL6416A

Product data sheet

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Table 34. Static characteristics...continued
Tamb = -40 °C to +85 °C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
SymbolParameter

Conditions

Min

Typ

ΔIDD

additional quiescent[5]
supply current

SCL, SDA, RESET;
one input at VDD(I2C-bus) - 0.6 V,
other inputs at VDD(I2C-bus) or VSS;VDD(P) = 1.65 V to 5.5 V-

P port, ADDR; one input at VDD(P) - 0.6 V,
other inputs at VDD(P) or VSS; VDD(P) = 1.65 V to 5.5
V
VI = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V

[1]

Max

Unit

-

25

μA

-

-

80

μA

-

6

7

pF

-

7

8

pF

VI/O = VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V

-

7.5

8.5

pF

Ci

input capacitanceCio

input/output capacitance VI/O = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V

Rpu(int)

internal pull-up
resistance

input/output

50

100

150

kΩ

Rpd(int)

internal pull-downresistance

input/output

50

100

150

kΩ

[1]
[2]
[3]
[4]
[5]

For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 °C. Except for IDD, the typical values are at
VDD(P) = VDD(I2C-bus) = 3.3 V and Tamb = 25 °C.
The total current sourced by all I/Os must be limited to 160 mA.
Each I/O must be externally limited to a maximum of 25 mA and each octal (P0_0 to P0_7 and P1_0 to P1_7) must be limited to a maximum current of
100 mA, for a device total of 200 mA.
Typical value for Tamb = 25 °C. VOL = 0.4 V and VDD(I2C-bus) = VDD(P) = 3.3 V. Typical value for VDD(I2C-bus) = VDD(P) < 2.5 V, VOL = 0.6 V.
Internal pull-up/pull-down resistors disabled.

13.1 Typical characteristics
IDD
(µA)

002aag973

20

IDD(stb)(nA)

16

VDD(P) = 5.5 V
5.0 V
3.6 V
12
3.3 V
2.5 V
2.3 V
8

1000
800

VDD(P) = 5.5 V
5.0 V
3.6 V
3.3 V

600
400

4
0
- 40

002aag974

1400

VDD(P) = 1.8 V
1.65 V
- 15

10

35

60
85
Tamb (°C)

IDD = IDD(I2C-bus) + IDD(P)
Figure 25. Supply current versus ambient temperature

PCAL6416A

Product data sheet

2.5 V
2.3 V
1.8 V
1.65 V

200
0
- 40

- 15

10

35

60
85
Tamb (°C)

Figure 26. Standby supply current versus ambient
temperature

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
002aag975

20
IDD
(µA)
16

002aah201

1.2

Tamb = - 40 °C
25 °C
85 °C

IDD(P)
(mA)

12

0.8

8

0.4

4
0
1.5

2.5

3.5

4.5
5.5
VDD(P) (V)

Tamb = 25 °C
IDD = IDD(I2C-bus) + IDD(P)
Figure 27. Supply current versus supply voltage

PCAL6416A

Product data sheet

0

0

4

8

12
16
number of I/O held LOW

Figure 28. Supply current versus number of I/O held
LOW

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Isink
(mA)

002aaf578

35
30

Tamb = - 40 °C
25 °C
85 °C

25

30

15

15

10

10

5

5
0.1

Tamb = - 40 °C
25 °C
85 °C

25
20

0

002aaf579

35

20

0

0.2

VOL (V)00.3

a. VDD(P) = 1.65 V
Isink
(mA)

Isink
(mA)

0

0.2

VOL (V)

0.3

b. VDD(P) = 1.8 V
002aaf580

50

002aaf581

60
Isink
(mA)

40
Tamb = - 40 °C
25 °C
85 °C

30

0.1

Tamb = - 40 °C
25 °C
85 °C

40

20

20

10
0

0

0.1

0.2

VOL (V)c. VDD(P) = 2.5 V
Isink
(mA)

0

0.3

002aaf582

Tamb = - 40 °C
25 °C
85 °C

60
50

Isink
(mA)

VOL (V)

0.3

30

20

20

10

10
0.2

Tamb = - 40 °C
25 °C
85 °C

50

30

0.1

002aaf583

60

40

e. VDD(P) = 5.0 V

0.2

70

40

0

0.1

d. VDD(P) = 3.3 V

70

0

0

VOL (V)

0.3

0

0

0.1

0.2

VOL (V)

0.3

f. VDD(P) = 5.5 V

Figure 29. I/O sink current versus LOW-level output voltage with CCX.X = 11b

PCAL6416A

Product data sheet

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2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
002aaf561

30Isource(mA)

Isource(mA)

Tamb = - 40 °C
25 °C
85 °C

20

002aaf562

35
Tamb = - 40 °C
25 °C
85 °C

30
25
20
15

10

10
5

0

0

0.2

a. VDD(P) = 1.65 V
002aaf563

Tamb = - 40 °C
25 °C
85 °C

40

0

0.2

0.4
0.6
VDD(P) - VOH (V)b. VDD(P) = 1.8 V

60Isource
(mA)

0

0.4
0.6
VDD(P) - VOH (V)Isource(mA)

002aaf564

70
Tamb = - 40 °C
25 °C
85 °C

60
50
40
30

20

20
10

0

0

0.2

0.4
0.6
VDD(P) - VOH (V)c. VDD(P) = 2.5 V
002aaf565

0.4
0.6
VDD(P) - VOH (V)002aaf566

Tamb = - 40 °C
25 °C
85 °C

60

30

0

0.2

90
Isource(mA)

Tamb = - 40 °C
25 °C
85 °C

60

0

d. VDD(P) = 3.3 V

90Isource
(mA)

0

30

0

e. VDD(P) = 5.0 V

0.2

0.4
0.6
VDD(P) - VOH (V)

0

0

0.2

0.4
0.6
VDD(P) - VOH (V)f. VDD(P) = 5.5 V

Figure 30. I/O source current versus HIGH-level output voltage with CCX.X = 11b

PCAL6416A

Product data sheet

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
VOL
(mV)

002aah056

120
100
(1)

80
60

160

(2)

40

120

(4)

20

(3)

0
- 40

002aah057

200
VDD(P) - VOH (mV)

VDD(P) = 1.8 V
5V

80
- 15

10

35

60
85
Tamb (°C)

1. VDD(P) = 1.8 V; Isink = 10 mA
2. VDD(P) = 5 V; Isink = 10 mA
3. VDD(P) = 1.8 V; Isink = 1 mA
4. VDD(P) = 5 V; Isink = 1 mA

40
0
- 40

- 15

10

35

60
85
Tamb (°C)

Isource = -10 mA

Figure 31. LOW-level output voltage versus temperature Figure 32. I/O high voltage versus temperature with
with CCX.X = 11b
CCX.X = 11b

14 Dynamic characteristics
2

Table 35. I C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 34.
SymbolParameter

Conditions

Standard2
mode I C-bus

Fast-mode2
I C-bus

Unit

Min

Max

Min

Max

fSCL

SCL clock frequency

0

100

0

400

kHz

tHIGH

HIGH period of the SCL clock

4

-

0.6

-

μs

tLOW

LOW period of the SCL clock

4.7

-

1.3

-

μs

tSP

pulse width of spikes that must be
suppressed by the input filter

0

50

0

50

ns

tSU;DATdata set-up time

250

-

100

-

ns

tHD;DATdata hold time

0

-

0

-

ns

tr

rise time of both SDA and SCL signals

-

1000

20

300

ns

tf

fall time of both SDA and SCL signals-

300

20 × (VDD/ 5.5 V)

300

ns

tBUF

bus free time between a STOP and
START condition

4.7

-

1.3

-

μs

tSU;STA

set-up time for a repeated START
condition

4.7

-

0.6

-

μs

tHD;STA

hold time (repeated) START condition

4

-

0.6

-

μs

tSU;STO

set-up time for STOP condition

4

-

0.6

-

μs

tVD;DATdata valid time

-

3.45

-

0.9

μs

PCAL6416A

Product data sheet

SCL LOW to SDA
output valid

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
2

Table 35. I C-bus interface timing requirements...continued
Over recommended operating free air temperature range, unless otherwise specified. See Figure 34.
SymboltVD;ACKParameter

data valid acknowledge time

Conditions

ACK signal fromSCL LOW to SDA(out) LOW

Standard2
mode I C-bus

Fast-mode2
I C-bus

Unit

Min

Max

Min

Max

-

3.45

-

0.9

μs

Table 36. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 36.
SymbolParameter

tw(rst)reset pulse widthtrec(rst)

reset recovery time

trst
[1]

Conditions[1]

reset timeStandard2
mode I C-bus

Fast-mode2
I C-bus

Unit

Min

Max

Min

Max

30

-

30

-

ns

200

-

200

-

ns

600

-

600

-

ns

Minimum time for SDA to become HIGH or minimum time to wait before doing a START.

Table 37. Switching characteristics
Over recommended operating free air temperature range; CL ≤ 100 pF; unless otherwise specified. See Figure 35.
SymbolParameter

Conditions

Standard2
mode I C-bus

Fast-mode2
I C-bus

Min

Max

Min

Max

Unit

tv(INT)

valid time on pin INTfrom P port to INT

-

1

-

1

μs

trst(INT)

reset time on pin INTfrom SCL to INT

-

1

-

1

μs

tv(Q)

data output valid timefrom SCL to P port

-

400

-

400

ns

tsu(D)

data input set-up timefrom P port to SCL

0

-

0

-

ns

th(D)

data input hold timefrom P port to SCL

300

-

300

-

ns

PCAL6416A

Product data sheet

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

15 Parameter measurement information
VDD(I2C-bus)
RL = 1 k

DUT

SDA
CL = 50 pF
002aag977

a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition(P)(S)

Address
Bit 7
(MSB)

Address
Bit 1

R/W
Bit 0
(LSB)

ACK
(A)

Data
Bit 7
(MSB)

Data
Bit 0
(LSB)

STOP
condition(P)
002aag952

b. Transaction format
tHIGH

tLOW

tSP
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)

SCL
tBUF

tr

tVD;DATtf

tf(o)tVD;ACKtSU;STA

SDA
tf
tHD;STAtrtSU;DATtHD;DATtSU;STO
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)tVD;ACK
repeat START condition
STOP condition

002aag978c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
2
Byte 1 = I C-bus address; Byte 2, byte 3 = P port data.
1. See Figure 16.
2

Figure 33. I C-bus interface load circuit and voltage waveforms

PCAL6416A

Product data sheet

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
VDD(I2C-bus)
RL = 4.7 k

INT

DUT

CL = 100 pF
002aag979

a. Interrupt load configuration
acknowledge
from slave
START condition

R/W

8 bits (one data byte)
from portslave address
SDA S

0

1

0

0

0

0 AD 1
DR

A

SCL

1

2

3

4

5

6

9

7

8

acknowledge
from slave

DATA 1no acknowledge
from master
STOP
condition

data from port
A

DATA 2

1

P

B
trst(INT) B

trst(INT)
INT
tv(INT)
data into
port

A
A

tsu(D)ADDRESSINTDATA 1

0.5 × VDD(I2C-bus)

SCL

DATA 2R/W

tv(INT)

0.3 × VDD(I2C-bus)
trst(INT)

0.5 × VDD(P)Pn

0.7 × VDD(I2C-bus)

A

0.5 × VDD(I2C-bus)

INT

View A - A

View B - B
002aag980

b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Figure 34. Interrupt load circuit and voltage waveforms

PCAL6416A

Product data sheet

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Pn

DUT

500
CL = 50 pF

2 × VDD(P)500002aag981

a. P port load configuration
SCL

P0

A

P7

0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)

SDA
tv(Q)
Pn
unstabledata

last stable bitAP7002aag982

b. Write mode (R/W = 0)SCL

P0tsu(D)

0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)

th(D)

Pn

0.5 × VDD(P)002aag983

CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 × VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
c. Read mode (R/W = 1)
Figure 35. P port load circuit and voltage waveforms

PCAL6416A

Product data sheet

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PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
VDD(I2C-bus)
RL = 1 k

SDA

DUT

Pn

DUT
CL = 50 pF

500
CL = 50 pF

2 × VDD(P)500002aag977

002aag981

a. SDA load configurationb. P port load configuration

START
SCL

ACK or read cycle

SDA

0.3 × VDD(I2C-bus)
trst

RESET

0.5 × VDD(I2C-bus)
trec(rst)

tw(rst)trst

Pntrec(rst)
0.5 × VDD(P)002aag984

CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
c. RESET timing
Figure 36. Reset load circuits and voltage waveforms

PCAL6416A

Product data sheet

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39 / 56

PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

16 Package outline
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.75 mm

B

D

SOT994-1A

terminal 1
index area

E

A
A1

c

detail X

e1
1/2 e

7

C

∅v M C A B∅w M C

b

e

12

y1 C

y

L
13

6

e

e2

Eh
1/2 e
1

18

terminal 1
index area

24

19

X

Dh
0

2.5

5 mm

scale
DIMENSIONS (mm are the original dimensions)
UNIT

A(1)
max

A1

b

c

D(1)

Dh

E (1)

Eh

e

e1

e2

L

v

w

y

y1

mm

0.8

0.05
0.00

0.30
0.18

0.2

4.1
3.9

2.25
1.95

4.1
3.9

2.25
1.95

0.5

2.5

2.5

0.5
0.3

0.1

0.05

0.05

0.1

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCESOUTLINE
VERSION

IEC

JEDEC

JEITA

SOT994-1---

MO-220---EUROPEAN
PROJECTION

ISSUE DATE
07-02-07
07-03-03

Figure 37. Package outline SOT994-1 (HWQFN24)

PCAL6416A

Product data sheet

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40 / 56

PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

D

SOT355-1

E

A

X

c
HE

y

v M A

Z

13

24

Q
A2
pin 1 index(A 3 )

A1

A

θ
Lp

1

L

12
bp

e

detail X

w M

0

2.5

5 mm

scale
DIMENSIONS (mm are the original dimensions)
UNIT

A
max.

A1

A2

A3

bp

c

D (1)

E (2)

e

HE

L

Lp

Q

v

w

y

Z (1)

θ

mm

1.1

0.15
0.05

0.95
0.80

0.25

0.30
0.19

0.2
0.1

7.9
7.7

4.5
4.3

0.65

6.6
6.2

1

0.75
0.50

0.4
0.3

0.2

0.13

0.1

0.5
0.2

8o
0o

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1

REFERENCES
IEC

JEDEC

JEITA

EUROPEAN
PROJECTION

ISSUE DATE
99-12-27
03-02-19

MO-153Figure 38. Package outline SOT355-1 (TSSOP24)

PCAL6416A

Product data sheet

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41 / 56

PCAL6416A

NXP Semiconductors
2

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
VFBGA24: plastic very thin fine-pitch ball grid array package;
24 balls; body 3 x 3 x 0.85 mm

B

D

SOT1199-1

Aball A1
index area

E

A2

A

A1

detail X

e1
e

C

C A B
C

Øv
Øw

b

y1 C

y

E
e
D
e2

C
B
A
ball A1
index area

1

2

3

4

X

5

0

1
scale

Dimensions
Unit
mm

2 mm

A

A1

A2

b

D

E

e

e1

e2

max 1.00 0.25 0.75 0.35
nom 0.85 0.20 0.65 0.30
min 0.75 0.15 0.60 0.25

3.1
3.0
2.9

3.1
3.0
2.9

0.5

2

2

v

w

y

0.15 0.05 0.08

y1
0.1
sot1199-1_po

Outlineversion
SOT1199-1

References
IEC

JEDEC

JEITA

Europeanprojection

Issue date
11-02-16
12-03-13---

Figure 39. Package outline SOT1199-1 (VFBGA24)

PCAL6416A

Product data sheet

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NXP Semiconductors
2

PCAL6416A

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

Figure 40. Package outline SOT1895-1 (X2QFN24)

PCAL6416A

Product data sheet

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NXP Semiconductors
2

PCAL6416A

Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

17 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth accountof soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.

17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attachedto Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering methodthat is ideal for all IC packages. Wave soldering is often preferred when through-holeand Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.

17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder comingfrom a standing wave of liquid solder. The wave soldering process is suitable for thefollowing:• Through-hole components• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation• The moisture sensitivity level of the packages• Package placement• Inspection and repair• Lead-free soldering versus SnPb soldering

17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

17.4 Reflow soldering
Key characteristics in reflow soldering are:
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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 41) than a SnPb process, thus
reducing the process window• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 38 and Table 39
Table 38. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)Package reflow temperature (°C)
Volume (mm³)
< 350

≥ 350

< 2.5

235

220

≥ 2.5

220

220

Table 39. Lead-free process (from J-STD-020D)
Package thickness (mm)Package reflow temperature (°C)
Volume (mm³)< 350

350 to 2000

> 2000

< 1.6

260

260

260

1.6 to 2.5

260

250

245

> 2.5

250

245

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 41.

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
temperature

maximum peak temperature= MSL limit, damage level

minimum peak temperature= minimum soldering temperaturepeak
temperaturetime
001aac844

MSL: Moisture Sensitivity Level
Figure 41. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365“Surface mount reflow soldering description”.

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

18 Soldering: PCB footprints
Footprint information for reflow soldering of VFBGA24 package

SOT1199-1

Hx
P

P

Hy

see detail X

solder land (SL)solder paste deposit (SP)solder land plus solder paste
SL/SP
occupied areaSRsolder resist (SR)detail X

Dimensions in mm
P

SL

SP

SR

Hx

Hy

0.50

0.30

0.30

0.40

3.30

3.30

Issue date

13-11-25
13-12-05

Remark:Recommend stencil thickness: 0.1 mm
sot1199-1_fr

Figure 42. PCB footprint for SOT1199-1 (VFBGA24); reflow soldering

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Footprint information for reflow soldering of TSSOP24 package

SOT355-1

Hx
Gx
P2(0.125)Hy

Gy(0.125)By

Ay

C

D2 (4x)

D1

P1
Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land
occupied area

DIMENSIONS in mm
P1

P2

Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650

0.750

7.200

4.500

1.350

0.400

0.600

8.200

5.300

8.600

7.450

sot355-1_fr

Figure 43. PCB footprint for SOT355-1 (TSSOP24); reflow soldering

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

Figure 44. PCB footprint for SOT994-1 (HWQFN24); reflow soldering (1 of 3)

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

Figure 45. PCB footprint for SOT994-1 (HWQFN24); reflow soldering (2 of 3)

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

Figure 46. PCB footprint for SOT994-1 (HWQFN24); reflow soldering (3 of 3)

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers
Footprint information for reflow soldering of X2QFN24 package

SOT1895-1

2.21
0.32

pin A10.4

0.25

0.25 0.32

0.4

2.21

0.08

0.15

0.15

occupied area

solder resist

solder lands

solder paste

0.08

Dimensions in mm
Issue date

16-08-12
16-09-05

sot1895-1_fr

Figure 47. PCB footprint for SOT1895-1 (X2QFN24); reflow soldering

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

19 Abbreviations
Table 40. Abbreviations
AcronymDescription

ESD

ElectroStatic Discharge

FET

Field-Effect Transistor

GPIO

General Purpose Input/Output

2

I C-busInter-Integrated Circuit bus

I/O

Input/Output

LEDLight-Emitting Diode

LSB

Least Significant Bit

MSB

Most Significant Bit

PCBPrinted-Circuit Board

POR

Power-On Reset

SMBus

System Management Bus

20 Revision history
Table 41. Revision history
Document ID

Release date

Data sheet status

Change notice

Supersedes

PCAL6416A v.7.1

20220830

Product data sheet-

PCAL6416A v.7

Modifications:• Updated SOT994-1 reflow soldering footprint information

PCAL6416A v.7

20210330

Product data sheet-

PCAL6416A v.6.2

PCAL6416A v.6.2

20170407

Product data sheet-

PCAL6416A v.6.1

PCAL6416A v.6.1

20161103

Product data sheet-

PCAL6416A v.6

PCAL6416A v.6

20141009

Product data sheet-

PCAL6416A v.5

PCAL6416A v.5

20131210

Product data sheet-

PCAL6416A v.4

PCAL6416A v.4

20130506

Product data sheet-

PCAL6416A v.3

PCAL6416A v.3

20121224

Product data sheet-

PCAL6416A v.2

PCAL6416A v.2

20121005

Product data sheet-

PCAL6416A v.1

PCAL6416A v.1

20120808

Product data sheet--

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21 Legal information
21.1 Data sheet status
Document status[1][2]

Product status[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for productdevelopment.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

21.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may resultin modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have noliability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet isintended for quick reference only and should not be relied upon to containdetailed and full information. For detailed and full information see therelevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with theshort data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors productis deemed to offer functions and qualities beyond those described in the
Product data sheet.

21.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited inaccordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of theirapplications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for thecustomer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use bycustomer’s third party customer(s). Customer is responsible for doing allnecessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.

All information provided in this document is subject to legal disclaimers.

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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Suitability for use in non-automotive qualified products — Unless
this data sheet expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testingor application requirements. NXP Semiconductors accepts no liability forinclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warrantyof the product for such automotive applications, use and specifications, and(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.

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Translations — A non-English (translated) version of a document, including
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated andEnglish versions.

21.4 Trademarks
Notice: All referenced brands, product names, service names, andtrademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.

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Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, andconfiguration registers

Contents
1
2
2.1
3
3.1
4
5
5.1
5.2
6
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5

General description ............................................ 1
Features and benefits .........................................2
Agile I/O features ...............................................3
Ordering information .......................................... 3
Ordering options ................................................ 3
Block diagram ..................................................... 4
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 5
Voltage translation .............................................. 6
Functional description ........................................7
Device address ..................................................7Interface definition ............................................. 7
Pointer register and command byte ...................8
Register descriptions ......................................... 9
Input port register pair (00h, 01h) ......................9
Output port register pair (02h, 03h) ................... 9
Polarity inversion register pair (04h, 05h) ........ 10
Configuration register pair (06h, 07h) .............. 10
Output drive strength register pairs (40h,41h, 42h, 43h) ................................................. 11
7.4.6
Input latch register pair (44h, 45h) ...................11
7.4.7
Pull-up/pull-down enable register pair (46h,47h) ..................................................................12
7.4.8
Pull-up/pull-down selection register pair
(48h, 49h) ........................................................ 13
7.4.9
Interrupt mask register pair (4Ah, 4Bh) ............13
7.4.10Interrupt status register pair (4Ch, 4Dh) .......... 14
7.4.11
Output port configuration register (4Fh) ...........14
7.5
I/O port .............................................................14
7.6
Power-on reset ................................................ 15
7.7
Reset input (RESET) ....................................... 15
7.8Interrupt output (INT) ....................................... 16
8
Bus transactions ............................................... 16
8.1
Write commands ..............................................16
8.2
Read commands ............................................. 18
9Application design-in information ................... 22
9.1
Minimizing IDD when the I/Os are used tocontrol LEDs .................................................... 22
9.2
Output drive strength control ........................... 23
9.3
Power-on reset requirements .......................... 24
9.4
Device current consumption with internal
pull-up and pull-down resistors ........................25
9.5
I2C-bus error recovery techniques .................. 26
10
Limiting values .................................................. 26
11
Recommended operating conditions .............. 27
12
Thermal characteristics ....................................27
13
Static characteristics ........................................ 28
13.1
Typical characteristics ......................................30
14
Dynamic characteristics ...................................34
15
Parameter measurement information ..............36
16
Package outline .................................................40
17
Soldering of SMD packages .............................44

17.1
17.2
17.3
17.4
18
19
20
21

Introduction to soldering .............................
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
Soldering: PCB footprints ................................ 47
Abbreviations .................................................... 53
Revision history ................................................ 53
Legal information .............................................. 54

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

© 2022 NXP B.V.

All rights reserved.

For more information, please visit: http://www.nxp.com
Date of release: 30 August 2022
Document identifier: PCAL6416A