ColdFire® V4 Core
The ColdFire V2 Core & Standard Product Platform (CFV2SPPC1)
combines the ColdFire V2 Core with industry-proven platform
peripherals to form a complete low-cost, low-power
microcontroller subsystem supported by a vast ecosystem ofdevelopment tools and runtime software. The CFV2SPPC1 isthe same ColdFire V2 processor core and platform/peripheral
IP implemented in NXP MCF5208 devices. With the CFV2SPPC1,
you get:• A fully synthesizable implementation of the popular ColdFire
architecture• Reliability—from processor and peripheral IP alreadydeployed in millions of embedded systems worldwide

Industry-Leading 32-Bit Performance
The ColdFire V4 Core achieves best-in-class 32-bit processor
performance through a combination of features including a9-stage pipeline with limited superscalar (dual-issue) instruction
execution. The 9-stage pipeline consists of a 4-stage Instruction
Fetch Pipeline (IFP) and 5-stage Operand Execution Pipeline(OEP) decoupled by a FIFO instruction buffer. The optional FPU
executes instructions in parallel with the OEP. Separate clocks
for the CPU and system bus enable the V4 ColdFire Core tooperate at a higher frequency than the rest of the system.

Example SoC Using
CFV2SPPC1.

Local RAM and cache, running at the CPU clock rate, further
maximize system efficiency by reducing the overall numberof system bus accesses, leaving more system bus bandwidthavailable for other system resources such as other anotherprocessor or DMA controller. The system bus is the industry
standard AMBA 2 AHB. The ColdFire V4 Core includes bothan AHB master port and an AHB slave port, which enables anexternal AHB master to access the ColdFire V4 local RAM, either
while the ColdFire V4 Core is running or while it is in low-power
STOP mode.

Applications
Processors based on the ColdFire architecture can be found inover 500 million devices worldwide, powering systems ranging
from cameras and printers to robotics and factory automation.
The superior performance of the ColdFire V4 Core makes itsuitable for the most demanding applications such as high-end
home entertainment, network storage, telecommunications,and networked gaming devices. Tightly integrated DIV andEMAC units support DSP-like algorithms for applications suchas VoIP. For applications requiring floating-point calculations,the optional FPU provides IEEE-754 compliant floating-point
support, operating on 64-bit, double-precision floating-point
data and supporting single precision and signed-integer input
operands.

Features• 32-bit address and data paths• Variable-length RISC architecture for maximum code density• ColdFire ISA Revision C plus dedicated instructions for
integrated arithmetic hardware (DIV, EMAC, and FPU)
• Branch acceleration for minimal change-of-flow execution
time

The MMU provides virtual-to-physical address translation
using separate, software-managed instruction and datatranslation look aside buffers (TLBs), which are implemented
as flip-flops within the ColdFire V4 Core. The MMU supports
software-configurable memory page sizes of 4 KB, 8 KB, 1 MB,
and 16 MB. The MMU is disabled upon exit from reset and must
be enabled by software before it can be used.

• Big-endian data organization• Up to 64 KB of local RAM with single-cycle access

Development Support• Separate instruction/data caches (up to 32 KB each)

The ColdFire architecture, including the ColdFire V2 Core, issupported by a vast assortment of development systems/tools
and run-time software including libraries, stacks, drivers, andoperating systems from providers such as NXP, Green Hills
Software, Wind River Systems, and many more. A free versionof the GNU compiler supporting ColdFire V2 targets is alsoavailable from www.gnu.org.

• MMU with variable page sizes (up to 16 MB)• AMBA 2 AHB system bus with master and slave ports• Master port for ColdFire V4 Core accesses• Slave port for external AHB master access to ColdFire V4local RAM• Bootable from local RAM or system (AHB) memory• STOP mode for low-power operation

NXP offers development boards, software, and CodeWarrior
Development Tools (including a free version. In addition, there
are several operating systems supporting the ColdFire V2architecture, including uClinux and several RTOS’s, such as theMQX RTOS from Embedded Access, Inc.

• ColdFire Debug Architecture Revision D+• Background Debug Mode (BDM)• Real-Time Trace (RTT)• Real-Time Debug (RTD)• On-chip, 128-entry trace buffer for low-cost trace overBDM• Fully synchronous, synthesizable, scannable design

Deliverables

Memory Architecture• Scripts for simulation and synthesis with commonly-usedEDA tools• Verilog source code
• Integration testbench and tests• Documentation

The ColdFire V4 Core supports up to 4 GB of physical memory,
including system memory accessed through the AMBA 2 AHB
system bus and up to 64 KB of local RAM connected directly
the processor high-speed local bus for single-cycle access.
The size of the local RAM is configurable (specified by input pinvalue) and may be 0 (no local RAM), 4, 8, 16, 32, or 64 KB.
The ColdFire V4 Core supports separate instruction and datacaches, also connected to the processor high-speed bus withsingle-cycle access. The caches are independently sized,
non-blocking, four-way set-associative with 16-byte line sizes.
Each cache can be configured to be 0, 2, 4, 8, 16, or 32 KB (alsospecified by input pin value).

For more information, please contact us at ip@silvaco.com.

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