Early power and performance
optimization of algorithm
implementation on ARM processors
Francesco Regazzoni
ALaRI Institute, University of Lugano (CH)www.alari.chOutlineMotivation of the work.
Overview of used tool: Mirabilis VisualSim.
Case study: AES algorithm.
First system.
Second system.
Conclusions.

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Motivations
 Achieving the required throughput at the lowest
power consumption is a primary concern in thearchitecture of mobile handheld devices.
 The selection of the processor and the architectureof the full system must be determined before
committing to hardware and software.
 A preliminary investigation of the performance vs.
power trade-off can be performed leveraging on
macro-architecture exploration.
 Using Mirabilis VisualSim a model of the systemthat provide such accuracy can be constructed in afew hours.
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VisualSim Overview 1/4
 VisualSim is a graphical and platform-independentarchitectural analysis and exploration software tool.
 VisualSim can be used in any application that requires thedesign of hardware and software elements.
 All of the system design aspects are addressed by VisualSim
using the building blocks.
 All of the building blocks, simulation platforms, analysis anddebugging required to construct a system are provide within asingle framework.
 Thus models in all these analysis can be constructed quickly
and easily.
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VisualSim Overview 2/4
 Key features:¾ Design with multiple abstraction levels.
¾ Integrated multi-simulation engines and JIT data types.
¾ Extensive libraries of parameterized models.
¾ Publish to the Web for communication and remoteexecution.
¾ Graphical entry and hierarchical modeling.
¾ Robust visualization and analysis capabilities.
¾ Import Java/C/C++ and link to Excel & MatLab.
¾ Automatic error checking between SmartBlocks models.
¾ Enable assertions for system-coverage.
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VisualSim Overview 3/4
 Applications¾ Design new and custom hardware and softwarearchitectures.
¾ Design sub-systems such as CPU, memory controllers andDMA.
¾ Sizing CPU speed, Bus width, Cache, Memory & Pipeline
stages.
¾ Architect embedded software.
¾ RTOS consideration.
¾ Design of new wireless and communication protocols.

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VisualSim Overview 4/4
 Analysis¾ Architecture utilization.
¾ Application response time.
¾ Functional correctness of algorithms.
¾ Buffer requirements.
¾ Implementation and design constraints
generation.
¾ Power

www.alari.chCase Study 1/3AES (Advanced Encryption Algorithm, FIPS 197):
 Block cipher: block size 128.
 Key size: 128; 192; 256.
 Round operations:¾ Shift row.
¾ Mix Column.
¾ Non linear transformation (SBOX).
¾ Add Round key.

 The Number of rounds depends on the key length.
www.alari.chCase Study 2/3
The algorithm runs on ARM processors indifferent systems.
Different key length are tested.
Measurements of:¾ Latency.
¾ Power consumed by the processor

The trade off is analyzed.

www.alari.chCase Study 3/3
The AES code is an open source version
taken from the web.
The code was annotate and compiled withthe gcc compiler to obtain the execution
trace.
The trace was used as input for the model of
the CPU inside Mirabilis VisualSim.

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AES source code from http://freshmeat.net/~devine10/

System one (Full system details)
Dual processor ARM7TDMI.
AES tasks are loaded on the two CPU.
Parameters checked:¾ System utilization.
¾ Processor latency.
¾ Processor instant power.
¾ Battery power.

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System one (Full system in VisualSim)

www.alari.chsource: www.arm.com

System one (ARM7TDMI in VisualSim)

www.alari.chsource: www.arm.com

System one (Processors Utilization)www.alari.ch

System one (battery and instant power)

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System two (Full system details)
Single processor ARM-8Cortex.
All AES tasks are loaded on the same CPU.
Parameters checked:¾ System utilization.
¾ Processor latency.
¾ Processor instant power.
¾ Battery power.

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System two (Full system in VisualSim)

www.alari.chsource: www.arm.com

System two (ARM8-Cortex in VisualSim)

www.alari.chsource: www.arm.com

System two (Processor Utilization)www.alari.ch

System two (battery and instant power)

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System Comparison
ARM8-Cortex/ARM7TDMI power
consumption:¾ 9.5

ARM8-Cortex/ARM7TDMI speed:¾2

ARM8-Cortex is fasterTwo ARM7TDMI consume less power

www.alari.chConclusionsPerformance/Power Trade off is of crucial
importance in embedded systems design.
The presented case study demonstrates thatusing Mirabilis VisualSim was possible to:¾ Model the full system in few hours (the fullexperiment was realized in less then 10 hours).
¾ Analyze the latency and the power consumed by
the full system ad its main components.
¾ Explore very quickly different implementationand platform.
www.alari.chQuestions?

www.alari.chThank you for attention.
(regazzoni@alari.ch)Please fell free to come to Mirabilis Design (boothF-51) for a demo
www.alari.ch