Fault Tolerant Operation of Motor Drive Fed byDual Inverter Focusing on DC-Bus Battery Failure
Yoshiaki Oto
Environment and Energy Systems
Shizuoka University
Shizuoka, Japanohto.yoshiaki.15@shizuoka.ac.jp

Toshihiko Noguchi
Environment and Energy Systems
Shizuoka University
Shizuoka, Japan
noguchi.toshihiko@shizuoka.ac.jp

Abstract— A fault tolerant operation of the DC-bus battery
in the dual inverter motor drive feeding an open-end winding
motor is described in this paper. The dual inverter motor drive
studied in this paper has a battery and a capacitor in parallel
across the DC-bus of each inverter, and it is assumed that thebattery across the DC-bus of one of the inverters is separated.
The dual inverter motor drive has the redundancy of theswitching state, which means that the particular voltage vectors
can be generated with the several redundant states. In the fault
tolerant operation, the failed inverter is operated with thecapacitor instead of the failed battery, and the capacitor voltage
is controlled at constant value by using the redundant switchingstate with a space vector modulation (SVM). In particular, thecapacitor voltage of the failed inverter is required to be
regulated at a half of the battery voltage of the normal condition
inverter, in order to utilize the redundancy of the switchingstate. On the other hand, in the normal condition, the battery
voltages of both inverters are same to expand the operation
region of the dual inverter system, because the system cangenerate the voltage vector to the motor by adding the output
voltages of two inverters. Therefore, it is necessary to discharge
the capacitor voltage smoothly up to a half of the battery voltageof the normal condition inverter, immediately after the failed
battery is separated. In this paper, the switching over techniquesfrom the normal condition to the fault tolerant operation of theDC-bus battery with the SVM in the dual inverter motor drive
are proposed. The proposed techniques are examined throughseveral computer simulations and experimental tests.
Keywords—fault tolerant operation, space vector modulation,
dual inverter motor drive, open-end winding motor, capacitor
voltage control

I. INTRODUCTION
Recently, a mileage improvement and autopilot
technologies of hybrid and electric vehicles are focused on.
However, the current system drives the permanent magnet(PM) motor with a 2-level inverter, whose DC-bus voltage isboosted with a bidirectional chopper. The improvement of theefficiency in the current system is difficult because the large
current flows into the voltage boost chopper, and the line toline voltage of the motor is a 2-level voltage waveform. And,
it is also difficult to achieve a fault tolerant operation, because
the current system cannot keep driving the motor if some
failure is occurred in either the inverter or the chopper.
Therefore, a dual inverter motor drive feeding an open-end
winding motor with two inverters is focused on [1]-[10]. The
dual inverter motor drive is expected to improve the efficiencyof the system, because the system is not required any voltage
boost converter and can generate a multilevel voltage
waveforms across the motor windings. And, the dual inverter
motor drive can achieve fault tolerant operations. So far, thefault tolerant operation of the switching device in the dualThis work was supported by the New Energy and Industrial
Technology Development Organization (NEDO) Grant-in-Aid for
Scientific Research from the National Government and Ministry of
Economy, Trade and Industry, Japan.
978-1-7281-3398-0/19/$31.00 ©2019 IEEE

inverter motor drive has been studied [11]-[13]. However, thefault tolerant operation, which assumes that the DC-bus
battery of one of the inverters is failed, has not been studied.
Therefore, the fault tolerant operations of the DC-bus battery
are focused on and are discussed in this paper.
The dual inverter system studied in this paper has a battery
and a capacitor in parallel across the DC-bus of each inverter.
In this paper, it is assumed that the DC-bus battery of one of
the inverters is in failure and is separated. In the fault tolerant
operation of the DC-bus battery, the failed inverter is operated
with the capacitor instead of the separated battery. The dual
inverter system has a redundancy in the switching state, whichmeans that the particular voltage vectors can be generated withthe several redundant switching states. In this time, thecapacitor voltage of the failed inverter must be controlled atconstant value. However, the capacitor voltage is required tobe regulated at a half of the battery of the normal condition
inverter to utilize the capacitor charging/discharging modes
among the redundant switching state. In order to select theswitching state which charges/discharges the capacitor
appropriately in the redundant switching states, a space vector
modulation (SVM) is employed to operate the dual inverter
motor drive in this paper. On the other hand, the DC-bus
battery voltages of the dual inverter system are same value inthe normal condition, in order to expand the operation region
by increasing the amplitude of the output voltage which is
generated by adding the output voltages of the two inverters.
Therefore, it is necessary to discharge the capacitor voltage
smoothly up to a half of the battery voltage of the normal
condition inverter, immediately after some failure is detectedin the battery and the failed battery is separated. In this paper,
the SVM techniques to switch over the dual inverter systemfrom the normal condition to the fault tolerant operation of theDC-bus battery are proposed. The proposed techniques are
Capacitor

Capacitor

Open-EndWinding Motor

Battery

Battery

150 V

150 V

INV1 (u1, v1, w1)(u2, v2, w2)’INV2(a) Normal condition.
Capacitor

Open-EndWinding Motor

Capacitor
75±5 V

Battery
150 V

INV1 (u1, v1, w1)(u2, v2, w2)’INV2(b) Fault tolerant circuit of DC-bus battery of INV2.
Fig. 1. Circuit configurations of dual inverter motor drive.

examined through several computer simulations andexperimental tests.
II. DUAL INVERTER MOTOR DRIVE
A. Circuit Configurations
The circuit configurations of the dual inverter motor drive
studied in this paper are shown in Fig. 1, where the left-handside and the right-hand side inverters are called INV1 and
INV2, respectively. Each leg of both inverters iscomplementary operated, and the switching state of the dual
inverter system is expressed as (u1, v1, w1) (u2, v2, w2)’,
where the switching state “1” means that the upper arm isturned on and “0” means the opposite. The both inverters havea battery and a capacitor across each DC-bus, whose voltages
are same in the normal condition because the dual inverter
system can expand the operation region by adding the output
voltages of two inverters. The dual inverter system has theredundancy in the switching state, which can generateparticular voltage vectors with the several redundant states.
The redundancy can achieve the fault tolerant operation of theDC-bus battery.
B. Fault Tolerant Operation of DC-Bus Battery
In this paper, it is assumed that some failure is occurred in
the DC-bus battery of the INV2 and the failed battery is
separated with the relay across the DC-bus of the INV2. In thefault tolerant operation, the INV2 is operated with thecapacitor instead of the failed battery, and the capacitor
voltage is regulated at a half of the battery voltage of the INV1
as shown in Fig. 1 (b). The relationship between the switchingstates and the capacitor charging/discharging modes in the
dual inverter motor drive enlarged from 0 to 60 degree isshown in Fig. 2. In case of the 1:1 DC-bus voltage ratio, either
the charging or the discharging mode can be used in the
redundant switching states. On the other hand, in case of the
1:0.5 DC-bus voltage ratio, both of the charging and thedischarging modes can be used redundantly. Therefore, the1:0.5 DC-bus voltage ratio is employed in this paper.
However, the operation region of the dual inverter system of
the 1:0.5 DC-bus voltage ratio is limited to m < 0.5, because
the longest voltage vectors which configure the most outerhexagon do not have the redundancy, and the voltage vectors
cannot be achieved the capacitor voltage control. That is why,
the switching over techniques of the dual inverter motor drivefrom the normal condition to the fault tolerant operation of theDC-bus battery in case of m < 0.5 are discussed in this paper.
C. Space Vector Modulation
The dual inverter system has the redundancy in theswitching state, which can generate the particular voltage withthe several redundant states. Therefore, it is required to selectthe appropriate switching state among the redundant states,
according to some requirements, in order to operate the dual
inverter system. The SVM is employed to operate the dual
inverter motor drive in this paper, because the SVM can selectthe switching state flexibly which charges/discharges thecapacitor voltage appropriately among the several redundantstates. Fig. 3 shows the principle of generating the command
voltage vector v* with the SVM, enlarged from 0 to 60 degree.
An inverter can only discrete voltage vectors like V0 and V60
in Fig. 3. Therefore, it is necessarily to synthesize the available
discrete voltage vectors at appropriate ratio, in order togenerate the voltage vector with an arbitrary amplitude and an
arbitrary phase in the SVM. In this time, the output time
durations of each voltage vector in one SVM period are(000)(001)’(-)(111)(001)’(-)(010)(011)’(-)(100)(101)’(-)(110)(000)’(0)(110)(111)’(0)(000)(000)’(0)(000)(111)’(0)(111)(000)’(0)(111)(111)’(0)(001)(001)’(0)(010)(010)’(0)(100)(100)’(0)(011)(011)’(0)(101)(101)’(0)(110)(110)’(0)(110)(001)’(-)(100)(001)’(-)(110)(011)’(-)

m = 0.5(000)(011)’(-)(111)(011)’(-)(101)(001)’(-)(110)(010)’(-)(100)(000)’(0)(100)(111)’(0)(110)(000)’(0) (110)(001)’(-)(110)(111)’(0)(110)(011)’(-)(000)(001)’(-)(100)(101)’(0)(111)(001)’(-)(110)(010)’(0)(110)(110)’(+)(000)(000)’(0)(100)(001)’(-)(000)(111)’(0)(111)(000)’(0)m = 0.25 m = 0.5 m = 0.75(111)(111)’(0)(100)(011)’(-)(000)(011)’(-) (100)(000)’(0)(111)(011)’(-) (100)(111)’(0)(100)(100)’(+)(+): Charging Mode(‐): Discharging Mode(0): Holding Modem = 1.0(100)(011)’(-)(a) 1:1 DC-bus voltage ratio.

(b) 1:0.5 DC-bus voltage ratio.

Fig. 2. Redundancy of switching state in dual inverter motor drive enlarged
from 0 to 60 degree.

V60
V60×T60/Tsv*

Vz
V0×T0/Ts

V0

Fig. 3. Principle of SVM.
SVM 1 Period
V0V0in(000)(011)’(-)(100)(000)’(0)(111)(011)’(-)(100)(111)’(0)V30(110)(010)’(-)(100)(101)’(+)(100)(100)’(+)

Hold

Discharge
Capacitor Voltage Command

V0in(000)(011)’(-)(100)(100)’(+)

Charge・・・(111)(011)’(-)

Discharge(+): Charging Mode(-): Discharging Mode(0): Holding Mode

Capacitor Voltage

Fig. 4. Capacitor voltage control with SVM.

required to be calculated. The components of the voltage
vectors V0 and V60 to synthesize the command voltage vector
v* are calculated as shown in Fig. 3, where Ts indicates the
SVM control period, and T0 and T60 indicates the output time
durations of the voltage vectors V0 and V60 during one SVM
period, respectively. In the SVM, the three voltage vectors
surrounding the region, where the command voltage vector v*
presents, are utilized to synthesize the command voltage
vector. In case of Fig. 3, for example, the three voltage vectors
V0, V60, and Vz are used for the SVM.
D. Capacitor Voltage Control
In the fault tolerant operation of the DC-bus battery, it isnecessarily both to control the capacitor voltage of the failed
inverter constantly and to generate the multilevel voltage
waveforms across the motor windings, simultaneously. The
capacitor voltage control is achieved with the redundancy ofthe switching state of the dual inverter motor drive with the
1:0.5 DC-bus voltage ratio. In this time, the SVM is required
to select the appropriate switching state whichcharges/discharges the capacitor appropriately among theseveral redundant states. As shown in Fig. 4, when the voltage
vector V0in is generated, the capacitor charging mode isselected if the capacitor voltage is lower than the command
value, for example. In this way, the simultaneous control of
the capacitor voltage and the multilevel voltage waveformgeneration can be achieved. However, the capacitor

Vb
|v*|

Vb

Vz

Vb

Vz
Va
Vdc2 = Vdc1

Vb
Vz

Vz
Va

Va
Vdc2 = Vdc1/2

Va(a) 0 < m ≤ 0.25.

Vb,Vb’,Vc’|v*|
Vz
Va,Va’,Vc
Vdc2 = Vdc1

Vb’

Vb’
Vc’
Vb

Vb

Vb’

Vc’

Vb

Vc

Vc

Va Va’Va Va’

Vc,Vc’Va Va’
Vdc2 = Vdc1/2(b) 0.25 < m ≤ 0.5.
Fig. 5. Proposed switching over technique for fault tolerant operation of DC-bus battery.

charging/discharging mode of each switching state may bechanged, depended on the instantaneous motor power factor[14]. Therefore, the selection of the appropriate switchingstate among the redundant state must be implemented,
considering the instantaneous motor power factor.
III. PROPOSED SWITCHING OVER TECHNIQUE FOR FAULTTOLERANT OPERATION
The dual inverter system in the normal condition is
operated with the 1:1 DC-bus voltage ratio, in order to expand
the operation region of the system. On the other hand, the fault
tolerant operation of the DC-bus battery is required to regulate
the capacitor voltage of the failed inverter at a half of thebattery voltage of the normal condition inverter. Therefore,
the SVM techniques to discharge the capacitor voltage of thefailed inverter smoothly up to a half of the battery voltage ofthe normal condition inverter, immediately after the failed
battery is separated, while generating the command voltage
vector across the motor windings at the same time, areproposed. The proposed SVM techniques to switch over thedual inverter motor drive from the normal condition to thefault tolerant operation assume two cases of the modulationindex, which is 0 < m ≤ 0.25 and 0.25 < m ≤ 0.5 as shown in
Fig. 5 (a) and (b), respectively.
The dual inverter motor drive has particular switchingstates to generate the voltage vectors Va and Vb in Fig. 5 (a),which utilize only the capacitor voltage of the INV2 togenerate the voltage vectors, and simultaneously candischarge the capacitor voltage. In case of 0 < m ≤ 0.25,
therefore, the proposed SVM technique is implemented withthe voltage vectors Va, Vb, and the zero voltage vector Vz,
which has the zero amplitude and keeps the capacitor voltage
by disconnecting the capacitor from the dual inverter circuit.
However, the switching state to generate the voltage vector Va
or Vb must be selected to discharge the capacitor of the failed
inverter and to utilize only the capacitor voltage to generate
the voltage vector among the redundant states with the SVM.
In other words, the selected switching state can achieve bothto discharge the capacitor of the failed inverter and to generate
the voltage vector Va or Vb with the amplitude which isvariable depending on only the capacitor voltage. In this way,
the SVM can switch over the dual inverter system from thenormal condition to the fault tolerant operation of the DC-bus
battery, while outputting the command voltage vector to themotor, according to the capacitor voltage of the INV2discharged up to a half of the battery voltage of the INV1 asshown in Fig. 5 (a).
On the other hand, in case of 0.25 < m ≤ 0.5, the voltage
vectors Va’, Vb’, Vc, and Vc’ are used for the SVM in
addition to the voltage vectors Va and Vb whose amplitudes
depend on only the capacitor voltage of the INV2. The voltage
vectors Va’ and Vb’ are generated with only the voltage of theINV1, that is, the amplitudes of the Va’ and Vb’ do not dependon the capacitor voltage of the INV2. The amplitudes of thevoltage vectors Vc and Vc’ are variable depended on thebattery voltage of the INV1 and the capacitor voltage of theINV2 as shown in Fig. 5 (b), because the voltage vectors are
generated by adding the output voltage vectors of the INV1
and the INV2. At first, the SVM to switch over the dual
inverter system to the fault tolerant operation in case of 0.25
< m ≤ 0.5 is performed in the same way as 0 < m ≤ 0.25, until
the straight line between the voltage vectors Va and Vb
inscribes the circle locus of the rotating command voltage
vector. Subsequently, the SVM is performed on the basis of
the three triangle regions. Every triangle region is surroundedwith the three voltage vectors, that is, (Va, Va’, Vc/Vc’), (Va’,
Vb’, Vc/Vc’), and (Vb, Vb’, Vc/Vc’). In this time, “Vc/Vc’”means that either the voltage vector Vc or Vc’ is selected
appropriately, considering the instantaneous motor power
factor, and is used for the SVM because either the voltage
vector Vc or Vc’ is the capacitor charging mode. In this way,
the proposed SVM techniques achieve to switch over the dual
inverter system smoothly from the normal condition to thefault tolerant operation of the DC-bus battery in case of m <0.5, while generating the command voltage vector to themotor at the same time.

IV. COMPUTER SIMULATIONS

Motor Current (A) U-Phase Voltage Capacitor Voltage
Vcap (V)Vu (V)

Fault Signal Motor Rotation Speed(r/min)A. Computer Simulation Conditions
Computer simulations have been conducted to examine
the proposed SVM techniques to switch over the dual inverter
system from the normal condition to the fault tolerant
operation smoothly. The control block diagram is indicated inFig. 6, where a surface permanent magnet (SPM) motor with
an open-end windings is controlled with a field-oriented
control (vector control) algorithm, so has a speed control loop
and a current control loop in the controller. The instantaneous
motor power factor is calculated from the phase difference
between the command voltage vector and the motor line
current vector on the synchronously rotating (d-q) reference
frame, which is utilized to select the appropriate switchingstate among the redundant states, as well as the feedback valueof the capacitor voltage of the INV2. A relay to simulate theseparation of the battery of the INV2 is inserted between thebattery and the capacitor across the DC-bus of the INV2. The
dual inverter system in the normal condition starts to transfer
the fault tolerant operation with the proposed SVM techniques
after the separation of the battery of the INV2 is detected withthe fault signal in Fig. 6. In other words, the capacitor voltageof the INV2 is discharged from 150 V to approximately 75 V
with the proposed SVM techniques after the DC-bus battery
separation is occurred in the INV2. Then, the capacitor voltage
is controlled within 75±5 V with the redundant switchingstates in the fault tolerant operation. However, the simulations
are conducted under the ideal condition, that is, there is nodead time.

i d*

ωm*

PI

＋
－

T*

1/PΨ

i q* ＋ －
＋

PI
PI

vd*

dq
↓
αβ

vq*

－

tan−1
tan−1

swu1

vα*

swv1

v*β

sww1

θ v*
θi*
Vcap

S
V
M

Fault
Signal

ωm

iu
INV1

iv

PM

Motor
swu2
swv2
sww2 INV2

1
s

id

αβ
↓
dq

iq

iα
iβ

uvw
↓
αβ

Fig. 6. Control block diagram.
TABLE I.

COMPUTER SIMULATION CONDITIONS

Switching frequency

10 kHzBattery voltages in normal condition

150 V

Capacitor voltage commandin fault tolerant operation

75±5 V

Capacitance of DC-bus capacitor

1330 µF

Dead time

0 µs
Number of poles

4

Number of flux linkage
Motorparameters0.174 Wb

Moment of inertia

0.00137 kgm2

Damping coefficient

0.01 N/rad/s

Phase resistance

1.1 Ω

Phase inductance

5 mH

1400
1200
1000
800
600
400
200
0
2

wm_rpmwm_rpm_ref

1
0
180
160
140
120
100
80
60
150
100
50
0
-50
-100
-150
4
2
0
iu
iv
iw

-2
-4
0

100

200

300

400

500

Time (ms)Motor Current (A)U-Phase Voltage Capacitor Voltage
Vcap (V)Vu (V)

Fault Signal Motor Rotation Speed(r/min)(a) m = 0.2 (600 r/min).
1400
1200
1000
800
600
400
200
0
2

wm_rpmwm_rpm_ref

1
0
180
160
140
120
100
80
60
150
100
50
0
-50
-100
-150
10
5
0
iu
iv
iw

-5
-10
0

50

100

150
Time (ms)(b) m = 0.4 (1200 r/min).
Fig. 7. Computer simulation results.

200

250

iw

B. Computer Simulation Results
The simulation results in case of the modulation index m= 0.2 and m = 0.4 are shown in Fig. 7 (a) and (b), respectively.
In the figures, the motor rotating speed, the fault signal, thecapacitor voltage, the U-phase voltage, and the motor line
currents are indicated. In the dual inverter motor drive in thenormal condition where both inverters are operated with thebattery with 150 V, the 5-level voltage waveforms are
generated between the motor winding terminals of each phaseat m = 0.2 and m = 0.4. On the other hand, the dual inverter
motor drive in the fault tolerant operation, in case of 0 < m ≤0.25, can generate the 5-level voltage waveforms with a half
amplitude of the normal condition as shown in Fig. 7 (a), thatis, with a closer amplitude to the command voltage vector than
the normal condition. Therefore, it is expected to reduce theharmonic component rate of the output voltage waveforms in
the fault tolerant operation, which results in the improvementof the total harmonic distortion (THD). And, the dual inverter
motor drive in the fault tolerant operation, in case of 0.25 < m≤ 0.5, can generate the 9-level voltage waveforms across the
motor windings as shown in Fig. 7 (b), which also results in
the improvement of the THD. In addition, at the both cases,
the dual inverter motor drive achieves to transient from thenormal condition to the fault tolerant operation smoothly withthe proposed SVM techniques, while generating the constantcommand voltage vector to the motor, as can be seen from thefigures.

Fig. 8. Experimental setup of dual inverter motor drive.
PARAMETERS OF TEST MOTORTABLE II.

Number of poles

4

Rated power

1000 W

Rated speed

2000 r/min

Rated torque4.78 Nm

Rated current

3.7 A

Armature resistance

1.1 Ω

Number of flux linkage

0.174 Wb

d-axis inductance

11.0 mH

q-axis inductance

25.0 mH
Switching Signals

Output Voltage Vector
Time Duration
6 bit

V. EXPERIMENAL TESTSDSP

Motor Current(A)

U-Phase Voltage
Vu (V)

Capacitor Voltage
Vcap (V)A. Experimental Setup
The experimental setup of the dual inverter motor drive
has been conducted to examine the proposed SVM techniques
180
160
140
120
100
80
60
200
150
100
50
0
-50
-100
-150
-200
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.50

Gate
Driver1

INV1
6 bit

FPGA
32 bitTI
TMS320C6657

XilinxXS6SLX452FGG676C

6 bit

Gate
Driver2

INV2
6 bit

Fig. 9. Block diagram of controller.

iu
iv
iw
100

200

300

400

500

Time (ms)Motor Current(A)

U-Phase Voltage
Vu (V)

Capacitor Voltage
Vcap (V)(a) m = 0.2 (400 r/min).
180
160
140
120
100
80
60
200
150
100
50
0
-50
-100
-150
-200
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.50

iu
iv
iw
100

200

300
Time (ms)(b) m = 0.4 (800 r/min).
Fig. 10. Experimental test results.

400

500

to switch over the system from the normal condition to thefault tolerant operation as shown in Fig. 8, where the 1-kW
open-end winding interior permanent magnet (IPM) motor iscontrolled with a vector control algorithm and a maximum
torque per ampere (MTPA) control method by the two 5-kVA
inverters. The control block diagram and the experimental
conditions are similar to the computer simulations in Fig. 6
and Table I, but the motor rotating speed is regulated by theload servo motor directly connected to the open-end winding
test motor, and the dead time is set to 4 µs. The SVM to control
the dual inverter motor drive is implemented in the digital
signal processor (DSP) and the field programmable gate array(FPGA) as shown in Fig. 9. The detections of the region where
the command voltage vector presents, the selection of thevoltage vectors which are utilized for the SVM, and thecalculations of the time durations are implemented in the DSP.
And, the FPGA outputs the switching signals to the gate
drivers of both inverters with the high resolution of 100 MHz
according to the calculation results of the DSP .
B. Experimental Test Results
The experimental test results of the modulation index m =0.2 and m = 0.4 are shown in Fig. 10 (a) and (b), respectively.
In the figures, the capacitor voltage, the U-phase voltage, andthe motor line current are indicated. The similar operation
characteristics to the computer simulation results have beenverified in the experimental test results. However, the voltage
waveforms of the dual inverter motor drive in the fault tolerant
operation have a lot of error voltage pulses. The error voltages
are generated during the dead time of the transient between theparticular switching states, where the switching devices in thesame phase of both inverters are synchronously turned on/off,and the several switching devices in one inverter aresynchronously turned on/off. Therefore, the SVM techniques
to reduce the error voltages are introduced [15][16]. The SVM
implemented in this paper employs the introduced techniques.
All in all, the proposed SVM techniques to switch over thedual inverter drive from the normal condition to the fault
tolerant operation smoothly have been verified to work well.
VI. CONCLUSION
In this paper, the fault tolerant operation of the DC-bus
battery in case of m < 0.5 in the dual inverter motor drive isdiscussed. In the fault tolerant operation, the failed inverter isoperated with the capacitor instead of the failed battery.
Therefore, it is required to control the capacitor voltage atconstant value, in particular, the redundancy of the switchingstate can be utilized by regulating the capacitor voltage at ahalf of the battery voltage of the normal condition inverter.
Therefore, it is necessary to discharge the capacitor voltage up
to a half of the battery voltage of the normal condition inverter,
immediately after some failure is detected in the battery andthe failed battery is separated. In this paper, the SVM
techniques to switch over the dual inverter motor drive fromthe normal condition to the fault tolerant operation smoothly
are proposed. And, the validity of the proposed SVM
techniques have been verified through the computer
simulations and the experimental tests. The consideration of
the fault tolerant operation in case of m > 0.5 in the dual
inverter motor drive is one of the future works of the authors.

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