High-Speed Switching Operation of MOSFETs
Using Auxiliary Circuit Shorting Load
- Applications to Chopper and Half-Bridge Inverter and Their Operation Characteristics -Toshihiko Noguchi

Tomohiro Mizuno

Department of Electrical and Electronic Engineering,
Faculty of Engineering,
Shizuoka University
3-5-1 Johoku, Naka-Ku, Hamamatsu,
Shizuoka 432-8561, Japan
ttnogut@ipc.shizuoka.ac.jp

Department of Electrical and Electronic Engineering,
Graduate School of Engineering,
Shizuoka University
3-5-1 Johoku, Naka-Ku, Hamamatsu,
Shizuoka 432-8561, Japanf0130155@ipc.shizuoka.ac.jp

Abstract— This paper describes a high-speed switching techniqueof power MOSFETs applied to a chopper and a half-bridge
inverter. The switching time must be shortened to operate power
converters using the power MOSFETs at high-frequency, butparasitic output capacitance prevents the MOSFETs fromturning off fast. In general, the turn-off time becomes longer as aload current is reduced because the reduced drain current takes
a long time to charge the parasitic output capacitance. In thepaper, a set of auxiliary switches and diodes in parallel with aload is proposed to reduce the turn-off time effectively. Thisadditional auxiliary circuit makes a high-frequency drive of thepower MOSFETs and switching-loss reduction of the power
converter possible. It has been confirmed through experimental
tests that the operational frequency range of the power converter
expands to MHz-order and that the power conversion efficiency
is effectively improved in a low-load range by employing the
proposed technique.
Keywords-component; MOSFET, high-speed switching, turnoff, auxiliary circuit, chopper, half-bridge inverter

I.

INTRODUCTION

In recent years, great attention has been paid on nextgeneration semiconductor devices such as SiC (Silicon
Carbide) based MOSFETs and diodes because they are very
promissing and attractive as power switching devices forvarious kinds of near future power converters. The SiC based
devices have the following remarkable features, which
completely surpasses conventional Si (Silicon) based
semiconductor devices:(1) approximately ten times higher voltage ratings than the
Si based semiconductor devices;(2) 105 V/μs-class switching speed;(3) as low on-resistance as 1/200 to 1/500 of theThis work has been supported by Grant-in-Aid for Scientific Research (B)23360122 from Ministry of Education, Culture, Sports, Science andTechnology, Japan and Joint Research with DENSO Laboratories, DENSO
Corporation, Japan since 2011.

conventional MOSFETs; and(4) over 300 °C junction temparature.
These very attractive features make it possible to improve
power density as well as efficiency of the power converters
dramatically. However, there still remain many problems to besolved from the veiwpoint of practical implimentation of such
SiC based MOSFETs. One of the problems is to achieve an
extremely high-speed operation without sacrificing theefficiency of the power converter. In general, parasitic
capacitors of the MOSFET disturb high-speed switching
because charging and discharging the parasitic capacitors maketurn-on time and turn-off time longer. To make matters worse,
as an on-resistance of the MOSFET becomes lower and thedrain current becomes higher, the MOSFET tends to increase
its parasitic capacitances because thickness and area of thedevice chip get thinner and larger. Similarly in the case of SiC
power devices, the parasitic capacitances of the SiC based
MOSFET are a great concern, which fades away the above
excellent features.
It is necessary to reduce both of the turn-on time and theturn-off time to achieve high-speed switching of the MOSFET.
Particuraly the turn-on time can be adjusted by controllingelectrical charge to the parasitic input capacitance.
Conventional approaches take some simple techniques to speed
up the turn-on time, i.e., reducing the gate resistance of the
MOSFET, and connecting a speed-up capacitor in parallel withthe gate resistance. Recently another new gate drive circuit is
proposed, which introduces inductive impulse superposition
technique to drive the high-speed MOSFET. The superposed
impulse gate current allows exteremely fast charge to theparasitic input capacitor of the MOSFET. On the other hand, it
is difficult to reduce the turn-off time by the above mentioned
techniques because a time constant to charge the parasitic
output capacitance of the MOSFET dominantly determines theturn-off time. Effective approaches to reduce the turn-off time
have not been established yet and are required for the future
power converters to improve its power density sramatically.

E1

S3

S4
S1

D3

vL
Load

E2

iL

D4

D1
C1

vds1

vgs1
S2

D2
C2

vgs2
Fig. 1. Chopper with proposed auxiliary circuit.

Fig. 3. Half-bridge inverter with proposed auxiliary circuit.

Fig. 2. Switching pattern of chopper with auxiliary circuit.

There are two manners to operate the power switching
devices, i.e., one is a soft switching technique and the other is a
hard switching technique. The former technique is basically
emplyed to reduce switching losses as well as radiation andconduction noises. However, the technique can reduce theswitching losses by lowering dv/dt and di/dt, while it seems to
be rather difficult to achieve a high-frequency operation suchas MHz-order switching because low dv/dt and di/dt increase
the switching time.
This paper proposes a new approach to achieve a highspeed switching operation of the MOSFET with large parasitic
output capacitors. The proposed approach is based on use of
an auxiliary circuit shorting the load. The porpose of this
auxiliary circuit is not the above mentioned soft switching but ahard swiching operation, so it makes a high-speed and highefficiency switching possible by enlarging dv/dt. The proposed
method is applied to a chopper and a half-bridge inverter aswell. It has been confirmed through experimental tests that the
chopper with the proposed auxiliary circuit can generate over
1-MHz output without deteriorated switching waveform andthe half-bridge inverter with the extended auxiliary circuit can
improve its total efficiency by 8 points in a low-load range
compared with the conventional inverter.
II.

CIRCUIT CONFIGRATION AND OPERATION

A. Chopper with Auxiliary Circuit Shorting Load
Figure 1 shows a chopper with a proposed auxiliary circuitthat consists of an additional auxiliary diode D2 and an
auxiliary switch S2. This auxiliary circuit is directly connectedin parallel with the load, which makes unidirectional current
flow possible with shorting the load. The DC power supply
voltage E is 100 V, the main power switching device S1 andthe auxiliary switch S2 are FK-30SM-5, MITSUBISHI, and theauxiliary diode D2 is STTH60L06, ST Microelectronics. The
load is an inductive load. C1 specifically shown in the figure isFig. 4. Switching pattern of inverter with auxiliary circuit.

a parasitic output capacitor of the main device S1, of which
capacitance is 580 pF. None of the parasitic capacitors of theauxiliary switch S2 are shown in Fig. 1 because they are
negligibly small compared with those of the main device S1.
The current rating of the auxiliary switch S2 is not needed to behigh because the drain current of the auxiliary switch S2 does
not flow continuously. Since the auxiliary switch S2 requires
high-speed switching at turn-on, a device with a small parasitic
input capacitor should be employed.
Figure 2 shows a switching pattern of the chopper with theproposed auxiliary circuit shorting load. In the figure, only aturning-off operation of the main device S1 is illustrated
because the auxiliary circuit works at only the timing of theturn-off of the main device S1. The auxiliary switch S2 turns
on right after the turn-off of S1. The current in Mode 1 flows
in a path of E→Load→S1→E, and the main device S1 turns
off at the end of the Mode 1. The auxiliary switch S2 must be
turned on as soon as the gate signal to the main device S1 goes
down. However, it takes certain time to turn on S2 and to turnoff S1 completely. Mode 2 is a period that both of theswitching devices are in such a transient state. In the Mode 2,
the current still flows in the path of E→Load→S1→E, andcharging the parasitic output capacitance of S1 gets started. In
this short period of the Mode 2, the charging speed is not fast
because the drain-source voltage rises according to a time
constant determined by the load and the parasitic output
capacitance C1. Therefore, the rising time of S1 depends on
the load current, and the lower load current makes the turn-offtime longer. In other words, it is difficult to achieve a fastswitching of S1 in a low-load range.

In order to solve the above problem, the proposed method
introduces the auxiliary circuit shorting load, which provides
the parasitic output capacitance C1 with a fast chargeable
current path. By turning on the auxiliary switch S2, the current
path of E→D2→S2→C1→E is established to charge theparasitic output capacitance C1 very rapidly, and the turn-offtime of S1 can effectively be improved. The charging currentof C1 is independent of the load current, so the fast switchingof S1 can be obtained even in the low-load range. Aftercompleting the turn-off process of S1, i.e., charging process of
C1, the proposed circuit gets into Mode 4, and the load current
circulates in the loop of Load→D1→Load like a conventional
buck chopper.
B. Haif-Bridge Inverter with Auxiliary Circuit Shorting Load
Figure 3 shows a proposed half-bridge inverter with anotherconfiguration of an auxiliary circuit. Since the load current andthe load voltage are bipolar in the case of the inverter, theauxiliary circuit must be a bidirectional and four-quadrant
switch. This is the reason why two sets of MOSFETs withbody diodes are connected in parallel with the load. The
proposed configuration of the inverter looks identical to theneutral point shorted or the T type three-level inverter, but the
purpose and the operation of the auxiliary circuit is far different
from those of the conventional three-level inverter. In otherwords, the proposed inverter does not work to generate thethree-level output voltage although the bidirectional switch isconnected to the load.
The power supply voltage E1 and E2 are 100V, the main
devices S1 and S2 are STY60NM60, ST Microelectronics,
auxiliary switches S3 and S4 are FK30SM-5, MITSUBISHI,
and the load is inductive of which power factor is 0.85. C1 andC2 represent parasitic output capacitors of the main devices S1and S2. As described in the previous section, parasitic
capacitors of the auxiliary switches S3 and S4 are omitted from
Fig.3 because of their negligibly smaller values compared withthose of the main devices. It is possible to employ low-current
and half-voltage rated switching devices in the auxiliary circuitas the load current does not flow continuously through theauxiliary circuit. Instead transient pulse-shaped current flows
through only in a turning-off moment of the main devices S1and S2.
Figure 4 shows a switching pattern of the half-bridge
inverter with the proposed auxiliary circuit shorting the load.
One of the auxiliary switches S3 and S4 turns on just after oneof the main devices S1 and S2 turns off. In Mode 1, it isassumed that the load is drawing the current in a path of
E1→S1→Load→E1. The parasitic output capacitance C2 hasbeen charged at the voltage of E1+E2 in this mode. By turning
off S1, charging of the parasitic output capacitance C1 gets
started in the path of E1→C1→Load→E1, whereas the otherparasitic output capacitance C2 is discharged in the path of
C2→Load→E2→C2 at the same time. In this short transientperiod, the charging time and the discharging time aregoverned by time constants between the load and each parasitic
output capacitance of the main device. Therefore, this transientperiod becomes longer as the load current gets lower. In otherwords, it is more difficult to achieve fast switching operation as
the load is reduced, especially in a low-load range. When theFig. 5. Experimental waveforms of conventional chopper at 200-kHz output.

Fig. 6. Experimental waveforms of proposed chopper at 200-kHz output.

dead time period to prevent a short circuit across the DC bus iscompleted during this charging and discharging period of theparasitic output capacitances, the other main device S2 isturned on. Turning on S2 dissipates energy stored in theparasitic output capacitance C2, and a short circuit current
flows through C1 and S2 in the path of E1→C1→S2→E2→E1.
Therefore, one of the auxiliary switch S3 is turned on as soon
as the main device S1 is turned off to make the fast switchingpossible. By turning on the auxiliary switch S3 in Mode 3, theparasitic output capacitance C1 is charged rapidly through thepath of E1→C1→D4→S3→E1. The other parasitic output
capacitance C2 is discharged quickly through the path of
C2→D4→S3→E2→C2 at the same time. This operation
mode allows to retrieve the energy stored in C2 to E2, which
contributes to improve total efficiency of the whole inverter
circuit. The current path in this period is independent of theload, so the fast switching can be achieved even in a low-loadcondition. In Mode 4, electrical charge remained in theparasitic output capacitance C2 is consumed by turning on S2
while the other parasitic output capacitance C1 is charged
quickly owing to a short current of E1→C1→S2→E2→E1.
The short current at this moment can be mitigated, compared
the proposed circuit with the conventional one. After theFig. 10. 1-MHz output waveforms of conventional chopper.

Fig. 7. Load to actual duty cycle characteristic.

Fig. 11. 1-MHz output waveforms of proposed chopper.

Fig. 8. Load to efficiency characteristic.

Fig. 9. Operation frequency to actual duty cycle characteristic.

circulating load current mode (Load→E2→D2→Load) in theMode 4, Mode 5 gets started and lets the load current flow
through the path of E2→Load→S2→E2. A similar operationis performed when the main device S2 is turned off and S1 isturned on.
III.

EXPERIMENTAL TEST RESULTS

A. Chopper with Auxiliary Circuit Shorting Load
Some experimental tests have been conducted to examine
feasibility of the proposed technique. Figures 5 and 6 show
operation waveforms of the conventional chopper and the
chopper with the proposed auxiliary circuit, respectively. In
both prototype circuits, operation frequency is 200 kHz, theduty cycle is 50 %, and the load is 400 Ω and 0.4 mH. As canbe seen in Fig. 5, the drain-source voltage vds1 rises very slowly
in the conventional chopper due to the parasitic output

capacitance of the main device. It takes a long time to charge
fully the parasitic output capacitance, which results in the slow
turning off of the main device. On the other hand, very rapid
rising of vds1 can be confirmed as shown in Fig. 6. This fastswitching operation is achieved by turning on the auxiliary
switch S2 just after the main device S1 is turned off. Even
though the same gate signals at the duty cycle of 50 % areapplied to the both choppers, actual duty cycles of the drainsource voltage waveforms are 55.3 % and 50.6 %, respectively.
In addition, according to the turn off dv/dt of vds1 in Figs. 5 and6, very high rate of 8.0 kV/μs can be confirmed with theproposed circuit, which is approximately 26 times of dv/dt ofthe conventional circuit. Figure 7 indicates a load to actual onduty cycle characteristic under the condition of a constant load
power factor at 0.62. It can be seen that the proposed circuit iscapable to operate around 50 % actual duty cycle even in a
low-load range. Both of the conventional and proposed
choppers can operate at 50 % actual duty cycle if they have aheavy load, i.e., a high load current, because the high load
current allows quick charge of the parasitic output capacitancein the both cases. Figure 8 shows a load to total efficiency
characteristic. As shown in the figure, the conventional circuit
has better result than the proposed one in the low-load range
less than 63 W. This efficiency degradation of the proposed
circuit is caused by a switching loss and a conduction loss of
the auxiliary circuit. However, the proposed technique makes
it possible to operate the chopper at very high operation
frequency. Figure 9 shows an actual duty cycles of vds1 when
the operation frequency is varied up to 1 MHz under thecondition of a 400-Ω constant load. As shown in the figure,the proposed circuit is capable to operate at almost 50 % actual
duty cycle over the range of 1 MHz, whereas the conventional
circuit is limited to work under 100 kHz. The actual duty
cycles of the both circuits are 79.1 % and 52.8 % at 1-MHz
operation frequency, respectively. Figures 10 and 11 indicate
the 1-MHz output waveforms of the conventional and the
proposed choppers. As shown in Fig. 10, the MOSFET of theconventional circuit does not work as a switch at 1 MHz

Fig. 12. Experimental waveforms of conventional inverter at 100-kHz output.

Fig. 14. Enlarged waveforms of conventional circuit.

Fig. 13 Experimental waveforms of proposed inverter at 100-kHz output.

because its slow rising time is dominant in the switching period.
As described above, the chopper with the proposed auxiliary
circuit has slightly lower efficiency in the low-load range, but
is capable to operate properly over the frequency range ofMHz-class.
B. Haif-Bridge Inverter with Auxiliary Circuit Shorting LoadTwo prototypes of a conventional inverter and an inverterwith a proposed auxiliary circuit have been set up to confirm
their operation characteristics. These inverters are operated at
an operation frequency of 100 kHz, a duty cycle of 50 %, adead time of 150 ns, and a load of 400 Ω plus 0.4 mH. Their
operating waveforms are shown in Figs. 12 and 13. As can beseen in the figures, there is hardly big difference between the
output voltages and the load currents of both inverters. Since
the dead time to prevent a short circuit across the DC bus isonly 150 ns, and the auxiliary circuit works only in the deadtime period, which does not affect the operating waveforms
detrimentally. Enlarged waveforms are depicted in Figs. 14
and 15 where the gate-source voltage vgs1, the drain-source
voltage vds1 and the load voltage vL are observed in detail. As
can be seen in these figures, the rising time of the drain-source
voltage waveform vds1 of the proposed circuit is effectively
improved, and it should be noted that the delay time between
the falling edge of the gate signal vgs1 and the rising edge of thedrain-source voltage vds1 is remarkably reduced by the
proposed technique. There is a dead to time to prevent a shortcircuit across the DC bus between turning-off operation of S1and turning-on operation of S2. One of the auxiliary switch S3
is turned on within the dead time period. The parasitic output
capacitance C1 is rapidly charged through the path of
E1→C1→D4→S3→E1, and energy stored in the otherparasitic output capacitance C2 is simultaneously retrieved to
the
power
sourceE2throughthepathof
C2→D4→S3→E2→C2.
This implies that energy
consumption of the electrical charge stored in C2 can bediminished when the main device S2 is turned on, which leads
to reduction of the turn-on loss of the main devices. In the caseFig. 15. Enlarged waveforms of proposed circuit.

of the conventional chopper, the time delay between the fallingedge of the gate signal vgs1 and the rising edge of the drainsource voltage vds1 is 380 ns. However, the time delay of the
proposed circuit can be reduced to 288 ns, and the total
efficiency is improved from 53.9 % to 60.0 %. As described sofar, not only speeding up the turn-off operation but also
improving the efficiency can be realized by the proposed
technique.
Figure 16 shows an efficiency characteristic of theconventional and the proposed inverters. It is found that theefficiency of the proposed circuit is higher than that of theconventional one in the low-load range under 28 W. The
maximum difference between the two efficiency characteristics
is 6.1 points at the lowest load condition of 14 W. Thisefficiency improvement is chiefly achieved by diminishing theturn-on loss of the main devices after the dead time period. In
addition, a relationship between the dead time and theefficiency is indicated in Fig. 17, where the load is kept
constant at 14 W. It can be seen that the longer dead time
makes turn-on loss lower and the total efficiency higher
because even the conventional circuit can charge or discharge
the parasitic output capacitance of the main devices during thedead time. In general, however, it is desirable to set the deadtime less than 5 % of the switching period, so the dead timeshorter than 500 ns is required in the 100-kHz prototype
inverter. When the 100-kHz inverter is operated in low-loadcondition, it is impossible to charge or discharge the parasitic

Fig. 16. Load to efficiency characteristic.

when the commanded duty cycle of the gate signal is 50 %.
Furthermore, it is confirmed that the turn-off dv/dt is enhanced
from 0.3 kV/μs to 8.0 kV/μs; hence this means that the
proposed technique can achieve 26 times high-speed switchingof the main device in comparison with the conventional
circuit.
On the other hand, the half-bridge inverter with theproposed auxiliary circuit is also possible to shorten the turnoff time from 380 ns to 288 ns even at a low output power of
14 W. It is confirmed that the total efficiency including the
proposed auxiliary circuit can be improved by 6.1 points from
53.9 % to 60.0 % in such a low-load range. Moreover, theproposed technique can shorten the dead time from 450 ns to
150 ns if the same level of the total efficiency, e.g. 60 %, isrequired.
The proposed method is very effective to drive the
MOSFETs with a large parasitic capacitance. Particularly, if
multiple MOSFETs are connected in parallel to enhance thecurrent capability, the method is suitable to such applications.
ACKNOWLEDGMENT

Fig. 17. Dead time to efficiency characteristic.

output capacitance quickly during the dead time. Therefore,
the proposed auxiliary circuit is very effective to achieve highspeed switching as well as high-efficiency switching. As canbe seen in Fig. 17, the efficiency of 60 % can be obtained at150-ns dead time by the proposed technique, but theconventional circuit requires 450-ns dead time to achieve 60-%
efficiency.
Since the conduction loss and the switching loss are
dominant factors of power conversion losses and the
conduction loss is almost same level between the conventional
and the proposed circuit, the efficiency improvement of the
proposed one owes reduction of the switching loss and retrievalof the energy stored in the parasitic output capacitance. The
proposed technique is considered to be effective and efficientwhen the MHz-class high-frequency power converters areoperated.
IV.

The authors wish to express their gratitude to Mr. T. Sasaya,
Mr. T. Kimura, and Mr. S. Katayama, DENSO ResearchLaboratories, DENSO Corporation for valuable financial andtechnical support to their power electronics laboratory,
Department of Electrical and Electronic Engineering, Facultyof Engineering, Shizuoka University.
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CONCLUSION

This paper has described a high-speed switching operationof MOSFETs using an auxiliary circuit shorting the load. The
proposed technique has been applied to a chopper and a halfbridge inverter, and their operation characteristics have been
confirmed through several experimental tests.
As a result, the proposed circuit surpasses the conventional
one particularly in a low-load range from various viewpoints.
In the case of the chopper application, the proposed techniqueis capable to drive the main switching device over 1-MHzeven in a low-load range, and the actual on-duty cycle of themain device is improved by 26.3 points from 79.1% to 52.8%

[6]

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