SHF Communication Technologies AG,Wilhelm-von-Siemens-Str. 23 D • 12277 Berlin–Marienfelde • Germany
Phone ++49 30 / 772 05 10 • Fax ++49 30 / 753 10 78
E-Mail: mail@shf.biz • Web: http://www.shf.biz

Datasheet
SHF 41210 A
Clock Recovery
Optical Receiver

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

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Description
The SHF 41210 A is an optical receiver and clock recovery unit. This is a half-width plug-in for theSHF 10000 A mainframe. Field installation or upgrade by the end-user is possible for thisequipment.
It can be specified as just a receiver (option OE), or just clock recovery (option CR) or with bothoptions. With both options fitted, they are connected internally so that the electrical data and therecovered clock signal are available from the outputs. It is still possible to use both options alone.
The optical receiver converts optical signals with a bit rate up to 50 Gbps into electrical signals.
Broadband operation is possible and the wide output dynamic range combined with excellent pulse
behavior makes the device ideal for optical system research.
The clock recovery extracts a clock signal at a frequency half of the incoming bit rate from anelectrical data signal at a nominal bit rate of about 40 Gbps or about 43 Gbps. It contains twoseparate VCOs which allow operation in a standard mode at 39.81 Gbps or in an FEC mode tocover FEC bit rates of 42.65 Gbps or 43.01 Gbps respectively. Two reference frequencies areincluded as standard. The clock recovery option does not support broadband operation.

FeaturesOptical Receiver
Broadband operation up to 50 Gbps
High optical sensitivity
Wide output dynamic range
High output saturation suitable for 2R regenerationExcellent pulse behavior
Unsurpassed high power handling capability
High responsivity
Clock Recovery
supports multiple data rates (standard bit rate mode at OC-768, non-FEC rates around 39.8 Gbps
and FEC bit rate mode at OC-768 FEC rates around 43 Gbps)
clock output frequency at half and quarter of the nominal input data bit ratea reference signal at input bit rate divided by 64 is required
only a 50 mV single ended input signal is required
excellent tolerance against input signal jitterOptions
CR – with clock recovery
OE – with optical/electrical converter
C40 – 40GHz clock output for clock recovery

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

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Specifications – SHF 41210 A
Option CR – Clock recovery
Parameter

Unit

Min.

Typ.

Max.

Comment

39.5
42.5

40.1
43.1

NON-FEC mode
FEC mode

50

1000

40/43 Gbps Data Input
Operating bit rate
VCO1
VCO2Gbps

Input Voltage

mV

625/672 MHz Reference Clock Input (bit rate divided by 64)
Input Frequency

MHz

617
664

627
674

Input Voltage

mV

200

800

Output Frequency

GHz

19.75
21.25

20.05
21.55

Output Voltage

mVpp400

NON-FEC modeFEC mode

Half Clock Output (half bit rate)

RMS-Jitter

fs

600

800

400500NON-FEC mode
FEC modeon scope display, measured
with Agilent 86100A with
precision time base

Clock/4 Output (quarter bit rate)
Output Frequency

GHz

9.875
10.625

Output Voltage

mVpp

400

RMS-Jitter10.02510.775600

fs

NON-FEC mode
FEC mode

800700on scope display, measured
with Agilent 86100A with
precision time base

40.1
43.1

NON-FEC mode
FEC mode

Full Clock Output (optional, full bit rate)
Output Frequency

GHz39.5
42.5

Output Voltage

mVpp

400

RMS-JitterSHF 41210 A – Rev. 1.2 – 10/JUN/2005

fs600

800500600

on scope display, measured
with Agilent 86100A withprecision time base

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Specifications – SHF 41210 AOption OE – Optical receiverParameter

UnitMin.

Wavelength range

Typ.

Max.

Comment

C and L band

High frequency 3dB pointGHz

Low frequency 3dB point

kHz30
30Conversion gain

mV/mW

Receiver sensitivity

dBm

-9

Output saturation voltage(peak-peak)

V

5

6

Rise/fall times

ps9

1010…90%

Optical input power

dBm

13CW

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

350450at 1550 nm

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Test Results
Option CR – Clock recovery

Half Clock Out @ 39.81 Gbps

Half Clock Out @ 43.018 Gbps

Clock/4 Out @ 39.81 Gbps

Clock/4 Out @ 43.018 Gbps

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

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Test Results
Option OE – Optical receiver

40 Gbps electrical output signal with
6dBm optical input power

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

Sensitivity measurement

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Application Remarks Clock Recovery
1. Open the “Clock Recovery Module” from the Module Menu.

2. The Clock Recovery Module is used to control the SHF 41210 A. The following screen isdisplayed when Clock Recovery Module is selected.

3. The unit can be operated in two bit rate ranges – the “NONFEC” range between 39.5 Gbps and40.1 Gbps and the “FEC” range between 42.5 Gbps and 43.01 Gbps. The desired range has to be
selected in the reference clock section.
4. The internally used phase detector needs a bit rate divided by 64 reference signal. If the operating
bit rate deviates from those supported by the internal reference oscillators, an external reference
signal has to be applied, e.g. operation at exactly 40 Gbps requires a 625 MHz reference signal(40G/64). The user has to select the appropriate setting in the reference clock section. If anoperating mode using an external reference is selected it is indicated by a green LED next to thisreference clock input (Ref. Clock In).
5. Depending on the topology used to split the incoming signal into the data and clock recovery pathit might be necessary to improve the input reflection coefficient with an attenuator.

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

Page 7/10Operation at 39.81 Gbps
Set the reference clock selector to “Internal Reference 1”.

Apply a data signal to the “Data In” input.
The recovered 19.9 GHz clock signal is available at the “Half Clock Out” output.
Operation at 43.01 Gbps
Set the reference clock selector to “Internal Reference 2”.

Apply your 43.01 Gbps data signal to the “Data In” input.
The recovered 21.5 GHz clock signal is available at the “Half Clock Out” output.
Operation between 39.5 Gbps and 40.1 Gbps
Set the reference clock selector to “External Reference 1”.

Apply a reference clock signal (bit rate divided by 64) to the “Ref Clock In” input.
Apply a data signal to the “Data In” input.
The recovered clock signal is available at the “Half Clock Out” output.
SHF 41210 A – Rev. 1.2 – 10/JUN/2005

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Operation between 42.5 Gbps and 43.1 Gbps
Set the reference clock selector to “External Reference 2”.

Apply a reference clock signal (bit rate divided by 64) to the “Ref Clock In” input.
Apply a data signal to the “Data In” input.
The recovered clock signal is available at the “Half Clock Out” output.

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

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Topologies
The incoming data signal has to be separated into two paths – the data path to the error analyzer andthe clock path to the clock recovery module. If you have an optical signal there are two possibilities tosplit – optical or electrical. From our point of view its better to split the optical signal (Fig. 1), provided
that you have two high speed photo diodes available.

Clock Recovery Module

Data In

Error Analyzer

Half Clock Out

Half Clock In

Data In

Attenuator

Fiber

Optical Power Splitter

Fiber

Photo DiodePre-Amp

Fiber

Photo Diode

Pre-Amp

Fig. 1
If you have to split the electrical signal, Fig. 2 applies. In case a 6 dB power splitter is used werecommend using an attenuator of at least 6 dB at the clock recovery data input to prevent
deterioration of the data signal going to the error analyzer.

Clock Recovery Module

Data In

Half Clock OutError Analyzer

Half Clock In

Data In

Attenuator

Fiber

Photo Diode

Pre-Amp

Fig. 2

SHF 41210 A – Rev. 1.2 – 10/JUN/2005

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