SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23D • 12277 Berlin • Germany
Phone +49 30 772051-0 • Fax +49 30 7531078
E-Mail: sales@shf-communication.com • Web: www.shf-communication.com

Datasheet
SHF 616 B
128 GBaud PAM4 Multiplexer

SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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Description
The SHF 616 B is a PAM4 Multiplexer operating at PAM4 baud rates up to 128 GBaud (256 Gbps) foruse in broadband test setups and telecom transmission systems.
The SHF 616 B is driven by four single ended serial NRZ data streams. Each two of these signals are
multiplexed to two binary data steam of double the speed. These two high speed signals are internallycombined to one differential PAM4 signal. With a programmable SHF BPG (e.g. the SHF 12105 A) you
have full control of the patterns into the PAM4-MUX. The SHF BCC Control Center software package
unifies the BPG to PAM4-MUX combination to virtually one 128 GBaud PAM4-Bit Pattern Generator. A
typical setup is shown in the figure 1 below.
A single ended clock signal with a frequency equivalent to the input data rate is required to drive theSHF 616 B. For data regeneration purposes all input data signals are re-sampled to mitigate any signal
impairments resulting e.g. from long cables. Therefore, it is possible to place the PAM4-MUX very
close to the DUT. Clock input port is AC-coupled. Data input and output ports are DC-coupled.

Features

Broadband operation up to 128 GBaud
Differential data output, 0.7 V differential output swing (0.35 V in single-ended operation)Single ended clock and data inputs
Latched (re-timed and re-shaped) input ports
Output amplitude & input threshold level control (remote by software)

Applications


100 Gbps (100GbE), 200 Gbps (200GbE), 400 Gbps (400GbE) & 1 Tbps (TbE) system evaluation
Broadband test and measurement equipment
PAM4 and Advanced Modulation Experiments

Block Diagram
Out OutSHF616 B

USB/LANA

2:1
Mux+B

Clk(MSB) (MSB)

2:1
Mux

A

B

(LSB) (LSB)

PowerSupply

SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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Ease of Use
Housed in a small benchtop case, this remote head can be easily embedded in the customer’s test
environment close to the DUT.

Figure 1 - Typical setup with SHF clock source, SHF BPG and the PAM4-MUX

The easy to use software package, SHF BCC Control Center is the most convenient way to control theMUX. The software reads the individual calibration tables of the multiplexers and sets the contribution ofthe bias voltages accordingly. The symmetry of the output signal can be set and is displayed in thegraphical user interface (GUI). The duty cycle (clock bias) of the multiplexer stages as well as the input
threshold level for the DC-coupled data inputs can be set. This enables the user to generate a perfectsignal just by a few intuitive clicks.

BCC Control Center - SHF 616 B
SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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Absolute Maximum Ratings
Parameter

Unit

Symbol

Min.

Typ.

Max.

CommentData Input Voltage

mV

Vdata in900

Peak-to-Peak

Clock Input Voltage

mVVclk in

900

Peak-to-Peak

External DC Voltage on
RF Clock Input PortVVDCin-10+10AC coupled input

External DC Voltage on
RF Data Input Ports

VVDCin-0.6+0.1

DC coupled inputs

DC Supply Voltage

VVcc

Unit

SymbolMin. Input Data Rate

Gbps

Rin,minMax. Input Data Rate

Gbps

Rin,max

64

Data Input Voltage

mVVdata in

300

800

Eye amplitude;
500 mV recommended

External DC Voltage on
RF Data Input Ports

V

VDCin

-0.50

DC coupled inputs

Min. Clock Input Frequency

GHzfin,min

Max. Clock Input Frequency

GHzfin,max64Clock Input VoltagemVVclk in

300

800

Peak-to-Peak;
500 mV recommended

External DC Voltage on
RF Clock Input PortVVDCin-9+9AC coupled input

Input Parameters

13.0

Specifications
Parameter

Min.

Typ.

Max.

CommentInput Parameters
11

1

1

The upper baud rate limit is defined by the absence of errors (BER < 10-12) of a NRZ output generated with the MSB + LSB bit synchronized. ThePAM4-MUX operates beyond this limit as shown in the typical eye diagrams below. However, it is just not currently possible to verify a true BER beyond
this limit.

SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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ParameterUnit

SymbolMin. Output Data Rate

GBaudRout,minMax. Output Data Rate

GBaud

Rout,max

Min.

Typ.

Max.

Comment

Output Parameters
22128

300
2703mV

Vout

Rise / Fall Time

pstr / tf

Equivalent Output Bandwidth

GHzBW

Differential Output Skew

pstskew

Supply Voltage

VVc

Supply Current

mA

Power Dissipation

Output Voltage537≤ 100 GBaud> 100 GBaud
Eye amplitude;
Single ended;
DC coupled;
Full scale;
Adjustable up to -6 dB

350
320

620%...80%;
Full scale;4deconvolved
Derived from Rise Time
5using formula ;-3 dB bandwidth

44
12+12+12.5

Ic

1000

1100

WPd

1213.2

Operating Temperature°C

Tambient

Heightmm

H

50.8

WidthmmW

221.4

Depthmm

D177

Weightgm

1700

General+11.5102.1 mm DC Power Jack

@ VC = +12V

35

2

The upper baud rate limit is defined by the absence of errors (< 10-12) of a NRZ output generated with the MSB + LSB bit synchronized. The PAM4MUX operates beyond this limit as shown in the typical eye diagrams below. However, it is just not currently possible to verify a true BER beyond thislimit.
3During start up / shut down of the SHF 616 B and turning on / off the RF outputs, voltage spikes up to +0.7 V can occur at the data output ports

4Calculation based on typical rise / fall times from oscilloscope data sheet and with a NRZ output generated by bit synchronization of the MSB + LSB𝑡𝑟 𝑑𝑒𝑐𝑜𝑛𝑣𝑜𝑙𝑣𝑒𝑑 = √(𝑡𝑟 𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑑 )2 − (𝑡𝑟 𝑜𝑠𝑐𝑖𝑙𝑙𝑜𝑠𝑐𝑜𝑝𝑒 )2 = √(𝑡𝑟 𝑚𝑒𝑎𝑠. )2 − (3.68 𝑝𝑠)25

Calculation based on formula: 𝐵𝑊 =0,22
𝑇𝑟

SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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Typical Output Eye Diagrams
31

The measurements below had been performed using a SHF 12105 A Bit Pattern Generator (PRBS 2 1) and a Tektronix DSA 8300 Digital Serial Analyzer (DSA) with Phase Reference Module (82A04B60G) and 70 GHz Sampling Module (80E11). The outputs of the PAM4 MUX module had beenconnected directly to the DSA input.

PAM4 Output Signal Measurement

Out @ 130 GBaud

Out! @ 130 GBaud

Out @ 128 GBaud

Out! @ 128 GBaud

Out @ 124 GBaud

Out! @ 124 GBaud

SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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Out @ 100 GBaud

Out! @ 100 GBaud

Out @ 80 GBaud

Out! @ 80 GBaud

Out @ 64 GBaud

Out! @ 64 GBaud

SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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Outline Drawing – SHF 616 B
SHF 616 B

PAM4 Multiplexer

PowerOutputs

OnOff

58.9

ErrorOutOut

0.5 Vpp Max

0.5 Vpp Max

50  / 1.85 mm Female

221.4

145.4
130.4
100.4
85.4
36.6

7.255.4

6 54 38.9177

785.2
95.2

1236.5beca50  / 1.85 mm Female
12 V / 2A-0.9 V < Vin < +0.4 VUSB
B MSB

A LSB

B LSB

ClkConnector
1.85mm (V) Female
1.85mm (V) Female
1.85mm (V) Female
1.85mm (V) Female
1.85mm (V) Female
1.85mm (V) Female
1.85mm (V) Female

A MSB

Designation
OutputOutput
A MSB
B MSB
A LSB
B LSB
Clock Input

EthernetService0.9 Vpp Max

Pos.
1234
5
67d

Pos.
abcde

Designation
USBGND
Ethernet
Power SupplyService

all dimensions in mm

SHF reserves the right to change specifications and design without notice - SHF 616 B - V002 – August 30, 2019

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