Performance Modeling of Digital
Processing Systems
Rajesh Chandra
Northrop Grumman Corporation

Deepak Shankar
Mirabilis Design Inc.

Approved for Public Release; Distribution is Unlimited; #21-0105; Dated 02/04/21© 2021, Northrop Grumman

Content
SW is applied here

• Timing prediction of software execution is hard
• Existing system-level modeling methodologies (SystemC,etc.) are complex and inadequate

Application− Provides theoretical performance prediction− But they are often error-prone and inconsistent with actual
performance data

Abstraction• Traditionally performance is estimated based onspreadsheets

Input:
Data rate
Input data size
Compute op

Processing power (GFLOPs)
I/O data rate
Memory size
Scale factor(based on historic data)

HWarchitecture /requirements

Performance(throughput, latencies)

HW, Bits

Timing is obtained from HW- disconnected from SW tasks

Compute system is too complex to analytically predict SW execution performance
Approved for Public Release; Distribution is Unlimited; #21-0105; Dated 02/04/21

Proposed Digital System Architecture Modeling
Top-level requirements• Processing systems comprise 2 parts− Functional behavior: well established tools andprocesses for modeling and verification− Timing behavior: no process or tool for modeling, haveno visibility how SW executes in HW

Functionalrequirements• Absence of timing behavior results inFunctional behavior- SW/FW code

− Unproven system level requirements (such as data
throughputs and error rates)− Incorrect requirements generation for design andimplementation• New tool and methodology proposed to modeltiming behavior− Connects architecture model with systems requirements− Generate optimal and implementable design
requirements

Timingrequirements

Timing behavior
Task timings and deadlines

SWFWSW

HWFPGACPUGapCPUFunctional
requirements

Timingrequirements
Integration & Test

(HW, SW)

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Performanceverification(1-4 years)

Performance Modeling Using VisualSim Tool
• VisualSim - architecture exploration tool formodeling timings behavior of digitalprocessing systems• Modeling approach – focus on data flow andtimings− Use key events and timings relevant toperformance, data flows, error rates and power
consumption− Use HW platform architecture model to obtaintiming information• Modeling flow
− Processor modeling uses statistical informationfrom software application− Other sub-systems are stochastic or cycle-accurate

Requirements
Behavioral flow(SW tasks)

Processingplatform (HW)Single boardcomputer

Data-driven
performance
estimates

VisualSim reduces modeling complexity by separating functional and timing behaviors
Approved for Public Release; Distribution is Unlimited; #21-0105; Dated 02/04/21

Content• Radar signal processing flow – SW/FW tasksMission
Processing latency
IQ data

Functions mapped toHW platform model• Processing platform (Single board computer)
Processor’s core utilization

PCIe port activitiesIdentify resource
contentions and bottlenecks

Tune SW tasks and HW configuration for desired processing performance
Approved for Public Release; Distribution is Unlimited; #21-0105; Dated 02/04/21

Summary• Identified gap in processing systems modeling and proposed timing-only analysis− Not focusing on functional aspects makes modeling relatively simple, enabling performance analysis oflarge processing systems• Proposed capability enables reasonably accurate performance estimate ofalgorithms early in architecture and design phases, before hardware is tested andsoftware is written− Recognized statistical nature of timings in compute systems− Unlike functional aspects, precision/cycle-accurate simulation is not required in most performance
analysis of processing systems

Approved for Public Release; Distribution is Unlimited; #21-0105; Dated 02/04/21

Thank You!

Approved for Public Release; Distribution is Unlimited; #21-0105; Dated 02/04/21