A Novel Five-level Three-phase PWM Rectifier
with Reduced Switch Count
Jun-ichi. Itoh*, Yuichi Noge*, Taketo Adachi**Nagaoka University of Technology, Niigata, Japan

Abstract–
This paper proposes a new circuit topology for a multilevel PWM rectifier. The proposed method forms a newcircuit by combining a diode clamp type topology with a flying capacitor type topology. The proposed circuit
uses only 12 switches, despite the use of a five-level three-phase PWM rectifier. Further, the proposed circuit
can obtain good performance same as a conventional multilevel circuit. This paper describes about thefeatures of the proposed topology; the control strategy and the loss analysis which is estimated by a circuit
simulator. In addition, the basic operation of the proposed method is confirmed by simulation andexperimental results. The proposed converter achieved THD (Total harmonic distortion) of 3.4% for the input
current and efficiency of 97.4% for a 1 kW class experimental setup.

Index TermMultilevel systems, Pulse width modulated power converters, AC-DC power conversion, Rectifiers, Powersystem harmonics*Nagaoka University of Technology, Nagaoka, Japan
Telephone: +81-258-47-9563
FAX: +81-258-47-9563
E-mail: itoh@vos.nagaokaut.ac.jp (Jun-ichi Itoh)noge@stn.nagaokaut.ac.jp (Yuichi Noge)adachi@stn.nagaokaut.ac.jp (Taketo Adachi)

This paper was presented in ECCE 2009 San Jose California and modified to submit in IEEE transaction on PELS.

I.

INTRODUCTION

Recently, the harmonics current in power grids have caused various problems, such as line voltage distortion andheating in power factor correction capacitors. The harmonics current in power grids is mainly generated by a dioderectifier which is used as a front converter of an inverter. In order to reduce the harmonics current of the power grid,
power factor correction (PFC) rectifier still stands for a very important technology. A PWM rectifier, which isconsisted of three switching legs, remains one of the popular PFC rectifiers. A PWM rectifier can reduce theharmonics current dramatically because the grid current is able to control.
A PWM rectifier requires high voltage rating devices in order to be applied into the medium voltage applications.
The high voltage rating devices have known problems, such as low switching speed and large saturation voltage
between the collector and the emitter. The low switching speed requires a large volume of a boost reactor and filter
since the high switching frequency cannot be achieved. As a result, extra cost is needed for the applying of the PWM
rectifier in a medium voltage power grid.
For a medium voltage power grid, multi-level converter technology is one of the solutions for high voltage
rectification application [1]-[3]. In general, a n-level converter can reduce the voltage stress of a switching device to1/(n–1) of the DC output voltage. There are many circuit configurations for a multi-level converter, such as the diodeclamp (DCLP) type [4]-[5] that uses clamp diodes and capacitors for the DC output voltage, the flying capacitor (FC)type [6]-[7] that uses clamping capacitors floating on the DC output voltage, and the cascaded h-bridge type [8]-[9]that uses isolated power supplies to clamp each level. In term of cost reduction and downsizing, the DCLP and FC
types are better solutions than the cascaded type, since the cascaded type requires a large transformer and many
switching devices.
However, for the multi-level converters that are more than three-level, the DCLP type requires balance circuits inthe DC part, in order to control the clamping capacitor voltage [10]-[11]. And as for the FC type, it requires several
capacitors for the clamping capacitors. In addition, both methods needed to use a high amount of switching devices.
For example, in the case of a five-level three-phase rectifier, 24 switching devices are required. In conclusion, theproblems of the multi-level converters would be the number of switching devices and the control of the clamping
capacitor voltage.
This paper proposes a novel five-level three-phase rectifier topology, which combines the DCLP and FC typeconverters, and discusses about the control strategy. The proposed converter requires only half of the number ofswitches in comparison to the DCLP and FC types, that is, only 12 switches are used for the five-level rectifier. The
point of the proposed topology is that high voltage diodes can be more easily to be utilized than the high voltage
switching devices. The features of the proposed circuit are described, and the space vector modulation is used as acontrol strategy. The used of space vector modulation can result in a good sinusoidal current of the power grid. In
addition, a loss analysis method based on the PSIM circuit simulator is introduced [13]. The validity of the proposed
rectifier, the control strategy, the parameter design method and the loss analysis are confirmed by experimental

results.

II.
A.

PROPOSED CIRCUIT TOPOLOGY

Conventional Circuit
Fig. 1 (a) shows the DCLP and (b) shows the FC type five-level PWM rectifier topology. The switching devices ofboth topologies are of the same voltage rating. Both converters can use a voltage rating of 1/4 for the DC output
voltage; however, these converters use 24 switching devices. As a result, the cost will be increased and the control
strategy is complicated. For example, the control strategy for the FC type five-level PWM rectifier is described in thefollowing.
The FC type five-level PWM rectifier has 16 switching patterns. The switching patterns and its rectifier input
voltage, which is the voltage point between the rectifier and the boost up reactor based on the neutral point of thepower grid.
There are many switching patterns which can charge or discharge the flying capacitor disregards of the same
voltage level. These switching patterns should be selected in order to control the voltage of each flying capacitor inconstant. When the phase shift PWM is applied, the flying capacitor voltage will be kept constant [14]-[15]. However,many voltage sensors are required to detect the voltage of the flying capacitors in terms of the voltage protection of
power devices.
On the other hand, for the DCLP type, the clamping capacitor voltage can not be controlled without an auxiliary
circuit except for specific circumstances [12]. Additional voltage regulators, such as DC choppers, are required tomaintain each clamping capacitor voltage at quarter of the DC output voltage.

S1
S2
S3
S4
Vdc
S4'
S3'
S2'
S1'
(a) Diode Clamp (DCLP)(b) Flying Capacitor (FC)Fig. 1. Conventional five-level PWM rectifier topologies (single leg).

B.

Proposed Circuit
Fig. 2 shows the proposed five-level PWM rectifier using only 12 switches. The proposed converter combines boththe DCLP and FC types into one circuit. The voltage stress of the switch is 1/4Vdc as same as that of the conventional
circuits. The voltage stress for diodes requires 1/2Vdc in the proposed circuit. The current waveform of the diode is
PWM waveforms. However, the diode voltage does not receive reverse voltage for half period of the power gridfrequency. As a result, there is no recovery mode in the high voltage diode. Thus, the cost of the high voltage low
speed diode is cheaper than the high voltage switching devices. It should be noted that if the regeneration mode isrequired, then the high voltage diodes can be used replaced with the high voltage switching devices. In this case, low
speed switching devices, such as a thyristor or a gate turn off thyristor (GTO), can be applied, because the highvoltage switching devices do not switch at high frequency, but only switch at the same frequency of the power grid.
The proposed topology can be applied for both low voltage (200V, 400V) application and medium voltage (3.3kV,
6.6kV) application. In the low voltage application, the low voltage rating MOSFETs can be used to improve theswitching frequency. On the other hand, in a medium voltage application, high voltage rating (1/2Vdc) diodes are
required. However, it costs lower than the high voltage rating IGBTs.
Table I shows a comparison among the DCLP, FC and proposed rectifier. The largest advantage of the proposed
circuit is that the number of components in the proposed circuit could be used by using high voltage diodes. The
number of switching devices in the proposed circuit is reduced to 12, which is half of the conventional circuits. It
should be noted that if the proposed concept is applied for N-level rectifier topology, then the number of switching
devices can always be reduced to half of that conventional N-level converter topology, because the outer diode canabsorb half of the DC output voltage.
The other large advantage of the proposed circuit is that the proposed circuit can control each of the clamping
capacitor voltage. The voltage of the inner clamping capacitor C1 can be controlled at 1/4Vdc, because the structure of
the inside part is the same as that to the FC type. The voltage of the middle capacitors (C2 and C3) also can also be

TABLE I
DS1
SS1

DR1
SR1
DR2

SR2
C1
SR3

C2
VC1

SR4

DR1

SS2

DR2

DT1

*1

DS2

ST2*2

DS2

DT2

*1

C1*2C2*1

C1 C2
SS3

COMPARISON OF THE DCLP, FC AND PROPOSED

ST1*2

ST3

*2

SS4

ST4*2

DS1

DT1*1

DT2

C3*1

CONVERTER
RL

Proposed

Vdc

DCLP

FC

*1

circuit
C3*1

Lin
Voltage rating: *1 1/2Vdc *2 1/4Vdc

Switch24

24

12

Diode*1

60

24

36

Capacitor

4

30

13

limited*2

possiblepossible

Control of thecapacitor voltage

Fig. 2. Proposed hybrid PWM rectifier.

*1

including FWD *2 under specific circumstances [12]controlled at 1/2Vdc, because this part is the same as the three-level rectifier. Note that the proposed circuit can not
run an invert operation where the reverse energy will flow into the circuit because the diodes are used instead ofswitches.
Fig. 3 shows the current path of the proposed rectifier in each switching pattern. The proposed rectifier has eightswitching patterns. However, the available switching patterns are constrained by the direction of the grid current
because the proposed circuit uses diodes in the main current path.
The switching patterns and rectifier input voltage levels are described as following. Note that the neutral point of
the DC side is defined as the zero voltage level in this discussion.
In principle, the proposed circuit can output seven voltage levels to the AC side of the converter. However, inorder to control the inner clamping capacitor (C1) voltage Vc, two switching patterns for the charge or discharge mode
are required. Therefore, to keep the two switching patterns, the voltage levels +Vdc/2 –Vc and +Vc, -Vc and –Vdc/2 +Vc
are set to the same voltage level of each. That is, Vc is set to Vdc/4. As a result, Vc can be controlled by switchingpattern of (2) and (3) or (6) and (7), respectively.

III.
A.

CONTROL STRATEGYSpace Vector Modulation
In the case of the proposed rectifier, there are 61 kinds of the voltage vectors, except for the charge or discharge+Vdc/2+Vdc/2+Vdc/2+Vdc/2

S1

S1

S1

S1

S2

S2

S2

S2

Vc

Vc

0

Vc

0

S3

S3

S3

S4

S4

S4

(1)

–Vdc/2(2)+Vdc/2–Vdc/2

Vc

0

(5)

S3
S4
–Vdc/2

(6)

S1

S1

S1

S2

S2

S2

S2

Vc

0

Vc

0

Vc

0

S3

S3

S3

S3

S4

S4

S4

S4

(3)

–Vdc/2(4)(a) Positive period of the input voltage.

–Vdc/2(7)–Vdc/20(8)(b) Negative period of the input voltage.

Fig. 3. Current path of the proposed rectifier.

–Vdc/2+Vdc/2+Vdc/2+Vdc/2

S1

Vc

0–Vdc/2

switching patterns to the inner clamping capacitor in the proposed circuit. Firstly, the nearest three space vectors
surrounding at the top of the output voltage vector of the rectifier are selected. Secondly, the output time ratio of
each of the voltage vector is calculated. Finally, the charge or discharge mode vector is selected according to theinner clamping capacitor voltage and the neutral point voltage of the DC output part. Further details of themodulation strategy are provided in ref. [16].
The inner clamping capacitor voltage is controlled by the selection of the switching pattern, since the proposed
rectifier can output the same voltage level using different switching patterns that achieved charge or discharge tothe inner clamping capacitor. For using the SVM, the output time of each switching pattern is managed by thecontroller. The capacitor voltage can be controlled accurately at this point.

B.

Control Block Diagram
Fig. 4 shows the control block diagram for the space vector modulation of the proposed rectifier. The DC output

voltage and the input current are controlled by a PI regulator on a rotating frame, the same as that in a conventional
PWM rectifier. In the switching table, the output vector is determined by the magnitude of the vector, the phase angleof the power grid, and the capacitor voltage controls the conditions by using a hysteresis controller.
Fig. 5 shows the voltage waveform of the rectifier input voltage. It is noted that the zero level of the rectifier input
voltage is defined as the neutral point voltage of the DC output part. Five-step stairs waveform is obtained as therectifier input voltage, which is divided into six sectors by the voltage levels.
Table II indicates the switching pattern table of the proposed rectifier. The inner clamping capacitor voltage iscontrolled by selecting the switching patterns, where it will appears the same voltage to the rectifier input voltage but
the inner clamping capacitor is controlled to either being charged or discharged. For example, in the sector II, when
the rectifier input voltage is +Vdc/2 or +Vdc/4, if the inner clamping capacitor voltage Vc is lower than its command
Vc*, the charge mode (S2 and S4 are turned on) will be selected. On the other hand, if Vc is higher than Vc*, thedischarge mode (S1 and S3 are turned on) will be selected. Thus, the inner clamping capacitor voltage can becontrolled constantly at all sectors.
+

iq*=0
Vdc*

+
_

PI

_

d -q

*

id +

PI

Vdc

1/4

_

a -b

PI

id

va*
vb*

iq

ir
is
it

d -q

vr
vt

q

3

_

_

+

3

Carriervsign+

Vc* 3 +

2
T1,T2

1
0

vin

4 Sr1-4Vector-info.

SVM

SW
table

4S

s1-4

3
3

_

3
Vc

Fig. 4. Control block diagram for the proposed circuit.

4S

t1-4

Additionally, the neutral point voltage of the DC output is controlled by the zero-phase sequence component in thevoltage commands at the power grid frequency as same as the conventional three-level inverter. The switchingpattern including the zero-phase sequence component is selected according to the input voltage polarity due to thelimitation of the current path that is caused by the clamping diodes. For example, when the input voltage is positive,
the switching pattern +0 in Table II will be selected for the zero level to increase the neutral point voltage. On theother hand, when the switching pattern –0 is selected where the input voltage is negative the neutral point voltage will
be decreased. As a result, the DC part capacitor (C3) voltage can be balanced.

IV.
A.

PARAMETER DESIGN METHOD

Inductance of Input Inductor (Lin)
When the switching frequency is higher than the input frequency, the fundamental component of the reactor

voltage assumes to be constant during a switching cycle. Then, the relations between the input inductor Lin and the
input current ripple Δiin can be expressed asiin 

va
1 a / fs w
vL dt  L
Lin 0
Lin f sw

(4)

where
Vconv Vv L  Vm sint   dc  (0  t   / 6)42 Vconv Vv L  Vm sint   dc  ( / 6  t   / 2)2 
 2

where fsw is the carrier frequency, ΔVconv is the input voltage ripple of the rectifier, Vm is the peak voltage of the
input phase voltage.
The duty ratio α for each section is defined as (5) because the rectifier voltage command is a sinusoidal waveform.

 a  2 sinta  2(sint  0.5)

(0  t   / 6)
( / 6  t   / 2)

(5)
TABLE IISWITCHING TABLE OF THE PROPOSED RECTIFIERI

IIIII IV

V

VI

SectorVoltage levelTurn-on switches

I+Vdc/4 , +0

S2-S4 (S1-S3), S3-S4

II+Vdc/2 , +Vdc/4

S1-S2, S2-S4 (S1-S3)

III+Vdc/4 , +0

S2-S4 (S1-S3), S3-S4

IV–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)

V–Vdc/4 , –Vdc/2

S1-S3 (S2-S4), S3-S4

VI–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)+Vdc/2+Vdc/4

t

0
Vdc/4
Vdc/2
Fig. 5. Rectifier input voltage waveform.

Fig. 6 shows the value of vLa when Vm and ΔVconv are defined to 1 p.u. and 0, respectively. Since the input current
ripple is dominated by vLa, the input current ripple Δiin becomes the maximum value at the duty ratio of 0.5 when the
DC voltage Vdc is 1 p.u. Then the input phase angles ωt are sin-1(1/4), or sin-1(3/4). Note that if the DC voltage ischanged, the peak position of vLa

is only shifted to right and the peak value does not change as shown in Fig. 7.

Consequently, the maximum input current ripple Δiin can be expressed as

V
V
3
1
iin  Vm sin(sin1 )  ( dc  conv )42
2
2 Lin f sw


V
V
3
1
Vm  ( dc  conv )42
2
2 Lin f sw

(6)

Therefore, Lin can be designed byVV
31Vm  ( dc  conv )42
2
2iin f sw

Lin 

(7)

Thus, the input reactor can be reduced by increasing the current ripple Δiin and the switching frequency fsw.

B.

Capacitance of Inner Clamping Capacitor (C1)
The variations of the output voltage are ±Vdc/2, ±Vdc/4, and 0. Note that ±Vdc/4 levels are outputted through theinner clamping capacitor C1. The maximum output time of ±Vdc/4 levels can be expressed as

Tsw _ max  1/ f sw

(8)Consequently, the maximum voltage ripple of C1 is given byVc 

iin _ peak  iin
1 Ts w_ max
iin _ peak  iin dt 
0
C1
C1 f sw(9)where iin_peak is the peak of the input current.
Practically, the peak current includes the ripple components. Therefore, the capacitance of C1 is decided by (10)from (9).
C1 

iin _ peak  iin
Vc f sw

(10)

where Δiin is the ripple current.

0.15

1.2

vLa

0.1

1.5

[p.u.]
0.05
0

Vdc=1.00

π/8

π/4
ωt [rad]

3π/8

π/2

Fig. 6. Input current ripple Δiin and phase angle of input voltage.

As shown in (10), the capacitance of C1 can be reduced by increasing the switching frequency and the allowance
voltage ripple ΔVc.

C.

Capacitance of DC part Capacitor (C3)
At first, the quantity of the electric charge flows into the neutral point should be calculated in order to design thecapacity of C3. The relations between the voltage level and the current at the neutral point are shown in Table III. It isnoted that the selected switching pattern depends on the phase angle of the input voltage. For example, the quantity ofthe electric charge which flow into the neutral point from R phase is expressed as following equations.
Qc 3 _ 030  

Ts / 120

Qc 3 _ 3060  

Ts / 6Ts / 12I m sint ( D0 _ 030 

I m sint (DVdc / 4 _ 030

DVdc / 4 _ 3060
2

2

)dt

(11)

)dt

(12)

where Ts is a period of the input voltage, Imsinωt is the input current of R-phase, D is the duty ratio. The subscripts
indicate the voltage level and the phase angle of the input voltage. It should be noted that duty ratio for 0 to 30° on
Vdc/4 level is used as a half of the original value because almost half of this period does not flow the current into theneutral point.
The rectifier voltage command is formed in sinusoidal, and then it can be defined as 100% at 0° and 0% at 30°
while outputting voltage level. At Vdc/4 output voltage level, the rectifier voltage command can be defined as 100% at
30° and 0% at 90°. Consequently, the duty ratio of each area can be expressed as
D0 _ 030  1  2 sint

DVdc / 4 _ 030  2 sint
DVdc / 4 _ 3060  2(1  sint )

(13)
(14)
(15)

The quantity of the electric charge Qnp from 0 to 60° region can be expressed by (16).
Qnp  2(Qc 3 _ 030  Qc 3 _ 3060 )

Ts / 60

 Im (

I m sint (1  sint )dt

4 3 1
 )Ts
16
12

(16)

On the other hands, the DC output voltage ripple is generated at six times of the input voltage frequency. Then, themaximum quantity of the rectifier input electric charge (Qin_R, Qin_T) can be expressed by (17), (18) for a half cycle ofthe output voltage ripple, i.e. Ts/12.

Qin _ R  

Ts / 120

I m sint dt

Im 
T

  cos s  1

12


(17)

Qin _ T  

Ts / 12

0



4 

I m sin t   dt
3 


Im 
 T 4  1   cos s       12 3  2 (18)

Qout is the quantity of the electric charge which is supplied to the load.
I loadTs
12

Qout 

(19)

where Qout is the DC output current.
Therefore, the quantity of the electric charge which flow into the neutral point at the interval of Ts/12 is expressedasQC 3  2(Qin _ R  Qin _ T )  3Qnp  Qout  1 8  3 3  I load  I m  

Ts


2
8

12



 


(20)

Note that Ts/12 is equal to /6. Next, the DC output voltage ripple ΔVdc can be expressed as (21) with the input
current ripple Δiin .

Vdc 

i
1(3 in  2QC 3 )
C2
f sw

(21)

Finally, the capacitance of C3 can be calculated.
C3 


i
1
(3 in  2QC 3 )
Vdc
f sw
  1 8  3 3  I  
1  iin  load Ts 
3
 2 I m  2Vdc  f sw
8  12  



 


(22)

As shown in (22), the capacity of C3 can be reduced by increasing voltage ripple ΔVdc and the switching frequency
fsw.

D.

Capacitance of Clamping Capacitor (C2)
The capacitance of C2 depends on the voltage fluctuation of the neutral point voltage at the DC link part. The
TABLE III
VOLTAGE LEVELS AND CONNECTION TO NEUTRAL POINT
Phase angle ofCurrent toVoltage level

input voltage

neutral point
0

Active+Vdc/4 (C1 Charge / Discharge)

Active/inactive+Vdc/4 (C1 Charge / Discharge)

Active/inactive+Vdc/2

Active0-30°30-60°

relations between the voltage ripple of the neutral point ΔVnp and C2 can be calculated from the quantity of theelectric charge flowing into the neutral point (Qnp), as expressed by (23).
Vnp 

Qnp
C2  C3



Vdc
2

(23)

As a result, the capacitance of C2 can be calculated by (24) from (23).

C2 

Im
4 3 1(
 )Ts  C3
2Vnp  Vdc
8
6

(24)

As shown in (24), the capacitance of C2 can be reduced by increasing the voltage ripple of neutral point ΔVnp.

V.

EXPERIMENTAL RESULT

Fig. 7 shows the operation waveforms for the proposed rectifier. The input voltage is 200 V, 50 Hz, the output
power is 1 kW (rating), and the DC output voltage command is set to 320 V, that is, the inner clamping capacitor
voltage command is set to 80 V (the circuit parameter is the same as Table IV). Sinusoidal input current waveforms
with THD of 3.4% is obtained (the 40th or less order components harmonics were considered). In addition, the DC
output voltage and the inner clamping capacitor voltage agrees with commands of that respectively. In Fig. 7, a
five-step voltage waveform is observed in the rectifier input voltage of the proposed converter, which agrees with the
expectation. It should be noted that the spike voltage in the rectifier input voltage is caused by the commutation of thediode at the edge of the sectors. However, each switching of the device voltage is clamped by the inner or outerclamping capacitor. Therefore, the low voltage rating switching device can be used as discussed in previous chapter.
Fig. 8 shows the harmonic analysis of input current. Each harmonic component is less than 2% which is complying
with IEC61000-3-2 standards.
Fig. 9 shows the load step response. A load is changed at the dotted line from 0.5 kW to 1.0 kW. The input current
is increased to twice of it. However, the DC output voltage and the inner clamping capacitor voltage are kept inconstant. Therefore, the load regulation characteristic is confirmed by this experimental result.
Fig. 10 shows the voltage ripple of the inner clamping capacitor and the rectifier input current ripple. Fig. 11
shows the voltage ripple of the DC output and the neutral point. The parameters are designed by the optimal design
methods which are discussed in section III. The results shown in Table V are accurately matched with the design
parameters.

Fig. 12 shows the efficiency and input power factor of the proposed rectifier. The maximum efficiency is 97.6% at
a 0.5 kW load, and an input power factor of over 98% is achieved at over 0.5 kW load. The proposed circuit canobtain efficiency of over 97% in a wide load condition because the switching frequency of the outer diode is the sameas the power grid frequency even if that of the inner switching device is high.
Fig. 13 shows the input current THD of the proposed rectifier. The proposed rectifier achieves 3.4% THD for the
input current. It should be noted that the THD increases in the light load condition because the magnitude of theharmonics component is almost constant. Therefore, the ratio between the fundamental and harmonics component
becomes larger in the light load condition
Fig. 14 illustrates the loss analysis result for a 1 kW load. The power loss is composed by linking a circuit
simulator (PSIM, Powersim Technologies Inc.) and a DLL (Dynamic Link Library) file. The DLL file contains a loss
table that calculates the switching loss and conduction loss based on the instantaneous values of the current and thevoltage of the power device, as written in [13]. This method can estimate the power semiconductor loss in any kind of
circuit configurations. The loss simulation results are well agreed with the efficiency from the experimental results. In
the proposed circuit, the conduction loss is the most dominant section of the power losses. In order to improve theefficiency, a low conduction loss device should be selected.

TABLE IVPARAMETERS OF THE PROPOSED RECTIFIER
Output power

1 [kW]

Input voltage

200 [V]

Input frequency

50Hz

Output voltage command (Vdc*)

320 [V]

Load resistance(RL)

100 []Inner clamping capacitor(C1)47 [F]

Clamping capacitor(C2)100 [F]

DC part capacitor(C3)220 [F]

Carrier frequency

10 [kHz]

Input inductor (Lin)2 [mH]

Input voltage [250V/div]0
Input current [5A/div]0

DC output voltage [250V/div]0
Inner clamping capacitor (C1) voltage[100V/div]
100
100

Content rate [%]0
Rectifier input voltage [250V/div]

0

10
10

11

0.1
0.1

10ms

Fig. 7. Experimental results of the proposed rectifier at a 1 kW.

01

3

5

7

9

10
11 13 15 17 19 20
21 23 25 27 29 30
31 33 35 37 39 40
41
Harmonic number

Fig. 8 Harmonic current analysis at 1kW.

Input voltage [250V/div]0
Input current [5A/div]0
DC output voltage [250/div]

0.5kW

0

1kW

Inner clamping capacitor (C1) voltage [100V/div]0

20ms

Fig. 9. Experimental result of load step response
DC output voltage (Vdc) [V]

2.5V/div

3.1V

320

85.7

Flying capacitor voltage (VC1) [V]

Neutral point voltage (Vnp) [V]
5V/div

9.4V

5V/div

160

80
74.3

Input current (iin) [A]Input current (iin) [A]
5A/div

0

5A/div

500mA/div

4ms

0
400s

4ms

Fig. 10. Experimental result of the inner clamping capacitor

Fig. 11. DC output voltage ripple and neutral point

voltage ripple and the input current ripple.

voltage ripple.

TABLE V
THEORETICAL AND EXPERIMENTAL RESULT OF THE RIPPLES.
Parameters

Equation

Theoretical

Experimental

Remarks

iin

(6)

1.1 A

1.0 A

Vconv = 7 V

VC

(9)

11.4 V

11 V

Vdc

(21)

3.1 V

3.0 V

Vnp

(23)

9.4 V

9.2 V

12.5

Input current THD [%]Efficiency andinput power factor [%]100
Input power factor

99
98

Efficiency
97
96
0.2

0.4

0.6 0.8 1.0 1.2
Output power [kW]

1.4

1.6

10.0
7.5
5.0
2.5
0
0.2

Fig. 12. Input power factor and efficiency of the proposed rectifier.

0.4

0.6 0.8 1.0 1.2
Output power [kW]

1.4

1.6

Fig. 13. Input current THD of the proposed rectifier.

Loss 2.4%
Efficiency 97.6%

Recovery loss 32.8%
Conduction loss 65.3%
Turn-on loss 1.5%
Turn-off loss 0.4%
0Fig. 14. Loss analysis results by loss simulation at a 1 kW load.

VI. CONCLUSIONS
A novel five-level PWM rectifier and its control strategy have been proposed. Features of the proposed circuit are
the following; number of reduction of the switching devices, and a controllable clamping capacitor voltage. The
proposed converter achieves THD of 3.4% for the input current at a 1 kW load and efficiency of 97.6% at a 0.5 kW
load for a 1 kW class experimental setup.

REFERENCES[1] B. Singh, B. N. Singh, and A. Chandra, et al, “A Review of Three-Phase Improved Power Quality AC-DC
Converters”, IEEE Transactions on industrial electronics, vol.51, no.3, pp.641-660, 2004.
[2] J. Rodriguez, L. G. Franquelo, and S. Kouro, et al : “Multilevel Converters: An Enabling Technology for
High-Power Applications”, Proceedings of the IEEE, vol.97, no.11, pp.1786-1817, 2009.
[3] U. Drofenic, J. W. Kolar, Y. Nishida, Y. Okuma, and J. Sun, “Three-Phase PFC Rectifier Systems“, PCC-Osaka
2002 Tutorials, pp.2-93, 2002.
[4] X. Yuan, I. Barbi, “Fundamentals of a New Diode Clamping Multilevel Inverter”, IEEE Transactions on powerelectronics, vol.15, no.4, pp.711-718, 2000.
[5] Z. Pan, F. Z. Peng, and K. A. Corzine, et al, “Voltage Balancing Control of Diode-Clamped MultilevelRectifier/Inverter Systems”, IEEE Transactions on industry applications, vol.41, no.6, pp.1698-1706, 2005.
[6] A. A. Sneineh, M. Wang, “Novel Hybrid Flying-Capacitor -Half-Bridge 9-Level Inverter”, TENCON 2006.
[7] X. Kou, K. A. Corzine, and Y. L. Familiant, “A Unique Fault-Tolerant Design for Flying Capacitor Multilevel
Inverter”, IEEE Transactions on power electronics, vol.19, no.4, pp. 979-987, 2004.
[8] D. Kang, Y. Lee, B. Suh, C. Choi, and D. Hyun, “An Improved Carrier-Based SVPWM Method Using Leg
Voltage Redundancies in Generalized Cascaded Multilevel Inverter Topology”, IEEE Transactions on powerelectronics, vol.18, no.1, pp. 180-187, 2003.
[9] F. Z. Peng, J, W. McKeever, and D. J. Adams, “A Power Line Conditioner Using Cascade Multilevel Inverters
for Distribution Systems”, IEEE Transactions on industry applications, vol.34, no.6, pp. 1293-1298, 1998.
[10] F. Z. Peng, “A Generalized Multilevel Inverter Topology with Self Voltage Balancing”, IEEE Transactions on
industry applications, vol.37, no.2, pp. 2024-2031, 2001.
[11] Natchpong Hatti, Kazunori Hasegawa, and Hirofumi Akagi, “A 6.6-kV Transformerless Motor Drive Using a
Five-Level Diode-Clamped PWM Inverter for Energy Savings of Pumps and Blowers”, IEEE Transactions on
power electronics, vol.24 No.3, pp. 796-803 2009.
[12] Maryam Saeedifard, Reza Iravani, and Josep Pou, “A Space Vector Modulation Strategy for a Back-to-Back
Five-Level HVDC Converter System”, IEEE Transactions on industrial electronics, vol.56 No.2, pp. 452-466
2009.
[13] Jun-ichi Itoh, Takashi Iida, and Akihiro Odaka, “Realization of High Efficiency AC link Converter System
based on AC/AC Direct Conversion Techniques with RB-IGBT”, Industrial Electronics Conference, Paris,
PF-012149, 2006.
[14] Dae-Wook Kang, Byoung-Kuk Lee, and Jae-Hyun Jeon, et al “A Symmetric Carrier Technique of CRPWM for
Voltage Balance Method of Flying-Capacitor Multilevel Inverter”, IEEE Transactions on industrial electronics,
vol.52 No.3, pp. 879-888 2005.
[15] Chunmei Feng, Jun Liang, and Vassilios G. Agelidis, “Modiﬁed Phase-Shifted PWM Control for Flying
Capacitor Multilevel Converters”, IEEE Transactions on power electronics, vol.22 No.1, pp. 178-185 2007.
[16] Jun-ichi Itoh, Yuichi Noge, and Taketo Adachi, “A novel five-level three-phase PWM rectifier using 12
switches”, Energy Conversion Conference and Exposition, San Jose, CA, pp3100-3107, 2009.

Jun-Ichi Itoh was born in Tokyo, Japan, in 1972. He received the M.S. and Ph.D. degrees in electrical andelectronic systems engineering from Nagaoka University of Technology, Niigata, Japan, in 1996, 2000,
respectively.
From 1996 to 2004, he was with Fuji Electric Corporate Research and Development, Ltd., Tokyo, Japan.
Since 2004, he has been with Nagaoka University of Technology, Niigata, Japan as Associate Professor.
His research interests are matrix converters, dc/dc converters, power factor correction techniques andmotor drives.
Dr. Itoh received the IEEJ Academic Promotion Award (IEEJ Technical Development Award) in 2007 and the Isao Takahashi
Power Electronics Award in 2010. He is member of the Institute of Electrical Engineers of Japan.

Yuichi Noge was born in Wakayama, Japan, in 1987. He received the B.S. degrees in electrical, electronics
and information engineering from Nagaoka University of Technology, Nagaoka, Japan, in 2008
respectively.
Since 2008, he has been with Nagaoka University of Technology as a master student. His main researchinterests are multilevel power converters.
Mr. Noge is a member of the Institute of Electrical Engineers of Japan.

Taketo Adachi was born in Miyagi, Japan, in 1984. He received the B.S. and M.S. degrees in electrical,
electronics and information engineering from Nagaoka University of Technology, Nagaoka, Japan, in 2007
and 2009 respectively.
Since 2009, he has been An employee of Fuji Electric FA Components & Systems Co., Ltd and memberof IEEJ.
His main research interests are multilevel power converters.