A control method to reduce a surge voltage ofindirect matrix converter by using zero current
and zero voltage switchingJun-ichi Itoh
Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Toshifumi Hinata

Koji Kato

Student Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japan

Student Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japan

Abstract— This paper proposes a method to decrease the surge
voltage for indirect matrix converter (IMC) by implementing acontrol method which combines the zero current (ZCS) andthe zero voltage switching (ZVS). In the high power
applications, the wiring in the DC link parts of the converter
contains of a large parasitic inductance. Then a large surge
voltage is appearing as a problem at the inverter stage. In the
proposed method, the standard value of the surge voltage in
the inverter stage becomes zero by enable the zero vector modeof the current source rectifier. Therefore, the peak value of thesurge voltage can be decreased. The basic operation andvalidation of the proposed method are confirmed
experimentally. As a result, the surge voltage at a generation ofa zero vector could be decreased by approximately 30 % from450 V to 312 V. By applying the proposed method, a highpower converter can use a smaller size snubber circuit and at
the same time achieves high reliability.

I.

INTRODUCTION

Recently, interface power converters for renewableenergy and hybrid electric vehicle systems have been studied
intensely. Various power sources can be applied in thissystem, for example, the AC power sources are such as windturbine, generators; and the DC power sources are such as
photovoltaic cells, batteries, and fuel cells. The conventional
power converter system composed of AC-DC, DC-DC and
DC-AC converters requires numbers of large energy buffers,
such as electrolytic capacitors. However, the electrolytic
capacitors in the conventional system have problems in termof size, life-time and costs.
On the other hand, the IMC has been actively studied [1-4]
to solve the problems. That is, the IMC has many advantages
such as small size and long life-time in comparison with theback to back system because the IMC has no large energy
storage; the electrolytic capacitor. The IMC for three-port
converters using a simple control method based on theindirect control method with a triangular carrier wave [5] has

978-1-4577-0541-0/11/$26.00 ©2011 IEEE

been investigated [6]. However, in the high power
applications where numbers of DC-DC converters areconnected to the DC link part of the IMC, the DC bus bar
becomes longer and the inductance is increasing depends on
the bus bar structure. Additionally, the inductance of the DC
link wiring is greatly affecting the surge voltage occurs on theswitching devices since the IMC is lack of DC link capacitor.
Therefore, in the high power interface applications,suppression of the surge voltage and the DC link inductanceare important issues.
In general, laminated bus bars [7] and snubber circuits areused as solutions to suppress the surge voltage. However,laminated bus bars still has a problem, that is, high power
converters increase not only the DC link inductance but also
the output current. Particularly, the minimum length of theDC bus is dominated by the module size in high power
converter. Besides, the input capacitor in IMC takes role in
the lossless snubber capacitor in the conventional inverter.
However the bar length between an input capacitor to an
inverter module becomes longer than the length between a
DC link capacitor to an inverter power module in theconventional converter.
The snubber circuit is applied to the IMC to suppress thesurge voltage. However, the snubber loss increases especiallyin the high power IMC due to difficult to archive low parasitic
inductance. As a result, the size, the cost and reliability are
increased. So the suppression of the surge voltage by applying
a control method becomes more effective.
This paper demonstrates a control method to reduce thesurge voltage in the IMC. In the proposed method, the peakvalue of the surge voltage is suppressed by adding a zero
vector mode of the current source rectifier. The proposed
method focuses on suppressing the surge voltage happening at
the generation of zero vectors which causes large surge
voltages. In chapter II, the circuit configuration of the IMC
and the occurrence of the surge voltage at the zero vectors are1385

Input filter

Figure 1: Basic concept of an AC and DC interface converter
systemVoltage source
inverter

Voltage source
rectifierSrp SspStp

Sup Svp Swp
U
V

R
S
T

W

Srn Ssn

Sun

Stn

DC/DC
converter(a) Current pathway transitions.

Sbp
Sbn

M

(b) Equivalent circuit (State 1).

Svn Swn

Bp
Bn

BatteryLbvbatt

Figure 2: BTB system with DC/DC converter

Input filter(c) Equivalent circuit (State 2).
Figure 4: Conventional control method

Figure 3: Indirect matrix converter with DC/DC
converterpresented. In chapter III, the mechanism of the proposed surge
voltage suppression is described. The basic operation andvalidation of the proposed method are confirmed byexperimental results in chapter IV. As a result, the surge
voltage which is often occurring at the generation of zero
vectors could be decreased by approximately 30% from 450
V to 312 V.
II.

CIRCUIT CONFIGURATION AND OCCURRENCE OF
SURGE VOTLAGE

Fig. 1 shows the basic concept of an AC and DC interface
converter system. As shown in Fig. 1, numbers of DC-DC
converters are connected to the DC link part in theapplication. The DC bus bar becomes longer and theinductance increases. Then, the large surge voltage ishappening during the switching. Furthermore, the surge
voltage becomes high because the DC link current increased.
Wiring inductances between switching devices in therectifier or the inverter can be decreased by using 6-in-1
modules. However, the inductances of the DC bus bars
depend on the configuration of AC and DC interface
converter system.
Fig. 2 shows a three-port interface converter configured
by a back to back converter system (BTB system). Thissystem consists of voltage source rectifier and voltage source
inverter and a DC power source. The boost up inductances at
the input side and the large capacitor at the dc link part are thecomplimentary components for this circuit. The size of the
BTB system becomes large and heavy. Furthermore, thelifetime of the electrolytic capacitor depends on the ambient
temperature of the circuit. So, the maintenance of the system
may be needed due to the application.
Fig. 3 shows a three-port interface converter for theenergy management system [6]. This system consists ofcurrent source rectifier, the voltage source inverter and a DC
power source. This circuit achieves smaller size and longer
life-time compared to the conventional BTB systems because
the large energy buffer components are not necessary.
However, in high power applications, the surge voltage
will increase at the inverter stage because of the IMC has not
the DC link capacitor to absorb the wiring inductance.
Fig. 4 shows the current pathway of the conventional
control method; zero current switching (ZCS). The dotted line
(State 1) in Fig. 4(a) shows the current pathway when the IMC
supplies electric power from the source (RST side) to the1386Carrier

Rectifiercarrierandcommandirec*

vu*
Inverter carrier *and command vv *
vw
Srp
Ssp
Stp
Rectifier
Srn
gate
Ssn
pulse
Stn

(a) Step 1.

Sup
Svp
Swp

Inverter
gate
pulse

(r-t)

(110) (100)DC
linkvoltag
e

vdc

DC
link
current

idc -iw

(0-0)

(s-t)

(0-0)

(000)

(100) (110) (100)

(000)

vrt

(r-t)

(100) (110)

vrt

vst

(b) Step 2.
iu

iu

A

-iw

iu

iu

B

A B

Zero vector

Zero vector-iw

Figure 6: Switching pattern of proposed method.

The surge voltage occurs when an IGBT is switchedbecause the freewheeling path for the inductive energy in theparasitic inductance disappears. In particular, when thecurrent in the DC link part is completely interrupted as shownin Fig. 4(c), the largest surge voltage occurs at the switching
device of the inverter stage. Therefore, the surge voltage at thezero vector modes needs to be suppressed.

Input filter(c) Step 3(surge voltage occurs).

III.

Input filter(d) Step 4.

(e) Step 5.
Figure 5: Commutation sequence of proposed method.

load. The solid line (State 2) in Fig. 4(a) shows the current
pathway, which is the zero vector mode. In this mode, thepower supply does not connect to the load. Fig. 4(b) shows theequivalent circuit of State 1 and Fig. 4(c) shows the equivalentcircuit of State 2. The equivalent circuits of the IMC can be
expressed by two step-down DC-DC converters. When boththe switches of two DC-DC converters are turned-on, therectifier (or the inverter) supplies the electric power to theload. However, when the switch of one of the DC-DC
converter is turned-off, the IMC does not supply electric
power.

SURGE VOLTAGE SUPPRESSION BY
PROPOSED METHOD

Fig. 5 shows the commutation sequence of the proposed
method. In the proposed method, the peak value of the surge
voltage is suppressed by adding the zero vector mode of thecurrent source rectifier between step 1 and step 3 as shown in
Fig. 5. First, when the IMC changes from the mode step 1 tostep 3, the rectifier outputs the zero vector mode by turn off
one leg in step 2 as shown in Fig. 5(b). The DC link voltage
becomes zero because of the zero vector mode of the rectifier
stage. Next, the inverter stage outputs the zero vectors asshown in Fig. 5(c). In this transition, the current in the DC link
wiring is interrupted, so the surge voltage occurs at theswitching device in the inverter stage. However, the peakvalue of the surge voltage is suppressed because the DC link
voltage is zero. This is the main point of the proposed
commutation strategy. Next, the rectifier stage changes to thenext switching pattern as shown in Fig. 5(d). The zero current
switching is achieved in the rectifier stage because the output
current is flowing within the inverter stage. Finally, the IMC
goes back to the normal condition as shown in Fig. 5(e).
Fig. 6 shows the switching pattern of the proposed
method. The basic control strategy is referred to Ref. [1,6].
Area “A” refers to the zero vector period of the rectifier stage.

1387

Figure 7: Control block diagram of proposed method.

In this period, The DC link voltage is zero. ZVS is achievedby switching the inverter stage in this period. Area “B”
represents the zero vector period of the inverter stage.
In the proposed method, the rectifier stage implements
the hard switching when outputs the zero vector modes. So
the switching loss occurs at rectifier stage. However, inverter
stage achieves ZVS simultaneously; as a result, the total loss
remains low in the proposed method.
Fig. 7 shows the block diagram of the proposed method.
The basic modulation method is same as the conventional
control method in the IMC. First, the ripple of the DC link
voltage is calculated from the input voltage detection. For
PWM in the rectifier stage, the symmetry carrier and a
modulation function which designed for the single leg
modulation are used. On the other hand, in the inverter stage,
the asymmetry carrier and a modulation function which
compensated the ripple of the DC link voltage are used. The
asymmetry carrier for the inverter stage is calculated to output
the zero vectors at the switching timing of the rectifier stage.
In the proposed method, the ZVS for the inverter stage
achieves at only zero vector mode of IMC. After the pulse
width modulation, the switching sequence is changed toproposed pattern as shown in Fig. 6 on FPGA.
IV.

EXPERIMENTAL RESULTS

The IMC for the three-port converter as shown in Fig. 3 is
implemented with the proposed method for experiment tests.
In the experimental setup, the AC source is connected to therectifier stage as an input power, and a R-L load is connectedto the inverter stage as a load. Table 1 shows experimental
parameters.
Fig. 8 shows the fundamental operation waveform of the
proposed control method. From Fig. 8, clear sinusoidal
waveforms obtained on the input side and the output side
confirms the validity of the proposed method.

Fig. 9 shows the comparison of the efficiency
characteristics. In this experiment, a DC-DC converter is notconnected. For the conventional control method, themaximum efficiency of the IMC is 94.6 %. On the other
hand, the maximum efficiency of the proposed method is94.5 %. The proposed method can apply without decreasing
the efficiency because the inverter stage achieves ZVS as
described in chapter III. Note that the efficiency of 1 % to 2 %will be improved by applying reverse blocking IGBT in therectifier stage.
In addition, for the IMC, the percentage of the
conduction loss is larger than the percentage of the switchingloss because ZVS or ZCS is applying. Therefore, in the caseof constant output power, the efficiency of the higher voltage
condition will be higher than that of the higher current
condition. However, at the higher modulation factor in the
proposed method, the output voltage waveform becomes
distortion because the zero vector periods of the rectifier
stage are outputted constantly to achieve the ZVS for the
inverter stage. So, the output voltage of approximately 140 V
is selected in the experiments. The output voltage waveform
will improve by applying voltage error compensations. As aresult, the efficiency will be improved.
Next, an experiment was conducted to confirm thereduction effect of the surge voltage. In this experiment, thesnubber circuit did not connect to the DC link part so that an
actual surge voltage could be read.
Table 2 shows experimental parameters. The wiring
inductance of 3.78 μH is inserted in DC link part to confirm
the proposed method. The low input voltage is used because
the maximum surge voltage needs to constantly maintain at
600 V due to the power device voltage rating even if the
proposed method is not applied. The output current is adjusted
by the output resistance Rout.
Fig. 10 shows the experimental results when the output
current is 7 A. For the conventional control method as shown

1388

Table 1: Experimental parameters forbasic operation.
Input line voltage
Input frequency
Output line voltage
Output frequency
Output DC voltage
Commutation timeCut-off frequency of
input filter
AC LoadDC Load200 [Vrms]
50 [Hz]140 [Vrms]
30 [Hz]
100 [V]2 [μs]
1.1 [kHz]
R
L
R
L

12.5[Ω]
3 [mH]
33 [Ω]
5 [mH]

Table 2: Experimental parameters formeasurement of surge voltage.

Figure 8: Experimental results with DC/DC converter.

Efficiency[%]

Input line voltage
Input frequency
Output frequency
Commutation time
Carrier frequency
Load inductance Lout
DC link inductance Ldc

Figure 9: Comparison of efficiency characteristics.

in Fig. 10(a), the large surge voltage occurs at the inverter
stage IGBT. It should be noted that the large surge voltage
occurs only at the upper side IGBT because the zero vector
mode of the inverter stage is generated by the lower side.
Therefore, in the lower side IGBT, the surge voltage at thezero vectors is not generated. For the proposed method asshown in Fig. 10(b), the surge voltage which occurs at thezero vectors is successfully suppressed. The peak value of thesurge voltage for the upper side IGBT is almost equivalent to
the peak value of the lower side IGBT.
Fig. 11 shows the comparisons between the conventional
control method and the proposed method.
For theconventional control method, the large surge voltage occurs
when the inverter stage outputs the zero vector modes asshown in Fig. 11(a) because the current in the DC link wiring
is interrupted suddenly. The peak value of the surge voltage is
450 V. On the other hand, the proposed method suppresses thesurge voltage when the inverter stage outputs the zero vector
as shown in Fig. 11(b). The peak voltage of the surge voltage
is 312 V. By applying the proposed method, the surge voltage
could be suppressed by approximately 30 %.
Fig. 12 shows the enlarged figure of the proposed method.
The DC link voltage becomes zero by outputting the zerocurrent vectors of the rectifier stage at point “A” as shown in
Fig. 12. After that, the switching device of the inverter stage
turns off at point “B” shown in Fig. 12. The inverter stage
achieves ZVS because the DC link voltage is zero.

70 [Vrms]
50 [Hz]30 [Hz]
2 [μs]
5 [kHz]
5 [mH]
3.78 [μH]

At point “B”, the large surge voltage occurs because theDC link current is interrupted. However, the standard value of
the DC link voltage is zero. Therefore, the proposed method
decreases the peak of the DC link voltage compared with theconventional method. From the experimental results, theverification of reduction on the surge voltage can be
confirmed.
Fig. 13 shows the enlarged figure at the point where thesurge voltage is the largest in Fig. 10(b). In Fig.13, the peak of
the surge voltage at zero vector periods can be decreased byapplying the proposed method. However, the peak value ofthe surge voltage for the non-zero vector periods is more than
312 V. This proposed method focuses on the surge voltage at
the generation of zero vector modes. Therefore, other than the
period of zero vectors, the proposed method cannot decrease
the peak value.
Fig. 14 shows the characteristics of the maximum voltage
between the corrector and the emitter of the IGBT in the
inverter stage. The maximum voltage for the switching
device is increasing with the increasing output current.
For the conventional control method, the surge voltage atthe zero vector modes is appearing as the maximum voltage.
On the other hand, by applying the proposed method, thesurge voltage at the zero vector modes is suppressed.
Therefore, the surge voltage occurring outside the zero
vector modes is appearing as the maximum voltage in the
proposed method.
For these reasons, the proposed method can decrease thepower loss at the snubber circuit, but the effect of decreasing
the peak voltage value is smaller in an output cycle.
Therefore, the reduction of capacitance in a snubber circuitmight not significant. For achieving the reduction of snubber
capacitance, the suppression of the surge voltage at any
switching in the inverter stage may be needed.

1389

10[ms/div]

Upper
IGBT
Vce [V](Swp)
100 [V/div]
0

Lower
IGBT
Vce [V](Swn)
100 [V/div]0(a) Conventional method.
(b) Proposed method.
Figure 10: Collector-emitter voltage of inverter stage IGBT.
20[ s/div]

Upper
IGBT
Vce [V](Swp)

312[V]

100 [V/div]0

Zero vector

Zero vector

Lower
IGBT
Vce [V](Swn)
100 [V/div]0(a) Conventional method.
(b) Proposed method.
Figure 11: Enlarged figure of zero vector mode.

The proposed method focuses on suppressing the surge
voltage happening at the generation of zero vectors. During
the zero vectors, the surge voltage is very high because theDC link current changes differently before and after theswitching pattern.
The basic operation and validation of the proposed
method are confirmed by experimental results. As a result, thesurge voltage at generation of the zero vectors could bedecreased by approximately 30 % from 450 V to 312 V.
In future works, the surge voltage will be suppressed byapplying the ZVS for all switching in the inverter stage withthe aim of the downsizing the size of snubber capacitance.
This study was supported by Industrial Technology Grant
Program in 2009 from New Energy and Industrial
Technology Development Organization (NEDO) of Japan.

Figure 12: The moment of the ZVS.

V.

CONCLUSIONSREFERENCES

This paper demonstrates a control method to reduce thesurge voltage of the IMC at the inverter stage. In applications
where numbers of DC/DC converters are connected to the DC
link part of the IMC, the DC bus bar becomes longer and theinductance increases. Then, the large surge voltage happens
while switching.

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[2]

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Conventional method ( )

450
400
350
300

Proposed method ( )

250
200

1

Figure 13: The largest surge voltage of proposed method.
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2

3

4
5
6
7
8
Output current [A]Figure 14: Peak voltage – Output current characteristics.