Current Stress Reduction for DC-link Capacitors ofThree-phase VSI with Carrier-based Continuous PWM
Koroku Nishizawa, Student Member, IEEE, Jun-ichi Itoh, Senior Member, IEEE,
Akihiro Odaka, Akio Toba, Hidetoshi Umida, Member, IEEE, and Satoru FujitaAbstract -- This paper proposes a novel continuous PWM(CPWM) method to reduce DC-link current harmonics in voltage
source inverters (VSIs) over wide range of load power factor. This
modulation method contributes to a current stress reduction of
DC-link smoothing capacitor and a suppression of its
temperature rise. Furthermore, a high cost digital hardware suchas a field-programmable gate array (FPGA) is not necessary
because this modulation is implemented with only one carrier.
The DC-link current harmonics are reduced by shifting voltage
references in every half control period to reduce a fluctuation of
the DC-link current around its average value. Experimental
results confirm that the application of the proposed CPWM
reduces the DC-link current harmonics by 24.2% at most andlowers an equilibrium capacitor temperature by 6.0℃ comparedto the conventional CPWM.
Index Terms—Two-level voltage source inverter, DC-link
capacitor, Inverter DC-link current harmonics, Continuous PWM

I.

INTRODUCTION

Three-phase AC motors are widely used in both industrial
and household applications [1]–[8]. A lifetime extension of the
AC motor drive systems has been actively researched for a
decade [9]–[14]. The employment of film capacitors in theDC-link part of the three-phase voltage source inverter (VSI)
instead of electrolytic capacitors, of which lifetime expectancy
is short, is one of the solution for the lifetime extension. On theother hand, the maximum allowable temperature of polypropylene, a dielectric material of the film capacitor, is 105℃
[15]; thus, the suppression of its temperature rise is important.
It is possible to suppress the temperature rise of the DC-link
capacitors by reducing the DC-link current harmonics of VSIs.
So far, several modulation methods of VSI which reduce theDC-link current harmonics have been proposed [10]–[14].
With a space vector PWM (SVPWM) presented in [13],voltage space vectors are selected in order that the zero vector
period is shortened to minimize the DC-link current harmonics.
Furthermore, this SVPWM adapts to the variation of the load
power factor by changing the applied voltage space vectors
according to polarities of inverter output phase currents.
However, the employment of the SVPWM leads to a constraintof digital hardware, i.e. the requirement of high cost hardware
such as field-programmable gate array (FPGA).
As another approach to reduce the DC-link current
harmonics, a new single-carrier-comparison discontinuous

PWM (DPWM) has been presented in [14]. In this DPWM,
voltage references of the classic DPWM are shifted at both thepositive-peak and negative-peak of a triangular carrier toreduce the DC-link current harmonics, and only one carrier isused for comparison. Thus, this DPWM can be implemented
with the general-purpose micro-computer. However, theDPWM strategy faces challenging disadvantage compared tocontinuous PWM (CPWM); in particular, the number ofswitching transition per control period in the DPWM is lessthan that in the CPWM. This leads to an increase of the AC
motor noises due to a high inverter output voltage harmonics.
Therefore, the applications of the DPWM are limited.
This paper proposes a novel carrier-comparison CPWM
which uses only one carrier to reduce the DC-link current
harmonics. This modulation method contributes the current
stress reduction of the smoothing capacitor in the motor drive
system and can be implemented with the general-purpose
micro-computer. In particular, three phase continuous voltage
references are shifted in every half control period to reduce thefluctuation of the DC-link current around its average value. By
optimizing the shifting manner of the voltage references, it ispossible to reduce the DC-link current harmonics over entire
region of the load power factor. One more contribution of thisCPWM is to overcome the problem of the DPWM, such aslarge inverter output voltage harmonics. Furthermore, thispaper verifies that the current stress reduction with theproposed CPWM contributes the suppression of the DC-link
capacitor temperature rise, which has not been demonstrated
by our past work in [16].
This paper is organized as follows: First, the reduction
method of the DC-link current harmonics by using the shiftedvoltage references is presented. Second, the effects on the DClink current, the output phase current harmonics and theinverter efficiency are compared between the conventional andproposed DPWM by analysis and experiment. Finally, thecapacitor temperature rise test is presented to confirm theeffectiveness of the proposed CPWM.
II.

INVERTER DC-LINK CURRENT HARMONICS WITHCONVENTIONAL CONTINUOUS PWM

Fig. 1 shows the voltage references of CPWM and output
phase currents at a modulation index m of 0.7 and a load power
factor cos φ of 0.707. Three phase voltage references v*x(x = u, v, and w) of the conventional CPWM [17] are sinusoidalwhere f is the fundamental frequency.
Fig. 2 shows zoomed-in waveforms of v*x, switching
functions sx and the DC-link current iDC.in at m = 0.7, 2πft = 25
degrees, and cos φ = 0.707. The DC-link current is thesuperposition summation of the switched current pulses fromeach leg and calculated as

iDC .in    sx  ix . x u ,v ,w

The shaded area of the DC-link current waveform in
Fig. 2 indicates the instantaneous root-mean-square (rms)value of the current flowing into the smoothing capacitor,
which is calculated as

I

0.5
0.5

vu*

Voltage references[p.u.]

 vu*  m  cos  2 ft  * vv  m  cos  2 ft  2 3 
v*  m  cos  2 ft  2 3
 w

1
1.0

II

III

IV

vv*

V

VI

v*w

m

0
0.0

-0.5
–0.5
-1
–1.0
-0.00260 0.002
0.006
0.014
0.018
10.00420.0080.0130.012
40.01650.020.022
6
1.2
1.2
0.8
0.8
iu
iv
iw
0.4
0.4
0
0.0
-0.4
–0.4
-0.8
–0.8
-1.2
–1.2
–30 0
0 0.002
30 0.004
60 0.006
90 0.008
120 0.01
150 0.012
180 0.014
210 0.016
240 0.018
270 0.02
300 0.022
330-0.002

Output phasecurrents [p.u.]waves as25 deg. (zoomed at–20 deg.
Figs. 2 and 4)(zoomed at Fig. 5)2πft [deg.]

Fig. 1. Continuous voltage references v*x and output phase currents ix at
m = 0.7 and cos φ = 0.707. The voltage sectors (I~VI) are determined by thepolarities of three-phase voltage references. The current sectors (1~6) aredetermined by the polarities of output phase currents.
1

Triangular carrier

vu*
v

*
v

vw*
-1

2
2
iC .rms Ts   iDC.in.rms Ts   iDC .in _ ave
1 Ts 2iDC .in dt
iDC .in.rms Ts  

Ts 0

3

iDC .in _ ave  4 m  I m cos 

su
sv





where Ts is the control period, Im is the maximum value of theoutput phase current, and φ is the load power factor lagging
angle. Note that a smaller fluctuation of the DC-link current
around its average value results in a smaller rms value of thesmoothing capacitor current [18]. With the conventional
CPWM, the center of the gate pulses is same as the center ofthe control period, which results in the longest overlap periodof the gate pulses. This leads to the large fluctuation of the DClink current around its average value, i.e. the high DC-linkcurrent harmonics.
III. PROPOSED PWM METHOD TO REDUCE DC-LINK
CURRENT HARMONICS OF VSI
It is obvious from (2) and (3) that the DC-link current
harmonics are highly influenced by the switching patterns andoutput phase currents, i.e. the load power factor. Therefore, theproposed CPWM reduces the DC-link current harmonics byshifting output voltage references in every half control period
and adjusting the gate pulse timings in the control period.
Furthermore, the proposed shifting rule of the voltage
references adapts to the load current conditions. In other words,
the proposed modulation method reduces the DC-link current
harmonics with adaptation for the variation of the load power
factor [16].

sw

V0

V1

V2

V7 V7

V2

V1

V0

iu
iDC.in_ave

iDC.iniu+iv
TsFig. 2. Zoomed-in waveforms of voltage references of conventional
CPWM v*x, switching functions sx, and iDC.in at m = 0.7, 2πft = 25 deg., andcos φ = 0.707.

A. Adjustment Method for Gate Pulse Timings
Fig. 3 shows the adjustment method for the gate pulse
timings with the voltage reference shift. Note that the proposed
voltage references are realized based on the premise that thereferences can be updated at both the positive-peak andnegative-peak of the triangular carrier with the generalpurposed micro-computer. The proposed voltage references
are generated by shifting the original continuous voltage
references v*x alternately to positive side and negative side in
every half control period. At first, the shifting coefficient (Ax)between the original and shifted reference is defined as a value
from 1.0 to 2.0. The shifting coefficient Ax of 1.0 indicates thatthe voltage reference shift is not performed as in Fig. 3(a). The
coefficient Ax of 2.0 indicates that the voltage references are
shifted maximally in linear-modulation region as in Fig. 3(b).
When v*x is positive as in Fig. 3, the maximum shifting amountΔv*x at Ax of 2.0 is limited by the positive-peak of carrier andcalculated as 1– v*x. In case of the negative v*x, the maximum

Δv*x is limited by the negative-peak of the carrier andcalculated as v*x +1. Furthermore, the shifting amount Δv*x is
defined to be varied from zero at Ax of 1.0 to the maximum
shifting amount at Ax of 2.0 linearly with regard to the value of
Ax. Then, the positively-shifted voltage reference v*xp and thenegatively-shifted voltage reference v*xn can be calculated asv*xp  v*x  v*x   2  Ax   vx*  Ax  1
 *
*
*
*
vxn  vx  vx  Ax  vx  1  1 
v  v  v  A   v  1  1
*
xp

*
x

*
x

x

*
x

 *
*
*
*
vxn  vx  vx   2  Ax   vx  Ax  1

 if v  0  ,*x 

 if v  0  .

1

vxp

*

vx

B. Proposed Voltage References for DC-link Current
Harmonics Reduction
Fig. 4 shows the zoomed-in waveforms of the proposed
voltage references, the switching functions, and the DC-linkcurrent at m = 0.7, 2πft = 25 degrees, and cos φ = 0.707. This
control period is located within the overlap period between
sector I (v*u > 0, v*v < 0, and v*w < 0) and sector A (iu > 0,iv < 0, and iw < 0). In case of the positive load power factor, i.e.
driving mode, iDC.in_ave is also positive according to (3). As
observed in Fig. 1, only iu is positive at 2πft = 25 degrees andcos φ = 0.707. During this control period, u-phase voltage
reference should become larger than the other two phasevoltage references, and the gate pulse su should cover sv and sw
in the time domain to avoid the iDC.in polarity flip compared tothe iDC.in_ave polarity. If the above criterion is not satisfied, iDC.in
becomes negative, leading to the large iDC.in fluctuation against
the positive iDC.in_ave. In addition to the above criterion, theoverlap of the other two gate pulses sv and sw should beshortened to further reduce iDC.in fluctuation around iDC.in_ave.
With those modified gate pulse timings, the applying durationof the output voltage vector V1 (1 0 0), which causes the large
difference between iDC.in (= iu) and iDC.in_ave, can be shortenedcompared to the conventional CPWM shown in Fig. 2. In
addition, the applying durations of V2 (1 1 0) and V6 (1 0 1),
which result in the small iDC.in harmonics, can be extended andgenerated with those gate pulses. In order to achieve both thecriterion for avoiding the iDC.in polarity flip compared to theiDC.in_ave polarity and the criterion for reducing the iDC.influctuation,v*xp

carrier

*

vx

v*xn

0

0

Δvx* = 0

Δvx* =1–vx*

-1

-1

sx

sx

v*xn

Ts
Ts
(a)
(b)
Fig. 3. Adjustment method for gate pulse timings with voltage reference
shift. (a) Ax = 1.0. (b) Ax = 2.0.

*xNote that (4) is dependent only on the polarity of v*x.
The gate pulse timings are adjusted during the control period
while maintaining these original pulse widths by shifting thevoltage references as in Fig. 3. In particular, the gate pulse
adjustment length is determined by the value of Ax. In addition,
the timing moves to the left when the voltage reference isshifted to the positive side in anterior half control period as inFig. 3(b); in contrast, the gate pulse timing is shifted to theright when the voltage reference is shifted to the positive sidein latter half control period.

1

carrier
*

vup*

1

v

*
u

v

*
v

*
un

vvp*

v

*
vwp

v *w

vvn*

-1

*
vwn

su
sv
sw

V0

V1

V6

V2

iu

iu+iw

iDC.inV0iDC.in_ave

iu+iv
Ts

Fig. 4. Zoomed-in waveforms of voltage references of proposed CPWM
v*x.PCPWM, switching functions, and iDC.in at m = 0.7, 2πft = 25 deg., andcos φ = 0.707. The shifting coefficients between the original voltage
references and shifted references are set as Au = 1.68, Av = 2.00, and Aw = 2.00.

1) v*u, whose output phase current is positive, is shifted tothe positive side simultaneously with the larger phasevoltage reference between the other two phases, i.e. v*v.
2) v*v and v*w are shifted alternately and maximally to thepositive side as long as they do not exceed v*up and v*un.
Fig. 5 shows another example of the zoomed-inconventional and proposed voltage references at m = 0.7,
2πft = –20 degrees, and cos φ = 0.707. This control period islocated within the overlap period between sector I (v*u > 0,v*v < 0, and v*w < 0) and sector F (iu > 0, iv < 0, and iw > 0). At
2πft = –20 degrees and cos φ = 0.707, only iv is negative as
observed in Fig. 1. Note that the only different phase current
polarity is negative which is inverse from the case in Fig. 4.
Even at this case, both of the criterion for avoiding the iDC.in
polarity flip and the criterion for reducing the iDC.in fluctuation
are effective to reduce the harmonics. In order to achieve thosecriteria,
1) v*v, whose output phase current is negative, is shifted to
the negative side simultaneously with the smaller phasevoltage reference between the other two phases, i.e. v*w.
2) v*u and v*w are shifted alternately and maximally to thenegative side as long as they do not become smaller
than v*vp and v*vn.

C. Design Flowchart of Shifting Coefficient Ax
Fig. 7 shows the design flowchart for Ax. At first, theconditions of the phase angle and the load current are detectedfrom the voltage sector (I~VI) and the current sector (1~6),
which are defined in Fig. 1. Then, Ax is calculated to satisfy
two criteria for the DC-link current harmonics reduction byusing equation (4) and the gate pulse widths tx. The gate pulse
widths tx can be calculated from v*x as

tx v*x  1.
2Note that there are 4 division processes to calculate all
shifting coefficients in the worst case, which might result in aheavy computation load. In practical, the calculation of Ax is
performed offline and the values of Ax are stored in a look-up
table. Note that the offline calculation of Ax provides the same
current stress reduction effect as the online calculation because
the value of Ax varies only with the phase (u, v, w), the phaseangle (0~360 deg.), the modulation index (0~1.0), and the load
current conditions (sector 1~6), which is independent from the
motor parameters.

1

Triangular carrier

v *u
v *w
v

*
v

-1

su
sv
sw

V0

V1

V6

V7

V7

V6

V1

V0

iu+iw
iu

iDC.iniDC.in_ave
Ts
(a)
1

v *u
vw*
v *v
-1

*
vwp
vun*

vup*

vvn*

vvp*

*
vwn

su
sv
sw

V1

V7

V6 V5 V0

iu+iw

iw

iu

iDC.iniDC.in_ave
Ts(b)Fig. 5. Zoomed-in waveforms of voltage references, switching functions,and ideal iDC.in at m = 0.7, 2πft = –20 deg., and cos φ = 0.707.
(a) Conventional CPWM. (b) Proposed CPWM with Au = 2.00, Av = 2.00, and
Aw = 2.00.

2.2
2.0
2
1.8
1.8
Au
Av
Aw
1.6
1.6
1.4
1.4
1.2
1.2
1.0
1
0.8
*
*
*
vu.PCPWM
1.2 -30
1.2
0 30 60 90vv.PCPWM
120 150 180 210vw.PCPWM
240 270 300 330
0.8
0.8
0.4
0.4
0.0
0
–0.4
-0.4
–0.8
-0.8
–1.2
-1.2
–30 0
30 60 90 120 150 180 210 240 270 300 330-30 0 30 60 90 120
180 210 240 270 300 330
2πft150[deg.]

Proposed voltage Divergence degreereferences [p.u.]coefficient Ax [-]Fig. 6 shows the variation of Ax and the proposed voltage
references v*x.PCPWM during one-cycle operation at m = 0.7 andcos φ = 0.707. As described in Figs 4 and 5, the voltage
references are shifted in every half control period to satisfy
both the criterion for avoiding the iDC.in polarity flip and thecriterion for reducing the iDC.in fluctuation. Nevertheless, incase of cos φ < 0.866 (φ > 30 deg.), there are areas where thecriterion for avoiding the iDC.in polarity flip cannot be satisfied.
In the phase range of 0~15 degrees in Fig. 6, for example, onlyiv is negative; thus, v-phase voltage reference should become
smaller than the other two phase voltage references to avoid
the iDC.in polarity flip. However, the original v-phase voltage
reference is not the minimum at this phase range and thecriterion cannot be satisfied. At these phase ranges, theproposed voltage reference shift further worsens the DC-linkcurrent harmonics. Therefore, the conventional CPWM isapplied at these phase ranges.
In case of the regenerative braking mode, iDC.in_ave becomes
negative according to (3). In this case, whether the certain
phase voltage reference should be maximized or minimized in
the criteria for DC-link current harmonics reduction is reversed
against the driving mode. Note that whether the motor
operating mode is driving or regenerative braking mode is
detected from the voltage phase angle conditions and thedetected output phase angle conditions [13].

IV. ANALYTICAL EVALUATIONS

Fig. 6. Variation of Ax and proposed voltage references v*x.PCPWM during
one-cycle operation at m = 0.7 and cos φ = 0.707. At the phase ranges of 0~15,60~75, 120~135, 180~195, 240~255, and 300~315, the DC-link current
harmonics cannot be reduced, and the conventional CPWM is applied. Notethat the switching frequency is set to be low for better illustration.

DC-link Capacitor RMS Current
The DC side of the three-phase VSI operates at six-foldfundamental frequency. Hence, the normalized DC-link

capacitor rms current can be calculated based on (3) byconsidering only a sixth of the fundamental period as

A.

1
NO

ta < tb + tc
YES

Aa = 1.0

Ab = 2.0v 1Ac = 2.0

Start
Ab 
voltage sector ==current sector

*
a
*
b

v 1

NO

Ac 

YES

voltage sector ==(current sector + 3)

YES

Aa 

va*  1
NO

Ab > 2.0
NO

YES

YES

YES

Ab = 2.0

YES

1

2

3

NO

Ac > 2.0NO

voltage sector is
odd number

1  va*vc*  1

NO
voltage sector is
odd number

2 vb*  va*  1

Aa 

4

Ac 

Ac = 2.0

*
b

2v

Aa 

v 1
*
a

2  A v  A
a

*
a

Ab 

a

vc*  12vc*
va*  1

2  A v  A
a

*
a

a

vb*  1Finish2

3NOta + tb –1< tc
YESta +tb –1< tc
YESNOta < tb + tc

Aa = 2.0

Ac = 1.0

Aa = 2.0vc*  1

Ab = 2.0

Aa 

vc*  1

Ac = 2.0Ab 

va*  1Ac 

vc*  1

2 vc*  vb*  1

vb*  1

1 v

*
c

Ab 

NO

Aa > 2.0

Aa = 2.0

Ac 

v 1
*
c

2  A v  A
*
c

c

v 1
*
b

Aa 

Ac 

2vb*
v 1
*
c

Ab 

2  A v  A
c

*
c

Ab 

v 1
*
b

vc*  12v   Aa  2  va*  Aa*b

vb*  1NO

YES

Ac = 2.0

2v

Aa 

v 1
*
c

vb*  1Ab 

va*  1

Ac > 2.0*a2vb*   Ac  2  vc*  Ac

Ac = 2.0

vb*  1Ac NO

Aa = 2.0

2vb*  va*  12vb*   Ac  2  vc*  Ac

Aa = 2.0

Ab = 2.02va*cvb*  1

NO

Ab > 2.0Ab 

2vb*  vc*  1

Aa = 1.0

YES

YES

Ac 

va*  1

Aa > 2.0

YES

NO

YES

Ac = 1.0
Aa 

Ab 

4

Ab 

2vc*
va*  12vb*   Aa  2  va*  Aa
vb*  1

c

v 1
*
a

FinishFinishFinishFig. 7. Design flowchart for Ax. The phase with the most positive voltage reference is denoted as phase a while the phase with the most negative voltage
reference is denoted as phase c. The phase which lies between phase a and phase c is denoted as phase b.



I C .rms (p.u.) 

1
Im





 tk

   i   T3

30

DC .in.ks2 iDC .in _ ave   d






where tk is the on-duty of a VSI voltage space vector Vk (su, sv,sw) within Ts, and iDC.in.k is the instantaneous DC-link current
value with the voltage space vector Vk.
Fig. 8 shows the analytical results of the DC-link capacitor
current with regard to the modulation index and the load power
factor angle. Fig. 8(a) confirms that with the application of theconventional CPWM, IC.rms(p.u.) becomes the maximum ataround m = 0.6 and absolute value of the load power factor|cos φ| = 1.0 due to the large difference between iDC.in (= 0 A)
and iDC.in_ave at the applying durations of zero vectors
V0 (0 0 0) and V7 (1 1 1). On the other hand, Figs. 8(b) and (c)confirm that the proposed CPWM reduces IC.rms(p.u.) under any
conditions of m and φ. In addition, a higher |cos φ| leads to agreater reduction effect on IC.rms(p.u.). This trend is resulted fromthe relationship between φ and the application ratio of theshifted voltage references in whole phase range. In case of|cos φ| > 0.866, the two criteria for the DC-link current
harmonics reduction can be satisfied over whole phase range.
Therefore, the shifted voltage references are applied overwhole phase range, leading a large reduction of IC.rms(p.u.).

 V  V   dt 
*

k



where Vk (k = 0~7) is the output voltage space vector of the
VSI, and V* is the voltage reference vector.
Fig. 9 shows one of examples of the harmonic flux
trajectories at m = 0.7 and 2πft = 25 degrees. The calculationof (7) and Fig. 9 evaluate and visualize the ripple current on a
per-carrier cycle base. Since the harmonic flux vector
characteristic has six-fold space symmetry, the perfundamental cycle (per 60 deg. in space) harmonic flux rms
value, which characterizes the load current quality and theharmonic losses in the test motor, is calculated as follows
RMS 

3





3
0



 N 1TsNTs

2

λ h dt.d . 

IC.rms (p.u.)_Conv [p.u.]

(b)



Fig. 10 shows the harmonic flux rms values of several
modulators. The distance between the trajectories and theorigin, which is the initial value of λh at the beginning of thecarrier cycle, corresponds to the magnitude of the harmonic
flux [19]. Thus, Figs. 9–10 confirm that the proposed CPWM
worsens the harmonic flux compared to those obtained withthe conventional CPWM. The reason is because the proposed
shifted voltage references result in the application of thevoltage space vector which is not the closest to V*, i.e. V6 in
Fig. 9. On the other hand, the proposed CPWM, of which
voltage references do not contain triplen harmonics, has abetter performance than the DPWM based DC-link current
harmonics reduction modulation method presented in [14].
V.

Load power factor angle  [deg.]

SIMULATION AND EXPERIMENTAL RESULTS

The performances of the conventional and proposed
CPWM are verified in PLECS simulation and experiment. In
this experiment, the three-phase 2-level VSI, composed ofIC.rms (p.u.)_Prop / IC.rms (p.u.)_Conv [-] N 1Ts

NTs

(a)

Modulation index m [-]λ h  LI h  Load power factor angle  [deg.]

IC.rms (p.u.)_Prop [p.u.]

Load Current Quality
In order to evaluate the load current quality, the concept ofharmonic flux presented in [19] is used. This concept does not
require the calculation of the harmonic spectrum of the inverter
output voltage waveform, which is complicated for the
proposed CPWM because of its gate pulse asymmetry in the
carrier cycle. When the switching frequency model of the load
motor is assumed as an inductance L, a harmonic load current
vector Ih has a proportional relationship between the harmonic
flux vector λh (time integral of the instantaneous error voltage
vector) as

Modulation index m [-]B.

Modulation index m [-]Nevertheless, in case of |cos φ| < 0.866, the conventional
CPWM is partially applied in the phase ranges where thecriteria cannot be satisfied. The application ratio of the shiftedvoltage references decreases as |cos φ| becomes small, andthere is no IC.rms(p.u.) difference between the conventional andproposed CPWM when cos φ = 0.

Load power factor angle  [deg.](c)Fig. 8. Analytical results of DC-link capacitor rms current with regard to m
and φ. (a) IC.rms(p.u.)_Conv. (b) IC.rms(p.u.)_Prop. (c) IC.rms(p.u.)_Prop / IC.rms(p.u.)_Conv ratio.

IGBT power module (7MBP50RA120, Fuji Electric Co., Ltd.),
is operated at the switching frequency of 10 kHz. A threephase induction motor (MVK8115A-R, Fuji Electric Co., Ltd.),
the rated power of which is 3.7 kW, is used as a test motor andcontrolled by V/f control with the conventional and proposed
CPWM, which are implemented into an evaluation board
TMS320C6713, Texas Instruments.

i
1
I DC .in (p.u.)  DC .in.rms 
Im
Im



2

 1

iDC .in.n  2
n 1 
where n is the harmonic order, and iDC.in.n is the n-order-V0h = V

V2

λh

1
2 7 0
7
0
2
1

V2h
*

-V0h = V

V1h

λh 0

V2h

0
1

*

V1h

2
6

V0, V7

V1

V0

V1
V6h

V6
(a)

(b)

Fig. 9. Harmonic flux trajectories at m = 0.7 and 2πft = 25 deg.
(a) Conventional CPWM. (b) Proposed CPWM.
DPWM based DC-link current harmonics
reduction modulation presented in [14]

0.350
0.300
0.250

λRMS [-]

A. DC-link Current Harmonics
Fig. 11 shows the u-phase voltage reference, the line-to-line
voltage, the DC-link current, and the output u-phase current
with each modulation method at m = 0.550 and cos φ = 0.866.
Note that the voltage references of the proposed CPWM are
shifted in every half control period as shown in Fig. 11(b). As
a result, the width of the step change in the DC-link capacitor
is reduced. On the other hand, the larger transitions between+Edc and –Edc seem to occur in the line-to-line voltage with theproposed CPWM. However, the zoomed-in waveform of vuv
shown in Fig. 11(b) confirms that the instantaneous voltage
transition between +Edc and –Edc never occurs due to the deadtime period. Therefore, the proposed CPWM does not increase
the motor surge voltage in practice compared to theconventional CPWM.
Fig. 12 shows the harmonic components of the DC-linkcurrent under the same conditions in Fig. 11. The maximum
value of the vertical axis (100%) indicates the maximum valueof the output phase currents. Even though the employment of
the proposed CPWM worsens the 1st switching-frequency
harmonic component of the DC-link current, the integer
multiple components of the switching frequency are reduced
compared to those with the conventional CPWM.
Consequently, the proposed CPWM reduces the DC-linkcurrent harmonics by 24.2%. Note that the DC-link current
harmonics is evaluated as IDC.in(p.u.), which is the rms value of
the DC-link current (iDC.in.rms) normalized by the maximum
value of the output phase current.

V2

Proposed CPWM

0.200
0.150
0.100

Conventional DPWM
Conventional CPWM

0.050
0.000
0.0

0.2

0.4

0.6

0.8

1.0

1.2

Modulation index m [-]Fig. 10. Comparison of harmonic flux rms values. In the proposed CPWM
calculations, the load power factor is set to 1.

component of the DC-link current harmonics. The harmoniccomponents of the DC-link current up to 20th-order of theswitching frequency are considered in this evaluation.
Figs. 13–14 show the VSI operating waveforms and theharmonic components of the DC-link current at m = 0.550 andcos φ = 0.643, i.e. low load power factor condition. Whencos φ = 0.643, the periods where the proposed shifted voltage
references are not adequate for reduction of the DC-link
v*u.PCPWM [2.0 -/div.]

vu* [2.0 -/div.]
0

0

+Edc

vuv [500 V/div.]

vuv [500 V/div.]0

Dead-time
width

0

iDC.in [20 A/div.]

iDC.in [20 A/div.]

0

0

0

iu [20 A/div.]

iu [20 A/div.]

0

–Edc

0

[10 ms/div.]

Ts[10 ms/div.](a)(b)
Fig. 11. u-phase voltage reference, line-to-line voltage, DC-link current, and output u-phase current at m = 0.550 and cos φ = 0.866 (30 deg. lagging), i.e. highload power factor condition in driving mode. (a) Conventional CPWM. (b) Proposed CPWM. The zoomed-in waveform of vuv is from the simulation model using
PLECS.

IDC.in(p.u.) = 0.425 [p.u.]

10
10

100
100

34.2 %

Input current [%]Input current [%]

100
100

5.59 %

1
0.1
0.1
0.01
0.01
0.001
0.001

10

IDC.in(p.u.) = 0.322 [p.u.]

15.3 %

11.7 %

10
10

1
0.1
0.1
0.01
0.01
0.001
0.001

100
100

1000
10000
100000
100
1000
10000
1000
10000
100000
10
100
1000
10000
Frequency [Hz]Frequency [Hz](a)(b)
Fig. 12. Harmonic components of DC-link current at m = 0.550 and cos φ = 0.866 (under same conditions in Fig. 11).
(a) Conventional CPWM. (b) Proposed CPWM.

100000100000v*u.PCPWM [2.0 -/div.]

vu* [2.0 -/div.]00

vuv [500 V/div.]

vuv [500 V/div.]00iDC.in [10 A/div.]

iDC.in [10 A/div.]00iu [10 A/div.]

iu [10 A/div.]00[10 ms/div.][10 ms/div.](a)(b)
Fig. 13. u-phase voltage reference, line-to-line voltage, DC-link current, and output u-phase current at m = 0.550 and cos φ = 0.643 (50 deg. lagging), i.e. low
load power factor condition in driving mode. (a) Conventional CPWM. (b) Proposed CPWM.
IDC.in(p.u.) = 0.356 [p.u.]
101024.3 %
6.03 %

1
0.1
0.1
0.01
0.01
0.001
0.001
10

100
100

Input current [%]Input current [%]

100
100

15.6 %

IDC.in(p.u.) = 0.320 [p.u.]
1010

5.89 %

1
0.1
0.1
0.01
0.01

0.001
0.001
1000
10000
100000
100
1000
10000
1000
10000
100000
10
100
1000
10000
Frequency [Hz]Frequency [Hz](a)(b)
Fig. 14. Harmonic components of DC-link current at m = 0.550 and cos φ = 0.643 (under same conditions in Fig. 13).
(a) Conventional CPWM. (b) Proposed CPWM.
100
100

current harmonics arise. Therefore, the conventional
sinusoidal voltage references are partially applied in these
periods. As a result, the proposed CPWM reduces the DC-linkcurrent harmonics by 10.2%. These results demonstrate thatthe proposed CPWM is effective in terms of reducing the DClink current harmonics even when the load power factor is low.
Fig. 15 shows the simulation and experimental results of theDC-link current harmonics at cos φ from 0.259 to 0.866, i.e.
driving mode. The proposed CPWM reduces the DC-linkcurrent harmonics under any conditions of the modulationindex and the load power factor. A higher load power factor
enables a greater reduction effect on the DC-link current
harmonics to be obtained. This trend is resulted from therelationship between φ and the application ratio of the shifted

100000100000voltage references in whole phase range, observed in Fig. 8.
Figs. 16–17 show the VSI operating waveforms and theharmonic components of the DC-link current at m = 0.445 andcos φ = –0.766, i.e. regenerative braking mode. The applicationof the proposed CPWM reduces the DC-link current harmonics
even in the regenerative braking mode. These results confirm
that the proposed CPWM is effective to reduce the DC-linkcurrent harmonics for the motor drive system, of which thevariation of the load power factor is considerably wide.

0.5000.500

cos φ = 0.866(φ = 30 deg.)Lines : Sim. results
Plots : Exp. results

Lines : Sim. results
Plots : Exp. resultscos φ = 0.866(φ = 30 deg.)

0.400

IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

0.400

0.300

cos φ = 0.259(φ = 75 deg.)

0.200

cos φ = 0.643(φ = 50 deg.)

0.100

0.300

cos φ = 0.259(φ = 75 deg.)

0.200

cos φ = 0.643(φ = 50 deg.)

0.100

0.000

0.000
0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

Modulation index
Modulation index m [-]Modulationindex m [-]Modulation(a)(b)
Fig. 15. Simulation and experimental results of DC-link current harmonics in driving mode. (a) Conventional CPWM. (b) Proposed CPWM.
v*u.PCPWM [2.0 -/div.]

vu* [2.0 -/div.]00

vuv [500 V/div.]

vuv [500 V/div.]00iDC.in [50 A/div.]

iDC.in [50 A/div.]00iu [50 A/div.]

iu [50 A/div.]00[10 ms/div.][10 ms/div.](a)(b)
Fig. 16. u-phase voltage reference, line-to-line voltage, DC-link current, and output u-phase current at m = 0.445 and cos φ = –0.766 (140 deg. lagging) inregenerative braking mode. (a) Conventional CPWM. (b) Proposed CPWM.

IDC.in(p.u.) = 0.378 [p.u.]

10

26.4 %
4.55 %

11

0.1
0.01
0.01
0.001
0.001
10

100
100

Input current [%]Input current [%]

100
100

IDC.in(p.u.) = 0.320 [p.u.]

10.5 %

1
0.1
0.1
0.01
0.01

0.001
0.001
1000
10000
100000
100
1000
10000
1000
10000
100000
10
100
1000
10000
Frequency [Hz]Frequency [Hz](a)(b)
Fig. 17. Harmonic components of DC-link current at m = 0.445 and cos φ = –0.766 (under same conditions in Fig. 16).
(a) Conventional CPWM. (b) Proposed CPWM.
100
100

B. Output Phase Current Harmonics
Fig. 18 shows the total harmonic distortion (THD) of theoutput u-phase current at cos φ = 0.866. The harmoniccomponents up to 40th-order of the fundamental frequency are
considered in this evaluation. These characteristics are similar
to the analytic results of the harmonic flux rms value shown in
Fig. 10. The proposed CPWM leads to higher distortion of theoutput phase current compared to those with the conventional
CPWM. Therefore, the application of the proposed CPWM
results in a trade-off between the improved DC-link current
harmonics and the worsened AC current harmonics.
Nevertheless, those output current THD with the proposed

16.6 %

10
10

100000100000CPWM is superior to those with the DPWM based DC-linkcurrent harmonics reduction modulation method presented in[14], and the almost same level of those with the conventional
DPWM method. In addition, the worsened output current THD
with the proposed CPWM can be improved by increasing theswitching frequency in case with the inductive load. Note thatthe higher switching frequency leads to the increase of theswitching losses; however, those impact on the inverter
efficiency can be reduced by applying the wide band gap
device such as SiC or GaN.

10.0

DPWM based DC-link current harmonics
reduction modulation presented in [14]8.0THD of iu [%]Proposed CPWM
6.0

4.0
2.0

Conventional CPWM
0.0

VI. TEMPERATURE RISE TEST FOR DC-LINK CAPACITORS

2PCap   RESR.n  iCap
.n . 
n1

Fig. 24 shows the measured capacitor core temperature. The
temperature rise tests are conducted until the container internal
temperature reaches 60℃, the rated temperature of the coatedvinyl of wire, while VSI operating under the experimental
conditions in Figs. 22–23. Assuming that the container has asufficient thermal resistance and the leakage heat through thecontainer is negligible, the heat quantity Q of the film capacitor
and its temperature T have following relationship.
Q  cPP w  T  T0  



0.4

0.6

0.8

1.2

100.0
95.0

Proposed CPWM
90.0
85.0

Conventional CPWM
80.0
75.0
0.0

0.2

0.4

0.6

0.8

1.0

Modulation index
Modulationindex mm [-][-]Fig. 19. Inverter efficiency comparison between conventional and proposed
CPWM against different modulation index at cos φ = 0.866.
Thermostatic bath: EPFH-125-2S (ISUZU)

iDC.in_ave iDC.in
DCL =
10 mH

Sup

Swp

Svp

iu

iCap
Vdc =
282.8 V

Cdc =
20 µF
Sun

vuv
Svn

Swn

IM

MVK8115A-R(Fuji Electric)
Pn = 3.7 kW
Nn = 1500 rpm

Inverter: 7MBP50RA120 (Fuji Electric)

Fig. 20. Temperature rise test setup.
100
100
62 mm

Built-inthermocouple

42 mm

C = 20 µF
w = 200 g

Capacitor coretemperature = 25℃

10
10

11

0.1
0.1
10

where cPP is the specific heat capacity of polypropylene, thevalue of which is 1.93 J/g∙℃ [21], w is the capacitor weight,
and T0 is the capacitor initial temperature. Note that, theinverter loss does not change with the conventional andproposed CPWM which can be observed from Fig. 19. Thus,
the capacitor temperature difference between the cases with

1.0

Fig. 18. THD of output u-phase current iu at cos φ = 0.866.

45 mm



0.2

Modulation index m [-][%]efficiency[%]
Inverterefficiency
InverterFig. 20 shows the temperature rise test setup. The DC-link
capacitor and the inverter are placed inside thermally-insulated
container (EPFH-125-2S, ISUZU), whereas the temperature
test starts from 25.0℃.
Fig. 21 shows the film capacitor under test as the DC-link
capacitor. The thermocouple is built in the central part of thefilm capacitor. An equivalent series resistance (ESR) is
measured using HIOKI 3532-50 LCR tester. At very low
frequencies, the ESR is high due to prevalent leakage. At low
frequencies, ESR is dominated by the dielectric losses which
decrease in inverse proportion to the frequency. At medium tohigh frequencies, the losses in the conductors are dominant and
ESR becomes relatively constant. At high frequencies, ESR
increases again due to the skin effect [20].
Figs. 22–23 show the VSI operating waveforms and theharmonic components of the DC-link capacitor current iCap
through the temperature rise test at m = 0.643, cos φ = 0.891
and the inverter output power Pinv of 2.7 kW. The proposed
CPWM reduce the switching frequency component of thecapacitor current. Furthermore, the capacitor loss, which canbe calculated as follows, is reduced by 31.7% with theproposed CPWM.

Conventional DPWM

0.0

Capacitor ESR RESR.n [mΩ]

C. Inverter Efficiency
Fig. 19 shows the inverter efficiency between theconventional and proposed CPWM at cos φ = 0.866. The
inverter efficiency is measured using Yokogawa WT 1800
power analyzer. The application of the proposed CPWM does
not influence on the inverter efficiency and the same level
efficiency with the conventional CPWM to be obtained due toits same number of switching transitions compared with theconventional CPWM, which can be observed from Figs. 2, 4.

1002
10

3
1000
10000
10
10 4
Frequency [Hz]100000
10 5

(a)
(b)
Fig. 21. Film capacitor under test. (a) Photograph of film capacitor.
(b) Measured ESR.

the conventional and proposed CPWM after t seconds is
calculated as

Tconv  t   Tprop

Pt  

Cap .conv

 .

 PCap. prop  t
cPP w*
vu.PCPWM[2.0 -/div.]

vu* [2.0 -/div.]00
vuv [500 V/div.]vuv [500 V/div.]00iCap [20 A/div.]00iu [50 A/div.]
0[5 ms/div.][5 ms/div.](a)(b)
Fig. 22. Operating waveforms through temperature rise test at m = 0.643,
cos φ = 0.891, and Pinv = 2.7 kW. (a) Conventional CPWM. (b) Proposed
CPWM.

CONCLUSION

1010Capacitor current [Arms]

The novel CPWM was proposed to reduce the DC-linkcurrent harmonics of the three-phase VSI, which flowed
through the DC-link capacitor, over wide variation of the load
power factor. Furthermore, the high cost hardware such as
FPGA was not necessary because this PWM strategy wasrealized with only one triangular carrier. The DC-link
capacitor current rms value were reduced by shifting thevoltage references in every half control period to reduce thefluctuation of the DC-link current around its average value. On
the other hand, the CPWM had a drawback of the large
distortion of the VSI output line-to-line voltage and phasecurrent as a result of the DC-link current harmonics reduction.
The experimental results confirmed that the application of
the proposed CPWM reduced the rms value of the DC-linkcurrent by 24.2% at most, and lowered the equilibrium
capacitor temperature by 6.0℃ compared to the conventional
CPWM. Furthermore, the proposed CPWM achieves the samelevel inverter efficiency with the conventional CPWM.
Therefore, the proposed CPWM contributed to the current
stress reduction on the DC-link capacitor, resulting in thethermal stress reduction and the reliability improvement for theDC-link film capacitors which are the heat-sensitive
components without worsening the inverter efficiency. On theother hand, the proposed CPWM led to two drawbacks forbeing adopted in real practice: the worsened output current
distortion, and the heavy computation load for calculating theshifting coefficients Ax online. Note that the worsened motor
current THD can be improved by increasing the switchingfrequency while achieving the same reduction effect on theDC-link current harmonics, which is independent on theswitching frequency. Furthermore, the computation load
problem can be solved by calculating Ax offline and storingthese values in a look-up table with the same current stress
reduction effect as the online calculation.

iu [50 A/div.]

011

PCap.conv= 0.777 W

1010

8.65 Arms

0.1
0.1
0.01
0.01

0.001
0.001
10

1002
10

3
1000
10000
10
10 4
Frequency [Hz]10000010 5

113.69 Arms
PCap.prop= 0.531 W

0.1
0.1
0.01
0.01

0.001
0.001
10

1002
10

3
1000
10000
10
10 4
Frequency [Hz]100000
10 5

(a)
(b)
Fig. 23. Harmonic components of DC-link capacitor current at m = 0.643,
cos φ = 0.891, and Pinv = 2.7 kW (under same conditions in Fig. 22).
(a) Conventional CPWM. (b) Proposed CPWM.

Capacitor core temperature [℃]VII.

iCap [20 A/div.]

Capacitor current [Arms]

The estimated capacitor temperature difference after 7200
seconds based on the capacitor losses and (12) is 4.59℃,
besides the temperature test results in Fig. 24 confirm thecapacitor temperature difference of 4.4℃ after 7200 seconds.
Thus, the experimental results agree well with the theoreticalvalue. Furthermore, the proposed CPWM lowers theequilibrium capacitor temperature, which is estimated from thetest results using the least-square method, by 6.0℃ comparedto the conventional CPWM.

100
90
80
70
60
50
40
30
20
10
0

Conventional CPWM
6.0℃
4.4℃

Proposed CPWM

0

5000




  25.0


1

t 
5375
86.3  25.0   1  e   25.0

 92.3  25.0   1  e

10000
15000
Time [sec.]

1
t
5375

20000

25000

Fig. 24. Measured capacitor core temperature and its approximated curve.

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474ba/pdf-generaltechnicalinformation.pdf[21] T. A. Osswald, G. Menges, Materials Science of Polymers for Engineers,
Munich: HANSER, 1995, p. 91.