Evaluation of Power Density of a Reduced Switch Count Five-level
Three-phase PWM Rectifier for Aircraft Applications
Jun-ichi Itoh, Yuichi Noge
Nagaoka University of Technology
1603-1 Kamitomioka, Nagaoka, Niigata, Japan

Summary
Recently, more electric aircraft concept is attracted to achieve more light weight and downsizing of an aircraft. This paper proposes a novel five-level three-phase rectifier topology, which combines the DCLP and FC type converters has
been proposed. The proposed converter requires only half of the number of switches in comparison with the DCLP andFC types, that is, only 12 switches are used for the five-level rectifier. Moreover, the volume of the input boost reactor
can be reduced due to 5-level input voltage waveform of the rectifier. This paper establishes the optimization design
method of the boost-up reactor, clamping capacitor and power devices in order to achieve high power density. Besides,
its volume and power-density are obtained by the theoretical analysis.

1

Introduction

Recently, more electric aircraft concept is attracted toachieve more light weight and downsizing of an aircraft[3]. A rectifier in the aircraft application is required to reduce harmonics current in a power grid. The harmonics
current in the power grid causes various problems, such asline voltage distortion and EMI. In order to reduce theharmonics current of the power grid, power factor correction (PFC) rectifier using a PWM rectifier is a very important technology in terms of light weight and downsizing in comparison to passive PFC rectifiers.
A PWM rectifier, which consists of three switchinglegs, is popular PFC rectifiers; however conventional
PWM rectifier of 2-level is difficult to reduces the input
harmonics current in the aircraft application because themaximum input frequency is around 800Hz. On the otherhands, a multi-level converter technology is one of thesolutions to obtain high efficiency and low input harmonics current for high frequency input at the same time [4].
In general, a n-level converter can reduce the voltage
stress of a switching device to 1/(n–1) of the DC output
voltage.
PWM rectifiers of 3-level using VIENNA topologies
have been achieved low harmonics current and highpower density [1]. This converter uses only six switchesin spite of three-level topology of a three-phase rectifier,however in terms of more reduction of loss and harmonics
current, the rectifier should make a lot of level.
There are many circuit configurations for a multi-level
converter, such as the diode clamp (DCLP) type that uses
clamp diodes and capacitors to divide the DC output voltage, the flying capacitor (FC) type that uses clamping capacitors floating on the DC output voltage [6]. However
the DCLP type rectifier more than four-level requires balance circuits in the DC part, in order to control the clamping capacitor voltage. In contrast, the FC type requires
several capacitors for the clamping capacitors. Besides,
both methods use many switches. For example, in thecase of a five-level three-phase rectifier, 24 switching devices are required. In conclusion, the problems of multi-

level converters are the number of switching devices andthe volume of the clamping capacitor voltage. Then it is
not enough to achieve high power density rectifier by
conventional multi-level rectifiers.
A five-level three-phase rectifier topology, which combines the DCLP and FC type converters has been proposed [4]. The proposed circuit requires only half of thenumber of switches in comparison with the DCLP and FC
types, that is, only 12 switches are used for the five-levelrectifier. The point of the proposed topology is that highvoltage diodes can be more easily to be utilized than highvoltage switching devices. Therefore the proposed converter reduces the number of components. Besides, a low
on-state resistance MOSFET is used instead of IGBT because the voltage stress of the power device becomes 1/4of the DC output voltage. That is the proposed converter
using MOSFET achieves high efficiency.
This paper discusses the optimization design method of
the boost-up reactor, clamping capacitor and power devices for the proposed circuit. In the proposed circuit, thevolume of the input boost reactor can be reduced due tofive-level input voltage waveform of the rectifier. In addition, the volume of the other passive components for the
proposed converter is mentioned to indicate the remarkable miniaturization of the proposed circuit in comparison
to the conventional two or three-level converter topology[5]. Besides, its volume and power density are discussed
by the theoretical analysis.

2

Proposed circuit topology

2.1

Conventional circuit

Figure 1 (a) shows the DCLP and (b) shows the FC
type five-level PWM rectifier topology. The switching
devices of both topologies are of the same voltage rating.
Both converters can use a voltage rating of 1/4 for the DC
output voltage; however, these converters use 24 switching devices. As a result, the cost increases and the control
strategy becomes complicated.
In the DCLP type, the clamping capacitor voltage can
not be controlled without an auxiliary circuit. Additional

voltage regulators, such as DC choppers, are required tomaintain each clamping capacitor voltage at quarter of theDC output voltage [7]. On the other hand, the FC type has
many switching patterns which can charge or discharge
the flying capacitor in disregard of the same voltage level.
These switching patterns should be selected in order tocontrol the voltage of each flying capacitor. However,
several flying capacitors are needed and many voltage
sensors are required to detect the voltage of the flying capacitors in practically.

2.2

Proposed circuit

Figure 2 shows the proposed five-level PWM rectifier
using only 12 switches. The proposed circuit combines
both the DCLP and FC types into one. High voltage rating diodes are required in the proposed circuit; however, afast recovery diode is unnecessary, because there is norecovery mode for the high voltage diode in the proposed
circuit. Thus, the high voltage low speed diode is cheaper
than the high voltage switching devices.
Table 1 shows a comparison among the DCLP, FC andproposed rectifier. The largest advantage of the proposed
circuit is that the proposed circuit allows the number ofthe switches and capacitors to reduce, so that the numberof switching devices becomes 12 in spite of three-phaserectifier, which is half of the conventional circuit. It
should be noted that if the proposed concept is applied forother multi-level count, then the number of switching devices can always be reduced to half of that conventional
topology, because the outside diode can take half of theDC output voltage.
The other large advantage of the proposed circuit is thatthe proposed circuit can control each clamping capacitor
voltage. The voltage of the inner clamping capacitor C1
can be controlled, because the structure of the inside partis the same as that to the FC type. The voltage of the middle capacitors (C2 and C3) also can also be controlled, because this part is the same as the three-level rectifier. Notethat the proposed circuit can not accept an invert operation where the reverse energy will flow because the diodes are used instead of switches.
Figure 3 shows the voltage waveform of the rectifier
input voltage. It is noted that the zero level of the rectifier
input voltage is defined as the neutral point voltage of theDC output part. Five-step stairs waveform is obtained as
the rectifier input voltage, which is divided into six sectors by the voltage levels.
Table 2 indicates the switching pattern table of the proposed rectifier. For example, in the sector II, when therectifier input voltage is +Vdc/2 or +Vdc/4, if the inner
clamping capacitor voltage Vc is lower than its command
Vc*, the charge mode (S2 and S4 are turned on) will be selected. On the other hand, if Vc is higher than Vc*, the discharge mode (S1 and S3 are turned on) will be selected.
Thus, the inner clamping capacitor voltage can be controlled constantly at all sectors.
Additionally, the neutral point voltage of the DC part iscontrolled by the zero levels as the same as a conventional

three-level inverter. The zero level output switching pattern is selected by the input voltage polarity. When the
input voltage is positive, the +0 is selected for the zerolevel to increase the neutral point voltage. On the other
hand, the –0 is selected when the input voltage is negative
to decrease the neutral point voltage. As a result, the DCpart capacitor (C3) voltage can be balanced by the zerolevel selection.

2.3

Experimental results

The proposed circuit was demonstrated by small capacity prototype. The circuit parameter and conditions isshown in Table 3. The input voltage is 200 V, 50 Hz, theoutput power is 1 kW (rating), and the DC output voltage(a) Diode Clamp (DCLP) (b) Flying Capacitor (FC)
Figure 1 Conventional five-level PWM rectifier topologies(single leg).

Figure 2 Proposed hybrid PWM rectifier.
Table 1Comparison of the DCLP, FC and proposed converter
DCLP

FC

ProposedcircuitSwitch

24

24

12

*

Diode

60

24

36

Capacitor

4

30

13

Control of thecapacitor voltage

impossible

possiblepossible*

including FWD

command is set to 320 V, that is, the inner clamping capacitor voltage command is set to 80 V. It is noted thatthe more high frequency power grid could not be used inlaboratory condition; however scaling among the control
period, switching frequency and power grid frequency has
been considered.
Figure 4 shows the operation waveforms for the proposed rectifier. The sinusoidal input current waveforms
without distortion are obtained and the total harmonics
current (THD) of that is 3.4% (the 40th or less order components harmonics were considered). In addition, the DC
output voltage and the inner clamping capacitor voltage
agrees with commands of that respectively. In Figure 4, a
five-step voltage waveform is observed in the rectifier input voltage of the proposed converter, which agrees withthe expectation. It should be noted that the spike voltage
in the rectifier input voltage is caused by the commutationof the diode at the edge of the sectors. However, eachswitching of the device voltage is clamped by the inner orouter clamping capacitor. Therefore, the low voltage rating switching device can be used.
Figure 5 shows the operation waveforms at 160Hz fundamental frequency. This condition is supposed to apply
in aircraft power supply systems (400Hz fundamental frequency at 50 kHz carrier) with a carrier and power supply
frequency scaling (160Hz fundamental frequency at 20
kHz carrier). The sinusoidal input current waveforms are
obtained, and the total harmonic distortion (THD) for the
input current is 2.4%.

3

Parameter design method

3.1

Inductance of boost-up inductor (Lin)

When the switching frequency is higher than the input
frequency, the fundamental component of the reactor
voltage assumes to be constant during a switching cycle.
Then, the relations between the input inductor Lin and the

input current ripple ∆iin can be expressed as∆iin =vα
1 α / f sw
v L dt = L∫
0
Lin
Lin f sw

(1).

where
∆Vconv Vv L = Vm sin ωt −  dc +
 (0 ≤ ω t ≤ π / 6 )42 ∆Vconv Vv L = Vm sin ωt −  dc + (π / 6 < ωt ≤ π / 2)2 
 2

where fsw is the carrier frequency, ∆Vconv is the input
voltage ripple of the rectifier and Vm is the peak voltage ofthe input phase voltage.
Table 3
Experiment parameters of the proposed rectifier
Output power
Input voltage
DC output voltage command (Vdc*)
Load resistance(RL)
Inner clamping capacitor(C1)
Clamping capacitor(C2)
DC part capacitor(C3)Carrier frequency
50 [Hz]Input inductor (Lin)
Carrier frequency
160 [Hz]
Input inductor (Lin)1 [kW]
200 [V]
320 [V]
100 [Ω]
47 [µF]
100 [µF]
220 [µF]
10 [kHz]2 [mH]
20 [kHz]2 [mH]

Input voltage [250V/div]00Input current [5A/div]0

DC output voltage [250V/div]0

Inner clamping capacitor (C1) voltage [100V/div]

10ms

0
Rectifier input voltage [250V/div]

Figure 4 Experimental results of the proposed rectifier
at a 1 kW. @ 50Hz fundamental frequency

Figure 3 Rectifier input voltage waveform.
Table 2
Switching table of the proposed rectifier
SectorVoltage levelTurn-on switches

I+Vdc/4 , +0

S2-S4 (S1-S3), S3-S4

II+Vdc/2 , +Vdc/4

S1-S2, S2-S4 (S1-S3)

III+Vdc/4 , +0

S2-S4 (S1-S3), S3-S4

IV–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)

V–Vdc/4 , –Vdc/2

S1-S3 (S2-S4), S3-S4

VI–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)

Figure 5 Experimental results of the proposed rectifier
at a 1 kW. @ 160Hz fundamental frequency

Since the rectifier voltage command is a sinusoidal
waveform, the duty ratio α for each section is defined as α = 2 sin ωtα = 2(sin ωt − 0.5)

(0 ≤ ωt ≤ π / 6)
(π / 6 < ωt ≤ π / 2)

(2).

Figure 6 shows the value of vLα when Vm and ∆Vconv aredefined to 1 p.u. and 0, respectively. Since the input current ripple is dominated by vLα, the input current ripple∆iin becomes the maximum value at the duty ratio of 0.5
when the DC voltage Vdc is 1 p.u. Then the input phaseangles ωt are sin-1(1/4), or sin-1(3/4). Note that if the DC
voltage is changed, the peak position of vLα is only
shifted to right and the peak value does not change asshown in Figure 6 Consequently, the maximum input current ripple ∆iin can be expressed as∆VconvV
3
1∆iin = Vm sin(sin −1 ) − ( dc +)42
2
2 Lin f sw
∆Vconv
V
3
1= Vm − ( dc +)42
2
2 Lin f sw

(3).

Therefore, Lin can be designed by∆VconvV
3
1)
Vm − ( dc +42
22∆iin f sw

depends on the phase angle of the input voltage. For example, the quantity of the electric charge which flow into
the neutral point from R phase is expressed as following
equations.
Qc 3 _ 0−30 = ∫Ts / 120

Qc 3 _ 30− 60 = ∫Ts / 6Ts / 12I m sin ωt ( D0 _ 0−30 +I m sin ωt (DVdc / 4 _ 0−30
2DVdc / 4 _ 30 −60
2

(8).

) dt

(9).

) dt

where Ts is a period of the input voltage, Imsinωt is the
input current of R-phase, D is the duty ratio. The
subscripts indicate the voltage level and the phase angleof the input voltage. It should be noted that duty ratio for
0 to 30° on Vdc/4 level is used as a half of the originalvalue because almost half of this period does not flow thecurrent into the neutral point.
The rectifier voltage command is formed in sinusoidal,
and then it can be defined as 100% at 0° and 0% at 30°
during zero output voltage level. At Vdc/4 output voltage
level, the rectifier voltage command can be defined as100% at 30° and 0% at 90°. Consequently, the duty ratioof each area can be expressed as(4).

D0 _ 0 −30 = 1 − 2 sin ωt(13).

Thus, the input reactor can be reduced by increasing thecurrent ripple ∆iin and the switching frequency fsw.

DVdc / 4 _ 0−30 = 2 sin ωt(14).

DVdc / 4 _ 30−60 = 2(1 − sin ωt )

(15).

Lin =

3.2

Capacitance of inner clamping capacitor (C1)

The output voltage variations of the proposed circuit
are ±Vdc/2, ±Vdc/4, and 0. Note that ±Vdc/4 levels are outputted through the inner clamping capacitor C1. The
maximum output time of ±Vdc/4 levels can be expressedasTsw _ max = 1 / f sw

(5).

The quantity of the electric charge Qnp from 0 to 60°
region can be expressed by (16).
Qnp = 2(Qc 3 _ 0 −30 + Qc 3 _ 30−60 )On the other hands, the DC output voltage ripple isgenerated at six times of the input voltage frequency.
Then, the maximum quantity of the rectifier input electriccharge (Qin_R, Qin_T) can be expressed by (17), (18) for ahalf cycle of the output voltage ripple, i.e. Ts/12.

Consequently, the maximum voltage ripple of C1 is givenbyiin _ peak
1 Tsw _ max iin _ peak
∆Vc =
dt =
C1 ∫0
2
2C1 f sw

0.15

(6).

0.1

where iin_peak is the peak of the input current.
Practically, the peak current includes the ripple
components. Therefore, the capacitance of C1 is decidedby (7) from (6).
C1 =iin _ peak + ∆iin
∆VC1 f sw

0.05
0

(7).

where ∆iin is the ripple current.
As shown in (10), the capacitance of C1 can be reduced
by increasing the switching frequency and the allowance
voltage ripple ∆Vc.

3.3

(16).

Capacitance of DC part capacitor (C3)

At first, the quantity of the electric charge flows into
the neutral point should be calculated in order to design
the capacity of C3. The relations between the voltage level
and the current that flows into the neutral point is shownin Table 4. It is noted that the selected switching patternFigure 6 Input current ripple ∆iin and phase angle of input
voltage.
Table 4
Voltage Levels and Connection to Neutral Point
Phase angle of
input voltage
0-30°

30-60°

Voltage level0+Vdc/4(C1 Charge / Discharge)+Vdc/4(C1 Charge / Discharge)+Vdc/2Current to neutral
point
ActiveActive/inactive
Active/inactive
ActiveTs

Qin _ R = ∫ 12 I m sin (ωt )dt

φ=

0

=

Im 
ωT

 − cos s + 1
12
ω


(17).

=

Im 
4  1 ωT
 − cos s − π  + ω  12 3  2 

Sc =

(18).

I load Ts
12

(19).

Next, the DC output voltage ripple ∆Vdc can be expressedas (21) with the input current ripple ∆iin .
∆Vdc =∆i1(3 in + 2∆QC 3 )
C2
f sw

(21).

Finally, the capacitance of C3 can be calculated. Note that
ωTs/12 is equal to π/6.
C3 =
=

1
∆i
(3 in + ∆QC 3 )
f sw
∆Vdc
I 74 − 33 3 − 6π I load 
1  ∆iin
−
+ m
3

4
12Ts 
∆Vdc  f sw 100πThe capacitance of C2 depends on the voltage fluctuation of the neutral point of the DC link part. The relations
between the voltage ripple of the neutral point ∆Vnp andC2 can be calculated from the quantity of the electriccharge flowing into the neutral point (Qnp), as expressedbyQnp
2(C 2 + C3 )

+

∆Vdc
2

(23).

As a result, the capacitance of C2 can be calculated by
C2 =

=

Qnp
2∆Vnp − ∆Vdc

I m 
π 9 3 
6− −

6 
2
4 
2∆Vnp − ∆Vdc

(24).
− C3

As shown in (24), the capacitance of C2 can be reduced
by increasing the voltage ripple of neutral point ∆Vnp.

4

Consideration of theoretical volume of passive components

4.1

Volume of input inductor

The input inductor volume is depend on several factors
which are maximum input current Imax, inductance L andsaturable flux density Bsat. The core flux of the input inductor (φ) can be expressed by

1π

1 I max

Sw =

π Id

l = 2 rw N

(27).

(28).

Figure 7 shows the shape of the boost-up inductor using
troidal core to obtain the input inductor volume (VL), (26),(27) and (30) are summarized as lSc
VL = π S c ++ 2 rw 

 2π
2



2

(29).

Volume of capacitors

The volume of the capacitor is depend on capacitance C,
dielectric constant εs and applied voltage. The thicknessof dielectric film ds depends on applied voltage. The capacitance C and the volume of the capacitor Vc can be expressed by (30) and (31).
C = ε 0ε s

Sds

Vc = Sd s =

(30).
Cd s

2

ε 0ε s(31).

From (31), the volume of the capacitor is proportional
to the capacitance and proportional to the square of the
thickness of dielectric film.

4.3

− C3

(26).

where Sc is the cross-section area of the winding wire. Id isthe allowable current density of the winding wire, which is
set to 10A/mm2 in this paper. The length of the magnetic
circuit l can be expressed by

4.2

Capacitance of Clamping Capacitor (C2)

∆Vnp =

rw =

(22).

From (22), the capacity of C3 can be reduced by increasing
voltage ripple ∆Vdc and the switching frequency fsw.

LI maxBsat NOn the other hands, the radius of the winding wire can be
expressed by

The quantity of the electric charge Qout which is supplied to the load is obtained by
Qout =(25).

where Sc is the cross-section area of the inductor core. Thisequation is transformed into

T

s
4 

Qin _ T = ∫ 12 I m sin  ωt − π dt
03 LI max= Bsat Sc
N

Comparison of volume

In this section, the proposed 5-level converter is compared with a DCLP 3-level converter. The total volume ofpassive components is calculated by sum of (29) and (31)according to each inductance and capacitance. Note thatthe inductance and capacitance are decided according to
the power rating or input frequency. In order to calculate
the value of the passive components Lin, C1, C2 and C3,
the design parameters are used in Table 5. In addition, theparameters of passive components are shown below. JFE
Steel JNHF (µs:4.1, Bsat:1.15[T]) high frequency electricalFigure 7 Configuration of the input inductor core. (crosssection diagram)steel sheet is used in calculation for the volume of an input boost-up inductor. In fact, concerning capacitors,
there are various types of dielectric constant εs and thickness dielectric film ds. In this paper, these parameters of
Nichicon GU series electrolytic capacitor are used in calculation.
Figure 8 shows the volume of passive components according to power rating. An upward trend of the volume
can be suppressed over 31 kW power rating area of the
proposed circuit. The advantage of the proposed circuit isintend.
Figure 9 shows the volume of passive components for
power supply frequency. The volume of the proposed circuit is drastically decreased by increasing the power supply frequency. For example, the volume of passive components of the proposed rectifier is 10.8% smaller than
DCLP at 50 Hz. However, it is smaller than 20.0% at 800
Hz. This is because the capacitor volume is the dominantparameter in the proposed circuit.
Figure 10 shows the power density of passive components as a function of power rating. It should be noted thatthe power density of power semiconductors and heat sinks
are assumed as almost same if power rating and the input
frequency is changed. High power density can beachieved in high power rating area over 31 kW.
These analysis results indicates that the proposed circuit is suitable for high frequency and large capacity application such as aircraft power supply systems.

[5] J. W. Kolar, J. Biela: "Exploring the Pareto Front ofMulti-Objective Single-Phase PFC Rectiﬁer Design
Optimization -99.2% Efﬁciency vs. 7kW/dm3 PowerDensity" IPEMC, 2009[6] P. Barbosa, P. Steimer : "Active Neutral-PointClamped Multilevel Converters" COMPEL, 2005
[7] N. Hatti, Y. Kondo, H. Akagi : "Five-Level DiodeClamped PWM Converters Connected Back-to-Backfor Motor Drives" IEEE Transactions on industry applications, vol.44, issue 4, pp.1268-1276, 2008

5

Figure 8 Volume of passive components for power
rating at f=800[Hz]Items

SymbolValue

Inductor current ripple
Capacitor voltage ripple
Switching frequency∆iin∆VC, ∆Vnp, ∆Vdc

10%
5%
50kHz

Volume of passive components [m3]Conclusion

Table 5
Calculation parameters

fs

0.004
0.003
0.002
0.001
0

A novel five-level PWM rectifier and its control strategy
have been proposed. Features of the proposed circuit are
the reduction in the number of switching devices, and acontrollable clamping capacitor voltage. The proposed
converter achieves THD of 3.4% for the input current at 50
Hz and 2.4% at 160 Hz for a 1 kW class experimental
prototype. Finally, the miniaturization of the passive
components is confirmed by consideration of thetheoretical volume calcuation. The volume of the passive
components are 20.0% smaller than DCLP three-level at
800 Hz. In addition, high power density can be achieved inhigh power rating area over 31 kW.

Volume of passive components [m3]6

Figure 9 Volume of passive components for power supply
frequency at P=50[kW]

Literature

0.00120.00080.0004
0
0

200

400

600

800

1000

Power density of passive
components [W/m3][1] B. Singh, B. N. Singh, and A. Chandra, et al, “A
Review of Three-Phase Improved Power Quality ACDC Converters”, IEEE Transactions on industrial
electronics, vol.51, no.3, pp.641-660, 2004.
[2] F. Z. Peng, “A Generalized Multilevel Inverter
Topology with Self Voltage Balancing”, IEEE
Transactions on industry applications, vol.37, no.2,
pp. 2024-2031, 2001.
[3] H. Wolf, T.Gathmann "Active Three-Phase Rectifier
for Aircraft Equipment" EPE 2005, Dresden, 2005[4] J. Itoh , Y. Noge and T. Adachi: “A novel Five-level
PWM Rectifier Using 12 switches”, ECCE IEEE, P83 1394 (2009)

0.0016

Figure 10 Power density of passive components for
power rating at f=800[Hz]