Switching Device Number Reduction for Three-Phase
Cascade-Modular Solid-State Transformer Systemwith Employment of Three-Phase T-Type Converter
Nam Hoai Le, Satoshi Nagai, Keisuke Kusaka and Jun-ichi Itoh
Department of Electrical engineering
Nagaoka University of Technology, NUT
Niigata, Japanlenam.iaoh@gmail.com
Abstract—This paper proposes a three-phase cascademodular solid-state-transformer (SST) system employed witha three-phase T-type converter to reduce the switching
device number. A conventional three-phase SST system
requires three single-phase SST subsystems, whereas the
proposed three-phase SST system requires only two singlephase SST subsystems due to the application of the threephase T-type converter. The operation of the proposed threephase SST system is confirmed by both simulation andexperiment. In the simulations, the three-phase SST systemwith the input voltage of 6.3 kV and the output voltage of
400V is evaluated. The unity power factor operation and the
low grid current total distortion harmonic (THD) of 0.96% isachieved, where the output current with low current ripple isalso achieved, satisfying the condition of the grid quality. In
the experiments, the grid currents with high current THD of
about 13.0% is obtained.
Keywords—DC grids, solid state transformers, three-phase Ttype converter

I.
INTRODUCTION
Nowadays, power grids face many challenges with anincreasing employment of renewable energy sources. SolidState Transformer (SST) is considered as an enabling
technology for ―Energy Internet‖, which provides full control
of power flow and protection against disturbances caused bysuch renewable energy sources. One of the SST applications
is the interface between medium voltage AC grids and low
voltage smart-grids. Several SST topologies has been
considered for this application [1]-[17].
Input-Series-Output-Parallel (ISOP) structure is generally
employed due to the properties of the application where theinput is high voltage / low current and the output is low
voltage / high current. In [1]-[2], [5], the ISOP structure isapplied for the SST system with the input of the single-phasemedium-voltage AC grid. Similarly, three single-phase SST
systems connecting in a delta connection can be employed in
the three-phase medium-voltage AC grid [1], [5]. However,this three-phase SST system faces many drawbacks, one ofwhich is a high number of switching devices.

On the other hand, the SWISS Rectifier, or three-phase
T-type converter in bidirectional operation mode, converts
the input of three phases into the output of two phases, i.e.
the phase between the maximum-to-medium phase, and the
medium-to-minimum
phase.
This
conversion
isaccomplished by the low switching frequency of theswitching devices in the three-phase T-type converter,
reducing significantly the switching loss. Therefore, many
application of the three-phase T-type converter taking
advantage of this property have been proposed [18]-[20].
Nevertheless, this property of the three-phase T-type
converter has not been employed into the three-phase SST
system to reduce the switching device number.
This paper proposes a three-phase cascade-modular SST
system employed with a three-phase T-type converter toreduce the switching device number. The original idea of thispaper is the employment of the three-phase T-type converterwith low switching frequency operation into the three-phasecascade-modular SST system. In particular, the high voltage
rating devices in the three-phase T-type converter is operated
at twice the grid frequency, leading to a significant switchingloss reduction. The simulation and experimental results
confirm the operation of the proposed system.
II.

CIRCUIT TOPOLOGY

Fig. 1 depicts the conventional and proposed three-phasecascade-modular SST systems. First, in the conventional
system, three rectifiers are connected to the three-phasemedium-voltage AC grid in a delta connection. The rectifier
converts line-to-line AC voltages to full-wave-rectification
waveforms, which are input into single-phase SST
subsystems.
Second, the ISOP structure is employed in the singlephase SST subsystem consisting of a cascade multi-level
converter and multiple resonant isolated DC-DC converters.
The cascade multi-level converter regulates the input current
Iin into the full-wave-rectification waveforms similarly tothe operation of the typical Power-Factor-Correction (PFC)
converter. Thanks to the multi-level topology, lowswitching frequency in each cell still results in a highRectifier or Unfolder

Single-phase
SST
Subsystem
[k=1]

400 V

Single-phase
SST
Subsystem[k=2]

6.6 kVrms

Single-phase
SST
Subsystem[k=3](a) Conventional three-phase cascade-modular SST system
Cascade MultiLevel Converter
Sp1-k
Iin-k

Cin

L

Vdc1-k

Ssp1-k

Spp1-k
Cr

lr

n:1

Cr

Lm
Cr
Spn1-k

Sn1-k

Vin-k

Resonant Isolated
DC-DC Connverter

Veq-k

Ssn1-kCell No. 1

Cr

Cout
Vout

Cell No. m(b) Single-phase SST subsystem
Three-phase T-type Converter
Srp

vr, vs, vt

ir

Ssp

Cell No. 1

Stp
Vin-1

Sr1 Sr2

R

isSingle-phase SST Subsystem [k=1]
Iout
400 V
Cell No. m

S

it

Ss2

Ss1

O

T

6.6 kVrms

Cell No. 1
Srn

Ssn

Stn

St1 St2

Vin-2
Cell No. m

Single-phase SST Subsystem [k=2](c) Proposed three-phase cascade-modular SST system
Fig. 1. Conventional and proposed three-phase cascademodular SST systems.
equivalent-frequency in the current ripple, leading to aminimization of an input inductor without increasing
switching loss.
Third, DC-link in each cell is connected with theresonant isolated DC-DC converter. The series-series
resonance compensation is selected for this DC-DC
converter due to the employment of a loosely-coupledtransformer, which enables the integration of the auxiliary
inductor lp into the transformer. The resonant isolated DCDC converter can achieve Zero-Voltage Switching (ZVS) at
turn-on of the switching devices, reducing the turn-on

switching loss [21]. One of the main drawbacks of theconventional system is the high number of switching
devices due to the requirement of three single-phase SST
subsystems.
On the other hand, the proposed three-phase cascademodular SST system with the three-phase T-type converter
requires only two single-phase SST subsystems.
Furthermore, the input voltage Vin-k of the single-phase SST
subsystem in the proposed system is lower than that of theconventional system due to a star connection in the
proposed system. Consequently, the cell number of thesingle-phase SST subsystem in the proposed system canalso be reduced.
Table I shows the comparison of switching device
number between the conventional and proposed three-phasecascade-modular SST systems. Note that the high-voltagerating switching devices of the three-phase T-type converterin the proposed system are same as those of three rectifiers in
the conventional system. Besides, the high-voltage-ratings
switching devices can be constructed by the seriesconnection of several Si-switching devices. Note that the low
switching frequency of the switching devices in the threephase T-type converter also results in the small snubber loss
when the CR snubbers are connected in parallel with theseries-connected switching devices. Furthermore, the numberof cell is calculated by the voltage rating of the switching
devices and the input voltage Vin-k of the single-phase SST
subsystem. It is concluded from Table I that the proposedsystem reduces the number of the switching devices by over
40% in any selection of the voltage rating. Note that Srp, Srn,
Ssp, Ssn, Stp and Stn can be employed with the diode if only
the unidirectional power flow is required.
III.

CONTROL METHOD

A. Switching pulse generation for three-phase T-type
converter
Fig. 2 depicts the switching pulse generation for thethree-phase T-type converter, whereas Table II shows theswitching table. In this digest, the three-phase T-type
converter is assumed to operate at unity power factor withpowering mode; therefore, Srp, Srn, Ssp, Ssn, Stp, and Stn arealways turned off. Next, the phase with the mid amplitude
compared to two other phases is connected to point O. In
particular, six states are determined from the relationshipamong three phase voltages as shown in Fig. 2(a); then, theswitching pulses are generated based on the state numbers
as shown in Fig. 2(b) and Table II. Consequently, the highvoltage-rating IGBTs Sr1, Sr2, Ss1, Ss2, St1, and St2 areswitched at only twice the grid frequency, leading to thesignificant switching loss reduction.
B. Control system of single-phase SST subsystem
The control system of the single-phase SST subsystem
consists of the feedback current control for the cascade
multi-level converter and the open loop control for the
resonant isolated DC-DC converter.

TABLE ICOMPARISON OF SWITCHING DEVICE NUMBER BETWEENCONVENTIONAL AND PROPOSED THREE-PHASE SST SYSTEMS.
Cell Number

VoltageRatingConv. SST
24
13
9
5

650 V
1.2 kV
1.7 kV
3.3 kVState
number

1

Number of Switching Device

Prop. SST
21
11
8
4
2

3

vr

Conv. SST
432
234
162
90
4

Prop. SST
252
132
96
48
5

vs

vr
vs
vt
vr
vs
vt

vmax_normalized
1
Max Voltage vmax
Determination
Vphase_amplitude
Iphase_amplitude
1
Min Voltage vmin|x|
Determination
Vphase_amplitude v

Iin-1_refIin-2_refmin_normalized(a) Current command generation
Iin-k_ref

PI
Iin-k
Vin-k

-1
m

1
nVout

duty
SWp1-k1

1m

SWn1-k

0

6

SWpm-kvt

Phase-shifted carrier

1

SWnm-k0(b) Feedback current control system
Fig. 3. Control block diagram of feedback current control
for cascade multi-level converter.
0o

60o

120o

180o

240o

300o

360o

(a) Relationship between phase voltages and state number
vr
vs
vt

State
State Number Number Switching Table ofThree-phase T-type
Determination
Converter

Srp, Srn, Sr1, Sr2
Ssp, Ssn, Ss1, Ss2
Stp, Stn, St1, St2(b) Switching pulse generation
Fig. 2. Switching pulse generation for three-phase T-type
converter.
TABLE IISWITCHING TABLE OF THREE-PHASE T-TYPE CONVERTER.
State no.
1
2
3
4
5
6

Sr1, Sr2
0
0
1
0
0
1

Ss1, Ss2
0
1
0
0
1
0

St1, St2
1
0
0
1
0
0

Srp, Srn, Ssp, Ssn, Stp, Stn
0
0
0
0
0
0

Fig. 3 depicts the control block diagram of the feedback
current control for the cascade multi-level converter. In Fig.
3(a), first, the maximum and minimum voltages vmax, vminamong vr, vs, vt in each states are determined. Then, vmax, vmin
are divided by the phase voltage amplitude to obtain thenormalized maximum and minimum voltages vmax_normalized,
vmin_normalized. Next, vmax_normalized is multiplied with the gridcurrent amplitude Iphase_amplitude to generate the input current
command of the first single-phase SST subsystem Iin-1_ref,whereas the absolute value of vmin_normalized is multiplied withIphase_amplitude to generate the input current command of thesecond single-phase SST subsystem Iin-2_ref.
The PI controller is employed in the feedback current
control system as shown in Fig. 3(b). The output of the PI
controller is divided by the number of cells m due to the

TABLE IIISIMULATION PARAMETERS.
Parameters
Line-to-line grid voltage
Rated output apparent power
Grid frequency
Rated output voltage
Device voltage rating
Number of cells
Boost inductor
Primary side capacitor
Transformer turn ratio
Sw. freq. multi-level converter
Sw. freq. isolated converter

Symbols
vg
Sout
fg
Vout
VDS
m
L (%Z)
Cinn:1
fsw_multi
fsw_isoValues
6.6 kVrms
45 kVA
50 Hz
400 V
1.7 kV8
5 mH (0.16%)
40 mF
2.55:1
12 kHz48 kHzcharacteristic of the multi-level operation. Then, the input
voltage of each single-phase SST subsystem Vin-k is feed
forward to compensate for the disturbance. The result isdivided by the multiplication of the output voltage Vout andthe turn ratio n of the transformer. Finally, the switchingpulses are generated by the comparison between the duty
and the carriers. Note that phase of each carriers in each cellis shifted to further reduce the current ripple.
Meanwhile, the voltage control for the primary side
capacitor Cin in each cell is unnecessary in this system. The
voltage of the primary side capacitor Vdc1_k might become
imbalanced due to the variation of Cin. Nevertheless, theparallel connection of the resonant isolated DC-DC
converter, whose duty ratio of each switch in one leg is kept
constant at 50%, clamps the average value of Vdc1_k to nVout.
Consequently, the voltage control for Cin is not required.
IV.

SIMULATION RESULTS

Table III shows the simulation parameters. The
proposed three-phase SST system is adopted with a threephase 6.6-kV AC grid, whereas the power rating of thesystem is 45 kVA. Note that the switching devices with thevoltage rating of 1.7 kV are employed in the proposed threephase SST system.

vr

4

vs

vt

Grid current [V]Grid phase voltage [kV]

6

6
2
0
-2
-4
-6

0

40

80

120
Time [ms]

160

4

is

0
-2
-4
0

40

80

(a) Grid phase voltages
Veq-1

6
4
2
0

40

80

120
Time [ms]

160

100

0.6
0.2
80

120
Time [ms]

160

200

Cell capacitor voltage [kV]

Cell capacitor voltage [kV]Vdc1-1~Vdc8-1

40

200

160

200

40
20
0

40

80

120
Time [ms](d) Output current

1.2

0

160

Iout

60

0

200

1.5

0

200

80

(c) Total cell voltages

0.8

160

120

Veq-2

8

0

120
Time [ms](b) Grid currents

Output current [A]Total cell voltage [kV]

10

it

2

-6

200

ir

1.5
1.2
Vdc1-2~Vdc8-2

0.8
0.6
0.2
0

0

40

80

120
Time [ms](e) Cell voltages of first single-phase SST subsystem(f) Cell voltages of second single-phase SST subsystem
Fig. 4. Operation of proposed three-phase SST system.
Fig. 4 depicts the operation of the proposed SST system.
Fig. 4(a)-(f) shows the grid phase voltages vr~vt, the gridcurrents ir~it, the total cell voltages Veq-1, Veq-2, the output
current Iout, and the cell voltages of the first and second
single-phase SST subsystems Vdc1-1~Vdc8-1, Vdc1-2~Vdc8-2, asshown in Fig. 1(b)-(c), respectively. According to Fig. 4(a)(b), the unity power factor operation and the low grid current
total distortion harmonic (THD) of 0.96% are achieved. Notethat in the simulation, the input filters have not been
considered, leading to the remaining current ripple in the gridcurrents; furthermore, the current THD is calculated up to
40th harmonic component. In Fig. 4(c), the multi-level
waveforms of total cell voltages Veq-1, Veq-2 are clearlyobserved, resulting in the high current-ripple equivalentfrequency despite of the low switching frequency of theswitching devices in each cell. In Fig. 4(d), the constant
output current Iout with very low current ripple is observed.
Note that in the simulation, the output filter has also not been
considered. The carrier phase shifting of the resonant
isolated DC-DC converter in each cell contributes to the
reduction of the output current ripple, leading to theminimization of the output filter. According to Fig. 4(e)-(f),the cell voltages of both the first and second single-phase
SST systems Vdc1-1~Vdc8-1, Vdc1-2~Vdc8-2 are maintained stably
even without any voltage control. The stable cell voltages areachieved thanks to the parallel connection of the resonant
isolated DC-DC converters, clamping the voltage in each cellto the output voltage. It can be observed that the cell voltages
consist of a relatively high voltage ripple. The reason is
because the primary side capacitor Cin is designed with a low
capacitance to avoid the requirement of the high-voltage
high-capacitance capacitors. As a result, the operation of the
proposed three-phase SST system is confirmed with theseresults.
V.

LABORATORY SETUP

Fig. 5 depicts the experimental circuit diagram andprototype, Table IV shows the experimental parameters, andFig. 6 depicts the miniature prototype of the three-phasecascade-modular solid-state transformer system with threephase T-type converter. The miniature prototype isconstructed with a three-phase T-type converter and two

Iout

Cell No. 1 of Single-phase SST Subsystem No. 1
Sp1-1

Spp1-1
Vdc1-1

L
Sn1-1
Srp

Ssp
ir

Stp

Cr

Ssp1-1

1:1

Ssn1-1
Cout

Lm

Vout
Ssn1-1

Spn1-1Ssp1-1

Veq1
Sr2
Cell No. 2 of Single-phase SST Subsystem No. 1

R
Sr1

vr, vs, vt
is

Ss2

S

Cell No. 1 of Single-phase SST Subsystem No. 2

O
Ss1
it

Sp1-2

St2

Spp1-2T

Ssn

Vdc1-2

L

St1
Srn

Cin

lr

Sn1-2

Stn

Cin

lr
Cr

n:1

Ssp1-2

Ssn1-2

Ssn1-2

Ssp1-2

Lm

Spn1-2

Veq2
Cell No. 2 of Single-phase SST Subsystem No. 2

Fig. 5. Circuit diagram of miniature prototype of three-phase cascade-modular solid-state transformer system with three-phase
T-type converter.
TABLE IV
EXPERIMENTAL PARAMETERS.
Parameters
Line-to-line grid voltage
Rated output power
Grid frequency
Rated output voltage
Number of cells
Boost inductor
Primary side capacitor
Output capacitor
Transformer turn ratio
Sw. freq. multi-level converter
Sw. freq. isolated converter
Switching Device

Symbols
vg
Pout
fg
Vout
m
L
Cin
Cout
n:1
fsw_multi
fsw_iso
SiC Rohm

Grid voltage vr [100 V / div]

Grid voltage vt [100 V / div]

Values120 Vrms
0.3 kW
50 Hz
40 V
2
4 mH
50 mF
1500 mF
1:1
20 kHz
50 kHz
SCT2080KE

Time [10 ms / div]
THDi = 13.2%
Grid current ir [5 A / div]

Grid current it [5 A / div]

Fig. 7. Operation waveforms of grid voltages and gridcurrents.

Fig. 6. Miniature prototype of proposed three-phase SST
system with one three-phase T-type converter and fourcells of single-phase SST subsystem.
single-phase SST subsystems, which have two cells each.
Switches Srp, Ssp, Stp, Srn, Ssn, and Stn are turned off because

only the powering mode with a unity power factor isoperated. The SiC devices from ROHM (SCT2080KE) are
employed for all the switches; however, the high voltage
rating IGBTs are applied for the switches in the three-phase
T-type converter in practical. Note that the primary side
capacitor value is much smaller than that of the output
capacitor in order to avoid the use of the high-voltage highcapacitance capacitor.
Fig. 7 depicts the operation waveforms of the gridvoltages and the grid currents. The same phase between thevr [1.0 p.u. / div]

vt [1.0 p.u. / div]

0
vt

vr

vs [1.0 p.u. / div]
Detection signal of Mode 10Time [0.5 ms / div]
ir [1.0 p.u. / div]

Detection signal of Mode 1

Time [2.0 ms / div]0

it [1.0 p.u. / div]

ir

0

it

is [1.0 p.u. / div](a) Accurate voltage relationship detection
vr [1.0 p.u. / div](b) Magnified waveforms of Fig. 8(a)vt [1.0 p.u. / div]0

Detection signal of Mode 10Time [0.5 ms / div]
ir [1.0 p.u. / div]vt

vr

vs [1.0 p.u. / div]

Detection signal of Mode 1

1 ms
Time [2.0 ms / div]0

it [1.0 p.u. / div]

ir

0
it

is [1.0 p.u. / div](c) Voltage relationship detection: Lagging
vr [1.0 p.u. / div](d) Magnified waveforms of Fig. 8(c)vt [1.0 p.u. / div]0

Detection signal of Mode 10Time [0.5 ms / div]
ir [1.0 p.u. / div]vt

vr

vs [1.0 p.u. / div]

it [1.0 p.u. / div]

Detection signal of Mode 10

1 ms
Time [2.0 ms / div]it0
is [1.0 p.u. / div]ir(e) Voltage relationship detection: Leading(f) Magnified waveforms of Fig. 8(e)Fig. 8. Simulated waveforms of grid voltages, detection signal of Mode 1, and grid currents under three cases of voltage
relationship detection.
s-phase voltage and s-phase current is confirmed as well asthat of the t-phase; this confirms the powering mode
operation. It is observed that the grid currents ir and it haverelatively high THD of over 13.0%. Note that the current
distortion is clearly observed at the changing point of theoperation mode shown in Fig. 2(a). The reason of thiscurrent distortion is because time delay between the mode
detection and the actual grid voltage relationship exists inpractical.
Fig. 8 depicts the simulated waveforms of the gridvoltages, the detection signal of Mode 1, and the gridcurrents under three cases of voltage relationship detection.

In Fig. 8(a)-(b), there is no time delay between the mode
detection and the actual grid voltage relationship; hence thecurrent commutates smoothly among the phases. However,as shown in Fig. 8(c)-(f), the current overshoots when thereis time delay between the mode detection and the actual gridvoltage relationship, which is set as 1.0 ms in this evaluation.
In particular, as shown in Fig. 8(c)-(d), considering the startof Mode 1, when the detection of Mode 1 is lagging
compared to the voltage relationship between r-phase and tphase, it is observed clearly that the current overshoothappens. Similarly, as shown in Fig. 8(e)-(f), when thedetection of Mode 1 is leading compared to the voltage

Total cell voltages of module 1 Veq-1 [100 V / div]

Cell Voltage Vdc1-1 [50 V / div]

Cell Voltage Vdc1-2 [50 V / div]

Total cell voltages of module 2 Veq-2 [100 V / div]
Cell Voltage Vdc2-1 [50 V / div]

Cell Voltage Vdc2-2 [50 V / div]

Output Voltage Vout [50 V / div]

Output Current Iout [10 A / div]

Time [10 ms / div]

Time [10 ms / div]

Fig. 10. Operation waveforms of cell voltages.
Fig. 9. Operation waveforms of total cell voltages, output
voltage and output current.
relationship between r-phase and t-phase, the current
overshoot also happens. These current overshootssignificantly worsen the grid current THD. In other words,
the current overshoots should be avoided to improve thegrid current quality. Note that these current overshoots
occur due to both the detection delay of the detection board
and the commutation delay of the bidirectional switches.
Fig. 9 depicts the operation waveforms of the total cellvoltages, the output voltage and the output current. The twolevel waveforms of total cell voltages Veq-1, Veq-2 are clearlyobserved, resulting in the high current-ripple equivalentfrequency despite of the low switching frequency of theswitching devices in each cell. It is observed that the output
current has small ripple. The reason of this ripple is because
the high current THD of the grid current, causing the ripple
in the input power as well as the output power. The increaseof the primary side capacitor in each cell Cin greatly
contributes to the power decoupling between the input andoutput, which indicates that the input power ripple does
small effects on the output power quality. Nevertheless, thisdesign is against the avoidance of the high-voltage highcapacitance capacitor design.
Fig. 10 depicts the operation waveform of the cellvoltages. The cell voltages of both the first and second
single-phase SST systems Vdc1-1~Vdc1-2, Vdc2-1~Vdc2-2 aremaintained stably even without any voltage control. The
stable cell voltages are achieved thanks to the parallel
connection of the resonant isolated DC-DC converters,

clamping the voltage in each cell to the output voltage. It canbe observed that the cell voltages consist of a relatively highvoltage ripple. The reason is because the primary side
capacitor Cin is designed with a low capacitance to avoid therequirement of the high-voltage high-capacitance capacitors.
Fig. 11 depicts the operation waveforms of the r-phasegrid voltage, and the three-phase T-type converter gate
signals. It is clearly observed that the switching devices of
the three-phase T-type converter are switched at very low
switching frequency, i.e. twice the grid frequency. Hence,
the high-voltage-rating IGBTs can be employed into thethree-phase T-type converter without introducing highswitching loss. This approach significantly decreases theswitching device number compared to the full-bridge
converter approach.
VI. CONCLUSION
This paper proposed the three-phase cascade-modular
SST system employed with the three-phase T-type converter
to reduce the switching device number. In particular, thehigh voltage rating devices in the three-phase T-type
converter was operated at twice the grid frequency, leading
to the significant switching loss reduction. Furthermore, only
two single-phase SST subsystems were required in the
proposed three-phase SST system compared to three of thatin the conventional three-phase SST system. Besides, the cellnumber in each single-phase SST subsystem of the proposed
three-phase SST system was lower than that of theconventional three-phase SST system. Consequently, theproposed three-phase SST system reduced the switching
device numbers by over 40% in any selection of the voltage
rating compared to that of the conventional three-phase SST
system. The operation of the proposed three-phase SST

system was confirmed in both the simulations andexperiments.
In the simulations, the three-phase SST system with the
input voltage of 6.3 kV and the output voltage of 400V wasevaluated. The unity power factor operation and the low gridcurrent total distortion harmonic (THD) of 0.96% wereachieved, where the output current with low current ripple
was also achieved, satisfying the condition of the grid quality.
In the experiments, the grid currents with high current THD
of about 13.0% was obtained. This high current THD wascaused by the misdetection between the operation mode andthe grid voltage relationship. In future works, theimprovement of the current THD will be focused.
Furthermore, the design of the prototype with high input
voltage will be evaluated.
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