Experimental Verification of a Multi-level Inverterwith H-bridge Clamp Circuit
for Single-phase Three-wire Grid Connection
Jun-ichi Itoh

Takayuki KarakiYuichi NogeNagaoka University of Technology
Nagaoka, JapanNagaoka University of Technology
Nagaoka, JapanTokyo metropolitan College ofIndustrial Technology Tokyo, Japan

karaki@stn.nagaokaut.ac.jp

noge@s.metro-cit.ac.jp

itoh@vos.nagaokaut.ac.jp

Abstract— A multilevel inverter with a H-bridge clamp
circuit is proposed for single-phase three-wire (1P3W) utility
connected applications such as PV systems. The proposed
inverter consists of two n-level inverters and a H-bridge clamp
circuit. The proposed inverter requires only 12 controllable
switches to obtain a 5-level output voltage though conventional
multi-level converters with grounded neutral point of the DC-bus
require 16 switches. The control strategy for the proposed circuit
is also discussed in this paper. Moreover, a numerical parameter
design method is established and then verified by experiments.
Finally, the grid connected operation is presented byexperimental results.
Keywords— Multi-level inverter, Single-phase three-wireconnection, Photovoltaic(PV) systems, Grid connection.

I.

INTRODUCTION

Recently, grid connected photovoltaic (PV) systems are
becoming popular more and more [1]. The grid connected
inverter is an important part in this PV system. A non-isolated
inverter has advantages such as less isolating transformer andhigh efficiency [2]. A single-phase two-wire (1P2W)
connection is used for home appliances. There is a commonmode leakage current which flows through the parasitic
capacitor between the PV and the ground by H-bridge inverters
at three-level operation. Several circuit topologies haveproposed in order to avoid this issue as shown in Ref. [3], [4].
For using these topologies, a common mode voltage is kept inconstant at every switching state. However, some additionalswitches are required on these topologies. A single-phase threewire (1P3W) connection is commonly used in Japan.
Generally, a H-bridge inverter with neutral point grounded DC
bus configuration is applied in order to eliminate the common
mode current [5], [6]. Therefore, by using the 1P3W
connection, the common mode current can be eliminated. Inaddition, the line-to-line output voltage waveform has threelevel and a safety issue is improved for grounded DC bus.
Therefore, the size of interconnection inductors are reduced
compared to 2-level inverter output voltage
On the other hand, multi-level inverters have been studied
and applied to the three-phase grid connected systems for
efficiency improvement [7], [8]. Recently the multi-level
inverters are used for not only medium voltage applications but
also low voltage applications such as PV inverters. A n-level
inverter can reduce the voltage stress of a switching device to1/(n-1) of the DC bus voltage. However, the n-level inverter
requires 2(n-1) switches per leg. As a result, the cost for

semiconductors and controller becomes higher. Thus, in termsof widespread use of the multi-level converters, the cost
reduction of the multi-level inverter especially is important forhome appliances.
In order to reduce the cost, an active neutral point clump(ANPC) inverter has been proposed by [9]. The ANPC requires
less high frequency switching devices and the controller issimple. However, the number of the switching devices is assame a conventional multi-level inverter. Therefore, in order todecrease the number of the switching devices, the shared active
stacked NPC (SASNPC) inverter has been proposed [10]. TheSASNPC inverter consists of unified clamp circuit to reduce
the number of switching devices. In Ref. [10], the SASNPC
inverter was only discussed for a three-phase 3-level operation.
However, all of the switching devices including the highvoltage (Vdc) clamp circuit are operated in carrier frequency.
Therefore, the switching loss becomes high. Moreover, themulti-level inverter which is suitable for 1P2W has not beenproposed.
In this paper, a multi-level inverter with a H-bridge clamp
circuit for a 1P3W connection is proposed. The proposed
inverter requires only 12 switches for a 5-level construction. It
is lesser than any other type of multi-level topologies whichuses 16 switches. In addition, the proposed inverter can beexpanded for 2n-1 level variations using two pair of n-level
inverters. Furthermore, the H-bridge clamp circuit is operated
in the grid frequency without switching losses. This paper isorganized as follows: first, fundamental circuit construction of
the proposed circuit is presented: second, the features of the
proposed circuit are described: finally, the control strategy withthe unbalanced voltage compensator of the DC capacitor isverified by experimental results.
II.

PROPOSED CIRCUIT TOPOLOGY

A. ANPC inverter
Fig. 1 shows the circuit configuration of a 2n-1 level ANPC
inverter applied in 1P3W grid. This inverter can use 8 switches
as the clamp circuit. The potential of the n-level inverter shiftedin each half cycle of positive and negative is possible.
B. Proposed inverter
Fig. 2(a) shows a 2n-1 level construction of the proposedinverter. The proposed inverter consists of two n-level DC sideinverters and H-bridge clamp circuit. The clamp circuit isTABLE I.

Switch(Carrier freq.)

COMPARISON OF THE NUMBER OF DEVICES IN FOURDIFFERENT MULTI-LEVEL TOPOLOGIES

Proposed

ANPC

DCLP

FC

88

16168(16*)

000212(24*)
006(12*)

Switch4(16*)(Grid freq.)
Diode0Flying Capacitor
2*：Voltage stress of 1/4Vdc
Fig. 1. Active neutral point clamped (ANPC) multi-level inverter.

(a)Fig. 3. Operation of upper/lower inverter and clamp switches.

(b)Fig. 2. Circuit configuration of a multilevel inverter for single-phase
three-wire utility connected system. (a) Proposed H-bridge clamped
converter. (b) Proposed H-bridge clamped converter at five-level
configration.

complementary to switch at the grid frequency. Thus, theswitching loss is very low in the clamp circuit.
Fig. 2(b) shows a 5-level model of the proposed inverter
where 3-level flying capacitor type (FC) is used as a DC side
inverter. Using the 3-level FC inverter, the voltage balancing of
the flying capacitors can simply be controlled by using 180degree phase shift modulation.

Table 1 shows a comparison of the number of components
among a diode clamped (DCLP), FC, ANPC and the proposed
inverter for 5-level model. All devices are standardized by
1/4Vdc voltage rating because of 5-level operation. The largest
advantage of the proposed inverter is that the proposed inverter
can reduce the number of the switches and capacitors. The
actual number of the switching devices becomes 12, which is
3/4 of the conventional 5-level inverter. Note that the voltage
rating of the clamp circuit becomes full Vdc because the clamp
circuit is connected to line-to-line grid voltage.
III.

PROPOSED CONTROL STRATEGIES

A. PWM strategy
Fig. 3 shows the voltage waveforms of the proposed 5-levelinverter. The upper and lower of the 3-level FC inverter areused in the PWM region. In the upper inverter, +Vdc/2 to 0patterns are used. In the lower inverter, 0 to -Vdc/2 patterns areused. The 180-degree phase shift carrier modulation is applied
to each inverter. The instantaneous magnitude of the reference
signal (Vu*, Vw*) is compared with the carrier signal. The clamp
circuits (S1u, S2u, S1w, S2w) are switched complementary with Uand W phase in the grid frequency.

TABLE II.

PhaseUW

Outputvoltage
Vdc/2
Vdc/4
Vdc/4
00
-Vdc/4-Vdc/4-Vdc/2
Vdc/2
Vdc/4
Vdc/4
00
-Vdc/4-Vdc/4-Vdc/2

No.
1234
5678910111213141516(a) ± Vdc /2

Outputcurrent
direction

Positive

Negative

Positive

Negative

SWITCHING CONDITION AND OUTPUT VOLTAGE.

Flying capacitor
C3Charge
Discharge
ChargeDischarge-C4Charge
Discharge
ChargeDischarge-S1
ONON
OFFOFFxxxx
ONONOFFOFFxxxx

Upper
S2S3
ON OFFOFF ONON OFFOFF ONxxxxxxxx
ON OFFOFF ONON OFFOFF ONxxxxxxxx(b) ± Vdc /4

Switching condition ("x"= not applicable)
InverterClamp circuit
Lower
U
W
S4
S5
S6
S7
S8
S1u
S2u S1w S2w
OFFxxxx
OFFxxxxON OFF OFF ON
ONxxxxONxxxxxON
ON OFF OFFxON OFF ON OFF
OFF ONON OFFx
OFF ON OFF ONx
OFF OFF ON
ONOFFxxxxOFFxxxx
OFF ONON OFFONxxxx
ONxxxxxON
ON OFF OFFxON OFF ON OFF
ON OFF OFF ONx
OFF ON OFF ONx
OFF OFF ON
ON(c) ± Vdc /4(d)0VFig. 4. Current pathway of proposed circuit topology.

Table 2 and Fig. 4 indicate the switching conditions and theoutput voltages of the proposed 5-level inverter. Fig. 4 shows
the current path of the proposed circuit topology. For example,in the sector I of Fig. 3, the output voltage of the U phase is+Vdc/4 or 0. The switching pattern No. 2~4 is used in sector I.
Using No. 3 and 4, the flying capacitor C3 can be charged ordischarged to control the voltage. The charge and discharge
patterns are equally generated in a single carrier period. Sameoutput current direction in each phase is not allowed. If U
phase current is positive, W phase current should be negative.
B. Control block diagram
Fig. 5 shows the control block diagram of the proposedinverter. The output current commands iu* and iw* are received
from external MPPT controller. The output currents arecontrolled by two independent PI regulators which areconnected to each phase. Then, the grid voltages vu and vw arecompensated by adding the detected value after the PI
regulators. The output current polarity is detected by “sign”
function. For example, if U phase current is positive, the Uphase output voltage command is connected to the upper
modulator. On the other hand, the W-phase output voltage
command is connected to the lower modulator. The unbalanced
voltages of C1, C2 are compensated by superimposed zero

phase current to the current commands. In particular,
compensation command is generated by a PI controller. The PI
controller operates to reduce the voltage difference between C1and C2. Then, the compensation current command is added or
subtracted to the current commands iu* and iw*.
Table 3 shows the truth table of the multiplexer MUX1 andMUX2. The multiplexers are used to switch the voltage
commands vu* and vw* to the upper and the lower inverters
based on the polarity of vu*. Therefore, when the output of theselector is 1, the output of the MUX1 is Y2, and the output ofthe MUX2 is Y1. Contrary to this, when the output of theselector is 0, the output of the MUX1 is Y1, and the output ofthe MUX2 is Y2.
IV.

PARAMETER DESIGN METHOD

A. Inductor (L1, L2)
When the switching frequency is higher than the input
frequency, the fundamental component of the inductor voltage
is assumed to be constant during a switching cycle. The current
ripple becomes the highest value at modulation ratio α=0.5.
Then, the relationship between the inductor Ln and the input
current ripple Δiin can be expressed asθ*icmd sin( θ )Fig. 5. Control block diagram of the proposed multi-level converter.
TABLE III.

TRUTH TABLE OF THE MUX1,2.

S01Δt................................................................. (1)
LnEq.1 can be modified toΔiin = V

Δt.................................................................. (2)Δiin
where V is the output voltage ripple of the inverter, Δt is theswitching period of the inverter. The V becomes 1/8Vdc at
α=0.5. The Δt becomes 1/4fs due to the phase shift modulation.
Consequently, the Ln can be expressed asY1
B1
A1

Y2
A2
B2Consequently, the maximum voltage ripple Δvn of Cn isgiven byC n = imV dc
1⋅...............................................(6)4V m 2Δv ⋅ f s

V.

SIMULATION AND EXPERIMENTAL RESULT

Ln = V1
1Ln = V dc..................................................... (3)84Δi ⋅ f s

B. Flying capacitor (C3, C4)
The output voltage variations of the proposed inverter are±Vdc/2, ±Vdc/4, and 0. Note that ±Vdc/4 levels are outputtedthrough the flying capacitor Cn. In addition, the all output
currents flow through the Cn at Vn*=±Vdc/4. In this case, theoutput current in at the Vn*=±Vdc/4 can be decided by1Vm sinωt = Vdc .......................................................... (4)4i n = i m sin ωt = i m

V dc............................................... (5)4VmFig 6 shows the simulation result of the proposed 5-level
inverter at 50 Hz grid frequency. The grid voltage is 200 V andthe output power is 1 kW. Clean sinusoidal input current
waveform is obtained, and the 5-level output voltage can beobserved. The maximum voltage ripple of the flying capacitor
vC3 is agreed to the designed value as shown in the Table 4.
Table 4 shows the circuit parameters of a 1 kW prototype.
Fig. 7 shows the steady state waveforms when RL load isused. The 5-level output voltage can be observed. Flyingcapacitor voltage is kept at 1/4 of DC-bus voltage (300 V / 4 =75 V).
Fig. 8(a) shows the operating waveforms of the proposed
circuit with the grid without the DC capacitor voltage
balancing control. The input current waveform is relatively
smooth and sinusoidal. However, there is voltage difference of68 V between the DC capacitor voltages vC1 and vC2. In thiscase, the total harmonics distortion (THD) of the input current
is 2.78%.

U phase output voltage vu [100V/div]
0W phase output voltage vw [100V/div]
0U phase output current iu [5A/div]
0W phase output current iw [5A/div]
Fig. 7. Operating waveforms. (RL load)

0Upper Flying capacitor voltage vc3 [5V/div]
19.1V

75 60

7080t[ms]90100Fig. 6. Operation waveforms by simulation.

TABLE IV.

PARAMETER AND CONDITION.

Rated power
DC bus voltage
Output voltage
Grid frequency
Rated current
Inductor

1 kW
300 V
200 Vrms
50 Hz
5 Arms4 mH (%Z=6.35)

Flying capacitor

4.7 μF

Electrolytic capacitor

360 μF

Carrier frequency

20 kHzDead time

1 μs

FC voltage ripple

25% (19 V)

Output current ripple

3.3%

Gate resistance

50 Ω

Inverter circuit
Clamp circuit

Switching device
TPH3006PS (600 V, 17 A)
IPW65R080CFD (650 V, 43.3 A)

Fig. 8(b) shows the operation waveforms with the DC
capacitor voltage balancing control. In this case, the voltage
differences between the upper and lower capacitors are verysmall. The output current THD is 2.52%. According to theexperimental results, the output current THD can be reduced
by applying the capacitor voltage balancing control. In
addition, the compensation of current does not flow steadily. Itis because the unbalanced voltage is caused by the unbalancedof power transition between the upper and lower inverters.
Fig. 9 shows the voltage ripple of the flying capacitors.
According to Fig. 10, the maximum amplitude of the voltage
ripple is 20.2 V. Design value of the voltage ripple is 19.0 V.

(a) Without DC capacitor voltage balancing control
U Line Voltage vu_pwm [100V/div]

0Upper DC capacitor Voltage vc1 [100V/div]

0Lower DC capacitor Voltage vc2 [100V/div]

150V[4ms/div]0

U Line current iu [10A/div](b) With DC capacitor voltage balancing control
Fig. 8. Operating waveforms. (Grid connected)

Therefore, the error range of the capacitor voltage ripple is±10%. According to (6), the error range of the voltage ripple isfrom 21.2 V to 25.9 V. Thus the result shows good agreementwith the designed value.
Fig. 10(a) shows the efficiency of the proposed circuit with
the RL load. According to Fig. 11, the efficiency is over 98%
for 0.2 kW to 1.0 kW of output powers, and the maximum
efficiency is 98.8% when output power around is 0.5 kW.
Fig. 10(b) shows the efficiency of the proposed circuit
when the proposed circuit is connected to the grid. The

99.0
98.8
98.6
98.4
98.2
98.00Fig. 9. Voltage ripple of the flying capacitors.

200400600

80010001200(a) Stand alone mode(R-L Load of Power factor:0.99)

efficiency is slightly lower than the RL load case. It is affectedby the difference of the grid power factor. The efficiency
degradation of the proposed inverter around 1-kW load iscaused by the on-state resistance of the MOSFETs.
Fig. 11 shows the output power factor of the proposed
circuit. The output power factor is over 99%. Thus, theoperation of the output current controller is confirmed.
VI.

CONCLUSION

A multilevel inverter with H-bridge clamp circuit wasproposed for single-phase three-wire utility connected
applications. The proposed inverter requires only 12
controllable switches to obtain a 5-level output voltage. In thecase of conventional multi-level converters with grounded
neutral point of the DC-bus, 16 switches are required. The
control strategy of the proposed system for the grid connection
is established. Besides, the design method of the passive
components is discussed and verified by simulation andexperiments. In addition, the unbalanced voltage of the DC
capacitors can be compensated by utilizing a PI regulator.
From the experimental results of the proposed circuit, amaximum efficiency of 98.8% was achieved.

(b) Grid connection modeFig. 10. Efficiency characteristics of the proposed inverter.

REFERENCES
[1]

[2]

[3]

[4]

[5]

[6]

David Meneses, Frede Blaabjerg, Osxar Garcia, Jose A Cbos,“Review and Comparison of Step-Up Transformerless Topologies for
Photovoltaic AC-Module Application“ IEEE Transactions on PowerElectronics, Vol. 28, No. 6, pp2649-2663 June 2013
F. Blaabjerg, F. Iov, T. Kerekes and R. Teodorescu, “Trends in powerelectronics and control of renewable energy systems” 14th PowerElectronics and Motion Control Conference, pp. K-1 - K19, 2010.
Bo Yang, Wuhua Li, Yujie Gu, Wenfeng Cui and Xiangning He“Improved transformerless inverter with common-mode leakage
current elimination for a photovoltaic grid-connected power system”,
IEEE Transactions on Power Electronics, Vol.27, No.2, pp. 752-762,
2012.
Ho-Dong Sun et. al., “Novel H-bridge multi-level inverter with DClink switches,” 8th International Conference on Power Electronics, pp.
271–350, 2011.
S. J. Chiang, Kuo-Lung Chai, and Ying-Yu Tzou, “Design andimplementation of single-phase three-wire rectifier-inverter for UPS
applications,” Power Electronics Specialists Conference, pp.19271932, 2004.
Y. Baba, M. Okamoto, E. Hiraki and T. Tanaka, “A half-bridge
inverter based current balancer with the reduced DC capacitors inFig. 11. Grid Power factor in grid connection mode.
single-phase three-wire distribution feeders,” Energy Conversion
Congress and Exposition, pp. 4233-4239, 2011.
[7] Lin Ma, T. Kerekes, R. Teodorescu, X. Jin, D. Floricau and M.
Liserre, “The high efficiency transformer-less PV inverter topologies
derived from NPC topology,” 13th European Conference on PowerElectronics and Applications, pp. 1-10, 2009.
[8] K. Yugo and J. Itoh, “Parameter design of a five-level inverter for PVsystems,” 8th International Conference on Power Electronics andECCE Asia, pp. 1886-1893, 2011.
[9] Barbosa, P.; Steimer, P.; Steinke, J.; Meysenc, L.; Winkelnkemper,M.; Celanovic, N: “Active neutral-point-clamped multilevelconverter,” Power Electronics Specialists Conference, pp. 2296-2301,
2005.
[10] A. Leredde, G. Gateau, D. Floricau, “New three level topology withshared components: properties, losses, and control strategy,” 35th
Annual Conference of IEEE Industrial Electronics, pp.673-678, 2009.