Cost-Effective A/D Flash MCU with EEPROM

HT66F002/HT66F0025/HT66F003/HT66F004

Revision: V2.30

Date: June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

Table of Contents
Features............................................................................................................. 6

CPU Features.......................................................................................................................... 6
Peripheral Features.................................................................................................................. 6

General Description.......................................................................................... 7
Selection Table.................................................................................................. 7
Block Diagram................................................................................................... 8
Pin Assignment................................................................................................. 8
Pin Description............................................................................................... 10
Absolute Maximum Ratings........................................................................... 15
D.C. Characteristics........................................................................................ 15
A.C. Characteristics........................................................................................ 16
A/D Converter Electrical Characteristics...................................................... 17
OPA Electrical Characteristics...................................................................... 17
LVR Electrical Characteristics....................................................................... 17
LCD Electrical Characteristics – HT66F004................................................. 18
Power on Reset Electrical Characteristics................................................... 18
System Architecture....................................................................................... 18

Clocking and Pipelining.......................................................................................................... 18
Program Counter.................................................................................................................... 19
Stack...................................................................................................................................... 20
Arithmetic and Logic Unit – ALU............................................................................................ 20

Flash Program Memory.................................................................................. 21

Structure................................................................................................................................. 21
Special Vectors...................................................................................................................... 21
Look-up Table......................................................................................................................... 21
Table Program Example......................................................................................................... 22
In Circuit Programming – ICP................................................................................................ 23
On-Chip Debug Support – OCDS.......................................................................................... 23

RAM Data Memory.......................................................................................... 24

Structure................................................................................................................................. 24
General Purpose Data Memory............................................................................................. 24
Special Purpose Data Memory.............................................................................................. 24

Special Function Register Description......................................................... 28

Indirect Addressing Registers – IAR0, IAR1.......................................................................... 28
Memory Pointers – MP0, MP1............................................................................................... 28
Bank Pointer – BP.................................................................................................................. 29
Accumulator – ACC................................................................................................................ 29
Program Counter Low Byte Register – PCL.......................................................................... 29
Look-up Table Registers – TBLP, TBLH................................................................................. 29

Rev. 2.30

2June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Status Register – STATUS..................................................................................................... 30

EEPROM Data Memory................................................................................... 32

EEPROM Data Memory Structure......................................................................................... 32
EEPROM Registers............................................................................................................... 32
Reading Data from the EEPROM ......................................................................................... 34
Writing Data to the EEPROM................................................................................................. 34
Write Protection...................................................................................................................... 34
EEPROM Interrupt................................................................................................................. 34
Programming Considerations................................................................................................. 35

Oscillators....................................................................................................... 36

Oscillator Overview................................................................................................................ 36
System Clock Configurations................................................................................................. 36
Internal High Speed RC Oscillator – HIRC............................................................................ 37
Internal 32kHz Oscillator – LIRC............................................................................................ 37
Supplementary Oscillator....................................................................................................... 37

Operating Modes and System Clocks.......................................................... 37

System Clocks....................................................................................................................... 37
System Operation Modes....................................................................................................... 38
Control Register..................................................................................................................... 39
Operating Mode Switching..................................................................................................... 41
NORMAL Mode to SLOW Mode Switching............................................................................ 42
SLOW Mode to NORMAL Mode Switching ........................................................................... 43
Entering the SLEEP0 Mode................................................................................................... 43
Entering the SLEEP1 Mode................................................................................................... 44
Entering the IDLE0 Mode....................................................................................................... 44
Entering the IDLE1 Mode....................................................................................................... 44
Standby Current Considerations............................................................................................ 45
Wake-up................................................................................................................................. 45

Watchdog Timer.............................................................................................. 46

Watchdog Timer Clock Source............................................................................................... 46
Watchdog Timer Control Register.......................................................................................... 46
Watchdog Timer Operation.................................................................................................... 47

Reset and Initialisation................................................................................... 48

Reset Functions..................................................................................................................... 49
Reset Initial Conditions.......................................................................................................... 52

Input/Output Ports.......................................................................................... 54

Pull-high Resistors................................................................................................................. 55
Port A Wake-up...................................................................................................................... 56
I/O Port Control Registers...................................................................................................... 57
Pin-shared Functions............................................................................................................. 58
I/O Pin Structures................................................................................................................... 62
System Clock output pin CLO................................................................................................ 63
Programming Considerations................................................................................................. 63

Rev. 2.30

3June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Timer Modules – TM....................................................................................... 63

Introduction............................................................................................................................ 63
TM Operation......................................................................................................................... 64
TM Clock Source.................................................................................................................... 64
TM Interrupts.......................................................................................................................... 64
TM External Pins.................................................................................................................... 64
TM Input/Output Pin Control Register.................................................................................... 65
Programming Considerations................................................................................................. 65

Standard Type TM – STM............................................................................... 67

Standard TM Operation.......................................................................................................... 67
Standard Type TM Register Description................................................................................ 67
Standard Type TM Operating Modes..................................................................................... 71

Periodic Type TM – PTM................................................................................. 81

Periodic TM Operation........................................................................................................... 81
Periodic Type TM Register Description.................................................................................. 81
Periodic Type TM Operating Modes....................................................................................... 85

Analog to Digital Converter........................................................................... 94

A/D Overview......................................................................................................................... 94
A/D Converter Register Description....................................................................................... 95
A/D Converter Operation........................................................................................................ 98
A/D Converter Input Signal.................................................................................................... 99
Conversion Rate and Timing Diagram................................................................................... 99
Summary of A/D Conversion Steps...................................................................................... 100
Programming Considerations............................................................................................... 101
A/D Transfer Function.......................................................................................................... 101
A/D Programming Examples................................................................................................ 102

Interrupts....................................................................................................... 104

Interrupt Registers................................................................................................................ 104
Interrupt Operation................................................................................................................110
External Interrupts.................................................................................................................112
Multi-function Interrupts.........................................................................................................112
A/D Converter Interrupt.........................................................................................................112
Time Base Interrupts.............................................................................................................113
EEPROM Interrupt................................................................................................................114
TM Interrupts.........................................................................................................................114
Interrupt Wake-up Function...................................................................................................114
Programming Considerations................................................................................................114

SCOM Function for LCD – HT66F004...........................................................115

LCD Peration.........................................................................................................................115
LCD Bias Current Control.....................................................................................................116

Application Circuits.......................................................................................117

Rev. 2.30

4June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Instruction Set................................................................................................118

Introduction...........................................................................................................................118
Instruction Timing..................................................................................................................118
Moving and Transferring Data...............................................................................................118
Arithmetic Operations............................................................................................................118
Logical and Rotate Operation...............................................................................................119
Branches and Control Transfer.............................................................................................119
Bit Operations.......................................................................................................................119
Table Read Operations.........................................................................................................119
Other Operations...................................................................................................................119

Instruction Set Summary............................................................................. 120

Table Conventions................................................................................................................ 120

Instruction Definition.................................................................................... 122
Package Information.................................................................................... 131

8-pin SOP (150mil) Outline Dimensions.............................................................................. 132
10-pin SOP (150mil) Outline Dimensions............................................................................ 133
10-pin MSOP Outline Dimensions....................................................................................... 134
16-pin NSOP (150mil) Outline Dimensions.......................................................................... 135
20-pin SOP (300mil) Outline Dimensions............................................................................ 136
20-pin SSOP (150mil) Outline Dimensions.......................................................................... 137
20-pin NSOP (150mil) Outline Dimensions.......................................................................... 138
24-pin SSOP (150mil) Outline Dimensions.......................................................................... 139

Rev. 2.30

5June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Features
CPU Features• Operating Voltage♦

fSYS = 8MHz: 2.2V~5.5V• Up to 0.5μs instruction cycle with 8MHz system clock at VDD=5V• Power down and wake-up functions to reduce power consumption• Two Oscillators♦

Internal High Speed 8MHz RC -- HIRC♦Internal Low Speed 32kHz RC -- LIRC

• Fully intergrated internal oscillator requires no external components• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP• All instructions executed in one or two instruction cycles• Table read instructions• 61 powerful instructions• Up to 4-level subroutine nesting• Bit manipulation instruction

Peripheral Features• Flash Program Memory: 1K×14/2K×15• RAM Data Memory: 64×8/96×8• True EEPROM Memory: 32×8
• Watchdog Timer function• Up to 18 bidirectional I/O lines• Software controlled 4-SCOM lines LCD driver with 1/2 bias (only available for HT66F004)• Multiple pin-shared external interrupts• Multiple Timer Modules for time measure, compare match output, capture input, PWM output,
single pulse output functions• Dual Time Base functions for generation of fixed time interrupt signals• Multi-channel 12-bit resolution A/D converter• Low voltage reset function• Wide range of available package types• Flash program memory can be re-programmed up to 10,000 times• Flash program memory data retention > 10 years• True EEPROM data memory can be re-programmed up to 100,000 times• True EEPROM data memory data retention > 10 years

Rev. 2.30

6June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
General Description
The devices are Flash Memory type 8-bit high performance RISC architecture microcontrollers.
Offering users the convenience of Flash Memory multi-programming features, these devices also
include a wide range of functions and features. Other memory includes an area of RAM Data
Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
Analog features include a multi-channel 12-bit A/D converter function. Multiple and extremely
flexible Timer Modules provide timing, pulse generation, capture input, compare match output,
single pulse output and PWM generation functions. Protective features such as an internal Watchdog
Timer and Low Voltage Reset coupled with excellent noise immunity and ESD protection ensurethat reliable operation is maintained in hostile electrical environments.
A full choice of HIRC and LIRC oscillator functions are provided including a fully integrated
system oscillator which requires no external components for its implementation.
The inclusion of flexible I/O programming features, Time Base functions along with many otherfeatures ensure that the devices will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.

Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory
and Data memory capacity. The following table summarises the main features of each device.
Part No.

Program
Data
Data
A/D
I/O
Memory Memory EEPROM
Converter

Timer
ModuleTime
R-Type
Stack
Base
LCD

Package

HT66F002

1K×14

64×8

32×8

8

12-bit×4

10-bit STM×1

2

2

—

8SOP
10MSOPHT66F0025

2K×14

64×8

32×8

8

12-bit×4

10-bit STM×1

2

4

—

8/10SOP

2

2—

16NSOP

2

4

4SCOM

16/20NSOP
20SOP
20/24SSOP

HT66F003

1K×14

64×8

32×8

14

12-bit×4

10-bit STM×1
10-bit PTM×1

HT66F004

2K×15

96×8

32×8

18

12-bit×8

10-bit PTM×2

Rev. 2.30

7June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Block Diagram
Watchdog
Timer
Flash/EEPROM
Programming Circuitry

EEPROM
Data
MemoryLow Voltage
Reset

Flash
Program
Memory

8-bit
RISC
MCU
Core

Reset
CircuitInterrupt
Controller

Time
Bases

Internal RC
Oscillators
12-bit A/DConverterI/O

RAM Data
MemoryTimer
Modules

Software LCD
DriverLCD Driver only for HT66F004

Note: LCD function is only available for HT66F004.

Pin Assignment
VDD/AVDD
PA6/STP0I/[STCK0]

1

8

VSS/AVSS2

7

PA0/[STP0]/[STP0I]/AN0/ICPDA

PA5/INT/STP0B/AN3

3

6

PA1/[STP0B]/AN1/VREF

PA7/[INT]/STCK0/RES/ICPCK45

PA2/[INT]/STP0/AN2/VREFO

HT66F002/HT66F0025
8 SOP-A
VDD/AVDD
PA6/STP0I/[STCK0]

1

10

2

9

PA0/[STP0]/[STP0I]/AN0/ICPDA

PA5/INT/STP0B/AN3

3

8

PA1/[STP0B]/AN1/VREF

PA7/[INT]/STCK0/RES/ICPCK

47

PA2/[INT]/STP0/AN2/VREFO

PA4

5

6

PA3/[INT]

VSS/AVSS

HT66F002
10 MSOP-A
VDD/AVDD
PA6/STP0I/[STCK0]

1

10

2

9

PA0/[STP0]/[STP0I]/AN0/ICPDA

PA5/INT/STP0B/AN3

3

8

PA1/[STP0B]/AN1/VREF

PA7/[INT]/STCK0/RES/ICPCK

47

PA2/[INT]/STP0/AN2/VREFO

PA4

5

6

PA3/[INT]

VSS/AVSS

HT66F0025
10 SOP-A

Rev. 2.30

8June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
VDD/AVDD
PA6/STP0I/[STCK0]

1

16

VSS/AVSS2

15

PA0/[STP0]/[STP0I]/AN0/ICPDA

PA5/INT/STP0B/AN3

3

14

PA1/[STP0B]/AN1/VREF

PA7/[INT]/STCK0/RES/ICPCK
PA4
NC

4

13

PA2/[INT]/STP0/AN2/VREFO

5

12

PA3/[INT]

6

11

NC

7

10

NC
NC

OCDSCK

8

9OCDSDA

HT66V002/HT66V0025
16 NSOP-A
PB2/PTP1B

1

16

PB1/[PTCK1]/STP0B

2

15

PB3/[PTP1]
PB4/[PTP1B]

PB0/[PTP1I]/VREFO

3

14

PB5/PTP1

PA3/INT/STCK0/AN3

4

13PA4/[INT]/PTCK1/STP0

PA2/[INT]/[STCK0]/AN2/OCDSCK/ICPCK

5

12

PA1/AN1/VREF

6

11

PA5/[INT]/PTP1I
PA6/[PTCK1]/STP0I/[STP0]

PA0/[STP0I]/AN0/OCDSDA/ICPDA

7

10

PA7/[PTCK1]/[STP0B]/RES

VSS/AVSS

89

VDD/AVDD

HT66F003/HT66V003
16 NSOP-A
VSS/AVSS

1

16

VDD/AVDD

PC0/SCOM0

2

15

PB0/INT0/AN0

PC1/SCOM1

3

14

PB1/INT1/AN1

PC2/RES
PA0/PTP0/ICPDA/OCDSDA

413

PB2/PTCK0/AN2

5

12

PA4/PTCK1/AN3

PA1/PTP0I

6

11

PA5/AN4/VREF

PA2/ICPCK/OCDSCK

7

10

PA6/AN5/VREFO

PA3/PTP1I

8

9

PA7/PTP1/AN6

HT66F004/HT66V004
16 NSOP-A
VSS/AVSS

1

20

VDD/AVDD

PC0/SCOM0

2

19

PB0/INT0/AN0

PC1/SCOM1

3

18

PB1/INT1/AN1

PC2/RES
PA0/PTP0/ICPDA/OCDSDA

417

PB2/PTCK0/AN2

5

16

PA4/PTCK1/AN3

PA1/PTP0I

615

PA5/AN4/VREF

PA2/ICPCK/OCDSCK714

PA6/AN5/VREFO

PA3/PTP1I

8

13

PA7/PTP1/AN6

PB6/PTP1B

912

PB3/SCOM3/AN7

PB5/PTP0B

10

11

PB4/CLO/SCOM2HT66F004/HT66V004
20 SOP-A/SSOP-A/NSOP-A

Rev. 2.30

9June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
NC

1

24

NC

VSS/AVSS

2

23

VDD/AVDD

PC0/SCOM0

322

PB0/INT0/AN0

PC1/SCOM1

4

21

PB1/INT1/AN1

PC2/RES

520

PB2/PTCK0/AN2

PA0/PTP0/ICPDA

619

PA4/PTCK1/AN3

PA1/PTP0I

718

PA5/AN4/VREF

PA2/ICPCK

8

17

PA6/AN5/VREFO

PA3/PTP1I

9

16

PA7/PTP1/AN6

PB6/PTP1B

10

15

PB3/SCOM3/AN7

PB5/PTP0B

11

14

PB4/CLO/SCOM2

NC

12

13

NC

HT66F004
24 SSOP-A

Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. AVDD&VDD means the VDD and AVDD are the double bonding. VSS&AVSS means the VSS and
AVSS are the double bonding.
3. The OCDSDA and OCDSCK pins are the OCDS dedicated pins.

Pin Description
With the exception of the power pins and some relevant transformer control pins, all pins on thesedevices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/Ofunction of the pins. However these Port pins are also shared with other function such as the Analog
to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table,
however the details behind how each pin is configured is contained in other sections of the datasheet.
HT66F002/HT66F0025
Pin NamePA0/[STP0]/[STP0I]/AN0/
ICPDA

PA1/[STP0B]/
AN1/VREF

PA2/[INT]/
STP0/AN2/
VREFORev. 2.30

Function

OPT

I/T

O/T

Description

PA0

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

STP0

PASR

—

CMOS

TM0 (STM) output

STP0I

PASR
IFS0

ST

—

TM0 (STM) input
ADC input channel 0

AN0

PASR

AN

—

ICPDA

—

ST

CMOS

ICP Data Line

PA1

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

STP0B

PASR

—

CMOS

TM0 (STM) inverting output

AN1

PASR

AN

—

ADC input channel 1

VREF

PASR

AN

—

ADC VREF Input

PA2

PAWU
PAPU
PASR

ST

CMOS

INT

PASR
IFS0

ST

—

STP0

PASR

—

CMOS

TM0 (STM) output

AN2

PASR

AN

—

ADC input channel 2

VREFO

PASR

—

AN

ADC reference voltage output

10

General purpose I/O. Register enabled pull-up andwake-upExternal interrupt input

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Pin Name

Function

OPT

I/T

O/T

Description

PA3

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

INT

PASR
IFS0

ST

—

PA4

PAWU
PAPU

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

PA5

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

INT

PASR
IFS0

ST

—

STP0B

PASR

—

CMOS

AN3

PASR

AN

—

PA6

PAWU
PAPU

ST

CMOS

PA3/[INT]

PA4

PA5/INT/STP0B/AN3

PA6/STP0I/[STCK0]PA7/[INT]/
STCK0/RES/ICPCKExternal interrupt input

External interrupt input
TM0 (STM) inverting output
ADC input channel 3
General purpose I/O. Register enabled pull-up andwake-up

STP0I

IFS0

ST

—

TM0 (STM) input

STCK0

IFS0

ST

—

TM0 (STM) clock input

PA7

PAWU
PAPU

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

INT

IFS0

ST

—

External interrupt input

STCK0

IFS0

ST

—

TM0 (STM) clock input

RES

RSTC

ST

—

External reset input

ICPCK

—

ST

CMOS

VDD

VDD

—

PWR

—

Digital positive power supply

AVDD

AVDD

—

PWR

—

Analog positive power supply

VSS

VSS

—

PWR

—

Digital negative power supply

AVSS

AVSS

—

PWR

—

Analog negative power supply

OCDSCKOCDSCK—ST—

On Chip Debug System Clock Line (OCDS EV only)

OCDSDAOCDSDA

—

ST

CMOS

On Chip Debug System Data Line (OCDS EV only)

Function

OPT

I/T

O/T

Description

PA0

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

STP0I

PASR
IFS0

ST

—

TM0 (STM) input
ADC input channel 0

ICP Clock Line

HT66F003
Pin NamePA0/[STP0I]/
AN0/OCDSDA/ICPDA

PA1/AN1/VREF

Rev. 2.30

AN0

PASR

AN

—

OCDSDA

—

ST

CMOS

On Chip Debug System Data Line (OCDS EV only)

ICPDA

—

ST

CMOS

ICP Data Line

PA1

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

AN1

PASR

AN

—

ADC input channel 1

VREF

PASR

AN

—

ADC VREF Input

11

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Pin NamePA2/[INT]/[STCK0]/AN2/OCDSCK/ICPCK

PA3/INT/STCK0/AN3

PA4/[INT]/PTCK1/STP0

PA5/[INT]/
PTP1I

PA6/[PTCK1]/STP0I/[STP0]

PA7/[PTCK1]/[STP0B]/RES

PB0/[PTP1I]/
VREFO

Rev. 2.30

Function

OPT

I/T

O/T

Description

PA2

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

INT

PASR
IFS0

ST

—

External interrupt input

STCK0

IFS0

ST

—

TM0 (STM) clock input

AN2

PASR

AN

—

ADC input channel 2

OCDSCK—ST—

On Chip Debug System Clock Line (OCDS EV
only)

ICPCK

—

ST

CMOS

ICP Clock Line

PA3

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

INT

PASR
IFS0

ST

—

External interrupt input

STCK0

IFS0

ST

—

TM0 (STM) clock input

AN3

PASR

AN

—

ADC input channel 3

PA4

PAWU
PAPU
PASR

ST

CMOS

INT

PASR
IFS0

ST

—

External interrupt input

PTCK1

PASR
IFS0

ST

—

TM1 (PTM) clock input

STP0

PASR

—

CMOS

TM0 (STM) output

PA5

PAWU
PAPU

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

INT

PASR
IFS0

ST

—

External interrupt input

PTP1I

IFS0

ST

—

TM1 (PTM) input

PA6

PAWU
PAPU
PASR

ST

CMOS

PTCK1

PASR
IFS0

ST

—

TM1 (PTM) clock input

STP0I

PASR
IFS0

ST

—

TM0 (STM) input

STP0

PASR

—

CMOS

TM0 (STM) output

PA7

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

PTCK1

PASR
IFS0

ST

—

STP0B

PASR

ST

CMOS

RES

RSTC

ST

—

PB0

PBPU
PBSR

ST

CMOS

PTP1I

PBSR
IFS0

ST

—

TM1 (PTM) input

VREFO

PBSR

—

AN

ADC reference voltage output

12

General purpose I/O. Register enabled pull-up andwake-upGeneral purpose I/O. Register enabled pull-up andwake-up

TM1 (PTM) clock input
TM0 (STM) inverting output
External reset input
General purpose I/O. Register enabled pull-up

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Pin Name

Function

OPT

I/T

O/T

PB1

PBPU
PBSR

ST

CMOS

PTCK1

PBSR
IFS0

ST

—

STP0B

PBSR

ST

CMOS

TM0 (STM) inverting output

PB2

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

PTP1B

PBSR

ST

CMOS

TM1 (PTM) inverting output

PB3

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

PTP1

PBSR

—

CMOS

TM1 (PTM) output

PB4

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

PTP1B

PBSR

—

CMOS

TM1 (PTM) inverting output

PB5

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

PTP1

PBSR

—

CMOS

TM1 (PTM) output

VDD

VDD

—

PWR

—

Digital positive power supply

AVDD

AVDD

—

PWR

—

Analog positive power supply

VSS

VSS

—

PWR

—

Digital negative power supply

AVSS

AVSS

—

PWR

—

Analog negative power supply

Function

OPT

I/T

O/T

Description

PA0

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

PB1/[PTCK1]/
STP0B

PB2/PTP1B

PB3/[PTP1]

PB4/[PTP1B]

PB5/PTP1

Description
General purpose I/O. Register enabled pull-up
TM1 (PTM) clock input

HT66F004
Pin Name
PA0/PTP0/OCDSDA/
ICPDA

PA1/PTP0I

PA2/ICPCK/OCDSCK

PA3/PTP1I

PA4/PTCK1/
AN3

PA5/AN4/VREF

Rev. 2.30

PTP0

PASR

—

CMOS

PT0 output

OCDSDA

—

ST

CMOS

On Chip Debug System Data Line (OCDS EV only)

ICPDA

—

ST

CMOS

ICP Data Line

PA1

PAWU
PAPU

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

PTP0I

—

ST

—

PA2

PAWU
PAPU

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

ICPCK

—

ST

CMOS

ICP Clock LineOCDSCK

—

ST

—

PA3

PAWU
PAPU

ST

CMOS

PTP1I

—

ST

—

PA4

PAWU
PAPU
PASR

ST

CMOS

PTCK1

PASR

ST

—

PTM1 clock input

AN3

PASR

AN

—

ADC input channel 3

PA5

PAWU
PAPU
PASR

ST

CMOS

AN4

PASR

AN

—

ADC input channel 4

VREF

PASR

AN

—

ADC VREF Input

13

PTM0 input

On Chip Debug System Clock Line (OCDS EV
only)
General purpose I/O. Register enabled pull-up andwake-up
PTM1 input
General purpose I/O. Register enabled pull-up andwake-upGeneral purpose I/O. Register enabled pull-up andwake-upJune 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Pin Name
PA6/AN5/
VREFO

PA7/PTP1/AN6

PB0/INT0/AN0PB1/INT1/AN1

PB2/PTCK0/
AN2

PB3/SCOM3/
AN7

PB4/CLO/SCOM2

PB5/PTP0B

PB6/PTP1B
PC0/SCOM0
PC1/SCOM1
PC2/RES

Function

OPT

I/T

O/T

Description

PA6

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

AN5

PASR

AN

—

ADC input channel 5

VREFO

PASR

—

AN

ADC reference voltage output

PA7

PAWU
PAPU
PASR

ST

CMOS

General purpose I/O. Register enabled pull-up andwake-up

PTP1

PASR

—

CMOS

PTM1 output

AN6

PASR

AN

—

PB0

PBPU
PBSR

ST

CMOS

INT0

PBSR

ST

—

External interrupt input

AN0

PBSR

AN

—

ADC input channel 0

PB1

PBPU
PBSR

ST

CMOS

INT1

PBSR

ST

—

External interrupt input

AN1

PBSR

AN

—

ADC input channel 1

PB2

PBPU
PBSR

ST

CMOS

PTCK0

PBSR

ST

—

PTM0 clock input

AN2

PBSR

AN

—

ADC input channel 2

PB3

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

SCOM3

SCOMC

—

SCOM

LCD driver output for LCD panel common

AN7

PBSR

AN

—

PB4

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

ADC input channel 6
General purpose I/O. Register enabled pull-up

General purpose I/O. Register enabled pull-up

General purpose I/O. Register enabled pull-up

ADC input channel 7

CLO

PBSR

—

CMOS

System clock output

SCOM2

SCOMC

—

SCOM

LCD driver output for LCD panel common

PB5

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

PTP0B

PBSR

ST

CMOS

PTM0 inverting output

PB6

PBPU
PBSR

ST

CMOS

General purpose I/O. Register enabled pull-up

PTP1B

PBSR

ST

CMOS

PTM1 inverting output

PC0

PCPU

ST

CMOS

General purpose I/O. Register enabled pull-up

SCOM0

SCOMC

—

SCOM

LCD driver output for LCD panel common

PC1

PCPU

ST

CMOS

General purpose I/O. Register enabled pull-up

SCOM1

SCOMC

—

SCOM

LCD driver output for LCD panel common

PC1

PCPU
RSTC

ST

CMOS

General purpose I/O. Register enabled pull-up

RES

RSTC

ST

—

External reset input

VDD

VDD

—

PWR

—

Digital positive power supply

AVDD

AVDD

—

PWR

—

Analog positive power supply

VSS

VSS

—

PWR

—

Digital negative power supply

AVSS

AVSS

—

PWR

—

Analog negative power supply

NC

NC

—

—

—

Not connected

Legend: I/T: Input type;		
O/T: Output type;		
PWR: Power;
OP: Optional by register option SCOM: Software controlled LCD COM
ST: Schmitt Trigger input;
CMOS: CMOS output;
AN: Analog pin

Rev. 2.30

14June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded
together internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together
internally with VSS.

Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
IOL Total...................................................................................................................................... 80mA
IOH Total.....................................................................................................................................-80mA
Total Power Dissipation.......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices atother conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.

D.C. Characteristics
Ta = 25°C
SymbolParameter

Test Conditions
VDD

Conditions

Min.

Typ.

Max.

Unit

VDD

Operating Voltage (HIRC)—

fSYS=8MHz

2.2

—

5.5

V

IDD1

Operating Current,
Normal Mode, fSYS=fH (HIRC)

3V

No load, fH=8MHz, ADC off,
WDT enable, LVR enable

—

1.0

2.0

mA

—

2.0

3.0

mA

Operating Current,
Slow Mode, fSYS=fL=LIRC

3V

No load, fSYS=LIRC, ADC off,
WDT enable , LVR enable

—

20

30

μA

—

30

60

μA

No load, fSYS=fH/2, ADC off,
WDT enable, LVR enable

—

1.0

1.5

mA

—

1.5

2.0

mA

No load, fSYS=fH/4, ADC off,
WDT enable, LVR enable

—

0.9

1.3

mA

—

1.3

1.8

mA

No load, fSYS=fH/8, ADC off,
WDT enable, LVR enable

—

0.8

1.1

mA

—

1.1

1.6

mA

No load, fSYS=fH/16, ADC off,
WDT enable, LVR enable

—

0.7

1.0

mA

—

1.0

1.4

mA

No load, fSYS=fH/32, ADC off,
WDT enable, LVR enable

—

0.6

0.9

mA

—

0.9

1.2

mA

No load, fSYS=fH/64, ADC off,
WDT enable, LVR enable

—

0.5

0.8

mA

—

0.8

1.1

mA

No load, ADC off, WDT enable,
LVR disable

—

1.3

3.0

μA

—

5.0

10

μA

No load, ADC off, WDT enable,
fSYS=8MHz on

—

0.8

1.6

mA

—

1.0

2.0

mA

IDD2

5V
5V
3V
5V
3V
5V
3V

IDD3

Operating Current,
Normal Mode, fH=8MHz (HIRC)

5V
3V
5V
3V
5V
3V
5V

IIDLE0

IDLE0 Mode Standby Current(LIRC on)3V

IIDLE1

IDLE1 Mode Standby Current(HIRC)

3V

Rev. 2.30

5V

5V

15

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

SymbolParameter

Test Conditions

Min.

Typ.

Max.

Unit

No load, ADC off, WDT disable,
LVR disable

—

0.1

1.0

μA

—

0.3

2.0

μA

—

1.3

5.0

μA

—

2.2

10

μA

VDD

Conditions

ISLEEP0SLEEP0 Mode Standby Current(LIRC off)

3V

ISLEEP1SLEEP1 Mode Standby Current(LIRC on)

3V
5V

No load, ADC off, WDT enable,
LVR disable

VIL1

Input Low Voltage for I/O Ports or
Input Pins except RES pin

5V

—

0

—

1.5

V

—

—

0

—

0.2VDDV

VIH1

Input High Voltage for I/O Ports or
Input Pins except RES pin

5V

—

3.5

—

5.0

V

—

—

0.8VDD

—

VDD

V

VIL2

Input Low Voltage (RES)

—

—

0

—

0.4VDDV

VIH2

Input High Voltage (RES)——

0.9VDD

—

VDD

V

IOL
IOH

I/O Port Sink Current
I/O Port, Source Current

RPH

Pull-high Resistance for I/O Ports

IOCDS

Operating Current, Normal Mode,fSYS=fH (HIRC) (for OCDS EV
testing, connect to an e-Link)

5V

3V

VOL=0.1VDD

18

36

—

mA

5V

VOL=0.1VDD

40

80

—

mA

3V

VOH=0.9VDD

-3

-6

—

mA

5V

VOH=0.9VDD

-7

-14

—

mA

3V

—

20

60

100

kΩ

5V

—

10

30

50

kΩ

—

1.4

2.0

mA

3V

No load, fH=8MHz, ADC off,
WDT enable

A.C. Characteristics
Ta = 25°C
SymbolfCPU

fHIRC

Parameter
Operating Clock

System Clock (HIRC)

Test Conditions
VDD

Condition

2.2~5.5V

—

Typ.

Max.

Unit

DC

—

8

MHz

3V/5V

Ta = 25°C

-2%

8

+2%

MHz

3V/5V

Ta = 0°C to 70°C

-5%

8

+5%

MHz

2.2V~5.5V Ta = 0°C to 70°C

-8%

8

+8%

MHz

2.2V~5.5V Ta = -40°C to 85°C

-12%

8

+12% MHzfLIRC

System Clock (LIRC)

tTIMERxTCKn, xTPnI Input Pulse Width

—

—

tRES

External Reset Low Pulse Width

—

tINT

Interrupt Pulse Width

—

tEERD

EEPROM Read Time

—

tEEWR

EEPROM Write Time

—

tSST

System Start-up Timer Period(Wake-up from HALT, fSYS off at
HALT state)—

System Reset Delay Time
(Power On Reset, LVR reset, WDT
S/W reset(WDTC)—

System Reset Delay Time(RES reset, WDT normal reset)

—

tRSTD

Min.

2.2V~5.5V Ta = -40°C to 85°C

8

32

50

kHz

0.3

—

—

μs

—

10

—

—

μs

—

0.3

—

—

μs

—

—

2

4

tSYS
ms

—

2

5

fSYS =HIRC

—

16

—

—

fSYS =LIRC

2

—

—

—

25

50

100

ms

—

8.3

16.7

33.3

ms

tSYS

Note: 1. tSYS= 1/fSYS
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.

Rev. 2.30

16

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
A/D Converter Electrical Characteristics
Ta = 25°C
SymbolAVDD

A/D Converter Input Voltage

VREF

A/D Converter Reference Voltage

INL

VDD

Conditions——

A/D Converter Operating Voltage

VADI

DNL

Test Conditions

Parameter

Differential non-linearity
Integral non-linearity

—

—

—

—

Min. Typ.

Max.

Unit

—

5.5

V

—

AVDD/
VREF

V

2

—

AVDD

V

—

±15

—

LSB

2.2
0

2.2V~2.7V VREF=AVDD=VDD, tADCK=8μs
2.7V~5.5V VREF=AVDD=VDD, tADCK=0.5μs

-3

—

+3

LSB

2.2V~2.7V VREF=AVDD=VDD, tADCK=8μs

—

±16

—

LSB

2.7V~5.5V VREF=AVDD=VDD, tADCK=0.5μs

-4

—

+4

LSB

3V

No load (tADCK=0.5μs)

—

1.0

2.0

mA

5V

No load (tADCK=0.5μs)

—

1.5

3.0

mA

IADC

Additional Current for A/DConverter EnabletADCK

A/D Converter Clock PeriodtADC

A/D Conversion Time
(Include Sample and Hold Time)

—

tADS

A/D Converter Sampling Time——

tON2ST

A/D Converter On-to-Start Time——

2.2V~2.7V

—

8

—

10

μs

2.7V~5.5V

—

0.5

—

10

μs

16

—

20

tADCK

—

4

—

tADCK

4

—

—

μs

12-bit A/D converter

OPA Electrical Characteristics
Ta = 25°C
SymbolParameter

Test Conditions
VDD

AVDD

OPA Operating Voltage

—

IOPA

OPA Operating Current

5V

VOPOS1

Input Offset Voltage

5V

VCM

Common Mode Voltage Range

5V

PSRR

Power Supply Rejection Ratio

CMRR
SR
GBW

Conditions

Min.

—

Typ.

Max.

Unit

2.7

─

5.5

V

─

200

350

μA

—

-15

─

15

mV

—

0.2

─

VDD-1.4

V

5V

—

60

80

─

dB

Common mode Rejection Ratio

5V

—

60

80

─

dB

Slew rate +, Slew rate -

5V

—

0.8

1.5

─

V/μs

Gain Band Width

5V—

No loadERRG

OPA Gain Error

5V

Gain=1/2/3/4
If OPA input voltage ≥ 0.2V

tSTART

OPA Turn On Stable Time—No external load

500

─

─

kHz

-5

Gain

+5

%

—

—

22

μs

Typ.

Max.

Unit

LVR Electrical Characteristics
SymbolParameter

Test Conditions
VDD

Conditions
—

Min.

VDD

Operating Voltage

—

1.9

—

5.5

V

VLVR

Low Voltage Reset Voltage— LVR Enable, 2.1V option

-5%

2.10

+5%

V

VBG

Reference Output with Buffer— TJ = +25°C @3.15V

-5%

1.04

+5%

V

tBGS

VBG Turn On Stable Time

— No load

—

—

200

μs

tLVR

Minimum Low Voltage Width to Reset

—

160

320

640

μs

Rev. 2.30—

17June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
LCD Electrical Characteristics – HT66F004
SymbolIBIASParameter

VDD/2 Bias Current for LCD

VSCOM

Test Conditions

Min.

Typ.

Max.

Unit

ISEL[1:0]=00

17.5

25.0

32.5

μA

ISEL[1:0]=01

35

50

65

μA

ISEL[1:0]=10

70

100

130

μA

ISEL[1:0]=11

140

200

260

μA

0.475

0.5

0.525

VDD

VDD

Conditions

5V

VDD/2 Voltage for LCD COM Port 2.2~5.5V No load

Power on Reset Electrical Characteristics
Ta = 25°C
SymbolTest Conditions

Parameter

VDD

Conditions

Min.

Typ. Max. Unit

VPOR

VDD Start Voltage to Ensure Power-on Reset

—

—

—

—

100

mV

RRPOR

VDD Rising Rate to Ensure Power-on Reset

—

—

0.035

—

—

V/ms

tPOR

Minimum Time for VDD Stays at VPOR to
Ensure Power-on Reset

—

—

1

—

—

ms

  

          

System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The device takes advantage of the usual features found within
RISC microcontrollers providing increased speed of operation and Periodic performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution
are overlapped, hence instructions are effectively executed in one cycle, with the exception of branchor call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which
carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions,etc. The internal data path is simplified by moving data through the Accumulator and the ALU.
Certain internal registers are implemented in the Data Memory and can be directly or indirectly
addressed. The simple addressing methods of these registers along with additional architecturalfeatures ensure that a minimum of external components is required to provide a functional I/O andA/D control system with maximum reliability and flexibility. This makes these devices suitable forlow-cost, high-volume production for controller applications

Clocking and Pipelining
The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into fourinternally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
Rev. 2.30

18

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where thecontents of the Program Counter are changed, such as subroutine calls or jumps, in which case theinstruction will take one more instruction cycle to execute.
                                                                        

 

 

                                                     System Clock and Pipelining

For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute thebranch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
                                                                                          

Instruction Fetching

Program Counter
During program execution, the Program Counter is used to keep track of the address of thenext instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading therequired address into the Program Counter. For conditional skip instructions, once the condition has
been met, the next instruction, which has already been fetched during the present instruction execution,is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Program Counter

DeviceRev. 2.30

Program Counter
High byte

PCL Register

HT66F002/HT66F003

PC9~PC8

PCL7~PCL0

HT66F0025/HT66F004

PC10~PC8

PCL7~PCL0

19

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, isavailable for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle isneeded to pre-fetch.

Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is neither part of the data nor part of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed
onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction,
RET or RETI, the Program Counter is restored to its previous value from the stack. After a device
reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or
RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer
to use the structure more easily. However, when the stack is full, a CALL subroutine instruction canstill be executed which will result in a stack overflow. Precautions should be taken to avoid suchcases which might cause unpredictable program branching. If the stack is overflow, the first Program
Counter save in the stack will be lost.
P ro g ra m

T o p o f S ta c k

S ta c k L e v e l 1

S ta c k
P o in te r
B o tto mo f S ta c k

C o u n te r

P ro g ra m
M e m o ry
S ta c k L e v e l N

DeviceStack Levels

HT66F002/HT66F003

2

HT66F0025/HT66F004

4Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated toreflect these changes. The ALU supports the following functions:• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC• Increment and Decrement: INCA, INC, DECA, DEC• Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Rev. 2.30

20

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For these devices theProgram Memory are Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device. By
using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming and updating.
DeviceCapacity

HT66F002/HT66F003

1K×14

HT66F0025

2K×14

HT66F004

2K×15Structure
The Program Memory has a capacity of 1K×14, 2K×14 or 2K×15 bits. The Program Memory isaddressed by the Program Counter and also contains data, table information and interrupt entries. Table
data, which can be setup in any location within the Program Memory, is addressed by a separate table
pointer register.
000H

HT66F002

HT66F0025

HT66F003

HT66F004

Initialisation Vector Initialisation Vector Initialisation Vector Initialisation Vector

004H
Interrupt Vectors

Interrupt Vectors

Look-up Table

Look-up Table

Interrupt Vectors

Interrupt Vectors

Look-up Table

Look-up Table

018H
01CH
n00H
nFFH

3FFH

14 bits

14 bits
7FFH

14 bits

7FFH

15 bits

Program Memory Structure

Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by these devices reset for program initialisation. After a device reset isinitiated, the program will jump to this location and begin execution.

Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers canstore fixed data. To use the look-up table, the table pointer must first be setup by placing the addressof the look up data to be retrieved in the table pointer register, TBLP. This register defines the total
address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the “TABRD[m]” or “TABRDL[m]” instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte fromthe Program Memory will be transferred to the TBLH special register. Any unused bits in thistransferred higher order byte will be read as “0”.
Rev. 2.30

21

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
The accompanying diagram illustrates the addressing data flow of the look-up table.
                
 


  

                                                            






Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from themicrocontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is “300H” which refers to the start
address of the last page within the 1K words Program Memory of the device. The table pointer issetup here to have an initial value of “06H”. This will ensure that the first data read from the datatable will be at the Program Memory address “306H” or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address of the specified page if the“TABRD [m]” instruction is being used. The high byte of the table data which in this case is equal
to zero will be transferred to the TBLH register automatically when the “TABRD [m]” instruction is
executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change thevalue of the TBLH and subsequently cause errors if used again by the main routine. As a rule it isrecommended that simultaneous use of the table read instructions should be avoided. However, insituations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Table Read Program Example
tempreg1 db ?		 ; temporary register #1
tempreg2 db ?		 ; temporary register #2::
mov a,06h 			 ; initialise low table pointer - note that this address is referenced
mov tblp,a			 ; to the last page or present page::tabrd tempreg1		 ; transfers value in table referenced by table pointer data at program					; memory address “306H” transferred to tempreg1 and TBLH
dec tblp 			 ; reduce value of table pointer by one
tabrd tempreg2 		 ; transfers value in table referenced by table pointer data at program					; memory address “305H” transferred to tempreg2 and TBLH in this					 ; example the data “1AH” is transferred to tempreg1 and data “0FH” to					; register tempreg2::
org 300h				; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::
Rev. 2.30

22

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
In Circuit Programming – ICPThe provision of Flash type Program Memory provides the user with a means of convenient and easy
upgrades and modifications to their programs on the same device. As an additional convenience,
Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface.
This provides manufacturers with the possibility of manufacturing their circuit boards complete witha programmed or un-programmed microcontroller, and then programming or upgrading the programat a later stage. This enables product manufacturers to easily keep their manufactured products
supplied with the latest program releases without removal and re-insertion of the device.
HoltekWrite Pins

MCU Programming Pins
HT66F002/HT66F0025

ICPDA

Function

HT66F003/HT66F004
PA0

ICPCK

PA7

Programming Serial Data
PA2

Programming Serial Clock

VDD

VDD

Power Supply

VSS

VSS

GroundThe Program Memory can be programmed serially in-circuit using this 4-wire interface. Data
is downloaded and uploaded serially on a single pin with an additional line for the clock. Two
additional lines are required for the power supply and ground. The technical details regarding thein-circuit programming of the device are beyond the scope of this document and will be supplied insupplementary literature.
Writer Connector
Signals

Writer Connector
Signals

MCU Programming
Pins

MCU Programming
Pins

Writer_VDD

VDD

Writer_VDD

VDD

ICPDA

PA0

ICPDA

PA0

ICPCK

PA7

ICPCK

PA2

Writer_VSS

VSS

Writer_VSS

VSS

*

*

*

*

To other Circuit

To other Circuit

HT66F003/HT66F004

HT66F002/HT66F0025

Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be
less than 1nF.

On-Chip Debug Support – OCDS
There is an EV chip which is used to emulate the HT66F00x device series. This EV chip device
also provides an “On-Chip Debug” function to debug the device during the development process.
The EV chip and the actual MCU devices are almost functionally compatible except for the “OnChip Debug” function. Users can use the EV chip device to emulate the real chip device behavior
by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The
OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS
clock input pin. When users use the EV chip for debugging, other functions which are shared with
the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip.
However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as
the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to thecorresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.

Rev. 2.30

23

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Holtek e-Link Pins

EV Chip Pins

OCDSDAOCDSDA

On-chip Debug Support Data/Address input/output

Pin Description

OCDSCKOCDSCK

On-chip Debug Support Clock input

VDD

VDD

Power Supply

GND

VSS

GroundRAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.

Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Manyof these registers can be read from and written to directly under program control, however, someremain protected from user manipulation. The second area of Data Memory is known as the General
Purpose Data Memory, which is reserved for general purpose use. All locations within this area areread and write accessible under program control.
The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers
are accessible in all banks, with the exception of the EEC register at address 40H, which is only
accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the
Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address
00H.

General Purpose Data Memory
There is 64 or 96 bytes of general purpose data memory which are arranged in Bank 0 and Bank1.
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user programing for both reading
and writing operations. By using the bit operation instructions individual bits can be set or reset
under program control giving the user a large range of flexibility for bit manipulation in the Data
Memory.

Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some areprotected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value “00H”.

Rev. 2.30

DeviceCapacity

HT66F002/HT66F0025/HT66F003

64×8

40H~7FH 40H EEC register only

HT66F004

96×8

40H~9FH 40H EEC register only

24

Bank 0Bank 1

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

Bank0 & Bank1
IAR0
MP0
IAR1
MP1
BP
ACC
PCL
TBLP
TBLH
UnusedSTATUS
SMOD
Unused
INTEG
INTC0
INTC1
Unused
MFI0
UnusedUnused
PA
PAC
PAPU
PAWU
IFS0
WDTC
UnusedTBC
SMOD1
Unused
EEA
EED

20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
~
3FH

Bank0 & Bank1
SADOL
SADOH
SADC0
SADC1
SADC2
RSTC
PASR
Unused
STM0C0
STM0C1
STM0DLSTM0DH
STM0ALSTM0AH
Unused: Unused, read as “00”

HT66F002/HT66F0025 Special Purpose Data Memory Structure

Rev. 2.30

25

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

Bank0 & Bank1
IAR0
MP0
IAR1
MP1
BP
ACC
PCL
TBLP
TBLH
UnusedSTATUS
SMOD
Unused
INTEG
INTC0
INTC1
Unused
MFI0
MFI1
Unused
PA
PAC
PAPU
PAWU
IFS0
WDTC
UnusedTBC
SMOD1
Unused
EEA
EED

20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
~
3FH

Bank0 & Bank1
SADOL
SADOH
SADC0
SADC1
SADC2
RSTC
PASR
PBSR
STM0C0
STM0C1
STM0DLSTM0DH
STM0ALSTM0AH
UnusedPB
PBC
PBPU
PTM1C0
PTM1C1PTM1DLPTM1DHPTM1ALPTM1AHPTM1RPL
PTM1RPH
Unused: Unused, read as “00”

HT66F003 Special Purpose Data Memory Structure

Rev. 2.30

26

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

Bank0 & Bank1
IAR0
MP0
IAR1
MP1
BP
ACC
PCL
TBLP
TBLH
UnusedSTATUS
SMOD
Unused
INTEG
INTC0
INTC1
Unused
MFI0
UnusedUnused
PA
PAC
PAPU
PAWU
UnusedWDTC
Unused
TBC
SMOD1
SCOMC
EEA
EED

20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH

Bank0 & Bank1
SADOL
SADOH
SADC0
SADC1
SADC2
RSTC
PASR
PBSR
UnusedPTM0C0
PTM0C1
PTM0DLPTM0DHPTM0ALPTM0AH
PTM0RPL
PTM0RPH
UnusedPTM1C0
PTM1C1PTM1DLPTM1DHPTM1ALPTM1AHPTM1RPL
PTM1RPH
PB
PBC
PBPU
PC
PCC
PCPU

: Unused, read as “00”

HT66F004 Special Purpose Data Memory Structure
HT66F002/HT66F0025/HT66F003
40H

HT66F004
40H

EEC
GeneralPurposeData Memory

EEC
GeneralPurposeData Memory

Unused

7FH

Unused9FH

General Purpose Data Memory

Rev. 2.30

27

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section,
however several registers require a separate description in this section.

Indirect Addressing Registers – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, incontrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as apair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair canaccess data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to theregisters indirectly will result in no operation.

Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used toaccess data from all banks according to BP register. Direct Addressing can only be used with Bank 0,
all other Banks must be addressed indirectly using MP1 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example
data .section ´data´adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block
db ?
code .section at 0 ´code´
org00hstart:
mov a,04h				 ; setup size of block
mov block,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp0,a				 ; setup memory pointer with first RAM address
loop:
clr IAR0				 ; clear the data at address defined by mp0
inc mp0					; increment memory pointersdz block				 ; check if last memory location has been cleared
jmp loop
continue:

The important point to note here is that in the example shown above, no reference is made to specificData Memory addresses.

Rev. 2.30

28

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Bank Pointer – BP
For this series of devices, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting
the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used
to select Data Memory Banks 0~1.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power
Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that theSpecial Function Data Memory is not affected by the bank selection, which means that the Special
Function Registers can be accessed from within any bank. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing
data from Bank1 must be implemented using Indirect Addressing.
• BP Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

—

—

DMBP0

R/W

—

—

—

—

—

—

—

R/W

POR

—

—

—

—

—

—

—

0

Bit 7 ~ 1

Unimplemented, read as "0"

Bit 0

DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1

Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate resultsfrom the ALU are stored. Without the Accumulator it would be necessary to write the result ofeach calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.

Program Counter Low Byte Register – PCL
To provide additional program control functions, the low byte of the Program Counter is madeaccessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.

Look-up Table Registers – TBLP, TBLH
These two special function registers are used to control operation of the look-up table which isstored in the Program Memory. TBLP is the table pointer and indicate the location where the tabledata is located. Its value must be setup before any table read commands are executed. Its value
can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data
pointing and reading. TBLH is the location where the high order byte of the table data is stored
after a table read data instruction has been executed. Note that the lower order table data byte istransferred to a user defined location.

Rev. 2.30

29

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operationand system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not takeplace during a subtraction operation; otherwise C is cleared. C is also affected by a rotate throughcarry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow fromthe high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of thehighest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.

Rev. 2.30

30

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• STATUS Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

TO

PDF

OV

Z

AC

C

R/W

—

—

R

R

R/W

R/W

R/W

R/W

POR

—

—

0

0

×

×

×

×
"×": unknown

Rev. 2.30

Bit 7~6

Unimplemented, read as "0"

Bit 5

TO: Watchdog Time-Out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred

Bit 4

PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction

Bit 3

OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the highestorder bit or vice versa

Bit 2

Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero

Bit 1

AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow from the highnibble into the low nibble in subtraction

Bit 0

C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does not takeplace during a subtraction operation
C is also affected by a rotate through carry instruction.

31

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
EEPROM Data Memory
These devices contain an area of internal EEPROM Data Memory. EEPROM is by its nature a
non-volatile form of memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are madeavailable to the designer. The availability of EEPROM storage allows information such as productidentification numbers, calibration values, specific user data, system setup data or other productinformation to be stored directly within the product microcontroller. The process of reading andwriting data to the EEPROM memory has been reduced to a very trivial affair.

EEPROM Data Memory Structure
The EEPROM Data Memory capacity is 32×8 bits for this series of devices. Unlike the Program
Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped and istherefore not directly accessible in the same way as the other types of memory. Read and Write
operations to the EEPROM are carried out in single byte operations using two address registers andone data register in Bank 0 and a single control register in Bank 1.

EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are theaddress registers, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Bank 0, they can be directly accessed in the same way as any otherSpecial Function Register. The EEC register however, being located in Bank1, cannot be directly
addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointerand Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H
in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register,BP, set to the value, 01H, before any operations on the EEC register are executed.
Bit

Name

7

6

5

4

3

2

1

0

EEA

—

—

—

D4

D3

D2

D1

D0

EED

D7

D6

D5

D4

D3

D2

D1

D0

EEC

—

—

—

—

WREN

WR

RDEN

RD

EEPROM Control Registers List
• EEA Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

D4

D3

D2

D1

D0

R/W

—

—

—

R/W

R/W

R/W

R/W

R/W

POR

—

—

—

0

0

0

0

0

Bit 7 ~ 5

Unimplemented, read as “0”Bit 4 ~ 0

Data EEPROM address
Data EEPROM address bit 4 ~ bit 0• EED Register
Bit

7

6

5

4

3

2

1

0

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7 ~ 0Rev. 2.30

Data EEPROM data
Data EEPROM data bit 7 ~ bit 0

32

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• EEC Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

WREN

WR

RDEN

RD

R/W

—

—

—

—

R/W

R/W

R/W

R/W

POR

—

—

—

—

0

0

0

0

Bit 7 ~ 4

Unimplemented, read as "0"

Bit 3

WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations.

Bit 2

WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application program will
activate a write cycle. This bit will be automatically reset to zero by the hardware after the write
cycle has finished. Setting this bit high will have no effect if the WREN has not first been set
high.

Bit 1

RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations.

Bit 0

RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application program will
activate a read cycle. This bit will be automatically reset to zero by the hardware after the readcycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.

Note: 1. The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The
WR and RD can not be set to “1” at the same time.
2. Ensure that the fSUB clock is stable before executing the write operation.
3. Ensure that the write operation is totally complete before changing the contents of the
EEPROM related registers.

Rev. 2.30

33

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placedin the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. Whenthe read cycle terminates, the RD bit will be automatically cleared to zero, after which the data canbe read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data isvalid for reading.

Writing Data to the EEPROM
The EEPROM address of the data to be written must first be placed in the EEA register and the data
placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC
register must first be set high to enable the write function. After this, the WR bit in the EEC registermust be immediately set high to initiate a write cycle. These two instructions must be executed
consecutively. The global interrupt bit EMI should also first be cleared before implementing any
write operations, and then set again after the write cycle has started. Note that setting the WR bit
high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle iscontrolled using an internal timer whose operation is asynchronous to microcontroller system clock,a certain time will elapse before the data will have been written into the EEPROM. Detecting when
the write cycle has finished can be implemented either by polling the WR bit in the EEC register orby using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically
cleared to zero by the microcontroller, informing the user that the data has been written to the
EEPROM. The application program can therefore poll the WR bit to determine when the write cycle
has ended.

Write Protection
Protection against inadvertent write operation is provided in several ways. After the devices
are powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds afurther measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.

EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an
EEPROM write cycle ends, the DEF request flag will be set. If the global, EEPROM Interrupt are
enabled and the stack is not full, a subroutine call to the EEPROM Interrupt vector, will take place.
When the EEPROM Interrupt is serviced, the EEPROM Interrupt flag DEF will be automatically
cleared. The EMI bit will also be automatically cleared to disable other interrupts.

Rev. 2.30

34

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic
by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank
Pointer could be normally cleared to zero as this would inhibit access to Bank 1where the EEPROM
control register exist. Although certainly not necessary, consideration might be given in theapplication program to the checking of the validity of new write data by a simple read back process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high,to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared
before a write cycle is executed and then re-enabled after the write cycle starts. Note that the devices
should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totallycomplete. Otherwise, the EEPROM read or write operation will fail.
Programming Examples• Reading data from the EEPROM - polling method

MOV A, EEPROM_ADRES 			 ; user defined address
MOV EEA, A
MOV A, 040H					; setup memory pointer MP1
MOV MP1, A					; MP1 points to EEC register
MOV A, 01H					; setup Bank Pointer
MOV BP, A
SET IAR1.1					; set RDEN bit, enable read operations
SET IAR1.0					; start Read Cycle - set RD bit
BACK:SZ IAR1.0					; check for read cycle end
JMP BACK
CLR IAR1						; disable EEPROM write
CLR BPMOV A, EED				 		; move read data to register
MOV READ_DATA, A• Writing Data to the EEPROM - polling method

MOV A, EEPROM_ADRES		
MOV EEA, A
MOV A, EEPROM_DATA			MOV EED, A
MOV A, 040H					MOV MP1, A					MOV A, 01H					MOV BP, A
CLR EMISET IAR1.3					SET IAR1.2													SET EMIBACK:SZ IAR1.2					JMP BACK
CLR IAR1						CLR BP

Rev. 2.30; user defined address; user defined data
; setup memory pointer MP1; MP1 points to EEC register; setup Bank Pointer; set WREN bit, enable write operations; start Write Cycle - set WR bit– executed immediately after; set WREN bit; check for write cycle end; disable EEPROM write

35

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Oscillators
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through registers.

Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. Two fully integrated internal oscillators, requiringno external components, are provided to form a wide range of both fast and slow system oscillators.
The higher frequency oscillator provides higher performance but carry with it the disadvantage ofhigher power requirements, while the opposite is of course true for the lower frequency oscillator.
With the capability of dynamically switching between fast and slow system clock, these devices
have the flexibility to optimize the performance/power ratio, a feature especially important in power
sensitive portable applications.
Type

Name

Freq.

Internal High Speed RC

HIRC

8MHz

Internal Low Speed RC

LIRC

32kHz

Oscillator Types

System Clock Configurations
There are two methods of generating the system clock, a high speed oscillator and a low speed
oscillator. The high speed oscillator is the internal 8MHz RC oscillator. The low speed oscillator is
the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as thesystem oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD registerand as the system clock can be dynamically selected.

fH/2
fH/4
High Speed Oscillator
HIRC

fH/8

fH

Prescaler

fSYS

fH/16
fH/32
fH/64

HLCLK
CKS2~CKS0 bits

Low Speed Oscillator
LIRC

fL

System Clock Configurations

Rev. 2.30

36

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Internal High Speed RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used toensure that the influence of the power supply voltage, temperature and process variations on theoscillation frequency are minimised. As a result, at a power supply of 5V and at temperature of 25°C
degrees, the fixed oscillation frequency of the HIRC will have a tolerance within 2%.

Internal 32kHz Oscillator – LIRC
The internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated
RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its
implementation. Device trimming during the manufacturing process and the inclusion of internalfrequency compensation circuits are used to ensure that the influence of the power supply voltage,
temperature and process variations on the oscillation frequency are minimised.

Supplementary Oscillator
The low speed oscillator, in addition to providing a system clock source is also used to provide
a clock source to two other device functions. These are the Watchdog Timer and the Time Base
Interrupts.

Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especiallytrue in battery powered portable applications. The fast clocks required for high performance willby their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided these devices with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.

System Clocks
These devices have two different clock sources for both the CPU and peripheral function operation.
By providing the user with clock options using register programming, a clock system can be
configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or a low frequency, fL, and isselected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system
clock can be sourced from HIRC oscillator. The low speed system clock source can be sourced fromthe internal clock fL. The other choice, which is a divided version of the high speed system oscillator
has a range of fH/2~fH/64.
There is one additional internal clock for the peripheral circuits, the Time Base clock, fTBC. fTBC issourced from the LIRC oscillators. The fTBC clock is used as a source for the Time Base interrupt
functions and for the TMs.

Rev. 2.30

37

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

fH/2
fH/4
High Speed Oscillator
HIRC

fH/8

fH

Prescaler

fSYS

fH/16
fH/32
fH/64

Low Speed Oscillator
LIRC

fLIRC

HLCLK
CKS2~CKS0 bits

fL

WDT

fTBC
fTB

IDLEN
fSYS/4

Time Base 0Time Base 1

TBCK

System Clock Configurations

Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation willstop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use.

System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance andpower requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,SLEEP1, IDLE0 and IDLE1 modes are used when the microcontroller CPU is switched off toconserve power.
Description

Operating
Mode

CPU

fSYS

fLIRC

fTBC

NORMAL modeOn

fH~fH/64

On

On

SLOW mode

On

fL

On

On

IDLE0 mode

Off

Off

On

On

IDLE1 mode

Off

On

On

On

SLEEP0 mode

Off

Off

Off

Off

SLEEP1 mode

Off

Off

On

Off

NORMAL ModeAs the name suggests this is one of the main operating modes where the microcontroller has allof its functions operational and where the system clock is provided the high speed oscillator. Thismode operates allowing the microcontroller to operate normally with a clock source will come fromthe high speed oscillator HIRC. The high speed oscillator will however first be divided by a ratio
ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the
SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided
clock ratio reduces the operating current.
Rev. 2.30

38

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower
speed clock source. The clock source used will be from the low speed oscillator LIRC. Runningthe microcontroller in this mode allows it to run with much lower operating currents. In the SLOW
Mode, the fH is off.
SLEEP0 Mode
The SLEEP Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fLIRC clock will be
stopped too, and the Watchdog Timer function is disabled.
SLEEP1 Mode
The SLEEP Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fLIRC clocks willcontinue to operate if the Watchdog Timer function is enabled.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the SMOD1 register is low. In the IDLE0 Mode thesystem oscillator will be inhibited from driving the CPU but some peripheral functions will remain
operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be
stopped.
IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the SMOD1 register is high. In the IDLE1 Mode thesystem oscillator will be inhibited from driving the CPU but may continue to provide a clock source
to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1
Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low
speed system oscillator. In the IDLE1 Mode, the Watchdog Timer clock, fLIRC, will be on.

Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
• SMOD Register
Bit

7

6

5

4

3

2

1

0

Name

CKS2

CKS1

CKS0

—

LTO

HTO

IDLEN

HLCLK

R/W

R/W

R/W

R/W

—

R

R

R/W

R/W

POR

0

0

0

—

0

0

1

1

Bit 7 ~ 5

CKS2 ~ CKS0: The system clock selection when HLCLK is “0”000: fL (fLIRC)
001: fL (fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In addition
to the system clock source, which can be the LIRC, a divided version of the high speed systemoscillator can also be chosen as the system clock source.

Rev. 2.30

39

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Bit 4

Unimplemented, read as "0"

Bit 3

LTO: Low speed system oscillator ready flag
0: Not ready
1: ReadyThis is the low speed system oscillator ready flag which indicates when the low speed systemoscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in
the SLEEP0 mode, but after a wake-up has occurred the flag will change to a high level after 1~2
cycles if the LIRC oscillator is used.

Bit 2

HTO: High speed system oscillator ready flag
0: Not ready
1: ReadyThis is the high speed system oscillator ready flag which indicates when the high speed systemoscillator is stable. This flag is cleared to “0” by hardware when the device is powered on andthen changes to a high level after the high speed system oscillator is stable. Therefore this flag
will always be read as “1” by the application program after device power-on.

Bit 1

IDLEN: IDLE Mode Control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT instruction is
executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE
Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep
the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU andthe system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP
Mode when a HALT instruction is executed.

Bit 0

HLCLK: System Clock Selection
0: fH/2 ~ fH/64 or fL
1: fH
This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock.
When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will beselected. When system clock switches from the fH clock to the fL clock and the fH clock will be
automatically switched off to conserve power.

• SMOD1 Register
Bit

7

6

5

4

3

2

1

0

Name

FSYSON

—

—

—

D3

LVRF

—

WRF

R/W

R/W

—

—

—

R/W

R/W

—

R/W

POR

0

—

—

—

0

x

—

0
“x” unknown

Bit 7

Rev. 2.30

FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable

Bit 6~4

Unimplemented, read as 0

Bit 3

D3: Reserved bit

Bit 2

LVRF: LVR function reset flag
0: Not active
1: Active
This bit can be clear to “0”, but can not be set to “1”.

Bit 1

Unimplemented, read as 0

40

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Bit 0

WRF: WDT Control register software reset flag
0: Not occur
1: OccurredThis bit is set to 1 by the WDT Control register software reset and cleared by the application
program. Note that this bit can only be cleared to 0 by the application program.

Operating Mode Switching
The devices can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executedusing the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the
NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the a HALT instruction. Whena HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode isdetermined by the condition of the IDLEN bit in the SMOD register and FSYSON in the SMOD1
register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from thehigh speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the highspeed clock source will stop running to conserve power. When this happens it must be noted that thefH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of otherinternal functions such as the TMs.

                             ­                                                             ­                                                                                             

Rev. 2.30

                 41

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMNORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the
HLCLK bit to “0” and setting the CKS2~CKS0 bits to “000” or “001” in the SMOD register.This
will then use the low speed system oscillator which will consume less power. Users may decide to
do this for certain operations which do not require high performance and can subsequently reduce
power consumption.
The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to bestable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.

         

 




 
                                                                                                 ­                                     ­                             Rev. 2.30

42

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL
Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or
HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As acertain amount of time will be required for the high frequency clock to stabilise, the status of the
HTO bit is checked.

                                                                                                                ­                                      ­                              Entering the SLEEP0 Mode
There is only one way for the devices to enter the SLEEP0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT off. When this instruction is executed under the conditions described above, the following will
occur:• The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.

Rev. 2.30

43

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMEntering the SLEEP1 Mode
There is only one way for the devices to enter the SLEEP1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT on. When this instruction is executed under the conditions described above, the following will
occur:• The system clock and Time Base clock will be stopped and the application program will stop at
the “HALT” instruction, but the WDT will remain with the clock source coming from the fLIRC
clock.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.

Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in SMOD1 register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:• The system clock will be stopped and the application program will stop at the “HALT” instruction, but the Time Base clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.

Entering the IDLE1 Mode
There is only one way for the devices to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in SMOD1 register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:• The system clock and Time Base clock will be on and the application program will stop at the“HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.

Rev. 2.30

44

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of
the devices to as low a value as possible, perhaps only in the order of several micro-amps except
in the IDLE1 Mode, there are other considerations which must also be taken into account by thecircuit designer if the power consumption is to be minimised. Special attention must be made to
the I/O pins on the device. All high-impedance input pins must be connected to either a fixed highor low level as any floating input pins could create internal oscillations and result in increased
current consumption. This also applies to devices which have different package types, as there may
be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-highresistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as
outputs. These should be placed in a condition in which minimum current is drawn or connected
only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode
the system oscillator is on, if the system oscillator is from the high speed system oscillator, theadditional standby current will also be perhaps in the order of several hundred micro-amps.

Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:• An external reset• An external falling edge on Port A• A system interrupt• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, If these devices are woken up by a WDT overflow, a Watchdog Timer reset will be
initiated. Although both of these wake-up methods will initiate a reset operation, the actual sourceof the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared bya system power-up or executing the clear Watchdog Timer instruction and is set when executing the“HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the “HALT” instruction. If the system is woken up by an interrupt, thentwo possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabledor when a stack level becomes free. The other situation is where the related interrupt is enabled andthe stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.

Rev. 2.30

45

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.

Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal fLIRC clock which is supplied by the
LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give
longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The
LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it
should be noted that this specified internal clock period can vary with VDD, temperature and process
variations. The WDT can be enabled/disabled using the WDTC register.

Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. The WRF software reset flag will be indicated in the SMOD1 register. These registers
control the overall operation of the Watchdog Timer.
• WDTC Register
Bit

7

6

5

4

3

2

1

0

Name

WE4

WE3

WE2

WE1

WE0

WS2

WS1

WS0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

1

0

1

0

0

1

1

Bit 7~ 3

WE4 ~ WE0: WDT function software control
10101: WDT disable
01010: WDT enable
Other values: Reset MCU
When these bits are changed to any other values by the environmental noise to reset the
microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles and the WRF
bit will be set to 1 to indicate the reset source.

Bit 2~ 0

WS2 ~ WS0: WDT Time-out period selection
000: 28/ fLIRC
001: 29/fLIRC
010: 210/fLIRC
011: 211/fLIRC
100: 212/fLIRC
101: 213/fLIRC
110: 214/fLIRC
111: 215/fLIRC
These three bits determine the division ratio of the Watchdog Timer sourece clock, which in turn
determines the timeout period.

Rev. 2.30

46

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• SMOD1 Register
Bit

7

6

5

4

3

2

1

0

Name

FSYSON

—

—

—

D3

LVRF

—

WRF

R/W

R/W

—

—

—

R/W

R/W

—

R/W

POR

0

—

—

—

0

x

—

0
“x” unknown

Bit 7

FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable

Bit 6~4

Unimplemented, read as 0

Bit 3

D3: Reserved bit

Bit 2

LVRF: LVR function reset flag
Refer to the Low Voltage Reset section.

Bit 1

Unimplemented, read as 0

Bit 0

WRF: WDT Control register software reset flag
0: Not occur
1: OccurredThis bit is set to 1 by the WDT Control register software reset and cleared by the application program.
Note that this bit can only be cleared to 0 by the application program.

Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This meansthat in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This isdone using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear WDT instruction will not be executed in
the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are
five bits, WE4~WE0, in the WDTC register to offer the Watchdog Timer enable/disable control andthe MCU reset. The WDT function will be disabled when the WE4~WE0 bits are set to a value of10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If theWE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device
after 2~3 LIRC clock cycles . After power on these bits will have a value of 01010B.
WE4 ~ WE0 Bits

WDT Function

10101B

Disable01010B

EnableAny other values

Reset MCU

Watchdog Timer Enable/Disable Control

Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timertime-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Four methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a value other than 01010B and 10101B is written into the
WE4~WE0 bit locations, the second is an external hardware reset, which means a low level on theexternal reset pin, the third is using the Watchdog Timer software clear instruction and the fourthis via a HALT instruction. There is only one method of using software instruction to clear the
Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT.

Rev. 2.30

47

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
The maximum time-out period is when the 215 division ratio is selected. As an example, with a 32
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1
second for the 215 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
WDTC Register

WE4~WE0 bits

Reset MCU
CLR

RES pin reset“CLR WDT”Instruction“HALT”Instruction

LIRC

fLIRC

11-stage Divider

8-to-1 MUX

7-stage Divider

WDT Time-out(28/fLIRC ~ 215/fLIRC)

WS2~WS0(fLIRC/21 ~ fLIRC/211)

Watchdog Timer

Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the devices can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from thelowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply
a reset condition when the microcontroller is running. One example of this is where after powerhas been applied and the microcontroller is already running, the RES line is forcefully pulled low.
In such a case, known as a normal operation reset, some of the microcontroller registers remainunchanged allowing the microcontroller to proceed with normal operation after the reset line isallowed to return high.
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup. Another reset exists in theform of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power
supply voltage falls below a certain threshold.

Rev. 2.30

48

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Reset Functions
There are several ways in which a microcontroller reset can occur, through events occurring bothinternally and externally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied tothe microcontroller. As well as ensuring that the Program Memory begins execution from the firstmemory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring thatall pins will be first set to inputs.
                           

Note: tRSTD is power-on delay, typical time=50ms
Power-On Reset Timing Chart

RES Pin Reset
Although the microcontroller has an internal RC reset function, if the VDD power supply rise time
is not fast enough or does not stabilise quickly at power-on, the internal reset function may beincapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilise. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which themicrocontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Timer.
For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connectedto the RES pin should be kept as short as possible to minimize any stray noise interference. For
applications that operate within an environment where more noise is present the Enhanced Reset
Circuit shown is recommended.
                                     Note: “*” It is recommended that this component is added for added ESD protection“**” It is recommended that this component is added in environments where power line noise
is significant
External RES Circuit

Rev. 2.30

49

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
More information regarding external reset circuits is located in Application Note HA0075E on theHoltek website.
Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the caseof other resets, the Program Counter will reset to zero and program execution initiated from this point.
        

  

 

             

Note: tRSTD is power-on delay, typical time=16.7ms
RES Reset Timing Chart• RSTC External Reset Register – HT66F002/HT66F0025/HT66F003
Bit

7

6

5

4

3

2

1

0

Name

RSTC7

RSTC6

RSTC5

RSTC4

RSTC3

RSTC2

RSTC1

RSTC0

R/W

R/W

R/W

R/W

R/W

R

R

R/W

R/W

POR

0

1

0

1

0

1

0

1

Bit 7 ~ 0

RSTC7 ~ RSTC0: PA7/RES selection
01010101: configured as PA7 pin or other function
10101010: configured as RES pin
Other Values: Inhibit to use
All reset will reset this register as POR value except WDT time out Hardware warm reset.

• RSTC External Reset Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

RSTC7

RSTC6

RSTC5

RSTC4

RSTC3

RSTC2

RSTC1

RSTC0

R/W

R/W

R/W

R/W

R/W

R

R

R/W

R/W

POR

0

1

0

1

0

1

0

1

Bit 7 ~ 0

RSTC7 ~ RSTC0: PC2/RES selection
01010101: Configured as PC2 pin or other function
10101010: Configured as RES pin
Other Values: Inhibit to use
All reset will reset this register as POR value except WDT time out Hardware warm reset.

Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage ofthe device and provide an MCU reset should the value fall below a certain predefined level. The
LVR function is always enabled during the normal and slow modes with a specific LVR voltage
VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur
when changing the battery, the LVR will automatically reset the device internally and the LVRF
bit in the SMOD1 register will also be set to1. For a valid LVR signal, a low voltage, i.e., a voltage
in the range between 0.9V~ VLVR must exist for greater than the value tLVR specified in the A.C.
characteristics. If the low voltage state does not exceed this value, the LVR will ignore the low
supply voltage and will not perform a reset function. The actual VLVR is 2.1V, the LVR will reset thedevice after 2~3 LIRC clock cycles. Note that the LVR function will be automatically disabled when
the device enters the SLEEP/IDLE mode.
                    

Note:tRSTD is power-on delay, typical time=50ms
Low Voltage Reset Timing Chart

Rev. 2.30

50

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• SMOD1 Register
Bit

7

6

5

4

3

2

1

0

Name

FSYSON

—

—

—

D3

LVRF

—

WRF

R/W

R/W

—

—

—

R/W

R/W

—

R/W

POR

0

—

—

—

0

x

—

0
“x” unknown

Bit 7

FSYSON: fSYS Control in IDLE Mode
Describe elsewhereBit 6~4

Unimplemented, read as 0

Bit 3

D3: Reserved bit

Bit 2

LVRF: LVR function reset flag
0: Not active
1: Active
This bit can be clear to “0”, but can not be set to “1”.

Bit 1

Unimplemented, read as 0

Bit 0

WRF: WDT Control register software reset flag
Refer to the Watchdog Timer Control Register section.

Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as an LVR reset except that the
Watchdog time-out flag TO will be set to “1”.
WDT Time-out
tRSTD
Internal Reset

Note: tRSTD is power-on delay, typical time=16.7ms
WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kindsof reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics fortSST details.
WDT Time-out
tSST
Internal Reset

WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart

Rev. 2.30

51

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags areshown in the table:
TO

PDF

0

0

Power-on reset

RESET Conditionsuu

LVR reset during NORMAL or SLOW Mode operation

1u

WDT time-out reset during NORMAL or SLOW Mode operation

1

1

WDT time-out reset during IDLE or SLEEP Mode operation
Note: “u” stands for unchanged

The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item

Condition After RESET

Program Counter

Reset to zeroInterrupts

All interrupts will be disabled

WDT, Time Bases

Cleared after reset, WDT begins counting

Timer Modules

Timer Modules will be turned off

Input/Output Ports

I/O ports will be setup as inputs

Stack PointerStack Pointer will point to the top of the stack

The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important toknow what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that wheremore than one package type exists the table will reflect the situation for the larger package type.
HT66F002

HT66F0025

HT66F003

Program
Counter

●

●

●

MP0

●

●

●

1xxx xxxx

1xxx xxxx

1xxx xxxx

1xxx xxxx

1uuu uuuu

MP1

●

●

●

1xxx xxxx

1xxx xxxx

1xxx xxxx

1xxx xxxx

1uuu uuuu

HT66F004

Register

Reset(Power On)

WDT Time-out(NormalOperation)

RES Reset(NormalOperation)

RES Reset(HALT)WDT Time-out(HALT)*

●

0

0

0

0

0

0

0

H

0

0

H

0

0

H

0

0

H

0

0

H

MP0

●

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

uuuu uuuu

MP1●xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

uuuu uuuu

BP

●

●

●

●

---- ---0---- ---0---- ---0---- ---0---- ---u

ACC

●

●

●

●

xxxx xxxx

uuuu uuuu

uuuu uuuu

uuuu uuuu

uuuu uuuu

PCL

●

●

●

●

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

TBLP

●

●

●

●

xxxx xxxx

uuuu uuuu

uuuu uuuu

uuuu uuuu

uuuu uuuu

TBLH

●

●

●

●

--xx xxxx--uu uuuu--uu uuuu--uu uuuu--uu uuuu

STATUS●●●●--00 xxxx--1u uuuu--uu uuuu--01 uuuu- - 11 u u u u

SMOD

●

●

●

●

0 0 0 - 0 0 11

0 0 0 - 0 0 11

0 0 0 - 0 0 11

0 0 0 - 0 0 11

uuu- uuuu

INTEG

●

●

●

●

---- --00---- --00---- --00---- --00---- --uu

INTC0

●

●

●

●

-000 0000-000 0000-000 0000-000 0000-uuu uuuu●●-000 -000-000 -000-000 -000-000 -000-uuu -uuu

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

INTC1

Rev. 2.30

●

●

52

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

HT66F003●●●

HT66F004

HT66F0025

MFI0

HT66F002

Register

●

MFI1

●

Reset
(Power On)

WDT Time-out(NormalOperation)

RES Reset(NormalOperation)

RES Reset(HALT)WDT Time-out(HALT)*--00 --00--00 --00--00 --00--00 --00--uu --uu0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu--00 --00--00 --00--00 --00--00 --00--uu --uu

PA

●

●

●

●

1111 1111

1111 1111

1111 1111

1111 1111

uuuu uuuu

PAC

●

●

●

●

1111 1111

1111 1111

1111 1111

1111 1111

uuuu uuuu

PAPU

●

●

●

●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PAWU

●

●

●

●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

●

●

IFS0

--00 --00--00 --00--00 --00--00 --00--uu --uu●0000 0-00

0000 0-00

0000 0-00

0000 0-00

uuuu u-uu

0 1 0 1 0 0 11

0 1 0 1 0 0 11

0 1 0 1 0 0 11

0 1 0 1 0 0 11

uuuu uuuu

WDTC

●

●

●

TBC

●

●

●

●

0 0 11 - 111

0 0 11 - 111

0 0 11 - 111

0 0 11 - 111

uuuu –uuu

SMOD1

●

●

●

●

0--- 0x-0

0--- 0x-0

0--- 0x-0

0--- 0x-0

u--- uu-u●-000 0000-000 0000-000 0000-000 0000-uuu uuuu

SCOMC
EEA

●

●

●

●

---0 0000---0 0000---0 0000---0 0000---u uuuu

EED

●

●

●

●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

SADOL(ADRFS=0)

●

●

●

●

xxxx ----

xxxx ----

xxxx ----

xxxx ----

uuuu ----SADOL(ADRFS=1)

●

●

●

●

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

uuuu uuuu

SADOH(ADRFS=0)

●

●

●

●

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

uuuu uuuu

SADOH(ADRFS=1)

●

●

●

●

---- xxxx---- xxxx---- xxxx---- xxxx---- uuuu

●

●

●

SADC0

0000 --00

0000 --00

0000 --00

0000 --00

uuuu --uu●0000 -000

0000 -000

0000 -000

0000 -000

uuuu -uuu

SADC1

●

●

●

●

000- -000

000- -000

000- -000

000- -000

uuu- -uuu

SADC2

●

●

●

●

00-- 0000

00-- 0000

00-- 0000

00-- 0000

uu-- uuuu

RSTC

●

●

●

●

0101 0101

0101 0101

0101 0101

0101 0101

uuuu uuuu

PASR

●

●

●

●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu--00 0000--00 0000--00 0000--00 0000--uu uuuu-000 0000-000 0000-000 0000-000 0000-uuu uuuu

●

PBSR

●

STM0C0●●●0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

STM0C1●●●0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

STM0DL●●●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

STM0DH●●●---- --00---- --00---- --00---- --00---- --uu

STM0AL●●●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

STM0AH●●●---- --00---- --00---- --00---- --00---- --uu

PTM0C0●0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM0C1●0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM0DL●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM0DH●---- --00---- --00---- --00---- --00---- --uu

PTM0AL●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM0AH●---- --00---- --00---- --00---- --00---- --uu

PTM0RPL●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu●---- --00---- --00---- --00---- --00---- --uu●0000 0---0000 0---0000 0---0000 0---uuuu u---PTM0RPH
PTM1C0Rev. 2.30●

53

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

HT66F003

HT66F004

HT66F0025

HT66F002

Reset(Power On)

PTM1C1●●0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM1DL●●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM1DH●●---- --00---- --00---- --00---- --00---- --uu

PTM1AL●●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM1AH●●---- --00---- --00---- --00---- --00---- --uu

PTM1RPL●●

0000 0000

0000 0000

0000 0000

0000 0000

uuuu uuuu

PTM1RPH●●---- --00---- --00---- --00---- --00---- --uu- - 11 1111

- - 11 1111

- - 11 1111

- - 11 1111--uu uuuu- 111 1111

- 111 1111

- 111 1111

- 111 1111

-uuu uuuu- - 11 1111

- - 11 1111

- - 11 1111

- - 11 1111--uu uuuu- 111 1111

- 111 1111

- 111 1111

- 111 1111

-uuu uuuu--00 0000--00 0000--00 0000--00 0000--uu uuuu●-000 0000-000 0000-000 0000-000 0000-uuu uuuuPC●- - - - - 111- - - - - 111- - - - - 111- - - - - 111---- -uuu

PCC●- - - - - 111- - - - - 111- - - - - 111- - - - - 111---- -uuu

PCPU●---- -000---- -000---- -000---- -000---- -uuu●---- 0000---- 0000---- 0000---- 0000---- uuuu

Register

●

PB

●
●

PBC

●
●

PBPU

EEC

●

●

●

WDT Time-out(NormalOperation)

RES Reset(NormalOperation)

RES Reset(HALT)WDT Time-out(HALT)*

Note: "*" stands for warm reset"-" not implement"u" stands for "unchanged""x" stands for "unknown"

Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports andwake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of awide range of application possibilities.
The devices provide bidirectional input/output lines labeled with port names PA~PC. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edgeof instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data islatched and remains unchanged until the output latch is rewritten.
Bit

Register
Name

7

6

5

4

3

2

1

0

PA

D7

D6

D5

D4

D3

D2

D1

D0

PAC

D7

D6

D5

D4

D3

D2

D1

D0

PAPU

D7

D6

D5

D4

D3

D2

D1

D0

PAWU

D7

D6

D5

D4

D3

D2

D1

D0

PASR

PAS7

PAS6

PAS5

PAS4

PAS3

PAS2

PAS1

PAS0

IFS0

—

—

—

INTPS1INTPS0—

STCK0PS STP0IPS

I/O Logic Function Register List – HT66F002/HT66F0025

Rev. 2.30

54

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Bit

Register
Name

7

6

5

4

3

2

1

0

PA

D7

D6

D5

D4

D3

D2

D1

D0

PAC

D7

D6

D5

D4

D3

D2

D1

D0

PAPU

D7

D6

D5

D4

D3

D2

D1

D0

PAWU

D7

D6

D5

D4

D3

D2

D1

D0

PB

—

—

D5

D4

D3

D2

D1

D0
D0

PBC

—

—

D5

D4

D3

D2

D1

PBPU

—

—

D5

D4

D3

D2

D1

D0

PASR

PAS7

PAS6

PAS5

PAS4

PAS3

PAS2

PAS1

PAS0

—

—

PBS5

PBS4

PBS3

PBS2

PBS1

PBS0

PBSR
IFS0

PTCK1PS1 PTCK1PS0 STCK0PS

STP0IPS PTP1IPS—

INTPS1 INTPS0

I/O Logic Function Register List – HT66F003
Bit

Register
Name

7

6

5

4

3

2

1

0

PA

D7

D6

D5

D4

D3

D2

D1

D0

PAC

D7

D6

D5

D4

D3

D2

D1

D0

PAPU

D7

D6

D5

D4

D3

D2

D1

D0

PAWU

D7

D6

D5

D4

D3

D2

D1

D0

PB

—

D6

D5

D4

D3

D2

D1

D0

PBC

—

D6

D5

D4

D3

D2

D1

D0

PBPU

—

D6

D5

D4

D3

D2

D1

D0

PC

—

—

—

—

—

D2

D1

D0

PCC

—

—

—

—

—

D2

D1

D0

PCPU

—

—

—

—

—

D2

D1

D0

PASR

PAS7

PAS6

PAS5

PAS4

PAS3

PAS2

PAS1

PAS0

PBSR

—

PBS6

PBS5

PBS4

PBS3

PBS2

PBS1

PBS0

I/O Logic Function Register List – HT66F004

Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the useof an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured
as an input have the capability of being connected to an internal pull-high resistor. These pull-highresistors are selected using register PAPU~PCPU, and are implemented using weak PMOS transistors.
• PAPU Register
Bit

7

6

5

4

3

2

1

0

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7 ~ 0Rev. 2.30

I/O Port A bit7~ bit 0 Pull-High Control
0: Disable
1: Enable

55

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• PBPU Register – HT66F003
Bit

7

6

5

4

3

2

1

0

Name

—

—

D5

D4

D3

D2

D1

D0

R/W

—

—

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

—

0

0

0

0

0

0

Bit 7~6
Bit 5~0

Unimplemented, read as 0
I/O Port B bit5~ bit 0 Pull-High Control
0: Disable
1: Enable• PBPU Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

—

D6

D5

D4

D3

D2

D1

D0

R/W

—

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

0

0

0

0

0

0

0

Bit 7
Bit 6~0

Unimplemented, read as 0
I/O Port B bit 6~ bit 0 Pull-High Control
0: Disable
1: Enable• PCPU Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

D2

D1

D0

R/W

—

—

—

—

—

R/W

R/W

R/W

POR

—

—

—

—

—

0

0

0

Bit 7~3

Unimplemented, read as 0

Bit 2~0

I/O Port C bit 2~ bit 0 Pull-High Control
0: Disable
1: Enable

Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up featureusing the PAWU register.
• PAWU Register
Bit

7

6

5

4

3

2

1

0

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7 ~ 0Rev. 2.30

I/O Port A bit 7 ~ bit 0 Wake Up Control
0: Disable
1: Enable

56

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PCC, to control the input/output
configuration. With these control registers, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of thecontrol register must be written as a “1”. This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a “0”,the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
• PAC Register
Bit

7

6

5

4

3

2

1

0

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

1

1

1

1

1

1

1

1

Bit 7 ~ 0

I/O Port A bit 7 ~ bit 0 Input/Output Control
0: Output
1: Input• PBC Register – HT66F003
Bit

7

6

5

4

3

2

1

0

Name

—

—

D5

D4

D3

D2

D1

D0

R/W

—

—

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

—

1

1

1

1

1

1

Bit 7 ~ 6

Unimplemented, read as 0

Bit 5 ~ 0

I/O Port B bit 5 ~ bit 0 Input/Output Control
0: Output
1: Input• PBC Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

—

D6

D5

D4

D3

D2

D1

D0

R/W

—

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

1

1

1

1

1

1

1

2

1

0

Bit 7

Unimplemented, read as 0

Bit 6~0

I/O Port B bit 6 ~ bit 0 Input/Output Control
0: Output
1: Input• PCC Register – HT66F004

Rev. 2.30

Bit

7

6

5

4

3

Name

—

—

—

—

—

D2

D1

D0

R/W

—

—

—

—

—

R/W

R/W

R/W

POR

—

—

—

—

—

1

1

1

Bit 7~3

Unimplemented, read as 0

Bit 2~0

I/O Port C bit 2 ~ bit 0 Input/Output Control
0: Output
1: Input

57

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have morethan one function. Limited numbers of pins can force serious design constraints on designers but
by supplying pins with multi-functions, many of these difficulties can be overcome. The way inwhich the pin function of each pin is selected is different for each function and a priority order isestablished where more than one pin function is selected simultaneously. Additionally there area PASR and a PBSR register to establish certain pin functions. Generally speaking, the analog
function has higher priority than the digital function. However, if more than two analog functions
are enabled and the analog signal input comes from the same external pin, the analog input will beinternally connected to all of these active analog functional modules.
Pin-shared Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes.
• PASR Register – HT66F002/HT66F0025

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

PAS7

PAS6

PAS5

PAS4

PAS3

PAS2

PAS1

PAS0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7~6

PAS7~PAS6: Pin-Shared Control Bits
00: PA5/INT
01: STP0B
10: PA5/INT
11: AN3

Bit 5~4

PAS5~PAS4: Pin-Shared Control Bits
00: PA2/INT
01: STP0
10: VREFO
11: AN2

Bit 3~2

PAS3~PAS2: Pin-Shared Control Bits
00: PA1
01: STP0B
10: VREF
11: AN1

Bit 1~0

PAS1~PAS0: Pin-Shared Control Bits
00: PA0/STP0I
01: STP0
10: PA0/STP0I
11: AN058

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• PASR Register – HT66F003
Bit

7

6

5

4

3

2

1

0

Name

PAS7

PAS6

PAS5

PAS4

PAS3

PAS2

PAS1

PAS0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7

PAS7: Pin-Shared Control Bit
0: PA7/PTCK1
1: STP0B
Note: PAS7 is valid when RSTC=55H

Bit 6

PAS6: Pin-Shared Control Bit
0: PA6/PTCK1/STP0I
1: STP0

Bit 5

PAS5: Pin-Shared Control Bit
0: PA4/INT/PTCK1
1: STP0

Bit 4

PAS4: Pin-Shared Control Bit
0: PA3/INT/STCK0
1: AN3PAS3: Pin-Shared Control Bit
0: PA2/INT/STCK0
1: AN2PAS2~PAS1: Pin-Shared Control Bits
0X: PA1
10: VREF
11: AN1
PAS0: Pin-Shared Control Bit
0: PA0/STP0I
1: AN0

Bit 3

Bit 2~1

Bit 0• PASR Register – HT66F004

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

PAS7

PAS6

PAS5

PAS4

PAS3

PAS2

PAS1

PAS0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7~6

PAS7~PAS6: Pin-Shared Control Bits
00: PA7
01: PTP1
10: PA7
11: AN6

Bit 5~4

PAS5~PAS4: Pin-Shared Control Bits
0X: PA6
10: VREFO
11: AN5

Bit 3~2

PAS3~ PAS2: Pin-Shared Control Bits
0X: PA5
10: VREF
11: AN4

Bit 1

PAS1: Pin-Shared Control Bit
0: PA4/PTCK1
1: AN3

Bit 0

PAS0: Pin-Shared Control Bit
0: PA0
1: PTP0

59

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• PBSR Register – HT66F003
Bit

7

6

5

4

3

2

1

0

Name

—

—

PBS5

PBS4

PBS3

PBS2

PBS1

PBS0

R/W

—

—

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

—

0

0

0

0

0

0

Bit 7~6
Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unimplemented, read as “0”PBS5: Pin-Shared Control Bit
0: PB5
1: PTP1
PBS4: Pin-Shared Control Bit
0: PB4
1: PTP1B
PBS3: Pin-Shared Control Bit
0: PB3
1: PTP1
PBS2: Pin-Shared Control Bit
0: PB2
1: PTP1B
PBS1: Pin-Shared Control Bit
0: PB1/PTCK1
1: STP0B
PBS0: Pin-Shared Control Bit
0: PB0/PTP1I
1: VREFO• PBSR Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

—

PBS6

PBS5

PBS4

PBS3

PBS2

PBS1

PBS0

R/W

—

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

0

0

0

0

0

0

0

Bit 7
Bit 6
Bit 5
Bit 4

Bit 3

Bit 2
Bit 1
Bit 0

Rev. 2.30

Unimplemented, read as “0”PBS6: Pin-Shared Control Bit
0: PB6
1: PTP1B
PBS5: Pin-Shared Control Bit
0: PB5
1: PTP0B
PBS4: Pin-Shared Control Bit
0: PB4
1: CLO
Note: PBS4 is valid when COM2EN=0
PBS3: Pin-Shared Control Bit
0: PB3
1: AN7
Note: PBS3 is valid when COM3EN=0
PBS2: Pin-Shared Control Bit
0: PB2/PTCK0
1: AN2
PBS1: Pin-Shared Control Bit
0: PB1/INT1
1: AN1
PBS0: Pin-Shared Control Bit
0: PB0/INT0
1: AN060

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• IFS0 Register – HT66F002/HT66F0025
Bit

7

6

Name

—

—

5

4

R/W

—

—

R/W

POR

—

—

0

3

2

1

0

—

—

INTPS1INTPS0

R/W

—

—

R/W

R/W

0

—

—

0

0

STCK0PS STP0IPS

Bit 7~6

Unimplemented, read as "0"

Bit 5

STCK0PS: STCK0 Pin Remapping Control
0: STCK0 on PA7
1: STCK0 on PA6

Bit 4

STP0IPS: STP0I Pin Remapping Control
0: STP0I on PA6
1: STP0I on PA0

Bit 3~2

Unimplemented, read as "0"

Bit 1~0

INTPS1, INTPS0: INT Pin Remapping Control
00: INT on PA5
01: INT on PA2
10: INT on PA3
11: INT on PA7• IFS0 Register – HT66F003
Bit
Name

Rev. 2.30

7

6

PTCK1PS1 PTCK1PS0

5
STCK0PS

4

3

STP0IPS PTP1IPS

2
—

1

0

INTPS1 INTPS0

R/W

R/W

R/W

R/W

R/W

R/W

—

R/W

R/W

POR

0

0

0

0

0

—

0

0

Bit 7~6

PTCK1PS1, PTCK1PS0: PTCK1 Pin Remapping Control
00: PTCK1 on PA4
01: PTCK1 on PA6
10: PTCK1 on PA7
11: PTCK1 on PB1

Bit 5

STCK0PS: STCK0 Pin Remapping Control
0: STCK0 on PA3
1: STCK0 on PA2

Bit 4

STP0IPS: STP0I Pin Remapping Control
0: STP0I on PA6
1: STP0I on PA0

Bit 3

PTP1IPS: PTP1I Pin Remapping Control
0: PTP1I on PA5
1: PTP1I on PB0

Bit 2

Unimplemented, read as "0"

Bit 1~0

INTPS1, INTPS0: INT Pin Remapping Control
00: INT on PA3
01: INT on PA2
10: INT on PA4
11: INT on PA5

61

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.

                         
 




           

      


 



 

            



 

 

                                         

Generic Input/Output Structure                                

 ­

  



  
 



                                    

 ­



                                             

A/D Input/Output Structure

Rev. 2.30

62

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
System Clock output pin CLO
The device HT66F004 provides a system clock output pin CLO. MCU system clock can output tothe CLO pin by setting pin-shared control register bit PBS4 to 1. The highest output frequency is
8MHz in this device. Please note that when the noise problem is an important issue, it is better not to
use CLO output function.

Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, allof the I/O data and port control registers will be set high. This means that all I/O pins will default
to an input state, the level of which depends on the other connected circuitry and whether pullhigh selections have been chosen. If the port control registers are then programmed to setup somepins as outputs, these output pins will have an initial high output value unless the associated port
data registers are first programmed. Selecting which pins are inputs and which are outputs can beachieved byte-wide by loading the correct values into the appropriate port control register or byprogramming individual bits in the port control register using the “SET [m].i” and “CLR [m].i”
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up functions. When the device is in the SLEEPor IDLE Mode, various methods are available to wake the device up. One of these is a high to lowtransition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control andmeasure time. To implement time related functions the devices include several Timer Modules,
abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
individual interrupts. The addition of input and output pins for each TM ensures that users areprovided with timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Standard and Periodic TM sections.

Introduction
The devices contain one or two TMs depending upon which device is selected with each TM having
a reference name of TM0~TM1. Each individual TM can be categorised as a certain type, namely
Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary intheir feature complexity. The common features to the Standard and Periodic TMs will be describedin this section and the detailed operation will be described in corresponding sections. The mainfeatures and differences between the two types of TMs are summarised in the accompanying table.
STM

PTM

Timer/Counter

Function√√

Input Capture√√

Compare Match Output√√

PWM Output

1

1

Single Pulse Output

1

1

PWM Alignment
PWM Adjustment Period & Duty

Edge

Edge

Duty or Period

Duty or Period

TM Function Summary
Rev. 2.30

63

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
DeviceTM0HT66F002/HT66F0025

10-bit STM

TM1—

HT66F003

10-bit STM

10-bit PTM

HT66F004

10-bit PTM

10-bit PTM

TM Name/Type Reference

TM Operation
The two different types of TMs offer a diverse range of functions, from simple timing operations
to PWM signal generation. The key to understanding how the TM operates is to see it in terms ofa free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a TM interrupt signal will be generated which can clear thecounter and perhaps also change the condition of the TM output pin. The internal TM counter isdriven by a user selectable clock source, which can be an internal clock or an external pin.

TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources. The
selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTM
control registers. The clock source can be a ratio of either the system clock fSYS or the internal highclock fH, the fTBC clock source or the external xTCKn pin. The xTCKn pin clock source is used toallow an external signal to drive the TM as an external clock source or for event counting.

TM Interrupts
The Standard and Periodic type TMs each has two internal interrupts, the internal comparator A orcomparator P, which generate a TM interrupt when a compare match condition occurs. When a TM
interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin.

TM External Pins
Each of the TMs, irrespective of what type, has two TM input pins, with the label xTCKn andxTPnI. The TM input pin xTCKn, is essentially a clock source for the TM and is selected using thexTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock
source to drive the internal TM. This external TM input pin is shared with other functions but will
be connected to the internal TM if selected using the xTnCK2~xTnCK0 bits. The TM input pin can
be chosen to have either a rising or falling active edge.
The other TM input pin, xTPnI, is the capture input whose active edge can be a rising edge, a fallingedge or both rising and falling edges and the active edge transition type is selected using the xTnIO1
and xTnIO0 bits in the xTMnC1 register.
The TMs each have two output pins with the label xTPn and xTPnB. When the TM is in the
Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low
level or to toggle when a compare match situation occurs. The external xTPn output pin is also thepin where the TM generates the PWM output waveform. As the TM output pins are pin-shared withother function, the TM output function must first be setup using registers. A single bit in one of theregisters determines if its associated pin is to be used as an external TM output pin or if it is to haveanother function. The number of output pins for each TM type is different, the details are provided
in the accompanying table.

Rev. 2.30

64

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
DeviceTM0TM1HT66F002/HT66F0025

STCK0, STP0I
STP0, STP0B—

HT66F003

STCK0, STP0I
STP0, STP0B

PTCK1, PTP1I
PTP1, PTP1B

HT66F004

PTCK0, PTP0I
PTP0, PTP0B

PTCK1, PTP1I
PTP1, PTP1B

TM Input/Output Pins

TM Input/Output Pin Control Register
Selecting to have a TM input/output or whether to retain its other shared function is implemented
using one register, with a single bit in each register corresponding to a TM input/output pin.
Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The
details of the pin-shared function selection are described in the pin-shared function section.

STM

Inverting Output

STP0B

Output

STP0

Capture Input

STP0I

TCK Input

STCK0

STM Function Pin Control Block Diagram

Inverting Output PTPnB

PTM

OutputPTPn

Capture Input

PTPnI

TCK Input

PTCKn

PTM Function Pin Control Block Diagram

Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA register, and CCRP register pair for
Periodic Timer Module, all have a low and high byte structure. The high bytes can be directly
accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing
to these register pairs must be carried out in a specific way. The important point to note is that datatransfer to and from the 8-bit buffer and its related low byte only takes place when a write or read
operation to its corresponding high byte is executed.
As the CCRA register and CCRP registers are implemented in the way shown in the following
diagram and accessing the register is carried out CCRP low byte register using the following
access procedures. Accessing the CCRA or CCRP low byte register without following these accessprocedures will result in unpredictable values.

Rev. 2.30

65

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
PTM Counter Register (Read only)
PTMnDL

PTMnDH

STM Counter Register (Read only)
STMDL

8-bit Buffer

STMDH

8-bit Buffer

PTMnAL

PTMnAHPTM CCRA Register (Read/Write)
STM0ALSTM0AH

STM CCRA Register (Read/Write)
Data Bus

PTMnRPL

PTMnRPH

PTM CCRP Register (Read/Write)
Data Bus

The following steps show the read and write procedures:• Writing Data to CCRA or PTM CCRP♦

Step 1. Write data to Low Byte STM0AL, PTMnAL or PTMnRPL– note that here data is only written to the 8-bit buffer.

♦

Step 2. Write data to High Byte STM0AH, PTMnAH or PTMnRPH– here data is written directly to the high byte registers and simultaneously data is latchedfrom the 8-bit buffer to the Low Byte registers.

• Reading Data from the Counter Registers and CCRA or PTM CCRP

Rev. 2.30♦

Step 1. Read data from the High Byte STM0DH, STM0AH, PTMnDH, PTMnAH or PTMnRPH– here data is read directly from the High Byte registers and simultaneously data is latchedfrom the Low Byte register into the 8-bit buffer.

♦

Step 2. Read data from the Low Byte STM0DL, STM0AL, PTMnDL, PTMnAL or PTMnRPL– this step reads data from the 8-bit buffer.

66

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Standard Type TM – STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM canbe controlled with two external input pins and can drive two external output pins.
DeviceTM Type

TM NameTM Input Pin

TM Output Pin

HT66F002
HT66F0025
HT66F003

10-bit STM

STM

STCK0, STP0I

STP0, STP0B

CCRP

3-bit Comparator P
fSYS/4
fSYS
fH/16
fH/64
fTBC
fTBC
STCK0

000
001
b7~b9
010
011
10-bit Count-up Counter
100
101
ST0ON
110 ST0PAU
b0~b9
111

ST0CK2~ST0CK0

10-bit Comparator A

Comparator P Match

STMP0F Interrupt
ST0OC
OutputControl

Polarity
Control

ST0M1, ST0M0
ST0IO1, ST0IO0

ST0POLCounter Clear 0
1
ST0CCLR
Comparator A Match
ST0IO1, ST0IO0
Edge
Detector

CCRA

ST0P
ST0PB

STMA0F Interrupt

STP0I

Standard Type TM Block Diagram

Standard TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal clock source.
There are also two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 3-bit
wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits
and therefore compares with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is toclear the counter by changing the ST0ON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources and can also control an output pin. All operating setup conditions are selected using relevantinternal registers.

Standard Type TM Register Description
Overall operation of the Standard TM is controlled using series of registers. A read only registerpair exists to store the internal counter 10-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes as well as three CCRP bits.

Rev. 2.30

67

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

STM0C0

ST0PAUST0CK2

ST0CK1ST0CK0

ST0ON

ST0RP2

ST0RP1

ST0RP0

STM0C1

ST0M1

ST0M0

ST0IO1

ST0IO0

ST0OC

ST0POLST0DPX

ST0CCLR

STM0DL

D7

D6

D5

D4

D3

D2

D1

D0

STM0DH

—

—

—

—

—

—

D9

D8

STM0AL

D7

D6

D5

D4

D3

D2

D1

D0

STM0AH

—

—

—

—

—

—

D9

D8

10-bit Standard TM Register List
• STM0C0 Register

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

ST0PAUST0CK2

ST0CK1ST0CK0

ST0ON

ST0RP2

ST0RP1

ST0RP0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

bit 7

ST0PAU: STM Counter Pause Control
0: Run1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the STM will remain powered up and continue toconsume power. The counter will retain its residual value when this bit changes from low to highand resume counting from this value when the bit changes to a low value again.

bit 6~4

ST0CK2~ST0CK0: Select STM Counter clock
000: fSYS/4001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fTBC
110: STCK0 rising edge clock
111: STCK0 falling edge clock
These three bits are used to select the clock source for the STM. The external pin clock source
can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock,while fH and fTBC are other internal clocks, the details of which can be found in the oscillator
section.

bit 3

ST0ON: STM Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the STM. Setting the bit high enables the counterto run, clearing the bit disables the STM. Clearing this bit to zero will stop the counter fromcounting and turn off the STM which will reduce its power consumption. When the bit changes
state from low to high the internal counter value will be reset to zero, however when the bitchanges from high to low, the internal counter will retain its residual value until the bit returns
high again. If the STM is in the Compare Match Output Mode or the PWM output Mode orSingle Pulse Output Mode then the STM output pin will be reset to its initial condition, as
specified by the ST0OC bit, when the ST0ON bit changes from low to high.

bit 2~0

ST0RP2~ ST0RP0: STM CCRP 3-bit register, compared with the STM Counter bit 9~bit 7
Comparator P Match Period
000: 1024 STM0 clocks
001: 128 STM0 clocks
010: 256 STM0 clocks
011: 384 STM0 clocks
100: 512 STM0 clocks
101: 640 STM0 clocks
110: 768 STM0 clocks
111: 896 STM0 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are thencompared with the internal counter’s highest three bits. The result of this comparison can beselected to clear the internal counter if the ST0CCLR bit is set to zero. Setting the ST0CCLR bit
68

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
to zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest three counter bits, the compare values exist in 128
clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow
at its maximum value.
• STM0C1 Register

Rev. 2.30

Bit

7

6

5

4

3

Name

ST0M1

ST0M0

ST0IO1

ST0IO0

ST0OC

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

ST0POL ST0DPX ST0CCLR

bit 7~6

ST0M1~ ST0M0: Select STM0 Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM output Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the STM. To ensure reliable operation the STM
should be switched off before any changes are made to the ST0M1 and ST0M0 bits. In the Timer/
Counter Mode, the STM output pin state is undefined.

bit 5~4

ST0IO1~ ST0IO0: Select STM0 function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM output Mode/ Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of STP0I
01: Input capture at falling edge of STP0I
10: Input capture at falling/rising edge of STP0I
11: Input capture disabled
Timer/counter Mode:
UnusedThese two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
In the Compare Match Output Mode, the ST0IO1~ST0IO0 bits determine how the TM output pinchanges state when a compare match occurs from the Comparator A. The TM output pin can be
setup to switch high, switch low or to toggle its present state when a compare match occurs fromthe Comparator A. When the ST0IO1~ST0IO0 bits are both zero, then no change will take placeon the output. The initial value of the TM output pin should be setup using the ST0OC bit. Notethat the output level requested by the ST0IO1~ST0IO0 bits must be different from the initialvalue setup using the ST0OC bit otherwise no change will occur on the TM output pin when acompare match occurs. After the TM output pin changes state it can be reset to its initial level bychanging the level of the ST0ON bit from low to high.
In the PWM Mode, the ST0IO1 and ST0IO0 bits determine how the TM output pin changes
state when a certain compare match condition occurs. The PWM output function is modified bychanging these two bits. It is necessary to change the values of the ST0IO1 and ST0IO0 bits only
after the TM has been switched off. Unpredictable PWM outputs will occur if the ST0IO1 and
ST0IO0 bits are changed when the TM is running.

bit 3

ST0OC: STM0 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial highPWM output Mode/ Single Pulse Output Mode
0: Active low
1: Active high69

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
This is the output control bit for the STM output pin. Its operation depends upon whether STM
is being used in the Compare Match Output Mode or in the PWM output Mode/ Single Pulse
Output Mode. It has no effect if the STM is in the Timer/Counter Mode. In the Compare Match
Output Mode it determines the logic level of the STM output pin before a compare match occurs.
In the PWM output Mode it determines if the PWM signal is active high or active low. In theSingle Pulse Output Mode it determines the logic level of the STM output pin when the ST0ON
bit changes from low to high.
bit 2

ST0POL: STM0 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the STM0 output pin. When the bit is set high the STM output pin
will be inverted and not inverted when the bit is zero. It has no effect if the STM is in the Timer/
Counter Mode.

bit 1

ST0DPX: STM0 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and duty controlof the PWM waveform.

bit 0

ST0CCLR: Select STM0 Counter clear condition
0: STM0 Comparator P match
1: STM0 Comparator A match
This bit is used to select the method which clears the counter. Remember that the Standard STM
contains two comparators, Comparator A and Comparator P, either of which can be selected toclear the internal counter. With the ST0CCLR bit set high, the counter will be cleared when acompare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The
ST0CCLR bit is not used in the PWM output mode, Single Pulse or Input Capture Mode.

• STM0DL Register
Bit

7

6

5

4

3

2

1

0

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R

R

R

R

R

R

R

R

POR

0

0

0

0

0

0

0

0

Bit 7 ~ 0

STM0 Counter Low Byte Register bit 7 ~ bit 0
STM0 10-bit Counter bit 7 ~ bit 0• STM0DH Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

—

D9

D8

R/W

—

—

—

—

—

—

R

R

POR

—

—

—

—

—

—

0

0

3

2

1

0

bit 7~2

Unimplemented, read as "0"

bit 1~0

STM0 Counter High Byte Register bit 1 ~ bit 0
STM0 10-bit Counter bit 9 ~ bit 8• STM0AL Register
Bit

6

5

4

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

bit 7~0Rev. 2.30

7

STM0 CCRA Low Byte Register bit 7 ~ bit 0
STM0 10-bit Counter bit 7 ~ bit 070

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• STM0AH Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

—

D9

D8

R/W

—

—

—

—

—

—

R

R

POR

—

—

—

—

—

—

0

0

bit 7~2

Unimplemented, read as "0"

bit 1~0

STM0 CCRA High Byte Register bit 1 ~ bit 0
STM0 10-bit Counter bit 9 ~ bit 8

Standard Type TM Operating Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the ST0M1 and ST0M0 bits in the STM0C1 register.
Compare Output Mode
To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by threemethods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the ST0CCLR bit is low, there are two ways in which the counter can becleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both STMA0F and STMP0F interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the ST0CCLR bit in the STM0C1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMA0F interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when ST0CCLR is high no STMP0F interrupt request flag will be generated. In the Compare
Match Output Mode, the CCRA can not be set to "0". If the CCRA bits are all zero, the counter will
overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the STMA0F interrupt
request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the STM output pin, will change
state. The STM output pin condition however only changes state when an STMA0F interrupt request
flag is generated after a compare match occurs from Comparator A. The STMP0F interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STM
output pin. The way in which the STM output pin changes state are determined by the condition of
the ST0IO1 and ST0IO0 bits in the STM0C1 register. The STM output pin can be selected using
the ST0IO1 and ST0IO0 bits to go high, to go low or to toggle from its present condition when acompare match occurs from Comparator A. The initial condition of the STM output pin, which is
setup after the ST0ON bit changes from low to high, is setup using the ST0OC bit. Note that if the
ST0IO1 and ST0IO0 bits are zero then no pin change will take place.

Rev. 2.30

71

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter Value

0x3FF

ST0CCLR = 0; ST0M[1:0] = 00

Counter
overflow

CCRP > 0Counter cleared by CCRP value

CCRP = 0Counter
Reset

ResumeCCRP > 0

CCRP

Pause

CCRA

Stop

Time

ST0ON
ST0PAU
ST0POLCCRP Int.
Flag STMP0F
CCRA Int.
Flag STMA0F
STM O/P Pin
Output Pin set
to Initial Level
Low if ST0OC= 0

Output Toggle
with STMA0F flag

Now ST0IO[1:0] = 10
Active High Output SelectOutput not affected by
STMA0F flag. Remains High
until reset by ST0ON bit

Output inverts
when ST0POL is highOutput Pin
Reset to initial value
Output controlled
by other pin - shared function

Here ST0IO[1:0] = 11
Toggle Output SelectCompare Match Output Mode – ST0CCLR = 0

Note: 1. With ST0CCLR = 0 a Comparator P match will clear the counter
2. The TM output pin controlled only by the STMA0F flag
3. The output pin reset to initial state by a ST0ON bit rising edge

Rev. 2.30

72

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

ST0CCLR = 1; ST0M[1:0] = 00

Counter Value
CCRA > 0Counter cleared by CCRA value

0x3FF

Resume

CCRA
Pause

CCRP

CCRA = 0Counter overflow
CCRA = 0
Stop

Counter Reset

Time

ST0ON
ST0PAU
ST0POLNo STMA0F flag
generated on
CCRA overflow

CCRP Int.
Flag STMA0F
CCRA Int.
Flag STMP0F
STM O/P Pin

Output does
not change
STMP0F notgenerated
Output not affected by
Output Pin set
to Initial Level
Low if ST0OC= 0

Output Toggle
with STMA0F flag

STMA0F flag. Remains HighNow ST0IO[1:0] = 10
Active High Output Selectuntil reset by ST0ON bit

Here ST0IO[1:0] = 11
Toggle Output SelectOutput inverts
when ST0POL is highOutput Pin
Reset to initial value
Output controlled
by other pin- shared function

Compare Match Output Mode – ST0CCLR = 1

Note: 1. With ST0CCLR = 1 a Comparator A match will clear the counter
2. The TM output pin controlled only by the STMA0F flag
3. The output pin reset to initial state by a ST0ON rising edge
4. The STMP0F flag is not generated when ST0CCLR = 1

Rev. 2.30

73

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Timer/Counter Mode
To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode theSTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STM output pin is not used inthis mode, the pin can be used as a normal I/O pin or other pin-shared function by setting pin-sharefunction register.
PWM Output Mode
To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10 respectively
and also the ST0IO1 and ST0IO0 bits should be set to 10 respectively. The PWM function within
the STM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM output mode, the ST0CCLR bit has no effect as thePWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the ST0DPX bit in the STM0C1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare matchoccurs from either Comparator A or Comparator P. The ST0OC bit in the STM0C1 register is used
to select the required polarity of the PWM waveform while the two ST0IO1 and ST0IO0 bits areused to enable the PWM output or to force the STM output pin to a fixed high or low level. The
ST0POL bit is used to reverse the polarity of the PWM output waveform.
• 10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=0
CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

128

256

384

512

640

768

896

1024

Duty

CCRA

If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128,
The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=1
CCRP

001b

010b

011b

100b

Period
Duty

101b

110b

111b

000b

768

896

1024

CCRA
128

256

384

512

640

The PWM output period is determined by the CCRA register value together with the STM clock
while the PWM duty cycle is defined by the CCRP register value.

Rev. 2.30

74

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter
Value

ST0DPX=0;ST0M[1:0]=10

Counter Clearedby CCRP

Counter reset when
ST0ON returns high

CCRP

Pause Resume

CCRA

Counter Stop If
ST0ON bit low

Time

ST0ON
ST0PAU

ST0POLCCRA Int.
Flag STMA0F
CCRP Int.
Flag STMP0F

STM O/P Pin(ST0OC=1)
STM O/P Pin(ST0OC=0)
PWM Duty Cycle
set by CCRA

Output controlled by
Other pin-shared function

PWM resumes
operation

Output Inverts
When ST0POL = 1

PWM Period
set by CCRPPWM Output Mode – ST0DPX = 0

Note: 1. Here ST0DPX = 0 - Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues running even when ST0IO[1:0] = 00 or 01
4. The ST0CCLR bit has no influence on PWM operationRev. 2.30

75

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter
Value

ST0DPX=1;ST0M[1:0]=10

Counter Cleared by CCRACounter reset when
ST0ON returns high

CCRA

Pause Resume

CCRP

Counter Stop If
ST0ON bit low

Time

ST0ON
ST0PAU

ST0POLCCRP Int.
Flag STMP0F
CCRA Int.
Flag STMA0F

STM O/P Pin(ST0OC=1)
STM O/P Pin(ST0OC=0)
PWM Duty Cycle
set by CCRP

Output controlled by
Other pin-shared function

PWM resumes
operation

Output Inverts
When ST0POL = 1

PWM Period
set by CCRAPWM Output Mode – ST0DPX = 1

Note: 1. Here ST0DPX = 1 - Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when ST0IO[1:0] = 00 or 01
4. The ST0CCLR bit has no influence on PWM operationRev. 2.30

76

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Single Pulse Mode
To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10
respectively and also the ST0IO1 and ST0IO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin.
The trigger for the pulse output leading edge is a low to high transition of the ST0ON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the ST0ON
bit can also be made to automatically change from low to high using the external STCK0 pin,which will in turn initiate the Single Pulse output. When the ST0ON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The ST0ON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the ST0ON bit is cleared to zero, which can be implemented using the application program orwhen a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the ST0ON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control thepulse width. A compare match from Comparator A will also generate a STM interrupt. The countercan only be reset back to zero when the ST0ON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The ST0CCLR and ST0DPX bits are not usedin this mode.
Leading Edge

Trailing Edge

ST0ON bit
0→1

ST0ON bit
1→0

S/W Command
SET“ST0ON”
or
STCK0 Pin
Transition

S/W Command
CLR“ST0ON”
orCCRA Compare
Match

STP0/STP0B Output Pin

Pulse Width = CCRA Value

Single Pulse GenerationRev. 2.30

77

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter Value

ST0M [1:0] = 10 ; ST0IO [1:0] = 11

Counter stopped
by CCRACounter Reset when
ST0ON returns high

CCRA
Pause

Counter Stopsby software

Resume

CCRP

Time
ST0ON
Software
Trigger

Auto. set by
STCK0 pin

Cleared by
CCRA match

STCK0 pin

Software
Trigger

Software
Trigger

Software
Software Trigger
Clear

STCK0 pin
Trigger

ST0PAU
ST0POLNo CCRP Interrupts
generated

CCRP Int. Flag
STMP0F
CCRA Int. Flag
STMA0FSTM O/P Pin(ST0OC=1)

STM O/P Pin(ST0OC=0)

Output Inverts
when ST0POL = 1

Pulse Width
set by CCRA

Single Pulse Mode

Note: 1. Counter stopped by CCRA match
2. CCRP is not used
3. The pulse is triggered by setting the ST0ON bit high
4. In the Single Pulse Mode, ST0IO [1:0] must be set to “11” and can not be changed.

Rev. 2.30

78

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Capture Input Mode
To select this mode bits ST0M1 and ST0M0 in the STM0C1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counterand can therefore be used for applications such as pulse width measurements. The external signal issupplied on the STP0I, whose active edge can be either a rising edge, a falling edge or both risingand falling edges; the active edge transition type is selected using the ST0IO1 and ST0IO0 bits in
the STM0C1 register. The counter is started when the ST0ON bit changes from low to high which is
initiated using the application program.
When the required edge transition appears on the STP0I the present value in the counter will belatched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on
the STP0I the counter will continue to free run until the ST0ON bit changes from high to low. Whena CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can beused to control the maximum counter value. When a CCRP compare match occurs from Comparator
P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals fromthe CCRP can be a useful method in measuring long pulse widths. The ST0IO1 and ST0IO0 bits canselect the active trigger edge on the STP0I to be a rising edge, falling edge or both edge types. If the
ST0IO1 and ST0IO0 bits are both set high, then no capture operation will take place irrespectiveof what happens on the STP0I, however it must be noted that the counter will continue to run. The
ST0CCLR and ST0DPX bits are not used in this mode.
There are some considerations that should be noted. If the captured pulse width is less than 2 timer
clock periods, it may be ignored by hardware. After the counter value is latched to the CCRA
registers by an active capture edge, the STMA0F flag will be set high after 0.5 timer clock period.
The delay time from the active capture edge received to the action of latching counter value to
CCRA registers is less than 1.5 timer clock periods.

Rev. 2.30

79

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter Value

ST0M [1:0] = 01

Counter clearedby CCRPCounter Counter
Stop
Reset

CCRP
YY

Pause

Resume

XX
Time
ST0ON
ST0PAU
Activeedge

Activeedge

Active edge

STM capture pin
STP0I

CCRA Int. Flag
STMA0F
CCRP Int. Flag
STMP0FCCRA
Value
ST0IO [1:0]
Value

XX
00 – Rising edge

YY

01 – Falling edgeXX
10 – Both edges

YY
11 – Disable Capture

Capture Input Mode

Note: 1. ST0M[1:0] = 01 and active edge set by the ST0IO[1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. The ST0CCLR and ST0DPX bits are not used
4. No output function – ST0OC and ST0POL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal tozero.

Rev. 2.30

80

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Periodic Type TM – PTM
The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM canalso be controlled with two external input pins and can drive two external output pins.
DeviceName

TM Input Pin

TM Output Pin

HT66F003

10-bit PTM

PTCK1, PTP1I

PTP1,PTP1B

10-bit PTM

PTCK0, PTP0I
PTCK1, PTP1I

PTP0,PTP0B
PTP1,PTP1B

HT66F004

Periodic TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock
source. There are two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with the CCRA and CCRP registers.
The only way of changing the value of the 10-bit counter using the application program, is toclear the counter by changing the PTnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pin. All operating setup conditions are
selected using relevant internal registers.
CCRP
Comparator P Match
10-bit Comparator P
000
001
b0~b9
010
Counter Clear 0
011
10-bit Count-up Counter
1
100
101 PTnON
PTnCCLR
110 PTnPAU
b0~b9
111
Comparator A Match
10-bit Comparator A
PTnCK2~PTnCK0
PTnIO1, PTnIO0

fSYS/4
fSYS
fH/16
fH/64
fTBC
fTBC
PTCKn

PTMPnF Interrupt
PTnOC
OutputControl

PTPn
PTPnB

PTnM1, PTnM0 PTnPOL
PTnIO1, PTnIO0
PTMAnF Interrupt
PTnCKS

Edge
Detector

CCRA

Polarity
Control

0
1

PTPnI

Periodic Type TM Block Diagram (n=0 or 1)

Periodic Type TM Register Description
Overall operation of the Periodic TM is controlled using a series of registers. A read only registerpair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which
setup the different operating and control modes.

Rev. 2.30

81

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Register
Name

Bit
7

6

5

4

3

2

1

0

—

—

PTMnC0PTnPAU PTnCK2

PTnCKnPTnCK0PTnON—

PTMnCn

PTnM1

PTnM0

PTnIO1PTnIO0PTnOC

PTnPOL

PTMnDL

D7

D6

D5

D4

D3

D2

D1

D0

PTnCKS PTnCCLR

PTMnDH

—

—

—

—

—

—

D9

D8

PTMnAL

D7

D6

D5

D4

D3

D2

D1

D0

PTMnAH

—

—

—

—

—

—

D9

D8

PTMnRPL

D7

D6

D5

D4

D3

D2

D1

D0

PTMnRPH

—

—

—

—

—

—

D9

D8

10-bit Periodic TM Register List (n=0 or 1)• PTMnC0 Register

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

PTnPAU

PTnCK2

PTnCK1

PTnCK0

PTnON

—

—

—

R/W

R/W

R/W

R/W

R/W

R/W

—

—

—

POR

0

0

0

0

0

—

—

—

Bit 7

PTnPAU: PTM Counter Pause Control
0: run1: pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue toconsume power. The counter will retain its residual value when this bit changes from low to highand resume counting from this value when the bit changes to a low value again.

Bit 6~4

PTnCK2~PTnCK0: Select PTM Counter clock
000: fSYS/4001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fTBC
110: PTCKn rising edge clock
111: PTCKn falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock source canbe chosen to be active on the rising or falling edge. The clock source fSYS is the system clock,while fTBC is another internal clock, the details of which can be found in the oscillator section.

Bit 3

PTnON: PTM Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter torun, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes fromhigh to low, the internal counter will retain its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initialcondition, as specified by the TM Output control bit, when the bit changes from low to high.

Bit 2~0

Unimplemented, read as “0”82June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• PTMnC1 Register

Rev. 2.30

Bit

7

6

5

4

3

Name

PTnM1

PTnM0

PTnIO1PTnIO0

PTnOC

2

1

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

PTnPOL PTnCKS PTnCCLR

Bit 7~6

PTnM1~ PTnM0: Select PTM Operation Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the PTnM1 and PTnM0 bits. In the Timer/
Counter Mode, the PTM output pin state is undefined.

Bit 5~4

PTnIO1~ PTnIO0: Select PTM output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of PTPnI or PTCKn
01: Input capture at falling edge of PTPnI or PTCKn
10: Input capture at falling/rising edge of PTPnI or PTCKn
11: Input capture disabled
Timer/counter Mode
UnusedThese two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the TM output
pin changes state when a compare match occurs from the Comparator A. The TM output pin canbe setup to switch high, switch low or to toggle its present state when a compare match occurs
from the Comparator A. When these bits are both zero, then no change will take place on the
output. The initial value of the TM output pin should be setup using the PTnOC bit. Note that theoutput level requested by the PT1IO1 and PTnIO0 bits must be different from the initial value
setup using the PTnOC bit otherwise no change will occur on the TM output pin when a compare
match occurs. After the TM output pin changes state, it can be reset to its initial level by changing
the level of the PTnON bit from low to high.
In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the TM output pin changes
state when a certain compare match condition occurs. The PWM output function is modified bychanging these two bits. It is necessary to change the values of the PTnIO1 and PTnIO0 bits only
after the TM has been switched off. Unpredictable PWM outputs will occur if the PTnIO1 andPTnIO0 bits are changed when the TM is running.

Bit 3

PTnOC: PTPn/PTPnB Output control bit
Compare Match Output Mode
0: initial low
1: initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active highThis is the output control bit for the TM output pin. Its operation depends upon whether TM isbeing used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Modeit determines the logic level of the TM output pin before a compare match occurs. In the PWM

83

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Mode it determines if the PWM signal is active high or active low.
Bit 2

PTnPOL: PTPn/PTPnB Output polarity Control
0: non-invert
1: invert
This bit controls the polarity of the PTPn/PTPnB output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in
the Timer/Counter Mode.

Bit 1

PTnCKS: PTM capture trigger source select0: From PTPnI
1: From PTCKn pin

Bit 0

PTnCCLR: Select PTM Counter clear condition
0: PTM Comparatror P match
1: PTM Comparatror A match
This bit is used to select the method which clears the counter. Remember that the Periodic TM
contains two comparators, Comparator A and Comparator P, either of which can be selected toclear the internal counter. With the PTnCCLR bit set high, the counter will be cleared when acompare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The
PTnCCLR bit is not used in the PWM, Single Pulse Output or Input Capture Mode.

• PTMnDL Register
Bit

7

6

5

4

3

2

1

0

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R

R

R

R

R

R

R

R

POR

0

0

0

0

0

0

0

0

Bit 7~0

PTM Counter Low Byte Register bit 7 ~ bit 0
PTM 10-bit Counter bit 7 ~ bit 0• PTMnDH Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

—

D9

D8

R/W

—

—

—

—

—

—

R

R

POR

—

—

—

—

—

—

0

0

3

2

1

0

Bit 7~2

Unimplemented, read as “0”Bit 1~0

PTM Counter High Byte Register bit 1 ~ bit 0
PTM 10-bit Counter bit 9 ~ bit 8• PTMnAL Register
Bit

6

5

4

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7~0Rev. 2.30

7

PTM CCRA Low Byte Register bit 7 ~ bit 0
PTM 10-bit CCRA bit 7 ~ bit 084

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• PTMnAH Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

—

D9

D8

R/W

—

—

—

—

—

—

R/W

R/W

POR

—

—

—

—

—

—

0

0

Bit 7~2

Unimplemented, read as “0”Bit 1~0

PTM CCRA High Byte Register bit 1 ~ bit 0
PTM 10-bit CCRA bit 9 ~ bit 8• PTMnRPL Register
Bit

7

6

5

4

3

2

1

0

Name

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7~0

PTM CCRP Low Byte Register bit 7 ~ bit 0
PTM 10-bit CCRP bit 7 ~ bit 0• PTMnRPH Register
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

—

D9

D8

R/W

—

—

—

—

—

—

R/W

R/W

POR

—

—

—

—

—

—

0

0

Bit 7~2

Unimplemented, read as "0"

Bit 1~0

PTMnRPH: PTM CCRP High Byte Register bit 1 ~ bit 0
PTM 10-bit CCRP bit 9 ~ bit 8

Periodic Type TM Operating Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register.
Compare Match Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be all cleared to
00 respectively. In this mode once the counter is enabled and running it can be cleared by threemethods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can becleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits
are all zero which allows the counter to overflow. Here both the PTMAnF and PTMPnF interrupt
request flags for Comparator Aand Comparator P respectively, will both be generated.
If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMAnF interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when PTnCCLR is high no PTMPnF interrupt request flag will be generated. In the Compare
Match Output Mode, the CCRA can not be set to “0”. If the CCRA bits are all zero, the counter will
overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMAnF interrupt
request flag will not be generated.

Rev. 2.30

85

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a PTMAnF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMPnF interrupt request
flag, generated from a compare match from Comparator P, will have no effect on the TM output pin.
The way in which the TM output pin changes state are determined by the condition of the PTnIO1
and PTnIO0 bits in the PTMnC1 register. The TM output pin can be selected using the PTnIO1
and PTnIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the TM output pin, which is setup after
the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1,
PTnIO0 bits are zero then no pin change will take place.
Counter Value

Counter overflow

CCRP=00x3FF

PTnCCLR = 0; PTnM [1:0] = 00
CCRP > 0Counter cleared by CCRP value

CCRP > 0Counter
RestartResume

CCRP

Pause

CCRA

Stop

Time
PTnON
PTnPAUPTnPOLCCRP Int. Flag
PTMPnF

CCRA Int. Flag
PTMAnFPTM O/P
Pin
Output pin set toinitial Level Low
if PTnOC=0

Output not affected by
PTMAnF flag. Remains High
until reset by PTnON bit

Output Toggle with
PTMAnF flag
Here PTnIO [1:0] = 11
Toggle Output selectNote PTnIO [1:0] = 10
Active High Output selectOutput Inverts
when PTnPOL is highOutput Pin
Reset to Initial value
Output controlled byother pin-shared function

Compare Match Output Mode – PTnCCLR = 0 (n=0 or 1)

Note: 1. With PTnCCLR = 0 – a Comparator P match will clear the counter
2. The TM output pin is controlled only by the PTMAnF flag
3. The output pin is reset to initial state by a PTnON bit rising edge

Rev. 2.30

86

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter Value

PTnCCLR = 1; PTnM [1:0] = 00
CCRA = 0Counter overflow

CCRA > 0 Counter cleared by CCRA value

0x3FF

CCRA=0Resume

CCRA

Pause

Stop

Counter Restart

CCRP
Time
PTnON
PTnPAUPTnPOLNo PTMAnF
flag generated
on CCRA
overflow

CCRA Int. Flag
PTMAnF
CCRP Int. Flag
PTMPnFPTM O/P
Pin

PTMPnF notgenerated

Output pin set toinitial Level Low
if PTnOC=0

Output does
not change
Output not affected by
TnAF flag. Remains High
until reset by PTnON bit

Output Toggle with
PTMAnF flag
Here PTnIO [1:0] = 11
Toggle Output selectNote PTnIO [1:0] = 10
Active High Output selectOutput Inverts
when PTnPOL is highOutput Pin
Reset to Initial value
Output controlled byother pin-shared function

Compare Match Output Mode – PTnCCLR = 1 (n=0 or 1)

Note: 1. With PTnCCLR = 1 – a Comparator A match will clear the counter
2. The TM output pin is controlled only by the PTMAnF flag
3. The output pin is reset to initial state by a PTnON rising edge
4. The PTMPnF flag is not generated when PTnCCLR = 1

Rev. 2.30

87

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Timer/Counter Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should all be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode theTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the TM output pin is not used in thismode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively
and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within
the TM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the PTnCCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the otherone is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore
be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare matchoccurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used to
select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are used
to enable the PWM output or to force the TM output pin to a fixed high or low level. The PTnPOL
bit is used to reverse the polarity of the PWM output waveform.
• 10-bit PWM Mode, Edge-aligned Mode
CCRP

CCRP = 0~1024

Period

CCRP=0 : period= 1024 clocks
CCRP=1~1023: period=1~1023 clocks

Duty

CCRA

If fSYS = 16MHz, PTM clock source select fSYS/4, CCRP = 512 and CCRA = 128,
The PTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.

Rev. 2.30

88

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter Value

PTnDPX = 0; PTnM [1:0] = 10

Counter clearedby CCRPCounter Reset when
PTnON returns high

CCRP
Pause Resume

CCRA

Counter Stop if
PTnON bit low

Time
PTnON
PTnPAUPTnPOLCCRA Int. Flag
PTMAnF

CCRP Int. Flag
PTMPnFPTM O/P Pin(PTnOC=1)

PTM O/P Pin(PTnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP

PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
When PTnPOL = 1

PWM Output Mode (n=0 or 1)

Note: 1. Here Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PTnIO[1:0] = 00 or 01
4. The PTnCCLR bit has no influence on PWM operationRev. 2.30

89

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Single Pulse Output Mode
To select this mode, the required bit pairs, PTnM1 and PTnM0 should be set to 10 respectively andalso the corresponding PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the PTnON
bit can also be made to automatically change from low to high using the external PTCKn pin,which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The PTnON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the PTnON bit is cleared to zero, which can be implemented using the application program orwhen a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PTnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate TM interrupts. The countercan only be reset back to zero when the PTnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR bit is also not used.
Leading Edge

Trailing Edge

PTnON bit0� 1

PTnON bit
1� 0

S/W Command
SET“PTnON”
or
PTCKn Pin
Transition
PTPn/PTPnB
Output Pin

S/W Command
CLR“PTnON”
or
CCRA Compare
Match

Pulse Width = CCRA Value

Single Pulse Generation (n=0 or 1)

Rev. 2.30

90

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter Value

PTnM [1:0] = 10 ; PTnIO [1:0] = 11

Counter stopped
by CCRACounter Reset when
PTnON returns high

CCRA
Pause

Counter Stopsby software

Resume

CCRP

Time
PTnON
Software
Trigger

Auto. set by
PTCKn pin

Cleared by
CCRA match

PTCKn pin

Software
Trigger

Software
Trigger

Software
Software Trigger
Clear

PTCKn pin
Trigger

PTnPAUPTnPOLNo CCRP Interrupts
generated

CCRP Int. Flag
PTMPnF
CCRA Int. Flag
PTMAnFPTM O/P Pin(PTnOC=1)

PTM O/P Pin(PTnOC=0)

Output Inverts
when PTnPOL = 1

Pulse Width
set by CCRA

Single Pulse Mode

Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the PTCKn pin or by setting the PTnON bit high
4. A PTCKn pin active edge will automatically set the PTnON bit high
5. In the Single Pulse Mode, PTnIO [1:0] must be set to “11” and can not be changed.

Rev. 2.30

91

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Capture Input Mode
To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counterand can therefore be used for applications such as pulse width measurements. The external signal
is supplied on the PTPnI or PTCKn pin, selected by the PTnCKS bit in the PTMnC1 register. The
input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; theactive edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register.
The counter is started when the PTnON bit changes from low to high which is initiated using theapplication program.
When the required edge transition appears on the PTPnI or PTCKn pin the present value in the
counter will be latched into the CCRA register and a TM interrupt generated. Irrespective of what
events occur on the PTPnI or PTCKn pin the counter will continue to free run until the PTnON bitchanges from high to low. When a CCRP compare match occurs the counter will reset back to zero;in this way the CCRP value can be used to control the maximum counter value. When a CCRP
compare match occurs from Comparator P, a TM interrupt will also be generated. Counting thenumber of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse
widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin
to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high,then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin,
however it must be noted that the counter will continue to run. The PTnCCLR, PTnOC and PTnPOL
bits are not used in this mode.
There are some considerations that should be noted. If PTCKn is used as the capture input source,then it cannot be selected as the PTMn clock source. If the captured pulse width is less than 2timer clock periods, it may be ignored by hardware. After the counter value is latched to the CCRA
registers by an active capture edge, the PTMAnF flag will be set high after 0.5 timer clock period.
The delay time from the active capture edge received to the action of latching counter value to
CCRA registers is less than 1.5 timer clock periods.

Rev. 2.30

92

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMCounter Value

PTnM [1:0] = 01

Counter clearedby CCRPCounter Counter
Stop
Reset

CCRP
YY

Pause

Resume

XX
Time
PTnON
PTnPAUPTM capture
pin PTPnIor PTCKn

Activeedge

Activeedge

Active edge

CCRA Int. Flag
PTMAnF
CCRP Int. Flag
PTMPnFCCRA
Value
PTnIO [1:0]
Value

XX
00 – Rising edge

YYXX

01 – Falling edge 10 – Both edges

YY
11 – Disable Capture

Capture Input Mode (n=0 or 1)

Note: 1. PTnM[1:0] = 01 and active edge set by the PTnIO[1:0] bits
2. A TM Capture input pin active edge transfers counter value to CCRA
3. The PTnCCLR bit is not used
4. No output function – PTnOC and PTnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal tozeroRev. 2.30

93

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronicsystems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with thecorresponding follow-on benefits of lower costs and reduced component space requirements.

A/D Overview
The devices contain a multi-channel analog to digital converter which can directly interface
to external analog signals, such as that from sensors or other control signals and convert thesesignals directly into a 12-bit digital value. The external or internal analog signal to be converted isdetermined by the SAINS and SACS bit fields. Note that when the internal analog signal is to beconverted, the pin-shared control bits should also be properly configured except the SAINS and
SACS bit fields. More detailed information about the A/D input signal is described in the “A/DConverter Control Registers” and “A/D Converter Input Signal” sections respectively.
Part No.

Input Channels

A/D Channel Select Bits

Input Pins

HT66F002
HT66F0025
HT66F003

4

SAINS2~SAINS0,
SACS1~SACS0

AN0~AN3

HT66F004

8

SAINS2~SAINS0,
SACS2~SACS0

AN0~AN7

The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
Pin-shared selection

SACS[2:0]
ENADC

AN0
AN5
AN6
AN7

SAPIN

MUX

12-bitSAR ADC

AVDD
VR

ADBZ

SADOH[7:0]

SAINT

SADOL[7:0]

VREFO
SAINS[2:0]

Divider

VREFO

fSYS

AVDD
VR
PASR
VREF
VBG
(1.04V)

SACKS[2:0]

ENOPA
VRI

OPA
SAVRS[3:0]

A/D Converter Structure

Rev. 2.30

94

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
A/D Converter Register Description
Overall operation of the A/D converter is controlled using five registers. A read only register pairexists to store the ADC data 12-bit value. The remaining three registers are control registers which
setup the operating and control function of the A/D converter.
Bit

Name

7

6

5

4

3

2

1

0

SADOL
(ADRFS=0)

D3

D2

D1

D0

—

—

—

—

SADOL
(ADRFS=1)

D7

D6

D5

D4

D3

D2

D1

D0

SADOH
(ADRFS=0)

D11

D10

D9

D8

D7

D6

D5

D4

SADOH
(ADRFS=1)

—

—

—

—

D11

D10

D9

D8
SACS0

SADC0

START

ADBZ

ENADC

ADRFS

—

—

SACS1

SADC1

SAINS2

SAINS1SAINS0

—

—

SACK2

SACK1

SACK0

SADC2

ENOPA

VBGEN

—

—

SAVRS3SAVRS2SAVRS1SAVRS0A/D Converter Register List – HT66F002/HT66F0025/HT66F003
Bit

Name

7

6

5

4

3

2

1

0

SADOL
(ADRFS=0)

D3

D2

D1

D0

—

—

—

—

SADOL
(ADRFS=1)

D7

D6

D5

D4

D3

D2

D1

D0

SADOH
(ADRFS=0)

D11

D10

D9

D8

D7

D6

D5

D4

SADOH
(ADRFS=1)

—

—

—

—

D11

D10

D9

D8

SADC0

START

ADBZ

ENADC

ADRFS

—

SACS2

SACS1

SACS0

SADC1

SAINS2

SAINS1SAINS0——SACKS2 SACKS1 SACKS0

SADC2

ENOPA

VBGEN

—

—

SAVRS3SAVRS2SAVRS1SAVRS0A/D Converter Register List – HT66F004

A/D Converter Data Registers – SADOL, SADOH
As the devices contain an internal 12-bit A/D converter, it requires two data registers to store theconverted value. These are a high byte register, known as SADOH, and a low byte register, known
as SADOL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits.
Any unused bits will be read as zero. Note that the A/D converter data register contents will not becleared to zero if the A/D converter is disabled.
ADRFS

SADOH
7

6

5

4

0

D11 D10

D9

1

0

0

0

SADOL

3

2

1

0

7

D8

D7

0

6

5

4

3

2

1

0

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

A/D Data Registers

Rev. 2.30

95

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
A/D Converter Control Registers – SADC0, SADC1, SADC2, PASR, PBSR
To control the function and operation of the A/D converter, several control registers known as
SADC0, SADC1 and SADC2 are provided. These 8-bit registers define functions such as theselection of which analog channel is connected to the internal A/D converter, the digitised data
format, the A/D clock source as well as controlling the start function and monitoring the A/D
converter busy status. The SACS2~SACS0 bits in the SADC0 register are used to determine which
external channel input is selected to be converted. The SAINS2~SAINS0 bits in the SADC1 registerare used to determine that the analog signal to be converted comes from the internal analog signal
or external analog channel input. If the SAINS2~SAINS0 bits are set to “000”, the external analog
channel input is selected to be converted and the SACS2~SACS0 bits can determine which external
channel is selected to be converted. If the SAINS2~SAINS0 bits are set to “001~011”, the AVDD
voltage is selected to be converted. If the SAINS2~SAINS0 bits are set to “101~111”, the OPA
output voltage is selected to be converted. When VREF or VBG is selected as ADC input or ADC
reference voltage, the OPA needs to be enabled by setting ENOPA to 1.
Note that when the programs select external signal and internal signal as an ADC input signal
simultaneously, then the hardware will only choose the internal signal as an ADC input. In addition,
if the programs select external reference voltage VREF and the internal reference voltage VBG as ADC
reference voltage, then the hardware will only choose the internal reference voltage VBG as an ADC
reference voltage input.
The pin-shared function control registers, named PASR and PBSR, contain the corresponding pinshared selection bits which determine which pins on Port A and Port B are used as analog inputs
for the A/D converter input and which pins are not to be used as the A/D converter input. Whenthe pin is selected to be an A/D input, its original function whether it is an I/O or other pin-sharedfunction will be removed. In addition, any internal pull-high resistors connected to these pins will be
automatically removed if the pin is selected to be an A/D input.
• SADC0 Register – HT66F002/HT66F0025/HT66F003

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

START

ADBZ

ENADC

ADRFS

—

—

SACS1

SACS0

R/W

R/W

R

R/W

R/W

—

—

R/W

R/W

POR

0

0

0

0

—

—

0

0

Bit 7

START: Start the A/D conversion
0→1→0: Start A/D conversion
0→1: Reset the A/D converter and set ADBZ to 0
1→0: Start A/D conversion and set ADBZ to 1

Bit 6

ADBZ: ADC busy flag
0: A/D conversion ended or no conversion
1: A/D is busy

Bit 5

ENADC: ADC enable/disable control register0: ADC disable
1: ADC enable

Bit 4

ADRFS: A/D output data format selection bit
0: ADC output data format → SADOH=D[11:4]; SADOL=D[3:0]
1: ADC output data format → SADOH=D[11:8]; SADOL=D[7:0]

Bit 3~2

Unimplemented, read as "0"

Bit 1~0

SACS1~SACS0: ADC input channels selection
00: ADC input channel comes from AN0
01: ADC input channel comes from AN1
10: ADC input channel comes from AN2
11: ADC input channel comes from AN3

96

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• SADC0 Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

START

ADBZ

ENADC

ADRFS

—

SACS2

SACS1

SACS0

R/W

R/W

R

R/W

R/W

—

R/W

R/W

R/W

POR

0

0

0

0

—

0

0

0

Bit 7

Bit 6
Bit 5
Bit 4
Bit 3
Bit 2~0

START: Start the A/D conversion
0→1→0: Start A/D conversion
0→1: Reset the A/D converter and set ADBZ to 0
1→0: Start A/D conversion and set ADBZ to 1
ADBZ: ADC busy flag
0: A/D conversion ended or no conversion
1: A/D is busy
ENADC: ADC enable/disable control register0: ADC disable
1: ADC enable
ADRFS: A/D output data format selection bit
0: ADC output data format → SADOH=D[11:4]; SADOL=D[3:0]
1: ADC output data format → SADOH=D[11:8]; SADOL=D[7:0]
Unimplemented, read as “0”SACS2~SACS0: ADC input channels selection
000: ADC input channel comes from AN0001: ADC input channel comes from AN1
010: ADC input channel comes from AN2
011: ADC input channel comes from AN3
100: ADC input channel comes from AN4
101: ADC input channel comes from AN5
110: ADC input channel comes from AN6
111: ADC input channel comes from AN7• SADC1 Register
Bit

7

6

5

4

3

2

1

0

Name

SAINS2

SAINS1SAINS0——SACKS2

SACKS1SACKS0

R/W

R/W

R/W

R/W

—

—

R/W

R/W

R/W

POR

0

0

0

—

—

0

0

0

Bit 7~5

Bit 4~3
Bit 2~0Rev. 2.30

SAINS2~SAINS0: Internal ADC input channel selection bit
000: ADC input only comes from external pin
001: ADC input also comes from AVDD
010: ADC input also comes from AVDD/2
011: ADC input also comes from AVDD/4
101: ADC input also comes from VR
110: ADC input also comes from VR/2
111: ADC input also comes from VR/4
Other Values: same as 000
Note: VR is OPA output voltage. VR can be one of VREF/VREF×2/VREF×3/VREF×4/VBG×2/ VBG×3/
VBG×4.
Unimplemented, read as "0"
SACKS2~SACKS0: ADC clock rate selection bit
000: SACLK=fSYS
001: SACLK=fSYS/2
010: SACLK=fSYS/4
011: SACLK=fSYS/8
100: SACLK=fSYS/16
101: SACLK=fSYS/32
110: SACLK=fSYS/64
111: SACLK=fSYS/128

97

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• SADC2 Register
Bit

7

6

5

4

3

2

1

0

Name

ENOPA

VBGEN

—

—

SAVRS3SAVRS2SAVRS1SAVRS0

R/W

R/W

R/W

—

—

R/W

R/W

R/W

R/W

POR

0

0

—

—

0

0

0

0

Bit 7
Bit 6
Bit 5~4
Bit 3~0

ENOPA: OPA enable/disable control register0: OPA disable
1: OPA enable
VBGEN: Bandgap buffer disable/enable control bit
0: Bandgap buffer disable
1: Bandgap buffer enable
Unimplemented, read as "0"
SAVRS3~SAVRS0: ADC reference voltage selection bit
0000: ADC reference voltage comes from AVDD
0001: ADC reference voltage comes from VREF
0010: ADC reference voltage comes from VREF × 2
0011: ADC reference voltage comes from VREF × 3
0100: ADC reference voltage comes from VREF × 4
1001: Inhibit to use
1010: ADC reference voltage comes from VBG × 2
1011: ADC reference voltage comes from VBG × 3
1100: ADC reference voltage comes from VBG × 4
Other Values: same as 0000
Note: (1) When Select VREF or VREF×2 or VREF×3 or VREF×4 as ADC reference voltage,
HT66F002/HT66F0025: pin share control bits (PAS3, PAS2) is (1, 0) to select VREF as input.
HT66F003: pin share control bits (PAS2, PAS1) is (1, 0) to select VREF as input.
HT66F004: pin share control bits (PAS3, PAS2) is (1, 0) to select VREF as input(2) VBG=1.04V(3) When SAVRS3=1, OPA selects VBG as input.
(4) If the programs select external reference voltage VREF and the internal reference
voltage VBG as ADC reference voltage, then the hardware will only choose the internalreference voltage VBG as an ADC reference voltage input.

A/D Converter Operation
The START bit is used to start and reset the A/D converter. When the microcontroller sets this bitfrom low to high and then low again, an analog to digital conversion cycle will be initiated. When
the START bit is brought from low to high but not low again, the ADBZ bit in the SADC0 register
will be cleared to zero and the analog to digital converter will be reset. It is the START bit that isused to control the overall start operation of the internal analog to digital converter.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in process or not. When the A/D converter is reset by setting the START bit from
low to high, the ADBZ flag will be cleared to 0. This bit will be automatically set to “1” by the
microcontroller after an A/D conversion is successfully initiated. When the A/D conversion iscomplete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internalinterrupt signal will be generated. This A/D internal interrupt signal will direct the program flow tothe associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the ADBZ bit in the SADC0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
Although the A/D clock source is determined by the system clock fSYS, and by bits SACK2~SACK0,
there are some limitations on the maximum A/D clock source speed that can be selected. As therecommended value of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be
taken for system clock frequencies. For example, if the system clock operates at a frequency of
4MHz, the SACK2~SACK0 bits should not be set to 000B or 11xB. Doing so will give A/D clock
periods that are less than the minimum A/D clock period or greater than the maximum A/D clock
period which may result in inaccurate A/D conversion values.
Rev. 2.30

98

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ENADC bit in the SADC0 register. This bit must be set high to power on the A/D converter. Whenthe ENADC bit is set high to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if nopins are selected for use as A/D inputs by configuring the corresponding pin-shared control bits, if
the ENADC bit is high then some power will still be consumed. In power conscious applications it
is therefore recommended that the ENADC is set low to reduce power consumption when the A/D
converter function is not being used.
The reference voltage supply to the A/D Converter can be supplied from either the internal ADC power
or from an external reference sources supplied on pin VREF or VBG voltage. The desired selection ismade using the SAVRS3~ SAVRS0 bits. As the VREF pin is pin-shared with other functions, when the
VREF pin is selected as the reference voltage supply pin, the VREF pin-shared function control bits
should be properly configured to disable other pin functions. When VREF or VBG is selected by ADC
input or ADC reference voltage, the OPA needs to be enabled by setting ENOPA=1.
Reference

SAVRS[3:0]

AVDD

0000

ADC Reference Voltage comes from AVDD

Description

VREF

0001

ADC Reference Voltage comes from External VREF

VREF×20010

ADC Reference Voltage comes from External VREF×2

VREF×30011

ADC Reference Voltage comes from External VREF×3

VREF×40100

ADC Reference Voltage comes from External VREF×4

VBG×2

1010

ADC Reference Voltage comes from VBG×2

VBG×3

1011

ADC Reference Voltage comes from VBG×3

VBG×4

1100

ADC Reference Voltage comes from VBG×4
A/D Converter Reference Voltage Selection

A/D Converter Input Signal
All of the A/D analog input pins are pin-shared with the I/O pins on Port A and Port B as well asother functions. The corredponding selection bits for each I/O pin in the PASR and PBSR registers,
determine whether the input pins are setup as A/D converter analog inputs or whether they haveother functions. If the pin-shared function control bits configure its corresponding pin as an A/D
analog channel input, the pin will be setup to be an A/D converter external channel input and theoriginal pin functions disabled. In this way, pins can be changed under program control to change
their function between A/D inputs and other functions. All pull-high resistors, which are setup
through register programming, will be automatically disconnected if the pins are setup as A/D
inputs. Note that it is not necessary to first setup the A/D pin as an input in the PAC and PBC port
control register to enable the A/D input as when the pin-shared function control bits enable an A/D
input, the status of the port control register will be overridden.
The A/D converter has its own reference voltage pin, VREF, however the reference voltage canalso be supplied from the power supply pin, a choice which is made through the SAVRS[3:0] in the
SADC2 register. The analog input values must not be allowed to exceed the value of VREF.

Conversion Rate and Timing Diagram
A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/Dclock cycles. Therefore a total of 16 A/D clock cycles for an A/D conversion which is defined as tADC
are necessary.
Maximum single A/D conversion rate = 1/(A/D clock period×16)

Rev. 2.30

99

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
However, there is a usage limitation on the next A/D conversion after the current conversion iscomplete. When the current A/D conversion is complete, the converted digital data will be stored
in the A/D data register pair and then latched after half an A/D clock cycle. If the START bit is set
to 1 in half an A/D clock cycle after the end of A/D conversion, the converted digital data stored
in the A/D data register pair will be changed. Therefore, it is recommended to initiate the next A/
D conversion after a certain period greater than half an A/D clock cycle at the end of current A/Dconversion.
tON2ST
ENADC

off

on

off
A/D sampling time
tADCS

on

A/D sampling time
tADCS

START

SACS2~SACS0>1/2tADCK>1/2 tADCK

ADBZ

011B

Power-on
Reset

010B

000B

Start of A/D
conversion

Start of A/D
conversion

Reset A/D
conversion
1. Define port configuration
2. Select analog channel

001B
Start of A/D
conversion

Reset A/D
conversion
End of A/D
conversiontADC
A/D conversion time

Reset A/D
conversion
End of A/D
conversiontADC
A/D conversion time

A/D Conversion Timing

Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion frequency by SACKS2~ SACKS0• Step 2
Enable the ADC by set ENADC=1• Step 3
Select which pins will be configure as ADC analog inputs• Step 4
If input comes from I/O, set SAINS[2:0]=000 and then set SACS bit fields to corresponding PAD
input
If input comes from internal input, set SAINS[2:0] to corresponding internal input source• Step 5
Select reference voltage comes from external VREF, AVDD or VBG by SAVRS[3:0]Note: (1) If select VREF as reference voltage, (PAS3, PAS2) = (1, 0) for HT66F002/0025/004(2) If select VREF as reference voltage, (PAS2, PAS1) = (1, 0) for HT66F003• Step 6
Select ADC output data format by ADRFS

Rev. 2.30

100

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• Step 7
If ADC interrupt is used, the interrupt control registers must be correctly configured to ensure
the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D converterinterrupt bits, ADE, must both set high in advance.
• Step 8
The A/D convert procedure can now be initialized by set START from low to high and then low
again• Step 9
If ADC is under conversion, ADBZ=1. After A/D conversion process is completed, the ADBZ
flag will go low, and then output data can be read from SADOH and SADOL registers. If the
ADC interrupt is enabled and the stack is not full, data can be acquired by interrupt service
program. Another way to get the A/D output data is polling the ADBZ flag.

Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by clearing the ENADC bit in the
SADC0 register. When this happens, the internal A/D converter circuits will not consume powerirrespective of what analog voltage is applied to their input lines. If the A/D converter input lines areused as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, thenthis may lead to some increase in power consumption.

A/D Transfer Function
As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single
bit analog input value of VDD or VREF divided by 4096.
1 LSB= (AVDD or VREF) / 4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage = A/D output digital value × (AVDD or VREF) / 4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitisedvalues will change at a point 0.5 LSB below where they would change without the offset, and thelast full scale digitised value will change at a point 1.5 LSB below the VDD or VREF level.
                            


 
 




      





 



  

 

       
  

  

Ideal A/D Transfer Function

Rev. 2.30

101

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
A/D Programming Examples
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used todetermine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion
clr ADE			 ; disable ADC interrupt
mov a,0BH
mov SADC1,a 			 ; select fSYS/8 as A/D clock and switch off the bandgap reference voltage
set ENADC
mov a,03h 				; setup PASR to configure pin AN0
mov PASR,a
mov a,20h
mov SADC0,a 			 ; enable and connect AN0 channel to A/D converter:
start_conversion:
clr START 				; high pulse on start bit to initiate conversion
set START 				; reset A/D
clr START 				; start A/Dpolling_EOC:
sz ADBZ 				; poll the SADC0 register ADBZ bit to detect end of A/D conversion
jmp polling_EOC 		 ; continue polling
mov a,SADOL 			 ; read low byte conversion result value
mov SADOL_buffer,a; save result to user defined register
mov a,SADOH 			 ; read high byte conversion result value
mov SADOH_buffer,a		 ; save result to user defined register::
jmp start_conversion ; start next a/d conversion

Rev. 2.30

102

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Example: using the interrupt method to detect the end of conversion
clr ADE 				; disable ADC interrupt
mov a,0BH
mov SADC1,a 			 ; select fSYS/8 as A/D clock and switch off the bandgap reference voltage
set ENADC
mov a,03h 				; setup PASR to configure pin AN0
mov PASR,a
mov a,20h
mov SADC0,a 			 ; enable and connect AN0 channel to A/D converter
Start_conversion:
clr START 				; high pulse on START bit to initiate conversion
set START 				; reset A/D
clr START 				; start A/D
clr ADF 				; clear ADC interrupt request flag
set ADE 				; enable ADC interrupt
set EMI 				; enable global interrupt::; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a 		 ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a; save STATUS to user defined memory::
mov a,SADOL 			 ; read low byte conversion result value
mov SADOL_buffer,a		 ; save result to user defined register
mov a,SADOH 			 ; read high byte conversion result value
mov SADOH_buffer,a		 ; save result to user defined register::
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a 			 ; restore STATUS from user defined memory
mov a,acc_stack 		 ; restore ACC from user defined memory
retiRev. 2.30

103

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or aninternal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The devices contain several externalinterrupts and internal interrupts functions. The external interrupts are generated by the action of
the external INT0~INT1 and INT pin, while the internal interrupts are generated by various internalfunctions such as the TMs, Time Base, EEPROM and the A/D converter.

Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in theaccompanying table. The number of registers depends upon the device chosen but fall into three
categories. The first is the INTC0~INTC1 registers which setup the primary interrupts, the second
is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG
register to setup the external interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual registers as well asinterrupt flags to indicate the presence of an interrupt request. The naming convention of thesefollows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number ofthat interrupt followed by either an “E” for enable/disable bit or “F” for request flag.
Enable Bit

Request Flag

Notes

GlobalFunction

EMI

—

—

INT Pin

INTE

INTF

—

A/D Converter

ADE

ADF

—

Multi-function

MF0E

MF0F

—

Time Bases

TBnE

TBnF

n=0 or 1—

EEPROM
TM

DEE

DEF

STMA0E

STMA0F

STMP0E

STMP0F—

Interrupt Register Bit Naming Conventions – HT66F002/HT66F0025
Enable Bit

Request Flag

Notes

GlobalFunction

EMI

—

—

INT Pin

INTE

INTF

—

A/D Converter

ADE

ADF

—

Multi-function

MFnE

MFnF

n=0 or 1

Time Bases

TBnE

TBnF

n=0 or 1

EEPROM

DEE

DEF

—

STMA0E

STMA0F

STMP0E

STMP0F

PTMA1E

PTMA1F

PTMP1EPTMP1F

TM—

Interrupt Register Bit Naming Conventions – HT66F003

Rev. 2.30

104

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Enable Bit

Request Flag

GlobalFunction

EMI

—

Notes
—

INTn Pin

INTnE

INTnF

n=0 or 1—

A/D Converter

ADE

ADF

Multi-function

MF0E

MF0F

—

Time Bases

TBnE

TBnF

n=0 or 1

EEPROM

DEE

DEF

—

PTMAnE

PTMAnF

PTMPnE

PTMPnFTM

n=0 or 1

Interrupt Register Bit Naming Conventions – HT66F004
Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

INTEG

—

—

—

—

—

—

INT0S1

INT0S0

INTC0

—

TB1F

TB0F

INTF

TB1E

TB0E

INTE

EMI

INTC1

—

ADF

DEF

MF0F

—

ADE

DEE

MF0E

MFI0

—

—

STMA0F

STMP0F——

STMA0E

STMP0E

Bit2

Bit1

Bit0
INT0S0Interrupt Register List – HT66F002/HT66F0025
Name

Bit7

Bit6

Bit5

Bit4

Bit3

INTEG

—

—

—

—

—

—

INT0S1

INTC0

—

TB1F

TB0F

INTF

TB1E

TB0E

INTE

EMI

INTC1

MF1F

ADF

DEF

MF0F

MF1E

ADE

DEE

MF0E

MFI0

—

—

STMA0F

STMP0F——

STMA0E

STMP0E

MFI1——

PTMA1F

PTMP1F——

PTMA1EPTMP1EInterrupt Register List – HT66F003
Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

INTEG

—

—

—

—

INT1S1INT1S0INT0S1

INT0S0

INTC0

—

TB1F

TB0F

INT0F

TB1E

TB0E

INT0E

EMI

INTC1

INT1F

ADF

DEF

MF0F

INT1E

ADE

DEE

MF0E

MFI0

PTMA1F

PTMP1F

PTMA0F

PTMP0F

PTMA1EPTMP1E

PTMA0E

PTMP0EInterrupt Register List – HT66F004• INTEG Register – HT66F002/HT66F0025/HT66F003

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

—

—

INT0S1

INT0S0

R/W

—

—

—

—

—

—

R/W

R/W

POR

—

—

—

—

—

—

0

0

Bit 7 ~ 2

Unimplemented, read as "0"

Bit 1 ~ 0

INT0S1, INT0S0: Defines INT interrupt active edge
00: Disable Interrupt
01: Rising Edge Interrupt
10: Falling Edge Interrupt
11: Dual Edge Interrupt

105

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• INTEG Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

—

—

—

—

INT1S1INT1S0INT0S1

INT0S0

R/W

—

—

—

—

R/W

R/W

R/W

R/W

POR

—

—

—

—

0

0

0

0

Bit 7 ~ 4

Unimplemented, read as “0”Bit 3 ~ 2

INT1S1, INT1S0: Defines INT1 interrupt active edge
00: Disable Interrupt
01: Rising Edge Interrupt
10: Falling Edge Interrupt
11: Dual Edge Interrupt

Bit 1 ~ 0

INT0S1, INT0S0: Defines INT0 interrupt active edge
00: Disable Interrupt
01: Rising Edge Interrupt
10: Falling Edge Interrupt
11: Dual Edge Interrupt• INTC0 Register – HT66F002/HT66F0025/T66F003

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

—

TB1F

TB0F

INTF

TB1E

TB0E

INTE

EMI

R/W

—

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

0

0

0

0

0

0

0

Bit 7

Unimplemented, read as "0"

Bit 6

TB1F : Time Base 1 Interrupt Request Flag
0: No request
1: Interrupt request

Bit 5

TB0F: Time Base 0 Interrupt Request Flag
0: No request
1: Interrupt request

Bit 4

INTF: INT Interrupt Request Flag
0: No request
1: Interrupt request

Bit 3

TB1E : Time Base 1 Interrupt Control
0: Disable
1: Enable

Bit 2

TB0E: Time Base 0 Interrupt Control
0: Disable
1: Enable

Bit 1

INTE: INT Interrupt Control
0: Disable
1: Enable

Bit 0

EMI: Global Interrupt Control
0: Disable
1: Enable

106

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• INTC0 Register – HT66F004
Bit

7

6

5

4

3

2

1

0

Name

—

TB1F

TB0F

INT0F

TB1E

TB0E

INT0E

EMI

R/W

—

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

0

0

0

0

0

0

0

Bit 7

Unimplemented, read as “0”Bit 6

TB1F: Time Base 1 Interrupt Request Flag
0: No request
1: Interrupt request

Bit 5

TB0F: Time Base 0 Interrupt Request Flag
0: No request
1: Interrupt request

Bit 4

INT0F: INT0 Interrupt Request Flag
0: No request
1: Interrupt request

Bit 3

TB1E : Time Base 1 Interrupt Control
0: Disable
1: Enable

Bit 2

TB0E: Time Base 0 Interrupt Control
0: Disable
1: Enable

Bit 1

INT0E: INT0 Interrupt Control
0: Disable
1: Enable

Bit 0

EMI: Global Interrupt Control
0: Disable
1: Enable• INTC1 Register – HT66F002/HT66F0025
Bit

7

6

5

4

3

2

1

0

Name

—

ADF

DEF

MF0F

—

ADE

DEE

MF0E

R/W

—

R/W

R/W

R/W

—

R/W

R/W

R/W

—

0

0

0

—

0

0

0

POR
Bit 7
Bit 6

Bit 5

Bit 4

Bit 3
Bit 2

Bit 1

Bit 0

Rev. 2.30

Unimplemented, read as "0"
ADF: A/D Converter Interrupt Request Flag
0: No request
1: Interrupt request
DEF: Data EEPROM Interrupt Request Flag
0: No request
1: Interrupt request
MF0F: Multi-function 0 Interrupt Request Flag
0: No request
1: Interrupt request
Unimplemented, read as "0"
ADE: A/D Converter Interrupt Control
0: Disable
1: Enable
DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
MF0E: Multi-function 0 Interrupt Control
0: Disable
1: Enable

107

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• INTC1 Register – HT66F003
Bit

7

6

5

4

3

2

1

0

Name

MF1F

ADF

DEF

MF0F

MF1E

ADE

DEE

MF0E

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7

Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0

MF1F: Multi-function 1 Interrupt Request Flag
0: No request
1: Interrupt request
ADF: A/D Converter Interrupt Request Flag
0: No request
1: Interrupt request
DEF: Data EEPROM Interrupt Request Flag
0: No request
1: Interrupt request
MF0F: Multi-function 0 Interrupt Request Flag
0: No request
1: Interrupt request
MF1E: Multi-function 1 Interrupt Control
0: Disable
1: Enable
ADE: A/D Converter Interrupt Control
0: Disable
1: Enable
DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
MF0E: Multi-function 0 Interrupt Control
0: Disable
1: Enable• INTC1 Register – HT66F004

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

INT1F

ADF

DEF

MF0F

INT1E

ADE

DEE

MF0E

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7

INT1F: INT1 Interrupt Request Flag
0: No request
1: Interrupt request

Bit 6

ADF: A/D Converter Interrupt Request Flag
0: No request
1: Interrupt request

Bit 5

DEF: Data EEPROM Interrupt Request Flag
0: No request
1: Interrupt request

Bit 4

MF0F: Multi-function 0 Interrupt Request Flag
0: No request
1: Interrupt request

Bit 3

INT1E: INT1 Interrupt Control
0: Disable
1: Enable

Bit 2

ADE: A/D Converter Interrupt Control
0: Disable
1: Enable

Bit 1

DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable

Bit 0

MF0E: Multi-function 0 Interrupt Control
0: Disable
1: Enable

108

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• MFI0 Register – HT66F002/HT66F0025/HT66F003
Bit

7

6

5

4

3

2

1

0

Name

—

—

STMA0F

STMP0F——

STMA0E

STMP0E

R/W

—

—

R/W

R/W

—

—

R/W

R/W

POR

—

—

0

0

—

—

0

0

Bit 7 ~ 6

Unimplemented, read as "0"

Bit 5

STMA0F: STM Comparator A match interrupt request flag
0: No request
1: Interrupt request

Bit 4

STMP0F: STM Comparator P match interrupt request flag
0: No request
1: Interrupt request

Bit 3 ~ 2

Unimplemented, read as "0"

Bit 1

STMA0E: STM Comparator A match interrupt control
0: Disable
1: Enable

Bit 0

STMP0E: STM Comparator P match interrupt control
0: Disable
1: Enable• MFI0 Register – HT66F004

Rev. 2.30

Bit

7

6

5

4

3

2

1

0

Name

PTMA1F

PTMP1F

PTMA0F

PTMP0F

PTMA1EPTMP1E

PTMA0E

PTMP0E

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

0

0

0

0

0

0

0

0

Bit 7

PTMA1F: PTM1 Comparator A match interrupt request flag
0: No request
1: Interrupt request

Bit 6

PTMP1F: PTM1 Comparator P match interrupt request flag
0: No request
1: Interrupt request

Bit 5

PTMA0F: PTM0 Comparator A match interrupt request flag
0: No request
1: Interrupt request

Bit 4

PTMP0F: PTM0 Comparator P match interrupt request flag
0: No request
1: Interrupt request

Bit 3

PTMA1E: PTM1 Comparator A match interrupt control
0: Disable
1: Enable

Bit 2

PTMP1E: PTM1 Comparator P match interrupt control
0: Disable
1: Enable

Bit 1

PTMA0E: PTM0 Comparator A match interrupt control
0: Disable
1: Enable

Bit 0

PTMP0E: PTM0 Comparator P match interrupt control
0: Disable
1: Enable

109

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM• MFI1 Register – HT66F003 only
Bit

7

6

5

4

3

2

1

0

Name

—

—

PTMA1F

PTMP1F——

PTMA1EPTMP1E

R/W

—

—

R/W

R/W

—

—

R/W

R/W

POR

—

—

0

0

—

—

0

0

Bit 7 ~ 6

Unimplemented, read as "0"

Bit 5

PTMA1F: PTM1 Comparator A match interrupt request flag
0: No request
1: Interrupt request

Bit 4

PTMP1F: PTM1 Comparator P match interrupt request flag
0: No request
1: Interrupt request

Bit 3 ~ 2

Unimplemented, read as "0"

Bit 1

PTMA1E: PTM1 Comparator A match interrupt control
0: Disable
1: Enable

Bit 0

PTMP1E: PTM1 Comparator P match interrupt control
0: Disable
1: Enable

Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A
match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether
the request flag actually generates a program jump to the relevant interrupt vector is determined by
the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to
its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actualinterrupt will not be generated and the program will not jump to the relevant interrupt vector. The
global interrupt enable bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller willthen fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a “JMP” which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a “RETI”, which retrieves the original Program Counter address fromthe stack and allows the microcontroller to continue with normal execution at the point where theinterrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in theaccompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit,
EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.

Rev. 2.30

110

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented frombecoming full. In case of simultaneous requests, the accompanying diagram shows the priority thatis applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
EMI auto disabled in ISR
LegendxxF

Request Flag, no auto reset in ISR

xxF

Request Flag, auto reset in ISR

xxE

Enable Bits

Interrupt
Name

Request
Flags

EnableBits

STM P

STMP0F

STMP0E

STM A

STMA0F

STMA0E

PTM P

PTMP1F

PTMP1E

PTM A

PTMA1F

PTMA1EInterrupt
Name

Request
Flags

EnableBits

MasterEnableVector

INT Pin

INTF

INTE

EMI

04H

Time Base 0

TB0F

TB0E

EMI

08H

Time Base 1

TB1F

TB1E

EMI

0CH

M. Funct. 0

MF0F

MF0E

EMI

10H

EEPROM

DEF

DEE

EMI

14H

A/D

ADF

ADE

EMI

18H

M. Funct. 1

MF1F

MF1E

EMI

1CH

PriorityHigh

Low

Interrupts contained within
Multi-Function Interrupts
HT66F003 onlyInterrupt Structure – HT66F002/HT66F0025/HT66F003
EMI auto disabled in ISR
LegendxxF

Request Flag, no auto reset in ISR

xxF

Request Flag, auto reset in ISR

xxE

Enable Bits

Interrupt
Name

Request
Flags

EnableBits

MasterEnableVector

INT0 Pin

INT0F

INT0E

EMI

04H

Time Base 0

TB0F

TB0E

EMI

08H

Time Base 1

TB1F

TB1E

EMI

0CH

Interrupt
Name

Request
Flags

EnableBits

PTM0 P

PTMP0F

PTMP0EPTM0 A

PTMA0F

PTMA0E

M. Funct. 0

MF0F

MF0E

EMI

10H

PTM1 P

PTMP1F

PTMP1E

EEPROM

DEF

DEE

EMI

14H

PTM1 A

PTMA1F

PTMA1E

A/D

ADF

ADE

EMI

18H

INT1 Pin

INT1F

INT1E

EMI

1CH

Interrupts contained within
Multi-Function Interrupts

PriorityHigh

Low

Interrupt Structure – HT66F004

Rev. 2.30

111

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
External Interrupts
The external interrupt is controlled by signal transitions on the pins INT and INT0~INT1. An
external interrupt request will take place when the external interrupt request flag, INTnF, is set,
which will occur when a transition, whose type is chosen by the edge select bits, appears on theexternal interrupt pin. To allow the program to branch to the interrupt vector address, the global
interrupt enable bit, EMI, and the external interrupt enable bit, INTnE, must first be set. Additionallythe correct interrupt edge type must be selected using the INTEG register to enable the externalinterrupt function and to choose the trigger edge type. As the external interrupt pins are pin-sharedwith I/O pins, they can only be configured as external interrupt pins by setting the pin-sharedregisters. The pin must also be setup as an input by setting the corresponding bit in the port control
register. When the interrupt is enabled, the stack is not full and the correct transition type appearson the external interrupt pin, a subroutine call to the external interrupt vector, will take place. Whenthe interrupt is serviced, the external interrupt request flag, INTnF, will be automatically reset
and the EMI bit will be automatically cleared to disable other interrupts. Note that the pull-highresistor selection on the external interrupt pin will remain valid even if the pin is used as an externalinterrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.

Multi-function Interrupts
Within these devices there are up to two Multi-function interrupts. Unlike the other independentinterrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM Interrupts.
A Multi-function interrupt request will take place when any of the Multi-function interrupt request
flags, MF0F~MF1F are set. The Multi-function interrupt flags will be set when any of their included
functions generate an interrupt request flag. To allow the program to branch to its respective interrupt
vector address, when the Multi-function interrupt is enabled and the stack is not full, and either oneof the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of
the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag, will be automatically reset and the EMI bit will be automatically cleared todisable other interrupts.
However, it must be noted that, although the Multi-function Interrupt flags will be automatically
reset when the interrupt is serviced, the request flags from the original source of the Multi-function
interrupts, namely the TM Interrupts, will not be automatically reset and must be manually reset by
the application program.

A/D Converter Interrupt
The devices contain an A/D converter which has its own independent interrupt. The A/D Converter
Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt
request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs
when the A/D conversion process finishes. To allow the program to branch to its interrupt vector
address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set.
When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, asubroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced,
the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be
automatically cleared to disable other interrupts.

Rev. 2.30

112

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Time Base Interrupts
The function of the Time Base Interrupts is to provide regular time signal in the form of an internalinterrupt. They are controlled by the overflow signals from their respective timer functions. Whenthese happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI
and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack
is not full and the Time Base overflows, a subroutine call to their respective vector locations willtake place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will
be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Theirclock sources originate from the internal clock source fTB. This fTB input clock passes through adivider, the division ratio of which is selected by programming the appropriate bits in the TBC
register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB,
which in turn controls the Time Base interrupt period, can originate from several different sources,
as shown in the System Operating Mode section.
• TBC Register
Bit

7

6

5

4

3

2

1

0

Name

TBON

TBCK

TB11

TB10

—

TB02

TB01

TB00

R/W

R/W

R/W

R/W

R/W

—

R/W

R/W

R/W

POR

0

0

1

1

—

1

1

1

Bit 7

TBON: TB0 and TB1 Control bit
0: Disable
1: Enable

Bit 6

TBCK: Select fTB Clock
0: fTBC
1: fSYS/4

Bit 5 ~ 4

TB11 ~ TB10: Select Time Base 1 Time-out Period
00: 4096/fTB
01: 8192/fTB
10: 16384/fTB
11: 32768/fTB

Bit 3

Unimplemented, read as "0"

Bit 2 ~ 0

TB02 ~ TB00: Select Time Base 0 Time-out Period
000: 256/fTB
001: 512/fTB
010: 1024/fTB
011: 2048/fTB
100: 4096/fTB
101: 8192/fTB
110: 16384/fTB
111: 32768/fTB      








  



                                      

  



Time Base Interrupt

Rev. 2.30

113

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
EEPROM Interrupt
An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit,
DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write
cycle ends, a subroutine call to the EEPROM Interrupt vector, will take place. When the EEPROM
Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, and the
EEPROM interrupt request flag, DEF, will also be automatically cleared.

TM Interrupts
The TMs each has two interrupts. All of the TM interrupts are contained within the Multi-function
Interrupts. For each of the TMs there are two interrupt request flags xTMPnF and xTMAnF and
two enable bits xTMPnE and xTMAnE. A TM interrupt request will take place when any of the
TM request flags are set, a situation which occurs when a TM comparator P or comparator A match
situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable
bit, MFnF, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator
match situation occurs, a subroutine call to the relevant TM Interrupt vector locations, will takeplace. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable otherinterrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.

Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low tohigh and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edgetransitions on the external interrupt pin, a low power supply voltage or comparator input change may
cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must
therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function
is to be disabled then the corresponding interrupt request flag should be set high before the device
enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up
function.

Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in theinterrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF1F, will
be automatically cleared, the individual request flag for the function needs to be cleared by theapplication program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will bedamaged once a CALL subroutine is executed in the interrupt subroutine.
Rev. 2.30

114

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it isrequired to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if thecontents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.

SCOM Function for LCD – HT66F004
The HT66F004 device has the capability of driving external LCD panels. The common pins for
LCD driving, SCOM0~SCOM3, are pin shared with certain pin on the I/O ports. The LCD signals
are generated using the application program.

LCD Peration
An external LCD panel can be driven using this device by configuring the I/O pins as common pins.
The LCD driver function is controlled using the SCOMC register which in addition to controllingthe overall on/off function also controls the bias voltage setup function. This enables the LCD COM
driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation.
The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. TheLCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function
selection bits. Note that the Port Control register does not need to first setup the pins as outputs toenable the LCD driver operation.
                                           

LCD COM BiasRev. 2.30

115

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
LCD Bias Current Control
The LCD COM driver enables a range of selections to be provided to suit the requirement of the
LCD panel which are being used. The bias resistor choice is implemented using the ISEL1 and
ISEL0 bits in the SCOMC register.
• SCOMC

Rev. 2.30

Bit

7

6

5

Name

—

ISEL1

ISEL0

4

3

2

1

0

R/W

—

R/W

R/W

R/W

R/W

R/W

R/W

R/W

POR

—

0

0

0

0

0

0

0

SCOMEN COM3EN COM2EN COM1EN COM0EN

Bit 7

Unimplemented, read as “0”Bit 6~5

ISEL1~ISEL0: Select resistor for R type LCD bias current(VDD=5V)
00: 2×100kΩ (1/2 Bias), IBIAS = 25μA
01: 2×50 kΩ (1/2 Bias), IBIAS = 50μA
10: 2×25 kΩ (1/2 Bias), IBIAS = 100μA
11: 2×12.5 kΩ (1/2 Bias), IBIAS = 200μA

Bit 4

SCOMEN: LCD control bit
0: Disable
1: Enable
When SCOMEN is set, it will turn on the DC path of resistor to generate 1/2 VDD bias voltage.

Bit 3

COM3EN: PB3/AN7 or SCOM3 selection
0: PB3/AN7
1: SCOM3

Bit 2

COM2EN: PB4/CLO or SCOM2 selection
0: PB4/CLO
1: SCOM2

Bit 1

COM1EN: PC1 or SCOM1 selection
0: PC1
1: SCOM1

Bit 0

COM0EN: PC0 or SCOM0 selection
0: PC01: SCOM0116

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Application Circuits
VDD
0.01µF**

1N4148*

VDD
10kΩ~
100kΩ

0.1µF
300Ω*

0.1µF~1µF

Reset
CircuitAN0~AN3
PA0~PA7RESVSSHT66F002/HT66F0025
VDD
0.01µF**

1N4148*

VDD
10kΩ~
100kΩ

0.1µF
300Ω*

0.1µF~1µF

Reset
CircuitAN0~AN3
PA0~PA7RES

PB0~PB5VSS
HT66F003
VDD
0.01µF**

1N4148*

VDD
10kΩ~
100kΩ

0.1µF
0.1µF~1µF

300Ω*

AN0~AN8
Reset
CircuitRES

PA0~PA7
PB0~PB6
PC0~PC2VSS
HT66F004

Note: "*" Recommended component for added ESD protection.
"**" Recommended component in environments where power line noise is significant.

Rev. 2.30

117

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set ofprogram instruction codes that directs the microcontroller to perform certain operations. In the caseof Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided toenable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.

Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,call, or table read instructions where two instruction cycles are required. One instruction cycle isequal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also takeone more cycle to implement. As instructions which change the contents of the PCL will imply adirect jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if noskip is involved then only one cycle is required.

Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.

Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature ofmost microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Caremust be taken to ensure correct handling of carry and borrow data when results exceed 255 foraddition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in thedestination specified.

Rev. 2.30

118

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of theoperation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.

Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which willcause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump backto the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, theprogram will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.

Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming whereindividual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].i"
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port withthe correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.

Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.

Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.

Rev. 2.30

119

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function andcan be consulted as a basic instruction reference using the following listed conventions.

Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic

Description

CyclesFlag Affected

Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory

1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note

Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C

Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC

1
1
1
1Note
1Note
1Note
1
1
1
1Note
1

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory

1
1Note
1
1Note

Z
Z
Z
Z

Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory leftRotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry

1
1Note
1
1Note
1
1Note
1
1Note

None
None
C
C
None
None
C
C

Arithmetic
ADD A,[m]ADDM A,[m]ADD A,x
ADC A,[m]ADCM A,[m]SUB A,x
SUB A,[m]SUBM A,[m]SBC A,[m]SBCM A,[m]DAA [m]Logic Operation
AND A,[m]OR A,[m]XOR A,[m]ANDM A,[m]ORM A,[m]XORM A,[m]AND A,x
OR A,xXOR A,x
CPL [m]
CPLA [m]Increment & Decrement
INCA [m]INC [m]DECA [m]DEC [m]RotateRRA [m]RR [m]RRCA [m]RRC [m]RLA [m]RL [m]RLCA [m]RLC [m]Rev. 2.30

120

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Mnemonic

Description

CyclesFlag AffectedMove Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC

1
1Note
1

None
None
None

Clear bit of Data Memory
Set bit of Data Memory

1Note
1Note

None
None

Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt

2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2

None
None
None
None
None
None
None
None
None
None
None
None
None

Read table (specific page or current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory

2Note
2Note

None
None

No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACCEnter power down mode

1
1Note
1Note
1
1Note
1
1

None
None
None
TO, PDF
None
None
TO, PDF

Data Move
MOV A,[m]MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch Operation
JMP addr
SZ [m]SZA [m]SZ [m].i
SNZ [m].i
SIZ [m]SDZ [m]SIZA [m]SDZA [m]CALL addr
RET
RET A,x
RETI

Table Read Operation
TABRD [m]TABRDL [m]Miscellaneous
NOP
CLR [m]SET [m]
CLR WDT
SWAP [m]SWAPA [m]HALT

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if noskip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

Rev. 2.30

121

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Instruction Definition
ADC A,[m]Description
Operation
Affected flag(s)ADCM A,[m]Description
Operation
Affected flag(s)ADD A,[m]Description

Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.

Operation
Affected flag(s)ACC ← ACC + [m]OV, Z, AC, C

ADD A,xDescription

Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added.
The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C

Operation
Affected flag(s)ADDM A,[m]Description
Operation
Affected flag(s)AND A,[m]Description
Operation
Affected flag(s)AND A,xDescription
Operation
Affected flag(s)ANDM A,[m]Description
Operation
Affected flag(s)Rev. 2.30

Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m]OV, Z, AC, C
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]Z
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND
operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]Z

122June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

Affected flag(s)Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter thenincrements by 1 to obtain the address of the next instruction which is then pushed onto thestack. The specified address is then loaded and the program continues execution from thisnew address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None

CLR [m]Description
Operation
Affected flag(s)Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00HNone

CLR [m].i
Description
Operation
Affected flag(s)Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0None

CLR WDT
Description
Operation

Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT clearedTO ← 0
PDF ← 0TO, PDFCALL addr
Description

Operation

Affected flag(s)CPL [m]Description
Operation
Affected flag(s)CPLA [m]Description
Operation
Affected flag(s)DAA [m]Description

Operation

Affected flag(s)Rev. 2.30

Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]Z
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]Z
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or[m] ← ACC + 06H or[m] ← ACC + 60H or[m] ← ACC + 66HC

123

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
DEC [m]Description
Operation
Affected flag(s)Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z

DECA [m]Description

Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
ZOperation
Affected flag(s)Affected flag(s)Enter power down modeThis instruction stops the program execution and turns off the system clock. The contents of
the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDFINC [m]Description
Operation
Affected flag(s)Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z

INCA [m]Description

Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z

HALTDescription
Operation

Operation
Affected flag(s)Operation
Affected flag(s)Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None

MOV A,[m]Description
Operation
Affected flag(s)Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]None

MOV A,xDescription
Operation
Affected flag(s)Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← xNone

MOV [m],A
Description
Operation
Affected flag(s)Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACCNone

JMP addr
Description

Rev. 2.30

124

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
NOP
Description
Operation
Affected flag(s)No operation
No operation is performed. Execution continues with the next instruction.
No operation
None

OR A,[m]Description

Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]Z

Operation
Affected flag(s)OR A,xDescription
Operation
Affected flag(s)ORM A,[m]Description
Operation
Affected flag(s)RETDescription
Operation
Affected flag(s)RET A,xDescription
Operation
Affected flag(s)RETI
Description

Operation
Affected flag(s)RL [m]
Description
Operation
Affected flag(s)Rev. 2.30

Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR
operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]Z
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified
immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the
RETI instruction is executed, the pending Interrupt routine will be processed before returning
to the main program.
Program Counter ← Stack
EMI ← 1
None
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)[m].0 ← [m].7
None

125

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
RLA [m]Description
Operation
Affected flag(s)RLC [m]Description
Operation
Affected flag(s)RLCA [m]Description
Operation
Affected flag(s)RR [m]
Description
Operation
Affected flag(s)RRA [m]Description
Operation
Affected flag(s)RRC [m]Description
Operation
Affected flag(s)Rev. 2.30

Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remainunchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)[m].0 ← C
C ← [m].7
C
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
Rotate Data Memory rightThe contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)[m].7 ← [m].0
None
Rotate Data Memory right with result in ACC
Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7.
The rotated result is stored in the Accumulator and the contents of the Data Memory remainunchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)[m].7 ← C
C ← [m].0
C

126

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROMRRCA [m]Description
Operation
Affected flag(s)SBC A,[m]Description

Operation
Affected flag(s)SBCM A,[m]Description

Operation
Affected flag(s)SDZ [m]Description

Operation
Affected flag(s)Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces
the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if theresult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if theresult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 thefollowing instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0None

Affected flag(s)Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, thefollowing instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0None

SET [m]Description
Operation
Affected flag(s)Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None

SET [m].i
Description
Operation
Affected flag(s)Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None

SDZA [m]Description

OperationRev. 2.30

127

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
SIZ [m]Description

Operation
Affected flag(s)SIZA [m]Description

Operation
Affected flag(s)SNZ [m].i
Description
Operation
Affected flag(s)SUB A,[m]Description
Operation
Affected flag(s)SUBM A,[m]Description
Operation
Affected flag(s)Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, thefollowing instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, thefollowing instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As thisrequires the insertion of a dummy instruction while the next instruction is fetched, it is a twocycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result isstored in the Accumulator. Note that if the result of subtraction is negative, the C flag will becleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]OV, Z, AC, C
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result isstored in the Data Memory. Note that if the result of subtraction is negative, the C flag will becleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]OV, Z, AC, C

Operation
Affected flag(s)Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator.
The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C

SWAP [m]Description
Operation
Affected flag(s)Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4None

SUB A,xDescription

Rev. 2.30

128

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
SWAPA [m]Description
Operation
Affected flag(s)SZ [m]
Description
Operation
Affected flag(s)SZA [m]Description

Operation
Affected flag(s)SZ [m].i
Description
Operation
Affected flag(s)TABRD [m]Description

Operation
Affected flag(s)TABRDL [m]Description
Operation
Affected flag(s)XOR A,[m]Description
Operation
Affected flag(s)Rev. 2.30

Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As thisrequires the insertion of a dummy instruction while the next instruction is fetched, it is a twocycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero,the following instruction is skipped. As this requires the insertion of a dummy instruction
while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
ACC ← [m]Skip if [m]=0
None
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Read table (specific page or current page) to TBLH and Data Memory
The low byte of the program code addressed by the table pointer (TBHP and TBLP or only
TBLP if no TBHP) is moved to the specified Data Memory and the high byte moved toTBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved
to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]Z

129

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
XORM A,[m]Description
Operation
Affected flag(s)XOR A,xDescription
Operation
Affected flag(s)Rev. 2.30

Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]Z
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z

130

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Package Information
Note that the package information provided here is for consultation purposes only. As thisinformation may be updated at regular intervals users are reminded to consult the Holtek website forthe latest version of the Package/Carton Information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Package Information (include Outline Dimensions, Product Tape and Reel Specifications)• The Operation Instruction of Packing Materials• Carton informationRev. 2.30

131

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
8-pin SOP (150mil) Outline Dimensions













 







SymbolDimensions in inch
Min.

Nom.

Max.

A

—

0.236 BSC—

B—

0.154 BSC

—
0.020

C

0.012

—

C’

—

0.193 BSC

—

D

—

—

0.069

E

—

0.050 BSC

—

F

0.004

—

0.010

G

0.016

—

0.050

H

0.004

—

0.010

α

0°

—

8°

SymbolA

Rev. 2.30



Dimensions in mm
Min.

Nom.

Max.

—

6.00 BSC—

B—

3.90 BSC

—

C

0.31

—

0.51

C’

—

4.90 BSC

—

D

—

—

1.75

E

—

1.27 BSC

—

F

0.10

—

0.25

G

0.40

—

1.27

H

0.10

—

0.25

α

0°

—

8°

132

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
10-pin SOP (150mil) Outline Dimensions



 










 







SymbolA

Dimensions in inch
Min.

Nom.

Max.

—

0.236 BSC—

B—

0.154 BSC

—

C

0.012

—

0.018

C′

—

0.193 BSC

—

D

—

—

0.069

E

—

0.039 BSC

—

F

0.004

—

0.010

G

0.016

—

0.050

H

0.004

—

0.010

α

0°

—

8°

SymbolRev. 2.30



Dimensions in mm
Min.

Nom.

Max.

A

—F

6.00 BSC—

B—

3.90 BSC

—
0.45

C

0.30

—

C′

—

4.90 BSC

—

D

—

—

1.75

E

—

1.00 BSC

—

F

0.10

—

0.25

G

0.40

—

1.27

H

0.10

—

0.25

α

0°

—

8°

133

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
10-pin MSOP Outline Dimensions
 

 



 





   

 



 



        

Symbol

Min.

Nom.

Max.

A

—

—

0.043

A1

0.000

—

0.006

A2

0.030

0.033

0.037

B

0.007

—

0.013

C

0.003

—

0.009

D

—

0.118 BSC—

E—

0.193 BSC

—

E1

—

0.118 BSC—e—

0.020 BSC

—

L

0.016

0.024

0.031

L1

—

0.037 BSC

—

y

—

0.004

—

θ

0°

—

8°

SymbolRev. 2.30

Dimensions in inch

Dimensions in mm
Min.

Nom.

Max.

A

—

—

1.10

A1

0.00

—

0.15

A2

0.75

0.85

0.95

B

0.17

—

0.33

C

0.08

—

0.23

D

—

3.0 BSC—E—

4.9 BSC—

E1—

3.0 BSC—e—

0.5 BSC

—

L

0.40

0.60

0.80

L1

—

0.95 BSC

—

y

—

0.1

—

θ

0°

—

8°

134

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
16-pin NSOP (150mil) Outline Dimensions



 








 





SymbolDimensions in inch
Min.

Nom.

Max.

A

—

0.236 BSC—

B—

0.154 BSC

—

C

0.012

—

0.020

C’

—

0.390 BSC

—

D

—

—

0.069

E

—

0.050 BSC

—

F

0.004

—

0.010

G

0.016

—

0.050

H

0.004

—

0.010

α

0°

—

8°

SymbolRev. 2.30



Dimensions in mm
Min.

Nom.

Max.

A

—

6.0 BSC—B—

3.9 BSC

—

C

0.31

—

0.51

C’

—

9.9 BSC

—

D

—

—

1.75

E

—

1.27 BSC

—

F

0.10

—

0.25

G

0.40

—

1.27

H

0.10

—

0.25

α

0°

—

8°

135

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
20-pin SOP (300mil) Outline Dimensions
 

 






 

 






SymbolDimensions in inch
Min.

Nom.

Max.

A

—

0.406 BSC—

B—

0.406 BSC

—

C

0.012

—

0.020

C’

—

0.504 BSC

—

D

—

—

0.104

E

—

0.050 BSC

—

F

0.004

—

0.012

G

0.016

—

0.050

H

0.008

—

0.013

α

0°

—

8°

SymbolRev. 2.30



Dimensions in mm
Min.

Nom.

Max.

A

—

10.30 BSC—

B—

7.50 BSC—

C—

7.50 BSC—

C’—

12.80 BSC—

D—

12.80 BSC—

E—

1.27 BSC

—

F

0.10

—

0.30

G

0.40

—

1.27

H

0.40

—

1.27

α

0°

—

8°

136

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
20-pin SSOP (150mil) Outline Dimensions
 

 






 

 






SymbolDimensions in inch
Min.

Nom.

Max.
—

A

—

0.236 BSC

B—

0.155 BSC

—

C

0.008

—

0.012

C’

—

0.341 BSC

—

D

—

—

0.069

E

—

0.025 BSC

—

F

0.004

—

0.0098

G

0.016

—

0.05

H

0.004

—

0.01

α

0°

―

8°

SymbolRev. 2.30



Dimensions in mm
Min.

Nom.

Max.

A

—

6.00 BSC—

B—

3.90 BSC

—

C

0.20

—

0.30

C‘

—

8.66 BSC

—

D

—

—

1.75

E

—

0.635 BSC

—

F

0.10

—

0.25

G

0.41

—

1.27

H

0.10

—

0.25

α

0°

―

8°

137

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
20-pin NSOP (150mil) Outline Dimensions
 

 






 

 






SymbolDimensions in inch
Min.

Nom.

Max.

A

0.228

0.236

0.244

B

0.146

0.154

0.161

C

0.009

—

0.012

C’

0.382

0.390

0.398

D

—

—

0.069

E

—

0.032 BSC

—

F

0.002

—

0.009

G

0.020

—

0.031

H

0.008

—

0.010

α

0°

—

8°

SymbolRev. 2.30



Dimensions in mm
Min.

Nom.

Max.

A

5.80

6.00

6.20

B

3.70

3.90

4.10

C

0.23

—

0.30

C’

9.70

9.90

10.10

D

—

—

1.75

E

—

0.80 BSC

—

F

0.05

—

0.23

G

0.50

—

0.80

H

0.21

—

0.25

α

0°

—

8°

138

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
24-pin SSOP (150mil) Outline Dimensions
 

 





 


 






SymbolDimensions in inch
Min.

Nom.

Max.
—

A

—

0.236 BSC

B—

0.154 BSC

—

C

0.008

—

0.012

C’

—

0.341 BSC

—

D

—

—

0.069

E

—

0.025 BSC

—

F

0.004

—

0.010

G

0.016

—

0.050

H

0.004

—

0.010

α

0°

—

8°

SymbolRev. 2.30



Dimensions in mm
Min.

Nom.

Max.
—

A

—

6.000 BSC

B—

3.900 BSC

—

C

0.20

—

0.30

C’

—

8.660 BSC

—

D

—

—

1.75

E

—

0.635 BSC

—

F

0.10

—

0.25

G

0.41

—

1.27

H

0.10

—

0.25

α

0°

—

8°

139

June 23, 2021

HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM

Copyright© 2021 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the timeof publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation thatsuch applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due tomalfunction or otherwise. Holtek's products are not authorized for use as criticalcomponents in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.

Rev. 2.30

140

June 23, 2021