Development of DC to Single-phase AC Voltage
Source Inverter with Active Power Decoupling
Based on Flying Capacitor DC/DC Converter
Hiroki Watanabe, Student Member, Tomokazu Sakuraba, Student Member, Keita Furukawa, Student Member IEEE,
Keisuke Kusaka, Member, IEEE, and Jun-ichi Itoh, Senior Member, IEEE
Abstract—In the present, an power decoupling method
without additional component is proposed for a DC to Singlephase AC converter, which consists of a flying capacitor DC/DC
converter (FCC) and the voltage source inverter (VSI). In
particular, a small flying capacitor in the FCC is used for both aboost operation and a double-line-frequency power ripple
reduction. Thus, the DC link capacitor value can be minimized inorder to avoid the use of a large electrolytic capacitor. In addition,
component design, of e.g., the boost inductor and the flying
capacitor, is clarified when the proposed control is applied.
Experiments were carried out using a 1.5-kW prototype in orderto verify the validity of the proposed control. The experimental
results revealed that the use of the proposed control reduced theDC link voltage ripple by 74.5%, and the total harmonic
distortion (THD) of the inverter output current was less than 5%.
Moreover, a maximum system efficiency of 95.4% was achieved
at a load of 1.1 kW. Finally, the high power density design isevaluated by the Pareto front optimization. The power densitiesof three power decoupling topologies, such as a boost topology, abuck topology, and the proposed topology are compared. As aresult, the proposed topology achieves the highest power density(5.3kW/dm3) among the topologies considered herein.

clamped converters (NPCs) or flying-capacitor DC/DC
converters (FCCs), have been used in two-stage power
conversion due to advantages such as high efficiency and highpower density. These advantages are obtained by using a low
on-resistance switching power device owing to the use of lowvoltage-rating devices in the multi-level topology. Meanwhile,the inductor volume can also be minimized because theharmonic components of the inductor voltage can be reduced.
In the FCC converter topology, the switched capacitor
converter (SCC) is the popular configuration [2]-[3]. SCC canachieve the boost-up operation without large inductor.
However, the inrush current on DC side occurs due to theflying capacitor. In order to solve this problem, the SCC withthe small inductor is considered in [4]. The SCC with small
inductor can reduce the inrush current in comparison with theconventional SCC. In addition, a high boost ratio can beachieved by small inductor and flying capacitor.
On the other hand, double-line-frequency power ripple
occurs in the DC side due to the single-phase AC grid. Thispower ripple leads to a decrease in a performance of theIndex Terms—Photovoltaic system (PV), Flying capacitor maximum power point tracking (MPPT). Therefore, a bulky
DC/DC converter, Active power decoupling, Power density electrolytic capacitor is usually required in the DC link indesign.
order to absorb the power ripple: i.e., a passive power
decoupling method is used. However, the electrolytic
I. INTRODUCTION
capacitor limits the life-time of the power converter according
N recent years, photovoltaic (PV) systems have been to the Arrhenius law.
actively researched as a sustainable power solution. As a
In order to solve this problem, active power decoupling
result, the world global market installation reached a record methods have been energetically studied [5-15]. The active
high of 277 GW in 2015 [1]. In order to use the generated power decoupling is realized through the addition of switching
power by PV panels, power converter systems (PCSs) are used devices and small passive energy buffer. Active power
to connect the PV system to the single-phase AC grid. These decoupling methods can reduce the capacitance required for
PCSs require the following capabilities: (1) high efficiency power ripple compensation, which enables the use of film
power conversion, (2) “plug and play” operation, (3) capacitors or ceramic capacitors instead of an electrolytic
maintenance free, and (4) small packaging design.
capacitor. Generally, the active power decoupling technique
In order to fulfill these capabilities, two-stage power can be categorized into two types: the power decoupling
conversion using a DC/DC converter and a voltage source technique based on parallel connection and series connection,
inverter (VSI) is generally used due to its simple configuration. where an auxiliary power decoupling circuit is connected toFurthermore, multi-level converters, such as neutral point the DC link or AC side. A topological review of these power
decoupling technique has been presented in [16]. In [16], these
Manuscript received March 21, 2017; revised May 1, 2017; accepted June
conventional techniques can reduce the capacitance for power
28, 2017.
decoupling. However, it is also reported the active power
Hiroki Watanabe, Tomokazu Sakuraba, Keita Fulukawa, Keisuke Kusaka
and Jun-ichi Itoh are with the Dept. Electrical Electronics and Information, decoupling methods based on series or parallel connection
Nagaoka University of Technology, Niigata 940-2188, Japan (e-mail:worsens the converter efficiency due to the loss from thehwatanabe@stn.nagaokaut.ac.jp;t_sakuraba@stn.nagaokaut.ac.jp;archer_FK
additional component [17]. Therefore, achievement of active@stn.nagaokaut.ac.jp;kusaka@vos.nagaokaut.ac.jp;itoh@vos.nagaokaut.ac.jp

I).

Largeinductor

iout
Cdc +

Iin

vac

Ldc
Vin

Large electrolytic
Boostcapacitor
converter
Fig. 1. DC to single-phase AC grid connected converter with typical boost
converter.

Vin

vac

DC/AC

DC/DC

Active power
decoupling(a) Parallel-connected topology

Cdc
Ldc

Cbuf

DC/DC

DC/AC

AC sideVin

DC link

Power decoupling cir.
(b) Conventional power decoupling
circuit in parallel connection

DC sidepower decoupling capability without the need for an additional
component is a key technique in realizing high efficiency andhigh power density [18].
This paper proposes a novel active power decoupling
method based on the FCC. The original contribution of thepresent paper is that active power decoupling control isachieved using a typical DC/DC converter without any
additional components in order to reduce the volume, cost, andconverter loss. In the paper, a multi-level DC/DC converter
that has capacitive storage is focused. Originally, the FCC has
a small flying capacitor in order to achieve a high boost ratio.
The proposed control uses this capacitor for both boost
operationanddouble-line-frequency
power
ripplecompensation, i.e., active power decoupling. As a result, theDC link capacitor value can be minimized. In addition, theadvantages of the multi-level converter remain. Thus, theconduction losses and the inductor volume are reduced incomparison with the typical boost converter. However, theactive power decoupling control decays the PV input current
control performance because the voltage fluctuation of theflying capacitor disturbs the input current control. Therefore,
this disturbance is compensated by the proposed input current
control.
The remainder of the paper is organized as follows. In
section II, the configuration of the proposed converter is
explained. In section III, the proposed active power
decoupling control is described. In section IV, the component
design of the proposed converter is explained, and thefundamental operation is then demonstrated experimentally. In
this section, high efficiency design is discussed based onconverter loss analysis. In section V, the high power density
condition is evaluated with the Pareto front optimization when
the switching frequency is changed.

vac

II. CIRCUIT CONFIGURATION
A. Two-stage DC to Single-phase AC grid connected
converter with typical boost converter.
Fig. 1 shows the DC to single-phase AC grid-connected
converter with a typical boost converter. The boost converter
boosts the PV input voltage above the peak value of the gridvoltage, and the generated power is supplied to the singlephase grid by the VSI. In this case, a bulky electrolytic
capacitor Cdc is required in the DC link due to the double-linefrequency power ripple of the single-phase grid. In addition, alarge DC inductor Ldc is used for the boost operation of the PV
input voltage Vin. In addition, the electrolytic capacitor limits
the life-time of converter.
B. Electrolytic capacitor less converter with active power
decoupling circuit.
Fig. 2 shows the active power decoupling configuration for
the electrolytic capacitor-less converter and the conventional
active power decoupling topologies considered herein [19-22].
Topologies can be categorized into two basic types, parallelconnected topologies and series-connected topologies asshown in Fig.2 (a), (b) and 2 (c), respectively. In particular,
the active power decoupling circuit is implemented in series orActive power
decoupling(c) Series-connected topology

Vin

DC/DC

DC/AC

vac

Including active power decoupling
capability(d) Proposed approach
Fig. 2. Active power decoupling approaches.

in parallel from the main power path. Consequently, the DC
link capacitance is drastically reduced, and a small film or
ceramic capacitor can be used instead of the bulky electrolytic
capacitor. However, the additional component increases theconverter loss. In addition, the circuit configuration becomescomplex as shown in Fig.2 (b), and the control for the
additional circuit must be modified for each conventional

topology in order to achieve active power decoupling. In orderto solve these problems, an approach in which the active
power decoupling capability is implemented through the
DC/DC converter is proposed, as shown in Fig. 2 (d).
C. Proposed active power decoupling scheme for DC/AC
conversion.
Fig. 3 describes the DC to single-phase AC grid-connected
converter with the FCC, which is used in the proposed active
power decoupling. In the proposed method, the small flying
capacitor Cfc is used for both the boost operation of the PV
input voltage Vin and the active power decoupling. The FCC
has many advantages compared to the typical boost converter.
First, the low voltage rating devices, which have low onresistance, can be used because the drain-source voltage ofeach MOSFET can be reduced due to the increase in thenumber of levels, i.e., the characteristic of the multi-level
topology. Therefore, low conduction loss can be achieved. In
addition, the volume of the boost inductor Lfc is small
compared to that of the typical boost converter. In the typicalboost converter, the inductor voltage alternates between zerovoltage and the DC link voltage. On the other hand, themaximum inductor voltage of FCC converter can be reducedin comparison with typical boost converter because theinductor voltage is clamped to the flying capacitor voltage andthe difference value between the DC link voltage and theflying capacitor voltage. In other words, in the typical boost
converter, the boost operation is achieved by only the boost
inductor whereas in the FCC converters (even when the
proposed method is applied) the boost operation is achieved
by both the boost inductor and the flying capacitor. As a result,the inductor current ripple in the FCC converters becomes low
in comparison with the typical boost converter. Therefore, theinductance in the FCC converters can be minimized comparedwith the typical boost converter.
In the conventional control for the FCC, the flying
capacitor voltage is maintained constant at the half of the DC
link voltage. In this paper, this flying capacitor voltage isfluctuated in order to realize active power decoupling.
Consequently, when active power decoupling is achieved by
the FCC, the DC link capacitance can be reduced, and thebulky electrolytic capacitor is not required. The contributionof the proposed converter has a simple configuration andrequires no additional components.
Note that, the decrease in the converter efficiency is an
important technical issue in active power decoupling methods.
The proposed active power decoupling approach has thepotential to achieve low efficiency degradation as compared toconventional active power decoupling topologies. On the other
hand, in the paper, a two-level VSI is used for grid connection.
In order to achieve high efficiency and to reduce the use of thegrid connected inductor, a multi-level inverter topology canalso be used. In this paper, only the FCC is focused.
III. CONTROL STRATEGY OF PROPOSED CONVERTER
A. Principle of active power decoupling
Fig. 4 shows the principle of power ripple compensation by

iac
Lfc

Iin

Cfc

Cdc

Lac
vac

Vin
Small
capacitor

Flying capacitor DC/DC converter(active power decoupling circuit)

Fig. 3. DC to single-phase AC grid connected converter with FCC. The
proposed active power decoupling approach does not require additional
component.
Vin / Iinvac / iac

vfc / ifc

vave

Iin

ifc
t

0

vac

vfc

Vin

Vacp
Iacp

0

0

iac
Pbuf_fc

Pin

pout
Charget0

PV input powert0Discharge
Flying capacitor
DC/DC conv.

t

0

V I
pout  acp acp (1  cos2t )2Single-phase
AC grid

Fig. 4. Principle of the active power decoupling. Buffer power Pbuf_fc ischarge and discharge by the flying capacitor Cfc. The Pbuf_fc is given by themismatch in instantaneous power between input power Pin and output
power Pout.

fluctuating the flying capacitor voltage. When both the output
voltage and current waveforms are sinusoidal, theinstantaneous output power pout is expressed as
pout 

Vacp I acp
2(1  cos 2t ) 





where, Vacp is the peak voltage, Iacp is the peak current, and 
is the angular frequency of the output voltage [23]. As shownin (1), the power ripple at twice the frequency of the singlephase power grid appears at the DC link.
In order to absorb this power fluctuation, the instantaneous
buffer power pbuf should be controlled by1
pbuf  Vacp I acp cos 2t 
2





where, the polarity of pbuf is defined as positive when the
flying capacitor Cfc discharges. Note that the active power of
Cfc is zero. As a result of the power decoupling, the input
power is matched to the output power. Thus, the relationshipbetween the input and output power is expressed as follows:1
pin  Vacp I acp  VIN I IN 
2





Pbuf_fc

S1

0

Fig. 5 shows the operation modes of the FCC. The
proposed converter is operated in two modes. In mode 1, theflying capacitor Cfc is discharged to the single-phase grid,whereas, in mode 2, the flying capacitor Cfc is charged. Eachmode is switched at twice the grid frequency. Through thesemodes, the flying capacitor voltage is fluctuated at twice thegrid frequency in order to compensate the mismatch power
between the PV side and the single-phase grid, and tomaintain a constant PV input power.

Cfc : Discharge
Lfcv in  v conv

v fc



Vdc

(a) Discharge mode (mode 1)
Pbuf_fc
0

S2
Cfc : Charge
Lfc
Iin

Cfc

Vconv

Vin

Vfc

Vdc

S4


(b) Charge mode (mode 2)
Fig. 5. Operation mode of the flying capacitor DC/DC converter forachieving active power decoupling.

where, vin is the PV input voltage, vconv is the terminal voltage,
vfc is the flying capacitor voltage, and vdc is the DC link
voltage. Conventionally, vfc is constant, and is clamped to vdc/2. Thus, the duty references in (4) and (5) become equal toeach other, and each switching mode, as shown in Fig. 5, isemployed equally. On the other hand, the proposed control
fluctuates the flying capacitor voltage in order to achieve thepower decoupling. As a result, the duty reference of thedischarge mode (mode 2) is different than that without thepower decoupling.
In addition, in the flying capacitor voltage control, theflying capacitor voltage vfc is fluctuated at twice the gridfrequency in order to compensate the single-phase powerfluctuation. The voltage reference vfc* is expressed as

Flying capacitor DC/DC converter
controlInput current control
vin
(ACR)
v
conv ++
iin*PI

vdc-vfc

iin

d1 +
+
d2 +

Di

+
vfc

+
PI

+

d1_with_buffer
d2_with_buffer

S3

0
1

dbuf

dc

S4

-vfc
vdc-vfc

Carrier(180˚shifted)

Flying capacitor voltage control

Proposed power(AVR)

decoupling control

vdc

S2

+
-

0

vfc

+

S1

+
-

1

+
vfc*

vdc*

VSI controld2 v in  v conv
v dc  v fc

Vfc

S3

Vin

B. Control block diagram of proposed converter
Fig. 6 shows the control block diagram of the FCC and the
VSI. In the proposed control, an automatic current regulator(ACR) and an automatic voltage regulator (AVR) are
implemented in order to control the generated power, and theactive power decoupling.
First, the duty references for the input current control are
expressed as

d1 

Cfc

Iin Vconv

iac*

PI
vac

Sin
PLL



+
iac

+
-

PI

Sup
Sun

vdc
Svp

1

DC link voltage control Inverter output current control -1
(AVR)
(ACR)

Carrier

Svn

Fig. 6. Control block diagram of proposed converter.
2

v
pout 
pv *fc   dc  out sin2t   1 
 2 C V  C
fc dc power decoupling duty reference given by the flying capacitor voltage control is added to the input current duty reference.
Fig. 7 shows the operation mode when the boost ratio is
more than two. In this case, the FCC has three modes. Fig. 8
where, pout is the output power, and  is the angular frequency shows the switching state on each operation mode both withof the single-phase grid voltage. Following (6), the flying and without power decoupling. Note that, the duty reference d
1
capacitor voltage includes the second-order harmonics of the is the duty ratio of the discharge mode (Mode II), the duty
single-phase grid frequency, and the voltage amplitude value reference d is the duty ratio of the charge mode (Mode IV),2
is inversely proportional to the flying capacitor value Cfc. In the other state is defined the inductor charge mode (Mode I,other words, when the flying capacitor voltage is fluctuated III, V)
largely, Cfc can be minimized.
First, the inductor voltage VL is expressed as
In order to ensure the stability between the input current
control and the flying capacitor voltage control, it is necessary V  V  V 


L
in
conv
to consider the non-linearity of the duty reference because the

d1

d1
S1

S1

S2

S2

S2

Vfc
Iin

Vdc

Vfc

S3
Vin

Vin

Vconv

Vdc

Iin
S3

Vin

Vfc

Vdc

Iin

S3

S1
Switching pulse

S1

ON

ON

S2

II
i) Capacitor discharge modeIVii) Capacitor charge mode

I

OFF

S4

S4
III

Mode IV

Fig. 7. Operation mode of FCC.

where, Vconv is the voltage across S3 and S4. Generally, theflying capacitor voltage is clamped to half of the DC link
voltage Vdc. In state II, Vconv equals to the difference value
between the DC link voltage and the flying capacitor voltage.
In state IV, Vconv equals to the flying capacitor voltage. Finally,in the state I, III, V, the inductor voltage equals to the input
voltage.
According to these conditions, when the active power
decoupling is not applied, Vconv is expressed as

II

III

S3

S4
IV

V

Without power decouplingiii) Inductor charge mode

d2+dbuf

S2
OFF

S3

S4
S4

S1

d2

I

II

III

IV

V

With power decoupling

Fig. 8. Switching state of the FCC.

d c (vdc  v fc )  v fc d buf 
dc  

v fc
d buf vdc  v fc









The proposed converter is operated by the typical PWM,
which means that the switching frequency is constant. The
controller operation is synchronized with the sampling
frequency and the control performance depends on the design
Vdc
Vdc
Vconv  d1
 d2
 dVdc   of PI controller. The flying capacitor voltage control is based22
on the input current control, which adjusts the duty for active
On the other hand, when the power decoupling is applied, d2 power decoupling. However, when the input current has
depends on the power decoupling control because the flying negative or zero periods, the flying capacitor cannot charge.
It means the flying capacitor voltage cannot control in thesecapacitor should be charged by the double-line frequency asmodes. Thus, the proposed converter has to be always
shown in Fig. 4 (b). In addition, the flying capacitor voltage
operated in continuous current mode. In addition, the overfluctuates around the half value of the DC link voltage due tomodulation limits the flying capacitor control because thethe power decoupling control. Following these reasons, when duty reference from the power decoupling control is added tothe active power decoupling is applied, Vconv_with_buffer is the input current control.
expressed as
When the MPPT is implemented, the input current
reference iin* is decided from the maximum power point. For
Vconv _ with _ buffer  d 1 Vdc  V fc   d 2  d buf V fc  dVdc  d buf V fc  example, when the Perturbation and Observation (P&O)
method is applied, the input power is calculated from thewhere, dbud is the duty ratio of the power decoupling mode. detected values of the input voltage and the input current.
Comparing (8) and (9), Vconv does not match, and dbud behaves When the value of the input power at the previous sampling*
as a disturbance to the input current control. Consequently, the period is less than the value, the input current reference iin is
increased.
On
the
other
hand,
when
the
previous
value
of
the
input current is fluctuated at the double-line frequency.
sampling period is higher thanIn order to obtain the constant input current, the input power at the previous*
thepresent
value,iin is decreased. On the other words, thedisturbance compensation is considered. In order tocompensate the disturbance introduced by the power typical MPPT control can be simply applied into the
proposed control.
decoupling, Vconv has to be matched in both case with orOn the AC side, the DC link voltage control and the inverter
without power decoupling. Thus, the disturbanceoutput current control are implemented in the VSI control. The
compensation duty dc is added to d1. In this case, Vconv_with_buffer
DC link voltage is regulated to be higher than the single-phaseis expressed as
peak grid voltage Vacp, and the inverter output current is
controlled to sinusoidal waveforms. Note that, the phase
Vconv _ with _ buffer  d1  d c Vdc  V fc   d 2  d buf V fc
 reference is given by the grid voltage vac and the phased
looked loop (PLL). As a result, the power factor becomes dVdc  d c Vdc  V fc   d buf V fc
unity.
According to (10), when the second and three terms
become zero, Vconv is matched in both equations (8) and (10).
Thus, dc is decided from (10), and it is expressed as

IV. COMPONENT DESIGNA. Flying capacitor Cfc
The flying capacitor Cfc is designed from the buffer energy (Vc max  Vc min )
2

2







where, Vcmax is the maximum value of the flying capacitor
voltage, Vcmin is the minimum value of the flying capacitor
voltage, and  is the angular frequency of the single-phasegrid. In the proposed FCC converter, the flying capacitor
becomes large in comparison with typical FCC converter
because the flying capacitor is utilized for both the boost-up
operation and the power decoupling. In order to reduce Cfc,
the voltage amplitude of the flying capacitor voltage should
be designed to be high.
Fig. 9 shows the relationship between the flying capacitor
fluctuation voltage and the flying capacitor with 1 kW. For
example, when the fluctuation voltage is set to 87 V, the flying
capacitor is reduced to 100 F. However, the over modulation
limits the flying capacitor control as explained in section III.
In the future work, the limitation of the proposed control will
be considered for optimization.
B. Boost inductor Lfc
The boost inductor Lfc is designed based on the current
ripple DiLfc of the inductor current. When the active power
decoupling is not applied, the flying capacitor voltage isclamped to the half of the DC link voltage. On the other hand,the proposed control fluctuates the flying capacitor voltage attwice the grid frequency. As a result, the inductor voltage issimilar to that without the active power decoupling. Thus, theboost-up inductor design of the proposed converter isconsidered from the maximum inductor ripple condition.
First, Lfc is designed from the inductor voltage and thecurrent ripple, and expressed as
L fc  VL
4 f sw DI





Flying capacitor [F]

C fc 

2Wbuffer

180
140
100
60
20
45

65

85
105
125
145
165
Flying capacitor fluctuation voltage [V]185

Fig. 9. Relationship between flying capacitor fluctuation voltage andflying capacitor.
Design value
1.0

Inductance Lfc

Wbuffer, which is the electric storage energy compensating thepower fluctuation. Then, Cfc is expressed asSim. value

Boost-up rate : 5

0.8
0.6
0.4
Boost-up rate : 2.5

0.2
0.0

fsw : 16 kHz
DI : 2.1 A
Vdc : 380 V
Lchopper : 1.8 mH

0.2
0.1
0.3
0.4
Flying capacitor fluctuation voltage DVfc

0.5

Fig. 10. Relationship between boost inductor value and ripple voltage offlying capacitor Cfc.

d 2 _ with _ buffer Vin   Vdc
 1 cos(2t ) 
1  

Vdc   v fc





where, d1_with_buffer and d2_with_buffer include the frequency
component, which is dependent on the power decoupling duty
dbuf and the control decoupling reference dc. Using (15) and(16), the boost inductor of the proposed circuit is expressed as

L fc 

max(vdc  v fc  vin )d1 _ with _ buffer , (v fc  vin )d 2 _ with _ buffer 
f sw DI Lfc

 

Fig. 10 shows the relationship between the boost inductor
value and the ripple voltage of the flying capacitor in the FCC.
where,  is the duty ratio, VL is the inductor voltage, fsw is the The switching frequency fsw is 16 kHz, and the DC linkswitching frequency, and DI is the ripple ratio of the inductor voltage Vdc is 380 V. The ripple current DILfc is 2.1 A, and thecurrent. In comparison with the typical boost converter, the inductance of the typical boost converter is 1.8 mH. Note that,inductance of the FCC can be reduced to one quarter because the inductance of the typical boost converter is constant withthe ripple current frequency becomes the twice the switching respect to the ripple voltage of the flying capacitor. In order tofrequency, and the voltage applied to the inductor VLfc is only consider the validity of the inductor design equation (17), thehalf the DC link voltage Vdc because of the flying capacitor design value and the simulation results are compared. In
voltage Vfc. However, in the proposed circuit, the duty ratio addition, the boost-up rate is changed from 2.5 to 5. The boost
and VL are continuously changed due to the power decoupling inductor value Lfc in the FCC is normalized by the inductancecontrol. Thus, the boost inductor of the proposed circuit is of the typical boost converter Lchopper. As shown in Fig. 9, thedesigned based on duty references d1_with_buffer and d2_with_buffer.
simulation results agree with the design values, thereby
In the proposed control, the duty references d1_with_buffer and confirming the validity of the boost inductor design. In
d2_with_buffer are expressed asaddition, the inductance ratio is less than 1p.u. for all
conditions, which implies that the inductance of the FCC isVin1  cos(2t ) 
d 1 _ with _ buffer  smaller than that of the typical boost converter.
Vdc
V. POWER DENSITY COMPARISON WITH PARETO OPTIMIZATIONIn this section, the design method for achieving high power
density and high efficiency in the DC to single-phase AC gridconnected system is discussed. In particular, several active
power decoupling topologies are compared in the terms of thepower density [24-25].
Fig. 11 shows the three topologies considered in thispaper, : the proposed active power decoupling, conventional
boost type active power decoupling, and conventional bucktype active power decoupling. In order to achieve high power
density and higher efficiency, the design flows for the active
power decoupling using the ceramic capacitor are introduced.
Then, from the design flowchart and the specifications ofcommercially-available products, the power density andefficiency of the active power decoupling circuit are evaluatedby Pareto optimization. Finally, the total loss and a total
volume at the maximum power density are compared.
A. Conventional boost-type power decoupling design
As shown in Fig. 11 (b), conventional boost type active
power decoupling uses a typical boost converter and a buffer
capacitor Cbuf to absorb the power ripple in the DC link.
Fig. 12 shows the design flowchart for optimizing thedesign of the boost type active power decoupling. First, thecapacitance of the buffer capacitor is calculated based on the
average voltage and the voltage fluctuation range of the buffer
capacitor. Then, the capacitor volume VolCbuf is determinedusing commercially-available products. The switching device
is decided based on the maximum voltage of the buffer
capacitor. In this paper, a switching device having a rating
voltage of 1200 V is used. The boost inductor is designed
based on the switching frequency fsw and the inductor ripple
current. The volume of the boost inductor is estimatedaccording to the area product method [26]. The heatsinkvolume is then calculated from the thermal resistance, which
depends on the conduction loss Ploss_cond and the switching loss
Ploss_sw of the switching devices. Finally, the Pareto
optimization is obtained by varying the switching frequency inorder to obtain the maximum power density point.
The buffer capacitor Cbuf is decided based on therelationship between the storage energy and the capacitor
voltage and can be designed in a manner similar to that used todesign the proposed FCC, as expressed in (13). When thebuffer capacitor amplitude voltage DVC_buf is increased, aswitching device with a high rating voltage is required. Thus,a switching device, which has the rating voltage of 1200 V is
selected because the peak capacitor voltage is 800V.
The buffer inductor is designed based on the allowable
ripple current DILf. The inductance becomes the maximum
value when the difference between the DC link voltage andthe buffer capacitor voltage reaches the maximum. Thus, theinductance of the buffer inductor is obtained as
ΔVc Vave   VdcVdc 2 Lbuf 
ΔVc
ΔiL f sw
Vave 
2

Iin

iac

Lfc

Cfc

Lac
Cac

Cdc

vac

Vin

Proposed active power
decoupling(a) Proposed active power decoupling

Sp

Vdc

SW1

Lcho

Lbuf

Vin

iac
VSI

Cbuf

vac

LC
filterCdc SW2
Sn

Boost converter Boost type active buffer(b) Conventional boost-type active power decoupling.

Sp

Vdc SW1
iac

Lcho

Cdc

Vin
SW2
Sn

Lbuf
VSI

iL

LC
filtervac

Cbuf

Boost converter Buck type active buffer(c) Conventional buck-type active power decoupling.
Fig. 11. Comparison of power decoupling topology.
Start
input
Pout
Vdc
vout
fout
a

f
DiL

Vin
iin
Diin

Decision Vave, DVc, Vave_fc, Dvfc
Calculation
Cbuf and Cfc, VolCbuf
Selection Switching device
Switching frequency fsw=1 kHz~100 kHz
Calculation
Lbuf and Lfc, VolLbuf
Calculation
Conduction loss and Switching loss, Volheatsink
Calculation total volumeVoltotal
Calculation
Power density rpower, Efficiency hby

The inductor volume depends on several parameters of thecomponents. Moreover, there are several ways to select thecore for the inductor. Thus, the buffer inductor is designed by
the area product method using the window area and the cross-fsw
EndFig. 12. Designing flow for boost-up and buck type power decoupling
circuit.

sectional area. Hence, the volume of the boost inductor VolLbuf

is calculated as

iL 

Vave
dv
Cbuf c 
Vdc
dt





3
4

2
 Lbuf I max 
VolLbuf  K v 

K
B
J
u
max







where, Kv is the volume coefficient depending on the shape ofcores, Imax is the maximum current flowing to the inductor, Ku
is the fill factor of the window, Bmax is the maximum flux
density of the core, and J is the current density of the windings.
The switching devices require a cooling system, e.g.,heatsinks and fans. In general, the cooling system is designed
based on the thermal resistance. The cooling system
performance index (CSPI) is introduced in order to estimate
the volume of the cooling system. The CSPI is an indication of
the cooling performance per unit volume of the cooling system.
The cooling system is small when CSPI becomes higher. The
volume of the cooling system Volheatsink is given by

Volheatsink 

1Rth f  a CSPIB. Conventional buck-type power decoupling design
The buck-type active power decoupling can reduce thebuffer capacitor voltage, as compared to the boost-up typeactive power decoupling, and it can still be designed based on
the flowchart shown in Fig. 12.
The buffer capacitor is designed by (13). However, the DC
link voltage limits the peak voltage of the buffer capacitor. As
a result, the buffer capacitance must be larger than thecapacitance of the boost-up type active power decoupling.
The inductance of the buffer inductor reaches the maximum value when the capacitor voltage is half the input voltage.
Thus, the inductance is designed bywhere, Rth(f-a) is the thermal resistance of the cooling system
which is given byRth  f  a  

T j  TaPloss

 Rth  j  c   Rth c  f   

Lbuf 

iL  Cbuf

Ploss _ sw _ buffer 

1 Tout 2
0iL ron _ buffer dt Tout1eon  eoff  f sw 1 0Tout vciL dt Edcd I md
Tout

Lcho ΔVcsin 2out t  
2





dvc
P
  out cos2out t  
dt
Vave



Vin Vdc  Vin
DI in f sw Vdc





where, DIin is the inductor current ripple, which is 30% of the
rated input current.
The total loss of the switching devices is expressed asin which, Tout is the period of the single-phase grid, ron is theon-resistance of the switching device, fsw is the switchingfrequency of the active power decoupling circuit, eon and eoff
are the turn-on and turn-off energy per switching referred froma datasheet, and Edcd and Imd are the voltage and current underthe measurement condition of the switching loss described in
the datasheet. The buffer capacitor voltage vc and the boost
inductor current iL are expressed asvc  Vave C. Boost converter design
In order to compare between the volumes of the FCC andthe conventional active power decoupling circuit, the volume
 design of the boost converter must be determined.
First, the boost inductor is determined bywhere, Ploss_cond and Ploss_sw are given by

Ploss _ cond _ buffer Vdc
4 ΔiL f sw

 where, iL is the current that flows to the smoothing inductor
which is given by

where, Tj is the junction temperature of the switching device,
Ta is the ambient temperature, Rth(j-c) is the junction-to-casethermal resistance and Rth(c-f) is the case-to-fin thermal
resistance. The total loss Ploss, which is composed of the
conduction loss Ploss_cond and the switching loss Ploss_sw of theswitching devices, is calculated as
Ploss  Ploss _ cond _ buffer  Ploss _ sw _ buffer  

According to (24), an increase in the switching frequency
leads to an increase in the switching loss. The cooling
performance can be improved by fans in order to minimize theuse of heatsinks. However, the system lifetime is limited bythese fans. Thus, the cooling system is designed based on theassumption that the natural cooling is used.

Ploss _ chopper  Ploss _ cond _ chopper  Ploss _ swi _ chopper where, the conduction loss Ploss_cond_chopper is calculated by
Di 2 
Ploss _ cond _ chopper  ron _ chopper  I in2  in  
3 




Moreover, Ploss_swi_chopper is the total switching loss by the
MOSFET Sp and Sn, the switching losses of which are obtained by

TABLE ICOMPONENT SPECIFICATIONS.
CircuitPart

Marking

Maximum ration

CircuitPart

Marking

Maximum ration

Cbuf

Murata Manufacturing
EVS20329S2G306MS09

400 V
30 F

Boost
chopper

Sp
Sn

ROHM
SiC-MOSFET, SCT120AF

650 V
29 A

ROHM
SiC-MOSFET, SCH2080KE

1200 V
40 A

ROHM
SiC-MOSFET, SCT120AF

650 V
29 A

Fuji Electric
IGBT, FGW30N120HD

1200 V
30 A

S1
S2
S3
S4

ROHM
SiC-MOSFET, SCTMU001F

400 V
20 A

Fuji Electric
Si-MOSFET, FMH30N60S1

600 V(2 seriesconnection)
30 A

Cfc

Murata Manufacturing
EVS20329S2G306MS09

400 V
30 F

Murata Manufacturing
EVS20329S2G306MS09

400 V
30 F

Cf

Murata Manufacturing
KC355WD72E225MH01

450 V
1 F

ROHM
SCT2120AF

650 V
29 A

Boost typeactive buffer SW1
SW2

Cbuf
Step down
type
active buffer SW1
SW2

99.5
99.5

1 kHz

fsw increases.

Flyingcapacitor
converter

25 kHz (400V SiC-MOSFET)

Switching device and Cf
200
200
Switching device and Cf
Volume [%]Efficiency [%]

9999
98.5
98.5
98
98

100%=1.43dm3

250
250

Buck type 10 kHz

Boost type 20 kHz
20 kHz (650V SiC-MOSFET)

150
150
Cfc
100
100

Lbuf
Cbuf
Heatsink

Lbuf
Cbuf

50
50

97.5
97.5

Flying capacitor converter
Boost converter and active buffer

Lfc

00

97
97

Lcho

FCC
FCC
1
2
3
4 type Buck
5 type
Boost
00
1
2
3
4
5
6
650V device 400V device
1000
2000
3000
4000
5000
6000
3
Power density [kW/dm ](20kHz)(25 kHz) (20 kHz) (10 kHz)
Fig. 13. Pareto front of FCC, and conventional active power decoupling circuit. Fig. 14. Volume distribution at maximum power density point.













1
Ploss _ sw _ sp f swVdc eon iin  Diin   eoff iin  Diin  Edcd I md
Ploss _ sw _ sn 1
f swVdc eon iin  Diin   eoff iin  Diin  Edcd I md

D. Pareto front optimization with proposed converter
Fig. 13 shows the Pareto front of the proposed FCC and theconventional active power decoupling circuit implemented in
the boost converter. Table I shows the selected component
specifications. Switching devices with a rating voltage of 650
V and 400 V are selected for the FCC, as shown in table I, andthe rating current chosen to be five times the rating input
current. The maximum voltages of the flying capacitor are set
to 340 V and 250 V for each selected switching device.
According to Fig. 13, the power density approaches the
maximum value, when a SiC-MOSFET with a rated voltage of
400 V is used in the FCC at 25 kHz. In particular, a maximum
power density of 5.3 kW/dm3 with an efficiency of 98.9% isachieved.
Fig. 14 shows the volume ratio of the components at the
maximum power density point. The component volumes arenormalized with the total volume of the passive topology as
100%. In the FCC with a 400 V-SiC MOSFET, the volume of
the flying capacitor is reduced by 54.6%, as compared to thatof the electrolytic capacitor. When a flying capacitor voltage
of 400 V is applied to the FCC, the flying capacitor volume is

TABLE II
EXPERIMENTAL PARAMETERS.

SymbolVin
Pout
Pratedfsw_FCC
fsw_VSI
VDC_ave
Cfc
Cdc
Lfc
vac
fac

Quantity
Input voltage
Output power
Rated power
Switching frequency of FCC
Switching frequency of VSI
DC link average voltage
Flying capacitor
DC link capacitor
Boost inductor
Grid voltage
Grid frequency

value
200 V
1.5 kW
1.5 kW
20 kHz
20 kHz350 V
180 F
20 F
1 mH
200 Vrms
50 Hz

twice that for the case of a rated voltage of 650 V. However,the volumes of the boost inductor and the cooling system are
reduced by 58.3% and 46.2%, respectively. As a result, thetotal volume of the FCC with switching devices with a rated
voltage of 400 V is 57.5% of that of the FCC with switching
devices with a rated voltage of 650 V.
VI. EXPERIMENTAL RESULTIn order to confirm the validity of the proposed circuit, a
1.5-kW prototype circuit is tested. Table II shows theexperimental parameters, and the experimental results areshown in Fig.15. In this experiment, for simplicity, MPPT
control is not introduced. In addition, a flying capacitor with180 F is used for voltage derating for each switching devices.

Flying capacitor voltage : fluctuation
Flying capacitor voltage : constant

Flying capacitor voltage vfc [100V/div]

Flying capacitor voltage vfc [100V/div]0

Input current iin [10A/div]0

Grid voltage vac [500V/div]

Input current : fluctuation

Input current iin [10A/div]

0

0

0

0

0
Inverter output current iac [10A/div](a)0

DC link voltage : fluctuation

Grid voltage vac [500V/div]

Inverter output current iac [10A/div]

4[ms/div]

Flying capacitor voltage and input current without proposed control

Input current : becomes constant4[ms/div](b) Flying capacitor voltage and input current with proposed control
DC link voltage fluctuation : reduced

DC link voltage vdc [250/div]

DC link voltage vdc [250V/div]00Flying capacitor voltage vfc [250V/div]0

Input current iin [10A/div]

Flying capacitor voltage vfc [250V/div]0

Input current iin [10A/div]

0

0

0

0
Inverter output current iac [10A/div]

4[ms/div](c) DC link voltage and flying capacitor voltage without proposed control
Fig. 15. Experimental result.

As show in Fig. 15 (a) and 15 (c), the flying capacitor
voltage vfc is constant. However, the inverter DC voltage vdc
fluctuates at twice the single-phase grid frequency, because
the instantaneous difference between the input and output
power is compensated by only the DC link capacitor Cdc. The
fluctuation of the DC link voltage also acts as a disturbance tothe control of the inverter output current. Consequently, thetotal harmonic distortion (THD) of the inverter output current
becomes 5.1%. More importantly, the input current iin
fluctuates greatly due to the power mismatch between the DC
input side and the AC output side. As a result, the performanceof MPPT control decays owing to this input current fluctuation.
On the other hand, in Fig. 15 (b) and 15 (d), the flying
capacitor voltage vfc is fluctuated by the proposed control, andvdc and iin become approximately constant. These results
confirm that the single-phase power fluctuation iscompensated by the flying capacitor Cfc. In addition the flying
capacitor average voltage is balanced at half the DC link
voltage.
Fig. 16 shows the harmonic analysis of the DC link voltage.
The second order harmonic component with the proposed
control is reduced by 74.5% as compared to that without thepower decoupling control. However, a small second-orderharmonic component still appears in the DC link voltage. Thisis because the power fluctuation compensation value has asmall error as compared to the actual single-phase powerfluctuation.
Fig. 17 (a) shows the THD characteristic of the inverter
output current with respect to the output power. Over the

4[ms/div](d) DC link voltage and flying capacitor voltage with proposed control

entire output power range, the inverter output current THD is
improved with the proposed control because the second orderharmonics of the DC link voltage is eliminated by the power
decoupling control. In addition, under a light load, the inverter
output current THD decays, because the ratio between thefundamental frequency and the harmonics increases.
Fig. 17 (b) shows the efficiency and the power factor
characteristics when the proposed control is applied. The
power factor is approximately unity due to the feed forward
control for grid disturbance, whereas the maximum systemefficiency reaches 95.4% at the output power of 1.1-kW.
Fig. 17 (c) shows the loss analysis results for the proposed
converter for an output power of 1.1-kW. According to Fig. 18,
the switching loss is dominant in the FCC and VSI due to thehigh recovery loss. When a wide-band gap device, such as a
SiC-MOSFET is applied, it is possible to reduce the switchingloss. On the other hand, the conduction loss of the FCC issmall because a low-on resistor switching device can be usedowing to the multi-level topology.
Fig. 18 shows the experimental waveforms obtained in theload transient response test. According to Fig. 18, the input
current is regulated to be constant by the proposed control
even when the output power is abruptly changed. In addition,
the fluctuation of the flying capacitor voltage becomes large
when the output power is changed from 0.1 p.u. to 0.7p.u..
This is because the power ripple increases under the heavy
load condition, and the charge and discharge values of theflying capacitor becomes larger. Moreover, the stable control

50

DC link voltage vdc [V]of the inverter output current without any spike current is also
confirmed.
The proposed FCC converter does not use the DC link
capacitor with high capacitance. Thus, in the load transientperiod, a large over shoot occurs on the DC link voltage. In
order to reduce the overshoot, the design of the PI control for
AVR is important. In the load transient test result of Fig.18,
the PI control gain is adjusted in order to reduce the voltage
over shoot. However, DC link voltage still has several
frequency components because the control design is not
optimized in this paper. As a result, the inverter output current
distorts in comparison with the Fig.15. Note that, the inverter
output current THD is 1.9% at 1 kW.

Fundamental
Frequency : 50 Hz

4074.5% reduced by
the proposed control

30
20
10
0

2
4
6
8
10 12 14(100 Hz)
Harmonic orderFig. 16. Harmonic analysis of DC link voltage.

16

18

20

VII. CONCLUSION
Inverter output
current THD [%]

4

[3]

[4]

[5]

[6]

1

0

200

600
1000
Output power [W](a) Inverter output current THD characteristics.

98

1400

Power factor
95.4%

96
94

Efficiency

92

0

200

600
1000
Output power [W]1400(b) Efficiency and power factor.

50

Loss [W][2]

With proposed control

90

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40

Output power : 1.1kW
Switching freq. : 20 kHz
Total loss : 49.8 W
Efficiency: 95.4%

Other loss
(including iron loss of Lfc)

Lfc_ Copper loss
S1-S4_ Conduction loss

FCC

S1-S4_ Switching loss
(including recovery loss)
30
Sup-Svn_ Conduction loss
20
10

VSI
Sup-Svn_ Switching loss
(including recovery loss)

0(c) Loss analysis result obtained at an output power of 1.1-kW.
Fig. 17. Inverter output current THD, efficiency, power factor and loss
analysis.

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Dekker Inc., 2004

DC link voltage vdc [200V/div]
Flying capacitor voltage vfc [200V/div]00Inverter output current iac [10A/div]0
Input current iin [5A/div]020[ms/div](a) 0.1p.u. to 0.7p.u.
DC link voltage vdc [200V/div]
Flying capacitor voltage vfc [200V/div]00Inverter output current iac [10A/div]0
Input current iin [5A/div]020[ms/div](b) 0.7p.u. to 0.1p.u.
Fig. 18. Experimental result in the load transient response test.

Hiroki Watanabe (S’13) was born in Niigata, Japan,
in 1989. He received his B.S. and M.S. degrees inelectrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan in 2013, 2015. He has been with Nagaoka
University of Technology as a Ph.D. course student inenergy and environment science from Nagaoka
University of Technology. His current researchinterests includes single-phase power conversion
system. He is a student member of the Institute ofElectrical Engineers of Japan and the IEEE.
Tomokazu Sakuraba (S’16) was born in Hokkaido,
Japan, in 1992. He received his B.S. and M.S. degrees
in electrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan in 2015, 2017. His current research interests
includes high power density converter. He is a student
member of the Institute of Electrical Engineers ofJapan and the IEEE.

Keita Fulukawa (S’16) was born in Shimane, Japan,
in 1994. He received his B.S. degrees in electrical,
electronics and information engineering from Nagaoka
University of Technology, Niigata, Japan in 2016. He
has been with Nagaoka University of Technology as a
M.S. course student in electrical, electronics andinformation engineering. His current research interests
an inductive power transfer system. He is a student
member of the Institute of Electrical Engineers ofJapan and the IEEE.

Keisuke Kusaka (S'13, M'16) was born in Miyagi,
Japan, in 1989. He received his B.S. and M. S. degrees
in electrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan in 2011, 2013, respectively. From 2015 to 2016,he was with Swiss Federal Institute of Technology in
Lausanne (EPFL), Switzerland as a trainee. In 2016,
he received his Ph.D. degree in energy andenvironment science from Nagaoka University ofTechnology. Since 2016, he has been with Nagaoka
University of Technology, Niigata, Japan as a researcher. His current researchinterests include the areas of inductive power transfer systems and highfrequency converters. Dr. Kusaka is a member of the Institute of ElectricalEngineers of Japan, the Society of Automotive Engineers of Japan and theIEEE.
Jun-ichi Itoh (M’04, SM’13) was born in Tokyo,
Japan, in 1972. He received his M.S. and Ph.D.
degree in electrical and electronic systems
engineering from Nagaoka University of Technology,
Niigata, Japan in 1996, 2000, respectively. From1996 to 2004, he was with Fuji Electric Corporate
Research and Development Ltd., Tokyo, Japan. He
was with Nagaoka University of Technology, Niigata,Japan as an associate professor. Since 2017, he has
been a professor. His research interests are matrix
converters, dc/dc converters, power factor correction
techniques, energy storage system and adjustable speed drive systems.
He received IEEJ Academic Promotion Award (IEEJ TechnicalDevelopment Award) in 2007. In addition, he also received Isao Takahashi
Power Electronics Award in IPEC-Sapporo 2010 from IEEJ, 58th OHM
Technology Award from The Foundation for Electrical Science andEngineering, November, 2011, Intelligent Cosmos Award from Intelligent
Cosmos Foundation for the Promotion of Science, May, 2012, and Third prize
award from Energy Conversion Congress and Exposition-Asia, June, 2013.
Prizes for Science and Technology (Development Category) from theCommendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology, April 2017.
Dr. Itoh is a senior member of the Institute of Electrical Engineers ofJapan, the Society of Automotive Engineers of Japan and the IEEE.