A Single-phase Current Source PV Inverter with Power
Decoupling Capability using an Active Buffer
Yoshiya Ohnuma Koji Orikawa Jun-ichi Itoh
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japanohnuma@npe.co.jp, orikawa@vos.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
Abstract—This paper proposes a new circuit configuration anda control scheme for a single-phase current source inverterwith a power decoupling circuit which is called as the active
buffer. The proposed inverter achieves low-DC-input voltage
ripple and also provides sinusoidal current that can achieve
unity power factor, without large passive components in DC
bus such as smoothing inductors and electrolytic capacitors.
These components are conventionally required in order todecouple the power pulsation caused by single-phase powersource. In this paper, the fundamental operations of the
proposed inverter are demonstrated experimentally. From theexperimental results, the input voltage ripple is 8.87% and theoutput current THD is 4.24%. In addition, the output power
factor over of 99% and a maximum efficiency of 94.9% are
obtained. Finally, it is confirmed that the maximum power
density of the conventional circuit and the proposed circuit are
2.75 kW/L at the switching frequency 70 kHz and 4.86 kW/L at
the switching frequency 80 kHz, respectively.

I.

INTRODUCTION

In recent years, solar power generation systems arewidely used in response to the fast grows and high demandsof electrical energy. Due to the environmental advantages,
solar power generation systems are often applied in the
housing and industries areas. One of key components of thesolar power systems is the photovoltaic (PV) inverter [1][10]. In practical, the voltage and current generated by a PV
fluctuate due to conditions of the weather and so on. That is,
the output power generated by a PV is changed. Therefore,
the maximum power point tracking (MPPT) control isrequired for a PV system. The PV inverters are required toachieve the maximum power point tracking (MPPT) function
and to provide a sinusoidal waveform that can achieve unity
power factor into the grid. In order to satisfy therequirements, many single phase circuits with a power
decoupling circuit has been proposed, which can beclassified as (i) passive power decoupling circuits with
passive components and (ii) active decoupling circuits withsemiconductor switches [11]-[16]. One of the most popular
power decoupling circuits is two-stage converters. It
comprises of a boost chopper and a voltage source inverter,is generally used [1]. However, the converter requires twolarge inductors (the boost inductor and the interconnectedinductor) which inherently increase the size of the inverter.
In addition, a large electrolytic capacitor is necessary inorder to compensate the power pulsation when the inverters
are connected to the single-phase grid because the power isfluctuating at twice of the grid frequency. In a hightemperature operating environment, the use of theelectrolytic capacitor is not preferred in terms of the lifetimeand the power density of the converter because the lifetimeof electrolytic capacitor decreases due to frequent charge/
discharge operations and the long hours of high temperature
operation.
In Ref. [12], a buck converter with a power decoupling
circuit has been proposed. An advantage of this converter isthat the number of semiconductor switch is only one in the
power decoupling circuit. However, a large inductor isrequired in order to achieve sinusoidal current that canachieve unity power factor. In Ref. [13]-[14], the power
decoupling circuits with soft-switching technique has been
proposed. At the resonance point, unity power factor can beachieved perfectly. However, the operation of the circuit
depends on the condition of a load. Moreover, the maximum
value of the circulation current increases. As a result,applications of the circuit are limited and the conduction loss
increases. On the other hand, matrix converters with a power
decoupling capability have been proposed [17]-[18]. In thoseconverters, high efficiency can be achieved because thenumber of switches where the current flows is reduced andthe smoothing capacitor is not required at a DC link part.
Nowadays, the current source inverter allows greatfeatures that the inverter can achieve both the MPPT
function and the grid-connected control by one converter.
However, a large smoothing inductor is required to decouple
the power pulsation caused by the single-phase power
generation. Therefore, conventional circuits with a power
decoupling capability have problems that the size and cost
increase depending on the number of passive components,
and also the power density is low.

The values of the active buffer capacitor can be reducedby controlling the capacitor voltage, allowing for the use ofsmall capacitors such as film capacitors or laminated ceramic
capacitors. Other passive components are required at the
input and output filters in the proposed inverter in order toeliminate the switching ripple. In addition, diodes that areconnected in series to the switches in the inverter are notrequired in the proposed inverter. Note that, the proposed
inverter is constrained at the operation with unity power
factor. First, the fundamental operations of the proposed
inverter are demonstrated and explained. Then, the principleof the controls strategy is illustrated. Lastly, the validity ofthe proposed controls is confirmed by experiments.
II.

CIRCUIT TOPOLOGY

A. Circuit Configuration
Fig. 1 shows one of the conventional PV inverter. The
conventional PV inverter which consists of the boost
chopper and the voltage source inverter, is used widely. The
inverter requires the two large inductors; the boost inductor
Ldc and the interconnected inductor Lac. Additionally, a large
electrolytic capacitor is also required in order to compensate
the power pulsation with a twice of the grid frequency when
the inverter is connected to the single-phase grid. Due to theabove reasons, downsizing for this converter becomesdifficult and challenge.
Fig. 2 presents the circuit structure of the proposed
converter. The proposed converter is constructed based on
the current source inverter with an active buffer circuit. The
proposed converter achieves the DC-voltage control for the
MPPT, operation on the inverter for an interconnection andpower pulsation with a small capacitance. These functions
are realized by the combined controls between the current
source inverter and the active buffer circuit. The low-voltage
ripples are obtained except a switching ripple even when asmall smoothing inductor Ldc is used. Moreover, the diodes
that are required in the current source inverter are notnecessary to achieve unity power factor. This is because thefree-wheeling mode is operated in the active buffer.
Additionally, recovery of the diodes does not occur because
there is no path to flow the current on the body-diodes of the
MOSFETs.

IIN
Ldc
Cdc

D1

S1

S3

Lac

Cc

S0

VIN

Lf iac
Cac

S2

vac

S4

Voltage source
inverter

Boost chopper

Figure 1. Conventional voltage inverter with a boot chopper.
iinv

IIN
Ldc
Cdc
VIN

D1
S0

ic

S1

S3

vc

Cc

Lf iacCac

va_dc

This paper proposes a new single-stage current source
inverter with a power decoupling circuit, which is called as
the active buffer [19], to overcome those drawbacks. The
proposed inverter is constructed based on a current source
inverter with an active buffer. The buffer circuit consists of
one switch, two diodes and one small capacitor. Therefore,
the size and the number of passive components in the
proposed circuit can be reduced compared with that ofconventional circuits. As a result, the proposed circuit canachieve high power density. The power pulsation with twiceof the grid frequency is decoupled by the active buffer
capacitor. Therefore, the proposed inverter can control thevariable input-DC-voltage to achieve the MPPT and provides
a sinusoidal current into the grid without the large inductor.

D0

S2

Active buffer
circuitCurrent source
invertervac

S4

Figure 2. Proposed PV inverter.

B. Operation modes
Fig. 3 illustrates the switching pattern of the proposed
inverter when the grid voltage is the positive. The current
pathway does not occur from the grid to the active buffer
capacitor because the active buffer capacitor voltage must be
higher than the grid voltage. Therefore, assuming that the
input is a continuous current source IIN, the current pathwaysof the proposed inverter have four modes based on theswitching pattern. In the mode 1, the input power (PVpower) is directly supplied to the single-phase grid. The
buffer power is controlled by the mode 2 and 3. In the mode
2, the current IIN flows into the capacitor in the active buffer
circuit. In contrast, in mode 3, the buffer capacitor isdischarged through the S0. The mode 4 is a current
freewheeling mode for the input current. Thus, the proposed
inverter performs both functions of a boost chopper (mode 1,
mode 4) and the buffering function for the power pulsationcompensation (mode 2, mode 3). The switches S3 and S4 arenot switched except the polarity of the grid is reversed. Thus,
the power control with PWM is held with combinations of S0
and S1, or S0 and S2. It means that the losses of the inverter
are dramatically reduced.
III.

CONTROL STRATEGY

Fig. 4 depicts the principle of power pulsationcompensation. When both the grid voltage vac and the output
current iac have sinusoidal unity power factor, theinstantaneous output power pout is expressed as follows;p out  V ACp I ACp sin 2 t 

1
1
V ACp I ACp  V ACp I ACp cos 2t 
2
2

(1),

IIN

S3

S1

S0

vAc

VIN
S2

S1

S0

Cc

IIN

VIN

IIN

S4

(S0:OFF, S1:OFF, S2:OFF, S3:OFF, S4:ON)(a) Mode 1.

(b) Mode 2.

S3

S1

S0

vAc
S2

S4

(S0:OFF, S1:ON, S2:OFF, S3:OFF, S4:ON)

S3

Cc

vAc

VIN
S2

S1

S0

Cc
IIN

S3

Cc

VIN

S4

vAc
S2

S4

(S0:ON, S1:OFF, S2:OFF, S3:OFF, S4:ON)(S0:ON, S1:ON, S2:OFF, S3:OFF, S4:ON)(c) Mode 3.

(d) Mode 4.
Figure 3. Operation modes of the proposed inverter.
vc

vin

vac

VCmax
VCmin
t

0

t

0

Iacp
t

0

＋

t

t

iac

Discharge0

vac=VACp sin(t)0＋

ic(LPF)

＋

iin

Vacp

iac=IACp sin(t)t0Chargepbuf
Discharge

pout

Charge＝＋t0Input powerpin [W]

＝

＝

＝

pin

t

0

Buffer powerpbuf [W]0tOutput power
pout [W]Figure 4. Compensation principle of power pulsation.

where VACp is the peak amplitude of grid voltage, IACp is thepeak amplitude of the output current, and  is the grid
angular frequency.
Base on (1), the power pulsation with twice of the grid
angular frequency appears in the output power. In order todecouple the power pulsation, the buffer circuit
instantaneous power pbuf is required, as given by1
pbuf   V ACp I ACp cos 2t 
2(2),where the polarity of pbuf is defined as positive when thebuffer capacitor discharges. The mean power of the buffer
circuit is zero because the buffer capacitor absorbs only thepower pulsation.

Consequently, the instantaneous input power pin will be
constant:1
pin  V ACp I ACp  VIN I IN
2

(3).

The proposed inverter is controlled in four modes asshown in Fig. 3. Therefore, assuming that the input current
IIN is continuous, the inverter current iinv and the capacitor
current ic can be expressed asiinv   d mode1
 i    d
 c   mode2

d mode3  I INd mode3 (4),where dmode1 through dmode4 are the duty ratios of the eachmode. The duty ratios are constrained by the continuous
current (IIN), as follows:d mode1  d mode2  d mode3  d mode4  1(5).

In order to obtain a sinusoidal output current, iinv isconstrained as (6). The capacitor current ic should becontrolled as (7), based on (2), in order to compensate thepower pulsation.
iinv  I ACp sin(t )ic  

V ACp I ACp
2v c

(6)

cos( 2t )(7)

Therefore, dmode1, dmode2 and dmode3 are controlled by thefollowing equations:d mode1 

I ACp
I IN

sin(t )  d mode3

 d mode2  d mode3  d tempo  V ACp I ACp
2vc I IN(8),

cos 2t  (9),where dtempo is defined as “– dmode2 + dmode3”. When thecapacitor current ic is positive, i.e., when dtempo is positive,mode 3 is selected in order to discharge the capacitor. In
contrast, when the capacitor current ic is negative, i.e., when
dtempo is negative, mode 2 is selected.
The ratio of IACp over IIN can be obtained as follows basedon (3), and substituting (10) into (8) and (9).
I ACp
I IN

2

VIN
V ACp

(10)

Therefore, dmode1, dmode2 and dmode3 are obtained by (11)and (12) by using (8), (9) and (10).

*Vd mode1  2 IN sin(t )  d mode3
V Acp

(11)


, d tempo  0d tempo
d mode2  , d tempo  00 d tempo , d tempo  0d mode3   0, d tempo  0



(12)

where VIN* is the reference value of the input DC voltage.
Note that VIN* has to satisfy (13) because all duty commands
should be positive value and satisfy (5).
*

VIN 

V Acp
2

(13)

From (13), the maximum of the input DC voltage is limitedby half of single phase maximum voltage. Therefore, (13)shows that PVs which has open circuit voltage bellow half ofthe single phase maximum voltage can be used. On the other
hand, the maximum of the input DC voltage is not related toa MPPT control because it is conducted by using the input
power generated by PVs.
Fig. 5 shows a control block diagram of the proposed
circuit. Based on (8), (9) and (10), the duty ratio commands
are calculated from the detected grid voltage vac, capacitor
voltage vc, input current iin, command of the input voltage
VIN*, minimum voltage of the active buffer capacitor VCmin,and capacitance of the active buffer capacitor Cc. The voltage
and current generated by a PV actually depend on conditionsof the weather and so on. In this paper, experimental
verifications for actual PVs are not conducted. However,using a maximum power point tracking (MPPT) control anda PI regulator, the proposed circuit can be adopted for actual
PVs. First, the maximum power point tracking (MPPT)
control is conducted by using detected input voltage vin andinput current il. Then, the controller of MPPT outputs thecommand of input current. The input current is controlled byusing a PI regulator and it outputs the command of input
voltage. As a result, the proposed method can be applied toactual PVs.
If the capacitance in a buffer circuit is changed due toapplied voltage, temperature variation and so on, thecommand of the voltage in the active buffer capacitance ischanged. As a result, the error in the required buffer circuit
power occurs and the input power fluctuates. However, eventhough the capacitance in the buffer circuit is changed,
unstable operation that proposed circuit cannot be connectedto the grid does not occur. That is why switching patterns of
the buffer circuit and the inverter are theoreticallydetermined based on (5). Therefore, the proposed method isrobust with respect to parameters variations from the view
point of the stability of operations.

D1

VIN

S0

Cdc

InterfaceFromsensorsPeakdetection

vac

PLL

q

pin
×

PI

S2

S4

vc sw1
sw2

sw3
sw4

Lac iacvac+

2

VCmin +Ssgn

dmode1s1+
2vc
d
Vacp PI



VIN

MPPT

D0

2VIN*
|sin(q)|Vacp

VIN*
cos(2q)
vc

il* +

S3

Sgn{sin(q)}

vc

il

S1

sw0

il

Vacp

Cc

dtempop In
sin(2q )  1
Cc

vc* +

+

PI

dmode2

Limit

-1

dPI

dmode3

Limit
1

VIN*

+
+
+
+

s2

Pulse transform

Ldc

s3

Carrier

0

Cc
VCmin

Figure 5. Control block diagram.
TABLE I. SWITCHING TABLE.
The numberof mode

Mode1
Mode2
Mode3
Mode4
Mode1
Mode2
Mode3
Mode4

ssgn
1
1
1
1
-1
-1
-1
-1

s1
1
0
0
0
1
0
0
0

s2
1
1
0
0
1
1
0
0

s3 sw0 sw1 sw2 sw3 sw4
1 0 1 0 0 1
0 0 0 0 0 1
1 1 1 0 0 1
0 1 0 0 0 1
1 0 0 1 1 0
0 0 0 0 1 0
1 1 0 1 1 0
0 1 0 0 1 0

Table I presents the pulse transform table for thegeneration of gate pulses. The gate pulses are given bycomparing the pulse transform tables with a triangle carrier.
Note that the capacitor voltage is controlled by a PI
controller.
IV.

EXPERIMENTAL RESULTS

In order to demonstrate the validity of the proposed
inverter, a 400-W prototype circuit has been tested. The
proposed control is implemented using a digital control
system with a digital signal processor (DSP, TMS320C6713
DSK) and a field-programmable gate array (FPGA, Actel
ProASIC Plus APA300). Note that the controller is not
optimized for the proposed circuit. A typical controller isused to check the fundamental operation of the proposed
circuit in our laboratory. In this paper, the power supplies areconnected at the input and output of the proposed circuit forthe simplicity since this paper aims to confirm a fundamental
operation. Moreover, the input and output sides arecontrolled as the current source mode and voltage source

Input
voltage[100V/div] 0
Input
current[5A/div]0
Outputvoltage 0[250V/div]
Outputcurrent 0[10A/div][5ms/div](a) Input and output waveform.

Capacitor
voltage[100V/div]0
Outputvoltage 0[250V/div]
Outputcurrent 0[10A/div][5ms/div](b) Capacitor voltage and output waveforms.
Figure 6. Experimental waveforms.

mode with assuming that the grid voltage is 100 V,
respectively. The input and output filters consist of a 1-mH(%XL = 1.25%) inductor and a 3.3-F capacitor. A 50-F
film capacitor is used for the active buffer capacitor. In theInput voltage VIN (V)

100

80

Output AC power factor

Efficiency andoutput power factor [%]70
Input current il (A)64Capacitor voltage vc (V)
400
350
300
250
Output voltage vac (V)
400
200
0
-200
-400 Output current i (A)
ac
4
2
0
-2
-4

96
94

Efficiency

92
90

100

200
300
Output power [W]400

Figure. 8. Efficiency and output AC power factor.

Time (s)20 (ms/div)

Figure. 7. Simulation waveforms.

experiment, the grid voltage is 100 Vrms, the input voltage
command is set to 70 V, and a carrier frequency is 20 kHz.
Fig. 6 shows the experimental waveforms of the
proposed circuit. Fig. 6 (a) illustrates the input and output
waveforms when the prototype is operated with the rated
power. From the experimental results, the output power
factor is 99.9%, and the total harmonics distortion (THD) of
output current is 4.24%. Simultaneously, DC voltage iscontrolled according to the reference value of 70 V.
Moreover, the voltage ripple is 9.33%. Fig. 6 (b) shows thecapacitor voltage which is fluctuating with twice of the gridfrequency. Furthermore, the amplitude of the voltage
fluctuation matches to theoretical value. Hence, it isconfirmed that the proposed circuit achieves the power
pulsation compensation with active buffer.
Fig. 7 shows the simulation waveforms of the proposed
circuit in a transient-state operation when the input power
and the input voltage are changed. From the simulation result,if the input voltage and input current are changed, the output
voltage and output current are stable without such surge
voltage and spike current. As a result, the proposed method
is robust for the transient-state operation.
Fig. 8 presents the efficiency and power factor
characteristics subjects to the output power. The output
power factor is 99% at the rating power and the maximum
efficiency is 94.9%. Additionally, high efficiency and power
factor are confirmed in wide range of output power.
Fig. 9 shows the harmonics analysis results of the
proposed circuit. The THD of the output current is less than
5% within the output power from 100 W to 400 W. From
this result, it is clear that the PV interconnection with theproposed circuit can be achieved. Besides, DC voltage ripple
is suppressed to less than 12% within the output power from

THD of output current and input
voltage ripple [%]

8

98

14
12

Input DC voltage ripple

1086THD of output AC current

4
2

100

200
300
Output power [W]400

Figure. 9. THD of output current and input voltage ripple.
TABLE II. SPECIFICATIONS OF THE PROTOTYPE CONVERTER.
Output power POUT

500 W

Output voltage VAC 200 V(rms) Output frequency fAC

50 Hz

Input voltage VIN

100 V

TABLE III. DEVICE INFORMATION OF PROTOTYPE CONVERTER.
S0,S1,S3

IPW60R041C6 (Infineon)

S2,S4

STY139N65M5 (STM)

D0,D1

DSEI120-06A (IXYS)VDS:650[V] RDS:0.041[W]Tr:10[ns] Tf:7[ns] Trr:950[ns]VDS:710[V] RDS:0.017[W]Tr:56[ns] Tf:37[ns] Trr:570[ns]VRRM:600[V] VF:1.3[V]
Trr:35[ns]100 W to 400 W. This is attributed that the power pulsation
are compensated by the active buffer circuit.
V.

COMPARISON TO CONVENTIONAL BOOST CHOPPER

In this section, a power density of the proposed circuit iscompared with the conventional boost chopper in order toclarify a superiority of the circuit. Table II provides thedesign specifications of the prototype. In this consideration, aPV with a rated voltage of 100 V and a grid of 200 V are
assumed.
A. Circuit Design and Calculation of Volume
1) Switching Devices: S and D
Table III presents the device information of the prototype.
The basis of selection for each component such as a switches

and diodes is in common. Thus, the same components areused in both the proposed circuit and conventional boost
chopper. In the selection of the MOSFETs, the switches S0,
S1, S3, which can achieve high speed switching, and theswitch S2, which has a low on resistance are selected.
Similarly, the fast recovery diodes D0 and D1 are selected.
2) DC Link Capacitor: Cc
In the conventional circuit, the average capacitor voltage
Vc is boosted up to 350 V. Besides, the allowable voltage
ripple is set to 2.5% where the voltage ripple is defined as(14) with using a fluctuation range of the voltage Vc.
ripC 

VC
2VC

(14)

On the other hand, the proposed converter has provenable to control the capacitor voltage significantly. The
minimum voltage and maximum voltage of the capacitor are
set to 282 V to 430 V respectively. The required lowest
capacitance is calculated from (15).

Cc 

POUT
4f ACVC ripC
2

(15)

Besides, the current ripple Iripple_Cc, which flows into thecapacitor, is obtained by
I ripple_ Cc 

POUT
VC

(16)

Note that, considering the current ripple from the boost
chopper and inverter, twice the ripple current, which is
calculated by (16), is used as a selected value.
The electrolytic capacitor is chosen as a DC link
capacitor of the boost chopper because the 260 F is neededin order to confirm the design specifications. In contrast, alaminated ceramic capacitor can be used because thecalculated value with (15) is 30 F. Note that, the DC link
capacitor CC is not affected by the switching frequency.
Besides, the volume of the capacitor is derived from
capacitors in the marketplace.
3) Inductor: Ldc, Lac
Each inductor is designed based on the ripple ratio of
inductor current. The ripple ratio of the boost inductor andthe interconnected inductor are set as 10% and 5%,
respectively. Note that the ripple ratio is defined by (17)using the ripple current IL and the average current of
inductors IL.
ripL 

I L
2I L

(17)

In case of the boost inductor Ldc, the required inductanceis obtained by (18).

Ldc 

VIN (VC  VIN )2 I L ripLVC f sw

(18)

where fsw is the switching frequency. Here, volumes of theinductors are evaluated using Area product concept [18].
4) Filter: Lf, Cac, Cdc
The standardized filter inductance Lf at the switchingfrequency of 10 kHz is set to 1% of the output power
capacity. The filter inductance Lf is determined so that the
ripple current is same according to the switching frequency.
Values of Cac and Cdc are selected so that the cut-off
frequency is one-tenth of the switching frequency.
5) Cooling fin
The volume of the cooling fin is estimated by CSPI
based on the power loss that is calculated from a simulation[21]. Here, natural air cooling is considered as the coolingmethod. In this paper, the CSPI value is 3, the volume of thecooling fin is calculated so that the chip temperature is below
than 125 deg. C when the ambient temperature is 45 deg. C.
VI.

COMPARIOSON OF POWER LOSS

This chapter shows the loss analysis using the circuit
simulator Piece-wise Linear Electrical Circuit Simulation(PLECS).
Fig. 10 shows the efficiencies of the conventional circuitand the proposed circuit when the switching frequency is 10
kHz and 100 kHz, respectively. When the switchingfrequency is 10 kHz, in the proposed circuit, the conduction
loss of the diodes is dominant in the total loss because thenumber of employed diodes is two. The total loss increases
due to the increasing of the switching loss when theswitching frequency is 100 kHz.
VII. COMPARISON OF VOLUMES
Fig. 11 shows pareto-front curves, which shows therelationship between the power density and the efficiency
according to variation of the switching frequency. As a result,
it is confirmed that the maximum power density of theconventional circuit and the proposed circuit is 2.75 kW/L at
the switching frequency 70 kHz and 4.86 kW/L at theswitching frequency 80 kHz, respectively. In addition, theproposed converter can achieve higher efficiency at highswitching frequency comparing with that of the conventional
circuit.
Fig. 12 shows ratios of each volume at the maximum
power density. As a result, it can be seen that the volume ofthe proposed circuit is reduced by approximately 40%
compared with that of the conventional circuit. In theconventional circuit, a DC link capacitor and aninterconnected inductor are the cause of the large size.
Especially, the volume of the DC link capacitor cannot bedecreased according to the increasing of the switchingfrequency. On the other hand, the volume of the buffer
capacitor in the proposed circuit can be decreased according
to the increasing of the switching frequency.

VIII. CONCLUSION[1]

M. Calais, J. Myrzik, T. Spoone, and V. G. Agelidis, “Inverters for
single-phase grid connected photovoltaic systems-an overview,” inProc. 2002 IEEE 33rd Annual Power Electronics Specialists
Conference, 2002. pesc 02, vol. 2, pp. 1995–2000, 2002.
[2] S. Kjaer and J. Pedersen, “A review of single-phase grid-connected
inverters for photo-voltaic modules,” IEEE Trans. Ind. Ap., vol. 41,
no. 5, pp. 1292-1306, 2005.
[3] D. Cao, S. Jiang, and X. Yu, “Low Cost Semi-Z-source Inverter forSingle-Phase Photo-voltaic Systems,” IEEE Trans. Power Electron.,
vol. 26, no. 12, pp. 3514-3523, 2011.
[4] S. Harb, H. Hu, N. Kutkut, I. Batarseh, and Z. J. Shen, “A three-port
Photovoltaic (PV) micro-inverter with power decoupling capability,”
in 2011 Twenty-Sixth Annual IEEE Applied Power Electronics
Conference and Exposition (APEC), no. 2, pp. 203–208, 2011.
[5] Z. Chao, H. Xiangning, and Z. Dean, “Design and control of a novel
module integrated converter with power pulsation decoupling forphotovoltaic system,” in Proc. International Conference on Electrical
Machines and Systems, ICEMS 2008, pp. 2637–2639, 2008.
[6] T. Shimizu, K. Wada, and N. Nakamura, “Flyback-Type Single-Phase
Utility Interactive Inverter With Power Pulsation Decoupling on the
DC Input for an AC Photovoltaic Module System,” IEEE Trans.
Power Electron., vol. 21, no. 5, pp. 1264-1272, 2006.
[7] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey and D.
P. Kothari, “A review of single-phase improved power quality ACDC converters”, IEEE Trans. Ind. Electron., vol. 50, No. 5, pp. 962981, 2003.
[8] Q. Li and P. Wolfs, “A Review of the Single Phase Photovoltaic
Module Integrated Converter Topologies With Three Different DC
Link Configuration,” IEEE Trans. Power Electron., vol. 23, no. 3, pp.
1320–1333, 2008.
[9] H. Hu, S. Harb, N. Kutkut, I. Batarseh, and Z. Shen, “A review of
power decoupling techniques for micro-inverters with three different
decoupling capacitor locations in PV systems,” IEEE Trans. PowerElectron., vol. PP, no. 99, p. 1, 2012.
[10] C. Rodriguez and G. Amaratunga, “Long-lifetime power inverter forphotovoltaic AC modules,” IEEE Trans. Ind. Elec., vol. 55, no. 7, pp.
2593-2601, Jul. 2008.
[11] J. C. Crebier, B. Revol, and J. P. Ferrieux, “Boost-chopper-derived
PFC rectifiers: interest and reality,” IEEE Trans. Ind. Elec., vol. 52,
no. 1, pp. 36–45, 2005.

6

Loss [W]

5
4
3
2
1
0

Conventional Proposed
circuitcircuit

100 kHz

16
14
12
10
8
6
4
2
0

D0 &D1
recovery losses
D0 &D1
conduction losses
S0
switching loss
S0
conduction loss

Conventional Proposed
circuitcircuit

S1~S4
switching losses
S1~S4
conduction loss

Figure. 10. Comparison of loss analysis.
100

10 kHz
10 kHz98

Efficiency [%]REFERENCES

10 kHz7

200 kHz

70 kHz96

200 kHz

20 kHz80 kHz

20 kHz300 kHz

Proposedcircuit94
300 kHz

Conventional
circuit12
3
4Power density [kW/l]

92
0

5

6

Figure. 11. Pareto-front curves.
200

S0~S4,D0~D1
Lf

160

Volume [cm3]This paper proposes a new circuit topology and a control
scheme for a single-phase current source inverter with apower decoupling circuit which is called as the active buffer.
The proposed inverter achieves low-DC-input voltage ripple
and also provides clear sinusoidal current into the singlephase grid, without large passive components in the DC bus.
These components are conventionally required in order todecouple the power pulsation caused by single-phase powersource. In this paper, the fundamental operations of the
proposed inverter are demonstrated experimentally. From theexperimental results, the input voltage ripple is 8.87% andthe output current THD is 4.24%. In addition, the output
power factor over of 99% and the maximum efficiency of
94.9% are obtained. Finally, it is confirmed that the
maximum power density of the conventional circuit and the
proposed circuit could be 2.75 kW/L at the switchingfrequency 70 kHz and 4.86 kW/L at the switching frequency
80 kHz, respectively.

Cac
Lac

120

Cc
80

Ldc
Cdc

40

Heat sink0

Conventional
circuit(at 70 kHz)

Proposedcircuit(at 80 kHz)

Note : values of Cdc and
Cac are very small

Figure. 12. Comparison of converter volumes.
[12] L. Huber, L. Gang, and M. M. Jovanovic, “Design-oriented analysis
and performance evaluation of buck PFC front end,” IEEE Trans.
Power Electron., vol. 25, no. 1, pp. 85–94, 2010.
[13] G. Moschopoulos, P. K. Jain, “A Novel Single-Phase Soft-Switchied
Rectifier With Unity Power Factor and Minimal Component Count”,
IEEE Trans. Ind. Electron., vol. 51, No. 3, pp. 566-576, 2004.
[14] C. Licitra, L. Malesani, G. Spiazzi, P. Tenti and A. Testa, “Singleended soft-switching electronic ballast with unity power factor,”
IEEE Trans. Ind. Ap., vol. 29, no. 2, pp. 382-388, 1993.
[15] P. T. Krein and R. S. Balog, “Cost-Effective Hundred-Year Life forSingle-Phase Inverters and Rectifiers in Solar and LED Lighting
Applications Based on Minimum Capacitance Requirements and a
Ripple Power Port,” 2009 Twenty-Fourth Annual IEEE Applied

Power Electronics Conference and Exposition, pp. 620-625, Feb.
2009.
[16] A. C. Kyritsis, N. P. Papanikolaou, and E. C. Tatakis, “A novel
Parallel Active Filter for Current Pulsation Smoothing on Single
Stage Grid-connected AC-PV Modules,” in Proc. 2007 European
Conference on Power Electronics and Applications, 2007, pp. 1-10.
[17] M. Saito, T. Takeshita, and N. Matsui, “A single to three phase matrix
converter with a power decoupling capability,” in Proc. 2004 IEEE
35th Annual Power Electronics Specialists Conference, 2004. PESC
04, 2004, pp. 2400–2405.
[18] M. Saito and N. Matsui: “A Single- to Three-phase Matrix Converter
for a Vector-Controlled Induction Motor", IEEE Industry
Applications Society Annual Meeting, 2008., IAS '08, pp. 1 - 6,(2008)[19] Y. Ohnuma and J.-ichi Itoh, “A control method for a single-to-threephase power con-verter with an active buffer and a charge circuit,”
Proc. IEEE Energy Conversion Con-gress and Exposition ECCE
2010, pp. 1801-1807, 2010.
[20] C. W. T. McLyman, Transformer and Inductor Design Handbook, 3rdEd., New York, NY: Marcel Dekker, 2004.
[21] J. W. Kolar, J Biela and J, Minibock：「Exploring the Pareto Frontof Multi –Objectice Single-Phase PFC Rectifier Design Optimization-99.2% Efficiency vs. 7kW/dm3 Power Density」，IPEMC 2009China，(2009)