Parasitic Parameters Analysis and Design of
Snubber Circuit on PCB for High-frequency
Wireless Power Transfer
Keisuke Kusaka
Nagaoka University of Technology
Nagaoka, Niigata, Japankusaka@vos.nagaokaut.ac.jp

Masamichi Yamaguchi
Nagaoka University of Technology
Nagaoka, Niigata, Japanm_yamaguchi@stn.nagaokaut.ac.jp

Abstract— This paper presents an analysis of the PCB
pattern, which is for a high-frequency inverter circuit. In a highfrequency inverter circuit, the design of the snubber circuit,which suppresses surge voltage, is essential to achieve kilowatt
operation. The authors are aiming to simulate a surge voltage inorder to decide the parameters of the snubber circuit. In thispaper, the surge voltage is simulated using the analysis result of
the PCB and the models of the passive components.
Furthermore, the surge voltage with changing the snubber
capacitor is evaluated in order to make the relationship between
the surge voltage and the snubber circuit parameters as the firststep of the parameters design by using simulation.
Keywords—Parasitic
Snubber circuit

parameters,

PCB,

Surge

voltage,Jun-ichi Itoh
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Thus, parasitic parameters on a PCB should be accuratelyanalyzed.
In this paper, the parasitic parameters on the PCB areanalyzed to estimate the surge voltage of the devices. First,
the parasitic parameters on the PCB are analyzed by using
electromagnetic analysis. In order to confirm the validationof the analysis result, analysis results are compared to themeasurement result. Furthermore, the surge voltage between
a drain and a source of FETs is simulated using the analysisresult. The simulated waveform is compared to themeasurement waveform. Finally, the maximum surge voltage
value with changing the snubber capacitor is investigated as
the first step of the circuit parameters design with simulation.
II. ELECTROMAGNETIC ANALYSIS OF PCB PATTERN

I. INTRODUCTION
In recent years, the demand for the higher power density ofa wireless power transfer (WPT) system is increasing.
Notably, passive components such as inductors andcapacitors should be miniaturized to reduce the circuit
volume. Employing a high switching frequency is one of themethods to achieve high power density. Thus, the megahertz
operation, which employs a GaN-transistor of a WPT system
for EV charger, has been actively studied [1–2].
However, the effect of the parasitic parameters on a printed
circuit board (PCB) should not be ignored when the switchingfrequency is high such as megahertz [3–4]. The parasitic
inductance on the DC-bus or snubber circuit pattern willcause a surge voltage between a drain and a source of FETs.

Figure 1 shows the circuit configuration of the megahertz
resonant inverter. The GaN-transistors (PGA26E07BA: 600
V, 26 A, Panasonic) are used for megahertz switching (6.78–13.56 MHz). Parasitic parameters of the DC-bus are one of
the causes of the surge voltage between the drain and thesource of the switching devices. Therefore, the DC-bus
pattern is analyzed and compared to the measurement resultin order to confilme the accuracy of the electromagneticanalysis result.
Figure 2 shows a circuit pattern of the DC-bus on the PCB.
Port 1 is the input side of the DC-bus, and Port 2 is the Hbridge side of the DC-bus. PCB consists of four conductive
layers and three dielectric layers. Table 1 shows the layer
parameters of the PCB. Furthermore, the copper conducting
rate is 58.7 MS/m, the relative permittivity of the FR4 is 4.5

Port 1 +FET1

CDC47 mF

VDC
50V

FET3
vds1

Cf1 Cf1 Cf11 mF

PCB

Port 2 +Cf2
Cf2
0.47 mF

Cf3
Cf3
470 pF

CDC

vds3

Rf1W

Rf

Cf4
100 pF

Cf2 Cf2 Cf3 Cf3

FET2

RL
100 W

Cf4

FET4LrPort 2 -Port 1 Snubber circuit

Fig. 1. High-frequency resonant inverter.

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

LrCr
7.2 mH 75 pF

Crand loss tangent is 0.02 in the simulation. Electromagnetic
analysis software: ADS (Advanced Design System,Keysight), is used to analyze the DC-bus pattern.
The two-ports S-parameter, which is used for the analysis
in ADS, is converted to the Y-parameter. Then, the parasitic
inductance and resistance are calculated from the Yparameters. Figure 3 shows the model of the parasitic
components between Port 1 and Port 2. The conversion
formula from Y-parameter to the parasitic components isexpressed as

Port 1 +Port 2 +Port 1 -Fig. 2. Layout of DC-bus.
Table 1. PCB layer parameter.

 1 
 1 
L12  Im   Im 
 ................................... (1), -Y12  -Y21 
 1 
R12  Re 
 ..................................................... (2),
 -Y12 In order to evaluate the effect on the surge voltage due tothe parasitic parameters, the analysis result of the PCB pattern,which includes parasitic parameters, is used in the time
domain simulation. The Spice model of the GaN-transistor isused in the simulation. Table 2 shows the parameters of theGaN-transistor model. The other circuit components are theideal model.
Figure 7 shows the drain-source voltage of FET1 withexperiment and simulation. For the comparison of the effectof the parasitic parameters, the simulation with an ideal DCbus pattern, which has no parasitic inductance, is also
simulated. The surge voltage in the drain-source occurs in thesimulated waveform with the results of the analysis of thePCB. On the other hand, the surge voltage does not occur inthe waveform without analyzed board data. The amplitude of
the surge voltage is 53.4 V in the simulation, and theexperimental result in the same condition with the simulation
is 32.0 V. The error rate of the surge voltage amplitude isMaterialThickness

AirCopper
FR4Copper
FR4Copper
FR4Copper
Air－0.040 mm
0.1 mm
0.035 mm
0.2 mm
0.035 mm
0.1 mm0.04 mm
－L12

Cg11

Rg11

R12Port 2

Cg22

Rg22Fig. 3. Parasitic-parameter model.
Port2Port1+

Port1-

Probe 1
Probe 2

Short

Port2+Fig. 4. Measurement of the DC-bus line on PCB.
Parasitic inductance Ljig nH

III. SIMULATION AND EXPERIMENT OF THE SURGE VOLTAGE

Layer
Dielectric
Top layer
Dielectric
2nd layer
Dielectric
3rd layer
DielectricBottom layer
DielectricPort 1

4.0
3.0
2.0
1.0
0.0

10 k

100k1M
Frequency f Hz

10M

100M

10M

100M

(a) Inductance of jig.
Parasitic resistance Rjig mW

where Y12, Y21 is the Y-parameters.
In order to confirm of the accuracy of the electromagnetic
analysis result, the parasitic conponents is measured in thetest board. The vector network analyzer (E5061B, Keysight)
is used to measure parasitic components. The shunt-throughmethod, which is able to measure impedance in milliohm, isused to measure the tiny parasitic components. Figure 4shows the PCB measurement. For the measurement ofparasitic parameters on DC bus, two probes is connected to
Port 2 in parallel, and the jig shorts Port 1. In order tocompensate the effect in impedance of the jig, the impedanceof the jig is subtracted from the measurement impedance ofthe DC bus. Figure 5 shows the measurement result of theparasitic parameters on the jig.
Figure 6 shows the analysis and measurement result of theDC-bus pattern. The parasitic inductance of the analysis is54.5 nH and the measurement is 52.5 nH at 6.78 MHz. The
parasitic resistance of the analysis is 93 mW , and themeasurement is 82 mW at 6.78 MHz. The error rate of theparasitic inductance is 3.8% and parasitic resistance is 13%.
The parasitic inductance and resistance measured by theexperiment show good agreement with the simulation. Thus,
the accuracy of the analysis result is confirmed. Therefore,
the analysis result is able to be used to evaluate the effect ofparasitic parameters in the PCB and design of the circuits
such as snubber circuit parameters.

Port 2 -

5.0
4.0
3.0
2.0
1.0
0.0

10 k

100k1M
Frequency f Hz(b) Resistance of jig.
Fig. 5 Parasitic-parameter of jig.

Parasitic inductance LPCB nH

70Analysis

605040Measurement

3020
10010 k100k

1MFrequency f Hz

10M

100M

(a) Parasitic inductanceParasitic resistance RPCB mW

66.9%. The resonant frequency of the surge voltage in theexperiment shows good agreement with the simulation in thefirst period. However, the frequency and decay of theoscillation of surge voltage do not match after the secondperiod.
The difference in the waveforms is caused by employing
ideal components in the simulation. In particular, the effectof ESR (equivalent series resistance) and ERL (equivalentseries inductance) in the capacitor should not be ignored inmegahertz switching circuits.
In order to simulate the waveform more accurately,parasitic parameters, such as ESR and ESL, should beconsidered. Hence, the parasitic parameters of passive
components are measured using the vector network analyzer.
Table 3 shows the measured value of the passive components
and reference value. The capacitance Cf1 cannot be measured
by the test fixture for SMD due to the size, so only thereference value is shown. The measured value of the passivecomponents is modeled and used in the following simulation.
Figure 8 shows the simulated waveform with the passive
components model. The surge voltage amplitude is almost thesame compared to the ideal model waveform, and the error of
the ringing period remains. However, the decay of the surge
voltage, especially the end of the ringing, shows more good
agreement by employing passive components model based on
the measurement.

1008060

Analysis40200

Measurement
10 k

100k

1M
Frequency f Hz

10M

100M(b) Parasitic resistanceFig. 6. Parasitic-parameter.
Table 2. Parameter of device model.
Drain side inductanceSource side inductance
Drain side resistanceSource side resistance
Output capacitanceIV. SNUBBER CIRCUIT PARAMETER AND SURGE VOLTAGE

Surge _ voltage _ rate vsurge _ max  VDC
VDC

 100 ........... (3).

The surge voltage rate, which is evaluated with passivecomponents models, is more accurate in comparison with theresult without the models of the passive components. Theerror is 16.4% between simulated surge voltage rate with thepassive components models, and experimental result at acapacitance Cf4 of 100 pF.
However, the difference in the surge voltage rate is stillhigh when the snubber capacitance Cf4 is 0 pF and 400 pF.
Because the errors, such as the measurement or the modelingerror of the passive components, the models error of the GaNtransistor, or the error of the analysis result of the PCB, still
remain.

100Analysis(with boad data)
Analysis(without boad data)60
vds1 [V]1.5 nH
1.0 nH
40 mΩ
8.5 mΩ
200 pF (at. 6.78MHz)

20 ns/div

80

40200Experiment-20

Fig. 7. Analyzed and measured vds1 waveform.
Table 3. Parameter of the passive components.
components
L
Cf1 (B58031I5105M062)
3 nH
Cf2 (C5750X7T2J474M250KE)
Cf3 (C3216C0G2J471J085AA) 1.2 nH
Cf4 (C3216C0G2J101J060AA) 1.2 nH
Rf (RC1206FR-071RL)-1008060

vds1 [V]The surge voltage is simulated accurately by employing
the model of passive components. It is possible to consider
methods to suppress the surge voltage at the circuit designphase.
As the first step of the design of snubber circuit
parameters, the snubber capacitance Cf4 and the resistance Rf4
is changed to investigate the effect to the amplitude of thesurge voltage in the simulation. Snubber capacitance Cf4 ischanged from the capacitance as same as the output
capacitance Coss of the devices. The capacitance of 0pF(without capacitor), 100 pF (half of the Coss), 200 pF( thesame value to the Coss), and 400 pF (two times of the Coss) is
selected for the simulation.
Figure 9 shows the surge voltage rate of the drain-source.
The surge voltage rate is expressed asLdLsRdRs
C oss

20 ns/div

ReferenceCR1 uF12 mΩ
0.47 uF 11 mΩ
470 pF 102 mΩ
100 pF 171 mΩ
1Ω

L
6.3 nH
4.4 nH7.0 nH
4.9 nH

Measurement
CR496 nF 195 mΩ
456 pF 269 mΩ
98 pF
790 mΩ

Analysis (with components model)
Analysis(without components model)

40200-20ExperimentFig. 8. Analyzed and measured vds1 waveform with passivecomponents model.

V. CONCLUSION

The surge voltage is simulated accurately by using theanalyzed PCB pattern and passive components model, which
is based on the measurements. The maximum surge voltage
and the decay of the ringing show good agreements between
analysis and experiment, comparing to the case without
passive components model. However, the error of the ringing
period still remains.
The surge voltage with changing the snubber capacitor isevaluated in order to make the relationship between the surge
voltage and the snubber circuit parameters as the first step of
the parameter design by using simulation. The maximum
surge voltage value with changing the snubber capacitor isinvestigated.
In the future work, the error between the measurement
and analysis will be compensated for more accurate
simulation.
ACKNOWLEDGMENT
This work was supported by Council for Science,
Technology and Innovation (CSTI), Cross-ministerial
Strategic Innovation Promotion Program (SIP), “Energysystems of an Internet of Energy (IoE) society” (Fundingagency:JST).
REFERENCES
[1]

[2]

[3]

[4]

J. Li and D. Costinett, "Comprehensive Design for 6.78 MHz WirelessPower Transfer Systems", 2018 IEEE Energy Conversion Congressand Exposition (ECCE), Portland, OR, 2018, pp. 906-913.
L. Jiang and D. Costinett, "A High-Efficiency GaN-Based Single-Stage
6.78 MHz Transmitter for Wireless Power Transfer Applications," inIEEE Transactions on Power Electronics, vol. 34, no. 8, pp. 7677-7692,
Aug. 2019, doi: 10.1109/TPEL.2018.2879958.
N. K. Trung, T. Ogata, S. Tanaka and K. Akatsu, "Attenuate Influenceof Parasitic Elements in 13.56-MHz Inverter for Wireless Power
Transfer Systems," in IEEE Transactions on Power Electronics, vol. 33,
no. 4, pp. 3218-3231, April 2018.
N. K. Trung and K. Akatsu, "Design challenges for 13.56MHz 10 kW
resonant inverter for wireless power transfer systems", 2019 10thInternational Conference on Power Electronics and ECCE Asia (ICPE
2019 - ECCE Asia), Busan, Korea (South), 2019, pp. 1-7.

Surge voltage rate %This paper presented the surge voltage simulation using
the analysis result of the PCB pattern. The parasitic
parameters on the PCB pattern are analyzed accurately using
electromagnetic analysis. Comparing to the measurement
result, the error rate of the analyzed parasitic inductance isonly 3.8% at 6.78MHz.

100
Simulation(without passive components models)

80
60
40Simulation(with passive components models)

200Experiment
0100200
Snubber capacitor Cf4 [pF]

Fig. 9. Surge voltage rate.

400