Experimental Verification of an EMC Filter Used
for PWM Inverter with Wide Band-Gap Devices
Jun-ichi Itoh, Takahiro Araki and Koji Orikawa
Department of Electrical, Electronics and Information Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp, arakit@stn.nagaokaut.ac.jp, orikawa@vos.nagaokaut.ac.jp
Abstract— This paper discusses a volume of an EMC
filter and a cooling system that are used for a PWM inverterwith wide band-gap devices. At first, the volume of reactor
that is used for EMC filter such as common mode coke coils
and differential mode choke coils are estimated bytheoretically. Then, the relationship between the carrier
frequency of the PWM inverter and the total volume offilter reactors are clarified by simulation. Moreover, therelationship between the carrier frequency and the volume
of a cooling system is calculated based on experimental
results. As a result, the total volume of the inverter systemthat contains filter reactors and cooling system will be
reduced by 54% at the carrier frequency of 300 kHz byusing a two stage filter compared to case of the carrier
frequency of 150 kHz by using one stage filter. In addition,
an induction motor is driven by a prototype of GaN-FET
inverter system with a 300-kHz carrier frequency. As aresult, the conduction noise is suppressed below the limit of
CISPR. Therefore, the proposed design method for EMC
filters is valid in the experiment. Furthermore, the power
loss of EMC filter is less than 2% compared with the total
loss of the GaN-FET inverter system.
Keywords— EMC filter; High-frequency switching; PWM
inverter; Wide Band-Gap Devices

I.

INTRODUCTION

Recently, the fast switching and low on-state voltage
drop are required for power conversion circuits in orderto reduce the power loss. However, silicon based
switching devices such as Si-MOSFETs and Si-IGBTs,
are difficult to achieve a significant performance
improvement because those devices performance isalmost reaching the limit that the derived from thephysical properties of silicon. On the other hand, theswitching devices based on a wide band-gap
semiconductor such as gallium nitride (GaN) or siliconcarbide (SiC) has been studied in recent years [1-3].
Those wide band-gap devices can perform fast-switching
and features low on-voltage drop compared with thenormal silicon devices under the high temperature
operation.
The one of problems of the wide band-gap device iscost. Therefore, it is expected that the wide band-gap
devices are used for general power converter. The power
conversion circuit with wide band-gap devices has beenstudied to achieve high efficiency in a high temperature

operation[4-12]. However, it seems that the performanceand the miniaturization effect are not discussed inprevious studies.
Authors have been focused on the volume of an EMC
filter for PWM inverter. The PWM inverter can control
the output voltage and output frequency by using
switching devices. However, the noise occurs at theswitching because the voltage and current are change
rapidly. Recently, this noise becomes lager because thefast switching devices such as wide band-gap devices areapplied to the PWM inverter in order to reduce theswitching loss. The noise may cause a false operation ofsurrounding control system. Hence, it is limited by someregulations such as CISPR (Special international
committee on radio interference). In order to suppress thenoise which is emitted from the PWM inverter, the EMC
filter that is constructed by passive components such as
inductor and capacitor is added to the input of theinverter system. In addition, the PWM inverter becomes
smaller depending on the high performance switching
device and development of cooling technique. Thus, thevolume of the EMC filter must be considered in order tominiaturize the inverter system.
The volume of the EMC filter is determined by theattenuation rate and frequency of the noise. The noisethat is emitted form a PWM inverter is varied by carrier
frequency. Therefore, the EMC filter is miniaturized
when the switching frequency is higher and higher. In
contrast, the switching loss is increased by the highfrequency switching. Consequently, the cooling system
becomes larger. Therefore, the volume of the coolingsystem must be considered for minimizing the EMC filter
under a high frequency switching operation. Although the
EMC filter design method are reported at constant carrier
frequency [13-14], it seems that the relation between the
power converter volume and the carrier frequency has notbeen discussed concretely through the experiments inpast works.
In this paper, the relationship between the carrier
frequency and the total volume of the inverter system is
discussed based on simulation and experiments using
GaN-FET inverter. At first, the loss and the volume
estimation method of the inverter system is mentioned.

Second, the design method of the multi stage EMC filter
is clarified. Then, the relationship between the carrier
frequency of the PWM inverter and the volume of filter
reactor is clarified by simulation, besides the relationshipbetween the carrier frequency and the volume of acooling system. At last, a prototype of GaN-FET inverter
is demonstrated by experiments using an R-L load and an
induction motor. Power loss and conducted emission of
the system are shown. As a result, it is confirmed that the
total volume of GaN-FET inverter system can be reduced
to 54% compared to the case of a single stage EMC filterby using a two stage EMC filter.
II.

VOLUME ESTIMATION METHOD

A. Power Loss of Switching Devices
Fig. 1 shows the system configuration of the PWM
inverter with GaN-FET. The switching loss of eachdevice PSW is calculated by (1) [15].
VDC I mPSW =eon + eoff f carrier ······························ (1)4πVDCd I md
where fcarrier is the carrier frequency, VDC is DC link
voltage, Im is the maximum output current, eon and eoff
are turn on and turn off energy of each switching, and
VDCd and Imd are voltage and current that described ondatasheet for measuring the switching time.
Table1 shows the simulation parameters that are used
for design of the EMC filter and cooling system.
The total loss generated in the switching devices Ploss
which be composed of the conduction loss and theswitching loss, is calculated by (2).
2⎛⎞I
Ploss = 6(PSW + PCON ) = 6⎜⎜ PSW + m RON ⎟⎟ ···················· (2)2⎝⎠where RON is the on-state resistance of the FET.

()

B. Volume of Cooling Systems
The PWM inverter needs cooling system such as heatsinks and fans because the switching devices are heatedby the switching loss and the conduction loss. Generally,cooling system is designed based on a thermal resistance.
However, the thermal resistance depends on its volume.
Therefore, CSPI (Cooling System Performance Index) is
introduced to estimate the volume of cooling system. The
CSPI indicates the cooling performance per unit volumeof the cooling system which is a reciprocal of the productof the volume and the thermal resistance. It means that ahigh performance cooling system shows high CSPI.
Therefore, the cooling system is miniaturized when CSPI
become higher. The volume of the cooling system
volcooling is given by (3) [16].
Ploss1················· (3)vol cooling ==Rth × CSPI (T j − Ta ) × CSPI
where Rth is the thermal resistance of the cooling system,
Tj is the junction temperature of the switching device, andTa is the ambient temperature.
C. Design method of multi stage EMC filter
Fig. 2 shows the circuit schematics of multi stage EMC

Fig. 1. Circuit configuration of three phase PWM inverter
that is constructed by GaN-FET.
Table 1. Simulation parameters that is used fordesigning the EMC filter and cooling system.
Input voltage Vin
200 V
Input frequency fin
50 Hz
DC voltage Vdc
282 V
Output voltage Vout
173 V
Output current Iout
1.9 A
Output frequency fout
50 Hz
Load impedance Zload
53 Ω
0.99
Power factor cosφ1
Modulation ratio α
CSPI
3
On-resistance RON
100 mΩ
Dead time Td
100 nsAmbient temperature Ta
20 ℃
Junction temperature Tj
100 ℃
Load factor k
0.1
Lead angle φ10π/180 rad
Leakage current Ileak
1 mA

Fig. 2. Circuit schematics of multi stage EMC filter.

filter. In this paper, the multi stage EMC filter isconstructed by connecting the single stage EMC filter inseries. Each filter that has different number of stages isdesigned to get a same attenuation. In addition, thecapacitance of X capacitors and Y capacitors are divided
equally for all stages.
At first, the X capacitor that suppresses the fluctuationsof the input voltage is designed by (4) using an allowable
lead angle of input current φ because it reduces the power
factor at the light load.
C Xn =

3kI in(1 − cos φ ) ······································ (4)2nωVin cos φwhere k is the load factor (output power/maximum

power), Iin is the input current, n is number of filter stage,ω is the input frequency, and Vin is the input voltage.
If the lead angle of the input current φ is small, (4) is
simplified as (5).
3kI in φ························································· (5)C Xn =nωV inSecond, the Y capacitor that bypass the common modecurrent is designed by (6) based on the acceptableleakage current Ileak.
3 I leak·························································· (6)C Yn =nωV inFinally, the inductance of differential mode choke coils
and common mode choke coils Ln are designed by (7) inorder to suppress the conduction noise below the limit of
CISPR. Also, the common mode noise and thedifferential mode noise are separated in order to evaluate
the each noise [17].
1Ln =········································· (7)12ω Att C n G 0 − G f n()

Fig. 3. Conduction noise evaluation systemused in simulation.
Table 2. Experimental conditions to measure the power
loss of GaN-FET inverter with RL load.
Input voltage Vin
100 V
Input frequency fin
50 Hz
DC link voltage VDC
140 V
1Modulation ratio α
Output frequency fout
20 Hz
Load impedance Zload
51 Ω
0.99
Power factor cosφAmbient temperature Ta
25 ℃
Dead time Td
100 nswhere ωAtt is the designed frequency of the LC filter, G0
is the peak value of the conduction noise without the
EMC filter, and Gf is the limit of CISPR.
D. Volume of EMC Filter
According to (5) and (6), the capacitance of X
capacitor and Y capacitor is not changed by the carrier
frequency. Also, the total capacitance is same regardlessof the number of EMC filter stages. Therefore, thevolume of those capacitors is not considered.
On the other hands, the reactor volume is changed
significantly by the parameter of the component. There
are several ways to select the core for the reactor. In thispaper, the reactors are designed by the Area Productconcept [18] using a window area and a cross-sectional
area. Therefore, the volume of the reactor volL is given by(8).
3⎛ 2W ⎞ 4⎟ ·············································· (8)vol L = K v ⎜⎜⎟⎝ K u Bm J ⎠where Kv is the constant value depending on the shape ofcores, W is the maximum energy of the reactor, Ku is theoccupancy of the window, Bm is the maximum flux
density of the core, and J is the current density of the wire.
III.

VOLUME EVALUATION OF INVERTER

A. Simulation conditions
Fig. 3 shows the conduction noise evaluation system.
The capacitors are added between the switching devices
and FG, and the output voltage midpoint and FG in orderto model the stray capacitances of a general inverter [14].
In this paper, modeled LISN and a spectrum analyzer isused to estimate the conduction noise by the simulation[19].
B. Experiomntal conditions
Table 2 shows the circuit parameters on experiment.

Fig. 4. The relationships between the number of filter stageand volume of filter reactor.
The GaN-FETs (VDSmax = 600 V, IDmax = 10 A, RON = 100mΩ) are used for the PWM inverter to achieve the 300kHz switching, and the Si-diodes are used as a rectifierpart to evaluate the conduction noise generated by the
inverter unit. The PWM inverter is controlled by V/fcontrol. The PWM signals are generated by comparing
the triangle wave and the output voltage command. The
conduction noise generated by control circuit is deducted
to evaluate the conduction noise of inverter.
C. Volume of filter reactor
Fig. 4 shows the relationships between the number offilter stage and the volume of differential mode chokecoil if the carrier frequency of PWM inverter is 300 kHz.
The volume of filter reactor for the case of single EMC
filter is applied to the inverter system is used as astandard volume regardless of the attenuation of EMC
filter. In addition, the volume of X capacitors and Y
capacitors are assumed as same regardless of the numberof filter stages because the total capacitance of each filter
is same. Owing to this, the EMC filter becomes smallest
if the volume of filter reactor is smallest by selecting thesuitable number of filter stage.

D. Loss analysis results
Fig. 6 shows the power loss that is measured from the
GaN-FET inverter. The maximum efficiency is 94.7%
when the carrier frequency is 150 kHz.
The conduction loss is given by y-intercept ofapproximate formula b because it is not related to carrier
frequency. On the other hands, the switching loss of
PWM inverter is given by slope of approximate formula.
From experimental results, the conduction loss andswitching loss on arbitrary output power is calculated by(9) and (10)1.0

1p.u.=0.0433 dm3 at fcarrier=150kHz, one stage

0.8

Three stages

0.6
0.4

One stage

0.2 Two stages
0
150

300
450
Carrier frequency [kHz]600(a) Differential mode choke coil
1.0

1p.u.=0.293 dm3 at fcarrier=150kHz, one stage

0.8
0.6

Three stages

0.4
0.2

One stage
Two stages

0
150

300
450
Carrier frequency [kHz]600(b) Common mode choke coilFig. 5. Volume of filter reactor.
14
Total power loss [W]

According to Fig. 4, the filter reactor becomes smallest
for the case of two stage filter is applied if the attenuationof filter is 30 dB. On the other hands, the single stage
filter is smallest if the attenuation of filter is 10 dB.
Moreover, the three stage filter is the smallest if theattenuation of filter is 50 dB. Consequently, the numberof filter stage that achieve smallest filter is decided by therequired attenuation of the filter.
Fig. 5 shows a relationship between the carrier
frequency and the volume of filter reactor. The volume offilter reactor for the case of single EMC filter and 150
kHz-carrier frequency is applied to the inverter system isused as a standard volume.
According to Fig. 5 (a) and Fig.5 (b), the volume ofdifferential mode choke coil and common mode chokecoil are reduced by high switching frequency because theattention of LC filter is large at the high frequency region.
In addition, the filter reactor becomes smaller regardlessof the number of filter stages. As is well known, from150 kHz to 30 MHz of conduction noise is limited by
CISPR. That is, the carrier frequency is match to thelowest frequency of limited band if the carrier frequency
is 150 kHz. In other words, the filter reactor becomeslargest if the carrier frequency is 150 kHz.
Besides, the choke coils of multi stage filter areminiaturized compared with the single stage filter. If thenumber of filter stage is increased from one to two, thevolume of filter reactor becomes half when the carrier
frequency is 150 kHz. Downsizing of EMC filter using
multi stage filter can achieve high efficiency because theswitching loss does not increase due to without theincreasing of switching frequency. On the other hand, thecomponents that construct the EMC filter such as chokecoils and capacitors are increased in proportion to thenumber of filter stages. Because of this, the two stage
filter is smaller compared with three stage filter.
The volume of filter reactor is almost same regardlessof the number of filter stages when the carrier frequency
is 600 kHz. In this case, the filter reactor is notminiaturized by using multi stage filter because filter
reactor is already downsized by high switching frequency.
Thereby, the multi stage filter is not suitable because
number of components is increased when the carrier
frequency is 600 kHz.

Ptotal=1.47×10-5fcarrier+4.67

12
10
8
6
150

300
450
Carrier frequency [kHz]600

Fig. 6. Measurement result of relationship between
carrier frequency and power loss of GaN-FET inverter.
2⎛ I out _ calc ⎞⎟ ·············································· (9)PCON = b × ⎜⎜ I out _ test ⎟⎠⎝V DC _ calc I out _ calc·······························(10)PSW = af carrier
V DC _ test I out _ test

where Iout_calc is the output current on arbitrary output
power, and Iout_test is the output current when the power
loss is measured in experimental.
Fig. 7 shows loss analysis results of GaN-FET inverter
based on experimental results. The conduction loss islarger than switching loss when the carrier frequency is
150 kHz. However, the switching loss become larger if
the carrier frequency is higher than 300 kHz. In otherwords, the switching loss has an insignificant effect on
total loss in low carrier frequency region. Consequently,
the proposed system can downsize the EMC filter
without increasing the volume of cooling system in low
carrier frequency region. Therefore, the PWM inverter
that can achieve low switching loss is suitable for
proposed system.
The rate between switching loss and conduction loss of

E. Power density of GaN-FET inverter
Fig. 10 shows the relationships between the carrier
frequency and total volume of inverter system that
contains filter reactors and cooling system. The volume
of other components is not included because it notdepends on carrier frequency. According to Fig.10, theinverter system is miniaturized by high frequency
switching because the volume filter reactors are
decreased sharply. On the other hand, the cooling system
is getting larger when the carrier frequency is higher than
300 kHz. Moreover, the volume of inverter system isreduced by using multi stage filter because the attentionof LC filter is significantly increased. As a result, thetotal volume of GaN-FET inverter system will be reducedby 54% at the carrier frequency of 300 kHz by using a
two stage filter compared to case of the carrier frequencyof 150 kHz by using one stage filter.
Fig. 11 shows the relationships between the carrier
frequency and the power density of the inverter system. It
means that a high efficiency and small inverter systemshows high power density. In this paper, the power
density ρpower is defined as (11) by using the rated powerof PWM inverter Pout and the total volume of inverter
system that contains filter reactors and the cooling system.
Pρ power = out ······················································ (11)
vol total
The power density is inverse proportion to the total
volume of the system. Therefore, the power density
becomes the highest at the carrier frequency of 300 kHz.
Similarly, the power density becomes highest if thetwo stage filter is applied to the inverter system. In thissystem, the power density is insignificantly changed even
if the carrier frequency becomes higher because EMC
filter is already downsized. In other words, thedownsizing of EMC filter by high frequency switching ismost effective if the single stage filter is applied.
Generally, the design of multi stage filter is complicatedowing to the increasing of components. Therefore, thedesign of EMC filter becomes easier if the single stage
EMC filter is miniaturized by high frequency switching.
Fig. 12 shows Pareto front curves of GaN-FET inverterat the range of carrier frequency from 150 kHz to 600
kHz. The Pareto front curves are used for determine thePower loss [%]PWM inverter depends on the characteristics of switching
device. Thus, the GaN-FET is suitable for proposedsystem because it can perform fast switching and low
switching loss.
Fig. 8 shows the calculation result of power loss if theinverter outputs the rated power. In this case, theconduction loss accounts more portions in a total loss
because conduction loss is proportional to the square of
the output current.
Fig. 9 shows the relationship between carrier
frequency and volume of cooling system. The volume ofcooling system is calculated by (3) based on experimental
results. The cooling system becomes large at the highfrequency region.

Fig. 7. Breakdown of power loss of GaN-FET inverter
based on experimental results.

Fig. 8. Calculation result of relationship between
carrier frequency and power loss of GaN-FET inverter.

Fig. 9. Relationship between carrier frequency
and volume of cooling system.
1.0
1p.u.=0.474 dm3 at fcarrier=150kHz, one stage
0.8
Three stages
0.6

0.4
150

One stage
Two stages
300
450
Carrier frequency [kHz]600

Fig. 10. Relationship between carrier frequency
and total volume of GaN-FET inverter system.

F. Measurement results of conduction noise
Fig. 13 shows the prototype of GaN-FET inverter
system. Three PCB boards are used to construct the threephase PWM inverter. Two GaN-FETs are mounted oneach PCB board and connected in series. This inverter iscontrolled by Peripheral Interface Controller and logic
ICs. The Si-diode rectifier and the GaN-FET inverter are
mounted on another heat sink, and both heat sinks are notconnected to the earth.
Fig. 14 shows the conduction noise of the PWM
inverter with GaN-FET. The red line indicates the limitof CISPR. It is noted that the carrier frequency is 300
kHz. In Fig. 14 (a), the two stage EMC filter is connectedto the input of inverter system. Additionally, theresistance and inductance are connected to the output of
inverter system as a load. As a result, the conduction
noise is suppressed below the limit of CISPR. Therefore,
the proposed design method for EMC filters is valid in
the experiment.
Fig. 14 (b) shows the conduction noise when the single
stage EMC filter is applied to the inverter system. At 9
MHz, the conduction noise is over the limit of CISPR.
That is because the attenuation of multi stage filter islarger than that of single stage filter at high frequency
region.
On the other hand, the conduction noise at 300 kHz isalmost same compared with Fig. 14 (b). It means theattenuation of single stage filter and multi stage filter aresame at the designed frequency of the filter. Therefore,
the proposed design method of EMC filters is valid
regardless of the number of filter stage.
IV.

Fig. 11. Relationship between carrier frequency
and power density of GaN-FET inverter.

Efficiency [%]optimum point in order to achieve many objectives. The
horizontal axis in Fig. 11 indicates the power density, andthe vertical axis in Fig. 11 indicates the efficiency of the
GaN-FET inverter. Therefore, the inverter system canachieve the high efficiency and the smaller size if thePareto front curve comes close to top right of the graph.
According to results, the EMC filter should beconstructed by two stage filter in order to achieve highpower density and high efficiency. In addition, the power
density becomes highest at the carrier frequency is 300
kHz, and the efficiency of GaN-FET inverter becomes
highest at the carrier frequency is 150 kHz.

Fig.12. Pareto front curve of GaN-FET inverter.
(Relationship between power density andefficiency of GaN-FET inverter)

MOTOR DRIVE EXPERIMENT

A. Experimental condition
Fig. 15 shows the system configuration when the
induction motor is driven by GaN-FET inverter. The
ground terminal of EMC filter and induction motor areconnected to the ground terminal of LISN. Similarly, theheat sink of the GaN-FET inverter is connected to the
LISN.
Table 3 shows the experimental condition. In thiscondition, the designed value of differential mode chokecoil is smaller than the leakage inductance of common
mode choke coil. Thereby, the differential mode chokecoil is assumed as leakage inductance of common mode

Fig. 13. Prototype of GaN-FET inverter.

choke coil.
B. Experimental results
Fig. 16 shows the power loss of the prototype inverter
system. It is noted that the power loss of GaN-FET
inverter that is proportion to the carrier frequency isdefined as switching loss. Also, the power loss that is notproportion to the carrier frequency is defined as
conduction loss.
From the experimental results, the efficiency of GaNFET inverter is low. That is because the power factor islow due to the drive of the induction motor by V/f control
at no load. In contrast, the power loss of EMC filter isless than 2% compared with the total loss of the GaNFET inverter system.
Fig. 17 shows the conduction noise when the induction
motor is driven by GaN-FET inverter. From the result,the conduction noise is suppressed below the limit of
CISPR. Therefore, the proposed design method for EMC
filters is valid in the experiment regardless of the load of
inverter system.
In addition, the conduction noise in the low frequency
region is increased compared to the Fig. 14 (a) because
the DC voltage of the inverter system is high. Hence, thenoise generated by the switching becomes larger.
Moreover, the conduction noise around 9 MHz is
decreased because parasitic capacitance of the load ischanged compared to the R-L load.
V.

CONCLUSIONSIn this paper, the relationship between the carrier
frequency and the total volume of the GaN-FET inverter
system is discussed based on simulation and experiments.
As a result, the total volume of GaN-FET inverter systemthat contains an EMC filter and a cooling system will be
reduced by 54% at the carrier frequency is 300 kHz byusing a two stage filter compared to case of the carrier
frequency of 150 kHz by using one stage filter.
In addition, an induction motor is driven by aprototype of GaN-FET inverter system with a 300-kHz
carrier frequency. As a result, the conduction noise issuppressed below the limit of CISPR. Therefore, theproposed design method for EMC filters is valid in theexperiment. Furthermore, the power loss of EMC filter isless than 2% compared with the total loss of the GaNFET inverter system.
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Others

Input power=103W at fcarrier=150 kHz

Filter loss

30
Rectifier loss
20
Switching loss
100Conduction loss
150

300
450
Carrier frequency [kHz]600

Fig. 16. Power loss of prototype inverter system
when drive the induction motor V/f control.

Fig. 17. Conduction noise of the prototype inverter systemwith induction motor.