FRT Capability of Single-phase Grid-connected
Inverter with Minimized Interconnected Inductor
Satoshi Nagai, Keisuke Kusaka and Jun-ichi Itoh
Department of Electrical Engineering
Nagaoka University of Technology, NUT
Nagaoka, Niigata, Japan
Satoshi_nagai@stn.nagaokaut.ac.jp, kusaka@vos.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp

Abstract— This paper proposes a fault-ride-through (FRT)
method for a single-phase grid-connected inverter with a minimized inductor by reducing the inverter output current overshoot. When a low-inductance interconnected inductor is used,
the inverter output current overshoot becomes very high at a
voltage sag and a voltage recovery. Therefore, a grid-voltage
fault stops the operation of the grid-connected inverter due to an
overcurrent protection. In the proposed method, the current
overshoot is suppressed by using a momentary gate-block with ahigh-performance disturbance observer. Moreover, the inverter
output current in steady state is also stabilized by using the highperformance disturbance observer. Consequently, by using the
proposed method, the grid-connected inverter continues to operate without interruption during the fault of the grid voltage. The
maximum overshoot rate of the inductor current at the voltage
recovery moment after fault clearance is reduced from 534% in
the conventional method to 46.5% in the proposed method.
Keywords—Grid-connected inverter; Fault ride through; Gateblock; Disturbance observer; Interconnected inductor.

I.

INTRODUCTION

In recent years, photovoltaics systems (PV) have been actively studied for low carbon emission [1]-[2]. In order to supply the power to single-phase grid, a power conversion system(PCS) is used. PCSs have been required to reduce the cost andsize. In particular, a minimization of the interconnected inductor in the PCS is necessary in order to increase the power density of the PCS [3]-[5]. This inductor can be minimized by reducing the inductance with high switching frequency. However, the inductance reduction of the inductor leads to the decrease in the disturbance suppression performance [6]. Moreover, the PCS is required to continue the operation during a
voltage sag without disconnecting from the grid [7]-[12] inorder to meet the fault ride through (FRT) requirements. Whenthe inductance is reduced, the inverter output current overshootbecomes very high at a voltage sag and a voltage recovery. In
order to meet the FRT requirements, the output current overshoot rate has to be less than 50% of the rated current. Therefore, it is not that simple to minimize the inductor by only increasing the switching frequency.
In a conventional FRT method, a reactive current is flown
by the grid-connected inverter during the voltage sag in order
to avoid the interruption of the inverter operation. In general,

the interconnected inductor is usually designed in such a waythat the impedance of the inductor is about %Z = 5% of thebase impedance of the system. In this case, the grid-connected
inverter can simply achieve FRT requirements because theinductor impedance is large, i.e. small current overshoots at
grid fault. When the inductor is minimized, high current overshoots occur at the voltage sag and the voltage recovery. Furthermore, the conventional method is controlled by a low speed
controller, e.g. Digital Signal Processor (DSP). Thus, it is difficult to suppress the inverter output current overshoot by the
low speed control of DSP. As a conclusion, when the gridconnected inverter with the low inductance of the inductor isapplied with the conventional FRT method, it is difficult tosatisfy the FRT requirements due to the high inverter-outputcurrent overshoot.
If the conventional FRT method employs a highperformance disturbance observer, it is observed that the disturbance observer can compensate for the disturbances causedby the voltage sag and the voltage recovery. Thus, the inverter
output current overshoot can be suppressed by the highperformance disturbance observer. However, this method needs
a high speed sampling and high speed PWM (Pulse Width
Modulation) control, because the voltage sag and the voltage
recovery are the disturbances which vary in very high speed.
Therefore, the high-performance disturbance observer is still
difficult to meet the FRT requirements
This paper proposes the FRT method that employs thehigh-performance disturbance observer realized on a fieldprogrammable gate array (FPGA) and a momentary gate-block.
The proposed FRT method has a current threshold to detect thevoltage sag or the voltage interruption. When the inverter output current exceeds the current threshold, the inverter output
current overshoot is suppressed by the momentary gate-block.
The proposed method is confirmed by a 1-kW prototype with
%Z of 1%. Furthermore, a zero voltage ride through (ZVRT) of
the single-phase grid-connected inverter, i.e. the most stringent
standards of the FRT requirements, is verified with the proposed FRT method. Moreover, the suppression of the inverter
output current overshoot is confirmed at both the voltage interruption and the voltage recovery during the grid fault.

II.

FAULT-RIDE-THROUGH CONTROL METHOD

Fig. 1 shows a circuit configuration of a single-phase gridconnected inverter. In this paper, a single-phase two-level inverter is employed due to its simplicity. By reducing the inductance L in order to minimize the inductor, the overshoot of
the inverter output current iout becomes very high at the voltage
sag. The high current overshoot stops the grid-connected inverter due to an overcurrent protection. Therefore, the gridconnected inverter with a minimized inductor cannot achieve
the FRT requirements.
Fig. 2 shows a reactive current control block for the FRT
operation. The phase θ is locked by phase locked loop (PLL)
based on the grid voltage detection value vac. During the voltage sag, the detection signal vfrt becomes high level, and thecurrent phase θ' is the sum of the grid voltage phase θ and π/2.
The reactive current control is realized by generating a current
command value with the current phase θ'.
Fig. 3 shows the control block diagram of the conventional
FRT operation where Vdc is the input DC voltage, Td is thedead-time period, iLdet is the inductor current detection value− sT
and fsw is the switching frequency, and e delay is the delay timeof the current detection and the A/D conversion. The current
controller is implemented by digital signal processor (DSP).
Moreover, a dead-time error voltage of the inverter output iscompensated by calculating the dead-time error voltage compensation at a steady state operation. When the inductance islow, it is difficult to compensate the grid disturbance by increasing the disturbance gain. Therefore, the inverter output
current overshoot becomes high at the voltage sag due to theuse of the conventional FRT control method.
Fig. 4 shows the control block diagram of the FRT operation with a disturbance observer, which has been proposed in[13]-[18]. It is possible to compensate a disturbance by thehigh-performance disturbance observer, which is implemented
on the FPGA. The disturbance compensate voltage is estimated from the output current and the voltage command,vˆdis =

(

)

ωc
*
v
+ ωc LiLdet − ωc Li Ldet
ωc + s conv

(1)

where, ωc is the cutoff angular frequency of the disturbanceobserver and vconv* is the output voltage command. The current
controller is implemented by DSP. On the other hand, the disturbance observer is implemented by the FPGA. At the steadystate operation, it is confirmed that the disturbance observer
compensates the output voltage error such as the dead-timeerror voltage and the voltage drop on the switching devices[19]. However, the amount of the inductor current variation islarge at the voltage drop and the voltage recovery. Therefore,
even if the high-performance disturbance observer is implemented in the inverter, the inverter output current overshootmay still become very high at grid faults.
Fig. 5 shows the control block diagram of the disturbanceobserver with the momentary gate-block for the FRT operation.
The proposed control method is employed by the FPGA. The

Fig. 1. Single-phase inverter circuit with LC filter. The inductance L is
reduced by increasing the switching frequency.

θ'

θ
π

θfrt

2

θfrt

π 2

Fig. 2. Reactive current control method for FRT operation. When voltage sag occurs, the phase θ' becomes leading by π/2 from θ.

sin(θ' )
1
V dc

e

1
sL

− sTdelay

Fig. 3. Control block diagram of conventional FRT operation. In theconventional method, the current controller is implemented by DSP.
FRT Control
DSP

sin(θ' )

iL*

+
-

iLdet

PI

Control System
FPGA
vconv*
+
+
c

v̂dis

- + s

c

+
+

Circuit+ v
vdead+ vdis ac

1
V dc

Vdc +

1
sL

iL
− sTdelay

c

e

L

iLdet

Fig. 4. Control block diagram of FRT operation with disturbance observer. The high-performance disturbance observer is still difficult tocompensate large disturbances such as voltage sag.

momentary gate-block signal OC_L and the voltage sag determination signal FRT_ST are determined by

(
(

)
)

(2),

)
)

(3),

0 iLdet ≥ I ref _ OC
OC_L = 1 iLdet < I ref _ OC((

0 vr _ th ≤ vrdet

FRT_ST = 
1 vr _ th > vrdet

where Iref_OC is the gate-block threshold of the inverter output
current overshoot, vr_th is the grid voltage lower threshold, vrdet
is the detected value of the grid voltage. When OC_L is zero,
the momentary gate block is active. The gate-block period is
the same as one period of the carrier. The integrator of the disturbance observer is initialized at the gate-block period after
the voltage drop. After that, the gate-block is released in order
to continue to operate the inverter. Note that the current over-sin(θ' )ωc Lv̂ disωcf so

Fig. 5. Control block diagram of ZVRT operation by using high-performance disturbance observer with momentary gate-block.
By using the gate-block, the inverter output current overshoot is suppressed at the voltage drop and the voltage recovery.
80 kHz (12.5 s)
40 MHz (25 ns)
0.......

4

5

X2

X1

6

.......

500

501

X3

X4

X5

ωc

.......

505.......

1000

Clock
(40MHz)
iLdet
HPF
cL

X6

v̂ dis

X5
X6

f so

0

1

vconv*

Y2.......

500

501

Y3

Y4

.......

505

506.......

1000

Clock
(40MHz)
Y5

LPF
Y1

Y5

ωc

Y1

v̂ disf soFig. 6. Timing chart of FPGA controller for high-performance disturbance observer.
X3, X5, Y3 and Y5 are changed by table of MUX1 and MUX2 in fig. 5.

shoot rate should be less than 50% of the rated current in order
to meet the FRT requirements.
Fig. 6 shows the timing chart of the HPF and the LPF in
FPGA for implementing the high-performance disturbanceobserver. In the HPF, the multiplying result of X2 is outputtedwith the delay of approximately 100 ns from the detected current of the interconnected inductor iLdet. The subtracting result
X1 is outputted after one clock. Note that one clock equals to 25
ns. X3 is one-sampling-period-delayed value of X1 or zero. X3value is selected from the table of MUX1 in Fig. 5. The adding
result X4 is outputted after one clock. X5 is one-samplingperiod-delayed value of X4 or zero. X5 value is also selectedfrom the table of MUX1 from Fig. 5. The multiplying result X6
is outputted with the delay of approximately 100 ns from X4.
On the other hand, in the LPF, the subtracting result Y2 is outputted after one clock. Y3 is outputted as one-sampling-perioddelayed value Y2 or zero. Y3 value is judged from the table of
MUX2 in Fig. 5. The adding result Y4 is output after one clock.
Y5 is outputted as one-sampling-period-delayed value of Y4 orzero. Y5 value is also judged from the table of MUX2 from fig.
5. The multiplying result Y1 is outputted with a delay of approximately 100 ns from Y4. Finally, the subtracting result v̂dis
is outputted after one clock. By the above timing, the disturbance observer is operated at high speed in FPGA.

III.

CALCULATION OF ALLOWABLE DELAY TIME FOR GATEBLOCK

Fig. 7(a) shows a circuit model for the interconnected inductor with the inverter output and the grid voltage. Focusing
on the transient response at the grid voltage recovery, the relationship between the time t and the inductor current iL is expressed byvconv = L

diL
+ vac
dt

(4).

Considering to divide the circuit model into two states; a normal operation and an operation of transient response. The normal operation is shown by fig. 7 (b) and the operation of transient response is shown by fig. 7 (c). Note that iL_1 is the inductor
current at the normal operation generated by an inverter output,
iL_2 is the inductor current at the transient phenomenon generated by the voltage recovery. Then, iL_1 and iL_2 are shown by

iL _ 1 = − I L

(5),

Vac
t
L

(6),

iL _ 2 = −(a) Interconnected inductor with inverter output and grid voltage.

(b) Only inverter output. (c)Only grid voltage.
Fig. 7. Circuit model for interconnected inductor after recovery voltage.
In the circuit model, the inverter output current is calculated.

where IL is the peak of the inductor current, Vac is the peak of
the grid voltage. The inductor current iL is shown by (7) that isexpressed by adding (5) to (6).

iL = − I L −

Vac
t
L

(7)

Moreover, the allowable delay time of the gate-block tbd is expressed by (8).
L
tbd = tth − tb =(− I L − iL _ th ) − (− I L − iL _ b )Vac=L(iL _ b − iL _ th )
Vac

(8)

where, tb is the period from the occurrence of the voltage recovery to when the inductor current reaches a gate-blockthreshold, tth is the period from the occurrence of the voltage
recovery to when the inductor current overshoot rate reaches
the FRT requirements, i.e. 50% of the rated current, iL_b is thegate-block threshold of the inductor current, iL_th is 50% of theinductor current overshoot.
IV.

DESIGN METHOD FOR MINIMIZATION OF
INTERCONNECTED INDUCTOR

Fig. 8 shows the flowchart for the minimization of the interconnected inductor in LC filter. At first, the initial conditions
which are the grid-voltage vac, the output power Pout, theFig. 8. Flowchart of design method for interconnected inductor. Inductance of interconnected inductor is decided by initial condition, after that,
it is confirmed that allowable delay time of gate-block tbd is more than
total delay time tdelay.

switching frequency fsw, the total delay time of the inductor
current detection and the control for the gate-block tdelay are
decided from the specifications of the grid-connected inverter.
By using the initial conditions, the inductance of the interconnected inductor L is calculated by (8). Moreover, the total delay
time tdelay must be shorter than the allowable delay time of gateblock tbd calculated by (8) in order that it is possible to carryout the gate-block before the inductor current overshoot rate
reaches the FRT requirements during the voltage recovery, i.e.
tth. Consequently, the FRT operation meets the FRT requirements by suppressing the inductor current overshoot. Whentdelay is longer than tbd, it is necessary to increase the inductance
L to increase tbd more than tdelay. Besides, the capacitance of thefilter capacitor in LC filter is decided by the cut-off frequency
depending on the switching frequency.

300

Table 1. Calculation result.

200
100
0
-100
-200
-300
15
10
5
0
-5

V.

EXPERIMENTAL RESULTS

Table 2 shows the experimental conditions. In this paper, a1-kW prototype is verified. The inductance of the interconnected inductor L is 1.27 mH (%Z = 1.0%), the carrier frequency
fcry is 80 kHz, the gate-block threshold for suppressing the inductor current overshoot OC_L is 9.0 A, and the over current
protection threshold OC is 20 A. When the inductor current
reaches to the OC value, the gate-block is active until reset
manually.

10 ms/div-15(a) Waveform of ZVRT operation.
300
200
100
0
-100
14
12
10

7.20 s9.00 A

10.67 A86
420
Voltage drop operation.

5 s/div

Grid voltage [V]Fig. 9 shows the simulation result of the proposed FRT
method during short grid failure. In the simulation, the total
delay time tdelay is 7.2 μs, whereas the others parameter aresame as the initial conditions of Table 1. Fig. 9 (b) shows thesimulation result at the voltage drop operation. In this result,the inductor current overshoot rate exceeds 50%. However, theFRT requirements does not restrict the current overshoot at thevoltage drop. Fig. 9(c) shows the simulation result at the voltage recovery operation. In this simulation, the inductor current
overshoot rate is suppressed to be less than 50%. Moreover, theerror rate of the calculation result and the simulation result is
0.09%. Therefore, it is confirmed that (8) is valid equation.

-10

Inductor current [A]Table 1 shows the calculation result for the allowable delay
time of the gate-block tbd. As the initial conditions, the gridvoltage peak Vac is 282.8 V, the rated inverter output current
peak IL is 7.07 A, the inductance of the interconnected inductor
L is 1.27 mH (%Z = 1.0%), the inverter output current threshold for the gate-block iL_b is 9.0 A, the inverter output current
limit by FRT requirements iL_th is 10.6 A (1.5 times of IL). By
using the initial conditions, the allowable delay time tbd is calculated from (8), which results in 7.2 μs. In order to achieve
the FRT requirements, it is necessary to achieve that the total
delay time of the inductor current detection and the control ofgate-block is less than 7.2 μs. However, the inverter circuit has
the delay time of the current detection and the sampling. It isdifficult to reduce the total delay time less than 7.2 μs. Thus,
the momentary gate-block signal OC_L is generated by theanalog detection in the detection board in order to reduce thedelay time less than 7.2 μs. The fast detection by the analog
detection and the disturbance observer implemented on the
FPGA together help to meet the FRT requirements.

(c) Voltage recovery operation.
Fig. 9. Simulation result proposed FRT method during short grid failure.
Inverter applied high-performance disturbance observer is also stopped
due to the over current protection.

Fig. 10 shows the experimental result of the conventional
FRT operation during short grid failure. It is observed from
Fig. 10 (b) that, the inductor current iL exceeds the over current
threshold value of 20 A, and after that, the inverter output is
stopped by the over current protection. The overshoot rate of
the inductor current is 534%. The conventional FRT control
method is difficult to suppress the output current overshoot.
This problem is caused by the total delay time of the current
control employed by DSP and the current detection. When the
total delay time is longer than the time that the current overshoot rate reaches the FRT requirements, i.e. 50% of the rated
current, it is impossible to suppress the inductor current overshoot under 50%.
Fig. 11 shows the experimental result of the highperformance disturbance observer during short grid failure. In
Fig. 11 (b), the inductor current iL also exceeds the over current
Table 2. Experimental conditions.

Output power P out 1 kW

Carrier fre.

DC link vol.

Ang. fre. of ACR

V dc 380 V

f cry
n

80 kHz6000 rad/s

Grid voltage v ac 200 V rms Samp. fre. of ACR f samp 20 kHz
Dead-timeT d 500 ns

Inter. Induc.

L(%Z)
OC level

Samp. fre. of DOB f so

80 kHz1.27 mH Cutoff fre. of DOB f c

2 kHz(1.0%)OC 20 A

delay time of GB tdelay < 6.5 s
OC_L level

Iref_OC 9

threshold value of 20 A even with the high-performance disturbance observer. After that, the inverter output is stopped by
the over current protection. The overshoot rate of the inductor
current is 486%. Because the control speed of the highperformance disturbance observer is not fast enough, the inverter output current overshoot reaches the over current protection threshold before the high-performance disturbance observer compensates for the inverter output current overshoot. If theinductor current overshoot current is suppressed by only thehigh-performance disturbance observer, the high speed sampling for the current detection, the high speed control (e.g.
MHz level) of the disturbance observer and PWM are needed.
Therefore, it is difficult to realize the ZVRT by using only thehigh-performance disturbance observer.
Fig. 12 shows the experimental result of the proposed FRToperation method during short grid failure. The proposed
method can realize the ZVRT operation without disconnectingfrom the grid. Fig. 12 (b) and (c) show the inductor current
waveforms at the voltage drop and the voltage recovery. The
maximum inductor current are 9.3 A and 10.4 A. These values
are suppressed under the over current threshold of 20 A. Moreover, at the voltage drop, the overshoot from a rated inductor
current peak of 7.1 A is 2.2 A, i.e. the overshoot rate of 31.0%.
At the voltage recovery, the overshoot from an inductor current
peak of 7.1 A is 3.3 A, i.e. the overshoot rate of 46.5%. Thus,
the grid-connected inverter with the minimized inductor is possible to operate during the voltage sag without the disconnection from the grid and to suppress the current overshoot rate(a) Waveform of ZVRT operation.

(a) Waveform of ZVRT operation.

(b) Voltage drop operation.
Fig. 10. Experimental result of conventional FRT operation during shortgrid failure. The grid-connected inverter is stopped due to the over current protection.

(b) Voltage drop operation.
Fig. 11. Experimental result of high-performance disturbance observer
during short grid failure. Inverter with high-performance disturbanceobserver is also stopped due to the over current protection.

less than 50% of rated inverter output current. Fig. 12 (d)shows the stability period of the inverter output after the voltage recovery. The period from the grid voltage recovery to thestability of the inverter output is 175.4 ms. This period depends
on the response time of PLL. Moreover, the E. ON code requires that the grid-connected inverter outputs more than 90%
before a voltage sag of less than 1.0 sec. Therefore, Fig. 12 (d)satisfies the E. ON code.
VI.

CONCLUSION AND FUTURE WORKThis paper proposed the FRT control method by using the
momentary gate-block with the high-performance disturbanceobserver. By using the proposed method, it was confirmed thatthe single-phase inverter with the minimized inductor of %Z =1% achieved the ZVRT operation without stopping the gridconnected inverter output. Moreover, the inductor current overshoot was suppressed less than 50% of rated inverter output
current. Thus, it was confirmed that the inductance of the interconnected inductor was reduced by 1% of %Z and still satisfied
the FRT requirements. Therefore, it was possible to minimize
the interconnected inductor by reducing the inductance.

Grid voltage vac 250 V/div
00
Inductor current iL 10 A/div

50 ms/div(a) Waveform of ZVRT operation.

Future work is the further minimization of the interconnected inductor with the application of a LCL filter.
REFERENCES[1]

Nimrod Vázquez, Marco Rosas, Claudia Hernández, Eslí Vázquez, andFrancisco Perez-Pinal, “A New Common-Mode TranceformerelessPhotovoltaic
Inverter”
IEEE
TRANSACTIONSON
INDUSTRIALELECTRONICS, VOL. 62, NO. 10, 2015 pp. 6381-6391.
[2] Sachin Jain and Vivek Agarwal, “A Single-Stage Grid Connected
Inverter Topology for Solar PV Systems With Maximum Power Point
Tracking” IEEE TRANSACTIONS ON POWER ELECTRONICS,
VOL. 22, NO. 5, 2007, pp 1928-1940.
[3] R. Peña-Alzola and M. Liserre,”LCL-Filter Design for Robust Active
Damping in Grid-Connected Converters,” IEEE TRANSACTIONS ON
INDUSTRIAL INFORMATICS, VOL. 10, NO. 4, 2014, pp. 2192-2203.
[4] R. Beres, X. Wang, F. Blaabjerg, M. Liserre, C. Bak, “A Review ofPassive Power Filters for Three-Phase Grid Connected Voltage-Source
Converters” IEEE Journal Emerging and Selected Topics in PowerElectronics, 2015.
[5] Min Huang, Xiongfei Wang, Poh Chiang Loh, Frede Blaabjerg, andWeimin Wu, “Stability Analysis and Active Damping for LLCL-FilterBased Grid-Connected Inverters”, IEEJ Journal of Industry
Applications, Vol.4, No.3, pp.187-195, 2015.
[6] R. W. Erickson and D. Maksimovic, Fundamentals of PowerElectronics, 2nd ed. New York: Springer-Verlag, 2001.
[7] Yongheng Yang, Frede Blaabjerg and Huai Wang, “Low-Voltage RideThrough of Single-Phase Transformerless Photovoltaic Inverters” IEEE
TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 3,
MAY/JUNE 2014, pp 1942-1952.
[8] E. Troester, “New German Grid Codes for Connecting PV Systems to
the Medium Voltage Power Grid” 2nd International Workshop on
Concentrating Photovoltaic Power Plants: Optical Design, Production,
Grid Connection.
[9] Jaber Alipoor, Yushi Miura, and Toshifumi Ise, “Voltage Sag Ridethrough Performance of Virtual Synchronous Generator”, IEEJ Journalof Industry Applications, Vol.4, No.5, pp.654-666, 2015.
[10] M. Tsili, S. Papathanassiou: “A review of grid code technicalrequirements for wind farms”, IET Renew. Power Gener., Vol. 3, No. 3,
pp. 308-332 (2009)[11] P. Rodriguez, A. V. Timbus, R. Teodorescu, M. Liserre and F.
Blaabjerg, “Flexible Active Power Control of Distributed Power(b) Voltage drop operation.

(c) Voltage recovery operation.

(d) Stable period of output after voltage recovery.
Fig. 12. Experimental result of proposed FRT control method
during short grid failure. The grid-connected inverter operates
without disconnecting from the grid.

Generation Systems During Grid Faults”, IEEE TRANSACTIONS ON
INDUSTRIAL ELECTRONICS, VOL. 54, NO. 5, 2007, pp. 2583-2592.
[12] S. Alepuz, S. Busquets-Monge, J. Bordonau, J. A. Martínez-Velasco, C.
A. Silva, J. Pontt and J. Rodríguez, “Control Strategies Based on
Symmetrical Components for Grid-Connected Converters Under
Voltage Dips” IEEE TRANSACTIONS ON INDUSTRIAL
ELECTRONICS, VOL. 56, NO. 6, 2009, pp. 2162-2173.
[13] K. Lee, T. M. Jahns, T. A. Lipo, V. Blasko and R. D. Lorenz,“Observer-Based Control Methods for Combined Source-Voltage
Harmonics and Unbalance Disturbances in PWM Voltage-Source
Converters”
IEEE
TRANSACTIONSON
INDUSTRYAPPLICATIONS, VOL. 45, NO. 6, 2009, pp. 2010-2021.
[14] N. Hoffmann, M. Hempel, M. C. Harke and F. W. Fuchs, “Observerbased Grid Voltage Disturbance Rejection for Grid Connected Voltage
Source PWM Converters with Line Side LCL filters” IEEE Energy
Conversion Congress and Exposition (ECCE), 2012, pp. 69-76.
[15] T. Hoshino, J. Itoh, and T. Kaneko, “Dead-time Voltage Error
Correction with Parallel Disturbance Observers for High Performance

V/f Control” IEEE Industry Applications Conference, 2007. 42nd IAS
Annual Meeting, pp. 2038-2044.
[16] Carl J. Kempf and Seiichi Kobayashi “Disturbance Observer andFeedforward Design for a High-Speed Direct-Drive Positioning Table”
IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY,
VOL. 7, NO. 5, 1999, pp 513-526[17] T. Yamaguchi, Y. Tadano, and N. Hoshi, “Using a Periodic DisturbanceObserver for a Motor Drive to Compensate Current Measurement
Errors”, IEEJ Journal of Industry Applications, Vol.4, No.4, pp.323-330,
2015.
[18] K. Sayama; S. Anze; K. Ohishi; H. Haga; T. Shimizu, ” Robust and Fine
Sinusoidal Voltage Control of Self-sustained Operation Mode for
Photovoltaic Generation System” IECON 2014 - 40th Annual
Conference of the IEEE Industrial Electronics Society[19] S. Nagai, H. N. Le, T. Nagano, K. Orikawa, J.Itoh: "Minimization ofInterconnected Inductor for Single-Phase Inverter with HighPerformance Disturbance Observer", the 2016 8th International PowerElectronics and Motion Control Conference - ECCE Asia, No. Wb8-06,
2016.