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AND8273/D
Design of a 100 W Active
Clamp Forward DC-DC
Converter for Telecom
Systems Using the
NCP1562

INTRODUCTION

April, 2020 − Rev. 4

APPLICATION NOTE

respond in the same cycle to line voltage changes. It
provides the controller some advantages ofcurrent−mode control, while eliminating noise
susceptibility, low power jitter and the need for ramp
compensation.
• Dual Mode Overcurrent Protection Circuit: handles
momentary and continuous overcurrent conditions
differently to provide the best tradeoff in system
performance and safety.
• Line Under/Overvoltage Detector: circuits enable thedevice when the line voltage is within the pre−selectedvoltage range. A resistor divider from the input line
biases the under and overvoltage detectors. The
accurate UV limit allows the converter to operate athigh duty ratio without creating additional component
stresses.

The NCP1562 PWM controller contains all the featuresand flexibility needed to implement an active clamp forward
dc−dc converter. This IC operates from an input supply up
to 150 V, thus covering the input voltages usually found in
telecom, datacom and 42 V automotive systems. One canalso note that the NCP1562 can be used in mains related
applications (e.g. desktop, server, flat TVs) as it can besupplied by an auxiliary power supply.
The NCP1562 is the ideal choice for new generation
isolated fixed switching frequency dc−dc converters using
the active clamp topology with synchronous rectification toachieve extremely high conversion efficiency. This
controller will help designers cope with their daily
challenge, “small form factor highly protected module”
through the following features:• Dual Outputs with Adjustable Overlap Delay:
provide design flexibility. Output 1 (OUT1) drives themain switch in a forward or flyback converter topology.
Output 2 (OUT2) can be used to drive an active
clamp/reset switch, a synchronous rectifier switch, orboth. OUT2 has an adjustable overlap delay to prevent
simultaneous conduction of the switching elements.
• Soft−Stop: discharges the active clamp capacitor prior
to turn off to eliminate unwanted oscillations.
• An Internal Startup Regulator: provides power to the
NCP1562 during startup. Once the system powers up,
the regulator is disabled, thus reducing power
consumption. The regulator can be powered directlyfrom the input line.
• Soft−Start: allows the system to turn on in a controlledmanner and reduce stress on system components.
• Adjustable Maximum Duty Ratio: allows the design
to be optimized without a penalty on drain voltage.
Duty ratio is controlled within ±5%.
• Adjustable Volt−second Limit: prevents transformer
saturation and improve transient response.
• Line Feedforward: adjusts the duty ratio inversely
proportional to line voltage, allowing the controller to© Semiconductor Components Industries, LLC, 2013www.onsemi.com

DESIGN SPECIFICATIONS

The flexibility of the NCP1562 is demonstrated byexamining a detailed design of a dc−dc converter for thetelecom system. The converter delivers up to 100 W at 3.3 V.
The converter specifications are listed in Table 1. A forward
active clamp topology is selected for the converter, as itprovides very high efficiency.
Table 1. Design Specifications

1

Parameter

SymbolMin

Max

Input Voltage

Vin (V)

33

76

FrequencyfSW(kHz)

Full Load Efficiencyh (%)

Duty Ratio

D

350 (typ)
90

−
65%

Output Voltage

Vout (V)

Output Voltage Ripple

Vout(rip) (mV)

3.267

3.333

Output Current

Iout (A)330

Output Power

Pout (W)−100

Ambient Temperature

TA (C)

Derating Factor

−

50

50
90%

Publication Order Number:
AND8273/D

AND8273/D
ACTIVE CLAMP FORWARD TOPOLOGY

The active clamp forward (ACF) topology has multiple
advantages compared to a traditional forward converter. The
benefits of the active clamp topology can be easily
maximized once the unique characteristics of this topology
TX1

+
Vin

−

NP:NS = 1:N
ISEC/N

ISEC

IMAG

Lout

Synchronous
RectifierControl

LMAG

LLKG

QFW

Cout

IP
QREC

NCP1562
OUT1
OUT2

are fully understood. Figure 1 shows a simplified schematicof an active clamp forward topology. The transformer model(TX1) consists of an ideal transformer, magnetizing (LMAG)
and leakage (LLKG) inductances.

CdrainQmain

CclampQclampCC

Figure 1. Active Clamp Forward Converter

The active clamp network consists of the P−channel
clamp switch (Qclamp) and clamp capacitor (Cclamp). Thisconfiguration is known as low side active clamp. A high sideclamp could have been implemented using an N−channel
MOSFET and clamp capacitor in parallel with thetransformer primary. However, it requires a floating gate
drive signal increasing system cost and complexity.
The differences between traditional and active clamp
forward converters are during the main switch off time. In
the active clamp topology, the transformer is reset at a lower
voltage during the complete off time instead of a higher
voltage during a shorter period of time. Figure 2 shows acomparison between the drain waveforms of both
topologies. The traditional forward waveform was takenwith a primary:reset winding ratio of 5:3 instead of 1:1. The
5:3 ratio allowed operation above 50% duty cycle.

The differences go beyond the replacement of the reset
winding and catch diode with a clamp capacitor and a clamp
switch. There are many system considerations and benefits
provided by the active clamp topology as described below:
1. Facilitates zero volt switching (ZVS) or
low−voltage/soft switching of the main and active
clamp switches.
2. The ability to operate above 50% duty ratio with ahigh turns ratio without a penalty on drain voltage.
3. A high turns ratio reduces:a.) The reflected output current component on
the primary side allowing the use of a smaller
Qmain.
b.) The secondary voltage allowing the use oflower voltage rectification elements.
4. Lower output inductance is required due to thehigher duty ratio.
5. Signals for driving a synchronous rectifier are
readily available.
The operation of the active clamp forward is discussed indetail with the use of Figure 3. This figure shows the powerstage waveforms of an active clamp forward converter insteady state. One switch cycle is divided in several timeintervals to facilitate the analysis.

Reset Winding

Active
Clamp

Figure 2. Drain Voltage Waveforms for Traditionaland Active Clamp Forward Topologies

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AND8273/D
decreasing and reaches zero at t4. It is imperative for Qclamp
to be on at t4. Otherwise, IP will not have a path to reverse
its direction.
Time interval t4−t5:
The primary current has reversed direction and is now
discharging Cclamp. The drain voltage begins to decrease.
The magnetizing current continues to build up in the reverse
direction.
Time interval t5−t6:
The active clamp switch turns off at t5. It is critical toachieve a fast turn off Qclamp to force the magnetizing
current to discharge the drain capacitance. Otherwise,
current will continue flowing through Qclamp.
The drain voltage decays as the drain capacitance isdischarged. The minimum drain voltage is determined by
the inductive energy (EL) stored in the magnetizing andleakage inductances. If the inductive energy is greater thanthe capacitive energy stored in the drain capacitance, ZVS
is achieved. If the magnetizing energy is not enough, an
external inductor can be added to facilitate ZVS.
The inductive energy is increased by reducing LMAG. Thismight be counter intuitive. But let me explain; Let’s startwith the magnetizing energy equation given by Equation 1.

OUT1

OUT2

VDS

IQ(main)IP
t2
t0

t1 t3 t4t5 t6

EL(MAG) + 1 @ LMAG @ IMAG 2
2

Figure 3. Active Clamp Forward Waveforms(eq. 1)

For a given voltage and on time, the LMAG and IMAG
product is constant. That is, if LMAG decreases by 1/2, IMAG
increases by 2. As IMAG is squared, the net effect is anincrease in energy.

Time interval t0 − t1:
The main switch turns on at t0. The active clamp switch
remains off. The primary current (IP) flows through thetransformer and the main switch. This current is the sum of
the transformer magnetizing (IMAG) and reflected
secondary currents. No current flows through Qclamp andcurrent flows in the secondary side through the forward
rectifier, QREC. The primary current continues to build
while Qmain is on.
Time interval t1 − t2:
The main switch turns off at t1. The forward rectifier turns
off at t1 eliminating the reflected secondary current
component from IP if the leakage inductance effect isneglected. The primary current is now the magnetizing
current. It continues to flow in the same direction charging
the drain capacitance, Cdrain.
Time interval t2 – t3:
At time t2 the drain voltage reaches the clamp capacitor
voltage. The primary current charges both the drain
capacitance and Cclamp. The primary current flows throughthe body diode of Qclamp. The clamp capacitor is several
orders of magnitude larger Cdrain, causing the voltage slope
to drop. The drain ripple voltage is determined by theresonance between LMAG and Cclamp.
Time interval t3−t4:
The active clamp switch can turn on at any time between
t2 and t4 under ZVS conditions. Once Qclamp turns on,
current flows through its channel. The magnitude of IP is

DESIGN PROCEDURE

The converter design is divided in several steps to ease thedesign process. The process begins with the power stage as
it determines most of the system components. The designcontinues with the feedback loop followed by the setup of
the controller, the NCP1562. Finally, the system
performance is evaluated and compared to the design target.
Throughout this application note, operation at theminimum and maximum input voltages are referred as low
and high line, respectively.
TRANSFORMER

A power transformer (TX1) is used to step down thevoltage and provide voltage isolation between the input
supply and the load. The transformer in this design has threewindings; primary, secondary and auxiliary.
Contrary to a traditional forward transformer, an active
clamp transformer is designed with low magnetizing
inductance. The stored magnetizing energy is used todischarge the drain capacitance and facilitate ZVS as
explained earlier. In addition, LMAG affects the loop
response as it affects a pair of complex zeros introduced by
the active clamp stage. It is discussed later in the feedback
loop section.
The input to output voltage relationship is described by
Equation 2.

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AND8273/D
Vout +

ǒVin * VNDS(on) * Vf (QREC)Ǔ @ D

ACTIVE CLAMP STAGE(eq. 2)

The active clamp topology recycles the transformer
magnetizing energy using a resonant circuit. This resonant
circuit is composed of the magnetizing inductance andclamp capacitor. The parasitic drain capacitance and leakage
inductance are ignored as they are very small. The resonant
frequency of LMAG and Cclamp is selected low enough tomaintain a constant voltage during the main switch off time.
That is, the resonant period is significantly larger than theswitching period of the controller.
The clamp capacitor determines the drain ripple voltage(VDS(ripple)) during the main switch off time. The ripple
voltage is inversely proportional to Cclamp. The active clamp
capacitor also affects the loop response as it contributes toa pair of complex zeros introduced by the active clamp stage.
It is discussed later in the Feedback Loop Section. If duty
ratio changes rapidly, the voltage across Cclamp has tochange accordingly. Otherwise, the transformer may
saturate. Therefore, a tradeoff between ripple voltage andtransient response has to be considered in the selection of
Cclamp. The design tool facilitates the selection of Cclamp byplotting VDS(ripple) and the normalized peak flux excursion
vs Cclamp as shown in Figure 5.

where, N is the primary to secondary turns ratio, VDS(on) is
the voltage drop across Qmain, Vf(QREC) is the voltage drop
across QREC, D is the duty ratio and Vin is the input voltage.
Equation 2) is used to select N given a target maximum duty
ratio. An additional factor to consider in the selection of N
is the drain voltage of the main switch (VDS) during the offtime as it depends on the duty ratio. Equation 3 shows therelationship between VDS and D.
VDS +

Vin
1*D

(eq. 3)

The NCP1562 Excel−based design tool (downloadablefrom http://www.onsemi.com). provides an easy way toevaluate the interaction between the turns ratio, duty ratio
and maximum drain voltage as shown in Figure 4. The drain
voltage is almost constant over the complete operating
range. A high turns ratio is desired to reduce the primary
current and the secondary voltage. However, it causes thedrain voltage to increase very rapidly at low line. The ideal
turns ratio is the one that achieves equal drain voltages at low
and high line.

60

VDS(ripple), DRAIN VOLTAGE RIPPLE (V)

125

40

N=5

50
25
0

2.5

50

N=6

100
75

3.0

Ripple Voltage at High Line

30

40

50

60

70

80

Vin, INPUT VOLTAGE (V)NORMALIZED PEAK FLUXVDS, DRAIN VOLTAGE (V)

150

2.0

Flux at Low Line

30

1.5

20

1.0

10

0.5

0

0

2

4

6

8

10

12

14

16

18

0

CLAMP CAPACITANCE (nF)

Figure 4. Clamp Voltage vs. Input Voltage for
Several Turns Ratios

Figure 5. VDS(ripple) and Normalized Peak Flux vs.
CclampUsing the design tool a turns ratio of 6 is selected for a
maximum duty ratio of 63%. The ideal turns ratio is 6.5, but
it would have increased the complexity of the transformer.
In high current output converters, it is desired to keep thesecondary turns at the lowest level (e.g. 1 turn) to reduce
conduction losses. The primary turns (NP) are set at 6 and thesecondary turns (NS) are set at 1. A 12:2 (NP:NS) ratio could
have been used to reduce core losses. Low core losses are
beneficial when conduction losses are low, as can be the casewhen operation at high line. The magnetizing inductance is
set at 120 mH to reduce conduction losses.
A planar transformer is selected due to its low profile andrepeatable characteristics. The custom transformer ismanufactured by Payton Planar Magnetics and can be easilyordered under part number 51665.

The magnetizing current charges and discharges the active
clamp capacitor every cycle and is given by Equation 4.
IMAG [f

Vin @ D
SW @ LMAG(eq. 4)

It is absolutely critical to consider the ripple current ratingin the selection of Cclamp. Otherwise, the capacitor may
overheat. The minimum ripple current rating of Cclamp is
determined by the magnetizing rms current. Assuming themagnetizing current reverses direction halfway during theoff time, the clamp capacitor rms current is approximated by
Equation 5.
ICclamp(rms) [f

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4

Vin @ D
SW @ LMAG

Ǹ1 *2 D(eq. 5)

AND8273/D
The worst case condition is at high line.
Using the Design Tool, an rms magnetizing current of
0.294 A is calculated. A ceramic capacitor is preferred due
its low equivalent series resistance (ESR). TDK’s
C3216X7R2J103M is used. Although maximum drain
voltage of this design is 150 V, a 630 V capacitor is used as
it is readily available.

The minimum output capacitance required to maintain the
output voltage ripple below our target of 50 mV is calculatedusing Equation 8.
Cout +The output L−C (Lout−Cout) filter averages the squarewave signal at the transformer output. The output inductor,
Lout, is sized such that it operates in continuous conduction
mode at the minimum output current, Iout(min) using
Equation 6.
Lout +

ǒǓ

Vout(rip) + Iout(rip) @ RESR

SW

(eq. 6)2 @ Iout(min)where, D(min) is the minimum duty ratio. Solving
Equation 6,
Lout +

Ǔ
3.3 @ ǒ1*0.271
350
2@3+ 1.15 mH

MAIN SWITCHA MOSFET is used as the main switch. Several factors,
including current, voltage stress and power dissipation are
considered for the MOSFET selection.
The shape of the primary current is shown in Figure 7. It
consists of the primary magnetizing and reflected output
currents. The valley of the primary current, IP(VL) is
approximated to the inductor current divided by the turns
ratio.
In practice, IP(VL) is slightly less as the magnetizing
current starts negative due to the resonant transition. But it
is a good approximation as the magnetizing current issignificantly smaller than the reflected output inductor
current.

using the D(min) provided by the Design Tool, a minimum
inductance of 1.15 mH is required. A custom 1.5 mH inductorfrom Payton Planar Magnetics is used. It can be easilyordered under part number 51666.
The inductor ripple current, Iout(rip), reaches its maximum
value at high line and it is given by Equation 7.
Iout(rip) +Vout @ 1*ton(min)
f

Lout

SW

(eq. 7)

Solving Equation 7,
Iout(rip) +Ǔ
3.3 @ ǒ1*0.271
350
1.5(eq. 9)In order to maintain Vout(rip) below our target, RESR has tobe below 10.9 mW.
Please consider that Equation 8 provides a minimum
value to maintain Vout(rip) within target. In most cases, ahigher Cout is required to meet voltage holdup requirements
and shape the frequency response of the converter as it isdescribed later in the Feedback Loop Section. For thisdesign, Cout is set at 544 mF using a parallel combination of
tantalum capacitors for bulk capacitance and ceramic
capacitors for RESR reduction.

1*D(min)f(eq. 8)A minimum capacitance of 33 mF is required. The
capacitor ESR also affects the output voltage ripple asshown in Equation 9.

OUTPUT L−C FILTER

Vout @

Iout(rip)
8 @ f SW @ Vout(rip)+ 4.58 A

a maximum ripple current of 4.58 A is obtained. Figure 6
shows the inductor current at low and high line as provided
by the Design Tool.

IMAG

33
IL, INDUCTOR CURRENT (A)High Line
32
Low Line

31

IP(PK)

Iout/NIP(VL)

30
29
ton
28
27

T
0

0.5

1.0

1.5

2.0

2.5

Figure 7. Primary Current Waveform

3.0

The primary peak current, IP(PK), is given by Equation 10.
The maximum IP(PK) occurs at high line when the output
inductor ripple current is at its highest.

Time (ms)Figure 6. Calculated Output Inductor Current at
Low and High Conditions

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AND8273/D
a worst case scenario as the provided RqJA does not include
airflow. Also, it is for a lower copper weight than the oneused on this board.
The thermal resistance of the main switch can be reducedby maximizing the copper area around the package. A
heatsink can also be added on top of the package.

Iout ) Iout(rip)Vin @ D2(eq. 10)IP(PK) +)N
LMAG @ f SW

The main switch experiences conduction and switchinglosses. The conduction losses are given by Equation 11.
Pcon + IP(rms) 2 @ RDS(on)(eq. 11)ACTIVE CLAMP SWITCH

where, RDS(on) is the switch on resistance and IP(rms) is theprimary rms current. The primary rms current is given by
Equation 12.

ǸǒIP(PK) ) IP(PK) @ IP(VL) ) IP(VL) Ǔ @ D3

IP(RMS) +2

2

The active clamp switch experiences low conduction
losses because only the magnetizing current flows throughit. Switching losses are negligible because the active clamp
switch is turned on after the body diode is conducting.
IR’s IRF6217PBF is used for the active clamp switch. It
is a 150 V P−channel MOSFET with an on resistance of
2.4ĂW. Only conduction losses are considered for the power
dissipation of the active clamp switch. Solving Equation 11,
a power dissipation of 0.58 W is calculated for a TJ(max) of
79_C.
The designer may be tempted to use a lower on resistanceswitch to reduce conduction losses. However, this may
counterproductive. The active clamp switch has to turn off
quickly to divert the magnetizing current and discharge thedrain capacitance to achieve ZVS. If not, the magnetizing
current will keep flowing through the switch preventing thedrain capacitance to be discharged and achieve ZVS. A
larger active clamp switch will have lower conduction losses
but may increase switching losses on the main switch if ZVS
is affected.
The low side active clamp circuit is easier to implement
as it is compatible with a ground referenced gate drive
signal. However, it requires a negative voltage to turn on the
P−channel MOSFET. It is generated using a level shiftcircuit as the one shown in Figure 1. Active clamp forward
converter. It consists of a diode and an ac coupling capacitor(CC). The ac coupling capacitor is selected using
Equation 15.

(eq. 12)

The turn on switching loss of the main switch isapproximated by Equation 13.
PSW(Qmain) +VDS @ IP(VL) @ tSW(on) @ f SW
6(eq. 13)

where, VDS is the drain voltage at which the main switch
turns on, tsw(on) is the switch turn on time. The main switch
turn off switching losses are very small and are ignored.
In an active clamp converter, the main switch achieves
Zero−Volt Switching (ZVS) under specific operating
conditions. ZVS is affected by input voltage and output load.
Even if ZVS is not achieved, reduced voltage switching is
obtained. As a first approximation, the input voltage is usedas the switch voltage at turn−on for our calculations.
The capacitance at the drain voltage should be minimized
to facilitate ZVS. That includes the main and active clamp
switches output capacitance (Coss) and transformer
capacitance. Therefore, Coss should also be considered inaddition to the typical RDS(on) and gate charge parameters
for the selection of the main switch. Fairchild’s FDD2582 isselected for this design as it provides the best tradeoff
between RDS(on) and Coss. It is a 150 V N−channel MOSFET
with an RDS(on) of 58 mW.
Using the Design Tool the power dissipation of the main
switch at high and low line assuming a 50 ns turn on time iscalculated to be 1.49 W and 1.56 W, respectively. Powerdissipation of the main switch is dominated at low line byconduction losses and at high line by switching losses. The
maximum power dissipation of the main switch is calculatedusing Equation 14.
P+

TJ(max) * TA(max)
RqJA

CC +

VDRV @ (1 * D) @ D
QG)
DVC @ RGS @ f SW
DVC(eq. 15)

where, QG is the total gate charge of the switch, VDRV is thegate drive voltage, DVC is the gate voltage ripple (should be~ 10% VDRV), and RGS is the gate to source resistor. A
0.01ĂmF is used for a 12 V gate voltage with an RGS of 10 kW.

(eq. 14)

AUXILIARY SUPPLY REGULATOR

where, RθJA is the junction to ambient thermal resistanceand TJ(max) and TA(max) are the maximum junction andambient temperatures, respectively. Please keep in mind that
Equation 14 assumes there are no other heat sources in thesystem. However, this is not the case in a real system.
As specified in Table 1, TA(max) is 50°C. Solving
Equation 14 for TJ(max) at high line, a maximum TJ of 131°C
is calculated. The maximum allowed TJ is 158°C assuming
an 90% derating for TJ(max) of the FDD2582.
Power dissipation of the main switch is high and shouldbe verified during design validation to make sure it is still
within acceptable limits. However, keep in mind that this is

The NCP1562 has an internal startup circuit. It charges the
supply capacitor (CAUX) on the VAUX pin until the startup
threshold is reached. The startup circuit is then disabled andthe controller is biased by CAUX. The auxiliary capacitor issized to store enough energy to maintain VAUX above its
turnoff threshold, VAUX(off2). An auxiliary supply biases
VAUX under normal operating conditions to prevent theconverter from turning off.
The auxiliary supply can be generated from a winding on
the transformer or on the output inductor. The maindifference is the speed at which the supply voltage builds up.

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AND8273/D
INPUT FILTER

The supply from the transformer builds up quickly where as
the output inductor supply builds up with Vout. However, theoutput inductor supply is inherently regulated. In thisdesign, the auxiliary supply is implemented from thetransformer to reduce the value of CAUX. An L−C filter(LAUX−CAUX) is used to average the voltage from theauxiliary winding as shown in Figure 8.
LAUX

To VAUX Pin
VAUX

+
−

−

CAUX

Vf

An input L−C (Lin−Cin) filter is used to reduce EMI andprovide a solid input voltage to the converter. The input filter
design is constrained by stability and power rating criteria.
Oscillation will occur if the converter input impedance,
Zin, is lower than the filter output impedance, Zout. The
converter closed loop input impedance is ultimately
determined by the converter feedback loop. However, theconverter input impedance can be approximated as anegative resistor using 18.

+

NAUX

Zin(dBW) [ −20 log

NS

ǒ

R
Zout(dBW) [ Lin ø n @ Cin ) ESRn

TX1

Figure 8. Auxiliary Supply ArchitectureSW(eq. 16)

Solving Equation 16, 3.6 turns are required for a VAUX of
12 V and a Vf of 0.7 V. The turns are rounded up to 4 for a
VAUX of 13.35 V.
The LC filter averages the voltage as long as the inductor
operates in continuous conduction mode. The auxiliary
inductor value is selected in the same manner as the output
inductor using Equation 6 by replacing the “out” subscriptwith “AUX”. The auxiliary current (IAUX) is calculatedusing Equation 17.
IAUX + IAUX3 ) f @ (QT(main) ) QT(clamp))

Ǔ (eq. 19)

where, n is the number of capacitors in parallel.
The input inductor is selected to handle the converter
average input current. Coilcraft’s DS3316P−152 is used as
the input inductor.
The input capacitors are selected based on the input ripple
current given by 20. Ceramic capacitors are preferred due
their low ESR and high ripple current capability. TDK’s
C4532X7R2A225MT are used as the input capacitors.

The number of auxiliary turns (NAUX) is calculated using
Equation 16.
AUX ) Vf Ǔ @ Np
ǒVDC
Vin

(eq. 18)

The L−C filter output impedance is given by 19.

NP

NAUX [

outǓǒVIoutǸǒ

Iin(rms) +IMAG 2(1−D)
D
2)I
2
I
P(PK)IP(VL) ) IP(PK) Ǔ )3 P(VL)2(eq. 20)Equation 20 is an approximation and assumes themagnetizing current reverse directions halfway during theoff time. It can be observed that equations 12 and 20 are very
similar. The main difference is the ripple component addedby the active clamp during the reset of the transformer.
Equation 20 sets the minimum capacitance to comply withthe capacitor input ripple current rating. Additional
capacitance may be needed to insure the system is stable
over the complete operating range.
The input filter is implemented using a 1.5 mH inductor
with four 2.2 mF capacitors in parallel. Figure 9 shows the
L−C filter output impedance and the approximatedconverter input impedance over frequency obtained with the
Design Tool. As the capacitor ESR changes over frequency,
the ESR at the filter corner frequency is used for the analysis.

(eq. 17)

where, IAUX3 is the controller bias current (refer to the
NCP1562 datasheet) and QT(main) and QT(clamp) are the total
gate charge of the main and active clamp switches,
respectively. Solving Equation 17, an IAUX of 23.2 mA is
obtained. The required inductor for an IAUX(min) of 15% of
IAUX is 694 mH. Coilcraft’s DO1606T series is selected forthe auxiliary inductor. This series is very rugged and has avery low profile. The next size up in the DO1606T series isused. It is 1000 mH.
As previously discussed, CAUX must be sized to maintain
VAUX above VAUX(off2) during startup. The NCP1562
reduces the CAUX requirement by turning on the startup
circuit if an intermediate threshold (VAUX(off1)) is reached.
This, in addition to the other factors that affect the auxiliary
supply (load current, soft start period, etc.) make theselection of VAUX non trivial. Empirically it was found that
88 mF works well under all operating conditions. However,116ĂmF was used as the components were readily available
from distribution. The VAUX capacitance consists of one
22ĂmF ceramic capacitor across the NCP1562 to reducenoise, and two 47 mF tantalum capacitors for bulk storage.

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7

AND8273/D
50
40
IMPEDANCE (dBW)30

Converter

20
10
0
−10

Input Filter

−20
−30
−40
−50

0.1

1

10
FREQUENCY (kHz)

100

1000

Figure 9. Input Filter Output Impedance andApproximated Converter Input Impedance

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8

AND8273/D
In general, if the system oscillates, the input filter output
impedance can be decreased as in most cases the converter
input impedance is dictated by the system specifications.
This can be accomplished adding a damping network.

portion of the output voltage thus severely affecting theefficiency.
The active clamp topology lends itself for synchronousrectification as it has signals readily available that may be
used for driving a synchronous rectifier. The synchronousrectifiers are driven from the main transformer output
winding as shown in Figure 10. This configuration is known
as self−driven synchronous rectification (SD−SR).

SYNCHRONOUS RECTIFICATION

Low output voltage converters require synchronousrectification to achieve high efficiency. If a diode is used forrectification, the forward voltage drop becomes a significant

Lout

TX1

+

Vin

−

+

−

VFW

VREC

−

NCP1562
OUT1

QFW

Cout

+

Qmain

QREC
CclampOUT2QclampCC

Figure 10. Synchronous Rectification Circuit

The voltage of the transformer output when the main
switch is on (VFW) and off (VREC) are given by equations 21
and 22.
V
VFW + inN
VREC +

If the secondary voltage is not compatible with the
MOSFET gate voltage, a few alternatives are available aslisted below:
1. Use a lower transformer turns ratio.
2. Add an extra winding or use a stacked winding on
the transformer secondary.
3. Drive the MOSFETs from the primary side (OUT1and OUT2) using a gate drive transformer.
The selection of the rectification MOSFETs in an SD−SR
configuration is not trivial. Both conduction and switchinglosses should be optimized for the best overall efficiency.
Contrary to traditional belief, the lowest RDS(on) MOSFET
will not always provide the best overall efficiency. The
incremental reduction in conduction losses of a low RDS(on)MOSFET may be overcome by an increase in switchinglosses.
ON Semiconductor’s NTMFS4835N is selected for both
QREC and QFW MOSFETs. It is a 30 V MOSFET with amaximum RDS(on) of 5.0 mW and a maximum gate chargeof 39 nC at 4.5 V. The NTMFS4835N is housed in a SO−8
Flat Lead (FL) package. The SO−8 FL is a leadless packagewith an exposed tab to reduce thermal resistance andparasitic inductance and capacitance.
The maximum power dissipation of the SD−SR
MOSFETs is calculated using Equation 14. The
NTMFS4835 datasheet provides an RqJA of 55.1°C/W anda TJ(max) of 150°C. Telecom products are usually designed
for a TA(max) of 50°C. Solving Equation 14, with 90%
derating on TJ(max) each MOSFET can dissipate 1.54 W. If
higher power dissipation is required, a heatsink can be added
to the MOSFET to reduce its RqJA.

(eq. 21)

Vclamp(eq. 22)N

Before SD−SR can be used, the voltage at the transformer
output needs to be calculated to ensure it is high enough toturn on the rectification MOSFETs but it does not exceed its
maximum gate voltage. Using the NCP1562 Design Tool therange for VFW and VREC is calculated between 4.7 V and12.7 V as shown in Figure 11. A MOSFET characterizedwith a 4.5 V gate voltage should be used to ensure therectification MOSFET turn on.
14

STRESS VOLTAGE (V)

12
VFW

10
8

VREC

6
4
2
0

30

40

50

60

70

80

Vin, INPUT VOLTAGE (V)Figure 11. Synchronous Rectifier Gate Voltage

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9

AND8273/D
complicates the frequency compensation of the converter as
it occurs at the desired crossover frequency range. The poleis due to the impedance and capacitance at the collector
terminal. Fortunately, there are a few tricks to move theoptocoupler pole to a higher frequency and increase thesystem bandwidth.
First, a cascode stage using a bipolar transistor (Q1) is
placed between the optocoupler pull up resistor (REA) andthe collector of the optocoupler as shown in Figure 13. The
collector impedance is now the impedance looking into theemitter of the bipolar transistor which is very small. The
optocoupler pole is effectively moved to a higher frequency(> 50 kHz).

The converter high output current requires multiple
MOSFETs to be used in parallel due to the high conduction
losses. The number of MOSFETs for QFW and QREC isdetermined by calculating the losses of each one anddividing it by the maximum power dissipation given by
Equation 14.
The maximum power dissipation of QREC occurs at low
line and for QFW at high line. The conduction losses for
QREC and QFW are given by equations 23 and 24,
respectively.
(eq. 23)

Pcond(FW) + Iout(rms) 2 @ (1 * D) @ RDS(on) (eq. 24)

VREF

The gate charge losses of the driver and body diodeconduction losses are given by 25 and 26, respectively.
Pdriver + f SW @ QG(TOT) @ Vgate(eq. 25)

Pbd + Vbd @ Iout @ f SW @ tdead(eq. 26)

R6
VEA

Figure 12 shows the synchronous rectification losses
calculated by the NCP1562 Design Tool.

REA

Q1
R11

4.0

POWER (W)

Feedback

Figure 13. High Bandwidth Optocoupler Biasing
Configuration

3.0

Second, the optocoupler diode is driven with an ideal
current source. This arrangement works very well duringtransients and power up. As the diode is driven with a current
instead of a voltage source, the error amplifier output does
not have to swing too far during a transient. This
arrangement is also immune to supply voltage variations.
The optocoupler gain changes with its bias current, Iopto.
It is not uncommon for an optocoupler to have a gain
variation of 10 or more over the operating current range. As
the optocoupler bias current changes from low to high line,
it presents a design challenge. In addition, optocoupler
performance changes with age and temperature. A low gain
optocoupler is preferred to minimize its impact in the overallsystem gain. NEC’s PS2703−1−M optocoupler is used inthis design.
The optocoupler manufacturer recommends biasing the
optocoupler at 1 mA. Our optocoupler is designed to operate
at 1 mA at nominal input voltage (48 V). However, the bias
current at low or high line will be slightly different. Equation
27 relates the duty ratio to optocoupler bias current,

2.5
2.0

Rectification MOSFET

1.5
1.0
0.5
0.0

Vref(EA)

R13

Freewheeling MOSFET

3.5

−
+

Pcond(REC) + Iout(rms) 2 @ D @ RDS(on)

30

40

50

60

70

80

Vin, INPUT VOLTAGE (V)Figure 12. Synchronous Rectification Losses

The full load losses for QFW and QREC are 3.6 W and
3.4 W, respectively. Two MOSFETs are used in parallel foreach of QFW and QREC. However it is apparent that externalcooling or a heatsink is required to deliver full power.
Alternatively, a larger number of MOSFETs in parallel
could have been used.
Almost no ringing is observed on the drain of thesynchronous rectifiers. This is due to the minimum parasitic
inductance and capacitance of the SO−8 FL package and thetight layout of the output power stage. No R−C snubbers are
required across the synchronous rectifiers.

REA +VREF * (3 @ D ) 0.9)
Iopto

(eq. 27)

where, VREF is the voltage reference of the controller. The
NCP1562 Design Tool suggests a duty ratio of 0.43 atnominal input voltage. Solving 27, an REA of 2.81 kW issuggested. An REA of 3.01 kW is used. The base of the Q1
is biased at approximately 1.5 V using R6 and R11. That
insures the optocoupler collector−emitter voltage is kept
above its saturation voltage of 0.3 V.

OPTOCOUPLER AND VEA CIRCUITThe output voltage is regulated by comparing the error
signal in the VEA pin to the feedforward (FF) ramp. An
optocoupler transmits the error signal across the isolation
boundary. Typically, optocouplers introduce a pole around10 kHz. This pole limits the system bandwidth andwww.onsemi.com
10

AND8273/D

1
2p ǸLout @ Cout(eq. 28)

1
2p @ RESR @ Cout(eq. 29)

P1, 2(LC) +ZESR +
P1, 2(AC) +(1 * D)MAGNITUDE (dB)

The converter regulates the output voltage by adjusting
the duty ratio using a negative feedback loop. If the loop is
not stable, the converter will oscillate. To insure the loop is
stable and has adequate transient response, the closed loop
response should have a minimum phase margin of 45° under
all line and load conditions. This is accomplished by shaping
the open loop response using an error amplifier.
The first step is to determine the open loop frequency
response of the converter. An active clamp forward
converter operating in voltage mode has two poles, p1,2(LC),due to the output LC filter and one zero, zESR, due to the
output capacitor series resistance. In addition it has twocomplex zeros introduced by the active clamp network. The
complex zeros are not shown due to their great complexity.
The complex zeros happen before the system poles P1,2(AC).
The system crossover frequency should be selected below
P1,2(AC) to avoid the complex poles. Equations 28 through30 show the system poles and zeros.

0

40

−20

30

−40

20

−60

10

−80

0

−100

−10

−120

−20

−140

−30

−160

−40
−50

−180
0.01

0.1

1

GMOD +

Vout

R19
R20

Using the values calculated earlier GMOD is 1.86 dB. The
gain of the optocoupler is given by 32.
GOPTO +REA @ CTR
R13

−200

The maximum achievable bandwidth is limited by
p1,2(AC) at low line. Therefore, the system crossover
frequency, fCO, should be set lower than p1,2(AC). In thisdesign, fCO is set at 20 kHz.
Several EA configurations are available. A type II error
amplifier, as the one shown in Figure 15, is used in thisdesign as it provides adequate phase margin. A type II error
amplifier has 2 poles and 2 zeros. The first pole is at theorigin. The frequency of the remaining pole and zeros arecalculated using 33 through 35.

(eq. 31)N

100

Figure 14. Simulated Open Loop Frequency
Response

The ESR of the output capacitors is very low (<1 mW),
pushing ZESR above 100 kHz. The worst case of the active
clamp RHP is at low line. In this design it is around 41.1 kHz.
The controller or modulator gain, GMOD, is given by 31.
RFF @ f SW @ CFF

10

FREQUENCY (kHz)(eq. 30)

2p ǸLMAG @ Cclamp

50

PHASE (°)

FEEDBACK LOOP

C25

R30

D5
R21

C29

(eq. 32)−
EA

Frequency (kHz)Magnitude (dB)

p1,2(LC)

5.6−z(ESR)> 200

p1,2(AC)

41.1

−

GMOD

−

1.86

GOPTO

−

18.7

Vref(EA)

Figure 15. Type II Error Amplifier
fp2 +Table 2. SYSTEM POLES AND ZEROSParameter+where, CTR is the optocoupler transfer ratio, R13 is theresistor at the optocoupler anode. Assuming a CTR of 1 thegain is 18.7 dB.
The controller gain and system poles and zeros are listed
in Table 2. The simulated open loop frequency response isshown in Figure 14. The simulated frequency response does
not show the complex zeros or P1,2(AC) as they are
dependent on the operating conditions.

1
2p @ C29 @ (R21 ø R30)

(eq. 33)

1fz1 +2p @ C29 @ R21(eq. 34)

1fz2 +2p @ C25 @ R20(eq. 35)

Resistor R19 is added to provide an injection point tomeasure the frequency response. A small resistor value (10to 20 Ω) is used for R19 so it does not affect the dc operating
point. Diode D5 clamps the output of the error amplifier
during startup to improve the transient response.
The selection of the compensation network components
begins by determining the error amplifier gain, GEA, using 36.
GEA + 20 @ log

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11

ǒRR20
Ǔ
21

(eq. 36)

AND8273/D
The maximum voltage of either A or B provides thevoltage supply for the EA and the TLV431. Signals A and B
are taken from the dot (A) and non−dot (B) ends of thesecondary winding of the main transformer. The NCP1562
Design Tool shows a minimum voltage of approximately
7 V. The maximum value of R7 is calculated using 37.

The system open loop gain in Figure 14 Simulated Open
Loop Frequency Response at the desired crossover
frequency of 15 kHz is 5 dB. Therefore, the EA gain is set
at −8.77 dB to achieve a gain of 0 dB at approximately
15 kHz. Resistors R20 and R21 are set at 5.9 kW and
16.2 kW, respectively. One compensation zero is placed
before and one after p1,2(LC) at 482 Hz and 9.8 kHz,
respectively. Capacitors C25 and C29 are set at 0.056 mF and1000 pF, respectively. The second pole is set at a 457 kHz
setting R30 at 348 W. The simulated frequency response isshown in Figure 16. The simulated crossover frequency isaround 15 kHz with a 60° phase margin.
Measured Phase

30

135

10 Measured Gain

45

0

0

−10

−45

−20

−90

−30

−135
0.1

1

10

100

PHASE (°)

90

MAGNITUDE (dB)

20

−180

ERROR AMPLIFIER VOLTAGE REFERENCE

The error amplifier reference voltage (Vref(EA)) is
generated using On Semiconductor’s TLV431 as shown in
Figure 17.
−
+

D3

C9

C6

IK

TLV431

Ibias

R27

+

D6

R7

+

B

R12

C5

Vref(EA)

1.25 V R28−(eq. 37)

This converter is designed to deliver 100 W under normal
operating conditions. However, under a fault condition thecurrent may increase significantly and permanently damage
the system. The NCP1562 incorporates an extremely
accurate current limit circuit to protect the system while acurrent limit condition is present. A low propagation delay
combined with an extremely accurate current limit threshold
limit the maximum power delivered under a current limit
condition. This allows the designer to have a robust and safe
system without excessive over design.
The NCP1562 has two overcurrent protection methods,
cycle by cycle and cycle skip. In cycle by cycle, theconduction period ends once the current limit threshold isreached. Cycle skip is enabled if the converter is in acontinuous current limit for a user programmed time. Whilein cycle skip mode, the converter power downs and restart
after a user determined time.
The NCP1562A is used in this design. It has a current limit
voltage threshold, VILIM, of 0.2 V. A current sense resistor
is used to reduce system cost and complexity. It is calculatedusing 38.

FREQUENCY (kHz)A

IK ) Ibias

CURRENT LIMIT CIRCUIT

Figure 16. Simulated System Frequency Response

EA

V(A or B) * 0.7 V

where, Vf is the diode drop of D3 or D6 and IK is the TLV431
minimum cathode current. Solving 37 with an IK of 80 mA
sets the maximum value of R7 at 10.9 kW. The value of R7
is set at 4.22 kW.
The switching noise at nodes A and B is attenuated byplacing a small resistor (R12) in series with D3 and D6. The
value of R12 is set at 49.9 W. The components of the peakdetector (D3, D6, R12 and C9) are placed close to each otherbut away from the EA to keep noise low. A bypass capacitor(C6) is placed across the supply terminals of the EA. BothC9 and C6 are set at 0.1 mF.

180

40

−40

R7 +

−

Rsense +Figure 17. Error Amplifier Reference Voltage

The error amplifier reference voltage is set at 3.3 V using
R27 and R28. This eliminates the need of a bias resistor
between the EA inverting input and ground.
The voltage across R28 is regulated at 1.25 V by the
TLV431. Assuming a bias current (Ibias) of 500 mA, R28 isset at 2.49 kW. Resistor R27 is set by calculating thedifference between Vref(EA) and 1.25 V and dividing it by
Ibias. It is set at 4.22 kW. Capacitor C5 provides noise
immunity for Vref(EA). It is set at 1000 pF.

VILIM
IP(PK)(eq. 38)

Using IP(PK) calculated earlier, Rsense is calculated at
34 mW. The value of the sense resistor is set at 33 mW.
The NCP1562 incorporates a 75 ns leading edge blanking
circuit to mask the leading edge spike of the current signal.
The demo board also provides external blanking time using
a simple RC low pass filter comprised of R10 and C11. The
cutoff frequency of the low pass filter is selected several
orders of magnitude greater than the operating frequency to
avoid distortion of the current sense signal. The value of R10

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12

AND8273/D
is set at 100 W and C11 is set at 100 pF. The complete current
sense circuit is shown in Figure 18.

A small capacitor of at least 1000 pF is required on the
UVOV to provide noise immunity and filter turn ON andturn OFF transitions on the input line.
The Design Tool suggests using an R1 of 504 kW and an
R2 of 32.4 kW. Used values are 523 W and 32.4 kW for R1
and R4, respectively. The calculated operating voltage range
is between 35.31 V and 80.15 V with Vin increasing andbetween 32.52 V and 75 V with Vin decreasing.

Main Switch

R10+

To CS Pin

VCS

C11

RsenseMAXIMUM DUTY RATIO−As shown in Figure 4, the drain voltage of the main switchof an active clamp converter increases rapidly at low input
voltages. Accurate duty ratio control allows the designer tofully optimize the system without risking exceeding thevoltage rating of the main switch.
The NCP1562 incorporates an extremely accurate duty
ratio control. It is trimmed during manufacturing to achieve
better that ±5% accuracy over the complete temperature andprocess range.
Duty ratio and frequency are controlled using a timing
resistor, RT, and capacitor, CT, on the RTCT pin. The resistor
is connected between the VREF and RTCT pins and thecapacitor is connected between the RTCT and GND pins.
The converter is designed to operate at 350 kHz with amaximum duty ratio of 63%. Taking into account theoverlap time delay, the required oscillator duty ratio is 66%.
The Design Tool suggests initial values for RT and CT of
14.5 and 320 pF, respectively. Final values of RT and CT are
set at 15 kW and 300 pF.

Figure 18. Current Sense Circuit

The converter enters the cycle skip current mode if acontinuous over current condition is exists. Once a current
limit event is detected, a 90 mA current source begins
charging the capacitor on the CSKIP pin. If the capacitor
charges to 3 V, the converter enters a soft stop mode. A cycle
skip period of 330 ms is set with a 0.01 mF capacitor.
UNDER AND OVER VOLTAGE DETECTORThe NCP1562 facilitates design by incorporating tightly
controlled undervoltage (UV) detector. In addition, it
incorporates an independent overvoltage (OV) detector in
the same pin. The pin is biased using a resistor divider asshown in Figure 19.
Vin

R1

VOLT SECOND LIMIT AND FEEDFORWARD

To UVOV Pin
C16

A forward converter regulates the output voltage by
maintain a constant Volt−second (V−sec) product. If the
maximum V−sec product is exceeded, the transformer will
saturate and possibly damage to the system. Therefore, it iscritical to accurately control the V−sec product in a forward
converter.
The NCP1562 implements V−sec limit by generating a
Feedforward (FF) Ramp proportional to Vin and comparing
it to a 3 V reference. The ramp is generated by charging an
external capacitor (CFF) with a resistor (RFF) from Vin.
Feedforward is achieved by changing the slope of the FF
Ramp while maintaining a constant error voltage.
Feedforward reduces line voltage variations and provides afrequency gain independent of Vin making the system easier
to compensate.
The peak voltage of the ramp is set below 3 V undernormal operating conditions. The margin allows theconverter to quickly respond during a transient.
The FF components are calculated starting with thedesired maximum FF charge current, IFF. Given IFF, RFF iscalculated by dividing the maximum input voltage by IFF.
The FF capacitor is calculated using 41.

R4

Figure 19. UVOV Bias Circuit

The minimum operating voltage of the system iscontrolled by comparing the voltage on the UVOV pin to a
2 V reference, VOV. The system turn on threshold, Vin(UV),
is determined by the ratio of the resistor divider on the UV
pin as shown in equation 39.
Vin(UV) + VUV @(R1 ) R4)
R4

(eq. 39)

The maximum operating voltage, Vin(OV), is controlled bycomparing the voltage on the UVOV pin to an internal 3 V
reference, VOV. An internal current source (Ioffset(UVOV))sinks 50 mA into the UVOV pin once the UVOV voltage
exceeds 2.5 V. The voltage offset introduced by this current
source allows independent adjustment of Vin(UV) andVin(OV) (patent pending). The OV threshold depends on theratio of the resistor divider as well as the absolute value of
R1 as shown in equation 40.
Vin(OV) + VOV @(R1 ) R4)
R4

CFF +

) (Ioffset(UVOV) @ R1) (eq. 40)

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13

IFF @ V * sec(max)3V(eq. 41)

AND8273/D
soft−stop provides a controlled turn off without any
unwanted oscillations on the drain voltage.

Our transformer has a V−sec(max) of 62.4 V−msec.
Selecting an arbitrarily IFF of 1.75 mA, the Design Toolsuggest values of 43.4 kW and 479 pF for RFF and CFF,
respectively. Final values are 45.3 kW for RFF and 470 pF for
CFF. As duty ratio control is very important, the tolerances
for RFF and CFF are set at 1% and 5%, respectively.
SOFT−START

Soft−start slowly starts the converter and reduces stressduring power up. The NCP1562 implements soft−start bycomparing the voltage in the SS pin to the FF Ramp.
Soft−start is adjusted by placing an external capacitor,
CSS, between the SS pin and ground. The capacitor ischarged with a constant 10 mA current source. The peakvoltage of the FF Ramp is 3 V. Therefore, soft−start ends
once the SS voltage exceeds the FF Ramp or it exceeds 3 V.
Under steady state conditions the SS capacitor is charged to
3.8 V.

Figure 20. Converter Power Down using Soft−Stop

SOFT−STOP

The same capacitor is used for soft−start and soft−stop.
The minimum soft−start time is determined by the requiredsoft−stop period. A soft−start to soft−stop ratio of 1/10 is set
with the internal charge and discharge currents. If a different
ratio is required, a resistor can be placed between the VREF
and SS pins to increase the SS charge current.

The clamp capacitor in a forward topology needs to bedischarged while powering down the converter. If thecapacitor remains charged after power down it may damage
the converter. First, the resonant tank between Cclamp and
LMAG used for ZVS during normal operation will continue
to resonate after power down as long as energy is stored in
the capacitor. Second, a long reset time is applied to thetransformer during power up as duty ratio slowly increases
from 0%. If the capacitor is charged during power up, themaximum V−sec of the transformer may be exceeded. This
will push the transformer far into the third quadrant of theB−H curve, possibly saturating the transformer.
The NCP1562 solves these problems by using a novel
approach called soft−stop. Soft−stop reduces the duty ratio
until it reaches 0% prior to turn off. Duty ratio is reduced bydischarging the capacitor on the SS pin using a 90 mA current
source. The voltage of the clamp capacitor is given by 42. It
can be observed that the clamp capacitor voltage willapproach zero as duty ratio approaches zero.
V @D
Vclamp + in
1*D

BOARD LAYOUT

The converter is built to validate the design using a 4 layer
FR4, double sided board. The converter meets the industry
standard half brick (2.3 in. x 2.4 in.) footprint and pinout.
Power components are placed on the top layer (primary) andcontrol components on the bottom (secondary) layer. The
board is constructed using 2 oz copper. The top and bottom
layers are plated to 3 oz. to improve power dissipation. The
two inner layers are used for ground and signal routing.
During the layout process care was taken to:
1. Minimize trace length, especially for high current
loops.
2. Use wide traces for high current connections.
3. Use a single ground connection.
4. Keep sensitive nodes away from noisy nodes suchas drain of power switches.
5. Place decoupling capacitors close to ICs.
6. Sense output voltage at the output terminal to
improve load regulation.
The layers are numbered 1 through 4 from top to bottom
and are shown in Figure 21 through Figure 24. The top andbottom layers show the component location.

(eq. 42)

Empirically it is determined that a 0.1 mF is sufficient todischarge the clamp capacitor under all operating
conditions. The worst case condition for soft−stop is lightload at high line. During this condition, VEA is at its lowest
making the achievable soft−stop time a minimum for a given
capacitance. Figure 20 shows the drain of the main switch
during power down at high line and no load. As expected,

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14

AND8273/D

Figure 21. Layer 1 (Top)

Figure 23. Inner Layer 3

Figure 22. Inner Layer 2

Figure 24. Layer 4 (Bottom)

The layout files may be available. Please contact your sales representative for availability.

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15

AND8273/D
DESIGN VALIDATION

The top and bottom view of the board are shown in Figure 25 and Figure 26, respectively.

Figure 26. NCP1562 Demo Board Bottom View

Figure 25. NCP1562 Demo Board Top View

The circuit schematic is shown in Figure 27 and the bill of material is listed in Table 3.

www.onsemi.com
16

Figure 27. Circuit Schematic

www.onsemi.com

270 p

R8
32.4k

C24

0.1

C8

CS
470 p

R3
45.3 k

2.2

C4

R18
3.01 k
3
BC817

2
R11
4.22 k

1

Q1

U1

16
VAUX
Vin
15
UVOV OUT1
14
FF
PGND
13
CS
OUT2
12
GND CSKIP
11
RTCT
tD
10
SS
SYNC
9
VREF VEA

NCP1562A

22

R6
10 k

1
2
3
4
5
6
7
8

C7

0.1

47

47

C23

D1
= MBRM120ET1G
D2-D7 = MMSD914T1G
X1= FDD2582
X2= IRF6217PBF
X3-X6 = NTMFS4835NT1G

C12

C30

R9
15 k

0.01

C16

Vref

2.2

2.2

2.2

R1
523 k

C3

C2

C1

L1
1.5 m

27 p

R4
32.4 kJ5

J2+36-72 V
-

J1

C22
+

C31
+

0.1

C28

CS

1

C10

R5
44.2 k

X1

7

6T

4

4T
2

1

0.018

C14

D4

0.01

PS2703-I-M-A

3

2200 p

C27

U2

R17
10 k

4

X2

2

1

1000 p

C5

6
5

X4

R23
2.0

X3

U4B
7

1,2,3

SEC_PWR2

R2
5,6,7,8
33 m

4 C26

9

1T

8

TX1
51665

4

R16
10 k 3
100
100 p

R10

C13 0.01

C11

4.75
D1

R15

D2

D7

5,6,7,8
5,6,7,8
+
-

17

4

4

1,2,3

1,2,3

R24
10 k

3

1,2,3

5,6,7,8C15
2.2

SEC_PWR2

SEC_PWR1

4
R25
10 k

X5

2
Q2 1
BC807

R14
953

348

R13

2.0

R29

SEC_PWR1

D6

D3

4

X6

24.9

R26

1

49.9
C9
0.1

R12

5.9 k

4

4.22 k
C6 3
0.1
5

R7

4

150

8 LM258G

2
3

0.056

C25

47 150

D5

U4A

47

R30
348

R19
10

R28
2.49 k

R27
4.22 k1000 p

C29

150

C17 C18 C19 +C20 +C21 +

R20

1,2,3

5,6,7,8

L2
1.5 m

+
-

L3
1000 m

R22
open

R21
16.2 k

J4

+
3.3 V
-

J3

AND8273/D

AND8273/D
Table 3. BILL OF MATERIALS
Reference
C1−C4
C5,C29
C6,C8,C9,C28
C7
C10
C11
C12
C13,C16
C14
C15
C17,C18
C19,C20,C21
C22, C31
C23
C24
C25
C26
C27
C30
D1
D2−D7
J1,J2,J5
J3,J4
L1
L2
L3
R1
R2
R3
R4, R8R5R9R10R7, R11, R27
R12
R13, R30
R14
R15
R6, R16−R17, R24−R25
R18
R19
R20
R21
R22
R23,R29
R26
R28
TX1
U1
U2
U3
U4
X1
X2
X3−X6
Q1
Q2

Value
2.2
1000 p
0.1
22
1
100 p
300 p
0.01
0.018
2.2
47
150
47
0.1
470 p
0.056
0.01
2200 p
27 p

1.5 m
1.5 m
1000 m
523 k
0.035
45.3 k
32.4 k
44.2 k15 k100
4.22 k
49.9
348
953
4.75
10 k
3.01 k10
5.9 k16.2 kopen
2.00
24.9 k2.49 k

BC817−25
BC807−25

Part
C4532X7R2A225MT
VJ0805A102JXAAT
VJ0805Y104KXAAT
C4532X5R1C226M
C3216X7R1E105M
VJ0805A101KXAAT
VJ0805A301JXAAT
VJ0805Y103KXAAT
VJ0805Y183KXAATC2012X5R1A225K
C3225X5R0476M
T520B157M006ATE045
595D476X9016C2T
C3216X7R2A104K
VJ0805A471JXAAT
VJ0805Y563KXXAT
C3216X7R2J103M
C4532X7R3D222K
VJ0805A270JXAATMBRM120ET1G
MMSD914T1G
3103−2−00−21−00−00−08−0
3231−2−00−34−00−00−08−0
DS3316P−152
51666
DO1606T−105
CRCW0805523KFKEA
LRC−LRF3WLF−01−R033−F
CRCW120645K3FKEA
CRCW080532K4FKEA
CRCW080544K2FKEA
CRCW080515K0FKEA
CRCW0805100RFKEA
CRCW08054K22FKEA
CRCW080549R9FKEA
CRCW0805348RFKEA
CRCW0805953RFKEA
CRCW12064R75FKEA
CRCW080510K0FKEA
CRCW08053K01FKEA
CRCW120610R0FKEA
CRCW08055K90FKEA
CRCW08051622FKEA
CRCW0805...
CRCW12062R00FKEA
CRCW080524K9FKEA
CRCW08052K49FKEA
51665
NCP1562ADBR2G
PS2703−1−M−A
TLV431ASNT1G
LM258DG
FDD2582 (*SUD25N15−52)
IRF6217PBF
NTMFS4835NT1G
BC817−25LT1G
BC807−25LT1G*Alternate Part number
1. TDK components can be ordered at (847) 803−6100.
2. Vishay Components can be ordered at (402) 563−6866.
3. Payton components can be ordered at (561) 989−9585 ext. 13.
4. Kemet components can be ordered at (480) 831−2151.

www.onsemi.com
18

Vendor
TDK
VishayVishayTDKTDKVishayVishayVishayVishay
TDK
TDK
Kemet
VishayTDKVishayVishayTDKTDKVishayON Semiconductor
ON Semiconductor
Mill−Max
Mill−Max
Coilcraft
PaytonCoilcraft
VishayIRC Electronics
VishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayPaytonON Semiconductor
NECON Semiconductor
ON Semiconductor
Fairchild (Vishay)IR
ON Semiconductor
ON Semiconductor
ON Semiconductor

Comments
100 V
50 V
16 V
25 V, 20%
If not Available, use 270 pF

6.3 V
6.3 V
16 V
100 V
10%
630 V
2000 VUse only if C12 is 270 pF
20 V, 1 A Schottky
100 V Diode40 mils
80 mils
Input Choke
Output Choke
Aux. Supply Choke
Current Sense R
0.25 W

Power Tx
Controller
Optocoupler
Shunt Reference
Op Amp
150 V MOSFET
150 V PFET
30 V MOSFET
npn transistor
pnp transistor

AND8273/D
95

The converter performance is evaluated and compared toour original goals. The evaluation criteria includes:
1. Open loop frequency response.
2. Efficiency.
3. Line and load regulation.
4. Step load response.
5. Output voltage ripple.
The open loop response is measured injecting an AC
signal across R19 using a network analyzer and an isolationtransformer as shown in Figure 28. The open loop responseis the ratio of B to A.

94
EFFICIENCY (%)+

To Error Amplifier
Inverting Input

Vin = 36 V

89
88

0

Reg(load) +

25

30

180

30

135

20

Simulated Phase 90
45

Measured Gain0
Measured Phase

Vout(no load)(eq. 44)

Line regulation is measured below 0.01% and load
regulation is measured below 0.23%.
The dynamic response of the converter at 48 V isevaluated stepping the load current from 50% to 75% andfrom 75% to 50% of Iout(max). The step load response isshown in Figure 31.

−45

−10

−90

Simulated Gain

−30

−135

−40

−180

10

Vout(no load) * Vout(full load)(eq. 43)

PHASE (°)

40

1

20

DVout
Reg(line) +
DVin

REF
A Network
AnalyzerB

The measured and calculated open loop responses areshown in Figure 29. The measured phase margin is 57_ andthe crossover frequency is 16.7 kHz. A good correlation isobserved between the simulated and calculated responses up
to around 30 kHz. The simulated tool does not show thecomplex zeros and P1,2(AC) of the active clamp.

−20

15

Figure 30. Efficiency vs. Output Current

Figure 28. Open Loop Frequency Response
Measurement Setup

010Line and load regulation are calculated using 43 and 44,
respectively.
1:1

Z1

5

Iout, OUTPUT CURRENT (A)

Rbias

MAGNITUDE (dB)

90

86
85

R19

0.1

Vin = 76 V

91

Vout
−

out

10

92

87

Lout
To Converter C

Vin = 48 V

93

100

Figure 31. Output Voltage Response to a Step Loadfrom 22.5 A to 15 A.

The output voltage ripple is measured at 16 mV at highline and full load. It is significantly below the 50 mV target.
The output voltage ripple waveform at high line and full load
is shown in Figure 32.

FREQUENCY (kHz)

Figure 29. Measured and Calculated Open Loop
Frequency Responses

The full load efficiency of the converter is measured
above 91% across the complete input voltage range.
Figure 30 shows the efficiency vs output current at 36 V,
48 V and 72 V. The peak efficiency is measured at 92.8%.

www.onsemi.com
19

AND8273/D

Air Flow
Figure 34. Thermal Image of the Bottom of the Board
at Low Line and Full Load Condition
Figure 32. Output Voltage Ripple at High Line andFull Load
THERMAL PERFORMANCEThis demo board is designed to operate with airflow as ina telecom system. Airflow is required if the converter
operates above 50% of its rated power. Optimum cooling isachieved when air flows from the output side to the input
side.
The thermal performance of the board is evaluated using
an infrared camera. Figure 33 through Figure 36 show
several images of the board at full load. Images include top
and bottom layers at low and high line. All images weretaken with airflow from the output side to the input side.

Air Flow
Figure 35. Thermal Image of the Top of the Board atHigh Line and Full Load Condition

Air Flow
Air Flow
Figure 33. Thermal Image of the Top of the Board at
Low Line and Full Load Condition

Figure 36. Thermal Image of the Bottom of the Board
at High Line and Full Load Conditionwww.onsemi.com
20

AND8273/D
The converter provides excellent transient response.
Output voltage ripple is measured at 16 mV. Phase marginand crossover frequency are measured at 57_ and 16.7 kHz,
respectively.
This demo board is designed to demonstrate the featuresand flexibility of the NCP1562. This design should not be
used for production or manufacturing purposes.

Most of the losses on the board are on the main switch andsynchronous rectifiers. The synchronous rectifier losses are
dominated by conduction losses. At low line, QFW has thehigher duty ratio and thus the higher power dissipation asshown in Figure 33. At high line, QREC has the higher duty
ratio and thus the higher power dissipation as shown in
Figure 35.
The NCP1562 demo board thermal performance can be
optimized by using heatsinks, integrating magnetic
components on the board, using additional layers andplacing the synchronous rectifiers farther away from eachother.
Please keep in mind that this is a demonstration board to
showcase the flexibility of the NCP1562. A commerciallyavailable dc−dc converter will use advanced packaging andmanufacturing techniques to maximize power dissipation ofcritical components.

REFERENCES

1. Pressman, Abraham I. Switching Power Supply Design.
2nd ed. New York, NY: MacGraw Hill.
2. Ridley, Ray. “The Evolution of Power Electronics.”
Switching Power Magazine.
3. High Performance Active Clamp/Reset PWM Controller
Datasheet NCP1562, www.onsemi.com.
4. Dhaval Dalal and Larry Wofford, “Novel Control IC forSingle Ended Active−Clamp Converters,” in HFPC’95
Conf. Proc., pp. 136−146, 1995.
5. G. Stojcic, F. Lee and S. Hiti, “Small−Signal
Characterization of Active Clamp PWM Converters,” in
VPEC Seminar Conf. Proc., pp. 237−245, 1995.

SUMMARY

A 100 W converter is designed and built using the active
clamp forward topology. The converter is implemented
using the NCP1562. The full load efficiency is measured
above 91% over the complete operating range.

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