FRT Operation for Single-Phase Grid-Tied
Inverter with Active Power
Decoupling Capability
Jun-ichi Itoh1, Satoshi Nakamura1, Satoshi Nagai1, and Hiroki Watanabe1
1

Nagaoka University of Technology, Japan

Abstract-- This paper proposes a Fault Ride-Through(FRT) operation for a single-phase grid-tied inverter with anactive power decoupling capability. The power decoupling
circuit achieves the double-line-frequency power pulsationcompensation with a small capacitance; consequently, atransient response with a sudden load change becomesworsen because a large energy buffer, i.e. bulky electrolytic
capacitors, does not apply. In particular, high overshootvoltages occur in a DC-link voltage when the grid voltage sagof the single-phase grid occurs, resulting in the interrupt of
the FRT operation due to the over voltage protection. In
order to solve this problem, the buffer capacitance is designedin the consideration of the overshoot amount of the DC-link
voltage. The theoretical value of the overshoot amount isverified with a 1-kW prototype. As an experimental result,
The error between the experimental and the calculation value
is within 10%. Furthermore, the proposed control achieved
both the FRT operation and the active power decoupling
capability.
Index Terms—DC-AC Inverters, FRT Operation, Active
Power Decoupling,

I. INTRODUCTION
In recent years, photovoltaics (PV) systems have been
actively employed to solve environmental problems suchas global warming [1]-[3]. In the PV systems, each PV
module is connected to a single-phase grid by a DC tosingle-phase AC converter which consists of a boost
converter and the voltage source inverter (VSI).
Furthermore, maximum power point tracking (MPPT) is
applied to optimize the power generation efficiency.
However, an instantaneous power pulsation due to thesingle-phase grid fluctuates the PV generated power,
which results in low power generation efficiency.
Therefore, power decoupling capability is necessary in the
DC to single-phase AC converter to guarantee
instantaneous power pulsation.
A passive power decoupling method with large
electrolytic capacitors is a typical solution. However, a life
time of the electrolytic capacitors depends on theenvironmental temperature according to Arrhenius
equation. As a result, system reliability is limited due tothe electrolytic capacitors. On the other hand, active power
decoupling methods such as DC active filters have been
researched to solve the life-time problem [4]-[13]. In thesemethods, the single-phase power pulsation is compensatedby a small capacitance, leading to the application of film
or ceramic capacitors instead of the bulky electrolytic
capacitors. As the result, the converter reliability is nolonger restricted by the life time of the electrolytic
capacitors.
Meanwhile, with the expansion of the PV systems, local
grid voltage sag might occur when several PVs are
disconnected from the grid, which might lead to awidespread loss of generation. In order to prevent thisproblem, a Fault Ride-Through (FRT) capability isrequired to continue the power converter operation during
the grid voltage sag [13]-[24]. However, in the power
converter employing the active power decoupling
capability, high overshoot and undershoot voltages occur
in a DC-link voltage during the grid voltage sag due to thelack of a large energy buffer, i.e. a large capacitance.
Overshoot might trigger over voltage protection, andundershoot distorts the input / output current during theDC-link voltage falls below the grid voltage. Therefore
overshoot and undershoot voltages might interrupt the
FRT operation. Reference [13] proposes an FRT operation
with an active power decoupling scheme. However, theamount of the DC-link voltage overshoot has not been
considered during the voltage sag. In addition, in the otherpapers, the DC-link voltage overshoot in worst condition
at voltage sag is not sufficiently studied with the power
pulsation and the small capacitance of the DC-link.
In this paper, a control method of the FRT operation
with the small energy buffer is proposed. First, theprinciples of following contents are shown in section II;(1) mechanism of the power pulsation compensation, (2)reduction of the capacitance for the buffer capacitancewith the active power decoupling method, (3) the design
method of the steady state buffer capacitance. Second, theDC-link voltage overshoot amount at the voltage sag is
obtained by converting the transfer function of the control
block. Moreover, the overshoot amount is shown by using
an approximate equation. The DC-link capacitance isdesigned under the condition that the DC-link capacitanceis limited by considering the DC-link voltage overshoot atthe voltage sag. Finally, the FRT operation of the grid-tied
inverters with the small capacitance is confirmed byexperiments. The experiments are conducted with the gridconnection of 100 V or 200 V. The experimental results

show that the DC link voltage value follows the command
value even during the voltage sag. Furthermore, the output
power recovers after the grid-voltage recovery as before
the voltage sag. Therefore, the grid-tied inverter with thesmall buffer capacitance is possible to achieve the FRT
operation in the worst condition of the voltage sag. By
using the theoretical value with the approximate equation,
the error with experimental value is less than 10%.

iinv

ic
ichop

iac

Vc

Cbuf

iL

Lac

vdc

Vac

Lin

iin
Vin

II. CIRCUIT CONFIGURATION AND ACTIVE POWER
DECOUPLING METHOD(a) Grid-tied inverer with power decoupling circuit

VIN

vc
VCmax
VCmin
t
0

0

t

t

0

t
iac=Iacp sin(t)
t

pout

＝

＝

t＝ 0
Input powerpin [W]

iac
Iacp
t 0

pbuf

0

Vacp
0

＋

ic(LPF)0
pin

vac
vac=Vacp sin(t)

＋

IIN

＝

B. Operation principle
Fig. 1 (b) shows the relationship between the input
power, the instantaneous output power, and thecompensation power of the energy buffer in the active
power decoupling circuit. Firstly, the instantaneous output
power Pout when the output voltage and current aresinusoidal waveforms is expressed as
V I
Pout  out out (1  cos 2 t )(1)
2
where Vout is the peak grid voltage, Iout is the peak output
current, and  is the angular frequency of the grid.
According to (1), the single-phase instantaneous power
pulsation occurs at twice the frequency of the gridfrequency. Moreover, the input power Pin is expressed as
1
Pin  Vout I out  Vin I in(2)2
where Vin is the DC input voltage, and Iin is the DC input
current. In order to keep the input power constant, i.e. theinstantaneous power Pin, the frequency component of thesecond term in (1) is actively compensated by the buffer
capacitor. Therefore, the instantaneous power Pbuf of thebuffer capacitor is controlled by1
Pbuf   Vout I out cos(2 t )(3).
2
The active power decoupling circuit charges anddischarges the differential power between the input andoutput power. In addition, the charging or discharging
energy of the buffer capacitor E is expressed as
1
E  Cbuf V 2
(4)
2
where Cbuf is the buffer capacitance, and V is the buffer
capacitor voltage peak to peak value. According to (4), thecompensation energy in DC-link capacitor is achieved by

VSI

Power decoupling
circuit＋

A. Circuit method
Fig. 1 (a) shows the circuit configuration which consistsof the active power decoupling circuit based on the boost
converter and the VSI. The active power decoupling circuitachieves the power decoupling operation by the small
capacitance Cbuf. Therefore, the single-phase power
pulsation is compensated by a small capacitance, leading
to the application of film or ceramic capacitors instead of
the bulky electrolytic capacitors. In addition, this circuit isalso utilized for a boost-up operation of a PV input voltage.
Consequently, the proposed circuit does not require
additional components such as an inductor for the power
decoupling capability.

t ＋0

Buffer powerpbuf [W]t

Output power
pout [W](b) Principle of power decoupling
Fig. 1. Grid-tied inverter with active power decoupling circuit andprinciple of power decoupling. The circuit consists of typical boost
converter and small buffer capacitance Cbuf. This circuit does notneed additional components for the power decoupling. According
to Fig.1 (b), the differential power between the input and output
power is compensated by small capacitance Cbuf.

increasing the buffer capacitance Cbuf as in the passive
power decoupling method. On the other hand, the active
power decoupling circuit actively charges and discharges
the buffer capacitor to control the buffer energy, which
implies V is increased instead of increasing Cbuf. Note
that, the compensation power for the power pulsation Wc
is expressed as follows


4
V I
p
1
WC  Vout I out  cos  2t  dt  out out  out

2
2



4

(5).

In addition, the capacitor power is obtained from thecapacitance and the buffer capacitor voltage and expressed
as
1
1
2
2
(6)
W  C V
 C V
C

2

buf

C max

2

buf

C min

where VCmax and VCmin are the maximum and minimum
values of the allowable voltage fluctuation, respectively.
The required capacitance is calculated from (5) and (6),and expressed as

2WC
(7).
VC max 2  VC min 2
According to (7), the capacitance of the buffer capacitor ispossible to decrease as the fluctuation of the DC-link
voltage increases. However, the design of Cbuf in (7) is a
design value for a steady-state operation. Therefore, theload fluctuation and the voltage sag operation are notconsidered in (7). The design method considering thetransient phenomenon is described in the next chapter.
Cbuf 

100

Ratio to output before
Voltage sag [%]III. CONTROL METHOD AND CHALLENGES OF FRT

80% or more of the output power before the voltage sagwithin 1.0 second of the voltage recovery

80

Voltage sag(withmin 1.0 s)

OPERATION

B. Challenges of FRT operation with active power
decoupling capability
In general, the DC-link voltage control is employed in the
VSI control, whereas the input current control is applied in
the boost converter to achieve MPPT. Consequently, theDC-link voltage control bandwidth is designed to low to
avoid the interference of the power pulsation frequency;
hence, the high overshoot and undershoot voltage in DC
link when the sudden load change might occur due to theDC-link capacitance minimization thank to the active
power decoupling capability.
Fig. 3 shows the simulation results of the FRT
operation with the active power decoupling capability inthe ideal condition. Note that the active current becomes
zero, whereas the reactive current is provided from the VSI

1.0

0.0
(Voltage recovery)

A. FRT requirement in grid interconnection
A power converter in a photovoltaic system might halt
operation when voltage sag occurs or at the voltage
recovery. Therefore, FRT operation controls the voltage
and frequency fluctuation during the grid voltage
recovery and supports the recovery of the output power.
Fig. 2 (a) shows the operation of FRT at the momentary
voltage drop. In Japan, the FRT operation after thevoltage recovery is required that the output power isrecovered to 80% of the output power before theoccurrence of the voltage sag. Furthermore, the output
power recovery must be within one second after thevoltage recovery. Table I shows the FRT requirements ofseveral country including Japan. The FRT requirements
are different in each country.
There are countries in Europe having the FRT
requirements that is required to inject the reactive current
during the voltage sag. Fig. 2 (b) shows an FRT operationin which a reactive current is injected to the grid side
during voltage sag. The reactive current is injected toassist the grid voltage recovery. After the grid voltage
recovery, the inverter output power is recovered by
gradually switching from the reactive current to the active
current.

(a)
Grid voltage [V]Time[s]

FRT requirements in Japan
Voltage sag period

Output current [A]Injection reactive current(b) Operation of the voltage sag period
Fig. 2. FRT operation for grid-tied inverter.

600

Large over shoot and undershoot occur at voltage
recavary
DC-link voltage Vdc [V]400200
Output current Iac [A]Output current is distorted due
to under shoot of Vdc

20
0
-20
Output voltage Vac [V]
400
200
0
-200
-400
Fig. 3. FRT operation with small DC-link capacitance when DCvoltage control is applied to VSI control. High overshoot andundershoot occur at the grid voltage recovery. As the result, theoutput current distorts due to undershoot of Vdc.

Table I. FRT requirements.
country

Voltage drops down

Voltage sag time

Voltage or output power recovery timeJapan
Germany
BritishAmerica

0%
0%
0%
20 %

1000 ms
150 ms
140 ms625 ms

80% more than the output power within 1.0 s
90% more than the grid-voltage within 1.5 s
90% more than the output Power within 1.0 s
90% more than the grid voltage within 3.0 s

C. Control method
Fig. 4 shows the proposed control block diagram of the
proposed circuit. In this paper, the DC-link voltage control
is performed on the VSI side or the power decoupling side
respectively. In the former, the DC-link voltage control is
employed in the VSI circuit together with the output
current iout control. In the later, the DC-link voltage control
is employed in the power decoupling circuit together with
the input current iin control. Note that the power
decoupling control is achieved by feeding forward thecapacitor current reference at the output of the DC-link
voltage control. The charge and discharge current for the
buffer capacitor is expressed asPic  out cos(2 t )(8)vc
where ic is the feed forward current to achieve the power
decoupling. The VSI control is composed of the phasesynchronization with the phase locked loop (PLL) control,
and the output current iac control. The phase of the output
current advances 90 degrees during the grid voltage sag.
The difference between the DC-link voltage control
employed in the VSI side and that employed in the power
decoupling side is that the power supply source for the DClink is from the grid voltage or the solar cell voltage. The
DC-link voltage control employed in the VSI side cannot
maintain the DC-link voltage during the voltage sag
because there is no power supply source for the DC-link
capacitor. Therefore, in order to control the DC-link
voltage during the voltage sag, the DC-link voltage control
is employed in the power decoupling side to supply thepower from the solar cell to the DC-link capacitor.
D. Detection method of voltage sag
Fig.5 shows the voltage-sag detection method isachieved by detecting the grid voltage and using the Highpass filter (HPF) on the control side. The grid voltage vac
is defined as vacsin θ. Moreover, Differential of vacsinθ
which is vaccosθ is derived by the grid voltage and HPF.
The magnitude of the grid voltage vac can be expressed as(9).
vac2 sin   vac2 cos   vac
HPF differentiates the grid voltage. According equation(9), the magnitude of the grid voltage is constant regardlessof the phase of the grid voltage. The grid voltage drops toPower decoupling circuit control
Feed forward control
for power decoupling
ic*
+
+
+
PI
ｰ ACR
+

Pac
cos( )
vc

+

iin*

vin

iL
iac

vac

PLL

 + +frt
vfrt

6

Gate
signals

MUX

0

2

MUX

1
Vdc

carrier*
iac* ｰ ACR++ AVR vdc Iout
+
+
Vdc*
PI
sin()PIVinｰvdc vac

1
Vdc

PWM

Vac*
Iac *
vc

Voltagerecoveryoperation1
/2

Normaloperation
vfrt

0
0

frt
VSI control(a) AVR with grid-tied inverter
Power decoupling circuit control
Vac*
Feed forward control
Pac
for power decouplingcos( )
Iac *
vc
vc
ic*
AVR
ACR
vdc iin* +
+
+
+
PI
Vdc*
PI
+
Vin
ｰ
ｰ
+
iL
vdc
vin
i ac
Iout*

vac

sin()

PLL

iac*+

vac

ｰ ACR + +
PI

1
Vdc

6

Gate
signals

carrier

MUX

frt

+

1
Vdc

PWM

or PV during the grid voltage sag. As shown in Fig. 3, thegrid-tied inverter operates stably before the grid voltage
sag. However, the output current distorts when the DC
link voltage undershoots less than the instantaneous gridvoltage after the grid voltage recovery. Therefore, the DClink voltage minimum value is requried to keep higher than
the grid-voltage-peak value at the grid voltage drop andrecovery. In the active power decoupling method, the DClink capacitance is reduced by largely varying the DC-link
voltage; this leads to a large overshoot and undershootoccurring at the voltage drop and recovery. Therefore,
design of the buffer capacitance is necessary to consider
not only the steady state operation but also the voltage sag
operation.

+

MUX

vfrt

0

2

Normaloperation
vfrt

frt

0
0

Voltagerecoveryoperation1
/2

VSI control(b) AVR with power decoupling circuit
Fig. 4. Control block diagram of proposed circuit. The feedforward
control and the DC-link voltage control are applied to the power
decoupling circuit control to achieve both FRT operation and thepower decoupling operation.
Grid voltage
vac sin( )vac cos( )HPF
Eq.(9)

Grid voltage
value vac

Fig. 5. Voltage-sag detection method.

0 V due to the voltage sag, resulting the value of equation(9) becoming zero. The detection of the voltage sag isrealized by comparing the grid voltage with the thresholdvalue. However, the use of HPF causes a detection delay
time. In order to reduce the delay time, it is necessary toraise the cutoff frequency of the HPF. However, thedetection error of the instantaneous drop occurs due to thehigh cutoff frequency. The cutoff frequency of HPF isdesigned to be ten times compared to the grid frequency.

IV. CONSIDERATION OF DC-LINK VOLTAGE OVERSHOOTAT VOLTAGE SAG

ic

In a power decoupling circuit, the amount of the DClink voltage overshoot at the voltage sag depends on theload fluctuation. The DC-link voltage overshoot is causedby fluctuations in the buffer capacitor current ic and theinverter input current iinv due to the load fluctuation.
Therefore, the overshoot of the DC-link voltage isdetermined by the disturbance response such as the buffer
capacitor current and the inverter current.
Fig. 5 (a) shows the control block diagram of the power
decoupling side. In this control block, the Auto current
regulator (ACR) response is much higher than the auto
voltage regulator (AVR) response. Thus, the ACR gain is
set to 1.0. Kpv and Tv of the proportional-integral (PI)controller for AVR are expressed by the following
equations.
(10)
K pv  2nv C
2

nv

c

Fig. 6 (a) shows the controller on the power decouplingside including the inverter-output-current controller. The
disturbances in the power decoupling controller occur due
to the output current iac fluctuation at the voltage sag.
Fig. 6 (b) shows the disturbance-transfer-function
model from the inverter current to DC-link voltage in Fig.
6 (a). Generally, an overshoot amount due to the
disturbance is obtained by the transfer function from a step
response or a ramp response of disturbance with Laplacetransform and inverse Laplace transform. The transfer
functions of ACR and AVR are second-order systems.
Therefore, the disturbance transfer function of AVR
including ACR is a fourth-order system. The transfer
function of the fourth order system is converted to the time
domain by inverse Laplace transform. However,formalizing the amount of overshoot requires complicatedcalculations in the forth-order transfer function. Therefore,
the overshoot of the DC-link voltage is derived by anapproximate equation. The elements required to derive theovershoot of the DC-link voltage are the variation of theoutput power Pout, the buffer capacitance Cbuf, the average

Kpv (

ｰ

vdc iL+Vin

1  sTv)
sTv

ViniL* vdc iconv++ 1 +ic sCbuf vc

Vdc

Control block diagram of power decoupling side
ｰ

Iinv

+

AVR

(a)

1
sCbuf

ｰ
Vin
vdc

Vdc

vdc
Vin

Kpv (

1  sTv
)
sTv

AVR

(b)

Inverter current disturbance response of power decoupling
controller
Fig. 5. Derivation of disturbance response.

*
Iout

(11)

where is the damping coefficient, and nv is the angularfrequency of the voltage controller.
Fig. 5 (b) shows the disturbance-transfer-function
model from the inverter current to DC-link voltage in Fig.
5 (a). The disturbance transfer function of the inverter
input current iinv is expressed as
1
 s
C
(12),
Gload _ iinv ( s )  2
s  2nv s  nv 2
where s is the Laplace operator. Similarly, the disturbancetransfer function due to the buffer capacitor current ic
expressed by (13)
1 Vin

s
C vdc
Gload _ i ( s )  2(13).
s  2nv s  nv 2

+

ｰ

PLL

+ frt

+

MUX

v frt

vout

iac*

iac

sin( )

vLac

PI

ｰ ACR

0

2

vac
vdc

ic
Vdc*

+

iac

1
sLac

iinv

vin

+
ｰ
vL
iL
vdc iL+
1 +
Vin +
1
PI
Vin
i
v
sL
conv ic sCbuf vc
iL*
dc
in
ACR

PI
ｰ AVR

+
Vdc

(a) Control block diagram of power decoupling side including
inverter-output current*
Ioutsin( )PLLiac*

 + +  frt

iac

ni 2
2
s  2ni s  ni 2

MUX

iinv

vac
vdc

ACR
0

2

1
s
C
s 2  2nv s  nv 2


Vdc

AVR

vout

v frt

(c)

Output current disturbance response of power decoupling
controller

Fig. 6. Derivation of disturbance response with inverter-outputcurrent controller.
2.50E-05

Average buffer capacitor Voltage Vc
Vc = 200 V

2.00E-05

Vc = 400 V

coefficient value K

TV 

Vdc*

vin

iinv

1.50E-05

Vc = 600 V

1.00E-05

5.00E-06

0.00E+000
0

50

100

150

200

250

300

350

400

Response angular frequency of AVR nv [rad/s]

Fig. 7. Coefficient K versus AVR response angular frequency nv
and buffer capacitor average voltage Vc.

voltage Vc, and the AVR response angular frequency nv.
The DC-link voltage is proportional to the output power
and inversely proportional to the buffer capacitance. The
approximate equation is expressed asVdc   K

Pout
Cbuf

Table II. Experimental conditions with 100-V grid-connection.

(14).

According to (14), the buffer capacitance considering theovershoot of the DC-link voltage is expressed as
Cbuf   K

Pout
Vdc

(15).

The coefficient K depends on the AVR response angularfrequency nv and the average voltage of the buffer
capacitor average voltage Vc.
Fig. 7 shows the coefficient K with the buffer capacitor
average voltage Vc and the AVR response angularfrequency nv. Fig. 7 is considering the ACR response
angular frequency is much larger than the AVR response
angular frequency. The coefficient K becomes small whenthe AVR response angular frequency nv is high. However,the coefficient K is almost constant in the high response
angular frequency range of AVR. Moreover, the rising
limit of the AVR response angular frequency depends on
the ACR response angular frequency. The buffer capacitor
average voltage Vc becomes high when the coefficient K
becomes small. The reason is that more energy is required
to raise the buffer capacitor voltage according to (4) and(6). However, raising the average voltage of the buffer
capacitor also increases the required withstand voltage ofthe switching devices. Therefore, the buffer capacitance isdesigned by the required withstand voltage of theswitching devices.

Quantity

SymbolValue

Input voltage
Output voltage
Rated power
Dead time
boost inductor
buffer capacitor
DC-link voltage
Interconnected inductor
Switching frequency
Voltage sag time

Vin
Vout
P
Tdt
L
Cbuf
vdc
Lac
fsw
Tvs

100 V
100 V
500 W
3.0 ms
3 mH
55 mF
300 V
6 mH
20 kHz
100 msDC-linkvoltage 100[V/div]

100 V
Input current 5[A/div]000Grid voltage 200[V/div]0
Output current 10[A/div]

50[msec/div](a) DC-link voltage control employing in the VSI control
DC-linkvoltage 100[V/div]
424 V(overshoot 41.3%)

Input current 5[A/div]0

160 V(undershoot 46.3 %)0

V. EXPERIMENTAL RESULT
A comparison of the case for DC-link voltage control is
performed in VSI side and the power decoupling side.
Table II shows the experimental conditions.
Fig. 9 shows the FRT operation during the grid voltage
sag. Note that in order to consider the worst case of the
maximum DC-link voltage overshoot, the voltage sag
occurs when the DC-link voltage reaches the maximum
voltage ripple during the steady-state operation.
Fig. 9 (a) shows the FRT operation when the DC-link
voltage control is employed in the VSI control. During thegrid voltage sag, the DC-link voltage control employing inthe VSI control cannot regulate the DC-link voltage. Thisis because there is conversion loss existing in the power
converter, whereas the input power is set to zero during thevoltage sag. As a result, the DC-link voltage drops below
the maximum value of the grid voltage to the input voltage(100 V). The grid voltage recovers when the DC-link
voltage maximum value is lower than the grid voltage
value. Therefore, the input and the output current are
distorted. Eventually, the protection circuit operates, andthe operation of the grid-tied inverter is halted.
Fig. 9 (b) shows the FRT operation when the DC-link
voltage control is employed in the power decoupling0
Grid voltage 200[V/div]0
Output current 10[A/div]

50[msec/div](b) DC-link voltage control employing in power decoupling circuit(nv = 100 rad /s)
DC-link voltage 100[V/div]
392 V(overshoot 30.7%)

192 V(undershoot 36.0 %)Input current 5[A/div]000Grid voltage 200[V/div]0
Output current 10[A/div]

50[msec/div](c) DC-link voltage control employing in power decoupling circuit(nv = 200 rad /s)
Fig. 9. FRT operation during grid voltage sag at 100 V gridconnection.

circuit. Since the energy required to maintain the voltage
is supplied from the input side even during a voltage sag,
it is observed that DC-link voltage value follows thecommand value even during the voltage sag. As a result,the output current distortion does not occur even after thegrid voltage recovery. Furthermore, the DC-link voltage
overshoot and undershoot are suppressed to 41.3%(124 V)
and 46.7%(140 V) for the DC-link average voltage (300
V). The DC-link voltage minimum value is always higher
than the grid voltage maximum value. Thus, the FRT
operation is achieved without any distortion of the input
and the output current. By using the overshoot amountwhich used the approximation formula in Chapter 4, thetheoretical calculation is derived by (14) as K = 1.5*10-5.
As the result, the amount of the DC-link voltage overshootis 136 V. The error between the experimental and thecalcuration value is 8.8%.
Fig. 9 (c) shows the AVR response angular frequencychanged to 200 rad / s from the condition of Fig. 9 (b). The
DC-link voltage overshoot and undershoot are suppressed
to 30.7% (92 V) and 36.0% (108 V) for the DC-link
average voltage (300 V). The overshoot amount at (14) is
calculated as K = 1.05*10-5. Thus, the amount of the DClink voltage overshoot is 96 V. The error between theexperimental and the calcuration value is 4.2%.
Furthermore, raising the AVR response angular frequency
reduces not only the overshoot of DC-link voltage but also
the undershoot of DC-link voltage.
Fig. 10 shows the experimental results of the FRT
operation with the designed buffer capacitanceconsidering the overshoot obtained in Chapter 4. Since themaximum rated voltage of IGBT is 600 V which is used in
the experiment, the DC-link voltage maximum value
including overshoot is designed to be 500 V. Table III
shows the conditions of this experiment.
Fig. 10 (a) shows the waveform from start of the voltage
sag to the output power recovery. In the experimental
waveform, the grid-tied inverter is possible to continue theoperation from the start of the voltage sag to the recover ofthe output power. However, the DC-link voltage
maximum value (262 V) becomes lower than the gridvoltage maximum value (282 V) due to the DC-link
voltage undershoot at the voltage recovery. Although, theinput and output current distortion do not occur. Therefore,
the buffer capacitance design is also necessary to consider
the DC-link voltage undershoot at the grid voltage reovery.
Fig.10 (b) shows the magnified waveform at theoccurence of a voltage sag. At the start of the voltage sag,the output current is confirmed to switch from the active
current to the reactive current. The overshoot amount ofDC-link voltage is 20.0% (100 V) of the DC-link averagevoltage (400 V). Thus, the DC-link voltage is suppressed
to around 500 V. Note that the overshoot amount with (14)is calculated as K = 1.05*10-5. As the result, the amount of
the DC-link voltage overshoot is 105 V. The error between
the experimental and the calcuration value is 4.8%.
However, the DC-link voltage is fluctuated due to theresonance of the input current at the start of the voltage sag.

Table III. Experiment parameters with 200-V grid-connection.
Quantity

SymbolValue

Input voltage
Output voltage
Rated power
Response frequency of AVR
Dead time
boost inductor
buffer capacitor
DC-link voltage
Interconnected inductor
Switching frequency
Voltage sag time

Vin
Vout
P

200 V
200 V
1.0 kW
200 rad/s
3.0 ms6 mH
100 mF
400 V
12 mH
20 kHz
100 ms

nv
Tdt
L
Cbuf
vdc
Lac
fsw
Tvs

DC-link voltage 100[V/div]

262 V

Input current 5[A/div]00Grid voltage 300[V/div]0
Output current 10[A/div]

50[msec/div](a) Operation waveform with minimum buffer capacitor design
DC-link voltage 100[V/div]

500 V(overshoot 5.5%)

Input current 5[A/div]00Grid voltage 300[V/div]0
Output current 10[A/div]

5[msec/div](b) Magnifiged waveform at the start of voltage sag
Fig. 10. Operating waveform by minimum buffer capacitor design
at 200 V grid-connection.
Table Ⅳ. Comparison of theoretical and experimental value for
DC-link voltage overshoot.
Verification conditions

Theoretical Measured Error
Value
value
Rate
[V]
[V]
[%]

Pout
waveform [W]Cbuf nv
Vc
K[mF] [rad/s] [V] [10-5]

Fig.9 (b)

500

55

100

200

1.5

136

124

8.8

Fig.9 (c)

500

55

200

200

1.05

92

96

4.2

Fig.101000 100

200

200

1.05

105

100

4.8

The resonance frequency of the input current fluctuation is
1 kHz, which is caused by the input LC filter resonance.
Table Ⅳ shows the comparison between the theoreticaland the experimental value for the overshoot amount of theDC-link voltage. From the Table IV, the error between thetheoretical and the experimental value is large when the

AVR response angular frequency is low. The cause of thelarge error is that the coefficient K is used as theapproximate equation for the overshoot amountcalculation. Other reasens of the error are that the ACR
response angular frequency is not included in the theapproximate equation and the delay time of the voltage sag
detection by HPF is not considered.

VI. CONCLUSION
In this paper, the FRT operation of the grid-tied
inverters with the small capacitance was proposed. The
analysis of the minimization limitation for the DC-link
capacitance considering the overshoot voltage during thegrid voltage sag was introduced. Moreover, it was
confirmed that the DC-link voltage control employed in
the power decoupling circuit achieved both the FRT
operation and the active power decoupling capability.
Moreover, the overshoot amount in the experimental result
was agreed with the theoretical value using theapproximate equation with an error within 10%. The
undershoot voltage caused the distortion in the input
current and the output current. This problem may stop thecircuit operation. In the future work, the calculation of theamount of DC-link voltage undershoot at grid voltage
recovery will be considered.
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