S2PC 2018, Jinju, Korea

Voltage Balance Control Method for Multi-port Grid-tied Inverterwith Square-wave-voltage Multilevel Converterand Active Power Filter Connected in Series
Mitsuru Miyashita1, Hayato Higa1, Jun-ichi Itoh1, Yuichi Noge2, Masaki Ishibashi31

Nagaoka University of Technology, 2 Tokyo University of Agriculture and Technology, 3 Tokyo Metropolitan College of Industrial Technology

This paper proposes a multi-port grid-tied inverter in order to reduce the power conversion loss. The proposed circuit consists of a multilevel
converter, a series active filter, and a full bridge inverter. In the proposed circuit, the number of inductors are reduced from four to two
compared to conventional circuit. In addition, a voltage balance controller is proposed in order to keep the capacitor voltage. The simulation
results confirm that the total harmonic distortion (THD) of the output current is less than 0.17%. Furthermore, capacitor voltage is balanced
under different the capacitance and initial voltage conditions.
Keywords Multi-port converter, Series active power filter, Constant capacitor voltage control

1. Introduction
With renewable energy, the generated electric power fluctuates
due to the weather conditions. In order to level the generated power,
energy storage systems such as a battery and a double-layer
capacitor are required [1]. In general, a power conversion system isemployed in a grid-tied inverter with a boost-up chopper and a DCAC converter to connect the PV modules and the battery to thesingle-phase grid system. However, the power conversion system
has the problems which are the increase in the power conversion
loss and the circuit volume due to the boost and grid tied inductors.
A multi-port converter has been actively researched in order toreduce the conversion loss and the circuit volume [2-4]. However,it cannot reduce the number of a inductor because of the grid-tied
inverter is required.
This paper proposes a multi-port grid-tied inverter which toreduce both the circuit volume and the power conversion loss. Onlyan active power filter and an output filter use the inductor. Therefore,
the circuit volume of the power converter is reduced. In addition, acapacitor voltage control is proposed in order to keep the voltage ineach cell. Moreover, the simulation results confirm that theoperation of the proposed circuit and capacitor voltage control
method.

2.

Proposed circuit and capacitor voltage control

2.1 Proposed circuit
Fig. 1 shows the configuration of the proposed circuit. The
proposed circuit consists of a square-wave-voltage multilevel
converter, an active power filter, and a full bridge inverter.
Furthermore, the square-wave-voltage multilevel converter consistsof the two cells (Cell A-B), and the active filter consists of the twocells (Cell C-D).
Fig. 2 shows the operation principle of the proposed circuit. Fig.
2(a) shows the input voltage of the full bridge inverter and theCorrespondence to: Jun-ichi Itoh. E-mail: itoh@vos.nagaokaut.ac.jp,Nagaoka University of Technology.
1603-1, Kamitomioka-machi, Nagaoka, Niigata, Japan, 940-2188
Japan.

Square-wave-voltage multilevel converter
Cell AS1
PV
Full bridge inverter
190 V
S2VA
Cell B
S3

S5

S4

S6

S1596 V

VB
Iout AC15 A

Series active power filter
Cell CS7
S9C1V
S8|Vgrid|

C3Vgrid

VC

S10S16

S132000 mF

C2S12AC200 V
3 kW

0.22 mF

Cell DS11L21 mH

2000 mF

C1VC2S17S18IL1L1S14300 mH

VD

100 kHz switching

Fig. 1. Circuit configuration of proposed circuit.
V
6E

Square-wave-voltage multilevel
converter Output voltage(Cell A,B)

2E

6Eth|Vgrid|

4E

Active power filter
charge area

Active power filter
discharge area

4Eth
2Eth0(a) |Vgrid| and Cell A, B output voltage.
Cell D output area

Cell C output Threshold
VCth0-VCth
Active power filter
output voltage(Cell C,D)

Cell C output area(b) Cell C and active filter output voltage.
Fig.2. Conceptual diagram of proposed circuit operation.

S2PC 2018, Jinju, Korea

output voltage of the Cell A and the Cell B, whereas Fig. 2(b) shows
the operation waveforms of the active power filter output voltage.
In Fig. 2 (a), the square-wave-voltage multi-level converter outputs
four level voltage which is synchronized with full-wave
rectification of the grid voltage. In Fig. 2(b), the series active power
filter operates to remove the harmonic components of the four level
voltage waveform which is output by the Cell A and the Cell B. In
consequence, the square-wave-voltage multilevel converter and theactive power filter output full-wave rectified waveform. Next, thefull bridge inverter converts the full-wave-rectification voltage
waveform into the sinusoidal voltage waveform, i.e. the switchingfrequency of twice grid frequency. Therefore, the converter loss isreduced by the proposed circuit due to low switching loss. In
addition, the inductor volume is also reduced because the inductor
voltage becomes the difference between the grid voltage andmultilevel square wave voltage.
Fig. 3 shows the block diagram of an inductor current control ofCell D. A waveform of the Cell A-D output current is required fullwave rectified waveform. Therefore, in the inductor current control
is provided command that the full-wave rectified waveform. Thus,
voltage and current that full-wave rectified waveform, output by theall cell.
2.2 Capacitor Voltage Control Method
In the proposed circuit, the capacitor voltage balance control andaverage control are implemented in order to stabilize the capacitor
voltage.
Fig. 4 shows the control block diagrams for the proposed circuit.
In Fig. 4(a) shows the capacitor voltage average control of the Cell
C and the Cell D, whereas Fig. 4(b) shows the capacitor voltage
balance control of the Cell C and the Cell D. In the capacitor voltage
average control, the total capacitor voltage of VC1 and VC2 isstabilized. The threshold value 2Eth, 4Eth, and 6Eth is controlled inorder to match the red area and the blue area in Fig. 2(a). In thecapacitor voltage balance control, the Cell C outputs the thresholdvalue VCth in order to match the red area of the positive and the red
area of the negative in Fig. 2(b). On the other hand, the capacitor inCell D, match the blue area of the positive and the blue area of thenegative in Fig. 2(b) is required. The capacitor voltage of Cell D isdetermined by the total voltage of the two cells and the capacitor
voltage of Cell C. The total voltage of the two cell are determinedby capacitor voltage average control, whereas the capacitor voltageof Cell C is determined by the capacitor voltage balance control.
Therefore, the Cell C and the Cell D of the capacitor voltages arebalanced by two voltage controls.

3. Simulation Results
The fundamental operation of the proposed circuit and capacitor
voltage control are verified by simulation. In the simulation, theideal voltage sources are applied as the power supplies in squarewave-voltage multilevel converter. In addition, the capacitor
voltage commands vc1* and vc2* are set to 32 V.
Fig. 5 shows the operation waveforms of the steady state and thetransient state. In Fig 5, the Cell A-D output voltage is confirmedthat the full-wave rectified waveform. Moreover, the total harmonic
distortion (THD) of the output current is 0.17%. In addition, thecapacitor voltage VC1 and VC2 includes the ripple voltages. Theripple voltage VC1 and VC2 have 12.6 V and 5.88 V. The ripple
voltage which fluctuates at twice grid frequency is caused by thecapacitor voltage control. At the transient state, the output current+|Isin(ωt)| iL1++|vgrid|-vA-vB-vC

iL1*PIS11S12PWM
÷

S13S14Fig. 3. Block diagram of the Cell D with inductor current control.
vC2-1PWM

iC*
Eth*+ 2Eth++PI÷ × -1+1E
Iout_maxvC1+vC2+ 4Eth+Logic(vC1+vC2)+3E+ 6Eth++5E |vgrid|(a) Capacitor voltage average control of Cell C and Cell D.
iC1*+ VCth+PI
vC1
÷ × +×+Logic
Iout
1 vC2/2
vC2+ -VCth-1Charge / Discharge|vgrid|-2E-4E
Signal(1 or -1)

S1S2

VC1*+VC2*S3S4S5S6S7S8S9S10(b) Capacitor voltage balance control of Cell C and Cell D.
Fig. 4. Control block diagrams of the proposed circuit.
Grid voltage [V]200

5 ms/div

0-200
Grid output current [A]
200-20
Output volgate [V]300

All cell output
voltage

200

Active power filter
output voltage

100

Cell A+Cell B
output voltage

0C1 and C2 Capacitor voltage [V]
C1 (Cell C)voltage (averaging at fSW)
C2 (Cell D)voltage (averaging at fSW)

40

VC2:5.88 V

20
32.0 V
00.0

VC1:12.6 V
0.2

0.4

0.6
0.8
Time [s]Fig. 5. Waveforms of the simulation results.

1.0is also sinusoidal waveform. Thus, the validity of the capacitorvoltage control is confirmed by simulation.
In the future work, the verification of the proposed circuit will be
conducted by an actual prototype circuit

References[1]N. Kawakami, et al: lCRERA, pp. 1 - 5, (2012)[2]A. Bhattacharjee et al: “Review of Multi Port Converters for Solar and Energy
Storage Integration”, IEEE Trans. PELS, Early Access, (2018)[3]B. G. Dobbs, et al: IEEE Trans. PELS, Vol.1, No.1, pp. 6-9, (2003)[4]H. Zhu, et al: IEEE Trans. IE, vol.62, no. 8, pp. 4937-4947, (2015)