Multi-port Converter with Square-wave-voltage
Multilevel Converter and Active Power Filter
Connected in Series
Jun-ichi Itoh
Dept. of Electrical, Electronics, andInformation Engineering
Nagaoka University of Technology
Nagaoka, Japan
itoh@vos.nagaokaut.ac.jp

Mitsuru Miyashita
Dept. of Electrical, Electronics, andInformation Engineering
Nagaoka University of Technology
Nagaoka, Japanmiyashita@stn.nagaokaut.ac.jp

Keisuke Kusaka
Dept. of Electrical, Electronics, andInformation Engineering
Nagaoka University of Technology
Nagaoka, Japan
kusaka@vos.nagaokaut.ac.jp

Yuichi Noge
Dept. Electrical and Electronic Engineering
Tokyo University of Agriculture and Technology
Tokyo, Japan
noge@go.tuat.ac.jp

Masaki Ishibashi
dept. Electrical and Electronics Engineering
Tokyo Metropolitan College of Industrial Technology
Tokyo, Japan
masaki_i@metro-cit.ac.jp

Abstract—This paper proposes a multi-port converter,
which has multiple power sources with a buck converter orinverter connected in series, with an active power filter for a
reduction of power conversion loss and circuit volume of anenergy storage system. The proposed circuit consists of amultilevel converter, a series-active power filter, and an
unfolder. In the proposed circuit, the number of inductors is
reduced from four to two compared to the conventional circuit.
Moreover, the proposed circuit reduces harmonic componentsof output voltage with a multilevel topology in order to reducethe volume of a filter inductor. In addition, a voltage control
system is proposed for the converter to regulate the capacitor
voltage of the active power filter. It is demonstrated that a 1-kW
prototype circuit with Si-MOSFETs achieves a maximum
efficiency of 99.3%. Furthermore, the capacitor voltage isregulated to constant even when the load power is stepped fromno-load to full load.

converter is still needed. Meanwhile, in Ref. [5], the converter
consists of two DC input ports and an AC output port.
However, the DC-link voltage must be higher than the
maximum voltage of the output AC voltage, leading to therequirement of the high voltage rating devices. Consequently,
the high switching frequency to reduce the circuit volume islimited due to the decrease in efficiency.

Keywords— Multi-port converter, Multilevel DC-AC converter,
Series-active power filter, Constant capacitor voltage control

I. INTRODUCTION
In recent years, fuel cell (FC) systems are widely studied
due to its high energy efficiency. However, the response of theoutput power of FC is typically slow against load fluctuation.
In order to overcome the load fluctuation, auxiliary energy
storage systems using batteries or double-layer capacitors are
typically required [1]. In general, a power conversion system
is employed in a grid-tied inverter with boost-up converters
and a DC-AC converter to connect FC and the battery to thesingle-phase grid system [2]. However, this power conversion
system faces several problems which are the increase in the
power conversion loss and the circuit volume due to the boost
and filter inductors. In particular, a reduction of the boost andfilter inductors is required.
Multi-port converters have been proposed to reduce theconversion loss and the circuit volume [3–5]. In Ref. [4], two
DC input ports are connected in series in order to achieve a
DC-DC conversion with one inductor. However, the multiportconverters still require a DC-AC converter with the AC gridconnection. Thus, the interconnecting inductor in the DC-AC

Besides, multilevel DC-AC converters have been
proposed to reduce the harmonic components [6–12]. For
instance of the multilevel topologies, such as a neutral point
clamped converter [9] and flying-capacitor converter [10] arestudied. However, the multilevel topologies increaseswitching loss because each device is operated with PWM. In[11–12], the multilevel voltage waveform is obtained by thecascade connection of the full-bridge cells. In the cascadeconnected full-bridge cell topology, the full-bridge cells haveto have an isolated power supply at DC side. Thus, circuit
volume is increased by isolate power supplies, e.g., isolationtransformer with the converter. However, the number of
output voltage levels is limited due to the number of full-bridecells. Consequently, cascade-connected full-bridge cell
topology has a relationship between circuit volume andnumber of output voltage levels. Moreover, the topology
increases switching loss since each cell is operated with PWM.
This paper proposes a multi-port DC-AC converter which
reduces both the circuit volume and the power conversion loss.
The original idea of this paper is that each converter of the
input port is connected in series. In addition, the active filter
is connected in series with FC and the battery converters withsquare-wave-operation in order to form a multilevel topology.
So, the circuit volume of the power converter is reduced.
Moreover, the harmonic components of the output voltage isreduced by the multilevel topology. In the proposed circuit,capacitors are used at a DC-link of the active power filter inorder to increase the number of voltage level without isolation
power supplies. In addition, the power density of the proposed
circuit is compared with the conventional topology through aPareto front optimization. Finally, the operation of the
proposed circuit is demonstrated in the experiment. The
prototype circuit achieves a maximum efficiency of 99.3% at

90% of rated power. Besides, the operation of the proposed
circuit is verified under the fluctuation of the capacitor initial
voltage and the DC-link voltage.
II. CIRCUIT TOPOLOGY AND CAPACITOR VOLTAGE CONTROLMETHOD
A. Circuit Configuration and Operation Principle
Figure 1 shows the conventional circuit, which consists ofa DC-AC converter and two boost-up converters, one ofwhich is connected to FC, whereas the other is connected to
auxiliary energy storage systems. Consequently, theconventional circuit requires at least three main inductors L1,
L2, and L3. These inductors can be minimized by the designof high switching frequency. Nevertheless, the increase in theswitching frequency of the high voltage rating switches in theconventional circuit leads to a decrease in efficiency.
Figure 2 shows the proposed circuit. The proposed circuit
consists of a square-wave-voltage multilevel converter, an
active power filter, and an unfolder. Furthermore, the squarewave-voltage multilevel converter consists of the two cells(cell A and B), and the active filter consists of the two cells(cell C and D).
Figure 3 shows the operating principle of the proposed
circuit. Fig. 3 (a) shows the input voltage of the unfolder andthe output voltage of the cell A and cell B, whereas Fig. 3 (b)shows the operation waveforms of the active power filter
output voltage. In Fig. 3 (a), the square-wave-voltage multilevel converter outputs four level voltages, which aresynchronized with full-wave rectification of the grid voltage.
In Fig. 3 (b), the series active filter compensates the harmoniccomponents of the four-level voltages, which are output by thecell A and the cell B. Consequently, the square-wave-voltage
multilevel converter and the active filter output full-wave
rectified waveform. Next, the unfolder converts the full-waverectification voltage waveform into the sinusoidal voltage
waveform, i.e., the switching frequency of twice the gridfrequency. Therefore, the converter loss is significantly
reduced by the proposed circuit due to the low switchingfrequency of the unfolder and the employment of the low
voltage rating devices. In addition, the inductor volume is also
reduced because the voltage applied to the inductor is only thedifference between the grid voltage and multilevel squarewave voltage.
B. Voltage Conditions of Fuel Cell and Battery
Figure 4 (a) shows the circuit configuration of the DC-AC
converter by cell connection topology and single-phase
inverter. Note that the general single-phase PWM inverter
without active power filter shown in Fig. 4 (a) is assumed inthis consideration. The cell A and the cell B are required tosupply the maximum instantaneous power when the system
has no active power filter. So, the voltage condition of the cell
A and the cell B DC link voltage are expressed as
Vout _ peak  E A  E B(1),

where Vout_peak is the maximum voltage of the output voltage,
EA is cell A DC-link voltage, EB is cell B DC-link voltage.
According to (1), the total voltage of cell A and B should behigher than the maximum voltage of the grid voltage.
Figure 4 (b) shows the circuit configuration of the DC-AC
converter by cell connection topology and single-phase

Chopper A
L1

Grid-tied inverter

S1

C3

S5

S7

L3

S6

S8

C4

C1

EA

S2

L4 Iout

Chopper B
S3
L2
C2

EB

S4

Fig. 1. Conventional circuit.
Square-wave-voltage multilevel converter
Cell A
S1
Fuel cell C1
EA

S2

Cell B
Battery
EB

C2 S3

S5

S4

S6

VA
S15

Iout
L2
|Vgrid|

C3

ED

C4
S12

C5

Vgrid

VC

S8

S10

S13

IL1

Rsnb

Cell D
S11

S17

D1

VB

Series active power filter
Cell CS7
S9EC

Unfolder

S16

S18

Csnb
L1

S14

VD

Fig. 2. Proposed circuit.
V
VA+VB

Square-wave-voltage multilevel
converter Output voltage(cell A,B)

VB

(VA+VB)th|Vgrid|VA
Active power filter
charge area

Active power filter
discharge area

VAth
VBth

0

(a) |Vgrid| and Cell A, B output voltage

V

Cell D output area

Cell C output threshold
VCth

0
-VCth
Active power filter output
voltage(cell C,D)

cell C output area(b) Cell C and active filter output voltage
Fig. 3. Conceptual diagram of the proposed circuit operation.

inverter with the active power filter. The voltage condition of
the cell A, cell B, and active power filter are expressed as(2),

where EC is the DC-link voltage of the active power filter.
Note that (2) is instaneous condition. Thus, inverter withactive power filter is not output Vout_peak in continuity. The
input power must be equal to the output power of the active
power filter in order to keep the capacitor voltages. In addition,
the DC-link voltage of the cell A should be twice the cell B
voltage. The output voltage is three levels when the voltage ofthe cell A is equal to that of the cell B. On the other hand, thevoltage of the active power filter is high when the voltage ofthe cell A is higher than twice the voltage of the cell B. In theactive filter, the capacitor voltage of the active filter should behigh enough in order to compensate for harmonic components
by the cell A and cell B. So, the voltage condition of the cell
C and cell D capacitor voltage is shown as( EA  EB )  EC

(3),

where EC is the capacitor voltage of the active power filter.
Furthermore, the constant capacitor voltage control isrequired to achieve stable operation, which is carried out by
the capacitor voltage balance control and the average control.
C. Control System of the Proposed Circuit
Figure 5 shows the block diagram of the inductor current
control of the cell D. There are two main control objectives in
the proposed circuit: the sinusoidal grid current and theconstant capacitor voltages. The current output of the cell A–
D should be full-wave rectified waveform. Then, the unfolder
converts the full-wave rectified current output by the cell A–
D. The capacitor voltage regulation is explained as follows.
Figure 6 shows the capacitor voltage control of the
proposed circuit. Fig. 6(a) shows the total voltage control of
the cell C and cell D, whereas Fig. 6(b) shows that thecapacitor voltage balance control of the cell C and cell D. In
the total voltage control, the total capacitor voltage of EC and
ED is regulated. In particular, the outputs of the total voltage
control system, i.e., the VBth, VAth, and V(A+B)th, are controlled
to match the area colored by red and the area colored by bluein Fig. 3(a). In the capacitor voltage balance control, the cell
C outputs VCth to match the red area in Fig. 3(b). On the other
hand, the cell D outputs VDth to match the blue area in Fig. 3(b).
The total voltage control system regulates the sum of thecapacitor voltages in the cell C and cell D, whereas the balance
voltage control ensures the same capacitor voltage in the cell
C and cell D. As a result, the capacitor voltages in the cell C
and cell D becomes constant.
III. POWER DENSITY COMPARISON BETWEEN CONVENTIONAL
AND PROPOSED CIRCUIT
A. Losses of power devieces and inductor
This chapter discusses the efficiency and the power
density. The proposed topology shown in Fig. 2 is comparedto the conventional topology shown in Fig. 1.
Table I shows the parameters of the loss and circuit
volume analysis. In this consideration, the power losses by thepower semiconductors and the copper loss of the inductor are
calculated. It assumes that the iron loss of the inductor can beneglected because the inductor is designed to let its current
ripple low. The conduction loss of the power semiconductor

EA

Cell A

VA

EB

Cell B

VB(a)Without active power filter

EA

Cell AEB

Cell B

VB

EC

APF

VC

(b)

VA

With active power filter

Fig. 4. Circuit configuration of the two power supply inverter.

iL1|Isin(ωt)|+-|Vsin(ωt)|+÷
PI
vA+vB+vC eD

+
-

*

iL1

S11
S12

-1

+
-

S13
S14

CarrierFig. 5. Block diagram of the output current control.

EC*+ED*

+
PI
eC+eD

iC*
÷

Vth*
×

-1

Iout_max(eC+eD)

+
+
EB

+
-

+
+

+
-

EA

VBth
S1
S2
VAth
Logic
S3
S4
S5
S6

(VA+VB)th+++EA+EB |vgrid|

(a)

eC

+
eD

Total voltage control of capacitor voltages

PI

iC3*
÷
1
-1

Iout

×

+
+

+
-

×

Charge / Discharge
Signal

VCth

S7
Logic

1 eC/2

MUX

Vout _ peak  E A  E B  EC

-1

+
-

-VCth

S8
S9
S10

|vgrid|-vA-vB(b) Balance control of capacitor voltages
Fig. 6. Capacitor voltage control system.

is calculated by the on-resistance of the devices and the RMS
value of the device current. So, conduction loss of device Pcon
is shown as
Pcon  Ron I rms 2(4),

Rated power
Output voltage
Output current
Output frequency

1 kW
200 V
5A
50 Hz

Fuel cell voltage
190 V
Fuel cell output power
730 kW
Battery voltage
95 V
Battery output power
270 W
600 V MOSFET, RDS=15 mW
Cell A
IPW65R019C7(Infineon)

Proposed circuit
SwitchingdeviceCell B

200 V MOSFET, RDS=9.9 mW
IPP110N20N3(Infineon)

Cell C
Cell D

60 V MOSFET, RDS=2.1 mW
IPI120N06S4-H1(Infineon)

Unfolder600 V MOSFET, RDS=15 mW
IPW65R019C7(Infineon)

Switching loss
IPB200N15N3G(Infineon)

Turn ON

0.97 mJ (at 34 V, 20 A)

Turn OFF

5.63 mJ (at 34 V, 20 A)

Heatshink

Capacitor

Conventional
circuit8
6

Proposed circuit

4
2
0
0

10

20

30

40 50 60 70 80 90 100 110
Switching frequency[kHz]Fig. 7. Operation waveform with capacitor voltage control

Performance Index (CSPI) [13–14]. CSPI is a value showing
the thermal resistance per unit volume, which is expressed by

CSPI 3.0

Proposed circuit

Conventional circuit

10600 V MOSFET, RDS=15 mW
IPW65R019C7(Infineon)

Conventional circuit

Cell AKXG series (Nippon chemi-con)
350 V, 150 mF, 4 parallel

Cell BKXG series (Nippon chemi-con)
160 V,330 mF, 3 parallel

Cell C, Cell D

GXF series (Nippon chemi-con)
50 V, 300 mF

Chopper A

GXF series (Nippon chemi-con)
400 V, 68 mF ~ 12 mF

Chopper B

KXG series (Nippon chemi-con)
160 V, 68 mF ~ 51 mF

DC-link

Inductor

12

PARAMETERS OF THE LOSS AND CIRCUIT VOLUME.

Loss[W]

TABLE I.

Ripple current
Window utilization factor
Flux density
Current density

RWF series (Nippon chemi-con)
400 V, 1000 mF
10 %
0.3
0.3 T
3 A/mm2

where Ron is the on-resistance of the device, Irms is the RMS
value of the device current. In the proposed circuit, Irms is fullwave rectified waveform because the inductor current is
controlled by the inductor current controller of Fig. 5. In theconventional circuit, Irms is the average current of the inductor
and the sinusoidal waveform current of the DC-AC converter
outputs. The switching loss is measured by switching test of
the Si-MOSFET IPB200N15N3G (Infineon). Note thatswitching loss of each device is assumed that switching lossof each device is in proportion to an applied voltage anddevice current. The switching loss Pswitch is shown as
I

V
I
V
Pswitch   ave dc eon  ave dc eoff  f sw
I V
I moff Vmoff mon mon

(5),where eon is turn-on loss, eoff is turn-off loss, Iave is the average
current, Vdc is applied voltage of device, Vmon, Vmoff, Imon, andImoff are switching test voltage and current described in adatasheet, fsw is the switching frequency. In the proposed
circuit, the switching loss of the cell A, B, and C is neglected
because the switching is several times during one grid cycle.
The power loss of the inductor under the same core is
calculated from winding length. In addition, AC resistance byskin effect is calculated. The cupper loss of inductor is shownasPL  I rms 2 Rwdc  I ripple 2 Rwac

(6),

where Rwdc is DC resistance of winding, Rwac is AC resistanceconsidering a skin effect, Iripple is current ripple.
B. Circuit volume
The considered volume of the circuit comes from theheatsink, the inductor, and the capacitor. The volume of theheatsink is calculated based on the Cooling System

CSPI 

1
Rth ( s  a )Vol H(7),

where Rth(s-a) is the thermal resistance of the heatsink, and VolH
is the volume of the heatsink. The volume of the heatsink isdetermined by CSPI and the required thermal resistance of theheatsink from the junction temperature of the switching
devices. Besides, thermal resistance Rth(s-a) is shown as
Rth ( s  a ) 

T j  TaPcon  Pswitch

 Rth ( j  s )(8),where Rth(j-s) is the thermal resistance of the junction to theheatsink in K/W, Tj is the junction temperature of the device,
and Ta is the ambient temperature [13].
The volume of the inductor VolL is calculated by Area
Product [15]. Note that the required inductance is determinedby the inductor ripple current. The volume of the inductor isgiven by3

 2WL  4
VolL  K v  K u Bm J w (9),where Kv is the constant value which is determined by theshape of the core, Ku is the window utilization factor, Bm is theflux density, Jw is the current density, WL is maximum energyof the inductor. The volume of the inductor is determined by
the maximum energy of the inductor with Kv, Ku, Bm, and JW
are kept constant.
The capacitance is decided by the ripple current. The
capacitor is selected based on the standard of the capacitor
manufacturer. In particular, the volume of the capacitor is
calculated by the dimension provided in the datasheet.
Figure 7 shows the switching loss and device conduction
loss characteristics of the proposed circuit and theconventional circuit with varying the switching frequency
from10 kHz to 100 kHz. The device loss of the proposed
circuit is smaller than the conventional circuit at over 20 kHz
because of the low switching loss.
Figure 8 shows the loss distribution of the proposed circuitand conventional circuit at 10 kHz and 100 kHz switchingfrequency. In the proposed circuit, conduction loss of thedevice is dominant because the high number of the conduction
devices. However, switching loss of the proposed circuit islower than the conventional circuit because the cell D (PWM
cell) is low voltage. In addition, copper loss of inductor is*1 H : unit capacitance constant[17] based on an output average current
Iout_ave and a capacitor voltage(VC3* or VC4*).
*2 %L based on an output voltage Vout, an output current Iout, and an
output frequency fout.
*3 Proportional gain based on an output voltage Vout, an output current
Iout.

reduced in high frequency due to a reduced number of the turnof small inductance. From the above reasons, the power loss
reduced by up to 74.1% at the switching frequency of 100 kHz.
Figure 9 shows the Pareto front curves of the proposed
circuit and the conventional circuit. The Pareto front curveshows the trade-off between two parameters, which are theefficiency and the power density in this paper [16]. Note thatthe switching frequency is varied from 10 kHz to 1 MHz in
the conventional circuit, 10 kHz to 10 MHz in the proposed
circuit. As shown in Fig. 9, both the efficiency and the power
density of the proposed circuit are higher than theconventional circuit at the same switching frequency because
the low switching loss and the inductor current ripple
reduction due to the multi-level characteristic.
IV. EXPERIMENTAL RESULTS
Table II shows the condition of the experiments. The
fundamental operation of the proposed circuit and capacitor
voltage control ware verified by a 1.0-kW prototype with SiMOSFETs. In the experiment, the resistance load is connected
at the output. Note that each voltage condition of (I)–(III) is
applied to the cell A and cell B in the experiment.
Figure 10 shows the operation waveforms at the steadystate at the rated output power. The cell A and cell B output
square-wave-voltage waveform. The cell C and cell D output
difference between the sinusoidal waveform and square-15.2 W

Loss[W]

Switching freq. 100 kHz

Switching freq. 10 kHz

20
15

Inductor loss

10

Switching loss
Conduction loss

0

12.0 W
Loss reducedby 74.1%

4.19 W

5
Conventional
circuit

Proposedcircuit3.11 W
Conventional
circuit

ProposedcircuitFig. 8. Loss distribution of the proposed circuit and conventional circuit.

10 kHz100
Efficiency[%]

TABLE II.
EXPERIMENTAL CONDITIONS.
Parameter
SymbolValue
Output power
1 kW
Pout
Grid voltage
Vgrid
200 V
Grid output current
Iout
5A
Grid frequency
fgrid
50 Hz
Cell A voltage
EA
190 V
Condition(I)
Cell B voltage
EB
95 V
Cell A voltage
EA
172 V
Condition(II)
Cell B voltage
EB
84 V
Cell A voltage
EA
185 V
Condition(III)
Cell B voltage
EB
68 V
C3 capacitor voltage
EC*
32 V
C4 capacitor voltage
ED*
32 V
Cell C capacitor
C33300 mF (H=1.69 ms)*1
Cell D capacitor
C43300 mF (H=1.69 ms)*1
Step down inductor
L1
1.57 mH (%Z=1.2%)*2
Snubber capacitor
Csnb
4.4 mF
Snubber resistance
Rsnb
47 kW
PWM Carrier Frequency
fsw
20 kHzResponse
fPI1
2 kHz
Danping factor
zPI1
0.7
PI1
Propotional gain
27.6
KP1
Integral time
Ti1
111 ms
10 Hz
fPI2
Response
Danping factor
zPI2
0.7
PI2
Propotional gain
0.15
KP2
Integral time
22.2 ms
Ti2
Response
10 Hz
fPI3
Danping factor
zPI3
0.7
PI3
Propotional gain
0.29
KP3
Integral time
22.2 ms
Ti3

900 kHz
Proposed circuit

98

300 kHz
10 MHz96

Conventional circuit

94
92

1 MHz

90
0

0.5

1

1.5 2 2.5 3 3.5 4Power density[kW/dm3 ]4.5

5

Fig. 9. Pareto front curve of the proposed circuit and conventional circuit.

CellA+cell B voltage [250 V/div]
0V
0V
Active power filter voltage [100 V/div]
Output voltage[250 V/div]
THD:1.08 %0V

0A
Output current[5 A/div][4 ms/div]

Fig. 10. Operation waveform with capacitor voltage control at rated power(1 kW), Voltage condition (I) EA=190 V, EB=95 V EC=ED=32 V.

wave-voltage waveform. It is demonstrated that the output
voltages of the cell A–D are the full-wave rectified waveform.
In this operation condition, the total harmonic distortion(THD) of the output voltage is 1.08%.
Figure 11 shows the capacitor voltage waveforms. Fig. 11(a) shows the steady state. In Fig. 11(a), the capacitor voltage
EC and ED are regulated by the capacitor voltage control. In
addition, the capacitor voltage contains the ripple voltages,
which fluctuates at twice grid frequency.
Figure 11(b) shows the capacitor voltage and the output
waveforms during the transient state from no-load to full load.
During the transient state, the output current and output
voltage are sinusoidal. Besides, the capacitor voltage isconverged in 220 ms. Thus, the validity of the capacitor
voltage control is demonstrated by the experiment.

Output voltage [250 V/div]

Output voltage [500 V/div]

0V

0V

0A

0A
Output current [10 A/div]
Cell C capacitor voltage [10 V/div]

Output current [5 A/div]
Cell C capacitor voltage [10 V/div]
Cell D capacitor voltage [10 V/div][4 ms/div]

0V

Cell D capacitor voltage [10 V/div][40 ms/div]0V(a) Capacitor voltage waveform at steady state.

(b) Transient response of the capacitor voltage.

Fig. 11. Capacitor voltage waveform at rated power (1 kW), Voltage condition (I) EA=190 V, EB=95 V EC=ED=32 V.
Output voltage [500 V/div]

Output voltage [500 V/div]
0V

0V

0A

0A
Output current [10A/div]
Cell C capacitor voltage [10 V/div]

Output current [10A/div]
Cell C capacitor voltage [10 V/div]

Cell D capacitor voltage [10 V/div]

Cell D capacitor voltage [10 V/div][40 ms/div]

0V[40 ms/div]

0V(a) VC3 initial voltage +10%, VC4 initial voltage -10%.

(b) VC3 initial voltage -10%, VC4 initial voltage +10%.

Fig. 12. Capacitor voltage waveform at each capacitor voltage condition at rated power (1 kW), Voltage condition (I) EA=190 V, EB=95 V EC=ED=32 V.
CellA+cell B voltage [250 V/div]

CellA+cell B voltage [250 V/div]

0V

0V

0V

0V
Active power filter voltage [100 V/div]
Output voltage[250 V/div]
THD:1.16 %h:99.2 %0V

0A

Active power filter voltage [100 V/div]
Output voltage
THD:1.25 %[250 V/div]
h:99.2 %0V

0A
Output current[5 A/div][4 ms/div](a) Voltage condition (II) EA=172 V, EB=84 V EC=ED=32 V.

Output current[5 A/div][4 ms/div](b) Voltage condition (III) EA=185 V, EB=68 V EC=ED=32 V.

Fig. 13. Operation waveform at each voltage condition at rated power (1 kW).

Figure 12 shows the capacitor voltage fluctuation and theoutput waveforms during the transient state. In Fig. 12(a), theinitial voltages of EC and ED are set to +10% and -10% to thenominal value, respectively. Similarly, in Fig. 12(b), the initial
voltage of EC and ED are set to -10% and +10%, respectively.
From Fig. 12, the capacitor voltages converge by the capacitor
voltage control from the biased initial voltage conditions.

Thus, the capacitor voltage controller is not affected by the
initial voltage of the capacitor by unbalanced initial charge.
Figure 13 shows the operation waveforms of each voltage
condition. In Fig. 13(a), DC-link voltage of the cell A is 172
V, DC-link voltage of the cell B is 95 V. In Fig. 13(b), DClink voltage of the cell A is 185 V, DC-link voltage of the cell
B is 64 V. From the experiments, it is ensured that the output

CellA+cell B voltage [250 V/div]

Output voltage [500 V/div]
0V

0V
0V
Output voltage [250 V/div]

Cell C+ cell D voltage [100 V/div]0A
Output current [5 A/div]
Cell C capacitor voltage [10 V/div]

THD:2.97 %0V

Cell D capacitor voltage [10 V/div]0A
Output current[2 A/div][4 ms/div](a) Operation waveform with capacitor voltage control[40 ms/div]

0V(b) Transient respons of the capacitor from non-load to 400 W

Fig. 14. Operation waveform at load of 400 W, Voltage condition (I) EA=190 V, EB=95 V EC=ED=32 V.
Output voltage [500 V/div]

Output voltage [500 V/div]

0V

0V

0A

0A
Output current [5 A/div]
Cell C capacitor voltage [10 V/div]

Output current [5 A/div]
Cell C capacitor voltage [10 V/div]

Cell D capacitor voltage [10 V/div]

0V[40 ms/div](a) Voltage condition (II) EA=172 V, EB=84 V EC=64 V.

Cell D capacitor voltage [10 V/div][40 ms/div]0V(b) Voltage condition (III) EA=185 V, EB=68 V EC=64 V

Fig. 15. Capacitor voltage waveform at each capacitor voltage condition at 400 W, Voltage condition (I) EA=190 V, EB=95 V EC=ED=32 V.

voltage and output current is the sinusoidal waveform at eachDC-link voltage condition. Consequently, the output
waveforms are not affected by DC-link voltage under thevoltage condition(I)-(III). However, the voltage condition is
not cleared that circuit operation to achieve. Thus,
clarification of the voltage conditions is future work.
Figure 14 shows the operation waveforms with a light
load: it is 0.4p.u. (400 W). Note that voltage condition is (I).
Fig. 14 (a) shows the operation waveforms at the steady state.
Fig. 14 (b) shows the capacitor voltage waveforms and output
waveforms at light load. In the light load, the output voltage
and current is the sinusoidal waveform. Moreover, the total
harmonic distortion (THD) of the output voltage is 2.97%.
Similarly, the capacitor voltage is stabilized by the capacitor
voltage controller at a transient state from Fig. 14(b).
Figure 15 shows the capacitor voltage change from theunbalanced initial voltage during the transient state at the lightload condition(400 W). In Fig. 15 (a), the initial voltage of EC
and ED are set to +10% and -10%, respectively. the initial
voltage of EC is +10% and the initial voltage of ED is -10%.
Similarly, in Fig. 15 (b), the initial voltage of EC and ED are
set to -10% and +10%, respectively. It is verified that thecapacitor voltage is stabilized even at light load condition.

Figure 16 shows the THD characteristic of the output
voltage when the output power is changed from 348 W to1000 W at voltage condition of (I). The minimum THD is
1.06% at a load of 900 W, whereas the efficiency at rated load
is 1.08%. The maximum THD is 4.6% at a load of 348 W. In
the light load, the output voltage THD is increased caused by
the ratio between the fundamental component and theharmonics component increases.
Figure 17 shows the efficiency characteristic with theoutput power from 348 W to 1000 W at voltage condition of(I). The maximum efficiency is 99.3% at a load of 900 W,
whereas the efficiency at rated load is 99.2%. The measured
efficiency is compared with the calculated value in section 3.
The error of the efficiency between measurement andcalculation is 0.4% that is caused by equivalent series
resistance (ESR) of the capacitor, snubber circuit, and coreloss of the inductor.
V. CONCLUSION
This paper proposed a multi-port DC-AC converter whichconnects the square-wave-voltage multilevel converter andthe active filter in series. The proposed circuit reduced boththe circuit volume and the power conversion loss. The loss ofthe proposed circuit reduced by up to 74.1% compared to theconventional circuit at the switching frequency of 100 kHz.

1p.u.=1.0 kW

THD of output voltage [%]5.0

REFERENCES

4.0
3.0

[1]

Minimum THD
1.06%

2.0
1.0
0.0

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

Output power[W]Efficiency[%]Fig. 16. THD characteristic at voltage condition (I).
99.4

1p.u.=1.0 kW

99.3

Maximum efficiency
99.3%

99.2
99.1
99.0
0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

Output power[p.u.]

Fig. 17. Efficiency characteristic at voltage condition (I).

The proposed circuit will achieve the power density of 4.0
kW/dm3 at 100 kHz. The power density of the proposed
circuit is calculated by Pareto front optimization at the natural
air cooling. Moreover, the validity of the proposed circuit andcapacitor voltage control is demonstrated by the experimentresults. In particular, it is verified that the THD of output
voltage is 1.06% at 900 W. Besides, it was also verified thatthe prototype circuit achieved the maximum efficiency of
99.3% at 900 W. In addition, operation of the proposed circuit
is ensured in each initial capacitor voltage, each DC-link
voltage, and each load conditions.

In the future work, the design on the capacitor of active
power filter will be clarified in order to improve the power
density. Moreover, the voltage conditions are cleared thatcircuit operation to achieve. Furthermore, the verification of
the loss analysis will be conducted.

H. Tao, A. Kotsopoulos, J. L. Duarte, and M. A. Hendrix: “A SoftSwitched Three Port Bidirectional Converter for Fuel Cell andSupercapacitor Applications”, Proc. of IEEE-PESC05, pp.2487-2493,
Recife, Brazil (2005-6)[2] P. Garcia, L.M. Fernandez, C.A. Garcia, and F. Jurado: “Energy
Management system of Fuel-Cell Battery Hybrid Tramway”, IEEE
Trans, Industrial Electronics, Vol.57, No.12, pp.133-139 (2010)[3] Amit Bhattacharjee, Nasser Kutkut, Issa Batarseh: “Review of MultiPort Converters for Solar and Energy Storage Integration”, IEEE
Transaction on Power Electronics, Vol.34, No.2, pp.1431-1445 (2019)[4] Xiaofeng Sun, Yue Zhou, Wei Wang, Baocheng Wang, Zhe Zhang:“Alternative Source-Port Tolerant Series-Connected Double-Input
DC-DC Converter”, IEEE Transaction on Power Electronics, Vol.30,
No.5, pp.2733-2742 (2015)[5] Hongfei Wu, Lei Zhu, Fan Yang, Tiantian Mu, Hongjuan Ge: “DualDC-Port Asymmetrical Multilevel Inverters With Reduced Conversion
Stages and Enhanced Conversion Efficiency”, IEEE Transaction on
Industrial Electronics, Vol.64, No.3, pp.2081-2091 (2017)[6] J. Rodríguez, J. Lai, and F. Z. Peng: “Multilevel Inverters: A Survey of
Topologies, Controls, and Applications“, IEEE Transactions on
Industrial Electronics, Vol.49, No.4, pp.724-738 (2002)[7] Tomoya Sugimoto, Takahiro Nozaki, and Toshiyuki Murakami:“Multilevel Inverter Topology Using Current Path Change for Zero
Current Switching”, IEEJ Journal of Industry Applications, Vol.8,
No.2, pp. 250-255 (2019)[8] Jakub Kucka, and Axel Mertens: “Common-Mode Voltage Injection
Techniques for Quasi-Two-Level PWM-Operated Modular Multilevel
Converters,” IEEJ Journal of Industry Applications, Vol.8, No.2, pp.
287-294 (2019)[9] A. Nabae, I. Takahashi, and H. Akagi: “A New Neutral-Point-Clamped
PWM Inverter”, IEEE Transactions of Industry Applications, Vol.17,
No.5, pp.518-523 (1981)[10] Sjef J. Settels, Jorge L. Duarte, and Jeroen van Duivenbode: “Flying
Capacitor Resonant Pole Inverter with Direct Inductor Current
Feedback”, IEEJ Journal of Industry Applications, Vol.8, No.3,
pp.444-451 (2019)[11] Hans Ertl, Johann W. Kolar, and Franz C. Zach: “Analysis of aMultilevel Multicell Switch-Mode Power Amplifier Employing
the ”Flying-Battery” Concept”, IEEE Transactions on Industrial
Electronics, Vol.49, No.4 (2002)[12] X. Lu, K. Sun, Y. Ma, L. Huang and S. Igarashi: "High performance
hybrid cascaded inverter for renewable energy system", in Proc. ofIEEE APEC, pp. 970-975 (2011)[13] Y. Kashihara, J. Itoh: "The performance of the multilevel converter
topologies for PV inverter", CIPS2012, pp. 67-72 (2012)[14] U. Drofenik, G. Laimer, Johann W. Kolar: “Theoretical Converter
Power Density Limits for Forced Convection Cooling”., Proceedingsof the International Power Conversion Intelligent Motion (PCIM)
Europe 2005 Conference, Nuremberg, Germany, June 7 - 9, pp. 608 619 (2005).
[15] Wm. T. Mclyman: “Transformer and inductor design handbook”,
Marcel Dekker Inc. (2004)[16] Johann W. Kolar, J Biela and J. Miniböck: “Exploring the Pareto Frontof Multi –Objective Single-Phase PFC Rectifier Design Optimization-99.2% Efficiency vs. 7kW/dm3 Power Density”, the 2009 IEEE
International Power Electronics and Motion, Wuhan, China (2009)[17] H. Fujita, S. Tominaga, and H. Akagi: “Analysis and design of a DC
voltage-controlled static VAr compensator using quad-series voltagesource inverters”, IEEE Transaction on Industry Applications, Vol.32,
No.4, pp.970-977 (1996)