A Single-phase Current Source PV Inverter with Power
Decoupling Capability using an Active Buffer
Yoshiya Ohnuma Koji Orikawa Jun-ichi Itoh
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japanohnuma@npe.co.jp, orikawa@vos.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
Abstract—This paper proposes a new circuit configuration anda control scheme for a single-phase current source inverterwith a power decoupling circuit which is called as the active
buffer. The proposed inverter achieves low-DC-input voltage
ripple and also provides sinusoidal current that can achieve
unity power factor, without large passive components in DC
bus such as smoothing inductors and electrolytic capacitors,
which are conventionally required in order to decouple thepower pulsation caused by single-phase power source. In thispaper, the fundamental operations of the proposed inverter are
demonstrated experimentally. From the experimental results,
the input voltage ripple is 8.87% and the output current THD
is 4.24%. In addition, the output power factor over of 99% anda maximum efficiency of 94.9% are obtained. Finally, it isconfirmed that the maximum power density of theconventional circuit and the proposed circuit are 2.75 kW/L at
the switching frequency 70 kHz and 4.86 kW/L at theswitching frequency 80 kHz, respectively.

I.

INTRODUCTION

In recent years, solar power generation systems arewidely used in response to the fast grows and high demandsof electrical energy. Due to the environmental advantages,
solar power generation systems are often applied in the
housing and industries areas. One of key components of thesolar power systems is the photovoltaic (PV) inverter [1]-[8].
The PV inverters are required to achieve the maximum
power point tracking (MPPT) function and to provide asinusoidal waveform that can achieve unity power factor into
the grid. In order to satisfy the requirements, many single
phase circuits with a power decoupling circuit has been
proposed, which can be classified as (i) passive power
decoupling circuits with passive components and (ii) active
decoupling circuits with semiconductor switches [10]-[13].
One of the most popular power decoupling circuits is twostage converters, which compose of a boost chopper with asemiconductor switch and a voltage source inverter as shownin Fig. 1, are generally used [1]. However, the converter
requires two large inductors (the boost inductor and theinterconnected inductor) which inherently increasing the sizeof the inverter. In addition, a large electrolytic capacitor isnecessary in order to compensate the power pulsation when
the inverters are connected to the single-phase grid because
the power is fluctuating at twice of the grid frequency. In ahigh temperature operating environment, the use of theelectrolytic capacitor is not preferred in terms of the lifetimeand the power density of the converter because the lifetimeof electrolytic capacitor decreases due to frequent charge/
discharge operations and the long hours of high temperature
operation.
In Ref. [11], a buck converter with a power decoupling
circuit has been proposed. An advantage of this converter isthat the number of semiconductor switch is only one in the
power decoupling circuit. However, a large inductor isrequired in order to achieve sinusoidal current that canachieve unity power factor. In Ref. [12]-[13], the power
decoupling circuits with soft-switching technique has been
proposed. At the resonance point, unity power factor can beachieved perfectly. However, the operation of the circuit
depends on the condition of a load. Moreover, the maximum
value of the circulation current increases. As a result,applications of the circuit are limited and the conduction loss
increases. On the other hand, matrix converters with a power
decoupling capability have been proposed [14]-[15]. In thoseconverters, high efficiency can be achieved because thenumber of switches where the current flows is reduced andthe smoothing capacitor is not required at a DC link part.
Nowadays, the current source inverter allows greatfeatures that the inverter can achieve both the MPPT
function and the grid-connected control by one converter.
However, a large smoothing inductor is required to decouple
the power pulsation caused by the single-phase power
generation. Therefore, conventional circuits with a power
decoupling capability have problems that the size and cost
increase depending on the number of passive components,
and also the power density is low.
This paper proposes a new single-stage current source
inverter with a power decoupling circuit, which is called as
the active buffer [16], to overcome those drawbacks. The
proposed inverter is constructed based on a current sourceinverter with an active buffer. The buffer circuit consists of
one switch, two diodes and one small capacitor. Therefore,
the size and the number of passive components in the
proposed circuit can be reduced compared with that ofconventional circuits. As a result, the proposed circuit canachieve high power density. The power pulsation with twice
the grid frequency is decoupled by the active buffer
capacitor. Therefore, the proposed inverter can control thevariable input-DC-voltage to achieve the MPPT and provides
a sinusoidal current into the grid without the large inductor.
The values of the active buffer capacitor can be reducedby controlling the capacitor voltage, allowing for the use ofsmall capacitors such as film capacitors or laminated ceramic
capacitors. Other passive components are required at the
input and output filters in the proposed inverter in order toeliminate the switching ripple. In addition, diodes that areconnected in series to the switches in the inverter are notrequired in the proposed inverter. Note that, the proposed
inverter is constrained at the operation with unity power
factor. The fundamental operations of the proposed inverter
are first demonstrated and explained. Then, the principle ofthe controls strategy is illustrated. Lastly, the validity of the
proposed controls is confirmed in experimental.
II.

CIRCUIT TOPOLOGY

A. Circuit Configuration
Fig. 1 shows one of the conventional PV inverter. The
conventional PV inverter, which consists of the boost
chopper and the voltage source inverter, is used widely. The
inverter requires the two huge inductors; the boost inductor
Ldc and the interconnected inductor Lac. Additionally, a hugeelectrolytic capacitor is also required in order to compensates
the power pulsation with a twice of the grid frequency when
the inverter is connected to the single-phase grid. Due to theabove reasons, downsizing for this converter becomesdifficult and challenge.
Fig. 2 presents the circuit structure of the proposed
converter. The proposed converter is constructed based on
the current source inverter with an active buffer circuit. The
proposed converter achieves the DC-voltage control for the
MPPT, operation on the inverter for an interconnection andpower pulsation with a small capacity. These functions are
realized by the combined controls between the current source
inverter and the active buffer circuit. The low-voltage ripples
are obtained except a switching ripple even when a small
smoothing inductor Ldc is used. Moreover, the diodes that are
required in the current source inverter are not necessary toachieve unity power factor. This is because the free-wheelingmode is operated in the active buffer. Additionally, recoveryof the diodes does not occur because there is no path to flow
the current on the body-diodes of the MOSFETs.
B. Operation modes
Fig. 3 illustrates the switching pattern of the proposed
inverter when the grid voltage is the positive. The current
pathway does not occur from the grid to the active buffer
capacitor because the active buffer capacitor voltage must be

Figure 1. Conventional voltage inverter with a boot chopper.

Figure 2. Proposed PV inverter.

higher than the grid voltage. Therefore, assuming that the
input is a continuous current source IIN, the current pathwaysof the proposed inverter have four modes based on theswitching pattern. In the mode 1, the input power (PVpower) is directly supplied to the single-phase grid. The
buffer power is controlled by the mode 2 and 3. In the mode
2, the current IIN flows into the capacitor in the active buffer
circuit. In contrast, in mode 3, the buffer capacitor isdischarged through the S0. The mode 4 is a current
freewheeling mode for the input current. Thus, the proposed
inverter performs both functions of a boost chopper (mode 1,
mode 4) and the buffering function for the power pulsationcompensation (mode 2, mode 3). The switches S3 and S4 arenot switched except the polarity of the grid is reversed. Thus,
the power control with PWM is held with combinations of S0
and S1, or S0 and S2. It means that the losses of the inverter
are dramatically reduced.
III.

CONTROL STRATEGY

Fig. 4 depicts the principle of power pulsationcompensation. When both the grid voltage vac and the output
current iac have sinusoidal unity power factor, theinstantaneous output power pout is expressed as follows;p out = V ACp I ACp sin 2 (ωt )=1
1
V ACp I ACp − V ACp I ACp cos(2ωt )
2
2

(1),

where VACp is the peak amplitude of grid voltage, IACp is thepeak amplitude of the output current, and ω is the grid
angular frequency.
Base on (1), the power pulsation with twice the grid
angular frequency appears in the output power. In order to(a) Mode 1.

(b) Mode 2.

(c) Mode 3.

(d) Mode 4.
Figure 3. Operation modes of the proposed inverter.

Figure 4. Compensation principle of power pulsation.

decouple the power pulsation, the buffer
instantaneous power pbuf is required, as given by1
pbuf = − V ACp I ACp cos(2ωt )2circuit(2),where the polarity of pbuf is defined as positive when thebuffer capacitor discharges. The mean power of the buffer

circuit is zero because the buffer capacitor absorbs only thepower pulsation.
Consequently, the instantaneous input power pin will be
constant:1
pin = V ACp I ACp = VIN I IN
2

(3).

The proposed inverter is controlled in four modes asshown in Fig. 3. Therefore, assuming that the input current
IIN is continuous, the inverter current iinv and the capacitor
current ic can be expressed as⎡iinv ⎤ ⎡ d mode1⎢ ⎥=⎢⎣ ic ⎦ ⎣ − d mode2

d mode3 ⎤⎥ ⋅ I INd mode3 ⎦(4),where dmode1 through dmode4 are the duty ratios of the eachmode. The duty ratios are constrained by the continuous
current (IIN), as follows:d mode1 + d mode2 + d mode3 + d mode4 = 1(5).

In order to obtain a sinusoidal output current, iinv isconstrained as (6). The capacitor current ic should becontrolled as (7), based on (2), in order to compensate thepower pulsation.
i inv = I ACp sin( ω t )ic = −V ACp I ACp
2v c

(6)

cos( 2ωt )(7)

Therefore, dmode1, dmode2 and dmode3 are controlled by thefollowing equations:d mode1 =I ACpsin(ωt ) − d mode3

I IN− d mode2 + d mode3 = d tempo = −V ACp I ACp
2vc I IN(8),

cos(2ωt ) (9),where dtempo is defined as “– dmode2 + dmode3”. When thecapacitor current ic is positive, i.e., when dtempo is positive,mode 3 is selected in order to discharge the capacitor. In
contrast, when the capacitor current ic is negative, i.e., when
dtempo is negative, mode 2 is selected.
The ratio of IACp over IIN can be ob tained as follows
based on (3), and substituting (10) into (8) and (9).
I ACp
I IN

=2

V IN
V ACp

(10)

Therefore, dmode1, dmode2 and dmode3 are obtained by (11)and (12) by using (8), (9) and (10).
*Vdmode1 = 2 IN sin(ωt) − dmode3
VAcp

(11)

⎧
, d tempo ≥ 0⎧d tempo⎪d mode2 = ⎨, d tempo ≤ 0⎪⎩0⎨⎧− d tempo , d tempo ≤ 0⎪⎪d mode3 = ⎨ 0, d tempo ≥ 0
⎩
⎩

(12)

where VIN* is the reference value of the input DC voltage.
Note that VIN* has to satisfy (13) because all duty commands
should be positive value and satisfy (5).
*V IN ≤

V Acp

(13)

2

From (13), the maximum of the input DC voltage is limitedby half of the of single phase maximum voltage.
Fig. 5 shows a control block diagram of the proposed
circuit. Based on (8), (9) and (10), the duty ratio commands
are calculated from the detected grid voltage vac, capacitor
voltage vc, input current iin, command of the input voltage
VIN*, minimum voltage of the active buffer capacitor VCmin,and capacitance of the active buffer capacitor Cc. Table I
presents the pulse transform table for the generation of gate
pulses. The gate pulses are given by comparing the pulse
transform tables with a triangle carrier. Note that thecapacitor voltage is controlled by a PI controller.
IV.

EXPERIMENTAL RESULTS

In order to demonstrate the validity of the proposed
inverter, a 400-W prototype circuit has been tested. In thispaper, the power supplies are connected at the input andoutput of the proposed circuit for the simplicity since thispaper aims to confirm a fundamental operation. Moreover,the input and output sides are controlled as the current source
mode and voltage source mode with assuming that the gridis 100 V, respectively. The input and output filters are
consisted of a 1-mH (%XL = 1.25%) inductor and a 3.3-μF
capacitor. A 50-μF film capacitor is used for the active
buffer capacitor. In the experiment, the grid voltage is 100
Vrms, the input voltage command is set to 70 V, and a carrier
frequency is 20 kHz.
Fig. 6 shows the experimental waveforms of the
proposed circuit. Fig. 6 (a) illustrates the input and output
waveforms when the prototype is operated with the rated
power. From the experimental results, the output power
factor is 99.9%, and the total harmonics distortion (THD) of
output current is 4.24%. Simultaneously, DC voltage iscontrolled according to the reference value of 70 V.
Moreover, the voltage ripple is 9.33%. Fig. 6 (b) shows thecapacitor voltage, where the capacitor voltage is fluctuatingwith twice of the grid frequency. Furthermore, the amplitudeof the voltage fluctuation matches to theoretical value. Hence,
it is confirmed that the proposed circuit achieves the power
pulsation compensation with active buffer.

2

VCmin −

p In

ωC c

{sin( 2θ ) − 1}

Figure 5. Control block diagram.

TABLE I. SWITCHING TABLE.

(a) Input and output waveform.

Fig. 7 presents the efficiency and power factor
characteristics subjects to the output power. The output
power factor is 99% at the rating power and the maximum
efficiency is 94.9%. Additionally, high efficiency and power
factor are confirmed achieving within a wide range of output
power.
Fig. 8 shows the harmonics analysis results of the
proposed circuit. The THD of the output current is less than
5% within the output power from 100 W to 400 W. From
this result, it is clear that the PV interconnection with theproposed circuit can be achieved. Besides, DC voltage ripple
is suppressed to less than 12% within the output power from
100 W to 400 W. This is attributed that the power pulsation
are compensated by the active buffer circuit.

(b) Capacitor voltage and output waveforms.
Figure 6. Experimental waveforms.

V.

COMPARISON TO CONVENTIONAL BOOST CHOPPER

In this section, a power density of the proposed circuit iscompared with the conventional boost chopper in order toclarify a superiority of the circuit. Table II provides thedesign specifications of the prototype. In this consideration, aPV with a rated voltage of 100 V and a grid of 200 V are
assumed.
A. Circuit Design and Calculation of Volume
1) Switching Devices: S and D
Table III presents the device information of the prototype.
The basis of selection for each component such as a switches
and diodes is in common. Thus, the same components areused in both the proposed circuit and conventional boost
chopper. In the selection of the MOSFETs, the switches S0,
S1, S3, which can achieve high speed switching, and theswitch S2, which has a low on resistance are selected.
Similarly, the fast recovery diodes D0 and D1 are selected.

Figure. 7. Efficiency and output AC power factor.

2) DC Link Capacitor: Cc
In the conventional circuit, the average capacitor voltage
Vc is boosted up to 350 V. Besides, the allowable voltage
ripple is set to 2.5% where the voltage ripple is defined as(14) with using a fluctuation range of the voltage ΔVc.
ripC =

ΔVC
2VC

(14)

On the other hand, the proposed converter has provenable to control the capacitor voltage significantly. The
minimum voltage and maximum voltage of the capacitor are
set to 282 V to 430 V respectively. The required lowest
capacitance is calculated from (15).

Cc =

POUT
2

4πf ACVC ripC

POUT
VC

TABLE II.

SPECIFICATIONS OF THE PROTOTYPE CONVERTER.

TABLE III.

DEVICE INFORMATION OF PROTOTYPE CONVERTER.

(15)

Besides, the current ripple Iripple_Cc, which flows into thecapacitor, is obtained by
I ripple _ Cc =Figure. 8. THD of output current and input voltage ripple.

(16)

Note that, considering the current ripple from the boost
chopper and inverter, twice the ripple current, which is
calculated by (16), is used as a selected value.
The electrolytic capacitor is chosen as a DC link
capacitor of the boost chopper because the 260 μF is neededin order to confirm the design specifications. In contrast, alaminated ceramic capacitor can be used because thecalculated value with (15) is 30 μF. Note that, the DC link
capacitor CC is not affected by the switching frequency.
Besides, the volume of the capacitor is derived from
capacitors in the marketplace.
3) Inductor: Ldc, Lac
Each inductor is designed based on the ripple ratio of
inductor current. The ripple ratio of the boost inductor andthe interconnected inductor are set as 10% and 5%,

respectively. Note that the ripple ratio is defined by (17)using the ripple current ΔIL and the average current of
inductors IL.
rip L =

ΔI L
2I L

(17)

In case of the boost inductor Ldc, the required inductanceis obtained by (18).
Ldc =VIN (VC − VIN )2 I L rip LVC f sw

(18)

where fsw is the switching frequency. Here, volumes of theinductors are evaluated using Area product concept [17].
4) Filter: Lf, Cac, Cdc
The standardized filter inductance Lf at the switchingfrequency of 10 kHz is set to 1% of the output power
capacity. The filter inductance Lf is determined so that the
ripple current is same according to the switching frequency.
Values of Cac and Cdc are selected so that the cut-off
frequency is one-tenth of the switching frequency.
5) Cooling fin
The volume of the cooling fin is estimated by CSPI
based on the power loss that is calculated from a simulation[18]. Here, natural air cooling is considered as the coolingmethod. In this paper, the CSPI value is 3, the volume of thecooling fin is calculated so that the chip temperature is below
then 125 deg. C when the ambient temperature is 45 deg. C.
VI.

Figure 9. Comparison of loss analysis.

COMPARIOSON OF POWER LOSS

This chapter shows the loss analysis using the circuit
simulator Piece-wise Linear Electrical Circuit Simulation(PLECS).
Fig. 9 shows the efficiencies of the conventional circuitand the proposed circuit when the switching frequency is 10
kHz and 100 kHz, respectively. When the switchingfrequency is 10 kHz, in the proposed circuit, the conduction
loss of the diodes is dominant in the total loss because thenumber of employed diodes is two. The total loss increases
due to the increasing of the switching loss when theswitching frequency is 100 kHz.

Figure. 10. Pareto-front curves.

VII. COMPARISON OF VOLUMES
Fig. 10 shows pareto-front curves, which shows therelationship between the power density and the efficiency
according to variation of the switching frequency. As a result,
it is confirmed that the maximum power density of theconventional circuit and the proposed circuit is 2.75 kW/L at
the switching frequency 70 kHz and 4.86 kW/L at theswitching frequency 80 kHz, respectively. In addition, theproposed converter can achieve higher efficiency at highswitching frequency comparing with that to the conventional
circuit.
Fig. 11 shows ratios of each volume at the maximum
power density. As a result, it can be seen that the volume ofthe proposed circuit is reduced by approximately 40%
compared with that to the conventional circuit. In theconventional circuit, a DC link capacitor and aninterconnected inductor are the cause of the large size.
Especially, the volume of the DC link capacitor cannot bedecreased according to the increasing of the switchingfrequency. On the other hand, the volume of the buffer
capacitor in the proposed circuit can be decreased according
to the increasing of the switching frequency.
VIII. CONCLUSION
This paper proposes a new circuit topology and a control
scheme for a single-phase current source inverter with a

Figure. 11. Comparison of converter volumes.

power decoupling circuit which is called as the active buffer.
The proposed inverter achieves low-DC-input voltage ripple
and also provides clear sinusoidal current into the singlephase grid, without large passive components in the DC bus,which are conventionally required in order to decouple thepower pulsation caused by single-phase power source. In thispaper, the fundamental operations of the proposed inverter
are demonstrated experimentally. From the experimental
results, the input voltage ripple is 8.87% and the output
current THD is 4.24%. In addition, the output power factor
over of 99% and the maximum efficiency of 94.9% areobtained. Finally, it is confirmed that the maximum power
density of the conventional circuit and the proposed circuit
could be 2.75 kW/L at the switching frequency 70 kHz and4.86 kW/L at the switching frequency 80 kHz, respectively.
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