電気学会論文誌●（●●●●●●●部門誌）
IEEJ Transactions on ●●●●●●●●●●●●●●●
Vol.●● No.● pp.●-●●
DOI: ●.●●/ieejeiss.●●.●

Paper

Input Current Harmonic Reduction based on Space Vector PWM
for Three-level Inverter Operating over a Wide Range Power Factor
Koroku Nishizawa＊, Student member, Jun-ichi Itoh＊a), Senior member
Akihiro Odaka＊＊, Member, Akio Toba＊＊, Senior member, Hidetoshi Umida＊＊, Fellow(Manuscript received Jan. 00, 20XX, revised May 00, 20XX)
This paper proposes a space vector pulse width modulation (SVPWM) that reduces current harmonics flowing through DC-link
capacitors of a three-level voltage source inverter in a three-phase motor drive system. The inverter input current harmonics areminimized by optimizing the applied voltage space vectors to reduce the fluctuation of the inverter input current around its averagevalue. Furthermore, the proposed strategy can be used for a wide range of load power factors by changing the combination ofvoltage space vectors according to output phase current conditions. It is experimentally shown that the proposed SVPWM reduces
the inverter input current harmonics by 27.4% at most, compared with that of the conventional SVPWM. Moreover, the analyticaland experimental results clarify that the proposed SVPWM reduces the inverter input current harmonics at any load power factor.
Keywords : Three-level voltage source inverter, Space vector PWM, Input current harmonics

1.

when the load power factor is around unity. Thus, it is not applicableto the 3LVSIs in motor drive systems, of which the variation of theload power factor is considerably wide.
In this paper, a novel space vector PWM (SVPWM) is proposed
to reduce the switching-frequency-order NPC-3LVSI input current
harmonics under any load power factor condition, i.e., both driving
and regenerative braking modes. The voltage vectors of 3LVSI are
optimally selected to minimize a fluctuation of the inverter input
current around its average value. Furthermore, the voltage vector
selection is based on the detected output phase current directions
for an adaptation to variations of the load power factor without aload power factor detection. The analytical calculations ensure thatthe employment of voltage vectors in this proposed SVPWM
reduce the inverter input current harmonics at any modulation
indices and load power factor. The original contribution of thisstrategy is the reduction of the 3LVSI input current harmonics overentire region of the load power factor, which is the crucial problem
with past works.
This paper is organized as follows; firstly, the configuration of
NPC-3LVSI are explained. Secondly, the analytical results on the
3LVSI input current are presented. Next, the reduction method of
the 3LVSI input current by changing the combinations of thevoltage space vectors are proposed. Finally, the modulator
performances on the input current harmonics, output current
harmonics, inverter efficiency, and common-mode voltage arecompared between the conventional and proposed SVPWM.

Introduction

Neutral-point-clamped (NPC) three-level voltage source
inverters (3LVSIs) (1) have been applied to medium-voltage highpower AC motor drive application such as traction drive system for
railway transportation due to their high-voltage high-power
capacity (2).
AC-electrified railway systems such as Shinkansen bullet trainsystem are generally composed of traction transformers, singlephase NPC rectifier, three-phase NPC-3LVSI, and induction
motors (3). In the DC-link part of this system, two filter capacitorswith the high-voltage capacity are implemented in series todecouple the unbalance between the instantaneous input and output
power. Heretofore, oil-filled capacitors have been generally used asfilter capacitors; however, these oil-filled capacitors require aperiodic maintenance due to theirs low resistance for moisture andheat shock. Consequently, the oil-filled capacitors have been
replaced by the film capacitors recently (4). Nevertheless, the film
capacitors may degrade or damage themselves with the self-heating
due to the capacitor ripple current (5). The inverter input current
contains numerous high-order switching-frequency harmonics
because the current is a superposition summation of the switchedcurrent pulses from each phase leg of 3LVSI (6)(7). Therefore, it isnecessary to reduce NPC-3LVSI input current harmonics.
So far, the modulation method to reduce the leakage current of
3LVSIs for PV systems by reducing the neutral-point voltage ripple
has been proposed (8). This modulation method also reduces thecapacitor current ripple; however, the capacitor current ripple is not
to be suppressed to the minimum. In addition, this modulation
method is effective in reducing the capacitor current ripple only

2. Three-level Inverter Input Current Harmonics
2.1 Configurations of Three-level Inverter
Fig. 1shows the configuration of NPC-3LVSI. The NPC inverter leads to
low switching losses since two series-connected devices splits thearm blocking voltage. However, it has high conduction losses
because there are two devices in the current path regardless of theoutput voltage level. Therefore, the NPC inverter becomes efficientin the medium-voltage and high-frequency applications (9).

a) Correspondence to: Jun-ichi Itoh.
E-mail: itoh@vos.nagaokaut.ac.jp＊
Nagaoka University of Technology.
1603-1, Kamitomioka-machi, Nagaoka, Niigata, Japan 940-2188＊＊
Fuji Electric Co., Ltd.
1, Fuji-machi, Hino, Tokyo, Japan 191-8502© 200● The Institute of Electrical Engineers of Japan.

1

SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)Table 1 lists the relationships between the switching functions
and the phase voltage of the NPC inverter. The switching function
is defined as:
1

sx j = 0

idc.in.P

P(S : ON ), ( x = u ~ w, j = 1 ~ 4 ) ................ (1)(S : OFF)

Cdcp

2

xj

xj

Edc

where x is the output phase and j is the number of device defined inFig. 1. There are three switching states in each leg of the 3LVSI,
and the three-level phase voltages are available.
2.2 Conventional Three-level Space Vector PWM
Fig. 2 shows the output voltage space vectors of 3LVSI in the reference frame. These voltage space vectors are illustrated on thebasis of the Clarke transform of 3LVSI three-phase output voltages.
The switching functions of each phase results in three different
values; therefore, there are 33 = 27 switching states in the 3LVSIs.
On the other hand, there are nineteen voltage space vectors(V0–V18) in total due to the switching state redundancy.
Fig. 3 shows the principle of the conventional three-level
SVPWM at sector I. Each sector of the conventional three-level
SVPWM is regarded as the space vector diagram of the two-level
SVPWM. Therefore, the classic two-level SVPWM is applicable ineach sector of the three-level SVPWM with an inner voltage
reference vector V*in. The inner vector is obtained by decomposing
the voltage reference vector V* by the equivalent zero vector of the
two-level SVPWM in each sector (e.g., V7 in the sector I) as:

Sw1

Su3

Sv3

Sw3

Motor
load
n

U
V

+ Edc

W

Su4

Sv4

Sw4

Su2

Sv2

Sw2

g

2

idc.in.N

N

Fig. 1.

Sv1

in

o

Cdcn

Su1
+ Edc

Configuration of NPC-3LVSI.

Table 1. Switching states of NPC inverter.
Switchingstate

vxo [V]

P (+)
0
N (–)

+ Edc/20– Edc/2

1
0
0

0
0
1

1
1
0

Sector
III
V3

V14

V2

[– + –][0 + –][+ + –]

V15

Vin* = V* − V6+i = V* − V6+i  ...................................... (2)Switching functions (x = u, v, w)
sx1
sx2
sx3
sx4



V9

V8

where γ is the phase angle of the inner voltage reference vector V*

SectorII

V13[+ + 0][0 0 –][0 + 0][– 0 –][– + 0][+ 0 –]

inand i is the number of sector where the voltage reference vector V*
exists. The sector I area is also divided into six sub-sectors 1–6 inthe same manner as the two-level SVPWM. Then, the three voltage
space vectors surrounding the sub sector where the inner vector
exists are selected. The inner voltage reference vector sampled ineach control period Ts is generated by synthesizing the three voltage
space vectors on the volt-second balance principle as (10):Sector V4
IV [– + +]

V0

V10

V16

Fig. 2.
frame.

where ta–tc are the duty cycles of each selected voltage space vector,
and a–c represent the number of selected voltage space vectors,
defined in Fig. 2.
2.3 Instantaneous RMS value of 3LVSI Input Current
Fig. 4 shows the waveforms of the voltage references and theoutput phase currents at unity load power factor. The output phasecurrents of 3LVSI are expressed as:

V6[0 – +][+ – +]

SectorVI

Output voltage space vectors of 3LVSI in  reference



V13

V8

2

 iu = I m cos ( 2 ft −  ) iv = I m cos ( 2 ft − 2 3 −  ) ........................................ (4)i = I cos ( 2 ft + 2 3 −  )mwI[+ – 0]

SectorV

Ts = ta + tb + tc

 Sector[+ – –]

V18[+ 0 +][0 – 0]V17[– – +]

V1[+ 0 0][0 – –]

V12[0 0 +][– – 0]V5ttt
Vin* = a Vx + b Vy + c Vz
Ts
TsTs............................................ (3)[0 0 0]

V11[– 0 +]

V*

V7[+ + +][– – –][0 + +][– 0 0]

0
1
1

V0

3
q
4


V7

Subsector 1
V* *
Vin
6


V1

SectorI

5

where Im is the maximum value of the output phase current, f is thefundamental frequency, and φ is the load power factor lagging angle,
respectively.
Fig. 5 shows the zoomed-in waveforms of the 3LVSI input
current when the conventional SVPWM is applied. The voltage
reference vector V* is sampled at sub-sector 1 in the sector I as
shown in Fig. 3. The instantaneous values of the P-side and N-side
input current of the both T-type and NPC 3LVSIs are thesuperposition summation of the switched current pulses from each

V12

V18
q : Phase angle of V* : Phase angle of inner vector Vin*

Fig. 3.

Conventional three-level SVPWM strategy at sector I.

phase leg and calculated as:

2

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)iDC .in.P =  ( sx1  ix ),x = u ,v , w

iDC .in. N =  ( sx 2  ix ) .

Sector.................................................. (5)x =u ,v , w

Although this paper focuses on NPC-3LVSI, note that therelationships between 3LVSIs input currents and those switchingstates are same for both T-type and NPC. Thus, the proposed
modulation strategy, explained from following section, is also
effective in reducing the capacitor current in the T-type 3LVSI.
In order to analyze the optimized combination of the voltage
space vectors for the minimum RMS value of the 3LVSI input
current, the RMS value of the 3LVSI input current in the N cycle ofthe carrier period, defined as the instantaneous RMS value (11), is
introduced.

iDC .in.RMS (Ts ) =1 ( N +1)Ts 2
2
iDC .in.P + iDC.in . N dt
2Ts NTs

(

(

)

vv*

vw*

iu

iv

iw

0

–30°

5°
30°

90°

150°

210°

270°

330°

2πft

Fig. 4. Waveforms of voltage references and output phase current
at unity load power factor. Sector I-VI are determined by the phaseangle.
iDC.in.P

iu.............. (6)iDC.in.avet0

iDC.in.N

iv
iw

where tk is the duty cycle of the selected voltage space vector,
iDC.in.P,k and iDC.in.N,k are the instantaneous values of the P-side andN-side input current when the selected voltage space vector Vk isapplied.
2.4 Average value of 3LVSI Input Current
The averagevalue of the 3LVSI input current over the fundamental period is
calculated as:

iDC .in.ave =

vu*
0

)

t
2
2
=  k iDC
.in. P ,k + iDC .in. N ,k .
k = a ,b ,c 2Ts

II

I

VI

V

IV

III

–iDC.in.ave
iv+iw= –iu

V7

V1

V7

V7
[+ 0 0][+ 0 –] [+ – –] [0 – –]

t7/4

t7/2

t13/2 t1/2

t1/2

t13/2

V13

V1

V13

[0 – –] [+ – –] [+ 0 –]

t7/4

Ts

Fig. 5. Zoomed-in waveforms of 3LVSI input current at m = 1.0,
2πft = 5°, and cos φ = 1.0 with conventional three-level SVPWM.
The voltage reference vector V* is located at sub-sector 1 in sector
I as shown in Fig. 3.

tk
1 2 
iDC .in. P ,k  dq
 2 0  k =a ,b,c Ts............................ (7)3= m  I m cos  .
4Note that the average value of the input current over thefundamental period is not dependent on the choice of the voltage
space vectors, but the modulation index, load current, and load
power factor.
2.5 Instantaneous RMS value of DC-link Capacitor
Current
The instantaneous RMS value of the current flowing
into the DC-link capacitors is derived by the difference between the
instantaneous RMS value of the 3LVSI input current (6) and theaverage value over the fundamental period (7) as follows:of the P-side input current iDC.in.P becomes zero, which leads to thelarge P-side input current iDC.in.P fluctuation around its averagevalue. Another equivalent zero vector V7 [+ 0 0] worsens the N-side
input current iDC.in.N fluctuation around its average value in the samemanner.

3. Reduction of 3LVSI Input Current Harmonics
3.1
Combinations of Voltage Space Vectors for
Minimum RMS value of 3LVSI Input Current
Fig. 6 shows
an example of optimized combination of the voltage space vectors
to minimize the RMS value of the 3LVSI input current at highmodulation indices, and when the phase currents iu is positive, andiv and iw are negative. The fluctuations of iDC.in.P and iDC.in.N around
its average value expressed as the shaded area in Fig. 6(b) become
smaller with the selection of the voltage space vectors V6, V18, V13
than those of the conventional three-level SVPWM shown in Fig.
5, resulting in the minimization of the RMS value of the 3LVSI
input current. Note that there are errors between the average valueof 3LVSI input current over the fundamental period (iDC.in.ave) andthe average values over the control period. This is because theaverage value of the 3LVSI input current over the control period
fluctuates at three-fold fundamental frequency due to the dc-bus
neutral point potential variation. In order to optimize the
combination of the voltage space vectors for the minimum RMS
value of the 3LVSI input current, first, the instantaneous values of
the 3LVSI input current with all possible voltage space vectors arecalculated off-line based on (5). Next, the three voltage space
vectors, which make the instantaneous values become close to theaverage value of the 3LVSI, are selected. Note that the triangle

2
2
iC .RMS (Ts ) = iDC.in. RMS (Ts ) − iDC .in.ave . .............................. (8)Since only the instantaneous RMS value of the 3LVSI input
current is dependent on the choice of the voltage space vectors, theinstantaneous RMS value of the DC-link capacitor current is also
dependent these choices. Thus, the lifetime of the DC-link
capacitors, which is affected by the instantaneous RMS value of theDC-link capacitor current (8), is extended by the selection of thevoltage space vectors that minimize the instantaneous RMS valueof 3LVSI input current (6).
Note that a small difference between the instantaneous values of
iDC.in.P and iDC.in.N, and these average values of the 3LVSI input
current iDC.in.ave results in a small instantaneous RMS value of
3LVSI input current (12). These fluctuations of iDC.in.P and iDC.in.N are
expressed as the shaded areas in Fig. 5. When the conventional
three-level SVPWM is applied, the equivalent zero vectors V7, of
which switching states are [+ 0 0] and [0 – –], are equally usedduring each control period in the sector I. In particular, when theequivalent zero vector V7 [0 – –] is applied, the instantaneous value
3

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)formed by the tips of these selected three voltage space vectors must
contain the tip of the voltage reference vector. These off-line
calculations and selections result in the voltage vectors for theminimum RMS value of the 3LVSI input current at unity load
power factor are V2, V13, V1, V18, and V6 in the high-modulationindex region shown as the green area in Fig. 6(a). On the other hand,the voltage vectors in the low-modulation index region shown as
the purple area in Fig. 6(a) at unity load power factor are V2, V8, V0,
V12, and V6(13). In other words, there are some optimized
combinations of the voltage space vectors for the minimum RMS
value of the 3LVSI input current. In the proposed three-level
SVPWM, the final combination of the applied voltage space vectors
is selected from these optimized combinations for the minimum
RMS value of the 3LVSI input current, considering the 3LVSI
output current quality.
3.2
Load Current Quality Consideration
In order toevaluate the 3LVSI output current quality, the concept of aharmonic flux (14) is used as an evaluation function of the load
current quality characterized by the modulation method because
this concept does not require the calculation of the output voltage
harmonic spectrum, which is difficult to obtain for the proposed
SVPWM due to its complicated selection of the voltage space
vectors. If the switching frequency model of the load motor isassumed as a pure inductance L, the harmonic load current vector
Ih is a proportional to the harmonic flux vector λh (time integral of
the instantaneous voltage error vector) in the Nth carrier cycle, as:
λ h = LI h = ( N +1)TsNTs

iDC.in.P

iu+iw
t

0

iDC.in.N

iv
iw–iDC.in.ave

V18

V13

V18

[+ – +] [+ – 0]

V6[+ 0 –][+ – 0] [+ – +]t6/2 t18/2

t13

V13

t18/2 t6/2(b) Instantaneous waveform of 3LVSI input current.

Fig. 6. One example of optimized combination of voltage space
vectors (V6–V18–V13) for minimum RMS value of 3LVSI input
current at m = 1.0, 2πft = 5°, cos φ = 1.0, and when iu is positive, iv
and iw are negative.

V2

V7
V12

o 7 13
V0
1

V

V7

1

V12

V18

1

λh

λh
V13

V8

13

V*

13 7

V1

V6

Ts

V2

1

V*

V18

[+ – 0]iDC.in.ave

V2
V8

V1

[+ – –]

iu

λh

V0

V*

(a) Combination of voltage space vectors (V6–V18–V13).

*

λh

V0

[+ 0 –]

V6 [+ – +]

k

V13

V13

V12

where Vk (k = 0–18) is the applied voltage space vector.
Fig. 7 shows the harmonic flux trajectories of all vector patterns
to achieve the minimum RMS value of the 3LVSI input current at

V8[+ + 0] V
8[0 0 –][+ 0 +][0 – 0]( V − V ) dt ...................................... (9)V2[+ + –]

V2

2 18
2 o

V*
V0

V7

13

V12

V18

V1

V13

V8

18
13
6
o
6

18

2

V*
V0

V7

18

V12

V18

o

V1
2

18

V18
1

V6
(a) Conventional 3-level SVPWM.

V2V6(b) V2–V13–V18.

(c) V6–V18–V13.

V2

1

V
V0

V

o

V0

V1

V7
V12

6

*

V13

V8

13

6

(e) V13–V1–V6.

V

o

V0

V1

V1

o

*

V
V0

V1

V7

V13

V8

V13

V8
o

*

V7

6

V12

V18

1

V6

V13

V8

6

V2

V2

V
V0

o

*

V1

V7

2

V12

V18

2

*

V7

13

(d) V18–V1–V2.

V2

1

λh

λh
V13

V8

V6

V6

V18

V12

V18

V12

V18

1

V6

V6
(f) V2–V1–V6.

(g) V2–V13–V6.

V6V6(h) V6–V18–V2.

(i) V13–V1–V18.

Fig. 7. Harmonic flux trajectories of all vector patterns to achieve minimum RMS value of 3LVSI input current at m = 1.0, and2πft = 5°. The trajectories are expressed as the red lines. The distance between the origin (o) and the trajectory is equal to the magnitude of
the harmonic flux, and continuously fluctuates. Figs. 7(b)–(i) are with the optimized combinations of the voltage space vectors for theminimum RMS value of the 3LVSI input current in the high-modulation indices region. With the combinations of the voltage space vectors
shown in (g)–(i), the voltage reference vector is not to be generated under these conditions of the modulation index and the phase angle.
4

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)the modulation index of 1.0, and the phase angle of 5°. Within the
carrier cycle the trajectories are drawn according to the selectedswitching sequence. In Fig. 7(a) as an example, two triangles areformed as the harmonic flux trajectory according to the selectedswitching sequence (V7–V1–V13–V7–V7–V13–V1–V7). Since thedistance between the origin and the trajectory is equal to themagnitude of the harmonic flux (14), Fig. 7 demonstrates that the
optimized vector combinations for the minimum RMS value of
3LVSI input current worsen the load current quality compared tothose with the conventional three-level SVPWM. The RMS valueof the harmonic flux over each control period is calculated as:

RMS (T ) =s( N +1)TsTs(f) V2–V1–V6

λRMS(Ts) [-](e) V13–V1–V6(d) V18–V1–V2(b) V2–V13–V18

2(c) V6–V18–V13(h) V6–V18–V2(a) Conventional(g) V2–V13–V6

3-level SVPWM

2πft [deg.]2

λ h dt . ........................................... (10)Fig. 8. Phase angle dependencies of RMS value of harmonic flux
over control period at m = 1.0.

Fig. 8 shows the phase angle dependencies of the RMS value ofthe harmonic flux over each control period (10) at the modulationindex of 1.0. Fig. 8 demonstrates that the optimized vector
combinations for the minimum RMS value of 3LVSI input current
worsen the values of λRMS(Ts) with regard to any phase angle
compared to the conventional 3-level SVPWM. However, it is also
demonstrated that the optimized combinations of voltage space
vectors V2–V13–V18, V6–V18–V13, V2–V13–V6, and V6–V18–V2
suppress the increase of the harmonic flux at the modulation index
of 1.0. For example, V2–V13–V6 combination leads to the smallest
increase of λRMS(Ts) in the phase range of 18°–30° as observed in Fig.
8. Note that λRMS(Ts) value has both the phase angle dependency andthe modulation index dependency. So, the proposed 3-level
SVPWM vector patterns are determined by selecting the
combination to achieve the smallest value of λRMS(Ts) from theoptimized vector combinations for the minimum RMS value of
3LVSI input current with respect to the phase angle and themodulation index. Note that the selection for the final combinationof the applied voltage space vectors is also performed off-line andany on-line calculations of (9) or (10) are not necessary.
Fig. 9 shows the proposed vector patterns to minimize the RMS
value of the 3LVSI input current when the phase currents iu ispositive, and iv and iw are negative with the consideration of the load
current quality.
Fig. 10 shows the flowchart for determining the detailed area i-x
in Fig. 9 and applied voltage space vectors. First, the duty cycles
corresponding to the applied voltage space vectors, listed in Fig. 9,
are calculated. Next, those calculated duty cycles are verified
whether those are realistic values or not. If there is only one realistic
case, it is identified as the area where the voltage reference vector
V* locates. If not, the phase angle (γ) of the inner voltage reference
vector determines the correct area. For example, duty cycles are
realistic values both in the parts of area ii and iii in Fig. 9. In thiscase, area ii and iii are identified whether γ exceeds 180° or not.
Note that this area identification process is just one example. In
practical use, the detailed area i-x is identified using look-up tables,
avoiding the heavy on-line computation load.
3.3
DC-bus Neutral Point Potential of 3LVSI
The
neutral current flowing out or into the neutral point of the DC-linkcauses the variation of the dc-bus neutral point potential. Its current
is related to the common-mode voltage of 3LVSI and calculated
from the switching functions and load currents as following.
in =  ( sx 3  sx 4  ix ). ................................................. (11)

V2
viii

V8
V0

i ii

V13

vi

iv

x

v

iii

Area
i
ii
iii
iv
v
vi
vii
viii
ix
x

V1

vii

V12

ix

V18

V6

Vectors
V8–V0–V12
V6–V12–V8
V2–V8–V12
V2–V8–V6V6–V12–V2
V2–V13–V6V6–V18–V2
V6–V18–V13
V2–V13–V18
V13–V1–V18

Fig. 9. Proposed vector patterns to minimize RMS value of
3LVSI input current when iu is positive and iv and iw are negativewith consideration of load current quality.
Start
Calculations for duty cycles (ta, tb, tc)
corresponding to the applied voltage
space vectors in each areas (i-x)
0 < tay, tby, tcy < Ts

(y = i ~ x)

Only one caseamong y = i and x satisfies
above conditions
YES

Area is identified as yNO

Correct area is identified from phaseangle (γ) of inner voltage reference
vector V*in

Selection for voltage space vectors
corresponding to area
FinishFig. 10. Flowchart for determining detailed area i-x and applied
voltage space vectors.
the dc components due to the error of the common-mode
voltage of 3LVSI or the capacitance mismatch connected
in series,and the fluctuation at triplen frequency of the fundamental
waveform due to the common-mode voltage fluctuation.
Both of them cause an excessive high voltage across theswitching devices, load current distortion, and motor torque ripple;
thus, the dc-bus neutral point potential control is necessary. Notex =u ,v, w

The variation of the dc-bus neutral point potential includes (15):5IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)that these problems occur both in the conventional and proposed
SVPWM unless the switching state (0) with the phase voltage ofzero is not used. Generally, the duty cycle of redundant vectors, ofwhich have redundant switching states such as V7 [+ 0 0] and[0 – –], is rearranged in order to reduce the variation of the dc-bus
neutral point potential (16). However, in the high-modulation index
region of the proposed SVPWM, no redundant vectors are selected;
thus, the dc-bus neutral point potential control is not achievable.
Note that the following two approaches have the potential toachieve the neutral potential control in the high-modulation index
region of the proposed SVPWM:
applying only large active vectors (e.g., V1 [+ – –],V2 [+ + –], V3 [– + –], V4 [– + +], V5 [– – +], V6 [+ – +]for proposed sector A), which do not depend on the dcbus neutral point potential, with the sacrificed load current
quality, orpartially (e.g., one-sixth phase angle period of all
proposed sectors) applying the conventional SVPWM,
which uses the redundant vectors during every switching
period, with the sacrificed reduction effect on the input
current harmonics.

4.

Table 2. Sector definitions of proposed SVPWM.

A
B
C
D
E
F

III
V3
V15

V14 
V9

C
V10

V
IV 4
V16

V2

i ii

V0

V12
E
V17



vi x

V1 

V7
F
V18
V6

V

Adaptation to Wide Load Power Factor Range

Conventional
SVPWM
ProposedSVPWM

IIB V8 iv viii V13
A

DV11
V5

I

I–VI: Conventional sector

VI

A–F: Proposed sector

Fig. 11. Layout of proposed sectors in  reference frame at load
power factor of 0.766 (40° lagging). The proposed sector A leadsby 40° from the conventional sector I.

The reduction of the RMS value of the 3LVSI input current
through the use of these optimized combinations of the voltage
space vectors is dependent on the load power factor because theinstantaneous values of the input current is dependent on not only
the switching patterns but also the output phase current. Therefore,
the adaption to the load power factor variation is important to
reduce the 3LVSI input current harmonics over wide load power
factor range, which is a typical requirement of the motor drive
system.
Table 2 lists the sector definitions of the proposed SVPWM.
These sectors A–F are determined by the combination of thedetected output phase current directions and used as the information
to recognize the load conditions.
Fig. 11 shows the layout of the proposed sectors in the reference frame at the load power factor of 0.766 (40° lagging). The
proposed vector patterns shown in Fig. 9 reduces the RMS value ofthe 3LVSI input current only when iu is positive and iv and iw arenegative, i.e., the sector A. These proposed sectors are rotated by
the phase shift angle φ according to the variation of the load power
factor. As a result, the proposed sectors A-F will lead by the load
power factor angle φ from the corresponding conventional sectors
I-VI. As shown by the mesh area in Fig. 11, a part of sector A is notavailable with the optimized combinations of the voltage space
vectors for the sector A because the mesh area is not covered by the
proposed vector patterns. In these mesh areas, new combinations of
the space vectors are ineffective in reducing the RMS value of
3LVSI input current; hence, the conventional SVPWM is applied.

5.

Current polarity(P: Positive, N: Negative)
iu
iv
iw
P
N
N
P
P
N
N
P
N
N
P
P
N
N
P
P
N
P

SectorI DC .in. RMS =
=



1

 
(i
  2
T
3

3
0

tk

k = a ,b ,c2
DC .in. P , k

s


2
+ iDC
.in. N , k  dq


)

2

tk 2
3 3
iDC .in. P ,k  dq , 
2 0  k =a ,b ,c Ts(. (12))The normalized DC-link capacitor RMS current is calculated
based on (7), (8), and (12) as:
I C . RMS (p.u.) =

2
2
tk
3 3
( iDC.in.P,k − iDC.in.ave )  dq . (13)
 

0
2
T
k
=
a
,
b
,
c
s



Fig. 12 shows the analytical results of the DC-link capacitor
RMS current with regard to the modulation index and the load
power factor angle. Fig. 12(a) demonstrates that IC.RMS(p.u.)_Conv
becomes the maximum at around m = 0.6 and absolute value of theload power factor |cos φ| = 1.0 with the conventional SVPWM. On
the other hand, Figs. 12(b) and (c) demonstrate that the proposed
SVPWM reduces IC.RMS(p.u.) under almost conditions of m and φ
except for φ = 90°. In addition, a higher |cos φ| leads to a greater
reduction effect on IC.RMS(p.u.). This trend is resulted from therelationship between φ and the application ratio of the optimized
combination of the voltage space vectors. When |cos φ| is lower than
0.866, the conventional SVPWM is partially applied in whole phaserange as observed in Fig. 11. The application ratio of the optimized
vector patterns decreases as |cos φ| becomes small, and there is noIC.RMS(p.u.) difference between the conventional and proposed
SVPWM when cos φ = 0.
5.2
RMS value of Harmonic Flux
Since the voltage
space vectors which are symmetric with regard to every 60° ofphase angle are applied in the modern PWM strategy for threephase system, the characteristics of λ2RMS(Ts) have the six-foldsymmetry. So, the RMS value of the harmonic flux overAnalytical Evaluations

5.1
RMS value of DC-link Capacitor Current
Since
the DC-side of the three-phase VSI operates at six-fold fundamental
frequency and the P-side and N-side operate symmetrically, theRMS value of 3LVSI input current is calculated from the P-side
input current by considering only a third of the fundamental periodas:

6

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Load power factor angle  [deg.](a) Conventional SVPWM.

Fig. 12.

IC.RMS (p.u.)_Prop / IC.RMS (p.u.)_Conv [-]Modulation index m [-]IC.RMS (p.u.)_Prop [p.u.]

Modulation index m [-]IC.RMS (p.u.)_Conv [p.u.]

Modulation index m [-]SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)Load power factor angle  [deg.]

Load power factor angle  [deg.](b) Proposed SVPWM.

(c) IC.RMS (p.u.)_Prop / IC.RMS (p.u.)_Conv ratio.

Analytical results of DC-link capacitor RMS current.

fundamental period is calculated as:

RMS =

3

0.350
0.350





3
0

2
RMS (Ts )dq . ............................................. (14)

0.250
0.250

λRMS
RMS [-]The load current quality with respect to the modulation index isevaluated without any load information by calculating the above
formula. In addition, relative comparison is possible by using λRMS.
Fig. 13 shows the RMS values of the harmonic flux overfundamental period in the linear modulation range. The distance
between the harmonic flux trajectories and the origin, which is theinitial value of λh at the beginning of the carrier cycle, corresponds
to the magnitude of the harmonic flux (14). Thus, Fig. 13 confirmsthat the proposed SVPWM worsens the harmonic flux comparedwith those obtained with the conventional SVPWM. This is because
the proposed vector patterns result in the application of the voltage
space vector which is not the closest to V*, i.e., V6 and V13 inFig. 6.

6.

Proposed SVPWM

0.300
0.300

0.200
0.200
0.150
0.150

Conventional SVPWM

0.100
0.100
0.050
0.050
0.000
0.000
0.0
0.0

0.2

0.4
0.4

0.8
0.8

1.0
1.0

1.2

Fig. 13. Comparison of harmonic flux RMS value. In the
proposed SVPWM calculations, the load power factor is set to 1.
vuv

Edc
0
–Edc

Simulation Results

iDC.in.P

Im

0
Im
0
– Im

vuv

Edc
0
–Edc

iDC.in.P

Im

Fig. 14 shows the PLECS simulation results with each
modulation method at the modulation index of 0.930 and the load
power factor of 0.866. The zoomed-in waveforms of the input
current demonstrate that the width of the step change in the input
current is reduced by the proposed SVPWM.

7.

0.6
0.6

Modulation
m [-]
[-]
Modulation index
index m

0

iu

Im
0
–Im

10 ms/div.

Imiu
10 ms/div.

Im

iDC.in.P
iDC.in.P

Experimental Results0

The performances of the conventional and proposed SVPWM areverified in experiment. In this experiment, 3LVSI, composed of
IGBT power modules (2MBI150U2A-060, Fuji Electric Co., Ltd.),
is operated at the switching frequency of 10 kHz. A test three-phaseinduction motor (MVK8115A-R, Fuji Electric Co., Ltd.), the rated
power of which is 3.7 kW, is controlled by V/f control with theconventional and proposed SVPWM, which are implemented into
an evaluation board (TMS320C6713, Texas Instruments).
7.1
Input Current Harmonics
Fig. 15 shows theoperating waveforms of 3LVSI with each modulation method at themodulation index of 0.930 and the load power factor of 0.866. The
width of the envelope in the input current is reduced by the
proposed SVPWM. On the other hand, the transitions between +Edc
and –Edc occur at worst in the line-to-line voltage with the proposed
SVPWM due to the proposed selection of the voltage space vectors,
whereas the voltage transition range with the conventional SVPWM
is Edc/2.
Fig. 16 shows the harmonic components of the input current
under the same conditions in Fig. 15. The 100% of the vertical axis

0

Ts

Ts

(a) Conventional SVPWM.

(b) Proposed SVPWM.

Fig. 14. Simulation results at m = 0.930 and cos φ = 0.866(30° lagging); output line-to-line voltage, P-side input current, andoutput phase current.
indicates the maximum value of the output phase current. The
proposed SVPWM reduces the switching frequency component by
16.6 points at most. Furthermore, the normalized input current
harmonics, estimated as follows, is reduced by 27.4%.

I DC .in (p.u.) =I DC .in.RMS
1
=
Im
Im

2

 1

iDC .in.l  ................ (15)2
l =1 
where IDC.in.RMS is the RMS value of the input current harmonics,
l is the harmonic order, and iDC.in.l is the l-order component of the
input current. The harmonic components of the input current up to
20th-order of the switching frequency are considered in thisevaluation.
7

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)Conventional sector
I

IV

III

II

V

VI

Proposed sector
A

B

C

D

E

F

vuv [200 V/div.]

vuv [200 V/div.]
0

0

0

0

iDC.in.P [20 A/div.]

iDC.in.P [20 A/div.]

iu [20 A/div.]

iu [20 A/div.]00[5 ms/div.][5 ms/div.](b) Proposed SVPWM.

(a) Conventional SVPWM.

Fig. 15. Experimental waveforms at m = 0.930 and cos φ = 0.866 (30° lagging); sector, output line-to-line voltage, P-side input current, andoutput phase current.
IDC.in(p.u.) = 0.402 [p.u.]100

24.2 %

Input current [%]Input current [%]

100
10
1
0.1
0.01
0.01

0.001
0.001
10

100
100

1000
10000
1000
10000
Frequency [Hz]

0.1
0.01
100

(a) Conventional SVPWM.

Fig. 16.

100000100000(b) Proposed SVPWM.

0.50

cos φ = 0.866(φ = 30 deg.)Lines : Ana. results
Plots : Exp. results

Lines : Ana. results
Plots : Exp. results

0.40

0.30

IDC.in(p.u.)
DC.in(p.u.) [p.u.]

0.40
IDC.in(p.u.)
DC.in(p.u.) [p.u.]

1000
1000
10000
Frequency [Hz]Harmonic components of input current at m = 0.930 and cos φ = 0.866 (30° lagging) (under same conditions as in Fig. 15).
0.50

cos φ = 0.259(φ = 75 deg.)

0.20

cos φ = 0.707(φ = 45 deg.)

0.10

cos φ = 0.866(φ = 30 deg.)

0.30
0.20

cos φ = 0.707(φ = 45 deg.)cos φ = 0.259(φ = 75 deg.)

0.10

0.00

0.00
0.0
0.0

0.2
0.2

0.4
0.6
0.8
0.4
0.6
Modulation
Modulationindex
indexm
m [-]
[-]

1.0

1.2

0.0

(a) Conventional SVPWM.

Fig. 17.

7.57 %

1

0.001
0.001
10

100000100000IDC.in(p.u.) = 0.292 [p.u.]

10

0.2

0.6
0.4
0.6
0.8
Modulation
Modulationindex
index m [-]

1.0
1.0

1.2

(b) Proposed SVPWM.

Analytical and experimental results of input current harmonics.

7.3
Inverter Efficiency
Fig. 19 shows the 3LVSI
efficiency, measured using Yokogawa WT 1800 power analyzer, atthe load power factor of 0.866. Fig. 19 demonstrates that the
proposed SVPWM improves the efficiency. The proposed SVPWM
may lead to the increased number of the voltage vector areachanging timing. However, the occurrence frequency of the voltage
vector area changing in the proposed SVPWM is much smaller than
the switching frequency. Figs. 5 and 6 demonstrate that the
proposed SVPWM leads to less number of switching transitions ineach switching period compare to the conventional SVPWM.
Therefore, the proposed SVPWM reduces the total number ofswitching transitions over the fundamental period compared to theconventional, leading to the small switching loss.
7.4
Common Mode Voltage
The common-mode
voltage of the three-phase inverter (vng in Fig. 1) is defined as thepotential of the star point of the motor load (n in Fig. 1) with respect

Fig. 17 shows the analytical and experimental results of the input
current harmonics at the load power factor from 0.259 to 0.866. The
proposed SVPWM reduces the input current harmonics under any
conditions of the modulation index and the load power factor.
Furthermore, these results confirm that the experimental results of
the input current harmonics match the analytical values well. A
higher load power factor enables a greater reduction effect on the
input current harmonics to be obtained.
7.2
Output Phase Current Harmonics
Fig. 18 shows
the total harmonic distortion (THD) of the output u-phase current at
the load power factor of 0.866. The harmonic components up to
40th-order of the fundamental frequency are considered in thisevaluation. The proposed SVPWM leads to the higher distortion of
the output phase current than those with the conventional SVPWM,
which is also observed from harmonic flux analysis in Fig. 13.

8

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)10

Conventional sector

ofiiuu [%]T HDof[%]THD

8
Proposed SVPWM

V

IV

III

II

I

VI

vuv [200 V/div.]

6
0

4
Conventional SVPWM

Edc/2 Edc/2

vcom [200 V/div.]

2
0

0
0.0

0.2

0.4
0.6
0.8
Modulation
Modulationindex
indexmm[-]
[-]

1.0
1.0

[5 ms/div.]

1.2
1.2

(a) Conventional SVPWM.

Fig. 18. Output u-phase current THD comparison between
conventional and proposed SVPWM against different modulationindex at cos φ = 0.866.

Proposed sectorF

vuv [200 V/div.]
0

100
3LVSI
efficiencyof iu [%][%]
T HD

E

D

C

B

A

Proposed SVPWM

vcom [200 V/div.]

95

Edc/2

Edc/3

0

Edc/3

90
Conventional SVPWM

Fig. 20. Measured common-mode voltage at m = 0.930 andcos φ = 0.866 (30° lagging).

85
80
0.2

0.6
0.8
0.4
0.6
0.8
Modulation
Modulationindex
indexmm[-]
[-]

1.0

100

1.2

vcom/Edc [%]0.0[5 ms/div.](b) Proposed SVPWM.

Fig. 19. 3LVSI efficiency comparison between conventional andproposed SVPWM against different modulation index atcos φ = 0.866.

10

6.76 %@ 3f

15.6 %@ fsw
0.242 %
@ 150 kHz

1

0.1
0.01

to the motor-frame ground (g in Fig. 1). In practical, the potentialof the center of the dc-bus (o in Fig. 1) with respect to the groundvog is small and slowly varies compared to vno. Therefore, thecommon-mode voltage vcom is defined as the potential difference
between n and o as (17):

0.001
10

100

1000
10000
1000
10000
Frequency [Hz]100000100000(a) Conventional SVPWM.

100

vcom/Edc [%]v +v +v
vcom = vng = vno + vog  vno = uo vo wo . ................... (16)3
The common-mode voltage with large magnitude might result inhigh common-mode current (CMC, motor leakage current). This
may lead to the motor bearing failures, EMI noise and so on (18)–(20).
Note that CMC (motor leakage current) flows to ground through theparasitic capacitances between the motor wirings and frame (19).
Fig. 20 shows the measured common-mode voltage with each
modulation method at the modulation index of 0.930 and the load
power factor of 0.866. Note that the star point of the several hundredkΩ resistances connected to 3LVSI three-phase outputs is probed toobserve vcom as the imaginary star point of the motor load. Fig. 20
demonstrates that the peak to peak value of vcom is increased withthe proposed SVPWM compared to the conventional SVPWM.
However, the dv/dt of vcom is important for the electromagnetic
interference (EMI) (21). When the conventional SVPWM is applied,the equivalent zero vector of the two-level SVPWM in eachconventional sector (e.g., V7 in the sector I) is always applied during
the switching period. The both switching states of the equivalentzero vector (e.g., [+ 0 0] and [0 – –] as V7) leads to the vcom stepchange of Edc/2 over an entire period. On the other hand, theproposed vector patterns to minimize the RMS value of 3LVSI

13.9 %@ 3f

10
10

4.13 %@ fsw

0.332 %
@ 150 kHz

1

0.1
0.01
0.01

0.001
10

100

10000
1000
10000
Frequency [Hz]100000(b) Proposed SVPWM.

Fig. 21. Harmonic components of common-mode voltage at
m = 0.930 and cos φ = 0.866 (30° lagging) (under same conditions
as in Fig. 20). The fundamental frequency f is 40 Hz. The switchingfrequency fsw is 10 kHz.
input current do not contain the application of the equivalent zero
vectors, leading the smaller vcom step change of Edc/3.
Fig. 21 shows the harmonic component of the common-mode
voltage under the same conditions in Fig. 20. Note that thecommon-mode voltage is normalized by Edc. By reducing the stepchange in vcom with the proposed SVPWM, the switching frequency
component of 10 kHz is reduced by 11.5 points, might be leading
to the smaller motor leakage current peak. On the other hand, theproposed SVPWM worsens the 3rd-order vcom component by 7.14
9

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)points compared to the conventional SVPWM. In the proposed
SVPWM, the positive switching state (+) is mainly applied in thefollowing proposed sectors (A, C, E), whereas the negative
switching state (–) is mainly applied in the following proposed
sectors (B, D, F). This asymmetric selection of the switching states
during the consecutive proposed sectors results in the larger vcom
fluctuation at triple frequency of the fundamental waveform, which
is observed in Fig. 20(b). Furthermore, the high-frequency
component such as of 150 kHz is increased by 0.0897 points due tothe complicated voltage space vector selections in the proposed
SVPWM. Assuming that CMC component of 150 kHz is dominant
to design common-mode filter attenuation, the worsened vcom
component of 150 kHz with the proposed SVPWM indicates thatthe proposed SVPWM might lead to the bulkier common-mode
filter than those with the conventional SVPWM.

8.

(5)
(6)

(7)

(8)

(9)

(10)

Conclusion(11)

A novel SVPWM was proposed to reduce 3LVSI input current
harmonics over wide variation of the load power factor. This
proposed SVPWM contributed to the current stress reduction of thesmoothing capacitor and its lifetime extension. The input current
harmonics was reduced by optimizing the combinations of theapplied voltage space vectors to minimize the fluctuation of theinstantaneous input current value around its average value. In
addition, this strategy could adapt to the wide range of load power
factor by changing the combinations of the applied voltage space
vectors according to the directions of the output phase currents.
The experimental results confirmed that the proposed SVPWM
reduce the rms value of 3LVSI input current by 27.4%, while itworsened 3LVSI output current THD. For the film capacitors in the
dc-bus of 3LVSI, the 27.4% input current harmonics reduction
might lead to 47.3% reduction of the capacitor loss and its heating.
Assuming that the electrolytic capacitors (NX series (22), NichiconCorp.) is applied in the dc-bus of 3LVSI, it might lead to 1.36 times
capacitor lifetime extension based on the estimated lifetime
equation (12)(23). Furthermore, the proposed SVPWM reduced
3LVSI input current harmonics over entire range of the load power
factor, which is the typical requirement of the motor drive system.
On the other hand, the dc-bus neutral point potential control is notachievable in the high-modulation index region of the proposed
SVPWM because no redundant vectors are used. However, by
sacrificing the load current quality or the reduction effect on the
input current harmonics, the dc-bus neutral point potential control
is achievable. In addition, the effect on EMI might be anotherdrawback of the proposed SVPWM and will be future task.

(12)

(13)

(14)

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(16)

(17)

(18)

(19)

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(21)

(22)

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(3)

(4)

Koroku Nishizawa

A. Nabae, I. Takahashi, and H. Akagi, “A New Neutral-Point-Clamped PWM
Inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523 (1981)
W. Song, X. Feng, and K. Ma Smedley, “A Carrier-Based PWM Strategy
With the Offset Voltage Injection for Single-Phase Three-Level NeutralPoint-Clamped Converters,” IEEE Trans. Power Electron., vol. 28, no. 3, pp.
1083–1095 (2013)
X. Ge, J. Pu, B. Gou, and Yong-Chao Liu, “An Open-Circuit Fault Diagnosis
Approach for Single-Phase Three-Level Neutral-Point-Clamped Converters,”
IEEE Trans. Power Electron., vol. 33, no. 3, pp. 2559–2570 (2018)
Fuji Electric Co., Ltd., Tokyo, Japan. Fuji Electric Journal, vol. 79, no. 2, pp.
110–117 (2006) (in Japanese)

10(Student member) received the B.S. degree inelectrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan, in 2015, where he is currently working toward
the Ph.D. degree. He is a student member of IEEJ andIEEE. His current research focuses on the modulation
strategy of converters.

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SVPWM for Three-level VSI Input Current Harmonic Reduction (Koroku Nishizawa et al.)Jun-ichi Itoh

(Senior member) received his M.S. and Ph.D. degree
in electrical and electronic systems engineering from
Nagaoka University of Technology, Niigata, Japan in
1996, 2000, respectively. From 1996 to 2004, he waswith Fuji Electric Corporate Research andDevelopment Ltd., Tokyo, Japan. He was with
Nagaoka University of Technology, Niigata, Japan as
an associate professor. Since 2017, he has been aprofessor. His research interests are matrix converters, dc/dc converters,
power factor correction techniques, energy storage system and adjustablespeed drive systems. He received IEEJ Academic Promotion Award (IEEJ
Technical Development Award) in 2007. In addition, he also received Isao
Takahashi Power Electronics Award in IPEC-Sapporo 2010 from IEEJ, 58th
OHM Technology Award from The Foundation for Electrical Science andEngineering, November, 2011, Intelligent Cosmos Award from Intelligent
Cosmos Foundation for the Promotion of Science, May, 2012, and Third
prize award from Energy Conversion Congress and Exposition-Asia, June,
2013. Prizes for Science and Technology (Development Category) from theCommendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology, April 2017. He is a senior memberof the Institute of Electrical Engineers of Japan, the Society of Automotive
Engineers of Japan and the IEEE.

Akihiro Odaka(Member) received the B.S. and M.S. degrees from
Tokyo Denki University, Tokyo, Japan, in 1996 and1998, respectively. Since 1998, he has been with Fuji
Electric Co., Ltd., Tokyo. He is a member of IEEJ andIEEE. His research interests include static converters
and power semiconductor applications.

Akio Toba(Senior member) received the M.E. and Ph.D.
degrees from Tokyo Metropolitan University, Tokyo,
Japan, in 1994 and 2006, respectively. In 1994, hejoined Fuji Electric Co. Ltd., Tokyo, where he has
been conducting the research and development of
power electronics, motor drives, and electricmachines. From 1997 to 1999, he was a Visiting
Researcher with Wisconsin Electric Machines andPower Electronics Consortium, University of
Wisconsin, Madison, USA. He is a senior member of IEEJ and a member ofIEEE.

Hidetoshi Umida(Fellow) received the B.E., M.E. and Ph.D. degrees
in electrical engineering from Tokyo Institute ofTechnology, Tokyo, Japan, in 1970, 1981 and 1984,
respectively. Since 1984, he has been with Fuji
Electric Co., Ltd., Tokyo. He is currently a Chief
Engineer with Fuji’s Corporate R&D Headquarters.
His research interests include control theory and its
application to motor drives and converters. He is afellow of IEEJ and a member of IEEE.

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