Current Balancing Method in Parallel Connected
Inverter Circuit for Megahertz WPT System
Masamichi Yamaguchi
Nagaoka University of Technology
Nagaoka, Niigata, Japanm_yamaguchi@stn.nagaokaut.ac.jp

Keisuke Kusaka
Nagaoka University of Technology
Nagaoka, Niigata, Japan
kusaka@vos.nagaokaut.ac.jp

Abstract— This paper proposes a current balancing circuitof a parallel-connected inverter for a WPT system operated inmegahertz. Current unbalance, which causes a thermal
unbalance and deterioration of the devices, occurs at the output
of each inverter when the output voltage has a difference
between the inverters. Thus, the current balancing circuit,which is able to be applied for megahertz operation, is required.
In this paper, the current balance circuit is investigated toachieve a parallel operation. The current balance circuit iscomposed of two transformers. A self-inductance ratio of thetransformers, which is used in the balance circuit, is calculatedby an analytical consideration to achieve the current balance
condition. The proposed circuit is implemented into a prototypeof the parallel-connected inverter operated around 6.78 MHz.
From the experiments, it is demonstrated that the current
unbalance of each inverter is 6.7% with the proposed balance
circuit.

Inv. 1VDC

In recent years, battery chargers for electric vehicles (EVs)are being developed rapidly by increasing the interest in EVs.
Notably, wireless power transfer (WPT) systems for battery
chargers have been actively studied for the viewpoint of safety
and convenience in this decade [1–2]. Rapid charging isrequired for EVs to reduce the charging time because thecharger using the WPT system takes a long time to charge theonboard batteries. Thus, increasing the output power of the
WPT system to at least ten-kilo watts order output system isurgent.
WPT systems with a transmission frequency of 85 kHz
have been commonly used in WPT systems. However, the tenkilo watts order in the 85 kHz system is bulky and heavy
because the WPT system has a ferrite in a transfer coil. A
heavy system on the vehicle directly causes an increase inpower consumption in the running. Thus, increasing the power
density of the WPT system is necessary. Employing
megahertz order switching frequency is one of the solutions toincrease power density. Thus, the megahertz operation in a
WPT system has been actively studied [3–8].
Inverter circuit, which is applied to WPT system inmegahertz operation, requires nano-second order switching.
Thus, a GaN device, which can switch in a few nano-second,is applied for the WPT system [9–10]. However, the output
power is regulated in a few kilo-watts because the rated powerof the GaN device is still low. On the other hand, the output
power of the WPT system requires ten-kilowatt order toachieve rapid charging for EVs. Thus, a parallel connection of
the GaN devices or inverter circuits [11–12] is necessary to

978-1-7281-9023-5/21/$31.00 ©2021 IEEE

i1

i3

Lr

Cr

v1

Inv. 2

RL

Balancecircuiti2

Resonant load

v2

Fig. 1. Configuration of the balance circuit in parallel-connected
inverter system.

i1
v1

Tr 1 : L1
e11

i2

Keywords—Current balance, Megahertz operation, Wirelesspower transfer, GaN-transistor

I. INTRODUCTION

Jun-ichi Itoh
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp

e12

M12

Tr 1 : L2

Tr 2 : L4

e21

e43

e22

e44

i3
v3

Tr 2 : L3
M34

v2

e33

e34

Fig. 2. Configuration and induced voltage in balance circuit.

accomplish a ten-kilo watts order system. Then, the current
balancing method is required to achieve the parallel
connection because the output voltage has a difference due tothe delay of the switching timing and the difference of theparasitic parameters of the devices between the inverters.
Current unbalance causes thermal unbalance, which may
cause the brake of the devices. However, the difficulty of theaccurate control of a switching timing is still a serious problem
because the control period should be smaller than a few nanosecond in megahertz operation. Moreover, the accurate
adjusting of parasitic parameters is also difficult. Thus, thecurrent balancing method should be employed by passive
components without additional current control.
In this paper, the current balancing method is studied forparallel-connected inverters in megahertz operation. The
advantage of the proposed method is that only passive
components are required because it is hard to control themegahertz operation system with nano-second order ofcontrol time. The rest of this paper is organized as follows.
First, a balancing circuit is theoretically analyzed. Thebalancing circuit is composed of two transformers to achieve
the balancing operation in a parallel structure. Then, theworking of the balancing circuit is simulated in the megahertz
operation. Finally, a prototype with the proposed balance
circuit is demonstrated.

TABLE I. Simulation parameter.
Main circuit parameter

II. CURRENT BALANCING METHOD
A. Configuration of Current Balance Circuit
Parallel connection of the megahertz inverter circuit isnecessary to achieve high output power in a WPT system.
However, the current unbalance occurs between paralleledcircuits caused by the phase difference or the output voltage
difference of each circuit. Thus, the balance circuit, which
absorbs the difference of output voltage in each inverter, isnecessary. Figure 1 shows the structure of the parallelconnected inverter using the balance circuit for the WPTsystem. The balance circuit is connected to the outputs of theinverters. The resonant circuit is connected to the output sideof the balance circuit as a load.
Figure 2 shows the configuration and induced voltage ofthe current balance circuit. The balance circuit consists of two
transformers. The primary side of each transformer isconnected to the output of each inverter. The secondary sideof each transformer is connected to a resonant load in series.
B. Design of Inductance Ratio of Transformer in Balancer
The output voltage v1 of the inverter is given by
v1 = e11 − e12 + e22 − e21 + e44 − e43 + v3 .................... (1).
In the balance circuit, currents i1, i2, and i3 are sinusoidal
because the resonant load is applied. Thus, v1 is expressed as
v1 = j ( L1 − M12 ) i1 + j ( L2 − M12 + L4 ) i3 − jM 34i2 + v3............................................................................ (2),where L1, L2, L3, and L4 are the self-inductances of eachwiring, M12 and M34 are the mutual-inductance. When two
transformers have the same self-inductance and mutualinductance, each inductance is expressed as
L1 = L3 = Lpri ......................................................... (3),L2 = L4 = Lsec ........................................................ (4),M 12 = M 34 = M .................................................... (5),where the Lpri represents the self-inductance of the primaryside, Lsec represents the self-inductance of the secondary side,
M represents mutual inductance. Equation (2) is simplified as
v1 = j ( Lpri − M ) i1 + j ( 2Lsec − M ) i3 − jMi2 + v3............................................................................ (6).
Similarly, the output voltage v2 is also expressed asv2 = j ( Lpri − M ) i2 + j ( 2Lsec − M ) i3 − jMi1 + v3............................................................................ (7).
Then (6) is added to (7),v1 + v2 − 2v3 = j ( Lpri − 2M ) ( i1 + i2 ) + 2 j ( 2Lsec − M ) i3............................................................................ (8).
When the ideal current balancing is achieved, the output
voltage v3 is the average value of each input voltage v1 and v2.
Furthermore, each input current i1 and i2 is the same value, andthe output current i3 is two times larger than each input current.
Each voltage and current condition in ideal balancing
condition is expressed as
v1 + v2......................................................... (9),2ii1 = i2 = 3 ......................................................... (10).
2v3 =Then, (9) and (10) are applied to (8), inductance equation in
the current balance condition is expressed as

DC link voltage

V DC

300 V

Rated power of each inverter

P

2 kW

Switching frequency

Fs

6.78 MHz

Duty

d

40%

Parasitic capasitanceat drain-source of GaN-Transistor

C ds

127 pF

Inductance of primary sideL pri

5.7 H

Inductance of secondary side

L sec

1.425 H

Resonant inductanceLr

5.7 H

Resonant capacitanceCr

100 pF

Load resistance

RL

10 

Balancer paameters

Load parameters

Lpri − 4M + 4Lsec = 0 ............................................ (11).
Mutual inductance M is expressed as
M = k Lpri Lsec ................................................... (12),k = 1 .................................................................. (13),where k is the coupling coefficient, which is considered asunity in an ideal condition. Using (11), (12), and (13), therelationship of Lpri and Lsec in balancing condition is expressedasLpri = 4Lsec .......................................................... (14).
As a result, the winding ratio of the primary windings to thesecondary windings is 2:1 to achieve the balancing conditionof the output current of each inverter.
C. Influence of Leakage Inductance in Balancer
Resonant inductance and capacitance are essential factors
to transmit the power in the WPT system. Thus, the leakage
inductance at the transformer should be considered to satisfy
the resonant conditions. The voltage equation between the
output voltage of Inv. 1 v1 and output voltage of the balance
circuit v3 is expressed as
v1 − v3 = j ( Lpri − M ) i1 + j ( 2Lsec − M ) i3 − jMi2........................................................................... (15).
Then, the current balancing condition (10) is applied to (15),LMM
v1 − v3 = j  pri −+ 2 Lsec − M −  i3 ............. (16).
2
2 
 2

Similarly, the voltage equation between the output voltage of
Inv. 2 v2 and output voltage of the balance circuit v3 is also
expressed as
LMM
v2 − v3 = j  pri −+ 2Lsec − M −  i3 ............. (17).
2
2 
 2

Inductance between the output of each inverter and output of
the balance circuit is expressed as
Lbalancer =

Lpri
2

−

M
M
+ 2Lsec − M −...................... (18),22where Lbalancer represents the inductance from the output ofeach inverter to the output of the balance circuit. Equation (18)is derived as

i3

20
i1

0

i2

-20
-40

100 ns/div

Output voltage [V]Output current [A]

40

450
300
150

v1
v2

0

-150
-300
-450

100 ns/div

i1

0

i2

-20
-40

100 ns/div

Transformer voltage [V]

i3

20

1500
1000
500

Transformer voltage [V]

40

1500
1000
500

Transformer voltage [V]Output current [A](a)Output current.
(b)Output voltage.
Fig. 3. Output voltage and current in ideal condition.

1500
1000
500

0

-500
-1000
-1500

Output current [A](a)Coupling coefficient k : 0.9.
40

i1

0

i2

-20
100 ns/div

Output current [A]

20
i1

i2

-20
-40

100 ns/div(b)Coupling coefficient k : 0.8.
i3

0Primary-side
Secondary-side

0

-500
-1000
-1500

(b)Coupling coefficient k : 0.8.
40

100 ns/div(a)Coupling coefficient k : 0.9.
i3

20

-40

Primary-side
Secondary-side

100 ns/div(c)Coupling coefficient k : 0.7.
Fig. 4. Output current with variation of coupling coefficient.

Lbalancer = 4Lsec (1 − k ) ........................................... (19),by applying (12), (13), and (14) to the (18). The influence ofthe leakage inductance appears in (19). Thus, Lbalancer should
be compensated to satisfy the resonant condition.

III. SIMULATION RESULTThe current balancing in a parallel-connected inverters
circuit is verified by simulation. The rated power of each
inverter is 2 kW, the total output power is 4 kW. Table I shows
the simulation parameters. The self-inductance of the primarywinding Lpri is determined to be the same value as resonanceinductance.
A. Zero Leakage Inductance Condition
Figure 3 shows the output voltage and current in ideal
condition. There is no difference in the output voltage between
the two inverters, and the coupling coefficient k is 1.0. The
output current of each inverter is completely balanced in theideal conditions.
B. Leakage Inductance Condition
Figure 4 shows the current waveforms when k is changed
from 0.7 to 0.9. The resonant condition does not change
because the leakage inductance of the balancer is compensatedby adjusting resonant inductance Lr based on (19). The current
balancing is also achieved with the difference of the coupling
coefficient. Figure 5 shows the voltage waveform of thetransformer with the variation of the coupling coefficient. The
voltage of the transformer increases with decreasing thecoupling coefficient.

Primary-side
Secondary-side

0

-500
-1000
-1500

100 ns/div(c)Coupling coefficient k : 0.7.
Fig. 5. Winding voltage at Tr1 with variation of coupling
coefficient.

C. Phase Delay of Output Voltage in Inv. 2 with Zero
Leakage Inductance
Current balancing is simulated with a phase difference ofthe output voltage between two inverters. The phase of theoutput voltage in the Inv. 2 is purposely delayed from Inv. 1
by 5%, 10%, and 25% of the time period. The coupling
coefficient k is 1.0.
Figure 6 shows the output current with phase delayed
condition. Total output current decreases gradually as theincreasing of phase delay value. The output current of each
inverter is almost balanced in a 5% delayed condition.
However, a slight difference in the output current occurs with
10% and 25% delayed conditions. Figure 7 shows the output
voltage with phase delayed condition. A zero-voltage
switching (ZVS) is not achieved at Inv. 2 with 10% and 25%
delayed condition.
D. Variation of Voltage Amplitude in Inv. 2 with Zero
Leakage Inductance
Current balance working is simulated with the differenceof the amplitude of the output voltage between two inverters.
The maximum output voltage of Inv. 2 is decreased to 290 V,
150 V, and 0 V. The maximum output voltage of Inv. 1 is 300
V in any condition. The phase delay value is zero and coupling
coefficient k is 1.0.
Figure 8 shows the output current with voltage difference
condition. The output current balances in any voltage
condition. Furthermore, the total output current i3 in thei3

Output voltage [V]Output current [A]

40
20

i1

0

i2

-20
-40

100 ns/div

450
300
150
0
-150
-300
-450

Output voltage [V]Output current [A]

i3

20
i1

0

i2

-20
-40

100 ns/div

450
300
150

i1

i2

-20
100 ns/div

Output voltage [V]Output current [A]

i3

-150
-300
-450
450
300
150

i1

i2

-20
100 ns/div

Output voltage [V]Output current [A]

i3

0

450
300
150

i1

i2

-20
100 ns/div

Output voltage [V]Output current [A]

i3

450
300
150

i2

100 ns/div

Output voltage [V]Output current [A]

i1

-20
-40

v2

100 ns/div
v1

v2
100 ns/div(b)Voltage difference : 150 V
i3

0

v1

0
-150
-300
-450

(b)Voltage difference : 150 V
40
20

100 ns/div(a)Voltage difference : 10 V

0

-40

v2

0
-150
-300
-450

(a)Voltage difference : 10 V
40
20

v1

(c)Phase delay : 25% (36.9 ns).
Fig. 7. Output voltage with phase delay.

40

-40

100 ns/div

0
-150
-300
-450

(c)Phase delay : 25% (36.9 ns).
Fig. 6. Output current with phase delay.
20v2(b)Phase delay : 10% (14.7 ns).

0

-40

v1

0

(b)Phase delay : 10% (14.7 ns).
40
20

100 ns/div(a)Phase delay : 5% (7.4 ns).

(a)Phase delay : 5% (7.4 ns).
40

v1
v2

450
300
150

v1
v2

0
-150
-300
-450

100 ns/div(c)Voltage difference : 300 V
Fig. 8. Output current with voltage difference.

(c)Voltage difference : 300 V
Fig. 9. Output voltage with voltage difference.

condition of v2 = 0 is the half value of the ideal condition.
Figure 9 shows the output voltage with voltage difference
condition. The ZVS is achieved in any voltage condition.

E. Phase Delay and Variation of Voltage Amplitude in
Inv.2 with Leakage InductanceThis section shows a simulation result with the variationsof the phase and amplitude of the output voltage when the
coupling coefficient is not unity. The phase delay is caused bya length difference of signal lines or dispersion of delays in
ICs and switching devices in an experiment. The phasedifference is selected to the 10% of the time period byconsidering the above differences. The difference in thevoltage amplitude is caused by a difference of parasitic
parameters of the devices, printed circuit boards, and adispersion of the on-resistance at the devices in an experiment.
Thus, the maximum output voltage of Inv. 2 is selected to 290

The result with voltage difference condition indicates thatthe total output current of the balance circuit i3 is proportional
to the average of each output voltage. Moreover, the output
current keeps conduction when the inverter does not output
the voltage as shown in figure 9 (c). The current should be
convection even if some devices are broken. Thus, anadditional current pass such as a diode is required.

i3

Output voltage [V]Output current [A]

40
20

i1

0

i2

-20
-40

100 ns/div

450
300
150

v1
v2

0
-150
-300
-450

100 ns/div(a)Coupling coefficient k : 0.9.
i3

Output voltage [V]Output current [A](a)Coupling coefficient k : 0.9.
40
20
i1

0

i2

-20
-40

100 ns/div

40

i3

20

i1

0

i2

-20
-40

100 ns/div

v1
v2

0
-150
-300
-450

100 ns/div(b)Coupling coefficient k : 0.7.
Fig. 11. Output voltage with variations of phase and amplitude.
Output voltage [V]Output current [A](b)Coupling coefficient k : 0.7.
Fig. 10. Output current with variations of phase and amplitude.

450
300
150

450
300
150

v1

v2

0

-150
-300
-450

100 ns/div

40

i3

20

i1

0

i2

-20
-40

100 ns/div

Output voltage [V]Output current [A](a)Output current.
(b)Output voltage.
Fig. 12. Output current and voltage with self-inductance difference between Tr1 and Tr2.
450
300
150

v1

v2

0

-150
-300
-450

100 ns/div(a)Output current.
(b)Output voltage.
Fig. 13. Output current and voltage with difference of the ratio of self-inductance.

V due to the difference of the parasitic parameters. The
coupling coefficient k is 0.7 and 0.9.

TABLE II. Parameters of experimental circuit.
Main circuit parameter

Figure 10 shows the current waveforms with the variationsof the phase and amplitude of the output voltage. The current
balancing is also achieved. Figure 11 shows the output voltage
waveforms. ZVS is achieved in Inv. 1, whereas ZVS is notachieved in Inv. 2.

DC link voltage

V DC

200 V

Switching frequency

Fs

6.4 MHz

Duty

d

36%

F. Variation of Self-inductance in Balance Circuit
The self-inductance of two transformers, which are usedin balancer, has tolerance in a prototype. Moreover, a ratio of
the inductance at the primary-side and secondary-side also hasa slight difference from the designed value. Thus, the workingof the current balancing with the inductance variation isnecessary. The maximum output voltage of Inv. 2 is 290 V,
the phase delay of the output voltage of Inv. 2 is 5% from Inv.
1, and the coupling coefficient k is 0.8 in the following
simulation.

Inductance of primary sideL pri

4.3 H

Inductance of secondary sideL sec

1.3 H

Coupling factor

k

0.84

Resonant inductanceLr

5.7 H

Resonant capacitanceCr

100 pF

Load resistance

RL

10 

Figure 12 shows the output current and voltage of theinverter with a variation of the self-inductance between the
two transformers. The self-inductances of the Tr1, L1 and L2,
are 1.5 times as much as the self-inductance of the Tr2, L3 andL4. From figure 12(a), the current balance is achieved between
two inverters. However, the ZVS working at the output
voltage of each inverter is not achieved, as shown in figure12(b).
Figure 13 shows the output current and voltage of two
inverters with a difference in the ratio of the self-inductance atBalancer paameters

Load parameters

the primary-side and secondary-side. The self-inductance ofthe primary-side L1 and L3 is 1.5 times as much as the designed
value. As a result, the inductance ratio of the primary-side to
the secondary-side is 6:1. From figure 13(a), the current
balance is also achieved between two inverters. However, theZVS working of the output voltage of Inv. 2 v2 is not achieved,
as shown in figure 13(b).
IV. EXPERIMENTS OF CURRENT BALANCING
The current balancing with the proposed balancer isdemonstrated with the parallel-connected inverters. Table IIshows the circuit parameters for the experiment. Figure 14

shows the balance circuit. The transformer used in thebalancer has no core. Moreover, the two transformers are
orthogonalized to avoid magnetic interference.

f 130 mm

A. Current Balancing without Phase Delay
Figure 15 shows the output current and voltage withoutphase delay. The amplitude of output voltage has a differenceof about 20 V. The output current of each inverter is balancedwith the difference of output voltage. Moreover, The output
voltage of each inverter achieves the ZVS.
B. Current Balancing with Phase Delay
Figure 16 shows the output current and voltage with aphase delay. The output voltage of Inv. 2 delayed 5.7 ns(3.8%) from Inv. 1. The output current of each inverter isalmost balanced. The maximum current of Inv.1 iinv1 is 4.5A
and the maximum current of Inv.2 iinv2 is 4.2A. The error rateof the output current is about 6.7%. The output voltage of each
inverter achieves the ZVS working.
V. CONCLUSION
In this paper, the current balance circuit for a parallelconnected inverter in the megahertz operation has been
proposed. The proposed circuit employs only passive
components, which do not need any additional current control.
The balancing circuit consists of two transformers. The ratioof the self-inductance of the transformers, primary-side tosecondary-side, to achieve the current balancing is derived
from the voltage equations. The current balance working issimulated with the phase difference and amplitude differenceof the output voltage between two inverters. Each output
current is balanced with the phase difference and amplitudedifference of the output voltage, and the self-inductancedifference of the balance circuit. Further consideration of the
ZVS condition of each inverter is necessary. The proposedbalance circuit is implemented into a prototype of the parallelconnected inverter circuit. From the experiments, it isdemonstrated that the output current of each inverter isbalanced with an error rate of 6.7% when the 3.8% phase delay
and 20V amplitude difference between the two inverters inmegahertz operation.
ACKNOWLEDGMENT
This work was supported by Council for Science,
Technology and Innovation (CSTI), Cross-ministerial
Strategic Innovation Promotion Program (SIP), “Energy
systems of an Internet of Energy (IoE) society” (Funding
agency: JST).
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Fig. 14. Balance circuit at 6.78 MHz range.
vinv2

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vinv1

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iinv2

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