Design of High-Order Phase-Lock loops Controller using
Simulink
Sitchai BOONPIYATHUD 1, Viboon CHUNKAG 2, and Pist LIUTANAKUL 2121

Department of Electrical Engineering, Pathumwan Institute of Technology, Thailand
Department of Electrical and Computer Engineering, King Mongkut’s University of Technology North Bangkok,Thailand

Introduction

Phase-Locked Loops (PLLs) have developed into manyother electrical, instrument control and electronic systems.
Inattentive of their individual implementation, with their related
specific problems, the basic theory common to all PLLs is noteasy to understanding. Fundamentally, this is because it isfeedback system and exhibits an intrinsic nonlinear nature.
Even assuming approximate linear model, analysis andsubsequent design, of any higher-order( above two ) PLL ischallenging. To make things even more difficult, the literatureon PLLs is plagued with some misconceptions which haveperpetuated for years. Among these misconceptions are the useof parameters to characterise the PLL which are meaninglessfor higher-order PLLs, such as the loop filter (LF) classifications(passive as opposed to active ) that do not make sense today inimplementations dominated by charge pump (CP) topologies,
and the confusion of order and type [1]. The accurate analysisof third-order phase-locked loops (PLLs) , those including asecond-order loop filter (LF) , is normally eluded because it isvery complex.
The goal of this paper however, is to propose an alternative
approach to the intuitive and analytic design of third -, and evenfourth-order loops, as a natural extension of second-order PLL.
The approach will also be seen as related to the extension of aconventional PLL (second order) with the so called “aidedacquisition” loops [2]. The concepts shown here are general ,but of particular interest in applications where the PLL need tooperated in a wide hold range, i.e., not a small fraction of thefree running frequency (FRF) of the oscillator.
The design and constructional features of the whole system
are presented in this paper. Experimental work has been carriedout on the induction heating system to measure the operation
performance under various loading conditions. Experimental
results indicate that the operates successfully with a power
factor very closed to unity. A simulation model has beendevelop using Simulink , which has been used to analyse anddesign the PLL control system. A mathematical model of thesystem has also been developed in discrete time, with which thestability of the system can be assessed.
2Experimental setup

Block diagram and induction heating circuit is shown in
Fig.1 and Fig.2, where it may be seen that the output power iscontrolled by a single phase controlled rectifier and that theinverter is of the voltage-fed load resonant type. A highfrequency impedance matching transformer with a turns ratio
33/6 has been designed and constructed with nearly condition isnature, and this is complex match the impedances of theconverter and induction heating coil.

Current
Zero-crossDetector

Phase Angle
Set Point

PhaseDetector

Low passfilter

PIController

Voltagecontrelledoscillator

Dead Band

Inverter

VoltageZero-crossDetector

Delay Time

Figure1. Block diagram of the proposed modified PLL
Diode Bridge
RectifierFull-Bridge
Inverterioid
S1
220 Vrms
50 HzCd

D1

S4

D4 Cb

Rd vd

vo
S3

D3

S2

Transformer
High-frequency

Induction Coiland Hard WorkCo

33 : 6D2

S1 S2 S3 S4DriverCircuitio(sensor)

PLLvo(sensor)

Figure 2. High frequency Induction heating circuit
2.1

Second-order PLL and Aided Acquisition loops
A typical model of an analog PLL including a phasedetector (PD), an LF, and a voltage-controlled oscillator (VCO)
shown in Fig.3. Signals θin and out are input and output
phases.VCO is usually modelled by integrator, since phase is theintegral of instantaneous frequency with gain Kv rads/(V.s). Asfor the PD, its model depends on the implementation, but it isusually approximated by the phase difference with in limited
range, scaled by a gain Kθ. The LF is assumed linear, and thus
the simplest case, apart from trivial PLL with no filter, is a firstorder one. Thus, its most general transfer function, assuming
unity dc gain, isss(1)H LF ( s )  H1 ( s )  (1) (1)1z
1 pequation for this particular case can be found elsewhere,
although they are quite often buried by particular electricalparameters dependent on the implementations of the filters.
Since dc filter gain is unity, PLL gain is defined as K=Kv.Kθ.
2.2
Third-order PLLS and Higher-order PLLs
This latter model, though conceptually interesting, can befurther simplified if one takes into consideration that the VCO
can be modelled as an integrator. Then , integration by the VCO
and the differentiator operation, comprising the scaling factor,
cancel out giving the equivalent scheme shown in Fig.5

Figure 3. PLL block diagram
Figure 8. Third-order loop-filter frequency response1
H LF ( s )  H1 ( s )(1 H ( s ))(1 H 3 ( s ))2sFigure 4. First-order loop-filter frequency response
Clearly, LF2 can be now combined with LF1 to give asingle LF. If LF1 is of order one, as in (1), and LF2 is also oforder one with a single pole at ω2sH 2 ( s )  1 (1 )(2)
2
We come up with a second-order LF and thus a third-order
PLL. The gobal response of such filter, also known asPrzedpelski Filter [5], is shown below, and its Bode plot presentin Fig.6.
ss(1)(1 )11 z2 2(3)H LF ( s )  H1 ( s )s1 H 2 ( s )s1
1 p
In this process we have gained some insight into meaning ofeach one of the time constants and signals into the circuit. A
constant value is an indication of the situation described. Such a
difference signal can be used the appropriate delay to further
correct the VCO input and minimize the phase error. The
proposed modification is shown in the Fig.7.
If the filter LF3 is of first-order too, with cut-off frequency ω3 ,then, the overall performance of the two loops can beassimilated to a single LF whose response is now.

Figure 5. Second-order PLL block diagramss 2  3 (1 1z )(1 2 )(1 3 )s2

(1s1 p(4))

Its bode plot is represent in Fig.8 where the time constant of
the new filter, 1/ω3, is higher than 1/ω2. This condition is
however not need for the correct operation of loop since,according to (4), the two poles can be exchange.
3Simulation Model

A Simulink model, which allows an evaluation of how thevarious feedback loop affect the operation of the PLL, and theevolution of the signals involved, was implemented, We willproceed by analyzing, first the operation of second-order loop
and then appraise how it is affected by the introduction of thenew loops. This will mimic the design procedure to be followed, regardless of whether the LF is implemented in a compact
manner in the final design(just plug-in the LF parameters fromdesign), or with the explicit feedback loop
4Conclusion

We have present high-order PLLs, as a natural extension oftype I PLLs of lower order (one, two and even three). Although
this approach in general ,we have restricted ourselves toshowing practical situation with order no higher than five, andtype no higher than III. The theorectical frame work is based on
the PLL model, and in particular the LF, through serval
feedback loop.
The analysis and the results presented in this paper support
two basic assumptionsthat, although not original, are notgenerally and explicitly accepted in the literature. First, there is
the assumption that PLL gain, K, characterises PLL bandwidth
more than any otherparameter. This is particularly true if westart the design with a highly damped, type I, PLL. Secondly,Type, much more than order, describes OLL performance.
References

Figure 6. Second-order loop-filter frequency response

Figure 7. Third-order PLL block diagram[1] Alfonso Carlosena, “Design of High-Order Phase-Lock Loops”,
IEEE trans. Circuits Syst.-II, Vol.54, No.1, pp. 9-13, Jan.2007.
[2] N. S. Bayindir, O. Kükrer and M. Yakup, “DSP-based PLLcontrolled 50-100 kHz 20 kW high-frequency induction heating system
for surface hardening and welding application,” IEE Proc.-Electr PowerAppl.,Vol. 150, No. 3, May 2003, pp. 365-370[3] A. B. Przedpelski, “Optimize phase locks to meet your needs-or
determine why you can’t,” Electron. Design, vol.16, no. 19, Sep.1979.
[4] Jing HUI, Xiaohui ZANG, Fengjiu ZHANG and Jinfei SHEN,“DPLL in Cooperated with PI Controller for HF-Inverter Control
System,” ICIEA 2006, pp. 1-5.
[5] N. Kamal, S. Al-Sarawi, N. E. Weste and D. Abbort, “A PhaseLocked Loop Reference Spur Modelling using Simulink,” ICEDSA
2010, pp. 279-283.