Optimization for the Number of Parallel-connected Switching
Devices in High-efficiency High-power Converters
Koroku Nishizawa1, Tetsunori Kinoshita1, and Jun-ichi Itoh1
1

Nagaoka University of Technology, Japan

Corresponding author: Koroku Nishizawa, koroku_nishizawa@stn.nagaokaut.ac.jp

Abstract
This paper proposes an optimal design method for a high-efficiency and high-power converters. The
system efficiency is improved by the design of the converters with the some small-current-rating parallelconnected devices, which achieve fast switching and low switching loss. The optimal number of parallelconnected SiC-MOSFETs for the maximum system efficiency is determined to achieve the reduction inboth the conduction and the no-load loss due to drain-source parasitic capacitance of a SiC-MOSFET.
The experimental results confirm that the optimal number of parallel-connected SiC-MOSFETs whichleads to the smallest total device losses exists.

1 Introduction
Recently, grid-tied inverters such as photovoltaic
systems, wind turbine systems have been actively
studied for energy conservation [1]–[3]. The gridtied inverter must have a small volume to increase
the power density of the system. The wide band
gap device such as silicon carbide metal-oxidesemiconductor
field-effecttransistor(SiCMOSFET) allows a lower device loss and higher
switching frequency; consequently, the heatsink
and the interconnected inductors can be shrunk[4]–[5]. In high-power converter applications,several SiC-MOSFET chips, connected in parallel,
are necessary for an increase of the converter
current capacity.
In a parallel drive of SiC-MOSFETs, steady andtransient current imbalance, leading a low system
reliability, might occur between these paralleled
SiC-MOSFETs due to the device parameters(such as Ron and Vth) and circuit stray inductancemismatches [6]. Then, some research works tried
to balance the transient current imbalance [7]–[8].
As noted above, the parallel-connected SiCMOSFETs has to deal with many challenges; thus,
the number of parallel-connected SiC-MOSFETs
should be only large enough to allow the system
rated current, i.e. the minimum required number.
On the other hand, new design method to improve
the system efficiency by increasing the number ofparallel-connected power devices and reducing
the conduction loss has been proposed [9]. This
design method is based on the premise that the
total switching loss are unchanged even when thenumber of parallel-connected devices increases.
However, the turn-on loss actually includes
voltage-current cross-over loss and so-called “noload loss” due to the discharge of the drain-source
parasitic capacitance of SiC-MOSFET [10].
Furthermore, the gate drive loss increases as thenumber of driven SiC-MOSFETs increase.
Therefore, it is necessary to determine the optimal
number of parallel-connected devices for a highsystem efficiency with the aim of the reduction in
not only the conduction loss but also the no-loadloss and the gate drive loss.
This paper presents the analysis about therelationships between each losses in theparalleled SiC-MOSFETs and the number ofparallel-connected SiCMOSFETs. In addition, therelationship between the required cooler
performance and the parallel number is also
clarified. The calculation results based on the
50 kW three-phase grid-tied inverter confirm thatthe low-current-rating SiC-MOSFET achieves thelow switching losses and be advantageous for thehigh system efficiency. Furthermore, theexperimental results using 4 kW three-phase
inverter confirm that the number of parallelconnected SiC-MOSFETs should be carefullyselected for achieving the high system efficiency
with the considerations of all the conduction loss
and the no-load loss due to the drain-source
parasitic capacitance and the gate drive loss.

2 Relationship between Losses
and Number of ParallelConnected Devices

iLoad /NiLoad /NCds

Cds(a) 1 device / 1 arm.

(b) N devices / 1 arm.

Fig. 1: Arm configuration examples.

(1)

2.1 Conduction Loss
Fig. 1 shows the configuration examples ofparallel-connected switches. The stray resistances
and inductances are neglected and the load
current iLoad are assumed to be equally divided by
the paralleled SiC-MOSFETs. In addition, the onresistances of SiC-MOSFETs are sufficiently small
and the forward voltage drop of the body diode ishigh due to the large bandgap of SiC [11];therefore, both the forward and inverse currents
flow in MOSFET except for the dead-time period.
Assuming that the dead-time is sufficiently shortand negligible, the conduction loss of a body diodeduring the dead-time is also negligible. Under
these assumptions, the conduction loss of theparalleled SiC-MOSFETs can be calculated as2

1 1 I 
Pcond = N  ron   m 
2 N 2
(2)
ron I m2=
4N
where N is the number of parallel-connected SiCMOSFETs, ron is the on-state resistance, and Im is
the maximum value of the load current. The
conduction loss is inversely proportional to thenumber of parallel-connected SiC-MOSFETs.

2.2 Switching Loss
Fig. 2 shows the relationship between switchingloss energies of SiC-MOSFET (SCT3080KL,
Rohm) and a drain current [12]. In this paper, theswitching loss is defined as the sum of turn-on loss,
turn-off loss, and body diode reverse recovery loss.
The body diode of SiC-MOSFET is a P-N junction
diode with short minority carrier lifetime [11]. This

700

Switching energy [mJ]Power device losses can be classified into the
conduction loss Pcond which is proportional to thesquare of the current, the switching loss Psw which
is proportional to the current, and the currentindependent no-load loss PCds.
Ploss = Pcond + Psw + PCds .

iLoad
iLoad

Datasheet
Ta = 25℃
Vdcd = 600 V
vgs = 18 V/0 V
RG_ext = 0 Ω
L = 750 µH

600
500
400
300

200

1
2
eon + CdsVdc
2

eoff

100
0
0

5

10
15
20
Drain current id [A]2530

Fig. 2: Switching loss energies of SCT3080KL, Rohm
versus drain current.

fact enables a fast recovery performance; thus, thediode reverse recovery loss is negligible. The
switching loss of the paralleled SiC-MOSFETs canbe calculated as()

 Vdc eon + eoff f sw  1 2 Im
Psw = N  0 N sin ( +  ) d
V
I
2

dcd
md



(

)

 Vdc I m eon + eoff f sw  1 2


=

0 sin ( +  ) d
V
I
dcd
md
 2


(3)

where Vdc is the DC-link voltage, eon and eoff are
the voltage-current cross-over turn-on and turn-off
energies per one switching transition, Vdcd and Imd
are the voltage and current when eon and eoff aremeasured, and fsw is the switching frequency.
Assuming that the turn-on and turn-off losses arealmost proportional to the drain current, the total
switching loss is unchanged even when thenumber of parallel-connected SiC-MOSFETs
changes.

2.3 No-load Loss due to Discharge ofDrain-Source Parasitic Capacitance

Pcond .1
+ Psw.1 + N  PCds.1 [W]N

Pcond .1 + Psw.1 + PCds.1 [W]

When the SiC-MOSFET turns off with the voltage
applied between the drain and source, the drainsource parasitic capacitance Cds is charged.
Consequently, the energies stored in the parasitic
capacitance are consumed as the joule loss in the
on-state resistance at the next turn-on hardswitching [10]. Therefore, the no-load loss is
described with the turn-on loss as the black line in
Fig. 2 and calculated as

1(4)
PCds = N  CdsVdc2 f sw .
2
The no-load loss is proportional to the number ofparallel-connected SiC-MOSFETs.

Tj [℃]Tj
Rth(j-c)

Tc [℃]

Rth(j-c)
Tc

Rth(c-f)Rth(c-f)

Tf [℃]Tf
Rth(f-a) [℃ / W]Rth(f-a)

Ta [℃]

Ta(a) 1 device / 1 arm.

Indicesj : Junction
c : Casef : Fina : Ambient(b) N devices / 1 arm.

Fig. 3: Heat equivalent circuits of each arm withthermal resistances.

2.4 Gate Drive Loss
In addition to the power device losses in (1), thepower consumed by the SiC-MOSFET gate drive
circuit also contributes the system efficiency. The
power consumption of the gate drive circuit can becalculated as [13]Pdrive = N  QgVgs f sw

(5)

where Qg is the total gate charge, and Vgs is thegate-source voltage. The gate drive loss is also
proportional to the number of parallel-connected
SiC-MOSFETs as the no-load loss.

3 Relationship between Required
Cooler Performance and Number
of Parallel-Connected Devices
Fig. 3 shows the heat equivalent circuits of eacharm with thermal resistances Rth. The case where
only one switch is attached to the heatsink isshown in Fig. 3(a), and the case where the plural
parallel-connected switches are attached to theheatsink is shown in Fig. 3(b), respectively. In thissection, the required thermal resistance ofheatsink Rth(f-a) is calculated as the required cooler
performance. Besides, the thermal resistance
between case and fin Rth(c-f) is neglected. In thecase where one switch is attached to the heatsinkshown in Fig. 3(a), the relationship between thejunction temperature and the power device losses
can be expressed as()

T j = ( Pcond .1 + Psw.1 + PCds.1 )  Rth ( j −c ) + Rth ( f −a ) + Ta

(6)

where Pcond.1, Psw.1, and PCds.1 are the conduction
loss, switching loss, and no-load loss in the casewhere the arm consists of only one switch. The
required heat sink thermal resistance Rth(f-a).req
such that the junction temperature does notexceed its absolute maximum rating Tj.max can becalculated as

Rth ( f −a ).1.req 

T j .max − Ta
Pcond .1 + Psw.1 + PCds.1− Rth ( j −c ) .

(7)

The required heatsink thermal resistance in thecase where the arm consists of plural switches
connected in parallel shown in Fig. 3(b) can becalculated in the same way above as

Rth ( f −a ). N .req 

T j .max − Ta−

Rth ( j −c ). (8)Pcond .1
N
+ Psw.1 + N  PCds.1
N
Expressions (7) and (8) confirm that the heatsinkof which thermal resistance is higher is applicableas the number of parallel-connected devices
increases in case where the sum of the conduction
loss and the no-load loss can be reduced byincreasing the parallel number. Besides, the firstterm of (8) becomes dominant as the parallel
number increases. The cooler of the power
converter is generally designed at the maximum
power and the maximum loss point, where theconduction loss is dominant. For the above
reasons, the required heatsink thermal resistancein (8) can be regarded as roughly proportional tothe parallel number N. Therefore, the heatsink
becomes shrunk as the parallel number increases
compared to the case where the arm consists of
only one switch.

Table. 1:

4 System Efficiency Dependence
on SiC-MOSFET Current-Rating
In this section, the system efficiency of 50 kW
three-phase 2-level grid-tied inverter, of which
specifications are listed in Table 1, is analyzed withthe several current-rating SiC-MOSFETs using
PLECS circuit simulator. The operating point at
25 kW (0.5 p.u.) is considered.
Table 2 lists the efficiency-related parameters of
the 1200 V-class SiC-MOSFETs released from
ROHM Co., Ltd. Five TO-247 package SiCMOSFETs and two full SiC power modules withdifferent current-ratings are selected forcomparison [12], [14]–[19]. All of them have thegate trench and source trench structures, i.e. all ofthem are ROHM 3rd generation SiC-MOSFET.
Nmin means the minimal required number ofparallel-connected devices to increase the current
capacity of each arm by 1.5 times the rated currentof 50 kW inverter.
RDS(on) is the on-resistance of SiC-MOSFET, therelated parameter to the conduction loss Pcond. Onresistance of each device tend to be smaller as thecurrent-rating of which increases. Note that an
actual on-resistance of each arm consisted ofplural switches connected in parallel is RDS(on)/N.
Psw(Pout=25 kW)/fsw means the total switching loss
energies of the three-phase inverter, of which thedevice parallel number is Nmin, at the output powerof 25 kW. This parameter is calculated based on
the datasheet using PLECS loss analysis. The
analysis results confirm that an application of thesmall-current-rating SiC-MOSFET saves the total
switching loss energies due to its fast switching
speed. As mentioned in sub-section 2.2, theswitching losses are theoretically unchanged inany device parallel number; therefore, the multiple

Table. 2:

Specification list of 50 kW three-phasegrid-tied inverter.
Rated output power
DC-link voltage
Line to line voltage
Power factor
Rated grid current
Switching frequency

Pn
Vdc
vac
cos φ
ign
fsw

50 kW
400 V
200 Vrms
0.96
150 Arms
20 kHzparallel connection of the small-current-rating
devices is advantageous for the switching loss
reduction.
Cds(Vds=400 V) is the drain-source parasitic
capacitance when the DC-link voltage of 400 V isapplied between drain and source, the relatedparameter to the no-load loss PCds. In discreteswitches which have only the body diode, Cds isalmost proportional to the device current-rating.
On the other hand, in power modules, the schottky
barrier diode is connected in parallel to the SiCMOSFETs. Therefore, Cds of these power modules
is higher than the value which is inferable from the
proportional relationship between Cds of SBD-lessdiscrete device and current-rating.
Qg(Vgs=18 V) is the total gate charge at the gatesource voltage of 18 V, the related parameter tothe gate drive loss Pdrive. As with Cds, Qg is almost
proportional to the current-rating in discreteswitches; but this relationship does not holdbetween discrete switch and power module. This
fact indicates that the power module consists ofseveral SiC-MOSFET chips with some currentcapacity margin and the chip parallel number isdecided with the consideration for the current
imbalance due to the chip parameter mismatchand stray component mismatch.

Parameters list of 1200 V-class SiC-MOSFETs released from ROHM Co., Ltd.
SiC-MOSFET

VDSS
[V]

ID
[A]

Nmin
[-]

RDS(on)[mΩ]

Psw(Pout = 25kW) /fsw
[mJ]

SCT3160KL [14]

1200

17

14

160

2.10

23

[12]

1200

31

8

80

2.46

50

60

SCT3040KL [15]

1200

55

5

40

3.87

60

102

SCT3030KL [16]

1200

72

4

30

5.36

90

131

119

178

SCT3080KL

SCT3022KL[17]

Cds(Vds = 400V) Qg(Vgs = 18V)
[pF]
[nC]
42

1200

95

3

22

4.94

[18]

1200

180

2

10

11.3

790

610

BSM400D12P3G002 [19]

1200

400

1

4.3

15.7

1730

1100

BSM180D12P3C007

EquivalentcircuitBody diodeSBD

100.099.5

System efficiency [%]SCT3160KL(1200 V, 17 A)

SCT3080KL
SCT3022KL(1200 V, 31 A)(1200 V, 95 A) SCT3040KL(1200 V, 55 A)

99.0

SCT3030KL(1200 V, 72 A)

98.5

BSM180D12P3C007 (1200 V, 180 A)
98.0

BSM400D12P3G002 (1200 V, 400 A)
97.5

97.0
0

5

10

15

20

25

30

35

40

45

50

Number of parallel-connected devices N [-](a) System efficiency versus number of parallel-connected devices.
600

552 W

Loss [W]

500

434 W
Pdrive

400
300

208 W

211 W

245 W

224 W

Psw + PCds

211 W

200
100

Pcond

0

SCT3160KL(1200 V, 17 A)
N = 34

SCT3080KL(1200 V, 31 A)
N = 16

SCT3040KL(1200 V, 55 A)
N=9

SCT3030KL(1200 V, 72 A)
N=8

SCT3022KL(1200 V, 95 A)
N=6

BSM180D12P3C007 BSM400D12P3G002(1200 V, 180 A)(1200 V, 400 A)
N=2
N=1(b) Loss distribution at maximum efficiency point.
Fig. 4: Loss analysis results of 50 kW three-phase VSI with several current-rating SiC-MOSFETs at operating
point of 25 kW (0.5 p.u.).

Fig. 4 shows the loss analysis results of the 50 kW
three-phase VSI with several current-rating SiCMOSFETs, listed in table 2. The system efficiency
is calculated with the consideration for Pcond, Psw,
PCds, and Pdrive. Fig. 4(a) confirms that the systemefficiency improves as the number of parallelconnected devices is increased from Nmin; then,the efficiency worsens after exceeding a certain
parallel number in the case of discrete switches.
This characteristic is attributed to the fact that theincreased amount of the no-load loss and gate
drive loss becomes higher than the decreased

amount of the conduction loss when N exceeds thecertain parallel number. On the other hand, thesystem efficiency does not improve even when theparallel number is increased from Nmin in the caseof power modules, of which no-load loss and gate
drive loss are inherently large. In addition, Fig. 4(a)confirms that the higher maximum systemefficiency can be obtained with the SiC-MOSFETs
whose current-rating is small. In particular, theefficiency can be improved at most when the 34
switches whose current-rating is the minimum
between the candidates (SCT3160KL) areSCT3160KL
SCT3080KL(1200 V, 17 A) (1200 V, 31 A)

System efficiency [%]

99.5
99.0

SCT3030KL(1200 V, 72 A)

98.5

SCT3040KL(1200 V, 55 A)

Sup

97.5

Swp
L
R
iu load load
vac iv
iw

Lf
Cdc
Vdc +

BSM180D12P3C007(1200 V, 180 A)

98.0

Svp

SCT3022KL(1200 V, 95 A)

Sun

BSM400D12P3G002(1200 V, 400 A)

Svn

Swn

97.0

Cf
0

0.1

0.2

0.3

0.4

isw.rms per one switch [p.u.]

Fig. 5: System efficiency versus normalized rms
current value per one switch.

connected in parallel. Fig. 4(b) confirms that the
conduction losses Pcond at the maximum efficiency
points are almost equal at around 100 W
regardless of the current-rating of the applied SiCMOSFET. This fact indicates that a high onresistance, which is a disadvantage of a smallcurrent-rating SiC-MOSFET, is conquerable byincreasing the parallel number and equivalently
increasing the chip area. Furthermore, Fig. 4(b)confirms that the gate drive loss Pdrive are almost
equal at around 3 W regardless of the currentrating. Therefore, Pdrive does not degrade thesystem efficiency even if the small-current-rating
SiC-MOSFETs are driven by multiple parallel
connections because these total gate charges are
sufficiently small. As a conclusion, the design ofthe converters in the configuration with the multiple
small-current-rating
parallel-connected
SiCMOSFETs, whose switching speed is faster thanthose of the large-current-rating SiC-MOSFETs, issuitable for pushing up the system efficiency.
Fig. 5 shows the relationship between theanalyzed system efficiency and the rms current
value per one switch. The horizontal axis means
the flowing current rms value per one switch which
is normalized by the maximum drain current ratingof each switch. This results confirm that the optimal
drain current derating pushes up the systemefficiency. In particular, about 85% drain current
derating is the optimal for the high efficiency.

5 Experimental Verification of
Optimized Number of ParallelConnected Devices
Fig. 6 shows the experimental setup of the 2 kW
three-phase VSI with the LC filter and the RL-load.
The experimental conditions are listed in Table 3.
The three-phase VSI system efficiency is

SiC-MOSFET: SCT3080KL (Rohm)(1200 V, 31 A)

Fig. 6: 2 kW three-phase VSI with LC filter.
Table. 3:Experimental conditions.
Rated output powerPnDC-link voltage
Vdc
Line to line voltagevacDC-link Capacitor
Cdc
Filter inductor (%Z)
Lf
Filter capacitor (%Y) Cf
Load Power factor
cos φ
Number of parallelNconnected devices
Switching frequency fsw
Dead-time
td

2 kW
400 V
200 Vrms
680 µF
3 mH (3.1%)
2.2 µF (1.4%)
0.96
1, 2, 410, 20 kHz
0.5 µsPhase voltage [100 V/div.]
U phaseV phase0V

Load current [10 A/div.]
0A

U phaseV phase[4 ms/div.]

Fig. 7: VSI operating waveforms at N = 4, fsw = 20 kHz.

measured using Yokogawa WT 1800 power
analyzer with regard to N of 1, 2, 4 and fsw of
10 kHz, 20 kHz. The VSI is driven by thetriangular-carrier comparison PWM with thesinusoidal modulating signals whose modulationindex of 0.86 and the fundamental frequency of
50 Hz.
Fig. 7 shows the VSI operating waveforms at the
number of parallel-connected device of 4 and theEfficiency

99.6

99.4

Psw + PCds

99.2

Pcond

99.0
1

2

3

4

Loss [W]

99.8

16
14
12
10
8
6
4
2
0

100.0

Pout = 1.81 kW
99.8

Psw + PCds

99.6

Efficiency
99.4

Efficiency [%]100.0

Pout = 1.86 kW
Efficiency [%]Loss [W]

16
14
12
10
8
6
4
2
0

99.2

Pcond

99.0
1

2

3

4

Numberparallel-connected
devices[-]N [-]Numberparallel-connected
devices[-]N [-]Deviceofparallel
connection number
Deviceofparallel
connection number(a) fsw = 10 kHz.
(b) fsw = 20 kHz.
Fig. 8: Measured inverter losses and system efficiency versus number of parallel-connected SiC-MOSFETs
against different switching frequency.

switching frequency of 20 kHz. Similar waveforms
are observed even when the number of parallelconnected devices and the switching frequency
are changed.
Fig. 8 shows the relationship between themeasured VSI losses, efficiency, and the numberof parallel-connected SiC-MOSFETs against
different switching frequency. In the case of fsw =10 kHz shown in Fig. 8(a), the conduction loss
decreases in inverse proportion to the number ofparallel-connected devices. In contrast, the sum of
the switching loss and no-load loss increases withlarge number of parallel-connected devices
because the equivalent drain-source parasitic
capacitance becomes large. In particular, in thecomparison between N = 2 and 4, a decrease in
the conduction loss and an increase in the no-loadloss are almost same, leading to the almost same
system efficiency level. On the other hand, in thecase of fsw = 20 kHz shown in Fig. 8(b), theincreased amount of the sum of the switching loss
and no-load loss by increasing N becomes larger
than the case of fsw = 10 kHz. As a result, themaximum system efficiency is obtained at N = 2.
These results confirm that it is necessary to
determine the number of parallel-connected SiCMOSFETs with the consideration of both theconduction loss and the no-load loss in order toachieve the higher system efficiency.

6 Conclusion
This paper clarified the relationships between
losses of the parallel-connected SiC-MOSFETs
applied in the power converters and the number ofparallel-connected number. In addition, therelationship between the required cooler

performance and the number of parallel-connected
devices was also clarified. Then, the systemefficiency and the power device losses of 50 kW
three-phase grid-tied inverter were calculated withseveral SiC-MOSFETs whose current-ratings aredifferent. These calculation results confirmed thatthemultiple
small-current-rating
parallelconnected SiC-MOSFETs achieve the low
switching losses and are advantageous for thehigh system efficiency. Lastly, the 2 kW threephase VSI system efficiency was measured withregard to the different number of parallelconnected devices and the switching frequency.
This experimental results confirmed that the theoryof relationships between losses of the parallelconnected SiC-MOSFETs and the parallel number
was correct, and the optimal number of parallelconnected SiC-MOSFETs which led to thesmallest total device losses existed. Based onthese works, the design guideline for the converter
configuration to achieve high-efficiency wasclarified.
In an actual system, the multiple parallelconnection of SiC-MOSFETs leads to somechallenging problems such as the complexity of thecircuit wiring patterns, the mismatches of the circuit
stray components, and the current imbalance
betweentheparallel-connected
devices.
Therefore, countermeasures against these
problems are necessary, and will be considered as
the future work.

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MOSFET (SCT3080KL). [Online]. Available:
https://www.rohm.co.jp/datasheet/SCT3080KL/sct
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Japan: Application Note on MOSFET Gate Drive
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MOSFET (SCT3160KL). [Online]. Available:
https://www.rohm.co.jp/datasheet/SCT3160KL/sct
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