Minimization of Interconnected Inductor
for Single-Phase Inverterwith High-Performance Disturbance Observer
Satoshi Nagai, Hoai Nam Le, Tsuyoshi Nagano, Koji Orikawa, Jun-ichi Itoh
Department of Electrical, Electronics and Information Engineering
Nagaoka University of Technology
Nagaoka, Japansatoshi_nagai@stn.nagaokaut.ac.jp
Abstract— When a inductance of a single-phase gridconnected inverter is minimized, the effect of the disturbance tothe current control such as the dead-time error voltage increases.
This paper proposes a disturbance compensation method byusing a high-performance disturbance observer. In particular, inthe control system, the current controller is implemented by thedigital signal processor, whereas the high-performance
disturbance observer is implemented by the field-programmablegate array in order to suppress the disturbance at high switchingfrequency. This results in the improvement of the current control
performance. With the experimental prototype, in case of theminimized inductance (%Z = 0.5%), the total harmonic
distortion (THD) of the output current is improved from 11.1%
to 2.9% at rated load by applying the proposed disturbancecompensation method. Furthermore, with the proposed
disturbance compensation method, it is confirmed that THD of
the output current is improved by over 68% at all load range.
Keywords— grid-connected inverter; interconnected inductor;
disturbance observer; FPGAI.

INTRODUCTION

In recent years, photovoltaics systems (PV) have been
actively researched for energy saving. In general, a power
conditioning system (PCS) is used to supply power from thePV system to a single-phase grid. PCS has been actively
studied in order to reduce the cost and size [1]-[2]. In order tominimize the PCS, an interconnected inductor in the PCS isrequired to be minimized [3]-[4]. The minimization of theinductor enables the PCS not only to be applied in space-saving
applications, but also to reduce cost. The inductor can be
minimized by reducing the inductance with high switchingfrequency. By applying the next generation switching devices,e.g. SiC-MOSFET and GaN-FET, the high frequency
switching with low switching loss can be accomplished.
However, the disturbance suppression performance decreases
with the reduced inductance [5]. As a result, total harmonic
distortion (THD) of the inverter output current becomes worse
because the effect of the disturbance voltage which is causedby the disturbance sources such as the dead-time error voltage
increase.

In a conventional dead-time voltage error compensation
method, the error voltage is estimated from the inverter dc-link
voltage, the dead-time, the switching frequency and the
direction of the output current [6]. However, the conventional
method suffers many problems; the disturbance compensation
performance is limited by the delay time of a current sensor
and an A/D converter, and the voltage drop of the switching
device is also unconsidered. These problems worsen THD of
the output current when the inductance is small. Furthermore,
the error voltage by the dead-time becomes larger due toincreasing the switching frequency. Therefore, the PCS
requires an effective disturbance compensation method in orderto reduce the inductance without worsening THD of the output
current.
In order to overcome the above problem, the compensation
for the error voltage by a disturbance observer, has been
proposed in [7]-[11]. The disturbance observer compares the
feedback current and the command in order to estimate thevoltage error. Therefore, the disturbance observer is required to
be operated as high as the switching frequency because theerror voltage caused by the dead-time or the voltage drop of theswitching device occurs at the switching frequency. As a result,the cost of the control hardware becomes undesirable when the
disturbance observer is implemented with the high speed
digital signal processor (DSP).
This paper proposes the concept in which the highperformance disturbance observer is implemented by the fieldprogrammable gate array (FPGA), whereas the current
controller is implemented by the slow speed DSP. This avoids
the cost increase of the control hardware, whereas thedisturbance suppression performance is increased by operating
the disturbance observer at the switching frequency by FPGA.
This paper is organized as follows; first in section II, the designof the disturbance observer in the s-plane is introduced, and theemployment of the disturbance observer into FPGA is
explained in detail. Next, in section III and IV, the validity ofthe proposed method are confirmed by the simulations andexperiments with a 1-kW prototype. Finally, the design of the
disturbance-observer cutoff frequency is evaluated.

II. DEAD-TIME VOLTAGE ERROR COMPEMSATION USINGDISTURBANCE OBSERVER
A. Control method
Fig. 1 shows a circuit configuration of a single-phase gridconnected inverter. In this paper, an H-bridge single-phasetwo-level inverter is considered due to its simplicity. When the
inductance L is reduced in order to minimize the volume of theinterconnected inductor, the effect of the disturbance voltage
such as the dead-time error voltage increases. This worsens
THD of the output current iout.
Fig. 2 shows a control block diagram of the conventional
dead-time voltage error compensation. In the conventional
method, the error voltage from the dead-time vdead is estimatedin order to compensate for the output voltage of the inverter.
The dead-time error voltage is expressed by

Fig. 1. Single-phase inverter circuit with LC filter. In order to minimize
the interconnected inductor, the inductance L is reduced by increasing theswitching frequency.

iL*v dead = Vdc Td f sw sign(i Ldet )(1)

where, Vdc is the input DC voltage, Td is the dead-time period,
iLdet is the inductor current detection value of the inverter, fsw isthe switching frequency of the inverter, and sign(x) is a signfunction. If x > 0 then sign(x) = 1, if x < 0 then sign(x) = -1, if x
= 0 then sign(x) = 0. It is noted that the detection delay time of
the current sensor, and the drop voltage on the switching
devices are not considered in Eq.(1). These factors also become
the disturbance to the output current control. The relationshipbetween the disturbance voltage and the inductance is
explained by the transfer function from the disturbance voltage
to the output current witch is derived asiL
1s=vdis L s 2 + 2ζω n s + ω n 2(2)

where, vdis is the disturbance voltage that is sum of the error
voltages caused by the dead-time and the drop voltage of theswitching device, ζ is the damping factor, ωn is the angularfrequency of the current controller, and s is the Laplace
operator. When the inductance L becomes small, thedisturbance gain becomes higher. As a result, the accuracy ofthe voltage error compensation becomes more important when
the small interconnected inductor is applied.
Fig. 3 shows the control block diagram of the proposed
method with the disturbance observer. In order to solve theproblem in the conventional method, the disturbance observeris utilized to compensate all the disturbances accurately. As thedisturbance voltage affects the output current, the disturbancecompensate voltage v̂dis is estimated from the output current
and the voltage command,vˆdis =()

ωc*vconv + ωc LiLdet − ωc LiLdet
ωc + s(3)where, ωc is the cutoff angular frequency of the disturbanceobserver, vconv* is the output voltage of the inverter, andControl System Circuit +vdeadv
vac DSP+ vdis ac

+
-

iLdet

PI
sign

+ +

+

1

Vdc

+ V dcVdc Td fsw

e

+ -

1
sL

iL

− sTdelay

Fig. 2. Control block diagram of conventional dead-time error
compensation. In the conventional method, the error voltage from thedead-time vdead is estimated in order to compensate for the output voltageof the inverter

1
V dc

Vdc

1
sL

e

− sTdelay

Fig. 3. Control block diagram of dead-time error compensation with
disturbance observer. The disturbance observer is used to estimate all the
disturbance voltage.
− sTdelayis the delay time of the current detection and the A/D
conversion. It should be noted that the delay time of the current
detection and the A/D conversion are not used in the
disturbance estimation. In this paper, the current controller isimplemented by DSP, whereas the disturbance observer isimplemented by FPGA. This concept achives the highperformance disturbance observer for high accuracy
compensation.
e

B. Configration of the FPGA
The estimated disturbance voltage by using the disturbanceobserver in (3) is rewritten as in (4).

vˆdis = −

ωc s
ωc
*
Li Ldet +vconv
ωc + sωc + s(4)

In (4), the first term on the right side describes that theinverter output current iLdet is multiplied with the inductance Lof the interconnected inductor and then passed through a highpass filter (HPF). The second term on the right side shows thatthe voltage command vconv* is passed through a low pass filter(LPF). In the right side of (4), let the first term and the second

v̂ dis
ωc L
ωc
f so

ωc
f so

Fig. 4. Module block diagram of disturbance observer in FPGA. The disturbance observer is composed of thehigh pass filter and the low pass filter in FPGA. By implementing the disturbance observer in FPGA, thedisturbance observer can operate faster to compensate for the disturbance. This enables the interconnectedinductance is reduced without worsening THD of the output current.

term be X1, and Y1, respectively, (5) and (6) are obtained asfollows;

X 1 = ω c Li Ldet −

Y1 =

(v
s

ωc

*
conv

ωc
s

X1

(5)

)

(6)

− Y1

Applied the bilinear transformation into (5) and (6), (7) and (8)are obtained as follows;

ωc

z −1
f so
X 1 = ω c Li Ldet −X1
1 − z −1

ωc

z −1
f so
*
Y1 =
vconv − Y1
1 − z −1

(

)

(7)

(8)

where, fso is the sampling frequency of the disturbance observer.
The disturbance observer is implemented by using (7) and (8).
Fig. 4 shows the module block diagram of the disturbanceobserver that is implemented in FPGA. The disturbanceobserver is composed of the HPF and the LPF. The voltage
between both the ends of interconnected inductor is estimatedby inputting the detected current of the interconnected inductor
iLdet to the HPF. The voltage command vconv* is input to the LPF.
The disturbance estimation voltage v̂ dis is calculated bysubtracting the output of the HPF to output of the LPF.
The HPF is composed by a multiplier, an adder and a
subtractor. X2 is derived by multiplying the detected current of
the interconnected inductor iLdet and the gain ωcL. The output of

the HPF is derived by subtracting X6 to X2. X3 is one-sampling
period-delayed value of X1. X5 is one-sampling period-delayed
value from the output of the adder X4. The adding X5 to X3
realizes the integration. X6 is obtained by multiplying the
integrated value X4 to the gain ωc/fso. X6 shows the value of that
X1 is integrated in one sampling time of the disturbanceobserver 1/fso. On the other hand, the LPF is also composed bya multiplier, an adder and a subtractor. Y2 is derived bysubtracting the output of LPF Y1 to the input of LPF vconv*. Y3 isone-sampling period-delayed value of Y2. Y4 is obtained byadding Y5 to Y3. Y5 is one-sampling period-delayed value of Y4.
The output of the LPF Y1 is obtained by multiplying Y4 to thegain ωc/fso. According to the above results, the disturbance
estimation voltage v̂ dis is derived by subtracting the output of
the HPF X1 to the output of the LPF Y1.
Fig. 5 shows the timing chart of the HPF and the LPF in
FPGA controller. In the HPF, the multiplying result of X2 isoutputted with the delay of about 100 ns from the detectedcurrent of the interconnected inductor iLdet. The subtracting
result X1 is outputted after one clock. Note that, one clock
equals 25 ns. X3 is one-sampling period-delayed value of X1.
The adding result X4 is outputted after one clock, whereas themultiplying result X6 is outputted with the delay of about 100
ns from X4. On the other hand, in the LPF, the subtracting
result Y2 is outputted after one clock. Y3 is outputted with delayof one-sampling from Y2. The adding result Y4 is output after
one clock. Y5 is outputted with delay of one-sampling from Y4.
The multiplying result Y1 is outputted with delay of about 100
ns from Y4. Finally, the subtracting result v̂ dis is outputted after
one clock. According to the above timing, the disturbanceobserver is operated in FPGA.
III. SIMULATION RESULT
Table 1 shows the simulation conditions. In this simulation,
both the switching frequency fsw and the sampling frequency ofthe disturbance observer fso are 100 kHz, whereas the sampling
frequency of the current controller fsamp and the cutoff
frequency of the disturbance observer fc are 20 kHz.

80 kHz (12.5 s)
40 MHz (25 ns)
0.......

4

5

X2

X1

6

.......

500

501

X3

X4

X5

ωc

.......

505.......

1000

Clock
(40MHz)
iLdet
HPF
cL

X6

v̂ disX5
X6

f so(a) Timing chart of HPF.

v̂ disωcf so(b) Timing chart of LPF.
Fig. 5. Timing chart of FPGA controller. According to the above timing, the high-speed disturbance observer isachieved by FPGA.

TABLE. I SIMULATION CONDITION.

Fig. 6 shows the simulation result of the output current
when the conventional and proposed disturbance compensation
method are applied. From Fig. 6, it is confirmed that THD of
the output current with the conventional and proposed
disturbance compensation method are 19.7% and 3.3%,
respectively. Thus, it is confirmed that THD of the output
current is improved by 83.2% by the proposed disturbancecompensation method.
Fig. 7 shows the relationship between THD of the inverter
output current and the output power. When the detection delay
Tdelay is 3 μs, THD of the output current with the conventional
disturbance compensation method becomes worse. On theother hand, in the proposed disturbance compensation method,
because the disturbance observer can estimate all the
disturbances from the feedback output current, the disturbancedue to the detection delay is suppressed. As a result, THD of
the output current is maintained at low value even when thedetection delay is introduced to the circuit. In particular, atlight load of 0.2 p.u., THD of the output current is improved
from 47% to 12% by the proposed disturbance compensation
method. These results confirm that the proposed disturbance(a) Conventional method.
50 Output current iout[A]THD:3.3%

0-50

40[ms]
20(b) Proposed method.
Fig. 6. Output current waveform with conventional and proposed
disturbance compensation method. In the simulation result, THD of theoutput current is improved by 83.2% by the proposed disturbancecompensation method.
0

compensation method using the disturbance observer
compensates the dead-time error voltage, even when there is
the detection delay. These simulation results verify the validityof the proposed disturbance compensation.

TABLE II EXPERIMENTAL CONDITION.

0

Grid voltage 250 V/div
Fig. 7. Inverter output current THD versus Output power characteristics.
At the load range from 0.2 p.u. to 1.0 p.u., THD of the output current is
improved by the proposed disturbance compensation method.

IV. EXPERIMENTAL RESULT

Output current 5 A/div Output current THD : 11.1%

0
4 ms/div

A. Evaluation of inverter output current THD
Table 2 shows the experimental conditions. Similarly, inthe experiment, THD of the output current is compared when
the conventional and proposed disturbance compensation
method is applied.
Fig. 8 depicts the experimental result of the output current
when the conventional and proposed disturbance compensation
method are applied. At rated load, THD of the inverter output
current is improved from 11.1% to 2.9% by applying the
proposed disturbance compensation method at the disturbanceobserver cutoff frequency of 2 kHz. A high distortion occurs at
the zero crossing of the inverter output current in theconventional disturbance compensation method. This distortion
occurs due to the detection delay of the output current polarity.
On the other hand, even when there is the detection delay, theproposed disturbance compensation method using the
disturbance observer can compensate the disturbance voltage.
As a result, the distortion due to the dead-time error is reduced
significantly. In addition, when the cutoff frequency of the
disturbance observer is higher, the effect of the proposed
disturbance compensation is larger. Because, by increasing thecutoff frequency of the disturbance, the control bandwidth ofthe disturbance observer is increased which enable tocompensate for the disturbance faster. Therefore, the current
control system achieved the high disturbance suppression
performance using the disturbance observer with the highcutoff frequency, which can be implemented simply by the
FPGA.
Fig. 9 shows the experimental result of the output current
when the conventional and proposed disturbance compensation
method are applied at light load. THD of the inverter output
current is improved from 44.0% to 14.0% by applying the
proposed disturbance compensation method. A high distortionin the waveform of the conventional method occurs. This(a) Conventional disturbance compensation method.

(b) Proposed disturbance compensation method at the disturbanceobserver cutoff frequency of 1 kHz.

0

Grid voltage 250 V/div
Output current 5 A/div

Output current THD : 2.9%

0
4 ms/div(c) Proposed disturbance compensation method at the disturbanceobserver cutoff frequency of 2 kHz.
Fig. 8. Output current waveform in conventional and proposed
disturbance compensation method at rated load of 1 kW. THD of theoutput current is improved by74.0% by using the proposed method.

50
0

Improved by 68.2%

1 p.u. = 1 kW

40

Grid voltage 250 V/div

30

Output current 2 A/div Output current THD : 44.0%

20

Conventional method

Proposed method

10

0
4 ms/div(a) Conventional disturbance compensation method.

0

Improved by 74.0%
0

0.2

0.4
0.6
Output power [p.u.]

0.8

1.0

Fig. 10. Experimental characteristic of inverter output current THD
versus output power. At the load range from 0.1 p.u. to 1.0 p.u., THD of
the output current is improved over 68.2% by using the proposed
disturbance observer.

0

Output current 2 A/div Output current THD : 16.1%

0
4 ms/div(b) Proposed disturbance compensation method at the disturbanceobserver cutoff frequency of 1 kHz.

Harmonic components on
inverter output current [A]Grid voltage 250 V/div

Fig. 11. Harmonic analysis. The high-frequency components of theinverter output current are reduced by using the disturbance observer.

(c) Proposed disturbance compensation method at the disturbanceobserver cutoff frequency of 2 kHz.
Fig. 9. Output current waveform in conventional and proposed method atlight load of 100 W. THD of the output current is improved by 68.2% byusing the proposed method.

distortion occurs because the effective value of thefundamental wave is small whereas the disturbance value suchas the dead-time voltage error remains almost constant.
Therefore, the compensation value of the conventional method
is greatly influenced by the fundamental wave at the light load.
On the other hand, the proposed disturbance compensation
method using the disturbance observer decrease greatly the
distortion of the inverter output current at the light load.
Because, the proposed method estimated the disturbancevoltage by the inverter output current.

Fig. 10 shows the relationship between THD of the inverter
output current and the output power. From Fig. 10, it isconfirmed that the proposed disturbance compensation method
reduces THD of the output current effectively compared withthat of the conventional disturbance compensation method in
the load range from 0.1 p.u. to 1.0 p.u.. In particular, byapplying the proposed disturbance compensation method, THD
of the output current is reduced by 68.2% and 74.0% at load of
0.1 p.u. and 1 p.u., respectively. These results verify thevalidity and effectiveness of the proposed disturbancecompensation method.
Fig. 11 shows the Fast Fourier Transform (FFT) analysis of
the output current at rated load. In the FFT analysis, thefrequency components from the fundamental wave of 50 Hz to20th orders of the fundamental wave are shown. In Fig. 11, thehigh frequency components of the inverter output current isreduced by using the disturbance observer. Thus, the inverteroutput-current distortion by the dead-time error voltage isreduced greatly. As a conclusion, even with the small
inductance, the low THD of the output current can still beachieved by using the proposed disturbance observer which is
implemented by FPGA.

0

Grid voltage 250 V/div
Output current 2 A/div Output current THD : 37.4%

04 ms/div(a) DOB sampling frequency of 20 kHz.

(b) DOB sampling frequency of 40 kHz.
Fig. 12. Output current waveform in proposed method by increasing
sampling frequency at rated load. When the sampling frequency of the
disturbance observer is changed from 20 kHz to 40 kHz, THD of theinverter output current is improved by 30.2%.

B. Evaluation of disturbance-observer sampling frequency
Fig. 12 shows the inverter output current waveform withdifferent disturbance-observer sampling frequencies at rated
load. Note that the cutoff frequency of the disturbance observeris 2 kHz. In Fig. 12 (a), when the sampling frequency of the
disturbance observer is 20 kHz, THD of the inverter output
current is 4.3%. In Fig. 12 (b), when the sampling frequency ofthe disturbance observer is 40 kHz, THD of the inverter output
current is 3.0%. Thus, when the sampling frequency of the
disturbance observer is changed from 20 kHz to 40 kHz, THD
of the inverter output current is improved by 30.2%. The higher
the disturbance-observer sampling frequency becomes, themore THD of the inverter output current is improved. This isbecause the disturbance observer is possible to compensate thedisturbance at high speed. As a conclusion, the high sampling
frequency of the disturbance observer is possible to increase
the disturbance suppression performance of the current control
system.
Fig. 13 shows the inverter output current waveform withdifferent disturbance-observer sampling frequencies at lightload of 0.1 p.u.. In addition, the cutoff frequency of the
disturbance observer is 2 kHz. In Fig. 13 (a), when thesampling frequency of the disturbance observer is 20 kHz,THD of the inverter output current is 37.4%. In Fig. 13 (b),when the sampling frequency of the disturbance observer is 40
kHz, THD of the inverter output current is 12.5%. Thus, when
the sampling frequency of the disturbance observer is changed(a) DOB sampling frequency of 20 kHz.

(b) DOB sampling frequency of 40 kHz.
Fig. 13. Output current waveform in proposed method by increased
sampling frequency at light load. When the sampling frequency of the
disturbance observer is changed from 20 kHz to 40 kHz, THD of theinverter output current is improved by 66.6%.

Fig. 14. Experimental characteristic of inverter output current THD
versus output power with different sampling frequency. When thesampling frequency of the disturbance observer is increased from 20 kHz
to 80 kHz, THD of the output current is reduced by 33.3% and 62.5% atload of 0.1 p.u. and 1 p.u., respectively.

from 20 kHz to 40 kHz, THD of the inverter output current is
improved by 66.6%. Therefore, it is concluded that even atlight load, THD of the inverter output current is still improved
when the sampling frequency of the disturbance observer isincreased.
Fig. 14 shows the relationship between THD of the inverter
output current and the output power, when the sampling
frequency of the disturbance observer is 80 kHz, 40 kHz and
20 kHz, respectively. From Fig. 14, it is confirmed that THD of

the inverter output current is reduced in the load range from 0.1
p.u. to 1.0 p.u. at most when the sampling frequency of the
disturbance observer is 80 kHz. As an expected result, with thehigh disturbance-observer sampling frequency, THD of theinverter output current is improved. When the sampling
frequency of the disturbance observer is increased from 20 kHz
to 80 kHz, THD of the inverter output current is improved from
4.3% to 2.9% at rated load. THD of the output current isreduced by 33.3% and 62.5% at load of 0.1 p.u. and 1 p.u..
From Fig. 8 to Fig. 14, it is confirmed that THD of theinverter output current with reducing inductance of theinterconnected inductor is improved by applying the
disturbance observer. In addition, when the disturbanceobserver with high sampling frequency and high cutoff
frequency is applied, THD of the inverter output current is
improved greatly. Therefore, in order to reduce the inductanceof the interconnected inductor, the concept where the highperformance disturbance observer is implemented by FPGA isproved to be effective.
V. CONCLUSION
In order to achieve the minimization of the interconnectedinductor, this paper proposed the dead-time voltage error
compensation with the high-performance disturbance observer
implemented by FPGA. Even when the inductance isminimized to %Z of 0.5%, the high-performance disturbanceobserver suppressed effectively all the disturbance voltage suchas the dead-time error voltage, and the drop voltage on theswitching device. In the experimental verification with a 1-kW
miniature prototype, the proposed method reduced THD of theinverter output current from 11.1% to 2.9% at the rated load. In
addition, it was confirmed that increasing sampling frequency
and cutoff frequency of the disturbance observer can further
improve THD of the inverter output current.
Future works will be confirmed the operation of the
proposed disturbance compensation at 6-kW load. In addition,
the operation of Fault-Ride-Through (FRT) is also verified
using the disturbance observer.
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