REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate to current MIL-PRF-38535 requirements. - PHN

18-04-16

Thomas M. HessB

Update boilerplate paragraphs to current VID description requirements.
- PHN

23-09-18

Muhammad A. Akbar

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

Revision Status of Sheets
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SHEET
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SHEET
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SHEET

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PMIC N/A
Original date of drawing
YY MM DD

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

PREPARED BY
Phu H. Nguyen

TITLE

CHECKED BY
Phu H. Nguyen
APPROVED BY

12-12-14

https://www.dla.mil/landandmaritime
MICROCIRCUIT, DIGITAL, MIXED SIGNALMICROCONTROLLER, MONOLITHIC SILICON

Thomas M. HessSIZE

CAGE CODE

A

REV B

16236

DWG NO.

PAGE

V62/12620

1 OF 12AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V155-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircuit,with an operating temperature range of -40ºC to +125ºC.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12620-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

MSP430G2230-EP

Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X

8

JEDEC MS-012

Plastic small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

SIZE
A

CAGE CODE
16236
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B

DWG NO.
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PAGE 2

1.3 Absolute maximum ratings.

1/

Voltage applied at VCC to VSS ............................................................................................... -0.3 V to 4.1 V
Voltage applied to any pin .................................................................................................... -0.3 V to VCC +0.3 V 2/
Diode current at any device terminal .................................................................................... ±2 mA
Storage temperature: 3/
Unprogrammed device .................................................................................................. -55°C to 150°C
Programmed device ...................................................................................................... -40°C to 150°C
1.4 Recommended operating conditions.
Supply voltage, (VCC):
During program execution ............................................................................................. 1.8 V to 3.6 V
During flash program/erase ........................................................................................... 2.2 V to 3.6 V
Supply voltage, (VSS) .......................................................................................................... 0 V
Operating free air temperature, (TA) ..................................................................................... -40°C to 125°C
Processor frequency (Maximum MCLK frequency) 4/ 5/
VCC = 1.8 V, Duty cycle = 50% ±10% ............................................................................ dc to 6 MHz
VCC = 2.7 V, Duty cycle = 50% ±10% ............................................................................ dc to 12 MHz
VCC = 3.3 V, Duty cycle = 50% ±10% ............................................................................ dc to 16 MHz
2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
J-STD-020––

Registered and Standard Outlines for Semiconductor Devices
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state
surface mount devices.
(Copies of these documents are available online at https://www.jedec.org.)__________
1/

2/
3/
4/
5/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods
may affect device reliability.
All voltage values referenced to VSS. The JTAG fuse blow voltage, VFB is allowed to exceed the absolute maximum rating.
The voltage is applied to the TEST pin when blowing the JTAG fuse..
Higher temperature may be applied during board soldering according to the current JEDEC J STD 020 specification withpeak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of
the specified maximum frequency.
Modules might have different maximum input clock specification. See the specification from the manufacturer data sheet.

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PAGE 3

3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (ifapplicable) above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics
are as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Terminal function. The terminal function shall be as shown in figure 3.

3.5.4

Functional block diagram. The functional block diagram shall be as shown in figure 4.

3.5.5

Safe operating area. The safe operating area shall be as shown in figure 5.

3.5.6

POR/Brownout Reset (BOR) vs Supply voltage. The POR/Brownout Reset (BOR) vs Supply voltage shall be as
shown in figure 6.

3.5.7

VCC(drop) level with a Square voltage drop to gernerate a POR/Brownout signal. The VCC(drop) level with a Squarevoltage drop to gernerate a POR/Brownout signal shall be as shown in figure 7.

3.5.8

VCC(drop) level with a Triangle voltage drop to gernerate a POR/Brownout signal. The VCC(drop) level with a Triangle
voltage drop to gernerate a POR/Brownout signal shall be as shown in figure 8.

3.5.9

DCO wake-up time from LPM3/4 vs DCO frequency. The DCO wake-up time from LPM3/4 vs DCO frequency
waveforms shall be as shown in figure 9.

3.5.10

USI low level output voltage vs output current. The USI low level output voltage vs output current shall be as shown infigure 10.

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PAGE 4TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions

VCC

TA

2/

Min

Active mode supply current into VCC excluding external current
fDCO = fMCLK = 1 MHz,
Active mode (AM) current
IAM, 1MHz(1 MHz)fACLK = 0 Hz,
Program executes in flash,

2.2 V

BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 0, SCG0 = 0
SCG1 = 0, OSCOOFF = 0
Low power mode Supply current (into VCC) Excluding external current
ILPM0, 1MHz fMCLK = 0 MHz,Low power mode 0(LPM0) current
fSMCLK = fCDO = 1 MHz,fACLK = 32,768 Hz,
3/BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
Low power mode 2
ILPM2
fMCLK = fSMCLK = 0 MHz,(LPM2) current
fCDO = 1 MHz,fACLK = 32,768 Hz,
4/BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
Low power mode 3(LPM3) current

ILPM3, VLO

4/

Low power mode 4(LPM4) current

ILPM4

5/

Limits

3V

390

µA

25°C

2.2 V

29

µA

46

µA

0.7

µA

9.3

µA

0.5

µA

1.5

µA

7.1

µA

2.2 V

125°C
25°C

2.2 V

85°C
2.2 V

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
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µA

65 TYPTA = 125°C
fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1

SIZE
A

µA

2.2 V

25°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1

220 TYP

25°C

125°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = from internal LF oscillator(VLO),CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0

Unit
Max

B

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PAGE 5TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolVCC

Conditions

Schmitt Trigger inputs (Port P1)
Positive going input threshold

0.45 VCC

0.75 VCC

V

1.35

2.25

V

0.25 VCC

0.55 VCC

V

3V

0.75

1.65

V

3V

0.3

1.0

V

20

50

kΩ

3V

Negative going input threshold

VIT-

voltage
Input voltage hysteresis (VIT+ - VIT-)

Vhys

Pullup/pulldown resistor

RPull

Input capacitance
Leakage current (Port P1)
High impedance leakage current
Outputs (Port P1)
High level output voltage

CI

Unit
Max

VIT+

voltage

LimitsMin

2/

For pullup: VIN = VSS
For pulldown: VIN = VCC
VIN = VSS or VCC

5 TYP

Ilkg(Px.y)

6/

VOH

I(OHmax) = -6 mA 8/

3V

VCC – 0.3

TYP

V

VOL

I(OLmax) = 6 mA 8/

3V

VSS + 0.3

TYP

V

fPx.y

CL = 20 pF, RL = 1 kΩ 9/ 10/3V

12 TYPMHz

fPort°CLK

CL = 20 pF 10/3V

16 TYPMHz

VCC(start)dVCC/dt ≤ 3 V/s

See figure 10 through figure 12

V(B_IT-)

dVCC/dt ≤ 3 V/s

See figure 10

Vhys(B_IT-)

dVCC/dt ≤ 3 V/s

See figure 10td(BOR)

34/

�����/NMI pin
Pulse length needed at RST
to accept reset internallyt(reset)34/

Low level output voltage
Output frequency (Port P1)
Port output frequency (with load)
Clock output frequency
POR/Brownout reset (BOR)
See figure 10

11/

7/

3V

pF

±120

0.7 x
V(B_IT-)

TYP

140

TYP

nA

V
1

2000
3V

2

V
mV
µs
µs

See footnote at end of table.

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PAGE 6

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Symbol

VCC

Limits

Unit

Min

Max

RSELx < 14

1.8

3.6

V

RSELx = 14

2.2

3.6

V

3V

3.0
0.096

3.6
TYP

V
MHz

2/

DCO frequency
Supply voltage

VCC

Conditions

DCO frequency (0, 0)

fDCO(0,0)

RSELx = 15
RSELx = 0, DCOx = 0, MDDx = 0

DCO frequency (0, 3)

fDCO(0,3)

RSELx = 0, DCOx = 3, MDDx = 0

3V

0.12

TYP

MHz

DCO frequency (1, 3)

fDCO(1,3)

RSELx = 1, DCOx = 3, MDDx = 0

3V

0.15

TYP

MHz

DCO frequency (2, 3)

fDCO(2,3)

RSELx = 2, DCOx = 3, MDDx = 0

3V

0.21

TYP

MHz

DCO frequency (3, 3)

fDCO(3,3)

RSELx = 3, DCOx = 3, MDDx = 0

3V

0.30

TYP

MHz

DCO frequency (4, 3)

fDCO(4,3)

RSELx = 4, DCOx = 3, MDDx = 0

3V

0.41

TYP

MHz

DCO frequency (5, 3)

fDCO(5,3)

RSELx = 5, DCOx = 3, MDDx = 0

3V

0.58

TYP

MHz

DCO frequency (6, 3)

fDCO(6,3)

RSELx = 6, DCOx = 3, MDDx = 0

3V

0.80

TYP

MHz

DCO frequency (7, 3)

fDCO(7,3)

RSELx = 7, DCOx = 3, MDDx = 0

3V

0.80

DCO frequency (8, 3)

fDCO(8,3)

RSELx = 8, DCOx = 3, MDDx = 0

3V

1.6

TYP

MHz

DCO frequency (9, 3)

fDCO(9,3)

RSELx = 9, DCOx = 3, MDDx = 0

3V

2.3

TYP

MHz

DCO frequency (10, 3)

fDCO(10,3)

RSELx = 10, DCOx = 3, MDDx = 0

3V

3.4

TYP

MHz

DCO frequency (11, 3)

fDCO(11,3)

RSELx = 11, DCOx = 3, MDDx = 0

3V

4.25

TYP

MHz

DCO frequency (12, 3)

fDCO(12,3)

RSELx = 12, DCOx = 3, MDDx = 0

3V

4.3

DCO frequency (13, 3)

fDCO(13,3)

RSELx = 13, DCOx = 3, MDDx = 0

3V

7.8

DCO frequency (14, 3)

fDCO(14,3)

RSELx = 14, DCOx = 3, MDDx = 0

3V

8.6

DCO frequency (15, 3)

fDCO(15,3)

RSELx = = 15, DCOx = 3, MDDx = 0

3V

15.25

TYP

MHz

DCO frequency (15, 7)

fDCO(15,7)

RSELx = 15, DCOx = 7, MDDx = 0

3V

21

TYP

MHz

Frequency step between range
RSEL and RSEL + 1
Frequency step between tap
DCO and DCO + 1
Duty cycle

SRESL

SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)

3V

1.35

TYP

ratio

SDCO

SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

3V

1.08

TYP

ratio

3V

50

TYP

%

1.50

7.30
TYP
13.9

MHz

MHz
MHz
MHz

See footnote at end of table.

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PAGE 7

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Conditions

VCC

TA

Unit

Min

Max

3V

-3

3

%

3V

-3

3

%

3V

-3

3

%

3V

-3

3

%

1.8 V to
3.6 V

-3

3

%

1.8 V to
3.6 V

-3

3

%

2.2 V to
3.6 V

-3

3

%

3 V to 3.6
V

-6

3

%

1.8 V to
3.6 V

-5

+5

%

1.8 V to
3.6 V

-5

+5

%

2.2 V to
3.6 V

-5

+5

%

3.0 V to
3.6 V

-6

+6

%

2/
Calibrated DCO frequencies – Tolerance over temperature -40°C to 125°C
BCSCTL1 = CALBC1_1MHz,-40°C to 125°C
1 MHz tolerance over
DCOCTL = CALDCO_1MHz,
temperature
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHz,-40°C to 125°C
8 MHz tolerance over
DCOCTL = CALDCO_8MHz,
temperature
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHz,-40°C to 125°C
12 MHz tolerance over
DCOCTL = CALDCO_12MHz,
temperature
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHz,-40°C to 125°C
16 MHz tolerance over
DCOCTL = CALDCO_16MHz,
temperature
calibrated at 30°C and 3 V
Calibrated DCO frequencies – Tolerance over supply voltage VCC
BCSCTL1 = CALBC1_1MHz,
25°C
1 MHz tolerance over VCC
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHz,
25°C
8 MHz tolerance over VCC
DCOCTL = CALDCO_8MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHz,
25°C
12 MHz tolerance over VCC
DCOCTL = CALDCO_12MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHz,
25°C
16 MHz tolerance over VCC
DCOCTL = CALDCO_16MHz,
calibrated at 30°C and 3 V
Calibrated DCO frequencies – Overall tolerance
BCSCTL1 = CALBC1_1MHz,-40°C to 85°C
1 MHz tolerance overall
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHz,-40°C to 85°C
8 MHz tolerance overall
DCOCTL = CALDCO_8MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHz,-40°C to 85°C
12 MHz tolerance overall
DCOCTL = CALDCO_12MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHz,-40°C to 85°C
16 MHz tolerance overall
DCOCTL = CALDCO_16MHz,
calibrated at 30°C and 3 V

LimitsSee footnote at end of table.

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PAGE 8TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolVCC

Conditions
2/

Wake up from Lower Power Models (LPM3/4)
DCO clock wake up time from
tDCO,LPM3/4 BCSCTL1 = CALBC1_1MHz,
LPM3/4
DCOCTL = CALDCO_1MHz,
12/BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,

CPU wake up time fromtCPU,LPM3/4
LPM3/4 13/Internal Very Low power Low frequency Oscillator (VLO)
VLO frequency
fVLO
TA = -40°C to 85°C

Limits

2.2 V/ 3 V

2 TYP

µs

1.5 TYP

µs

1 TYP

µs

1 TYP

µs

3V

1 / fMCLK +tClock,LPM3/4
3V

4

dfVLO/dT

TA = -40°C to 85°C

dfVLO/dVCC

TA = 25°C

Timer_A clock frequency

fTA

Timer_A capture timing
USI, Universal Serial Interface
USI clock frequency

fTA,cap

Loe level output voltage on
SDA and SCL

VOL,I2C

fUSI

TYP
20

µs
kHz

23

TA = 125°C
VLO frequency temperaturedrift 14/
VLO frequency supply voltage
drift 15/
Timer_A

Unit
Max

Min

Internal: SMCLK
External: TACLK, INCLK
Duty cycle = 50% ±10%TAx

3V

0.5 TYP%/°C

1.8 V to
3.6 V

4 TYP

%/V

fSYSTEM

3V

External: SCLK,
Duty cycle = 50% ±10%
SPI slave mode USI module in I2C
mode,
I(OLmax) = 1.5 mA

MHz

20fSYSTEM

3V

TYP

VSS

ns
TYP

MHz

VSS + 0.4

V

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 9TABLE I. Electrical performance characteristics - Continued. 1/
Test

Symbol10 Bit ADC, Power supply and input range conditions
Analog supply voltage
VCC
VSS = 0
Analog input voltage 17/

ADC10 supply current

18/

Reference supply current,
reference buffer disabled

VAx

IADC10

IREF+

19/
Reference buffer supply
current with ADC10SR = 0

IREFB,019/
Reference buffer supply
current with ADC10SR = 1

IREFB,119/
Input capacitance

CI

Input MUX ON resistance

RI

VCC

Conditions

All Ax terminal, Analog inputs
selected in ADC10AE register
fADC10CLK = 5.0 MHz,ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REFON = 0,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
Only one terminal Ax can beselected at one time
0 V ≤ VAX ≤ VCC

Limits

Unit

Min

Max

2.2

3.6

V

0

VCC

V

3v

0.6 TYP

mA

3V

0.25 TYP

mA

3v

0.25 TYP

mA

3V

1.1 TYP

mA

3v

0.5 TYP

mA

3V

27

pF

TYP

Ω

2/

3V

3v

1000

See footnote at end of table.

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PAGE 10

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Symbol10 bit ADC, Built in voltage reference
Positive built in reference analog

35/
VCC, REF+

2/
IVREF+ ≤ 1 mA, REF2_5V = 0
IVREF+ ≤ 1 mA, REF2_5V = 1

Positive built in reference voltage

IVREF+ ≤ IVREF+ max, REF2_5V = 0

ILD,VREF+

VREF+ load regulation

VREF+ load regulation response
time
Maximum capacitance at pin VREF+

CVREF+

Temperature coefficient

TCREF+

Setting time of internal reference
voltage to 99.9% VREF

tREFON

Setting time of reference buffer to
99.9% VREF

tREFBURST

10 Bit ADC, External reference

20/ 36/

V

3.0
3V

34/

1.59

V

2.34

2.65

V

3V

IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≠ 0.75 V,
REF2_5V = 0
IVREF+ = 500 µA ±100 µA
Analog input voltage VAx ≠ 1.25 V,
REF2_5V = 1
IVREF+ = 100 µA → 900 µA
VAx ≠ 0.5 V x VREF+,
Error conversion result ≤ 1 LSB,
ADC10SR = 0
IVREF+ ≤ 1 mA, REFON = 1, REFOUT=1
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1
mA
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1
REFBURST = 1, ADC10SR = 0

V

1.4

±1

mA
LSB

±2
3V
LSB
±2
ns
3V

400

3V

100

pF

3V

±190

3.6 V

30

ppm/°
C
µs

3V

2

µs

1.4

VCC

V

1.4

3

V

VEREF-VEREF+ > VEREF-,
SREF1 = 1, SREF0 = 0
VEREF- ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1
22/
VEREF+ > VEREF-

0

1.2

V

ΔVEREFVEREF+ > VEREF- 24/

1.4

VCC

V

Positive external reference input
voltage range 21/

VEREF+

Negative external reference input
voltage range 23/
Differential external reference input
voltage range,
ΔVEREF = VEREF+ - VEREFStatic input current into VEREF+

IVEREF+

Static input current into VEREF-

Unit
Max

2.2

IVREF+ ≤ IVREF+ max, REF2_5V = 1
Maximum VREF+ load current

LimitsMin

supply voltage range
VREF+

VCC

Conditions

IVEREF-

0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 0
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1
22/
0 V ≤ VEREF- ≤ VCC

3V±1 TYP

µA

3V

0 TYP

µA

3V

±1 TYPµA

See footnote at end of table.

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PAGE 11TABLE I. Electrical performance characteristics - Continued. 1/
Test
10 Bit ADC, Timing parameters
ADC10 input clock frequency

Symbol36/
fADC10CLKADC10 built in oscillator
frequency

fADC10OSC

Conversion timetCONVERT

Turn on setting time of the ADC
tADC10ON
10 Bit ADC, Linearity parameters
36/
Integral linearity error
EI
Differential linearity error

ED

Offset error

EO

Gain error

EG

For specified

ADC10SR = 0

performance of ADC10
linearity parameters

ADC10SR = 1

ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
fADC10CLK from ACLK, MCLK, or SMCLK:ADC10SSELx ≠ 0
25/

Source impedance RS < 100 Ω

ISENSORTCSENSOR

Sample time required if channel
10 is selected 28/
Current into divider at channel 11
VCC divider at channel 11
Sample time required if channel
11 is selected 30/
RAM
RAM retention supply voltage 31/

36/

REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1 INCHx = 0Ah

Limits

Unit

Min

Max

0.45

6.3

MHz

0.45

1.5

MHz

3V

3.7

6.3

MHz

3V

2.06

3.51

µs

13 x ADC 10DIV x
1/fADC10CLK
100

µs

2/

Total unadjusted error
ET
10 Bit ADC, Temperature sensor and built in VMID
Temperature sensor supply
current 26/

VCC

Conditions

3V

3V

±1

LSB

3V

±1

LSB

3V

±1

LSB

3V

±2

LSB

3V

±5

LSB

3V

60 TYP

µA
mV/°C
µs

27/

3V

3.55 TYP

tSensor(sample) ADC10ON = 1 INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
ADC10ON = 1 INCHx = 0Bh

3V

30

VMID
tVMID(sample)

V(RAMh)

ADC10ON = 1 INCHx = 0Bh,
VMID ≠ 0.5 x VCC
ADC10ON = 1 INCHx = 0Bh,
Error of conversion result ≤ 1 LSB

3V

29/

µA

3V

1.5 TYPV

3V

CPU halted

ns

1220

ns

1.6

V

See footnote at end of table.

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PAGE 12TABLE I. Electrical performance characteristics - Continued. 1/
Test
Spy-Bi-Wire interface
Spy-Bi-Wire input frequency

2/
3/
4/
5/
6/
7/
8/
9/
10/
11/
12/
13/
14/
15/
16/

fSBW
tSBW,Low

Spy-Bi-Wireenable time
(Test high to acceptance of first clock edge
32/)
Spy-Bi-Wire return to normal operation time

tSBW,En

Voltage level on TEST for fuse blow

VCC

Conditions

TA = -40°C to 105°C

tSBW,RetRInternal

TA = -40°C to 105°C

Limits

Unit

Min

Max

2.2 V/3 V

020

2.2 V/3 V

0.025

15

µs

1

µs

2/

Spy-Bi-Wire low clock pulse lengthInternal pulldown resistance on TESTJTAG fuse 33/ 37/
Supply voltage during fuse blow condition

1/

Symbol

2.2 V/3 V

MHz

2.2 V/3 V

15

100

µs

2.2 V/3 V

25

90

kΩ

VCC(FB)

2.5

VFB

6

V
7

V

Supply current into TEST during fuse blow

IFB

100

mA

Time to blow fuse

tFB

1

ms

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured bycharacterization and/or design.
Over recommended operating free air temperature range (unless otherwise noted). All inputs are tied to 0 V or to VCC.
Outputs do not source or sink any current.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor
is disabled.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum
voltage drop specified.
A resistive divider with two 0.5 kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of
the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT-) + Vhys(B_IT-) is ≤ 1.8 V.
The DCO clock wake up time is measured from the edge of an external wake up signal (for example, port interrupt) to the firstclock edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Calculated using the box method: (MAX(-40°C to 85°C) - MIN(-40°C to 85°C)) / MIN(-40°C to 85°C) / (85°C – (-40°C)).
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / Min(1.8 to 3.6 V) / (3.6 V – 1.8 V).
The leakage current is defined in the leakage current table with Px.y/Ax parameter.

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PAGE 13TABLE I. Electrical performance characteristics - Continued. 1/
17/
18/
19/
20/
21/
22/
23/
24/
25/
26/
27/
28/
29/
30/
31/
32/
33/
34/
35/
36/
37/

The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion result.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied by terminal VCC. Consumption is independent of the ADC10ON control bit, unless aconversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, isalso the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should
follow the recommendations on analog source impedance to allow the charge to settle for 10 bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with
reduced accuracy requirements.
Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference
buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be
applied with reduced accuracy requirements.
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are
already settled.
The sensor current ISENSOR is consuimed if (ADC10ON = 1 and REFON = 1) or (ADC10ON =1 and INCH = 0Ah and sample
signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of thetemperature sensor input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor, typ = TCSensor (273 + T[°C] + VOffset,sensor[mV] or
VSensor, typ = TCSensor T[°C] + VSensor(TA = 0°C)[mV].
The typical equivalent is impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution
should happen during this supply voltage condition.
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin highbefore applying the first SBWCLK clock edge.
Once the fuse is blown, no further access to the JATG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is
switched to bypass mode.
Minimum and maximum parameters are characterized up to TA = 105°C unless otherwise noted.
Over recommended operating free air temperature range unless otherwise noted.
Over recommended ranges of supply voltage and up to operating free air temperature TA = 105°C (unless otherwise noted).
TA = 25°C, over recommended ranges of supply voltage (unless otherwise noted).

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PAGE 14Case Xeb

8.010(0.25)

M

5
E

1

E1

4

PIN 1
INDEX AREADSEE
DETAIL A
A1

A

c

0°-8°

.004(0.10)

GAGE
PLANE

SEATING PLANE.010(0.25)

L
DETAIL A

SymbolA
A1bc
D

Inch es
Min
Max
.004
.012
.005
.189

.069
.010
.020
.010
.197

Dimensions

Millim eters
Min
Max
0.10
0.31
0.13
4.80

1.75
0.25
0.51
0.25
5.00

SymbolInch esMin
Max

Millim eters
Min
Max

E
E1
e
L

.150
.157
.228
.244
.050 BSC
.016
.050

3.80
4.00
5.80
6.20
1.27 BSC
0.40
1.27

NOTES:
1. All linear dimensions are in inches (millimeters).
2. This drawing is subject to change without notice.
3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 (0.15) each side.
4. Body width does not include interlead flash. Interlead flash shall not exceed .017 (0.43) each side.
5. Reference JEDEC MS-012.
FIGURE 1. Case outline.

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PAGE 15

Terminal
numberTerminal symbol

Terminal
numberTerminal symbol

1
2
3
4

DVCC
P1.2/TA0.1/A2
P1.5/TA0.0/A5/SCLK
P1.6/TA0.1/A6/SDO/SCL

5
6
7
8

DVSS
TEST/SBWTCK�����/NMI/SBWTDIO
RST
P1.7/A7/SDI/SDA

FIGURE 2. Terminal connections.

Term inal
Name
P1.2/
TA0.1/
A2
P1.5/
TA0.0/
A5/
SCLK
P1.6/
TA0.1/
A6/
SDO/
SCL
P1.7/
A7/
SDI/
SDA
�����
RST/
NMI/
SBWTDIOTEST/SBWTCK
DVCC
DVSS

I/O

Description

No.
2

I/O

3

I/O

4

I/O

5

I/O

6

I

7

I

1
8

General purpose digital I/O pin
Timer_A, capture: CCI1A input, compare Out1 output
ADC10 analog input A2General purpose digital I/O pin
Timer_A, compare Out0 output
ADC10 analog input A5
USI: clock input in I2C mode; clock input/output in SPI mode
General purpose digital I/O pin
Timer_A, capture: CCI1B input, compare Out1 output
ADC10 analog input A6
USI: Data output in SPI mode
USI: I2C clock in I2C mode
General purpose digital I/O pin
ADC10 analog input A7
USI: Data output in SPI mode
USI: Data input in I2C mode
Reset imput
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Select test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test.
Digital supply voltage
Digital ground reference

The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented but not available on the device pinout. To avoid floating
inputs, these digital I/Os should be properly configured. The pullup or pulldown resistors of the unbounded P1.x GPIOs should
be enabled, and the VLO should be selected as the ACLK source. (See manufacturer for more information).

FIGURE 3. Terminal function.

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PAGE 16

XIN

VCC

VSS

FLASH

RAM

2 kB

128 B

P1.2,P1.5,
P1.8,P1.7

XOUT

BASIC CLOCKSYSTEM+ADC

PORT P1

10-BIT
4 CHANNEL
AUTOSCAN
1 ch DMA

4 I/O
INTERRUPTCAPABILITY
PULL-UP/DOWNRESISTORS

ACLK
SMCLK

MCLK

16 MHzCPU
INCL 16REGISTERS

MAB

MDB

EMULATION
(2BP)

JTAG
INTERFACE

WATCHDOGWDT+
BROWNOUTPROTECTION

15/16-BIT

SPY-BI WIRETIMER_A2

USI

2 CC
REGISTERSUNIVERSALSERIAL
INTERFACE
SPI,I2C

RST/NMIFIGURE 4. Functional block diagram.

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PAGE 17

LEGEND:SYSTEM FREQUENCY-MHz

16 MHz

SUPPLY VOLTAGE RANGE,DURING FLASH MEMORYPROGRAMMING

12 MHz

SUPPLY VOLTAGE RANGE,DURING PROGRAM EXECUTION

6 MHz

1.8 V

2.2 V

2.7 V

3.3 V

3.6 V

SUPPLY VOLTAGE-V

NOTE:
1. Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of
2.2 V.
FIGURE 5. Safe operating area.

VCC
Vhys(B_IT-)

V(B_IT-)
VCC(START)

10td(BOR)

FIGURE 6. POR/Brownout Reset (BOR) vs Supply voltage.

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PAGE 18

V
2

t

CC

PW

3V
V

CC

=3 V

TYPICAL CONDITIONS

-V

1.5

V CC(drop)

1V

CC(drop)

.5

0
.001

1

1000
1 ns

tpw -PULSE WIDTH-

1 nss
tpw -PULSE WIDTH-s

FIGURE 7. VCC(drop) level with a Square voltage drop to generate a POR/Brownout signal.

V
2

t

CC

PW

3V
V

CC

=3 V

TYPICAL CONDITIONSV CC(drop)

-V

1.5

1
V

CC(drop)

.5

t
f

=t
r

0
.001

1
tpw -PULSE WIDTH-

1000

t
f

t
r

s
tpw -PULSE WIDTH-s

FIGURE 8. VCC(drop) level with a Triangle voltage drop to generate a POR/Brownout signal.

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PAGE 19

DCO WAKE TIME-us

10.00

1.00

RSELx=0...11

.10
.10

RSELx=12...15

1.00

10.00

DCO FREQUENCY-MHz

FIGURE 9. DCO wake-up time from LPM3/4 vs DCO frequency.

5.0

5.0

VCC =3 V

TA =25° C

4.0

3.0
TA =85° C
2.0

1.0

0.0
0.0

0.2

0.4

0.6

0.8

TA =25° C

4.0

I OL -LOW-LEVEL OUTPUT VOLTAGE-mA

I OL -LOW-LEVEL OUTPUT VOLTAGE-mA

VCC =2.2 V

3.0

TA =85° C

2.0

1.0

0.0
0.0

1.0

0.2

0.4

0.6

0.8

V -LOW-LEVEL OUTPUT VOLTAGE-V
OL

V -LOW-LEVEL OUTPUT VOLTAGE-V
OL

FIGURE 10. USI low level output voltage vs output current.

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PAGE 20

1.0

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard
commercial practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data
book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes areprovided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as aguarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online
database of all current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Top sidemarking

Transport
media

Vendor part number

V62/12620-01XE

01295

G230EP

Tape and real

MSP430G2230QDREP

Tube

MSP430G2230QREP

1/ The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
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PAGE 21