ZVRT Capability of Minimized-LCL-filter-basedSingle-phase Grid-tied Inverter with High-speed
Gate-block
Satoshi Nagai, Keisuke Kusaka, Jun-ichi Itoh
Nagaoka University of Technology
Department of Energy and Environment Science Engineering
Nagaoka, Niigata, Japansatoshi_nagai@stn.nagaokaut.ac.jp, kusaka@vos.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
Abstract— This paper proposes a Zero-Voltage Ride-Through(ZVRT) method and an LCL filter optimization design method tomeet the Fault Ride Through (FRT) requirements for a singlephase grid-tied inverter with a minimized LCL filter. The inverter
output current overshoots at a voltage sag when the small LCL
filter is used. As a proposed method in this paper, the inverter
output current overshoot is suppressed with the high-speed gateblock at the grid voltage drop and recovery. In order to suppress
the overshoot current which is faster than switching period, thispaper clarifies the design method of the minimized LCL filter tomeet the FRT requirements. In particular, the designed LCL filter
results that the interconnected inductor impedance is 1.0% of theinverter normalized impedance, whereas the filter inductor is %Z= 0.78%. Moreover, the inverter output current overshoot rate issuppressed to 37.2% by the high-speed gate-block and thedesigned LCL filter. Therefore, it is possible to meet the FRT
requirements with the proposed ZVRT method and the designed
LCL filter.
Keywords—grid-tied inverter; FRT capability; minimized LCL
filter; high-speed gate-blockI.

INTRODUCTION

In recent years, photovoltaic systems (PV) have been
actively studied for energy saving [1]-[3]. The PV system isapplied with a grid-tied inverter in order to convert from DC
power source to AC power. The inverter is required to have asmall volume [4]-[5]. In particular, the interconnected inductor
occupies a majority of the inverter size. Therefore, theinterconnected inductor is highly required to reduce the size.
Conventionally, an LC filter is employed due to its simplicity.
The size of inductor is reduced by high switching frequency with
SiC and GaN devices from the view point of the reduction of thecurrent ripple. The filter capacitor is designed from the cutoff
frequency of the inverter side LC filter. However, in order toeffectively reduce the current ripple components of the inverter
output current with an extremely minimized filter, the grid-side
inductor is employed to form the LCL filter which has a highattenuation rate [6]-[7].
The grid-tied inverter is required to meet the Fault Ride
Through (FRT) requirements, in order to continue the operationof the inverter during the voltage sag [8]-[13]. Moreover, it isnecessary to suppress the inverter output current overshoot rate
to less than 50% of the rated output current peak. Generally, an

inductance of interconnected inductor is necessary to be
designed in order to meet the FRT requirements. For instance,
the interconnected inductor impedance is 2.1% of the inverter
normalized impedance in order to carry out the FRT in [8]. Thisis because the reduction of the inductance for the interconnectedinductor causes the decrease of the disturbance suppression
performance. Furthermore, when the interconnected-inductor
value is small, the inverter output current overshoot increases
during the voltage sag. When the disturbance effects becomelarge in the short grid failure, the Zero-Voltage Ride-Trough(ZVRT) operation and the reduction of the inverter output
current overshoot are difficult to achieve in the small inductor
because the inverter output current overshoot becomes high.
In [14], the ZVRT operation with the minimized
interconnected inductor constructed by LC filter is developed byauthors. In order to meet the FRT requirements, the grid-tied
inverter is applied the momentary high-speed gate-block method.
The gate-block operation is carried out when the inverter output
current reaches the current threshold. By applying this method,
the inverter output current overshoot rate is reduced to less than
50%. Thus, the grid-tied inverter with the minimized
interconnected inductor meets the FRT requirements. However,when the LCL filter is applied as output filter or considering grid
inductance with the LC filter, resonance occurs in the grid-side
LC filter because of a voltage fluctuation. Thus, the inverter
output current overshoot that is the sum of the resonance current
and the steady-state current occurs in the LCL filter during thevoltage sag. Therefore, in order to meet the FRT requirements,
the ZVRT operation method and the LCL filter design methodby considering the resonance current in the grid-side LC filter
and the steady-state current are necessary.
In this paper, the ZVRT operation method meeting FRT
requirements is proposed with a high-speed gate-block and thedesign method of the LCL filter. When the grid voltage
fluctuation such as voltage drop and voltage recovery is detected,
the gate-block operation is carried out. Thus, by using the
proposed method, the grid-tied inverter with the minimized LCL
filter is possible to continue the operation without disconnectingfrom the grid. In addition, in order to meet the FRT requirements,
it is necessary to optimally design the LCL filter. The LCL filter
is designed by deriving the equation of the inverter output
current at the grid voltage recovery with the gate-block. Thisensures that the inverter output current overshoot rate which
includes the resonance current of the grid-side LC filter is lessthan 50% of the rated output current peak at the voltage recovery.
The ZVRT operation meeting FRT requirements isdemonstrated with a 1-kW prototype.
II.

Figure 3 shows the control block diagram of theconventional FRT operation where Vdc is the input DC voltage,
Td is the dead-time period, iL1det is the inductor current detection
value, fsw is the switching frequency and Tdelay is the delay timeof the inductor current detection. The current controller isimplemented by digital signal processor (DSP). Moreover, adead-time error voltage of the inverter output is compensated byusing the dead-time error voltage compensation at a steady-state
operation. When the inductance of the interconnected inductor
becomes low, the grid current is distorted by the grid disturbancedue to the increasing disturbance gain. Therefore, the inverter
output current overshoot is caused due to the use of theconventional FRT method at the voltage sag.
Figure 4 shows the control block diagram of theconventional FRT operation with a disturbance observer [15][21]. The disturbance observer is implemented by digital
hardware in field-programmable gate array (FPGA). Thus, thedisturbances such as dead time error voltage and voltage drop ofswitching devices are compensated at high speed. The
disturbance voltage v̂dis is estimated from the output current andthe voltage command as

c
s L
*
vL  c 1 iL1det c  sc  swhere ωc is the cutoff angular frequency of the disturbanceobserver, vconv* is the inverter output voltage command and s is
the Laplace operator. Moreover, the current controller is addedwith the detected voltage of the filter capacitor vcdet for a voltagefeedforward compensation. Consequently, the dead-time
voltage error is compensated by the disturbance observer,

iL2

L1
Vdc

vconv
S2

Figure 2 shows a reactive current control method for an FRToperation. The phase  is locked by phase-locked-loop (PLL)
based on the grid voltage detection value vacdet. During thevoltage sag, the detection signal vfrt becomes one, and the current
phase ' is the sum of the present voltage phase  and /2. The
reactive current control is achieved by generating a current
command value with the current phase '.

vˆdis S3
iL1

ZERO-VOLTAGE RIDE-THROUGH METHOD FORMINIMIZED LCL FILTER

A. Conventional FRT Method
Figure 1 shows a circuit configuration of a single-phase gridtied inverter with an LCL filter. In this paper, an H-bridge singlephase two-level inverter is employed due to its simplicity. In
order to minimize the LCL filter, the inductance and capacitance
are reduced by increasing the switching frequency of the inverter.
Due to the reduction of the inductance in the LCL filter, theinverter output current overshoots at the grid voltage drop andthe grid voltage recovery. Consequently, the grid-tied inverter is
stopped by the over current protection, and cannot continue theoperation with the reduced inductance.



S1

Rf
vc

L2
vac

Cf

S4

Fig. 1. Single phase inverter circuit with LCL filter. The interconnectedinductor L1 and the filter inductor L2 are reduced by increasing theswitching frequency.
DSP
vacdet
0


2

PLL
MUX

θ

FRT

vfrt

MUX
Normaloperation
0

θfrt

0

 2

θ'

+ +

θfrt

vfrt

1

Fig. 2. Reactive current control method for FRT operation. Whenvoltage sag occurs, the phase ' is advanced by /2 from .
FRT Control

Controller
vcdet

DSP

sin(θ' )+-PI

iL1det

sign

iL1*

+ +

+

Main circuit
+ v
vdead
+ vdis c

1

Vdc+ V dcVdc Td fsw

e

+ -

1
sL1

iL1

 sTdelay

Fig. 3. Control block diagram of conventional FRT operation. In theconventional method, the current controller is implemented by DSP.
Controller

FRT Control

DSP FPGA vcdet

sin(θ' )

iL1*

+
-

iL1det

PI

vL*

c
s c

+ +
+
+ -

vconv* 1V dcsc L1s  cMain circuit
+ v
vdead
+ vdis ac
Vdc +

1
sL1

e

iL1
 sTdelay

iL1detFig. 4. Control block diagram of conventional FRT operation with
disturbance observer. In this method, the disturbance observer isimplemented by FPGA in order to compensate wideband
disturbances.

whereas the grid voltage is compensated by the voltage
feedforward. However, when the short grid failure occurs, thedisturbance compensation with the voltage feedforward and the
disturbance observer cannot detect the grid failure immediately
due to the delay time of the detection and the sampling. Thus,
the inverter output current overshoot rate becomes higher than
50% with the minimized LCL filter. Therefore, the high-speed
control is necessary in order to suppress the overshoot of theinverter output current iL2 during the voltage sag.
B. Proposed ZVRT Method
Figure 5 shows the control block diagram of the high-speed
gate-block with the disturbance observer for the ZVRT
operation. In order to suppress the inverter output current
overshoot, a gate-block is carried out by the detection of the gridvoltage fluctuation. By filtering the grid voltage by a high-pass-filter (HPF), the gate-block operation is carried out when the
HPF output gets over the threshold Vac_GB. Furthermore, in orderto achieve the ZVRT operation at high speed response, the gateblock control is implemented by digital hardware in FPGA,
whereas the HPF and the detection circuit are constructed byanalog circuit. Therefore, the detection delay time until the gateblock operation is minimized, i.e. one of the main factors to
reduce the overshoot.
III.

Figure 7 shows the circuit model with the LCL filter after thegate-block (t ≧ tbd) in the area (ii) of Fig. 6. The equation of theinverter output current during the transient interval is derived byconsidering the LCL filter circuit from the viewpoints of theinverter and the grid separately. After the gate-block, the inverter
output voltage Vconv is applied to the inverter-side LC filter inorder to inject the current of the reverse vector to the inverter
output current. The inverter output voltage is equal to the input
DC voltage Vdc. When considering the inverter output side, therated inverter output current peak –IL2 flows until the gate-blockis carried out. Thus, the positive inverter output voltage Vconv isapplied after the gate-block in order to flow the current with thepositive direction. In Fig. 7, the circuit equations are derived asshown in (2)-(4)sin(θ' )Vconv stbdVe
 sL1I L1 (s)  sL2 I L 2 (s)  ac ss
I Cf ( s )



Vac

s



I L1 (s)  I L 2 (s)  ICf (s) 



sC f

 sL2 I L 2 ( s ) 

HPF-Vac_GB

FPGA
vcdet

iL1*

Vac_GB

*

+

PI

-

vL + + 1+ Vdc

ciL1dets c +-

Figure 6 shows the transient phenomenon of the inverter
output current with the LCL filter at the grid voltage recovery.
Area (i) of Fig. 6 shows the time from the voltage recovery towhen the gate-block is carried out (0 ≦ t ≦ tbd). Area (ii) shows
the time after the gate-block operation (t ≧ tbd). Note that tbd isthe delay time from the voltage sag to when the gate-block iscarried out. In the area (i), the delay time tbd is the sum of thedelay time of the gate-block such as the detection delay time of
the analog circuit and the control delay time of the gate-block
operation in the FPGA. The inverter-output-current maximum
value iL2_max and the time reaching the maximum current timax are
calculated in area (ii). In addition, the LCL filter is designed inorder that the inverter output current maximum value is less than
the inverter output current overshoot rate of 50% ith according to
the FRT requirements.



DSP

OPTIMIZED DESIGN FOR MINIMIZING LCL FILTER

A. Derivation of Output Current at Grid Voltage Recovery
When a grid voltage sag occurs, a resonance occurs in thegrid-side LC filter. The inverter output current overshoots due tothe combination of the resonance current and the steady-state
current. The gate-block operation in H-bridge inverter is
impossible to suppress resonances in the grid-side LC filter.
Thus, it is necessary to design the parameters of the LCL filter
with the grid-side LC filter resonance in order to meet the FRT
requirements. The equation of the inverter output current at thevoltage recovery is derived in order to design the LCL filter.

vacdet

OC_L

+
-

TRIP_

+
-

S1

Detection board
S2

+
-

v̂dis

-1

sc L1s  c

S3

+
-

S4

CarrieriL1det e sTdelay

iL1

Fig. 5. Control block diagram of ZVRT operation with gate-block. By
using gate-block, the inverter output current overshoot is suppressedat the grid voltage drop and the grid voltage recovery.
Grid voltage vac
Gridvoltagepeak Vac0

Voltagerecoverytime

0sGate-block

Inverter output
Current iL2

(i)
0

(ii)
time

tbd

Rated
current
peak -IL2iL2_maxith

Gate-block signal
H
L

time

Fig. 6. Transient phenomenon of inverter output current iL2 with LCL
filter during voltage recovery. The LCL filter has to be designed inorder that the maximum current iL2_max is less than the limitation ithof the current overshoot according to FRT requirements.

iL1
Vconvu(t - tbd)

L1
Cf

iL2
iCf

L2
Vacu(t)Fig. 7. Circuit model with LCL filter after gate-block. The transientphenomenon of Inverter output voltage and grid voltage areconsidered.

where IL1(s) is Laplace transform of the interconnected inductor
current iL1, IL2 (s) is Laplace transform of the filter inductor
current iL2, Icf (s) is Laplace transform of the filter capacitor
current icf, and Vac is the grid voltage peak. By using (2)-(4) andthe rated inverter output current peak IL2, the filter inductor
current iL2 is expressed as

iL 2   I L 2 

START

Vconv (t  tbd )  Vac t
L1  L2 L L 
L1C f L2  L1
1
2 
t 
 Vac sin L1  L2  L2
L
C
L
1 f 2 
 L L2
 Vconv sin  1t  tbd  L1C f L2








1
L1  L2

Decision of grid voltage vac, switching frequency fsw,
gate-block delay time tbd, DC-link voltage Vdc,
inverter output power Pout and inverter output
current overshoot rate of 50% ithCalculation of inductance for interconnectedinductor L1 by output current ripple rate (8) or %Z of
output impedance (9)Calculation of capacitance for filter capacitor Cf by
cutoff frequency of inverter side LC filter (10)In order to design the LCL filter meeting FRT requirements, theperiod until the inverter output current reaches maximum
entitled timax as shown in Fig. 6 is derived as follows. First,
considering (6) as the filter inductor resonance voltage
component vL2_res(t),LvL 2 _ res (t )  1 Vac sin L2 Vconv sin L1  L2 t
L1C f L2 
L1  L2
t  tbd 
L1C f L2


Calculation of time reaching maximum inverter
output current timax (7)Derivation of maximum inverter output current
iL2_max by substituting timax to t in (5)Set filter-inductor value L2 to zeroIncrease L2
iL2_max = ithti max 

L2 < L1

NO

YES
END

tbd
 L1 Vac


 1
L
V
 2 conv
Fig. 8. Flowchart of LCL filter optimized design for grid-tied inverter.
The LCL filter is designed to meet FRT requirements.

2
 L1 Vac 2 L C L 2 L C V  L V
2  1 1 f 2  1 f ac   1 ac tbd
L1  L2 Vconv  L2 Vconv
 L2 Vconv
 L1  L2

 L1 Vac 1 L2 Vconv








where the approximation of sin( x)  x  x3 / 6 is applied to (6)in order to derive (7). By substituting timax in (7) to t in (5), themaximum inverter output current after the gate-block iL2_max isderived.
B. Flowchart of LCL filter design
Figure 8 shows the flowchart of the LCL filter design method.
First, the inverter side LC filter is designed from thespecification of the inverter. For example, the interconnectedinductor L1 is designed from the current ripple, the switchingfrequency or %Z for the output impedance of the inverter. The
inductance of the interconnected inductor L1 is derived as shownin (8) or (9)


NO

YES

When the differentiate equation for (6) becomes zero, the timereaching the maximum inverter output current timax is derived as

L1 

Vac Vdc  VacI L1 f sw Vdc





L1 

2f grid Pout
% Z L1 vac 2





where IL1 is the current ripple of the interconnectedinductor, %ZL1 is %Z of the interconnected inductor, fgrid isfrequency of the grid, vac is rms value of the grid voltage and Poutis inverter output power. The filter capacitor Cf is determinedfrom the cutoff frequency of the inverter-side LC filter fLC_cut.
The filter capacitor Cf is expressed as


Cf 

2f

1

L
2

LC _ cut

1

After that, the filter inductor L2 is determined to meet the FRT
requirements according to (5) and (7). When determining thefilter inductor, if the interconnected inductor L1 is less than thefilter inductor L2, the inverter side LC filter should be redesigned.
Table I shows the calculation result of the LCL filter design
based on the flowchart of Fig. 8. The interconnected inductor
impedance is 1.0% of the inverter normalized impedance,
whereas the filter inductor is 0.78%. The filter capacitor isdetermined to let the cutoff frequency of inverter side LC filterbe 10 kHz (one eighth of switching frequency). In the calculation
result with the designed LCL filter, the output current overshootrate is suppressed less than 50%. Moreover, in order to reduce
the resonance current in the LCL filter, a damping resistor Rf isINITIAL CONDITION AND CALCULATION RESULT OF LCLFILTER DESIGN.

Inverter output current iL2 [A]-400 I L 2  1.5

1.29 mH
0.2 mF0.99 mH-10.3 A
(45.2%)

Filter capacitor Cf 0.25

0.40

0

2.00
4.00
6.00
8.00
Delay time for gate-block operation [ms]

0.20
0.15
0.10
10.0

Fig. 9. Relationship between delay time of gate-block operation anddesign parameters of minimized LCL filter in 1-kW system. The
LCL filter parameter is designed in order that the inverter output
current overshoot rate is 50%.

connected to the filter capacitor in series. The resistance of thedamping resistor is selected in order to consume below 0.1% of
the inverter output power. Therefore, the voltage drop of thedamping resistor is ignored.
Figure 9 shows the characteristics of the delay time for thegate-block operation and the minimized LCL filter parameter
when the maximum inverter output current overshoot rate is
50%. In this design, the LCL filter is designed as follows; thecutoff frequency of the inverter side LC filter is 10 kHz, thecutoff frequency of the grid-side LC filter is 12 kHz, and the
maximum inverter output current overshoot rate becomes 50%
at the voltage recovery. In Fig. 9, when the delay time for thegate-block operation is short, the interconnected inductor and thefilter inductor are possible to minimize. This is because when
the delay time for the gate-block operation is short, the effect of
the inverter output current overshoot caused by the short grid
failure is small. On the other words, the interconnected-inductor
value and the filter-inductor value are limited by the delay time
for gate-block operation.

Grid Voltage vac [V]1.00

Filter Inductor L2

10
5
0
-5
-10
10 ms/div

-15

400
200
0

-200
15

Inverter output
current iL2 [A]

0.30

10

9.9 A (40.3%)

5
0200 ms/div-5(b) Voltage drop operation.

Grid Voltage vac [V]

1.20

0.60

15

(a) Waveform of ZVRT operation.
0.35

Interconnected Inductor L1

0

-200

1.40

0.80

200

400
200
0
-200
5

Inverter output
current iL2 [A]%Z of inductor L1 and L2 [%]Calculation result
Interconnected inductor L1
Filter capacitor Cf
Filter inductor L2
Maximum inverter output current
at recovery voltage iL2_max

283 V
380 V
1 kW
7.07 A
380 V
80 kHz3.0 ms%Y of capacitor Cf [%]Initial condition
Grid voltage Vac
DC-link voltage Vdc
Output power Pout
Rated inverter output current IL2
Inverter output voltage Vinv
Switching frequency fsw
Gate-block delay time tbd
Inverter output current limit
by FRT requirement ith

Grid Voltage vac [V]400
TABLE I.

0
-5

-10
-15

10.2 A (44.2%)

200 ms/div(c) Voltage recovery operation.
Fig. 10. Simulation result of grid failure with minimized LCL filter byusing proposed design method. The inverter output current
overshoot rate is suppressed to become less than 50%.

C. Simulation of ZVRT with designed LCL filter
In order to confirm validity of the designed LCL filter inTable I, the ZVRT operation with the designed LCL filter isevaluated in simulation. Figure 10 shows the simulation resultsof the ZVRT with the proposed high-speed gate-block method.

S1

Vdc

S3

vconv
S2

TABLE II.
iL1

iL2

L1

L2

Rf
vc

Output power Pout 1 kW
DC link vol. Vdc 380 V

Lg
vacdetEXPERIMENTAL CONDITION.

Filter cap.
Carrier fre.
200 Vrms Ang. fre. of ACR

Cf
fcry

n 6000 rad/s
Inter. Induc. L1 1.29 mH Samp. fre. of ACR fsamp 20 kHz(1.0%) Samp. fre. of DOB fso 80 kHz
(%Z)
2 kHz
Filter Induc. L2 0.99 mH Cutoff fre. of DOB fc(0.78%) GB delay time(%Z)
tdelay < 3 ms

vac

Grid voltage vac

Cf

S4

Output current
overshoot rate [%]Fig. 11. Circuit configuration with grid impedance Lg. In actual gridconnection, there is grid impedance between the inverter output andthe grid voltage.

50 ms/div

0

50
45
40
35
30
25
00

0.2 mF80 kHzLg : Grid inductanceL2 : Inductance of filter inductor

Grid voltage vac 250 V/div(b) Voltage drop

20

40
60
Lg / L2 [%]

80

100

Output current iL2 10 A/div
0

Fig. 12. Simulation results of inverter output current overshoot rate at
grid voltage recovery and ratio between grid inductance Lg and filter
inductance L2. When the grid impedance is low, the output current
overshoot rate becomes high.

By using the proposed high-speed gate-block method, theinverter output current is suppressed to 9.9 A at the grid voltage
drop as shown in Fig. 10 (b) (Overshoot rate: 40.3%). Moreover,at the grid voltage recovery, the inverter output current
overshoot is suppressed to 10.2 A as shown in Fig. 10 (c)(Overshoot rate: 44.2%). Thus, the grid-tied inverter with theminimized LCL filer meets the FRT requirements by using the
proposed high-speed gate-block method. Comparing the inverter
output current overshoot between the calculation value and thesimulation value at the voltage recovery, the error rate is 2.2%.
Thus, the validity of the LCL filter design method meeting the
FRT requirements is confirmed. Moreover, the error between thecalculation value and the simulation value occurs due to thedamping resistor, the precision of approximation and the steadystate current at the grid voltage recovery is constant value in thecalculation. Therefore, by using the high-speed gate-block
method and the optimized LCL filter design method, it ispossible to minimize the LCL filter and still meet the FRT
requirements.
D. Consideration of inverter output current overshoot ratewith grid impedance
Figure 11 shows the circuit diagram considering a grid
inductor connected to the LCL filter at the grid-side. The effectof the grid impedance for the FRT capability by using the
proposed high-speed gate-block method is confirmed under thecondition that there is grid impedance in the actual grid. As
shown in Fig. 11, it is impossible to directly detect the gridvoltage vac, because the detection point of the grid voltage is
between the grid inductor Lg and the filter inductor L2.
Figure 12 shows the simulation results of the relationshipbetween the inverter output current overshoot rate at the gridvoltage recovery and the ratio between grid impedance and filter(a) Waveform of ZVRT operation.
200 ms/div
Grid voltage vac
250 V/div0

Maximum current 41.2 A(483%)

Output current iL2
10 A/div0(b) Voltage drop operation.
Fig. 13. Experimental results of grid failure with conventional FRT
method. The inverter output current overshoot is large due to thedetection delay and the sampling delay at the voltage drop.

inductance Lg/L2. Note that the filter-inductor value L2 is 0.99
mH (%Z of 0.78%) which is designed in Table I. The grid
impedance Lg is changed from zero to the filter-inductor value
L2. As shown in Fig. 12, the inverter output current overshootrate is reduced by increasing the grid impedance Lg. The reason
is because the inverter output current variation is reduced byincreasing the grid impedance Lg.
IV.

EXPERIMENTAL RESULT

Table II shows the experimental condition. The LCL filter
that designed in Table I is used. Note that in the experiment, inorder to consider the worst case of the grid, the ZVRT operationis confirmed without the grid inductor.
Figure 13 shows the experimental result of the ZVRT
operation with the conventional FRT method without the highperformance disturbance observer. After the grid voltage drop,
the inverter output current overshoots to 41.2 A (Overshoot rate:

50 ms/div

Grid voltage vac 250 V/div

0

Grid voltage vac 250 V/div

50 ms/div0

Output current iL2 10 A/div

Output current iL2 10 A/div
00(b) Voltage drop(b) Voltage drop(c) Voltage recovery(a) Waveform of ZVRT operation.

(c) Voltage recovery(a) Waveform of ZVRT operation.
200 ms/div

0

200 ms/div

0

Grid voltage vac 250 V/div

Grid voltage vac 250 V/div

Maximum current
10.5 A (48.5%)

Maximum current 13.2 A (86.7%)00Output current iL2 10 A/div(b) Voltage drop operation.

Output current iL2 10 A/div(b) Voltage drop operation.
200 ms/div

00

200 ms/div

0

Grid voltage vac 250 V/div

Output current iL2 10 A/div0

Maximum current 12.3 A (73.9%)

Grid voltage vac 250 V/div

Output current iL2 10 A/div
Maximum current 9.70 A(37.2%)(c) Voltage recovery operation.

(c) Voltage recovery operation.

Fig. 14. Experimental results of grid failure with conventional FRT
method by applying disturbance observer. The inverter output
current overshoot rate exceeds 50% due to the delay for disturbancecompensation caused by the detection delay and sampling delay.

Fig. 15. Experimental results of grid failure with proposed ZVRT
method. By applying the proposed method, it is possible to continue
the operation of the inverter, and satisfy the FRT requirements.

483%). After that, the inverter stops operation by the overcurrent protection. Due to the detection delay and the samplingdelay, the inverter output current overshoot with the minimized
LCL filter is large. As a result, the inverter output current
reaches the over current threshold. Therefore, in order to meet
the FRT requirements, a high speed control method that is fasterthan the conventional method is necessary.
Figure 14 shows the experimental result for the ZVRT
operation of the conventional FRT method with the highperformance disturbance observer. In Fig. 14 (a), it is possible
to continue the operation during the grid failure. However, in Fig.
14 (b), the inverter output current maximum value is 13.2 A atthe voltage drop (Overshoot rate: 86.7%). Moreover, in Fig. 14(c), the inverter output current maximum value at the voltage
recovery is 12.3 A (Overshoot rate: 73.9%). Thus, it is
impossible to reduce the inverter output current overshoot rate
less than 50% at the voltage recovery. If the sampling frequency
for the disturbance compensation increases, it is possible tosuppress the inverter output current overshoot less than thethreshold value of over current protection with the highperformance disturbance observer. However, due to the delay
time of the detection and the sampling, the inverter output
current overshoot rate exceeds 50% with the minimized LCL
filter that is composed by the minimized interconnected inductor(%Z of 1.0%) and filter inductor (%Z of 0.78%). As a conclusion,
it is necessary to reduce the detection delay time in order to meet
the FRT requirements with the minimized LCL filter.

Figure 15 shows the experimental result of the ZVRT
operation with the proposed high-speed gate-block method. The
inverter output current overshoot at the grid voltage drop is 10.5
A (Overshoot rate: 48.5%), whereas the inverter output current
overshoot at the grid voltage recovery is 9.70 A (Overshoot rate:
37.2%). From the experimental result, the FRT requirements are
satisfied by the proposed high-speed gate-block method.
Therefore, it is confirmed that the grid-tied inverter with theminimized LCL filter meets the FRT requirements by the
proposed high-speed gate-block method and the designed LCL
filter. There is error of 5.6% between the overshoot current ofcalculation result and experimental result at the grid voltage
recovery. The error is caused by the approximation when
deriving the equation, and the inconsideration of the damping
resistor.
V.

[9]

[10]

[11]
[12]

CONCLUSION

In this paper, the ZVRT operation of the single-phase gridtied inverter with the minimized LCL filter was verified. It was
confirmed that the inverter output current overshoot rate during
the voltage sag was suppressed to become less than 50% by the
proposed high-speed gate-block method and the design of the
LCL filter. In particular, the interconnected inductor was
minimized to 1.0% of %Z and the filter inductor is minimized to
0.78% of %Z in the 1-kW prototype. Therefore, by applying the
proposed method, it is possible to reduce the size of LCL filter
and to meet the FRT requirements.

[13]

[14]

[15]

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