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PCM2704, PCM2705, PCM2706, PCM2707
SLES081D – JUNE 2003 – REVISED DECEMBER 2006

STEREO AUDIO DAC WITH USB INTERFACE,SINGLE-ENDED HEADPHONE OUTPUT AND S/PDIF OUTPUTFEATURES• On-Chip USB Interface:– With Full-Speed Transceivers– Fully Compliant With USB 1.1 Specification– Certified by USB-IF– Partially Programmable Descriptors– Adaptive Isochronous Transfer for
Playback– Bus-Powered or Self-Powered Operation• Sampling Rate: 32, 44.1, 48 kHz• On-Chip Clock Generator:
Single 12-MHz Clock Source• Single Power Supply:– Bus-Powered: 5 V, Typical (VBUS)– Self-Powered: 3.3 V, Typical• 16-Bit Delta-Sigma Stereo DAC– Analog Performance at 5 V (Bus-Powered),
3.3 V (Self-Powered):– THD+N: 0.006% RL > 10 kΩ,
Self-Powered)– THD+N: 0.025% RL = 32 Ω)– SNR: 98 dB– Dynamic Range: 98 dB– PO: 12 mW RL = 32 Ω)– Oversampling Digital Filter– Pass-Band Ripple: ±0.04 dB– Stop-Band Attenuation: –50 dB– Single-Ended Voltage Output– Analog LPF Included• Multiple Functions:– Up to Eight Human Interface Device (HID)
Interfaces (Depending on Model andSettings)– Suspend Flag
– S/PDIF Out With SCMS
– External ROM Interface (PCM2704/6)•– Serial Programming Interface (PCM2705/7)– I2S Interface (Selectable on PCM2706/7)
Package:– 28-Pin SSOP (PCM2704/5)– 32-Pin TQFP (PCM2706/7)

APPLICATIONS
•
•
•
•
•

USB Headphones
USB Audio Speaker
USB CRT/LCD Monitor
USB Audio Interface Box
USB-Featured Consumer Audio Product

DESCRIPTION
The PCM2704/5/6/7 is TI's single-chip USB stereo
audio DAC with USB-compliant full-speed protocol
controller and S/PDIF. The USB-protocol controller
works with no software code, but USB descriptors
can be modified in some parts (for example, vendor
ID/product ID) through the use of an external ROM(PCM2704/6), SPI (PCM2705/7), or on request. (1)The PCM2704/5/6/7 employs SpAct™ architecture,
TI's unique system that recovers the audio clockfrom USB packet data. On-chip analog PLLs withSpAct enable playback with low clock jitter.

(1)

The modification of the USB descriptor through external ROM
or SPI must comply with USB-IF guidelines, and the vendor
ID must be your own ID as assigned by the USB-IF. The
descriptor also can be modified by changing a mask; contact
your representative for details.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct is a trademark of Texas Instruments.
Mac OS is a trademark of Apple Computer, Inc.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
Intel is a trademark of Intel Corporation.
Microsoft, Windows, Windows Me, Windows XP are trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does notnecessarily include testing of all parameters.

Copyright © 2003–2006, Texas Instruments Incorporated

PCM2704, PCM2705, PCM2706, PCM2707
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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)VBUS–0.3 V to 6.5 V

VCCP, VCCL, VCCR, VDD–0.3 V to 4 V

Supply voltage differences

VCCP, VCCL, VCCR, VDD±0.1 V

Ground voltage differences

PGND, AGNDL, AGNDR, DGND, ZGND

Supply voltage±0.1 V

HOST
Digital input voltage

Analog input voltage–0.3 V to 6.5 V

D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT,
PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3–0.3 V to (VDD + 0.3) V < 4 V

VCOM–0.3 V to (VCCP + 0.3) V < 4 V

VOUTR–0.3 V to (VCCR + 0.3) V < 4 V

VOUTL–0.3 V to (VCCL + 0.3) V < 4 V±10 mA

Input current (any pins except supplies)
Ambient temperature under bias

–40°C to 125°C

Storage temperature–55°C to 150°C

Junction temperature

150°C

Lead temperature (soldering)

260°C, 5 s

Package temperature (IR reflow, peak)
(1)

260°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range

Supply voltage

VBUS
VCCP, VCCL, VCCR, VDD

MIN

NOM

MAX

4.35

5

5.25

3

3.3

3.6

Digital input logic level

V

TTL compatible

Digital input clock frequency
Analog output load resistance

11.99412

16

32

Analog output load capacitance
Digital output load capacitanceOperating free-air temperature, TA

2

UNIT

–25

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12.006

MHz

100

pF

20

pF

85

°C

Ω

PCM2704, PCM2705, PCM2706, PCM2707
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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data (unless otherwise noted)
PARAMETERTEST CONDITIONSPCM2704DB, PCM2705DB,
PCM2706PJT, PCM2707PJT
MIN

TYP

UNIT

MAX

DIGITAL INPUT/OUTPUT
Host interface

Apply USB revision 1.1, full-speed

Audio data format

USB isochronous data format

INPUT LOGIC
VIH

2

3.3

VIL

–0.3

0.8

2

5.5

VIH (1)

Input logic level

VIL (1)–0.3

IIH (2)
IIL (2)
IIH

Input logic current

IIL

0.8

VIN = 3.3 V±10

VIN = 0 V

±10

VIN = 3.3 V

Vdc

65

100

µA

±10

VIN = 0 V

OUTPUT LOGIC
VOH (3)

IOH = –2 mA

VOL (3)

IOL = 2 mA

VOH

Output logic level

IOH = –2 mA

VOL

2.8
0.3
2.4

IOL = 2 mA

Vdc

0.4

CLOCK FREQUENCY
Input clock frequency, XTI
fs

11.994

Sampling frequency

1212.00632, 44.1, 48

MHz
kHz

DAC CHARACTERISTICS
Resolution

16

Bits

Audio data channel

1, 2ChannelDC ACCURACY
Gain mismatch, channel-to-channel±2±8% of FSR

Gain error±2±8% of FSR

Bipolar zero error±3±6% of FSR

RL > 10 kΩ, self-powered,
VOUT = 0 dB

0.006%

0.01%

RL > 10 kΩ, bus-powered,
VOUT = 0 dB

0.012%

0.02%

RL = 32 Ω, self-/bus-powered, VOUT = 0 dB

0.025%

DYNAMIC PERFORMANCE (4)THD+N

Total harmonic
distortion + noiseLine (5)Headphone
THD+N
S/N

Total harmonic distortion + noise

VOUT = –60 dB

Dynamic range

EIAJ, A-weighted

90

98

dB

Signal-to-noise ratio

EIAJ, A-weighted

90

98

dB

60

70

dB

Channel separation
(1)
(2)
(3)
(4)
(5)

2%

HOST
D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI
FUNC0, FUNC1, FUNC2
fIN = 1 kHz, using the System Two™ Cascade audio measurement system by Audio Precision™ in the RMS mode with a 20-kHz LPF
and 400-Hz HPF.
THD+N performance varies slightly, depending on the effective output load, including dummy load R7, R8 in Figure 32.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)
all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data (unless otherwise noted)
PARAMETERTEST CONDITIONSPCM2704DB, PCM2705DB,
PCM2706PJT, PCM2707PJT
MIN

TYP

UNIT

MAX

ANALOG OUTPUT
Output voltage

0.55 VCCL, 0.55 VCCR

Center voltage

0.5 VCCP

Load impedanceLine

AC coupling

10

Headphone

AC coupling

16

LPF frequency response

Vp-p
V
kΩ

32

Ω

–3 dB

140

kHz

f = 20 kHz

–0.1

dB

DIGITAL FILTER PERFORMANCE
Pass band

0.454 fs

Stop band

0.546 fsHz
±0.04

Pass-band ripple
Stop-band attenuation–50

Delay time

Hz
dB
dB

20/fs

s

POWER SUPPLY REQUIREMENTS
Voltage range

Supply current

Power dissipation(self-powered)Power dissipation(bus-powered)Internal power-supply
voltage (7)

VBUS

Bus-powered

4.35

5

5.25

VCCP, VCCL, VCCR,
VDD

Self-powered

3

3.3

3.6

Line

DAC operation

23

30

Headphone

DAC operation RL = 32 Ω)

35

46

Line/headphone

Suspend mode (6)

150

190

Line

DAC operation

76

108

Headphone

DAC operation RL = 32 Ω)

116

166

Line/headphone

Suspend mode (6)

495

684

Line

DAC operation

115

158

Headphone

DAC operation RL = 32 Ω)

175

242

Line/headphone

Suspend mode (6)

750

998

µW

VCCP, VCCL, VCCR,
VDD

Bus-powered

3.35

3.5

Vdc

85

°C

3.2

Vdc

mA
µA
mW
µW
mW

TEMPERATURE RANGE
Operating temperature
θJA

(6)
(7)

4

Thermal resistance–25
28-pin SSOP
(PCM2704/5)

100

32-pin TQFP
(PCM2706/7)

80

°C/W

Under USB suspend state.
VDD, VCCP, VCCL, VCCR. These pins work as output pins of internal power supply for bus-powered operation.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

PIN ASSIGNMENTS
PCM2704/PCM2705
DB PACKAGE(TOP VIEW)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

XTI
SSPND
TEST0
TEST1
HID2/MD
HID1/MC
HID0/MS
HOST
VCCP
PGND
VCOM
AGNDR
VCCR
VOUTR

VBUS
D+
D–
VDD
DGND
FUNC1
FUNC2
DOUT

1
2
3
4
5
6
7
8
9
10
11
12
13
14

24 23 22 21 20 19 18 17

ZGND
AGNDL
VCCL
VOUTL
VOUTR
VCCR
AGNDR
VCOM

25

16

26

15

27

14

28

13

29

12

30

11

31

10

32

9
1 2 3

4

5 6 7

PSEL
DT
CK
XTO
XTI
SSPND
TEST
FSEL

8

PGND
VCCP
HOST
FUNC3
FUNC0
HID0/MS
HID1/MCHID2/MD

XTO
CK
DT
PSEL
DOUT
DGND
VDD
D–
D+
VBUS
ZGND
AGNDL
VCCL
VOUTL

PCM2706/PCM2707
PJT PACKAGE(TOP VIEW)

P0020-01

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

Terminal Functions (PCM2704DB/PCM2705DB)TERMINALNAME

I/O

DESCRIPTION

AGNDL

12

—

Analog ground for headphone amplifier of L-channel

AGNDR

17

—

Analog ground for headphone amplifier of R-channel

CK

2

O

Clock output for external ROM (PCM2704). Must be left open (PCM2705).

D+9

I/O USB differential input/output plus (1)D–

8

I/O USB differential input/output minus (1)

DGND

6

—

Digital ground

DOUT

5

O

S/PDIF output

DT

3

I/O Data input/output for external ROM (PCM 2704). Must be left open with pullup resistor (PCM2705). (1)

HID0/MS22I

HID key state input (mute), active HIGH (PCM2704). MS input (PCM2705). (2)HID1/MC23

I

HID key state input (volume up), active HIGH (PCM2704). MC input (PCM2705). (2)HID2/MD24

I

HID key state input (volume down), active HIGH (PCM2704). MD input (PCM2705). (2)

HOST

21

I

Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation (LOW: 100 mA, HIGH: 500 mA). (3)

PGND

19

—

Analog ground for DAC, OSC, and PLL

PSEL

4

I

Power source select (LOW: self-power, HIGH: bus-power) (1)

SSPND

27

O

Suspend flag, active LOW (LOW: suspend, HIGH: operational)

TEST0

26

I

Test pin. Must be set HIGH (1)

TEST1

25

I

Test pin. Must be set HIGH (1)

VBUS

10

—

Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.

VCCL

13

—

Analog power supply for headphone amplifier of L-channel (4)

VCCP

20

—

Analog power supply for DAC, OSC, and PLL (4)

VCCR

16

—

Analog power supply for headphone amplifier of R-channel (4)

VCOM

18

—

Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.

VDD

7

—

Digital power supply (4)

VOUTL

14

O

DAC analog output for L-channel

VOUTR

15

O

DAC analog output for R-channel

XTI

28

I

Crystal oscillator input (1)

XTO

1

O

Crystal oscillator output

ZGND

11

—

Ground for internal regulator

(1)
(2)
(3)
(4)

6

NO.

LV-TTL level
LV-TTL level with internal pulldown
LV-TTL level, 5-V tolerant
Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

Terminal Functions (PCM2706PJT/PCM2707PJT)TERMINAL
NAME

NO.

I/O

DESCRIPTION

AGNDL

26

—

Analog ground for headphone amplifier of L-channel

AGNDR

31

—

Analog ground for headphone amplifier of R-channel

CK

14

O

Clock output for external ROM (PCM2706). Must be left open (PCM2707).

D+23

I/O USB differential input/output plus (1)D–

22

I/O USB differential input/output minus (1)

DGND

20

—

Digital ground

DOUT

17

O

S/PDIF output/I2S data output

DT

15

I/O Data input/output for external ROM (PCM2706). Must be left open with pullup resistor (PCM2707). (1)

FSEL

9

I

FUNC0

5

I/O HID key state input (next track), active HIGH (FSEL = 1). I2S LR clock output (FSEL = 0). (2)

FUNC1

19

I/O HID key state input (previous track), active HIGH (FSEL = 1). I2S bit clock output (FSEL = 0). (2)

FUNC2

18

I/O HID key state input (stop), active HIGH (FSEL = 1). I2S system clock output (FSEL = 0). (2)

FUNC3

4

I

HID key state input (play/pause), active HIGH (FSEL = 1). I2S data input (FSEL = 0). (2)HID0/MS6I

HID key state input (mute), active HIGH (PCM2706). MS input (PCM2707) (2)HID1/MC7I

HID key state input (volume up), active HIGH (PCM2706). MC input (PCM2707) (2)HID2/MD8I

HID key state input (volume down), active HIGH (PCM2706). MD input (PCM2707) (2)

HOST

3

I

Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation. (LOW: 100 mA, HIGH: 500 mA). (3)

PGND

1

—

Analog ground for DAC, OSC, and PLL

PSEL

16

I

Power source select (LOW: self-power, HIGH: bus-power) (1)

SSPND

11

O

Suspend flag, active LOW (LOW: suspend, HIGH: operational)

TEST

10

I

Test pin. Must be set HIGH (1)

VBUS

24

—

Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.

VCCL

27

—

Analog power supply for headphone amplifier of L-channel (4)

VCCP

2

—

Analog power supply for DAC, OSC, and PLL (4)

VCCR

30

—

Analog power supply for headphone amplifier of R-channel (4)

VCOM

32

—

Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.

VDD

21

—

Digital power supply (4)

VOUTL

28

O

DAC analog output for L-channel

VOUTR

29

O

DAC analog output for R-channel

XTI

12

I

Crystal oscillator input (1)

XTO

13

O

Crystal oscillator output

ZGND

25

—

Ground for internal regulator

(1)
(2)
(3)
(4)

Function select (LOW: I2S DATA output, HIGH: S/PDIF output) (1)

LV-TTL level
LV-TTL level with internal pulldown
LV-TTL level, 5-V tolerant
Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

BLOCK DIAGRAM (PCM2704DB/PCM2705DB)
VCCP

VCCL

VCCR

VDD

PGND

AGNDL

AGNDR

DGND

ZGND

Power
Manager

SSPND

5-V to 3.3-V
Voltage Regulator

VBUS

DAC
Control
Endpoint

VOUTR

XCVR

Analog
PLL

VOUTL

USB
ProtocolController
USB SIE

VCOM

D+
D–

S/PDIF Encoder

DOUT

FIFO

ISO-Out
Endpoint

HID
Endpoint

PSEL

EEPROM
Interface (1)SPIInterface (2)

CK
DT
HOST

HID0/MS
HID1/MCHID2/MD

TEST0
TEST1

PLL (×8)

XTI

96 MHzTracker(SpAct)12 MHz XTO
B0054-01

8(1)

Applies to PCM2704DB(2)

Applies to PCM2705DB

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

BLOCK DIAGRAM (PCM2706PJT/PCM2707PJT)
VCCP

VCCL

VCCR

VDD

PGND

AGNDL

AGNDR

DGND

ZGND

Power
Manager

SSPND

5-V to 3.3-V
Voltage Regulator

VBUS

DAC
Control
Endpoint

VOUTR

XCVR

Analog
PLL

VOUTL

USB
ProtocolController
USB SIE

VCOM

D+
D–

S/PDIF
Encoder

DOUT

DOUT
LRCK
BCK
SYSCK
DIN

FSEL
FUNC0
FUNC1
FUNC2
FUNC3

I2S I/F
FIFO

ISO-Out
Endpoint

EEPROM
Interface (1)

CK
DT
HOST

HID3: Next Track (1)HID4: Previous Track (1)HID5: Stop (1)HID
Endpoint

HID6: Play/Pause (1)SPIInterface (2)HID0/MS
HID1/MCHID2/MDPSELTESTPLL (×8)

XTI 12 MHz

96 MHzTracker(SpAct)

XTO
B0055-01(1)

Applies to PCM2706PJT(2)

Applies to PCM2707PJT

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted)

DAC Digital Interpolation Filter Frequency Response
AMPLITUDE
vsFREQUENCYAMPLITUDE
vsFREQUENCY

0

0.05
0.04

−20
0.03
0.02
Amplitude – dB

Amplitude – dB

−40
−60
−80

0.01
0.00
−0.01
−0.02

−100

−0.03
−120
−0.04
−140
0

1

2

3

−0.05
0.0

4

f – Frequency [× fS]

0.1

0.2

0.3

0.4

f – Frequency [× fS]

G001

Figure 1. Frequency Response

0.5
G002

Figure 2. Pass-Band Ripple

DAC Analog Low-Pass Filter Frequency Response
AMPLITUDE
vsFREQUENCY

0.0

0

−0.5

−20
Amplitude – dB

Amplitude – dB

AMPLITUDE
vsFREQUENCY

−1.0

−1.5

−2.0
0.01

−40

−60

−80
0.1

1

10

100

1

f – Frequency – kHz
G003

Figure 3. Pass-Band Characteristics

10

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10

100

1k

10k

f – Frequency – kHz
G004

Figure 4. Stop-Band Characteristics

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE
vsFREE-AIR TEMPERATURETOTAL HARMONIC DISTORTION + NOISE
vsFREE-AIR TEMPERATURE
0.05
THD+N – Total Harmonic Distortion + Noise – %THD+N – Total Harmonic Distortion + Noise – %0.05
Bus-Powered
VOUT = 0 dB
0.04

0.03
32 Ω
0.02
10 kΩ
0.01

0.00
−50

−25

0

25

50

75

TA – Free-Air Temperature – °C

0.03
32 Ω
0.02

0.01
10 kΩ

−25

0

25

50

75

TA – Free-Air Temperature – °C

G005

Figure 5.

Figure 6.

TOTAL HARMONIC DISTORTION + NOISEvsSUPPLY VOLTAGE

TOTAL HARMONIC DISTORTION + NOISEvsSUPPLY VOLTAGE

100
G006

0.05
THD+N – Total Harmonic Distortion + Noise – %THD+N – Total Harmonic Distortion + Noise – %

0.04

0.00
−50

100

0.05
Bus-Powered
VOUT = 0 dB
0.04

0.03
32 Ω
0.02
10 kΩ
0.01

0.00
4.0

Self-Powered
VOUT = 0 dB

4.5

5.0

VCC – Supply Voltage – V

5.5

Self-Powered
VOUT = 0 dB
0.04

0.03
32 Ω
0.02

0.01

0.00
3.0

G007

Figure 7.

10 kΩ

3.1

3.2

3.3

3.4

VCC – Supply Voltage – V

3.5

3.6
G008

Figure 8.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE
vsSAMPLING FREQUENCYTOTAL HARMONIC DISTORTION + NOISE
vsSAMPLING FREQUENCY
0.05
THD+N – Total Harmonic Distortion + Noise – %THD+N – Total Harmonic Distortion + Noise – %0.05
Bus-Powered
VOUT = 0 dB
0.04

32 Ω

0.03

0.02
10 kΩ
0.01

0.00

Self-Powered
VOUT = 0 dB
0.04

0.03

32 Ω

0.02

0.01
10 kΩ

0.00
30

35

40

45

50

fS – Sampling Frequency – kHz

30

G009

DYNAMIC RANGE and SNR
vsFREE-AIR TEMPERATURE

DYNAMIC RANGE and SNR
vsFREE-AIR TEMPERATURE

50
G010

105
Self-Powered

Dynamic Range and SNR – dB

103

101

99
Dynamic Range
97

103

101

99
Dynamic Range
97
SNR

SNR

−25

0

25

50

75

TA – Free-Air Temperature – °C

100

95
−50

G011

Figure 11.

1245

Figure 10.

Bus-Powered

95
−50

40

Figure 9.

105

Dynamic Range and SNR – dB

35

fS – Sampling Frequency – kHz

−25

0

25

Figure 12.

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TA – Free-Air Temperature – °C

75

100
G012

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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted)
DYNAMIC RANGE and SNRvsSUPPLY VOLTAGE

DYNAMIC RANGE and SNRvsSUPPLY VOLTAGE

105

105
Self-Powered

103

Dynamic Range and SNR – dB

Dynamic Range and SNR – dB

Bus-Powered

101

99
Dynamic Range
SNR

97

95
4.0

4.5

5.0

101

99
Dynamic Range
SNR

97

95
3.0

5.5

VCC – Supply Voltage – V

103

3.2

3.3

3.4

3.5

VCC – Supply Voltage – V

G013

Figure 13.

Figure 14.

DYNAMIC RANGE and SNR
vsSAMPLING FREQUENCYDYNAMIC RANGE and SNR
vsSAMPLING FREQUENCY

105

3.6
G014

105
Bus-Powered

Self-Powered

103

Dynamic Range and SNR – dB

Dynamic Range and SNR – dB

3.1

101

99

Dynamic Range

97

SNR

95

103

101
Dynamic Range
99

SNR

97

95
30

35

40

45

50

fS – Sampling Frequency – kHz

30

G015

Figure 15.

35

40

45

fS – Sampling Frequency – kHz

50
G016

Figure 16.

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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted)
SUSPEND CURRENT
vs
FREE-AIR TEMPERATURE

200

200

150

150
Suspend Current – µA

Suspend Current – µA

SUSPEND CURRENTvsSUPPLY VOLTAGE

100

50

50

0
4.0

4.5

5.0

0
−50

5.5

VBUS – Supply Voltage – V

−25

G017

25

Figure 17.

Figure 18.

AMPLITUDE
vsFREQUENCYAMPLITUDE
vsFREQUENCY

0

0

−20

−20

−40

−40

−60
−80

50

75

100
G018

−60
−80

−100

−100

−120

−120

−140

−140
0

5

10

15

20

0

20

f – Frequency – kHz

40

60

80

100

120

f – Frequency – kHz

G019

Figure 19. Output Spectrum (–60 dB, N = 8192)

140

TA – Free-Air Temperature – °C

Amplitude – dB

Amplitude – dB

100

G020

Figure 20. Output Spectrum (–60 dB, N = 8192)

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006DETAILED DESCRIPTION
Clock and Reset
For both USB function and audio function, the PCM2704/5/6/7 requires a 12-MHz (±500 ppm) clock, which canbe generated by the built-in oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must beconnected to XTI (pin 28 for PCM2704/5, pin 12 for PCM2706/7) and XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) with one large (1-MΩ) resistor and two small capacitors, the capacitance of which depends on thespecified load capacitance of the crystal resonator. An external clock can be supplied from XTI (pin 28 for
PCM2704/5, pin 12 for PCM2706/7). If an external clock is supplied, XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) must be left open. Because no clock disabling pin is provided, it is not recommended to use theexternal clock supply. SSPND (pin 27 for PCM2704/5, pin 11 for PCM2706/7) is unable to use clock disabling.
The PCM2704/5/6/7 has an internal power-on reset circuit, and it works automatically when VDD (pin 7 for
PCM2704/5, pin 21 for PCM2706/7) exceeds 2 V typical (1.6 V–2.4 V), which is equivalent to VBUS (pin 10 for
PCM2704/5, pin 24 for PCM2706/7) exceeding 3 V typical for bus-powered applications. About 700 µs is
required until internal reset release.

Operation Mode Selection
The PCM2704/5/6/7 has the following mode-select pins.
Power Configuration Select/Host Detection
PSEL (pin 4 for PCM2704/5, pin 16 for PCM2706/7) is dedicated to selecting the power source. This selection
affects the configuration descriptor. While in bus-powered operation, maximum power consumption from VBUS isdetermined by HOST (pin 21 for PCM2704/5, pin 3 for PCM2706/7). For self-powered operation, HOST must beconnected to VBUS of the USB bus with a pulldown resistor to detect attach and detach. (To avoid excessive
suspend current, the pulldown should be a high-value resistor.)
Table 1. Power Configuration SelectPSEL

DESCRIPTION

0

Self-powered1

Bus-powered

HOST

DESCRIPTION

0

Detached from USB (self-powered)/100 mA (bus-powered)1

Attached to USB (self-powered)/500 mA (bus-powered)

Function Select (PCM2706/7)
FSEL (pin 9) determines the function of FUNC0–FUNC3 (pins 4, 5, 18, and 19) and DOUT (pin17). When the
I2S interface is required, FSEL must be set to LOW. Otherwise, FSEL must be set to HIGH.
Table 2. Function Select
FSEL

DOUT

FUNC0

FUNC1

FUNC2

FUNC3

0

Data out (I2S)LRCK (I2S)

BCK (I2S)SYSCK (I2S)

Data in (I2S)

S/PDIF data

Next track (HID) (1)Previous track (HID) (1)Stop (HID) (1)Play/pause (HID) (1)1(1)

Valid on the PCM2706; no function assigned on the PCM2707.

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USB Interface
Control data and audio data are transferred to the PCM2704/5/6/7 via D+ (pin 9 for PCM2704/5, pin 23 for
PCM2706/7) and D– (pin 8 for PCM2704/5, pin 22 for PCM2706/7). D+ should be pulled up with a 1.5-kΩ (±5%)
resistor. To avoid back voltage in self-powered operation, the device must not provide power to the pullup
resistor on D+ while VBUS of the USB port is inactive.
All data to/from the PCM2704/5/6/7 are transferred at full speed. The following information is provided in thedevice descriptor. Some parts of the device descriptor can be modified through external ROM (PCM2704/6), SPI(PCM2705/7), or internal mask ROM on request.
Table 3. Device Descriptor
DEVICE DESCRIPTOR

DESCRIPTION

USB revision

1.1 compliant

Device class

0x00 (device defined interface level)

Device subclass

0x00 (not specified)

Device protocol

0x00 (not specified)

Max packet size for endpoint 0

8 bytes

Vendor ID

0x08BB (default value, can be modified)

Product ID

0x2704/0x2705/0x2706/0x2707 (These values correspond to the model number, and the value can be
modified.)

Device release number

1.0 (0x0100)

Number of configurations

1

Vendor strings"Burr-Brown from TI" (default value, can be modified)

Product strings"USB Audio DAC" (default value, can be modified)

Serial number

Not supported

The following information is contained in the configuration descriptor. Some parts of the configuration descriptor
can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or on request.
Table 4. Configuration Descriptor
CONFIGURATION DESCRIPTOR

DESCRIPTIONInterfaceThree interfaces

Power attribute

0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value canbe modified.)

Max power

0x0A, 0x32 or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on
PSEL and HOST. This value can be modified.)

The following information is contained in the string descriptor. Some parts of the string descriptor can be
modified through external ROM (PCM2704/6), SPI (PCM2705/7), or on request.
Table 5. String Descriptor
STRING DESCRIPTOR

16

DESCRIPTION#00x0409#1

Burr-Brown from TI (default value, can be modified)#2

USB Audio DAC (default value, can be modified)

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Device Configuration
Figure 21 illustrates the USB audio function topology. The PCM2704/5/6/7 has three interfaces. Each interface isenabled by some alternative settings.

Endpoint #0

Default
Endpoint

FU
Endpoint #2(IF #1)IT
TID1Audio Streaming
Interface

OT
TID2

Analog Out

UID3Standard Audio Control Interface (IF #0)

Endpoint #5(IF #2)HID Interface
PCM2704/5/6/7
M0024-01

Figure 21. USB Audio Function Topology
Interface #0 (Default/Control Interface)
Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes
the standard audio control interface. Audio control interface consists of a terminal. The PCM2704/5/6/7 has threeterminals:• Input terminal (IT #1) for isochronous-out stream• Output terminal (OT #2) for audio analog output• Feature unit (FU #3) for DAC digital attenuator
Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept two-channel
audio streams constructed of left and right channels. Output terminal #2 is defined as a speaker (terminal type0x0301). Feature unit #3 supports the following sound control features:• Volume control• Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 dB to –64 dB
in steps of 1 dB. Changes are made by incrementing or decrementing one step (1 dB) for every 1/fS timeinterval, until the volume level reaches the requested value. Each channel can be set to a separate value. The
master volume control is not supported. A request to the master volume is stalled and ignored. The built-in
digital mute controller can be manipulated by an audio-class-specific request. A master mute control request is
acceptable. A mute control request to an individual channel is stalled and ignored. The digital volume control
does not affect the S/PDIF and I2S outputs (PCM2706/7).

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Interface #1 (Isochronous-Out Interface)
Interface #1 is for the audio-streaming data-out interface. Interface #1 has the following three alternative
settings. Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operationalsettings.
ALTERNATIVESETTINGDATA FORMAT

00

TRANSFERMODE

SAMPLING RATE(kHz)

Zero bandwidth01

16-bitStereo2s complement (PCM)

Adaptive32, 44.1, 48

02

16-bitMono

2s complement (PCM)

Adaptive32, 44.1, 48

Interface #2 (HID Interface)
Interface #2 is the interrupt-data-in interface. Interface #2 comprises the HID consumer control device.
Alternative setting #0 is the only possible setting for interface #2.
On the HID device descriptor, eight HID items are reported as follows for any model, in any configuration.
Basic HID Operation
Interface #2 can report the following three key statuses for any model. These statuses can be set by the
HID0–HID2 pins (PCM2704/6) or the SPI port (PCM2705/7).
• Mute (0xE2)• Volume up (0xE9)• Volume down (0xEA)
Extended HID Operation (PCM2705/6/7)
By using the FUNC0–FUNC3 pins (PCM2706) or the SPI port (PCM2705/7), the following additional conditions
can be reported to the host.
• Play/Pause (0xCD)• Stop (0xB7)• Previous (0xB6)• Next (0xB5)
Auxiliary HID Status Report (PCM2705/7)
One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI
command or external ROM. This definition must be described as on the report descriptor with a three-byte
usage ID. AL A/V Capture (0x0193) is assigned as the default for this status flag.
Endpoints
The PCM2704/5/6/7 has three endpoints:• Control endpoint (EP #0)• Isochronous-out audio data-stream endpoint (EP #2)• HID endpoint (EP #5)
The control endpoint is a default endpoint. The control endpoint is used to control all functions of the
PCM2704/5/6/7 by standard USB request and USB audio-class-specific request from the host. The
isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The
isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is aninterrupt-in endpoint. The HID endpoint reports HID status every 10 ms.
The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent
endpoint from the isochronous-out endpoint. This means that the effect of HID operation depends on host
software. Typically, the HID function is used to control the primary audio-out device.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006DAC
The PCM2704/5/6/7 has a DAC that uses an oversampling technique with 128-fS second-order multibit noise
shaping. This technique provides extremely low quantization noise in the audio band, and the built-in analog
low-pass filter removes the high-frequency components of the noise-shaping signal. DAC outputs through theheadphone amplifier VOUTL, and VOUTR can provide 12 mW at 32 Ω, as well as 1.8 Vp-p into a 10-kΩ load.

Digital Audio Interface—S/PDIF Output
The PCM2704/5/6/7 employs S/PDIF output. Isochronous-out data from the host is encoded to S/PDIF output
DOUT, as well as to DAC analog outputs VOUTL and VOUTR. Interface format and timing follows the IEC-60958
standard. Monaural data is converted to the stereo format at the same data rate. S/PDIF output is not supported
in the I2S I/F enable mode.
Channel Status Information
The channel status information is fixed as consumer application, PCM mode, copyright, digital/digital converter.
All other bits are fixed as 0s, except for the sample frequency, which is set automatically according to the data
received through the USB.
Copyright Management
Digital audio data output always is encoded as original with SCMS control. Only one generation of digital
duplication is allowed. The implementation of this feature is optional. Note that it is your responsibility for
determining whether to implement this feature in your product or not.

Digital Audio Interface—I2S Interface Output (PCM2706/7)
The PCM2706 and PCM2707 can support the I2S interface, which is enabled by FSEL (pin 9). In the I2S
interface enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT,
respectively. They provide digital output/input data in the 16-bit I2S format, which also is accepted by the internal
DAC. I2S interface format and timing are shown in Figure 22, Figure 23, and Figure 24.
SYSCK(256 fS)
1/fS
LRCK

R-Channel

L-Channel

BCK(64 fS)

DOUT

1

2

3

14

MSB
DIN

1

2

15

16

1

LSB
3

14

15

2

3

14

MSB
16

1

2

15

16

1

LSB
3

14

15

2

MSB
16

1

2
T0009-04

Figure 22. Audio Data Interface Format

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50% of VDD

LRCK (Output)t(BCL)t(BCH)t(BL)50% of VDD

BCK (Output)t(BCY)

t(BD)

t(LD)

DOUT (Output)

50% of VDD

t(DS)
t(DH)
DIN (Input)

50% of VDD
T0010-05

SYMBOLPARAMETER

MIN

MAX

UNIT

t(BCY)BCK pulse cycle time

300

ns

t(BCH)BCK pulse duration, HIGH

100

ns

t(BCL)BCK pulse duration, LOW

100

ns

t(BL)

LRCK delay time from BCK falling edge

–20

40

ns

t(BD)

DOUT delay time from BCK falling edge

–20

40

ns

t(LD)

DOUT delay time from LRCK edge

–20

40

ns

t(DS)

DIN setup time

20

ns

t(DH)

DIN hold time

20

ns

NOTE: Load capacitance of LRCK, BCK, and DOUT is 20 pF.

Figure 23. Audio Interface Timing
SYSCK(Output)t(SLL)t(SLH)LRCK(Output)t(SBL)t(SBH)BCK(Output)
T0196-01

SYMBOLPARAMETER

MIN

MAX

UNIT

t(SLL), t(SLH)

LRCK delay time from SYSCK rising edge

–5

10

ns

t(SBL), t(SBH)

BCK delay time from SYSCK rising edge

–5

10

ns

NOTE: Load capacitance is 20 pF.

Figure 24. Audio Clock Timing

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External ROM Descriptor (PCM2704/6)
The PCM2704/6 supports an external ROM interface to override internal descriptors. Pin 3 (for PCM2704)/pin 15(for PCM2706) is assigned as DT (serial data) and pin 2 (for PCM2704)/pin 14 (for PCM2706) is assigned as CK(serial clock) of the I2C interface when using the external ROM descriptor. Descriptor data is transferred from theexternal ROM to the PCM2704/6 through the I2C interface the first time when the device activates after
power-on reset. Before completing a read of the external ROM, the PCM2704/6 replies with NACK for any USB
command request from the host to the device itself. The descriptor data, which can be in external ROM, are as
follows. String descriptors must be described in ANSI ASCII code (1 byte for each character). String descriptors
are converted automatically to unicode strings for transmission to the host. The device address of the external
ROM is fixed as 0xA0. The data must be stored from address 0x00 and must consist of 57 bytes, as describedin the following items. The data bits must be sent from LSB to MSB on the I2C bus. This means that each byteof data must be stored with its bits in reverse order. Read operation is performed at a frequency of XTI/384(approximately 30 kHz). The content of power attribute and max power must be consistent with actual
application circuit configuration (PSEL, HOST setting, and actual power usage from VBUS or USB connector),otherwise, it may cause improper or unexpected PCM2704/6 operation.
• Vendor ID (2 bytes)• Product ID (2 bytes)• Product string (16 bytes in ANSI ASCII code)• Vendor string (32 bytes in ANSI ASCII code)• Power attribute (1 byte)• Max power (1 byte)• Auxiliary HID usage ID in report descriptor (3 bytes)

DT

CK

1−7

8

9

1−8

9

1−8

9

9

Device Address

R/W

ACK

DATA

ACK

DATA

ACK

NACK

S

Start Condition

P

Stop Condition

R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgment of a Byte if 0
DATA: 8 Bits (Byte)
NACK: Not Acknowledgment if 1

T0049-02

M

M

M

S

S

M

S

M

S

M

M

S

Device address

R/W

ACK

DATA

ACK

DATA

ACK

...

NACK

P

Figure 25. External ROM Read Operation

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Start

Repeated Start

Stopt(D-HD)t(BUF)t(D-SU)t(DT-F)t(P-SU)t(DT-R)DT

t(CK-R)t(RS-HD)t(LOW)CK

t(S-HD)t(HI)t(RS-SU)t(CK-F)
T0050-02

SYMBOLPARAMETERf(CK)

CK clock frequency

MIN

UNIT

100

kHz

t(BUF)Bus free time between a STOP and a START condition

4.7

µs

t(LOW)

Low period of the CK clock

4.7

µs

t(HI)

High period of the CK clock4µst(RS-SU)

Setup time for START/repeated START condition

4.7

µs

t(S-HD)t(RS-HD)

Hold time for START/repeated START condition4µst(D-SU)

Data setup time

250

ns

t(D-HD)

Data hold time

900

ns

t(CK-R)

Rise time of CK signal

20 + 0.1 CB 1000nst(CK-F)

Fall time of CK signal

20 + 0.1 CB 1000nst(DT-R)

Rise time of DT signal

20 + 0.1 CB 1000ns

20 + 0.1 CB 10000t(DT-F)

Fall time of DT signalt(P-SU)

Setup time for STOP condition

CB

Capacitive load for DT and CK lines

VNH

Noise margin at HIGH level for each connected device (including hysteresis)

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0.2 VDDnsµs

4

Figure 26. External ROM Read Interface Timing Requirements

22

MAX

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External ROM Example
Here is an example of external ROM data, with an explanation of the example following the data.
0xBB, 0x08, 0x04, 0x27,
0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E,
0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61,
0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20,
0x80,
0x7D,
0x0A, 0x93, 0x01

The data is stored, beginning at address 0x00.
Vendor ID: 0x08BB
Product ID: 0x2704
Product string: Product strings. (16 bytes)
Vendor string: Vendor strings are placed here. (32 bytes, 31 visible characters are followed by 1 space)
Power attribute (bmAttribute): 0x80 (Bus-powered)
Max power (maxPower): 0x7D (250 mA)
Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture)
Note that the data bits must be sent from LSB to MSB on the I2C bus. This means that each data byte must be
stored with its bits in reverse order.

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Serial Programming Interface (PCM2705/7)
The PCM2705/7 supports the serial programming interface (SPI) to program the descriptor and to set the HID
state. Descriptor data is described in the External ROM Descriptor section.
t(MHH)
MS

50% of VDD
t(MLS)t(MCL)t(MCH)t(MLH)

MC

50% of VDD
t(MCY)LSB

MD

50% of VDD

t(MDS)t(MDH)
T0013-04

SYMBOLPARAMETER

MIN

TYP

MAX

UNIT

t(MCY)

MC pulse cycle time

100

ns

t(MCL)

MC low-level time50

nst(MCH)

MC high-level time50

nst(MHH)

MS high-level time

100

ns

t(MLS)

MS falling edge to MC rising edge20

nst(MLH)

MS hold time20nst(MDH)

MD hold time15nst(MDS)MD setup time

20

ns

Figure 27. SPI Timing Diagram(1) Single Write Operation
16 Bits
MS
MC
MD
MSB

LSB

MSB

(2) Continuous Write Operation
16 Bits y N Frames
MS
MC
MD
MSB

LSB

MSB

LSB

MSB

LSB

N Frames
T0012-02

Figure 28. SPI Write Operation

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SPI Register (PCM2705/7)
B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

0

0

0

ST

0

ADDR

0

D0

D1

D2

D3

D4

D5

D6

D7

D[7:0]

Function of the lower 8 bits depends on the value of the ST (B11) bit.

ST = 0 (HID status write)
D7

Reports MUTE HID status to the host (active high)

D6

Reports volume-up HID status to the host (active high)D5

Reports volume-down HID status to the host (active high)D4

Reports next-track HID status to the host (active high)D3

Reports previous-track HID status to the host (active high)D2

Reports stop HID status to the host (active high)

D1

Reports play/pause HID status to the host (active high)D0

Reports extended command status to the host (active high)ST = 1 (ROM data write)D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB
The content of power attribute and max power has to be consistent with actual application circuit configuration(PSEL, HOST setting, and actual power usage from VBUS or USB connector), otherwise, it may cause
improper or unexpected PCM2705/7 operation.
ADDR

Starts write operation for internal descriptor reprogramming (active high)This bit resets descriptor ROM address counter and indicates following words should be ROM data (describedin the External ROM Example section). 456 bits of ROM data must be continuously followed after this bit has
been asserted. The data bits must be sent from LSB (D0) to MSB (D7).
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as HID status write when ST is
set low.
ST

Determines the function of the lower 8-bit data as follows:
0: HID status write
1: Descriptor ROM data write
Table 6. Functionality of ST and ADDR Bit Combinations
ST

ADDR

0

0

HID status write

FUNCTION

01

HID status write and descriptor ROM address reset

10

Descriptor ROM data write1

1

Reserved

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USB Host Interface Sequence
Power-On, Attach, and Playback Sequence
The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. Aftera connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While
waiting for the audio data (idle state), the analog output is set to bipolar zero (BPZ).

ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ

When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audio
data, into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next
subsequent start-of-frame (SOF) packet.

VDD
0V

Bus Idle
D+/D−

SSPND

VOUTL
VOUTR

700 µs

3.3 V(Typ.)

2.0 V (Typ.)

Î
Î
Î
Î

Bus Reset

Î
Î
Î
Î

Î
Î
ÎÎÎ
Î
ÎÎÎ
ÎÎ
ÎÎÎ
Î
Î
ÎÎÎ
Î
ÎÎÎ
ÎÎ
ÎÎÎ
Î
ÎÎÎ
Î Î
ÎÎÎÎ
ÎÎÎ Î
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
1st Audio Data

Set Configuration

SOF

SOF

2nd Audio Data

SOF

BPZ

Device Setup

1 ms

Internal Reset
Ready for Setup

Ready for Playback
T0055-01

Figure 29. Initial Sequence26

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

Play, Stop, and Detach Sequence
When the host finishes or aborts the playback, the PCM2704/5/6/7 stops playing after completing the output of
the last audio data.
VBUS

ÎÎ
ÎÎ
Î
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎAudio Data

D+/D–

SOF

Audio Data

SOF

Last Audio Data

SOF

SOF

SOF

VOUTL
VOUTR
Detach

1 ms

T0056-01

Figure 30. Play, Stop, and Detach
Suspend and Resume Sequence

Î
Î
Î
Î
Î

ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ

The PCM2704/5/6/7 enters the suspend state after the USB bus has been in a constant idle state forapproximately 5 ms. While the PCM2704/5/6/7 is in the suspend state, SSPND flag (pin 27 for PCM2704/5,
pin 11 for PCM2706/7) is asserted. The PCM2704/5/6/7 wakes up immediately when detecting the non-idle stateon the USB bus.
D+/D−

SSPND

Idle

5 ms

Suspend

VOUTL
VOUTR
ActiveActive

2.5 ms

T0057-01

Figure 31. Suspend and Resume

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

Typical Circuit Connection 1 (Example of USB Speaker)
Figure 32 illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.
X1
C1

C2
R1

PCM2704DB
External ROM(Optional)

1 XTO

XTI

28

SCL

2 CK

SSPND

27

SDA

3 DT

TEST0

26

4 PSELTEST1

25

5 DOUT

HID2/MD

24

6 DGND

HID1/MC

23

7 VDD

HID0/MS

22

8 D–

HOST

21

9 D+

VCCP

20

10 VBUSPGND

1911 ZGND

VCOM

1812 AGNDL

AGNDR

17

13 VCCL

VCCR

16

14 VOUTL

VOUTR

15

SUSPEND

R9S/PDIF OUT

VOLUME–

USB ’B’
Connector

C7

R2
R3

D–

VOLUME+
MUTE

R4
D+
VBUS

C3

GND
C6

C4

+

C8

C5
C9
+

C13

+

+
+
Notes:
C11
C12
C10
C14
X1: 12-MHz crystal resonator
TPA200X
C1, C2: 10-pF to 33-pF (depending on load capacitance of crystal resonator)
Power
C3, C4, C5, C6, C7: 1-µF ceramic
Amp
R5
R6 R7
R8
C8: 47-µF electrolytic
C9, C10: 100-µF electrolytic (depending on tradeoff between required frequency
response and discharge time for resume)
C11, C12: 0.022-µF ceramic
C13, C14: 1-µF electrolytic
R1: 1 MWR2, R9: 1.5 kW
R3, R4: 22 W
R5, R6: 16 W
R7, R8: 330 W (depending on tradeoff between required THD performance and pop-noise level for suspend)
Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kW ±20%, which is the discharge pathfor C9 and C10.
External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power source.
S0073-01

Figure 32. Bus-Powered Application
NOTE:

The circuit illustrated in Figure 32 is for information only. Whole-board design should
be considered to meet the USB specification as a USB-compliant product.

28

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Typical Circuit Connection 2 (Example of Remote Headphone)
Figure 33 illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.
C9+

Headphone+

C6+

PLAY/PAUSE
NEXT TRACK
MUTE
VOLUME+

29

28

VCCR

VOUTR

VOUTL

27

26

25
ZGND

30

VCCL

31

AGNDL

32

AGNDR

C4

VCOM

C5

C3

C11

C12

R5

R6

R7

R8

R9

PGND

2

VCCP

VBUS 24
D+ 23

3

HOST

D– 22

4

FUNC3

VDD 215

FUNC0
HID0/MS

FUNC1 19

7

HID1/MCFUNC2 18

8

HID2/MD

DOUT 17

VBUS

R3

D+
D–
R4

GND

C8

DGND 20

6R10USB ’B’
Connector

R2

1

PCM2706PJTC10C7PREVIOUS TRACK
STOP

FSEL

TEST

SSPND

XTI

XTO

CK

DT

PSEL

VOLUME–

9

10

11

12

13

14

15

16

External ROM(Optional)
SDA

SUSPEND
R1

R11
SCL

X1

C1

C2

Notes:
X1: 12-MHz crystal resonator
C1, C2: 10-pF to 33-pF (depending on load capacitance of
crystal resonator)
C3, C4, C5, C7, C8: 1-µF ceramic
C6: 47-µF electrolytic
C9, C10: 100-µF electrolytic (depending on required frequency
response)
C11, C12: 0.022-µF ceramic

R1: 1 MWR2, R11: 1.5 kW
R3, R4: 22 W
R5, R6: 16 W
R7, R8, R9, R10: 3.3 kW
External ROM power can be supplied from VCCP, but any otheractive component must not use VCCP, VCCL, VCCR, or VDD asa power source.
S0074-01

Figure 33. Bus-Powered Application
NOTE:

The circuit illustrated in Figure 33 is for information only. Whole board design should
be considered to meet the USB specification as a USB-compliant product.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

Typical Circuit Connection 3 (Example of DSP Surround Processing Amp)
Figure 34 illustrates a typical circuit connection for an I2S- and SPI-enabled self-powered application.
+
C8
+

C6
+

SUSPEND

VCCL

AGNDL

ZGND

PGND

R6

R7

VBUS 24

2

VCCP

D+ 23

3

HOST

D– 22

4

FUNC3

VDD 215

FUNC0

DGND 20

6

HID0/MS

FUNC1 19

7

HID1/MCFUNC2 18

8

HID2/MD

DOUT 17

DT

PSEL

PCM2707PJT

CK

MD

C11

9

10

11

12

13

14

15

16

C9
R8

R9

R10

R11

USB ’B’
Connector

R2

1

XTO

MC

25

XTI

MS

26

SSPND

LRCK

27

TEST

DIN

28

FSEL

TAS300X
I2S I/F Audio Device

29

VOUTL

AGNDR

C5

30
VCCR

31

C4

VOUTR

32
VCOM

C3

C10

Headphone

VBUS

R3

D+
D–
+

R4

R12

GND

C7
BCK
SYSTEM CLOCK
DOUT

R5
R1
X1
C1

Power
C2

3.3 V
GND

Notes:
X1: 12-MHz crystal resonatorC10, C11: 0.022-µF ceramic
C1, C2: 10-pF to 33-pF (depending on load capacitance of crystal
R1, R12: 1 MW
resonator)
R2, R5: 1.5 kW
C3, C4: 1-µF ceramic
R3, R4: 22 W
C5: 0.1-µF ceramic and 10-µF electrolytic
R6, R7: 16 W
C6, C7: 47-µF electrolytic
R8, R9, R10, R11: 3.3 kW
C8, C9: 100-µF electrolytic (depending on required frequency response)
SPI host (DSP) must have responsibility to handle D+ pullup if descriptor is programmed by SPI. SPI host must not activate D+ pullup until all internalregisters have been set. D+ pullup must not be activated while detaching from host.
D+ must not activate (HIGH: 3.3 V) before programming of the PCM2707 by SPI is completed.
D+ must not activate (HIGH: 3.3 V) while the device is detached from the USB.
VBUS of the USB can be used to detect USB bus power status. (Note that VBUS of the USB connector is 5 V.)
S0075-01

Figure 34. Self-Powered Application
NOTE:

The circuit illustrated in Figure 34 is for information only. Whole board design should
be considered to meet the USB specification as a USB-compliant product.

30

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

APPENDIX
Operating Environment
For appropriate operation, one of the following operating systems must be running on a host PC equipped with a
USB port certified by the manufacturer. If these conditions are met, the operation of the PCM2704/5/6/7 does
not depend on the operating speed of the CPU. Texas Instruments has tested and confirmed the following listed
operating environments. The PCM2704/5/6/7 may work with other PCs and operating systems also, but proper
operation using them has not been tested and cannot be assured by TI.
Operating System• Microsoft™ Windows™ 98SE/ Windows Me™ Japanese/English edition (For Windows 98SE and Windows
Me, the HID function is not fully functional with the default class driver.)• Microsoft Windows 2000 Professional Japanese/English edition• Microsoft Windows XP™ Home/Professional Japanese/English edition (For Windows XP, use the latest
version of the USB audio driver, which is available on the Windows update site, or apply Service Pack 1. See
the Q310507 white paper available from Microsoft.)• Apple Computer Mac OS™ 9.1 or later Japanese/English edition• Apple Computer Mac OS X 10.0 or later English edition• Apple Computer Mac OS X 10.1 or later Japanese edition SP (For the Mac OS X 10.0 Japanese edition,plug and play does not work appropriately for USB audio devices.)
PC: One of These PC-AT Compatible Computers Running a Listed OS (OS Requirement Must Be Met)
• Motherboard using Intel ™ 440 BX or ZX chipset (using the USB controller in the chipset)• Motherboard using Intel i810 chipset (using the USB controller in the chipset)• Motherboard using Intel i815 chipset (using the USB controller in the chipset)• Motherboard using Intel i820 chipset (using the USB controller in the chipset)• Motherboard using Intel i845 chipset (using the ICH2 USB controller in the chipset)• Motherboard using Intel i845 chipset (using the ICH4 USB controller in the chipset)• Motherboard using Intel i850 chipset (using the USB controller in the chipset)• Motherboard using Intel i848 chipset (using the ICH5/R USB controller in the chipset)• Motherboard using Intel i865 chipset (using the ICH5/R USB controller in the chipset)• Motherboard using Intel i875 chipset (using the ICH5/R USB controller in the chipset)• Motherboard using Apollo KT133 chipset (using the USB controller in the chipset)• Motherboard using Apollo KT333 chipset (using the USB controller in the chipset)• Motherboard using Apollo Pro Plus chipset (using the USB controller in the chipset)• Motherboard using MVP4 or MVP3 chipset (using the USB controller in the chipset)• Motherboard using Aladdin V chipset (using the USB controller in the chipset)• Motherboard using SiS530 or SiS559 chipset (using the USB controller in the chipset)• Motherboard using SiS735 chipset (using the USB controller in the chipset)NOTE:

The PCM2704/5/6/7 has been acknowledged in a USB compliance test. However,
the acknowledgment is for the PCM2704/5/6/7 device only, and does not apply to thecustomer's system using the PCM2704/5/6/7.

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SLES081D – JUNE 2003 – REVISED DECEMBER 2006

REVISION HISTORY

Changes from C Revision (June 2006) to D Revision ................................................................................................... Page
•
•
•
•
•
•

Added SYSCK specification, changed Figure 22 ............................................................................................................... 19
Added Figure 24 for clock timing specification ................................................................................................................... 20
Added attention to store in reverse order (LSB to MSB) .................................................................................................... 21
Added attention to store in reverse order (LSB to MSB) .................................................................................................... 23
Added attention to transfer from LSB to MSB for descriptor ROM data............................................................................. 25
Added attention to transfer from LSB to MSB for descriptor ROM data............................................................................. 25

Changes from B Revision (May 2005) to C Revision ..................................................................................................... Page••••

Added attention to inconsistent data set and corrected errors ........................................................................................... 21
Added attention to inconsistent data set and corrected errors ........................................................................................... 23
Added attention to inconsistent data set and corrected errors ........................................................................................... 25
Added attention to inconsistent data set and corrected errors ........................................................................................... 25

Changes from A Revision (May 2004) to B Revision ..................................................................................................... Page••

32

Changed data sheet to new format ...................................................................................................................................... 1
New table added to data sheet ............................................................................................................................................. 2

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6-Dec-2006

PACKAGING INFORMATION
Orderable Device

Status (1)Package
Type

Package
Drawing

Pins Package Eco Plan (2)Qty

Lead/Ball Finish

MSL Peak Temp (3)PCM2704DB

ACTIVE

SSOP

DB

28

47

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2704DBG4ACTIVE

SSOP

DB

28

47

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2704DBR

ACTIVE

SSOP

DB

28

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2704DBRG4ACTIVE

SSOP

DB

28

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2705DB

ACTIVE

SSOP

DB

28

47

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2705DBG4ACTIVE

SSOP

DB

28

47

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2705DBR

ACTIVE

SSOP

DB

28

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2705DBRG4ACTIVE

SSOP

DB

28

2000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2706PJTACTIVE

TQFP

PJT

32

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2706PJTG4ACTIVE

TQFP

PJT

32

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2706PJTR

ACTIVE

TQFP

PJT

32

1000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2706PJTRG4ACTIVE

TQFP

PJT

32

1000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2707PJTACTIVE

TQFP

PJT

32

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2707PJTG4ACTIVE

TQFP

PJT

32

250

Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2707PJTR

ACTIVE

TQFP

PJT

32

1000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM

PCM2707PJTRG4ACTIVE

TQFP

PJT

32

1000 Green (RoHS &no Sb/Br)CU NIPDAU

Level-1-260C-UNLIM(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

6-Dec-2006(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATAMPQF112 – NOVEMBER 2001

PJT (S-PQFP–N32)

PLASTIC QUAD FLATPACK

0,45
0,30

0,80

0,20 M

0,20
0,09

Gage Plane

32
0,15
0,05

1

0,25
0°– 7°

7,00 SQ
0,75
0,45

9,00 SQ

1,05
0,95
Seating Plane
0,10

1,20
1,00

4203540/A 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

MECHANICAL DATAMSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN
0,38
0,22

0,65
28

0,15 M

15

0,25
0,09
8,20
7,40

5,60
5,00

Gage Plane
1

14

0,25

A

0°–ā8°

0,95
0,55

Seating Plane
2,00 MAX

0,10

0,05 MINPINS **

14

16

20

24

28

30

38

A MAX

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30

DIM

4040065 /E 12/01
NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

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