2023 EDITION
東北大学 国際集積エレクトロニクス研究開発センター

Tohoku University
Center for Innovative Integrated
Electronic Systems

Center for Innovative Integrated Electronic Systems

Tohoku University Center for Innovative Integrated Electronic Systems

Open up Innovation

Goal of the center :Model “B-U-B (Business-University-Business)”of integrated electronics from the international industry-a cademic alliance!
Lead the recovery and new creation
Leap towar d world-class

Fabrication technology
Circuit design technology
System design technology

Industry-academic collaboration

Software technology
Algorithm technologyetcNational Project

Materials suppliers
Embedded equipment suppliers
Embedded software companies

Community-based cooperation project

Other Universies andResearch Institues

Electronic equipment

The Center aims to contribute to theenhancement of global competitiveness in the fieldof next-generation integrated electronics systems, andwork toward the creation of practical applications
and new industries, through the research anddevelopment of innovative devices and its integrated
electronic systems and constructing a consortiumfor this field under the international
collaboration among industries,
universities and government.

Flexible joint research frame work
between industry-academic alliance
Knowledge based on accomplishments
between academic-industrial
collaborations

NEEDS

Centralized administrative control andstrategic operation of world-class
intellectual properties of core technologies(in Japan and overseas)

Materials suppliers
System design companies
System software companies
System companies
Networking companies
Content providers
IT·solution companies
Car electronics companies
etc.

RegionSupportPartnershipCenter for Innovative
Integrated Electronic
Systems (CIES)

Miyagi Sendai Iwate
Prefecture City Prefecture取る(established in Oct. 2012)

Downstream
industries

Regional companies, etc.

Ultra-low power spintronics semiconductor development hub
Consistent development from design, prototyping, evaluation, and system
Creation of world-leading low-power technology through development anddemonstration

Global standard joint research contracts

Leading the world in the development of spintronics semiconductors and their application systems
Power consumption of semiconductors reduced
to 1/100
AI Chip変更

Integrated electronics is a technology that is used in all kinds of industrial
products and social infrastructure, and determines the quality of our lives. To meet thesocial needs of carbon neutrality, AI/IoT/DX, and Society 5.0, innovative integrated
electronics systems that can achieve significant low-power operation are required.
The Center for Innovative Integrated Electronic Systems (CIES) has conducted the
CIES consortium consisting of industry-academia joint researches, major national
projects, and regional collaboration projects through the cooperation of domestic andforeign companies from fields such as materials, equipment, devices, circuits and systems
with support of local government. This center plays a part in the "Technology Co-creation for
Semiconductor of Tohoku University" established by Tohoku University in 2021, and is
expanding its R&D fields from spintronics to AI hardware and power electronics, and has
promoted to develop core technologies related to integrated electronics. In addition, we arecollaborating with Tohoku University startup "Power Spin Inc." to accelerate the social
implementation of developed technologies and the further advancement of industry-academia
collaboration.
In June 2023, Japan's "Semiconductor/Digital Industrial Strategy" was revised, and "advanced
technology development (spintronics technology) at academia-based centers" was positioned as agoal/strategy. We recognize that the responsibility of this center has increased significantly. At the G7
Hiroshima Summit, the “the U.S.-Japan University Partnership for Workforce Advancement and Research &Development in Semiconductors (UPWARDS) for the Future" was concluded. In response, this center is working
on innovative semiconductor R&D, manufacturing, supply chain, and human resource development throughcollaboration between industry and Japanese and U.S. universities.
Through these activities, we hope to contribute to the development of our home prefecture, Miyagi Prefecture,
the realization of a carbon-neutral society, and ensuring economic growth and economic security.
The development of this center to this day is due to the continued support and cooperation of many people. I
would like to express my deepest gratitude to all for your dedication and continued support.

変更予定

March 2024

Tetsuo Endoh
Director of CIES

・Materials technology
・Fabrication technology

etc.

0.001

1

-97%

-99%

0.03

0.01

CMOS-based Spintronics

CMOS-based Spintronics

Collaboration
with TIA / Fundry

Innovation in materials andmanufacturing technology

Innovation in evaluation
technology

System innovation

Spintronics low-power
semiconductor
designCMOS
manufacturing

Spintronics
material / device
manufacturing

Spintronics low-power
Semiconductor
chip demonstration

System development
utilizing spintronics lowpower semiconductor

Contribution to strengthening
industrial competitiveness throughsocial implementation

Tohoku univ. modell

CIES symbol and its messages

SOT-MRAM

Design innovation

Bringing further innovation

・Device technology
・Circuit design technology

・System design technolo gy ・Software technology
・Algorithm technology

1-99.9%

CMOS-based Spintronics

Innovative technology from Tohoku Univ.
Spintronics semiconductors

featureAdvanced core technolo gies and intellectual properties frommaterials/devices/ p rocesses to system/architectures,
created and reserve d at Tohoku University under its“Research First” prin ciple and “Open Doors” philosop hy,
and “Practice-Oriented Research and Education” ethos.

1

STT-MRAM

3RZHU

The world's only 300mm compatible R & D facility in semiconductor development
spintronics

Core
technology

1

Materials technology
Device technology

Co-creation field(CIES consortium)

Embedded devices*1 Official support from Miyagi Prefecture throughthe system of special zones for the promotion ofprivate investment (information service relatedindustries) that was applied for jointly by the
Miyagi prefectural government and municipal
governments in the prefecture.
*2 Official support from Sendai City through anamount corresponding to the fixed property tax,etc., according to an agreement made by
Tohoku University and Sendai City.

(Leading-edge technology seeds)

3RZHU

300mm wafer process line,
facilities for device,characterization & physicalanalysis in university campus
for the first time in JapanLSIs

3RZHU6SHHG

First privately donatedresearch and development
center by founded Tohoku
University in Science Park

Tohoku University

Co-creation ﬁeld thatmatches diverse
needs and seeds(needs to University)

Materials suppliers
Device manufacturers
Circuit design companies
Fabrication equipment suppliers

Sof tware

Our Mission
and Vision

Industry groups

SEEDS

fe aturefeatureHardwareUpstream
industries

Cooperation【 Venture from Tohoku University 】

Semiconductor manufacturing process / dmaterial / image sensor
development demonstration hub
MEMS design / process development demonstration hub

A virtuous cycle of funds by creating new Industries through innovative technology from Tohoku Univ. andaccelerating social implementation

Creating markets for spintronics semiconductor
manufacturing / evaluation equimpents and design tools

Technology recipient:• From domestic and overseas semiconductor-relatedindustries to semiconductor user companies• Tohoku University startup “Power Spin Inc.”

Creation of low-power chip design market by circuit IP andarchitecture of spintronics semiconductors

Core technology: Spintronics + CMOS

Tohoku univ. New AI / IoT spintronics semiconductor prototype line
Creating low-power semiconductor / system market that contributes to carbon neutrality

Symbolic messages
Green-based color: Ecology & low power
Meaning of “i” : Innovation & integration
Three rings converging into “ i ” :Integration of knowledge, science & technology with “ i ” ,Collaboration of industry, academia and government with “ i ” ,Combination of many kinds of layer researcher from material to system with “ i ”

2CIES Consortium R&D Scope

R&D Division (CIES Consortium)
A

Organization of CIES Consortium
Industry-academia consortium framework executive
Executive Vice President: Takuro Ueda

SupportIndustry-academia consortium management representative

Participation in operations

Center for Innovative Integrated
Electronic Systems (CIES)
Director: Tetsuo EndohCompanies

R&D division(established in Oct. 2012)- Materials- Circuits

Universities
andResearch institutes- Processes- Equipment◎ R&D program regarding leadingedge integration electrical
technology◎ Novel IP licensing system◎ Sharing research information◎ Joint educational programs
Research assistant (RA)nternship◎ Re- education for industrial
researcher and engineer

Strategic planning divisionin Japan and overseas◎High performance
Clean Room◎300 mm process line
& 300 mm evaluation tools
compatible with leading edge
industrial research lines◎Many kinds of physicalanalysis tools◎ Participation of faculty members
and Ph.D. Students◎ Joint educational programs
Research assistant (RA)nternship◎ Sharing research information
and research facility◎ CIES Joint Research- Research planning- Publicity

Facility technology division- Facility mgt, Research equipment mgt, Safety andhealth, Information security

Support office- General affairs - Accounting- Research partnership

Establishment of COE forindustry-academia collaborations

Industrialization
Commercialization

Development and mobilizationof human resources

Technology Co-creation for Semiconductor of Tohoku University
Hub for MEMS Design and Process

Hub for Spintronics Low Power Semiconductor
Spintronics low-power semiconductors,
high density memory, high performance processors

MEMS technology (micromachines,
sensors, photonics, etc.）

MEMS
sensors

CIES

Spintronics

Cooperation

Hub for Semiconductor Manufacturing Process,Parts, Material and Image Sensors
Semiconductor manufacturing process,
Manufacturing process
high-performance image sensors

μSIC

Applications

NICHe

Startups originated at TU

TohokuSemiconductor
TOHOKU
Consortiumon Design of
Semiconductor
Electronics
Industry
Electronicsand
DesignConsortium

Next-Generation
Semiconductor Project

CIES Consortium R&D Scope

SystemTechnology

Research and development on embedded security technology

R&D of 3D non-volatile memory

B

National Projects

Car electronics

3

Higher energy efficiency①Spintronics/New Memory②AI Hardware③Power Electronics

MTJ/CMOS hybrid technology+ 3D memory

Brain computing& AI system

SiC/GaN on Si
module & system
1

R&D of next-generation high-power converters for power and industry

Innovative spintronics X semiconductor research hub
Development of advanced semiconductor manufacturing technology／
Photonics-electronic convergence interface memory module technology
Feasibility study／ Research and development of microfabrication core technologies for nonvolatile MRAMat 1.5nm node and beyond

Standby power-free system by MTJ/CMOS Hybrid technologies and its environmental tolerance test(for space application)

JSPS

Spintronics/Vertical elements of two-dimensional materials

SIP Project (3rd Phase)

Limit to energy saving

R&D of integration and packaging technologies

JAXA Space Exploration
Innovation Hub

CAO

Integrated Electronic Systems

R&D of next-generation electrical component technologies

Development of design technology to accelerate industrial application of AI edge computing／
Design efficiency of AI processing semiconductors by CMOS/spintronics-hybrid technology and its applications

MEXT Research and Developmentof Basic Technologies for Creating
Innovative Power Electronics

AI system

R&D of WBG power module technologies

NEDO Development of Technology
for Designing Energy-Efficient AI
Semiconductor Chips and Systems

Core-to-Core Program

Edge computing

R&D of error correction technologies in flexible information processing
R&D of MTJ/CMOS Hybrid AI application processors

NEDO Project for Researchand Development of Enhanced
Infrastructures for Post 5G
Information and Communications
Systems

2

R&D of a VLSI platform for real-world intelligent integrated systems

R&D of brain-type processing circuit technologies

MEXT Initiative to Establish Nextgeneration Novel Integrated Circuits
Centers (X-NICS)

Carbon Neutral, Digital Shift, Society 5.0

R&D of circuit and design tool technologies

R&D of supersensitive magnetic sensors using ferromagnetic tunnel junctions

Device/Module/CircuitTechnology

Overseas ResearchInstitutions

R&D of measurement, evaluation and analysis technologies

Embedded Device Technology

CircuitTechnology

Industry-academia-government co-creation with international cooperation

R&D of manufacturing technologies

R&D of technologies to automatically design environments for low-energy consumption
and highly functional VLSI processors based on non-volatile memory

3D Integrated Circuit Technology/Materials

STT/SOT-MRAM &Spintronics/CMOS Hybrid
processor

R&D of STT-MRAM・SOT-MRAM and Spintronics/CMOS Hybrid application processor

in Japan and overseas- Devices- System- IP mgt- Contract- HR development

LSI
Technology

Participatingcompanies
Spintronics

Joint management board on industry-academic alliance
Forum for long-term strategic visions

3D
MemoryParticipation

R&D of material and device technologies

Region Regional companies, etc

AI Hardware

・Graduate School of Engineering
・Graduate School of Information Science・Research Institute of ElectricalCommunication
・Institute for Materials Research・Research Center for Rare Metal
and Green Innovation
・Center for Science and Innovation in
Spintronics

Industry-Academic Collaboration

Iwate
Prefecture

Power Electronics

Participation in operations

SendaiCity

Partnership

Director: Tetsuo Endoh

Tohoku University

MiyagiPrefecture

Research and development of integrated power electronics for the realization of a decarbonized societyIntelligent power electronics system with USPM to support grid stabilizationC

J-Innovation HUB（International Development Category） Center for Innovative Integrated Electronic Systems

D

Community-based Cooperation Projects
Integrated Electronics
Project

R&D of electronic device components for IT

Car Electronics Project

R&D of electronic device components for automotive

Tohoku Semiconductor
Electronics Design Consortium

Human resource development, resilience of supply chains, and promotion of research and development

4

A

Industry – Academic CollaborationA

Spintronics LSI Technology

Industry – Academic Collaboration

Spintronics Embedded Device Technology

R&D of supersensitive magnetic sensors using
ferromagnetic tunnel junctions

R&D of STT/SOT-MRAM &Spintronics/CMOS Hybrid processor
Prof.
In this R&D project, the technologies for STT/SOT-MRAM & Spintronics/CMOS Hybrid processor are Prof.
Tetsuo Endoh
Shoji Ikeda
researched and developed with combing the spintronics technology and the silicon CMOS technology,
in joint efforts between industry and academia.
The actual R&D items are as follows. ①Material/device technologies for the spintronics devices that have a compatibility for CMOS
integrated circuits, ②Unit process/process integration technologies using the industry-standard 300mm Si wafers, ③Highly efficientmeasurement/evaluation technologies and multifunctional analysis technologies, ④Circuit and design tool technologies that cover frombasic memory cells to large scale integrated circuits.
By integrating these developed technologies, we have designed STT/SOT-MRAM, and microcontrollers and AI application
processors such as image recognition processors using spintronics/CMOS hybrid technology, and have demonstrated low power
consumption performance in their integrated circuits prototyped using 300mm process lines. From now on, we will continue to promotefurther technological innovation through this project. In this way, we will accelerate the practical application of nonvolatile working
memory and nonvolatile logic, which will realize dramatic low-power systems, and contribute to the realization of a carbon neutral
society.

Prof.

Yasuo AndoProf.

Mikihiko Oogane

Magnetic sensors are widely used in various fields, such as environment, security, medical appliances, information technology,
automobiles, etc. Additionally, the market scale of magnetic sensors is several billion dollars*. In this research, we will develop magnetic
sensor devices with high sensitivity, small size, low power consumption and low cost using magnetic tunnel junctions (MTJs). A
revolution in market of magnetic sensors is expected by realization of high-performance MTJs.
* IHS iSuppli Market Research

Development of high sensitive magnetic sensors using magnetic tunnel junctions

A

Industry – Academic CollaborationA

Spintronics LSI Technology

R&D of technologies to automatically design environments
for low-energy consumption and highly functional
VLSI processors based on non-volatile memory

Prof.

Takahiro Hanyu

Associate Prof.

Daisuke Suzuki

1. Development of a CAD environment for NV-FPGAs
FPGAs (Field-Programmable Gate Array) is a
attractive hardware platform for various applications. We
have been establishing the environment by combining
an open-source CAD tool, called Verilog-to-Routing(VTR), with nonvolatile logic-circuit IPs.
2. Development of a NV-based circuit IPs
We have also been developing logic circuit IPs forrealizing a further energy-efficient/highly functional
NV-FPGA.

It is expected that the NV-FPGA is utilized in a wide
variety of applications such as IoT and mobile devices.

5

Spintronics System Technology

Research and development on embedded
security technology

To overcome a power-wall problem in 4x-nm CMOS era and beyond, our R&D project aims to develop nonvolatile (NV)-device-based
logic-circuit Intellectual Properties (IPs) and its automatic design environment. The actual development items are as follows:

3. Applications to AI accelerators
As an effective application, we have been developing
NV-FPGA-based energy-efficient AI accelerator.

Industry – Academic Collaboration

Figure: Example of an automatic circuit-design CAD environment based on high-level synthesis(C language). Utilizing C-language-based design assets, it is possible to design nonvolatile logic
circuits/VLSI processors. As a result, it could become easy to explore the optimal design architecture
for AI accelerators.

This R&D project aims to study
emerging security technologies for IoT(Internet of Things) where numerous andvarious devices are connected to network.
In particular, we study device security andremote authentication technologies forM2M (machine-to-machine) communication.
The study for device security includes
implementation technologies of confidential
communication and authentication underlimited resource and power supply. In
contrast, the study for remote authentication
includes efficient entity authentication
technologies between terminal(s) andserver(s)/terminal(s). By the above studies,
we expect to establish fundamental
technologies for connecting various
devices in a safe manner to the cyber
space.

Prof.

Takafumi Aoki

Implementation security evaluation for M2M devices

Prof.

Naofumi Homma

Prototype application of remote authentication between terminaland server

6

A

Industry – Academic CollaborationA

Spintronics System Technology

Industry – Academic Collaboration

AI Hardware Circuit Technology

R&D of error correction technologies
in flexible information processing

R&D of a VLSI platform for real-world intelligent
integrated systems

Prof.

Prof.

Tetsuo Endoh

Tetsuo Endoh

In DRAMs and other storage devices, cosmic rays, temperature conditions, and other factors can cause the storage bits to flip,
resulting in incorrect calculation results. ECC (Error Correction Code) technology has been developed to detect and correct theseerrors, by converting the original data into an error correction code with redundancy, which can detect errors and restore the originaldata. However, in order to increase the correction capability (i.e., to detect and correct more errors), a large amount of redundancy isrequired to match the capability (Fig. 1).
ECC technology is also used in “memory”, an important component in computers, and in particular, memory that has an ECC
circuit implemented as hardware is called ECC memory (Fig.2). Normally, the ECC algorithm called "SECDED", which is capable ofcorrecting 1-bit errors and detecting 2-bit errors, has been commonly used in ECC memory. In this study, we have been exploring andverifying not only SECDED, but also the most suitable ECC algorithm with high correction capability for STT-MRAM based on software,
which is easy to implement and improve by trial and error. The BCH code can select the number of bits that can be corrected undercertain constraints. On the other hand, Golay codes can detect and correct errors and recover data with a simpler calculation than BCH
codes, although the code length and the number of correctable bits are fixed.

The aim of our project is to develop a new reconfigurable
LSI with low power, high performance and high soft-error
tolerance for real-world intelligent systems, big-data
a p p l i c a t i o n s a n d i n f r a s t r u c t u re a p p l i c a t i o n s . F o rstate-of-art process technologies with smaller featuresizes, 3-D integration and an ultra low supply voltage, wedevelop synchronous/asynchronous hybrid circuits withautonomous supply-voltage control, MRAM-based nonvolatile logic circuits for low stand-by leakage power andhigh soft-error tolerance, and high-level design tools thatallow us to exploit easily reconfigurable LSI applications
using these advanced circuit technologies.

Computer architecture by ultra-low-power reconfigurable
LSI (FPGA) based on non-volatile logic with fine-grain power-control capability

A

Industry – Academic Collaboration

Fig.1 The horizontal and vertical axes
are "code rate" and "the maximum
number of correctable bits over code
length", respectively. There is a tradeoff relationship between the both. Anyerror-correcting code is never beyond
the theoretical bound, called Singleton
Bound.

Fig. 2 A schematic figure of ECC Memory. The device can correct error bits in data and send theright data to the system, thanks to redundant bits included within the data.

1RQYRODWLOH)3*$

A

AI Hardware Circuit Technology

Prof.

Prof.

Tetsuo Endoh

Tetsuo Endoh［Learning］

Conventional （Offline learning）［Reasoning （on the spot）］
AI chip

Learning
using GPU
Data for learning

Data on the spot

Learned network weighting
Recognition accuracy is decreased by the difference of
the acquisition conditions between learning and reasoning.
AI chip available for online learning （Target of this R&D）
［Learning and Reasoning］
AI chip

Data on the spot
Both learning and reasoning are using the data on the spot
Recognition accuracy is not decreased !

data
nism

7

AI Hardware Circuit Technology

R&D of MTJ/CMOS Hybrid
AI application processors

R&D of brain-type processing
circuit technologies
In this research and development, we have developed edge
AI processors with low power consumption and high speed
which are important for Society5.0.
In the conventional edge AI processors, after learning
process which has been performed offline using GPU, learned
parameter data have been used for inference process of AI chip.
Generally, since the data acquisition conditions at inference (onthe spot) are different with those at learning, the recognition
accuracy of AI chip is always decreased.
In order to solve this problem, we have researched anddeveloped the architecture / circuit / device technologies of thehigh-accuracy and ultra-high-speed edge AI processors which
can learn and make an inference on the spot. MRAM attracts
attention as nonvolatile memory, so we establish a base in thearchitectures / circuits to utilize MRAM thoroughly, and continue
to develop the system-level fine-grain power gating, the highefficiency data transfer mechanism to dissolve data transfer
bottleneck, the circuits / devices of MRAM suitable for uses, andthe novel AI processor architectures with offline/online learning.

Industry – Academic Collaboration

Advances in deep learning (DL) technology and parallel processors (e.g., GPUs) that can perform large-scale operations at highspeed have made it possible to achieve highly accurate and fast object recognition, which was difficult until now (Figure 1). However,while these processors are capable of high-speed computation, they also consume a lot of power for accessing storage circuits, so it isnecessary to reduce power consumption when installing them in in-vehicle computers and edge devices. Power consumption reduction
can be expected by compressing and optimizing the DL algorithm. Furthermore, by applying power gating (PG), which takes advantageof the non-volatility of MTJ/CMOS hybrid circuits, power consumption reduction can be expected from power reduction during memory
circuit access.
Therefore, we are developing a scheme to analyze the performance (recognition accuracy, speed, and memory access patterns) for
DL algorithms running on various hardware (Figure 2). By analyzing memory patterns and improving algorithms suitable for PG, we aim
to develop DL algorithms that match MTJ/CMOS hybrid circuit technology.
Fig.1 Object detection
results recognized
by one of famousalgorithms, YOLOv3.
The algorithm can detect
small objects in the
picture.

Fig. 2 A scheme of performance analysis of DL model selected from Model Zoo, being executed on CPU/GPU/
FPGA. The analysis includes detection accuracy, speed and memory performance analysis, though which we try
to select suitable DL models, and modify algorithm of those as well.

8

A

Industry – Academic Collaboration

A

Power Electronics Module Technology

A

Industry – Academic Collaboration

Prof.

Prof.

Yoshikazu Takahashi Tetsuo EndohProf.

Associate Prof.

Prof.

Power Electronics Circuit Technology

R&D of next-generation high-power
converters for power and industry

Research and development of next-generationelectrical equipment technology
Prof.

9

Industry – Academic Collaboration

Prof.

Yoshikazu Takahashi Tetsuo EndohIn this research theme, industry and academia collaborate on
research and development of assembly integration technologies to takeadvantage of the superior characteristics of new WBG devices such
as GaN-on-Si and SiC. This contributes to reducing the size, weight,
functionality, and performance of power electronics equipment.
We are developing the following technologies.
1. Passive component technology
Development of low loss / ultra-small reactor and transformer
technology with low iron loss and copper loss even when driving athigh frequencies, and development of capacitor technology that canwithstand high temperatures of 250 degrees or higher.
2. Power integrity technology
and high heat dissipation layout technology
Development of power integrity technology for various PCB substrates
applied to high integration density power electronics circuits.
Development of high heat dissipation layout technology that does notincrease chip temperature at high frequency
3. Bonding materials and technology
Development of low thermal resistance and high reliability bonding
materials and technology for assembling GaN on Si devices, gatecircuits, and various passive components on insulating substrates andcooling structures.

A

Power Electronics Equipment Technology

In this research theme, industry and academia are researching anddeveloping DC-DC converters using GaN on Si lateral power devices thatcan be driven at high frequencies.
This contributes to the realization of a highly efficient and ultracompact DC-DC converter that can handle the increased power supply
due to the increase in the number of sensors and actuators associatedwith the progress of automated driving in automobiles.
We are developing the following technologies.
1. High-frequency drive technology for DC-DC converters
Development of high-frequency drive technology using ultra-highspeed GaN on Si lateral power devices that enables downsizing ofpassive components such as passive components such as isolationtransformers, reactors, and capacitors in DC-DC converter.
2. Low noise technology
Reduction of noise filter (miniaturization of DC-DC converter) bydriving DC-DC converter at high frequency (2MHz or higher) above AM
radio frequency band, and development of optimum driving technology
to suppress ringing noise.
3. High power technology
Development of parallel connection operation technology andmultiphase operation technology for GaN on Si devices

Power Electronics integration Technology

R & D on assembly integration technology

Research and Development of WBG Power
Module Technology
In this research theme, industry-academia collaboration is underway
to develop power module technology that maximizes the features of widebandgap (WBG) power devices such as SiC-MOSFETs and GaN on Si
lateral power devices, which combine low loss and high speed. This willcontribute to the realization of high-performance electric vehicles (EVs),
compact and high-efficiency power supplies for data centers, and smart
cities that optimize power supply operations.
Following technologies are being developed.
1. Voltage and current oscillation suppression technology
for WBG power modules
Development of low-inductance module technology to suppress
voltage and current oscillation and spike voltage during switching
while taking advantage of the high-speed performance of WBG powerdevices.
Development of active gate drive circuit technology.
2. low thermal resistance technology
Development of high thermal conductivity insulating substratetechnology to suppress temperature rise during high frequency
operation of WBG power chips, which are becoming smaller and higher
power density.
3. high heat dissipation technology
Development of new air-cooled and water-cooled cooler
technologies to cope with the increasing capacity of WBG powerdevices.

Industry – Academic Collaboration

Prof.

Yoshikazu Takahashi Tetsuo Endoh

Shuji Katoh

In this R & D, with a view to contributing to the mass introductionof renewable energy and electrification, we are developing circuits andcontrol technologies for high-power converters. The converters are for1) PCSs for wind power generation and solar power generation, etc.
2) The various power equipment installed in factories, large construction
machines, ships and EVs etc.

Tetsuo Endoh

Industries
Railways
Data centers
EV stations

Power converters can be increased in output power by connecting
multiple small converters cascaded in series using multi-level technology.
Such multi-level converters can output sine-wave voltages with low.
Specifically, the following technologies has been being developed.
( i ) Circuit and control technologies to significantly reduce the size and lossof multi-level converters(ii) Circuit and control technologies to improve the robustness of multilevel
converters

SupplyBalancing

Demand0XOWLOHYHO&RQYHUWHU
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10

B

National ProjectB

MEXT Initiative to Establish Next-generation Novel Integrated Circuits Centers (X-NICS)

Innovative spintronics X semiconductor research hub
We will put spintronics, which is a game change technology for low-power integrated circuits led by Japan, at
the core. We will comprehensively conduct from R&D of new materials and devices, R&D of circuits, architectures andintegrated technologies that bring out their characteristics, to prototype verification for low-power semiconductor chipsthat accelerate the development of CMOS semiconductors with collaborative and cooperating organizations. While
promoting this activity, we will lead the creation of new science and the transformation of the information society bycultivating the fusion area of electronics with light / neuro / topology, and pioneering new applications such as medicalcare, space, and information security, and then contribute to the improvement of our research and development
capabilities related to semiconductors. We have young researchers and students actively and strategically participate
in this hub, and develop human resources who have the practical ability and a bird's-eye view.
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Overview of the hub concept

B

National ProjectNEDO

NEDO Project for Research and Development of Enhanced Infrastructures
for Post 5G Information and Communications Systems
Prof.

Tetsuo Endoh

Photonics-electronic convergence interface memory module technology
Prof.

Endoh
Tohoku University will participate in a project as a subcontractor after the "Photonics-electronic convergence interfaceTetsuo
memorymodule technology" jointly proposed by Kioxia
Corporation
andNTT wasadoptedin NEDO Project
Research andconvergence
DevelopmentofTohokuUniversity will
participate
in a project
as a subcontractor
after thefor"Photonics-electronicinterfacememory module technology" jointly proposed by Kioxia Corporation and NTT was adopted in NEDO Project for Research
Enhanced Infrastructures for Post 5G Information
and Communications Systems.
and Development of Enhanced Infrastructures for Post 5G Information and Communications Systems.
the IOWN
promoted by
In the IOWN initiative promoted byInNTT,
datainitiative
centersNTT,
data
centers
requireData center scalerequire disaggregated computing, whichconnects computing,multiple which
disaggregated
R&D area for this project
connects
multiplecomputingresources
computing resources (such as CPUs and GPUs) directly to optical
Optical interconnect(such as CPUs and GPUs) directly to
Optical chiplet
High
Bandwidthinterconnects in order to efficiently processopticala wideinterconnects
variety of realin order to Optical chiplet
Memory Controller
Buffer(Memory
efficiently process a wide variety ofMemoryServing Unit)
time requests from multiple users. Additionally,
memoryreal-time requests
frommust
multiple users.
Additionally,
memory usage
must be shared
Optical disaggregated environment
be shared by multiple computing resources
to improveby multiple computing resources to
Directly connected optical CPU pools, FPGA pools, memory pools, etc.
efficiency.
improve usage efficiency.
In this technology development,
R&D Items
In this technology development, Tohoku
University
has- High bandwidth compatible memory controller (Memory Serving Unit)
Tohoku University has subcontracted- High bandwidth buffer memory
part of the technology
development of
subcontracted part of the technology developmentof photonic- Packaging technology
photonic fabric attached memory
Memory module that can be directly
Features of this project
fabric attached memory module (PFAM), whichconnected to optical interconnect
module realizes(PFAM), memorywhichrealizes- Optical communication bandwidth of 512Gbps or morememory that can be accessed by- 30% lower power consumption compared to conventionalthat can be accessed by broadband opticalaccess from multiple
broadband optical access from multiple
computingresourcesvia
opticalcomputing resources via optical interconnect.

interconnect.

11

R&D Director (TEL)

Prof.

Prof.

Prof.

Takashi Hayakawa Shoji Ikeda

National Project

NEDO

Development of technology for designing energyefficient AI semiconductor chips and systems

Development of design technology to accelerate industrial application of
AI edge computing

Development of advanced semiconductor manufacturing technology

Development of advanced semiconductor manufacturing technology

Research and development of microfabricationcore technologies for nonvolatile MRAM at
1.5nm node and beyond

B

Project for Research and Development of Enhanced Infrastructures
for Post 5G Information and Communications Systems

Photonics-electronic convergence interface
memory module technology

Project for Research and Development of Enhanced Infrastructures
for Post 5G Information and Communications Systems

In order to achieve low latency in the post-5G era for edge-side systems
such as smartphones and IoT/AI processors, high performance edge
computing is necessary under the power supply limitation environment.
However, the dilemma of power consumption and computing performance
will continue to be an issue in the development of technologies beyond the
1.5nm node, which is an extension of conventional silicon technologies.
As a result, there will be limitations in advancing the performance of edge
systems and expanding their business fields.
In this theme, research and development of microfabrication technology
for nonvolatile MRAM at the 1.5nm node and beyond will contribute toovercoming the dilemma between power consumption and computing
performance by reducing power consumption through nonvolatility andminiaturization based on MRAM/CMOS hybrid LSI technology. This will
enable the realization of edge-side systems with low power consumption
and low latency for the post-5G era, and contribute to carbon neutrality as asynergistic effect of its social implementation.
Based on the following, we are developing fundamental microfabrication
technologies for nonvolatile MRAM for the semiconductor process 1.5nm
node and beyond;Tokyo Electron Limited (TEL): Development of core technology for RIE
etching at MTJ pitch for the 1.5nm node and beyond
Tohoku University, CIES: Processes development, fabrication, andevaluation to verify the developed RIE technology

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Prof.

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3URFHVV

1HZDSSOLFDWLRQNational Project

Design efficiency of AI processing
semiconductors by CMOS/spintronicshybrid technology and its applications
The research project on "Design efficiency of AI processing
semiconductors by CMOS/spintronics-hybrid technology and its
applications (principal investigator: Tohoku University; representative:
prof. Takahiro Hanyu)" proposed in 2022 was accepted by the newenergy and industrial technology development organization (NEDO). The
project was adopted by NEDO for "development of AI chips and nextgeneration computing technology enabling high-efficiency and highspeed processing / development of design technology to accelerateindustrial application of AI edge computing".
The current AI processing handles a large amount of data andrequires high-speed computation, which results in huge power
consumption. In particular, since the allowable power consumption
is limited at the edge, innovative and power-efficient AI computing
technologies are desired.
This research aims to develop a high power-efficient computing
technology suitable for edge AI that maximizes the characteristics of
CMOS technology, which is currently the mainstream, and spintronics
technology, which is highly compatible, non-volatile, and areaefficient, by integrating these technologies. In addition, as its social
implementation, we will apply the technology to in-vehicle systems andto next-generation surveillance systems such as watchdog systems.

Prof.

Takahiro Hanyu

Edge surveillance systems

Ko Yoshikawa

Shoji Ikeda

In-vehicle systems

12

B

National Project

B

JAXA Space Exploration Innovation Hub

Standby power-free system by MTJ/CMOS
hybrid technologies and its environmental
tolerance test (for space application)

National ProjectProf.

Tetsuo Endoh

Associate Prof. (JAXA)

Daisuke Kobayashi

13

National Project

Yoshikazu Takahashi

Fig.1 R&D system for integrated power electronics to realize a decarbonized society.

Cabinet Office Cross-ministerial Strategic Innovation Promotion Program (SIP) 3rd

Intelligent power electronics system with USPM
to support grid stabilization

Research Center Formation Project - A. Advanced Center Formation Type -This research theme proposing a new verticaldevice by integrating current spintronics technology
with two-dimensional materials in order to createnext-generation spintronics technology. The aim is
to integrate distinctive research from Japan, the UK,
France, and the US.
1. Japan-UK collaboration
The University of Cambridge in the UK has worldclass film production technology and theoreticalanalysis for two-dimensional materials.
2. Japan-France cooperation
France's CNRS/Thales has been establishedspintronics basic theory, led by Dr. A. Fert, who won
the Nobel Prize in Physics in 2007. In this research,
we will contribute to the creation of new spintronic
devices using advanced microfabrication facility for
two-dimensional materials.
3. Japan-US cooperation
Japanese team collaborate with Stanford
University on biosensing research field as a new
application possibility for spintronics devices.

Prof.

This research theme aims to research and develop
circuit systems that take full advantage of the superior
performance of WBG devices to the limit, and torealize smaller size, higher performance, higher power
density, and higher efficiency in next-generation
inverters and power supplies through the developmentof ultra-compact, high-performance power modules,
power unit and the application of optimal passive
components.
Applied products include motor drive inverters for
EVs, small and medium-sized inverters for industrialuse, and power supplies for data centers, which arewidely used in society to handle small and medium
power ranges.
Tohoku University, which is the representative
institution, Ibaraki University and Waseda University,
which are research-sharing institutions, and anadvisory board as a cooperating company will
promote research and development on five subthemes that are important for power electronics
research.
By advancing these research and development
efforts, we will create next-generation powerelectronics technologies and products that willlead the world and contribute to the realization of adecarbonized society.

B

Core to core project"Spintronics/Vertical elements of
two-dimensional materials"

MEXT Research and Development of Basic Technologies for Creating Innovative Power Electronics

Research and development of integrated power electronics
for the realization of a decarbonized society

A research proposal “Standby-power-free system by MTJ/CMOS hybrid technology and its environmental resistance test (for space
applications)” by CIES, Tohoku University in FY2019 was selected for the request for proposal (RFP) by the JAXA Space Exploration Innovation
Hub to expand “the human sphere of life and active area by exploring the solar system frontier”. The project was selected as a follow-up research
in FY2021, and is accelerating research and development.
For space exploration beyond Moon and Mars, long-term missions of more than 10 years are expected in environments where solar energy is
weak, so ultra-low power electronic systems that cannot be achieved with existing technologies is required. Another important issue forspacecraft electronic systems is the need for both standby power and space radiation resistance.
In this proposal, we will research a systemthat does not require standby power using
MTJ/CMOS hybrid technology that integrates
CMOS technology and MTJ, which is a spintronic
device developed by us. We aim to realize
innovative semiconductor devices and integrated
circuits that improve efficiency and reduce power
consumption by orders of magnitude. Specifically,
we will conducted the research on the materials
for higher performance and higher reliability, andthe MTJ/CMOS hybrid devices/circuits/integration
process/chip technologies.
Based on the reliability evaluation including
radiation tolerance test by JAXA, we aim to createa p o w e r- f r e e i n t e g r a t e d c i r c u i t t h a t h a senvironmental tolerance in addition to thenon-volatility and high speed in MTJ/CMOS hybrid
chips. This contributes to the solution of theresearch theme “Research on Standby Powerless
Research on standby power-free information processing systemwith radiation tolerance using MTJ/CMOS hybrid technology
Systems” specified by JAXA.

B

National ProjectProf.

Tetsuo EndohProf.

Associate Prof.

Hiroshi Naganuma

This R&D aims to develop elemental technologies for next-generationhigh power density USPMs with a wide range of energy management(EMS) applications and grid stabilization functions, as well as application
technologies for smart inverters and smart power supplies. Nagaoka
University of Technology is the lead organization for this research anddevelopment, and Tohoku University CIES is in charge of developing
reliability-enhancing technologies for next-generation USPMs throughoptimal packaging technology as a joint research institute. Specifically, we
are working to suppress jump voltage and reduce noise during switchingby reducing the inductance of power device packages applied to nextgeneration USPMs, and to achieve high integration with gate circuits
and passive components in pursuit of a compact and easy-to-handle
structure. In addition, in order for the next-generation USPM to contributeto the stabilization of the power system, it is necessary to respond tosynchronization and pseudo-inertia forces as a grid-forming inverter.
We will conduct research and development on package structures andgate drive methods that enable suppression of heat generation andtemperature rise and overvoltage suppression of power semiconductor
chips during high-current operation, which are essential for improving
the synchronization and pseudo-inertia of next-generation USPMs. By
advancing these R&D activities, we will contribute to the constructionof intelligent power electronics systems with USPMs that support gridstabilization.

Associate Prof.

Yoshikazu Takahashi Shuji Katoh

14

C

D

J-Innovation HUB (International Development Category)

Activities for J-Innovation HUB initiative(International development category)Community-based Cooperation Project

Tohoku Semiconductor Electronics Design ConsortiumProf.

Tetsuo Endoh

CIES was selected as the 1st industry-academia base of the‶J-Innovation HUB Initiative″, a project of the Ministry of Economy,
Trade and Industry (METI) launched in 2020 (International development
category).
Under this initiative, METI targets regional innovation hubs
(mainly universities), and assesses and selects outstanding industryacademia bases that are playing a leading role as hubs for networks ofcompanies. The aim is to enhance their creditworthiness, focus public
support measures on them, and enhance the capabilities of the topranking hubs. METI selects the hubs in two categories: the international
development category and the regional contribution category.
METI will advance dialogues with each of the selected hubs and will
provide them with tailor-made support measures, including budgets andrelaxation of regulations.
Partners participating in the activities of CIES are expected to takeadvantage of the preferential treatment of this J-Innovation HUB policy.

Global enterprises

Prof.

● The Tohoku Study Group on the Design of Semiconductor and Electronics Industry was formed in the aim ofdeveloping semiconductor related industries in Tohoku and Japan through strengthening their competitiveness.
● The main agenda for the group is as follows: (1) human resource development, (2) resilience of supply chains,and (3) promotion of research and development (R&D).

<Date of establishment>
June 10, 2022 (The 1st meeting: July 4, 2022)
https://www.tohoku.meti.go.jp/s_monozukuri/mono_hando.html

Companies outside
the region<Members>(1) Semiconductor and related industries(2) Universities, NITs, AIST, etc.
(3) Economic associations(4) Government agencies

Regional companies andmunicipalities

99 companies and organizations participate in total.
(as of 2024.1.5)

International development category Hub

Source: Tohoku Bureau of Economy, Trade and Industry(Source: Ministry of Economy, Trade and Industry)D

Community-based Cooperation Project

Integrated Electronics

Car Electronics

PromotionＣof regional cooperation in
integrated electronics
car Cooperationelectronicsinfields
Promotion ofand
Regional
Community-based Cooperation Project

The Semiconductor Technology Co-creation Center

Toward Japan’s largest semiconductor R&D ecosystem

Integrated Electronics and Car Electronics Projects

Integrated Electronics and Car Electronics

Prof.

TetsuoProf. Endoh

This activity aims to spread excellent core technologies of local
Tetsuo Endoh
This activity aims to spread excellent core technologies ofcompanies to the worldwithcooperationof
local
government
andlocal companies to the world with cooperation of local
Iwate Manufacturing
Iwate Semiconductor andAutomotive Industry
Electronics Industry Promotion
administrative agencies.
In particular,
the following
activities
have thegovernment
and administrative
agencies.
In particular,
Promotion Room
Conference
following activities have been promoted.
Tohoku Stuｄｄy Group Design ofbeen promoted.
Semiconductor and Electronics Industry
1)
Sophisticate core technologies of local companies by1) Sophisticate core technologies
of local companies by integrating
Technology Matching
Sendai
Ｍｉｙａｇｉ
integrating fundamental technologies and scientificIndustrial
New Industry
Meti Tohoku
Promotion Division
Promotion Division
fundamental technologiesknowledge
and scientificknowledge of CIES;
Meetingof CIES;MiyagiAdvancedElectronics
About
Companies2) D evelop cooperationcompanies
electronics～a place to meet～2) among
Develop local
cooperation
among in
local
companies in
And Machinery Industry
Association
1700 participate
electronics
field, and apply
the core
and automotive field, andapply andtheautomotive
core technologies
to new
Miyagi Automotive Industry
to new ofapplication,
and work on in
study
application, and work ontechnologies
study meeting
commercialization
Promotion Council
meeting of commercialization in cooperation with Miyagi
cooperation with Miyagi and Iwate Prefectural Government ;<Seedsof
Local
Companies>
and Iwate Prefectural Government ;<Seeds of CIES> Unique and core technologies
3) Promote cooperation3)between
companies
ｄvanced core technologies
Promote local
cooperation
betweenandlocalworld-classcompanies and  Aｄ
<Needs of local Companies>
companies at CIES as world-classa place tomeet, atandcoreand  Scientific deep understaning
companies
CIESspread
as a placethe
to meet, Few chance of finding customers forof CIES>possessing technologies
spread theto
core
technologies of local companies
thetechnologies
world. of local companies to the <Needs
 Technological issues that High barriers to enter newworld.
CIES
consortium
members
technologies
Under these activities, unique core technologies by local
bring to CIES
 Insufficient resource for scientific
Under these activities, unique core technologies by local
understanding
companies will be applied to integrated electronics and carcompanies will be applied to integrated electronics and car
electronics, and the application
andcommercializationoftheelectronics, and the application and commercialization of the
Basic policy of the Community-based cooperation
Basic policyof the Community-based cooperation
innovative devices will bepromoted
towillnext
generationof IT
and carof IT
innovative
devices
be promoted
to next
generation
andcarelectronics.
electronics.
will continue to contribute to Tohoku promotion.
CIES will continue CIES
to contributeto Tohoku promotion.

CIES

15

Tetsuo Endoh〇 Background and purpose
In order to contribute to strengthening the international
competitiveness of Japan's semiconductor industry, the Tohoku
University Semiconductor Technology Co-Create center willleverage its openness as a university to share the university's
diverse results with various institutions, creating synergies andbuilding an R&D ecosystem.
〇 Initiative details and effects
This co-creation organization has three hubs, and we,
center for innovation integrated Electronics systems is one ofthem, as a “Hub for Spintronics Low Power Semiconductor”.
We are responsible for the design, prototype demonstration,and evaluation of next-generation memory MRAM, as well as
its system development. In addition, Tohoku University has the“Hub for Semiconductor Manufacturing Process, Parts, Material
and Image Sensors” based on ultra-clean process technology
and image sensor technology and the “Hub for MEMS Design
and Process,” which is responsible for R&D, technical evaluation,and prototyping of various devices and advanced packaging
technologies. We collaborates with these two centers to leadsemiconductor research in Japan.
https://semicon.tohoku.ac.jp/en/

high density memory, high performance processors

16

MEXT Initiative to Establish Next-generation Novel Integrated Circuits Centers (X-NICS)MEXT Initiative to Establish Next-generation Novel Integrated Circuits Centers (X-NICS)

Semiconductor Human Resource Development
at Innovative Spintronics X Semiconductor Research Hub

X-nics industry-academia collaboration seminar in 2023
We aim to develop human resources
who have a bird's-eye view of thetechnology value chain of semiconductor
integrated circuits, from materials,
elements, design, circuits, architecture,
integration technology, prototyping,evaluation, and systemization while
deepening our own core technologies
and specialized fields. We also aim todevelop human resources with businesssense and planning ability by utilizing
practical education provided by partnercompanies. Furthermore, in addition
to educating students, we are also
working on recurrent human resource
development of young teachers andengineers.

Technology and IP for automotive semiconductors, etc.
Electrical industry and its IP strategy
Future created by semiconductors
Towards transformation into mobility company
Changes in car society and challenges for automotive semiconductors
Beauty of NAND
Computing platform that accelerates AI
Beyond 5G technology
Forefront of flash memory
SoC and OS transition and outlook for IVI
Power semiconductor module packaging technology that contributes to CN
Technology trends in advanced packaging
Computing & Memory

Sumitomo Electric Industries
Panasonic
JEITA
Toyota Motor
DENSO
Western DigitalNECNICTKIOXIAAISIN
FUJI ELECTRIC
ResonacIntel

Advanced Human Resource Development Program

The following programs have been implemented with the objective of developing
young research resources in the field of integrated electronics technology.
●RA System within X-nics① Lectures and curriculum delivered by industry-academia
Human resources with business sense and an overview of the entire
joint faculties (credit courses)

technological value chain of semiconductor integrated circuits, including
materials, devices, design, circuits, architecture, integration technology,
prototyping, evaluation, and systemization, who can also deepen their own
understanding of core technologies and specialized fields.

In these courses, we explain the types of talents required in industry
sectors and society as a whole, create curriculum based on those principles,and offer lectures by members of industry-academia joint faculties.

② Participating in Tohoku Semiconductor Electronics Design
Consortium

We participate in Tohoku Semiconductor Electronics Design
Consortium responsible for the human resource development etc. in
Tohoku established by Ministry of Economy, Trade and Industry.

③ Industry-academia collaboration OJT system promoting
advanced human resource development●Internship system

A promotion system has been organized targeting doctoral course
students (DCs), post-doctoral fellows (PDs), and young faculties etc.,
to help to take part in internships at companies participating in CIES
consortium.

④ Participating in University program●RA system within the CIES consortium

We elucidate the responsibilities of people engaged in industryacademia collaborative research and aim to encourage graduate sudents/postdoctoral / young researchers to participate in industry-academia
collaborative research by providing compensation.

●Center for Science and Innovation in Spintronics (CSIS)In the certification of "Designated National University", the CSIS
is aiming to establish a hub that pioneers new field of "Spin-Centered
Science" in the world by strategically gathering outstanding researchers
through international collaborations.

●Center for Spintronics Research Network, Tohoku University (CSRN)The CSRN is aiming at the formation of research network hub topromote collaborative research with domestic and international institutes
for accelerating international competitiveness of world-leading spintronics
research, creating new industries, strengthening the current industry anddeveloping next generation human resources.

●Graduate Program in Spintronics, Tohoku University (GP-Spin)

This program aims to foster researchers who can play an active roleinternationally in spintronics area which is our strength research field.
This program is supervised by world leading professors including CIES
members.

●Tohoku Forum for Creativity

We participate in a university program that develop human resources
who can start a business or play an active role in a company through theresearch. The program cultivates not only fundamental business skills
like management and communication but also advanced skills like setting
issues and solving problems.

X-nics RA Students
Overview of Semiconductor Human Resource Development at Innovative Spintronics X Semiconductor Research Hub

Strategic Planning Division
Strategic planning division establishes flexible joint research frame workin order to operate it efficiently and actively, based on the world-class coretechnologies and experienced administration support.

Intellectual Property (IP), which are core IP and emerging new IP, can be

managed as our valuable asset and enable to provide them for consortium members
efficiently. Based on this new IP system, flexible and global standard joint researchcontracts are ready for domestic and overseas companies.

Strategic Planning Division

Facility Technology Division
Practical IP management

IP pool / share / acquired sub-systems

Contract

Flexible and global standard

Research planning

Attractive and sustainable topics

HR development

Internship with cooperated companies

Publicity

Public relations for networking

Facility technology division focuses on four main functions in order to achieve safety, stable, and efficient research anddevelopment. Not only gas and liquid leakage, particle sensor management, in/out security control for research zone, but also
24 hours monitoring of electricity, gas and water can provide safe and validity
research and development circumstance.
Facility management
300mm process line / Supply facilities
We operate a clean room with a 300mm wafer process line. Management
duties include daily inspections to ensure stable and safe operations. Maintenanceis carried out to ensure stable operation of the 300mm wafer process equipment
Research quipment management
installed in the clean room.
300mm process equipment / 300mm evaluation tools
As for ensuring safety, safety education is conducted to the facility andequipment users. To provide instruction and improve safety and health, we
Safety and healthestablished a safety and health committee, safety patrols, and evacuation drills.
Safety and health committee / Safety patrols /Evacuation drills
As for information security, we manage network security for informationequipment in CIES and also provide education to
Information security
facility and equipment users.
Facility Technology Division

17

Information control / Information leak control /Information security literacy

18

The center of excellence (COE) of academic-industrial alliancenetworking the world-wide intelligence and creating new knowledgeof humankind by innovative integrated electronics and sophisticatedtraining-based education

Graduate School of
Pharmaceutical
Science
Aobayama North Campus

Graduate School of Science

Miyagi University of Education
Tohoku University
Center for
Innovative Integrated
Electronic Systems

Energy Center

Frontier Research Institute forInterdisciplinary Sciences
Cyberscience Center

Animal Research
Facility
for Agricultural
Science

Aobayama
GroundAobayama East Campus

Graduate School ofGraduate School ofEngineering
Information
International Research
Sciences
Institute of Disaster Science
NORTH1
Sendai City Subway Tozai Line
Graduate School of
Aobayama Station
Environmental
Studies
SOUTH1
Aobayama Midori New Industry Creation Hatchery Center (NICHe) Annex
Welfare Facilities
Innovation Center for Creation of a Resilient Society

Multidisciplinary
Research Laboratory
for Agricultural Science

Aobayama Commons

Aobayama New Campus

Research Center for Rare Metal
and Green Innovation

Acces sBy Subway
Please take subway Tozai Line bound for “Yagiyama
Zoological Park Station” from “Sendai Station”, and get off
subway at “Aobayama Station”. (about 9 mins ride) Pleasego out from Exit South 1, and it is about 10 minutes’ walkfrom “Aobayama Station” to CIES.

Contact

Tohoku University
Center for Innovative Integrated
Electronic Systems

468-1 Aramaki Aza Aoba, Aoba-ku, Sendai,
Miyagi 980-8572, JAPANTEL: +81-22-796-3410 FAX: +81-22-796-3432
E-mail: support-oﬃce@cies.tohoku.ac.jp
HP：http://www.cies.tohoku.ac.jp/english/2023.3