DATASHEETADF-D3030
Dual 3.0 Gsps, 14-bit ADC and Dual 3.0 Gsps 16-bit DAC
FMC Module. VITA 57.1

BENEFITS Dual ADC/DAC on a Single FMC Module

The ADF-D3030 FMC module from DEG is a highly integrated, dual
channel ADC and dual channel DAC FMC module. The AD9208 fromAnalog Devices delivers 14 Bit resolution at sample rates of up to3.0 Gsps. The DAC is an Analog Devices AD9172. This 16 Bit DAC
device operates at 3.0 Gsps natively and up to 12.0 Gsps in interpolation mode. A VITA 57-compliant FPGA Mezzanine Card (FMC) interface, the ADF-D3030 offers industry-wide platform compatibility
with the PCIe/VME/VXS/VPX carrier board of your choice. The ADFD3030 and associated HDL firmware are compatible with Xilinx®
FPGA processors.

 Wide Dynamic Range for both ADC and DAC
 Convection and Conduction-Cooled Versions
 Enables SWaP-C Sensitive Systems: High Density, Small Footprint, Low PowerFEATURES
 Dual Channel 3.0 Gsps 14-bit ADC
 Dual Channel 3.0 Gsps 16-bit DAC : 12 GHz inInterpolation Mode JESD204B SERDES Interface: x 8 Lanes DAC andx8 Lanes ADC @ 15.0 Gbs per Lane Built-in Clock Jitter Cleaner

Flexible, cost-effective solution
By coupling this core architecture with the compact and flexible
FMC form factor, DEG has enabled customers to rapidly and costeffectively build compact systems with significant SWaP-C benefits.
By incorporating two channels of both high speed ADC and DAC ona single FMC module, high-channel density, wideband digital receivers can be incorporated into the latest generation of highperformance sensor and EW systems. This flexible approach reduces the overall power consumption and cost while increasing
ruggedness and reliability.
The ADF-D3030 is ideally suited for low latency EW applications andsignal intelligence systems that require wide dynamic range andhigh sensitivity.

 Four Internal Digital Down-Converters per ADC
ChannelPerformance

ADC PERFORMANCE Up to 5 GHz of usable analog input full power
bandwidth – AC Coupled.

The ADF-D3030 incorporates the JESD204B SERDES Interface standard. The ADC and DAC each utilizes 8 lanes to and from a carrierboard FPGA. Sustained data transfer rates of 15.0 Gbytes/sec. aresupported.

 ENOB = 9.5 effective bits, Fin = 765 MHz
 SNR = 58.8 db @ Fin = 765 MHz
 SFDR = 71 dB @ Fin = 765 MHz

www.delphieng.com

ADF-D3030 Performance Specification
ClocksThe ADF-D3030 provides an onboard synthesizer which covers
the entire ADC and DAC sampling range. Delphi incorporates aclock jitter cleaner on the ADF-D3030, which improves ADC
and DAC performance.

ADC Specifications
Number of ADC channels

2

Sampling Rate Options

2500 to 3100 Msps,
1900 to 2600 Msps
1300 to 2100 Msps

Input Bandwidth

3.0 GHz

Input Impedance

50 Ω, AC-coupled

SNR (typical)

58.8 dB @ Fin = 765 MHz

External Clock via front-panel clock input

SFDR (typical)

71.0 dB @ Fin = 765 MHzTrigger

ENOB (typical)

9.5 Bits @ Fin = 765 MHz

A trigger event is initiated by a positive transition. The trigger
threshold is software-controllable in a wide range. An autotrigger feature enables signal capture or synthesis without atrigger.

DAC Specifications

The following sources can be selected for the synthesizer:• External reference signal• Low noise onboard reference – 50 ppm accuracy over theentire temperature range of the product

ADCLink
Delphi’s ADCLink VHDL source code provides the specific ADC/DAC interface and control logic necessary to integrate withyour carrier board FPGA.
ADCLink capabilities include: onboard/external reference clock
control, trigger threshold control, and full control over ADC
and DAC devices.

Number of DAC channels

2Sampling rate

3.0 Gsps

Sampling rate

12.0 Gsps (w/Interpolation)

Output bandwidth

6.0 GHz

Output impedance

50 Ω, AC-coupled

Clock and Trigger Specifications
External Clock Input Freq.

3.0 - 12.0 GHz

Ext. Reference Clock Input10 MHz to 750 MHz

Trigger input

Single-ended 50 Ω

www.delphieng.com