Industrial PCIe Gen3 x4 M.2(2280)

Solid State Drive E-Series
DRAM LESS(SanDisk Bics4 3D-TLC)

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Industrial PCIe Gen3 x4 M.2(2280) SSD (3D-TLC)

Revision History
Revision

Description

Date

V1.0

New release

May 20222

May 202y V1.0

Industrial PCIe Gen3 x4 M.2(2280) SSD (3D-TLC)

Table of Contents
1. Product Description................................................................................................................4
1.1. Product Overview..................................................................................................................4
1.2. Product Features...................................................................................................................4
1.3. Specifications.......................................................................................................................5
1.4. Performance.......................................................................................................................5
1.5. TBW (Tera Bytes Written) ....................................................................................................6
1.6. System Requirement.............................................................................................................61.6.1. Power Requirement..........................................................................................................6
1.6.2.
Operating System.............................................................................................................62.
Detailed Specification...........................................................................................................7
2.1. Physical Specifications........................................................................................................72.1.1.
Overlook............................................................................................................................7
2.1.2.
Dimension.........................................................................................................................72.2. Electronic Specifications ....................................................................................................8
2.2.1.
Product Definition.............................................................................................................82.2.2.
Pin Signal Assignment...................................................................................................92.3. Support Commands............................................................................................................112.4. Shock & Vibration...............................................................................................................13
2.5. Error Detection and Correction.........................................................................................132.6. Wear-Leveling.....................................................................................................................132.7. Bad Blocks Management...................................................................................................132.8. Mean Time between Failures (MTBF)...............................................................................132.9. Endurance............................................................................................................................142.10. Transfer Mode.....................................................................................................................143.
Installation Requirements.................................................................................................14
3.1.
M.2 Pin Directions..............................................................................................................143.2.
Electrical Connections for M.2……..................................................................................14
3.3.
Device Drive………………………….................................................................................14

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1. Product Description
1.1. Product Overview'ADTEC PCIe Gen3 x4 M.2(2280)' is the storage device based on NAND flash memorytechnology.
This product complies with JEDEC standard form factor and PCIe/NVMe standard interface andsuitable for data storage media and code storage device for embedded system and boot disk.
By using M.2 SSD, it is possible to operate good performance for the systems, which have M.2
interface. With small form factor, the applicable appliance can add or install PCIe storage device
on its Mother Board or Complete set.

1.2. Product FeaturesHigh performance and reliability.
Small form factor with PCIe/NVMe Standard Interface connector (M.2).
Build-in Global Wear-leveling and Hardware Advanced LDPC ECC engine.
 Correct capability up to 350 bits per 2Kbytes.
Compliant with PCIe Gen3 up to 4-lanes support.
Memory Capacities
 3D-TLC: 120GB / 240GB / 480GB / 960GB



Data Security
 Build-In AES 256 encryption.
 TCG Opal 2.0 Compliant.
 Support SHA256










Support AHCI as well as NVMe.
Support S. M. A. R. T. function.
Support Intel CPPM total set.
Support SRiS for cable less.
Sudden power-fails management.
Noiseless and stable installation to system.
Silent, low-power operation. Resistant to shock and vibration.
Automatic sleep and wake-up mechanism to save power.
Operating as Boot Disk.
Supports Bad Block Management.
Fully Compliant with RoHS directive.
CE and FCC Compatibility.

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1.3. Specifications
Interface

PCIe Gen3 x4 compatible

NAND Flash Type

3D-TLC

Controller

ET7315

Form Factor

M.2 (NGFF) 2280

Connector Type

NVMe (75 pin)

Capacity

3D-TLC: 120GB / 240GB / 480GB / 960GB

Performance (Max)

Read: 3200MB/s, Write: 2500MB/s

Power Consumption (Max)< 7W

Operating Temperature

0˚C ~ +70˚C

Storage Temperature-40˚C ~ +85˚C

Humidity

0°C~55°C /95% RH

S.M.A.R.T (Health Monitor)

Yes

Dimension (L x W x H)

80 x 22 x 2.2mm
Table 1: M.2 PCIe SSD Specifications

1.4. Performance
Sequential
Sequential
Random(QD32)(512KB)(4KB)
Type Capacity
Read Write Read Write ReadWrite(MB/s) (MB/s) (MB/s) (MB/s) (IOPS) (IOPS)
120GB 1870.7 412.2 338.2 383.0 14546 50944
240GB 1793.4 659.3 507.4 415.9 12872 40218
3D-TLC
480GB 1716.1 1318.5 1014.8 831.8 11195 29466
960GB 1697.5 1540.0 809.0 848.7 10112 32998

Random(4KB QD32)
ReadWrite(IOPS) (IOPS)
86272
97792
93030
93261
99789
88730
104269 89779*Performance may vary based on SSD capacity, hardware test platform, test software, operating system and other system variables.

Table 2: M.2 PCIe SSD Performance

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1.5. TBW (Tera Bytes Written)
Capacity

TBW

120GB

80TB

240GB

160TB

480GB

320TB

960GB

640TB

Table 3: M.2 PCIe SSD TBW

1.6. System Requirement

The Host system which is connected to M.2 PCIe SSD should meet system requirements atminimum.
1.6.1. Power Requirement
Item

Input voltage

SymbolVIN

Rating+3.3V DC ± 5% 1000mA (max.)

Unit
V

Table 4: M.2 PCIe SSD Power Requirement

1.6.2. Operating System Windows family.
 Linux family.
 DOS or embedded system.

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2. Detailed Specification
2.1. Physical Specifications
2.1.1. Overlook

Figure 1: M.2 PCIe SSD Overlook Diagram

2.1.2. Dimension
The Dimensions of M.2 PCIe SSD are illustrated in Figure 2 and described in Table 6.

Figure 2: M.2 PCIe SSD Module Dimensions

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ParameterSpecifications

Width

22.0mm ± 0.15mm

Length80.0mm ± 0.15mm

Thickness

2.2mm ± 0.1mm

Table 6: M.2 PCIe SSD Module Physical Dimension

2.2. Electronic Specifications

2.2.1. Product Definition
M.2 PCIe SSD is designed to operate and work as Data or Code Storage device by NAND
Flash Memory and its Controller through PCIe/NVMe Standard Interface to Host Systems.

Figure 3: M.2 PCIe SSD Block Diagram

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2.2.2. Pin Signal Assignment
The signals assigned for PCIe/NVMe applications are described in Table 7.
PIN

Function

Description

PIN

Function

Description

74+3.3V

3.3V power

75

GNDGround72+3.3V

3.3V power

73GND

Ground70+3.3V

3.3V power

71

GND

Ground

DNC

69

DNCConnector Key

67

DNC

68

Connector Key

Connector KeyConnector KeyConnector KeyConnector KeyConnector Key

58

DNC

Connector Key

56

DNC

57

GND

Ground

54

DNC

55

REFCLKp

Reference clock p

52

CLKREQ#Clock request

53

REFCLKn

Reference clock n

50

PERST#

PCIe Fundamental Reset

51

GND

Ground

48

DNC

49

PERp0

PCIe RX Lane 0 p

46

DNC

47

PERn0

PCIe RX Lane 0 n

44

ALERT#

45

GND

Ground42

SMB_DATA

43

PETp0

PCIe TX Lane 0 p

40

AMB_CLK

41

PETn0PCIe TX Lane 0 n

38

DNC

39

GND

Ground

36

DNC

37

PERp1

PCIe RX Lane 1 p

34

DNC

35PERn1

PCIe RX Lane 1 n

32

DNC

33

GND

Ground30DNC

31PETp1

PCIe TX Lane 1 p

28

DNC

29

PETn1

PCIe TX Lane 1 n

26

DNC

27

GND

Ground

24

DNC

25

PERp2

PCIe RX Lane 2 p

22

DNC

23

PERn2

PCIe RX Lane 2 n

20

DNC

21

GND

Ground18+3.3V

3.3V power

19

PETp2

PCIe TX Lane 2 p

16+3.3V

3.3V power

17PETn2

PCIe TX Lane 2 n

14+3.3V

3.3V power

15

GND

Ground12+3.3V

3.3V power

13PERp3

PCIe RX Lane 3 p10

LED1#Status indicator for system LED

11PERn3

PCIe RX Lane 3 n

8DNC

9GND

Ground

6DNC

7PETp3

PCIe TX Lane 3 p

4+3.3V

3.3V power

5PETn3PCIe TX Lane 3 n2+3.3V

3.3V power

3

GND

Ground1GND

GroundTable 7: M.2 PCIe SSD connector pin definition

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Figure 4: M.2 PCIe SSD Connector Pin Assignment

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Industrial PCIe Gen3 x4 M.2(2280) SSD (3D-TLC)

2.3. Support Commands

Command Set summaries the command set with the paragraphs that follow describing
the individual commands and the task file for each.
CommandCodeProtocol90h
E7hECh91h
C8h
2Fh
C4h
20h

Device diagnostic
Non-data
PIO data-in
Non-data
DMA
PIO data-in
PIO data-in
PIO data-in

40h or 41h

Non-data

Set Feature
Set Multiple Mode
Write DMA

EFhC6hCAh

Non-data
Non-data
DMA

Write Multiple

C5h

PIO data-out

Write Sector(s)NOP30h00h

PIO data-out
Non-data

Read Buffer

E4h

PIO data-in

Write Buffer

E8h

PIO data-out

E5h or 98h
E3h or 97h
E1h or 95h
E6h or 99h
E2h or 96h
E0h or 94h

Non-data
Non-data
Non-data
Non-data
Non-data
Non-data

Security Set Password

F1h

PIO data-out

Security Unlock

F2h

PIO data-out

Security Erase Prepare
Security Erase Unit

F3h
F4h

Non-data
PIO data-out

Security Freeze Lock

F5h

Non-data

Security Disable Password

F6h

PIO data-out

General Feature Set

Execute Drive Diagnostic
Flush Cache
Identify Device
Initialize Drive Parameters
Read DMA
Read Log Ext
Read Multiple
Read Sector(s)Read Verify Sector(s)Power Management Feature Set
Check Power ModeIdle
Idle Immediate
SleepStandby
Standby Immediate

Security Mode Feature Set

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Industrial PCIe Gen3 x4 M.2(2280) SSD (3D-TLC)
CommandCodeProtocol

B0h
B0h
B0h
B0h
B0h
B0h
B0h
B0h
B0h
B0h

Non-data
Non-data
Non-data
Non-data
PIO data-in
PIO data-in
PIO data-in
Non-data
Non-data
PIO data-out

F8h
F9h
F9h
F9h
F9h
F9h

Non-data
Non-dataPIO data-out
Non-data
Non-data
PIO data-out

EAh24h
25h
29h
27h
42h
37h
35h
39h
34h

Non-data
PIO data-in
DMA
PIO data-in
Non-data
Non-data
Non-data
DMA
PIO data-out
PIO data-out

60h
61h

DMA Queued
DMA Queued

06h
70h

DMA
Non-data

SMART Feature Set
SMART Disable Operations
SMART Enable/Disable Autosave
SMART Enable Operations
SMART Execute OFF-LINE Immediate
SMART Read Log
SMART Read Data
SMART Read Threshold
SMART Return Status
SMART Save Attribute Values
SMART Write Log

Host Protected Area Feature Set
Read Native Max Address
Set Max AddressSet Max Set Password
Set Max Lock
Set Max Freeze Lock
Set Max Unlock

48-bit Address Feature Set
Flush Cache Ext
Read Sector(s) Ext
Read DMA Ext
Read Multiple Ext
Read Native Max Address Ext
Read Verify Sector(s) Ext
Set Max Address Ext
Write DMA Ext
Write Multiple Ext
Write Sector(s) Ext

NCQ Feature Set
Read FPDMA Queued
Write FPDMA Queued

OthersData Set Management
Seek

Table 8: Command List

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2.4. Shock & Vibration
ReliabilityVibration
Mechanical Shock

Test Conditions
10Hz to 2KHz, 20G, 3 axes
Duration: 0.5ms, 1500G, 3 axes

Reference Standards
IEC 68-2-6
IEC 68-2-27

Table 9: Shock/Vibration Testing for M.2 PCIe SSD

2.5. Error Detection and Correction

Highly sophisticated Error Correction Code algorithms are implemented. The ECC unit consistsof the Parity Unit (parity-byte generation) and the Syndrome Unit (syndrome-byte computation).
This unit implements a hardware LDPC ECC engine that can correct 350 bits per 2K bytes in an
ECC block. Code-byte generation during write operations, as well as error detection during readoperation, is implemented on the fly without any speed penalties.

2.6. Wear-LevelingFlash memory can be erased within a limited number of times. This number is called the erase
cycle limit or write endurance limit and is defined by the flash array vendor. The erase cycle limit
applies to each individual erase block in the flash device.
M.2 uses a ‘advanced wear-leveling’ algorithm to ensure that consecutive writes of a specificsector are not written physically to the same page/block in the flash. This spreads flash media
usage evenly across all pages, thereby extending flash lifetime.

2.7. Bad Blocks Management

Bad Blocks are blocks that contain one or more invalid bits whose reliability are not guaranteed.
The Bad Blocks may be presented while the SSD is shipped or may generate during the lifetimeof the SSD. When the Bad Blocks is detected, it will be flagged, and not be used anymore. TheSSD implement Bad Blocks management and replacement, Error Correct Code to avoid data
error occurred. The functions will be enabled automatically to transfer data from Bad Blocks tospare blocks, and correct error bit. After the reserved block less than 10 of each channel, theSSD will be locked, and cannot be read and written anymore. Host can send a vendor ATA
command to unlock the SSD for backup data or system from SSD.

2.8. Mean Time between Failures (MTBF)

Failure Rate: The total number of failures within an item population, divided by the total numberof life units expended by that population, during a particular measurement interval under statedcondition.
Mean Time between Failures (MTBF): A basic measure of reliability for repairable items: Themean number of life units during which all parts of the item perform within their specified limits,
during a particular measurement interval under stated conditions.

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Industrial PCIe Gen3 x4 M.2(2280) SSD (3D-TLC)
Product
M.2 PCIe SSDCondition
Telcordia SR-332 GB, 25°C

MTBF (Hours)>2,000,000

Table 10: M.2 PCIe SSD MTBF

2.9. EnduranceFlash Endurance: 3D-TLC: 3,000 P/E Cycle
Wear-Leveling Algorithm: Support.
Bad Blocks Management: Support.
Error Correct Code: Support.

2.10. Transfer Mode

M.2 PCIe SSD support following transfer mode: PCI-Express Gen-3 x4 Lane

3. Installation Requirements
3.1. M.2 Pin Directions

KEY M

Figure 5: Signal Segment and Power Segment

3.2. Electrical Connections for M.2

A PCIe/NVMe device may be directly connected to a host or connected to a host through anadaptor card.

3.3. Device Drive

No additional device drives are required. The M.2 can be configured as a boot device.

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4. Ordering Information
P/N

Capacity

AD80P3120G3DCENES

120GB

AD80P3240G3DCENES

240GBAD80P3480G3DCENES

480GB

AD80P3960G3DCENES

960GB

15Remark
SanDisk Bics4 3D-TLC
Normal Temp

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