High-Power GaN HFETs on Si Substrateby Nariaki Ikeda *, Jiang Li *, Kazuo Kato *, Shuusuke Kaya *,Toshiaki Kazama *, Takuya Kokawa *, Yoshihiro Sato *, Masayuki Iwami *,Takehiko Nomura *, Mitsuru Masuda *2 and Sadahiro Kato *Epitaxial growth technology for GaN devices on large-diameter Si substrate has
been studied in this paper, which is essential for device cost reduction. In aneffort to improve the buffer breakdown voltage for increasing the breakdown voltage of thedevice, carbon concentration in the GaN layer is controlled to find that the carbon concentration
significantly contributed to buffer breakdown voltage improvements. Device performance isevaluated for the devices with an AlGaN/GaN HFET structure on Si substrate, and it is shownthat the performance was equivalent to that of the device on sapphire substrate. A large-area
device having this structure is fabricated in order to confirm its potential as a power device, anda current capacity of 120 A or more and a breakdown voltage of 1.3 kV has been achieved. On
the other hand, with respect to the problematical issue of current collapse in GaN HFETs, the
HFET structure on Si substrate has resulted in a significant improvement compared with thestructure on sapphire substrate, thus realizing a high-performance device that does not show asalient current collapse up to 900 V.

ABSTRACT1.

INTRODUCTION

The device development of GaN, a wide bandgap semiconductor like SiC, is proceeding in expectation of characteristics superior to those of conventional Si-based
semiconductors. In particular, GaN-based field effect transistors (FETs) are able to operate at high power, high frequencies and high temperatures, exhibiting various excellent performance indexes 1)~3). In contrast to conventional
Si devices, those based on wide bandgap semiconductors such as SiC and GaN offer significantly better performance overcoming the so-called “silicon limit”, so that it
is expected that they can realize high-performance power
supplies in terms of low power loss, compactness andhigh efficiency, which was unachievable with conventional
Si devices.
With respect to epitaxial growth of GaN, recent
advancement in crystal growth technology has made it
possible to use Si for the substrate, thereby achieving
crystal growth of thick epitaxial layers on large diameter
Si wafers, which has been difficult conventionally.
Introducing an MOCVD (Metal Organic Chemical Vapor
Deposition) machine capable of multi-wafer crystal growthusing 4-in Si wafers, we have been investigating the crystal growth technology. In this paper, experimental resultsof GaN epitaxial layer growth on a 4-in Si wafer for highbreakdown voltage devices will be presented.
Fabrication of relatively large-area devices is needed to* Yokohama Research Lab., R&D Division*2 Ecology & Energy Lab., R&D Divisiondemonstrate the potential of a power device in general. In
the case of HFETs on Si substrate, however, in contrast toin the case of sapphire substrate, it is essential to reduce
the leak current in the buffer layer so as to realize a device
with a high breakdown voltage, and this requires someinventive processing techniques. With regard to current
enhancement, we have applied our unique structure to
the electrode, thereby achieving good large-current performance 6). In terms of breakdown voltage performance,
thick epitaxial layers of high resistance based on carbon
doping were used, and, simultaneously, a deep mesa
structure was formed by dry etching to achieve high output power.
On the other hand, the AlGaN/GaN HFET offers a highoutput, high-switching-speed device taking advantage of
its high-mobility, high-density, two-dimensional electron
gas layer formed on the interface, and the device is underdevelopment. However, suppression of current collapse isessential for practical use of GaN HFETs. Several research
institutes have so far reported on the effects of applicationof a field plate (FP) structure and so on to suppress thecurrent collapse 4), 5). In this paper, current collapse has
been evaluated for the HFETs with different substrates
and structures.

2.

RESULTS AND DISCUSSION

2.1 Results of Epitaxial Layer Growth on 4-in Si Wafer
In the past, we used 2-in Si (111) wafer for epitaxial
growth, whereby a GaN/AlGaN HFET structure wasformed on a buffer layer to obtain breakdown voltages inFurukawa Review, No. 34

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High-Density Multi-Fiber Connectors for Optical Interconnection

1.00

ers caused possibly by nitrogen vacancies, which resulted in the degradation in breakdown voltage. Accordingly
we tried to compensate for the nitrogen vacancies by proactively using a dopant. Carbon, one of the candidate
dopants, is expected to show a small coefficient of diffusion in GaN, so that, if suitable growth conditions are
selected, it can be used as a dopant provided with superior diffusion controllability in the depth direction. Figure 4
shows the schematic of a sample device for breakdown
voltage measurement of the buffer layer. In the experiment, by changing the growth conditions, GaN layers withdifferent carbon concentrations were grown on the buffer
layer, on which a high-concentration n-GaN layer was
grown to form an ohmic contact. A device for breakdown
voltage measurement was formed by etching the n-GaNlayer between the electrodes. Figure 5 shows the breakdown voltage of buffer layer versus carbon concentrationin the i-GaN layer estimated by SIMS. The distance
between the electrodes was kept at 10 μm to facilitatecomparison. Auto-doping of carbon was carried out by

750

Thickness（nm）

excess of 400 V 7). But since use of large-sized wafers is
indispensable for reducing the device cost, we haverecently introduced an MOCVD machine capable of processing five 4-in wafers at a time, and have since been
investigating epitaxial growth using 4-in Si (111) wafer
and TMGa, TMA1, and NH3 gases 8).
Figure 1 shows the AFM observation result of a surface
after growth. It is seen that a crack-free smooth surface isobtained in spite of the use of 4-in Si wafer. The surface
has an RMS roughness of 0.54 nm, and terraces due toatomic step can be observed. Figure 2 shows the resultsof thickness distribution evaluation for GaN epitaxial layeron 4-in Si wafer, in which evaluation is done in two directions, vertical and horizontal, with respect to orientation
flat (OF). The index of distribution is calculated, by dividing the standard deviation by the average, to be 2.9%.
Figure 3 shows a comparison of GaN layer thickness
between 4-in Si wafers. Excellent wafer-to-wafer distribution is obtained with a distribution index of 0.5 % or lower.
As mentioned above, it may be concluded that the epitaxial growth conditions developed here have characteristics
sufficient to realize high throughput.
It is thought that there are two crucial factors in improving the breakdown voltage of the device. One is enhancement of the resistance of epitaxial layers including thebuffer layer, and the other is increasing the thickness of
epitaxial layers. Whereas the breakdown voltage for buffer
layers conventionally obtained using the 2-in machine
was 500 V or higher, the same layer structure formed on a
4-in wafer was found to result in a problematic value ofapproximately 200 V. We investigated the cause of the
breakdown voltage decrease, and it was suggested that aleak current was generated due to the existence of carri-

700
650
600
550
500
450

0

Figure 1

0.25

0.50

0.75

Figure 3

2.5 nm0.50

0.0 nm3

4

5

6Comparison of GaN layer thickness among 4-in Si wafers.

5.0 nm0.75

01.00 µm

2

Wafer number

10〜50 µm
Metal
n-GaN

Metal
n-GaN

C-doped GaN 600 nm

0.25

0

1

Buﬀer layer
RMS=0.54 nm

Si（111）substrate

AFM image of GaN epitaxial layer on a 4-in Si wafer.

Figure 4

Schematic of GaN-based epitaxial layer sample forbreakdown voltage measurement.

750
OF-vertical

900

OF-horizontal

800

Breakdown voltage（V）

Thickness（nm）

700
650
600
550
500
450
-50

-30

-10

10

30

Thickness distributions of GaN layers on a 4-in Si wafer.

500
400
300
200
100
0
1.0×1016

50

Distance from the center（mm）

Figure 2700
600

1.0×1017

1.0×1018

1.0×1019

C-concentration （SIMS）（cm-3）

Figure 5

Breakdown voltage versus carbon concentration.

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High-Density Multi-Fiber Connectors for Optical Interconnection

Breakdown voltage of GaN layer（V）

controlling the growth conditions. It can be seen that the-316
carbon concentration is controlled from 10 cm to near
-3
19
10 cm , and that the breakdown voltage increases
depending on the carbon concentration. As the result, it
has been shown that breakdown voltages in excess of
800 V can be obtained.
In order to increase the total thickness of epitaxial layers, on the other hand, it is required to devise suitable
growth conditions and structures so that epitaxial layerswith minimized crack and warpage can be obtained. We
have optimized the conditions based on AlN/GaN structure, thereby succeeding in realizing a maximum total
thickness of 5.2 μm. Figure 6 shows the evaluation resultsof breakdown voltage versus electrode distance. As canbe seen, in the case of total epitaxial layer thickness of
2.3 μm, the breakdown voltage increases as the electrodedistance increases up to 20 μm, achieving a maximum
value of 800 V. Above 20 μm, however, the breakdown
voltage remains unchanged showing a tendency to saturate. In the case of 5.2-μm thick epitaxial layers, thebreakdown voltage also increases with increasing electrode distance, reaching 1,700 V or higher at an electrodedistance of 30 μm, above which a tendency to saturate
can be seen. To summarize, we may conclude that the
breakdown voltage of epitaxial layers improves withincreasing layer thickness. Figure 7 plots the maximum

2000

breakdown voltage for various layer thicknesses, showingthat the maximum breakdown voltage improves virtuallyin a linear relationship as the total thickness of epitaxial
layers increases. Thus it was decided to proceed todevice fabrication and characteristics evaluation based on
the investigation results mentioned above.
2.2 Evaluation Results of Device Characteristics
Epitaxial layers of AlGaN/GaN HFET structure were fabricated on a Si (111) substrate by means of MOCVD, andcomparisons were made with those formed on a C-facesapphire substrate. Prototyping of devices was carriedout using chlorine-based ICP (Inductively Coupled
Plasma) equipment to form mesa structure, the sputtering
method to form electrodes, and the PCVD (Plasma
Chemical Vapor Deposition) method to deposit SiO2 as apassivation layer and an inter-layer insulation layer. Figure
8 shows the photograph of a 4-in Si wafer with GaN epitaxial layers after processing of mesa etching and electrode forming. Since the wafer shows less significant warpage making the epitaxial layers suitable for post-processing, it is possible to process the 4-in wafer intact in acircular shape. Figure 9 shows the device structure
formed on Si wafer prototyped here, in which a deep
mesa is formed to reach the Si substrate to improve thebreakdown voltage, and the fingers are plated to reduce
the electrode resistance.
Devices were fabricated using epitaxial layers with different thicknesses. Figure 10 shows the DC characteris-

1600

1200

800

400

0

Epitaxial layer thickness: 5.2 µm
Epitaxial layer thickness: 2.3 µm

0

20

40

4 inch60

Electrode distance (µm)

Breakdown voltage of GaN layer（V）

Figure 6

Dependence of breakdown voltage on electrode distance for different total epitaxial thicknesses.

Figure 8

2000

1600

Gold plate

1200

Surfacepassivation

Gold plate
Interlayer ﬁlm

Gate
800

Source

400

0

0

2

4

Dependence of breakdown voltage on total epitaxial
layer thickness.

AlGaN
GaN

Drain

Buﬀer layer

6

Si substrate

Total epitaxial layer thickness (µm)

Figure 7

Photograph of post-processed 4-in wafer.

Electrode distance：30 µｍ

Figure 9

Schematic of HFET device structure on Si substrate.

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High-Density Multi-Fiber Connectors for Optical Interconnection

Figure 13 plots the gate-drain breakdown voltage withrespect to Lgd, of devices with different epitaxial layer
thicknesses. Whereas the breakdown voltage shows atendency to saturate at about 1,100 V in the case of epitaxial layer thickness of 3.5 μm, in the case of the 5.2-μm
thickness, the voltage tends to saturate above L gd =15 μm reaching 1,500 V or higher. And, in both cases, it isseen that the relationship is close to a linear line oftics of the devices. Figure 10 (a) shows the results for thedevice on sapphire substrate and Figure 10 (b) on Si substrate. The parameters for the devices evaluated here areas follows: total thickness of epitaxial layers on Si substrate is 3.5 μm; sheet resistance for the both substrates
is about 500 Ω/□; gate width Wg = 200 μm; gate length
Lg = 2 μm; and gate-to-drain distance Lgd = 10 μm. In thecase of the device on Si substrate, it was shown that thecurrent at a gate-to-source voltage V gs = 1V was
350 mA/mm or more, and the on-resistance was
10.4 Ωmm, a satisfactory value. In the case of the device
on sapphire substrate, comparable results were obtained
for the current and on-resistance. Meanwhile, Figure 11
shows the results for the 5.2-μm epitaxial layers on Si
substrate with Lgd = 15 μm. The on-resistance is somewhat larger--13.4 Ωmm, which may be attributed to thefact that the sheet resistance--630 Ω/□--is somewhat
higher than that of the epitaxial layers in Figure 10.
The devices with different Lgd values fabricated on Si
substrate were evaluated for their gate-drain breakdown
voltage. The evaluation was carried out using Flourinert toprevent creeping discharge, and with the electric potentialof the substrate floating. Figure 12 shows the results for
5.2-μm thick epitaxial layers. The breakdown voltage
increases as Lgd increases from 5 μm through 10 μm to
15 μm, reaching 1,500 V or higher at 15 μm. But at Lgd =20 μm the breakdown voltage showed a tendency to saturate at 1,630 V. Since the breakdown voltage of the buffer
layer of these epitaxial layers was around 1,700 V, it was
shown that the gate-drain breakdown voltage was limitedby the breakdown voltage of the buffer layer.

0.40
gs＝1 Vds（A/mm）

0.30
0 V

0.20
−1 V

0.10
−2 V

0.00

−3 V

0

5

10

15

20

ds（V）

Figure 11 DC characteristics of HFET using 5.2-μm epitaxial
layer on Si substrate.

2.0E−03
gd＝5 µmgs＝−6 V

0.4

0.3

ds（A/mm）

ds（A/mm）

0.4

gs＝1 V
0V

0.2

−1 V

0.1
0.0

ds（A/mm）

1.5E−03

0

5

10

15

0.2

gs＝1 V

1.0E−030gd＝15Vµm

5.0E−04
gd＝10 µm

0.1

−2V
−3 V
−4 V
20

0.3

0.0E＋00
25

0.0

0

0

5

ds（V）

−1 V

0.3
0V

0.2

−1 V

0.1

−2V

−3 V
−4 V
25

0.0

1500
25

0

5

10

15

−2 V
−3 V
20

25

ds（V）

Figure 10 (b) DC characteristics of AlGaN/GaN HFET on Si substrate.

2000

Figure 12 Lgd dependence of off-state characteristics for HFETs
using 5.2-μm epitaxial layer.

Breakdown voltage（V）

ds（A/mm）

gs＝1 V

0V

−2 V
1000
20
ds（V）

1.0MV/cm

2000

0.4

b＝1630 V

−1 V

−3 V

15

ds（V）

Figure 10 (a) DC characteristics of AlGaN/GaN HFET on sapphire substrate.

＝1 V

500
10

gd＝20 µm

1500
1000
500
0

Total epitaxial layer thickness: 5.2 µm
Total epitaxial layer thickness: 3.5 µm

0

5

10

15

20

25

gd（µm）

Figure 13 Breakdown voltage versus Lgd for small-area device
HFETs with different total epitaxial layer thicknesses.

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High-Density Multi-Fiber Connectors for Optical Interconnection

approximately 1.0 MV/cm, up to Lgd = 10 μm.
Next the results of formation of large-area devices will
be presented. Figure 14 shows the photo of a large-area
device fabricated here. Fingers are formed near the center, and pads for wire bonding are formed above andbelow. The size of finger area is 6.8 mm×1.5 mm.
The device mentioned above was evaluated for electrical characteristics. Figure 15 shows the measurement
results of gate-drain breakdown voltage, in which a device
with Wg = 340 mm and Lgd = 15 μm was evaluated. The
measurement was carried out as on-wafer, so that a†
Fluorinert immersion environment was used to prevent
creeping discharge. A breakdown voltage of 1.3 kV was
obtained at Vgs = -6 V. This result is recognized as the

G

G

S

1.5 mmD

6.8 mmFigure 14 Photograph of HFET large-area device. (Wg = 340 mm)

5.0 E−02
gs=−6 V
gd=15 µm

ds（A）

4.0 E−02
3.0 E−02
2.0 E−02b=1.3 kV

1.0 E−02
0.0 E＋00
0

500

1000

1500

ds（V）

Figure 15 Off-state characteristics for large-area device. (Wg =340 mm)150

gs=2 V100

2.3

Evaluation Results of Current Collapse
Characteristics
Having demonstrated the device with a sufficient breakdown voltage, we moved to evaluate current collapse
characteristics. For evaluation of current collapse, the socalled “pulse collapse method” has been used 4). Although
this method allows for on-wafer evaluation, it is somewhat
complicated in that the matching resistance has to bechanged to suit the device size, and so on. In order toestablish a convenient measurement method for current
collapse characteristics, we studied measurement methodology. Figure 17 illustrates the technique employed, inwhich the current collapse quantity is defined as the valueof R on_af/R on_bf, where measurement is made to obtain
initial on-resistance R on_bf, off-state, and on-resistanceR on_af, in this order. First, both the on-wafer measurement
and pulse collapse measurement methods were applied
to the same device, and measurement conditions were
optimized in order to obtain good correlation with thepulse collapse method. Since the conditions are strongly
influenced by off-stress time T_off, experiments were carried out with various off-stress times, and as a result, it
was found that T_off = 10 sec resulted in best agreementwith the pulse collapse method. Figure 18 shows the correlation between the two methods, in which measurement
was made with T_off = 10 sec. It can be seen that thepulse collapse method on the longitudinal axis has a linear relationship with respect to the on-wafer method on
the lateral axis. From the above results we may say that agood correlation is established with the pulse collapse
method, so that it has been decided to use hereafter thiscondition as an on-wafer current collapse evaluation technique.
Figure 19 shows the evaluation results of current col-

ds（A）

1V

ds

0V

50

−1 V

0

largest-ever value among the characteristics of high-power GaN HFETs on Si substrate ever achieved.
The device was mounted in a TO-220 package to beevaluated for the current-voltage characteristics. Figure
16 shows the results of drain current-voltage characteristics measurement for a device with Wg = 340 mm and Lgd= 15 μm, with changing Vgs from 2 V to -3 V. From the
Figure superior current-voltage characteristics can beseen, and the maximum current of 120 A was obtained at
V gs = 2 V. Meanwhile, the on-resistance was 51 mΩ
2(5.2 mΩcm when normalized by area).

5

10

Semiconductor test system
TESEC（351TT/P）
ds̲oﬀ
on̲bf

gs
15

ds（V）

Figure 16 On-state characteristics for large-area device (Wg =340 mm)† Fluorinert is a trademark of 3M.

ds

on̲af

（3）dson̲af−2 V −3 V0̲afCurrent collapse=
̲bf1
Slope=
̲bf（1）dson̲bf
1
Slope= ̲af（2）Oﬀ state

ds

̲int
0V

̲oﬀ

̲int

−6 V

time

Figure 17 On-wafer evaluation method for current collapse
characteristics.

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High-Density Multi-Fiber Connectors for Optical Interconnection

Pulse collapse（ on̲af/ on̲bf）

lapse characteristics for various devices, in which thegate-drain electric field Vds_off is plotted on the lateral axis
and the current collapse quantity on the longitudinal axis.
The measurements were made, on the devices with Lgd =15 μm, on wafer, in a Fluorinert environment to prevent
creeping discharge, and the substrate had equal potential
with the source. The results for three epitaxial layers withdifferent thickness on Si substrates are compared in the
Figure, and the results for the devices on sapphire areshown for comparison. In the case of sapphire substrate,
the current collapse is seen to increase as the drain voltage Vds_off increases, reaching five times or higher at 400
V. In the case of the devices on Si substrate, on the other
hand, the current collapse remains at a very low leveleven at high voltages, showing good results. This may be
attributed to the fact that crystal quality of epitaxial layers
on Si substrate has been much improved, and that electric field concentration has been relaxed by the field plate
effect of Si substrate due to its conductivity. The marks ■,●, and ■ in the Figure represent total epitaxial layer thicknesses of 2.5 μm, 3.4 μm, and 5.2 μm, respectively. In thecase of the total epitaxial layer thickness of 2.5 μm, thecurrent collapse quantity shows a relatively small changeof 1.1 times up to 350 V, and subsequently breaking down
at 400 V. In the case of 3.4 μm, it stayed constant at about
1.3 times up to 700 V, followed by a breakdown at 750 V.

15

In the case of 5.2 μm, it remained at about 1.6 times up to
900 V, followed by a breakdown at 950 V. These results
suggest that although breakdown voltage rises withincreasing epitaxial layer thickness, current collapse also
increases. If current collapse increases with increasing
layer thickness as has been suggested, it is thought,
some improvements must be made in order to resolve thetradeoff between epitaxial layer thickening for breakdown
voltage enhancement and current collapse improvement.
Here, field plate (FP) structure is generally considered asa measure for improving current collapse. Figure 20
shows its schematic. When a device has no FP structure,
the electric field tends to concentrate on the drain-side
end of the gate electrode. When the FP structure isemployed, it comes in a structure such that the gate electrode is elongated to the drain side (i.e., G-FP), or thesource electrode is extended to the drain side overlapping the gate electrode via an insulation layer (i.e., S-FP)
4). We have investigated here whether application of FP
structure improves current collapse characteristics.
Figure 21 shows the evaluation results of current collapse for the devices in the same lot using a 5.2-μm epitaxial layer, having different structures in terms of thegate-field plate length (Lgfp) and source-field plate length(Lsfp). It can be seen that the devices employing the FP
structure has been improved in comparison to the devic-

Source electrode

S-FP

Gate electrode
10

AlGaN layer
GaN layer

5

0

0

5

10

Reduction in electricfield relaxation effects
due to increased
epitaxial layer thickness

15

On-wafer measurement（ on̲af/ on̲bf）

Figure 18 Correlation between pulse-collapse method and onwafer method for current collapse characteristics.

Conductive Si substrate
Figure 20 Suppression of current collapse using field plate
structure.

No FP structures6

gd=15 µm

53.0

Epitaxial layer thickness

4

Current collapse( on̲af/ on̲bf)

Current collapse（ on̲af/ on̲bf）

Drain electrodeG-FP

3.0 µm(on sapphire substrate)3
on Si substrate
5.2 µm2
1

3.4 µm0200

2.5 µm

400

600

800

1000

ds̲oﬀ（V）

Figure 19 Dependence of current collapse characteristics on epitaxial layer thickness for different kinds of substrates.

2.0

1.0

No FP

No FP

G-FP
（ gfp=2 µm）fp̲G=2 µm

G-FP（ gfp=3 µm）fp̲G=3 µm

G-FP+S-FP（ gfp=1 µm
sfp=3 µm）fp̲G=1 µm, fp̲S=3 µm

Device structure

Figure 21 Comparison of current collapse between devices withand without field plate structures.

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High-Density Multi-Fiber Connectors for Optical Interconnection

es without the FP structure, and that, in the case of G-FP
structure, the current collapse improvement is dependent
on the length. From the results mentioned above, it has
been shown that the use of the FP structure suppresses
the degradation of current collapse characteristics due toincreased thickness in epitaxial layers.

CONCLUSION
Epitaxial growth technology for GaN layer on Si substrate
has been studied aiming at a new device with high breakdown voltage and low on-resistance. Epitaxial layer
growth using a 4-in multi-wafer machine is confirmed toresult in good uniformity both in-wafer and wafer-to-wafer
characteristics. In order to improve breakdown voltage
performance, the carbon concentration in GaN layer iscontrolled as a technique to enhance the breakdown voltage of the buffer layer, and it has been found that the carbon concentration significantly contributes to breakdown
voltage improvements. As the result, the maximum breakdown voltage of 1.7 kV has been obtained using a total
epitaxial layer thickness of 5.2 μm.
The HFET structure is formed on the above mentioned
epitaxial wafer to fabricate a device, and, as the result, adevice having good characteristics of 1.3 kV in break2
down voltage, 120 A in maximum current, and 5.2 mΩcm
in on-resistance is obtained at Wg = 340 mm. The current
collapse is evaluated, and it has been found that the current collapse can be suppressed low up to 900 V.
Moreover, application of the FP structures has been studied to find out that current collapse can be suppressed
further even in thick epitaxial wafers.

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