TECHNICAL DATA SHEETJade 78141A
1-channel 6.4 GHz A/D, 2-channel 3.2 GHz A/D
2-channel 6.4 GHz D/A, PCIe board with Kintex UltraScale FPGA

Complete radarand software radiointerface solution▪ Radar and communication receiver andtransmitter▪ Wideband data acquisition▪ Electronic Warfare transponder▪ Sensor interfaces▪ Remote monitoring▪ Waveform signal generator

The Jade® 78141A is a high-speed analog-to-digital and digital-toanalog converter with programmable DDCs (digitaldownconverters) and DUCs (digital upconverters). It is suitable forconnection to HF or IF ports of a communications or radar system.
Its built-in data capture and generator features offer an ideal turnkey solution as well as aplatform for developing and deploying custom FPGA-processing IP. It includes a 6.4 GHz,
12-bit A/D converter, dual 6.4 GHz, 14-bit D/As and a large DDR4 memory. In addition tosupporting PCI Express Gen. 3 as a native interface, the 78141A includes optional highbandwidth connections to the Kintex UltraScale FPGA for custom digital I/O.

FEATURES▪ Xilinx® Kintex® UltraScale™ FPGA▪ One-channel mode with 6.4 GHz, 12-bit A/D▪ Two-channel mode with 3.2 GHz, 12-bit A/Ds
▪ Programmable DDCs (digital downconverters)▪ Two 6.4 GHz, 14-bit D/As
▪ Programmable DUCs (digital upconverters)▪ 5 GB of 2400 MHz DDR4 SDRAM▪ µSync clock/sync bus for multiboard synchronization▪ PCI Express interface (Gen. 1, 2 & 3) up to x8▪ Optional LVDS port and gigabit serial connections for custom FPGA I/O

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TECHNICAL DATA SHEETJade 78141A

78141A BLOCK DIAGRAM
Click on a block for more information.

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TECHNICAL DATA SHEETJade 78141A

THE JADE ARCHITECTURE

A/D ACQUISITION IP MODULES

Evolved from the proven designs of Mercury’s Cobalt® and Onyx®
families, Jade® raises the processing performance while lowering
the overall power requirements by building on the Xilinx family ofKintex UltraScale FPGAs. As the central feature of the board
architecture, the FPGA has access to all data and control paths,
enabling factory-installed functions as well as providing an ideal
platform for user-created intellectual property (IP).

The 78141A features two A/D Acquisition IP Modules for easy
capture and data moving. The IP module can receive data fromthe A/D, or a test signal generator. The IP module has
associated a 5 GB DDR4 memory for buffering data in FIFO
mode or for storing data in transient capture mode.

Each member of the Jade family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The 78141A factory-installed functions include twoA/D acquisition and two D/A waveform generator IP modules. In
addition, IP modules for DDR4 SDRAM memories, a controller for
all data clocking and synchronization functions, a test signal
generator and a PCIe interface complete the factory-installed
functions and enable the 78141A to operate as a complete
turnkey solution, without the need to develop any FPGA IP.

XILINX KINTEX ULTRASCALE FPGAS
Depending on the requirements of the processing task, the Kintex
Ultrascale can be selected from a range of FPGAs: KU035 through
KU115. The KU115 features 5520 DSP48E2 slices and is ideal formodulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between
transmission and reception. For applications not requiring large
DSP resources or logic, a lower-cost FPGA can be installed.

In single-channel mode, all of 5 GB are used to store the singlechannel of input data. In dual-channel mode, one half of thememory stores data from input channel 1 and the other halfstores data from input channel 2. In both modes, continuous,full-rate transient capture of 12-bit data is supported.
The memory bank is supported with a DMA engine for moving
A/D data through the PCIe interface. This powerful linked-list
DMA engine is capable of a unique Acquisition Gate Drivenmode. In this mode, the length of a transfer performed by a link
definition need not be known prior to data acquisition; rather, it
is governed by the length of the acquisition gate. This isextremely useful in applications where an external gate drives
acquisition and the exact length of that gate is not known or is
likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing a sample-accurate time stampand data length information. These actions simplify the hostprocessor’s job of identifying and executing on the data.

D/A WAVEFORM GENERATOR IP MODULE
A/D CONVERTER STAGE
The board's analog interface accepts analog HF or IF inputs on apair of front panel SSMC connectors with transformer-coupling
into a Texas Instruments ADC12DJ3200 12-bit A/D. The
converter operates in single-channel interleaved mode with asampling rate of 6.4 GHz and an input bandwidth of 7.9 GHz; or,in dual-channel mode with a sampling rate of 3.2 GHz and input
bandwidth of 8.1 GHz.
The A/D built-in digital down-converters (DDCs) support 2x
decimation in real output mode and 4x, 8x, or 16x decimation incomplex output mode. The A/D digital outputs are delivered intothe Kintex UltraScale FPGA for signal processing, data capture
or for routing to other module resources.

The 78141A factory-installed functions include a sophisticated
D/A Waveform Generator IP module. It allows users to easily
record to the dual D/ As waveforms stored in either on-board
memory or off-board host memory.

DIGITAL UPCONVERTER AND D/A STAGE
A Texas Instruments DAC38RF82 DUC (digital upconverter) andD/A accepts a baseband real or complex data stream from theFPGA and provides that input to the upconvert, interpolate anddual D/A stages. When operating as a DUC, it interpolates andtranslates real or complex baseband input signals. It delivers
real or quadrature (I+Q) analog outputs to the dual 14-bit D/Aconverter. Analog output is through a pair of front panel SSMC
connectors.
If translation is disabled, the DAC38RF82 acts as a dual
interpolating 14-bit D/A. In both modes the DAC38RF82 provides
interpolation factors from 1x to 24x.

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TECHNICAL DATA SHEETJade 78141A

CLOCKING AND SYNCHRONIZATION▪ ADC Overload LED: There is one red OV(overload) LED for all ADC inputs. This LED
indicates either an overload detection inone of the ADC12DJ3200s, or an ADC FIFOoverrun.

The 78141A accepts a sample clock via a front panel SSMC
connector. A second front panel SSMC accepts a TTL signal thatcan function as Gate, PPS or Sync.
A front panel µSync bus connector allows multiple modules tobe synchronized, ideal for multichannel systems. The µSync busincludes gate, reset, and in and out reference clock signals. The
Model 7892 high-speed sync module can be used to drive thesync bus to synchronize multichannel systems.

▪ Analog Input Connectors: Two SSMC
coaxial connectors, labeled In 1 and IN 2:
one for each ADC input channel.
▪ DAC Underrun LED: One red underrun UR
LED for both DAC outputs. This
LED illuminates when the DAC38RF82
FIFO is out of data.

MEMORY RESOURCES
The 78141A architecture supports a 5 GB bank of DDR4 SDRAM
memory. User-installed IP along with the Mercury-supplied
DDR4 controller core within the FPGA can take advantage of thememory for custom applications.

▪ Analog Output Connectors: Two SSMC
coaxial connectors, labeled OUT 1 andOUT
2: one for each DAC38RF82 output channel.
▪ PPS LED: The green PPS LED illuminates
when a valid PPS signal is detected. TheLED will blink at the rate of the PPS signal.

PCI EXPRESS INTERFACEThe 78141A includes an industry standard interface fully compliant
with PCI Express Gen. 1, 2, and 3 bus specifications. Supporting PCIelinks up to x8, the interface includes multiple DMA controllers for
efficient transfers to and from the module.

▪ Trigger Input Connector: One SSMC
coaxial connector, labeled TRIG, for inputof an external trigger.
▪ Clock LED: The green CLK LED illuminates
when a valid sample clock signal isdetected. If the LED is not illuminated, noclock has been detected and no data fromthe input stream can be processed.

FRONT PANEL CONNECTIONS
The front panel includes seven SSMC coaxial connectors for
input/output of analog RF, clock, and trigger, signals, and a 12-pin
Sync Bus input connector. The front panel also includes seven LEDindicators.

▪

Clock Input Connector: One SSMC coaxialconnector, labeled CLK, for input of an external sample
clock.

▪ Reference Clock Input Connector: The SSMC coaxial
connector, labeled REF, for input of an external reference
clock.
▪ Link LED: The green LNK LED indicates the link speed
when a valid link has been established over the PCIeinterface, as follows: Gen 1 - LED blinks slowly (less thanonce per second); Gen 2 - LED blinks about once per second;
Gen 3 - LED will be constantly on.
▪ Sync Bus Connector: The 19-pin µSync front panel
connector, labeled SYNC/GATE, provides sync and gate
input signals for A/D and D/A Processing.
▪ User LED: The green USR LED is for user applications.
▪ Over Temperature LED: The red TMP LED illuminates whenan over-temperature or over-voltage condition is indicated byany of the temperature/voltage sensors on the PCB.

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TECHNICAL DATA SHEETJade 78141A

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IPcores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installed
FPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jade
design. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of all
hardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSP
components. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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TECHNICAL DATA SHEETJade 78141A

Because all Jade boards are shipped with a full suite of built-inIP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEETJade 78141A

SPECIFICATIONS
Front Panel Analog Signal Inputs
Input Type: Transformer-coupled, front panel female SSMC
connectors

A/D Converters

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing

Type: ADC12DJ3200

Option -702: L2 (air-cooled)

Sampling Rate: Single-channel mode: 6.4 GHz; dual-channel
mode: 3.2 GHz▪ Operating Temp: -20° to 65° C

Resolution: 12 bits
Input Bandwidth: single-channel mode: 7.9 GHz; dual-channel
mode: 8.1 GHz

D/A Converters▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: Half-length PCIe card

Type: Texas Instruments DAC38RF82▪ Depth: 181.10 mm (7.13 in)

Output Sampling Rate: 6.4 GHz.

▪ Height: 111.25 mm (4.38 in)

Resolution: 14 bits

Weight: Approximately 14 oz (400 grams)

Sample Clock Source
Front panel SSMC connector

Timing Bus
19-pin µSync bus connector includes sync and gate/trigger
inputs, CML

External Trigger Input
Type: Front panel female SSMC connector, LVTTL
Function: Programmable functions include: trigger, gate,
sync and PPS

Field Programmable Gate Array
Standard: Xilinx Kintex UltraScale XCKU035-2
Option -084: Xilinx Kintex UltraScale XCKU060-2
Option -087: Xilinx Kintex UltraScale XCKU115-2

Custom I/O
Option -104: installs 24 pairs of LVDS connections from theFPGA to a 68-pin header for custom I/O.
Option -105 (only available with option -084 or -087): provides
an 8X gigabit link between the FPGA and a serial connector tosupport serial protocols

MemoryType: DDR4 SDRAM
Size: 5 GB
Speed: 1200 MHz (2400 MHz DDR)

ORDERING INFORMATION
Model

Description

78141A

1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A,
Kintex UltraScale FPGA - PCIe

Options:-084

XCKU060-2 FPGA-087

XCKU115-2 FPGA-104

LVDS FPGA I/O-105

Gigabit serial FPGA I/O-702

Air-cooled, Level 2Contact Mercury for compatible option combinations and complete
specifications of rugged and conduction-cooled versions. Options maychange, so be sure to contact Mercury for the latest information.

ACCESSORY PRODUCTS
ModelDescription

2171

Cable Kit: SSMC to SMA

7892

High-Speed Synchronizer and Distribution Board

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 or x8

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TECHNICAL DATA SHEETJade 78141A

FORM FACTORSDEVELOPMENT SYSTEMSJade products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Jade Model 71141A XMC (8Channel 250 MHz A/D with DDC, Kintex UltraScale FPGA) has thefollowing variants:

Mercury offers development systems for Jade products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system thatensures optimum performance of Jade boards. Please contact
Mercury to configure a system that matches your requirements.

Model52141A

3U VPX board (single XMC)

54141A

3U VPX board (single XMC with optical/backplane RF)

57141A

6U VPX board (single XMC)

58141A

6U VPX board (dual XMC)

71141A

XMC module

78141A

PCIe board (single XMC)

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International Headquarters
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Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF78141A

Visit: mrcy.com/go/MP78141A+41 22 884 5100 tel

The Mercury Systems logo is a registered trademark of Mercury Systems, Inc. Other marks used herein may be trademarks or registered trademarksof their respective holders. Mercury products identified in this document conform with the specifications and standards described herein.
Conformance to any such standards is based solely on Mercury’s internal processes and methods. The information contained in this document issubject to change at any time without notice.
© 2023 Mercury Systems, Inc. 1-0-060923-DS-J78141

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