High-Power Operation of Normally-Off GaN MOSFETs
Yuki Niiyama *, Tatsuyuki Shinagawa *2, Shinya Ootomo *3, Hiroshi Kambayashi *,Takehiko Nomura *, and Sadahiro Kato *A power transistor to be incorporated into the power supply circuitry for
automobiles and home appliances has been developed. The semiconductormaterial used is GaN that is characterized by its higher critical electric field and higher maximum
saturation velocity than those of Si. A metal-oxide-semiconductor (MOS) structure of metal/SiO2/
GaN has been used to achieve normally-off operation in which no current flows unless a gate
voltage is applied, since this operation is generally required for power transistors to ensure
system safety. High-temperature, high-power operation of GaN MOSFETs has been realized hereby improving the quality of the SiO2/GaN interface thus reducing the contact resistance between
the metal and GaN. The threshold voltage, breakdown voltage, operation current and maximum
operation temperature were +3 V, higher than 1550 V, larger than 2.2 A and 250°C, respectively.

ABSTRACT1.

INTRODUCTION

Power transistors are incorporated as a switching elementin power supply circuits like inverters. Since inverters cancontrol motors by converting the frequency of AC power
supply, they are widely used for energy-efficient motor
control; and hence in hybrid cars, as well as in energysaving home appliances such as air-conditioners andinduction heating (IH)-based cooking devices and industrial motors. For this reason, great expectations are placedon the performance enhancement of power transistors,
since this would result in loss reduction in inverters,
achieving higher energy efficiency and leading to a contribution to environmental improvements.
Currently, Si-based insulated gate bipolar transistors(IGBTs) are used as power transistors. But their performance deteriorates drastically at high temperatures with areduced operation current above 200°C 1). This is largely
attributable to the material performance of Si, so that it isabsolutely imperative to develop a power transistor innear future using a new material, in order to realize alarge output power and small on-resistance at high-temperature environments.
We recognized the potential of gallium nitride (GaN), akind of nitride semiconductor, as a new material. GaN hasa higher breakdown voltage and a higher saturation
velocity than those of Si, and therefore, a GaN-based
power transistor shows possibilities to realize a highbreakdown voltage and low on-resistance 2), 3). Since* GaN Power Electronics Team, Yokohama R&D Lab., R&D
Div.
*2 Photonic Device Research Ctr., Yokohama R&D Lab., R&D
Div.
*3 Analysis Technology Ctr., Yokohama R&D Lab., R&D Div.

reduction in the on-resistance means reduction in heatgeneration, this can also result in simplification of coolingsystems such as heat sinks, thereby making a significant
contribution to efficiency enhancement and downsizing of
power supply circuits.
The structure of power transistors using GaN comes in
two kinds: heterostructure field-effect transistor (HFET)
and metal/oxide/semiconductor field-effect transistor(MOSFET). Until now, much work has been done on
AlGaN/GaN-based HFETs. The reason is that a twodimensional electron gas (2DEG) is generated at the
AlGaN/GaN interface as a result of spontaneous andpiezo polarization, making it possible to obtain high electron concentrations. However, AlGaN/GaN HFETs intrinsically show a negative threshold voltage, resulting in normally-on operation. Thus they need a drive circuit to control the gate bias, which leads to the necessity of additional study to cope with circuit complexity and cost
increases. Especially in view of power device applications, the normally-off type transistor in which no current
flows at no gate bias is strongly required from the application system side, and this requirement is justified when
one considers any replacement of Si power transistors
presently in use or the importance of malfunction prevention against possible surge voltages during power out­ages.
On the other hand, the MOSFET has the advantages oflow gate leakage current and simple structures, in addition to the fact that its structure allows normally-off operation. Accordingly, a number of research institutions
recently report on the performance of GaN MOSFETs 9)~13).
Chow et al. have fabricated a GaN MOSFET that has
achieved a threshold current of 3.3 V and operation current of 10 mA at 150°C 10), but the current and temperature
would require further improvements.

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High-Power Operation of Normally-Off GaN MOSFETs

Selective and low resistive
ion-implanted layer

Low interface statesat SiO 2 / GaN
Gate

SourceSiO 2n+High crystalline
quality of GaN
epi-layer

Drain

n+

p-GaN

Substrate

Figure 1

Developmental issues for performance enhancementof GaN MOSFETs.

What deserves special attention in the developmenttasks for the MOSFET here is, as shown in Figure 1, thequality improvement of the SiO2/GaN interface and theresistance reduction for the contact layer selectively
formed under the electrodes. In MOSFETs, a channel isformed on the GaN surface under the gate in which a current flows between the source and the drain thus effecting
device operation. If the SiO2/GaN interface has poor quality, electrons in the channel are captured at the interface
states, so that the channel resistance increases. The
threshold voltage also deviates from the design value,
thereby posing the problem of ringing at switching.
Therefore, it is essential to improve the quality of the SiO2/
GaN interface, or in other words, to reduce the interface
states. With respect to the contact layer needed for current conduction between the metal and semiconductor,
an n-type dopant of Si ion is implanted into p-type GaN
crystal to selectively form an n-type conduction layer. It
also becomes important to choose optimized implantation conditions to recover the damages generated due toimplantation, as well as to find out optimum annealing
conditions for activation of Si, in order to form a low-resistance contact layer.
In this report, the developmental history of ion implantation technologies aimed at quality enhancement of SiO2/
GaN interface and formation of low-resistance contact

layer will be described first. Then, the device characteristics of GaN normally-off MOSFETs fabricated using theseelemental technologies will be presented.

2.

IMPROVEMENT OF SiO2/GaN INTER15), 16)
FACE QUALITY

MOS capacitor samples for evaluating the interface state
density were fabricated, in which n-type GaN was used inorder to investigate the near-bottom energy of conduction
+
−
17
−3
band. First, n-type GaN (Nd – Na ~ 2x10 cm ) 1 μm
in thickness was grown on a sapphire substrate (0001)cby metal-organic chemical vapor deposition (MOCVD).
The GaN surface was cleansed using common RCAcleaning, and SiO2 50 nm in thickness was deposited byplasma-enhanced chemical vapor deposition (PECVD).
After that, the sample was annealed in a nitrogen flow inan electric furnace, and subsequently, the ohmic electrode (Ti/AlSi/Mo) and gate electrode (Ti/Au) were formedby sputtering and lift-off process. Lastly, the capacitancevoltage (C-V) characteristics at 200°C were measured by
an impedance analyzer, and the interface state density
was calculated by the Terman method 17).
Figure 2 shows the interface state density distribution of
the SiO2/GaN-based MOS capacitor annealed at different
temperatures. The interface state density is seen to
decrease at higher annealing temperatures. In the case of
11−2−1
900°C, it is lower than 1x10 cm eV at an energy position 0.4 V apart from the near-bottom energy of conduction band. These values are sufficiently low for satisfactory
operation of the MOSFET device.
1.0E+13

Gate

Ohmic

SiO2
n-GaN

Dit (cm ‒2 eV ‒1)

Figure 1 shows developmental issues necessary for
performance enhancement of GaN MOSFETs. Since theGaN crystal is usually prepared through heteroepitaxial
growth on a substrate having a different lattice constant,the crystal contains a number of dislocations that affectdevice characteristics and reliability, so that it becomes
essential to improve the crystalline quality. It is reported
that a high crystalline quality of GaN can be obtained byinserting a buffer layer between the substrate and GaN
crystal and by optimizing the growth conditions of the
GaN crystal 14).

1.0E+12

Sapphire sub.

900 C

Anneal at 800 C

1.0E+111000 C

1.0E+10

0

0.2

0.4

0.6

0.8

1

E C ‒ E (eV)Figure 2

3.

Interface state density (D it ) of SiO2/GaN, annealed at
800, 900 and 1000°C.

Si ION IMPLANTATION IN GaN AND ITS18), 19)
ACTIVATION

We investigated the conditions for ion implantation and+activation annealing aimed at n -layer formation. Si as an

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High-Power Operation of Normally-Off GaN MOSFETs

n-type dopant was used for doping. First, un- and17−3
Mg-doped GaN ( [Mg] ~ 1x10 cm ) 2 μm in thickness
were grown on a sapphire substrate (0001)c by MOCVD.
Then, SiO2 screen oxide 20 nm in thickness was deposited on GaN using a PECVD to suppress any damage or
pollution due to ion implantation. Subsequently, Si ion
implantation was carried out in four steps in order toadjust the depth profile of Si atoms by 150 nm. The
implantation energy levels were 30, 60, 120 and 190 keV.
After the screen oxide was removed, 500-nm thick SiO2
capping layer was deposited. Activation annealing was
performed in an Ar ambient by a rapid thermal annealing(RTA), followed by removal of the capping layer. Finally,
the Hall measurement was carried out to determine thesheet resistance and sheet carrier density in the ionimplanted layer by the van der Pauw.
Figure 3 shows the results of Hall measurement of GaN
after Si ion implantation and activation annealing. It canbe seen that the activation ratio (the ratio of sheet carrier
density over Si dose) tends to decrease with lower Si
doses. This may be attributable to the compensation ofdonors by the energy level developed by crystalline
defects 20). The activation ratio of the ion-implanted layer
formed in the Mg-doped GaN was lower than that in the
undoped GaN, probably because activated donors werecompensated by the acceptors. The activation ratio ofactivation annealing at 1260°C for 30 sec was higher thanthat at 1200°C for 10 sec, indicating that a high thermal
budget is needed for activation. As the result, we were+successful in obtaining an n layer of sufficiently low
resistance with a sheet carrier density of 26 Ω/sq. and a
15−2sheet carrier density of approx. 3x10 cm (activation
15−2
ratio: 100%), using a Si dose of 3x10 cm . Moreover,activation was successfully carried out at a low Si dose of13−2
some 10 cm .

4.

FABRICATION AND LARGE CURRENTAND HIGH BREAKDOWN VOLTAGE OF21)~ 24)
GaN MOSFET

Having successfully formed an SiO2/GaN with a low-resis+
tance n layer and good interface quality, we proceeded
to fabricate GaN MOSFET based on these elemental
technologies. Please refer to the literature 25) for the device
design, since it is not possible to go into detail here
because of space limitations.
17−3First, Mg-doped GaN ([Mg] ~ 1x10 cm ) 1 μm inthickness was grown on a sapphire substrate (0001)c by+
MOCVD. Next, to form n layer, Si ions were implanted
into the source and drain regions to a depth of 150 nm
15−2with a total dose of 3.0x10 cm . And, activation annealing was performed in an Ar ambient by an RTA at 1260°C
for 30 sec. Next, gate oxide of SiO2 60 nm in thickness
was deposited on the GaN surface by PECVD. After that,annealing was performed in a nitrogen flow in an electric
furnace at 900°C for 30 min to reduce the interface states.
And, apertures were provided at the source and drain
regions by wet etching. After that, source and drain electrodes of Ti/Al were deposited by sputtering, followed bya lift-off process, and annealing was performed in an
nitrogen ambient at 600°C for 5 min. The sheet resistance+and contact resistance of the n layer were 65 Ω/sq. and−72
1.9x10 Ωcm . Finally, gate electrode of Ti/Au wasformed on the gate oxide layer of SiO2 by sputtering andlift-off.
Figure 4 shows the current-voltage (I-V) characteristics
of GaN MOSFET at 250°C. The channel length and width
are 4 μm and 16 mm, respectively. In the output characteristics, it has been observed that the drain current
changes by the gate voltage and that the drain current
Gate

Source1E+16n+Undoped GaN (1260℃, 30 s)

2.5

Vg = +14 V
+12 V
+10 V

I d (A)

2.0

1E+14

0.015

1.5
1E+13
Electrode ElectrodeIon ‒ implanted

1E+12

GaN
Sapphire sub.

1E+11
1E+14

1E+15

1E+16

Dose ( cm ‒2 )Figure 3

Relationship between sheet carrier density and Si
total doses.

+8 V

Vd = 0.1 V

0.010
0.005
0.000
‒5

1.0

1
0.1
0.01
1E ‑ 3
1E ‑ 4
1E ‑ 5
1E ‑ 6
1E ‑ 7
1E ‑ 8
1E ‑ 9|I d | (A)

100% activation

I d (A)

Sheet carrier density ( cm ‒2 )Sapphire sub.

Mg-doped GaN (1200℃, 10 s)

1E+13

n+

Mg-doped GaN

Mg-doped GaN (1260℃, 30 s)

1E+15

Drain

SiO2

0

5

Vg (V)

10

15

+6 V
0.5
0.0
‒0.5
0

+4 V

0 V to +2 V
5250 C
L ch = 4μm
Wch = 16 mm
1015

Vd (V)
Figure 4

Output characteristics at 250°C of GaN MOSFET withgate width of 16 mm. (Inset: transfer characteristics)

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High-Power Operation of Normally-Off GaN MOSFETs(a) Conventional

Vg = 0 V
G
S OxideN+
P
Potential
Field(b) RESURF type

Vd

Vg = 0 V

A
D
N+

x

G
S OxideN+
P

Vd
B

RESURF(N-)

C
D x
N+

Potential

Vd
x

Field

Drain bias at G-D

Leaning potential in RESURF→ Breakdown at gate side

→ Relax ﬁeld under gate side

Figure 5VdxSchematic of potential and field of (a) conventional
MOSFET and (b) RESURF-MOSFET.

The Si dose for RESURF layer formation was 6x1013−2
cm ; the sheet resistance and the sheet carrier density
12
after activation annealing were 23 kΩ/sq. and 1.1x10−2cm , respectively; the lengths for the channel and
RESURF were 4 μm and 20 μm, respectively; and thegate width was 150 mm.
Figure 6 shows the output characteristics of RESURFMOSFET. The breakdown voltage was higher than 1550 V,
and this value divided by the RESURF length, which is 80
V/μm largely surpasses the critical electric field of Si,
which is 30 V/μm. Moreover, the operation current exceeded 2.5 A. This is the first time in the world that a single
device of GaN MOSFET has achieved both 1550-V and
2.5-A operations. These results show that this lateral GaN
MOSFET can be applied in power switching devices.

Source
n+
3.0

Gate
SiO2

Drain
RESURF n+

Mg-doped GaN
Sapphire sub.
+14V

2.5

Drain current (A)increases and saturates depending on the drain voltage,
thus confirming transistor operation. The drain current at
a gate voltage of +15 V was more than 2 A. To the best of
our knowledge, the operation temperature of 250°C is thehighest in the world. Moreover, more than 1-A operationof GaN MOSFET was observed for the first time. In thetransfer characteristics, the threshold voltage is +3 V,
confirming normally-off operation. Furthermore, the gate
voltage at which weak inversion occurs exceeded 0 V; thesub-threshold slope was 328 mV/dec. ; the gate leakage
current was lower than 100 nA ; and the On/Off ratio was
5
10 .
With this device structure, however, since the electricfield concentrates on the drain side end of the gate oxide
layer, the breakdown voltage of the transistor is determined by that of SiO2. As a result, the breakdown voltage
is limited to 40 V at the most. In order to disperse the field
concentration, field concentration spots are intentionally–formed by inserting an n layer of REduced SURface Field(RESURF) 26) between the gate and the drain, thereby tilt+
ing the electric potential with respect to the n layer.
Figure 5 shows the schematics of (a) conventional
MOSFET and (b) RESURF-MOSFET, where the RESURF
is inserted between the gate and drain electrodes. In thecase of conventional MOSFETs, when the gate voltage Vg
is lower than the threshold voltage Vth, and the drain voltage Vd is extremely high, breakdown occurs in the gate
oxide layer near the spot “A” in Figure 5 (a). In the off
states, the source and gate are equipotential with theground, and the resistance of the gate oxide is higher
than that of the channel region. For these reasons, almost
all the electric field concentrates on the gate oxide, resulting in breakdown near there. In the case of RESURFMOSFET, on the other hand, the electric field concentrates on the two spots of the gate oxide marked “B” inFigure 5 (b) and the RESURF layer marked “C” in Figure
5 (b); more specifically, field concentration occurs on−
three spots including the n /p junction in the layer thickness direction. Therefore, the electric fields in the gate
oxide layer decrease thus increasing the breakdown voltage. We have fabricated GaN RESURF-MOSFETs byusing the Si ion implantation technique aforementioned toprepare the RESURF layer.

+12V

2.0

+10V

1.5
+8V
1.0
+6V
0.5
+4V

RT
L ch =4 μm
L res =20 μm
W ch =16 mm

V g = ‒10V

V g =0V to +2V

0.0
0

10

20

30

1400 1600 1800

Souce to drain voltage (V)Figure 65.

Output characteristics of GaN RESURF-MOSFET.

CONCLUSIONSA GaN-based MOSFET has been developed as a powerdevice to be incorporated in power supply circuits where
high-temperature, large-current and high-breakdown voltage operation is required.
+
Both the formation of n layer and the reduction of SiO2/
GaN interface states were needed for operation of GaN+
MOSFETs. The n layer was formed by Si ion implantation15
and activation annealing. Under the conditions of 3x10
−2
cm in Si ion total dose and of 1260°C for 30 sec in activation annealing, the sheet resistance and sheet carrier
15−2
density obtained were 26 Ω/sq. and 3x10 cm (activation ratio: 100%), respectively. Moreover, a high-quality
SiO2/GaN interface was obtained by annealing at 900°C
for 30 min. The interface states density calculated by the
C-V characteristics at 200°C and the Terman method was11−2−1
lower than 1x10 cm eV ( Ec – E = 0.4 eV ) .
Then a GaN MOSFET was fabricated on a sapphire

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High-Power Operation of Normally-Off GaN MOSFETs

substrate (0001)c. The device operation was confirmed at
250°C, the highest temperature in the world. The threshold voltage and the operation current were +3 V andlarger than 2 A, respectively. Moreover, a GaN RESURFMOSFET with higher breakdown voltage was fabricated,achieving the device operation of higher than 1550 V in
breakdown voltage and larger than 2.5 A in operation
current.
We believe that GaN MOSFETs will find applications in
broad fields where high-temperature operation is needed,
besides power supplies for automobiles and home appliances.

ACKNOWLEDGMENTS
This work has been carried out in industry-academia collaboration with numerous universities. We would like tooffer particular thanks to Professor Tat-Sing Paul Chowand Dr. Weixiao Huang (currently with Freescale
Semiconductor, Inc.) of Rensselaer Polytechnic Institute(RPI) in the U.S. for the constructive discussions on the
MOSFET process technology; Professor Tamotsu
Hashizume of Hokkaido University for his guidance ininterface characteristics evaluation technology; and Vice
President Yasuhiro Shiraki (professor emeritus of the
University of Tokyo) and Dr. Kentarou Sawano of Tokyo
City University for their making ion implantation equipment and RTA available for us.

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