TECHNICAL DATA SHEETJade 52131
8-channel 250 MHz A/D with DDC
3U VPX board with Kintex UltraScale FPGA

Complete radarand software radiointerface solution▪ Radar and software radio receiver▪ Wideband data acquisition▪ Communications receiver▪ Remote monitoring▪ Analog signal interface for data recording▪ Sensor interfaces

The Jade® 52131 is a multichannel, high-speed data converter withmultiband DDCs (digital downconverters). It is suitable forconnection to HF or IF ports of a communications or radar system. Its
built-in data capture feature offers an ideal turnkey solution as well as aplatform for developing and deploying custom FPGA-processing IP.
It includes eight A/Ds, a complete multi-board clock and sync section and a large DDR4memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model
52131 includes optional high-bandwidth connections to the Kintex UltraScale FPGA forcustom digital I/O.

FEATURES▪ Xilinx® Kintex® UltraScale™ FPGA
▪ Eight 250 MHz 16-bit A/Ds

▪ Multichannel, multiboard
synchronization with clock/sync bus▪ Eight multiband DDCs (digitaldownconverters)▪ Optional clock/sync generator for
multiboard systems▪ 5 GB of 2400 MHz DDR4 SDRAM▪ PCI Express interface (Gen. 1 & 2) up tox4

▪ Sample clock synchronization to anan external reference▪ LVPECL clock/sync bus for
multiboard synchronization▪ Programmable frequency synthesized
sample clock generator▪ Sample clock synchronization to an
external reference▪ Optional LVDS port and gigabit serial
connections for custom FPGA I/O▪ Compatible with VITA-46, VITA-48 andVITA-65 (OpenVPX™ Specification)▪ Ruggedized and conduction-cooledversions▪ Navigator Design Suite for softwareand custom IP developmentmrcy.com

TECHNICAL DATA SHEETJade 52131

52131 BLOCK DIAGRAM
Click on a block for more information.

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TECHNICAL DATA SHEETJade 52131

THE JADE ARCHITECTURE
Each member of the Jade family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The factory-installed functions include eight or 16
A/D acquisition IP modules for simplifying data capture andtransfer.
Evolved from the proven designs of Mercury’s Cobalt and Onyx
families, Jade raises the processing performance with the newflagship family of Kintex UltraScale FPGAs from Xilinx. As thecentral feature of the board architecture, the FPGA has accessto all data and control paths, enabling factory-installed
functions including data multiplexing, channel selection, datapacking, gating, triggering and memory control.
The Jade architecture organizes the FPGA as a container fordata-processing applications where each function exists as anintellectual property (IP) module. Each member of the Jade
family is delivered with factory-installed applications ideallymatched to the board’s analog interfaces.
The 52131 factory-installed functions include eight A/Dacquisition IP modules for simplifying data capture and transfer.
Each of the eight acquisition IP modules contains a powerful,programmable DDC IP core; an IP module for DDR4 SDRAM
memory; a controller for all data clocking and synchronization
functions; a test signal generator; and a PCIe interface. These
complete the factory-installed functions and enable the 52131 tooperate as a complete turnkey solution for many applications,
thereby saving the cost and time of custom IP development.

EXTENDABLE IP DESIGNFor applications that require specialized functions, users caninstall their own custom IP for data processing. The Navigator®
FPGA Design Kits include the board’s entire FPGA design as ablock diagram that can be edited in Xilinx’s Vivado tool suite.
In addition to the block diagrams, all source code and complete
IP core documentation is included. Developers can integrate
their own IP along with the wide range of IP functions containedin the Navigator® IP library, or use the Navigator® kit tocompletely replace the IP with their own.

XILINX KINTEX ULTRASCALE FPGAS
Depending on the requirements of the processing task, the Kintex
Ultrascale can be selected from a range of FPGAs: KU035 through
KU115. The KU115 features 5520 DSP48E2 slices and is ideal formodulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between

mrcy.comtransmission and reception. For applications not requiring large
DSP resources or logic, a lower-cost FPGA can be installed.

A/D CONVERTER STAGE
The board's analog interface accepts eight analog HF or IF
inputs on front panel MMCX connectors with transformer
coupling into four Texas Instruments ADS42LB69 dual 250 MHz,
16 bit A/D converters.
The digital outputs are delivered into the Kintex UltraScale
FPGA for signal-processing or routing to other module
resources.

A/D ACQUISITION IP MODULES
The 52131 features eight A/D Acquisition IP Modules for easily
capturing and moving data. Each IP module can receive datafrom any of the eight A/Ds or a test signal generator.
Each IP module has an associated DMA engine for easily moving A/Ddata through the PCIe interface. These powerful linked-list DMA
engines are capable of a unique Acquisition Gate Driven mode. In thismode, the length of a transfer performed by a link definition need not
be known prior to data acquisition; rather, it is governed by thelength of the acquisition gate. This is extremely useful in applications
where an external gate drives acquisition and the exact length of thatgate is not known or is likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing A/D channel ID, a sample-accurate
time stamp and data length information. These actions simplify
the host processor’s job of identifying and executing on the data.

DDC IP CORES
Within each A/D Acquisition IP Module is a powerful DDC IP
core. Because of the flexible input routing of the A/DAcquisition IP Modules, many different configurations can beachieved including one A/D driving all eight DDCs or each of theeight A/Ds driving its own DDC.
Each DDC has an independent 32-bit tuning frequency setting that
ranges from DC to ƒs, where ƒs is the A/D sampling frequency. Each
DDC can have its own unique decimation setting, supporting as many
as eight different output bandwidths for the board. Decimations canbe programmed from 2 to 32,768 providing a wide range to satisfy
most applications.
The decimating filter for each DDC accepts a unique set ofuser-supplied 18-bit coefficients. The 80% default filters deliver
an output bandwidth of 0.8*ƒs/N, where N is the decimation
setting. The rejection of adjacent-band components within the3

TECHNICAL DATA SHEETJade 52131

80% output bandwidth is better than 100 dB. Each DDC delivers
a complex output stream consisting of 24-bit I + 24-bit Q or 16bit I + 16-bit Q samples at a rate of ƒs/N.

CLOCKING AND SYNCHRONIZATION
An internal timing bus provides all timing and synchronization
required by the A/D converters. It includes a clock, a sync andgate or trigger signals. An on-board clock generator receives anexternal sample clock from the front panel MMCX connector.
This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit.

MEMORY RESOURCES
The 52131 architecture supports a 5 GB bank of DDR4 SDRAM
memory. User-installed IP along with the Mercury-supplied
DDR4 controller core within the FPGA can take advantage of thememory for custom applications.

PCI EXPRESS INTERFACEThe 52131 includes an industry-standard interface fullycompliant with PCI Express Gen. 1, 2 and 3 bus specifications.
Supporting PCIe links up to x4, the interface includes multiple
DMA controllers for efficient transfers to and from the board.

In an alternate mode, the sample clock can be sourced from an
on-board programmable voltage-controlled crystal oscillator. In
this mode, the front panel MMCX connector can be used toprovide a 10 MHz reference clock for synchronizing the internaloscillator.
A front panel 12-pin LVPECL Clock/Sync connector allows
multiple boards to be synchronized. In the slave mode, it
accepts LVPECL inputs that drive the clock, sync and gatesignals. In the master mode, the LVPECL bus can drive thetiming signals for synchronizing multiple boards.
Up to three additional boards can be driven from the LVPECL
bus master, supporting synchronous sampling and sync
functions across all connected boards. For systems requiringhigh channel counts, the Model 5292 System Synchronization
and Distribution board can synchronize up to four 52131s.

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4TECHNICAL DATA SHEETJade 52131

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IPcores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installed
FPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jadedesign. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of all
hardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSPcomponents. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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TECHNICAL DATA SHEETJade 52131

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEETJade 52131

FRONT PANEL CONNECTIONS
The front panel includes ten MMCX
coaxial connectors for clock, trigger, andanalog input signals, and a 12-pin Sync
Bus input/output connector. The front
panel also includes seven LEDindicators.
▪ Analog InputConnectors: Eight
MMCX coaxialconnectors, labeled In
1, 2, 3, 4, 5, 6, 7, and8: one for each
ADC input channel.
▪ ADC Overload LED:
There is one red OV(overload) LED for all
ADC inputs. This LED
indicates either anoverload detection inone of the ADS42LB69s,
or an ADC FIFO overrun.
▪ Sync Bus Connector:
The 12-pin µSync front
panel connector,
labeled SYNC/GATE,provides clock, sync andgate input/output pins
for the Low Voltage
Positive Emitter
Coupled Local (LVPECL) Sync Bus.
▪ Trigger Input Connector: One
MMCX coaxial connector, labeledTRIG, for input of an external trigger.
▪ PPS LED: The green PPS LED
illuminates when a valid PPS signal isdetected. The LED will blink at therate of the PPS signal.
▪ Clock Input Connector: One MMCX
coaxial connector, labeled CLK, forinput of an external sample clock.
▪ Clock LED: The green CLK LED
illuminates when a valid sample clocksignal is detected. If the LED is notilluminated, no clock has beenmrcy.comdetected and no data from the input
stream can be processed.
▪ Master LED: The yellow MAS LED
illuminates when this 71131 is the Sync
Bus Master. When only a single 71131
is used, it must be a Master.
▪ Link LED: The green LNK LED
indicates the link speed when a valid
link has been established over thePCIe interface, as follows: Gen 1 - LEDblinks slowly (less than once persecond); Gen 2 - LED blinks about
once per second; Gen 3 - LED will be
constantly on.
▪ User LED: The green USR LED is foruser applications.
▪ Over Temperature LED: The red
TMP LED illuminates when an overtemperature or over-voltage
condition is indicated by any of thetemperature/voltage sensors on the71131 PCB.

SPECIFICATIONS
Front Panel Analog Signal Inputs
Input Type: Transformer-coupled,
front panel female MMCX connectors
Transformer Type: Coil Craft WBC46TLB
Full Scale Input: +4 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz

A/D Converters
Type: Texas Instruments ADS42LB69
Sampling Rate: 10 MHz to 250 MHz
Resolution: 16 bits

Digital Downconverters
Quantity: Eight channels
Decimation Range: 2x to 32,768x in
three stages of 2x to 32x
LO Tuning Freq. Resolution: 32 bits, 0to ƒs

FIR Filter: 18-bit coefficients, 24-bit
output, user-programmablecoefficients
Default Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dB
stopband attenuation

Sample Clock Sources
On-board clock synthesizer

Clock Synthesizer
Clock Source: Selectable from onboard programmable VCXO (10 to 810MHz), front panel external clock or
LVPECL timing bus
Synchronization: VCXO can be locked
to an external 4 to 180 MHz PLL
system reference, typically 10 MHz
Clock Dividers: External clock or VCXO
can be divided by 1, 2, 3, 4, 6, 8, or 16
for the A/D clock

External Clock
Type: Front panel female MMCX
connector, sine wave, 0 to +10 dBm,
AC-coupled, 50 ohms, accepts 10 to800 MHz divider input clock or PLL
system reference

Timing Bus
12-pin connector LVPECL bus
includes, clock/sync/gate/PPS inputs
and outputs; TTL signal forgate/trigger and sync/PPS inputs

External Trigger Input
Type: Front panel female MMCX
connector, LVTTLFunction: Programmable functions
include: trigger, gate, sync and PPS

Field Programmable Gate Array
Standard: Xilinx Kintex UltraScaleXCKU035-2▪ Option -084: Xilinx Kintex
UltraScale XCKU060-2▪ Option -087: Xilinx Kintex
UltraScale XCKU115-2

LO SFDR: >108 dB
Phase Offset Resolution: 32 bits, 0 to360 degrees

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TECHNICAL DATA SHEETJade 52131

Custom I/O

ORDERING INFORMATION

Option -104: Connects 24 LVDS pairs between the FPGA andVPX P2ModelDescription

Option -105:Connects eight gigabit serial lanes between theFPGA and VPX P1

52131

8-channel 250 MHz A/D with DDCs 3U VPX board withKintex UltraScale FPGAMemory
Type: DDR4 SDRAM
Size: 5 GB
Speed: 1200 MHz (2400 MHz DDR)

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing
Option -702: L2 (air-cooled)▪ Operating Temp: -20° to 65° C

Options:-084

XCKU060-2 FPGA-087

XCKU115-2 FPGA-104

LVDS FPGA I/O through P14 connector-105

Gigabit serial FPGA I/O through P16 connector-702

Air-cooled, Level 2-763

Conduction-cooled, Level 3

Contact Mercury for compatible option combinations and complete
specifications of rugged and conduction-cooled versions. Options maychange, so be sure to contact Mercury for the latest information.

ACCESSORY PRODUCTS▪ Storage Temp: -40° to 100° C
Model

Description

Option -763: L3 (conduction-cooled)5292

High-Speed Synchronizer & Distribution Board▪ Operating Temp: -40° to 70° C

9192

Rackmount High-Speed System Synchronizer▪ Relative Humidity: 0 to 95%, non-condensing▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: VPX board▪ Depth: 170.61 mm (6.717 in)▪ Height: 100 mm (3.937 in)
Weight: Approximately 14 oz (400 grams)

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TECHNICAL DATA SHEETJade 52131

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR JADE PRODUCTS

Mercury offers development systems for Jade products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system thatensures optimum performance of Jade boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORSJade products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Jade Model 71131 XMC (8Channel 250 MHz A/D with DDC, Kintex UltraScale FPGA) has thefollowing variants:
Model
52131

3U VPX board (single XMC)

54131

3U VPX board (single XMC with optical/backplane RF)

57131

6U VPX board (single XMC)

58131

6U VPX board (dual XMC)

71131

XMC module78131

PCIe board (single XMC)

Corporate Headquarters
50 Minuteman RoadAndover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury InternationalLearn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/CF52131

Visit: mrcy.com/go/MP52131+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation ThatMatters, Jade and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2023 Mercury Systems, Inc. 1-0-012723-DS-J52131

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