SDカー ド
MLC:8-256GB
aMLC:4-128GB(ET1288+SanDisk 15nm MLC)

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株式会社アドテック

SD 4-256GB

REVISION HISTORY
Revision

Description

Date

V1.1

First released

August 2015

V2.1

For SanDisk 1Znm solution

January 2017

V2.2

Updated part number information

May 2017

V2.3

Added sMLC 4GB~32GB

May 2017

V2.4

Added Product Feature information

June 2017

V2.5

Added MLC 128GB/256GB and sMLC 64GB/128GB

October 2017

V2.6

Added ESD Ability and Table 4March 2018

V2.7

Added waterproof and power consumption information

April 2018

V2.8

Name changed from sMLC to aMLC.

June 2018

V2.9Added 1.3 TBW (Tera Byte Written).

March 2020

V3.0

Added 1.2 Product Features and 3.8 Dust proof

July 2020

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SD 4-256GB
1. Product Introduction
1.1. Overview
The Industrial SD Card is designed for demanding industrial applications.
Moreover, the Industrial SD Card supports Ultra High Speed (UHS) interface transfer mode,
provides high write/read data transfer rate, high random IOPS, sudden Power-Fails protection,
adaptive static wear-leveling, read/program disturb management, etc.
It was designed to meet the high quality, high reliability, high performance, and versatileenvironmental requirements.
1.2. Product Features⚫ Interface: 9 pins SD standard interface⚫ Compliant SD Card Specification 3.0⚫ Density support:◼ MLC:8GB~256GB◼ aMLC (Advanced MLC, single bit per cell MLC): 4GB~128GB⚫

Bus Speed Mode:◼ DS-Default Speed mode: 3.3V signaling, frequency up to 25MHz, up to 12.5MB/sec◼ HS-High Speed mode: 3.3V signaling, frequency up to 50MHz, up to 25MB/sec◼ SDR12: 1.8V signaling, frequency up to 25MHz, up to 12.5MB/sec◼ SDR25: 1.8V signaling, frequency up to 50MHz, up to 25MB/sec◼ SDR50: 1.8V signaling, frequency up to 100MHz, up to 50MB/sec◼ SDR104: 1.8V signaling, frequency up to 208MHz, up to 104MB/sec◼ DDR50: 1.8V signaling, frequency up to 50MHz, sampled on both clock edges, upto 50MB/s

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Operating at -25°C to 85°C
Flash: MLC NAND Flash (SDTNSGAMA-008G, SDTNSGAMA-016G)
Controller: ET1288
Program/Erase Cycle: 3,000 Cycles (MLC)
Program/Erase Cycle: 20,000 Cycles (aMLC)
Built-in ECC corrects up to 43 bits/1 KBRead disturbance management (Auto-Refresh)
Adaptive wear levelingManagement of sudden power-fails
SMART Function support
Support CPRM (Content Protection for Recordable Media) of SD Card
Support Water & Dust proof IEC 60529 IP58
aMLC (Advanced MLC, single bit per cell MLC) support, enhance the performance andproduct endurance.

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1.3. TBW (Tera Bytes Written)
Capacity

4GB

8GB

16GB

32GB

64GB

128GB

256GB

MLC

―

19.6TB

39.2TB

78.4TB

156.8TB

313.6TB

627.2TB

aMLC

65.3TB

130.6TB

261.2TB

522.4TB

1047.3TB 2094.6TB―*The endurance of disk could be varying based on user behavior, NAND endurance cycles, and write amplification factor.
It is not guaranteed by flash vendor.
*Client workload by JESD-219A

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SD 4-256GB
2 . SD Card Interface Description
2.1 SD Pin Assignment
Table 1: SD Bus Mode Pin Definition
Pin #Name

TypeSD Description

1

CD/DAT3

I/O

Card Detect / Data Line [Bit3]

2

CMD

PPCommand / Response3

VSS

Supply Voltage Ground

4VDD

S

Supply Voltage

5

CLKIClock

6VSS

Supply Voltage Ground7DAT0I/O

Data Line [Bit 0]

8DAT1I/O

Data Line [Bit 1]

9DAT2I/O

Data Line [Bit 2]

Notes:1) S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers.
2) The extended DAT Lines (DAT1-DAT3) are input on power up. They start to operate as
DAT lines after SET_BUS_WIDTH command. The Host shall keep its own
DAT1-DAT3 lines in input mode, as well, while they are not used. It is defined so, in orderto keep compatibility to Multi-media Cards.
3) After power up this line (Pin1) is input with 50Kohm pull-up (can be used for card detection
or SPI mode selection). The pull-up should be disconnected by user,
during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command.
Table 2: SPI Bus Mode Pin Definition
Pin #Name

TypeSD Description

1

CSI

Chip Select (neg true)

2

DII

Data In

3VSSS

Supply Voltage Ground

4

VDDS

Supply Voltage

5

SCLKIClock

6VSSS

Supply Voltage Ground

7DOO

Data Out8RSVReserved9RSVReserved

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Figure 1: Functional Diagram

2.2 SD Bus Topology
The SD bus has six communication lines and three supply lines:⚫ CMD: Command is bi-directional signal. (Host and card drivers are operating in push pullmode.)⚫ DAT0-3: Data lines are bi-directional signals. (Host and card drivers are operating in pushpull mode.)⚫ CLK: Clock is a host to cards signal. (CLK operates in push pull mode.)⚫ VDD: VDD is the power supply line for all cards.
⚫ VSS: VSS is the power ground line.
During the initialization process, commands are sent to each card individually, allowing theapplication to detect the cards and assign logical addresses to the physical slots. Data is always
sent to each card individually. However, to simplify the handling of the card stack, after
initialization, all commands may be sent concurrently to all cards. Addressing
information is provided in the command packet.

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SD 4-256GB

The following figure shows the bus topology of several cards with one host in SD Bus mode.

Figure 2: Memory Card System Bus Topology

2.3 SPI Bus Topology
The memory Card SPI interface is compatible with SPI hosts available on the market. As anyother SPI device, the SD Memory Card SPI channel consists of the following 4 signals:⚫
⚫
⚫
⚫

CS: Host to card Chip Select signal.
CLK: Host to card clock signal.
Data In: Host to card data signal.
Data Out: Card to host data signal.

Another SPI common characteristic, which is implemented in the Memory Card as well, is byte
transfers. All data tokens are multiples of 8bit bytes and always byte aligned to the CS signal.
The card identification and addressing methods are replaced by a hardware Chip Select(CS) signal. There are no broadcast commands, a card (slave) is selected by asserting (activelow) the CS signal. The CS signal shall be continuously active for the duration of the SPI
transaction (command, response, and data). The only exception occurs during card programming,
when the host can de-assert the CS signal without affecting the programming process.
The SPI interface uses the 7 out of the SD 9 signals (DAT1 and DAT2 are not used, DAT3 is theCS signal) of the SD bus.

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SD 4-256GB
3 . Specifications
3.1. Performance
Max. Data Transfer Rate
◼ Read: 90MB/s; Write: 70MB/s
3.2. NAND Flash Memory
Industrial SD Card uses Multi Level Cell (MLC) NAND Flash memory, which is non- volatility,
high reliability and highspeed memory storage.
3.3. Power Requirement
3.3.1. DC Input Voltage◼ 2.7V to 3.6V
3.4. Temperature Range◼ -25°C to +85°C
3.5. Humidity
Relative Humidity: 5-95%, non-condensing
3.6. Waterproof
Waterproof level: IEC 60529 IPX8.
Test Condition

Referred standard

Depth of water 1.5m for 30 mins.

IEC 60529 IPX8

3.7. ESD Ability
Test Condition

Referred standard⚫ Contact discharge: ± 2KV, ± 4KV

SD Spec. Appendix D.1⚫ Air discharge: ± 4KV, ± 8KV, ± 15KVSD Spec. Appendix D.2

3.8. Dust Proof
Dust proof level: IEC 60529 IP5X.
Test Condition

Referred standard

Depression of 2 KPa, Talcum powder 2kg/m³, 8 hrs. IEC 60529 IP5X

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SD 4-256GB

4 . Electrical Specifications
4.1. General DC Characteristic
Table 3: Absolute Maximum Ratings
SymbolParameter

Min.

Max.

UnitNoteTstorage

Storage Temperature-4085°C-Ta

Ambient Operating Temperature-2585°C-VI

3.3V External Input Voltage

-0.3

3.6V

-

Table 4: Power Consumption
SymbolIRead

Parameter

Min.

Typ.

Max.

Unit

Read Current at 3.3V (High Speed Mode)-

76200mA

Read Current at 1.8V (UHS-I Mode)-

220800mA

Write Current at 3.3V (High Speed Mode)-

80200mA

Write Current at 1.8V (UHS-I Mode)-

210800mA

Standby Current-0.615mA

IWriteISTBY

4.2. Bus Operation Conditions for 3.3V Signaling
4.2.1 Threshold Level for High Voltage Range
Table 5: Threshold Level for High Voltage
SymbolMinMax

Unit

Supply Voltage

Parameter

VDD

2.7

3.6

V

Output High Voltage

VOH0.75* VDD

Output Low Voltage

VOL

Input High Voltage

VIH

Input Low Voltage

VIL

RemarkV

IOH=2mA VDD min0.125* VDD

V

IOL=2mA VDD min

0.625* VDD

VDD+0.3

V

Vss-0.3

0.25*VDD

V

250

ms

From 0V to VDD minRemark

Power Up Time4.2.2 Peak Voltage and Leakage Current
Table 6: Peak Voltage and Leakage Current
Parameter
Peak voltage on all lines

SymbolMinMaxUnit-0.3

VDD+0.3

V-1010uA-1010uA

All Inputs
Input Leakage Current
All Outputs
Output Leakage Current

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SD 4-256GB
4.2.3 Bus Signal Line Load
Table 7: Bus Operating Conditions - Signal Line's Load
Parameter

Symbol

Min

Max

Unit

Pull-up resistance

RCMDRDAT

10100KΏTo prevent bus floating

Total bus capacitance foreach signal line

CL

40pF

1 card CHOST+CBUS shall not exceed 30pF

Card capacitance foreach signal pin

CCARD10pF

16nH90KΏ

May be used for card detection

5uF

To prevent inrush current

Maximum signalinductancePull-up resistance insidecard(pin1)

RDAT3

Capacity Connected toPower LineCC10Remark

4.2.4 Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related tothe supply voltage.

Figure 4: Bus Signal Levels

To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card
input and output voltages shall be within the specified ranges shown in Table 6 for any
VDD of the allowed voltage range.

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SD 4-256GB
4.2.5 Bus Timing (Default)

Figure 5: Card input Timing (Default Speed Card)

Figure 6: Card Output Timing (Default Speed Mode)
Table 8: Bus Timing-Parameters Values (Default Speed)
Parameter

SymbolMin.

MaxUnit

RemarkClock CLK （All values are referred to min（VIH）and max（VIL）
Clock frequency data transfer

fpp025MHz

CCARD ≤ 10pF (1 card)

Clock frequency Identification

fOD0(1)/100400

KHz

CCARD ≤ 10pF (1 card)

Clock low time

tWL

10ns

CCARD ≤ 10pF (1 card)

Clock high time

tWH10ns

CCARD ≤ 10pF (1 card)

Clock rise timetTLH

10ns

CCARD ≤ 10pF (1 card)

Clock fall timetTHL10ns

CCARD ≤ 10pF (1 card)

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SD 4-256GB

Inputs CMD, DAT (referenced to CLK)
Input set-up time

tISU

5ns

CCARD ≤ 10pF (1 card)

Input hold time

tTH

5ns

CCARD ≤ 10pF (1 card)

Output Delay time during Data
Transfer Mode

tODLY

014ns

CL ≤ 40pF (1 card)

Output Hold time

tOH

050ns

CL ≤ 40pF (1 card)

Outputs CMD, DAT (referenced to CLK)

(1) 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock isrequired (refer to Chapter 4.4-Clock Control)

4.2.6 Bus Timing (High-Speed Mode)

Figure 7: Card Input Timing (High Speed Card)

Figure8: Card Output Timing (High Speed Mode)

13

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SD 4-256GB
Table 9 : Bus Timing – Parameters Values(High Speed)
Parameter

Symbol

Min.

Max

Unit

RemarkClock CLK （All values are referred to min（VIH）and max（VIL）
Clock frequency data transfer
Clock low time
Clock high time
Clock rise time
Clock fall time
Inputs CMD, DAT (referenced to CLK)
Input set-up time
Input hold time
Outputs CMD, DAT (referenced to CLK)

MHznsnsnsnsCCARD ≤CCARD ≤CCARD ≤CCARD ≤CCARD ≤6ns

CCARD ≤ 10pF (1 card)

2ns

CCARD ≤ 10pF (1 card)

nsCL ≤ 40pF (1 card)

nspF

CL ≥ 15pF (1 card)
1 card

fpp
tWL
tWH
tTLH
tTHL

077tISUtTH50

33tODLY
14Output Delay time during Data Transfer Mode
Output Hold time
2.5tOH40CLTotal System capacitance for each line11) In order to satisfy sever timing, host shall drive only one card.

10pF (1 card)
10pF (1 card)
10pF (1 card)
10pF (1 card)
10pF (1 card)

4.3 Bus Operation Conditions for 1.8V Signaling
4.3.1 Threshold Level for High Voltage Range
Table 10: Threshold Level for High Voltage
Parameter

SymbolMinMax

Unit

RemarkSupply Voltage

VDD

2.7

3.6

VRegulator Voltage

VDDIO

1.7

1.95

V

Generated by VDD

Output High Voltage

VOH

1.4

V

IOH=2mA VDD min

Output Low Voltage

VOL0.45

V

IOL=2mA VDD min

Input High Voltage

VIH

1.27

2.0V

Input Low Voltage

VIL

Vss-0.30.58

V

4.3.2 Peak Voltage and Leakage Current
Table 11: Peak Voltage and Leakage Current
Parameter
Input Leakage Current

SymbolMinMaxUnit-22uA

14Remark
DAT3 pull-up is disconnected

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SD 4-256GB

4.3.3 Bus Timing Specification in SDR12, SDR25, SDR50 and SDR104 Modes
4.3.3.1 Clock Timing

Figure 9: Clock Signal Timing
Table 12: Clock Signal Timing
SymboltCLKMinMax

Unit

Remark

4.8-ns208MHz (Max.), Between rising edge, VCT=0.975V-tCR, tCF

0.2* tCLKtCR, tCF < 2.00ns (max.) at 208MHz, CCARD=10pF
tCR, tCF < 2.00ns (max.) at 100MHz, CCARD=10pF
The absolute maximum value of tCR, tCF is 10ns

ns

regardless of clock frequency
Clock Duty

3070%

4.3.3.2 Card Input Timing

Figure 10: Card Input Timing
Table 13: SDR50 and SDR104 Input Timing
SymbolMinMaxUnit

SDR104 modetIS

1.40-ns

CCARD = 10pF, VCT = 0.975V

tIH

0.80

ns

CCARD = 5pF, VCT = 0.975V

SymbolMinMaxUnit

SDR12, SDR25 and SDR50 modestIS

3.00-ns

CCARD = 10pF, VCT = 0.975VtIH0.80-ns

CCARD = 5pF, VCT = 0.975V

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SD 4-256GB
4.3.3.3 Card Output Timing
4.3.3.3.1 Output Timing of Fixed Data Window (SDR12, SDR25 and SDR50)

Figure 11: Output Timing of Fixed Date Window
Table 14: Output Timing of Fixed Data Window
SymbolMinMax

Unit

tODLY－7.5nstCLK ≥ 10.0ns, CL=30pF, using driver Type B,
for SDR50.

14

nstCLK ≥ 20.0ns, CL=40pF, using driver Type B,
for SDR25 and SDR12.

－ns

Hold time at the tODLY (min.). CL=15pFtODLY
tOH

1.5Remark4.3.3.3.2 Output Timing of Variable Window (SDR104)

Figure 12: Output Timing of Variable Data Window
Table 15: Output Timing of Variable Data Window
SymbolMinMaxUnit

RemarktOP-2UI

Card Output Phase

ΔtOP-350

+1550

ps

Delay variation due to temperature change after tuning

tODW

0.60

-UI

tODW = 2.88ns at 208MHz

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SD 4-256GB

5. Mechanical Dimensions
The mechanical dimensions of industrial SD card were basically followed themechanical form factor definitions on SD-Memory card specifications which constructed by SD
card association.

Figure 13: Top View

Figure 15: Side View
Figure 14: Bottom View

17

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SD 4-256GB

6. Ordering Information
Flash Type

MLC

aMLC

Part Number
EHC08GMBWGBECD
EHC16GMBWHBECD
EHC32GMBWHBECD
EXC64GMBWHBECD
EXC12GMBWHBECD
EXC25GMBWHBECD
EHC04GPBWGBECDA
EHC08GPBWHBECDA
EHC16GPBWHBECDA
EHC32GPBWHBECDA
EXC64GPBWHBECDA
EXC12GPBWHBECDA

18Capacity
8GB
16GB
32GB
64GB
128GB
256GB
4GB
8GB
16GB
32GB
64GB
128GB

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