DATASHEET

VP831

3U VPX FPGA Processing Card Virtex UltraScale+, Zynq UltraScale+, FMC+
The VP831 is a 3U VPX high-performance
FPGA processing board featuring Xilinx®
Virtex UltraScale+™ and Zynq® UltraScale+™
technology. A technology upgrade from theexisting VP889 product aligned with theSensor Open Systems Architecture™ (SOSA)
technical standard, it is designed for the mostdemanding, mission critical military/defense
and commercial applications such ascommunications, sensor processing, radar,and electronic warfare just to name a few.
SecureThe Zynq UltraScale+ multiprocessor systemon-chip (MPSoC) brings advanced security
to the forefront. The VP831 is capable ofadvanced encrypted bit streams and secureboot capability, enabled by Xilinx tools. Thismakes it an ideal tool for applications where IP
security is a top concern.
Heterogeneous Processing Capability
Many RF and signal processing systems
require both a streaming DSP with an
FPGA and a general-purpose processor for
decisions and control. Traditionally, theseprocessing requirements were handled
by separate processing cards. With theVP831, both functions in a single module
are available by leveraging application andreal-time processing ARM cores of theZynq UltraScale+ MPSoC. Including theZynq UltraScale+ MPSoC removes theneed for a single board computer in some
applications, providing customers an efficient
way to maximize system performance while
reducing complexity.

Flexibility You Need for the SystemYou Want
The VITA 57.4-compliant FMC+ site allows
users to take advantage of Abaco’s industryleading FMC I/O portfolio. Modular I/O built
on an FMC+ standard interface enables
engineers to easily upgrade to futuretechnology without a complete systemredesign. Availability of both low-latency
LVDS data bus and JESD204B/C high-speed
serial interface makes the VP831 a versatilesolution for many RF data acquisition
applications.
Offload Data More Efficiently
The VP831 has VPX backplane interfacesaligned with the SOSA RF payload slot
profile, supporting 40/100 Gigabit Ethernet
data plane, PCIe Gen3 x4 expansion planeand Ethernet control plane connections to ahost computer or other payloads. With theflexibility of different RF front-ends and dataconverters, even these modern highspeed
data connections might be too slow for adirect transfer. To overcome this challenge,
the VP831 is available with an optional dual
channel 100 Gigabit Ethernet fiber optic
interface for transfers up to 25 GB/s.
The VP831 is available with two cooling
options, air or conduction, making it an ideal
COTS product for early designs and capableof being deployed into operational assets.
When paired with Abaco’s extensive portfolioof multi- architecture processing boards
including SBCs, GPGPUs, and fabric switches
the state of-the-art VP831 enables systems
to be built from leading edge, interoperable
components.

FEATURES:• Two product releases- Gen1, first in a series- Gen2, family upgrade• Dual FPGA architecture- Virtex UltraScale+- Zynq UltraScale+ MPSoC(ZU3EG in Gen1, ZU5EG inGen2)• Application Processing Unit
- Quad-core ARM Cortex-A53• Real-time Processing Unit
- Dual-core ARM Cortex-R5• Up to 18 GBytes DDR4
• FireFlyTM Gen2 Optical
Transceivers option• I/O- 10/40G Ethernet (100G
Ethernet support over copperin Gen2)- PCIe Gen3 x4- Gigabit Ethernet in Gen1,• 10G Ethernet in Gen2
- Dual 100G Ethernet optical- 8 LVDS GPIO
- RF-to-backplane (NanoRF)
in a conduction cooled
configuration with anaccompanying FMC; RF-thrufront-panel in an air cooled• VITA 57.4 HSPC FMC+ site
interfacing with the UltraScale+• Aligned to SOSA standard• Air-Cooled / Conduction Cooled
configurations available• MIL-I-46058C compliant
conformal coating (optional)

DATASHEET

VP831 3U VPX FPGA Processing Card Virtex UltraScale+, Zynq UltraScale+, FMC+
Specifications

Block diagram*

Physical Specifications• 3U VPX 1.0” pitch• Air-cooled or conduction cooled* Intended as a reference for basic features and connections and not an actual product layout or design

Real-time Processing Unit (Zynq)• Dual-core ARM Cortex-R5 MPCore• Up to 600MHzMemory• Two 64-bit 8GBytes DDR4 (16GB total)
memory blocks; up to 2400 Mb/s to FPGA
• 32-bit 2GBytes DDR4 memory to Zynq
FPGA Mezzanine Card (FMC) Support• 1x HSPC FMC+ site (Gen2)• Configurable with Abaco’s FMC portfolio
SOSA Aligned VPX Backplane Options• P1.1 to P1.4, 4x MGT @ 25.78125 Gb/s
(10.3125 Gb/s in Gen1) line rate
• P1.5, 1x MGT @ 10.3125 Gb/s
• (1.25 Gb/s in Gen1) line rate
• P1.8, 1x MGT @ 10.3125 Gb/s
• (1.25 Gb/s in Gen1) line rate
• P1.9 to P1.12, 4x MGT @ 16.0 Gb/s
• (8.0 Gb/s in Gen1) line rate
Flexible RF/Optical Backplane Options• Dual NanoRF 10 port connector option inconduction cooled for ADC/DAC/ CLK/TRIG (when used with an FMC)
• Dual 4-lane bidirectional optical interface
via FireFly Gen2 (optional) - 100G Ethernet
or Aurora independent channels up to 25
GB/s
Operating Temperature• 0°C to +55°C (Level 1 air-cooledenvironment with 400 LFM mean airflow)• -40°C to +70°C (Level D conduction
cooled environment at the card thermalinterface)

UART/JTAG
to USB2Gb BPI
Flash(FPGA Config)

1Gb QSPI
Flashx8(Zynq Boot)

Zynq PS
2GB DDR4

Xilinx
Zynq Ultrascale+XCZU3EG/5EGx32

A484 19mm / C784 23mm

uSD
CardSDIOFPGA PL
4GB DDR4FPGA PL
4GB DDR4x64x64(Opt. 8GB)

(Opt. 8GB)JTAG

FMC Site

12V/3.3V

JTAG

DPutp01 10GBASE-KREP00-EP03 PCIe Gen3 x4

XCVU5P/XCVU9P
B2104 47.5mm Package

EP04-EP07 User Def. 8-pair LVDS GPIO
SATA3.0
UART RX/TX
CPutp01

RS232
COMGigE
PHYCPutp01

Digital
Domain Clock
Generation

P1

DP01 40GBASE-KR4

XilinxVirtex Ultrascale+

160 SE IO / 80 LVDS
24x MGT / 16Gbps

P0

IPMB A/B

SPI

x16
10x Diff
SSTL18
PCIe
Gen2 x2

IPMC
VITA46.11

48 SE IO / 24 LVDSFMC Expansion
FMC+ HPC
VITA 57.4

CPutp01

Application Processing Unit (Zynq)• Quad-core ARM Cortex-A53 MPCore• Up to 1.5GHz

USB

10GBASE-KRZynq UltraScale+ MPSoC• XCZU3EG (Gen1)• XCZU5EG (Gen2)FP Debug &JTAG Port

PWR/Board
Mgmt Hot
Swap Ctrl

LEDs(Config/Status)/ResetJTAG

CPutp01
1000BASE-KX

Virtex UltraScale+ FPGA• XCVU9P (default)• XCVU5PFP Reset andStatus LEDsSPI

SOSA RF Payload Slot Profile• SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n

MP

1000BASE-KX
10GBASE-KR

4xGTY

OpticalTx/Rx

100Gbps Optical

4xGTY

OpticalTx/Rx

100Gbps Optical

Ordering information
For available product part numbers, contact your local product expert.

Board Support Package (BSP)• Open Source access to most of the firmware- 40G Ethernet with optional RoCEv2 (RDMAover Converged Ethernet) available- Xilinx PCIe DMA engine included- 100G Ethernet over optical interface
available (optional 100Gbps Aurora)- Optional ANSI/VITA 49.2 VITA Radio
Transport (VRT) subset protocol supportfor Software Defined Radios• Open source Windows and Linux API• For VxWorks, please contact Abaco
Systems

Applications• Electronic Warfare (EW)
• Signal Intelligence (SIGINT)• Radar/Sonar• Software Defined Radio (SDR)• Multi-Function Communication Systems• Telecommunications/Broadband Wireless• Networking and Base Stations Equipment• Ultra-Wide-Band Satellite Digital Receiver• Optical and Photonics Instrumentation• RF and EMI Test Instrumentation• Biomedical Imaging – Medical Equipment

Xilinx and Zynq are registered trademarks, and UltraScale+ is a trademark of Xilinx, Inc. FireFly is a trademark ofSamtec, Inc. PCIe is a trademark of PCI-SIG. ARM is a registered trademark of ARM Limited.

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