TECHNICAL DATA SHEET

Onyx 52760
4-channel 200 MHz, 16-bit A/D
3U VPX board with Virtex-7 FPGA

Complete radarand software radiointerface solution▪ Radar and software radio receiver▪ Remote monitoring▪ Communications receiver▪ Sensor interfaces▪ Analog signal interface for data recording▪ Wideband data acquisition

The 52760 is a multichannel, high-speed data converter suitablefor connection to HF or IF ports of a communications or radarsystem. Its built-in data capture features offer an ideal turnkey solution
as well as a platform for developing and deploying custom FPGAprocessing IP.
The 52760 includes four A/Ds and four banks of memory. It features built-in support for
PCI Express over the 3U VPX backplane.

FEATURES▪ Supports Xilinx® Virtex®-7 VXT FPGA
▪ GateXpress® supports dynamic FPGA reconfiguration across PCIe
▪ Four 200 MHz 16-bit A/Ds
▪ 4 GB of DDR3 SDRAM▪ Sample clock synchronization to an external system reference▪ LVPECL clock/sync bus for multiboard synchronization▪ Optional user-configurable gigabit serial interface▪ Optional LVDS connections to the Xilinx® Virtex®-7 FPGA for custom I/O▪ 3U VPX form factor provides a compact, rugged platform▪ Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65(OpenVPX™ System Specification)▪ Ruggedized and conduction-cooled versions available

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TECHNICAL DATA SHEETOnyx 52760

52760 BLOCK DIAGRAMS

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TECHNICAL DATA SHEETOnyx 52760

THE ONYX ARCHITECTURE

A/D ACQUISITION IP MODULES

Based on the proven design of the Mercury Cobalt family, Onyx
raises the processing performance with the new flagship familyof Virtex-7 FPGAs from Xilinx. As the central feature of theboard architecture, the FPGA has access to all data and control
paths, enabling factory-installed functions including data
multiplexing, channel selection, data packing, gating, triggeringand memory control. The Onyx Architecture organizes the FPGA
as a container for data processing applications where eachfunction exists as an intellectual property (IP) module.

The 52760 features four A/D Acquisition IP Modules for easily
capturing and moving data. Each IP module can receive datafrom any of the four A/Ds or a test signal generator.

Each member of the Onyx family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The 52760 factory-installed functions include four
A/D acquisition IP modules for simplifying data capture anddata transfer.
IP modules for DDR3 SDRAM memories, a controller for all data
clocking and synchronization functions, a test signal generator,
and a PCIe interface complete the factory-installed functions
and enable the 52760 to operate as a complete turnkey solution
without the need to develop any FPGA IP.

EXTENDABLE IP DESIGNFor applications that require specialized functions, users can install
their own custom IP for data processing. The GateFlow FPGA
Design Kits include all of the factory-installed modules as document
source code. Developers can integrate their own IP with thefactory-installed functions or use the GateFlow kit to completely
replace the IP with their own.

XILINX VIRTEX-7 FPGAThe Xilinx Virtex-7 FPGA site can be populated with one of two FPGAs
to match the specific requirements of the processing task. SupportedFPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1
slices and is ideal for modulation/demodulation, encoding/decoding,encryption/decryption, and channelization of the signals between
transmission and reception. For applications not requiring large DSP
resources or logic, the lower-cost VX330T can be installed.

A/D CONVERTER STAGE
The board's analog interface accepts four full-scale analog HFor IF inputs on front panel SSMC connectors at +8 dBm into 50
ohms with transformer coupling into four Texas Instruments
ADS5485 200 MHz, 16-bit A/D converters.

Each IP module has an associated memory bank for buffering data in
FIFO mode or for storing data in transient capture mode. All memorybanks are supported with DMA engines for easily moving A/D data
through the PCIe interface.
These powerful linked-list DMA engines are capable of a unique
Acquisition Gate Driven mode. In this mode, the length of atransfer performed by a link definition need not be known prior
to data acquisition; rather, it is governed by the length of theacquisition gate. This is extremely useful in applications where
an external gate drives acquisition and the exact length of thatgate is not known or is likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing A/D channel ID, a sample-accurate
time stamp and data length information. These actions simplify
the host processor’s job of identifying and executing on thedata.

CLOCKING AND SYNCHRONIZATION
An internal timing bus provides all timing and synchronization
required by the A/D converters. It includes a clock, two sync
and two gate or trigger signals. An on-board clock generator
receives an external sample clock from the front panel SSMC
connector. This clock can be used directly by the A/D or divided
by a built-in clock synthesizer circuit. In an alternate mode, thesample clock can be sourced from an on-board programmable
voltage-controlled crystal oscillator. In this mode, the front
panel SSMC connector can be used to provide a 10 MHz
reference clock for synchronizing the internal oscillator.
A front panel 26-pin LVPECL Clock/Sync connector allows
multiple modules to be synchronized. In the slave mode, it
accepts LVPECL inputs that drive the clock, sync and gate
signals. In the master mode, the LVPECL bus can drive thetiming signals for synchronizing multiple boards.
Multiple 52760’s can be driven from the LVPECL bus master,supporting synchronous sampling and sync functions across allconnected boards.

The digital outputs are delivered into the Xilinx® Virtex®-7 FPGAfor signal processing, data capture or for routing to other board
resources.

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TECHNICAL DATA SHEETOnyx 52760

MEMORY RESOURCES
The 52760 architecture supports four independent DDR3 SDRAM
memory banks. Each bank is 1 GB deep and is an integral part ofthe module’s DMA capabilities, providing FIFO memory space forcreating DMA packets. Built-in memory functions include
multichannel A/D data capture, tagging and streaming.
In addition to the factory-installed functions, custom userinstalled IP within the FPGA can take advantage of thememories for many other purposes.

PCI EXPRESS INTERFACEThe Model 52760 includes an industry-standard interface fullycompliant with PCI Express Gen. 1 and 2 bus specifications.
Supporting PCIe links up to x4, the interface includes multiple
DMA controllers for efficient transfers to and from the board.

GATEXPRESS FOR FPGA CONFIGURATIONThe Onyx architecture includes GateXpress®, a sophisticated
FPGA-PCIe configuration manager for loading and reloading theFPGA. At power up, GateXpress immediately presents a PCIetarget for the host computer to discover, effectively giving theFPGA time to load from FLASH. This is especially important forlarger FPGAs where the loading times can exceed the PCIe
discovery window, typically 100 msec on most PCs.

Once booted, GateXpress allows the user three options for
dynamically reconfiguring the FPGA with a new IP image:▪ The first is the option to load an alternate image fromFLASH through software control. The user selects thedesired image and issues a reload command.
▪ The second option is for applications where the FPGA
image must be loaded directly through the PCIe interface.
This is important in security situations where there can be
no latent user image left in nonvolatile memory whenpower is removed. In applications where the FPGA IP may
need to change many times during the course of amission, images can be stored on the host computer andloaded through PCIe as needed.
▪ The third option, typically used during development,
allows the user to directly load the FPGA through JTAGusing Xilinx iMPACT.
In all three FPGA loading scenarios, GateXpress handles thehardware negotiation simplifying and streamlining the loadingtask. In addition, GateXpress preserves the PCIe configuration
space allowing dynamic FPGA reconfiguration without a hostcomputer reset to rediscover the board. After the reload, thehost simply continues to see the board with the expected
device ID.

The board’s configuration FLASH can hold four FPGA images.
Images can be factory-installed IP or custom IP created by theuser, and programmed into the FLASH via JTAG using XilinxiMPACT or through the board’s PCIe interface. At power up theuser can choose which image will load based on a hardware
switch setting.

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TECHNICAL DATA SHEETOnyx 52760

READYFLOW
Mercury provides ReadyFlow® BSPs (Board Support Packages) for
all Cobalt, Onyx, and Flexor products. Available for both Linux andWindows, these packages:▪ Provide a path for quick start-up through application
completion▪ Allow programming at high, intermediate and low levels tomeet various needs▪ Are illustrated with numerous examples▪ Include complete documentation and definitions of allfunctions▪ Include library and example source code.
ReadyFlow BSPs contain C-language examples that can be used
to demonstrate the capabilities of Cobalt, Onyx, and Flexor
products. These programming examples will help you get an
immediate start on writing your own application. They provide
sample code that is known to work, giving you a means ofverifying that your board set is operational.

COMMAND LINE INTERFACEThe Command Line Interface provides access to pre-compiled
executable examples that operate the hardware right out of thebox, without the need to write any code. Board-specific hardware

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operating arguments can be entered in the command line tocontrol parameters: number of channels to enable, sample
clock frequency, data transfer size, reference clock frequency,
reference clock source, etc.
The Command Line Interface can be used to call an example
application from within a larger user application to control thehardware, and parameter arguments are passed to theapplication for execution. Functions that control dataacquisition automatically save captured data to a pre-named
host file or are routed to the Signal Analyzer example function
for display.

SIGNAL ANALYZER
When used with the Command Line Interface, the Signal
Analyzer allows users to immediately start acquiring anddisplaying A/D data. A full-featured analysis tool, the Signal
Analyzer displays data in time and frequency domains. Built-in
measurement functions display 2nd and 3rd harmonics, THD,and SINAD. Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals.

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TECHNICAL DATA SHEETOnyx 52760

GATEFLOWThe User Application Container

The GateFlow® FPGA Design Kit (FDK) allows the user to modify,

Shown below is the FPGA block diagram of a typical Cobalt,
Onyx or Flexor module. The User Application Container holds acollection of different installed IP modules connected to thevarious interfaces through the standard ports surrounding thecontainer. The specific IP modules for each product aredescribed in further detail in the datasheet of that product.

replace and extend the standard installed functions in the FPGA
to incorporate special modes of operation, new controlstructures, and specialized signal-processing algorithms.
The Cobalt (Virtex-6), Onyx (Virtex-7), and Flexor (Virtex-7)
architectures configure the FPGA with standard factory-suppliedinterfaces including memory controllers, DMA engines, A/D andD/A interfaces, timing and synchronization structures, triggeringand gating logic, time stamping and header tagging, data
formatting engines, and the PCIe interface. These resources areconnected to the User Application Container using well-defined
ports that present easy-to-use data and control signals,
effectively abstracting the lower-level details of the hardware.

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The GateFlow FDK provides a complete Xilinx's ISE or Vivado
project folder containing all the files necessary for the FPGA
developer to recompile the entire project with or without any
required changes. VHDL source code for each IP module
provides excellent examples of how the IP modules work, how
they might be modified, and how they might be replaced withcustom IP to implement a specific function.

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TECHNICAL DATA SHEET
Onyx 52760

A/D PERFORMANCE

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Spurious Free Dynamic Range

Spurious Pick-up

fin = 70 MHz, fs = 200 MHz, Internal Clockfs = 200 MHz, Internal ClockTwo-Tone SFDR

Two-Tone SFDR

f1 = 30 MHz, f2 = 70 MHz, fs = 200 MHz

f1 = 69 MHz, f2 = 71 MHz, fs = 200 MHz

Adjacent Channel Crosstalk

Input Frequency Response

fin Ch2 = 70 MHz, fs = 200 MHz, Ch 1 shown

fs = 200 MHz, Internal Clock

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TECHNICAL DATA SHEET
Onyx 52760

FRONT PANEL CONNECTIONSSPECIFICATIONSThe XMC front panel includes six SSMC coaxial connectors and a26-pin Sync Bus connector for input/output of clock, trigger
and analog signals. The front panel also includes ten LEDs.

Front Panel Analog Signal Inputs
Input Type: Transformer-coupled, front panel female SSMCconnectors
Transformer Type: Coil Craft WBC4-6TLB▪ Sync Bus Connector: The 26-pin Sync
Bus front panel connector, labeled
SYNC/GATE, provides clock, sync, andgate input/output pins for the Sync Bus.
▪ Link LED: The green LNK LED blinks
when a valid link has been establishedover the PCIe interface.
▪ User LED: The green USR LED is foruser applications.
▪ MAS LED: The yellow
MAS LED illuminates when this model isthe Sync Bus Master.
▪ PPS LED: The green PPS LED
illuminates when a valid PPS signal isdetected. The LED will blink at the rate ofthe PPS signal.
▪ Over Temperature LED: The red TMP
LED illuminates when an overtemperature or over-voltage condition isindicated by any of thetemperature/voltage sensors on the PCB.
▪ Clock Input Connector: One SSMC
coaxial connector, labeled CLK, for inputof an external sample clock.
▪ Trigger Input Connector: The
SSMC coaxial connector labeled TRIG isfor input of an external trigger. The signalmust be a LVTTL signal.
▪ Analog Input Connectors: Four SSMC coaxial
connectors, labeled IN 1, IN 2, IN 3 and IN 4 are for each
ADC input channel.
▪ ADC Overload LED: Four red OV (overload) LEDs foreach A/D input.

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Full Scale Input: +8 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz

A/D Converters
Type: Texas Instruments ADS5485
Sampling Rate: 10 MHz to 200 MHz
Resolution: 16 bits

Sample Clock Sources
On-board clock synthesizer

Clock Synthesizer
Clock Source: Selectable from on-board programmable VCXO
(10 to 810 MHz), front panel external clock or LVPECL timingbusSynchronization: VCXO can be locked to an external 4 to 180
MHz PLL system reference, typically 10 MHz
Clock Dividers: External clock or VCXO can be divided by 1, 2,4, 8, or 16 for the A/D clock

External Clock
Type: Front panel female SSMC connector, sine wave, 0 to
+10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz
sample clock or PLL system reference

Timing Bus
26-pin connector LVPECL bus includes, clock/sync/gate/PPS
inputs and outputs; TTL signal for gate/trigger and sync/PPS
inputsExternal Trigger Input
Type: Front panel female SSMC connector, LVTTL
Function: Programmable functions include: trigger, gate,sync and PPS

Field Programmable Gate Array▪ Standard: Xilinx Virtex-7 XC7VX330T-2▪ Optional: Xilinx Virtex-7 XC7VX690T-2

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TECHNICAL DATA SHEETOnyx 52760

Custom I/O▪ Option -104: Provides 20 pairs of LVDS connections
between the FPGA and the VPX P2 connector for custom
I/O

ORDERING INFORMATION
Model

Description

52760

4-Channel 200 MHz A/D with Virtex-7 FPGA - 3U VPXOptions

Description-073

XC7VX330T-2 FPGA

Type: DDR3 SDRAM-076

XC7VX690T-2 FPGA

Size: Four banks, 1 GB each-104

LVDS FPGA I/O to VPX P2

Speed: 800 MHz (1600 MHz DDR)

-105

Gigabit serial FPGA I/O to VPX P1-702

Air-cooled, Level 2-763

Conduction-cooled, Level 3▪ Option -105: Provides one 8X or two 4X gigabit links
between the FPGA and the VPX P1 connector to support
serial protocols

MemoryPCI-Express Interface
PCI Express Bus: Gen. 1 or Gen. 2: x4

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing
Option -702: L2 (air-cooled)

Contact Mercury for compatible option combinations.

ACCESSORY PRODUCTS
Model

Description

2171

Cable Kit: SSMC to SMA▪ Operating Temp: -20° to 65° C▪ Storage Temp: -40° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing
Option -763: L3 (conduction-cooled)▪ Operating Temp: -40° to 70° C▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: Form Factor: 3U VPX▪ Depth: 170.6 mm (6.717 in.)▪ Height: 100 mm (3.937 in.)
Weight▪ VPX Carrier: 110 grams (3.9 oz.);▪ XMC Module: approximately 400 grams (14 oz.) with 2slot heatsink

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TECHNICAL DATA SHEETOnyx 52760

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR ONYX PRODUCTS

Mercury offers development systems for Onyx products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system thatensures optimum performance of Onyx boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORS
Onyx products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Onyx Model 71760 XMC (4Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA) has thefollowing variants:
Model
52760

3U VPX board (single XMC)

57760

6U VPX board (single XMC)

58760

6U VPX board (dual XMC)

71760

XMC module

78760

PCIe board (single XMC)

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Avenue Eugène-Lance, 38
PO Box 584
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For technical details, contact:mrcy.com/go/CF52760

Visit: mrcy.com/go/MP52760+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation ThatMatters, Cobalt, Flexor, Onyx, GateXpress, GateFlow, and ReadyFlow. Other marks used herein may be trademarks or registered trademarks of theirrespective holders. Mercury believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The
information contained herein is subject to change without notice.
© 2022 Mercury Systems, Inc. 1-0-112322-DS-O52760

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