CCVPX-16AISS8AO4C
16-Bit, 12-Channel, 2-MSPS Conduction-Cooled
3U VPX Analog Input/Output Board
With Eight Simultaneously Sampled Analog Inputs, Four Analog Outputs,and Input Sampling Rates to 2.0 MSPS per channel

 Analog Inputs:
 8 Differential analog inputs with dedicated 16-Bit ADC per channel True simultaneous sampling of all inputs to 2.0 MSPS per channel
 SAR architecture; no minimum sample rate Analog Outputs:
 4 Single-ended analog outputs with dedicated 16-Bit DAC per channel
 Simultaneous output clocking rates to 1.0 MSPS per channel
 Selectable direct-write or FIFO-buffered access Buffer configurable as open for data streaming, or circular for periodic functions
 Common Analog I/O Features:
 Selectable input/output ranges: ±10V, ±5V, ±2.5V
 Independent 256-Ksample input and output FIFO data buffers
 Hardware clock and sync I/O for multiboard operation
 Internal power conversion
 DMA engine minimizes bus congestion
 Timing controlled by internal rate generator, by software clocking, or externally Three independent 24-Bit frequency dividers
 On-demand autocalibration
 Front-panel system I/O access 16-Bit bidirectional TTL digital I/O port
 Conforms to PCI Express Specification revision 1.0a; x1 link operating at 2.5Gbps
 3U VPX form factor

High Performance Data Acquisition
Arbitrary Waveform Generation

Event Capture
Ultrasound

Robotics
Positioning Systems--- PRELIMINARY --REV: 022317

8302A Whitesburg Drive · Huntsville, AL 35802
Phone: (256) 880-8787 or (800) 653-9970 FAX: (256) 880-8788 Email: Solutions@GeneralStandards.com

CCVPX-16AISS8AO4C Preliminary

The 16-Bit CCVPX-16AISS8AO4C analog I/O module samples and digitizes eight input channels
simultaneously at rates up to 2.0 Megasamples per second for each channel. The resulting 16-bit
sampled data is available to the PCI Express host through a 256K-Sample FIFO buffer. Sampling
can be controlled in groups of 1 through 8 channels, and the sample clock can be generated froman internal rate generator, or through software, or by external hardware. Both burst andcontinuous sampling modes are supported. Input ranges are software-selectable as ±10V, ±5V, or±2.5V. The inputs can be divided into two channel groups with independent range assignments.
Four analog output channels provide software-selected output ranges of ±10V, ±5V or ±2.5V
independently of the input range selection, and are accessed either directly through dedicatedcontrol registers, or output data can be routed through a 256K-Sample FIFO buffer for waveformgeneration. Output clocking rates are supported up to 1.0 Megasamples per second. A 16-Bit
bidirectional digital port can be configured as two independent byte-wide ports.
On-demand autocalibration determines and applies offset and gain correction values for all input
and output channels. A selftest input switching network routes output channels or calibrationreference signals to the analog inputs, and permits board integrity to be verified by the host..
SystemI/O ConnAnalog Outputs (4)±10V, 5V, 2.5V
Chan-00 of 8 Identical Input Channels
Analog Inputs

Selftest
Switching±10V, 5V, 2.5V

Inputs 01-07

Diff
Amp16-Bit
ADC

Channels 01 to 07

Voltage
ReferenceInput
DataInput Control

External Clock and Sync I/O16-Bit
DAC (4)Sample-Rate
Generators (3)+5VDC+12VDC

PowerConversion

LocalController

Regulated
Power Voltages

PCI ExpressInterface
Adapter

Local Bus

Host Conn(PCI Express)

Figure 1. CCVPX-16AISS8AO4C; Functional Organization

This product conforms to the VPX baseline standard ANSI/VITA 46.0-2007 (R2013). Systemconnections are made at the front panel through a high-density front-panel I/O connector.
Power requirements consist of +12VDC and +5VDC in compliance with the VPX specification,and operation over the specified temperature range is achieved with standard conduction
cooling.
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CCVPX-16AISS8AO4 Preliminary

At +25 OC, with specified operating conditions.

Analog Input Characteristics:
Configuration:

Eight differential analog input channels; Dedicated 16-Bit ADC per channel.
Optional 4-Channel version available.

Voltage Ranges:

Independently assignable between two groups of input channels as:±10V, ±5V or ±2.5V full scale.

Input Impedance:

2 Megohms Line-Line in parallel with 40pF.

Bias Current:

100 nanoamps typical all ranges

Crosstalk Rejection:

84dB, DC-10kHz. 70dB at 100kHz.

Signal/Noise Ratio (SNR):

82dB typical; 10Hz to 500kHz

Common Mode Rejection:

65dB DC-10kHz; 53dB at 100kHz. Typical with CMV = ±10V, Vin = Zero.

Overvoltage Protection:±25V with power applied, ±15 Volts with power removed.

Analog Input Transfer Characteristics:
Resolution:

16 Bits (0.0015 percent of FSR)

Sample Rate:

Zero to 2.0 MSPS per channel

Sampling Mode::

Simultaneous; all active input channels

DC Accuracy:(Maximum composite
error after autocalibration)

Range±10V±5V±2.5V

Small Signal Bandwidth:

Zero to 5MHz, -3dB, all ranges

Settling Time:

500ns to 0.1%; halfscale step; typical; all ranges.

Power Bandwidth:

3MHz, 10Vp-p, -3dB

Integral Nonlinearity:±0.007 percent FSR

Differential Nonlinearity:±0.003 percent FSR.

Midscale Accuracy
± 2mV
± 1mV
± 0.8mV

Fullscale Accuracy
± 5mV
± 3mV
± 2mV

(FSR = fullscale range; e.g.: 20Von ±10Vrange).

Analog Input Operating Modes and Controls
Input Data Buffer:

256K-sample FIFO

Sample Clock Sources:

Internal rate generator; External Hardware Clock I/O, Software clock.

Sampling Modes:

Continuous sampling, and triggered burst.

Internal Rate Generators:

Two independent rate generators, one for ADC clocking; one for burst
triggering. Both programmable from 4-2,000,000 sample clocks per second,using 24-Bit dividers from the 64MHz master clock frequency.

External Clock I/O:

TTL, bidirectional. Zero to 2,000,000 sample clocks per second.

Principal Status Register:

Consolidates critical status flags at a single Longword location.

Input Data Format:16 Bits. Selectable as offset binary or two's complement. First-channel andend of-burst tagged.

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CCVPX-16AISS8AO4 PreliminaryAnalog Output Characteristics:
Configuration:

Four single-ended output channels. (Two external and two internal output
channels if the SMA inputs I/O ordering option is specified).

Voltage Ranges:±10, ±5 or ±2.5 Volts; Independent of analog input ranges.

Output Resistance:

1.0 Ohm maximum at I/O connector pins.

Output protection:

Withstands sustained short-circuiting to ground

Load Current:

Zero to ±3ma per channel

Load Capacitance:

Stable with any load capacitance

Noise:

2.0mV-RMS, 10Hz-100KHz typical

Glitch Impulse:

7 nV-s, typical on ±5V range

Analog Output Transfer Characteristics:
Resolution:

16 Bits (0.0015 percent of FSR)

Output Access:Direct register access or 256K-Sample FIFO buffer.

DC Accuracy:(Max error, no-load)

Range
±10V
±5V
±2.5V

Settling Time:

2us to 0.1 percent, typical with halfscale step, no-load.

Crosstalk Rejection:

70 dB minimum, DC-100 kHz

Integral Nonlinearity:±0.007 percent of FSR, maximumDifferential Nonlinearity:±0.002 percent of FSR, maximum

Output Data Format:

16 Bits. Same format as selected for analog inputs.

Midscale Accuracy
±4mV
±2mV
±1.5mV±Fullscale Accuracy
±8mV
±6mV
±4mV

Analog Output Operating Modes and Controls
Output Data Buffer:

256K-sample FIFO

Sample Clock Sources:

Internal rate generator; External Clock I/O, Software clock.

Burst Triggering Sources:

TTL external Trigger I/O (shared with analog inputs), Software trigger.

Clocking Modes:

Continuous or periodic clocking, and triggered burst.

Internal Rate Generator:

Programmable from 4-1,000,000 output clocks per second.
Divides Master Clock frequency to clocking rate using a 24-bit divider.

External Clock I/O:

TTL, bidirectional. Zero to 1,000,000 sample clocks per second.

Output Data Format:

16-Bits. Selectable as offset binary or two's complement.

Digital I/O Port:
Dual Independent 8-Bit bidirectional I/O ports. Standard TTL levels. Direct register Access.
±8 mA loading when configured as outputs. 0.15 mA source when configured as inputs.

Host Bus Compatibility:
Conforms to VPX VITA 46.0.
Also conforms to PCI Express Specification revision 1.0a; x1 Link operating at 2.5Gbps.
DMA transfers as bus master with two DMA channels.

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CCVPX-16AISS8AO4 Preliminary

Power Requirements+5VDC ±0.2 VDC, 0.8Amps typical, 1.0 Amps maximum.
+12VDC ±0.4 VDC, 0.3 Amps typical, 0.4 Amps maximum
Total power consumption: 7.6 Watts typical, 10 Watts maximum. (Outputs fully loaded).
Mechanical Characteristics
Height:18.8mm (0.74 in)
Depth:
170.6 mm (6.717 in)
Width:
100.0 mm (3.937 in)Shield:Side-1 is protected by an EMI shield.
Thermal transfer rails are provided for conduction cooling.

Environmental Specifications
Ambient Temperature Range:

Operating: 0 to +80 Degrees Celsius inlet airStorage: -40 to +85 Degrees Celsius

Relative Humidity:

Operating and Storage: 0 to 95%, non-condensing

Altitude:Operation to 10,000 ft.

Cooling:Standard conduction cooling thermal interfaces.

Specify the basic product model number followed by an option suffix "-A-B-C-D", as indicated below.
For example, model number CCVPX-16AISS8AO4C-8-4 -64.000M-0 describes a 3U VPX module witheight input channels, four output channels, a standard 64MHz master clock frequency, and no customfeatures.

Optional Parameter
Number of Input Channels

Number of Output Channels

Master Clock Frequency

Value

Specify Option As:

8 Input Channels

A=84 Input Channels

A=44 Output Channels

B=4No Analog Outputs

B=064.000MHzC = 64.000M

Custom frequency; 64-66 MHz

C = (Custom frequency)M

Custom Feature---D** Blank or zero (0) if no custom feature applies.

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CCVPX-16AISS8AO4 Preliminary

Table 1. System I/O Connector Pin FunctionsPinSignal

Pin43

OUTPUT RTN------Signal

42

OUTPUT RTN

85

ANA OUT 0041

OUTPUT RTN

84

ANA OUT 01

40

OUTPUT RTN

83

ANA OUT 02

39

OUTPUT RTN

82

ANA OUT 03

38

INPUT RTN

81

INPUT RTN

37

INP00_LO180

INP00_HI36

INPUT RTN

79

INPUT RTN

35

INP01_LO

178

INP01_HI34

INPUT RTN

77

INPUT RTN

33

INP02_LO

276

INP02_HI32

INPUT RTN

75

INPUT RTN

31

INP03_LO

274

INP03_HI30

INPUT RTN

73

INPUT RTN

29

INP04_LO172

INP04_HI28

INPUT RTN

71

INPUT RTN

27

INP05_LO170

INP05_HI26

INPUT RTN

69

INPUT RTN

25

INP06_LO268

INP06_HI224

INPUT RTN

67

INPUT RTN

23INP07_LO

266

INP07_HI22

INPUT RTN

65INPUT RTNPIN 43PWBPIN 85

1221Panel Pin-view
1Figure 2. System I/O Connector

2System I/O Mating Connector:
Omnetics # MNPO-85-DD-N-EJS-C,
dual-row, straight tail.
(Assembled cables available)

VTEST RTN

64

VTEST

20

INPUT RTN

63

INPUT RTN

19

DIGITAL RTN

62

DIO 0018

DIGITAL RTN

61

DIO 01

17

DIGITAL RTN

60

DIO 02

16

DIGITAL RTN

59

DIO 0315DIGITAL RTN

58DIO 04

14

DIGITAL RTN

57DIO 05

13DIGITAL RTN

56

DIO 06

12

DIGITAL RTN

55

DIO 07

11DIGITAL RTN

54

DIO 08

10DIGITAL RTN

53

DIO 099

DIGITAL RTN

52

DIO 108

DIGITAL RTN

51

DIO 117

DIGITAL RTN

50DIO 126

DIGITAL RTN

49

DIO 135

DIGITAL RTN

48

DIO 144

DIGITAL RTN

47DIO 153

DIGITAL RTN

46

OUTPUT CLK I/O

2

DIGITAL RTN

45

INPUT CLK I/O

1

DIGITAL RTN

44

TRIGGER I/O

2PIN 44

1211PIN 1

Input Group-A.
Input Group-B.
(4 input-channel modules contain input Channels 00-03).

General Standards Corporation assumes no responsibility for the use of any circuits in this product. No circuit patent licenses are implied.
Information included herein supersedes previously published specifications on this product and is subject to change without notice.

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