TECHNICAL DATA SHEET

Onyx 52730
1 GHz A/D and 1 GHz D/A
3U VPX board with Virtex-7 FPGA

Complete radar andsoftware radio
interface solution▪ Radar and communication receiver andtransmitter▪ Wideband data acquisition▪ Electronic Warfare transponder▪ Sensor interfaces▪ Remote monitoring▪ Waveform signal generator

The 52730 is a high-speed data converter, suitable for connection
to HF or IF ports of a communications or radar system. Its built-in
data capture and playback features offer an ideal turnkey solution.
The 52730 includes 1 GHz A/D and D/A converters and four banks of memory. It features
built-in support for PCI Express over the 3U VPX backplane.

FEATURES▪ Supports Xilinx® Virtex®-7 VXT FPGA
▪ GateXpress® supports dynamic FPGA reconfiguration across PCIe
▪ One 1 GHz 12-bit A/D▪ One 1 GHz 16-bit D/A▪ 4 GB of DDR3 SDRAM▪ Sample clock synchronization to an external system reference▪ Dual-µSync clock/sync bus for multiboard synchronization▪ PCI Express (Gen. 1 and 2) interface up to x4▪ Optional LVDS connections to the Xilinx® Virtex®-7 FPGA for custom I/O▪ 3U VPX form factor provides a compact, rugged platform▪ Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65(OpenVPX™ System Specification▪ Ruggedized and conduction-cooled versions available

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TECHNICAL DATA SHEET
Onyx 52730

52730 BLOCK DIAGRAMS

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Onyx 52730

THE ONYX ARCHITECTURE

A/D ACQUISITION IP MODULES

Based on the proven design of the Mercury Cobalt family, Onyx
raises the processing performance with the new flagship familyof Virtex-7 FPGAs from Xilinx. As the central feature of theboard architecture, the FPGA has access to all data and control
paths, enabling factory-installed functions including data
multiplexing, channel selection, data packing, gating, triggeringand memory control. The Onyx Architecture organizes the FPGA
as a container for data processing applications where eachfunction exists as an intellectual property (IP) module.

The 52730 features an A/D Acquisition IP Module for easy
capture and data moving. The IP module can receive data fromthe A/D, a test signal generator, or from the D/A Waveform
Playback IP Module in loopback mode. The IP module has
associated memory banks for buffering data in FIFO mode or forstoring data in transient capture mode. The memory banks aresupported with a DMA engine for moving A/D data through the
PCIe interface.

Each member of the Onyx family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces. The 52730 factory-installed functions include an A/D
acquisition and a D/A waveform playback IP module forsimplifying data capture and data transfer.
IP modules for DDR3 SDRAM memories, a controller for all data
clocking and synchronization functions, a test signal generator
and a PCIe interface complete the factory-installed functions
and enable the 52730 to operate as a complete turnkey solution,
without the need to develop any FPGA IP.

This powerful linked-list DMA engine is capable of a unique
Acquisition Gate Driven mode. In this mode, the length of atransfer performed by a link definition need not be known prior
to data acquisition; rather, it is governed by the length of theacquisition gate. This is extremely useful in applications where
an external gate drives acquisition and the exact length of thatgate is not known or is likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing a sample-accurate time stamp,
and data length information. These actions simplify the hostprocessor’s job of identifying and executing on the data.

EXTENDABLE IP DESIGN

D/A WAVEFORM PLAYBACK IP MODULE

For applications that require specialized functions, users can install
their own custom IP for data processing. The GateFlow FPGA
Design Kits include all of the factory-installed modules as document
source code. Developers can integrate their own IP with thefactory-installed functions or use the GateFlow kit to completely
replace the IP with their own.

The 52730 factory-installed functions include a sophisticated
D/A Waveform Playback IP module. A linked-list controller
allows users to easily play back waveforms stored in either onboard memory or off- board host memory to the D/A.

XILINX VIRTEX-7 FPGAThe Xilinx Virtex-7 FPGA site can be populated with one of two FPGAs
to match the specific requirements of the processing task. Supported
FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1
slices and is ideal for modulation/demodulation, encoding/decoding,encryption/decryption, and channelization of the signals between
transmission and reception. For applications not requiring large DSP
resources or logic, the lower-cost VX330T can be installed.

A/D CONVERTER STAGE
The front end accepts an analog HF or IF input on a front panel
SSMC connector with transformer coupling into a Texas
Instruments ADS5400 1 GHz, 12-bit A/D converter.

Parameters including length of waveform, delay from playback
trigger, waveform repetition, etc. can be programmed for eachwaveform.
Up to 64 individual link entries can be chained together tocreate complex waveforms with a minimum of programming.

D/A CONVERTER STAGE
The 52730 features a Texas Instruments DAC5681Z 1 GHz, 16-bit
D/A. The converter has an input sample rate of 1 GS/sec,
allowing it to accept full-rate data from the FPGA. Additionally,
the D/A includes a 2x or 4x interpolation filter for applications
that provide 1/2 or 1/4 rate input data. Analog output is througha front panel SSMC connector.

The digital outputs are delivered into the Virtex-6 FPGA for
signal processing, data capture or for routing to other module
resources.

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Onyx 52730

CLOCKING AND SYNCHRONIZATION
Two internal timing buses provide either a single clock or two
different clock rates to the A/D and D/A signal paths.
Each timing bus includes a clock, sync and a gate or trigger
signal. An on-board clock generator receives a sample clock
either from the front panel SSMC connector or from an onboard programmable VCXO (Voltage-Controlled Crystal
Oscillator). In this latter mode, the front panel SSMC connector
can be used to provide a 10 MHz reference clock to phase-lockthe VCXO. Either clock source (front panel or VCXO) can be useddirectly or can be divided independently by 2, 4, 8, or 16 toprovide different lower frequency A/D and D/A clocks.
A pair of front panel µSync connectors allows multiple modules
to be synchronized. They accept CML inputs that drive theboard’s sync and gate/trigger signals.
The Model 5292 and 9192 synchronizers can drive multiple 52630
μSync connectors enabling large, multichannel synchronous
configurations. Also, an LVTTL external gate/trigger input isaccepted on a front panel SSMC connector.

MEMORY RESOURCES
The 52730 architecture supports four independent DDR3 SDRAM
memory banks. Each bank is 1 GB deep and is an integral part ofthe module’s DMA capabilities, providing FIFO memory space forcreating DMA packets. Built-in memory functions include
multichannel A/D data capture, tagging and streaming.
In addition to the factory-installed functions, custom userinstalled IP within the FPGA can take advantage of thememories for many other purposes.

The board’s configuration FLASH can hold four FPGA images.
Images can be factory-installed IP or custom IP created by the user,
and programmed into the FLASH via JTAG using Xilinx iMPACT or
through the board’s PCIe interface. At power up the user canchoose which image will load based on a hardware switch setting.
Once booted, GateXpress allows the user three options for
dynamically reconfiguring the FPGA with a new IP image:▪ The first is the option to load an alternate image from
FLASH through software control. The user selects thedesired image and issues a reload command.
▪ The second option is for applications where the FPGA
image must be loaded directly through the PCIe interface.
This is important in security situations where there can be
no latent user image left in nonvolatile memory whenpower is removed. In applications where the FPGA IP may
need to change many times during the course of a
mission, images can be stored on the host computer andloaded through PCIe as needed.
▪ The third option, typically used during development,
allows the user to directly load the FPGA through JTAG
using Xilinx iMPACT.
In all three FPGA loading scenarios, GateXpress handles the
hardware negotiation simplifying and streamlining the loadingtask. In addition, GateXpress preserves the PCIe configuration
space allowing dynamic FPGA reconfiguration without a hostcomputer reset to rediscover the board. After the reload, thehost simply continues to see the board with the expected
device ID.

PCI EXPRESS INTERFACEThe Model 52730 includes an industry standard interface fullycompliant with PCI Express Gen. 1 and 2 bus specifications.
Supporting PCIe links up to x4, the interface includes multiple
DMA controllers for efficient transfers to and from the board.

GATEXPRESS FOR FPGA CONFIGURATIONThe Onyx architecture includes GateXpress®, a sophisticated
FPGA-PCIe configuration manager for loading and reloading the
FPGA. At power up, GateXpress immediately presents a PCIetarget for the host computer to discover, effectively giving the
FPGA time to load from FLASH. This is especially important forlarger FPGAs where the loading times can exceed the PCIe
discovery window, typically 100 msec on most PCs.

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Onyx 52730

READYFLOW
Mercury provides ReadyFlow® BSPs (Board Support Packages) for
all Cobalt, Onyx, and Flexor products. Available for both Linux andWindows, these packages:▪ Provide a path for quick start-up through application
completion▪ Allow programming at high, intermediate and low levels tomeet various needs▪ Are illustrated with numerous examples▪ Include complete documentation and definitions of all
functions▪ Include library and example source code.
ReadyFlow BSPs contain C-language examples that can be used
to demonstrate the capabilities of Cobalt, Onyx, and Flexor
products. These programming examples will help you get an
immediate start on writing your own application. They provide
sample code that is known to work, giving you a means ofverifying that your board set is operational.

COMMAND LINE INTERFACEThe Command Line Interface provides access to pre-compiled
executable examples that operate the hardware right out of thebox, without the need to write any code. Board-specific hardware

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operating arguments can be entered in the command line tocontrol parameters: number of channels to enable, sample
clock frequency, data transfer size, reference clock frequency,
reference clock source, etc.
The Command Line Interface can be used to call an example
application from within a larger user application to control the
hardware, and parameter arguments are passed to theapplication for execution. Functions that control dataacquisition automatically save captured data to a pre-named
host file or are routed to the Signal Analyzer example function
for display.

SIGNAL ANALYZER
When used with the Command Line Interface, the Signal
Analyzer allows users to immediately start acquiring anddisplaying A/D data. A full-featured analysis tool, the Signal
Analyzer displays data in time and frequency domains. Built-in
measurement functions display 2nd and 3rd harmonics, THD,
and SINAD. Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals.

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Onyx 52730

GATEFLOWThe User Application Container

The GateFlow® FPGA Design Kit (FDK) allows the user to modify,

Shown below is the FPGA block diagram of a typical Cobalt,
Onyx or Flexor module. The User Application Container holds acollection of different installed IP modules connected to thevarious interfaces through the standard ports surrounding thecontainer. The specific IP modules for each product aredescribed in further detail in the datasheet of that product.

replace and extend the standard installed functions in the FPGA
to incorporate special modes of operation, new control
structures, and specialized signal-processing algorithms.
The Cobalt (Virtex-6), Onyx (Virtex-7), and Flexor (Virtex-7)
architectures configure the FPGA with standard factory-suppliedinterfaces including memory controllers, DMA engines, A/D and
D/A interfaces, timing and synchronization structures, triggeringand gating logic, time stamping and header tagging, data
formatting engines, and the PCIe interface. These resources areconnected to the User Application Container using well-defined
ports that present easy-to-use data and control signals,
effectively abstracting the lower-level details of the hardware.

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The GateFlow FDK provides a complete Xilinx's ISE or Vivado
project folder containing all the files necessary for the FPGA
developer to recompile the entire project with or without any
required changes. VHDL source code for each IP module
provides excellent examples of how the IP modules work, how
they might be modified, and how they might be replaced withcustom IP to implement a specific function.

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Onyx 52730

FRONT PANEL CONNECTIONSThe XMC front panel includes two 19-pin µSync Bus connectors
and four SSMC coaxial connectors and input/output of analog
signals. The front panel also includes seven LEDs.
▪ Sync Bus Connector: The two 19-pin
Sync Bus front panel connectors, labeled
SYNC/GATE, provide sync and gate
input signals for the Sync Bus. The top
connector, labeled D/A at the right of thepanel is for DAC timing inputs. The lower
connector, labeled A/D is for ADC timing
inputs.
▪ Link LED: The green LNK LED blinks
when a valid link has been establishedover the PCIe interface.
▪ User LED: The green USR LED is foruser applications.
▪ Over Temperature LED: The red TMP
LED illuminates when an overtemperature or over-voltage condition isindicated by any of thetemperature/voltage sensors on the
Model PCB.
▪ DAC Underrun LED: There is one red
UR (underrun) LED for the D/A output.
This LED illuminates when the DAC5681Z
FIFO is out of data.
▪ Analog Output Connector: The SSMC
coaxial connector, labeled OUT is foranalog signal output from the DAC5681Z.
▪ Clock LED: The green CLK LED
illuminates when a valid sample clock signal is detected. If
the LED is not illuminated, no clock has been detected
and no data from the input stream can be processed.
▪ Clock Input Connector: One SSMC coaxial connector,
labeled CLK, for input of an external sample or reference
clock.
▪ PPS LED: The green LED to the right of the TRIG input
illuminates when a valid PPS signal is detected.
▪ Trigger Input Connector: One SSMC coaxial connector,
labeled TRIG is for input of an external gate or trigger
signal.

mrcy.com▪ ADC Overload LED: The red OV (overload) LED:
indicates an overload detection in the ADS5400 or an
ADC FIFO overrun.
▪ Analog Input Connector: SSMC coaxial connector,
labeled IN is for analog signal input for the ADS5400.

SPECIFICATIONS
Front Panel Analog Signal Inputs
Input Type: Transformer-coupled, front panel female SSMC
connectors

A/D Converter
Type: Texas Instruments ADS5400
Sampling Rate: 100 MHz to 1 GHz
Resolution: 12 bits

D/A Converter
Type: Texas Instruments DAC5681Z
Input Data Rate: 1 GHz max.
Interpolation Filter: bypass, 2x or 4x
Output Sampling Rate: 1 GHz max.
Resolution: 16 bits

Front Panel Analog Signal Outputs
Output Type: Transformer-coupled, front panel female SSMC
connectors

Sample Clock Sources
On-board clock synthesizer generates two clocks: one A/Dclock and one D/A clock

Clock Synthesizer
Clock Source: Selectable from on-board programmable VCXO
or front panel external clock
VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and1213 to 1417 MHz
Synchronization: VCXO can be phase-locked to an external 4
to 200 MHz system reference, typically 10 MHz
Clock Dividers: External clock or VCXO can be divided by 1,
2, 4, 8, or 16, independently for the A/D clock and D/A clock

External Clock
Type: Front panel female SSMC connector, sine wave, 0 to
+10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz
divider input clock, or PLL system reference

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Onyx 52730

Timing Bus
19-pin µSync bus connector includes sync and gate/trigger
inputs, CML

External Trigger Input
Type: Front panel female SSMC connector, LVTTL
Function: Programmable functions include: trigger, gate,
sync and PPS

Option -763: L3 (conduction-cooled)▪ Operating Temp: -40° to 70° C▪ Storage Temp: -50° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions: Form Factor: 3U VPX▪ Depth: 170.6 mm (6.717 in.)Field Programmable Gate Array▪ Standard: Xilinx Virtex-7 XC7VX330T-2▪ Optional: Xilinx Virtex-7 XC7VX690T-2▪ Height: 100 mm (3.937 in.)
Weight▪ VPX Carrier: 110 grams (3.9 oz.);

Custom I/O▪ Option -104: Provides 24 pairs of LVDS connections
between the FPGA and the VPX P2 connector for custom
I/O▪ Option -105: Provides one 8X or two 4X gigabit links
between the FPGA and the VPX P1 connector to support
serial protocols

MemoryType: DDR3 SDRAM▪ XMC Module: approximately 400 grams (14 oz.) with 2slot heatsink

ORDERING INFORMATION
Model

Description

52730

1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX

Options

Description-073

XC7VX330T-2 FPGA

-076

XC7VX690T-2 FPGA-104

LVDS FPGA I/O to VPX P2-105

Gigabit serial FPGA I/O to VPX P1-702

Air-cooled, Level 2-763

Conduction-cooled, Level 3

Size: Four banks, 1 GB each
Speed: 800 MHz (1600 MHz DDR)

PCI-Express Interface
PCI Express Bus: Gen. 1 or Gen. 2: x4

Environmental
Standard: L0 (air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: -20° to 90° C▪ Relative Humidity: 0 to 95%, non-condensing

Contact Mercury for compatible option combinations.

ACCESSORY PRODUCTS

Option -702: L2 (air-cooled)
Model

Description▪ Storage Temp: -40° to 100° C

2171

Cable Kit: SSMC to SMA▪ Relative Humidity: 0 to 95%, non-condensing

5292

High-Speed Synchronizer and Distribution Board

9192

Rackmount High-Speed System Synchronizer▪ Operating Temp: -20° to 65° C

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Onyx 52730

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR ONYX PRODUCTS

Mercury offers development systems for Onyx products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system that
ensures optimum performance of Onyx boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORS
Onyx products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Onyx Model 71730 XMC (8Channel 250 MHz A/D with DDC, Kintex UltraScale FPGA) has thefollowing variants:
Model
52730

3U VPX board (single XMC)

57730

6U VPX board (single XMC)

58730

6U VPX board (dual XMC)

71730

XMC module

78730

PCIe board (single XMC)

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PO Box 584
CH-1212 Grand-Lancy 1
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For technical details, contact:mrcy.com/go/CF52730

Visit: mrcy.com/go/MP52730+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Cobalt, Flexor, Onyx, GateXpress, GateFlow, and ReadyFlow. Other marks used herein may be trademarks or registered trademarks of theirrespective holders. Mercury believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The
information contained herein is subject to change without notice.
© 2022 Mercury Systems, Inc. 1-0-112322-DS-O52730

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