DATASHEETFMC126 high pin count FMC ADC
4-channel 10-bit ADC - 5 Gsps

The FMC126 is a Quad-Channel Multi-Mode ADC FMC daughtercard, fully compliant with VITA 57.1 Standards. The card provides
four 10-bit ADC channels that enable simultaneous samplingof 4, 2, or 1 channel with a maximum sample rate of 1.25 Gsps
(4-channel mode), 2.5 Gsps (2-channel mode), or 5.0 Gsps
(1-channel mode).
The sample clock can be supplied externally through a coax
connection or supplied by an internal clock source (optionallylocked to an external reference). The clock tree enables cascadingof multiple boards for synchronous sampling. Additionally atrigger input for customized sampling control is available.
ANSI/VITA 47

Air-cooled

The FMC126 daughter card is mechanically and electricallycompliant to the FMC standard as established by ANSI/VITA 57.1.
The HPC (high-pin count)-compatible FMC126 has front panel I/O
and can be used in a conduction-cooled environment. The designis based on the E2V Quad ADC EV10AQ190 chip-set having DDR
LVDS outputs. The analog signal inputs are available on the frontpanel on coax connections and have individual calibration circuits
for fine-tuning of gain, offset, and phase. The FMC126 allows
flexible control on clock source, sampling frequency, and calibration
through an I2C communication bus. Furthermore the card isequipped with power supply and temperature monitoring and offers
several power-down modes to switch off unused functions.

Conduction-cooled

FEATURES:

EAC4

EAC6

ECC1

ECC4

Operatingtemperature

0C to +55C-40C to +70C

0C to +55C-40C to +85C

Storagetemperature-40C to +85C

-50C to +100C-40C to +85C-55C to +105C-- 4-Channel 1.25 Gsps A/D conversion
ModeHumidity

95%

95%95%95%

Operatingvibration

5Hz to 100Hz PSD= 0.04g2/Hz

5Hz to 100H PSD =0.04g2/Hz
100 Hz to 1000 Hz
PSD = 0.04 gs^2/
Hz

5 Hz to 100 Hz PSD
increasing at 3 dB/
octave-- 2-Channel 2.50 Gsps A/D conversion
Mode

100 Hz to 1000 Hz
PSD = 0.04 gs^2/
Hz

5 Hz to 100 Hz PSD
increasing at 3 dB/
octave100 Hz to 1000 Hz
PSD = 0.1 g2/Hz

100 Hz to 1000 Hz
PSD = 0.1 g2/Hz• VITA 57.1-2010 compliant

1000 Hz to 2000Hz PSD decreasing
at 6 dB/octave

1000 Hz to 2000
Hz PSD decreasing
at 6 dB/octave

1000 Hz to 2000
Hz PSD decreasing
at 6 dB/octave

1000 Hz to 2000
Hz PSD decreasing
at 6 dB/octave• Conduction Cooled

20g, 11 millisecond,
half-sine or 20g,
11 millisecond,
terminal sawtooth
shock pulses in all
three axes

20g, 11 millisecond,
half-sine or 20g,
11 millisecond,
terminal sawtooth
shock pulses in all
three axes

40g, 11 millisecond
shock half-sine or
40g, 11 millisecond,
terminal sawtooth
shock pulses in all
three axes

40g, 11 millisecond
shock half-sine or
40g, 11 millisecond,
terminal sawtooth
shock pulses in all
three axes

Operating altitude-1500 ft to 60,000ft (with airflow)-1500 ft to 60,000ft (with airflow)-1500 ft to 60,000ft-1500 ft to 60,000ft

Conformal coating

Optional

Optional

Optional

Optional

Operating shock• Quad - Dual - Single 10-Bit Channel
Operation-- 1-Channel 5.00 Gsps A/D conversion
Mode• 1.5V to 3.3V VADJ operation• 1.25Gsps DDR LVDS outputs• Coax front panel inputs on SSMC
connectors• Single ended AC-coupled analog
inputs• Flexible clock tree enables-- internal clock-- external clock-- cascading multiple boards (optional)• HPC (high-pin count) compatible• Mil-I-46058c Conformal Coating
Compliant (optional)

DATASHEETFMC126 high pin count FMC ADC 4-channel 10-bit ADC - 5 Gsps
Block diagramHDMI

MGT [4]

Board
Monitoring

LVTTL [4]Tx[5]LVDS Sync [1]
LVDS Clo ck [1]Trigger/
Sync

LVDS Trigger [1]

CLK

LVDS Overrange [4]SYNC

LVDS Clo ck [1]
LVDS Data [10]A

LVDS Clo ck [1]Quad ADC
EV10AQ190

B

LVDS Data [10]

LVDS Data [10]
LVDS Clo ck [1]DSupport• User Manual• ML605 reference design available• Reference firmware design (VHDL)• Reference ISE project for Virtex-6• Email support (support@abaco.com)

Rx[5]

LVDS Clo ck [1]

CTx
[5]

MICTOR 38-pins
Multi Gigabit Transceiver(optional)

Application• Direct RF Down conversion• Software defined radio (SDR)• RADAR/SONAR• Ultra Wideband Satellite Digital Receiver• Medical equipment• Aerospace and test instrumentation

Rx[5]

MICTOR 38-pins
Multi Gigabit Transceiver(optional)

I2C

Status & Control

Specifications

LVDS Data [10]FMC126 PerformanceFs = 1.25 Gsps
Full scale input
Avg (A,B,C,D)

9,59,057
55

8,553

8,0
7,551

7,049

6,547

6,045

50

1250

100

SNR

85

065

0ENOB

45025

Fin [MHz]50

AS9100 Certified

59
SNR [dBFs] / SFDR [dBc]

10,0

ENOB [bits]Performance• 500mVpp analog input range• Selectable input bandwidth (1.0GHz /3.0GHz)• Individual Gain control (±10%)• Individual Offset control (±40mV)• Individual Phase control (±15ps)• > 60dB channel isolation (crosstalk)Board
Control

Clock/Sync
Tree

Clock/Reference

EEPROM

FMC High-pin Count 400-pins
LVDS

The FMC126 comes with an integrated
Cross Point Switch allowing flexible
mapping of analog inputs to theconverters. Unused converters canbe placed in standby mode or a fullstandby mode can place all channels inpower saving mode. The digital output
interface of the FMC126 compromises
four 10-bit DDR LVDS busses at
1.25Gbps (full speed sampling). The
build in pattern generation feature on
the FMC126 enables training on thecarrier hardware.

SFDR

Ordering information
Talk to us about your algorithmic requirements, Abaco Systems is a full-service firmware and software development house. We are a specialist at high performance FFT and Video Processing. Check with us, we may have IP
Cores that meet requirements for your application, right off the shelf.

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