Development of Wafer-Level Chip Size Package (WL-CSP)
by Toshiaki Asada *, Toshiaki Amano *, Kazuhito Hikasa *, Ken’ichi Sugahara *,Hirofumi Oshima * and Yoshimi Ono *2

Recently electronic equipment have remarkably improved becoming more compact and lighter and having upgraded function, requiring semiconductor packages mounted thereon to be more compact, thin-bodied and lightweight as wellas to enable high-density mounting on substrates. Thus a new semiconductor package calledwafer-level chip size package (hereafter called WL-CSP) technology is drawing attention. In
response to such situations, the authors have developed a new WL-CSP, in which a tape substrate is bonded with wafers in a continuous roll-to-roll manufacturing process enabling cost
reduction and quick delivery, and a resin post structure is adopted for the terminal pads toensure high reliability. This paper reports on the structure, manufacturing process and results ofprototype manufacturing of Furukawa Electric’s original WL-CSP, together with its features andreliability test results.

ABSTRACT1.

INTRODUCTION

semiconductor packages mounted on these electronics
products are keenly required to be more compact, thinbodied and lightweight as well as to enable high-density
mounting on substrates. See Figure 1.
Against this background, a new semiconductor packaging technology called WL-CSP is drawing attention, where

Recently electronics products represented by mobile
phones, mobile computers, personal digital assistance(PDA) and digital still cameras (DSC) have been remarkably improved becoming more compact and lighter andhaving upgraded function. Along with such market trends,

Miniaturization, weight reduction,function upgrading

Trend inmobile phone

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WL-CSP: Real chip-size
package, where chips are
redistributed, electrode formed
and resin sealed in a wafer
process to make individual
pieces.

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Insertion mounting

Figure 1

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* Ecology and Energy Laboratory, R&D Division*2 Production Technology Development Center, Production
Technology and Engineering Division

Furukawa Review, No. 31

2007

13

Development of Wafer-Level Chip Size Package (WL-CSP)

chips are packaged plainly as in the wafer state. In the
WL-CSP process, all the steps including redistribution,
electrode formation, resin sealing and dicing are carriedout in a series of wafer processes, and the size of a semiconductor chip finally cut from the wafer corresponds to
its package size. Thus the WL-CSP process can be said
ideal from the standpoint of miniaturization and weight
reduction, so that the process has already been employedin mobile phones and so forth. We have developed a new
WL-CSP manufacturing technology, in which a solderedtape substrate is bonded to wafers enabling quick delivery and cost reduction. And we have adopted a resin post
structure for the terminal pads on the mounting substrate,and confirmed its high reliability. In this paper, theachievements of this high-bonding reliability WL-CSP
manufactured by the new process will be reported.

2.

DEVELOPMENTAL BACKGROUND OFFURUKAWA’S WL-CSP

Furukawa Electric has developed FBTI (Flexible Bumped
Tape Interposer) 1) as an interposer for semiconductor
devices to cope with weight reduction, height lessening
and speed upgrading, and began marketing the productin 2001. The FBTI is an interposer designed on the presumption of using flip-chip bonding that is more suited forspace saving and high-frequency operation than the conventional wire bonding. As shown in Figures 2 and 3, theinterposer comprises SnAg solder bumps formed on atape substrate to be used for electrical connection with
Flip-chip mounting surface

SnAg
導体
基Conductor
SnAg Solder
Sololderder
older
Bump
Substrate
材
Bump

Pitch:150
Pitch
: 150
µmp
µm

Bump
バンプ部 Bump diameter
Diameter：：75 µmBump Height:10
height:10〜25〜µm

Product appearance

Mounting pad surface

Via部
Via

semiconductor chips. The FBTI which may be called atape substrate with soldered bumps is manufactured by acontinuous method named roll-to-roll method, aiming atcost reduction.
The FBTI has been applied to semiconductor packages
called TQON (Thin Quad Outline Non-Leaded) and SBM(System Block Module) at Toshiba Semiconductor
Company. The structure of these products is such that Au
stud bumps formed on semiconductor chips are flip-chipbonded to SnAg solder bumps on the FBTI, and high reliability has been confirmed in these applications. In viewof these achievements, and based on the idea of combining the two technologies, i.e., the tape substrate manufacturing technology for FBTI aiming at cost reduction andthe flip-chip bonding technology having proven reliability
through applications, we considered it was highly feasible
to realize Furukawa’s original WL-CSP, and embarked on
the development accordingly.

3.

CONCEPT OF FURUKAWA’S WL-CPS

Figures 4 and 5 show the structures of copper post-type
WL-CSP with an established track record in the market
and Furukawa’s WL-CSP, respectively. The copper posttype WL-CSP commercially available has a characteristic
structure in which copper posts 100 µm in height areformed on the wafer redistribution to ensure the reliabilityof mounting with the substrate. The manufacturing process of the copper post-type WL-CSP includes forming ofredistribution to build routing circuitry on the wafer, formation of copper posts and resin sealing, necessitating special manufacturing equipment required by the wafer process. Moreover, the plating process for formation of copper posts constituting the characteristic structure takes
much time, and the delivery time allegedly takes a rather
long time because the manufacturing starts at the time ofwafer reception.

Via SnAg
SnAg
Via
Substrate
基Solder-plated
めっき Via
Solder材

Al padUBM

Pitch:500
Pitch
: 500
µmp
µm
Via diameter
Diameter：:150
150 µm〜µm
Via Height:2.0
height : 2.0〜16.0

Figure 2

Cu re-distribution

PI layerIC

Appearance of FBTI.
Top view

Cu postEpoxy seal

Figure 4

Schematic structure of commercially available WL-CSP.

BGA pad

Al padDCA pad with
SnAg solder bump

Polyimide ﬁlm(Glass epoxy)
SolderplatedPassivation

Au stud bumpIC

Bottom view

Cu pattern

Cross-section

Figure 3

Adhesion

Schematic structure of FBTI.

Figure 5

Schematic structure of Furukawa’s WL-CSP.

Furukawa Review, No. 31

2007

14

Development of Wafer-Level Chip Size Package (WL-CSP)

On the other hand, the manufacturing process of the
Furukawa’s WL-CSP can be broadly divided into three:manufacturing of the tape substrate with resin posts, formation of Au stud bumps on the wafer and bonding of thewafer and the tape substrate. See Figure 6. With regard to
the manufacturing process of the tape substrate with resin
posts, application of the roll-to-roll manufacturing process
for tape substrates with an established track record for
FBTI is expected to result in cost reductions. Moreover,because manufacturing of the tape substrate can be started upon receipt of design information on the wafer, only
the later manufacturing processes of Au stud bump formation and bonding of the wafer and the tape substrate
are to be carried out after receipt of the wafer, thus
enabling quick delivery.
The structure of Furukawa’s WL-CSP is characterized
by its terminal pad --called resin post, containing resin.
WL-CSPs are generally used with their terminal pads
loaded with solder balls, and they are mounted on themounting substrate. The mounting reliability of electronic
components such as semiconductor packages is usually
evaluated by means of thermal shock test. In the case of
WL-CSP which is mounted on substrates using solder
balls, its reliability is influenced by a cracking mechanism
such that a mechanical stress is applied to the solder
balls due to the difference in the coefficients of thermal
expansion between a semiconductor chip made of silicon
and a mounting substrate called FR-4 printed circuitboard, generating cracks either between the WL-CSP and
the solder balls or between the mounting substrate andthe solder balls. These cracks can grow to cause fatigue
failures, and this constitutes a main cause of malfunction.
That is to say, in terms of reliability test conditions, thelower the stress on the solder balls, the longer the lifetime
until failure. Stress analysis based on simulation of theterminal pad structure shows, as illustrated in Figures 7
and 8, that the resin post structure results in a reduced
maximum stress at the solder joints than the copper post
structure, and thus it is expected that the joint lifetime isimproved.
In the Furukawa’s WL-CSP, moreover, the Au studbumps on the wafer (i.e., semiconductor chip) are flipchip bonded to the solder bumps on the tape substrate.
Since this flip-chip bonding of Au to SnAg has a trackrecord in semiconductor packages as mentioned before,
and this structure is advantageous in terms of high-frequency operation, the Furukawa’s WL-CSP is thought tobe promising to cope with a high-speed memory device

named DDR3-DRAM which will come on the market in the
future.

4.

TECHNOLOGICAL PROBLEMS WITHFURUKAWA’S WL-CSP

In the manufacturing process of commercially available
WL-CSP, routing circuitry is formed on the wafer, so thatthe wafer processes including direct application of photodefinable elastomer on the wafer, exposure, development,
metal plating, and etching are carried out directly on thewafer. Wafer processes for semiconductors are typically
employed to deal with the crucial points of manufacturing
such as precise alignment of the exposure mask on to thewafer. On the other hand, manufacturing of Furukawa’s
WL-CSP comprises, differing completely from that of commercially available WL-CSP, the process of flip-chip bonding the Au stud bumps formed on the wafer to the solder
bumps formed on the tape substrate, and this presented
two major technological problems. One is the high levelof dimensional accuracy required for the tape substrate,
and the other is high-precision bonding of the tape substrate and the wafer.
The dimensional accuracy required for the tape substrate depends on the design parameters such as I/O pad
pitch of the semiconductor chip, and can be derived asshown in Figure 9, which was calculated on the following
assumptions; formation accuracy of Au stud bumps:±3.5 µm; mounting accuracy between tape substrate andSilicon wafer
Copper
Solder layer
Glass-epoxy
substrate

Figure 7

Resin layer

Condition
Copper post height: 100 µm
Joint height: 90 µm-40℃⇔+125℃ thermal shock test
Maximum stress: 914 MPa

Calculated stress distribution of commercially available WL-CSP.
Condition
Protrusion height: 50 µm
Joint height: 50 µm-40℃⇔+125℃ thermal shock test
Maximum stress: 284 MPa

Inversion

Au bumps formed on wafer

Roll-to-roll process, where
tape substrate with SnAg
solder bumps are formed

Figure 6

Wafer bonding by
Au/SnAg ﬂip-chipbonding

Back-grinding/dicing

Pick & place into tray

Concept of Furukawa’s WL-CSP manufacturing process.

Figure 8

Calculated stress distribution of Furukawa’s WL-CSP.

Furukawa Review, No. 31

2007

15

Development of Wafer-Level Chip Size Package (WL-CSP)

wafer: ±5 µm; tip diameter of Au stud bump: 15 µmφ;and minimum gap: 25 µm. It can be seen that, assuming
an I/O pad pitch of 80 µm for a semiconductor chip using
8-in wafer, the position accuracy of the solder bumps on
the tape substrate is required to be not greater than about
19 µm over 100 mm (i.e., the center to periphery distanceof 8-in wafer). In the future, if the I/O pad pitch of semiconductor chips becomes narrower, or larger wafers (say12-in) are used, it would be necessary to take appropriate
measures to cope with such changes, including: 1) toreduce the tip diameter of Au stud bump, 2) to adopt narrower minimum gaps, and 3) to improve the accuracy oftape substrate. In manufacturing the tape substrate for
the Furukawa’s WL-CSP, material handling of substrateand suppression of its deformation constitute important
technical points because the continuous manufacturing
scheme of roll-to-roll method is employed together withthe use of tape substrates susceptible to deformation. By
combining appropriate measures such as selection of fixing carrier material for the substrate, ingenious fixation
method and circuit formation method, we have succeeded in achieving a position accuracy of ±5 µm. See Figure
10. To improve the position accuracy further, it would benecessary to control the tape manufacturing environment
including temperature and humidity.
Bonding process of the tape substrate and wafer afteralignment, constituting the second problem, is also specific to the Furukawa’s WL-CSP. Mounting accuracy at thisprocess obviously influences the position accuracy of thesubstrate, so that bonding equipment is required to be as
good as possible in mounting accuracy. We investigated

Position accuracy required fortape substrate（µｍ）

30
25

the market to acquire some equipment with a mounting
accuracy specification of ±5 µm, but due to its uniqueprocess behaviors we were unable to find out any.
Accordingly, we at the Production Technology Development
Center developed an alignment press machine in-house,
and the machine is currently used to manufacture prototype products for performance evaluation. See Figure 11.
At present, when a tape substrate and wafer are bonded
together, the position accuracy of Au stud bumps in relation to solder bumps has been confirmed to be satisfactory. See Figure 12.

5.

RELIABILITY EVALUATION

Reliability evaluation procedures can be divided into reliability evaluation of the WL-CSP itself (hereafter called primary mounting reliability evaluation) and that of the substrate-mounted WL-CSP using solder balls (hereafter
Setting of work → Up-down alignment through image processing→

Temporary press → Transfer→

Vacuum press

About
0.1 atm

3 ton max

Assumptions (position accuracy)
Accuracy of Au stud bump: ±3.5 µm

Tip diameter of Au stud bump: φ15 µm

Bonding accuracy: ±5.0 µm

Minimum gap: 25 µm

20
15
10
5
0

Figure 11 Appearance of alignment press machine.
40

50

60

70

80

90

100

Semiconductor I/O pad pitch（µm）

Figure 9

Position accuracy required for the tape substrate.

Au stud diameter: 60 µm
SnAg bump diameter: 150 µm

Tape substrate accuracy
for 8-in wafer

仕上がり
仕上がり
Finish

工程５

Process5
工程５

工程４

Process4
工程４

工程３

Process工程３
3

工程２

Process 工程２
2

工程１

Process
工程１
1

±５μｍ以
±5
µm 内

0.02000.02000.02000.01500.01500.01500.01000.01000.01000.00500.00500.00500.00000.00000.0000-0.0050-0.0050-0.0050-0.0100-0.0100-0.0100-0.0150-0.0150-0.0150-0.0200-0.0200-0.0200（ｍｍ）

Tolerance from sheet center
シート中心からの公差（mm）
シート中心からの公差（ｍｍ）

100 mmテープ基板のはんだバンプ位置精度
テープ基板のはんだバンプ位置精度

プロセス

Process
プロセス

Figure 10 Position accuracy of solder bumps on the tape substrate.

Figure 12 Confirmation of position accuracy of WL-CSP using
soft X-ray image.

Furukawa Review, No. 31

2007

16

Development of Wafer-Level Chip Size Package (WL-CSP)

called secondary mounting reliability evaluation).
The sample chip used for reliability evaluation is anevaluation TEG chip 6.3-mm square having pads of 48
pins around the chip periphery, as shown in Figure 13.
5.1 Reliability of Primary Mounting
The tape substrate was designed in such a way that,when a WL-CSP consisting of a TEG chip and tape substrate is mounted on a substrate for secondary mounting
reliability evaluation, a daisy chain is formed. Bonding
conditions of the tape substrate to the wafer was optimized in terms of deformation of Au stud bumps, flow of
SnAg solder around Au stud bumps, and thickness of theinsulation layer.
With respect to the contents of evaluation, after eachtest item shown in Table 1 was performed, the terminal
pads were confirmed for presence or absence of conduction by the four-terminal method, along with abnormalities
confirmation by observation of the appearance and thecross-section. In the cross-section observation especially,close attention was paid to crack generation at the Au/
SnAg bonding portions as well as to layer peeling at thesemiconductor chip/adhesive layer and at the tape substrate/adhesive layer.
The results of reliability evaluation for the current prototyping show that all samples passed the tests satisfactorily as shown in Table 1, demonstrating excellent reliability〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜of this semiconductor package. Thus reliability of Au/
SnAg flip-chip bonding was confirmed.
5.2 Reliability of Secondary Mounting
The most commonly used printed circuit board of FR-4
was adopted as a substrate for evaluating the mounting
reliability. The mounting pad pitch was 0.5 mm, andSnAgCu solder balls 0.3 mm in diameter were used. Twotypes of samples were evaluated paying attention to thechip thickness and solder ball layout, and the results areshown in Figure 14. One was in peripheral pad layout
having 48 mounting solder balls on the periphery ---theminimum number necessary for creating a daisy chain,
and its chip thickness was 530 µm, while the other was inan area array pad layout having solder balls at a 0.5-mm
pitch, and its chip thickness was 200 µm.
Figure 15 is the Weibull distribution of the failure rates
obtained by the reliability evaluation, where the conduction of the daisy chain created by the mounting substrateand WL-CSP was monitored during thermal shock test(-40℃ to 125℃, held 7 min at each temperature). The
blue line shows the results for peripheral pad layout using
solder balls with a chip thickness of 530 µm, whereby it isdemonstrated that the initial development target of 400
cycles at a failure rate of 1% has been achieved. The redline in turn shows the results for area array pad layout
using solder balls with a chip thickness of 200 µm, corresponding to a total package thickness of 280 µm excluding solder balls. It can be seen that better results are
obtained here, rendering not only small area packages
but also thin packages sufficiently promising. With commercially available WL-CSPs, it is allegedly difficult to

Reliability evaluation of WL-CSP itself〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜〜

Reliability evaluation of substrate-mounted WL-CSP

Perspective view of the chip from the top
Blue: Wiring pattern on tape substrate
Black: Mounting pad
Red: Wiring pattern on chip
Green: Flip-chip bonding portion

Conditions and results of PKG reliability test.

Test

Condition

Failure rate

Thermal shock-65 ⇔ 150℃ 1,000 cycles

0/22High temp. storage

150℃ 1,000 hrs

0/10

Autoclave

121℃ 85%RH 500 hrs

0/10Pre-conditioning（JEDEC）

85℃ 85%RH 168 hrs
250℃ reflow 3 pass

0/22

Y-PLOT
99.999
99.99
99.9
99
95
90
80
70
60
50
40
30
20
15
10

3
2

Chipﾁｯﾌﾟ厚530
thickness:μｍｔ
530 µmt
ﾍﾟﾘﾌｪﾗﾙ実装
Peripheral
pad layout

1

6.30
5.00

0
-1
-2

7
5
4
3
2

-3
Chipﾁｯﾌﾟ厚200
thickness:μｍ
200 µmtｔ
ﾌﾙｱﾚｲ実装
Area array
pad layout

1.5
1

0.7
0.5
0.4
0.3
0.2
0.15
0.1
0.07
0.05
0.04
0.03
0.02
0.015
0.01

6.30
6.30
5.00

-40℃⇔+125℃
held 7 min各７分保持
at each temperature

-4
-5
-6
-7
-8
-9

10

100

-10
10000

1000

Accumulated failure rate lnln(1-/(1-F(t)))

Table 1

Area array pad layout

6.30
5.00

Figure 13 Sample for reliability evaluation.

Peripheral pad layout

Figure 14 Comparison of surface mounting methods.

6.30
5.00

Thickness of mounting substrate:
0.8 mm (FR-4, pattern on both sides)
Pad diameter: φ230 µm
Solder ball: φ300 µm SnAgCu
Chip thickness: 530 µm，200 µm
Mounting pad diameter: φ230 µm
Mounting pad pitch: 0.5 mm
Number of mounting pad
Area array pad layout: 121
Peripheral pad layout: 48

5.00

6.30

5.00

Accumulated failure rate F(t) (%)

6.30

Number of cycles (times)

Figure 15 Solder joint reliability test results.

Furukawa Review, No. 31

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Development of Wafer-Level Chip Size Package (WL-CSP)

reduce the chip thickness due to rather large stresses
resulting from the fact that the copper post is 100 µm inheight and that a thick resin layer is used to embed thecopper posts. In contrast with this, Furukawa’s WL-CSP
has great possibilities of reducing the chip thickness
lower than that evaluated at this time, because it undergoes back grinding process after bonding the wafer andthe tape substrate.
Now let us consider the failure mechanism of WL-CSP.
Failure analysis of cross-sections observed after thermal
shock tests suggests that failures occur between the solder ball and the mounting substrate or the WL-CSP, andmore precise observation reveals that cracks are createdat the interface between CuSn compound ---a hard substance made by diffusion of copper into solder, and solder which is rather soft. With respect to the location of
fracture occurrence, a major influence is exerted on thesolder balls on the four corners, because these are where
the stress due to the difference in the coefficients of thermal expansion between the semiconductor chip and thesubstrate tends to concentrate on. In accordance with
this, in actual evaluation, it has been confirmed that conductivity NGs occur at the solder balls on the four corners
very often.
Observation of peeled surfaces on the solder balls
reveals a continuous striped pattern which runs perpendicularly from the WL-CSP’s corners to the center. See
Figure 16. From these analyses, it can be seen that the
failure mechanism is such that due to repeated strains
generated by the difference in the coefficients of thermal
expansion between the semiconductor chip and themounting substrate, cracks are generated at the interface

between the hard metal compound layer and the soft solder layer, and they grow to cause fatigue fracture. Given
the fact that the Furukawa’s original WL-CSP having aproprietary structure of resin post fractures in the samemode as for the common BGA components mounted on
substrates using solder balls, it can be said that theyshare the same concept of reliability for mounting substrates. From this standpoint, we are making efforts topromote study to ensure reduced height and improved
reliability.

6.

CONCLUSION

We have recently developed WL-CSP, an ideal package interms of miniaturization and weight reduction, using a
manufacturing process completely different from conventional wafer process, whereby the tape substrate is bonded to the wafer. It has been confirmed that the new process makes quick delivery and reduced cost compatible,
and bonding reliability for mounting substrates is ensured
through the adoption of a new structure in which the terminal pads comprise resin posts. We have confirmed thepossibility of thin-bodied packages using the WL-CSP,
since good reliability has been confirmed for a thin package 200 µm in chip thickness, corresponding to a total
package thickness of 280 µm excluding solder balls.
While commercially available WL-CSPs are only applied
to high-yield wafers since they are manufactured by wafer
processes, Furukawa’s WL-CSP enables individual mounting of selected KGDs using a flip-chip bonder. Moreover,when it comes to semiconductor chips having multitudesof I/O pads, all the mounting pads can not be placed on
the bottom face of the chip to configure the fan-in, but incase of individual mounting of chips the fan-out layout byplacing mounting pads on the outside of the chip is permitted. Thus, this WL-CSP is expected to develop as ahigh-reliability semiconductor package with resin posts
for terminal pads.

反射電子像

Traveling directionof fracture
破壊進行方向Ｃu6Sn5

Enlargement

CuSn
Ｃu3Sn
layer
銅箔

Peeled surface on solder ballFigure 16 Analysis of failure.

REFERENCE
1) Hikasa et al., “Development of Flexible Bumped Tape Interposer”,
Furukawa Review, No.24, pp.59-64 (2003)

Furukawa Review, No. 31

200718