TECHNICAL DATA SHEETJade 54821
3-channel 200 MHz A/D with DDC,
2-channel 800 MHz D/A with DUC
3U VPX board with Kintex UltraScale FPGA

Complete radarand software radio
interface solution▪ Radar and communication receiver andtransmitter▪ Electronic Warfare transponder▪ Wideband data acquisition▪ Remote monitoring▪ Sensor interfaces▪ Waveform signal generator

The Jade® 54821 is a multichannel, high-speed data converter with
programmable DDCs (digital downconverters) and a DUC (digital
upconverter). It is suitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture feature offers
an ideal turnkey solution as well as a platform for developing anddeploying custom FPGA-processing IP.
It includes three A/Ds, a complete multiboard clock and sync section, a large DDR4
memory, three DDCs, one DUC and two D/As. In addition to supporting PCI Express Gen. 3
as a native interface, the 54821 includes optional high-bandwidth connections to the
Kintex UltraScale FPGA for custom digital I/O.

FEATURES▪ Exceptional dynamic range and analog
signal integrity▪ Xilinx® Kintex® UltraScale™ FPGA
▪ Three 200 MHz 16-bit A/Ds
▪ Three multiband DDCs (digital
downconverters)▪ One DUC (digital upconverter)▪ Two 800 MHz 16-bit D/As
▪ 5 GB of 2400 MHz DDR4 SDRAM▪ Programmable frequency synthesized
sample clock generator▪ Sample clock synchronization to an anexternal reference▪ PCI Express interface (Gen. 1, 2 & 3) up to x8▪ Multichannel, multiboard synchronization withclock/sync bus▪ Optional clock/sync generator for
multiboard systems▪ Optional LVDS port and gigabit serial
connections for custom FPGA I/O▪ Compatible with VITA-46, VITA-48 andVITA-65 (OpenVPX™ Specification)▪ Ruggedized and conduction-cooled
versions▪ Navigator Design Suite for software andcustom IP development▪ Powerful DMA controllers for moving data

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TECHNICAL DATA SHEETJade 54821

54821 BLOCK DIAGRAM (STANDARD CONFIGURATION AND OPTION -109 SHOWN.)
Click on a block for more information.

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TECHNICAL DATA SHEETJade 54821

54821 BLOCK DIAGRAM (OPTIONS -111 AND -112 SHOWN.)
Click on a block for more information.

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TECHNICAL DATA SHEETJade 54821

THE JADE ARCHITECTURE
Evolved from the proven designs of Mercury’s Cobalt® and Onyx®
families, Jade® raises the processing performance while lowering
the overall power requirements by building on the Xilinx family of
Kintex UltraScale FPGAs. As the central feature of the board
architecture, the FPGA has access to all data and control paths,
enabling factory-installed functions as well as providing an ideal
platform for user-created intellectual property (IP).
Each member of the Jade family is delivered with factoryinstalled applications ideally matched to the board’s analog
interfaces.

XILINX KINTEX ULTRASCALE FPGAS
Depending on the requirements of the processing task, the Kintex
Ultrascale can be selected from a range of FPGAs: KU035 through
KU115. The KU115 features 5520 DSP48E2 slices and is ideal formodulation/demodulation, encoding/decoding, encryption/
decryption, and channelization of the signals between
transmission and reception. For applications not requiring large
DSP resources or logic, a lower-cost FPGA can be installed.

A/D CONVERTER STAGE
The board's analog interface accepts three analog HF or IF
inputs on front panel SSMC connectors with transformercoupling into three Texas Instruments ADS5485 200 MHz, 16-bit
A/D converters. The digital outputs are delivered into the FPGA
for signal processing, data capture, and for routing to othermodule resources.

A/D ACQUISITION IP MODULES
The 54821 features three A/D Acquisition IP Modules for easily
capturing and moving data. Each module can receive data fromany of the three A/Ds, or a test signal generator. Eachacquisition module has a DMA engine for efficiently moving A/D
data through the PCIe interface.
These powerful linked-list DMA engines are capable of a unique
Acquisition Gate Driven mode. In this mode, the length of atransfer performed by a link definition need not be known prior
to data acquisition; rather, it is governed by the length of theacquisition gate. This is extremely useful in applications where
an external gate drives acquisition and the exact length of thatgate is not known or is likely to vary.
For each transfer, the DMA engine can automatically construct
metadata packets containing A/D channel ID, a sample-accurate
time stamp, and data length information. These actions

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simplify the host processor’s job of identifying and executing on
the data.

DDC IP CORES
Within each A/D Acquisition IP Module is a powerful DDC IP
core. Because of the flexible input routing of the A/D
Acquisition IP Modules, many different configurations can beachieved, including one A/D driving all DDCs or each of the A/Ds
driving its own DDC.
Each DDC has an independent 32-bit tuning frequency settingthat ranges from DC to ƒs, where ƒs is the A/D sampling
frequency. Each DDC can have its own unique decimation
setting, supporting as many as three different output
bandwidths for the board. Decimations can be programmed
from 2 to 32,768, providing a wide range to satisfy mostapplications.
The decimating filter for each DDC accepts a unique set ofuser-supplied 18-bit coefficients. The 80% default filters deliver
an output bandwidth of 0.8*ƒs/N, where N is the decimation
setting. The rejection of adjacent-band components within the
80% output bandwidth is better than 100 dB. Each DDC delivers
a complex output stream consisting of 24-bit I + 24-bit Q or16bit I +16-bit Q samples at a rate of ƒs/N.

D/A WAVEFORM PLAYBACK IP MODULE
The 54821 factory-installed functions include a sophisticated D/A
Waveform Generator IP module. A linked-list controller allows
users to easily play back to the dual D/As waveforms stored ineither on-board memory or off-board host memory.
Parameters such as location of waveform to be output, lengthof waveform, and delay from playback trigger, can be
programmed for each waveform. Up to 64 individual link entries
can be chained together to create complex waveforms with aminimum of programming.

DIGITAL UPCONVERTER AND D/A STAGE
A Texas Instruments DAC5688 DUC (digital upconverter) and D/A
accepts a baseband real or complex data stream from the FPGA
and provides that input to the upconvert, interpolate, and dual
D/A stages. When operating as a DUC, it interpolates andtranslates real or complex baseband input signals to any IF
center frequency from DC to the sample rate. It delivers real or
quadrature (I+Q) analog outputs to the dual 16-bit D/A converter.
Analog output is through a pair of transformer coupled front
panel SSMC connectors.

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TECHNICAL DATA SHEETJade 54821

If translation is disabled, the DAC5688 acts as a dual
interpolating 16-bit D/A with output sampling rates up to 800
MHz. In both modes, the DAC5688 provides interpolation factorsof 2x, 4x and 8x. In addition to the DAC5688, an FPGA-based
interpolator core provides additional interpolation from 2x to
32,768x. The two interpolators can be combined to create a
total range from 2x to 262,144x.

CLOCKING AND SYNCHRONIZATION
Two internal timing buses provide either a single clock or two
different clock rates to the A/D and D/A signal paths. Eachtiming bus includes a clock, sync, and a gate or trigger signal.
An on-board clock generator receives an external sample clockfrom the front panel SSMC connector.
This clock can be used directly for either the A/D or D/Asections or can be divided by a built-in clock synthesizer circuit
to provide different A/D and D/A clocks. In an alternate mode,the sample clock can be sourced from an on-board
programmable VCXO (Voltage-Controlled Crystal Oscillator). In
this mode, the front panel SSMC connector can be used toprovide a 10 MHz reference clock for synchronizing the internal
oscillator.
A front panel 26-pin LVPECL Clock/Sync connector allows
multiple modules to be synchronized. In the slave mode, it
accepts LVPECL inputs that drive the clock, sync and gate
signals. In the master mode, the LVPECL bus can drive thetiming signals for synchronizing multiple modules. Multiple
54821s can be driven from the LVPECL bus master, supporting
synchronous sampling and sync functions across all connected
modules.

3U VPX INTERFACEThe 54821 complies with the VITA 65.0 3U VPX specification. In
addition to supporting PCIe Gen. 3, x8 on the VPX P1 connector,
option -105 adds up to 8 more gigabit serial lanes connected
directly to the FPGA for supporting user-installed protocols.
The 54821 offers flexible analog and digital interface options for
the VPX-P2 to meet system-specific requirements.
Option -104 provides 24 pairs of LVDS connections between the
FPGA and the VPX P2 connector for custom I/O. This option
cannot be combined with option -111 or -112.
When purchased with option -109, the 54821 supports the
emerging VITA 66.5 standard and provides four optical duplex
lanes to a mating VITA 66.5 backplane connector. With the
installation of a serial protocol like 10 or 40 Gigabit Ethernet in
the FPGA, the VITA 66.5 interface enables high-bandwidthcommunications between boards or chassis independent of the
PCIe interface.
Options 111 and 112 provides analog signal routing through the
VPX backplane. Both options replace front panel connectors for
RF In, RF Out, Sample Clock/Reference Clock In and
Gate/Trigger/Sync/PPS In with coax signals that pass throughthe backplane for connections to other boards or chassis.
Option -111 is compatible with VITA 67.2. Option -112 iscompatible with VITA 67.3C.
See Specifications for the OpenVPX Profile.

MEMORY RESOURCES
The 54821 architecture includes a 5 GB bank of DDR4 SDRAM
memory. This resource is used by the board's built-in functions fordata storage and buffering, but can also be used for custom
applications. The Navigator FDK provides a memory controller aswell as guidance on the most efficient use of the memory whencreating IP functions.

PCI EXPRESS INTERFACEThe 54821 includes an industry standard interface fully compliant
with PCI Express Gen. 1, 2, and 3 bus specifications. Supporting PCIe
links up to x8, the interface includes multiple DMA controllers for
efficient transfers to and from the module.

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TECHNICAL DATA SHEETJade 54821

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on the
powerful AXI4 standard. multilevel documentation for each IP
core is a mouse click away, and fully consistent with Xilinx IP
cores.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado®
Design Suite includes the complete Vivado project folder foreach Jade product with all design files for the factory-installed
FPGA IP. Vivado’s IP Integrator is a graphical design entry toolthat visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Jade
design. Developers can quickly import, delete, and modify IP
blocks and change interconnection paths using simple mouse
operations.

The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational control of all
hardware functions on the board and IP functions in the FPGA. The
BSP structure is designed to complement the functions of the FDK bymaintaining a one-to-one relationship between FDK and BSP
components. For each IP block found in the FDK library, a matchingsoftware module can be found in the BSP. This organization simplifies
the creation and editing of software to support new IP functions andmodifications to existing IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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TECHNICAL DATA SHEETJade 54821

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEETJade 54821

A/D PERFORMANCE

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Spurious Free Dynamic Range

Spurious Pick-up

fin = 70 MHz, fs = 200 MHz, Internal Clockfs = 200 MHz, Internal Clock

Two-Tone SFDR

Two-Tone SFDR

f1 = 30 MHz, f2 = 70 MHz, fs = 200 MHz

f1 = 69 MHz, f2 = 71 MHz, fs = 200 MHz

Adjacent Channel Crosstalk

Input Frequency Response

fin Ch2 = 70 MHz, fs = 200 MHz, Ch 1 shown

fs = 200 MHz, Internal Clock

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TECHNICAL DATA SHEETJade 54821

D/A PERFORMANCE
Spurious Free Dynamic Range

Spurious Free Dynamic Range

fout = 70 MHz, fs = 800 MHz, Interpolation = 4,
Internal Clockfout = 100 MHz, fs = 800 MHz, Interpolation = 4,
Internal Clockmrcy.com

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TECHNICAL DATA SHEETJade 54821

FRONT PANEL CONNECTIONS: STANDARD

FRONT PANEL CONNECTIONS: OPTIONS -111 AND -112

The front panel includes six SSMC coaxial connectors and a 26pin Sync Bus connector for input/output of timing and analog
signals. The front panel also includes ten LEDs.

The front panel includes a 26-pin Sync Bus connector for
input/output of timing and analog signals. The front panel also
includes ten LEDs. See VPX P2 for RF and clock signals.

▪ Sync Bus Connector: The 26-pin front panel
connector, labeled SYNC/GATE, provides
clock, sync, and gate input/output pins for the
LVPECL Sync Bus.

▪ Sync Bus Connector: The 26-pin front panel
connector, labeled SYNC/GATE, provides
clock, sync, and gate input/output pins for the
LVPECL Sync Bus.

▪ Link LED: The green LNK LED blinks when avalid link has been established over the PCIeinterface.

▪ Link LED: The green LNK LED blinks when avalid link has been established over the PCIeinterface.

▪ User LED: The green USR LED is for user
applications.

▪ User LED: The green USR LED is for user
applications.

▪ Master LED: The yellow MAS LED illuminates
when this is the Sync Bus Master. When only asingle model is used, it must be a Master.

▪ Master LED: The yellow MAS LED illuminates
when this is the Sync Bus Master. When only asingle model is used, it must be a Master.

▪ PPS LED: The green PPS LED illuminates
when a valid PPS signal is detected. The LED
will blink at the rate of the PPS signal.

▪ PPS LED: The green PPS LED illuminates
when a valid PPS signal is detected. The LED
will blink at the rate of the PPS signal.

▪ Over Temperature LED: The red TMP LED
illuminates when an over-temperature orover-voltage condition is indicated by any of
the temperature/voltage sensors on the PCB.

▪ Over Temperature LED: The red TMP LED
illuminates when an over-temperature orover-voltage condition is indicated by any of
the temperature/voltage sensors on the PCB.

▪ Clock LED: The green CLK LED illuminates
when a valid sample clock signal is detected.
If the LED is not illuminated, no clock has been detected andno data from the input stream can be processed.

▪ Clock LED: The green CLK LED illuminates
when a valid sample clock signal is detected.
If the LED is not illuminated, no clock has
been detected and no data from the input
stream can be processed.

▪ Clock Input Connector: One SSMC coaxial connector,
labeled CLK, for input of an external sample clock.
▪ Analog Output Connectors: Two SSMC coaxial connectors,labeled OUT 1 and 2: one for each DAC5688 output.

▪ D/A Underrun LED: There is one red UR (underrun) LED forthe D/A output. This LED illuminates when the DAC5688 FIFO
is out of data.

▪ D/A Underrun LED: There is one red UR (underrun) LED forthe D/A output. This LED illuminates when the DAC5688 FIFO
is out of data.

▪ CH LEDs: There are three red CH1, CH2 and CH3 LEDs: onefor each A/D input. Each LED indicates either an analog input
overload in the associated ADS5485, or an A/D FIFO overrun.

▪ Analog Input Connectors: Three SSMC coaxial connectors,labeled IN 1, IN 2, and IN 3: one for each ADS5485 input channel.
▪ A/D Overload LEDs: There are three red OV (overload)
LEDs: one for each A/D input. Each LED indicates either ananalog input overload in the associated ADS5485, or an A/D
FIFO overrun.

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TECHNICAL DATA SHEETJade 54821

SPECIFICATIONS
Front Panel Analog Signal Inputs
Input Type: Transformer-coupled
Connector Type: SSMC (standard)
Transformer Type: Coil Craft WBC4-6TLB
Full Scale Input: +8 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz

A/D Converters
Type: Texas Instruments ADS5485
Sampling Rate: 10 MHz to 200 MHz
Resolution: 16 bits

Sample Clock Sources
On-board clock synthesizer generates two clocks: one A/Dclock and one D/A clock

Clock Synthesizer
Clock Source: Selectable from on-board programmable VCXO
(10 to 810 MHz), front panel external clock or LVPECL timing
bus
Synchronization: VCXO can be locked to an external 4 to 180
MHz PLL system reference, typically 10 MHz
Clock Dividers: External clock or VCXO can be divided by 1, 2,
3, 4, 6, 8, or 16, independently for the A/D and D/A clock

External Clock

Quantity: Three channels

Input Type: Sine wave, 0 to +10 dBm, AC-coupled, 50 ohms,
accepts 10 to 800 MHz divider input clock or PLL systemreference

Decimation Range: 2x to 32,768x in three stages of 2x to 32x

Connector Type: SSMC (standard)

Digital Downconverters

LO Tuning Freq. Resolution: 32 bits, 0 to ƒs
LO SFDR: >108 dB
Phase Offset Resolution: 32 bits, 0 to 360 degrees
FIR Filter: 18-bit coefficients, 24-bit output, with userprogrammable coefficients
Default Filter Set: 80% bandwidth, <0.3 dB passband ripple,>100 dB stopband attenuation

D/A Converters
Type: Texas Instruments DAC5688
Input Data Rate: 250 MHz max.
Output IF: DC to 400 MHz max.
Output Signal: 2-channel real or 1-channel with frequency
translation
Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x
interpolation
Resolution: 16 bits

Digital Interpolator CoreInterpolation Range: 2x to 32,768x in three stages of 2x to
32x

Total Interpolation Range
D/A and Interpolator Core Combined: 2x to 262,144x

Front Panel Analog Signal Outputs
Output Type: Transformer-coupled
Connector Type: SSMC (standard)
Transformer Type: Coil Craft WBC4-6TLB
Full Scale Output: +4 dBm into 50 ohms
3 dB Passband: 300 kHz to 700 MHz

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Timing Bus
26-pin connector LVPECL bus includes clock/sync/gate/PPS
inputs and outputs; TTL signal for gate/trigger and sync/PPS
inputsField Programmable Gate Array
Standard: Xilinx Kintex UltraScale XCKU035-2▪ Option -084: Xilinx Kintex UltraScale XCKU060-2▪ Option -087: Xilinx Kintex UltraScale XCKU115-2

Custom I/O
Option -104: Provides 24 pairs of LVDS connections between
the FPGA and the VPX P2 connector for custom I/O (notavailable with options -111 and -112)
Option -105: provides an 8X gigabit link between the FPGA
and the VPX P1 connector to support serial protocols (gigabit
link is 4X when combined with option -109)

VPX Options
Option -109: VITA 66.5 interface provides optical 4X duplex
lanes (not available with options -111 or -112).
Option -111: VITA 67.2: RF In, RF Out and Sample
Clock/Reference Clock In (these replace the front panel
connectors, not available with option -109).
Option -112: VITA 67.3C: RF In, RF Out and Sample
Clock/Reference Clock In (these replace the front panel
connectors, not available with option -109).

MemoryType: DDR4 SDRAM
Size: 5 GB
Speed: 1200 MHz (2400 MHz DDR)

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TECHNICAL DATA SHEETJade 54821

PCI-Express Interface

ORDERING INFORMATIONPCI Express Bus: Gen. 1, 2 or 3: x8

OpenVPX Profile

Model

Description

The 54821 is compatible with multiple OpenVPX profiles.
Profile for standard and option -109 shown below, contact
Mercury for other optional profiles.

54821

2-channel 500 MHz A/D with DDC, 2-channel 800 MHz D/A
3U VPX board with Kintex UltraScale FPGASLT3-PAY-2F2U1E-14.6.10-n.

Options:

Environmental
Standard: L0 (Air-cooled)▪ Operating Temp: 0° to 50° C▪ Storage Temp: –20° to 90° C▪ Relative Humidity: 0 to 95%, non-cond.
Option -702: L2 (Air-cooled)▪ Operating Temp: –20° to 65° C▪ Storage Temp: –40° to 100° C▪ Relative Humidity: 0 to 95%, non-cond.
Option -763: L3 (conduction-cooled)▪ Operating Temp: –40° to 70° C▪ Storage Temp: –50° to 100° C-084

XCKU060-2 FPGA-087

XCKU115-2 FPGA-104

LVDS FPGA I/O through P14 connector-105

Gigabit serial FPGA I/O-109

VITA 66.5: Optical 4X duplex lanes-111

VITA 67.2: RF In, RF Out and Sample Clock/Reference
Clock In-112

VITA 67.3C: RF In, RF Out and Sample Clock/Reference
Clock In

-702

Air-cooled, Level 2-741

VPX REDI compliant-763

Conduction-cooled, Level 3

Contact Mercury for compatible option combinations and complete
specifications of rugged and conduction-cooled versions. Options maychange, so be sure to contact Mercury for the latest information.

ACCESSORY PRODUCTS
Model

Description

2171

Cable Kit: SSMC to SMA▪ Relative Humidity: 0 to 95%, non-cond.

PhysicalDimensions: 3U VPX board▪ Depth: 170.61 mm (6.717 in)▪ Height: 100 mm (3.937 in)
Weight: Approximately 15.9 oz (450 grams)

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TECHNICAL DATA SHEETJade 54821

DEVELOPMENT SYSTEMSLIFETIME SUPPORT FOR JADE PRODUCTS

Mercury offers development systems for Jade products. They
come with all pre-tested software and hardware ready for
immediate operation. These systems are intended to saveengineers and system integrators the time and expense
associated with building and testing a development system that
ensures optimum performance of Jade boards. Please contact
Mercury to configure a system that matches your requirements.

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

FORM FACTORSJade products are available in standard form factors including
3U VPX, 6U VPX, PCIe, and XMC. The Jade Model 71821 XMC (3Channel 200 MHz A/D with DDC and 2-Channel 800 MHz D/A with
DUC, Kintex UltraScale FPGA) has the following variants:
Model
52821

3U VPX board (single XMC)

54821

3U VPX board (single XMC with optical/backplane RF)

57821

6U VPX board (single XMC)

58821

6U VPX board (dual XMC)

71821

XMC module

78821

PCIe board (single XMC)

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF54821

Visit: mrcy.com/go/MP54821+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Jade and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2023 Mercury Systems, Inc. 1-0-011823-DS-J54821

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