SDカー ドTLC:64-512GB
aTLC:16-256GB(ET1289+SanDisk Bics5 3D-TLC)

データシート

株式会社アドテック

SD 16-512GBREVISION HISTORYRevision

Description

Date

V1.0

New release

July 2023

V1.1

Added 512GB.

May 2024

2May 2024 Rev1.1

SD 16-512GB
1. Product Introduction
1.1. Overview
The Industrial SD Card is designed for demanding industrial applications.
The Industrial SD Card is compatible with SD 3.0 and provides excellent performance.
The built-in auto ECC function can detect and correct errors during data transfer.
Moreover, the Industrial SD Card supports Ultra High Speed (UHS) interface transfer mode,
provides high write/read data transfer rate, high random IOPS, sudden Power Fails protection,
adaptive static wear-leveling, read/program disturb management, etc.
It was designed to meet the high quality, high reliability, high performance, and versatileenvironmental requirements.
1.2. Product Features
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Interface: 9 pins SD standard interface
Compliant SD Card Specification Ver. 3.01 / 4.1 / 5.1 / 6.1
Density support:
 3D-TLC: 64GB~512GB
 3D-aTLC (Advanced TLC, single bit per cell TLC): 16GB~256GBBus Speed Mode: DS-Default Speed mode: 3.3V signaling, frequency up to 25MHz, up to 12.5MB/sec
 HS-High Speed mode: 3.3V signaling, frequency up to 50MHz, up to 25MB/sec
 SDR12: 1.8V signaling, frequency up to 25MHz, up to 12.5MB/sec
 SDR25: 1.8V signaling, frequency up to 50MHz, up to 25MB/sec
 SDR50: 1.8V signaling, frequency up to 100MHz, up to 50MB/sec
 SDR104: 1.8V signaling, frequency up to 208MHz, up to 104MB/sec
 DDR50: 1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up
to 50MB/s
Operating at -25°C to 85°C
Flash: 3D-TLC NAND Flash (SanDisk Bics5)
Controller: ET1289
Program/Erase Cycle:
 TLC: 3,000 Cycles
 aTLC: 30,000 Cycles
Built-in ECC corrects up to 120bits/1 KB
Read disturbance management (Auto-Refresh)
Adaptive wear levelingManagement of sudden power-fails
SMART Function support
aTLC (Advanced TLC, single bit per cell TLC) support, enhance the performance andproduct endurance.

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SD 16-512GB
1.3. TBW (Tera Bytes Written)
Capacity

16GB

32GB64GB128GB

256GB

512GBTLC――

112.6TB

225.3TB

450.5TB

900.9TB

aTLC

366.9TB

735.3TB

1470.1TB 2932.9TB 5669.7TB―*The endurance of disk could be varying based on user behavior, NAND endurance cycles, and write amplification factor.
It is not guaranteed by flash vendor.
*Client workload by JESD-219A

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SD 16-512GB
2 . SD Card Interface Description
2.1 SD Pin Assignment
Table 1: SD Bus Mode Pin Definition
Pin #Name

TypeSD Description

1

CD/DAT3

I/O

Card Detect /Data Line [Bit3]

2CMDPPCommand / Response

3VSSS

SupplyVoltage Ground

4VDDS

SupplyVoltage

5CLKIClock6VSSS

SupplyVoltage Ground

7DAT0

I/O

Data Line [Bit 0]

8DAT1

I/O

Data Line [Bit 1]

9DAT2

I/O

Data Line [Bit2]

Notes:1) S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers
2) The extended DAT Lines (DAT1-DAT3) are input on power up. They start to operate as
DAT lines after SET_BUS_WIDTH command. The Host shall keep its own
DAT1-DAT3 lines in input mode, as well, while they are not used. It is defined so, in orderto keep compatibility to Multi-media Cards.
3) After power up this line (Pin1) is input with 50Kohm pull-up (can be used for card detection
or SPI mode selection). The pull-up should be disconnected by user,
during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command.
Table 2: SPI Bus Mode Pin Definition
Pin #Name

TypeSD Description

1

CSI

Chip Select (neg true)

2DII

Data In3

VSSS

Supply Voltage Ground

4

VDDS

Supply Voltage5SCLKIClock6VSSS

Supply Voltage Ground

7DOO

Data Out

8RSVReserved

9RSVReserved

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SD 16-512GB

Figure 1: Functional Diagram

2.2 SD Bus Topology
The SD bus has six communication lines and three supply lines:
 CMD: Command is bi-directional signal. (Host and card drivers are operating in push pullmode.) DAT0-3: Data lines are bi-directional signals. (Host and card drivers are operating in pushpull mode.) CLK: Clock is a host to cards signal. (CLK operates in push pull mode.) VDD: VDD is the power supply line for all cards.
 VSS: VSS is the power ground line.
During the initialization process, commands are sent to each card individually, allowing theapplication to detect the cards and assign logical addresses to the physical slots. Data is always
sent to each card individually. However, to simplify the handling of the card stack, after
initialization, all commands may be sent concurrently to all cards. Addressing
information is provided in the command packet.

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SD 16-512GB
The following figure shows the bus topology of several cards with one host in SD Bus mode.

Figure 2: Memory Card System Bus Topology

2.3 SPI Bus Topology
The memory Card SPI interface is compatible with SPI hosts available on the market. As anyother SPI device, the SD Memory Card SPI channel consists of the following 4 signals:

CS: Host to card Chip Select signal.
CLK: Host to card clock signal.
Data In: Host to card data signal.
Data Out: Card to host data signal.

Another SPI common characteristic, which is implemented in the Memory Card as well, is bytetransfers. All data tokens are multiples of 8bit bytes and always byte aligned to the CS signal.
The card identification and addressing methods are replaced by a hardware Chip Select(CS) signal. There are no broadcast commands, a card (slave) is selected by asserting (activelow) the CS signal. The CS signal shall be continuously active for the duration of the SPI
transaction (command, response, and data). The only exception occurs during card programming,
when the host can de-assert the CS signal without affecting the programming process.
The SPI interface uses the 7 out of the SD 9 signals (DAT1 and DAT2 are not used, DAT3 is theCS signal) of the SD bus.

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SD 16-512GBFigure 3: SPI mode SD Memory Card Bus System

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SD 16-512GB
3 . Specifications
3.1 Performance
Max. Data Transfer Rate
 Read: 90MB/s; Write: 70MB/s
3.2 NAND Flash Memory
Industrial SD Card uses Triple Level Cell (TLC) NAND Flash memory, which is non- volatility, highreliability and highspeed memory storage.
3.3 Power Requirement
3.3.1. DC Input Voltage
 2.7V to 3.6V
3.4 Temperature Range -25°C to +85°C
3.5 HumidityRelative Humidity: 5-95%, non-condensing
3.6 Waterproof
Waterproof level: IEC 60529 IPX8.
Test Condition

Referred standard

Depth of water 1.5m for 30 mins.

IEC 60529 IPX8

3.7 ESD Ability
Test Condition

Referred standard

 Contact discharge: ± 2KV, ± 4KV

SD Spec. Appendix D.1

 Air discharge: ± 4KV, ± 8KV, ± 15KVSD Spec. Appendix D.2

3.8 Dust Proof
Dust proof level: IEC 60529 IP6X.
Test Condition

Referred standard

Depression of 2 KPa, Talcum powder 2kg/m³, 8 hrs. IEC 60529 IP6X

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SD 16-512GB
4 . Electrical Specifications
4.1 General DC Character
Table 3: General DC Character
Parameter

SymbolMinMaxUnit

Peak voltage on all lines

―-0.3

3.6

V

All input leakage current―-1010μA

All output leakage current―-1010μA

Supply voltage for low voltage range

VDDL

―

―

V

Supply voltage for high voltage range

VDDH

2.7

3.6

V

Supply voltage differential

―

-0.5

0.5

V

Remark

4.2 Bus Signal Line Loading
Table 4: Bus Signal Line Loading
SymbolMinMax

Unit

Pull up resistance for SD command line

Parameter

RCMD

4.7100KΏPull up resistance for SD data line

RDAT

10100KΏ

Total Bus capacitance for each signal line

CL―30pF

Signal line inductance――16pF

Pull-up resistance inside card (pin 1)

RDAT3

10150KΏ

Remark

4.3 Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.

Figure 4: Bus Signal Levels

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SD 16-512GB
Table 5: Bus Signal Level
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage

Symbol
VOH
VOL
VIH
VIL
VOH
VOL
VIH
VIL

Min
2.4―
2.0-0.3
1.4―
1.26-0.3

Max―Unit
V
VV
V
V
VV
V

0.4

3.6
0.8
―
0.45
2.1
0.58

Remark
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 1.8V
VDD = 1.8V
VDD = 1.8V
VDD = 1.8V

4.4 Bus Timing (Default Speed Mode)

Figure 5: Timing diagram data input/output referenced to clock (Default Speed Mode)
Table 6: Bus Timing - Parameters Values (Default Speed)
Parameter
Input CLK_SD
Clock frequency data transfer mode

SymbolMin.

Max.

UnitRemarkfpp―

25

MHz

CL≦ 10pF (1 card)

Clock frequency Identification mode

fOD―

400KHzCL≦ 10pF (1 card)tWL/tWH

10―ns

CL≦ 10pF (1 card)

Clock rise time / Clock fall timetTLH/tTHL
Input CMD_SD/DATA_SD, referenced to CLK_SD
Input set-up time
tISU

―

10ns

CL≦ 10pF (1 card)

5―nsCL≦ 10pF (1 card)

Input hold time
tIH
Output CMD_SD/DATA_SD, referenced to CLK_SD
Output Delay time during Data Transfer ModetODLY

5―ns

CL≦ 10pF (1 card)―14ns

CL≦ 40pF (1 card)

Output Delay time during Identification Mode―50ns

CL≦ 40pF (1 card)

Clock low time / Clock high timetODLY(1) All timing values are measured relative to 50% of voltage level.
(2) Rise and fall times are measured from 10% - 90% of voltage level.

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SD 16-512GB
4.5 Bus Timing (High-Speed Mode)

Figure 6: Timing diagram data input/output referenced to clock (High-Speed Mode)
Table 7: Bus Timing - Parameters Values (High-Speed)
Parameter
Input CLK_SD
Clock frequency data transfer mode

SymbolMin.

Max.

UnitRemarkfpp

050

MHzCL≦ 10pF (1 card)

Clock low time / Clock high time

tWL/tWH

7―ns

CL≦ 10pF (1 card)

Clock rise time / Clock fall timetTLH/tTHL
Input CMD_SD/DATA_SD, referenced to CLK_SD
Input set-up time
tISU―

3ns

CL≦ 10pF (1 card)

6―ns

CL≦ 25pF (1 card)

Input hold time
tIH
Output CMD_SD/DATA_SD, referenced to CLK_SD
Output Delay time during Data Transfer ModetODLY2―nsCL≦ 25pF (1 card)―14ns

CL≦ 40pF (1 card)

Output hold time
Total System capacitance for each line

2.5――40nspF

CL≧ 15pF (1 card)tOH
CL(1) All timing values are measured relative to 50% of voltage level.
(2) Rise and fall times are measured from 10% - 90% of voltage level.

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SD 16-512GB
Table 8: Bus Timing - Parameters Values (SDR104/SDR50/SDR25/SDR12)
Parameter

SymbolInput CLK_SD
Clock frequency data transfer modefpp
Clock cycle timetCLK
Clock duty cycle
Clock rise time / Clock fall timetTLH/tTHL
Input CMD_SD/DATA_SD, referenced to CLK_SD
Input set-up time for SDR104
tISU
Input set-up time for SDR50tISU
Input hold time
tIH
Output CMD_SD/DATA_SD, referenced to CLK_SD

Min.

Max.

Unit

Remark04.830―208―
70
0.2*tCLK

MHzns%
ns

CL = 10pF
CL = 10pF

1.4
30.8―
――nsnsns

CL = 10pF
CL = 10pF
CL = 5pF

Output Delay time for SDR50tODLY―

7.5ns

Output Delay time for SDR25 and sdr12

tODLY―14ns

Output hold time
Total System capacitance for each line

tOH
CL1.5――40nspF

CL = 10pF

CL = 30pF,
using driver Type B
CL = 40pF,
using driver Type B
CL = 15pF

4.6 Bus Timing (DDR Mode)

Figure 7: Timing diagram data input/output referenced to clock (DDR Mode)

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SD 16-512GB
Table 9 : Bus Timing – Parameters Values(DDR)
Parameter

Symbol

Min.

Max.

Unit

4555%

RemarkInput CLK_SD
Clock duty cycle
Input CMD_SD, referenced to CLK_SD
Input set-up timetISU

3―nsCL≦ 10pF (1 card)Input hold time

tIH

0.8―

ns

CL≦ 10pF (1 card)

Output Delay time during data transfer mode

tODLY

―

13.7

ns

CL≦ 30pF (1 card)

Output hold time

tOH

1.5―

ns

CL≧ 15pF (1 card)

Input set-up time

tISUddr3―

ns

CL≦ 10pF (1 card)

Input hold time

tIHddr0.8―

nsCL≦ 10pF (1 card)

Output Delay time during data transfer modetODLYddr―

7ns

CL≦ 25pF (1 card)

Output hold time

tOHddr1.5―

nsCL≧ 15pF (1 card)

Output CMD_SD, referenced to CLK_SDInput DATA_SD, referenced to CLK_SD

Output DATA_SD, referenced to CLK_SD

14

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SD 16-512GB
5. Mechanical Dimensions
The mechanical dimensions of industrial SD card were basically followed the mechanicalform factor definitions on SD-Memory card specifications which constructed by SD card
association.

Figure 13: Top View

Figure 15: Side View
Figure 14: Bottom View

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SD 16-512GB

6. Ordering Information
Flash Type

TLC

aTLC

Part Number

Capacity

ADS1U1064G3DEEDES

64GB

ADS1U1128G3DEEDES128GB

ADS1U1256G3DEEDES256GB

ADS1U1512G3DEEDES512GB

ADS1U1016GPDEEDES

16GB

ADS1U1032GPDEEDES

32GB

ADS1U1064GPDEEDES

64GB

ADS1U1128GPDEEDES128GB

ADS1U1256GPDEEDES

256GB

16NoteMay 2024 Rev1.1