TECHNICAL DATA SHEET

Quartz 6001
8-channel A/D & D/A QuartzXM modulewith Xilinx Zynq UltraScale+ RFSoC - Gen 1

Unique QuartzXM
eXpress Module enables
custom deployment▪ High-bandwidth data streaming▪ Waveform signal generator▪ Analog I/O for digital recording andplayback▪ Communication receiver and transmitter▪ Sensor interfaces▪ Electronic Warfare transponder

Quartz ® Model 6001 is a high-performance Quartz eXpress Module(QuartzXM) based on the Xilinx Zynq UltraScale+ RFSoC FPGA. The
RFSoC FPGA integrates eight RF-class A/D and D/A converters into the
Zynq’s multiprocessor architecture, creating a multichannel data
conversion and processing solution on a single chip.
The 6001 has been designed to bring RFSoC performance to a wide range of different
applications by offering the FPGA in a small system-on-module solution measuring only
2.5 by 4 inches. In addition to the RFSoC FPGA, the 6001 includes all of the support
circuitry needed to maximize the performance of the RFSoC. The 6001 is available on
standard form factor carriers including 3U VPX, SOSA aligned 3U VPX, PCIe, and small
form factor enclosures in both commercial and rugged options. In many applications oneof Mercury's carrier configurations can provide a final, deployable turn-key solution.
In situations where only a custom form factor will satisfy the application requirements,
Mercury supports the 6001 with a design kit that helps users engineer and build their own
custom carrier. As a complete and tested module, the Model 6001 QuartzXM encapsulates
best-in-class electrical and mechanical design, eliminating some of the most challenging
aspects of embedded circuit design and allowing users to focus on an application-specificcarrier design.

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TECHNICAL DATA SHEET
Quartz 6001

FEATURES▪ 16 GB of DDR4 SDRAM

The Navigator BSP includes support for Xilinx's PetaLinux runningon the ARM Cortex-A53 processors. When running under
PetaLinux, the Navigator BSP libraries enable complete control of
the 6001 either from applications running locally or on the ARMs,
or using the Navigator API control and command from remotesystem computers.

▪ LVDS connections to the Zynq UltraScale+ FPGA for custom
I/O

CARRIER DESIGN PACKAGE▪ Unique QuartzXM eXpress Module enables deployment incustom form factors▪ Incorporates Xilinx® Zynq® UltraScale+™ RFSoC▪ GTY connections for gigabit serial communication▪ Ruggedized and conduction-cooled versions available▪ Includes a complete suite of IP functions and example
applications▪ Navigator® BSP for software development▪ Navigator® FDK for custom IP development▪ Carrier Design Package available to enable custom carrier
design▪ Free lifetime applications support

Mercury offers the Model 4801 Carrier Design Kit for users
interested in designing their own carrier for the 6001 QuartzXM.
The kit uses the Mercury Model 5950 3U OpenVPX carrier as areference design. The kit includes:▪ Pin definitions and electrical specifications of all signals on
the module▪ 3D models of the module▪ Thermal profiles of the module and components▪ Carrier reference design schematics▪ PCB stack-up recommendations

BOARD ARCHITECTURE▪ PCB design guidelines and routing rules

The 6001 board design positions the RFSoC as the cornerstoneof the architecture. All control and data paths are accessible by
the RFSoC’s programmable logic and processing system. A fullsuite of Mercury-developed IP and software functions utilize
this architecture to provide data capture, generation, andprocessing solutions for many of the most common application
requirements. For many applications, the Model 6001's built-infunctions can be used as the foundation for custom
applications.

▪ Operating system and bootstrap guidelines

EXTENDABLE IP DESIGNFor applications that require specialized functions, users caninstall their own custom IP for data processing. Mercury’s
Navigator FPGA Design Kit (FDK) includes the board’s entire
FPGA design as a block diagram that can be edited in Xilinx’s
Vivado® IP Integrator. In addition to the IP Integrator block
diagrams, all source code and complete IP core documentation
is included. Developers can integrate their own IP along with thefactory-installed functions or use the Navigator kit tocompletely replace the Mercury IP with their own.

▪ Additional electrical and mechanical engineering guidanceModel 6001 QuartzXM customers must purchase the Model 5950
3U VPX carrier board, which includes the QuartzXM within an
open-standard form factor. This allows the user to start IP
development and proof of concept designs immediately on a
known, tested platform while they develop their own carrier forlater deployment. To further speed development tasks, Mercury
offers a single-slot 3U VPX development chassis with the Model
5950 installed, along with a rear transition module (RTM) and allneeded cables.

The Navigator Board Support Package (BSP), the companion
product to the Navigator FDK, provides a complete C-callable
library for control of the 6001’s hardware and IP. The Navigator
FDK and BSP libraries mirror each other where each IP function
is controlled by a matching software function, simplifying thejob of keeping IP and software development synchronized.

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Quartz 6001

6001 BLOCK DIAGRAM
Click on a block for more information.

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Quartz 6001

A/D CONVERTER STAGE

PCI EXPRESS INTERFACEThe 6001 accepts analog IF or RF inputs from the carrier board
on a multichannel connector, delivering the inputs asdifferential pairs into the RF signal chain of the RFSoC. Inside
the RFSoC, the analog signals are routed to eight 4 GSPS, 12-bit
A/D converters. Each converter has built-in digital
downconverters with programmable 1x, 2x, 4x, or 8x decimationand independent tuning. The A/D digital outputs are delivered
into the Zynq’s programmable logic and processor system forsignal processing, data capture, or for routing to otherresources.

In many applications, the 6001 will be used with a PCIe interface
provided by the carrier. The Navigator FDK library includes
multiple DMA controllers for efficient transfers to and from themodule.

POWER MANAGEMENT

In addition to the A/D’s built-in decimation, an additional stageof IP-based decimation provides another 16x stage of data
reduction, ideal for applications that need to stream data fromall eight A/Ds.

The RFSoC FPGA requires nine different and separate power
supplies. In addition, other peripheral circuits needed by the
RFSoC require separate supplies. The 6001 includes thirteen
different onboard power supplies to support the RFSoC andassociated circuitry. Because the supply complexity andsequencing is managed by the 6001 module, a custom carrierneeds only to provide a single 12V supply to the module, greatly
simplifying the carrier design.

D/A CONVERTER STAGE

EXPANDABLE I/O

The RFSoC’s eight D/A converters accept baseband real orcomplex data streams from the FPGA’s programmable logic.
Each 6.4 GSPS, 14-bit D/A includes a digital upconverter withindependent tuning and interpolations of 1x, 2x, 4x and 8x. The
individual D/A outputs are delivered to the carrier board througha multichannel connector as differential pairs.

The 6001 provides an interface to all of the digital signals
needed by the RFSoC’s processing system and programmable
logic sections through a high-speed connector to the carrier.
The RFSoC’s GTY high-speed gigabit serial interfaces aresupported by connectors capable of delivering 28 Gb/sec,
needed for protocols like 100GigE.

When the 6001 QuartzXM is installed on Mercury’s 3U Open VPX
carrier as the Model 5950, both the RF inputs and outputs aretransformer coupled to front panel MMCX connectors. For
applications that require special analog processing or
connectorization, the 6001 can be mounted on a customdesigned carrier to satisfy the specific application
requirements.

OPTIMIZED IP

CLOCKING AND SYNCHRONIZATIONThe 6001 accepts all of the clock signals required by the RFSoC
through a multisignal connector from the carrier. In addition,
the 6001 design includes a clock management section for
distributing the clock and synchronization signals throughout
the module.

MEMORY RESOURCES
The 6001 architecture supports up to a 8 GByte bank of DDR4
SDRAM memory accessible from the Programmable Logic. Userinstalled IP, along with the Mercury-supplied DDR4 controller
core within the FPGA, can take advantage of the memory forcustom applications.

Xilinx has created an integrated processing solution in the RFSoC
that is unprecedented. The key to unlocking the potential of the
RFSoC is efficient operation using optimized IP and application
software. Mercury helps streamline the process from development
to deployed application by providing a full suite of built-in functions.
These address the data flow and basic processing needed for someof the most common applications.
Several example applications using the Mercury Model 5950 are
described on the following pages. (The Mercury Model 5950
delivers the 6001 QuartzXM as a 3U OpenVPX board.) For eachexample, the board’s included IP is all that is needed todemonstrate the application and may satisfy the full set of
requirements for any particular application. These applications
can also be the starting point for adding additional IP from theNavigator IP library or for adding custom IP.

Up to an 8 GByte bank of DDR4 SDRAM is available to theProcessing System as program memory and storage.

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EXAMPLE 1 - HIGH BANDWIDTH DATA STREAMING
applications capturing the raw, full bandwidth data is crucial.
The 5950’s dual 100 GigE UDP engine provides a high bandwidth
path for moving data off of the board. Along with the built-in
data acquisition IP, the 5950 can stream two full bandwidth A/Ddata streams over optical cable to a downstream storage orprocessing subsystem.

The RFSoC’s eight 4 GSPS A/Ds are capable of producing an
aggregate data rate of 64 GB/sec when all channels are enabled.
While capturing this much raw data is not feasible, the A/Ds
built-in digital downconverters can reduce this data throughput
in many applications to a rate reasonable for the data streaming
and storage components downstream in the system. In some

DDR
SDRAM
RF In

A/Ds
Data
Acquisition
IP Block

Dual
100 GigE
UDP
IP Block

D/As
Zync UltraScale+ RFSoC

8x 25 Gb/sec
OpticalTransceivers

VPX

100 GigE Out 1
VITA
66.4

100 GigE Out 2

Model 5950

EXAMPLE 2 - WAVEFORM GENERATOR
The 5950’s IP supports multiple D/A signal source options. A
simple loopback path allows samples received by the A/Ds to be
output through the D/As. A CW signal generator produces a sine
output with programmable frequency. A chirp generator, ideal
for radar applications, outputs sweep signals with programmable

RF In

RF OutDDR
SDRAM

CW Signal
Generator
IP Block

A/Ds

D/As

frequency, ramp, phase offset, gain offset, and length. The
generators also include flexible trigger options with bothinternal and external triggering.

M
U
X

VPX

PCIe
Gen. 3x8

Chirp
Generator
IP Block
VITA
66.4

Zync UltraScale+ RFSoC
Model 5950

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EXAMPLE 3 - MULTIMODE DATA ACQUISITION SYSTEM
In some applications multiple data acquisition modes may need
to be operated at the same time. A required dataflow could be
full bandwidth streaming of a single A/D channel over 100 GigE toa data recorder while another channel of A/D data is stored assnapshots in the board's DDR4 SDRAM and read by the ARM

RF In

processor while yet other A/D channels are down converted
using the A/Ds’ built-in DDCs and streamed over PCIe. The 5950
provides these modes with built-in IP supporting complex data
streaming scenarios without the need for creating custom IP.

DDR SDRAM
Memory Control
IP Block

A/Ds
Data
Acquisition
IP Block

VPX

PCIe
Gen. 3
x8

VITA
66.4

100 GigE Out

PCIeGen. 3 X8
IP Block

D/As
Zync UltraScale+ RFSoC

DDR
SDRAM

Dual 100 GigE
UDP IP Block

8x 25 Gb/sec
OpticalTransceivers

Model 5950

FLEXIBLE MODULAR DESIGN
While the Quartz 6001 follows the form factor of a standard 3U
OpenVPX board, the unique modular design of Mercury’s 6001
QuartzXM eXpress Module provides the flexibility to deploy thissolution in many different situations. The heart of the QuartzXM
is a system on module containing all of the key components
including the RFSoC FPGA, DDR4 SDRAM, and power and clock
management.
In the case of the 6001, the QuartzXM is mounted on a 3U
OpenVPX carrier which complements the design with a timing
bus generator, analog signal conditioning, a GPS receiver and an
8x 28 Gbps optical transceiver. As a module and carrier board
set, the 6001 becomes a complete, ready to deploy 3U OpenVPX

solution available for a range of operating environments fromcommercial to rugged and conduction-cooled.
The 6001 QuartzXM can also be mounted on other carriers
available from Mercury to support standard form factors; or for
applications that require a non-standard footprint, Mercury
supports the module with a design kit for users to engineer andbuild their own custom carrier. As a complete and tested
module, the QuartzXM encapsulates best-in-class electrical andmechanical design, eliminating some of the most challenging
aspects of embedded circuit design and allowing the user tofocus on the application specific carrier design.

QuartzXM eXpress Module

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Quartz 6001

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.
The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design
Suite includes the complete Vivado project folder for each Jade
product with all design files for the factory-installed FPGA IP.
Vivado’s IP Integrator is a graphical design entry tool that visuallypresents the complete block diagram of all IP blocks so thedeveloper can access every component of the Jade design.
Developers can quickly import, delete, and modify IP blocks andchange interconnection paths using simple mouse operations.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on the
powerful AXI4 standard. multilevel documentation for each IP coreis a mouse click away, and fully consistent with Xilinx IP cores.
The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational
control of all hardware functions on the board and IP functionsin the FPGA. The BSP structure is designed to complement thefunctions of the FDK by maintaining a one-to-one relationshipbetween FDK and BSP components. For each IP block found in
the FDK library, a matching software module can be found in
the BSP. This organization simplifies the creation and editingof software to support new IP functions and modifications toexisting IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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Quartz 6001

SPECIFICATIONS

Digital Upconverters

Field Programmable Gate Array▪ Quantity: 1 per D/AProcessing System:

Type: (standard) Xilinx Zynq
UltraScale+ RFSoC XCZU27DR▪ Interpolation Range: 1x, 2x, 4x, and8x▪ Type: DDR4 SDRAM▪ Option -028: RFSoC XCZU28DR▪ LO Tuning Freq. Resolution: 48
bits

Speed: (standard) -1 speed grade▪ Option -002: -2 speed grade

RFSoC RF Signal Chain
Analog Inputs▪ Filter: 80% pass band, 89 dB stopband attenuation
Sample Clock▪ Quantity: 8▪ Source: Received through boardto-board, multichannel connector▪ Connector: Board-to-board,
multichannel differential▪ Quantity: 4 A/D clocks, 2 D/Aclocks▪ Input Type: Differential▪ SysRef▪ Full Scale Input: 1Vp-p into 100
ohm on-die termination▪ Received through board-to-board,
multichannel connector▪ RF Input Frequency Max: 4 GHz (asper Xilinx datasheet)
A/D Converters▪ Quantity: 8▪ Sampling Rate: 4.0 GHz▪ Resolution: 12 bits
Digital Downconverters▪ Quantity: 1 per A/D▪ Decimation Range: 1x, 2x, 4x, and
8x▪ LO Tuning Freq. Resolution: 48
bits, 0 to ƒs▪ Filter: 80% pass band, 89 dB stopband attenuation
Analog Outputs▪ Quantity: 8

RFSoC RF Processing System

Memory▪ Size: (standard) 4 GB; Option -151:
8 GB▪ Speed: 1200 MHz (2400 MHz DDR)
Programmable Logic:▪ Type: DDR4 SDRAM▪ Size: (standard) 5 GB; Option -151:
8 GB▪ Speed: 1200 MHz (2400 MHz DDR)

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 or
x8

Environmental
Option -703: L3 (conduction-cooled)

ARM Cortex-A53:▪ Operating Temp: –40° to 70° C▪ Quantity: 4▪ Storage Temp: –50° to 100° C▪ Speed: 1.5 GHz▪ Relative Humidity: 0 to 95%,
noncondensing

ARM Cortex-R5:▪ Quantity: 2▪ Speed: 600 MHz

QuartzXM Digital Connector(Programmable Logic)
Parallel: 32 single-ended or 16 pairs of
LVDS connections

PhysicalDimensions:▪ Depth: 101.6 mm (4 in)▪ Height: 63.5 mm (2.5 in)
Weight: 3.5 oz (99 grams)

GTY: 16 full duplex lanes @ 28 Gb/sec
Processing
GPIO: 8 single-ended

QuartzXM Digital Connector(Processing System)▪ Connector:Board-to-board,
multichannel differential

GTR: 4 full duplex lanes▪ Input Type: Differential

SPI: Quantity 1▪ Full Scale Output: 32 mA

UART: Quantity 1

D/A Converters

SD Card Interface: Quantity 1▪ Quantity: 8

GPIO: 8 single ended

I2C: Quantity 2▪ Sampling Rate: 6.4 GHz▪ Resolution: 14 bits

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Quartz 6001

ORDERING INFORMATIONQUARTZ PRODUCTS
The 6001 is also available on these carriers:

Model

Description

6001

8-channel A/D & D/A QuartzXM module with Xilinx Zynq
UltraScale+ RFSoC - Gen 1

Options

Description-002-2 FPGA speed grade, -1 standard-028

XCZU28DR FPGA (XCZU27DR is standard)-151

8 GB processor system memory, 8 GB programmable
logic memory-703

Air-cooled, Level L3

Contact Mercury for compatible option combinations and complete
specifications.

Model

Description

4801

QuartzXM Carrier Design Kit

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

Model

Description

5550

8-Channel A/D & D/A Zynq UltraScale+ RFSoC (Gen 1)
SOSA aligned 3U VPX board

5950

8-Channel A/D & D/A Zynq UltraScale+ RFSoC (Gen 1)
3U VPX board

6350

8-Channel A/D & D/A Zynq UltraScale+ RFSoC (Gen 1)
small form factor enclosure

6350S

8-Channel A/D & D/A Zynq UltraScale+ RFSoC (Gen 1)
small form factor subsystem

7050

8-Channel A/D & D/A Zynq UltraScale+ RFSoC (Gen 1) PCIe
board

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF6001

Visit: mrcy.com/go/MP6001+41 22 884 5100 tel

The Mercury Systems logo is a registered trademark of Mercury Systems, Inc. Other marks used herein may be trademarks or registered trademarksof their respective holders. Mercury products identified in this document conform with the specifications and standards described herein.
Conformance to any such standards is based solely on Mercury’s internal processes and methods. The information contained in this document issubject to change at any time without notice.
© 2023 Mercury Systems, Inc. 1-0-060623-DS-Q6001

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