DISCO Technical Review Feb. 2016

Silicon wafer thinning, the singulation process, and die strength
Sales Engineering Department
Abstract
In recent years, the realization of the IoT (Internet of Things) society, in which anyone can connect to thenetwork to search for anything at anytime from anywhere, is approaching. For the IoT to progress,
semiconductor devices (chips), such as various types of sensors and communication and memory devices,manufactured by forming a circuit on the silicon wafer, are essential. In general, both “thinning” and“minimizing” are required. On the other hand, die strength improvement is also very important for
improving the yield of the manufacturing process and enhancing the endurance of the final product. This
review explains the die strength of the CMP and DP stress-relief wafer thinning processes and the DBG
singulation process.

1. Introduction
During front-end production of semiconductor
devices, electronic circuits such as transistors areformed on the surface of a silicon wafer.
Subsequently, in back-end production, the wafer
backside is thinned and the wafer is singulated bydicing. The chips are then encapsulated in a
package that will be delivered to end-users. The
need for thinner chips has been growing in recent
years to support lower package heights and allow
several chips to be stacked and encapsulated inpackages.
For wafer thinning, the grinding process with agrinder is normally used from the viewpoints ofcost and productivity. Since wafers are ground in
the brittle mode, streaks called saw marks asshown in Fig. 1 are created and a damaged layer
remains on the processed surface.
In order to remove this damaged layer, a stressrelief process, such as chemical mechanicalpolishing (CMP) and dry polishing (DP), isStandard Process (TGM=Thin Grinding Mounting)

BG Wheel
Si Wafer
BG tape
Chuck Table

Si Wafer
Dicing tape

DBG Process
Half CutDicing

BG Tape
Laminating

Half-cut dicing firstBackGrinding

Dicing TapeMounting

BG TapeRemoving

Dividing into dies during backgrinding

Fig.2 DBG process flow

introduced. CMP uses slurry as an abrasive. DP
does not use water or chemicals, including slurry.
Consequently, DP excels in terms of cost andenvironment because it does not require abrasives
or recovery and treatment of wastewater.
When a wafer is cut into chips, full-cut dicing
with a blade is employed. Since this process alsouses the brittle mode, micro-cracks calledchippings are generated on the front and rear sidesof the wafer. As a countermeasure for thisproblem, dicing before grinding (DBG) process isalso applied. In this process, as shown in Fig. 2,grooving (half-cut dicing) is performed from thefront side before grinding. Then, when thehalf-cut groove is reached during grinding, thewafer is divided into chips.
DBG has an advantage in that backside chipping
can be greatly reduced since the damaged layer on
the backside caused by the half-cut dicing iseliminated by the grinding process. Fig. 3 shows
the difference between the backside chipping forstandard and DBG processes.

Fig.1 Saw mark image

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DISCO Technical Review Feb. 2016

the standard of cantilever bending test, the morecommonly used 3-point bending test wasemployed in this review.

Die backside after standard
process (single cut)

3. Evaluation results
3.1
Influence of saw marks
As mentioned above, due to grinding duringwafer thinning, saw marks remain. Since they areformed radially from the center, each chip has adifferent saw mark angle. Because of this, theinfluence of saw mark angles on the 3-point
bending die strength test was evaluated. Die
strength was measured for 20 chips each at threesaw mark angles: 0º, which is parallel to theindenter of the 3-point bending test, 45º, and 90º,
which crosses the indenter at right angle. For
grinding, wafers were thinned to 200 µm using
the #2000 and #4800 grinding wheels. For dicing,the standard full cut was performed.
As shown in Fig. 5, chip strength decreased
dramatically at 0º (when the indenter is parallel tothe saw mark). When comparing chips processedwith the #2000 wheel between 0º and 90º, theminimum value of the latter is 2.3 times higher
than the former. This result clearly shows that thedie strength is influenced by the saw mark angles.

Die backside after DBG

Fig.3 Photos showing backside chipping
comparison

Through these processes, memory chips used insmartphones and tablets can now be thinned tobelow 100 µm. However, wafers and chips are
sometimes broken in the manufacturing process,which deteriorates the yield. Therefore,
improvement in the die (chip) strength is requiredat the same time. This review will explain the die
strength at each stage of the semiconductor
production process.
2. Evaluation method
As a method of measuring the die strength,
Semiconductor
Equipment
andMaterials
International (SEMI) has specified the standard of
3-point bending as G86-0303[1]. In the 3-point
bending test, as shown in Fig. 4, a chip is simply
supported without securing both ends and a
vertical load is continuously applied with anindenter until the chip is broken. When the chipbreaks, the load is recorded as the maximum load.
On the upper side of the chip, compressive stress
is applied while tensile stress is generated on thelower side. Generally, brittle materials havehigher compressive stress than tensile stress. Thus,
this test observes the tensile stress on the lowerside. The maximum breaking load is calculated asa bending stress value per unit area with Equation1.

σ fb =

3PB L
2bh 2 (Equation 1)

Although SEMI has also defined G96-1014[2] as
Fig.5 Die strength by 3-point bending (saw markangle comparison)

3.2
Effect of stress relief
Next, the effect of stress relief for removing
grinding damage and saw marks to have a mirror
surface was evaluated. A layer of approximately 2µm was removed using the abovementioned CMPand DP to have a mirror surface after grinding

Fig.4 Die strength measurement by 3-point
bending

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DISCO Technical Review Feb. 2016

processed surface, die strength was increased dueto the greatly reduced backside chipping by DBG.
3.4
Summary
The 3-point bending test results reveal that
improving grinding damage (saw mark angle) on
the chip backside, first of all, enables increasing
the minimum values of chip strength. By reducing
the backside chipping after that, the overall
strength could be enhanced. The best results could
be obtained by the DBG + DP process.
Fig.6 Die strength by 3-point bending (stressrelief comparison)

4. Conclusion
The need for thinning of semiconductor chips is
becoming more intense. A size of 30 µm or less isrequired in some cases and therefore higher die(chip) strength becomes more important.
Naturally, damage sustained in chips must be
reduced using the lowest cost possible.
Identifying the proprieties of factors influencing
the chip strength is therefore very important. We
will further evaluate influencing factors at thesides and front surface of the chips.

with the #2000 wheel. For dicing, the standard
full cut was used again.
As a result, die strength independent of saw marks
could be obtained (Fig. 6). No difference in thedie strength between CMP and DP could be found.
However, although grinding damage wasremoved, the average and maximum values ofstrength were not substantially improved. Thispoint suggests that factors other than the chipbackside condition may influence the results ofthe 3-point bending test.

References[1] SEMI G86-0303：2011. TEST METHODFOR MEASUREMENT OF CHIP (DIE)STRENGTH BY MEAN OF 3-POINT
BENDING[2] SEMI G96-1014：2014. TEST METHODFOR MEASUREMENT OF CHIP (DIE)STRENGTH BY MEAN OF CANTILEVER
BENDIN

3.3
Influence of backside chipping
Lastly, the influence of chipping generated on thefour sides of chip backside was evaluated.
Comparative samples were made using the DBG
process, which can greatly reduce backsidechipping. For the backside condition of chips, thesurfaces processed with the #2000 and DP wheels
were evaluated.
As shown in Fig. 7, there was no difference
between standard full cut dicing and DBG for thebackside condition of chips processed with the#2000wheel.
However,
ontheDPFig.7 Die strength by 3-point bending (backsidechipping comparison)

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