Current-driven crystallization promotion
for multilevel storage in phase-change memory
You Yin, Rosalena Irma Alip, and Sumio Hosaka
Graduate School of Engineering, Gunma University
1-5-1 Tenjin, Kiryu, Gunma 376-8515, JapanABSTRACT
In this study, we report current-driven crystallization promotion for multilevel storage in both lateral and verticalphase-change memories (PCMs). For the lateral device, the active medium consists of a top 50-nm TiN/150-nm SbTeN.
It was demonstrated that the number of distinguishable resistance levels can readily reach 16 and even higher. For thevertical device, TiSi3/Ge2Sb2Te5/TiN structure was adopted and 8 distinct resistance levels were demonstrated. Theseresistance levels in this study result from the initial threshold switching and the subsequent current-driven
crystallization promotion induced by Joule heating.
Keywords Multi-level storage, Crystallization promotion, Phase-change memory

INTRODUCTION
To increase the memory capacity without further increasing cost, researchers have focused their attention on
multilevel storage (MLS), which is data storage of more than two levels per memory cell. 1) In recent years, MLS has
been demonstrated in both conventional and emerging memories, such as flash memory, phase-change memory(PCM),2-4) and resistive random access memory (RRAM). However, flash memory itself has many demerits and themechanism of RRAM is still not understood very well. And MLS was demonstrated by using multilayer structures or
the properties of phase-change materials with different phase-change temperatures. But the available number ofresistance levels is strictly dependent on the number of multilayers or the phase-change temperatures.
Although MLS with more than 8 resistance levels was demonstrated by some groups such as IBM based onhigh-power amorphization, 5) there is a lack of study on MLS based on low-power crystallization. In this study, we
report the control of resistance realized mainly through the gradual enlargement of the crystallization region induced bycurrent-driven Joule heating using a lateral and a vertical structures and 8-16 resistance levels are demonstrated using
this method.

RESULTS AND DISCUSSIONS
1. Lateral device
The active layers of the device consist of 150-nm-thick SbTeN6) layer and an additional top 50-nm-thick TiN layer asshown in Fig. 1(a). Fig. 1(b) shows our concept of MLS based on filament formation, crystallization and the subsequentenlargement of the crystalline zone (e.g., n resistance levels here).
Fig. 2(a) shows the programming characteristics of the device by current sweepings from 0 to the programming
currents Ip. The programming currents were 0.5, 1, 2, and 3.5 mA, respectively. It can be observed that the intermediatelevels were very stable because the changed resistance levels can be retained until the sweeping current became higher
than the former programming current. In particular, the resistance can be determined by the stop current. It should benoted that more intermediate levels are possible by reducing the programming current interval, as shown in Fig. 2 (b).
The resistance-programming current (R-Ip) curve in Fig. 2(c) shows the possibility of 16-level storage. Stability of theresistance levels created by crysatallization promotion shown in Fig. 3.
2. Vertical device
A cross section of our vertical device is schematically shown in Fig. 4.7) The crystallization (C-GST) promoted withincreasing amplitude of programming currents in our device was investigated on the basis of finite element analysis, asshown in Fig. 5. Figure 6(a) shows the shifted current-voltage (I-V) curves of Sn (n=1–8) when the current was swept
between the electrodes. We first swept the device current forward from 0 to the maximum current Imax1 of 0.2 mA andbackward from 0.2 to 0 mA. The I-V curve corresponds to S1 in Fig. 6(a). Then, we increased the maximum current to0.3 mA (Imax2) and swept the current from 0 to 0.3 mA and then back to 0 mA. The measured I-V curve corresponds toS2 in Fig. 4(a). Similarly, we gradually increased the maximum currents to 0.5mA (Imax3), and finally to 3.5 mA (Imax8),and the I-V curves of S3, S4, S5, S6, S7 and S8 were measured. All of these curves are shown in Fig. 6(b) without anyshift.
The device resistances read at a low current with increasing programming currents are shown in Fig. 6(c). Thesesubsequent gradual resistance drops resulted from the enlargement of the crystalline region, as shown in Fig. 5(a). 8
distinct and stable resistance levels were created here, and they were induced by current-driven programming. These
discrete resistance levels corresponding to crystallization regions of different sizes were determined by theprogramming currents.

CONCLUTIONS
A lateral SbTeN-based PCM device with a top TiN heating layer and a vertical TiSi3/Ge2Sb2Te5/TiN device wereproposed and investigated for multilevel storage. Current-driven crystallization promotion was demonstrated forultra-multiple-level storage. The crystallization induced by Joule heating is non-volatile, low-power and current-driven,and allows ultra-multiple-level storage. This phenomenon is expected to be employed in practical applications todramatically increase the memory capacity without increasing the cell size.

ACKNOWLEDGEMENTS
This work was financially supported by Grant-in-Aid for Young Scientists and Grant-in-Aid for Scientific
Research from the Ministry of Education, Culture, Sports, Science and Technology of Japan (Nos. 24686042,21710135, and 24360003).

REFERENCES
1.

Y. Yin, N. Higano, H. Sone, and S. Hosaka, Appl. Phys. Lett. 92 (2008) 163509.

2.

S. R. Ovshinsky, Jpn. J. Appl. Phys. 43 (2004) 4695.

3.

Y. Yin, K. Ota, T. Noguchi, H. Ohno, H. Sone, and S. Hosaka, Jpn. J. Appl. Phys. 48 (2009) 04C063.

4.

Y. Yin, and S. Hosaka, Appl. Phys. Lett. 100 (2012) 253503.

5.

Y. C. Chen, C. T. Rettner, S. Raoux, G. W. Burr, S. H. Chen, R. M. Shelby, M. Salinga, et al., Tech. Dig.
IEDM, 2006, p. 777.

6.

Y. Yin, H. Sone, and S. Hosaka, J. Appl. Phys. 102 (2007) 064503.

7.

Y. Yin, and S. Hosaka, Jpn. J. Appl. Phys. 51 (2012) 064101.

(b)Insulator
TiN heater
SbTeN

r1rｈ

rｎ-2

r2(b)

2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0

Wg=400 nm, Lg=1000 nm
17. 0-1.7 mA
9. 0-0.9 mA
16. 0-1.6 mA
8. 0-0.8 mA
15. 0-1.5 mA
7. 0-0.7 mA
14. 0-1.4 mA
6. 0-0.6 mA
13. 0-1.3 mA
5. 0-0.5 mA
12. 0-1.2 mA
4. 0-0.4 mA
11. 0-1.1 mA
3. 0-0.3 mA
10. 0-1.0 mA
2. 0-0.2 mA
17.

0.5

rhr2

1.5
2.0
2.5
3.0
Device voltage V (V)

3.5

4.050

r1

rｎ-2
rｎ-1
Principle for MLS
r1→r1cfield)
r2 →r2c

1. 0-0.1 mA(c)
Device current @ 0.5 V (mA)

r1

1.
1.0

S-shapedoutline(Crystallization due to concentration of electric

0.15(Crystallization via Joule heating- 1)

0.01

rn-2→rn-2c (Crystallization via Joule heating- n-3)
rn-1→rn-1c (Crystallization via Joule heating- n-2)100.05

0.0

0.4
0.8
1.2
Programming current (mA)

Device resistance (k)rｎ-1

TiN electrode
Insulator
Si Sub.

Device current I (mA)

(a)

1.6

Fig. 2 (a) and (b) MLS programming by current sweepof the device for MLS at programming current intervals

Fig. 1 (a) Schematic cross-sectional diagram of ourof

fabricated lateral PCM device with an additional top

between resistance and programming current, showing

TiN heating layer. (b) Equivalent circuit and principle ofstaircase-like characteristics for MLS.

0.5-1.5 and 0.1 mA, respectively. (c) Relationship(a)Ｒ4、“4”

Ｒ3、“3”
Ｒ2、“2”

Current @ 0.5 V (A)the device for MLS.
110
10090
80
7060504030
2010R3SL3R2SL2R1

SL1R001000 2000 3000 4000 5000 6000oＲ1、“1”

ＩＲ

Ｒ0、“0”

ＶＲ

Annealing time @ 80 C (s)Fig. 3 Thermal stability at 80oC.

Bottomelectrode

7Top
electrode

TiSi3

GST

SiO2

Sisubstrate

Fig. 4 Schematic cross-sectional diagram of our(a)fabricated vertical PCM device.

Device current I (mA)

6SiO2TiN
SiN

5
S8: 0-3.5-0 mA

S7: 0-2.5-0 mA

4

S6: 0-1.8-0 mA

3

S5: 0-1.2-0 mA

2

S4: 0-0.8-0 mA
S3: 0-0.5-0 mA1(a)S2: 0-0.3-0 mA

0 S1: 0-0.2-0 mA(b)

Device current I (mA)

0.0

0.4
0.6
0.8
Device voltage V (V)

2

S8

1

S1

Device resistance R (k)

0.0(c)

1.0

S8:0-3.5-0 mA
S7:0-2.5-0 mA
S6:0-1.8-0 mA
S5:0-1.2-0 mA
S4:0-0.8-0 mA
S3:0-0.5-0 mA
S2:0-0.3-0 mA
S1:0-0.2-0 mA

30(b)

0.2
0.4
0.6
0.8
Device voltage V (V)

1.01010.1
1
Programming current Ip (mA)

Fig. 5 (a) Simulated crystallization promotion based on
finite element analysis. Crystallization begins with a0.2

Fig. 6 multilevel storage in the fabricated device. (a)filament formation with an outline of . Crystallization

Shifted I-V curves when the current was swept forward

then proceeds from  to , and finally to . (b)from 0 mA to the programming current and backward

Temperature distribution of GST when a pulse isfrom the programming current to 0 mA. (b) I-V curves

applied. The outline of crystallized area changes from 

without any shift exhibit an S-shaped outline due to theto 

resistancechanges.

(c)

Deviceresistanceprogramming current showing eight resistance levels.

vs