IEEE 1149.7 Compact TAP

Overview

The Compact TAP IP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantageof IEEE 1149.7 features such as:• 2-pin access to your on-chip IEEE 1149.1 test infrastructure• Reduced scan times through shorter scan paths• Efficient use of the 2-pin interface for both test and debug
The Compact TAP IP supports all mandatory and optional features of IEEE Std. 1149.7-2009.

IEEE Std 1149.7-2009

IEEE Std. 1149.7-2009 defines a next-generation TestAccess Port (TAP), known as TAP.7, which extends IEEE1149.1 TAP (TAP.1) functionality in several ways. WhereasIEEE 1149.1 was original developed as a solution for
testing board-level interconnect, IEEE 1149.7 offers
additional features to support increased chip integration,
power management, application debug, and device
programming. IEEE 1149.7 features are grouped into sixclasses, each of which is a superset of all the lower classes:• Class T0 maintains strict compliance to IEEE 1149.1
while also providing support for multiple IEEE 1149.1
TAPs on a single chip
• Class T1 adds support for the IEEE 1149.7 commandprotocol, generation of functional and test resets, andpower control• Class T2 adds the capability to bypass a chip’s systemtest logic, resulting in a 1-bit path for Instruction
Register (IR) and Data Register (DR) scans• Class T3 adds support for connecting TAP.7
controllers in a 4-wire star topology (TAP.7 controllers
connected in parallel)• Class T4 adds support for 2-pin operation (allsignalling done using only TMS(C) and TCK(C)), whichmeans that TDO and TDI can be removed or used forother functions• Class T5 adds support for up to two data channels
for non-scan data transfers, with each data channel
supporting up to sixteen on-chip data transfer clients

IEEE 1149.7 Compact TAP IP Features• Supports IEEE 1149.7 classes T0–T5• Supports all mandatory and optional scan formats:
JScan0–3, MScan, OScan0–7, and SScan0–3• Supports all IEEE 1149.7 mandatory and optionalfeatures, commands, and registers• Firewall provides robust hot-connect protection bydisabling TCK to on-chip test logic until the Debug Test
System (DTS) deactivates hot-connect protection• Partitioned along IEEE 1149.7-specified functionalboundaries:• Reset and Selection Unit (RSU) for class T0 optionalfeatures(contained within the APU)
• Extended Processing Unit (EPU) for extended (classT1–T3) operation• Advanced Processing Unit (APU) for advanced (classT4 and T5) operation• Separate blocks for clock and reset signal conditioning• Data channel (class T5) logic is optional and is,therefore,isolated into a separate top-level module

Configuration Options

Through hardware parameters, you can select thefollowing optional features of the Compact TAP IP:• Power-down support. If you choose to include powerdown support, the Compact TAP IP supports all IEEE1149.7 powerdown modes and the power-down
mode restore feature. Powerdown support requires a32-kHz clock for the power-down timer• Data channel (class T5) support:• Transport function with 1 or 2 physical data channels(PDCs), each supporting up to 16 data channel clients• Transport function with 0 PDCs (no data channel
support; however, the Compact TAB IP remains online
if the DTS initiates the transport protocol to a different
target sharing the same DTS connection)• No transport function or data channelInterfaces• Compact IEEE 1149.7 (JTAG) interface to off-chip DTS• IEEE 1149.7 (JTAG) interface to on-chip test logic• Power control/status interface to on-chip logic• Functional/test reset interface to on-chip logic• Configuration interface for node ID, JTAG device ID,
decoupleat- startup, Controller ID, and TDI/TDO pinfunctions
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eusales@silvaco.com• Data channel interface for optional data channels• 32-kHz clock (optional, used for power-down modesupport)• Power-on reset• DFT signals to control clock and reset for scan testingof the Compact TAP logic

Configuring Interfaces

The off-chip interface of the Compact TAP IP includes all
required and optional IEEE 1149.7 interface signals, plus
the associated enable and pullup control signals for thechip-level I/O pads. You can choose to connect TCK(C),TMS(C), TDI(C), and TDO(C) to support both IEEE 1149.1
and IEEE 1149.7 debug/test environments or connect
only TCKC and TMSC to support only IEEE 1149.7 twopin
operation. For further flexibility, you can connect TDI(C)and TDO(C) and, at run-time, select either their respective
IEEE 1149.7 functions or user-defined functions.
The Compact TAP IP also supports nTRST and return
TCK (RTCK), each of which is optional and uses anadditional chip-level I/O pin. RTCK is not a standard IEEE
1149.7 signal, but is provided to support non-standard
implementations where TCK is adapted to an on-chipfunctional clock.
The interface to on-chip test logic is an IEEE
1149.1-compliant TAP interface for connection to a chiplevel TAP controller and, optionally, multiple embedded
TAP controllers. The 4-bit TAP state of the Compact TAP
IP is available for the on-chip test logic to use insteadof implementing an additional TAP state machine. The
onchip data channel client interface functions as definedin IEEE Std. 1149.7-2009.
The size of the Compact TAP IP class T4 configuration isapproximately 2500 gates in a typical 90-nm process. Class
T5 with full data channel support adds approximately1300 gates.

Deliverables• Synthesizable Verilog source code
• Integration testbench and tests• Documentation• Scripts for simulation and synthesis with support forcommon EDA tools

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