SDIF-3
Version 1.0

August/05/1999

Sony Corporation

1.Purpose
The purpose of SDIF-3 format digital interface is to enable DSD signal exchange between
various DSD equipment.
2.Application area
SDIF-3 format digital interface is to be used as DSD signal exchange between DSD
equipment.
3.Overview
This interface is based upon 75ohm BNC, unbalance transmission, 1channel in one cable andexternal word clock(WCK). And its bit rate is 5.6448MbPS(fsdsd = 2.8224Mbps) or
11.2896Mbps(fsdsd = 5.6448Mbps). Transmission is 1channel unbalance transmission and ituses word clock as synchronization technique.
4. Physical Characteristics
The SDIF-3 interface is based upon connectors and cables generally covered by thedescription “75ohm BNC”.
An equipment output is presented on a single 75ohm BNC female connector. If the equipment
has a conducting/metallic chassis the outer conductor of the BNC connector shall be directly
bonded to the chassis.
An equipment input is presented on a single 75ohm BNC female BNC connector, If theequipment has a conducting/metallic chassis the outer conductor of each BNC connector shallbe directly bonded to the chassis. Provision should be made to provide a switchable 75ohm
termination at each receiver. Such switching may be accomplished, either physically orelectrically, locally or remotely, manually or automatically.
5. Logical Characteristic
5-1 Modulation Method.
Phase Modulation
Bit rate= 5.6448Mbps when fsdsd is 2.8224MHz.
=11.2896Mbps when fsdsd is 5.6448MHz.

5-2 Word Clock
Duty 50%(±10%)frequency=44.1kHz

5-3 Format
It consists of signals of data and Word Clock , and data bits are immediately followed bytheir inverted bit signals.
Clock(twice dsd bit rate)

Source coding

Channel coding Data
(Phase Modulation)

1001

11tTLHtTHL

6. Timing Chart
Word Clock(WCK) and Channel coding data timing.
WCKtp

T

Channel Coding DatatjitterParameterT

T = 1/(2×ｆsdsd) (typical)

tp
tTLH(Rise Time)tTHL(Fall Time)tjitter (peak to peak)-20 ns < tp ＜ 20 ns
tTLH < 10 ns *1
tTHL < 10 ns *1
tjitter < 5 ns*1

When cable length=0m and 75Ω terminated.
tTLH = tTHL is desirable.

VOH (Outout Voltage High)tTLH or tTHL
0.9VO
H0.1VO
HT=1/(2×fsdsd)
7.Electrical characteristicParameter*2VOHVOL*2VOH > 2.4V
*2
VOL < 0.55V

When cable length=0m and 75Ω terminated.

8. Appendix
A. Recommended circuit diagrams
A-1 Unbalanced Driver+5V

10Ω
B1A1Signal

DIR
OE

22p

GND

GND

SN74ABT25245

A-2 Unbalanced Receiver+5V+5V

47Ω
Signal
75Ω
GND

33p

RA
B

S

Y

SN75124

APPENDIXAs SDIF-3 format DIO interface sends WORD CLOCK and DATA in different BNC cable, there
can be a difference in delay time between them. And also as SDIF-3 DATA is 88.5ns period
high-speed signal, there is a possibility of bit shift of data. Consideration on selection of BNC
cable and connection is needed to avoid this data bit shift.
1. When data transmitter is WORD CLOCK master.
Slave

Master
WCK
CH1
CH210m

WCK

10m
10m

CH1
CH2

2. When data receiver is WORD CLOCK master.
Slave
Master
WCK
CH1
CH21m

WCK

1m
1m

CH1
CH2

3. When there is a WORD CLOCK distributor.
Slave

Master
WCK
CH1CH2Slave

1m
1m

WCK

1m
1m
1m
1mWCKWC
K
WC
KWC
Slave
K
WCK

CH1
CH21m
1m
1m
1m

Slave
WC
K
CH1CH2CH1CH2CH3CH4CH5CH6