ColdFire® V2 Core & SPPC1
The ColdFire V2 Core & Standard Product Platform (CFV2SPPC1)
combines the ColdFire V2 Core with industry-proven platform
peripherals to form a complete low-cost, low-power
microcontroller subsystem supported by a vast ecosystem ofdevelopment tools and runtime software. The CFV2SPPC1 isthe same ColdFire V2 processor core and platform/peripheral
IP implemented in NXP MCF5208 devices. With the CFV2SPPC1,
you get:Standard Peripherals and Interconnect• A fully synthesizable implementation of the popular ColdFirearchitecture• Reliability—from processor and peripheral IP alreadydeployed in millions of embedded systems worldwide

Variations of the CFV2SPP5208 with different combinations of onboard peripherals are also available. For example, you can add
more peripherals, such as another Fast Ethernet Controller, oromit peripherals that you don’t need to reduce system gate count.

ColdFire V2 Core

Platform Features and Performance

The ColdFire V2 Core is a low-power, low-area, 32-bit processor
core with single-cycle-access local SRAM and a direct-mappedcache that can be configured as instruction cache, data cache,or split instruction/data cache. The ColdFire V2 Core delivers
over 250 DMIPS of performance at 240 MHz and includes anenhanced MAC unit for DSP-like functions and faster executionof multiply instructions.

On-board peripherals and their features include:

Like all ColdFire architecture processors, the ColdFire V2
Core features a variable-length instruction set for maximum
code density, industry-standard AMBA 2 AHB system bus
interface for rapid system integration, and a wide selection ofdevelopment tools, operating systems, drivers, and libraries
from both commercial and open source providers.

Example SoC Using
CFV2SPPC1.

The CFV2SPP5208 includes the ColdFire V2 Core, plus the fully
integrated peripherals shown in Figure 1, providing commonly
needed functions such as Ethernet, interrupt control, DMA, timers,and various serial interfaces. An AMBA 2 AHB Crossbar Switch
provides the system interconnect, supporting simultaneoustransfers between multiple AHB masters and slaves, including
externally-connected AHB masters and slaves.

• FlexBus Controller• Connects up to 6 on-chip or off-chip memories/devices• Independently programmable transfer characteristics foreach device (wait states, address setup/hold)• Enhanced DMA (eDMA) Controller• 16 independently programmable DMA channels• Programmable channel arbitration modes• Support for channel linking and scatter/gather operation• Interrupt Controller• 64 programmable interrupt sources, 20 of which areavailable for external interrupts• Unique vector for each interrupt source• Support for low-power mode wake-up• UART• Programmable clock source, data formats, and modes(normal/loopback)• Error detection• Four maskable interrupt conditions• DMA Timer module• Programmable clock source• Programmable prescaler• Programmable interrupt or DMA request upon timer
event• Miscellaneous Control Module (MCM)• Software watchdog timer• Reset status, low-power mode control, and core fault
status registers

Development Support
The ColdFire architecture, including the ColdFire V2 Core, issupported by a vast assortment of development systems/tools
and run-time software including libraries, stacks, drivers, andoperating systems from providers such as NXP, Green Hills
Software, Wind River Systems, and many more. A free versionof the GNU compiler supporting ColdFire V2 targets is alsoavailable from www.gnu.org.
NXP offers development boards, software, and CodeWarrior
Development Tools (including a free version. In addition, there
are several operating systems supporting the ColdFire V2architecture, including uClinux and several RTOS’s, such as theMQX RTOS from Embedded Access, Inc.

Deliverables• Verilog source code
• Integration testbench and tests

Power Saving Features
The CFV2SPP1 features software-controlled shutdown of
selected clocks to support a variety of chip-level low-power
modes:• Documentation• Scripts for simulation and synthesis with commonly-used
EDA tools• Independent shutdown of selected peripheral clocks• Shutdown of the ColdFire V2 Core CPU clock in response toa ColdFire STOP instruction

Debug Support
The CFV2SPPC1 supports ColdFire Debug Architecture Revision
B+, including:• Background Debug Mode (BDM)• Real-Time Trace (RTT)• Real-Time Debug (RTD)

For more information, please contact us at ip@silvaco.com.

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