DISCO Technical Review Mar. 2016

Wafer ultra-thinning process for 3D stacked devices and the influences on thedevice characteristics
Sales Engineering Department
Abstract
In the semiconductor industry, 3D integration using through-silicon via (TSV) has been considered to be a
promising way for improving performance and density instead of conventional device scaling. Si wafer
thinning is an important technology in 3D stacking. Since the ultra-thin device provides low aspect ratio
TSV, several advantages can be expected, such as reduced parasitic RC delay, lower power consumption,and lower TSV residual stress. However, the effects of ultra-thinning on the device are still unclear. In thisreview, we report the results of the electrical characteristics before and after thinning down to 10 µm using
FRAM (Ferroelectric Random Access Memory), HP (High performance) Logic, and DRAM (Dynamic
Random Access Memory).
TSV process can be achieved (Fig. 2).

1. INTRODUCTION
Scaling of devices—the driving force of thesemiconductor industry—is now facing a major
technical and economic transition stage. 3D
integration technology using through-silicon via(TSV) has been considered a promising solution
to overcome scaling limitations as reported in theexample of low volume production using TSV[1].
By connecting stacked chips with the TSV
vertical wiring, the wide bandwidth I/O andreduction of interconnects length can be achieved.
Further, shorter interconnects lengths lead to the
reduction of power consumption as well asparasitic resistance and capacitance. Stacked
devices can give us small footprint, and therefore,
this technology is expected to be used in mobile
devices (Fig. 1)[2]. Si wafer thinning is essential in
3D stacking because multiple devices are stacked.
A structure in which ultra-thinned wafers arestacked allows forming a low aspect ratio TSV
and reducing parasitic resistance and capacitance.
At the same time, lower power consumption,
lower TSV residual stress, and lower cost of the

However, the effects of ultra-thinning on devices
are not well explored yet. In this review, therefore,
the effects of thinning on devices will be clarified.
To report the thinning limit, electricalcharacteristics were evaluated and physicalanalysis was performed using ferroelectric
random access memory (FRAM), highperformance (HP) logic, and dynamic random
access memory (DRAM) wafers thinned to have a
Si thickness of 10 µm or less[2-5].
2. WAFER THINNING PROCESS
Si wafers are thinned in two stages: backgrinding(BG) and stress relief (Fig. 3). During thegrinding stage, the two types of grinding are
performed using wheels with different grit sizes.
The grit size is generally described as # (mesh),and the larger the value, the smaller is the grit size.
Rough grinding (#320) and fine grinding (#2000)
are performed up to their respective specified

Fig. 1 Comparison between 2D and 3D devices

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DISCO Technical Review Mar. 2016

caused by grinding and stress relief were analyzed.
The influence of strain caused by thinning wasanalyzed with µ-Raman spectroscopy. Afterrough grinding, fine grinding, and CMP, thewafers were measured from the backside in thedepth direction using µ-Raman spectroscopy andthe strain was calculated from the shift amount(Fig. 4). This graph shows a compressive stress ofapproximately 450 MPa was generated on thebackside after rough grinding and it remained as
an elastic stress up to the depth of 40 µm. After
fine grinding, the stress near the backside wassignificantly reduced to 120 MPa, and it remained
as an elastic stress up to the depth of 10 µm. After
CMP, no residual stress was observed because it
was reduced to a level that µ-Raman spectroscopy
cannot detect.

Fig. 2 Advantages of ultra-thinning of Si

thicknesses. In the rough grinding process using awheel with a large grit size, the grinding speed ishigh; however, a large damage layer remains on
the ground surface. Dislocation and stacking fault
can be found at a depth of up to approximately 5µm. This type of damage layer can besignificantly reduced through fine grinding using
a wheel with a small grit size. Nevertheless, evenafter grinding with #2000, a damage layer withthe thickness of approximately 0.2 µm remains.
When the final Si thickness is sufficiently thick,grinding can be completed with fine grinding.
However, because the damage layer at thebackside weakens the mechanical strength, stressrelief may be required to remove the damage layer
in the case of a thin chip. For example, stressrelief can be performed using ultra poligrind(UGP), chemical mechanical polish (CMP), anddry polish (DP). The combination of grinding andstress relief is optimized based on the required
specifications.

The distribution of vacancy-type defects causedby grinding was verified using positronannihilation spectroscopy (Fig. 5). When apositron with a positive charge is captured by avacancy-type defect after entering a solid, its
electron momentum distribution is different fromthat of the electron at an interstitial site. Therefore,
its Doppler broadening is sharpened. When thepositron is captured by the vacancy-type defect,
the shape parameter (S parameter) becomes larger.
In addition, larger the void size, the larger is the S
parameter. The distribution of defects simulated
from the measurement results of the Si wafer after
fine grinding and CMP are shown in Fig. 5. After
fine grinding, almost all defects stayed at a depthof approximately 100 nm from the backside,which is identical to the TEM observation results.
After the CMP, in accordance with the removal ofthe damage layer, defects are slightly distributed
up to the depth of 10 nm from the backside.

The backside strain and distribution of defects

Fig. 3 Si wafer thinning process and backside TEM images after grinding and stress relief

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DISCO Technical Review Mar. 2016

Temporary bonding & Thinning

450
Coarse grind

400

Fine grind

350

CMP

300

support wafer

Front side

Device wafer

Temporaryadhesive

support wafer

]
a 250
P
M
[ 200
s
s
150
e
tr
S 100

Device wafer

Permanent Bonding
support wafer
Device wafer
Base wafer

Permanent
adhesive50

De-bonding0

support wafer

-50
0

10

20

30

40

Device wafer

50

Base wafer

Distance from backside-surface [µm]Wafer Probing

Fig. 4 Depth profile of strain distribution usingµ-Raman spectroscopy (calculated from shift
amount)Device wafer
Base wafer

Fig. 6 Device wafer thinning and evaluation flowusing WOW process

As shown above, depending on the thinning
process, the backside strain and defectdistribution are significantly changed. Hereinafter,
influences of these strains and defects on devices
will be verified.

is coated, the wafer is thinned to the target
thickness by grinding. For the thinning process,only the stress relief method is varied dependingon the device type. The target remaining Si
thickness was 4-40 µm (Table 1). The
Grinder/Polisher DGP8761 (DISCO) was used
for grinding. Total thickness variation (TTV) was
less than 2 µm within a 300 mm wafer afterthinning. The thinned device wafer was mounted
on the second support substrate where thepermanent bond is coated, and the electricalcharacteristics were evaluated after de-bonding
the first support substrate.

3. EXPERIMENTAL
Device wafer thinning and evaluation flow using
the wafer-on-a-wafer (WOW) process isintroduced in this section (Fig. 6)[6]. The effects ofthinning were evaluated using 180-nm node
FRAM, 45-nm node HP logic, and 40-nm node
DRAM wafers.
After the device side of the wafer is bonded to thefirst support substrate where the temporary bond

0.56

Table 1

Wafer thinning process and target Si
thickness for each device type

DeviceCoarse
grind

Fine
grind

stressreliefFinal Si
thickness
[µm]

FRAM

#320

#2000

CMP

9

HP Logic

#320

#2000

UPG

7

DRAM

#320

#2000

w/o

40~4

0.555

Fine grind
0.55

r
te
e
m0.545ar
a
P 0.54
S
CMP
0.535

0.53
0

50

100

150

Depth [nm]Fig. 5 Distribution of defects simulated from themeasurement results of positron annihilation
spectroscopy

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DISCO Technical Review Mar. 2016

Fig. 9 TTV measurement results of the DRAM
wafer thinned to 4 µm

applied as stress relief process. Fig. 7 shows theSEM cross-sectional image and hysteresis
property of the FRAM wafer thinned up to a
thickness of 9 µm. Because the hysteresis
property before and after thinning shows only thedifference within the measurement error scope, it
indicates that the thinning and wet processes did
not cause degradation.

Fig. 7 (a) A SEM cross-sectional image of the
FRAM wafer after thinning and (b) hysteresis
property before and after thinning.

Next, the influence of thinning on the HP logic
device will be explained. The HP logic wafer wasprocessed with UPG as stress relief from themechanical strength and gettering property aspect
to thin it to have the remaining Si thickness of 7
µm. For this logic wafer, strain technology was
introduced to enhance the transistor performanceby improving electron mobility. This type ofwafer also has a Cu/Low-k interconnects structure
to improve RC delay, and its mechanical strength

4. RESULTS AND DISCUSSION
The characteristics before and after the thinningof FRAM, which is used as non-volatile memory,
were examined. FRAM uses ferroelectrics as acapacitor. If hydrogen is incorporated in the
ferroelectric film, it deprives oxygen from theferroelectric crystals. This causes a defect, andtherefore, the polarization characteristic of theferroelectric film is degraded. In order to verify
the influence of moisture, the CMP process wasFig. 10 (a) An image of the DRAM wafer thinned
to 4 µm and (b) the retention property before andafter thinning.

Fig. 8 (a) A SEM cross-sectional image of the HP
logic wafer after thinning and (b) drive electricalcharacteristics before and after thinning

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DISCO Technical Review Mar. 2016is weaker than that of the Al/SiO2 interconnects.
That is, it seems to be easily influenced by theresidual stress on the backside and the thinning
process. However, even when the wafer wasthinned to have a remaining Si thickness of 7 µm,
the transistor drive current did not change (Fig. 8).
This result indicates that residual stress anddefects that occur after UPG do not affect thecharacteristics of logic devices.

REFERENCE[1] D. U. Lee, K. W. Kim, K. W. Kim, H. Kim, J.
Y. Kim, Y. J. Park, J. H. Kim, D. S. Kim, H. B.
Park, J. W. Shin, J. H. Cho, K. H. Kwon, M. J.
Kim, J. Lee, K. W. Park, B. Chung, S. Hong,IEEE ISSCC2014, pp. 432 (2014).
[2] Y. S. Kim, S. Kodama, Y. Mizushima, N.
Maeda, H. Kitada, K. Fujimoto, T. Nakamura,
D. Suzuki, A. Kawai, K. Arai, and T. Ohba,
IEEE Symp. on VLSI Technol., pp.26 (2014).

Finally, the effect of the remaining Si thickness
on device characteristics was thoroughly
examined using the DRAM wafer. The Si
thickness was in the range from 4-40 µm and only
rough grinding and fine grinding were performed.
TTV ranged from 1.02 to 1.94 µm when a 300
mm wafer was processed. When the thickness
was 4 µm, TTV of 1.02 µm could be obtained (Fig.
9). The thickness of 4 µm is equivalent to 0.5 % of
the original thickness (775 µm) and it issufficiently thin for visible light to penetrate (Fig.
10 (a)). The variations of the retention
characteristic for the Si remaining thickness were
examined, but even when the wafer was thinned
to 4 µm, no degradation was observed (Fig. 10(b)). As explained in Chapter 2, compressive
stress and defects remain at the backside, and theretention characteristic does not change afterthinning. Therefore, it can be explained that stressand defects caused by grinding do not affectthicknesses up to 4 µm.

[3] Y. S. Kim, N. Maeda, H. Kitada, K. Fujimoto,
S. Kodama, A. Kawai, K. Arai, K. Suzuki, T.
Nakamura, and T. Ohba, Microelectronic Eng.,
Elsevier, 107 pp. 65 (2013).
[4] Y. S. Kim, A. Tsukune, N. Maeda, H. Kitada,
A. Kawai, K. Arai, K. Fujimoto, K. Suzuki, Y.
Mizushima, T. Nakamura, T. Ohba, T.
Futatsugi, and M. Miyajima, IEEE IEDM Tech.
Dig. pp.365 (2009).
[5] N. Maeda, Y.S. Kim, Y. Hikosaka, T. Eshita,
H. Kitada, K. Fujimoto, Y. Mizushima, K.
Suzuki, T. Nakamura, A. Kawai, K. Arai, and T.
Ohba, IEEE Symp. on VLSI Technol., pp.
105-106 (2010).
[6]T. Ohba, Y. S. Kim, Y. Mizushima, N. Maeda,
K. Fujimoto, and S. Kodama, IEICE Electronics
Express, 7 pp. 20152002 (2015).

5. CONCLUSION
The variations of electrical characteristics when
the FRAM, HP logic, and DRAM wafers were
ultra-thinned using the WOW technology were
examined. With this technology, the variations of
Si thickness could be 2 µm or less. In order toclarify the thinning effects on devices, thethinning of FRAM, HP logic, and DRAM wafers
with Si thicknesses of 9, 7, and 4 µm, respectively,
were evaluated. However, the degradation ofthese device wafers was not observed. In
addition, the physical analysis results did notreveal the effects of strain and defects caused bythinning.
The use of ultra-thin Si devices substantiallyshortens the interconnects length of a stacked
chip and greatly reduces parasitic resistanceand capacitance compared with conventional
devices. We are working on further optimizationand development of our technologies aiming at
providing ultra-thin devices.

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