1Development of a pipeline CAMAC controller
with PC/104-Plus single board computer
Yoshiji Yasu, Eiji Inoue, Hirofumi Fujii, Youichi Igarashi, Masahiro Ikeno, Manobu Tanaka, Kazuo
Nakayoshi, Hideyo Kodama, Shuichi Harada and Haruyuki Kyoo

Abstract--A pipeline CAMAC controller with PC/104-Plussingle board computer has been developed. The architecture ofthe pipeline CAMAC controller is completely different fromthat of traditional CAMAC controller. The pipeline CAMAC
controller adopted truly pipelined command and data paths
from/to computer memory to/from CAMAC. The pipelinemethod enabled the controller maximum speed of CAMAC,approximately up to 3 MB/sec with 24-bit data. The controller
also has a DAQ function such as event numbering for coexistence with other equipment such as VME.
Not only the functionality and the performance but also thepipeline architecture and the design concept are described.
I.

The PC/104-Plus is a standard PCI specification forembedded systems [2]. The board computer with low
power consumption includes a flash disk with IDE interface,
Fast Ethernet, USB and so on. Many PC/104-Plus based
single board computers are available in the industry.

INTRODUCTION

The Pipeline CAMAC controller occupies 2 slots(station 24,25) in a CAMAC crate[1]. In Fig. 1, there arethe controller in a CAMAC crate and a PC connected to thecontroller via Fast Ethernet. The controller consists of a
PC/104-Plus-based single board computer, PCI interface(PCI control) and CAMAC interface (CAMAC control).

Fig. 1. Pipeline CAMAC controller

Y.Yasu, E.Inoue, H.Fujii, Y.Igarashi, M.Ikeno, M.Tanaka, K.Nakayoshi
and H.Kodama are with High Energy Accelerator Research Organization(KEK), Tsukuba, Japan(http://www-online.kek.jp/ , http://onlax2.kek.jp/~kairo/
e-mail: Yoshiji.YASU@kek.jp)
S.Harada is with TOYO corporation, Tokyo, Japan(http://www.toyo.co.jp/)
H.Kyoo is with Fird corporation, Tokyo, Japan( http://www2.ocn.ne.jp/~fird/)

Fig. 2. Front Panel of Pipeline CAMAC controller
The PCI and CAMAC interfaces consist of an ALTERA
FPGA, respectively [3]. Those VHDL codes for theinterfaces have been also developed. The PCI control is
originally designed for the pipeline CAMAC controller while
the PCI cores available from commercial are not convenientfrom the pipeline point of view. The PCI control is also
designed in general purpose. The communication protocol
between the PCI and the CAMAC is well defined. Thus, thePCI control is usable for other I/O device.
The controller has a DAQ function such as event
numbering. The signal handling of trigger-input and busy-out
are implemented while the event count can be read out. Thisfeature is important to co-exist with other equipment such as
VME which already implements timing & trigger control
signaling.
From application point of view, the pipeline CAMAC
controller will make the traditional system based on CAMAC
powerful because it is an intelligent controller including CPUwith Fast Ethernet and realizes maximum speed of CAMAC
access.
II. FUNCTIONALITY
The pipeline CAMAC controller is located into 24th and25th slots of CAMAC crate. It mainly consists of PC/104-2Plus Single Board Computer, PCI control and CAMAC
control.
The board computer adopted is Advantech PCM-9370, 3.5inch (145 x 102 mm) Transmeta Crusoe 500 MHz processor
single board computer including TM5400 processor, 320 MB
memory, two IDE UltraDMA33 with 512 MB flash disk,
LCD/CRT controller, 10/100 Mbps Ethernet controller, two
1.1 compliant USB ports, mini-din connector for keyboard,
PS/2 mouse and so son [4]. The power consumption istypically 10.7W [4]. Those devices are available at the front
panel of the controller as in Fig.2.
In the CAMAC control, there are a CAMAC Executor, aCAMAC LAM Handler (CAMAC Interrupter), a DAQ
Executor and a DAQ Trigger Handler (DAQ Interrupter).
Figure 3 shows the architecture of CAMAC control. TheExecutors accept a packet including at least a command
frame or more from CPU via PCI, execute them and thensend reply frames to CPU. The frame is a unit of CAMACaccess. The pipeline CAMAC controller can execute
CAMAC command with small overhead continuously bygetting the command frames from a computer memory andthen sending the reply frames to the computer memory, via
PCI bus. The command FIFO and the reply FIFO have thesize of 256 frames each. The Interrupters generate a packet
including a reply frame and then send to CPU. When LAM
or Trigger interrupt occurs during the Executor processes apacket, the generation of interrupt reply frame will be
postponed. After the packet is processed, the interrupt reply
frame will be sent.

Fig. 3. Architecture of CAMAC control
The command and reply frames have 64-bit fixed-length.
It consists of an 8-bit header and a 56-bit payload. The
payload for basic CAMAC command frame contains
CAMAC station number N, CAMAC sub-address A,
CAMAC function F and data to be written if necessary. Thatfor the reply frame additionally contains CAMAC status suchas Q & X and read data if the CAMAC function is 'read'.
That for CAMAC LAM includes 24-bit LAM pattern andthat for DAQ Trigger includes 32-bit event count. DAQ
Executor can clear Busy-out signal while the signal disables
next event trigger. Fig. 4 and Fig. 5 show the frame formatof CAMAC function and DAQ function, respectively.

Fig. 4. Frame format of CAMAC function

Fig. 5. Frame format of DAQ function
The architecture of PCI control is shown in Fig. 5. There
are Tx/Rx FIFO, Tx/Rx engines and PCI multiplexer forTx/Rx. Tx and Rx engines work independently while PCI
multiplexer manages the PCI usage for Tx and Rx engines.
Tx/Rx FIFOs have the depth of 256 with 32-bit width each.
Tx/Rx engines have two modes, master and slave. The slavemeans PCI slave which the PCI interface becomes. In mastermode, the PCI interface can transfer data from/to memory incomputer without CPU intervention. Thus, master mode not
only reduces CPU usage but also realizes fast transfer incomparison with the slave mode. From the programming
point of view, the programmed I/O uses the PCI slave mode
while Block I/O (DMA) uses the PCI master mode.

Fig. 6. Architecture of PCI control

3On one hand, the pipeline CAMAC controller sends
multiple command frames, which include N, A, F and data ifnecessary, via Tx I/O registers. On the other hand, thecontroller receives multiple reply frames, which also includes
N, A, F, status (Q and X) and data if necessary, via Rx I/Oregisters. The operations to Tx and Rx are done concurrently,independently, or asynchronously. If DMA is used in bothsides, the throughput reaches maximum speed. DMA
function is provided on traditional CAMAC controller [5],but the function is limited such as Address-scan, Q-stop andso on. For the pipeline CAMAC controller, any operations toCAMAC are executed in DMA mode. There is no limitation.
Thus, the pipeline CAMAC controller is completely different
from traditional CAMAC controller, from DMA point ofview, too.
There are special CAMAC functions to the controller itself.
For examples, CAMAC C and CAMAC Z are generated bythose functions. All of the functions are shown in Table I.
The fast cycle means S2 timing will be ignored in this mode.
This is illegal from CAMAC protocol point of view, butthere are lots of CAMAC modules usable in this mode.
TABLE ISPECIAL CAMAC FUNCTIONSTABLE IIPCI I/O REGISTER MAP

In block I/O, memory address register is used for pointing
to address of kernel command/reply frame buffers and presetcount register represents the number of frames in quad-word(8 bytes) to be transferred. After the transfer is initiated by
setting DMA-start flag, the actual count register counts thenumber of frames in quad-word (8 bytes) transferred actually.
Control register and status register contains control andstatus information related to interrupt and block transfer.
System register is used by system administrator.

IV. SOFTWARE

III. OPERATIONThe PCI I/O register map includes three kinds of registers.
One is for Tx and another is for Rx. The other is system
register. Those registers are located in PCI I/O space and thesize of those registers is 32-bit. Table II shows the map.
In programmed I/O, data1 and data2 registers for Tx andRx are used for sending command frames and receiving replyframes, respectively. FIFO count register contains number ofdata in long-word (4bytes). For an example, Rx FIFO countregister is used for getting the number of data to betransferred as reply frames after sending command frames.

The choice of a suitable Operating System (OS) for PC
compatible hardware is dependent on the expectedfunctionality. Since the software tools, like compilers andutilities are, Open Source Software / GNU products, acommodity Open Source OS, Linux is chosen. A Linux
distribution kit tailored by KEK is implemented for thepipeline CAMAC controller.
The board computer has a flash disk. The flash disk has alimited life expectancy. The life expectancy is measured in
the number of erase cycles. Linux frequently erases thedirectories of /var and /tmp. Thus, they are implemented as
RAM disk.
The device driver and the library for the pipeline CAMAC
controller have been developed. CAMAC and DAQ
command frames are generated and then stored into a frame
buffer by the frame generator. The command frames in aframe buffer are executed by Programmed I/O routines,
Block I/O routines or the combined routines in same manner.
The reply frames are stored into another frame buffer as
result of the command frame executions. The reply frame
includes CAMAC status and data. The extractors of thestatus and the data from the reply frames are provided. The

4wait routines for LAM interrupt and Trigger interrupt arealso available [6], [7].
V. DESIGN CONCEPTThe pipeline CAMAC controller adopted truly pipelined
command and data paths from/to computer memory to/from
CAMAC. The pipeline method enabled the controller
maximum speed of CAMAC access, approximately up to 3
MB/sec with 24-bit data. In the pipeline method, themultiple command frames and the multiple reply frames areprocessed asynchronously, independently or concurrently.
This feature is different from that of the traditional CAMAC
controller [8] and expands the feasibility of I/O method. Thepipeline method is best for the speed up of I/O throughput.
The method applied to the pipeline CAMAC controller isgenerally usable, namely, as the access method to I/O object
controller, which includes not only CAMAC but also readoutequipment such as Flash ADC as in Fig. 7.

Fig. 7. Access to I/O object
VI.

Fig. 8. CAMAC timing

VII. CONCLUSIONS
A pipeline CAMAC controller with new architecture has
been developed.
The CAMAC access speed reached up to maximum speedof CAMAC, approximately 3 MB/s with 24-bit data.
The pipeline method will be useful for not only CAMAC
controller but also other controller, generally, I/O objectcontroller.

PERFORMANCECAMAC executor executes a CAMAC command frame in1.04 usec. Fig. 8 shows CAMAC timing. There are CAMAC
Busy signal and CAMAC S1 signal in the vertical axis. The
horizontal axis is timing in unit 1 usec. Each CAMAC cycle
is continuously done in 1.04 usec The speed was achievedby the DMA operation.
In fast mode which ignores CAMAC S2 timing signal, it
executes the command frame in 0.72 usec.

VIII. ACKNOWLEDGMENT
The authors would like to thank the people in KEK online
and electronics group for their support.
IX. REFERENCES
[1]

[2]
[3]
[4]
[5]

[6]
[7]
[8]

IEEE, "IEEE Standard Modular Instrumentation and Digital Interface
System (CAMAC) (Computer Automated Measurement and Control)
IEEE Std 583-1975
PC/104 Embedded Consortium, PC/104-Plus Specification Version 1.2,
August 2001
Altera Corporation, http://www.altera.com/Advantech Co., Ltd., Board computer PCM-9370
http://www.advantech.co.jp/epc/SBC/biscuit/pcm9370.html
KineticSystems Corp., VME to 3922 Interface w/DMA model 2917Z1A & Model 2915-Z1A & PCI Interface to 3922 Model 2915Z1A & Parallel Bus Crate Controller Model 3922-Z1B
http://www.kscorp.com/www/products/camac.htm
Home page of Parallel CAMAC project,
http://www-online.kek.jp/~yasu/Parallel-CAMAC/
Yet another page of Parallel CAMAC project in Japanese,
http://www-online.kek.jp/~inoue/para-CAMAC/TOYO Corp., CAMAC Crate Controller type CC/7700 and HostInterface Board types CC/ISA and CC/PCI in Japanese
http://www.toyo.co.jp/daq/index.html