3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16CDATASHEET

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1

Rev.1.6

GD25B16C

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Contents
1.

FEATURES ..............................................................................................................................................................42.

GENERAL DESCRIPTION .........................................................................................................................................5

3.

MEMORY ORGANIZATION .....................................................................................................................................7

4.

DEVICE OPERATION ...............................................................................................................................................8

5.

DATA PROTECTION ................................................................................................................................................96.

STATUS REGISTER ................................................................................................................................................ 117.

COMMANDS DESCRIPTION ................................................................................................................................. 13
7.1.

WRITE ENABLE (WREN) (06H) ................................................................................................................................ 16

7.2.

WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 16

7.3.

READ STATUS REGISTER (RDSR) (05H OR 35H) .......................................................................................................... 16

7.4.

WRITE STATUS REGISTER (WRSR) (01H) ................................................................................................................... 17

7.5.

WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 17

7.6.

READ DATA BYTES (READ) (03H)............................................................................................................................. 18

7.7.

READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .............................................................................................. 18

7.8.

DUAL OUTPUT FAST READ (3BH) .............................................................................................................................. 19

7.9.

QUAD OUTPUT FAST READ (6BH) ............................................................................................................................. 19

7.10.

DUAL I/O FAST READ (BBH) .................................................................................................................................... 20

7.11.

QUAD I/O FAST READ (EBH) ................................................................................................................................... 22

7.12.

QUAD I/O WORD FAST READ (E7H) ......................................................................................................................... 23

7.13.

PAGE PROGRAM (PP) (02H) .................................................................................................................................... 24

7.14.

QUAD PAGE PROGRAM (32H) .................................................................................................................................. 25

7.15.

SECTOR ERASE (SE) (20H) ....................................................................................................................................... 26

7.16.

32KB BLOCK ERASE (BE) (52H) ............................................................................................................................... 27

7.17.

64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 27

7.18.

CHIP ERASE (CE) (60/C7H) ..................................................................................................................................... 28

7.19.

DEEP POWER-DOWN (DP) (B9H) ............................................................................................................................. 28

7.20.

RELEASE FROM DEEP POWER-DOWN OR HIGH PERFORMANCE MODE AND READ DEVICE ID (RDI) (ABH) .............................. 29

7.21.

READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 30

7.22.

READ IDENTIFICATION (RDID) (9FH) ......................................................................................................................... 31

7.23.

HIGH PERFORMANCE MODE (HPM) (A3H) ................................................................................................................ 31

7.24.

CONTINUOUS READ MODE RESET (CRMR) (FFH)........................................................................................................ 32

7.25.

READ UNIQUE ID (4BH) .......................................................................................................................................... 33

7.26.

PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 33

7.27.

PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 34

7.28.

ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 34

7.29.

PROGRAM SECURITY REGISTERS (42H) ....................................................................................................................... 35

7.30.

READ SECURITY REGISTERS (48H) ............................................................................................................................. 36

7.31.

ENABLE RESET (66H) AND RESET (99H) ..................................................................................................................... 37

7.32.

READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) ................................................................................................. 37

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Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash8.

GD25B16C

ELECTRICAL CHARACTERISTICS ............................................................................................................................ 42
8.1.

POWER-ON TIMING ........................................................................................................................................... 42

8.2.

INITIAL DELIVERY STATE ..................................................................................................................................... 42

8.3.

ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 42

8.4.

CAPACITANCE MEASUREMENT CONDITIONS .................................................................................................... 43

8.5.

DC CHARACTERISTICS......................................................................................................................................... 44

8.6.

AC CHARACTERISTICS ......................................................................................................................................... 45

9.

ORDERING INFORMATION................................................................................................................................... 48
9.1.

10.

VALID PART NUMBERS ............................................................................................................................................ 49
PACKAGE INFORMATION ................................................................................................................................. 50

10.1.

PACKAGE SOP8 150MIL ........................................................................................................................................ 50

10.2.

PACKAGE SOP8 208MIL ........................................................................................................................................ 51

10.3.

PACKAGE USON8 (3X2MM, 0.45MM THICKNESS) ....................................................................................................... 52

10.4.

PACKAGE WSON8 (6X5MM) ................................................................................................................................... 53

11.

REVISION HISTORY .......................................................................................................................................... 54

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Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

1. FEATURES
� 16M-bit Serial Flash� Program/Erase Speed-2048K-byte-Page Program time: 0.6ms typical-256 bytes per programmable page

-Sector Erase time: 45ms typical-Block Erase time: 0.15/0.25s typical� Standard, Dual, Quad SPI-Chip Erase time: 7s typical-Standard SPI: SCLK, CS#, SI, SO� Flexible Architecture-Dual SPI: SCLK, CS#, IO0, IO1-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3-Sector of 4K-byte-Block of 32/64k-byte

� High Speed Clock Frequency
� Low Power Consumption-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s-1μA typical stand-by current-Quad I/O Data transfer up to 480Mbits/s-1μA typical power down current

� Software Write Protection

� Advanced Security Features-Write protect all/portion of memory via software-128-Bit Unique ID for each device-Top or Bottom, Sector or Block selection-4*256-Byte Security Registers With OTP Locks-Discoverable parameters(SFDP) register� Cycling endurance� Single Power Supply Voltage-Minimum 100,000 Program/Erase Cycles-Full voltage range:2.7~3.6V

� Data retention

� Package Information-20-year data retention typical-SOP8 (150mil)-SOP8 (208mil)-USON8(3x2mm, 0.45mm thickness)-WSON8 (6*5mm)

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Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

2. GENERAL DESCRIPTIONThe GD25B16C (16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad
SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2, and I/O3. The Dual I/O data is transferred with speedof 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.

CONNECTION DIAGRAM
CS#

1

8

VCC

CS#

1

SO

2

7

IO3

SO

2

IO2

3

6

SCLK

IO2

3

VSS

4

5

SI

VSS 4

Top View

8�LEAD SOP

Top View

8�LEAD USON/WSON

I/O

Description

CS#

I

Chip Select Input

SO (IO1)

I/O

Data Output (Data Input Output 1)

IO2

I/O

Data Input Output 2
GroundSI (IO0)

I/O

Data Input (Data Input Output 0)

SCLK

I

Serial Clock Input

IO3

I/O

Data Input Output 3

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Power Supply

5

Rev.1.6

7

IO3

5

Pin Name

VCC

VCC

6 SCLKPIN DESCRIPTION

VSS

8

SI

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16CBLOCK DIAGRAM

IO2
IO3
SCLK

SPI
Command &Control Logic

CS#
SI(IO0)SO(IO1)

Write Protect Logic
and Row Decode

StatusRegisterHigh Voltage
Generators
Page Address
Latch/Counter

Column Decode And
256-Byte Page Buffer

Byte Address
Latch/Counter

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Flash
Memory6

Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

3. MEMORY ORGANIZATION
GD25B16C
Each device has

Each block has

Each sector has

Each page has

2M

64/32K

4K

256

bytes

8K

256/128

16

-

pages

512

16/8

-

-

sectors

32/64

-

-

-

blocksUNIFORM BLOCK SECTOR ARCHITECTURE
GD25B16C 64K Bytes Block Sector Architecture
Block

31

30

……

……

2

1

0

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SectorAddress range

511

1FF000H

1FFFFFH

……

……

……

496

1F0000H

1F0FFFH495

1EF000H

1EFFFFH

……

……

……

480

1E0000H

1E0FFFH

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

47

02F000H

02FFFFH

……

……

……

32

020000H

020FFFH

31

01F000H

01FFFFH

……

……

……

16

010000H

010FFFH

1500F000H

00FFFFH

……

……

……

0

000000H

000FFFH

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

4. DEVICE OPERATIONSPI ModeStandard SPI
The GD25B16C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the risingedge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPIThe GD25B16C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of thestandard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPIThe GD25B16C supports Quad SPI operation when using the “Quad Output Fast Read” (6BH), ”Quad I/O Fast
Read”(EBH), “Quad I/O Word Fast Read” (E7H) and “Quad Page Program” (32H) commands. These commands allow data
to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the
SI and SO pins become bidirectional I/O pins: IO0 and IO1.

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Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

5. DATA PROTECTION
The GD25B16C provide the following data protection methods:��

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:-Power-Up-Write Disable (WRDI)-Write Status Register (WRSR)-Page Program (PP)-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)��Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory
array that can be read but not change.

��

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down Mode command.
Table1.0 GD25B16C Protected area size (CMP=0)
Status Register Content

Memory Content

BP4

BP3

BP2

BP1

BP0

BlocksAddresses

Density

Portion

X

X

0

0

0

NONE

NONE

NONE

NONE

0

0

0

0

1

31

1F0000H-1FFFFFH

64KB

Upper 1/32

0

0

0

1

0

30 to 31

1E0000H-1FFFFFH

128KB

Upper 1/16

0

0

0

1

1

28 to 31

1C0000H-1FFFFFH

256KB

Upper 1/8

0

0

1

0

0

24 to 31180000H-1FFFFFH

512KB

Upper 1/4

0

0

1

0

1

16 to 31

100000H-1FFFFFH

1M

Upper 1/2

0

1

0

0

1

0

000000H-00FFFFH

64KB

Lower 1/32

0

1

0

1

0

0 to 1000000H-01FFFFH

128KB

Lower 1/16

0

1

0

1

1

0 to 3000000H-03FFFFH

256KB

Lower 1/8

0

1

1

0

0

0 to 7000000H-07FFFFH

512KB

Lower 1/4

0

1

1

0

1

0 to 15000000H-0FFFFFH

1M

Lower 1/2

X

X

1

1

X

0 to 31000000H-1FFFFFH

2M

ALL

1

0

0

0

1

31

1FF000H-1FFFFFH

4KB

Top Block

1

0

0

1

0

31

1FE000H-1FFFFFH

8KB

Top Block

1

0

0

1

1

31

1FC000H-1FFFFFH

16KB

Top Block

1

0

1

0

X

31

1F8000H-1FFFFFH

32KB

Top Block

1

1

0

0

1

0

000000H-000FFFH

4KB

Bottom Block

1

1

0

1

0

0

000000H-001FFFH

8KB

Bottom Block

1

1

0

1

1

0

000000H-003FFFH

16KB

Bottom Block

1

1

1

0

X

0

000000H-007FFFH

32KB

Bottom Block

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Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Table1.1 GD25B16C Protected area size (CMP=1)
Status Register Content

Memory Content

BP4

BP3

BP2

BP1

BP0

BlocksAddresses

Density

Portion

X

X

0

0

0

0 to 31000000H-1FFFFFH

2M

ALL

0

0

0

0

1

0 to 30000000H-1EFFFFH

1984KB

Lower 31/32

0

0

0

1

0

0 to 29000000H-1DFFFFH

1920KB

Lower 15/16

0

0

0

1

1

0 to 27000000H-1BFFFFH

1792KB

Lower 7/8

0

0

1

0

0

0 to 23000000H-17FFFFH

1536KB

Lower 3/4

0

0

1

0

1

0 to 15000000H-0FFFFFH

1M

Lower 1/2

0

1

0

0

1

1 to 31010000H-1FFFFFH

1984KB

Upper 31/32

0

1

0

1

0

2 to 31020000H-1FFFFFH

1920KB

Upper 15/16

0

1

0

1

1

4 to 31040000H-1FFFFFH

1792KB

Upper 7/8

0

1

1

0

0

8 to 31080000H-1FFFFFH

1536KB

Upper 3/4

0

1

1

0

1

16 to 31

100000H-1FFFFFH

1M

Upper 1/2

X

X

1

1

X

NONE

NONE

NONE

NONE

1

0

0

0

1

0 to 31000000H-1FEFFFH

2044KB

Lower 511/512

1

0

0

1

0

0 to 31000000H-1FDFFFH

2040KB

Lower 255/256

1

0

0

1

1

0 to 31000000H-1FBFFFH

2032KB

Lower 127/128

1

0

1

0

X

0 to 31000000H-1F7FFFH

2016KB

Lower 63/64

1

1

0

0

1

0 to 31001000H-1FFFFFH

2044KB

Upper 511/512

1

1

0

1

0

0 to 31002000H-1FFFFFH

2040KB

Upper 255/256

1

1

0

1

1

0 to 31004000H-1FFFFFH

2032KB

Upper 127/128

1

1

1

0

X

0 to 31008000H-1FFFFFH

2016KB

Upper 63/64

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Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

6. STATUS REGISTER
S15

S14

S13

S12

S11

S10

S9

S8

SUS

CMP

HPM

Reserved

Reserved

LB

QE

SRP1

S7

S6

S5

S4

S3

S2

S1

S0

SRP0

BP4

BP3

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program orErase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined inTable1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Chip
Erase (CE) command is executed, only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, power supply lock-down or one time programmableprotection.
SRP1

SRP0

Status Register00

Software Protected

1

0

1

1

Power Supply Lock-Down(1)(2)
One Time Program(2)Description
The Status Register can be written to after a Write Enablecommand, WEL=1.(Default)
Status Register is protected and can not be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and can not be
written to.

NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile read only bit which allows Quad operation. The default value of QE bit is1, and it cannot be changed so that the Quad IO2 and IO3 pins are enabled all the time.
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control
and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers
will become read-only permanently.

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits
to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
HPM bit
The High Performance Flag (HPM) bit indicates the status of High Performance Mode (HPM). When HPM bit sets to 1,
it means the device is in High Performance Mode, when HPM bit sets 0 (default), it means the device is not in High
Performance Mode.
SUS bit
The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down, powerup cycle.

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Dual and Quad Serial Flash

GD25B16C

7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on thefirst rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, mostsignificant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might befollowed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the commandsequence has been shifted in. For the commands of Read, Fast Read, Read Status Register or Release from Deep PowerDown, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction canbe completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return todeselected status.
For the commands of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the commandis rejected, and is not executed. That means CS# must be driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if CS# is driven high at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name

Byte 1

Write Enable
Write Disable
Volatile SR
Write Enable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
Fast Read(7)Continuous Read Mode
Reset
Page Program
Quad Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase

06H
04H
50H

Enable Reset
Reset
Program/Erase
Suspend

Byte 2

05H
35H
01H
03H
0BH
3BH

(S7-S0)(S15-S8)(S7-S0)
A23-A16
A23-A16
A23-A16BBH

A23-A8(2)6BH

A23-A16

EBH
E7H

Byte 3

Byte 4

Byte 5

Byte 6(continuous)(continuous)(S15-S8)
A15-A8
A15-A8
A15-A8

A7-A0
A7-A0
A7-A0

(D7-D0)
dummy
dummy

(Next byte)(D7-D0)(D7-D0)(1)

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A7-A0
M7-M0(2)A15-A8(D7-D0)(1)

A23-A0
M7-M0(4)A23-A0
M7-M0(4)dummy(5)(D7-D0)(3)(continuous)

dummy(6)(D7-D0)(3)(continuous)

A23-A16
A23-A16
A23-A16
A23-A16
A23-A16

A15-A8
A15-A8
A15-A8
A15-A8
A15-A8

A7-A0
A7-A0
A7-A0
A7-A0
A7-A0

A7-A0

(continuous)
dummy(D7-D0)(3)

FFH
02H
32H
20H
52H
D8H
C7/60
H
66H
99H
75H

n-Bytes13

Rev.1.6(D7-D0)(D7-D0)(3)

Next byte(continuous)3.3V Uniform Sector
Dual and Quad Serial Flash
Program/Erase Resume
Deep Power-Down
Release From DeepPower-Down, And
Read Device ID
Release From DeepPower-Down
Manufacturer/
Device ID
Read Unique ID

7AH
B9H
ABH

GD25B16C

dummy

dummy

dummy

(DID7DID0)

90H

dummy

dummy

00H

4BH

00H

00H

00H

(MID7MID0)
dummy(continuous)

ABH(DID7DID0)(continuous)(UID7UID0)

High Performance
Mode
Read Serial Flash
Discoverable
Parameter
Read Identification

A3H

dummy

dummy

dummy

5AH

A23-A16

A15-A8A7-A0

9FH

Erase Security
Registers(8)Program Security
Registers(8)Read Security
Registers(8)44H(MID7M0)
A23-A16(JDID15JDID8)
A15-A8(JDID7JDID0)
A7-A0

42H

A23-A16

A15-A8

A7-A0(D7-D0)(D7-D0)48H

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)dummy(D7-D0)(continuous)

NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8

A6, A4, A2, A0, M6, M4, M2, M0

IO1 = A23, A21, A19, A17, A15, A13, A11, A9

A7, A5, A3, A1, M7, M5, M3, M1

3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8,

A4, A0, M4, M0

IO1 = A21, A17, A13, A9,

A5, A1, M5, M1

IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)

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GD25B16C

IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register0: A23-A16=00H, A15-A8=00H, A7-A0= Byte Address;
Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address.
9. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, W7, x)
10. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0,

M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)

IO1 = (A21, A17, A13, A9, A5, A1,

M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)

IO2 = (A22, A18, A14, A10, A6, A2, M6, M2,

x, x, x, x, MID6, MID2, DID6, DID2, …)

IO3 = (A23, A19, A15, A11, A7, A3, M7, M3,x, x, x, x,

MID7, MID3, DID7, DID3, …)Table of ID Definitions:
GD25B16C

Operation Code

MID7-MID0

ID15-ID8

ID7-ID0

9FH

C8

40

15

90H

C8

14

ABH

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7.1. Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low � sending the Write Enable command � CS# goes high.
Figure 1. Write Enable Sequence Diagram

CS#
SCLK

0

1

2

3

4

5

6

7

CommandSI

06H
High-ZSO

7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:CS# goes low �Sending the Write Disable command �CS# goes high. The WEL bit is reset by following condition: Powerup and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.
Figure 2. Write Disable Sequence Diagram

CS#
SCLK
SI
SO

0

1

2

3

4

5

6

7

Command04H
High-Z

7.3. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The
command code “35H”, the SO will output Status Register bits S15~S8.

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Figure 3. Read Status Register Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

S7~S0 or S15~S8 out
6 5 4 3 2 1 0

CommandSI

05H or 35H

SO

High-ZMSB

7

S7~S0 or S15~S8 out
6 5 4 3 2 1 0

7

MSB

7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S1 and S0 of the Status Register. CS# must be
driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR)
command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE bit will be cleared to 0. As
soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write
Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1.
Figure 4. Write Status Register Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

7

6CommandSI
SO

01H

Status Register in

MSB

5

4

3

2

1

0 15 14 13 12 11 10 98High-Z

7.5. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change thesystem configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles oraffecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register commandmust be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not
set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register
bit values.

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Figure 5. Write Enable for Volatile Status Register Sequence Diagram

CS#
SCLK

0

1

2

3

4

5

7

6

Command(50H)
SI

SO

High-Z7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during
the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a
Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore,
be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 6. Read Data Bytes Sequence Diagram
CS#
SCLK

0

1

SI
SO

2

3

4

5

6

7

8

24-bit address

Command03H
High-Z28 29 30 31 32 33 34 35 36 37 38 39

9 10

23 22 21

3

2

1

0

MSB
MSB

7

6

5

Data Out1
4 3 2 1

Data Out2

07.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency f C, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after eachbyte of data is shifted out.

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Figure 7. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

8

7

9 10

24-bit address

CommandSI

28 29 30 31

23 22 21

0BH

1

2

3

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI

Dummy Byte
7

6

5

4

3

0

1

2

SO

7
MSB

Data Out1
6 5 4 3 2

Data Out2
0 7 6 5MSB

1

7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 8. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure 8. Dual Output Fast Read Sequence Diagram
CS#
SCLK
SI
SO

0

1

2

3

4

5

6

7

8

9 10

Command28 29 30 31

24-bit address

3BH

3

23 22 212

1

0

High-ZCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI

Dummy Clocks

SO

4

2

0

6

4

2

0

6

Data Out1
Data Out2
7 5 3 1 7 5 3 1
MSB
MSB

7

6

7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure 9. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.

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Figure 9. Quad Output Fast Read Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

8

9 10

Command
IO0

24-bit address

6BH

IO1

2

1

0

High-Z
High-Z

IO3

High-Z

SCLK

3

23 22 21

IO2

CS#

28 29 30 31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks

7.10.

IO0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

IO3

7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4

Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched induring the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The commandsequence is shown in followed Figure10. The first byte addressed can be at any location. The address is automaticallyincremented to the next higher address after each byte of data is shifted out.

Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual
I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The commandsequence is shown in followed Figure11. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next
command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Resetcommand can be used to reset (M7-0) before issuing normal command.

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Figure 10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#

0

SCLK

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

6

4

2

0

6

4

2

0

6

4

2

0

6

4

7

5

3

1

7

5

3

1

7

5

3

1

7

5

CommandSI(IO0)BBH

SO(IO1)

A23-16

A15-8

A7-0

CS#
SCLK

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SI(IO0)

6

4

2

0

6

4

2

0

6

4

2

0

6

4

2

0

6

SO(IO1)

7

5

3

1

7

5

3

1

7

5

3

1

7

5

3

1

7

Byte1

Byte2

Byte3

Byte4

Figure 11. Dual I/O Fast Read Sequence Diagram (M7-0= AXH)
CS#
SCLK

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

6

4

2

0

6

4

2

0

6

4

2

0

6

4

5

3

1

7

5

3

1

7

5

3

1

7

5

7

A23-16

A15-8

A7-0

M7-4 Dummy

CS#
SCLK

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SI(IO0)

6

4

2

0

6

4

2

0

6

4

2

0

6

4

2

0

6

SO(IO1)

7

5

3

1

7

5

3

1

7

5

3

1

7

5

3

1

7

Byte1

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Byte2

Byte3

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Rev.1.6

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M7-4 Dummy

7.11.

3.3V Uniform Sector
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GD25B16C

Quad I/O Fast Read (EBH)The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.

Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous ReadMode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other thanAXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous ReadMode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 12. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

0

SCLK

1

2

3

4

5

6

7

Command
IO0

EBH

Dummy

A23-16 A15-8 A7-0 M7-0

Byte1 Byte2

Figure 13. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)
CS#
8

9 10 11 12 13 14 15

0

1

2

3

4

5

6

7

IO0

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

SCLK

A23-16 A15-8 A7-0 M7-0

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each byteof data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast
read command.

Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then thenext Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code.
The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other thanAXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous ReadMode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 14. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

7

0

SCLK

1

2

3

4

5

6

7

Command
IO0

E7H

A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

Figure 15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)
CS#

8

9 10 11 12 13 14 15

0

1

2

3

4

5

6

7

IO0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

7

SCLK

A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

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7.13.

3.3V Uniform Sector
Dual and Quad Serial FlashPage Program (PP) (02H)

GD25B16C

The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted datathat goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low � sending Page Program command � 3-byte address on SI � at least
1 byte data on SI � CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to thedevice, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last databyte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, andBP0) is not executed.

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Figure 16. Page Program Sequence Diagram

CS#
5

6

7

8

9 10

Command24-bit address

02H

3

23 22 21

2

Data Byte 1

1

0 7

6

5

4

3

2

1

2079

SI

28 29 30 31 32 33 34 35 36 37 38 39

2078

4

2076

3

2077

2

2075

1

2074

0

SCLK

1

0

0

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2073

CS#

2072

MSB

7

6

SCLK
SI

Data Byte 2
7

6

5

4

3

2

MSB

7.14.

Data Byte 3

1

0 7

6

5

4

3

2

MSB

Data Byte 256

1

0

5

4

3

2

MSB

Quad Page Program (32H)

The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use
Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes
and at least one data byte on IO pins.
The command sequence is shown in Figure17. If more than 256 bytes are sent to the device, previously latched data
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While theQuad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.

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GD25B16C

Figure 17.Quad Page Program Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

9 10

Command
IO0

28 29 30 31 32 33 34 35 36 37 38 39

24-bit address3

Byte1 Byte2

0 4

0

4

0

4

0

4

0

5

1

5

1

5

1

5

1

IO2

6

2

6

2

6

2

6

2

IO3

7

3

7

3

7

3

7

3

539

540

541

542

543

1

538

2

537

32H

23 22 21
MSB

IO1

SCLK

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

536

CS#

Byte11 Byte12

Byte2534

4

Byte256

IO0

4

IO1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

IO2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

IO3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7.15.

0

4

0

4

0

4

0

4

0

4

0

0

4

0

0

4

0

4

0

4

0

Sector Erase (SE) (20H)

The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN) commandmust previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is enteredby driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low � sending Sector Erase command � 3-byte address on SI �
CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, theStatus Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle iscompleted, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protectedby the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.

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GD25B16C

Figure 18. Sector Erase Sequence Diagram

CS#
SCLK

0

1

3

4

5

6

7

8

Command

SI

7.16.

2

9

29 30 31

24 Bits Address

20H

23 22
MSB

2

1

0

32KB Block Erase (BE) (52H)

The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of thesequence.
The 32KB Block Erase command sequence: CS# goes low � sending 32KB Block Erase command � 3-byte address
on SI � CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of thelast address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# isdriven high, the self-timed Block Erase cycle (whose duration is t BE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle iscompleted, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which isprotected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 19. 32KB Block Erase Sequence Diagram

CS#
SCLK
SI

7.17.

0

1

2

3

4

5

6

7

8

Command52H

929 30 31

24 Bits Address

23 22
MSB

2

1

0

64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of thesequence.
The 64KB Block Erase command sequence: CS# goes low � sending 64KB Block Erase command � 3-byte address
on SI � CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of thelast address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# isdriven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

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3.3V Uniform Sector
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GD25B16C

completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which isprotected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 20. 64KB Block Erase Sequence Diagram

CS#
SCLK

0

1

3

4

5

6

7

8

9

Command

SI

7.18.

2

29 30 31

24 Bits Address

D8H

2

23 22
MSB

1

0

Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving
CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of thesequence.
The Chip Erase command sequence: CS# goes low � sending Chip Erase command � CS# goes high. The
command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has beenlatched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to checkthe value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, andis 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1, and BP0) bits are 0. The Chip Erase (CE)command is ignored if one or more sectors are protected.
Figure 21. Chip Erase Sequence Diagram

CS#
SCLK

0

1

2

4

5

6

7

Command

SI

7.19.

3

60H or C7H

Deep Power-Down (DP) (B9H)

Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects thedevice, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from DeepPower-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby
Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS#
must be driven low for the entire duration of the sequence.

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The Deep Power-Down command sequence: CS# goes low � sending Deep Power-Down command � CS# goeshigh. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to I CC2 and the Deep Power-Down Mode is entered. Any Deep PowerDown (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on thecycle that is in progress.
Figure 22. Deep Power-Down Sequence Diagram

CS#
SCLK

tDP

0 1 2 3 4 5 6 7
CommandSI

Stand-by mode Deep Power-down mode

B9H

7.20. Release from Deep Power-Down or High Performance Mode and Read
Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can beused to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic
identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving theCS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure23. Release from Power-Down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and othercommand are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving theCS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. The Device ID value is listed in
Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed bydriving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the sameas previously described, and shown in Figure24, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and othercommand will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure 23. Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
SCLK
SI

0

1

2

3

4

5

6

7

t RES1

CommandABH
Deep Power-down mode

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3.3V Uniform Sector
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GD25B16C

Figure 24. Release Power-Down/Read Device ID Sequence Diagram
CS#
0

1

2

3

4

5

6

7

8

29 30 31 32 33 34 35 36 37 38

9

SCLK

SI

SO

t RES23 Dummy Bytes

Command

23 22

ABH

2

0

1

MSB

High-Z

MSB

7.21.

7

Device ID
5 4 3 26

10

Deep Power-down Mode Stand-by Mode

Read Manufacture ID/ Device ID (REMS) (90H)

The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID commandthat provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK withmost significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will beread first.
Figure 25. Read Manufacture ID/ Device ID Sequence Diagram

CS#
0

SCLK

2

3

4

5

6

7

8

9 10

28 29 30 31

24-bit address

CommandSI

23 22 21

90H

3

2

High-Z

SO

CS#

1

32

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI
SO

7
MSB

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Manufacturer ID
6 5 4 3 2 1

Device ID
0

7

MSB

30

Rev.1.6

6

5

4

3

2

1

0

1

0

7.22.

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Read Identification (RDID) (9FH)

The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of thedevice in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is notdecoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. Thisis followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being
shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure26. The Read Identification(RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device
is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode andexecute commands.
Figure 26. Read Identification ID Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6

9FH
Command

SI
SO

MSB

CS#

Manufacturer ID
5 4 3 2 10

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SCLK
SI
SO

7

MSB

7.23.

6

5 4 3 2 1
Memory TypeJDID15-JDID8

0

7

MSB

6

5 4 3 2
Capacity
JDID7-JDID01

0High Performance Mode (HPM) (A3H)

The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging ofinternal charge pumps so the voltages required for accessing the flash memory array are readily available. The
command sequence: CS# goes low�Sending A3H command� Sending 3-dummy byte�CS# goes high. See Figure27.
After the HPM command is executed, the device will maintain a slightly higher standby current (Icc8) than standard SPI
operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI standby
current (Icc1). In addition, Power-Down command (B9H) will also release the device from HPM mode back to standard
SPI standby state.

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Figure 27. High Performance Mode Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

8

9

CommandSI

29 30 31t HPM

3 Dummy Bytes

A3H

2

23 22
MSB

1

0

SO
High Performance Mode

7.24.

Continuous Read Mode Reset (CRMR) (FFH)

The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce
command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require theBBH/EBH/E7H command code.
Because the GD25B16C has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25B16C
will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous
Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in
Figure28.
Figure 28. Continuous Read Mode Reset Sequence Diagram
Mode Bit Reset for Quad/Dual I/O

CS#

0

1

2

3

4

5

SCLK

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SI(IO0)

FFH

SO(IO1)

Don`t Care

IO2

Don`t Care

IO3

Don`t Care32

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6

7

7.25.

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Read Unique ID (4BH)

The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The
Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low � sending Read Unique ID command � 3-Byte Address(000000H) �Dummy Byte�128bit Unique ID Out �CS# goes high.
Figure 29. Read Unique ID Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

9 10

28 29 30 31

24-bit address(000000H)
23 22 21
3 2

Command

SI

8

4BH

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI

Dummy Byte

7

6

5

SO

7.26.

4

3

2

1

0

7
MSB

Data Out1
6 5 4 3 2

1

Data Out2
0 7 6 5MSB

Program/Erase Suspend (PES) (75H)

The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H) and
Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page
Program command (02H / 32H) are not allowed during Program/Erase suspend. Program/Erase Suspend is valid only
during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required
to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status Register equal
to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS bit equal to
1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within“tsus” and the SUS bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend
period will reset the device and release the suspend state. The command sequence is show in Figure30.

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Figure 30. Program/Erase Suspend Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

tSUS

CommandSI

75H
High-ZSO

Accept read command

7.27.

Program/Erase Resume (PER) (7AH)

The Program/Erase Resume command must be written to resume the program or sector/block erase operation after
a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS bit equal
to 1 and the WIP bit equal to 0. After issued the SUS bit in the status register will be cleared from 1 to 0 immediately, theWIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page willcomplete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend
is active. The command sequence is show in Figure31.
Figure 31. Program/Erase Resume Sequence Diagram

CS#
SCLK
SI

0

1

2

3

4

5

6

Command
7AH

SO

7.28.

7

Resume Erase/Program

Erase Security Registers (44H)

The GD25B16C provides four 256-byte Security Registers which can be erased and programmed individually. These
registers may be used by the system manufacturers to store security and other important information separately from themain memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low � sending Erase Security Registers command �
CS# goes high. The command sequence is shown in Figure32. CS# must be driven high after the eighth bit of the commandcode has been latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high,the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle isin progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress(WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status
Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will bepermanently locked; the Erase Security Registers command will be ignored.

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Address

A23-A16

A15-A10

A9-A0

Security Registers

00000000

000000

Don’t Care

Figure 32. Erase Security Registers command Sequence Diagram

CS#

0

SCLK

1

2

3

4

5

6

7

8

9

CommandSI

7.29.

29 30 31

24 Bits Address

2

23 22
MSB

44H

1

0

Program Security Registers (42H)

The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256 bytes
Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set
the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers
command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one databyte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated.
While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program Security
Registers command will be ignored.
Address

A23-A16

A15-A8

A7-A0

Security Registers 0

00H

00H

Byte Address

Security Registers 1

00H

01H

Byte Address

Security Registers 2

00H

02H

Byte Address

Security Registers 3

00H

03H

Byte Address

Figure 33. Program Security Registers command Sequence Diagram
CS#
5

6

7

8

9 10

Command24-bit address

3

23 22 21

2

Data Byte 1

1

0 7

6

5

4

3

2

1

2078

42H

2079

SI

28 29 30 31 32 33 34 35 36 37 38 39

2076

4

2077

3

2075

2

1

0

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2072

MSB

2073

1

2074

0

SCLK

SCLK
SI

Data Byte 2
7

6

5

4

MSB

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3

2

Data Byte 3

1

0 7

6

5

4

3

2

MSB

Data Byte 256

1

0

7
MSB

35

Rev.1.6

6

5

4

3

2

0

7.30.

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Read Security Registers (48H)

The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency f C, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after eachbyte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H,
the command is completed by driving CS# high.
Address

A23-A16

A15-A10

A9-A0

Security Registers

00000000

000000Address

Figure 34. Read Security Registers command Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

7

9 10

28 29 30 31

24-bit address

CommandSI

8

23 22 21

48H

3

2

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI
SO

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Dummy Byte
7

6

5

4

3

2

1

0
7
MSB

36

Data Out1
6 5 4 3 2

Rev.1.6

1

Data Out2
0 7 6 5MSB

7.31.

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Enable Reset (66H) and Reset (99H)

If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7M0) and Wrap Bit Setting (W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low � Sending Enable Reset command � CS# goeshigh � CS# goes low � Sending Reset command � CS# goes high. Once the Reset command is accepted by the device,
the device will take approximately tRST/ tRST_E to reset. During this period, no command will be accepted. Data corruption
may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is
accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing theReset command sequence.
Figure 35. Enable Reset and Reset command Sequence Diagram

CS#
0

SCLK

1

2

SI

3

4

5

6

7

0

2

3

4

5

CommandCommand

66H

99H

6

7

High-Z

SO

7.32.

1

Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functionaland feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables canbe interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216.
Figure 36. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

CommandSI

9 10

28 29 30 31

24-bit address

5AH

3

23 22 212

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO

http://www.elm-tech.com

Dummy Byte

7

6

5

4

3

2

1

0

7 6
MSB

37

Rev.1.6

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Table3. Signature and Parameter Identification Data Values
Description
SFDP Signature

Comment
Fixed:50444653H

Data

Data

07:00

53H

53H

01H

15:08

46H

46H

02H

23:16

44H

44H

03H

31:24

50H

50H

Add(H)DW Add(Byte)(Bit)

00H

SFDP Minor Revision Number

Start from 00H

04H

07:00

00H

00H

SFDP Major Revision Number

Start from 01H

05H

15:08

01H

01H

Number of Parameters HeadersStart from 00H

06H

23:16

01H

01H

UnusedContains 0xFFH and can never be

07H

31:24

FFH

FFH

08H

07:00

00H

00H

Start from 0x00H

09H

15:08

00H

00H

Start from 0x01H

0AH

23:16

01H

01H

Parameter Table Length

How many DWORDs in the

0BH

31:24

09H

09H

(in double word)

Parameter table

Parameter Table Pointer (PTP)

First address of JEDEC Flash

0CH

07:00

30H

30H

Parameter table

0DH

15:08

00H

00H

0EH

23:16

00H

00H

0FH

31:24

FFH

FFH

10H

07:00

C8H

C8H

changedID number (JEDEC)

00H: It indicates a JEDEC specified
headerParameter Table Minor Revision
NumberParameter Table Major Revision
Number

UnusedContains 0xFFH and can never bechangedID Number

It is indicates GigaDevice(GigaDevice Manufacturer ID)

manufacturer ID

Parameter Table Minor Revision

Start from 0x00H

11H

15:08

00H

00H

Start from 0x01H

12H

23:16

01H

01H

Parameter Table Length

How many DWORDs in the

13H

31:24

03H

03H

(in double word)

Parameter table

Parameter Table Pointer (PTP)

First address of GigaDevice Flash

14H

07:00

60H

60H

Parameter table

15H

15:08

00H

00H

16H

23:16

00H

00H

17H

31:24

FFH

FFH

NumberParameter Table Major Revision
Number

UnusedContains 0xFFH and can never bechangedhttp://www.elm-tech.com

38

Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Table4. Parameter Table (0): JEDEC Flash Parameter Tables
Description

Comment

Add(H)DW Add(Byte)

(Bit)

Data

Data

00: Reserved; 01: 4KB erase;
Block/Sector Erase Size

10: Reserved;

01:00

01b

02

1b

03

0b

11: not support 4KB erase
Write Granularity

0: 1Byte, 1: 64Byte or larger

Write Enable Instruction

0: Nonvolatile status bit

Requested for Writing to Volatile

1: Volatile status bit

Status Registers(BP status register bit)
0: Use 50H Opcode,

Write Enable Opcode Select for

1: Use 06H Opcode,

Writing to Volatile Status

Note: If target flash status register is

Registers

Nonvolatile, then bits 3 and 4 must

30H

E5H

04

0b

07:05

111b

15:08

20H

16

1b

18:17

00b

19

0b

be set to 00b.
UnusedContains 111b and can never bechanged4KB Erase Opcode

31H(1-1-2) Fast Read

0=Not support, 1=Support

Address Bytes Number used in

00: 3Byte only, 01: 3 or 4Byte,

addressing flash array

10: 4Byte only, 11: Reserved

Double Transfer Rate (DTR)
clocking

0=Not support, 1=Support

32H

20H

F1H

(1-2-2) Fast Read

0=Not support, 1=Support

20

1b(1-4-4) Fast Read

0=Not support, 1=Support

21

1b(1-1-4) Fast Read

0=Not support, 1=Support

22

1b

23

1b

33H

31:24

FFH

37H:34H

31:00

00FFFFFFH

UnusedUnusedFlash Memory Density(1-4-4) Fast Read Number of Wait

0 0000b: Wait states (Dummy

statesClocks) not support(1-4-4) Fast Read Number ofMode Bits

000b:Mode Bits not support
39H(1-1-4) Fast Read Number of Wait

0 0000b: Wait states (Dummy

statesClocks) not support

Mode Bits

44H
07:05

010b

15:08

EBH

20:16

01000b

3AH

000b:Mode Bits not support(1-1-4) Fast Read Opcode

http://www.elm-tech.com

00100b38H(1-4-4) Fast Read Opcode(1-1-4) Fast Read Number of

04:00

3BH

39

Rev.1.6

FFH

EBH

08H
23:21

000b

31:24

6BH

6BH

3.3V Uniform Sector
Dual and Quad Serial Flash
Description

Comment(1-1-2) Fast Read Number of Wait

0 0000b: Wait states (Dummy

statesClocks) not support(1-1-2) Fast Read Numberof Mode Bitsof Wait states

Clocks) not support

(Bit)
04:00

000b: Mode Bits not support
3FH
0=not support

1=support

Unused0=not support

Data

1=support

40H

UnusedData

01000b
08H

07:05

000b

15:08

3BH

20:16

00010b

3EH(1-2-2) Fast Read Opcode(4-4-4) Fast Read

(Byte)

3DH
0 0000b: Wait states (Dummy(2-2-2) Fast Read

DW Add000b: Mode Bits not support(1-2-2) Fast Read Numberof Mode Bits

Add(H)

3CH(1-1-2) Fast Read Opcode(1-2-2) Fast Read Number

GD25B16C

3BH

42H
23:21

010b

31:24

BBH

00

0b

03:01

111b

04

0b

07:05

111b

BBH

EEH

Unused43H:41H

31:08

0xFFH

0xFFH

Unused45H:44H

15:00

0xFFH

0xFFH

20:16

00000b

(2-2-2) Fast Read Number

0 0000b: Wait states (Dummyof Wait states

Clocks) not support(2-2-2) Fast Read Numberof Mode Bits

46H

Unused(4-4-4) Fast Read Number of Wait

0 0000b: Wait states (Dummy

statesClocks) not support(4-4-4) Fast Read Numberof Mode Bits

Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector/block size=2^N bytes
0x00b: this sector type don’t exist

Sector Type 2 erase Opcode
Sector Type 3 Size

Sector/block size=2^N bytes
0x00b: this sector type don’t exist

Sector Type 3 erase Opcode
Sector Type 4 Size

Sector/block size=2^N bytes
0x00b: this sector type don’t exist

Sector Type 4 erase Opcode

http://www.elm-tech.com

47H

31:24

FFH

FFH

49H:48H

15:00

0xFFH

0xFFH

20:16

00000b40

Rev.1.6

00H
23:21

000b

4BH

31:24

FFH

FFH

4CH

07:00

0CH

0CH

4DH

15:08

20H

20H

4EH

23:16

0FH

0FH

4FH

31:24

52H

52H

50H

07:00

10H

10H

51H

15:08

D8H

D8H

52H

23:16

00H

00H

53H

31:24

FFH

FFH

000b: Mode Bits not support

Sector Type 1 erase Opcode
Sector Type 2 Size

000b

4AH

(4-4-4) Fast Read Opcode
Sector Type 1 Size

23:21

000b: Mode Bits not support(2-2-2) Fast Read Opcode

00H

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Table5. Parameter Table (1): GigaDevice Flash Parameter Tables
Description

Comment

Add(H)DW Add(Byte)(Bit)

61H:60H

63H:62H

Data

Data

15:00

3600H

3600H

31:16

2700H

2700H

2000H=2.000V
Vcc Supply Maximum Voltage

2700H=2.700V
3600H=3.600V
1650H=1.650V

Vcc Supply Minimum Voltage

2250H=2.250V
2300H=2.300V
2700H=2.700V

HW Reset# pin

0=not support 1=support

00

0b

HW Hold# pin

0=not support 1=support

01

0b

Deep Power Down Mode

0=not support 1=support

02

1b

SW Reset

0=not support 1=support

03

1b

11:04

99H

SW Reset Opcode

Should be issue Reset Enable(66H)
before Reset cmd.

65H:64H

799CH

Program Suspend/Resume

0=not support 1=support

12

1bErase Suspend/Resume

0=not support 1=support

13

1b

14

1b

15

0b

66H

23:16

FFH

FFH

67H

31:24

64H

64H

0=not support 1=support00

0b0=Volatile

01

0b

09:02

FFH

10

0b

UnusedWrap-Around Read mode

0=not support 1=support

Wrap-Around Read mode Opcode
08H:support 8B wrap-around read

Wrap-Around Read data length

16H:8B&16B
32H:8B&16B&32B
64H:8B&16B&32B&64B

Individual block lockIndividual block lock bit(Volatile/Nonvolatile)

1=Nonvolatile

Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status

0=protect1=unprotect

6BH:68H

Secured OTP

0=not support 1=support

11

1b

Read Lock0=not support 1=support

120bPermanent Lock0=not support 1=support

13

1b

Unused

15:14

11b

Unused

31:16

FFFFH

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41

Rev.1.6

EBFCH

FFFFH

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Vcc(max)
Chip Selection is not allowed

Vcc(min)
Device is fully
accessible

tVSL

VWI

Time

Table6. Power-Up Timing and Write Inhibit Threshold
SymbolParameter

Min

tVSL

VCC(min) To CS# Low

1.8

VWI

Write Inhibit Voltage

1.5

Max

Unit
ms

2.5

V

8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Registercontains 00H (all Status Register bits are 0), except QE bit (S9) is set to 1..

8.3. ABSOLUTE MAXIMUM RATINGS
Parameter

Value

Unit

Ambient Operating Temperature-40 to 85

�Storage Temperature-65 to 150

�Applied Input / Output Voltage-0.6 to VCC+0.4

V

Transient Input / Output Voltage-2.0 to VCC+2.0

V-0.6 to 4.2

V

VCC

Figure 37. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns

Maximum Positive Overshoot Waveform

20ns

20ns

Vss
Vcc + 2.0V

Vss-2.0V
Vcc

20ns

20ns

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42

Rev.1.6

20ns

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

8.4. CAPACITANCE MEASUREMENT CONDITIONS
SymbolParameter

Min

Typ

Max

Unit

Conditions

CIN

Input Capacitance6

pF

VIN=0V

COUT

Output Capacitance8pF

VOUT=0V

CL

Load Capacitance30

Input Rise And Fall time

0.8VCCpF
5ns

Input Pulse Voltage

0.1VCC to 0.8VCC

V

Input Timing Reference Voltage

0.2VCC to 0.7VCC

V

Output Timing Reference Voltage

0.5VCCV

Input timing reference level

0.1VCC

0.7VCC
0.2VCC

Output timing reference level
AC Measurement Level

Note: Input pulse rise and fall time are <5ns

http://www.elm-tech.com

43

Rev.1.6

0.5VCC3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

8.5. DC CHARACTERISTICS(T= -40�~85�, VCC=2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ

Max.

Unit.

ILI

Input Leakage Current

±2

μA

ILO

Output Leakage Current

±2

μA

ICC1

Standby Current

1

5

μA

1

5

μA

15

20

mA

13

18

mA

CS#=VCC,
VIN=VCC or VSS

ICC2Deep Power-Down Current

CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC /0.9VCC
at 120MHz,

ICC3Operating Current (Read)

Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /0.9VCCat 80MHz,
Q=Open(*1,*2,*4 I/O)

ICC4Operating Current (PP)

CS#=VCC

20

mA

ICC5

Operating Current(WRSR)

CS#=VCC

20

mA

ICC6

Operating Current (SE)

CS#=VCC

20

mA

ICC7

Operating Current (BE)

CS#=VCC

20

mA

ICC8

Operating Current (CE)

CS#=VCC

20

mA

ICC9

High Performance Current

1.2

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL =100uA

0.2

V

VOH

Output High Voltage

IOH =-100μA

0.6

VCC-0.2

Note:
1.

Typical values given for TA=25°C.

2.

Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

44

Rev.1.6

V3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

8.6. AC CHARACTERISTICS(T= -40�~85�, VCC=2.7~3.6V, CL=30pf)
SymbolParameter

Min.

Typ.

Max.

Unit.

104

MHz

80

MHz

120

MHz

80

MHz

Serial Clock Frequency For: Dual I/O(BBH),

fC

Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/OWithout High Performance Mode), on 3.0V-3.6V power supply
Serial Clock Frequency For: Dual I/O(BBH),

fC1

Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/OWithout High Performance Mode), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual I/O(BBH),

fC2

Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/OWith High Performance Mode), on 2.7V-3.6V power supply

fR

Serial Clock Frequency For: Read(03H)tCLH

Serial Clock High Time

4

ns

tCLL

Serial Clock Low Time

4

ns

tCLCH

Serial Clock Rise Time (Slew Rate)

0.1

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.1

V/ns

tSLCH

CS# Active Setup Time

5

ns

tCHSH

CS# Active Hold Time

5

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5

ns

tSHSL

CS# High Time�read/write�

20

ns

tSHQZ

Output Disable Time

tCLQX

Output Hold Time

1.2

ns

tDVCH

Data In Setup Time

2

ns

tCHDX

Data In Hold Time

2

ns

tCLQV

Clock Low To Output Valid

7

ns

tDP

CS# High To Deep Power-Down Mode

20

μs

20

μs

tRES1

6

CS# High To Standby Mode Without Electronic Signature
Read

ns

tRES2

CS# High To Standby Mode With Electronic Signature Read

20

μs

tSUS

CS# High To Next Command After Suspend

20

μs

tRS

Latency Between Resume And Next SuspendtRST

CS# High To Next Command After Reset (Except From

100

μs
30

μs

12

ms

Erase)
tRST_ECS# High To Next Command After Reset (From erase)tW

Write Status Register Cycle Time

5

30

ms

tBP1

Byte Program Time( First Byte)

30

50

μs

tBP2

Additional Byte Program Time ( After First Byte)

2.5

12

μs

tPP

Page Programming Time

0.6

2.4

ms

tSE

Sector Erase Time(4K Bytes)

45

300

ms

tBE1

Block Erase Time(32K Bytes)

0.15

1.2

s

http://www.elm-tech.com

45

Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

tBE2

Block Erase Time(64K Bytes)

0.25

2.0

s

tCE

Chip Erase Time(GD25B16C)

7

20

s

Note:
1.

Typical values given for TA=25°C.

2.

Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

46

Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Figure 38. Serial Input Timing
tSHSL

CS#

tCHSL
SCLK

tSLCH

tDVCH

tCHSH

MSB

SO

High-Z

tCHCL

tCLCH

tCHDX

SI

tSHCH

LSB

Figure 39. Output Timing

CS#

tCLH

SCLK
tCLQV

tCLQV

tCLQX

tCLL

tCLQX

SO

LSB

SI
Least significant address bit (LIB) in

Figure 40. Resume to Suspend Timing DiagramCS#

http://www.elm-tech.com

ResumeCommandtRS

47

Rev.1.6

SuspendCommandtSHQZ

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

9. ORDERING INFORMATIONGD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
Temperature Range
I: Industrial (-40� to +85�)
J: Industrial (-40� to +105�)*
E: Industrial (-40� to +125�)*
F: Industrial+ (-40� to +85�)**
3: Automotive (-40� to +85�)*
2: Automotive (-40� to +105�)*
A: Automotive (-40� to +125�)*Package Type
T: SOP8 150mil
S: SOP8 208mil
E: USON8 (3x2mm, 0.45mm thickness)
W: WSON8 (6x5mm)
Generation
C: C Version
Density
16: 16M bit
Series
B: 3V, 4KB Uniform Sector, default x4I/O
Product Family
25: SPI NOR Flash*This datasheet applies to temperature range I: Industrial (-40� to +85�) and F: Industrial+ (-40� to +85�) only.
Please contact GigaDevice sales for extended temperature industrial products and automotive products.
**F grade has implemented additional test flows to ensure higher product quality than I grade.

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48

Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

9.1. Valid Part Numbers

GD25B16C

Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40� to +85�)Product Number

Density

Package Type

GD25B16CTIG
GD25B16CSIG
GD25B16CEIG
GD25B16CWIG

16Mbit
16Mbit
16Mbit
16Mbit

SOP8 150mil
SOP8 208mil
USON8 (3x2mm, 0.45mm thickness)
WSON8 (6x5mm)

Temperature Range F: Industrial+ (-40� to +85�)Product Number

Density

Package Type

GD25B16CTFG
GD25B16CSFG
GD25B16CEFG
GD25B16CWFG

16Mbit
16Mbit
16Mbit
16Mbit

SOP8 150mil
SOP8 208mil
USON8 (3x2mm, 0.45mm thickness)
WSON8 (6x5mm)

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49

Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

10. PACKAGE INFORMATION
10.1.

Package SOP8 150MIL
D
8

5

E

E1

h
L1

L
1

4

“A”

θ

b

A2

A
b

Base Metalc

Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.10

1.25

0.31

0.10

4.80

5.80

3.80

Nom

-

0.15

1.45

0.41

0.20

4.90

6.00

3.90

Max

1.75

0.25

1.55

0.51

0.25

5.00

6.20

4.00

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.

http://www.elm-tech.com

50

Rev.1.6

e

L

L1

0.40
1.27

0.90

1.04

h

θ

0.25

0°

-

-

0.50

8°

3.3V Uniform Sector
Dual and Quad Serial Flash

10.2.

GD25B16C

Package SOP8 208MIL
D
8

5

E

E1

L
1

4

“A”

L1

θ

b

A

A2

b

Base Metalc
Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.05

1.70

0.31

0.15

5.13

7.70

5.18

Nom

-

0.15

1.80

0.41

0.20

5.23

7.90

5.28

Max

2.16

0.25

1.90

0.51

0.25

5.33

8.10

5.38

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.

http://www.elm-tech.com

51

Rev.1.6

e

L

L1

0.50
1.27

0.85

θ
0°

1.31

8°

3.3V Uniform Sector
Dual and Quad Serial Flash

10.3.

GD25B16C

Package USON8 (3x2mm, 0.45mm thickness)c

D

PIN 1#E

A1
A

Top View

Side View

D1

L1

4

5

E1

e

b

1

8

L
Bottom View

Dimensions
Symbol

A

A1

c

b

D

D1

E

E1

Min

0.40

0.00

0.10

0.20

2.90

0.15

1.90

1.55

Nom

0.45

0.02

0.15

0.25

3.00

0.20

2.00

1.60

Max

0.50

0.05

0.20

0.30

3.10

0.25

2.10

1.65

Unit
mm

e

L

L1

0.30
0.50

0.35

0.10

0.40

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity �0.08mm. Package edge tolerance�0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.

http://www.elm-tech.com

52

Rev.1.6

10.4.

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Package WSON8 (6x5mm)c

D
PIN 1#E

A1
A

Top View

Side View

D2
4

5

e

E2

b

1

8

L
Bottom View
Dimensions
Symbol

A

A1

c

b

D

D2

E

E2

Min

0.70

0.00

0.180

0.35

5.90

3.30

4.90

3.90

Nom

0.75

0.02

0.203

0.40

6.00

3.40

5.00

4.00

Max

0.80

0.05

0.250

0.50

6.10

3.50

5.10

4.10

Unit
mm

e

L
0.50

1.27

0.60
0.75

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity �0.08mm. Package edge tolerance�0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These leadshapes are compatible with each other.

http://www.elm-tech.com

53

Rev.1.6

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

11. REVISION HISTORY
Version No
1.0

Description

Page

Date

Initial ReleaseAll

2015-7-23

Modify AC CHARACTERISTICS: tCHCL Min.0.2 V/ns Change to---

0.1 V/ns

1.1

tCLCH Min.0.2 V/ns Change to 0.1 V/ns

2015-11-5

Modify POWER-ON TIMING: tPUW Min 1ms Change to 5ms
Modify Figure 40. Power-on Timing Sequence Diagram
Modify AC CHARACTERISTICS: add tRST_R & tRST_P &1.2--2015-12-18

tRST_E
Modify POWER-ON TIMING: TVSL Min 10us Change to 5ms

1.3

Modify the length the Unique ID from 64 bits to 128 bits

P4

Modify tVSL from 5ms to 1.8ms

P42

Modify VWI from 2.1~2.5V to 1.5~2.5V

P42

Delete DATA RETENTION AND ENDURANCE

P42

Delete Output Short Circuit Current

P42

Modify VCC from -0.6~VCC+0.4 to -0.6~4.2V

P42

Modify Icc9 from 400~800uA to 0.6~1.2mA

P44

Add tRS to the AC Characteristic, of which the min value is 100us

P45

Modify tBE1 max value from 0.3/0.7s to 0.8/1.2s (<50K/50-100K

P45

2018-5-21

cycling)
Modify tBE2 max value from 0.5/0.8s to 1.2/2.0s (<50K/50 -100K

P45

cycling)

1.4

1.5
1.6

Delete tRST_P and tRST_R

P45

Add tRST, of which the max. value is 30us

P45

Add J and E to 7th code of ordering information

P48

Update the description of all packages

P49-51

Modify 4BH command

P33

Modify Ordering Information

P48

Modify tSE max value from 150/300ms to 300ms��

P45

Modify tBE1 max value from 0.8/1.2s to 1.2s��

P45

Modify tBE2 max value from 1.2/2.0s to 2.0s

P46

Add packages of SOP8 150mil,USON8 3x2mm

P50,52

http://www.elm-tech.com

54

Rev.1.6

2018-9-11

2018-12-4
2019-10-10

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B16C

Important NoticeThis document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the propertyof their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product, including,but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company does notassume any liability arising out of the application or use of any Product described in this document. Any information provided
in this document is provided only for reference purposes. It is the responsibility of the user of this document to properly
design, program, and test the functionality and safety of any application made of this information and any resulting product.
Except for customized products which has been expressly identified in the applicable agreement, the Products are designed,
developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The
Products are not designed, intended, or authorized for use as components in systems designed or intended for the operationof weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control instruments,
airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical devices orsystems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management,or other uses where the failure of the device or Product could cause personal injury, death, property or environmental
damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the Products inaccordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and customers shalland hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage, or other liability
arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the Company as well as
it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other liabilities, including claims
for personal injury or death, arising from or related to any Unintended Uses of the Products. Customers shall discard thedevice according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves theright to make changes, corrections, modifications or improvements to this document and the Products andservices described herein at any time, without notice.

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55

Rev.1.6