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Table of Contents

Application Note

ADC Input Circuit Evaluation for C2000 MCUs (using
TINA-TI simulation tool)

ABSTRACTThe analog-to-digital converter (ADC) is a key module used to sense feedback and monitoring signals in areal-time control application. However, without careful design and evaluation of the circuits driving the ADC input,
significant sample-and-hold circuit (S+H) settling errors can occur, resulting in poor performance of the ADC
sensing and thus the system. This application report will identify the resources that can be used to understand
ADC input settling and design appropriate ADC driving circuits as well as how to evaluate these resources in thespecific context of TMS320F2837xD, TMS320F2837xS, TMS320F2838x, TMS320F2807x, TMS320F28004x,
TMS320F28002x, TMS320F28003x, TMS320F280013x, and TMS320F280015x series microcontrollers.
Project collateral and source code discussed in this application report can be downloaded from the following
URL: http://www.ti.com/lit/zip/spract6.

Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Mechanism of ADC Input Settling...................................................................................................................................... 3
1.2 Symptoms of Inadequate Settling...................................................................................................................................... 3
1.3 Resources.......................................................................................................................................................................... 3
2 Input Settling Design Steps................................................................................................................................................... 6
2.1 Select the ADC...................................................................................................................................................................7
2.2 Find the Minimum Op-Amp Bandwidth and RC Filter Ranges...........................................................................................7
2.3 Select an Op-Amp..............................................................................................................................................................9
2.4 Verify the Op-Amp Model................................................................................................................................................... 9
2.5 Build the ADC Input Model.................................................................................................................................................9
2.6 Refine RC Filter Values Via Simulation............................................................................................................................ 12
2.7 Perform Final Simulations................................................................................................................................................ 12
2.8 Input Design Worksheet................................................................................................................................................... 12
3 Example Circuit Design........................................................................................................................................................13
3.1 Select the ADC.................................................................................................................................................................13
3.2 Find the Minimum Op-Amp Bandwidth and RC Filter Ranges.........................................................................................14
3.3 Verify the Op-amp Model................................................................................................................................................. 14
3.4 Build the ADC Input Model...............................................................................................................................................15
3.5 DC Node Analysis............................................................................................................................................................ 16
3.6 Refine RC Filter Values Via Simulation (Part 1)............................................................................................................... 17
3.7 Refine RC Filter Values Via Simulation (Part 2)............................................................................................................... 18
3.8 Refine RC Filter Values Via Simulation (Part 3)............................................................................................................... 20
3.9 Further Refinement.......................................................................................................................................................... 20
3.10 Further Simulations........................................................................................................................................................ 20
3.11 Completed Worksheet.................................................................................................................................................... 21
4 Working With Existing Circuits or Additional Constraints............................................................................................... 22
4.1 Existing Circuits................................................................................................................................................................22
4.2 Pre-Selected Op-Amp...................................................................................................................................................... 23
4.3 Pre-Selected Rs and Cs Values........................................................................................................................................24
5 Summary............................................................................................................................................................................... 25
6 References............................................................................................................................................................................ 25
7 Revision History................................................................................................................................................................... 25

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List of Figures
Figure 1-1. Settling of the ADC S+H Capacitor........................................................................................................................... 3
Figure 2-1. Screenshot of Analog Engineer's Calculator............................................................................................................. 7
Figure 2-2. F28004x ADC Input Model...................................................................................................................................... 10
Figure 2-3. Example Timings for tacq (Piecewise Linear)........................................................................................................... 11
Figure 2-4. Example Timings for tdis (Piecewise Linear)............................................................................................................ 12
Figure 3-1. F280049 Example Analog Engineer's Calculator Output........................................................................................ 14
Figure 3-2. F280049 Example TINA-TI Circuit.......................................................................................................................... 15
Figure 3-3. F280049 Example Tacq Source Timings..................................................................................................................16
Figure 3-4. F280049 Example Tdis Source Timings...................................................................................................................16
Figure 3-5. F280049 Example Transient Analysis Configuration...............................................................................................17
Figure 3-6. F280049 Example Initial Transient Results............................................................................................................. 17
Figure 3-7. Sweep Button.......................................................................................................................................................... 18
Figure 3-8. F280049 Example Sweep Control Dialog............................................................................................................... 18
Figure 3-9. F280049 Example Rs Initial Sweep Results............................................................................................................ 19
Figure 3-10. F280049 Example Rs Fine Sweep Results........................................................................................................... 19
Figure 3-11. F280049 Example Final Transient Results ...........................................................................................................20
Figure 4-1. Example Circuit Utilizing Charge Sharing............................................................................................................... 22
Figure 4-2. Cs Voltage With Rs = 100 Ω.....................................................................................................................................23
Figure 4-3. Cs Voltage With Rs = 1k Ω....................................................................................................................................... 23
Figure 4-4. Analog Engineer's Calculator Output for OPA2320.................................................................................................24

List of Tables
Table 1-1. Series of Devices........................................................................................................................................................ 5
Table 2-1. Calculator Input Type Map.......................................................................................................................................... 8
Table 2-2. ADC Input Settling Design Worksheet...................................................................................................................... 13
Table 3-1. ADC Input Settling Design Worksheet (F280049 Example)......................................................................................21

Trademarks
TINA-TI™ is a trademark of Texas Instruments.
PSPICE® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.

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Introduction

1 Introduction
When designing a system utilizing C2000 real-time MCUs, evaluating the input circuits that are driving the
ADC for proper settling is a necessary step. Inadequate settling can lead to a variety of sampling issues, mostcommonly signal distortion and memory-crosstalk. This application report explores the methodology presented in
the seven-part video series on ADC input settling by TI precision labs: TI Precision Labs - SAR ADC Input Driver
Design in the specific context of the ADCs on C2000 real-time MCUs.

1.1 Mechanism of ADC Input Settling
To convert a sensed analog voltage to a digital conversion result, the ADC first must accurately capture theapplied input voltage into its sample-and-hold circuit (S+H). As shown in Figure 1-1, this entails charging theinternal ADC S+H capacitor (Ch) to within some acceptable tolerance (typically 0.5 LSBs) of the applied voltage
within the configured acquisition window time (also referred to as the S+H time).
Sample and Hold Capacitor Settling During Aquisition

C28x MCU ADC
+5 V
±+

1.8 V

VSH

S1
OPA320

+

+

Ron
500 Ÿ

Rs
50 Ÿ
Cs
220 pFCH
12.5 pF

Vin

N-Bit
Register

+
Comp
N-Bit
CDAC

Sample and hold Voltage

FS

¾ FS
Vin ± 0.5 LSB

½ FS
VSH

¼ FS

Closes at start of acquisition
3.0 V

VREFHI0
Acquisition Time

Figure 1-1. Settling of the ADC S+H Capacitor
Quickly charging Ch to the applied voltage is complicated by the finite bandwidth and settling time of theexternal ADC driver circuit and of the settling time of the internal ADC S+H circuit. In Figure 1-1, the driveris show as an op-amp (OPA320), which has a finite bandwidth, and the driver circuit also has intentionallyplaced source resistance (Rs) and intentionally placed source capacitance (Cs) which have a finite settling time
determined by their RC time constant. Note that other circuit topologies are possible for driving the ADC, andthese circuits may have additional components that need to be modeled to ensure appropriate settling time.
These components could include unintentional parasitics such as the output impedance of a sensor or theeffective source resistance of a voltage divider. Figure 1-1 also shows that the ADC has an internal parasitic
switch resistance (Ron). This, along with Ch, provides an additional RC time constant that limits settling speed.

1.2 Symptoms of Inadequate Settling
Once a voltage has been captured into the S+H capacitor, the ADC will translate this voltage into a digitalconversion result during the conversion phase. The CPU can then use this result to control or monitor thesystem. However, if the captured voltage does not accurately represent the applied voltage due to settling error,
the final conversion result will have errors even if the ADC conversion process is perfect.
These settling errors will manifest differently depending on whether the ADC is sampling the same channel
repeatedly or scanning through multiple channels in a sequence. The settling errors will also manifest differently
depending on the starting voltage on the S+H capacitor at the beginning of the acquisition phase. Some ADC
architectural implementations will have a starting S+H voltage close to the previously sampled voltage whileother architectures will usually start the acquisition phase with a discharged S+H capacitor.

1.3 Resources
The following tools and materials are useful for ADC driver circuit design and evaluation for input settling.

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1.3.1 TINA-TI SPICE-Based Analog Simulation Program
TI provides the TINA-TI application to TI customers to allow easy SPICE-based simulation of circuits utilizing
TI products. Because this application report uses PSpice for TI instead of TINA-TI to evaluate circuit settling
performance, it is not necessary to ensure TINA-TI is downloaded and installed before proceeding. However, the
TINA-TI application and additional resources are still made available.
Link to Tool Folder: TINA-TI™
1.3.2 PSPICE for TI Design and Simulation Tool
TI provides the PSpice for TI application to TI customers to allow easy SPICE-based simulation of circuits
utilizing TI products. This application report utilizes this program to evaluate circuit settling performance. Ensure
this application is downloaded and installed before proceeding.
Link to Tool Folder: PSPICE® for TI
Link to PSpice for TI Training Series: Explore PSpice for TI
Link to TI E2E Support Forum: Welcome to TI E2E Design Support Forums
Link to Cadence PSpice for TI Forum: Welcome to PSpice Forum
1.3.3 TI Precision Labs - SAR ADC Input Driver Design Series
TI Precision Labs has provided an excellent eight-part video series that demonstrates how to design the input
drivers for a SAR ADC. Reviewing this material will help to further understand the high-speed op-amp based
signal conditioning design process and options.
Link to Video Training Series: TI Precision Labs - SAR ADC Input Driver Design
1.3.4 Analog Engineer's Calculator
The analog engineer's calculator tool provides a variety of very useful GUI-based calculation tabs to assist with
common analog circuit design tasks. The high-speed op-amp design methodology takes advantage of the Data
Converters ➔ ADC SAR Drive calculator.
Link to Tool Folder: Analog Engineer's Calculator
1.3.5 Related Application Reports
TI provides several application reports that pertain to the design and evaluation of ADC input circuits on C2000
real-time MCU devices. These application reports are listed along with brief descriptions.

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Application Report Title

Schematic Capture and Simulation Tool

PurposeADC Input Circuit Evaluation for C2000
MCUs (TINA-TI)

TINA-TIADC Input Circuit Evaluation for C2000
MCUs (PSpice for TI)

PSpice for TI

Describes how to design and evaluate a
traditional high-speed ADC driving circuit.
Input circuit includes an op-amp. Appropriate
when sampling a high bandwidth signal near
the maximum sample rate of the ADC.

Charge-Sharing Driving Circuits for C2000
ADCs (TINA-TI)

TINA-TI

Charge-Sharing Driving Circuits for C2000
ADCs (PSpice for TI)

PSpice for TI

Methods for Mitigating ADC Memory CrossTalk

TINA-TIADC Input Circuit Evaluation for C2000 MCUs (using TINA-TI simulation tool)

Describes how to design and evaluate acharge-sharing ADC driving circuit. Input
circuit may or may not include an op-amp.
Appropriate when sampling a signal with asufficiently low bandwidth and sample rate.
Describes strategies to mitigate memory
cross-talk error when the input circuitdesign does not achieve adequate settling.
Applicable under special circumstances.

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Introduction

1.3.6 TINA-TI ADC Input Models
This application report is bundled with pre-generated ADC input models for several families of devices. The
families of devices are listed alongside the ADC input models associated with each family and a brief descriptionof each ADC input model.
For C2000 devices that are not listed in Table 1-1, the input models can still be used as long as the signal
mode matches (use a single-ended model for single-ended ADC operation or use a differential model fordifferential ADC operation). The Ron and Ch values also need to be updated to match the values specified in thedevice-specific data manual.
Table 1-1. Series of Devices
Series of Devices

ADC Input Model

Description

TMS320F2807x

F2807x_Ext

F2807x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

TMS320F2837xD, TMS320F2837xS

F2837x_Ext_12BSE

F2837x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

F2837x_Ext_16BDE

F2837x ADC input model
External reference of 3.0 V
16-bit resolution
Differential input mode

F2838x_Ext_12BSE

F2838x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

F2838x_Ext_16BSE

F2838x ADC input model
External reference of 3.0 V
16-bit resolution
Single-ended input mode

F2838x_Ext_16BDE

F2838x ADC input model
External reference of 3.0 V
16-bit resolution
Differential input mode

F28002x_Ext

F28002x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

F28002x_Int25

F28002x ADC input model
External reference of 2.5 V
12-bit resolution
Single-ended input mode

F28002x_Int33

F28002x ADC input model
External reference of 3.3 V
12-bit resolution
Single-ended input mode

F28004x_Ext

F28004x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

F28004x_Int25

F28004x ADC input modelInternal reference of 2.5 V
12-bit resolution
Single-ended input mode

F28004x_Int33

F28004x ADC input modelInternal reference of 3.3 V
12-bit resolution
Single-ended input mode

TMS320F2838xD, TMS320F2838xS

TMS320F28002x

TMS320F28004x

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Table 1-1. Series of Devices (continued)
Series of Devices

ADC Input Model

Description

TMS320F28003x

F28003x_Ext

F28003x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

F28003x_Int25

F28003x ADC input modelInternal reference of 2.5 V
12-bit resolution
Single-ended input mode

F28003x_Int33

F28003x ADC input modelInternal reference of 3.3 V
12-bit resolution
Single-ended input mode

F280013x_Ext

F280013x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

F280013x_Int25

F280013x ADC input modelInternal reference of 2.5 V
12-bit resolution
Single-ended input mode

F280013x_Int33

F280013x ADC input modelInternal reference of 3.3 V
12-bit resolution
Single-ended input mode

F280015x_Ext

F280015x ADC input model
External reference of 3.0 V
12-bit resolution
Single-ended input mode

F280015x_Int25

F280015x ADC input modelInternal reference of 2.5 V
12-bit resolution
Single-ended input mode

F280015x_Int33

F280015x ADC input modelInternal reference of 3.3 V
12-bit resolution
Single-ended input mode

TMS320F280013x

TMS320F280015x

CAUTION
While the ADC input models for multiple C2000 devices are bundled with this application report,
input model component values should always first be verified with the device-specific data manual
before proceeding. For more information, see Section 2.5.

2 Input Settling Design Steps
The TI Precision Labs - SAR ADC Input Driver Design methodology to design an ideal ADC input driver can be
broken into the steps below. Subsequent sections will discuss how these steps can be applied to C2000 ADCs.
1.
2.
3.
4.
5.
6.
7.

Select the ADC.
Find the minimum op-amp bandwidth and RC filter ranges.
Select an op-amp.
Verify the op-amp model.
Build the ADC input model.
Refine RC filter values via simulation.
Perform final simulations

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Input Settling Design Steps

2.1 Select the ADC
It is assumed that you have already selected a C28x based microcontroller with one or more integrated ADCs
modules. The C28x product search can be used to select an MCU: C2000 real-time control MCU - Products andthe C2000 peripheral guide enumerates the differences between peripherals on different devices (including theADC): C2000 Real-Time Control MCU Peripherals Reference Guide.
Once a C2000 device has been selected, you should locate the following information in the device-specific data
manual before proceeding.
Data Manual Information

Location

Comments

Minimum sample window duration"ADC Operating Conditions" table in the"ADC Electrical Data and Timing" section

Some devices support multiple resolutions
modes and signaling modes; ensure thatthe parameter correspond to the mode you
intend to use.

ADC input model"Input Model Parameters" table in the "ADC
Input Model" section

Some devices support multiple resolutions
modes and signaling modes; ensure that themodel correspond to the mode you intend touse.

Specific parasitic capacitance for selected
ADC pin"Per-Channel Parasitic Capacitance" table inthe "ADC Input Model" section

If channel assignment is not yet known, use
the value for ADCIN15

ADC timings"ADC Timings" table in the "ADC Timing
Diagrams" section

Some devices support multiple resolutions
modes and signaling modes; ensure that thetimings correspond to the mode you intend
to use. You will also need to know yourintended CPU clock (SYSCLK) and ADC
clock (ADCCLK) rate. If not yet known, use
the maximum ADCCLK value given in the"ADC Operating Conditions" table along withthe maximum SYSCLK for the device.

2.2 Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
Once you have located the detailed ADC information in the device-specific data manual, you can use the Analog
Engineer's Calculator to determine the minimum required driving op-amp bandwidth as well as the potential
ranges of the external source resistor and external source capacitor to put on the ADC input.
Open the Analog Engineer's Calculator application and select the calculator Data Converters -> ADC SAR Drive
calculator. This will give a calculator window similar to that shown in Figure 2-1.

Figure 2-1. Screenshot of Analog Engineer's Calculator

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Once the correct calculator is open, enter the input information.
2.2.1 Select TypeC2000 ADCs can be configured as either single-ended input mode or differential input mode depending on theparticular device. The calculator allows several input mode types. Table 2-1 maps the C2000 input modes tocalculator selection types.
Table 2-1. Calculator Input Type Map
C2000 Signal Mode

Calculator Input Type Selection

Single-ended"Single Ended #1"

Differential"Differential"

2.2.2 Resolution
Enter the resolution of the ADC mode to be used in bits. For C2000 ADCs this will usually be 12-bits or 16-bits.
Note
Usually the actual resolution of the ADC will be selected. However, in cases where an ADC channel
does not need to utilize the full resolution of the ADC, a lower value can be entered to relax the input
settling design requirements.
For example:
Resolution = 12 bits, Csh = 12.5 pF, Full-scale range = 3.0 V, Acquisition duration = 100 ns• Full resolution of 12 bits requires minimum op-amp bandwidth of 37 MHz and settling to better than
0.366 mV
• Reduced resolution of 10 bits (approximately 0.1% settling) requires a minimum op-amp bandwidthof 28 MHz and settling to better than 1.465 mV
2.2.3 CshEnter the value of the ADC S+H capacitor. This can be found as the parameter "Ch" in the Input Model
Parameters table in the device-specific data manual. Different resolutions and reference modes may havedifferent input model parameters, so ensure that the parameter is selected that corresponds to the intended ADC
use mode.
2.2.4 Full-Scale Range
Enter the voltage corresponding to the full-scale range of the ADC. When using external reference mode, thiscorresponds to the voltage supplied on the VREFHI pin of the ADC, usually 2.5 V or 3.0 V. When using internalreference mode (on supported devices), this corresponds to the voltage range of the selected reference mode
(2.5 V or 3.3 V).
2.2.5 Acquisition TimeEnter the target ADC acquisition window time. For the lowest ADC conversion latency (corresponding to the
maximum ADC sample rate), select the minimum value of the parameter "Sample window duration" in the ADC
Operating Conditions table in the device-specific data manual.

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Input Settling Design Steps

Note
Selecting a target S+H time larger than the ADC minimum acquisition time can ease the input settlingdesign requirements for the input driving op-amp.
For example:
Resolution = 12- bits, Csh = 12.5 pF, Full-scale range = 3.0 V• Acquisition time = 75 ns requires a driving op-amp with around 50 MHz of bandwidth• Acquisition time = 150 ns requires a driving op-amp with around 25 MHz of bandwidth• Acquisition time = 750 ns requires a driving op-amp with around 5 MHz of bandwidth
These decisions can be made on a per-channel basis since the C2000 ADC wrapper allows per-SoC
configuration of the S+H time (by using the ACQPS setting in the SoC control register).
2.2.6 Outputs
Once all inputs have been provided to the calculator, record the outputs for later analysis•••

Rfilt and Cfilt output ranges will be explored via TINA-TI simulation in order to determine an optimal drivercircuit
The max error target output corresponds to 1/2 LSBs at the specified resolution. The final TINA-TI simulation
will be considered successful if the settling is within this bound.
The gain bandwidth output will be used in the next step to select an appropriate op-amp. The selected
op-amp should have a unity-gain bandwidth of this value or better for best settling performance.

2.2.7 Math Behind the Calculator
Additional information about analytically determining the required op-amp bandwidth and ranges of Rfilt and Cfilt
can be found in the final TI Precision Labs video in the SAR ADC Input Driver Design series: Math Behind the
R-C Component Selection.

2.3 Select an Op-Amp
An appropriate op-amp next needs to be selected for the ADC driver circuit. This op-amp needs to meet theminimum unity gain bandwidth reported by the Analog Engineer's calculator.
Additional instructions for selecting the op-amp are given in the TI Precision Labs video: Selecting and Verifying
the Driver Amplifier.
Note
If selecting an op-amp to meet the specified requirements is proving difficult, remember that both thesettling resolution and the target acquisition time can be relaxed (if the application requirements allow)
to relax the driving op-amp requirements. These can both be adjusted on a per-channel basis to allow
critical ADC inputs to have optimal performance while axillary ADC inputs can be allowed to haverelaxed performance.

2.4 Verify the Op-Amp Model
Next, it is necessary to obtain the TINA-TI model for the op-amp selected in the previous step.
The TI Precision Labs video Selecting and Verifying the Driver Amplifier provides detailed instructions on how
to obtain the TINA-TI model for the selected op-amp as well as how to verify the model against the information
provided in the device-specific data manual.

2.5 Build the ADC Input Model
To simulate and refine the ADC input driver circuit in TINA-TI, it is first necessary to build a TINA-TI input
model for the ADC. The TI Precision Labs video Building the SAR ADC Input Model outlines how to perform
this process based on the information provided in the device-specific data manual for an ADC device. Thisapplication report is bundled with pre-generated ADC input models for TMS320F2837xD, TMS320F2837xS,
TMS320F2838x, TMS320F2807x, TMS320F28004x, and TMS320F28002x family devices, so manual creationof the models is not necessary. However, the video does show how to configure your TINA-TI simulation
parameters (via the slides titled "Optimizing Simulation Results").
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CAUTION
The first time a settling simulation is run, do not skip the instructions to configure the simulation
parameters in the Building the SAR ADC Input Model video. These instructions can be found in the"Optimizing Simulation Results" section.

Figure 2-2. F28004x ADC Input ModelAn example of one of the provided ADC input models can be seen in Figure 2-2. The following sections briefly
describe the primary functions of each model component.
2.5.1 Vin
Vin is the applied voltage that is used to charge the S+H capacitor. While any input can be simulated, applying
the full-scale input voltage provides the worst-case DC settling conditions because the S+H capacitor always
starts discharged in this model.
2.5.2 Voa , Voa_SS, and Verror
TINA-TI op-amp models incorporate various non-idealities, which results in the DC steady state output of the
op-amp at Voa not exactly matching Vin. The steady state output at Voa can be simulated and entered into Voa_ss
such that Verror is an accurate representation of only the input settling error.
2.5.3 Rs, Cs, and Vcont
Rs and Cs are the source resistance and source capacitance. These values correspond to Rfilt and Cfilt in
the TI Precision Labs training terminology. Rs resistance is controlled by the control voltage Vcont. Rs is a
voltage-controlled resistor with gain of 1 (1 V = 1 Ω, 10 V = 10 Ω, and so forth) instead of a simple resistor toallow parameter sweeping when there are two Rs resistors in the differential models.
2.5.4 Ch, Ron, and Cp
Component values for the ADC input model.

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Ch, the S+H capacitor, corresponds to Csh in the TI Precision Labs training terminology while Ron, the S+H
switch on resistance, corresponds to Rsh.
Cp is the pin-specific input capacitance. This is not modeled in the TI Precision Labs training, but can be
optionally added to the simulation to improve simulation accuracy. This is particularly helpful for pins that are
multiplexed with VDAC (alternate DAC voltage reference pin) that have a value of Cp, which is greater than 100
pF on most devices.
Pins that are multiplexed with the buffered DAC output on F2837x and F2807x devices have a parasitic 50k
Ω pull-down resistor present on these pins. It is recommended to add this resistor to the model (not shown in
Figure 2-2) to better represent behavior of these pins.
CAUTION
While the ADC input models for multiple C2000 devices are bundled with this application report,
input model component values should always first be verified with the device-specific data manual
before proceeding. Values for Ch and Roncan be obtained from the Input Model Parameters table inthe device-specific data manual while values for Cp can be obtained from the Per-Channel Parasitic
Capacitance table. In any cases where the device-specific data manual values disagree with thevalues in this document or in the provided models, the device-specific data manual values should
always be considered the correct values.
2.5.5 S+H Switch, Discharge Switch, tacq, and tdis
Switch "S+H" controls when the S+H capacitor, Ch, is being charged by the driving circuit. The timings for thisswitch are controlled by tacq. Sample tacq timing configurations for a 75 ns acquisition window are shown in
Figure 2-3.
Switch "Discharge" controls when the S+H capacitor, Ch, is being reset by being discharged to ground. The
timings for this switch are controlled by tdis. Sample tdis timing configurations for a 1 μs trigger period are show in
Figure 2-4.
When neither tacq or tdis are active, the value of the S+H capacitor is held at its final settled values.
Note that the timings are configured to emulate conversions triggered at a set 1 MHz frequency instead of
back-to-back continuous conversions. This more closely emulates the typical C2000 ADC use case of being
periodically triggered by the ePWM module. The triggering rate can be modified to match the actual applicationePWM trigger rate by modifying the period of the tacq and tdis timing sources. Do, however, ensure that thetrigger rate is slower than the total S+H plus acquisition time for the ADC conversion. The ADC conversion time
can be found in the device-specific data manual table "ADC Timings".

Figure 2-3. Example Timings for tacq (Piecewise Linear)
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Figure 2-4. Example Timings for tdis (Piecewise Linear)

2.6 Refine RC Filter Values Via Simulation
Once the ADC input model has been combined with the op-amp simulation model, simulation can be used to
select the best values of Rs and Cs. In-depth instructions for performing the component refinement simulation
can be found in TI Precision labs video Refine the Rfilt and Cfilt Values on ADC Drive or by following the input
circuit design example in Section 3.
Once optimal values of Rs and Cs have been determined, a final simulation should be performed using theclosest available standard component values. This establishes the final settling error, which can be compared tothe settling error target obtained from the Analog Engineer's Calculator.
If the settling error does not meet the target, additional iteration is required that will entail evaluating a different
op-amp, evaluating different Rs and Cs values, or relaxing the S+H time or settling resolution targets.

2.7 Perform Final Simulations
Additional simulations to verify the robustness of the design can also optionally be performed. These include:••••

Simulate with a longer S+H duration to ensure that input is consistently settling
Observe settling at the op-amp's output node. This node should also settled to within 1/2 LSBs (or theselected settling target) at the end of the acquisition period
Observe settling over multiple cycles
Perform settling simulations with an AC input

Information on performing these simulations can be found in the TI Precision Labs video Final SAR ADC Drive
Simulations.

2.8 Input Design Worksheet
Table 2-2 lists the required inputs needed to evaluate an ADC input driving circuit and provides a place tosummarize the outputs. Completing this worksheet for each unique circuit in your real-time control application isrecommended to ensure good settling performance. For some circuits, it may be desireable to use the alternate
design methodology presented in the application report Charge-Sharing Driving Circuits for C2000 ADCs (using
TINA-TI simulation tool). That report also provides a worksheet that can be evaluated using the alternate design
methodology.

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Table 2-2. ADC Input Settling Design Worksheet
SymbolDescription

Vfs

Full scale voltage range

In external reference mode, this is the voltage supplied to the VREFHI pin(usually 3.0V or 2.5 V)
In internal reference mode, this is the effective input range based on the selectedreference mode (usually 3.3 V or 2.5 V)

N

Target settling resolution(bits)

Usually the same as the resolution of the ADC
Lower resolution can be targeted to relax the input design requirements

Verrmax

Maximum error target

Vfs / 2N+1
Obtain using Analog Engineer's Calculator: ADC SAR Drivetsh

S+H time

Enter target S+H time if known
Longer S+H times will result in less stringent BW requirements for the driving
op-amp.
Can be solved for given a pre-determined op-amp selection or a pre-determined
RS and CS

Ron

ADC switch resistance

Provided in the Input Model Parameters table in the device-specific data manual
TI precision labs training refers to this as "Rsh"

Ch

ADC S+H capacitance

Provided in the Input Model Parameters table in the device-specific data manual
TI precision labs training refers to this as "Csh"Cp

ADC pin parasitic
capaciance

Provided in the Per-Channel Parasitic Capacitance table in the device-specificdata manual

CS (range)

Range of source
capacitanceObtain using Analog Engineer's Calculator: ADC SAR Drive.
TI precision labs training refers to this as "Cfilt"

RS (range)

Range of source
resistanceObtain using Analog Engineer's Calculator: ADC SAR Drive.
TI precision labs training refers to this as "Rfilt"

BWOPA

ADC driver op-amp
minimum bandwidth

Obtain using Analog Engineer's Calculator: ADC SAR Drive.

Op-ampSelected Op-amp partnumberRecord selected op-amp here

Voa_ssSteady state op-amp
output voltage

Generated from DC nodal analysis of the Voa node
Copy to Voa_ss before proceeding with other simulations

CS (final)

Final source capacitance

Final selected CS from simulation.
TI precision labs training refers to this as "Cfilt"

RS (final)

Final source resistance

Final selected RS from simulation.
TI precision labs training refers to this as "Rfilt"

BWRsCsFilter bandwidth from CS
and RS

1 / (2π·CS·RS )Actual settling error

Ensure Verr < Verrmax
Othwerwise, additional iteration on selection of CS , RS , or the driving amplifier isneeded.

Verr

Value

Comments

Note
For proper settling, the filter bandwidth will be necessarily higher
than the ½ the sampling frequency, thus the combination of CS and
RS generally will not function as an anti-aliasing filter.

3 Example Circuit Design
The following sections work through and discuss designing an example C2000 circuit for input settling.

3.1 Select the ADC
This example assumes an F280049 device in external reference mode (VREFHI = 3.0 V) using channel A0.
Triggering will occur at 1 MHz. This ADC supports 12-bit single-ended sampling only.
From the TMS320F28004xMicrocontrollers Data Manual, the following key values are obtained:••••

Minimum sample window duration = 75 ns
Ch = 12.5 pF
Ron = 500 Ω
Cp = 12.7 pF

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ADC conversion time = 210 ns (teoc in the ADC Timings table from the TMS320F28004xMicrocontrollers Data
Manual) = 21 SYSCLK cycles, SYSCLK = 100 MHz)

3.2 Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
Figure 3-1 shows the inputs and outputs to the Analog Engineer's Calculator for this example. From this, we
obtain the following key values:••••

Cs = 240 pF (120 pF to 360 pF range, if needed)
Rs range = 17 Ω to 138 Ω
Op-amp minimum bandwidth = 37 MHz
Settling error target (1/2 LSBs) = 366 µV

Note that, in conjunction with the op-amp selection step, it was found that slightly relaxing the S+H durationfrom the ADC minimum of 75 ns to 100 ns reduced the required op-amp bandwidth from 50 MHz to 37 MHz.
This allowed for an op-amp selection that better met the project constraints (OPA2350) while still meeting theapplication requirements for sample latency.

Figure 3-1. F280049 Example Analog Engineer's Calculator Output

3.3 Verify the Op-amp Model
The latest OPA2350 model was obtained from ti.com.

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3.4 Build the ADC Input Model
The OPA2350 model was combined with the provided F28004x_Ext.TSC ADC input model. In addition to setting
the driving amplifier to OPA2350, the following were performed on the TINA-TI file to prepare for simulation:
•
•
•
•
•
•
•
•
•

Op-amp power supplies set to an appropriate voltage (5.0 V and ground)
Vin set to full-scale voltage (3.0 V)
Cs and Cp initial value set to full-scale voltage (3.0 V)
Voa_ss set to the voltage obtained from DC nodal voltage analysis (demonstrated in the next section)
Tacq and Tdis source period set to 1000 ns (1 MHz trigger frequency)
Tacq source S+H time set to 100 ns
Cp, Ron, and Ch values set based on values obtained from the device-specific data manualCs set to the nominal value provided by calculator
Rs set to a value in the calculator provided range (by setting Vcont)

The initial circuit is shown in Figure 3-2 and the timings for tacq and tdis are shown in Figure 3-3 and Figure 3-4.

Figure 3-2. F280049 Example TINA-TI Circuit

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Figure 3-3. F280049 Example Tacq Source Timings

Figure 3-4. F280049 Example Tdis Source Timings

3.5 DC Node Analysis
To finalize the TINA-TI input model, a DC node analysis is performed to determine the steady-state output value
for Voa given the specific op-amp being evaluated ( Analysis →DC Analysis → Calculated nodal voltages). For
OPA2350 in this circuit, this gives:•

Voa = 3.000014 V

Which is then copied to the Voa_ss voltage source.
CAUTION
Ensure that the simulation parameters are configured per the "Optimizing Simulation Results" slides
from the Building the SAR ADC Input Model video.

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3.6 Refine RC Filter Values Via Simulation (Part 1)
Now that the circuit is setup for simulation, the first step is to run a basic transient analysis to ensure everythingis functioning and to check the initial settling. The transient analysis can be run via the TINA-TI menu options:
Analysis → Transient...
The settling should be captured after allowing the circuit to stabilize for a couple sampling cycles, so a time
period of 2.5 μs to 5.5 μs is selected as shown in Figure 3-5. This allows capture of the full 3rd and 4th sampling
cycles (each cycle is 1us since the trigger frequency is 1 MHz).

Figure 3-5. F280049 Example Transient Analysis Configuration
Figure 3-6 shows the output waveforms from the transient simulation after separating the outputs (View →Separate outputs). The error voltage scale has also been adjusted to show a range of +10 mV to -10 mV(double-click on Verror, then enter -10m in the "Lower limit" field and 10m in the "Upper limit" field, then click"OK").
From this output, it is clear that:•••

Discharge and acquisition times are functioning as expected
The transients on Voa and Vpin are of reasonable magnitude (less than 100 mV, so the signal settling will beconsidered a small signal event)
Verror is settling to about 14 µV, which is well within the error target of 366 µV

Figure 3-6. F280049 Example Initial Transient Results
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3.7 Refine RC Filter Values Via Simulation (Part 2)
Now that the basic simulation has shown that the simulation is fundamentally working, sweeps can be performed
to refine the Rs component selection.
To perform a sweep, click on the sweep button, then click on the Vcont voltage source (which controls the valueof Rs).

Figure 3-7. Sweep Button
This will bring up a dialog box. Select the "..." button next to the Voltage [V] parameter and configure the sweep
to select 5 points on a linear scale from 13 Ω to 138 Ω as shown in Figure 3-8.

Figure 3-8. F280049 Example Sweep Control Dialog
The output of the transient simulation with a sweep of Rs is shown in Figure 3-9. Note that the outputs haveagain been separated, and all outputs other than Vpin and Verror have been deleted. Verror range has been set to-50 mV to +50 mV and the waveform has been limited to better observe the settling.
From this output, it can be concluded:••

18

Higher resistance values in the Rs range do not provide quick enough settling. For instance, 106 Ω only
settles to 6.6 mV in the allocated S+H time while the settling target is 366 µV
A good range for further investigation would be 10 Ω to 50 Ω

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Figure 3-9. F280049 Example Rs Initial Sweep Results
Figure 3-10 shows the results of a sweep of Rs from 10 Ω to 50 Ω. From this set of waveforms, it appears thatvalues of Rs from 10 Ω to 30 Ω all provide settling that greatly exceeds the design target. A final value of Rs wasthus selected as 27 Ω.

Figure 3-10. F280049 Example Rs Fine Sweep Results

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3.8 Refine RC Filter Values Via Simulation (Part 3)
With the final Rs and Cs values determined, a final transient simulation can be performed to validate thecomponent selections. The results of this final simulation can be seen in Figure 3-11. From these results, itappears that the settling crosses the settling target of 366 µV somewhere around 67 ns and the final settling at
100 ns is around 17 µV. The final application circuit should have excellent ADC input settling.

Figure 3-11. F280049 Example Final Transient Results

3.9 Further Refinement
Overall, it appears that this design has quite a bit of settling margin. If further optimization is desired, thedesigner could explore using an op-amp with slightly lower bandwidth. Alternately, the simulation supports using
a S+H window that is shorter than 100 ns, if desired.
Another area refinement is to resolve a circuit with intentionally higher Rs and Cs. As designed, the low-passfilter bandwidth of the Rs and Cs circuit is about 2.5 MHz, so this circuit provides some rejection of highfrequency noise. By intentionally increasing Rs and Cs, the filter bandwidth can be lowered, resulting in additional
noise rejection. However, note that the Rs and Cs circuit can generally not provide a true anti-aliasing filter, as
this would necessarily result in a settling time constant that would be much too large to allow proper settling. If atrue anti-aliasing filter is needed, this should be built as a separate filter stage before the ADC drive stage.
CAUTION
Even if the simulations indicate that the input could settle faster than the minimum acquisition
window specified in the device-specific data manual, do not select an acquisition window that
violates the device-specific data manual minimum acquisition window time.

3.10 Further Simulations
As indicated in Section 2.7, once the final components are selected, it is possible to perform additional
simulations to further validate the design. This design was validated over multiple cycles and with increased
S+H duration (not shown). No issues were identified in these additional simulations.

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3.11 Completed Worksheet
Table 3-1 shows the completed worksheet for the F280049 with OPA2350 example.
Table 3-1. ADC Input Settling Design Worksheet (F280049 Example)
SymbolDescription

Value

Comments

Vfs

Full scale voltage range

3.0 V

In external reference mode, this is the voltage supplied to the VREFHI pin(usually 3.0 V or 2.5 V)
In internal reference mode, this is the effective input range based on the selectedreference mode (usually 3.3 V or 2.5 V)

N

Target settling resolution(bits)

12 bits

Usually the same as the resolution of the ADC
Lower resolution can be targeted to relax the input design requirements

Verrmax

Maximum error target

366 uVVfs / 2N+1
Obtain using Analog Engineer's Calculator: ADC SAR Drivetsh

S+H time

100 nsEnter target S+H time if known
Longer S+H times will result in less stringent BW requirements for the driving
op-amp.
Can be solved for given a pre-determined op-amp selection or a pre-determined
RS and CS

Ron

ADC switch resistance500 Ω

Provided in the data manual table "Input Model Parameters"
TI precision labs training refers to this as "Rsh"

Ch

ADC S+H capacitance

12.5 pF

Provided in the data manual table "Input Model Parameters"
TI precision labs training refers to this as "Csh"Cp

ADC pin parasitic
capacitance12.7 pF

Provided in the data manual table "Per-Channel Parasitic Capacitance"

CS (range)

Range of source
capacitance

240 pF(120pF to
360pF)

Obtain using Analog Engineer's Calculator: ADC SAR Drive.
TI precision labs training refers to this as "Cfilt"

RS (range)

Range of source
resistance

17 to 138 Ω

Obtain using Analog Engineer's Calculator: ADC SAR Drive.
TI precision labs training refers to this as "Rfilt"

BWOPA

ADC driver op-amp
minimum bandwidth

37 MHzObtain using Analog Engineer's Calculator: ADC SAR Drive.

Op-ampSelected Op-amp partnumber

OPA2350

Record selected op-amp here

Voa_ssSteady state op-amp
output voltage

3.000014 V

Generated from DC nodal analysis of the Voa node
Copy to Voa_ss before proceeding with other simulations

CS (final)

Final source capacitance

240 pF

Final selected CS from simulation.
TI precision labs training refers to this as "Cfilt"

RS (final)

Final source resistance27 Ω

Final selected RS from simulation.
TI precision labs training refers to this as "Rfilt"

BWRsCsFilter bandwidth from CS
and RS

2.5 MHz

Actual settling error

17 μV

Verr

1 / (2π·CS·RS )NoteFor proper settling, the filter bandwidth will be necessarily higher
than the ½ the sampling frequency, thus the combination of CS and
RS generally will not function as an anti-aliasing filter.
Ensure Verr < Verrmax
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4 Working With Existing Circuits or Additional Constraints
The TI Precisions Labs design methodology explored in this report start by assuming a S+H window is known
and that the op-amp and Rs and Cs have not yet been determined. The following sections provide some
guidance if one or more of these components has already been selected or otherwise needs to be constrained.

4.1 Existing Circuits
Fully determined input driving circuits can of course be simulated to check their settling using the provided ADC
input models and simulation methodology.
Note that it is especially important to verify the performance over many sampling cycles for existing circuits thatwere not designed using the TI Precision Labs methodology. One common case where this is important is when
the input was designed using a "charge-sharing" design methodology.
4.1.1 Brief Overview of Charge Sharing
Normally, as the size of Cs increases, the settling time will also increase. It is generally not advantageous tomake Cs very large. However, if Cs becomes sufficiently large, it can fully provide all the charge needed to drive
Ch to within the settling error target, regardless of the value of Rs.
The external source still needs to recharge Cs through Rs in the time between samples, otherwise each sample
will slowly deplete the voltage on Cs. This results in a sample-rate limitation based on the magnitude of the Rs
resistance.
For 1/2 LSBs settling, the critical value of Cs occurs at Cs = 2(N+1) x Ch.
4.1.2 Charge Sharing Example
In the example circuit in Figure 4-1, Cs has been set to approximately 2(N+1) x Ch and the sample trigger rate is
set to 100 kHz.

Figure 4-1. Example Circuit Utilizing Charge Sharing

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Working With Existing Circuits or Additional Constraints

Figure 4-2 shows the pin transient over many sampling cycles when Rs is 100 Ω. It can be seen that the voltage
on the pin (which is the voltage directly on Cs) recovers to within 1/2 LSBs in the time between conversions.
This results in good ADC input settling using a very short S+H window as long as the sample-rate remains at or
below 100 ksps.

Figure 4-2. Cs Voltage With Rs = 100 Ω
Now consider the results in Figure 4-3. Rs has been set to 1k Ω. In this case, the voltage on Cs is slowly
depleted sample-by-sample until an equilibrium is reached. At equilibrium, the pin voltage has an error of about
3.5 mV. Even though Ch will quickly match the Cs voltage during the S+H phase, the voltage on Cs has asignificant error.

Figure 4-3. Cs Voltage With Rs = 1k Ω
To resolve this error, either Rs would need to be decreased or the sample rate would have to be reduced.
This example underscores the importance of simulating circuits with large Cs or Rs over many cycles.

4.2 Pre-Selected Op-Amp
If the op-amp has already been selected for the input driver, the easiest method for proceeding with the design isto iterate the acquisition time setting in the Analog Engineer's Calculator until the necessary bandwidth matches
the bandwidth of the pre-selected op-amp. The designer can then record the Cs and Rs component ranges andproceed with the design per the existing methodology (assuming that the predicted S+H meets the application's
latency or sample rate requirements).
4.2.1 Pre-Selected Op-Amp Example
The designer wants to use OPA2320 as the driving op-amp for an ADC input (perhaps there is a spare channel
from an OPA2320 performing another function on the PCB). OPA2320 has a bandwidth of 20 MHz and the ADC
in question has a Ch value of 12.5 pF. By iterating the acquisition window input of the calculator, the solution
shown in Figure 4-4is found and thus a S+H window of 185 ns can be targeted.

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Figure 4-4. Analog Engineer's Calculator Output for OPA2320

4.3 Pre-Selected Rs and Cs Values
If both external source components have been pre-selected, a target acquisition time can be determined bysimulating the circuit with an ideal source or with an op-amp with very high bandwidth. This initial target
acquisition time can then be used to provide some guidance in op-amp selection, and then design refinement
can proceed as normal.
4.3.1 Analytical Solution for ADC Acquisition Time
A quick method for estimating the ADC S+H time given selections of Rs and Cs (along with the input model
parameters from the device-specific data manual) is to use the formulas shown in Equation 1 and Equation 2:

TRS

R on C h

RS CS

Cp

§
·
2N
In ¨
¸ In C S© t arget settlingerror ¹
acquisition time TkkCp / Ch(1)

4.3.2 Example Analytical Solution for ADC Acquisition Time
•
•
•
•
•
24

n = 12 bits
Ron = 500 Ω
Ch = 12.5 pF
Cp = 12.7 pF
Target settling error = 1/2 LSBs
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Summary

Rs = 180 Ω
Cs = 150pF

T

180 :

500 : 12.5 pF 180 : 150 pF 12.7 pF§ 150 pF 12.7 pF ·§ 4069 LSBs ·In ¨¸¸ In ¨
12.5 pF© 0.5 LSBs ¹©
¹
acquisition time 37.8 ns u 6.4 242 ns

k37.8 ns

6.4 time cons tan ts(2)

5 Summary
Input settling is an important design consideration for ADC driving circuits. Without proper evaluation, distortionand memory cross-talk errors could occur, resulting in degraded sensing performance and accuracy.
By using the excellent resources provided by in the TI Precision Labs - SAR ADC Input Driver Design videoseries, the Analog Engineer's Calculator, and the guidance in this application report, input settling can besystematically evaluated to ensure that ADC driving circuits have appropriate settling performance.

6 References••••

TI Precision Labs - SAR ADC Input Driver Design
Analog Engineer's Calculator
TINA-TI
Texas Instruments: TMS320F28004xMicrocontrollers Data Manual

7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2020) to Revision A (March 2023)
Page• Updated the Abstract of this document.............................................................................................................. 1• Updated the numbering format for tables, figures and cross-references throughout the document.................. 3• Updated Section 1.3.5........................................................................................................................................ 4• Updated Section 1.3.6........................................................................................................................................ 5

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