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Table of Contents

Application Note

UCC28950/UCC28951 600-W, Phase-Shifted, Full-Bridge
Application Note

Michael O'Loughlin
ABSTRACTIn high-power server applications to meet high-efficiency goals of greater than 92% some power-supply
designers have found it easier to use a phase-shifted full-bridge (PSFB) converter (Figure 2-1). This is because
the PSFB converter can obtain zero-voltage switching on the primary side of the converter reducing switchinglosses and increasing overall system efficiency. The purpose of this application note is to review the design of a
600-W, phase-shifted, full-bridge converter , using the UCC28950 or the newer UCC28951 PSFB controller. The
design specifications for this design are presented in Table 1-1. Hopefully this information will aid other power
supply designers in their efforts to design an efficient phase-shifted, full-bridge converter. Also note there is an
Excel Design Tool that goes along with this application note as well to aid in the design process.

Table of Contents
1 Design Specifications.............................................................................................................................................................2
2 Functional Schematic.............................................................................................................................................................2
3 Power Budget..........................................................................................................................................................................3
4 Transformer Calculations (T1)...............................................................................................................................................3
5 QA, QB, QC, QD FET Selection..............................................................................................................................................6
6 Selecting LS ............................................................................................................................................................................7
7 Output Inductor Selection (LOUT).......................................................................................................................................... 7
8 Output Capacitance (COUT).................................................................................................................................................... 8
9 Select FETs QE and QF.......................................................................................................................................................... 9
10 Input Capacitance (CIN)...................................................................................................................................................... 11
11 Setting Up the Current Sense (CS) Network (CT, RS, RRE, DA) ...................................................................................... 12
12 Voltage Loop and Slope Compensation........................................................................................................................... 13
13 Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS).................................................................................16
14 Turning SR FETs-off Under Light Load Conditions.........................................................................................................21
15 600 W FSFB Detailed Schematic and Test Data...............................................................................................................21
16 References.......................................................................................................................................................................... 25
17 Revision History................................................................................................................................................................. 25

List of Figures
Figure 2-1. UCC28950/UCC28951 Phase-Shifted, Full-Bridge Functional Schematic............................................................... 2
Figure 4-1. T1 Primary and QE and QF FET Currents................................................................................................................ 4
Figure 9-1. Vg vs. Qg for QE and QF FETs................................................................................................................................ 10
Figure 12-1. Loop Gain and Loop Phase...................................................................................................................................15
Figure 13-1. tABSET to Achieve Valley Switching at Light Loads................................................................................................ 18
Figure 13-2. tCDSET to Achieve Valley Switching at Light Loads................................................................................................ 19
Figure 15-1. Daughter Board Schematic................................................................................................................................... 21
Figure 15-2. Power Stage Schematic........................................................................................................................................ 22
Figure 15-3. 600-W Phase Shifted Full Bridge Efficiency.......................................................................................................... 23
Figure 15-4. Q4g Q4d, VIN = 390 V, IOUT = 5 A.......................................................................................................................... 23
Figure 15-5. Q3g Q3d, VIN = 390 V, IOUT = 5 A.......................................................................................................................... 23
Figure 15-6. Q4g Q4d, VIN = 390 V, IOUT = 10 A........................................................................................................................ 24
Figure 15-7. Q3g Q3d, VIN = 390 V, IOUT = 10 A........................................................................................................................ 24
Figure 15-8. Q4g Q4d, VIN = 390 V, IOUT = 25 A........................................................................................................................ 24
Figure 15-9. Q3g Q3d, VIN = 390 V, IOUT = 25 A........................................................................................................................ 24

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Trademarks

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Figure 15-10. Q4g Q4d, VIN = 390 V, IOUT = 25 A...................................................................................................................... 25
Figure 15-11. Q3g Q3d, VIN = 390 V, IOUT = 25 A.......................................................................................................................25

List of Tables
Table 1-1. Design Specifications..................................................................................................................................................2

Trademarks
All trademarks are the property of their respective owners.

1 Design Specifications
Table 1-1. Design Specifications
Description

Min

Typ

Max

Input Voltage

370 V (VINMIN)

390 V (VIN)410 V (VINMAX)

Output Voltage (VOUT)

11.4 V

12 V (VOUT)

50 V

Continuous Output Power (POUT)

600 W

Allowable VOUT Transient

600 mV ( VTRAN)

Full Load Efficiency

93% (η)94%

Inductor (LOUT) Switching Frequency

200 kHz (fS)

2 Functional Schematic
CT
+
OUTA
VIN

RRE

CIN

QA

QC

DB

OUTC

QBd

QDd
LS

DA

OUTB

OUTD

DC

RS

_

QD

QB

T1

CS

LOUT
+

CBP1
VREF
VOUT

OUTE

1uF
RB

RI

RA

CZ

RD
825k
RDELCDRDELAB

OUTF

RT
RSUM

VOUT
_

CBP2
1uF

CS

RLF1
22 ohm

2 EA+
3 EA-

OUTA 22OUTA

4 COMP
5 SS/ENOUTB 21
OUTC 20OUTB
OUTC

6 DELABOUTD 19

7 DELCD
8 DELEFOUTE 18
OUTF 17

9 TMINSYNC 16

10 RT

RTMIN
RDELEFCOUT

GND 24
VDD 23

1 VREF

RC

CSS

QF

UCC28950/UCC28951

CP

RF

QE

12V Bias
RLF2
1k

OUTD
OUTE
VREF

OUTF
SYNC

RCA1 RDA1

RE

CS 15

11 RSUM

ADEL 1412 DCMADELEF 13

CLF
330pF
RCA2

RDA2

RG

VREF

Figure 2-1. UCC28950/UCC28951 Phase-Shifted, Full-Bridge Functional Schematic

2

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Power Budget

3 Power Budget
To reach the efficiency goal in this PSFB design, careful consideration needs to be taken in selecting electricalcomponents. The devices need to be selected based voltage rating, current rating and power dissipation. The
initial step in this design process is to set a power budget (PBUDGET) which the total losses of the electricalcomponents selected for the design cannot exceed.
PBUDGET = POUT ×

1−η≈ 45.2 W
η(1)

4 Transformer Calculations (T1)

The PSFB uses a transformer to deliver energy from the primary to the secondary. The voltage is stepped up or
down through the transformers turns ratio (a1).
NV

a1 = NP = V IN

(2)

VRDSON = 0.3 V(3)DMAX = 70 %

(4)

S

OUT

Estimated FET voltage drop (VRDSON):

Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will givesome room for dropout if a PFC front end is used.

a1 =VINMIN − 2 × VRDSON × DMAX
≈ 21
VOUT + VRDSON(5)

Calculated typical duty cycle (DTYP) based on average input voltage.
DTYP =

VOUT + VRDSON × a1
≈ 0.66
VIN − 2 × VRDSON(6)

To keep the RMS current in the output capacitance to a minimum LOUT will be selected so the inductor ripple
current (ΔILOUT) will be 20% of the DC output current. ΔILOUT is needed to calculate transformer peak and RMS
currents
P
× 0.2
ΔILOUT = OUT= 10 A
V(7)

OUT

Care needs to be taken in selecting a transformer with the correct amount of magnetizing inductance (LMAG).
The following equations calculate the minimum magnetizing inductance of the primary of the transformer (T1) toensure the converter operates in peak-current mode control. If LMAG is too small the magnetizing current could
cause the converter to operate in voltage mode control instead of peak-current mode control. This is because
the magnetizing current is too large, it will act as a PWM ramp swamping out the current sense signal across RS.
V

× 1 − DTYP
≈ 2.76 mH
LOUT × 0.5 × fsa1

LMAG ≥ ΔIIN

(8)

Figure 4-1 shows T1 primary current (IPRIMARY) and synchronous rectifiers currents, (QE (IQE) and QF (IQF)), withrespect to the synchronous rectifier gate drive currents. Note that IQE and IQF are also T1’s secondary winding
currents as well. Variable D is the converters duty cycle.

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Transformer Calculations (T1)

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IPP
IMP2

IMP2 ≈ IPP - ΔILOUT/(2×a1)

IMS2

IMS2 ≈ IPS - ΔILOUT/(2)IMP

IPRIMARY

0A

D

On
QEg
Off
On
QFg
Off
IQE

0A
IQF

IPS
IMS

0A
-ΔILOUT/2

Figure 4-1. T1 Primary and QE and QF FET Currents
Calculate T1 secondary RMS current (ISRMS):P

IPS = VOUT +OUTPIMS = VOUT −4OUTΔILOUT≈ 55 A
2(9)

ΔILOUT≈ 45 A
2(10)

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Transformer Calculations (T1)

IMS2 = IPS −ΔILOUT≈ 50 A
4(11)

Secondary RMS current (ISRMS1) when energy is being delivered to the secondary:DMAX
2

ISRMS1 =I −I
IPS × IMS + PS 3 MS

2

≈ 29.6 A(12)Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are bothon.
1 − DMAX
2

ISRMS2 =I −I
IPS × IMS2 + PS 3MS2

2

≈ 20.3 A(13)

Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during freewheeling
period, please refer to Figure 4-1.
ΔILOUT
2

ISRMS3 =1 − DMAX≈ 1.1 A
2×3

(14)

Total secondary RMS current (ISRMS):

ISRMS = ISRMS12 + ISRMS22 + ISRMS32 ≈ 36.0 A(15)

Calculate T1 Primary RMS Current (IPRMS):
V
× DMAX∆ ILMAG = INMIN≈ 0.47 A
LMAG × f S
P

IPP = V OUT+OUT × ηP

IMP = V OUT−OUT × η(16)

ΔILOUT 12
a1 + ∆ ILMAG ≈ 3.3 A(17)

ΔILOUT 12
a1 + ∆ ILMAG ≈ 2.8 A(18)

T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary.
IPRMS1 =I −I
DMAX IPP × IMP + PP 3 MP2

≈ 2.5 A

(19)

T1 Primary RMS (IPRMS2) current when the converter is free wheeling.
IMP2 = IPP −IPRMS2 =ΔILOUT 1
a1 ≈ 3.0 A
2(20)

1 − DMAX IPP × IMP2 +Total T1 primary RMS current (IPRMS)

IPP − IMP2
3

2

≈ 1.7 A

IPRMS = IPRMS12 + IPRMS22 ≈ 3.1 A

(21)

(22)

The transformer calculations were given to Vitec a magnetic manufacturer to design a custom transformer tomeet our design requirements. The transformer they designed for this application is part number 75PR8107 andthe transformer has the following specifications.

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QA, QB, QC, QD FET Selection

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a1 = 21(23)

LMAG = 2.8 mH(24)

LLK = 4 uH

(25)

DCRP = 0.215 Ω(26)

DCRS = 0.58 Ω(27)

Measured leakage inductance on the Primary:Transformer Primary DC resistance:

Transformer Secondary DC resistance:

Estimated transform losses (PT1) are twice the copper loss.
Note
This is just an estimate and the total losses can vary based on magnetic design.
PT1 ≈ 2 × IPRMS2 × DCRP + 2 × ISRMS2 × DCRS ≈ 7.0 W(28)

PBUDGET = PBUDGET − PT1 ≈ 38.1 W(29)

Calculate remaining power budget:

5 QA, QB, QC, QD FET Selection
The FETs to drive the HBridge (QA..QD) need to selected based on maximum drain to source voltage(VdsQA_max) and peak drain to source current (IdsQA_max).
VdsQA_max ≥ VINMAX = 410 V(30)

IdsQA_max ≥ IPP = 3.3 A(31)

The FETs then need to be selected based on efficiency goals and FET power dissipation (PQA) and is a trial anerror process. Equations 32 through 38 are used to estimate PQA based on FET data sheet parameters. To meet
our efficiency goals, we selected a 20 A, 650 V, CoolMOS FETs from Infineon that had an estimated PQA of 2.1
W and would enable us to hit our efficiency goals.
In this design, to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon werechosen for QA..QD.
FET drain to source on resistance:
Rds on QA = 0.220 Ω(32)

COSS_QA_SPEC = 780 pF(33)

VdsQA = 25V(34)

FET Specified COSS:

Voltage across drain-to-source (VdsQA) where COSS was measured, data sheet parameter:

Calculate average Coss [2]:6

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Selecting LS
VdsQA

COSS_QA_AVG = COSS_QA_SPEC V≈ 193 pF
INMAX

(35)

QAg = 15 nC(36)

Vg = 12 V(37)

PQA = IPRMS2 × Rds on QA + 2 × QAg × Vg × fs
2 ≈ 2.1 W(38)

PBUDGET = PBUDGET − 4 × PQA ≈ 29.7 W(39)

QA FET gate charge:

Voltage applied to FET gate to activate FET:

Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg):

Recalculate power budget:

6 Selecting LS

Calculating the shim inductor (LS) is based on the amount of energy required to achieve zero voltage switching.
This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node. The
following equation selects LS to achieve Zero Voltage Switching (ZVS) at 100% load down to 50% load based on
the primary FET’s average total COSS at the switch node.
Note
There might be more parasitic capacitance than was estimated at the switch node and LS might haveto be adjusted based on the actual parasitic capacitance in the final design.

LS ≥ 2 × COSS_QA_AVG

VINMAX2

IPP ΔILOUT 2
2 − 2 × a1

− LLK ≈ 26 uH(40)

For this design Vitec Electronics Corporation designed a customer LS, part number 60PR964. 60PR964 had a
DC resistance (DCRLS) of 27 mΩ.
DCRLS = 27 mΩ(41)

PLS = 2 × IPRMS2 × DCRLS ≈ 0.5 W(42)

Estimate LS power loss (PLS) and readjust remaining power budget:PBUDGET = PBUDGET − PLS ≈ 29.2 W(43)

7 Output Inductor Selection (LOUT)
To keep the RMS current in the output capacitance to a minimum LOUT will be designed for and inductor ripple
current (∆ILOUT) will be 20% of the DC output current.
P
× 0.2
× 0.2
ΔILOUT = OUT= 600W≈ 10 A
V
12V

(44)

OUT

V
× 1 − DTYP
LOUT = OUT≈ 2 uH
ΔI
×f
LOUT

(45)

s

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Output Capacitance (COUT)

ILOUT_RMS =www.ti.com

IOUT

2

+

ΔILOUT 2= 50.3 A
3(46)

The LOUT inductor requirements to meet these design specifications was given to Vitec Electronics Corp andthey design a custom inductor for this design that met are design requirements, part number 75PR108. The
75PR108 had a DC resistance (DCRLOUT) of 750 µΩ
DCRLOUT = 750 uΩ

(47)

PLOUT = 2 × ILOUT_RMS2 × DCRLOUT ≈ 3.8 W(48)

Estimate output inductor losses (PLOUT) and recalculate power budget. Note PLOUT is an estimate of the inductor
losses and was estimated to twice the copper loss. Note this may vary based on magnetic manufactures. It isadvisable to double check the magnetic loss with the magnetic manufacture.

PBUDGET = PBUDGET − PLOUT ≈ 25.4 W(49)

8 Output Capacitance (COUT)

The output capacitor is being selected based on holdup time (tHU) and load transient requirements.
tHU is the time it takes LOUT to change 90% of its full load current:
LOUT × POUT × 0.9
VOUT
tHU =
= 7.5 μs
VOUT

(50)

During load transients most of the current will immediately go through the capacitors equivalent series resistance(ESRCOUT). The following equations are used to select ESRCOUT and COUT based on a 90% load step in current.
The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the output capacitance (COUT) is
selected for 10% of VTRAN.
V

× 0.9

ESRCOUT ≤ PTRAN× 0.9 = 12 mΩ

(51)

OUT
VOUT

POUT × 0.9 × tHU
V
COUT ≥ V OUT≈ 5.6 mF
TRAN × 0.1(52)

Before selecting the output capacitance it is also required to calculate the output capacitor RMS current(ICOUT_RMS).
ICOUT_RMS =ΔILOUT≈ 5.8 A
3

(53)

To meet our design requirements five 1500-µF, aluminum electrolytic capacitors were chosen for the designfrom United Chemi-Con, part number EKY-160ELL152MJ30S. These capacitors had an ESR of 31 mΩ. The fivecapacitors when used in series will have an equivalent ESR of 6.2 mOhm which meets are design requirements.
Number of output capacitors:
n=5

(54)

COUT = 1500uF × n ≈ 7500 uF(55)

Total output capacitance:

Effective output capacitance ESR:8

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Select FETs QE and QF

ESRCOUT = 31mΩn = 6.2 mΩ

(56)

PCOUT = ICOUT_RMS2 × ESRCOUT ≈ 0.21 W(57)

PBUDGET = PBUDGET − PCOUT ≈ 25.2 W(58)

Calculate output capacitor loss (PCOUT):

Recalculate remaining Power Budget:

9 Select FETs QE and QF

The synchronous FETs are chosen based on current and voltage ratings; as well as, power dissipation to meetthe designs efficiency goals. This can be a trial an error process. We selected an evaluated a 75-V, 120-A FETs,from Fairchild, part number FDP032N08 to see if they could be used for synchronous FETs QE and QF to hit ourefficiency goals. After estimating the total FET losses and power budget it was determined that these FETs could
be used in this design.
QEg = 152nC(59)

Rds on QE = 3.2 mΩ

(60)

Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), anddrain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage inthe design (VdsQE) that will be applied to the FET in the application.
Voltage across FET QE and QF when they are off:
VdsQE =

2 × VINMAX
≈ 39V
a1

(61)

Voltage where FET COSS is specified and tested in the FET data sheet:
Vds_spec = 25 V

(62)

COSS_SPEC = 1810 pF(63)

Specified output capacitance from FET data sheet:

Average QE and QF COSS [2]:VdsQE

COSS_QE_AVG = COSS_SPEC V≈ 1.6 nF
ds_spec(64)

IQE_RMS = ISRMS = 36.0 A(65)

QE and QF RMS current:

To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the gatecharge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate charge at theend of the miller plateau (QEMILLER_MAX) for the given VDS.

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QEMILLER_MIN ≈ 52 nC

QEMILLER_Max ≈ 100 nC
Figure 9-1. Vg vs. Qg for QE and QF FETs
Maximum gate charge at the end of the miller plateau:
QEMILLER_MAX ≈ 100 nC(66)

QEMILLER_MIN ≈ 52 nC(67)

Minimum gate charge at the beginning of the miller plateau:

Note

The FETs in this design were driven with UCC27324 setup to drive 4-A (IP) of gate drive current.
IP ≈ 4A(68)

Estimated FET Vds rise and fall time:tr ≈ tf = 100nCI− 52nC = 48nC
4A ≈ 24 ns
P
2

(69)

2

Estimate QE and QF FET Losses (PQE):
P

f

f

f

PQE = IQE_RMS2 × Rds on QE + VOUT × VdsQE tr + tf 2s + 2 × COSS_QE_AVG × VdsQE2 2s + 2 × QgQE × VgQE 2s

PQE ≈ 9.3 W

OUT

(70)
(71)

Recalculate the power budget and check remaining power budget to hit efficency goal.
PBUDGET = PBUDGET − 2 × PQE ≈ 6.5 W
10

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Input Capacitance (CIN)

10 Input Capacitance (CIN)
This design was being fed by a PFC pre-regulator and the input capacitor (CIN) will need to be selected basedon holdup requirements; as well as, ripple current and voltage requirements.
Note
The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).
Calculate tank frequency:
fR =12π LS × 2 × COSS_QA_AVG(73)

Estimated delay time:

tDELAY = f 2× 4 ≈ 314ns(74)

1− tDELAY × fs = 94 %DCLAMP = fs

(75)

R

Effective duty cycle clamp (DCLAMP):

VDROP is the minimum input voltage where the converter can still maintain output regulation. The converter’s
input voltage would only drop down this low during a brownout or line-drop condition if this converter was
following a PFC pre-regulator.
VDROP =

2 × DCLAMP × VRDSON + a1 × VOUT + VRDSONDCLAMP

CIN was calculated based on one line cycle of holdup:
CIN ≥1
2 × POUT × 60Hz
VIN2 − VDROP2= 276.2 V≈ 364 uF

(76)

(77)

Calculate high frequency input capacitor RMS current (ICINRMS).
P

ICINRMS = IPRMS12 − V OUT× a1
INMIN

2

= 1.8 A(78)

To meet the input capacitance and RMS current requirements for this design we chose a 330-µF capacitor from
Panasonic part number EETHC2W331EA.
CIN = 330 uF(79)

ESRCIN = 0.150 Ω(80)

PCIN = ICINRMS2 × ESRCIN = 0.5 W(81)This capacitor had a high frequency (ESRCIN) of 150 mΩ this was measured with an impedance analyzer at both
120 and 200 kHz.

Estimate CIN power dissipation (PCIN):

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Setting Up the Current Sense (CS) Network (CT, RS, RRE, DA)

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PBUDGET = PBUDGET − PCIN ≈ 6.0 W(82)

There is roughly 6.0 W left in the power budget left for the current sensing network, and biasing the control
device and all resistors supporting the control device.

11 Setting Up the Current Sense (CS) Network (CT, RS, RRE, DA)
The current sense transforer (CT) chosen for this design had a turn’s ratio (a2) of 100:1. This transformer was
selected to attenenuate the T1's primary current for current sensing to reduce power disipation in the current
sense resistor (RS) improving system efficency.
Ia2 = IP = 100

(83)

S

Calculate nominal peak current (IP1) at VINMIN:
Peak primary current:
VINMAX × DMAXPOUT
ΔILOUT 1
IP1 = VOUT×η +2
a1 + LMAG × 2 × f s ≈ 3.3 A(84)

The voltage where peak current limit will trip.
VP = 2V(85)

Calculate current sense resistor (RS) and leave 200 mV for slope compensation:
V − 0.2V

RS = I P

PEAK × 1.1
a2≈ 49.9 Ω(86)

Select a standard resistor for RS:
RS = 48.7 Ω(87)

Estimate power loss (PRS)for RS:PRS =IPRMS1 2
× RS ≈ 0.03 W
a2

(88)

Calculate maximum reverse voltage (VDA) on DA:D

VDA = VP × 1 −CLAMP
D

CLAMP

≈ 29.8 V(89)

Estimate DA power loss (PDA):

P
× 0.6VPDA = V OUT × η × a2 ≈ 0.01 W
INMIN

(90)

Calculate RS reset resistor RRE:

Resistor RRE is used to reset the current sense transformer CT.
RRE = 100 × RS = 4.87 kΩ

(91)Resistor RLF and capacitor CLF form a low pass filter for the current sense signal (Pin 15). For this design wechose the following values. This filter has a low frequency pole (fLFP) at 482 kHz. This should work for mostapplications but maybe adjusted to suit individual layouts and EMI present in the design.

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Voltage Loop and Slope Compensation

RLF = 1 kΩ(92)

CLF = 330 pF(93)

f LFP = 2πf × R1 × C
LF

LF= 482 kHz(94)

The current sense network dissipated roughly 0.04 W and had very little effect on the power budget.
PBUDGET ≈ PBUDGET − PRS − PDA ≈ 5.96 W(95)

12 Voltage Loop and Slope Compensation
The UCC28950/1 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency
noise. This pin needs at least 1 µF of high frequency bypass capacitance (CBP1). Please refer to figure 1 forproper placement.
CBP1 = 1 uF

(96)

The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (RA, RB), for this design
example we are going to set the error amplifier reference voltage (V1) to 2.5 V. Select a standard resistor value
for RB and then calculate resistor value RA.
UCC28950/1/1 reference voltage:
VREF = 5 V(97)

V1 = 2.5 V(98)

Set voltage amplifier reference voltage:

RB = 2.37 kΩ

(99)

R × VREF − V1
RA = B= 2.37 kΩ
V1

(100)

Voltage divider formed by resistor RC and RI are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).
Select a standard resistor for RC:
RC = 2.37 kΩ

(101)Calculate RI:
RI =Rc × VOUT − V1
≈ 9 kΩ
V1(102)

Then choose a standard resistor for RI:
RI = 9.09 kΩ(103)Compensating the feedback loop can be accomplished by properly selecting the feedback components (RF, CZ
and CP). These components are placed as close to pin 3 and 4 as possible of the UCC28950/1.
Calculate load impedance at 10% load (RLOAD):
2V
RLOAD = P OUT= 2.4 ΩOUT × 0.1

(104)

Approximation of control to output transfer function (GCO(f)) as a function of frequency:

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ΔVOUT
R
1 + 2πj × f × ESRCOUT × COUT
GCO f ≈ ΔV
= a1 × a2 × LOAD
RS × 1 + 2πj × f × RLOAD × COUT ×
S fC
1+2π × fDouble pole frequency of GCO(f):

PP

1

+

2
S f
2π × f PP(105)

f PP ≈ fs
4 = 50 kHz(106)

S f = 2π × j × f(107)

Angular velocity:

Compensate the voltage loop with type 2 feedback network. The following transfer function is the compensation
gain as a function of frequency (GC(f)). Please refer to Figure 2-1 for component placement.
ΔV

2πj × f × R × C + 1

FZ
GC f = ΔV C =2πj × f × CZ × CP × RF
OUT
2πj × f × CZ + CP RI
+1
C +C
Z

P

(108)

(109)

Calculate voltage loop feedback resistor (RF) based on crossing the voltage (fC) loop over at a 10th of the double
pole frequency (fPP).
fPP
f C = 10
= 5 kHz

RF =

RI
f PP
GCO 10(110)≈ 27.9 kΩ

(111)

Select a standard resistor for RF.
RF ≈ 27.4 kΩ

(112)

1

(113)

Calculate the feedback capacitor (CZ) to give added phase at crossover.
CZ =f ≈ 5.8nF
2 × π × RF × C
5CZ = 5.6nF(114)

Select a standard capacitance value for the design.
Put a pole at two times fC.
CP = 2 × π × R1 × f × 2 ≈ 580pF
F
C

(115)

CP = 560pF(116)

TVdB f = 20log GC f × GCO f(117)

Select a standard capacitance value for the design.

Loop gain as a function of frequency (TV(f)) in dB.

Plot theoretical loop gain and phase to graphically check for loop stability (Figure 11-1). The theoretical loop gaincrossed over at roughly 3.7 kHz with a phase margin of greater than 90 degrees.

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Voltage Loop and Slope Compensation

Note
It is wise to check your loop stability of your final design with transient testing and/or a network
analyzer and adjust the compensation (GC(f)) feedback as necessary.

Figure 12-1. Loop Gain and Loop Phase
To limit over shoot during power up the UCC28950/1 has a soft-start function (SS, Pin 5) which in this application
was set for a soft start time of 15 ms (tSS).
tss = 15 ms
t

(118)

× 25uAss
Css = V1
+ 0.55 ≈ 123 nF(119)

Css = 150 nF(120)

Select a standard capacitor for the design.

The UCC28950/1 also provides slope compensation for peak current mode control (Pin 12). This can be set bysetting RSUM with the following equations. The following equations will calculate the required amount of slope
compensation (VSLOPE) that is needed for loop stability.
Note
The change in magnetizing current on the primary ΔILMAG contributes to slope compensation.
V 1 − DTYP
∆ ILMAG = INL× fs = 234 mA

(121)

MAG

To help improve noise immunity VSLOPE is set to have a total slope that will equal 10% of the maximum current
sense signal (0.2 V) over one inductor switching period.

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Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)

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VSLOPE1 = 0.2V × fs × 0.04V
us

(122)

∆ ILOUT× RS 1 − DTYP × f S
a1 × 2 − ∆ ILMAGVSLOPE2 = 0.2V × fs −= 0.04V
us
a2

(123)

If VSLOPE2 < VSLOPE1 set VSLOPE = VSLOPE1
If VSLOPE2 ≥ VSLOPE1 set VSLOPE = VSLOPE2
3

Ω
RSUM = V 2.5V × ×100.5us≈ 125.4 kΩ

(124)

RSUM = 127 kΩ

(125)

SLOPE

Select a standard resistor for RSUM.

13 Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)This application note presents a fixed delay approach to achieving ZVS from 100% load down to 50% load.
When the converter is operating below 50% load the converter will be operating in valley switching. In order toachieve zero voltage switching on switch node of QBd, the turn-on (tABSET) delays of FETs QA and QB needs
to be initially set based on the interaction of LS and the theoretical switch node capacitance. The following
equations are used to set tABSET initially.
Equate shim inductance to two times COSS capacitance:
2π × f RLS =1
2π × f R × 2 × COSS_QA_AVG(126)

Calculate tank frequency:
fR =12π LS × 2 × COSS_QA_AVG(127)

Set initial tABSET delay time and adjust as necessary.
Note
The 2.25 factor of the tABSET equation was derived from empirical test data and may vary based on
individual design differences.
tABSET = f 2.25
× 4 ≈ 346 ns

(128)

R

The resistor divider formed by RDA1 and RDA2 programs the tABSET, tCDSET delay range of the UCC28950/1.
Select a standard resistor value for RDA1.
NotetABSET can be programmed between 30 ns to 1000 ns.
RDA1 = 8.25 kΩ

(129)

The voltage at the ADEL input of the UCC28950/1 (VADEL) needs to be set with RDA2 based on the following
conditions.
If tABSET > 155 ns set VADEL = 0.2 V, tABSET can be programmed between 155 ns and 1000 ns:
If tABSET ≤ 155 ns set VADEL = 1.8 V, tABSET can be programmed between 29 ns and 155 ns:
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Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)

Based on VADEL selection, calculate RDA2:
R
× VADELRDA2 = DA1
5V − VADEL ≈ 344 Ω(130)

Select the closest standard resistor value for RDA2:
RDA2 = 348 Ω(131)Recalculate VADEL based on resistor divider selection:
VADEL = R

5V × RDA2= 0.202 V
DA1 + RDA2

RDELAB =0.15V + VADEL × 1.46 × 103
tABSET − 5ns
1
×× 1A≈ 30.4 kΩ
ns
5

(132)

Resistor RDELAB programs tABSET:(133)

Select a standard resistor value for the design:
RDELAB = 30.1 kΩ

(134)

Note

Once you have a prototype up and running it is recommended you fine tune tABSET at light load tothe peak and valley of the resonance between LS and the switch node capacitance. In this design the
delay was set at 10% load.

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Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)

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Set tABSET at resonant tank Peak and ValleytABSET = t1 - t0

tABSET = t4 - t3

QBd

QAg

Miller PlateautMILLER = t2 - t1

QBg

Miller PlateautMILLER = t5 - t4
t3 t4 t5

t0 t1 t2

Figure 13-1. tABSET to Achieve Valley Switching at Light Loads
The initial starting point for the QC and QD turn on delays (tCDSET) should be initially set for the same delay as
the QA and QB turn on delays (Pin 6). The following equations program the QC and QD turn-on delays (tCDSET)
by properly selecting resistor RDELCD (Pin 7).
tABSET = tCDSET(135)

Resistor RDELCD programs tCDSET:RDELCD =0.15V + VADEL × 1.46 × 103
tABSET − 5ns
1
×× 1A≈ 30.4 kΩ
ns
5

(136)

Select a standard resistor for the design:
RDELCD = 30.1kΩ

18

(137)

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Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)

Note
Once you have a prototype up and running it is recommended to fine tune tCDSET at light load. In thisdesign the CD node was set to valley switch at roughly 10% load. Obtaining ZVS at lighter loads withswitch node QDd is easier due to the reflected output current present in the primary of the transformer
at FET QD and QC turnoff/on. This is because there was more peak current available to energize LS
before this transition, compared to the QA and QB turnoff/on.

Set tCDSET at resonant tank Peak and ValleytCDSET = t1 - t0

tCDSET = t4 - t3

QDd

QCg

Miller PlateautMILLER = t2 - t1

QDg

Miller PlateautMILLER = t5 - t4
t0 t1 t2

t3 t4 t5

Figure 13-2. tCDSET to Achieve Valley Switching at Light Loads
There is a programmable delay for the turnoff of FET QF after FET QA turnoff (tAFSET) and the turnoff of FET
QE after FET QB turnoff (tBESET). A good place to set these delays is 50% of tABSET. This will ensure that theappropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large it will cause
OUTE and OUTF not to overlap correctly and it will create excess body diode conduction on FETs QE and QF.
tAFSET = tBESET = tABSET × 0.5(138)

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The resistor divider formed by RCA1 and RCA2 programs the tAFSET and tBESET delay range of the UCC28950/1.
Select a standard resistor value for RCA1.

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Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)

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Note
tEFSET and tBESET can be programmed between 32 ns to 1100 ns.
RCA1 = 8.25 kΩ

(139)

The voltage at the ADELEF pin of the UCC28950/1 (VADELEF) needs to be set with RCA2 based on the following
conditions.
If tAFSET < 170 ns set VADEL = 0.2 V, tABSET can be programmed between 32 ns and 170 ns:
If tABSET > or = 170 ns set VADEL = 1.7 V, tABSET can be programmed between 170 ns and 1100 ns:
Based on VADELEF selection, calculate RCA2:
RCA1 × VADELEF
RCA2 = 5V− VADELEF ≈ 4.25 kΩ

(140)

Select the closest standard resistor value for RCA2:
RCA2 = 4.22 kΩ

(141)Recalculate VADELEF based on resistor divider selection:
5V × RCA2= 1.692 V
CA1 + RCA2VADELEF = R(142)

The following equation was used to program tAFSET and tBESET by properly selecting resistor RDELEF.
RDELEF =tAFSET × 0.5 − 4ns
2.65V − VADELEF × 1.32 × 103
1
×× 1A≈ 14.1 kΩ
ns
5

(143)

A standard resistor was chosen for the design.
RDELEF = 14 kΩ

(144)

tMIN = 100 ns(145)

RTMIN = 12.1 kΩ

(146)

RTMIN =

(147)

Resistor RTMIN programs the minimum duty cycle on time (tMIN) that the UCC28950/1 (Pin 9) can demand before
entering burst mode. If the UCC28950/1 controller tries to demand a duty cycle on time of less than tMIN thepower supply will go into burst mode operation. Please see the UCC28950/1 data sheet for details regarding
burst mode. For this design we set the minimum on time to 100 ns.

The minimum on time is set by selecting RTMIN with the following equation.

tMIN − 15ns × 103≈ 12.9 kΩ
6.6s

A standard resistor value is then chosen for the design.
RTMIN = 12.1 kΩ

(148)

There is a pin that is provided for setting up the converter switching frequency (Pin 10). The frequency can beselected by adjusting timing resistor RT.

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RT =Turning SR FETs-off Under Light Load Conditions
2.5 × 106 ΩHz
V
fS
2

3
−Ω
V × VREF − 2.5V × 2.5 × 10 ≈ 60 kΩ

(149)

Select a standard resistor for the design.
RT = 61.9 kΩ

(150)

14 Turning SR FETs-off Under Light Load Conditions
To increase efficiency at lighter loads the UCC28950/1programmed (Pin 12, DCM) under light load conditions
to turn off the synchronous FETs on the secondary side of the converter (QE and QF). This threshold is
programmed with resistor divider formed by RE and RG. This DCM threshold needs to be set at a level before theinductor current goes discontinues. The following equation sets the synchronous rectifiers to turnoff at roughly
15% load current.

VRS =POUT × 0.15 ΔILOUT
× RS
+
VOUT
2
= 0.29V
a1 × a2(151)

RG = 1 kΩ

(152)

Select a standard resistor value for RG.
R V
− VRS
RE = G REF≈ 16.3 kΩ
V

(153)

RS

Select a standard resistor value for this design
RE = 16.9k(154)

15 600 W FSFB Detailed Schematic and Test Data

Copyright © 2017, Texas Instruments Incorporated

Figure 15-1. Daughter Board Schematic

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600 W FSFB Detailed Schematic and Test Data

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Note

+

+

+

+

+

+

+

Black triangles designate not populated.

Figure 15-2. Power Stage Schematic
Note
It is recommended to use an RCD clamp to protect the output synchronous FETs from over voltage
due to switch node ringing. This RCD clamp is formed by diodes D4, D6 and resistor R6, R8 and R9
and capacitor C1.

22

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600 W FSFB Detailed Schematic and Test Data

Figure 15-3. 600-W Phase Shifted Full Bridge Efficiency
Full bridge gate drives and primary switch nodes (QBd and QDd) at VIN = 390 V, IOUT = 5 A.

Valley Switching

Valley Switching

QBd/Q4d

QBd/Q4d

Q4g

Q4g

QB/Q4 = off

QB/Q4 = off

QB/Q4 = on

QB/Q4 = on

0V
QA/Q1 = ontABSET

0V
QA/Q1 = on

QA/QB = offtABSETtD Slight Delay after tABSET
before Miller Plateau

Figure 15-4. Q4g Q4d, VIN = 390 V, IOUT = 5 A

QA/QB = offtD Slight Delay after tABSET
before Miller Plateau

Figure 15-5. Q3g Q3d, VIN = 390 V, IOUT = 5 A

Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 10 A

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600 W FSFB Detailed Schematic and Test Data

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Valley Switching

QBd/Q4d

QDd/Q3d

Q3g

ZVS

Q4g

0V

QD/Q3 = off

QB/Q4 = off

QD/Q3 = on

QB/Q4 = on
0V

QA/Q1 = on

0V

QC/Q2 = on

QC/Q2 = off

QA/QB = off

tCDSETtABSETtD Slight Delay after tABSETtD Slight Delay after tCDSET
before Miller Plateau

before Miller Plateau

Figure 15-7. Q3g Q3d, VIN = 390 V, IOUT = 10 A

Figure 15-6. Q4g Q4d, VIN = 390 V, IOUT = 10 A
Note

Switch node QBd/Q4d is valley switching and node QDd/Q3d has achieved ZVS. It is not uncommon
for switch node QDd/Q3d to obtain ZVS before QBd/Q4d. This is because during the QDd/Q3d switch
node voltage transition, the reflected output current provides immediate energy for the LC tanking at
the switch node. Where at the QBd/Q4d switch node transition the primary has been shorted out by
the high side or low side FETs in the H bridge. This transition is dependent on the energy stored in LS
and LLK to provide energy for the LC tanking at switch node QBd/Q4d making it take longer to achieve
ZVS.
Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 25 A

ZVS Achieved

QBd/Q4d

QDd/Q3d

Q3g

ZVS

Q4g
QB/Q4 = off

QD/Q3 = off

QB/Q4 = on
0V

QA/Q1 = on

QD/Q3 = on
0V

QC/Q2 = on

QA/QB = off

QC/Q2 = off

tCDSETtABSET

Figure 15-9. Q3g Q3d, VIN = 390 V, IOUT = 25 A

Figure 15-8. Q4g Q4d, VIN = 390 V, IOUT = 25 A
Note

When the converter is running at 25 A both switch nodes are operating into zero voltage switching(ZVS). It is also worth mentioning that there is no evidence of the gate miller plateau during gate driverswitching. This makes sense because the voltage across the drain and source of FETs QA throughQD has already transition before the gate drives have transitioned.

24

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References

Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 50 A

ZVS

QBd/Q4d

QDd/Q3d

Q3g

ZVS

Q4g
QB/Q4 = off

QD/Q3 = off

QB/Q4 = on
0V

QA/Q1 = on

QD/Q3 = on
0V

QC/Q2 = on

QA/QB = off

QC/Q2 = off

tCDSETtABSET

Figure 15-11. Q3g Q3d, VIN = 390 V, IOUT = 25 A

Figure 15-10. Q4g Q4d, VIN = 390 V, IOUT = 25 A
Note
ZVS was maintained from 50% to 100% output power.

16 References
1. Bill Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM
Controller Unitrode Application Note SLUA107, September 5, 1999
2. Lazlo Balogh, Design and Application Guide for High Speed Mosfet Gate Drive, Unitrode Power Supply
Design Seminar, Topic 2, 2001
3. Colin Gillmore, Making the Correct Choice: UCC28950-Q1 or UCC28951-Q1 , Application Note SLUA853,
December 2017, Topic 2, 2001
4. Texas Instruments, UCC28950 Green phase-shifted full-bridge controller with Synchronous Rectification
control, data sheet
5. Texas Instruments, UCC28951 Green phase-shifted full-bridge controller with Synchronous Rectification
control, data sheet

17 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2011) to Revision D (March 2022)
Page• Updated to include UCC28951 and update equations to new TI format throughout publication........................ 1

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