White PaperSNOAA34 – February 2019

TI BAW technology enables ultra-low jitter clocks for highspeed networks
Benyong Zhang, Arvind Sridhar, Ernest Ting-Ta Yen, Xiaolin Lu

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Contents
Introduction ................................................................................................................... 2
Ultra-Low Noise Voltage-Controlled BAW Oscillator IP................................................................. 4
LMK05318 Ultra-Low Jitter Network Synchronizer Chip Architecture ................................................ 6
Better Mid-Band Phase Noise (10kHz~1MHz) ........................................................................... 9
Allow Usage of Low Frequency TCXO/OCXO/XO to Reduce Total Solution Cost ................................. 9More Reliable Phase Noise and Total rms Jitter ........................................................................ 9Conclusions ................................................................................................................. 10
Additional Information ...................................................................................................... 10
List of Figures1

Simplified diagram for network synchronizers used in communication equipment timing cards and line
cards. .......................................................................................................................... 2

2

Basic structure of a Bulk Acoustic Wave (BAW) resonator. ........................................................... 4

3

The modified Butterworth-Van Dyke (MBVD) model, electrical equivalent of a BAW resonator .................. 4

4

Typical 2.5GHz VCBO phase noise (measured at a carrier frequency of 1.25GHz). The total rms jitter isaround 33fs. .................................................................................................................. 5

5Compare phase noise performance of LMK05318 2.5GHz VCBO with the state-of-art LC VCO of
LMX2582 (normalized to 2.5GHz) ........................................................................................ 5

6

LMK05318 simplified chip level block diagram........................................................................... 6

7

Typical DPLL/APLL1 312.5Mhz output phase noise. TJrms_12_20Mhz is around 47fs. ......................... 7

8

Typical APLL2 155.52Mhz output phase noise. FVCO2=5598.72Mhz, APLL2
FPD=2500Mhz/18=138.8…Mhz. TJrms_12_20Mhz is around 118fs. ............................................... 8

9

CLKout phase noise comparison of LMK05318 with conventional LC VCO based network synchronizers
from competition.............................................................................................................. 9
List of Tables

1

Compare phase noise performance of LMK05318 2.5GHz VCBO with the state-of-art LC VCO of
LMX2582 (normalized to 2.5GHz) . ....................................................................................... 52

Benefits of LMK05318 Network Synchronizer with a 2.5GHz VCBO when compared with conventional
solution with an LC VCO .................................................................................................. 10

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Introduction

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1

Introduction
DPLL (Digital Phase-Locked Loop) based network synchronizers, which generate and distribute clean
output clocks to various sub-systems based on received network clocks, are critical components incommunication network equipment. The simplified diagram in Figure 1 demonstrates how network
synchronizers are used in timing cards and line cards of typical communication equipment such as routersand switchers. To comply with requirements of communication standards such as ITU-T G.8262, network
synchronizers are used to detect valid input clocks, filter input clock wander, and perform hitless switching
and holdover functions. Low noise clocks are generated based on APLL’s (Analog Phase-Locked Loop)locked to an external crystal reference oscillator (XO), or a temperature-compensated XO (TCXO) or anoven-stabilized XO (OCXO).
Timing Card

Backplane

LMK05XXX DPLL (Active)
Input Clock Detection
Hitless Switching
HoldoverWander Filtering
IEEE 1588 Support
Jitter Cleaning
Output Clock Generation

Line Card

19.44MHz312.5MHzPHY
LMK05318 DPLL
Input Clock Detection
Hitless Switching
50MHz
Jitter Cleaning
Output Clock Generation
156.25MHz

TCXO/OCXOLMK05XXX DPLL (Backup)
Input Clock Detection
Hitless Switching
HoldoverWander Filtering
IEEE 1588 Support
Jitter Cleaning
Output Clock Generation

Switch
SOC

19.44MHzTCXO/XO

TCXO/OCXO

Figure 1. Simplified diagram for network synchronizers used in communication equipment timing cards
and line cards.
One key specification for network synchronizers is output clock integrated root-mean-square (rms) jitter,
which is integrated over a certain frequency band specified by various communication standards. The
required network synchronizers output clock jitter is becoming more and more challenge to meet stringent
signal noise ratio (SNR) / bit error rate (BER) requirement and have good design margins ascommunication network data rates continue to increase due to explosive data traffic growth. For example,
as communication networks evolve from 100 Gigabits per second (Gbps) to 400 Gbps systems, systemdesigners require that network synchronizers output clocks maximum total rms jitter integrated from 12kHz
to 20MHz (TJrms_12kHz_20Mhz, including spurs) to be less than 150fs. For simplicity, in the following
discussion of output clock total rms jitter, the integration bandwidth is always from 12kHz to 20Mhz andspurs are always included.
The state-of-the-art network synchronizer IC’s typically generate output clocks based on an integrated
high frequency LC VCO. The VCO phase noise is limited by quality factor of its integrated LC tank,typically around 20~30 after optimization. Assuming the LC VCO is locked by a PLL with a very narrow
loop bandwidth such as 100Hz, the output clock rms jitter could be around several hundred fs or higher,
mainly dominated by LC VCO phase noise, thus unable to meet 150fs requirement.

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Introduction

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To achieve better rms jitter, designers can increase the APLL loop bandwidth to attenuate close-in phasenoise from a VCO. However, due to the analog nature of fractional-N APLL, the APLL inherent in-band
phase noise is limited by analog imperfections and may be sensitive to process, supply, temperature(PVT) variations as well as crosstalk effects. The crystal reference oscillator phase noise is also limited.
As a result increasing APLL loop bandwidth beyond certain range may cause APLL inherent in-band
phase noise and crystal reference oscillator phase noise to become the dominant contributors thus
preventing further reduction of total rms jitter. Furthermore, increasing APLL loop bandwidth also degrades
filtering of fractional-N spurs and quantization noise thereby may degrade total rms jitter performance.
With a low noise high frequency (such as 48Mhz) XO, the optimum PLL loop bandwidth for minimum rms
jitter could typically be a few hundred kHz or higher for state-of-the-art network synchronizer IC’s utilizing
LC VCO’s, which results in maximum total rms jitter around 150fs or higher. For these reasons theconventional network synchronizers based on LC VCO are becoming the performance bottleneck for 400Gbps and future higher speed communication systems.
Another drawback of conventional network synchronizers based on LC VCO is their requirement of a highfrequency low noise crystal reference oscillator for total rms jitter optimization. To meet stringent holdoveraccuracy requirements for certain systems, such as max +/- 4.6ppm as specified for Sync E in ITU-T
G.8262, a TCXO or OCXO is preferred over a normal un-compensated XO. However, reliable highfrequency low noise TCXO’s or OCXO’s are not easily available and are usually expensive. Therefore
system designers have to make trade-off’s among clock phase noise/jitter performance, holdoveraccuracy, and total solution cost.
To solve this challenge issue, designers can utilize the LMK05318 network synchronizer IC solution thatfeatures a Bulk Acoustic Wave (BAW) technology. This device uses a high-Q BAW resonator co-packaged
with silicon IC to implement an ultra-low noise integrated Voltage-Controlled BAW Oscillator (VCBO). As
shown in the following, the 2.5GHz VCBO close-in (1kHz~100kHz) phase noise is about 10~20dB better
than the state-of-the-art LC VCO. The innovative BAW technology greatly reduces the synchronizedoutput clock phase noise/rms jitter thereby meeting the challenge requirement of max rms jitter less than
150fs with comfortable margin, which exceeds 400-Gbps system requirements and allows future migration
to data rates above 400-Gbps. Additionally, this solution lowers overall solution cost by eliminating theneed for a high frequency low noise TCXO or OCXO.

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3Ultra-Low Noise Voltage-Controlled BAW Oscillator IP

2

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Ultra-Low Noise Voltage-Controlled BAW Oscillator IP
BAW resonators featuring high operating frequency up to a few GHz and small size have been used formobile applications such as filters in the RF front-end of wireless transceivers for many years. The BAW
resonator is a piezoelectric thin film resonator, which operates similarly to a quartz crystal. As shown in
Figure 2, a piezoelectric thin film is sandwiched between two metal electrodes and several acoustic
reflectors to confine mechanical energy. The end result is a very stable high-Q resonator tank.
Electrodes

Piezoelectric layer

Substrate

Figure 2. Basic structure of a Bulk Acoustic Wave (BAW) resonator.
The electrical equivalence of a BAW resonator can be represented by a modified Butterworth-Van Dyke
(MBVD) model, as shown in Figure 3. Like a conventional crystal resonator, it has a parallel resonancefrequency Fp and serial resonance frequency Fs.
Resonator

Static branchElectrical loss

Motional branch

Figure 3. The modified Butterworth-Van Dyke (MBVD) model, electrical equivalent of a BAW resonator
Through many years of joint research and development efforts among various functional teams within thecompany, TI has perfected the recipe for a high frequency high-Q BAW resonator while simultaneously
solved the challenge of co-packaging it with silicon IC. The typical quality factor of a BAW resonator usedin 2.5GHz VCBO is 1200.
The total rms jitter of a typical 2.5GHz VCBO based on TI’s innovative BAW technology is around 33fs at
1.25Ghz output, as shown in Figure 4. Comparison results of phase noise performance of LMK05318
2.5GHz VCBO with the state-of-art LC VCO of LMX2582 (normalized to 2.5GHz) are shown in Figure 5
and Table 1. The 2.5GHz VCBO close-in (1kHz~100kHz) phase noise is about 10~20dB better than thestate-of-the-art LC VCO, which clearly demonstrates the phase noise/jitter advantage of VCBO. Based on
this superior low phase noise VCBO technology, ultra-low jitter network synchronizer products like
LMK05318 are developed to meet challenge requirements of advanced high speed communication
networks such as 400Gbps systems.

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Figure 4. Typical 2.5GHz VCBO phase noise (measured at a carrier frequency of 1.25GHz). The total rms
jitter is around 33fs.
-60
LMX2582 5.5GHz LC VCO (normalized to 2.5GHz)
LMK05318 2.5GHz VCBO
Phase Noise (dBc/Hz)

-80

-100

-120

-140

-160
1E+3

2E+3

3E+3

5E+3 7E+3 1E+4

2E+4 3E+4
5E+4 7E+4 1E+5
Frequency Offset (Hz)

2E+5

3E+5

5E+5 7E+5 1E+6
figu

Figure 5. Compare phase noise performance of LMK05318 2.5GHz VCBO with the state-of-art LC VCO of
LMX2582 (normalized to 2.5GHz)
Table 1. Compare phase noise performance of LMK05318 2.5GHz VCBO with the state-of-art LC
VCO of LMX2582 (normalized to 2.5GHz) .
Offset Frequency (Hz) LMX2582 5.5GHz LC VCO(normalized to 2.5GHz) (dBc/Hz)

LMK05318 2.5GHz VCBO
(dBc/Hz)

Improvement
(dB)

1k

-64.8

-90

25.2

10k

-96.5

-110

13.5

100k

-120.8

-130

9.2

1M

-141.7-145

3.3

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LMK05318 Ultra-Low Jitter Network Synchronizer Chip Architecture3

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LMK05318 Ultra-Low Jitter Network Synchronizer Chip Architecture
LMK05318 is the industry’s first commercial network synchronizer that utilizes a high frequency high-Q
BAW resonator integrated in a standard QFN package together with the silicon IC to form a VCBO togenerate ultra-low jitter clocks. The chip level block diagram of the LMK05318 ultra-low jitter network
synchronizer is shown in Figure 6.
VDDO (x6)
1.8 / 2.5 / 3.3 V

Power Conditioning

Outputs(all blocks)

SYNC

Reference Inputs
×1, ×2

OUT0

VCO1

÷R
5-b

0

PFD

0
1
2
3

÷OD
8-b

OUT1

÷N

1

40-b Frac-N
Hitless Switching
and Priority Selection

PRIREF

SECREF

0
1
2
3

DPLL
÷R
16-b

TDC

÷FB

DCO

÷RS

÷RP

/1 to /32

/3 to /6

APLL2

VCO2

EEPROM/2 to /7

÷NRegisters

0
1
2
3

Post
Dividers

PFD

Digital
I2C/
SPI

0
1
2
3

40-b Frac-N

FINC/FDECSDA/SDI
SCL/SCKGPIO2/SDO/FINC
GPIO1/SCSGPIO0/SYNCN
HW_SW_CTRL
PDN

8-b

OUT3

Input
Monitors

REFSELOUT2
÷OD/2 to /7

24-b Frac-N

÷OD
8-b

÷OD
8-b

OUT4

OUT5

2

3

0
1
2
3

÷OD
8-b

OUT6

ROM

Device Control and Status

STATUS1/FDEC STATUS0

AC-LVDS, AC-CML, AC-LVPECLor HCSL

XO

APLL1

0
1
2
3

PLL
Monitors

CAP
(x3)

LF1

÷OD
8-b × 24-b

AC-LVDS, AC-CML, AC-LVPECL,HCSL, or 1.8-V LVCMOSVDD (x5)
3.3 V

OUT7

LF2

Figure 6. LMK05318 simplified chip level block diagram.
LMK05318 has a fully programmable DPLL core, which provides input clock detection/monitoring,
wander/jitter filtering, and supports industry’s best hitless input clock switching and holdover functionality.
The device can operate in normal operation mode with DPLL enabled, holdover mode with input clocks
disabled, or free run mode. LMK05318 meets requirements of various communication standards such as
ITU-T G.8262. Features such as on-chip EEPROM, on-chip LDO’s, make it easy to configure and operate
the device. Refer LMK05318 datasheet for many other useful features.
The VCO1 of APLL1 is a 2.5GHz VCBO. Output clocks generated from APLL1 achieves industry's best-inclass output clock rms jitter and phase noise performance. As shown in the following Figure 7, the312.5Mhz output typical total rms jitter is around 47fs.

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LMK05318 Ultra-Low Jitter Network Synchronizer Chip Architecture

Figure 7. Typical DPLL/APLL1 312.5Mhz output phase noise. TJrms_12_20Mhz is around 47fs.
APLL2 with a 5.5~6.25GHz LC VCO can be used to generate clocks that cannot be generated from
2.5GHz VCBO directly. For 155.52Mhz output from APLL2, total rms jitter is around 118fs.

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LMK05318 Ultra-Low Jitter Network Synchronizer Chip Architecture

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Figure 8. Typical APLL2 155.52Mhz output phase noise. FVCO2=5598.72Mhz, APLL2
FPD=2500Mhz/18=138.8…Mhz. TJrms_12_20Mhz is around 118fs.
Additional benefits of LMK05318 solution with a VCBO are summarized in Table 2 and discussed in thefollowing.

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Submit Documentation FeedbackBetter Mid-Band Phase Noise (10kHz~1MHz)

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4

Better Mid-Band Phase Noise (10kHz~1MHz)As shown in Figure 9, the mid-band phase noise (10kHz~1MHz) of LMK05318 is much better thanconventional solutions based on LC VCO’s since it is mainly dominated by VCBO close-in phase noise
and there is no big noise hump contributed by wide-band APLL1,. This is a big advantage in systems suchas wireless cellular macro base-stations that require stringent clock mid-band phase noise at certain
frequency offsets (like MC-GSM phase noise at 800kHz offset, etc).
-80
LMK05318
Competitor
Phase Noise (dBc/Hz)

-100

-120

-140

-160

-180
1E+2 2E+2

5E+2 1E+3 2E+3

5E+3 1E+4 2E+4
5E+4 1E+5 2E+5
Frequency Offset (Hz)5E+5 1E+6 2E+6

5E+6 1E+7 2E+7
figu

Figure 9. CLKout phase noise comparison of LMK05318 with conventional LC VCO based network
synchronizers from competition.

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Allow Usage of Low Frequency TCXO/OCXO/XO to Reduce Total Solution CostThanks to the ultra-low noise VCBO, it can be observed from Figure 7 that the ultra-low jitter of LMK05318
output clocks is achieved with APLL1 loop bandwidth of a few kHz, which implies external
XO/TCXO/OCXO phase noise has less impact for total rms jitter. Low frequency (like 10~20MHz)
TCXO/OCXO/XO may be used for LMK05318 without significant impact to total rms jitter, thereby lowering
total solution cost.
As a comparison, the conventional solution requires high frequency (around 50MHz ) external
TCXO/OCXO/XO’s with low phase noise that are typically more expensive.

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More Reliable Phase Noise and Total rms Jitter
There are a few reasons that LMK05318 output clock total rms jitter is less susceptible to Process, Supply,
Temperature (PVT) variations. First, LMK05318 output clock total rms jitter is mainly dominated by VCBO
phase noise and insensitive to APLL in-band phase noises and external TCXO/OCXO/XO phase noise. As
a comparison, for conventional solution using wide-band APLL with LC VCO, its total rms jitter is sensitive
to APLL in-band phase noise and external TCXO/OCXO/XO phase noise. Note in-band phase noise of
fractional APLL is sensitive to modulation nonlinearities so that it can vary quite a lot over PVT variations.
Second, for conventional solution, the wide loop bandwidth (at least several hundred kHz) of APLL makes
it more difficult to filter out fractional spurs and fractional PLL quantization noise. In contrast, for
LMK05318 with narrow loop bandwidth APLL ( a few kHz), the fractional spurs and fractional PLL
quantization noise can be easily filtered out resulting lower output clock phase noise/jitter.

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Conclusions

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Table 2. Benefits of LMK05318 Network Synchronizer with a 2.5GHz VCBO when compared withconventional solution with an LC VCO
Factors

Network Synchronizer Based VCBO

Network Synchronizer Based LC VCO

APLL FPD frequency

Low FPD can be used (a few MHz or lower)
and still achieve good rms jitter

High FPD (about 50 MHz or higher) is required
to achieve good rns jitter

APLL loop bandwidth for optimum total rms
Narrow (below a few kHz)jitter (12 kHz to 20 MHz)

Wide (above a few hundred kHz)

Mid-band phase noiseSuperior mid-band phase noise (10 kHz to~1 MHz)Worse mid-band phase noise due to noise
contribution of wideband APLL

Max total rms jitter (12 kHz to 20 MHz)

100 fs or less150 fs or higher

APLL in-band phase noise variation over
PVT

Total rms jitter is less sensitive to APLL inband phase noise over PVT

Total rms jitter is sensitive to APLL in-band
phase noise over PVT

APLL fractional spurs and quantizationnoise over PVT

Lower APLL fractional spurs andquantization noise due to more filtering of
narrowband APLL

Worse APLL fractional spurs and quantizationnoise due to less filtering of wideband APLL

Cost of reference crystal oscillator

Can use normal low-frequency
TCXO/OCXO/XO to reduce overal solution
cost

Need expensive low-noise high-frequency
TCXO/OCXO/XO to achieve good rms jitter

7

Conclusions
The required network synchronizers output clock jitter is becoming more and more challenging forconventional solutions based on LC VCO to achieve as communication network data rates keep goinghigher. A new network synchronizer solution LMK05318 based on the break-through BAW technology wasdeveloped to significantly improve phase noise / rms jitter performance over conventional solutions basedon LC VCO. The BAW resonator is manufactured in a CMOS-compatible process and is integrated withthe silicon IC die in a standard QFN package. The 2.5GHz VCBO close-in (1kHz~100kHz) phase noise isabout 10~20dB better than the state-of-the-art LC VCO, which clearly demonstrates the phase noise/jitter
advantage of VCBO. The output clock typical total rms jitter is 33fs at 1250MHz output and is 47fs for
312.5Mhz output. The output clock maximum total rms jitter is less than 100fs, exceeding stringent rms
jitter specification required for high speed 400-Gbps communication networks. Unlike conventional
approach based on a LC VCO, a lower frequency lower cost normal TCXO/OCXO can be used with
LMK05318, which reduces total solution cost. Additional benefits of LMK05318 network synchronizer witha 2.5GHz VCBO are summarized in Table 2.

8Additional Information
Here is more information from TI on the Ultra Low Jitter Network Synchronizer Product SNAS771.

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