Very large FFT forTMS320C6678 processors
Xiaohui Li
Applications EngineerProcessors

Ellen Blinka
Marketing engineer
Processors
Texas Instruments

Introduction
This white paper discusses the very large FFT (VLFFT) demo, which implements
one-dimensional complex single-precision floating-point FFTs of size 16K to 1024K
samples on 1, 2, 4 and 8 DSP cores of TI’s TMS320C6678 8-core fixed- and floatingpoint DSP in order to demonstrate the capabilities of the C66x DSP core as well as thecapability of the architecture to accommodate parallelization across multiple cores withperformance boosts proportional to the number of cores added. The FFT was chosen
as the algorithm for this demo as FFTs are common signal processing building blocks
used in applications such as medical imaging, communications, and military andcommercial radars, and electronic warfare (jammers, anti-jammers). The 1024K sample
FFT is shown to take only 6.4 ms when the algorithm is run on all eight DSP cores ofthe TMS320C6678 device at 1 GHz.

TMS320C6678 SoC

Multicore Navigator+*The TMS320C6678 device is an eight-core DSP
based on TI’s C66x fixed- and floating-point DSP**+<<<< -C66x DSP*+<<<< -*+<<<< -*+<<<< -*<<<< -512KB L2
Per C66x Core
011100100010001111

4MB MSMC SRAM

consumes less than 10 W in typical use cases. It

DDR3 72b -1600

also features 512 KB of L2 memory per DSP coreSystemMonitor

Debug

EDMAPktDMA

Security AccelerationPac

Multicore Shared
Memory Controller

which speed it can produce 160 GFLOPS andPowerManager+

C66x DSP C66x DSP C66x DSP

architecture which enables full multicore entitlement.
It is capable of operating at up to 1.25 GHz, atSystemServices

C66x DSP C66x DSP C66x DSP+<<<< -core and built on TI’s innovative KeyStone™

+<<<< -C66x DSP

TeraNet*<<<< -40 nm

Packet AccelerationPac

1G Ethernet Switch
High Speed SerDes Lanes

EMIF and IO

and 4 MB of shared memory for a total of 8 MB ofEMIF16

SPI

GPIO
×16

PCIe
2×

HyperLink
4×

on-chip memory, all with ECC. The DDR3 interface

I 2C

TSIP
×2

UART

SRIO
4×1GbE
2×is capable of running up to 1600 MTPS, can accessFigure 1: TMS320C6678 block diagram

up to 8 GB of external memory and is a 64-bit+ 8-bit ECC interface. Peripherals include PCIe,VLFFT demo

Serial RapidIO® and Gigabit Ethernet, as well as TI’s
HyperLink interface which provides up to 50-Gbps
connection to other TI DSP, ARM®, and ARM+DSP

The VLFFT algorithm requires input data to beprocessors, as well as to FPGAs though third-party

placed in the device’s external memory. During

IP blocks.

the demo, data is accessed, distributed to andIn the VLFFT demo, the TMS320C6678 device

processed by the DSP cores, and then the output isoperates at 1 GHz, using DDR3 transfers at

placed into external memory. The cycle counts and1333 MHz.

times measured incorporate this entire process. The
software can be configured to use different numbers

Very large FFT for TMS320C6678 processors

2January 2015

of cores (1, 2, 4, or 8) to do the computation on

FFTs of size N1 on each core, and step 4 by

FFTs of the following sizes:

computing N1/(number of cores) FFTs of size N2 on• 16K

each core. Core 0 is used as a master core and is• 32K

responsible for synchronizing all the cores, and therest of the cores are used as slave cores. On each

• 64K

core, depending on the sizes of N1 and N2, the• 128K

total number of FFTs on each core is divided into

• 256K

several smaller blocks in order to accommodate• 512K

the size of the L2 SRAM per core. Each block of• 1024K

data is prefetched by DMA from external memory

The FFT implementation is designed to achieve

into L2 SRAM and the FFT results are written backmaximum performance by distributing theto external memory by DDR. Two DMA channels

computational load across multiple cores, and by

are used by each core to transfer input and output

fully utilizing the high-performance computational

samples between external memory (DDR3) andpower of the C66x DSP cores. The basic

internal memory (L2 SRAM).

decimation-in-time approach is used to formulate a
one-dimensional very large FFT computation into aResults

form similar to a two-dimensional FFT computation.
For very large N, it can be factored into N = N1*N2.
If it is very large, a one-dimensional input array canThe results from running the FFT code

be represented as a two-dimensional array of N1

on a TMS320C6678 evaluation board

rows and N2 columns and then the following steps(TMDSEVM6678LE) are listed in Table 1 oncan be taken to compute a one-dimensional very

the following page in both DSP cycles and inlarge FFT from this representation:

milliseconds. Ideally when the number of cores

1. Compute N2 FFTs of N1 size in the column

used for the calculation is doubled, the cycle countdirections

should be cut in half, but this is rarely achieved in

2. Multiply by twiddle factor

real-world situations due to overhead from data

3. Store N2 FFTs of N1 size in row directions tomovement, memory block sizing, and non-infinite

form a N2 by N1 two-dimensional array

bandwidths of data input mechanisms (here,

4. Compute N1 FFTs of N2 size in the column

external memory). In this example, when two cores

direction

are used instead of one the time to run the FFT is
reduced on average by 49.3 percent (1.97×), nearly

5. Store data in column direction to form a N2 byreaching the ideal halving of cycle count. When fourN1 two-dimensional arraycores are used instead of one the time to run theThis algorithm is described fully by Takahashi in

FFT is reduced on average by 72.5 percent (3.67×),“High-performance parallel FFT algorithms for theand when eight cores are used the time is reduced

Hitachi SR8000.”[1]on average by 81.6 percent (5.7×).

In multicore implementation, step one isaccomplished by computing N2/(number of cores)

Very large FFT for TMS320C6678 processors

3January 2015

FFTsizeto a memory boundary being reached as the 8Performance of Computing Very Large FFT(DSP cycles) TMS320C6678-1 GHz, DDR-1330 MHz

cores are consuming data faster than they can be

1 core2 cores

4 cores

8 cores

supplied with data from external memory. The time

16K

473175261457

159063131405to calculate a 1024K FFT, a million point FFT, is

32K

914699478129278405

197939shown to be 6.4 ms when using all eight DSP cores

64K

1856711922285507845314560at 1 GHz.

128K

4099502

20042171059706

640926

256K

8794604

432349922275411185959

512K

18669157

929143147035903102933

1024K

38556557

19328150

9605249

6403155

Improvement over single-core performance

FFTsize8

Performance of Computing Very Large FFT(time, ms) TMS320C6678-1 GHz, DDR-1330 MHz
1 core2 cores

4 cores

8 cores

16K

0.473

0.261

0.159

0.131

32K

0.915

0.478

0.278

0.198

64K

1.857

0.922

0.508

0.315

128K

4.100

2.004

1.060

0.641

256K

8.795

4.323

2.228

1.186

512K

18.669

9.291

4.704

3.103

1024K

38.55719.3289.6056.403

7651 Core
42 Cores
34 Cores8 Cores

21016K

32K

64K

128K

256K

512K

1024K

Size of FFT

Figure 2: Performance improvement of multiple
cores over single core

Table 1: Results of FFT on one, two, four and eight
DSP cores in cycles and milliseconds

Conclusions

It can be seen that the time reduction improves
as FFT size increases from 16K to 256K for both

It is shown that a million point FFT can be executed

the two- and the four-core use cases, and evenby the TMS320C6678 device in as little as 6.4 ms

more dramatically in the eight-core use case.

when all eight cores are operating on the data inThis is because for these smaller FFTs, as moreparallel, at 1 GHz. With these speeds, the DSP cancores are added, the penalty from parallelizing

be used for real-time operations in applications

the code is small relative to the improvement fromsuch as radar, electronic warfare, medical imaging,adding the extra cores. Past 256K size FFTs, theand more. Execution time could be improved even

improvement is either flat, having reached the 2×

further by running the TMS320C6678 device at theor 4× improvement for the two- and four-core use

maximum speed possible, 1.25 GHz, and usingcases, or decreases in the case of eight cores

higher bandwidth DDR3, 1600 MTPS.

being used. This decrease in improvement is due

Very large FFT for TMS320C6678 processors

4January 2015

References[1] D. Takahashi, “High-performance Parallel FFT algorithms for the Hitachi SR8000,” in Proceedings of theFourth International Conference/Exhibition on High-Perfomance Computing in the Asia-Pacific Region,
2000.

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