Real-Time Control Reference Guide

Message from the editors

ti.comMessage from the editors
This document is intended as a valuable quick guide for often used system-level design formulae and real-time control
concepts in order to help facilitate real-time control application design. We hope you find this collection of material
useful.
Here is a brief overview of the key areas included:• Mathematical Models• First and Second Order Systems• Filters• Controller Types• A/D Conversions• Comparator Basics• Characteristics of a Real-Time Processor• Encoder Basics• Pulse Width Modulation Basics• D/A Conversions
Additional resources to explore:
Control Theory Seminar• A four-part technical seminar that offers an introduction to control theory covering fundamental concepts, feedback
systems, transient response, and discrete-time systems.
State Space Control Seminar• A four-part course in control theory based on the state space modeling paradigm covering state space models,
properties of linear systems, state feedback control, and linear state estimators
Introduction to Microcontroller Programming for Power Electronics Control Applications• This book contains the fundamental subjects of the interdisciplinary field of power electronic based systems,
which draws knowledge from circuit and control theory, (digital) signal processing for embedded implementationelectrical machines/drives and power semiconductor devices. This book also presents state-of-the-art techniques
to implement modulation schemes and control algorithms in a commercial microcontroller (MCU) suitable for rapid
prototyping approach, and hint for designing analog circuits, such as low voltage converter, output filters/load.
Control Theory Fundamentals• This book provides a readable introduction to control of both continuous time and discrete time systems. The first
four chapters of the book cover classical methods using transfer functions. The remaining chapters cover analysis
and design using state space methods. Worked examples are included to illustrate key topics in each section. The
book contains five appendices; a review of matrix algebra, reference tables of Laplace and z transforms, supporting
Matlab scripts, and a case study in controller design using state space methods.

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ti.comDigital Control of Dynamic Systems• This book's emphasis is on designing digital controls to achieve good dynamic response and small errors while
using signals that are sampled in time and quantized in amplitude. Both transform (classical control) and state-space(modern control) methods are described and applied to illustrative examples.
Digitally Controlled High Efficiency and High Power Density PFC Cicuits - 3 Part Series• These series of presentations introduce two bridgeless PFC designs using C2000™ MCU. TI high voltage GaN isused to implement a 3.3kW interleaved CCM totem-pole PFC and a 1.6kW interleaved TRM totem-pole PFC designs.
Detailed design considerations are provided to minimize switching loss, current crossover distortion, input current
THD and improve efficiency and PF.
Digital Power SDK• C2000's Digital Power SDK is a cohesive set of software infrastructure, tools, and documentation designed tominimize C2000™ MCU-based digital power system development time targeted for various AC-DC, DC-DC and
DC-AC power supply applications
TIDM-DC-DC-BUCK• The BOOSTXL-BUCKCONV reference design provides a quick and easy way to learn about digital power supply
control and design using C2000 devices.
TI Reference Designs• Ready-to-use reference designs with theory, calculations, simulations, schematics, PCB files and bench test results.
TI Precision Labs
• On-demand courses and tutorials ranging from introductory to advanced concepts that focus on application-specificproblem solving
TI E2E Community• Support forums for all TI products

Table of Contents
Message from the editors......................................................................................................................................................................... 2
System Design............................................................................................................................................................................................6
Control...................................................................................................................................................................................................... 7
Feedback control......................................................................................................................................................................................8
Dynamic systems..................................................................................................................................................................................... 9
System stability...................................................................................................................................................................................... 11
Timing requirements............................................................................................................................................................................... 12
Discrete Time Domain............................................................................................................................................................................ 15
Filters...................................................................................................................................................................................................... 17
Controllers................................................................................................................................................................................................ 23
Linear PID............................................................................................................................................................................................... 24
Linear PI..................................................................................................................................................................................................26
Nonlinear PID..........................................................................................................................................................................................27
2P2Z....................................................................................................................................................................................................... 29
3P3Z....................................................................................................................................................................................................... 30
Direct form controllers............................................................................................................................................................................ 31
ADC............................................................................................................................................................................................................36
ADC definitions.......................................................................................................................................................................................37

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ADC resolution........................................................................................................................................................................................37
Quantization error of ADC...................................................................................................................................................................... 39
Total harmonic distortion (THD).............................................................................................................................................................. 40
AC signals...............................................................................................................................................................................................42
DC signals.............................................................................................................................................................................................. 43
Settling time and conversion accuracy.................................................................................................................................................. 44
ADC system noise.................................................................................................................................................................................. 45
Comparator...............................................................................................................................................................................................47
Basic operation.......................................................................................................................................................................................48
Offset and hysteresis.............................................................................................................................................................................. 48
Propagation delay...................................................................................................................................................................................49
Processing................................................................................................................................................................................................ 51
Data representation................................................................................................................................................................................ 52
Central processing unit...........................................................................................................................................................................55
Memory...................................................................................................................................................................................................56
Direct memory access (DMA)................................................................................................................................................................. 57
Interrupts................................................................................................................................................................................................ 58
Co-processors and accelerators............................................................................................................................................................ 58
Encoders................................................................................................................................................................................................... 61
Encoder definitions.................................................................................................................................................................................62
Types of encoders.................................................................................................................................................................................. 62
Description of encoders......................................................................................................................................................................... 62
Absolute Vs incremental encoders......................................................................................................................................................... 63
Pulse width modulation (PWM)............................................................................................................................................................... 66
PWM definitions..................................................................................................................................................................................... 67
Duty cycle............................................................................................................................................................................................... 67
Resolution...............................................................................................................................................................................................68
Deadband............................................................................................................................................................................................... 69
DAC............................................................................................................................................................................................................72
DAC definitions.......................................................................................................................................................................................73
DAC error................................................................................................................................................................................................73
DAC output considerations.................................................................................................................................................................... 78
Mathematical models.............................................................................................................................................................................. 82
Laplace transforms.................................................................................................................................................................................83
Transfer function..................................................................................................................................................................................... 83
Transient response................................................................................................................................................................................. 84
Frequency response............................................................................................................................................................................... 84
Z-domain................................................................................................................................................................................................ 89

List of Figures
Figure 2-1. Control system...........................................................................................................................................................................7
Figure 2-2. Closed loop system................................................................................................................................................................... 7
Figure 2-3. Unit step response of a 1st order system (τ=1)....................................................................................................................... 10
Figure 2-4. Unit step response of an under-damped 2nd order system....................................................................................................11
Figure 2-5. Digital control system.............................................................................................................................................................. 16
Figure 2-6. Sampling..................................................................................................................................................................................16
Figure 2-7. Filter response curves..............................................................................................................................................................19
Figure 3-1. Parallel form linear PID controller.............................................................................................................................................24
Figure 3-2. Series form of linear PID controller.......................................................................................................................................... 25
Figure 3-3. PID control action.................................................................................................................................................................... 26
Figure 3-4. Nonlinear PID input architecture..............................................................................................................................................27
Figure 3-5. Nonlinear control law input-output plot................................................................................................................................... 27
Figure 3-6. Nonlinear PID linearized region................................................................................................................................................29
Figure 3-7. Phase and gain characteristics of a 2P2Z compensator......................................................................................................... 29
Figure 3-8. Phase and gain characteristics of a 3P3Z compensator......................................................................................................... 30
Figure 3-9. Representation of DF11...........................................................................................................................................................31
Figure 3-10. Representation of DF13.........................................................................................................................................................32
Figure 3-11. Representation of DF22.........................................................................................................................................................33
Figure 3-12. Representation of DF23.........................................................................................................................................................34
Figure 4-1. ADC transfer function.............................................................................................................................................................. 37
Figure 4-2. ADC full-scale range (FSR) unipolar.........................................................................................................................................37

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ti.comFigure 4-3. ADC full-scale range (FSR) differential.....................................................................................................................................38
Figure 4-4. Quantization error of an ADC converter...................................................................................................................................39
Figure 4-5. Fundamental and harmonics in VRMS.................................................................................................................................... 41
Figure 4-6. Fundamental and harmonics in dBc........................................................................................................................................41
Figure 4-7. Settling time and conversion accuracy....................................................................................................................................44
Figure 4-8. ADC noise................................................................................................................................................................................ 45
Figure 5-1. Comparator diagram............................................................................................................................................................... 48
Figure 5-2. Comparator hysteresis............................................................................................................................................................ 48
Figure 5-3. Comparator input to output switching delay........................................................................................................................... 49
Figure 6-1. Signal chain............................................................................................................................................................................. 56
Figure 6-2. Direct memory access............................................................................................................................................................. 57
Figure 6-3. CPU interrupt flow................................................................................................................................................................... 58
Figure 7-1. Quadrature signal.................................................................................................................................................................... 64
Figure 8-1. PWM output.............................................................................................................................................................................67
Figure 8-2. PWM duty cycle.......................................................................................................................................................................67
Figure 8-3. PWM resolution....................................................................................................................................................................... 68
Figure 8-4. PWM deadband.......................................................................................................................................................................70
Figure 9-1. DAC transfer function.............................................................................................................................................................. 73
Figure 9-2. DAC midpoint offset error........................................................................................................................................................ 74
Figure 9-3. DAC gain error......................................................................................................................................................................... 75
Figure 9-4. DAC xero-code error................................................................................................................................................................75
Figure 9-5. DAC full-scale error..................................................................................................................................................................76
Figure 9-6. DAC DNL................................................................................................................................................................................. 77
Figure 9-7. DAC INL................................................................................................................................................................................... 77
Figure 9-8. DAC linear range......................................................................................................................................................................79
Figure 9-9. DAC settling time..................................................................................................................................................................... 80
Figure 9-10. DAC load regulation...............................................................................................................................................................80
Figure 10-1. Pole gain and phase.............................................................................................................................................................. 86
Figure 10-2. Zero gain and phase.............................................................................................................................................................. 88

List of Tables
Table 2-1. Characteristics of a good control system................................................................................................................................... 7
Table 2-2. Rise and peak time for systems................................................................................................................................................ 12
Table 2-3. Damping ratios based on classification.................................................................................................................................... 14
Table 2-4. Filter types.................................................................................................................................................................................17
Table 2-5. First order filters........................................................................................................................................................................ 19
Table 2-6. Second order filters................................................................................................................................................................... 20
Table 3-1. Tuning parameter effect on the gain shape...............................................................................................................................28
Table 4-1. LSB voltage vs. resolution and reference voltage.....................................................................................................................39
Table 4-2. Conversion accuracy achieved after a specified time.............................................................................................................. 44
Table 4-3. Time required to settle to a specified conversion accuracy......................................................................................................44
Table 5-1. Comparator inputs to output.....................................................................................................................................................48
Table 6-1. Primitive data types...................................................................................................................................................................52
Table 6-2. Multiplier prefixes and abbreviations........................................................................................................................................ 52
Table 6-3. ASCII table................................................................................................................................................................................ 52
Table 6-4. Real-time control processor - characteristics........................................................................................................................... 55
Table 6-5. Memory types........................................................................................................................................................................... 57
Table 8-1. Common PWM resolution values..............................................................................................................................................69
Table 9-1. DAC error correlation................................................................................................................................................................ 78
Table 9-2. Unit conversions for error.......................................................................................................................................................... 78
Table 9-3. Straight line end points for INL..................................................................................................................................................79
Table 10-1. Important Laplace transform pairs.......................................................................................................................................... 83
Table 10-2. Response portions.................................................................................................................................................................. 84
Table 10-3. Examples of common gain values and dB equivalent............................................................................................................ 85
Table 10-4. Z-Transform Properties........................................................................................................................................................... 90

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System Design

ti.comSystem Design
Control •Feedback control •Dynamic systems •System stability •Timing requirements •Discrete Time Domain •Filters •Notes •

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System Design

ti.comControl"A control system is considered to be any system which exists for the purpose of regulating or controlling the flow ofenergy, information, money, or other quantities in some desired fashion" - W.L.Brogan, Modern Control Theory, 1991.
r(t)

y(t)

Control
System

r(t)

y(t)

t

t

Figure 1. Control system.

The principle objective of control is to force the system output to accurately follow an input.
Table 1. Characteristics of a good control system.
Term

Definition/Explanation

Stability

Stability is the quality, state, or degree of being stable. In order for asystem to be stable, the gain and phase margins need to be positive.

Steady State Accuracy

How close the output is to the desired input. The closer the output is tothe input the better the steady state accuracy is.

Satisfactory Transient Response

A transient response shows how the system behaves when it is takenout of equilibirum. Ideally, the system should not deviate from the steadystate.

Satisfactory Frequency Response

A frequency response displays the output of a system in terms ofmagnitude and phase as a function of frequency.

Reduced Sensitivity to Disturbances

Disturbance in control systems signify any unwanted or unexpected
inputs that alter the system's output which cause an increase in thesystem error.

Open loop versus closed loop
There are two types of control systems, open and closed. Within an open control system, the control action is notdependent on external influences nor does it incorporate feedback to alter the output response. In contrast, within aclosed loop system the control action is indeed dependent on external influences and utilizes feedback to adapt andachieve the desired results.

r

e

u

F

ym

G

y

H

Figure 2. Closed loop system.

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System Design

ti.comWhere
F = controller transfer function
G = plant transfer function
H = sensor transfer functionr = reference inpute = error signal
u = control effort
y = output

ym = feedback
Equations:

Error equatione = r − Hy(1)

y = FGe(2)

y 1 + FGH = FGr(3)

L = FGH(4)

Output Equation

Error and output equations combined

Open loop transfer function

Closed loop transfer functionyFGr = 1 + FGH(5)Feedback control
Feedback is when any part of the system’s output is brought back to the input and utilized as part of the input to thesystem. It is sometimes referred to as “closed loop control”. Feedback control can be categorized as one of the mostimportant segments within any closed loop system since it improves the performance of the system.
When properly applied feedback can:• Reduce or eliminate steady state error characteristics.
• Reduce the sensitivity of the system to parameter variations.
• Change the gain or phase of the system over some desired frequency range.
• Reduce the effects of load disturbance and noise on system performance.
• Cause an unstable system to become stable.

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ti.com• Linearize a non-linear component.
Error ratio
The error ratio (sensitivity function) determines the loop sensitivity to disturbance.
e11
r = 1 + FGH = 1 + L = S(6)Dynamic systems
First order system
Equations

1st order differential equation
τy′ t + y t = u t(7)Transfer function of 1st order systemy s= sτ 1+ 1
u s(8)Response of system
y t = L−1 sτ 1+ 1 u s(9)Response of system following a unit step responsety t = 1 − e− τ

(10)

Where

τ = time constant of the system
y t = output functionu t = input function

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ti.comFigure 3. Unit step response of a 1st order system (τ=1).

Second order system
Equations
2nd order differential equationy″ t + 2ζωny′ t + ω2ny t = ω2nu t(11)Transfer function of 2nd order system
ω2
y s
n
= 2
u s
s + 2ζωns + ω2n(12)Characteristic equation
s2 + 2ζωns + ω2n = 0(13)

s = − ζωn ± ωn ζ2 − 1(14)Poles of a linear 2nd order system

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ti.comUnit step response of an under-damped 2nd order systemω

y t = 1 − ωn e−σtsin ωdt + φ
φ = cos−1 ζ

(15)

d

(16)

Where

y t = output functionu t = input function

ωn = un-damped natural frequency
ωd = damped natural frequency
ζ = damping ratio

Figure 4. Unit step response of an under-damped 2nd order system.

System stability
Stability is one of the most important requirements when designing a control system. If the closed loop transfer
function of a system is known then the stability of the system can be observed through the denominator of the transfer
function in factored form (characteristic equation) by identifying if the real parts are positive or negative. However, inorder to accurately measure how stable a system is, the gain and phase margins are used. Both of these margins are
obtained through the Bode plot of the frequency response. Gain and Phase margins define the amount of change inopen-loop gain and phase that is required to make a closed-loop system stable.

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ti.comFor a system to be stable, both the gain and phase margins need to be positive.
Gain margin

The gain margin is the difference between 0 dB and the gain at the phase cross-over frequency that gives a phase of−180°. If the gain margin GH jω

at the frequency of ∠GH jω = − 180 ° is greater than 0 dB (positive gain margin),then the closed-loop system is stable.
Phase margin

The phase margin is the difference in phase between −180° and the phase at the gain cross-over frequency that gives
a gain of 0 dB. If the phase ∠GH jω at the frequency of GH jωclosed-loop system is stable.

= 1 is greater than −180° (positive phase margin), thePhase margin is related to the damping of a second-order system through the following equation:PMζ = 100

(17)

Where

ζ = damping ratio

PM = phase margin

Timing requirements
Peak/rise time
Table 2. Rise and peak time for systems.
System Order
1st Order

System Classification

Rise Time %Peak Time
Usually categorized as 2.2 τ, whereτ is the time constant-

10 - 90

2nd Order

Under-damped

0 - 100

Time at which the step response
reaches its maximum

2nd Order

Over-damped

10 - 90

Peak time is not defined

Equation
Peak Time
tp = ωπ β =
n

Where

π

(18)

ωn 1 − ζ2ζ = damping ratio

ωn = undamped natural frequency
Settling time

The settling time is the time required for a system to settle within a certain percentage of the input amplitude. For asecond order system, a settling time is desired in which the response remains within 2% of its desired value.

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ti.comDefinitions
Settling time of 1st order system
4τ

(19)

1
ts = σln δc(20)Settiling time of 2nd order systemωc = ωn(21)σ = ζωn(22)dDamping coefficient

Lograrithmic decrementxδ = ln x0(23)1

Tolerance fraction for underdamped systems (in most cases this is 0.02)cδ =1 − ζ2

(24)

Where

τ = time constant (time it takes for the step response to reach 63% of its final value)

x0 /x1 = the amplitudes of two successive peaks within a step response

ωn = un-damped natural frequency
ωd = damped natural frequency
ζ = damping ratio
OvershootOvershoot quantifies the amount the step response deviates from the ideal settling amplitude at the peak time.
Definitions
Peak response
Mp = 1 + exp−πζ
1 − ζ2(25)

Percentage of overshootP . O . = 100e−πζ/ 1 − ζ

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ti.comDamping ratioζ=PO−ln 100(27)PO
π2 + ln2 100

Damping

The dynamic behavior of a second order system is defined by the damping ratio and un-damped natural frequency.
Table 3. Damping ratios based on classification.
Damping Ratio

Roots

ζ>1

s = − ζωn ± ωns = − ωnζ=1Classification
ζ2 − 1s = − ζωn ± jωn 1 − ζ20<ζ<1s = ± jωnζ=0Over-damped
Critically damped
Under-damped
Un-dampedWhereζ = damping ratio

ωn = un-damped natural frequency
Delay

There are many types of delays that can be introduced within a control system, some are inherent to the system andsome are external.
Definitions
Delay in the time domainℒ f t−T(28)

e−sTf s(29)

Delay in laplace domain

Magnitude of delaye−iωT =cos ωT

Phase of delay2+ − sin ωT

2

=1

(30)

< e−iωT = tan−1 −sinωTcosωT = − ωT

(31)

The time delay will not affect the magnitude since the magnitude of a pure delay is always equal to one, no matter thefrequency of the input. However, the phase will get more and more negative as the frequency increases. If the phasebecomes negative then the system could become unstable.

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One way to compensate for a negative phase margin is to decrease the bandwidth but this will lead to slower
performance. Which is why time delay in a control loop is detrimental both to performance and stability.
Delay Type

Closed Loop Transfer Function with Delay
Included

SensorActuatoryFGr = 1 + FGe−sT

y
FG
−sT
r =e
1 + FGe−sT

Description
The sensor that measures the process output, y,delays passing on the measured value by T timeunits
The input can influence the plant without passing
through the delay

Where
e−sT = delay transfer function

Discrete Time Domain

Discrete time refers to variables as occurring at distinct, separate "points in time". A discrete-time signal is a time series
that consists of a sequence of quantities and is obtained by Figure 6 from a continuous-time signal at uniformly spaced
times.
Pros of Digital Control• High repeatability and reliability• Easy to prototype and make changes
Cons of Digital Control• Increased 'delay' in the feedback loop
• Lower performance compared to analog control

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ti.comDiscrete Time

Continuous Time

e(k)

u(k)

u(t)

F (z)

r(k)

Hold

G(s)

y(t)

ym(t)

ym(k)

Sampler

H(s)

r(k)
ym(k)
ym(t)

+

e(k)

u(k)

Sampler

F(z)

Hold

ym(t)

ym(t)

u(t)

±

ym(t)

ym(k)

t

t

t

t

Figure 5. Digital control system.

Definitions:• Sample: Signals represented as sequences of numbers.
• Sampling Period (T): The space between samples.
• Sampling Frequency (FT ): Inverse of the sampling period.
Amplitude

SampleTime
T

Figure 6. Sampling.

Note
In practice, continuous time signals are sampled using an ADC

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ti.comFilters
Definitions:• -3dB Frequency/Cutoff Frequency (f−3dB /fc ): The input frequency that causes the output signal to drop by -3dB
relative to the input signal. For a high-pass and low-pass filter there is only one -3dB frequency, but for band-pass,and band-stop there are two -3db frequencies, referred to as f1 and f2 within Table 4.

• Center Frequency (f0 ): This is a term that describes the central frequency that lies between the upper and lower
cutoff frequencies of band-pass and band-stop filters.

• Stopband Frequency (fS ): A particular frequency at which the attenuation reaches a specified value. For low-passand high-pass filters the frequencies beyond the stopband frequency are reffered to as the stopband. However, forpass-band or stop-band, and notch filters two stopbands exist.

• Bandwidth (β): The bandwidth is the width of the passband, and the passband is the band of frequencies that do notexperience significant attenuation when moving from the input of the filter to the output of the filter• Quality Factor (Q): The quality factor of a filter conveys its damping characteristics. In the time domain, damping
corresponds to the amount of oscillation in the system’s step response. In the frequency domain, higher Q
corresponds to more (positive or negative) peaking in the system’s magnitude response. For a band-pass, band-stop,and notch filter, Q represents the ratio between the center frequency and the -3dB bandwidth, Q = f 0 / f 2 − f 1

Filter Types

Table 4. Filter types.
Type

Definition

Response Curve

Gain
Stopband–3 dB

High-Pass (HPF)

Removes low frequencies andretains high frequencies

PassbandFrequencyfs

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fc

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ti.comType

Definition

Response Curve

Gain

–3 dB
Low-Pass (LPF)

Removes high frequencies andretains low frequencies

Passband

StopbandFrequency
fc

fs

Gain
passbandpassband-3dB
Band-Stop (BSF)

Removes an interval of frequencies
with a band, retains others

stopbandbandwidth

Frequency
f1

f0

f2

Gain
stopbandstopband-3dB
Band-Pass (BPF)

Retains an interval of frequencies
with a band, removes others

Passbandbandwidth

Frequency
f1

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f0

f2

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ti.comFilter Orders

Filters can be of first order, second order, third order, and so forth. This is defined by the number of poles found within
the Section 10.2. This chapter will focus on 1st and 2nd order filters. Figure 7 shows the difference on a magnitude plot
between a 1st (red curve) and 2nd order filter (blue curve).
Gain (dB)0-3dB roll-off-20-20 dB/Decade-6dB roll-off-40-40 dB/Decade
-60

-80
-3

Log (f/f3dB)
-2

-1

0

1

2

3

4

Figure 7. Filter response curves.

Definitions:• Passive: Only includes passive components such as resistors, capacitors, and inductors.
• Active: Includes active components such as op-amps while still utilizing resistors and capacitors.
Table 5. First order filters.
Filter Type

Active/Passive

CircuitGain (Vout/Vin)

R

Low-Pass

Passive

VIN

C

XC
2
R + XC2

VOUT

GND
C

High-Pass

Passive

R

VIN

R
R2 + XC2

VOUT

GND
R

Low-Pass

ActiveReal-Time Control Reference Guide+
AV = 1
–
VIN

C
VOUT

19

XC
=1
2
R + XC2

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ti.comFilter Type

Active/Passive

CircuitGain (Vout/Vin)

C

High-Pass+
AV = 1–

Active

VIN

VOUT

R

R
=1
2
R + XC2

Where
Transfer function of 1st order low pass filterωC
H s = s+ω(32)

CTransfer function of 1st order high pass filter
H s = s +sω(33)

1
f C = 2πRC

(34)

C

Cutoff frequency

ωC = 2πf C(35)

1
Xc = 2πfC(36)

Capacitive reactance

Table 6. Second order filters.
Filter Type

Active/Passive

Circuit
R1

Low-Pass

Passive

R2

C1

VIN

C1

High-Pass

Passive

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C2

VOUT

1 n
where n is the number
2of stages

C2

R1

VIN

Gain (Vout/Vin)

R2

VOUT

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ti.comFilter Type

Active/Passive

CircuitGain (Vout/Vin)

C1

R1

Low-Pass

R2
+
AV
–

Active
C2

VIN

VOUT
RB

RA

1+

R1
C1

High-Pass

C2

RA
RB

+
AV
–

Active
R2

VIN

VOUT
RB

RA

Where
Transfer function of 2nd order low pass filterω 2C
H s = 2s + 2ω s + ω 2
C

(37)

C

Transfer function of 2nd order high pass filter2s
H s = 2s + 2ωCs + ωC2(38)

1
f C = 2πRC

(39)

Cutoff frequency (same capacitor and resistor values)

ωC = 2πf C(40)

Cutoff frequency (different capacitor and resistor values)
fC =1
2π R1R2C1C2(41)

ωC = 2πf C

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ti.comNotes

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Controllers

ti.comControllers
Linear PID •Linear PI •Nonlinear PID •2P2Z •
3P3Z •
Direct form controllers •Notes •

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Controllers

ti.comLinear PID

Linear Proportional Integral Derivative (PID) controllers calculate an error value, e(t), based on the set point and theprocess variable, and apply a correction based on a proportional, integral, and derivative term. A PID controller is aparticular case of a 2P2Z controller, where A1 = -1 and A2 = 0.
Term

Description

Component

Proportional

The proportional component depends only on the
difference between the setpoint and the process variable

Integral

The integral component sums the error term over time,
giving a complete controller error history up to the present
time. This effectively causes an increase over time unlessthe error is zero, so the effect is to drive the steady-state
error to zero.

u t = Kpe t

Derivative

The differential component causes the output to decrease
if the process variable is increasing rapidly. The derivative
response is proportional to the rate of change of theprocess variable.

tu t = Ki∫0 e τ dτu t = Kdde t
dt

Proportional:
Where
e t = error value

Kp = proportional gain
Ki = integral gain

Kd = derivative gain

Parallel Linear PID

Figure 8. Parallel form linear PID controller.

Real-Time Control Reference Guide

24

October 2021

Controllers

ti.comWherer = input
y = feedbacke = erroru = output

Kp = proportional gain
Ki = integral gain

Kd = derivative gain
Series Linear PID

Figure 9. Series form of linear PID controller.

Wheree = erroru = output

Kp = proportional gain
Ki = integral gain

Kd = derivative gain
PID equation

Control law for PIDtde t

u t = Kpe t + Ki∫0 e τ dτ + Kd dt

(43)

Where

Kp = proportional gain
Real-Time Control Reference Guide

25

October 2021

Controllers

ti.comKi = integral gain

Kd = derivative gain

Figure 10. PID control action.

Linear PI
Linear proportional integral controllers are like linear PID controllers, but only have two tuning parameters, a proportionalterm and an integral term.
EquationControl law for linear PItu t = ubias + Kpe t + Ki∫0 e t dt

(44)

Where

ubias = controller bias set by the error when the controller is switched from manual to automatic mode

Kp = proportional gain
Ki = integral gaine t = error value

Real-Time Control Reference Guide

26

October 2021

Controllers

ti.comNonlinear PID

A nonlinear proportional integral derivative (Nonlinear PID) controller utilizes a power function to implement the control
law. The NLPID is an adaptation of the linear PID in which a non-linear law based on a power function is placed in series
with each path.
P-termnon-linear block

V4

I-termnon-linear block

V5

D-termnon-linear block

V6

V1
+

Pre-conditioning
block

r(k)
±

V2
V3

y(k)

Figure 11. Nonlinear PID input architecture.

Tuning parameter
Each nonlinear block shapes the servo error according to a power function law in which the normalized input (the servo
error) is raised to the power of an adjustable tuning parameter, α . The tuning parameter determines the degree andOutputdirection of the gain shape.

Servo Error

Figure 12. Nonlinear control law input-output plot.

Real-Time Control Reference Guide

27

October 2021

Controllers

ti.comTable 7. Tuning parameter effect on the gain shape.
Parameter

Value

Effectαp<1Smaller gain as error is large, not sensitive tosmall error.

>1

Higher gain when error is large, higher gain whenerror is small and by that more sensitive to smallchanges.

αi-1 < αi < 0αpαd > 1αdSolves integral windup problem by reducing the
integral action when error is large.
Makes the differential gain small when the error
is small which results in less sensitivity to noise.

To prevent undesired results, the solution is to define an input range covering the origin over which the gain is held
constant. The gain in this region is chosen to ensure that linear and nonlinear curves intersect precisely at theirboundaries, resulting in a smooth, glitch-free transition from one region to the other.
EquationsNonlinear control law
y x, α, δ =αx sign x , when x ≥ δδα − 1x ,(45)

when x < δ

Proportional error expression
ep = e(46)

ei = edt(47)d
ed = dte(48)

u = Kpy ep, αp, δp + Kiy ei, αi, δi + Kdy ed, αd, δd(49)Integral error expression

Derivative error expression

Reconstructed nonlinear control law

Where

x = input
y = output

α = tuning parameterδ = logarithmic decrement
K = controller gain

Real-Time Control Reference Guide

28

October 2021

Controllers

ti.comFigure 13 shows the linear and nonlinear regions for a tuning parameter less than one. Notice that the linear gain is
independent of the input x, so it does not need to be computed each time the controller runs. The linear gain is fixed foreach path and needs to only be recomputed when either of the nonlinear parameters in that path is adjusted.
y

-¨
x
¨

Figure 13. Nonlinear PID linearized region.

2P2Z
The 2-Pole/2-Zero (2P2Z) compensator is a filter which introduces a specific gain and phase boost into the system
considering two poles and two zeros.

Figure 14. Phase and gain characteristics of a 2P2Z compensator.

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October 2021

Controllers

ti.comEquationTransfer function of 2P2Z compensatorsωp0 1 + wz1
Hc s = KDC s
1 + ws
P2

(50)

3P3Z

The 3-Pole/3-Zero (3P3Z) compensator is a filter that introduces a specific gain and phase boost into the system
considering three poles and three zeros.

Figure 15. Phase and gain characteristics of a 3P3Z compensator.

EquationTransfer function of 3P3Z compensatorsωp0 1 + wz1
1 + wsP2

Hc s = KDC s

Real-Time Control Reference Guide

1 + ws
z2
s
1+ w
P3

(51)

30

October 2021

Controllers

ti.comDirect form controllers
DF11

The first order direct form 1 (DF11) compensator implements a first order, or “simple lag” type frequency response.
e(k-1)
e(k)

Z-1
d1

x

b0

b1

v2

x

v3

v4
+

+

u(k)

v6
v5
-a1

x

d2
u(k-1)

Z-1

Figure 16. Representation of DF11.

Equations
General form of discrete time first order transfer function
F z =b0 + b1z−1
1 + a1z−1(52)Difference equationu k = b0e k + b1e k − 1 − a1u k − 1

Real-Time Control Reference Guide

(53)

31

October 2021

Controllers

ti.comDF13

The third order direct form 1 (DF13) compensator is a common type of discrete control structure used to implement a
control law of dynamical system model specified either as a pole-zero set, or as a rational polynomial in z (a discrete
time transfer function). The DF13 controller uses two, three-element delay lines to store previous input and output datarequired to compute u k .
e(k)

Z-1

x

b0

Z-1

Z-1

x

b1

+

x

b2

v1

v0

x

b3

v3

v2

+

v7

d3
e(k-3)d2e(k-2)d1e(k-1)

d0

+

u(k)
d4

+

v5

v6

v4
-a3

x

-a2

x

Z-1
u(k-3)
d7

-a1

x

Z-1
u(k-2)
d6

Z-1
u(k-1)
d5

Figure 17. Representation of DF13.

Equations
General form of a third order transfer function
F z =b0 + b1z−1 + b2z−2 + b3z−3
1 + a1z−1 + a2z−2 + a3z−3(54)

Difference equationu k = b0e k + b1e k − 1 + b2e k − 2 + b3 k − 3 − a1u k − 1 − a2u k − 2 − a3u k − 3

Real-Time Control Reference Guide

32

(55)

October 2021

Controllers

ti.comDF22

The second order direct form 2 (DF22) compensator is sometimes referred to as a “bi-quad” filter, and is commonly used
in a cascaded chain to build up digital filters of higher order.
b0

e(k)

v0

v7

x

+

u(k)

x1

Z-1
b1

-a1
x1d

x

v1

v5
v3

+

x2

x

v6

Z-1
b2

-a2
x2d

x

v2

+

v4

x

Figure 18. Representation of DF22.

Equations
Transfer function of second order discrete time compensatorF z =b0 + b1z−1 + b2z−2
1 + a1z−1 + a2z−2(56)

Difference Equationu k = b0e k + b1e k − 1 + b2e k − 2 − a1u k − 1 − a2u k − 2

Real-Time Control Reference Guide

33

(57)

October 2021

Controllers

ti.comDF23
The third order direct form 2 (DF23) compensator is similar in all respects to the DF22 compensator.
e(k)

b3

x

x

b2

v6

v4
x3d

+

x3

Z-1

x

x2

Z-1

v1
x1d

+

v5

-a2

x

b0

v2
x2d

+

v7

-a3

x

b1

x1
Z-1

+

u(k)

v3

x

-a1

x

Figure 19. Representation of DF23.

EquationControl law equationu k = b0e k + b1e k − 1 + b2e k − 2 + b3 k − 3 − a1u k − 1 − a2u k − 2 − a3u k − 3

Real-Time Control Reference Guide

34

(58)

October 2021

Controllers

ti.comNotes

Real-Time Control Reference Guide

35

October 2021

ADC

ti.comADC
ADC definitions •ADC resolution •Quantization error of ADC •Total harmonic distortion (THD) •AC signals •DC signals •Settling time and conversion accuracy •ADC system noise •Notes •

Real-Time Control Reference Guide

36

October 2021

ADC

ti.com
ADC definitions
Resolution = n

The number of bits used to quantify the input

Number of codes = 2n

The number of output code combinations

Full-scale range input = FSR

Sets the converter input range and the LSB voltage

LSB = FSR / 2n

The voltage step size of each LSB

Full-scale input voltage = (2n – 1) • 1LSB

Full-scale input voltage of the analog-to-digital converter (ADC)

Full-scale output code = 2n – 1

Largest code that can be readTransfer function: Output Code = FLOOR [VIN / (FSR/2n )]Relationship between input voltage and output code

Full-scale code = 4095
111111111111
111111111110
Number of Codes = 2n111111111101
111111111100
111111111011
111111111010

000000000101
000000000100
000000000011
000000000010
000000000001

Full-scale voltage= 3.0-1

1LSB = 732 µV

3.0

3.0-1

3.0-3

Input voltage (V)

3.0-2

0.0+3

0.0+2

0.0
Resolution= 12 bits

0.0+1000000000000
Full-scale
range = 3.0= 3 V/4096 = 732 µV

Figure 20. ADC transfer function.

ADC resolution
ADC resolution for unipolar
A/D converter inside the MCU
3VDigitalBus

VREFHIFSR
0 to 3 V

ADC
12 bits
VREFLO
GND

Figure 21. ADC full-scale range (FSR) unipolar.

Real-Time Control Reference Guide

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ADC

ti.comFull-scale range (FSR) unipolar equations
Full Scale Range
FSR = VREFHI − VREFLO(59)

1LSB = FSRn(60)

One Least Significant Bit

Where

2

FSR = full-scale range
PGA = PGA gain
1LSB = one least significant bit or resolution of the data convertern = resolution number of bits
VREF = reference voltage
Example calculation for the circuit above
2.5 V
1LSB = FSR
N =12 = 610.35 μV
2

2

ADC resolution for differential signals
A/D converter inside the MCU
3VDigitalBus

ADCIN_P

FSR
0 to 3 V

VREFHI
VREF/2

SE to DIADC
16 bits
VREFLOADCIN_N

GND

Figure 22. ADC full-scale range (FSR) differential.

Where
FSR = full-scale range
1LSB = one least significant bit or resolution of the data convertern = resolution number of bits
VREFHI = reference voltage high
VREFLO = reference voltage low

Real-Time Control Reference Guide

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ADC

ti.comResolution voltage vs. full-scale range
Table 8. LSB voltage vs. resolution and reference voltage.
Resolution

FSR (Full-Scale Range)
2.5 V

3V

3.3V

8

9.67 mV

11.7 mV

12.9 mV

10

2.44 mV

2.93 mV

3.222 mV

12

610 µV732 µV

806 µV14152.5 µV

183 µV

201 µV16

38.14 µV

45.77 µV

50.35 µV

18

9.53 µV

11.44 µV

12.58 µV

202.384 µV

2.861 µV

3.147 µV

22

596 nV715 nV787 nV24

149 nV179 nV

196 nV

Quantization error of ADC

000000000101
000000000100
000000000011
000000000010
000000000001
000000000000+½ LSB–½ LSB

Figure 23. Quantization error of an ADC converter.

Quantization error
The error introduced as a result of the quantization process. The amount of this error is a function of the resolution of theconverter. The quantization error of an ADC converter is ½ LSB. The quantization error signal is the difference between
the actual voltage applied and the ADC output (Figure 23). The RMS of the quantization signal is RMSNoise = 1 LSB.
12Signal-to-noise ratio (SNR) from quantization noise only
MaxRMSSignal =FSR 2

RMSNoise = 1 LSB

212MaxRMSSignal
SNR = RMSNoise =N−1= 1 LSB × 2
2

1 LSB × 2N − 1
1 LSB

Real-Time Control Reference Guide

12

(61)
(62)

2

= 2N − 1 6

(63)

39

October 2021

ADC

ti.com6

SNR dB = 20log SNR = 20log 2 N + 20log 2(64)

SNR dB ≈ 6.02N + 1.76

(65)

Where

FSR = full-scale range of the ADC converter
1LSB = the voltage of 1LSB,VREF/2n
N = the resolution of the ADC converter
MaxRMSSignal = the RMS equivalent of the ADC’s full-scale input
RMSNoise = the RMS noise from quantization
SNR = the ratio of RMS signal to RMS noise
ExampleWhat is the SNR for an 8-bit ADC converter with 5 V reference, assuming only quantization noise?
Answer
SNR = 2N − 1 6 = 28 − 1 6 = 314(66)

SNR(dB) = 20log(314)

SNR(dB) = 6.02(8) + 1.76 = 49.9 dB

Total harmonic distortion (THD)
Total harmonic distortion (VRMS)
22
2
V2
2 + V3 + V4 + . . . + Vn
RMSDistortion
× 100
THD % = MaxRMSSignal
× 100 =V
RMSDistortion
THD dB = 20log MaxRMSSignal

(67)

1

(68)

Where

THD = Total Harmonic Distortion, the ratio of the RMS distortion to the RMS signal
RMSDistortion = the RMS sum of all harmonic components
MaxRMSSignal = the RMS value of the input signal
V1 = the fundamental, generally the input signal
V2, V3, V4, …Vn = harmonics of the fundamental

Real-Time Control Reference Guide

40

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ADC

ti.comFigure 24. Fundamental and harmonics in VRMS.

Total harmonic distortion (dBc)
D2

D3

D4

Dn

THD dBc = 10log 10 10 + 10 10 + 10 10 + … + 10 10

(69)

Where

THD = Total Harmonic Distortion. The ratio of the RMS distortion to the RMS signal.
D1 = the fundamental, generally the input signal. This is normalized to 0 dBc.
D2, D3, D4, …Dn = harmonics of the fundamental measured relative to the fundamental

Figure 25. Fundamental and harmonics in dBc.

Real-Time Control Reference Guide

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October 2021

ADC

ti.comExampleDetermine THD for the example above.
Answer
THD dBc = 10 log 10−92
10

THD dBc = − 74.76 dB

+ 10

−75
10

+ 10

−95
10

+ … + 10−110
10AC signals

Signal-to-Noise and Distortion (SINAD)
MaxRMSSignal
RMSNoise2 + RMSDistortion2

SINAD dB = 20log
SINAD dB = − 20log

10−SNR dB
10

+ 10

(70)

THD dB
10(71)

Effective Number of Bits (ENOB)ENOB =

Where

SINAD dB − 1.76dB
6.02

(72)

MaxRMSSignal = the RMS equivalent of the ADC’s full-scale input
RMSNoise = the RMS noise integrated across the ADC converters
RMSDistortion = the RMS sum of all harmonic components
SINAD = the ratio of the full-scale signal-to-noise ratio and distortion
THD = Total harmonic distortion. The ratio of the RMS distortion to the RMS signal.
SNR = the ratio of RMS signal to RMS noise
ExampleCalculate the SNR, THD, SINAD and ENOB given the following information:
MaxRMSSignal = 1.76VRMSVRMS RMSDistortion = 50 μVRMS
RMSNoise = 100 μVRMS
Answer
1.76 V

SNR dB = 20log 100 μVRMS
50 μV

RMS

THD dB = 20log 100 μVRMS

RMS

Real-Time Control Reference Guide= 84.9 dB= − 90.9 dB
42

October 2021

ADC

ti.com
SINAD dB = 20log
SINAD dB = − 20log

1.76 VRMS22100 μVRMS + 50 μVRMS

10−84.9 dB10

− 1.76 dB
ENOB = 83.9 dB6.02= 13.65+ 10= 83.9 dB−90.9 dB
10

= 83.9 dB

DC signals
N

2
NoiseFreeResolution = log2 PeaktoPeakNoiseinLSB

(73)

N

2
EffectiveResolution = log2 rmsNoiseLSB(74)

EffectiveResolution ≈ NoiseFreeResolution + 2.7(76)

PeaktoPeakNoiseinLSB ≈ 6.6 × rmsNoiseLSB

(75)

Note

The maximum effective resolution is never greater than the ADC resolution. For example, a 24-bit converter
cannot have an effective resolution greater than 24 bits.

ExampleWhat is the noise-free resolution and effective resolution for a 24-bit converter assuming the peak-to-peak noise is 7
LSBs?
Answer24

NoiseFreeResolution = log2 27= 21.2

EffectiveResolution = log2 27= 23.924

6.6

EffectiveResolution = 21.2 + 2.7 = 23.9

Real-Time Control Reference Guide

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ADC

ti.comSettling time and conversion accuracy
Time constant =

R
VIN

= RC

VIN A/DC

Figure 26. Settling time and conversion accuracy.
Table 9. Conversion accuracy achieved after a specified time.
Settling Time in Time Constants(NTC)

Accuracy in Bits (N)Settling Time in Time Constants(NTC)

Accuracy in Bits

1

1.44

10

14.43

2

2.89

11

15.87

3

4.33

12

17.31

4

5.77

13

18.76

5

7.21

14

20.20

6

8.66

15

21.64

7

10.10

16

23.08

8

11.54

17

24.53

9

12.98

18

25.97

Where
N = the number of bits of accuracy the RC circuit has settled to after NTC number of time constants
NTC = the number of RC time constants. Where one time constant equals R∙C.
Note
For a FSR step. For single-ended input ADC with no PGA front end, FSR (full-scale range) = VREF.
Table 10. Time required to settle to a specified conversion accuracy.
Settling Time in Time Constants(NTC)

Accuracy in Bits (N)Settling Time in Time Constants(NTC)

Accuracy in Bits

8

5.5

17

11.78

9

6.24

18

12.48

10

6.93

19

13.17

11

7.62

20

13.86

12

8.32

21

14.56

13

9.01

22

15.25

14

9.70

23

15.94

15

10.40

24

16.64

16

11.04

25

17.33

Real-Time Control Reference Guide

44

October 2021

ADC

ti.comWhere
NTC = the number of time constants required to achieve N bits of settling. Where one time constant equals R∙C.
N = the number of bits of accuracy
Note
For a FSR step. For single-ended input ADC with no PGA front end, FSR (full-scale range) = VREF.

ADC system noise
Reference
V nRef
V nT

V nAmpV nADCAMP

SNRtotal*

ADC

Figure 27. ADC noise.
VFSR_RMS =VFSR × 0.707
2

SNRADC = 20 × log
VnADC =
VnT =

Where

VFSR_RMSVnADC

VFSR_RMSSNRADC
10
20

VnADC

2

(77)

+ VnAmp

2

(78)
(79)

+ VnRef

2(80)

VFSR = the ADC full scale range from the data sheet
VFSR_RMS = This finds the maximum RMS amplitude of a sine wave applied to an ADC. Dividing the ADC full scale range
by 2 converts peak-to-peak to peak. Multiplying by 0.707 converts to RMS.
SNRADC = Data converter signal to noise ratio specification from data sheet
VnADC = Noise in volts RMS derived from the SNR equation. Converting noise to volts allows it to be combined withamplifier and reference noise.
VnAmp = Amplifier noise in volts RMS calculated or simulated using data sheet parameters
VnRef = Reference noise in volts RMS calculated or simulated using data sheet parameters
VnT = Total noise in volts RMS calculated by combining ADC, amplifier, and reference noise

Real-Time Control Reference Guide

45

October 2021

ADC

ti.comNotes

Real-Time Control Reference Guide

46

October 2021

Comparator

ti.comComparator
Basic operation •Offset and hysteresis •Propagation delay •Notes •

Real-Time Control Reference Guide

47

October 2021

Comparator

ti.comBasic operation
Table 11 gives the expected behavior of the comparator output based on the state of the inputs.
Comparator Inside the MCU
V+
VIN+

+
Output

VIN––
V–

Figure 28. Comparator diagram.
Table 11. Comparator inputs to output.
Inputs Condition

OutputIN+ > IN-

HIGH (V+)

IN+ = IN-

Indeterminate(chatters - see Hysteresis)

IN+ < IN-

LOW (V-)

Offset and hysteresis
The basic comparator will have an offset error that is the internal offset between the VIN+ and VIN- inputs. This error term
needs to be added to the ideal threshold voltage to determine when the comparator output will change vs a change in its
inputs.
The basic comparator configuration may also oscillate or produce noisy "chatter" output if the applied differential input
voltage is near the comparator's offset voltage. This usually occurs when the input signal is moving very slowly acrossthe switching threshold of the comparator.
This problem can be prevented by the addition of hysteresis or positive feedback. The hysteresis transfer curve is shownin Figure 29. This curve is a function of three components: VTH, VOFF, VHYST.

VTH + VOFF – (VHYST / 2)

VTH + VOFF

VTH + VOFF + (VHYST / 2)

Figure 29. Comparator hysteresis.

Real-Time Control Reference Guide

48

October 2021

Comparator

ti.comWhere:• VTH = the actual set voltage or threshold trip voltage• VOFF = internal offset voltage between VIN+ and VIN-. This voltage is added to VTH to form the actual trip point at
which the comparator must respond to change output states• VHYST = the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise.

Propagation delay
There is a delay between when the input crosses the reference voltage and the output responds. This is called the
propagation delay. Propagation delay can be different based on the rate of change of the inputs. Propagation is mostaccurately measured by using input signals with a fast ramp such as a digital or square wave.
MCU
V+
VREF + VOFF + (VHYST / 2)

VIN+

Output

–

Input
VIN

VREF

VREF

+

V–

–

VREF - VOFF - (VHYST / 2)
tpLH

tpHL

“1”

Output“0”

Figure 30. Comparator input to output switching delay.

Real-Time Control Reference Guide

49

October 2021

Comparator

ti.comNotes

Real-Time Control Reference Guide

50

October 2021

Processing

ti.comProcessing
Data representation •Central processing unit •Memory •Direct memory access (DMA) •Interrupts •Co-processors and accelerators •Notes •

Real-Time Control Reference Guide

51

October 2021

Processing

ti.comData representation
Table 12. Primitive data types.
Type

Default

Size

Boolean

False

1 bit

Byte

0

8 bits

Char

\u000

16 bitsShort

0

16 bitsInt

0

32 bitsLong

0

64 bits

Float

0.0f

32 bits

Double0.0d

64 bits

Note
Not all CPU architectures use the same bit counts to represent primitive data.
For example, C2000 has a 16-bit architecture and does not support 8-bit types. For a list of data types
supported by C2000 devices, see the TMS320C28x Optimizing C/C++ Compiler v21.6.0.LTS.
Note
The size of data pointers depends on the architecture.
Table 13. Multiplier prefixes and abbreviations.
MultiplierPrefixAbbreviation

109

Giga

G

106

Mega

M

Kilo

k

10−3

Milli

m

10−6

Micro

u

10−9

Nano

n

10−12

Pico

p

10−15

Femto

f

103

Table 14. ASCII table.
Binary

Oct

Dec

Hex

Chr

0100000

040

32

20

Space

0100001

041

33

21

!

0100010

042

34

22

"

0100011

043

35

23

#

0100100

044

36

24

$

0100101

045

37

25

%

0100110

046

38

26

&

0100111

047

39

27

'

0101000

050

40

28

(

Real-Time Control Reference Guide

52

October 2021

Processing

ti.comBinaryOct

Dec

0101001

051

41

29

)

0101010

052

42

2A

*

0101011

053

43

2B

+

0101100

054

44

2C

,

0101101

055

45

2D

-

0101110

056

46

2E

.

0101111

057

47

2F

/

0110000

060

48

30

0

0110001

061

49

31

1

0110010

062

50

32

2

0110011

063

51

33

3

0110100

064

52

34

4

0110101

065

53

35

5

0110110

066

54

36

6

0110111

067

55

37

7

0111000

070

56

38

8

0111001

071

57

39

9

0111010

072

58

3A

:

0111011

073

59

3B

;

0111100

074

60

3C

<

0111101

075

61

3D

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C

1000100

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D

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69

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E

1000110

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F

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G

1001000

110

72

48

H

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I

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4A

J

1001011

113

75

4B

K

1001100

114

76

4C

L

1001101

115

77

4D

M

1001110

116

78

4E

N

1001111

117

79

4F

O

1010000

120

80

50

P

1010001

121

81

51

Q

1010010

122

82

52

R

1010011

123

83

53

S

1010100

124

84

54

T

1010101

125

85

55

U

1010110

126

86

56

V

1010111

127

87

57

W

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53

Hex

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October 2021

Processing

ti.comBinary

Oct

Dec

Hex

1011000

130

88

58

X

1011001

131

89

59

Y

1011010

132

90

5A

Z

1011011

133

91

5B

[

1011100

134

92

5C

\

1011101

135

93

5D

]

1011110

136

94

5E

^

1011111

137

95

5F

_

1100000

140

96

60

`

1100001

141

97

61

a

1100010

142

98

62

b

1100011

143

99

63

c

1100100

144

100

64

d

1100101

145

101

65

e

1100110

146

102

66

f

1100111

147

103

67

g

1101000

150

104

68

h

1101001

151

105

69

i

1101010

152

106

6A

j

1101011

153

107

6B

k

1101100

154

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6C

l

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155

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6D

m

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156

110

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n

1101111

157

111

6F

o

1110000

160

112

70

p

1110001

161

113

71

q

1110010

162

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r

1110011

163

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s

1110100

164

116

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t

1110101

165

117

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u

1110110

166

118

76

v

1110111

167

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w

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170

120

78

x

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171

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y

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~

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Processing

ti.comCentral processing unit
CPU basics

A CPU executes all of the instructions within a program. The design of a CPU cannot be altered once it has been
manufactured. A CPU's performance is based on many factors and often times requires a benchmark analysis toproperly be evaluated. Multiple specifications need to be evaluated together to properly determine a CPU's performancesuch as the ones defined below.
Definitions:• Clock Frequency/Speed: A measure of the number of cycles the CPU executes per second (usually specified inmegahertz (MHz) or gigahertz (GHz)).
• Cycle: The amount of time of a singular clock pulse (inverse of the clock speed). Different CPU designs handle
instructions differently. Some instructions may require multiple cycles while others may be executed in less than acycle.
• MIPS: Maximum number of instructions that can be executed every cycle.
• MFLOP: Maximum number of floating point operations that can be executed every cycle.
CPU pipeline
A CPU pipeline describes the different processing elements that need to be completed either in parallel or sequential
order by the different stages of instruction execution. This is embedded in the design of the CPU. During the CPU
design, the goal is to optimize the performance of this pipeline by always keeping the different stages busy. The moreparallelism there is within the CPU's pipeline the more availability there is to perform multiple instructions at a time. A
common set of stages includes:• Instruction Fetch• Instruction Decode• Execution• Memory Access• Write Back
Characteristics of a real-time processor
Table 15 contains key characteristics that determine how good a processor is at performing a real-time control task. The
term "fast" is used as a relative term to indicate the best performance possible. The execution speed of a complex task
is determined by the number of CPU cycles needed to complete the constituent operations.
Table 15. Real-time control processor - characteristics.
Characteristic

Description

Fast at performing math operations

Math operations: MUL, ADD, SUB

Fast at trigonometric operations

Trigonometric operations: SIN, COS, ATAN, DIV

Fast at saturation operations

Saturation operations check for out of bounds conditions and if detected
the value is clamped or saturated

Contains deterministic execution

A real-time control application has a fixed amount of time to execute
algorithms, and if the time taken to perform the algorithms is deterministic(or known) it is easier to budget the available MIPS

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Processing

ti.comCharacteristic

Description

Fast access to peripheral registers

For example, reading sensor inputs (example: ADC) and writing to output
registers (example: EPWM)

Fast Interrupt Response

The processor needs to respond to periodic interrupt events with low
latency to satisfy real time deadlines

Floating-point operation capability

Floating-point operations are generally easier to use which make thecontrol algorithms more robust

32-bit and 64-bit data precision

A processor that can be scaled in precision based on the application is
ideal

Multicore Support

Having dual cores or more helps increase the amount of tasks that are
executed given a specified amount of time

Signal chain
A signal chain is an important part in evaluating a CPU's performance as it encompasses all of the key components fortask operation. Below are the different actions that comprise a signal chain.
• Latch or Respond to Interrupt - The trigger event is latched by hardware which in many real-time control applications
triggers ADC sampling upon which interrupt occurs and CPU responds to the interrupt by entering the ISR.
• Context Save - The CPU stores the state of the current process it is doing• Read Peripheral or Sensor - The CPU has to read the value that has been acquired by a peripheral or sensor*• Execute the control algorithm - Most of the time within an interrupt will be consumed by the control algorithm since
this tends to be the most math intensive portion and requires lots of CPU cycles• Write the output value - Once the output is calculated it is typically written to a control peripheral** = Efficiency in reading or writing to peripherals is a key aspect of a real-time processor. The bus architecture of a device
can influence how quickly the CPU can read/write peripherals and can impact processing times as typically control loops
will involve reading from and writing to peripherals.
Trigger Events Occurs

1
Latch andRespond to
Interrupt

2
Context Save

3
Read Sensor
Input

Sample4

5

Control
Algorithm

Write Output
OutputFigure 31. Signal chain.

MemoryAn important aspect to any real-time control microcontroller is the memory. Various memory types are described within
Table 16. There are many addressability options as well. Some processors have byte addressable memory while others
may have word addressability. Addressability is the smallest unit of content in memory that can be accessed by theCPU. The industry standard for 8-bit addressability is referred to as byte addressable. In contrast, word addressablerefers to anything that is not byte addressable. Additionally, some processors might have different word sizes for different
tasks.

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Processing

ti.comTable 16. Memory types.
Type

Description

FLASH

Flash is a type of nonvolatile memory (NVM). Flash is erased in units
called sectors (or blocks) and writes content (data or code) at the wordlevel. A wait-state is a delay experienced by the CPU when accessing aslower memory or interface. Content stored in Flash is not erased after a
microcontroller is powered down.

Random Access Memory (RAM)RAM is used to store data and other results that are created while a
microcontroller is at work. Content stored in RAM is erased after the
microcontroller is powered down.

Read Only Memory (ROM)ROM contains specialized tasks that will never change.

CACHE

Cache is smaller, faster memory, located closer to a processor core,
which stores copies of the content from frequently used main memory
locations. Usually, processors have many levels of cache memory. The
cache provides content storage and instructions to prevent the CPU fromwaiting for content to be retrieved from RAM. Typically, a processesor thatruns from cache needs to run at least 2x MHz faster than a processor
using a tightly coupled memory system. There can be unpredictabledelays when content from cache is refreshed.

Tightly Coupled Memory (TCM)

TCM is memory that is stored on-chip and never cached. This is useful forrunning code but more importantly to store critical content and as stackspace.

Direct memory access (DMA)
Direct Memory Access (DMA) is a feature that allows subsystems or peripherals to access RAM without intervention of
the CPU. This is a helpful feature for real-time control applications since it allows the CPU to work on other tasks ofthe control algorithm, while the DMA transfers data between address locations (both memory and register). The DMA is
not always restricted between RAM and other subsystems, but rather can be utilized from memory to memory. A DMA
transfer can be started by a peripheral or a software trigger. This capability increases data throughput and allows for amore efficient use of interrupts.

Data Access
CPU

MemoryBus
Peripherals

DMA
Controller

Data AccessFigure 32. Direct memory access.

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Processing

ti.comInterrupts

An interrupt is a response by the processor to an event that needs attention. The processor executes instructions thatare defined within the interrupt service routine (ISR) as soon as is capable, and then goes back to normal operationaltasks. Unlike idle loops where code waits for an event to occur, interrupts provide the opportunity to have non-idle code
loops that execute based on the CPU's availability and priority of tasks.
Instruction 1

ProgramFlow

Instruction 2

Instruction 3

Instruction 4Interrupt Occurs

Interrupt Instruction 1

Interrupt Instruction 2

Instruction 5

Program
Flow

Interrupt Handler
StartsInterrupt
ServiceRoutineInterrupt Instruction 3
Interrupt Handler
Stops

Instruction 6

Instruction 7

Instruction 8

Figure 33. CPU interrupt flow.

Interrupt latency is an important factor in understanding the response time of a real-time system. The typical methodby which interrupt latency of a system is assessed is the number of cycles it takes for the hardware to respond to aninterrupt and branch to the interrupt vector (hardware latch and respond). However, in a real-time application this is only
part of the response.

Co-processors and accelerators
Co-Processors
For optimized performance co-processors and accelerators are helpful. A co-processor is used to supplement thefunctions performed by the main CPU. This creates a model in which multi-threading is utilized. Tasks can be divided
across the CPUs depending on the functions to be implemented.

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Accelerators

Accelerators are intended to help the CPU perform certain tasks more efficiently by extending the capabilities of a CPU
through registers and instructions. The added efficiency can often times remove the need of additional co-processors.
Some common accelerators are presented below:• Trigonometric Math Unit: Accelerates several specific trigonometric math operations like sine, cosine, arc tangent,
divide, and square root.
• Cryptographic Unit: Accelerates encryption algorithms such as the data encryption standard (DES) symmetricencryption algorithm and the advanced encryption system (AES) symmetric encryption algorithm.
• Floating-Point Unit: Provides floating-point math support which alleviates scaling and saturation concerns.
• Complex Math Unit: Accelerates math operations like add, subtract, and multiply.

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Processing

ti.comNotes

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Encodersti.comEncoders
Encoder definitions •Types of encoders •Description of encoders •Absolute Vs incremental encoders •Notes •

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Encodersti.comEncoder definitions
Resolution

The number of measuring segments or units in one revolution of an encoder shaft or 1 in/mm of alinear scale. Encoder resolution is commonly measured in pulses per revolution (PPR) or lines per
revolution (LPR) for incremental encoders. For Absolute encoders it is measured in bits, for example
a 12-bit Absolute encoder has resolution of 212= 4096 counts per revolution.

Speed

Maximum speed at which the device can rotate without sustaining physical damage, often defined
as revolutions per minute (RPM).

Positional Accuracy

It is the maximum error of a reading, in arc seconds. One degree is 3600 arc seconds.

Absolute Encoder Codes

Binary, BCD or Gray format.

Incremental Encoder Signal Types

Quadrature - Refers to A and B channels that are 90o out of phase.
Single Channel - Unidirectional allowing one count per physical line.
Pulse & Direction - Direction channel may be combined with single-channel counting or muliple­
channel counting with quadrature.

Encoder output

The type of electrical signal that will be produced: Digital Square Wave, Analog Voltage, Analog
Current, Serial (RS232, RS422, and so forth.), Parallel (GPIB), Serial Synchronous Interface (SSI),
Ethernet, CANbus, and so forth.

Types of encoders
Position Encoders are used to obtain position, direction and speed information from machines in order to determine
the mechanical position of an object. This mechanical position is an "absolute position". They may also be used todetermine a change in position between the encoder and object as well. The change in position in relation to the object
and encoder would be an incremental change. Position Encoders are widely used in the industrial arena for sensing theposition of tooling and multi-axis positioning. There are many different types of encoders, but they basically fall into fourmain sensing techniques. Those being:• Mechanical• Magnetic• Optical• Electromagnetic
Within those categories, there are two differing encoder measurement types:• Absolute• Incremental (some incremental encoders are classified as quadrature encoders)
An encoder with an optical sensing type interprets data in pulses of light which can then be used to determine suchthings as position, direction and velocity. The shaft rotates a disc with opaque segments that represent a particularpattern. These encoders can determine the movement of an object for "rotary" or "shaft" applications while determining
exact position in "linear" functions. This encoder sensing technique can be used in various applications such as printers,
CNC milling machines and robotics.

Description of encoders
Linear encoders
The Linear Encoder uses a transducer to measure the linear distance between two points. These encoders can use
a rod or a cable that is run between the encoder transducer and the object that will be measured for movement. As
the object moves, the transducer's data collected from the rod or cable creates an output signal that is linear to theobject's movement. As the distance is measured, the Linear Encoder uses this information to determine the position of
the object.

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Encodersti.comAn example of where a linear encoder may be used is for a CNC milling machine where precise movement
measurements are required for accuracy in manufacturing. Linear Encoders can be "Absolute" or "Incremental".
Rotary encoders
A Rotary encoder collects data and provides feedback based on the rotation of an object or in other words, a rotating
device. Rotary Encoders are sometimes called "Shaft Encoders". This encoder type can convert an object's angular
position or motion based on the rotation of the shaft, depending on the measurement type used.
"Absolute Rotary Encoders" can measure "angular" positions while"Incremental Rotary Encoders" can measure things such as distance, speed and position.
Rotary Encoders are employed in a wide variety of application areas such as computer input device like mice andtrackballs as well as robotics.
Position encoders
A Position Encoder is used to determine the mechanical position of an object. This mechanical position is an "absolute
position". They may also be used to determine a change in position between the encoder and object as well. The change
in position in relation to the object and encoder would be an incremental change.
Position Encoders are widely used in the industrial arena for sensing the position of tooling and multi-axis positioning.
Optical encoders
An Optical Encoder interprets data in pulses of light which can then be used to determine such things as position,
direction and velocity. The shaft rotates a disc with opaque segments that represent a particular pattern. These encoders
can determine the movement of an object for "rotary" or "shaft" applications while determining exact position in "linear"functions. Optical encoders are used in various applications such as printers, CNC milling machines and robotics.

Absolute Vs incremental encoders
To demonstrate the difference between Absolute and Incremental Encoders we will use the Rotary Encoder type as an
example.
Absolute rotary encoders
Absolute rotary encoders are capable of providing unique position values from the moment they are switched on. Thisis accomplished by scanning the position of a coded element. Each position in these systems correspond to a uniquecode. The number of codes, n, per revolution corresponds to the resolution or 2^n unique positions.
• Multiple Interface Options: Analog, Ethernet, Fieldbus, Parallel, Serial• Singleturn and Multiturn Revolution• Optical, Mechanical, Magnetic, and Electromagnetic Measuring Principles
Incremental encoders
Incremental encoders generate a pulse train output signal each time the shaft rotates. The number of pulses per
revolution defines the resolution of the device, the number of pulses indicates the change in angle, the frequency ofpulses is proportional to the rate of position change, and the phase indicates the direction of movement. Each time theencoder is powered on it begins counting from zero, regardless of where the shaft is. Initial homing to a reference point,often called an index or Z signal, is therefore inevitable in all positioning tasks, both upon start up of the control system
and whenever power to the encoder has been interrupted.
• QEPA, QEPB, QEPI (Index), and inverted Signals are output of the Incremental Encoders• Flexible Scaling Functionality

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Encodersti.comFigure 34 is an example of a quadrature signal moving in the forward direction (QEPA leads QEPB).
QEPA

QEPB

QEPI

Figure 34. Quadrature signal.

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Encodersti.comNotes

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Pulse width modulation (PWM)

ti.comPulse width modulation (PWM)
PWM definitions •Duty cycle •Resolution •Deadband •Notes •

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Pulse width modulation (PWM)

ti.com
PWM definitions
Period (T) = 1/F

The duration after which the PWM pattern will repeat itself

Frequency (F) = 1/T

Inverse of the period

On-Time

The amount of time the output signal has a logic high value during a period

Off-Time

The amount of time the output signal has a logic low value during a period

Amplitude

The max voltage of the output signal
Voltage

Amplitude

ON-Time

OFF-Time
Time
Tpwm

Figure 35. PWM output.

Duty cycle
Duty cycle describes the portion of the PWM period that is 'on' or high. The duty cycle is measured as a percentage.
Time"
Duty Cycle % = "ON
Period *100

(81)

Time"
Average Output Voltage V = "ON
Period * Amplitude(82)

Voltage

25 %

75 %

ON

ON

Average
Voltage

Amplitude

ON

50 %

OFF

OFF

OFF

Time

Figure 36. PWM duty cycle.

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Pulse width modulation (PWM)

ti.comExampleWhat is the duty cycle for an average voltage output of 2.75 V if the amplitude is 3 V and the period is 200 ms?
AnswerTime""ON Time"
Average Output Voltage = "ON
Period * Amplitude = 2.75 = 200ms * 3
Time"
183ms
Duty Cycle % = "ON
Period *100 = = 200ms *100 = 91.5%

ON Time = 183ns

(83)
(84)

ResolutionF
PWM resolution % = F PWM *100%(85)

PWMCLKT
PWM resolution bits = log2 T PWM

Where

(86)

PWMCLK

PWMresolution = the granularity with which the duty cycle can be modulated
FPWM = frequency of PWM output, 1/ TPWMFPWMCLK = frequency of PWM clock, 1/ TPWMCLKTPWM = period of PWM output, 1/ FPWM

TPWMCLK = period of PWM clock, 1/ FPWMCLK

Tpwm

Tpwmclk

Figure 37. PWM resolution.

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Pulse width modulation (PWM)

ti.comTable 17. Common PWM resolution values.
PWM Frequency (kHz)Resolution (bits)

Resolution (%)

20

12.3

0.02

50

11

0.05

100

10

0.1

150

9.4

0.15

200

9

0.2

250

8.6

0.25

500

7.6

0.5

1000

6.6

1

1500

6.1

1.5

2000

5.6

2

ExampleWhat is the resolution of a PWM output that has a 500 ns period and a PWM clock frequency of 200 MHz?
Answer
PWM resolution % = F

FPWM

PWMCLK*100% =T

PWM resolution bits = log2 T PWM

PWMCLK

1
500ns
200MHz *100 = 1 %= log2500ms
1200MHz= 6.64 bits → 6 bits

DeadbandFigure 38 illustrates a PWM output with both rising and falling edge delays applied. This method provides a means
to delay the switching of a gate signal, thereby allowing time for gates to turn off and preventing a short circuit. To
explain further, power-switching devices turn on faster than they shut off. This issue would momentarily provide a pathfrom supply rail to ground, resulting in a short circuit. The separation of PWM signal transitions between the outputs isreferred to as "dead-band"• Rising edge delay (RED) is a delay at the rising edge of the output• Falling edge delay (FED) is a delay at the falling edge of the output

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Pulse width modulation (PWM)

ti.com
Tpwm

RED

FED

Figure 38. PWM deadband.

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Pulse width modulation (PWM)

ti.comNotes

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DAC

ti.comDAC
DAC definitions •DAC error •DAC output considerations •Notes •

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DAC

ti.com
DAC definitions
Resolution = n

The number of bits used to represent each input code

Number of codes = 2n

The number of possible codes that can be enumerated

Full-scale range output = FSR

The limit of the output voltage range

LSB = FSR
2n

The voltage difference between two consecutive codes

Full-scale output voltage = (2n – 1) • 1LSB

The maximum voltage that can be output

Full-scale input code = 2n – 1

The largest code that can be represented

Transfer function: VOut = FSR • Code2n

Relationship between input code and output voltage

FSR = 3.3000 V

DAC Output Voltage (V)Full-scale voltage = 3.2992 V

Voltage Resolution = FSR / 2n
Example: 3.3 V / 4096 = 806 uV

3.2984 V
3.2976 V

0.0024 V
0.0016 V
0.0008 V

0xFFF

0xFFE

0xFFD

0x003

0x002

0x001

LSB Resolution = (n) bits
Example: n = 12 bits

0x000

0.0000 V
Full-scale code = 2n - 1
Example: 212 - 1 = 4095

DAC Code in Hex Format (LSB)
Number of codes = 2n
Example: 212 = 4096 codes

Figure 39. DAC transfer function.

DAC error
DAC offset error
Offset error describes the deviation from the ideal y-axis intercept for the DAC transfer function. The effect of offset error
applies uniformly across the output range, and does not include the contribution of gain error or any nonlinear errors that
may be present in zero-code error.
For an ideal transfer function described as:
VOut = ( FSRn • Code)(87)

VOut = ( FSRn • Code) + EOffset

(88)

2

The effect of offset error (EOffset) is modeled as:
2

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DAC

ti.comOffset error may be derived using different techniques such as a simple mid-point measurement, or a calculated y-axis
intercept based on a best fit line that is extrapolated from multiple measured points.
FSR = 3.3000 V

DAC Output Voltage (V)Full-scale voltage = 3.2992 V
Measured

3.2984 V

Ideal

Offset Error
1.6500 V

Midpoint Code = 2n / 2
Example: 212 / 2 = 2048

0.0008 V

0xFFF

0xFFE

0x800

0x001

0x000

0.0000 V

DAC Code in Hex Format (LSB)

Figure 40. DAC midpoint offset error.

DAC gain error
Gain error describes the deviation from the ideal slope of the DAC transfer function. The effect of gain error scales inmagnitude across the output range, and does not include the contribution of offset error or any nonlinear errors that may
be present in full-scale error.
For an ideal transfer function described as:
VOut = ( FSRn • Code)(89)

VOut = ( FSRn • Code) • EGain

(90)

2

The effect of gain error (EGain) is modeled as:
2

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DAC

ti.comGain error is derived from the measured values of multiple points in the transfer function. The methodology used forextrapolating the gain error may vary between devices.
FSR = 3.3000 V

DAC Output Voltage (V)Full-scale voltage = 3.2992 V
Gain
Error

3.2984 V
Ideal

MeasuredGain

1.6500 V

Ideal
Gain

Measured

0.0008 V

0xFFF

0xFFE

0x800

0x001

0x000

0.0000 V

DAC Code in Hex Format (LSB)

Figure 41. DAC gain error.

DAC zero-code error
Zero-Code error is an end-point error for when Code = 0 is loaded into the DAC code register. The intention is todescribe how close to the zero voltage the DAC output can reach when set to the minimal output value. Zero-Code error
is correlated to the cumulative effects of offset error and linearity error.
A positive error indicates that the measured output voltage for Code = 0 is higher than ideal, whereas a negative error
indicates that the measured output voltage for Code = 0 is lower than ideal.
FSR = 3.3000VDAC Output Voltage (V)Full-scale voltage = 3.2992V
3.2984V
Measured

1.6500V

Ideal

0.0008V

0xFFF

0xFFE

0x800

0x001

0.0000V
0x000

Zero-Code Error

DAC Code in Hex Format (LSB)

Figure 42. DAC xero-code error.

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DAC

ti.com
DAC full-scale error
Full-Scale error is an end-point error for when Code = 2n-1 is loaded into the DAC code register. The intention is todescribe how close to the full-scale voltage the DAC output can reach when set to the maximum output value. Full-Scaleerror is correlated to the cumulative effects of gain error and linearity error.
A negative error indicates that the measured output voltage for Code = 2n-1 is lower than ideal, whereas a positive error
indicates that the measured output voltage for 2n-1 is higher than ideal.
FSR = 3.3000VDAC Output Voltage (V)Full-scale voltage = 3.2992V
Full-Scale
Error

3.2984V

Ideal

1.6500V

Measured
0.0008V

0xFFF

0xFFE

0x800

0x001

0x000

0.0000VDAC Code in Hex Format (LSB)

Figure 43. DAC full-scale error.

DAC differential non-linearity (DNL)
Differential Non-Linearity (DNL) describes the difference between measured versus ideal step sizes between sequential
codes. The DAC manual will typically express only the minimum and maximum deviations for the linear region of thetransfer function. DNL performance is typically at its worst near the power supply rails due to internal component
saturation. Most modern DACs are monotonic, meaning that the output voltage will not decrease when the input code isincremented. Figure 44 shows both monotonic and non-monotonic DNL.

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DAC

ti.com-0.5 LSB
DNL

Output Voltage

Ideal
Code

NonMonotonic
Ideal
Code

Ideal
Code

+0.5 LSB
DNL-1.5 LSB
DNL

CodeFigure 44. DAC DNL.

DAC integral non-linearity (INL)
Integral Non-Linearity (INL), sometimes referred to as relative accuracy, describes the deviation of the measured output
versus a straight line fit of the transfer function. While DNL expresses the relationship between measured vs ideal code
step-sizes, INL expresses the cumulative effects of sequential DNL errors. The DAC manual will typically express only
the minimum and maximum deviations for the linear region of the transfer function. INL error cannot be corrected using a

Output Voltage

simple two point fit calibration.

Consecutive DNL
Errors Accumulate toMake INL Errors

INL
Integral Non-Linearity
Maximum Error fromEnd Point F T

CodeFigure 45. DAC INL.

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DAC total unadjusted error (TUE)
The Total Unadjusted Error (TUE) is the statistical combination of uncorrelated error sources in the linear region ofoperation for the DAC. Table 18 shows the correlative relationships between the various DAC errors that are defined inthis chapter.
Table 18. DAC error correlation.
Error

OffsetGain

Zero-CodeFull-Scale

DNL

INL

Offset--Correlated

Correlated

-

-

Gain

-

-

-

Correlated--

Zero-CodeCorrelated

-

-

-

-

-

Full-Scale

Correlated

Correlated--

Correlated

Correlated

DNL

-

-

-

Correlated-

Correlated

INL

-

-

-

Correlated

Correlated-

The TUE equation is shown below, where all error sources must first be normalized to a common unit format (such as
LSBs or parts per million). Table 19 shows the calculations required to convert between different unit formats.
TUE Equation
TUE = EOffset2 + EGain2 + EINL2

(91)

Where

EOffset = The static component of output error across the transfer function. See DAC Offset Error.
EGain = The proportionate component of output error across the transfer function. See DAC Gain Error.
EINL = The maximum deviation of the output from a straight-line fit of the transfer function. See DAC INL.
Table 19. Unit conversions for error.
To
Codes

Convert
Codes
Volts
From
%
ppm

Volts • 2n
VFSR

Volts

%

ppm

Codes • VFSR
2nCodes • 100
2n

Codes • 1062n-% • 2n100% • VFSR100

ppm • 2n106

ppm • VFSR
106

Volts • 100
VFSR-

ppm • 100
106

Volts • 106
VFSR% • 106
100-

A single TUE calculation can be useful for comparing the relative performance between different DACs, but it may not
produce accurate estimates of typical error in the system. For example, the TUE equation treats EGain as a uniform
contributor of error across the transfer function, but EGain is actually a scaled error with minimal influence on the lower
codes. An improved estimate of system error may be produced by breaking up the transfer function into multiple regions,where the error components are adjusted in the TUE calculation based on their expected contribution to each region.

DAC output considerations

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DAC linear range

Linear range defines the region of the DAC transfer function that is expected to follow a uniform slope, where the range
can be described using either the code range or the output voltage range. The linear range for a DAC is often the sameas its full programmable range.
FSR = 3.3000 V
Measured

DAC Output Voltage (V)Full-scale voltage = 3.2992 V

Ideal
Linear Output
Range

1.6500 V

Linear Code
Range
0xFFF

0x800

0x000

0.0000 V

DAC Code in Hex Format (LSB)

Figure 46. DAC linear range.

If the DAC linear range is a subset of the full programmable range, some error parameters (such as those relating to gain
and linearity) may apply to the linear range only. These error parameters may include additional qualifiers such as end
point correction. For example, Table 20 shows how the straight line reference used for calculating the INL error may bederived from measured values as opposed to ideal values.
Table 20. Straight line end points for INL.
End Points

Ideal LineEnd Point Corrected LineMin Code

Code = 0

Minimum Linear CodeMin Voltage

Ideal Voltage

Measured Voltage

Max Code

Code = 2n-1

Maximum Linear CodeMax Voltage

Ideal Voltage

Measured Voltage

DAC settling time
The settling time describes the speed at which the DAC output will reach a known and useful level after the input code ismodified. If the DAC is used as a static reference level, the settling time may only be a minor consideration that applies
once during system initialization. For systems that require a dynamic DAC output, the settling time may instead be amajor consideration for meeting real-time deadlines.
Figure 47 shows a preconditioned DAC output of V0 before the input DAC code is changed at time T0. The new DAC
code has a target output value of V2 that will require some amount of full settling time (T2 - T0) to reach. In the time
between T0 and T2, the DAC output would typically be described as unstable.
If the full settling time (T2 - T0) is considered to be too slow for practical usage, an intermediate settling time (T1 - T0)
may be provided with a bounded expectation for settling error (V1 - V2).

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ti.comV0

Measured

V1
V2

Settling Error

T0

T1

T2

Settling Time
Figure 47. DAC settling time.

DAC load regulation
Load regulation describes the ability of the DAC output to drive an electrical load while still meeting its performance
specifications. The maximum load is often expressed in terms of a minimum resistance and maximum capacitance of alow-pass RC filter configuration as shown in Figure 48.
A resistive load that is less than RMIN may overwhelm the drive strength of the DAC output. A capacitive load that isgreater than CMAX may lead to instability of the DAC output.
RMIN
DAC
CMAX

GND
Figure 48. DAC load regulation.

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ti.comMathematical models
Laplace transforms •Transfer function •Transient response •Frequency response •Z-domain •Notes •

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Laplace transforms
Linear system analysis is facilitated by the use of Laplace transforms.
If f(t) is a real function of time defined for all t > 0, its Laplace tansform f(s) is,f s =L f t∞= ∫0+ f t e−stdt(92)

Table 21. Important Laplace transform pairs.
f(t)

f(s)

Step function, u t

1
s

1
s+α

e−αt

sin ωtω
s2 + ω2tnn!
sn + 1ss2 + ω2cos ωtf k t =

dkf t
dtk

skF s − sk − 1f 0′′ − sk − 2f′ 0′′ − … − f k − 1 0′′
F s
1 0s + s ∫−∞ f t dt

t∫−∞ f t dt

Impulse function δ t1e−αtsin ωt

s+α
s+α

2
1
2 1/2e−αtsin ωt + ∅ω α−α +ω

1 − ζ2

+ ω2

s+a
2
+ ω2

e−αtcos ωt

ωn

ω
2

s+a
2
+ ω2

s+α

ω
∅ = tan−1 −αωn22s + 2ζωns + ωn2e−ζωntsin ωn 1 − ζ2t , ζ < 11
1
e−atsin ωt − ∅+α2 + ω2 ω α2 + ω2

1
2

s s+α

ω
∅ = tan−1 −α+ ω2Transfer function
any n t + … + a1y′ t + a0y t = bmu m t + … + b1u′ t + b0u t

For initial zero conditions, the differential equation can be written in Laplace form as,ansny s + … + a1sy s + a0y s = bmsmu s + … + b1su s + b0u s
ansn + … + a1s + a0 y s = bms + … + b1s + b0 u s
α s y s = β s u sReal-Time Control Reference Guide

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ti.comThe dynamic behavior of a system is characterized by the roots of β s and α s
The m roots of β s are called the zeros of the system,
β s = bmsm + … + b1s + b0

(93)

The n roots of α s are called the poles of the system,
α s = ansn + … + a1s + a0

(94)

β s

The ratio α s is the transfer function of the system
G s =b sm + . . . + b1s + b0
y s
β s
=
= m n
u s
α s
ans + . . . + a1s + a0

(95)

The transfer function of a system is the Laplace transform of its impulse response,
y t = g t *u t = L−1 G s u s(96)

Transient response

The numerator and denominator of a transfer function, G s can be factorized to express the transfer function itself interms of poles and zeros,y s =As − z1 s − z2 . . . s − zmu ss − p1 s − p2 . . . s − pn(97)This rational function yields q terms, state vectors, through partial fraction expansion,
ε

εq

ε

y s = s −1r + s −2r + . . . + s − r
q
1
2

(98)

The time response is a sum of exponential terms, where each index is a denominator root,
r t

r t

r t

r

t

r t

y t = ε1e 1 + ε2e 2 + . . . + εne n + εn + 1e n + 1 + . . . + εqe q
Table 22. Response portions.

(99)

Response Type

Representation

Value

Transient Responseyc t

ε1er1t + ε2er2t + . . . + εnernt

Steady State Response

εn + 1ern + 1t + . . . + εqerqt

yp t

Description
The n terms in y(t) with roots
originating from comprise thetransient response
The a-n terms originating from u(s)comprise the steady state response

Frequency response
If a steady state sine wave, u t = u0sin ωt + α is applied to a linear system denoted by G s , the linear system would
respond at the same frequency with a certain phase and magnitude, giving output y t = y0sin ωt + β . The amplitudeyis modified by u0 and the phase is shifted by ∅ = β − α or < G jω0Real-Time Control Reference Guide

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ti.comBode plot basics

The frequency response for the magnitude or gain plot is the change in voltage gain as frequency changes. The change
is specified on a Bode plot, a plot of frequency versus voltage gain in dB (decibles). Bode plots are usually plotted
as semi-log plots with frequency on the x-axis, log scale, and gain on the y-axis, linear scale. The other half of thefrequency response is the phase shift versus frequency and is plotted as frequency versus degree phase shift. Phaseplots are usually plotted as semi-log plots with frequency on the x-axis, log scale, and phase shift on the y-axis, linear
scale.
Definitions
Voltage gain in decibels
Voltage gain dB = 20 log

Power gain in decibels

VOUT
VIN

(100)

P

Power gain dB = 10 log POUT
IN

(101)

Used for input or output power
Power measured dBm = 10 log

Power measured W
1 mW

(102)

Table 23. Examples of common gain values and dB equivalent.
A (V/V)A (dB)

0.001

-60

0.01

-40

0.1

-20

1

0

10

20

100

40

1,000

60

10,00080

100,000

100

1,000,000

120

10,000,000

140

Where
Roll-off rate is the decrease in gain with frequency
Decade is a tenfold increase or decrease in frequency (from 10 Hz to 100 Hz is one decade)
Octave is the doubling or halving of frequency (from 10 Hz to 20 Hz is one octave)

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ti.comBode plots: Poles
fP
100

0.707∗G V/V = –3 dB
Actualfunction

G (dB)

80

Straight-line
approximation–20 dB/decade

60

40

20

0
1

10

100

1k

10k

100k

1M

10M

100k

1M

10M

Frequency (Hz)(degrees)

+90

+45
0°

10

100

1k

10k

0

–45

f
–5.7° at P
10–45°/decade–84.3° at fP x 10

–90

–90°

–45° at fP

Figure 49. Pole gain and phase.

Where
Pole location = f p (cutoff frequency)

Magnitude f < f p = GDC (for example, 100 dB)
Magnitude f = f p = -3 dB

Magnitude f > f p = -20 dB/decade
Phase f = f p = −45°

Phase 0.1 f p < f < 10 f p = −45°/decade
Phase f > 10 f p = −90°
Phase f < 0.1 f p = 0°
Pole (equations)

As a complex number
GV =

VOUT
VIN =

j

GDC

(103)

f +1
fp

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ti.comMagnitude
GV =

VOUT
VIN =

GDC
2
f
+1
fp

Phase Shift(104)θ = − tan−1 ff(105)

GdB = 20Log GV

(106)

p

Magnitude in dB

Where

GV = voltage gain in V/V

GDB = voltage gain in decibels

GDC = the dc or low frequency voltage gainf = frequency in Hz

f p = frequency at which the pole occurs

θ = phase shift of the signal from input to output
j = indicates imaginary number or −1

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ti.comBode plot (zeros)
80

Straight-line
approximation+20 dB/decade

G (dB)

60

40
Actualfunction

20

+3 dB
0
1

10

100

1k

10k

100k

1M

10M

+90°

+90

+45° at f Z(degrees)

84.3° at f Z x 10
+45
0°

f
5.7° at Z
10

10

100

+45°/decade

0

–45

1k

10k

100k

1M

10M

Frequency (Hz)–90

Figure 50. Zero gain and phase.

Where
Zero location = f z

Magnitude f < f z = 0 dB

Magnitude f = f z = +3 dB

Magnitude f > f z = +20 dB/decade
Phase f = f z = +45°

Phase 0.1 f z < f < 10 f z = +45°/decade
Phase f > 10 f z = +90°
Phase f < 0.1 f z = 0°
Zero (equations)

As a complex number
GV =

VOUT
f
VIN = GDC j f p + 1(107)

Magnitude

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ti.comGV =VOUT
VIN = GDC

Phase Shiftf 2
fz + 1(108)

θ = tan−1 zf(109)

GdB = 20Log GV(110)

Magnitude in dB

Where

GV = voltage gain in V/V

GDB = voltage gain in decibels

GDC = the dc or low frequency voltage gainf = frequency in Hz

f z = frequency at which the zero occurs

θ = phase shift of the signal from input to output
j = indicates imaginary number or −1

Z-domain

Definition of Bilateral Z-Transform−nx z = ∑∞
n = − ∞x n z

(111)

−n
x z = ∑∞
n = 0x n z(112)Definition of Unilateral Z-Transform

Where:

x[n] = discrete time signalx(z) = the z-domain transform of the discrete time signal
n = integerz = complex number (Aejϕ = A cos ϕ + jsin ϕ )A = magnitude of z
j = imaginary unit

ϕ = phase in radians

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ti.comTable 24. Z-Transform Properties
Property

Z-Transform

Linearity

af 1 n + bf 2 n = aF1 z + bF2 z−1−n
f n + k = zk F z − ∑kn = 0f n z

Shift left by kf n − k = z−kF z

Shift right by k
Convolution
Final Value Theorem

Real-Time Control Reference Guiden

90

f 1 n *f 2 n = F1 z F2 z

lim f n = lim z − 1 F z∞
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