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74AXPnT245 – transceiver
Quad dual supply translating transceiver; 3-state••••

Functions & applications

Translating transceiver for wide voltage ranges.
Low static and dynamic power consumption for portableapplications.
Ioff circuitry provides power-down mode operation
Specified from -40 °C to 125 °C

Key technical features & portfolio•••

2

VCC(A) & VCC(B)

ICC

Package

74AXP4T245PW

0.9V – 5.5V

24μA

TSSOP16

74AXP4T245BQ

0.9V – 5.5V

24μA

DHVQFN16

74AXP8T245PW

0.9V – 5.5V

35μA

TSSOP24

74AXP8T245BQ

0.9V – 5.5V

35μA

DHVQFN24

Nexperia NPI Guide 2019

Industrial applications
General portable consumer applications
Enterprise and Telecom applications

Application diagram

New portfolio with 4-bit & 8-bit dual supply transceivers
Wide supply voltage offers from 0.9V to 5.5V
Small footprint packages for both TSSOP and DHVQFNPortfolio•••

SPI interface application

Available packages (W x L x H in mm)
PW(SOD403-1)

BQ(SOD763-1)

5 x 4.4 x 1.1

3.5 x 2.5 x 1.0

PW(SOD355-1)

BQ(SOD815-1)

7.8 x 4.4 x 2.05.5 x 3.5 x 1.0Logic

Design benefit

GX4 MicroPak
4 pad, low power gates

Design benefit•••

X2SON4 MicroPak provide the industry’s smallest footprint
for logic plastic packages
with a pad spacing ≥0.4mm no step-down stencil required- enables low cost board manufacturing
RoHS and dark-green compliant with NiPdAu lead finish
Low profile height of 0.35mm••

AUP and LVC families offer• 1G34GX4: Buffer• 1G17GX4: Buffer Schmitt-trigger• 1G07GX4: Buffer with open-drain• 1G04GX4: Inverter• 1G14GX4: Inverter Schmitt-trigger
Propagation delay• AUP1G: tpd 4.0ns (Vcc 1.8V, CL 15pF)• LVC1G: tpd 2.0ns (Vcc 2.5V, CL 50pF)
Static current 0.01µA for LVC1G and 0.1µA for AUP1G
Portfolio

3VoltageMax. Output

Temperature Range

LVC1G

1.65-5.5V± 32mA−40 to +125 °C

AUP1G

0.8-3.6V± 4mA−40 to +125 °C

Nexperia NPI Guide 2019

•Space constrained applications such as
smartphones, tablets and portables
Communication and industrial
applications

GX4(SOT1296-2)

0.6 x 0.6 x 0.32

Key technical features & portfolio••

Available packages (W x L x H in mm)

Package advantageLogic•

Functions & applications

74AVC1T8xxx Qualcomm
Single dual-supply translating 2-input OR or NOR with strobe••••

Functions & applications

Low cost alternative solution for Qualcomm's referenceboard design.
Wide supply voltage range
 VCC(A): 0.8 V to 3.6 V
 VCC(B): 0.8 V to 3.6 V
Supports mixed-mode voltage operations
Maximum data rates: 500 Mbit/s(1.8V to 3.3V translation)
 320 Mbit/s(translate to 2.5V or 1.8V)

Key technical features & portfolio•••••4Portfolio

VCC(A) &VCC(B)

OutputCurrent

Prop del(tPD)

Tamb

74AVC1T8832GS

0.8 – 3.6V+/-12mA

2.4ns-40~125°C

74AVC1T8128GS

0.8 – 3.6V+/-12mA

2.4ns-40~125°C

Wireless module
Mobile / Portable applications
Industrial applications

Application diagram•Over-voltage tolerant inputs, accepts voltages up to 3.6V
IOFF circuitry provides partial power down operation
Inputs with Schmitt trigger action
Suspend mode
High noise immunity

Nexperia NPI Guide 2019•••

Example of voltage translation
between the MCU and a WIFI
chipset on different voltage rails

Available packages (W x L x H in mm)
Package nameXSON8

pin count

8version

SOT833-1

suffixGTPitch (mm)0.50

WxL xH(mm)1.0 x 1.95 x 0.50

Logic

Design benefit

LV-A logic Family
Low leakage family for partial power down by IOFF circuit•••••••

Functions & applications

IOFF circuitry supports partial power-down
Low noise operation: VOL(p) < 0.8 V
Fully specified at 3.3 V and 5.0 V supply nodes
overvoltage tolerant inputs support mixed-mode voltage
Schmitt-trigger inputs for slowly transitioning input signals
Latch-up performance exceeds 250 mA
ESD - HBM exceeds 3 kV (ANSI/ESDA/JEDEC JS-001, Class 2)

Key technical features & portfolio••••

5IOFF power down
Low noise
3.3V and 5V supply voltage supportTranslater function

Part number

Portfolio sizefeatures

74LVxxxAxx

8 parts

Inverter, buffer, transceiver, OVT,CMOS inputs

74LVxxxATxx

5 parts

Inverter, buffer, transceiver, OVT, TTLinputs74AHCVxxxAxx

6 parts

Inverter, buffer, transceiver, OVT,
Schmitt trigger inputs

74AHCTxxxAxx

7 parts

Inverter, buffer, transceiver, OVT, TTL
inputsNexperia NPI Guide 2019••••

The LV-A family is designed to support
applications where in different modes
e.g. stand-by mode a part of the PCB isshut down. Applications:
Printer
TV sets
Desktop and notebook computer

Application diagram•Example of voltage translation between
MCU and system rail at different
voltage

Available packages
Package name

TSSOP

TSSOP

Pin count1420

version

SOT402-1

SOT360-1suffix

PWPW

Pitch (mm)

0.65

0.65

W x L x H (mm)6.4 x 5.0 x 1.1

6.4 x 6.5 x 1.1

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Design benefitOn roadmap

Autosense translators NXB/NXS
A family of 1-8 bit bidirectional level shifter and voltage translator with auto direction sensing

••
•
•
•
•

Functions & applications

Two completely separate power lines may be usedtranslates logic voltage levels with auto direction sensing
versions for open-drain (NXB) and push-pull CMOS logic(NXS) output
Pb-free, RoHS and dark green compliantspecified for partial power-down applications using IOFF
Automotive version on roadmap

Key technical features & portfolio••••

voltages: VCC(A)= 1.65 V to 3.6 V; VCC(B)= 2.3 V to 5.5 V
Maximum data rates: 26 Mbps (Push-pull)
Inputs accept voltages up to 5.5 V
Latch-up performance <100 mA per JESD 78B Class II

Part number

6Portfolio
sizepackages

NXx0101xx

1 bit

6

GM= XSON6 (SOT886), GS= XSON6(SOT1202), GW= TSSOP6 (SOT363-1)

NXx0102xx

2 bit

4

GT= XSON8 (SOT833-1)
DC= VSSOP8 (SOT765-1)

NXx0104xx

4 bit

6

GU12= XQFN12 (SOT1174-1)
BQ= DQFN14 (SOT762-1)
PW= TSSOP14 (SOT402-1)

NXx0108xx

8 bit

4

BQ= DQFN20 (SOT764-1)
PW= TSSOP20 (SOT360-1)

Nexperia NPI Guide 2019••••

Mobile application like smartphone,
wearables
Computing application like notebook,tablet, desktop PC
Industrial application
Automotive applications (on roadmap)

Application diagram•

Example of voltage translation between
1.8V MCU and 3.3V system rail

Available packages (selection)
Package
name

XSON6

XSON8XQFN12pin count

6812Version

SOT1202

SOT833-1

SOT1174-1

SuffixGSGTGU12Pitch (mm)

0.35

0.50

0.40

WxL xH(mm)1.0 x 1.0 x
0.35

1.0 x 1.95 x
0.50

2.0 x 1.7 x
0.50

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Design benefit

Automotive
qualified

MicroPak packages AEC-Q100 qualified
Automotive qualified Mini logic in leadless packages

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Functions & applications

Optimized for speed and power
Low propagation delay
Low dynamic power dissipation
Pb-free, RoHS and dark green compliant
specified for partial power-down applications using IOFF

Key technical features & portfolio•••••

Very small footprint - up to 65% space saving overtraditional leaded packages
pin pitch options: 0.5, 0.35 mm
Low profile height: 0.5 or 0.35 mm
Leadless - no bent leads, no co-planarity issues
Pb-free, RoHS and dark green compliant

Part number

7TypesFeatures

74AUPxxxxxGx-Q100

7Gates, Inverter, buffer, voltage translator,multiplexer, OVT, CMOS or Schmitt trigger inputs

74AVC1T45GS-Q100

1single bit, dual supply transceiver, bidirectional
level translation

74LVCxxxxxGx-Q100

14Gates, Inverter, buffer, voltage translator,multiplexer, OVT, CMOS or Schmitt trigger inputs

Nexperia NPI Guide 2019••••space constraint automotive
applications e.g.:
Infotainment
ADASBMS

Application diagram•

Example of uni-directional logic levelshifting translation

Available packages (selection)
Package
name

XSON6

XSON6

XSON8

pin count

668

version

SOT1202

SOT886

SOT833-1

suffixGS

GMGT

Pitch (mm)

0.35

0.50

0.50

WxL xH(mm)1.0 x 1.0 x0.35

1.0 x 1.45 x 0.50

1.0 x 1.95 x 0.50

LogicDesign benefit