Design considerations of GaN
devices for improving powerconverter efficiency and density
Salil Chellappan
Systems Manager,
Power Delivery Industrial Systems
Texas Instruments

The availability of Gallium Nitride (GaN) devices
for power conversion is improving, with many
manufacturers releasing catalog parts.
The application of these devices has gained the keen attention of power-systemdesigners from all over the world. Although a lot of study has gone into understanding
their properties, the selection of GaN devices for various power-conversion applications
based on their properties remains not well understood.
After much study dedicated to GaN as ancomparatively lower gate threshold voltage could

alternative to silicon in power switching, multiple

reduce noise margins. A third concern for thesemanufacturers now offer GaN switching devices

devices – although not very serious – is the higher

for power-conversion applications. However, yougate-leakage current, which could increase gate-

must look at the properties of GaN devices in detaildriver dissipation.

before assessing their suitability and advantages.

The depletion mode GaN device offers bothThis white paper will examine some of the mostperformance as well as manufacturing advantages.

important design considerations affecting power-

Its normally “on” nature may be a problem during

converter performance.

power-up and other abnormal operating conditions,

Device architecture

however. It also requires the use of a negative supply.

GaN switching devices come in two different types

depletion mode GaN high-electron mobility transistor

You can overcome this problem by connecting thebased on their internal architecture: enhancement(HEMT) in series with a low-voltage silicon MOSFET

mode (e-GaN) and cascoded depletion modein the cascoded d-GaN structure. The gate of the(d-GaN). An e-GaN switch operates like a normal

HEMT is shorted to the source of the MOSFET,

silicon metal-oxide semiconductor field-effectwhile the HEMT source connects to the drain of thetransistor (MOSFET), although it has reduced gate-

MOSFET [1]. As Figure 1 shows, the gate-to-source

to- source voltage levels. An e-GaN device also

voltage of the HEMT is the source-to-drain voltage ofhas a simpler architecture and packaging, low onresistance, and zero body-diode reverse recovery

DRAIN

DRAIN

(there is no body diode, but the channel itself is
GaN HEMT

bidirectional in nature and behaves like a body diode).
The first (and main) concern with this type of
GATE

device is the critical nature of its gate-drive design.

GATE

The problem is that the device’s fully enhanced

SI MOSFET

gate-drive voltage is very close to its breakdown

SOURCE

voltage – the safety margin is typically only about

e-GaN

1 V. This might cause a device failure in the eventof a voltage spike or parasitic ringing. Second, theDesign considerations of GaN devices for improving
power-converter efficiency and density

SOURCE

Cascode d-GaN

Figure 1. Symbols of e-GaN and cascode d-GaN devices highlight
structural difference.

2

November 2017

the MOSFET. So the silicon MOSFET can control the

TI direct-drive GaN

turning on and off of the GaN HEMT.

After comparing e-GaN and d-GaN structures, it

The main advantage of this structure is that theis obvious that most of the issues associated withcomplete cascoded d-GaN switch has the gate

the cascoded d-GaN are from the simultaneous

characteristics of a low-voltage silicon MOSFET.

switching of the silicon MOSFET and GaN HEMT.

Therefore, existing commercial MOSFET gate drivers

TI’s direct-drive technology overcomes this problem

can easily drive the cascoded d-GaN switch. Also,

by using only the silicon MOSFET to enable thebecause the gate characteristics of silicon MOSFETs

device. Figure 2 compares the configuration.

are well-known, there are no unknowns to deal with.
DRAIN

You will have to make some compromises in overall
performance because of the additional series silicon

DRAIN

GaN HEMTGaN HEMT

PWM

switch. The most significant impact on performance isarguably due to the reverse recovery associated withthe body diode of the silicon MOSFET. Because thecascoded d-GaN switch is a series combination, it will

PWM

have reverse recovery while conducting in a reverse

ENABLESI MOSFET

SOURCESI MOSFET

SOURCE

direction, unlike an e-GaN switch. The next significant
effect is the possibility of the silicon MOSFET

Cascode d-GaN

avalanching during turn-off due to the charge

TI Direct-Drive GaN

Figure 2. Configuration difference between cascode d-GaN and
Direct-Drive GaN.

imbalance between the drain-to-source capacitancesof the two series devices. This can potentially increase

As mentioned earlier, in cascode GaN, both theswitching losses and decrease reliability.

silicon and GaN devices turn on and off together.

A cascoded d-GaN has increased packaging

However, in the TI direct-drive GaN, the siliconcomplexity and cost due to the additional series

MOSFET is only used to overcome the problem

silicon switch. The higher number of devices andof power-up shoot-through. The silicon MOSFET

interconnections increase issues related to reliability.

is not switching; it turns on during power-up andParasitic inductance and capacitance between thestays on until power-down with an enable signal

Silicon switch and GaN HEMT may cause delay andthat’s applied only when the negative bias voltage

oscillation during switching transients and impact

to turn off the GaN HEMT is available [3]. Integrating

electrical performance.

the negative voltage supply and gate drives along

Another unfavorable effect with d-GaN devices

with the power switches ensures reliable andis the increased on-resistance because of the

precise control over switching of both the silicon

addition of the on-resistance of the silicon MOSFET.

MOSFET and GaN HEMT. Driving the GaN gate

The increase can be significant for lower-voltage

directly reduces the gate charge significantly. And(<200 V) cascoded d-GaN devices. So for low

completely eliminating the body diode’s reverse

voltages, e-GaN switches are a better choice. For

recovery and silicon-switch avalanching results in aa high-voltage (600 V) cascoded d-GaN device,considerable reduction in switching losses.

the additional resistance may be only about 5% of
the overall on-resistance [2]; at this voltage level,cascoded d-GaN is still a viable option.
Design considerations of GaN devices for improving
power-converter efficiency and density

3

November 2017

Other advantages resulting from the integration(SMD) packages with the Kelvin source pin closeof the drive circuit into the power devices include

to the gate pin. Using devices that have the gate

the ability to control the switching slew rate,

driver integrated with the GaN switch itself (as in TI’s

cycle-by-cycle over-current protection by sensing

direct-drive devices) is even better as it can avoid

the voltage drop across the silicon MOSFET andproblems with external layouts.

over-temperature protection.

Thermal management is another package-related

Device packaging

consideration. Most SMD packages depend

Because GaN devices are capable of very fastboard (PCB) for heatsinking. To improve thermal

on thermal transfer through the printed circuit

switching, the parasitics associated with theperformance, the user guide of a TI GaN daughter-package are extremely important. In certain cases,

card explains how to attach the heatsink to thethey can severely limit the device performance.

PCB [6]. Placing this below the thermal pad of the

Of all parasitic elements, common source

package reduces thermal resistance to the heatsink

inductance (CSI) is the most significant because ofconnected on the opposite side of the PCB.

its effects on electrical performance. The overall CSI

While the TO-220 package is better for thermalis the sum of the source inductance internal to the

management because the metal tab is available for

package and the lead inductance of the packageheatsinking, be aware of the issues discussed in thisitself. CSI has the potential to create ringing acrosspaper before considering its use.

the drain-to-source and gate-to-source voltages

Another package-related consideration is related toin the presence of high di/dt in the drain-to-source

electromagnetic interference (EMI). Most switchingcircuit, resulting in increased losses [4] and false

power circuits have the drain as the switching node.

switching [5]. In e-GaN devices, the ringing in VGS

But connecting the thermal pad to the drain cancan even result in breakdown of the gate, as theresult in high common-mode and radiated EMI.

safety margin is limited.

Therefore, a source-connected thermal pad is a

In silicon MOSFETs, a common practice is to damp

better choice from an EMI perspective.

this ringing by increasing the gate resistance andIn certain applications, the source can be theslowing down the switching. This isn’t advisable forswitching node. In such cases, connecting the

GaN devices because they will lose their inherent

heatsink (directly or through a capacitor) to a quiet

fast switching ability. Another solution is to provide

node (DC bus positive or return) can help reduce EMI.

a Kelvin source connection to remove CSI from thegate-drive circuit. While this can address the false

Drain voltage rating

switching problem, drain-to-source ringing can still

By design, most practical GaN devices are not

be present. A through-hole package like TO-220

avalanche-capable. So a sufficient voltage rating is

is not a very good option for GaN devices, as theimportant. Take care to not exceed the breakdown

significant lead inductances can prevent the optimal

voltage rating even during transient events. A voltage

utilization of their fast switching capability. Also, therating of 600 V is generally adequate at bus voltages

center drain arrangement of the TO-220 packageof up to 480 V for buck, boost and bridge topologies

is not ideal for the layout of a fast switching device.

(including half and full bridge, inductor-inductor

It would be better to use surface-mount device

Design considerations of GaN devices for improving
power-converter efficiency and density

capacitor [LLC], phase-shifted full bridge [PSFB], etc.).

4

November 2017

Output capacitance

Gate charge

There are two different output-capacitance

Gate charge is the parameter that indicates theparameters for a switching power device: one isdevice’s ability to switch fast. The lower value oftime-related and the other is energy-related. Time-the sum QGS2 + QGD indicates the device’s ability torelated output capacitance, CO(tr), is more importantachieve higher dV/dt – and consequently reduced

in soft-switching topologies, as it determines theswitching losses. Typically, GaN devices have adead time required for zero voltage switching (ZVS).

significant advantage here. e-GaN devices have

For GaN devices, this parameter is significantly lower

about 10x and d-GaN devices have about 2x-5x(5x-10x) than silicon super-junction MOSFETs. You

lower gate charges compared to silicon super-

may also see this parameter specified in terms ofjunction MOSFETs. You can also look at the RON x

charge (QOSS). In ZVS topologies, the reduced CO(tr)QG figure of merit to see if sufficiently low conduction

offers significant advantages compared to siliconlosses accompany low switching losses.

MOSFETs because the reduced dead time results in

dV/dt and di/dt sensitivity

lower circulating currents.

CSI-related false switching due to high di/dt was

Although CO(tr) is significantly lower for GaN

previously referenced in the “Device packaging”

devices, the same is not true for energy-related

section. Since the problem is mostly package

output capacitance, CO(er). You may see the sameand layout related, reducing CSI through properparameter expressed in terms of energy (EOSS).

package selection and proper layout is the solution

CO(er) is slightly higher for a cascoded d-GaN device
but almost equal for an e-GaN device compared

to di/dt-related issues.

to a top-of-the-line silicon super-junction MOSFETThe dV/dt sensitivity of power-switching devices

because, while the output capacitance (COSS) of

is caused by the interaction between the various

GaN devices does not vary much with voltage, it isparasitic capacitances and gate-drive circuitvery nonlinear for silicon super-junction MOSFETs.

impedances. This is also true for GaN devices.

Since the capacitance is much higher for super-

Figure 3 shows various parasitic capacitances andjunction MOSFETs at lower voltages and lower

the currents through them during a positive-goingat higher voltages, the energy content of thedV/dt event across the drain source.

overall charge can be similar. However, as COSS is

During a dV/dt event, the drain-source capacitancemuch more linear for GaN devices, the hysteresis(CDS) gets charged; at the same time, the gate-associated with the energy stored in it is lower

drain (CGD) and gate-source (CGS) capacitors also

compared to a silicon super-junction MOSFET of
CGD

comparable EOSS, allowing much more of the energy
to be recovered in a soft-switching application.
RG

CDS
RSink

CGS

Figure 3. Parasitic capacitances and currents in a GaN power device.

Design considerations of GaN devices for improving
power-converter efficiency and density

5

November 2017

charge in series. If unaddressed, the charging

losses, its reverse recovery is very slow, resulting incurrent through the CGD capacitor will flow throughsignificantly high switching losses.

and charge CGS beyond the gate threshold voltage

Even though GaN devices do not have a reverse(VTH) and turn the device on. This event, sometimes

body diode, they are capable of conducting incalled Miller turn-on and well-known in the context

reverse direction, as they are inherently bidirectionalof MOSFET switching, can be very dissipative. To

devices. As soon as the reverse voltage across them

determine the dV/dt sensitivity of a power-switchingexceeds the gate threshold voltage, they can startdevice, you can use a figure of merit called the Miller

conducting. This conduction can resemble the effectcharge ratio (QGD/QGS1). A Miller charge ratio of lessof a reverse body diode, with a cut-in forward dropthan 1 will guarantee theoretical dV/dt immunity. It

equal to the gate threshold voltage and dynamic

may not always be possible to get this ratio lower

resistance equal to the on-resistance. As this reverse

than 1, however, especially with higher voltage

conduction is a majority carrier effect, there is nodevices. In such cases, the effectiveness of diverting

associated reverse recovery. But since the gate

the CGD capacitor charging current through thethreshold voltage is much higher than a junction

gate-driving circuit determines the dV/dt immunity

diode forward voltage, the conduction losses can beof the circuit. Even though in Figure 3 the gate-drive

significant. Therefore, in most applications that needcircuit shows only resistances, the drive circuit canreverse conduction, you may need careful dead-involve inductance due to the layout, which can havetime-optimized synchronous rectification.

a significant impact on the effectiveness of diverting

Cascoded d-GaN devices have reverse recovery

the charging current. So the gate-drive circuit layout

because of the series-connected low-voltage silicon

becomes a critical factor in improving dV/dt immunity.

MOSFET, although the Qrr is considerably lower

A co-packaged gate driver can have a significant

than the reverse body diode of a comparable silicon

positive impact due to the lower impedance gate

super-junction MOSFET.

driving that is possible through its use.

TI’s direct-drive architecture completely eliminates

The gate-threshold voltage, VTH, is also of great

the reverse recovery of the silicon MOSFET, as

importance in ensuring dV/dt immunity. While athe channel is always on during switching and thehigher VTH is preferable, the structure of the e-GaN

diode never comes into operation. However, likeswitch results in lower gate-to-source voltage levels.

in an e-GaN FET, you should address the higher

Cascoded d-GaN devices are comparatively better

voltage drop during reverse operation with a robust

than e-GaN devices, as the gate structure is silicon

synchronous rectification scheme.

and the gate-to-source voltage levels are same as
those of silicon MOSFETs.

To soft switch or not

Reverse conduction

There is a general perception among many powersystem designers that GaN power switches

The reverse conduction characteristics of the power-

can make soft or resonant switching topologies

switching device are important in many switchingirrelevant due to their ability to switch very fast. The

topologies that use a totem-pole (half-bridge) powerassumption is that fast switching capability canstage. While the forward drop of the body diode inachieve comparable or even better efficiencies witha silicon MOSFET is low, ensuring low conduction

Design considerations of GaN devices for improving
power-converter efficiency and density

6

November 2017

hard-switching topologies; thus, soft switching may
become irrelevant. While this is true at the switchingfrequencies currently achievable with silicon
MOSFETs, there is significant EOSS loss associatedwith GaN devices, as discussed elsewhere inthis paper. As the switching frequency increases,
the EOSS loss becomes the most significant loss
component. Since the stored energy in the output
capacitance of GaN devices is much more easily
recoverable compared to silicon super-junction

References
1. W. Liu, H. Zhou and E. Persson. “Switching
Characteristics of Cascode GaN Switches,”
PCIM Europe, 2015.
2. A. Lidow, M. de Rooij, J. Strydom and D. Reusch.
“GaN Transistors for Efficient Power Conversion,”
Efficient Power Conversion Corp., APEC 2013
Educational Seminar S7, p. 16.
3. P. Brohlin, Y.K. Ramadass and C. Kaya.

MOSFETs, it makes a lot of sense to go for soft or“Direct-drive configuration for GaN devices,”

resonant switching, especially at multi-megahertz

Texas Instruments white paper (SLPY008),

switching frequencies.

October 2016.

Conclusion

4. D. Jauregui, B. Wang and R. Chen. “Power Loss
Calculation with Common Source InductanceThe device architecture, packaging and performance

Consideration for Synchronous Buck Converters,”

parameters of d-GaN and e-GaN devices continue toTexas Instruments application report (SLPA009A),

evolve towards as efficient, robust and cost-effective

July 2011.

alternatives to silicon MOSFETs in power conversion.
No doubt, many of the performance parameters
discussed in this whitepaper will be improved
significantly in the future. Higher levels of integrationof GaN devices like half bridge devices and integrated
gate driver with protection circuits will make theirusage in power conversion far easier. The adoption

5. J. Wang and H. Shu-Hung Chung. “Impact ofParasitic Elements on the Spurious Triggering
Pulse in Synchronous Buck Converter,” IEEE
Transactions on Power Electronics, Vol. 29,
Issue 12, December 2014, p. 6672-6685.
6. “Using the LMG3410-HB-EVM Half-Bridge andof GaN devices in soft switching topologies can

LMG34XXBB-EVM Breakout Board EVM,” Texas

push the power density of power converters to levels

Instruments user’s guide (SNOU140A), May 2017.

unprecedented with silicon switching technology.

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