Challenges in Front-end
Electronics for Future HEP
Experiments
R. J. Yarema
Fermilab
Batavia, Illinois
14th International Workshop on Vertex Detectors
Nikko, Japan, November 2005

Where is the Future?
ALICE

LHCB

T2K/NOvA, Japan/USA, 2009

SLHC, CERN, 2015

STAR/Phenix upgrade,
BNL, 2011

DESY, Hamberg

CBM, Darmstadt, 2015
November 7-11, 2005

SuperBELLE, KEK, 2012
Vertex 2005, Nikko, Japan

ILC, ?, 2015
2

What are the Challenges?
• The “Big Four” technical challenges– Lower power– Less Mass (high density)– Higher Radiation tolerance– Higher speed/performance• The practical challenges– Process obsolescence– Cost and complexity of new processes• Any one of these could be a talk by itself• Can only discuss a few thoughts for each
November 7-11, 2005

Vertex 2005, Nikko, Japan3

Lower Power• Front end electronics channel
count continues to increase.
e.g. SLHC, ILC, Super Belle– Higher channel counts increases
power which increases cooling needs– Added cooling means more mass

• Approaches to consider for
reducing analog and digital power

ASIC– Reduce power supply voltage– Power down
– Change design approach– Serial powering (to be discussed in
section on mass)
November 7-11, 2005

Vertex 2005, Nikko, Japan

4

Digital Power Reduction• Digital Power can be reduced by going to lower voltage (smallerfeature size processes)• CMOS logic power is proportional to CV2f (neglecting thetransconductance power andleakage current power)– Going from 0.25 D to 0.13 D reduces the power supply voltage from 2.5 to
1.5 V which reduces power by (2.5/1.5)2 = 2.77 at fixed frequency– In a very tightly packed digital circuit where trace length (capacitance) issmall compared to gate capacitance, C goes down. (Although the gate
capacitance per unit area goes up, the gate area goes down resulting in a
net decrease in C of about 1.73 for a given complexity)– Thus ideally, power could be reduced by 2.77 x 1.73 = 4.8 by going from
0.25D to 0.13 D.
– Unfortunately, frequency is often increased in DSM designs, limiting thepower savings.

• Since the transistor leakage current is usually low, there is no
significant advantage in reducing the power supply voltage during
periods of non-digital activity.
November 7-11, 2005

Vertex 2005, Nikko, Japan

5

Analog Power Reduction•••

Analog power can also be reduced by going to lower voltage (smaller feature size
processes).
Power in analog sections is Irms x V– Going from 0.25 D to 0.13 D reduces the power supply voltage from 2.5 to 1.5
V which ideally reduces power by (2.5/1.5) = 1.66, assuming constant current.
– In practice, the current in the analog section may actually be increased tocompensate for lower dynamic range. Thus the power savings in the analog
section is not as dramatic as in the digital section.
Since analog circuits draw current even when quiescent, significant power savings
can be achieved by ramping the analog voltage off during periods of inactivity.
Power reduction = 1/duty cycle.
– This approach has been used in Babar and is being considered for the ILC.
– Challenge is to insure that circuits are stable and ramped currents do not interferewith system operation.
Power off•

Another approach is to eliminate as many analog circuits as possible – go digital assoon as possible.
– Challenge is to live without analog signal information for as many systems as possible.
November 7-11, 2005

Vertex 2005, Nikko, Japan6

Less Mass
• Scattering from vertex and track detectors posesa serious problem for future HEP experiments– Currently the best hybrid pixel and silicon
strip front ends have about 1% - 2% X0• Includes silicon• Cabling, HDI, cooling, and support– Goal for some future experiments is a factorof 10 improvement or 0.1% X0 (100 micronsof silicon)• One approach is to reduce power so lessmass is need to extract heat from thedetector – this option already discussed• Some other approaches to reducing mass
– Series powering of modules– Thin silicon (detectors, ROC)
– Monolithic Active Pixels– 3D circuits
November 7-11, 2005

Vertex 2005, Nikko, Japan

C. Hoermann, PSI

7

Serial vs Parallel Powering ofHigh Density Detectors
Cables represent a significant portion of the massin a high density detector (silicon or pixel).
Use the ATLAS pixel detector as an example
Cables in the active region = 0.073%X0
In addition, power in cables to a 13 module
ATLAS SCT
ladder is 281% of power in the modules.
For upgrades to present systems or new lower mass
systems, the problem requires a new ideas – Serial Powering.
8 power
traces/mod

Va, VdVa, VdVa, Vd+sense+sense+senseModuleModuleModuleConstant
current

Parallel Power Scheme
November 7-11, 2005

Vertex 2005, Nikko, Japan

ModuleModuleModuleSerial Power Scheme
8Serial Power
Approach a• Serial voltage regulators•– Several approaches have been
examined using shunt andlinear regulators. Here are two.
Consider advantages to ATLAS
pixels– Number of power cables
reduced by factor of 50 (lower
mass, cost)– Radiation length/layer due tocables is reduced by factor of
6.5– Power dissipated in cables
reduced by factor of 10(Reduced heat pickup in otherdetector systems)– Voltage regulation done
locally gives better dynamic
performance– Lower power supply cost
November 7-11, 2005

I constant

Module
N

Lin
FE
reg
D
A

FE

D

Chip 1Lin
A reg

Chip n.

.

Approach b
Mod
N

Lin
reg D

Lin
reg D

FE A Lin
reg
Chip 1

Mod
1

Lin
reg D

FE A Lin
reg
Chip 1

Mod
2

Lin
reg D

FE A Lin
reg

Chip n

Vo

Lin
reg D

Lin
reg D

Chip 1Lin
reg D

FE A Lin
reg
Chip 1

.

.

.

To
DAQ

FE A Lin
reg

Chip n.

System with N modules and n chips

Vertex 2005, Nikko, JapanToDAQFE A Lin
reg
Chip n

Lin
reg D

To
DAQ

FE A Lin
reg

Chip nI = constantV = nVoModNFE A Linreg

9

Serial Power• Disadvantages– Slightly higher dissipation in chip
– AC coupled output needed to/from module• Added buffer and components on module• Challenges– Keep module to module noise pickup low

AC interface to/from pixel module• Shown to be low in test system– Examine all possible failure modes anddevelop protection schemes• Chip failure (shunt reg, overcurrent,
etc)• Bond pad failure– Integrate into future FE chips
November 7-11, 2005

Vertex 2005, Nikko, Japan

Iin

Iout
10

Wafer Thinning•

Detectors and readout chips make asignificant contribution to multiple scattering– Every 100 D of silicon is 0.1% X0– Hybrid pixels have 2 layers of silicon, eachgreater than 100 D thick••Take advantage of work being done inindustry by major companies (IBM, INTEL,
Toshiba, etc.) to reduce wafer thickness
Thinning

Thinned IC wafer (J. Joly, LETI)– Thinning to 50 microns is in production– State of the art – CMOS wafers thinned to 1015 microns by lapping/grinding followed bywet or plasma etch and CMP. Thinner for SOI.

•

Challenges– Handling/breakage– Thickness uniformity on large wafers– Circuit performance changes due to thinning• No change in Vt for 25u wafer (Fraunhofer,
IZM)• No change in Idsat for 25 u wafers (IZM)• More tests needed
November 7-11, 2005
Vertex 2005, Nikko, Japan

Thinned 200 mm wafertransferred on to glass
handle wafer (A.Young, IBM)11

Monolithic Active Pixel Sensors (MAPS)• Hybrid Pixel sensors have achieved a levelof maturity in HEP. Continuing future
problems are cost, mass, and cooling ofdetectors under high radiation.
• CCDS can be thin but need separate support
chips. They are not covered in this talk.
• Much work is being done on MAPS toreduce mass.
• A MAPS is a silicon structure where thedetector and the primary readout electronics
are processed on the same substrate.
– Note, only the top few microns of an IC
contain active circuitry.
– The rest is merely a support structure.

• MAPS can be divided into twoclassifications:– Those using standard CMOS processes.
– Those using specialized processes

Readout Chip

DetectorHybrid Pixel Principle
ROC

N-wellDetector
Non-active Substrate
MAPS Principle
Kucewicz, Krakow

November 7-11, 2005

Vertex 2005, Nikko, Japan

12

Standard CMOS Processes
NMOS
circuitryin P-well• MAPS with epi layer– Many groups studying concept – RAL, IReS,
Hawaii, INFN, etc.
– Most collect charge by diffusion from epi layer(5-15 um) & some charge from substrate– Challenges

Epitaxial
layer• Transistor options are limited• Many newer processes have thinner or no epi,
resulting in very small signals• TFA – Thin Film Active Pixel Sensor– Activity centered at CERN
– Radiation hard sensors, fast collection time
– Challenges

CMOS Monolithic Active Pixel Sensor
J. Velthuis, Liverpool• Low noise readout to handle small signals• Development of non-commercial process• Biggest advantage to CMOS MAPS is thelong term existence of the basic processes.

Thin Film Active Pixel Sensor
P. Jarron, CERN

November 7-11, 2005

Vertex 2005, Nikko, Japan

13

Non-standard Processes• Silicon on Insulator Detector

RO circuit
SiO2
wafer bondHigh resistivity
detector substrate– Work progressing at Poland, Italy– Should be rad hard, can have NMOS + PMOS
– Challenges• Fabrication of circuits at both sides of BOX• DEPFET

Silicon on Insulator Detector– Work centered Bonn, Mannheim, MPI– Uses high resistivity substrate for sensor, provides large
signal with low input capacitance– Challenges• Needs additional readout chips => more mass

• 3-D sensor– Work lead by Parker: provides high speed signals– No working model with readout chip at this time

DEPFET detector
N. Wermes, Bonn

• The biggest concern with all non-standard
processes is whether the process will matureand sill be available 10 years from now.
Remember DMILL!!
November 7-11, 2005

Vertex 2005, Nikko, Japan

3-D
sensorS. Parker, Hawaii

14

3D Circuits• Movement building within industry to develop 3D chips to meet ITRS
(International Technology Road map for Semiconductors)
requirements for increased speed and density.
• What is a 3D chip?
– A 3D chip is comprised of 2 or more layers (N) of semiconductor
devices which have been thinned, bonded, and interconnected toform a monolithic circuit.
– Frequently the layers are comprised of devices made in different
technologies.
• Reasons for 3D in industry– Reduce interconnect length (R, L, C)• Improve speed ( N1.5)• Reduce interconnect power ( 1/N0.5)• Reduce crosstalk– Reduce chip footprint size
– Process optimization for each layer• Can HEP take advantage of thistechnology?
November 7-11, 2005

The industry dream
Vertex 2005, Nikko, Japan

J. Joly, LETI

15

•

Wafer to wafer or die to wafer

3D Options
Known good die

Or

Wafer to wafer•

Die to wafer

Bonding chemistry

J, Lu, RPI••

Thinning - before or after bonding
Face to face, or face to backLayer 2
Layer 1•

Vias – Deep, Short, None
November 7-11, 2005

Face to Back CMOS Face to Face CMOS
Deep (25 D)

Deep, none

Vertex 2005, Nikko, Japan

Face to Back, SOI(Similar to MAPS SOI)
Short (1-10 D)
16

State of 3D• State of the art– Numerous option combinations
are being studied– Three and four layer stacks• A few commercial productsannounced• International effort is underway

3 layer cross section(Tezzaron)

USA:
Albany Nanocenter
U. Of Kansas,
U of Arkansas
Lincoln Labs, AT&T
MIT,RPI, RTI, TI
IBM, Intel, Irvine Sensors
Micron, Sandia Labs
Tessera, Tezzaron,
Vertical Circuits, Ziptronix
November 7-11, 2005

Asia:
ASET, NEC, University of Tokyo,
Tohoku University, CREST,
Fujitsu, ZyCube, Sanyo,Toshiba, Denso, Mitsubishi, Sharp,
Hitachi, Matsushita, Samsung
Europe: Fraunhofer IZM, IMEC Delft,
Infineon, Phillips, Thales, Alcatel Espace,
NMRC, CEA-LETI, EPFL, TU Berlin
Vertex 2005, Nikko, Japan17

3D Circuits in HEP••

Use in high density applications forexperiments starting in 2010 or later
Options– For detector applications use wafer to die
bonding to provide optimal yield– Although SOI processes are easier to thin, use
CMOS since CMOS processes are more
readily available•

Advantages

100 microns
RO chip
Detector
Step 1 - Thinned, no vias,
three side buttable, face to face
75 microns
RO chip
Detector– Offers best detector and readout technologies– Can increase circuit density without going tosmaller feature size process
Digital– Can use standard CMOS processes
Passive•

Disadvantage– Relatively early development stage•<100 microns

AnalogDetector

Challenges– Build multilayer chips that are 100 microns
thick or less.
– Handling thin circuits– Finding an industry or university partner

November 7-11, 2005

Step 2 - Thinned, deep vias,
four side buttable, back to faceVertex 2005, Nikko, Japan

Step 3 - Thinned, deep vias,
multiple layers, four side buttable

Possible dream pixel detector
for HEP
18

Higher Radiation Tolerance••

In last few years, HEP has moved away from
specialized rad hard processes.
Has been shown that commercial DSM processes can beused for HEP radiation hard designs.
– To overcome design problems due to threshold shift– To overcome transistor leakage current problems•

In commercial DSM processes– As gate oxides get thinner and thinner, threshold shiftswith radiation due to trapped interface states and trappedcharge become insignificant. (0.25 u CMOS)– Leakage current in field oxide still a problem in standard
0.25 u NMOS devices• Use special ELT (enclosed layout transistor) layout
rules (However, there is a design and size penalty)– How does radiation tolerance change at even smallerfeature size processes (0.13 u and below)• Can special layout rules be waived?
• Can tolerances > 100 Mrads be achieved?
November 7-11, 2005

Vertex 2005, Nikko, Japan

Standard Transistor Inverter

Enclosed Transistor Inverter
19Preliminary Radiation Results at 0.13u••

For ELT, no change in NMOS Vt orleakage current observed up to 140 Mrads
Core NMOS linear device performance– Leakage changes for all size devices– Vt changes for small devices– Changes due to Radiation Induced Narrow
Channel Effect (RINCE) –see F. Faccio.

•

Core PMOS (linear) device performance– No change in leakage for all device sizes– Apparent Vt shift for narrow device sizes

F. Faccio, CERN

November 7-11, 2005

Vertex 2005, Nikko, Japan20

0.13 micron (cont.)• Effects observed in 0.13 D were found to be dependent on dose rate
and temperature• The Total Ionizing Dose tolerance of the 0.13 D appears to be better
than a 0.25 D process.
• Challenges– How to design a circuit that takes advantages of the 0.13 - process and at
the same time minimizes the size of the circuit without using ELTs.
• Should circuits be pre-irradiated?
• Can standard cell libraries be used?
• Is overall circuit performance limited by I/O structures that have thicker gate
oxides?
• Will eventual process changes affect radiation performance?
• Are there any other problems that might be found at 0.13 - and how mightthese change for deeper sub micron processes?

– Investigate 0.13 - processes from other foundries
November 7-11, 2005

Vertex 2005, Nikko, Japan21

High Speed/Performance•

Bipolar front end circuits have been used with higher capacitancedetectors where fast shaping, low noise and low power are required.
– ATLAS SCT, Zeus LPS, etc.
– Separate CMOS readout used•High speed BiCMOS processes now available using SiGe (strained
silicon).
– Some current foundries: IBM, STM, AMS, IHP (Germany)•

Characteristics of SiGe BiCMOS process– Very high quality, high speed bipolars (200 GHz)
– Deep submicron CMOS for low power operation.

• Features of SiGe bipolar devices––––

Significant broadband and 1/f noise improvement over standard BJTs
SiGe BJT are inherently more radiation hard than standard BJTs
Noise does not change with radiation
Some unusual cryogenic features• As temperature goes down for BJTs, beta, speed, and noise get worse• As temperature goes down for SiGe, beta, speed and noise get better.

November 7-11, 2005

Vertex 2005, Nikko, Japan

22

Some SiGe applications for HEP•

SiGe CMOS technology proposed for ILC
and SLHC– ILC (J. Genat)• Front end circuitry for Silicon tracker: 50 pF
detector and noise < 1000e @ 3usec shaping– SLHC (E. Spenser)• At 20 cm, readout for short strips with Cdet
= 5 pf with fluence of 1015 n/cm2• At 60 cm, readout for strips with Cdet = 15
pF and fluence of 3 x 1014 p/cm2• Good radiation performance of SiGetransistors is critical– ATLAS replacement for ABCDS/FE using
IHP SG25H1 SCT-FE• Power saving for 25 pF detector: 1.5 mW/ch=> .36 mW/ch••

Other applications: High speed
communication, low noise cold electronics,
detectors.
Challenges: Cost, availability, consistency,
and yield from different vendors need tostudied by HEP community.
November 7-11, 2005

Radiation performance appears
to be acceptable for SLHC

Vertex 2005, Nikko, Japan

E. N. Spencer, SCIPP-UCSC

23

Process Obsolesce• Long term projects (and even some short term
projects) must face the challenge of process
obsolescence or foundry management changes– Causes rushed designs– Must buy large quantities of spares to cover loss of process.
– Obsolete processes – UTMC, DMILL, to name a couple– Largest CMOS feature size currently readily available through
MOSIS, CMP, Europractice is 0.7 microns. Look at trend for
SVX chips.

• Challenge– Plan ahead– Live with ever changing market
November 7-11, 2005

Vertex 2005, Nikko, Japan

24

CMOS Feature Size Decrease
SVX Feature Size vs. Year

CMOS Feature Size in Microns

3.5
3

SVX - Silicon Strip Readout Chips for
CDF and Dzero at Fermilab

SVX

2.5
SVX4 Photo
2
1.5

SVX2

1

SVX3

0.5
0

SVX4
1989

1996

1999

2003

Year Device went into Production
November 7-11, 2005

Vertex 2005, Nikko, Japan25

Selected Portions of ITRS
(International Technology roadmap for Semiconductors)

Table 81 a

November 7-11, 2005

Table 81 b

Many technological problems,
the next simplest approach could be
reducing trace length by going 3D.

Solutions are
known
Solutions are
not known

Vertex 2005, Nikko, Japan26

IC Fabrication Cost
• Can HEP afford 0.13 u and below DSM for lower
power, less mass, higher radiation, higher speed?
• Cost considerations– Design cost appears in several different ways
• Minimize number of design iterations– Use experienced designers when possible• Cost of tools - must upgrade with processes– FNAL tools» Cadence (DIVA, ASSURA, Dracula, Virtuoso)» Mentor (ELDO, Calibre, Mixedsignal simulation, Verilog)» Synopsys (Nanosim)– Maintenance ($325K/yr)– Wafer processing cost is not the major issue– Mask cost is a major issue

200 mm SVX wafer– Challenge• Maintain current IC designer experience for HEP• Share mask costs whenever possible
November 7-11, 2005

Vertex 2005, Nikko, Japan27

Mask Cost for CMOS Processes
900000800000

Cost in Dollars

7000006000005000004000003000002000001000000

From: E. Seebacher
11th LHC Electronics Workshop

1.2

0.8

0.6

0.35

0.25

0.18

0.15

0.13

Feature Size in Microns
November 7-11, 2005

Vertex 2005, Nikko, Japan28

Challenges and the Future•••

Technology tradeoffs must be made depending on the application.
As a general rule good tools and experienced designers will reduce the numberof design iterations saving development time and overall cost.
A few questions to think about– What is the proper balance between on chip regulation (higher power
dissipation) with the potential reduction in cabling mass and power?
– Will special design rules still be necessary at smaller CMOS features
sizes, or at what level will the special design rules be necessary– Will wafer thinning and 3D circuits become practical for HEP– Can power ramping be made to work in future very large systems• Readout stability• Thermal cycling• Pickup– Can analog information be given up to reduce
system complexity and reduce power dissipation?
– Can designs be tested in larger feature sizes to save development money• Similar thing was done before with rad soft to rad hard design process.

••Many questions – lots of work to be done
Start thinking now - the future is just around the corner
November 7-11, 2005

Vertex 2005, Nikko, Japan29

References
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C. Hoermann, PSI, Performance of CMS pixel detector Barrel Modules, 11th Workshop on Electronics for LHC, Heidelberg, September 2005.
D. B. Ta, et. al., University of Bonn, Serial Powering – Concept, Realization and Characterization of serially Powered Pixel Modules, 11th
Workshop on Electronics for LHC, Heidelberg, September 2005.
Marc Weber, et. al., RAL, Serial Powering for Silicon Strip Detectors at SLHC, 11th Workshop on Electronics for LHC, Heidelberg,
September 2005.
Jean-Pierre Joly, LETI-CEA, New Wafer to Wafer and chip to Wafer Device Stacking Technology Implementations, 3D Architectures for
Semiconductor integration and Packaging, Tempe, Arizona, June 2005.
A. M. Young, IBM, Perspectives on 3D-IC Technology, 3D Architectures for Semiconductor integration and Packaging, Tempe, Arizona, June
2005.
R. Wieland, et. al., Fraunhofer IZM, 3D Integration of CMOS Transistors with ICV-SLID Technology, 3D Architectures for Semiconductor
integration and Packaging, Tempe, Arizona, June 2005.
J. Lu, et. al., Rensselaer Polytechnic Institute, Wafer-Level Hyper-Integration Technology for 3D ICs and Packaging, 3D Architectures for
Semiconductor integration and Packaging, Tempe, Arizona, June 2005.
K. Williams, Research Triangle Institute, Pixelated Architectures: Drives for 3D integration Techniques, 3D Architectures for Semiconductor
integration and Packaging, Tempe, Arizona, June 2005.
B. Patti, Tezzaron Semiconductor, FaStack Technology, 3D Architectures for Semiconductor integration and Packaging, Tempe, Arizona, June
2005.
F. Faccio, et. al., CERN, Radiation-induced Edge Effects in Deep Submicon CMOS Transistors, to be published December 2005.
John Cressler, Georgia Institute of Technology, Assessing SiGe HBT Technology for Front-end Electronics Applications, 5th International
Meeting of Front-end Electronics, Snowmass, Colorado, June 2003
J. Genat, LPNHE, Paris, Front-End and Readout Electronics for Silicon Trackers at the ILC, Linear Collider Workshop, Stanford, Califorina,
March 2005.
E. N. Spencer, SCIPP-UCSC, Evaluation of SiGe BiCMOS Technologies for Next Generation Strip Readout, 11th Workshop on Electronics for
LHC, Heidelberg, September 2005.
E. Seebacher, Austria MicroSystems, Characterization and SPICE Modeling, 11th Workshop on Electronics for LHC, Heidelberg, September
2005.
P. Jarron, et. al., CERN, TFA Pixel Sensor Technology for Vertex Detectors, Vertex 2004, Como, Italy October, 2004
W. Kucewicz, AGH Univ of Science and Technology, Fully Depleted Monolithic Active Pixel Detector in SOI Technology, Bonn, February 3,
2005.
N. Wermes, Bonn University, Pixel Detectors, 11th Workshop on Electronics for LHC, Heidelberg, September 2005.

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30