Development ofwith PC104plus

a Pipeline CAMAC controller
single board computerIEEE –NPSS Real Time Conference 2003, 18-23 May 2003

Yoshiji Yasu, Eiji Inoue, Hirofumi Fujii, Youichi Igarashi,
Masahiro Ikeno, Manobu Tanaka, Kazuo Nakayoshi, Hideyo
Kodama, Shuichi Harada2 and Haruyuki Kyoo3
High Energy Accelerator Research Organization ( KEK ),Tsukuba, Japan(http://www-online.kek/jp, http://onlax2.kek.jp/~kairo/ ,e-mail: Yoshiji.YASU@kek.jp)
2TOYO Corporation, Tokyo, Japan(http://www.toyo.co.jp/ )3Fird Corporation, Tokyo, Japan(http://www2.ocn.ne.jp/~fird/)

Abstract
A pipeline CAMAC controller with PC/104-Plus single board computerhas been developed. The architecture of the pipeline CAMAC controller
is completely different from that of traditional CAMAC controller. Thepipeline CAMAC controller adopted truly pipelined command and data
paths from/to computer memory to/from CAMAC. The pipeline method
enabled the controller maximum speed of CAMAC, approximately up
to 3 MB/sec with 24-bit data. The controller also has a DAQ function
such as event numbering for co-existence with other equipment such asVME.
Not only the functionality and the performance but also the pipelinearchitecture and the design concept are described.

Overview of Pipeline CAMAC controller
Fast Ethernet

PC104plus PC board computer
PCM-9370's Crusoe TM5400,
Memory, Flash Disk, Ethernet,
USB, …
ALTERA FPGA for PCI
ALTERA FPGA for CAMAC

The pipeline CAMAC controller consists of a PC/104-Plus-based single board
computer, PCI interface (PCI control) and CAMAC interface (CAMAC control).

Overview of Pipeline CAMAC controller (cont.)
The PC/104-Plus is a standard PCI specification forembedded systems. Many PC/104-Plus based single board
computers are available.
The PCI and CAMAC interfaces consist of an ALTERA
FPGA, respectively . Those VHDL codes for the interfaces
have been also developed.
The board computer adopted is Advantech PCM-9370, 3.5inch (145 x 102 mm) Transmeta Crusoe 500 MHz processor
single board computer including TM5400 processor, 320 MBmemory, two IDE UltraDMA33 (with 512MB flash disk),
LCD/CRT controller, 10/100 Mbps Ethernet controller, two
1.1 compliant USB ports, mini-din connector for keyboard,
PS/2 mouse and so son. The power consumption is typically
10.7W.

Architecture of CAMAC control
There are a CAMAC Executor, a CAMAC
LAM Handler (CAMAC Interrupter), a DAQExecutor and a DAQ Trigger Handler (DAQInterrupter). The Executors accept a packet
including at least a command frame or morefrom CPU via PCI, execute them and thensend reply frames to CPU. The frame is anunit of CAMAC access.
The pipeline CAMAC controller can execute CAMAC command with small
overhead continuously by getting the command frames from a computer memory
and then sending the reply frames to the computer memory, via PCI bus. Thecommand FIFO and the reply FIFO have the size of 256 frames each. TheInterrupters generate a packet including a reply frame and then send to CPU.

Frame format
Command and reply frames have 64-bit fixed-length. It consists of an 8-bit
header and a 56-bit payload. The payload for basic CAMAC command frame
contains CAMAC station number N, CAMAC sub-address A, CAMAC
function F and data to be written if necessary. That for the reply frame
additionally contains CAMAC status such as Q & X and read data if theCAMAC function is read. That for CAMAC LAM includes 24-bit LAM
pattern and that for DAQ Trigger includes 32-bit event count. DAQ executor
can clear Busy-out signal while next event trigger is disabled.

Architecture of PCI control
There are, Tx/Rx FIFO, Tx/Rx engines
and PCI multiplexer for Tx/Rx. Tx andRx engines work independently while
PCI multiplexer manages the PCI
usage for Tx and Rx engines. Tx/Rx
FIFOs have the depth of 256 with 32bit width each.
The pipeline CAMAC controller sends multiple command frames, which
include N, A, F and data if necessary, via Tx I/O registers. On the other hand,the controller receives multiple reply frames, which also includes N, A, F,status (Q and X) and data if necessary, via Rx I/O registers. The operations toTx and Rx are done concurrently, independently, or asynchronously. If DMA isused in both sides, the throughput reaches maximum speed.

Operation and PCI I/O registers
The PCI I/O register map includes three kinds of registers. One is for Tx andanother is for Rx. The other is system register. Those registers are located inPCI I/O space and the size of those registers is 32-bit.
In programmed I/O, data1 and data2
registers for Tx and Rx are used forsending command frames and receiving
reply frames, respectively.
In block I/O, memory preset count register
represents the number of frames in quadword (8 bytes) to be transferred.
After the transfer is initiated by setting DMA-start flag, the actual countregister counts the number of frames in quad-word (8 bytes) transferred
actually.

Software
A Linux distribution kit tailored for the pipeline CAMAC controller isimplemented on the PC/104-Plus single board computer while Linux is Open
Source Software / GNU products, a commodity Open Source Operation
System for PC compatible hardware.
The device driver and the library for the pipeline CAMAC controller havebeen developed. CAMAC and DAQ command frames are generated and thenstored into a frame buffer by the frame generator. The command frames in aframe buffer are executed by Programmed I/O routines, Block I/O routines orthe combined routines in same manner. The reply frames are stored intoanother frame buffer as result of the command frame executions. The replyframe includes CAMAC status and data. The extractors of the status and thedata from the reply frames are provided. The wait routines for LAM interrupt
and Trigger interrupt are also available.

Design Concept
The pipeline CAMAC controller
adopted truly pipelined commandand data paths from/to computer
memory to/from CAMAC.
The pipeline method enabled the controller maximum speed of CAMAC access,approximately up to 3 MB/sec with 24-bit data. In the pipeline method, themultiple command frames and the multiple reply frames are processedasynchronously, independently or concurrently. The pipeline method is best forthe speed up of I/O throughput. The method is generally usable, namely, as theaccess method to I/O object controller, which includes not only CAMAC but
also readout equipment such as Flash ADC.

Performance
CAMAC executor executes a
CAMAC command frame in1.04 usec. The horizontal
axis is timing in unit 1 usec.
Each CAMAC cycle iscontinuously done in 1.04
usec The speed wasachieved by the DMA
operation.
In fast mode which ignores
CAMAC S2 timing signal, it
executes the command frame
in 0.72 usec.

CAMAC timing

Conclusions¾ A pipeline CAMAC controller with new architecture hasbeen developed.
¾ The CAMAC access speed reached up to maximum speedof CAMAC, approximately 3 MB/s with 24-bit data.
¾ The pipeline method will be useful for not only CAMACcontroller but also other controller, generally, I/O objectcontroller.

References¾ IEEE, "IEEE Standard Modular Instrumentation and Digital Interface System (CAMAC)(Computer Automated Measurement and Control) IEEE Std 583-1975¾ PC/104 Embedded Consortium, PC/104-Plus Specification Version 1.2, August 2001
¾ Altera Corporation, http://www.altera.com/¾ Advantech Co., Ltd., Board computer PCM-9370
http://www.advantech.co.jp/epc/SBC/biscuit/pcm9370.html¾ Home page of Parallel CAMAC project,
http://www-online.kek.jp/~yasu/Parallel-CAMAC/¾ Yet another page of Parallel CAMAC project in Japanese,
http://www-online.kek.jp/~inoue/para-CAMAC/¾ TOYO Corp., CAMAC Crate Controller type CC/7700 and Host Interface Board types CC/ISAand CC/PCI in Japanese,
http://www.toyo.co.jp/daq/index.html¾ KineticSystems Corp., VME to 3922 Interface w/DMA model 2917-Z1A & Model 2915-Z1A& PCI Interface to 3922 Model 2915-Z1A & Parallel Bus Crate Controller Model 3922-Z1B,
http://www.kscorp.com/www/products/camac.htm