The Open Era of Computing
Calista RedmondCEO, RISC-V International
November 2021

Thank you!

Open source and collaboration
are strategic to software and hardware
across industries.

This is theOpen era ofcomputing
Photo by THIS IS ZUN from Pexels

RISC-V is the free andopen Instruction Set
Architecture…

Open collaboration…

Design freedom…

Strategic future

Disruptive Technology
Barriers

Legacy ISA

RISC-V ISA

Complexity

1500+ base instructions
Incremental ISA

47 base instructions
Modular ISA$$$ – Limited

Free – Unlimited

License and Royalty
fees$$$Free

Design ecosystem

ModerateGrowing rapidly. Numerous extensions andcores. More design companies on RISC-V thanany other architecture

Software ecosystem

Extensive

Growing rapidly. Easy to compile for RISC-V

Design freedom

Unconstrained Opportunity
RISC-V Business ModelBarriers removed▪

Design risk▪

Cost of entry▪

Partner limitations▪

Supply chain

Collaboration
partners
Development

Supply chain

Expandedmarkets

Expandedgeographies

6

Beyond removing barriers,
RISC-V fuels our community toseize growing opportunities

50 billion
connectedand IoT
devices by2030

Source: Strategy Analytics

By 2025, 40% of application-speciﬁcintegrated circuits (ASICs) will be
designed by OEMs.

Custom ASICs Basedon RISC-V Will Enable
Cost-Eﬀective IoT
ProductDiﬀerentiation
Gartner, June 2020
Source: Gartner

The RISC-V CPU core market will grow at 114.9%
CAGR, capturing over 14% of all CPU cores by 2025
Nearly 80 billion RISC-V
CPU cores by 2025

Source: Semico Research Corp, March 2021

“The rise of RISC-V cannot be ignored...
RISC-V will shake up the $8.6-Billion
semiconductor IP market.”-- William Li, Counterpoint Research

Source: Counterpoint Research, September 2021

Growth in RISC-V IP, SW, and Tools is alreadyhappening
The total market forRISC-V IP andSoftware is expected
to grow to $1.07
billion by 2025 at a
CAGR of 54.1%

Source: Tractica, December 2019Today, nearly a quarter of designs incorporate
RISC-V

23% of ASIC and FPGA
projects incorporated
RISC-V in at least one
processor in a 2020 study.

Source: Tech Design Forum, November 2020

●Intel Nios processor based on
RISC-V, designed for performance.

●Alibaba RISC-V Xuantie processorline including four open sourced
processors for cloud and edgeservers●Imagination RISC-V CPU family, forboth the discrete CPU andheterogeneous computing markets●Seagate hard disk drive controller
with high-performance RISC-V CPU.

DataCenterCloudHPCTelecom &Communications●Andes 64-bit RISC-V processor has been
adopted by SK Telecom for thedevelopment of AI products.

●Alibaba PLCT Lab has ported Android 10
onto its in-house 64-bit RISC-V coreemulated in QEMU

●Google Pixel 6 Titan M2 in-house designed
RISC-V processor, with extra speed andmemory, and even more resilient toadvanced attacks.

●European Processor Initiative RISC-V
accelerator with ﬁrst chip Sep 2021●

Technical University of Munich (TUM)
quantum cryptography chip for quantum
computing security demands●

Tactical Computing Labs HPC-centricsoftware test suite for GCC and LLVM●

Cortus is developing a high-performance
RISC-V Out-of-Order processor core for
the European eProcessor project.

●

De-RISC market-ready HW-SW platform
for a multi-core RISC-V system-on-chipfor safety critical aerospace applications

HighPerformance
Computing

Johanna Baehr of TUM heads a team that has hidden four hardware Trojans on thischip - malicious functions that are integrated directly into the circuits.
Image: Astrid Eckert / TUM

EdgeComputing

A distributed, open architecture decentralizes
processing power, reduces latency, andsupports IoT performance in low bandwidthenvironments at low power.
●

Seeed Studio’s new development, theSipeed MAIX, a RISC-V 64 AI board forEdge Computing makes it possible toembed AI to any IoT device.

●

Micro Magic announced an incredibly
fast 64-bit RISC-V core achieving 5GHz
and 13,000 CoreMarks at 1.1V.

●

Western Digital SweRV Core enables
spectrum of compute at the edge

Artiﬁcial intelligence spans many areas from
Industrial IoT to ﬁnancial●Esperanto Emerges From Stealth With
1,000-Core RISC-V AI Accelerator.

●

StarFive released the world’s ﬁrst
RISC-V AI visual processing platform●

Andes released superscalar multicore
and L2 cache controller processors.

●

NVIDIA CUDA support on the Vortex
RISC-V GPGPU enables scaling from
1-core to 32-core GPU based on
RV32IMF ISA with OpenCL 1.2 graphics
API support.

AI / ML

Consumer
and IoTdevices●Huawei Hi3861 RISC-V board forHarmony OS developers for the IoTmarket●Zepp Health / Huami wearable
manufacturer OS supporting RISC-V
Reference Models for RISC-V P extension●GreenWaves ultra-low power GAP9
hearables platform for scene-aware andneural network-based noise reduction.

●Microchip released the ﬁrst SoC FPGA
development kit based on the RISC-V ISA.

●RIOS Lab announced PicoRio, anaﬀordable RISC-V open source
small-board computer.

●

SiFive world’s fastest development boardfor RISC-V Personal Computers.

●Imagination Technologies GPU can belinked together by a RISC-V core for ASIL-B
level designs with ISO26262 safety criticalcertiﬁcation.

●IAR Systems extended the functionalsafety version of its Embedded Workbench
software tool chain to the RISC-V core ofNsitexe, subsidiary of automotive leader
Denso.

●

Renesas and SiFive jointly develop next
generation RISC-V SoCs for automotive●

Renesas and NSI-TEXE announce
automotive SoC with RISC-V-based parallel
co-processor●

Europe’s GaNext project to simplify
designing power converters with GaN
power semiconductors while improving
eﬃciency and compactness for systems
such as electric vehicle chargers.

Automotive

“The scalable range of performance,
selectable safety features, andcustomization options provided by theAndes RISC-V core IP enables
Renesas to provide innovative
solutions for futureapplication-specific standardproducts,”--Sailesh Chittipeddi, EVP and GM,
Renesas IoT and Infrastructure

Renesas RISC-V ASSP
products use CPU coresfrom Andes for design
diﬀerentiation fromlow-end products●●●

Renesas ASSPs equipped with Renesas
ﬁrmware.
Renesas ASSPs are dedicated devices, user canset parameters of application programs.
Renesas plans a user interface to make iteasier for users to optimize solutions to theiruse case.

Renesas and SiFive partner for next generation high-end in-vehicle RISC-V SoCs and microcontrollers● RISC-V core and AI accelerators provide Renesas performance and scalability for in-vehicle
applications.
● SiFive's RISC-V cores oﬀer trace and debugging capabilities compatible with prevailing industry tools.
● Security solution is integrated to simplify integration and migration between diﬀerent models.
● SiFive RISC-V cores are silicon proven (veriﬁed to work within actual chips) and can be produced by amajor Si foundry with advanced fabrication technologies.

●Combines the advantages of a CPU,
GPU, and a dedicated LSI.

●Architek architecture processes AI
workloads with signiﬁcantly lower
power and higher eﬃciency than
general-purpose CPUs and GPUs.

●Targets AI processing for IoT edge. The
chip made by TSMC 12nm process is
4.5mm by 4.5mm, and its power
performance enables fan-less designs.

AI processor AiOnIc
by ArchiTeK with
SiFive's E3 series
RISC-V processor IPin addition to theArchiTek Intelligence
Pixel Engine (aIPE).

®

Acceleration, eﬃciency, reduced power.

NSITEXE AI accelerator ML041●The AI accelerator ML041 executes Neural networks (e.g. VGG16, MobileNet, and ResNet) at powereﬃciency of 12TOPS / W using 7nm geometry.

●

ML041 divides input data (Tiling) and concatenates the input and output of multiple layer processing toprocess the intermediate data. This reduces the data transfers with the external memory improving
the power performance.

●

ML041 also provides
a built-in diagnostic
circuit to detectrandom hardware
failures enabling AI
applications insafety-critical systems.

NSITEXE DR 1000 C, a RISC-V vector
processor●NSITEXE licensed Renesas DR 1000 C, a RISC-V-based vector accelerator
for arithmetic processing (e.g. model predictive control, real-timemodeling, sensor data processing) to meet automotive safety-criticalrequirements.

Ubiquitous AI Corporation’s RISC-V
Network Framework
Ubiquitous AI Corporation is creating RISC-V Middleware for implementing
communication functions based on the TCP / IP stack.

Dedicated Community
Services Fab,Chip SoC, IP, FPGA

design services

I/O Memory,

network, storage

Universities
and Research

Software Dev tools,

Industry cloud,ﬁrmware, OSmobile, HPC, ML,automotive

Press and Analysts

Investors and Funding
Individual Advocatessources27More than 2,400 RISC-V Members
across 70 Countries

104 Chip
SoC, IP, FPGA

Sept 2021

3 Systems
ODM, OEM

4 I/O

12 Industry

Memory, network, storage

Cloud, mobile, HPC, ML, automotive

18 Services

103 ResearchFab, design services

Universities, Labs, other alliances

46 Software

2k+ Individuals

Dev tools, firmware, OS

RISC-V engineers and advocates

RISC-V membership grew 133% in 2020.
In 2021, RISC-V membership has already doubled.

28…

…

RISC-V is thefoundation of
the Open era ofcomputing…

…

4k+ individuals in 60+ RISC-V
work groups and committees
330+ RISC-V solutions online

including cores, SoCs, software, tools,and developer boards

29 local RISC-V community
groups, with more than 5,400
engineers
We’re in the news! We have 40k+
followers on social media andacross the last year, we haveparticipated in 135+ news articles
along with amplifying RISC-V community
news 450+ times.

Technical Deliverables
Technical governance
Build technical deliverables
Work groups

Learning & TalentMulti-level online learning
Connecting universities withlabs, tests, and curricula
RISC-V Training Partners
Jobs and internships

Compatibility &Veriﬁcation

Visibility

Testing and compatibility
resources
Compatibility tests

Amplify member news, content,and success with press andanalysts
Original content programs
RISC-V, industry, and regional
events

Advocacy + Alliances

Marketplace Exchange

RISC-V Ambassadors
Geo and industry alliances
Local developer groups and events

Online marketplace ofproviders, products, services, andlearn
Technical developer forums

RISC-V delivers incredible
member support

RISC-V tech roadmap

RISC-V Innovation Roadmap AI SoCs, Application

Test Chips
Software tests
Linux port
2010 – 2016

ISA Deﬁnition
RISC-VFoundation

Proof of Concept SoCs
Minion processors for
power management,communications
Bare metal software
2017

RV32

2018

IoT SoCs
Microcontrollers
RTOS, Firmware
Development tools
Technical Steering
Committee,
HPC SIG,
GlobalPlatform
partnership
2019

RV32I and RV64I
Base instructions:Integer, ﬂoating
point, multiply anddivide, atomic, andcompact instructions
Priv modes,
Interrupts,
exceptions, memory
model, protection,and virtual memory* On track, subject to change

processors, LinuxDrivers, AI Compilers
Dev Board program
Development Partners
RISC-V Labs, Security
response process, AI
SIG, Graphics SIG,
Android SIG,
Communications SIG

2020

2021

2022

Arch compatibility
Zﬁnxframework,
ZiHintPause
Processor trace BitManip
VectorRISC-V Proﬁles &Platforms
Crypto Scalar
Virtual Memory
Hypervisor & Advanced
interrupt architecture
Cache mgt ops
Code size reduction*
Trusted Execution
Environment*
P (Packed SIMD)*

Industry Adoption
Proliferation of RISC-V CPUs acrossperformance and application spectrum
RISC-V dominant in universities
Strategic and growing adoption in HPC,
automotive, transportation, cloud,industrial, communications, IoT,
enterprise, consumer, and otherapplications
2023

2024

2025

RV32E and RV64E
64 bit and 128 bit addresses*
Vector Atomic and quad-widening*
Quad ﬂoating point in integer registers*
Crypto Vector*
Trusted Execution phase 2*
Jit pointer masking & I/D synch*
BitManip phase 2*
Cache management phase 2*… and more

Technical Deliverables

RISC-V Technical Programs
RISC-V Platform
A common, reusable
runtime environment that
operating systems andapplications can target to
improve portability andreuse. Provides
interoperability assurance.
RISC-V DeveloperBoards
Available to spurinnovation, provide
hands-on education,and engage early
adopters to test anddevelop.

RISC-V Development
Partner
Recognizes theinvestment anddedication oforganizations making
signiﬁcant technicalcontributions toRISC-V.

RISC-V Lab
Institutions that hosta lab with RISC-V
hardware for
CI/testing andgeneral availability
sandboxing.

RISC-V Compatible
Architectural Tests
created to help ensurethat software written will
run on implementations
that comply with that
proﬁle. Branding
available forcompatibility.

RISC-V ProﬁlesRefers to a base ISA andone or more extensions
that are speciﬁed as agroup so that applications
can be compiled once, run
on diﬀerent
implementations, and get
the same results.

RISC-V Ecosystem
HPC
Consumer

Data Center
IoT
Networking

Applications

SAIL

SPIK
E

Compilers

Simulators

Proﬁlers + Analysis Tools

CI/Testing

FormalModel

RTL

Architecture Tests
ISA
DV

Implementation Design & Microarchitecture
SiliconSoft IP

Services

SAIL

Debug

Boot

SecurityHypervisor

Performance

Operating Systems

Reliable, Serviceable, Diagnostic

Training
Academia
Research

RuntimesBeneﬁts
ofengaging
in RISC-V✔ Accelerate technical traction and insight✔ Contribute technical priorities, approaches, andcode✔ Gain strategic and technical advantage✔ Increase visibility, leadership, and market insight✔ Fill and increase engineering skills, retain andattract talent✔ Build innovation partner network and customerpipeline✔ Deepen, engage, and lead in local and industry
developer network✔ Showcase RISC-V products, services, training,and resources

Membership Options
Premier Member Beneﬁts• Board seat and Technical Steering Committee
seat included for $250k level• Technical Steering Committee seat included for$100k level• Eligible to lead workgroup and/or committee• Use of RISC-V Trademark for commercialization• Member logo / name listing on RISC-V website,alphabetical with Premier members• Solution / Product listing highlighted on RISC-V
Exchange, noted with member level• 4 case studies a year
• 2 blogs per month• 2 social media spotlights per month• Spotlight member proﬁle• Event sponsorship discountPremier Requirements• Membership open to any type of legal entity• $250k Annual membership fee that includes
Board seat and TSC seat
• $100k Annual membership fee that includes
TSC seat

Strategic Member Beneﬁts•••••••••

3 Board reps elected for the Strategic tier,including Premier members that do not
otherwise have a board seat
Eligible to lead workgroup and/or committee
Use of RISC-V Trademark for commercialization
Member logo / name listing on RISC-V website,alphabetical with Strategic members
Solution / Product listing highlighted on theRISC-V Exchange, noted with member level1 case study a year
1 blog per month
1 social media spotlight per month
Event sponsorship discountStrategic Member Requirements• Membership open to any type of legal entity• Annual membership fee based on employeesize• 5,000+ employees: $35k
• 500-5,000 employees: $15k
• <500 employees: $5k• <10 employees & company <2 yrs old: $2k

RISC-V Membership details
may be found online here

Community Member Beneﬁts•••

Two Board representatives
1 Community Board representative, elected
1 Individual Board representative, elected•

Member logo / name listing on RISC-V website,by member level1 case study a year
1 blog per quarter1 social media spotlight per quarter
Event sponsorship discount••••Community Requirements• Membership open to○academic institutions,○non-proﬁts,○
individuals not representing a legal entity• No annual membership fee

“The future depends on open
source tech, … RISC-V is gaining
traction in the hardware
manufacturing space throughout theworld, because it lowers barriers toentry and increases chip development
speed.”-- Wired“Though the architecture was created adecade ago by university professors,
RISC-V has been building its
ecosystem for years and has started
to hit its stride with big licensees like
Western Digital, SiFive, and even NVIDIA
itself.”-- VentureBeat“If it succeeds, RISC-V could lower the cost of developing a new chip and help
companies of all sizes to build exactly the processors they need.”-- Engadget

www.riscv.org@risc_v@Calista_Redmondrisc-v-international
calistaredmondThank You