The Journey of Two Novice LSI Enthusiasts:
Tape-Out of CPU+RAM
in Just One Month
Yuki Azuma / Kazuhide Uchiyama

RISC-V Day Tokyo 2023 Summer 2023/06/20

Self Introduction

Kazuhide Uchiyama, University of Electro-Communications,
Information Security Engineering Program @Cra2yPierr0t
I started building my own CPU to understand assembly language.
I have been an FPGA lover since then. I was researching a side-channel attack.
The abstract Chisato Nisikigi is my Internet name.

Self Introduction

Yuki Azuma, University of Tsukuba, Department of Physics @heppoko_yuki
l love to know how things work by building stuff from scratch. ex) OS, CPU
Recent work is accelerating the simulation code of cosmic ﬂuid dynamics in mybelonging lab.

We are CPU Enthusiast* CPU is BLACK-BOX* We hate BLACK-BOX* Shine the light and unravel BLACK-BOX!
* cpu-dev: The Group of CPU Enthusiasts

Application
Operating System
Computer Architecture
Micro Architecture
Logic
Digital Circuit
Analog Circuit
DevicePhysics

We are CPU Enthusiast
We used FPGA to make CPU then.
But FPGA couldn’t satisfy us, LSI is the truth.

cpu-dev group

Jacaranda-8: our original architecture
Tiny architecture
Implements interrupt

Jacaranda (fake Paulownia)
桐擬きmovaddandornotsllsrlsra

cmpjejmp

ldihldilldstiret

https://github.com/cpu-dev/cpu-dev.github.io/wiki/jacaranda-8_ISA_draft

Encounter with Open MPW Shuttle Program● There's something called Open MPW, apparently.
● They say we can make LSI with it for free.
● Why not join!

Open MPW Shuttle Program● The shuttle program started by Efabless● Skywater 130nm or GlobalFoundries 180nm● No production and shipping costs○224 WCSP chips and 2 evaluation boards● All tools and PDK are open source○Skywater PDK and OpenLANE● The 40 entries that pass the test among thosesubmitted are randomly selectedsky130(skywater 130nm process)● Developed by Cypress andmanufactured by Skywater● Began to be used around 2001
● 2020 PDK released by Googleand Skywater

OpenLANE Overview

OpenLANE● RTL-to-GDSII compiler made from a combination of about 20 OSS● It's all put together in a Docker container● Write Verilog and conﬁg and run to generate GDSII

Configuration of OpenLANE● Read the documentation
and write the TCL

path to verilog files
clock port
clock period
die size

conﬁg.tcl

Run OpenLANE● OpenLANE is executed with$ make <design name>● If successful, GDSII isgenerated with the analysis
results

Generating GDSII● Takes about 5 hours dependingon the design● Open MPW requirement is tobe reproducible from therepository

Generated GDSIIOpen Source Silicon Slack● 5676 members, 154 channels● Community for OpenMPW questions and EDA
tools OSS
● Supreme Developers Community
analog circuit channel

OpenRAM channel

One month to tapeout☆Death March to tapeout☆

Tapeout timeline
2020 Jul.

2021 Aug.

7/11 OpenMPW Announced

Sep.

Oct.

9/20 MPW-3 Announced

8/13 Kazu wrote
Japanese article of
OpenMPW Introduction

Nov.
10/29 Deadline
extended

10/4 Yuki and Kazu
decided to submit ourproject

11/15 MPW-3
new deadline

11/11 1:34 Tapeout test
succeeded!

2023 Jun 10
Our chips have arrived!

Day 0Verilog design
RTL Synthesis
Floorplanning
Placement
Static Timing Analysis
GDS2 design
Precheck
Tapeout check

We already had CPU HDL design then.

LSI chipDay 0
When Kazu knew the OpenMPW.
He was so fascinated.
No Japanese, No Knowledge➜ VLSI.JP !

Day 1

Our journey had started in Fukui.

10/4

19:00 Created Empty Project

14:30 Installed PDK・OpenLANE

Fukui Prefecture

21:30@Haneda Created Efablessaccount and GitHub repository
9:00 Decided to startOhminato Shrine since 1621

Installation point

Oshima Island in Fukui: The beginning

~Day 9Jacaranda-8 couldn't be synthesized as it was.
To enable synthesis, the battle with Yosys began...

Verilog design
RTL Synthesis
Floorplanning
Placement
Static Timing Analysis
GDS2 design
Precheck
Tapeout check

LSI chipDay 10

Verilog design
RTL Synthesis

Ultimately, synthesis succeed.

Floorplanning

Next battle target is... OpenROAD

Placement
Static Timing Analysis
GDS2 design
Precheck
Tapeout check

LSI chipOUT OF MEMORY!!!

Build Cycle
Placement &Routing start

Run OpenLANE

Super consuming
memoryChange conﬁg

Add swap toprevent OOM killer

Neglect computer(6h-24h)Day 11
SUPER Long Building time: 8 hours!
3 build/Day
Days remaining x 3= Number of Build opportunities

LSI BuildDear Bro♡
Buildcompleted!
01:38

Day 11Integrate other macro wasimpossible...
we didn't have knowledge and no documents
about macro placement.

Generating SRAM by Auto-Routing
Wanted to use OpenRAM

Novice’s RAM (Causes long build time)FACING MANY ERRORS!!!

Verilog design

Day 12 ~ 20

RTL Synthesis

Conﬁguration Battle, We are beginner
What is thisWhat is thisWhat is thisFloorplanning
Placement
Static Timing Analysis
GDS2 design

What is thisWhat is thisWhat is thisWhat is thisWhat is thisWhat is thisWhat is thisPrecheck

What is thisWhat is thisWhat is this

LSI chipTapeout check

Day 21 ~ 30

Verilog design
RTL Synthesis
Floorplanning
Placement
Static Timing Analysis
GDS2 design
Precheck
Tapeout check

Mysterious Tapeout Check

LSI chipDO完NE成Data Mem?

Inst Mem?

CPU?

Caravel Harness●Management SoC of the OpenMPW design●We can connect it by wishbone and logic analyzer wire●

Simulation with caravel is also provided.
○

Simulation including MSoC behavior is availableldi 01
mov r0, r3
ldi ffst r3, r0
ldi 41
mov r0, r3
ldi fdmov r1, r3
ldi feld r2, r3
ldi 01and r2, r3
cmp r2, r3
ldi 0cje r3st r1, r0
ldi 06
jmp r3// [0xff] ← 0x01 ; set status register// while([0xfe] == 0x01); ; wait until tx ready// set 'A' to TX register// loop

Summary* Finally, we could make our LSI without knowledge of semiconductor

engineering* Open Source Silicon slack members helped us much
* Fundamental documentation for newbie is not enough* Welcome to #japan-region

Expectations for OpenSourceSilicon* JAPAN!! COME ON!!
* Please write documentation more friendly for Software Engineer* We expect for widespread use in the ﬁeld of computational science!
expecting next system like GRAPE (N-body sim accelerator)* Please give us more recent PDK!

Acknowledgement* Efabless, Skywater, OpenSourceSilicon Slack, GoogleThank you for pleasant opportunities and support for us!
* Shumpei Kawasaki-san and RISC-V Days Tokyo
Thank you for inviting to precious Presentation time!
* Kristopher Tate-san and Takahiro Kinoshita-san
Thank you for rent an oscilloscope* And you…
We wish you a pleasant RISC-V Day andGood luck with the democratized LSI future!