AHB SecureSubsystem - ARM Cortex M3
Overview
The Silvaco Secure AHB Performance Subsystem is a highperformance AHB subsystem that allows for a high level ofhardware and software security. It integrates a securityconscious processor, the ARM Cortex-M3, with a securityconscious low power high-performance subsystem. Everythingis pre-integrated with the necessary AHB and APB IP cores
needed to run a small software kernel or a Real Time Operating
System (RTOS). This subsystem is ideal for any deeply embeddedsystem that requires enhanced security and protection fromcyber-attacks and intrusions, such as IoT, smart sensors, smart
controllers, and mixed signal devices.
Security in the Cortex-M3 is based on the MPU, Handler Mode,and privilege level. There are 8 memory ranges supported by theMPU and, it only regulates one Master component component the processor - in a multi-Master component system. To prevent
additional Master components from violating system integrity, theSecure AHB Subsystem adds the following IP• Secure AHB Fabric• SRAM Programmable Memory MPU• ROM Parameterized Memory MPU
The Secure AHB Fabric connects several AHB Master components(secure or non-secure) to several AHB Slave components (secureor non-secure) in a crossbar switch arrangement. In this system,
only the processor can produce secure AHB transactions, andall other AHB Master components are designated as non-secureat all times. AHB Slave components are categorized by theFabric as either secure or non-secure, depending on the levelof protection that is desired. A special case exists for memories,
which are designated as non-secure Slave components by theFabric. Security enforcement for memories is performed insteadby the SRAM Programmable Memory MPU and/or the ROM
Parameterized Memory MPU. This arrangement provides for
greater flexibility for each physical memory - each memory may
be divided into secure and non-secure regions - and potentiallyreduces the number of memory instantiations in the system.
The Secure AHB Fabric & Memory MPUs can be used stand-alone,
or in conjunction with the ARM Cortex-M3’s Memory Protection
Unit (MPU). The Secure Fabric can take care of all coarse memory
security partitioning leaving more room in the MPUs for finer tuning.
The subsystem’s AES core can be used to establish a Root ofTrust, with ROM code authenticating and decrypting a programfrom serial flash memory. A dedicated state machine canperform a direct load of encryption keys from an OTP memory,so the keys are never available to the processor. After bootup the AES, OTP, and even the ROM may be powered down
if desired. Once the program is decrypted and loaded intomemory, a hash signature in the boot header can be used toverify the code in memory before booting it.
Also included in the subsystem are Quad (or Octal) SPI – SerialFlash Controller, AHB Multi-Layer Fabric, Direct Memory
Access (DMA) controller, and Power Management (PMU) IPblocks. The subsystem is easily extended to add other user IPcores. The Q/OSPI performance may optionally be accelerated
with ARM’s Flash Cache IP, which is already pre-integrated into
the subsystem.

Target Applications

Configurable Peripherals• IoT Edge Devices• Secure AHB Fabric Interconnect• Mixed Signal Digital - MEMS

• GPIO (width, interrupt capability)• Smart Sensors, Smart Metering, Smart Lighting• I2C Master component• Health Monitors• I2C Slave component• Surveillance, Home Automation, Smart Thermostats• SPI Master component / Slave component• Machine/Motor Control, System Health Monitoring• Quad SPI Master component / Slave component (Octal SPIController optional)

Processor Options• 16550 UART

• ARM Cortex-M3 with low power logic, JTAG, MPU• Optional Instruction/Data Mux (Von Neuman or Harvard
Architecture)

Hardware Security Features• Optional ARM Flash Cache (order separately from ARM)

• SRAM & ROM MPUs

• ARM Memory Protection Unit (MPU) & Privilege level• AES H/W Encryption/Decryption

Infrastructure• Keys for AES can be in NV or OTP memory and directly
loaded into AES registers (No processor access)• CPU• Secure AHB Bus Matrix / Decode – 8 master component s,12 slave components• AHB to APB Bridge (2)• AHB Fabric is parameterized so each Controller and Target
can be designated as secure or non-secure• JTAG• If a non-secure AHB Controller attempts to access a secure
AHB Target, the access is blocked, bus info is captured, andan interrupt can be generated

Standard Peripherals

Software• 8,16,32-bit Internal SRAM Controller with MPU• An RTOS (such as FreeRTOS) may be used

• ROM with MPU• Secure Flash Loader, Boot Loader• Power Management Unit

• Examples using AES, Secure Fabric, and MPU• DMA (4 channels)• Interrupt and Fault Handlers• AES with optional secure key loader• Use of Main and Process Stacks• Windowed Watchdog Timer• Supervisory Call (SVC) examples• Timers (2)• Example test code for all IP Cores• Remap Register

Deliverables• Real-Time Clock• Verilog RTL source code
• Test bench with test suites• Documentation including User’s Guide and Integration Guide• Technology-independent synthesis constraints• C software example projects

For more information, please contact us at ip@silvaco.com.

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