Contributions
Open-Source IC & tapeouts➔ 1st Open Silicon Results

NIST Nanofabrication Accelerator➔ 1st Open Nanotechnology Platform➔ Cryogenic CMOS

Low-Power IC Design➔ Rapid Prototyping for Wearables

Hardware Security➔ 1st Open Root of Trust SoC

Low-Power SoC for Wearables●●●

Previous Work

Taped out in 55-nm DDC (Fujitsu) and published inISSCC 2019 and JSSC 2020
Power Domains○ 1.2v■ DC-DC converter■ Charge Pumps■ Clock generator■ Controller

RBB/FBB Charge-Pumps

Reconfigurable switched-cap.
DC-DC converter

DC-DC Output○ Cortex-M0 Processor○ 8KB SRAM
A 6.4 pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio
Measurement for Energy-Optimal Operation Across Wide-Range PVT Variation

67

Low-Power SoC for Wearables
Previous Work
Technology

55nm DDC process

Die Size

1500µm x 1970µm

CPU

ARM Cortex M0

On-chip Memory

8KB SRAM

Supply Voltage

1.2V

Power
Management
SchemeOn-chip Closed-loop
MEP-tracking

CPU & Memory
Operating Voltage

0.48V ~ 0.75V

Clock Frequency

100kHz ~ 6MHzPower

7.95µW @ TT, 25˚C ,1MHz

Minimum Energy
Per Operation

6.4pJ/cycle @ 0.55V, 500kHz
A 6.4 pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio
Measurement for Energy-Optimal Operation Across Wide-Range PVT Variation

68

Low-Power SoC for Wearables
Rapid Prototyping - AFE

Sensor Test Harness in Skywater 130
Lab on a Chip Concept
OP-AMP

DAC

ADC

Test Harness for Rapid Prototyping69

Low-Power SoC for Wearables
Rapid Prototyping - AFE

Test Harness in GF180

ADC

OPAMPOPAMPDAC

GF180 (Feb 2023)

70

On-Going Projects & Contributions

Open-Source IC & tapeouts➔ 1st Open Silicon Results

NIST Nanofabrication Accelerator➔ 1st Open Nanotechnology Platform➔ Cryogenic CMOS

Low-Power IC Design➔ Rapid Prototyping for Wearables

Hardware Security➔ 1st Open Root of Trust SoC

Open-Source Opentitan RoT

72

Open-Source Opentitan RoTWith OpenFASOC Generated Blocks

SAR ADC Block Diagram
Temperature Sensor
PLL

D-LDO
PMU

TRNG

OpenFASoC!
AutomatedportableanalogSource: https://docs.opentitan.org

SRC Select Disclosure73Proposed Techniques● Power Side-Channel Attack Resistant
Cryptographic AES SoC in Stacked
Voltage Domain● Secure Programmable PMU withnoise injection● ReRAM-based TRNG

Source: https://docs.opentitan.org

SRC Select Disclosure

74Cryptographic AES SoC
Stacked Voltage Domain

Source: https://docs.opentitan.org

SRC Select Disclosure

75

Open-Source Opentitan RoTVoltage Stacked SoC●●

1st version of the PMU
SoC includes:

Goals:-Source: https://docs.opentitan.org-○○

Crypto engine
IBEX Core

Perform DPA and check theefficiency of the power obfuscation
techniques
New open-source PPA (siliconresults)

76

Open-Source Opentitan RoTSecure Programmable PMU with Noise Injection

Source: https://docs.opentitan.org

77

RRAM based TRNG
HRS: 200KΩ

LRS: 20KΩ

Source: https://docs.opentitan.org

78Building Confidence in Open
DesignBuilding Confidence in Open Design

Start of
Skywater’s OpenMPW Program

MPW1Dec

End of2020…. Jun

2021

Aug

Oct

Dec

Feb

2022

AprJunAug

Oct

Dec

Feb

AprJun802024

Building Confidence in Open Design

Start of
Skywater’s OpenMPW Program

SKY130MPW1
Dec

End of2020

MPW2…. Jun Aug

2021

Oct

Dec

Feb

2022

AprJun

Aug

Oct

Dec

Feb

AprJun81

2024

Building Confidence in Open Design
GF 12-nm

Tapeout throughDARPA IDEA Program● 1st tapeout in GF12LP using open sourcetools●Signoff using PT○ @ TT|25C|0.8v|funcmax

350MHz●Temperature sensors

ADPLL○ TRANGE: -20 to 100oC○ Error: +/- 0.2oC (post-PEX)

SKY130SCPA

BLE-TX
MPW1
Dec

End of2020

MPW2
MPW3…. Jun Aug
Oct

2021

Dec

Feb

2022

AprJunAug

Oct

Dec

Feb
Feb
24thApr

Jun
May
28th

○ADPLL supports 1.8 to 2.7GHz

822024

Building Confidence in Open Design

Start of
Skywater’s OpenMPW Program

DARPA IDEA
Program

4 Testchips Already!
Big tapeout
mid-June

GF 12-nm

SKY130MPW1
Dec

End of2020

1st TO

MPW2
MPW3…. Jun Aug
Oct2021Nanofab. Accelerator
program w. NISTMPW4Dec

2nd TOMPW5
MPW6Feb
Apr Jun2022

3rd TO

4th TO

MPW7
MPW8Aug
Oct
Dec

NIST’sNanofabrication
TapeoutFebFeb
24thAprJun
May
28th832024

Building Confidence in Open Design

Start of
Skywater’s OpenMPW Program

DARPA IDEA
ProgramNanofab.
Accelerator
program w.
NIST

Globalfoundries
Open MPW
Program

Accelerating Fitbit’s
Custom Silicon Goals!

GF 180

GF 12-nm

GF 180MPW0SKY130MPW1Dec

End of2020

1st TO

MPW2
MPW3…. Jun Aug
Oct

2021

MPW4Dec

2nd TOMPW5
MPW6Feb
Apr Jun2022

3rd TO

4th TO

Project w. Fitbit

MPW7
MPW8AugOctDec

FebFeb
24thAprNIST’sNanofabrication
Tapeout
JunMay
28th842024

Building Confidence in Open Design Intel’sStart of
Skywater’s OpenMPW Program

DARPA IDEA
ProgramNanofab.
Accelerator
program w.
NIST

Globalfoundries
Open MPW
ProgramIntel 16-nm

GF 180

GF 12-nmUniversity ShuttleIntel 16-nm

GF 180MPW0SKY130MPW1
Dec

End of2020

1st TO

MPW2
MPW3…. Jun Aug
Oct

2021

MPW4Dec

2nd TOMPW5
MPW6Feb
Apr Jun2022

3rd TO

4th TO

Project w. Fitbit

MPW7
MPW8AugOctDec

FebFeb
24thAprNIST’s
Nanofabrication
TapeoutJunMay
28th

We Need More
Shuttles!

852024●●●●

Tape Outs in Intel 16 - OpenTitan SoC
Tapeout in Intel 16nm using OS tools
PD and timing optimization using OpenROAD
Used a modular flow to smoothly fill-in the gaps
using proprietary tools
Temperature Sensor RTL to GDS flow is fully
Open-Source

Floorplan of Intel 16 tapeout Including Opentitan, Temperature
sensor array and crossbar using OpenROAD

86

24 Temperature Sensors Array

Temp. Sensor

GPIO

Area = 33.048um x 34.02um

87OpenTitan Root of Trust SoC - Final Version
0.3 mmAll digital edge tracing TRNG
Tunable Noise Injection

On-chip high speed PLL

Crypto + Key Manager# of Macros

26Area2.18mm2

KeyManagerROM(32KB)

1.25 mm

20K

Entropy
SourceHMAC

Gate Count

Main
SRAM
(40KB)

KMAC

16KB

AES

Memory Size

OTBN

28MHz

EDN

Frequency

CSRNG

Secure Memory

FLASH(64KB)

Noise○○SPI

OpenTitan security subsystem

1.25 mm

PLL

TRNG

●●●
●

1.4 mmWhat is next?

Bridging Gaps between Hardware & Software
Make custom silicon easierto build, at scale, just likesoftware$ gcc -OSilicon“My god,it’s full of software!”90

Bridging Gaps between Hardware & Software
Packagingconda-eda

github.com/hdl/conda-eda
conda install --channel litex-hub \open_pdks.sky130a\
openlane\xls“My god,it’s full of software!”91Bridging Gaps between Hardware & Software
Packagingconda-eda

github.com/hdl/conda-eda

conda install --channel litex-hub \open_pdks.sky130a\openlane\xls

Reproducible, Reusable
Jupyter Notebook“My god,it’s full of software!”github.com/chipsalliance/silicon-notebooks/

92

Bridging Gaps between Hardware & Software●OpenFASOC GitHub Repo is mainly Code andDocumentation“My god,it’s full of software!”93Bridging Gaps between Hardware & Software●

OpenFASOC GitHub Repo is mainly Code andDocumentation○ Auditable and Transparent○ Regression Tests○ Systematic Metrics Extraction○ Dashboards“My god,it’s full of software!”94

Bridging Gaps between Hardware & Software●●OpenFASOC GitHub Repo is mainly Code andDocumentation○ Auditable and Transparent○ Regression Tests○ Systematic Metrics Extraction○ Dashboards
Analog Automation requires collaborative Work○ EDA, Analog/RF/Circuits, Software“My god,it’s full of software!”95

Bridging Gaps between EE & CS
●Existing efforts around Open-Source IC design

Computer
Science

EDA, Flows,Generators,Compilers,
etc…

Electrical &Computer
Engineering“My god,it’s full of software!”96

AURA Program

97

98

99

100

Notebook Code a Chip Competition at
ISSCC’23

101

Notebook Code a Chip Competition at
VLSI’23102

“Code-a-Chip” Notebook Competition at
VLSI'23 - Kyoto● IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)○ https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io

103

104

180 Attendees!! Record attendance
among all workshops at VLSI Symposium

105

The end!
Bonus slides

Implementation Challenges
A. The quantized behavior is best shown in single-defect gate interfaces.
a.

b.

When the device operates with a single defect, the CP current difference is either fully
present or not, there is no middle values caused by randomness.
It demands:
i. Heavy binning to select a candidate device
ii. Advanced process node that doesn’t produce too much defects

B. The current is extremely small (<10fA @ 40MHz, L/W=50nm/100nm [1])
a.

b.
c.

Leakages are everywhere. The author suggests DRAM-optimized technology to minimize
junction leakage [1].
Considering lock-in amplify or other low-level signal measurement techniques. [4, 5]
Direct amplification of this signal can result in a very large low-freq AC noise that’s difficult tofully eliminate on-die. Considering mixed-signal circuits.

Charge Pumping (CP) Defect Measurement

Itotal = Icp(f) + Iother[5]The number of SiO2-gate interface defects (Nit) can be measured by: applying a square wave to theMOS stack and measure the change in bulk current. The CP current can be isolated because it behavesdifferently with frequency compared to the other leakages.

Nanotechnology Accelerator

The concept

Example Usage of such a Carrier Wafer

The aim of this project is to put some test apparatus on a silicon chip, which will be used as the carrier wafer for new nanodevice fabrication.
Drastically reduced parasitics can lead to improved measurement quality and test ranges.
109instr

AdaptorIbex
SAdaptordata

I SRAM

data

Tape Outs in Intel 16 - OpenTitan SoCMS

D SRAM
AdaptorMain Crossbar
SM

M

SPIJTAG

Peripheral Crossbar
GPIO UART

I2C

SPI

110

OpenFASoC - Portable Transferrable Analog>10xcheaper!

MPW-1
MPW-2
MPW-3
MPW-4
MPW-5

130nm
Planar Bulk

SKY13064 temp sensors
D-LDO
AMS SoC
D-LDO
More temp sensors
skip
DC-DC
PLL
AMS SoC
More!!!

12nm
FinFet

GF12LP

Temp sensors
DC-DC
AMS SoC
PLL

Same fully open source tools
Same scripting generators

Test IC 1111

OpenFASoC - Portable Analog
Analog generators - Power DCDC + LDO, Temperature Sensors, PLLs,ADCs.
● Example mixed signal SoC integration.
● Silicon proven with increasingly more tape outs, increasingly faster!
●●●Fully open source flow using fully open source tooling (OpenROAD, Xyce).
Demonstrating acceleration of velocity and productivity.

>10xcheaper!

SKY130130nm
Planar Bulk

GF12LP
12nm
FinFetSame fully open source tools
Same scripting generators
112

SAR ADC Common Centroid Placement›Symmetrical Placement of unit caps
and switches
Output Spec.

CDL

FSAMPLING (MHz)PEX

1Unit Cap Value (fF)

2.6

Area (mm2)-0.04Power (µW)

6.72

11.2

Effective Number of Bits

7.86

7.75

best-caseNarrow

SAR ADC Block Diagram

8bits
SAR
ADC

common-centroid
placement
strategy

6bits
SAR
ADC
113

Open Source RoT

Inst
RAM

Peripherals
RISC-V
AXI

Data
RAM

114

OpenFASOC on MPW-II: Integrated Temperature
SensorsSensors are embedded inside the OpenTitan SoC andconnected through tilelink

Highly tunable VREF
with trimming bits

Non Default Routing isuse to route the header
cells to the 2nd voltage
domain power ringSensing elements
are sitting on asecond voltage
domainThe temperature sensor generator uses afully open source flow

115

OpenFASOC on MPW-II: D-LDO generator
Unit MIM
Decap cells
Highly tunable VREF
with trimming bits

Voltage Reference with symmetrical placement

Array of power switches
evenly placed using .py

Array of D-LDOs

116

Analog Cell Generation using ALIGN

Generated Analog “Auxiliary Cells”

2:1 converter SlicePower mux
Power mux

Strong arm latch
2:1 converter Slice
Strong arm latch

117

Tape Outs in Intel 16 - OpenTitan SoC●OpenTitan SoC contains○ SPI, GPIO interfaces○ Ibex CPU○ 16KB SRAM
○ Main crossbar and peripheral crossbar○ All peripherals are connected through TilelinkFrequency
28MHz

Util.
29%
*64%

Macro PlaceChannelMacro
Place Halo

Cell Pad

40 40

20 20

2 sitesArea425x425um2

Floorplan of in Intel 16 Including RAMs and an
OpenROAD based implementation of the Opentitan SoC

118

Tape Outs in Intel 16 - Power Numbers

119Temperature Sensor Variant B
Header BCorner

TTTT

TCONV (ms)

RSSSRFFF

0.1

Energy/Conv(nJ)

1.400.28

6.81

ErrorMAX (°C)

0.62

0.17

0.41

120

Temperature Sensor Variant C
Header CCorner

TTTT

TCONV (ms)

RSSSRFFF

0.1

Energy/Conv(nJ)

1.59

0.32

7.57

ErrorMAX (°C)

0.35

0.25

0.39

121

CHIPS Alliance AWG Activities
Techno/Design Loop
New Measured Data, Models, CI●●●Technology/Design Feedback Loop

Compatibility between open-source models versus closed models
Quality of models (Both closed and Open-source)
We have to define a Technology/Design feedback loop in the Open-source real
8xDiscrepancies Closed vs Open-Source tools
FrequencyPowerVVDD

Inaccuracy-31.50%539.63%-0.82%

780.93%-8.12%

181.81%-0.85%

0.00%-2.10%

106.59%-1.58%

323.15%-0.62%

87.81%-1.78%

228.61%-0.08%

82.38%-1.70%

192.13%-0.29%

80.25%-1.09%

0.00%-0.56%

79.70%-0.72%

117.29%123

Preliminary Measurements on Skywater 130nm

124Current version of thegenerator

Working version of the tools
suite and PDK

EDAtools

Config A

Working version of thegenerator

PDK

Current version of the tools suiteand PDK

EDAtools

Config A

PDK

CentralDatabaseMetri
MetriPower,cefficiency
cAA

MetricAA
MetricPower,efficiency
metrics

metrics

Metrics from“last-best”
version of thegenerator
Best version
with the list ofworking
configurations

Toolssuite
Metriand PDK
cA
versionMetrics from“now-best”
version of thegenerator
Tools suiteand PDK
versions info

MetricAA
MetricPower,efficiency
metrics
Metrics from“last-best”
version of thegenerator
List of tools
version andPDK version

125Current version of thegenerator

Working version of thetools suite and PDK

EDAtools

Config A

TempSense
generator

LDOgenerator

….

PDK

DC-DC
generator….

Generator
library
SharedDatabase

MetricMetricAPower,Aefficiency
metrics

Best version
with the list ofworking
configurations

Metr
Metr
Power,
icefficiency
icAA
Metrics from“last-best”
version ofthegenerator

Tools
Metr
suite andicPDK
A
versionDSE

metrics

Metrics from“now-best”
version ofthegenerator

Publish reports on
openfasoc.readthe
docs.io126