“An Effective Wayto Perform Correlation Power Analysis Attack on
Cryptographic RISC-V SoC”
Authors: Thai-Ha Tran, Cong-Kha Pham, and Trong-Thuc Hoang

Affiliation: Department of Computer and Network Engineering
The University of Electro-Communications, Tokyo, Japan

Position: Ph.D. student
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OUTLINE“An Effective Way to Perform Correlation Power Analysis
Attack on Cryptographic RISC-V SoC”
1. INTRODUCTION
2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATION
3. TARGETED RISC-V COMPUTER ARCHITECTURE

4. EXPERIMENTAL RESULTS
5. CONCLUSION
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1. INTRODUCTION❖ Profiled Power Analysis Attacks❖ Non-profiled Power Analysis Attacks❑ Simple Power Analysis (SPA)❑ Differential Power Analysis (DPA)❑ Correlation Power Analysis (CPA)❑ Non-profiled Deep Learning-based SCA❖ This poster is a part of our recent work,
which is under publication in IEEE Trans.
on Computers [1].
Fig. 1: Cryptographic design’s vulnerability
https://www.togawa.cs.waseda.ac.jp/English/research/app.html

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1. INTRODUCTION❖ Used power model in Correlation Power Analysis Attack❑ Hamming Weight model (HW): only 1 involves a significant amount of powerconsumption.
❑ Hamming Distance model (HD): 0 → 1 and 1 → 0 transitions have the same contribution.

❑ Switching Distance model (SD): transition 0 → 1 is assigned 1, the transition 1 → 0 isassigned factor φTable 1: Power consumption models [2].
Transition factors

HWHDSD

φ00

000φ01111φ1001φφ111004 /18

OUTLINE“An Effective Way to Perform Correlation Power Analysis
Attack on Cryptographic RISC-V SoC”
1. INTRODUCTION
2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATION
3. TARGETED RISC-V COMPUTER ARCHITECTURE

4. EXPERIMENTAL RESULTS
5. CONCLUSION
5 /18

2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATIONPower traces dataset(IDLE / ACTIVE)

Biasing
methodSubset_0

Subset_1

Var(PIDLE)
Var(PACTIVE)

φ6 /18

2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATIONPower traces dataset(IDLE / ACTIVE)

Biasing
methodSubset_0

Subset_1

Var(PIDLE)
Var(PACTIVE)

φFig. 2: Power traces in the IDLE mode
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2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATION
Var ( Pactive ) − Var ( Pidle )SNR Var ( Pidle )Power traces dataset(IDLE / ACTIVE)

 SNR0  ( 01(0) +   10(0) )(1)(1)
 SNR1  ( 01 +   10 )Biasing
methodSubset_0

Subset_1

Var(PIDLE)
Var(PACTIVE)

φ
Fig. 3: Histogram of power consumption
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OUTLINE“An Effective Way to Perform Correlation Power Analysis
Attack on Cryptographic RISC-V SoC”
1. INTRODUCTION
2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATION
3. TARGETED RISC-V COMPUTER ARCHITECTURE

4. EXPERIMENTAL RESULTS
5. CONCLUSION
9 /18

3. TARGETED RISC-V COMPUTER ARCHITECTURE❖ Framework: Chipyard❖ RISC-V cores: Rocket and Boom [3]❖ Targeted algorithm: AES❑ Run directly inside a RISC-V core
❑ Independent accelerator❖ Instruction set: RV32IMAC; RV64IMAFDC [4]Integer

Multiplication

AtomicFloating-point,

Double floating-point

Compress

Fig. 4: The targeted RISC-V SoC architecture
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3. TARGETED RISC-V COMPUTER ARCHITECTURE❖ Test platform: Kintex-7 XC7K160T of the Sakura-X side-channel analysis board.
Table 2: Post-implementation utilization of different config.
AES Accelerator

Name ofconfigurations

Core #1

Rocket1_32

Rocket_32

RocketR1_64

Core #2
LUTs (%)

FFs (%)

-6.89

9.59

RocketR_64

-5.22

8.28

RocketBoomR_32

Rocket_32

BoomR_32

3.56

4.82

RocketR2_64

RocketR_64

RocketR_64

3.38

5.51

BoomR1_64

BoomR_64

-

3.09

4.87

11 /18OUTLINE“An Effective Way to Perform Correlation Power Analysis
Attack on Cryptographic RISC-V SoC”
1. INTRODUCTION
2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATION
3. TARGETED RISC-V COMPUTER ARCHITECTURE

4. EXPERIMENTAL RESULTS
5. CONCLUSION
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4. EXPERIMENTAL RESULTS
Table 3: The probability of the two transitions of biasing subsets.

❖ Evaluation metric: Relative gain

N HD − N
G =N HD

Name of config.

φGφRocket1_32

0.85

13.50

RocketR1_64

0.72 ÷ 0.90

1.07

RocketBoomR_32

0.82

5.74

RocketR2_64

0.89

6.55

BoomR1_64

0.87

12.15
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4. EXPERIMENTAL RESULTS

Recommended range: 0.85 ÷ 0.87

Fig. 5: Optimal range of transition factors.
14 /18OUTLINE“An Effective Way to Perform Correlation Power Analysis
Attack on Cryptographic RISC-V SoC”
1. INTRODUCTION
2. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATION
3. TARGETED RISC-V COMPUTER ARCHITECTURE

4. EXPERIMENTAL RESULTS
5. CONCLUSION
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5. CONCLUSION❖ Overview the most suitable model for attacking the AES by applying three power
consumption models: HW, HD, and SD.

❖ Suggest an initial step for estimating the relationship between the quantity of leakage
information of the designs and the transition factors.
❖ The larger the relative gain is, the higher the attacking effectiveness is.
❑ Recommended range: 0.85 ÷ 0.87
❑ Highest effectiveness: Gφ = 13.35 % at φ = 0.85

❖ Future work:❑ Further experiment with other protected AES structures❑ Combines power consumption models with preprocessing techniques to enhance theperformance of the CPA evaluation.
16 /18REFERENCES[1] T. -H. Tran et al., "Transition Factors of Power Consumption Models for CPA Attacks on
Cryptographic RISC-V SoC," in IEEE Transactions on Computers.
doi: 10.1109/TC.2023.3262926.
[2] E. Peeters et al., “Power and electromagnetic analysis: Improved model, consequences
and comparisons,” Integration, vol. 40, no. 1, pp. 52–60, 2007.

[3] A. Dorflinger et al., “A Comparative Survey of Open-Source Application-Class RISC-V
Processor Implementations”. USA: Association for Computing Machinery, 2021.
[4] A. Waterman et al., “The RISC-V Instruction Set Manual, Volume I: User-Level ISA,
Version 2.0,” Tech. Rep. UCB/EECS-2014- 54, May 2014.

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“An Effective Way to Perform Correlation Power Analysis
Attack on Cryptographic RISC-V SoC”

THANK YOUFOR YOUR ATTENTION!

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