AEM10330

DATASHEET

Highly Versatile, Regulated Single-Output, Buck-Boost Ambient
Energy Manager For Up to 7-cell Solar Panels
FeatureDescription

Ultra-low power start-up- Cold start from 275 mV input voltage and 3 µW input
power (typical).

Very efficient energy extraction- Open-circuit voltage sensing for Maximum Power
Point Tracking (MPPT).
- Selectable open-circuit voltage ratios from 60% to
90% or fixed impedance.
- Programmable MPPT sensing period.
- MPPT voltage operation range from 100 mV to 4.5 V.

Adaptive and smart energy management- DCDC switches automatically between boost, buckboost and buck operation, according to input andoutput voltages, to maximize energy transfer.
- DCDC automatically handles multiple inputs andoutputs:- Keeps the internal supply and the load voltages
regulated while storing the excess of energy inthe storage element.
- The storage element can be used as an input tokeep the load and internal voltages regulated
when no energy is available on the source.

Load supply voltage- Selectable load voltage from 1.2 V to 3.3 V.
- Current drive capability: 30 mA in low power mode,
60 mA in high power mode.

Battery protection features- Selectableover-charge
andover-discharge
protection for any type of rechargeable battery or(super-)capacitor.
- Fast super-capacitor charging.
- Dual cell super-capacitor balancing circuit.

Smallest footprint, smallest BOM- Only four external components are required.
- One 10 µH inductor.
- Three capacitors: one 10 µF, one 22 µF and one atleast 40 µF.

SRC

10uH

LOUT

BUFSRCSOURCE

LDCDC

LIN

CSRC
22uF

VINT

AEM10330

VINT

Li-IonBattery

DS-AEM10330-v1.4

At start-up, user can choose between charging the storage
element first to accumulate energy before the application
circuit starts, or charge the load decouplinwg capacitor first to
start the application circuit faster.
With its unique cold start circuit, the AEM10330 can start
harvesting with an input voltage as low as 275 mV and from an
input power of 3 μW. The preset protection levels determine
the storage element voltages protection thresholds to avoid
over-charging and over-discharging the storage element andthus avoiding damaging it. Those are set throughconfiguration pins. Moreover, custom threshold voltages canbe obtained at the expense of a few configuration resistors.
The load voltage can be selected to cover most applicationneeds, with a maximum available load current of 60 mA.
The chip integrates all active elements for powering a typical
wireless sensor. Only three capacitors and one inductor are
required.

Applications
Asset Tracking/Monitoring

Industrial applications

Retail ESL/Smart sensors

Aftermarket automotive

Smart home/Building

Device Information
Part Number

Package

Body size [mm]10AEM10330J0000

QFN 40-pin

5x5mm

Part Number
LOAD

GND

Thanks to its Maximum Power Point Tracking system, theAEM10330 extracts the maximum energy available from thesource. It integrates an ultra-low power DCDC converter
which operates with input voltages ranging from 100 mV to
4.5 V.

Evaluation Board

CINT
10uF

VSTO

STO

The AEM10330 is an integrated energy management circuitthat extracts DC power from an ambient energy harvestingsource to simultaneously supply an application and store
energy in a storage element. The AEM10330 allows to extend
battery lifetime and ultimately eliminates the primary energy
storage element in a large range of applications.

CLOAD
47uF

LOAD

2AAEM10330J0010

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Table of Contents
1. Introduction
2. Pin Configuration and Functions
3. Absolute Maximum Ratings
4. Thermal Resistance
5. Typical Electrical Characteristics at 25 °C
6. Recommended Operation Conditions
7. Functional Block Diagram
8. Theory of Operation

6
7
9
9
10
11
12
13

9. System Configuration

17

10. Typical Application Circuits

23

11. Circuit Behavior

26

12. Performance Data

28

13. Schematic
14. Layout

33
34

15. Package Information

36

8.1. DCDC Converter ....................................................................................................................138.2. Cold-Start Circuit ...................................................................................................................138.3. AEM10330 States Description ..............................................................................................148.4. Maximum Power Point Tracking ...........................................................................................15
8.5. Balancing for Dual-Cell Supercapacitor ................................................................................16
9.1. High Power / Low Power Mode ............................................................................................179.2. Storage Element Configuration .............................................................................................179.3. Load Configuration ................................................................................................................199.4. Custom Mode Configuration ................................................................................................199.5. Disable Storage Element Charging ........................................................................................20
9.6. MPPT Configuration ..............................................................................................................219.7. ZMPP Configuration ..............................................................................................................219.8. Source to Storage Element Feed-Through ............................................................................219.9. External Components ............................................................................................................2210.1. Example Circuit 1 ................................................................................................................23
10.2. Example Circuit 2 ................................................................................................................24
11.1. Wake-up state, Start state and Supply state ......................................................................26
11.2. Supply state, Shutdown state and Reset state ...................................................................27
12.1. DCDC Conversion Efficiency From SRC to STO in Low Power Mode ...................................28
12.2. DCDC Conversion Efficiency From SRC to STO in High Power Mode ..................................29
12.3. DCDC Conversion Efficiency From STO to LOAD in Low Power Mode ................................30
12.4. DCDC Conversion Efficiency From STO to LOAD in High Power Mode ...............................31
12.5. Quiescent Current ...............................................................................................................32

14.1. Guidelines ...........................................................................................................................34- ...................................................................................................................................................35
15.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm) .........................................................36
15.2. Board Layout .......................................................................................................................37

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16. Revision History 38

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List of Figures
Figure 1: Simplified Schematic View .....................................................................................................6
Figure 2: Pinout Diagram QFN 40-pin ...................................................................................................7
Figure 3: Functional Block Diagram ......................................................................................................12
Figure 4: Simplified Schematic View of the AEM10330 ........................................................................13
Figure 5: Diagram of the AEM10330 States .........................................................................................14
Figure 6: Maximum LOAD Current Depending on VSTO and on VLOAD .................................................17
Figure 7: Custom Mode Settings ..........................................................................................................19
Figure 8: RZMPP Connection to the AEM10330 .....................................................................................21
Figure 9: Typical Application Circuit 1 ..................................................................................................23
Figure 10: Typical Application Circuit 2 ................................................................................................24
Figure 11: Wake-up state, Start state and Supply state .......................................................................26
Figure 12: Supply State, Shutdown state and Reset state ....................................................................27
Figure 13: DCDC Efficiency from SRC to STO for 1 mA and 10 mA in Low Power Mode ......................28
Figure 14: DCDC Efficiency from SRC to STO for 10 mA and 50 mA in High Power Mode ...................29
Figure 15: DCDC Efficiency from STO to LOAD in Low Power Mode ....................................................30
Figure 16: DCDC Efficiency from STO to LOAD in High Power Mode ...................................................31
Figure 17: Quiescent Current ...............................................................................................................32
Figure 18: Schematic Example ..............................................................................................................33
Figure 19: Layout Example for the AEM10330 and its Passive Components .......................................35
Figure 20: QFN 40-pin 5x5mm Drawing (All Dimensions in mm) .........................................................36
Figure 21: Recommended Board Layout for QFN40 package (All Dimensions in mm) ........................37

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List of Tables
Table 1: Power and Status Pins ............................................................................................................7
Table 2: Configuration and Ground Pins ...............................................................................................8
Table 3: Absolute Maximum Ratings ....................................................................................................9
Table 4: Thermal Resistance .................................................................................................................9
Table 5: Typical Electrical Characteristics .............................................................................................10
Table 6: Recommended Operation Conditions ....................................................................................11
Table 7: DCDC Converter Modes ..........................................................................................................13
Table 8: Storage Element Configuration Pins .......................................................................................18
Table 9: Load Configuration Pins ..........................................................................................................19
Table 10: MPP Ratio Configuration Pins ...............................................................................................21
Table 11: MPP Timing Configuration Pins ............................................................................................21
Table 12: Minimal Bill of Materials .......................................................................................................33
Table 13: Revision History ....................................................................................................................38

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AEM10330

DATASHEET

AEM10330
SourceStorage Element
STO

SRC
100mV - 4.5V
MAX

x
x
x
x
x
x

Li-ion cell
LiFePO4 cell
NiMH cell
Dual-cell supercapacitor
Single-cell supercapacitor
Other...

LOAD
1.2V/1.8V/2.5V/3.3V
60mA

Application
Circuit

1. Introduction
Figure 1: Simplified Schematic View

The AEM10330 is a full-featured energy efficient power
management circuit able to harvest energy from an energy
source (connected to SRC) to supply an application circuit(connected to LOAD) and use any excess of energy to charge
a storage element (connected to STO). This is done with aminimal bill of material: only capacitors and one inductor are
needed for a basic setup.

The Maximum Power Point (MPP) ratio is configurable thanks
to three configuration pins (R_MPP[2:0]) and ensures anoptimum biasing of the harvester to maximize power
extraction. Depending on the harvester, it is possible to adapt
the timings of the MPP evaluations with the two configuration
pins (T_MPP[1:0]) that sets the periodicity and the duration of
the MPP evaluation.

The heart of the AEM10330 is a regulated switching DCDC
converter with high power conversion efficiency.

Once started, if at any time the load requires more power
than can be harvested from the energy source, the AEM10330
automatically uses the storage element to keep the load
supplied.

At first start-up, as soon as a required cold-start voltage of
275 mV and a sparse amount of power of at least 3 μW is
available at the source, the AEM10330 coldstarts. After thecold start, the AEM extracts the power available from thesource if the working input voltage is at least 100 mV.
Through four configuration pins (STO_CFG[3:0]), the user canselect a specific operating mode out of 15 modes that covermost application requirements without any dedicatedexternal component. Those operating modes define theprotection levels of the storage element. If none of those 15
modes fit the user’s storage element, a custom mode is alsoavailable to allow the user to define a mode with custom
specifications.
Status pins ST_STO, ST_STO_RDY and ST_STO_OVDIS provide
information about the voltage levels of the storage element.
ST_STO is HIGH when the voltage of the storage element VSTO
is above VCHRDY and is reset when the voltage drops below
VOVDIS. ST_STO_RDY is HIGH when VSTO is above VCHRDY, andreset when VSTO drops below VCHRDY. ST_STO_OVDIS is HIGH
when VSTO drops below VOVDIS and reset when VSTO is above
VOVDIS. Status pin ST_LOAD is HIGH when the load voltage
VLOAD rises above VLOAD,TYP, and is reset when VLOAD drops
below VLOAD,MIN.

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DS-AEM10330-v1.4

The AEM10330’s DCDC converter can work in two modes:
LOW POWER MODE and HIGH POWER MODE, each one ofthese being optimized for a power range on SRC and LOAD.
The charging of the storage element can be prevented bypulling EN_STO_CH to GND, typically to protect the storage
element if the temperature is too low/high to safely charge it.
The AEM10330 also implements a SLEEP STATE, which
reduces the quiescent current to avoid wasting the energy
stored on the storage element when EN_SLEEP is HIGH.
At start-up, user can choose to prioritize starting theapplication circuit connected on LOAD, or charging thestorage element connected on STO. This is set by the
STO_PRIO pin.

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DATASHEET

ST_STO
EN_SLEEP
ST_STO_OVDISST_STO_RDY
ST_LOADSTO_CFG[2]STO_CFG[1]STO_CFG[0]T_MPP[1]
EN_STO_FT

2. Pin Configuration and Functions

40 39 38 37 36 35 34 33 32 31

CS_IN 1
ZMPP 2
SRC 3
GND 4
GND 5
GND 6
BUFSRC 7
LIN 8
LOUT 9GND 10QFN40
Top view

30 T_MPP[0]29 STO_PRIO
28 EN_HP
27 STO_CFG[3]26 GND
25 LOAD_CFG[1]24 LOAD_CFG[0]23 STO_OVCH
22 STO_RDY
21 STO_OVDISR_MPP[2]R_MPP[1]VINT
GND
R_MPP[0]
GND
LOAD
BAL
STO
EN_STO_CH

11 12 13 14 15 16 17 18 19 20

Figure 2: Pinout Diagram QFN 40-pin
NAME

PIN
NUMBERFUNCTION

Power Pins
CS_IN

1

Input for the eternal cold start circuit.

ZMPP

2

Used for the configuration of the ZMPP (optional). Must be left floating if not used.

SRC

3

Connection to the harvested energy source.

BUFSRC

7

Connection to an external capacitor buffering the DCDC converter input.

LIN

8

DCDC inductance connection.

LOUT

9

DCDC inductance connection.

VINT

13

Internal voltage supply.

LOAD

17

Output voltage to supply on application load.

BAL

18

Connection to mid-point of a dual-cell supercapacitor (optional).
Must be connected to GND if not used.

STO

19

Connection to the energy storage element - battery or (super-)capacitor.
Cannot be left floating. Must be connected to a minimum capacitance of 100 μF or to a rechargeable
battery.

ST_LOAD36

Logic
Output

HIGH:
VLOAD

HIGH when the LOAD voltage VLOAD rises above the VLOAD,TYP threshold.
LOW when VLOAD drops below VLOAD,MIN threshold.

ST_STO_RDY

37

Logic
Output

HIGH:
VLOAD

HIGH when VSTO is above VCHRDY.
LOW when VSTO drops below VCHRDY.

ST_STO_OVDIS

38

Logic
Output

HIGH:
VLOAD

HIGH when the AEM10330 state is SHUTDOWN STATE.
LOW when in any other state.

ST_STO

40

Logic
OutputHIGH:
VSTO

HIGH when the storage device voltage VSTO rises above VCHRDY threshold.
LOW when VSTO drops below the VOVDIS threshold.

Status Pins

Table 1: Power and Status Pins

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NAME

PIN
NUMBER

AEM10330

HIGH
LEVEL

FLOATING
STATE

VVINT

HIGH

Used for the configuration of the MPP ratio.
Read as HIGH when left floating.

VVINT

HIGH

Used for the configuration of the MPP timings.
Read as HIGH when left floating.

VVINT

HIGH

Used for the configuration of LOAD output voltage VLOAD.
Read as HIGH when left floating.

VVINT

HIGH

Used for the configuration of the threshold voltages for the energy storage element VOVDIS,VCHRDY and VOVCH.
Read as HIGH when left floating.

VVINT

HIGH

- Pulled up to VINT or floating: storage device (STO) has highest priority at
start-up- Pulled down to GND: load (LOAD) has highest priority at start-up

FUNCTION

Configuration Pins
R_MPP[0]15

R_MPP[1]12

R_MPP[2]11

T_MPP[0]30

T_MPP[1]32

LOAD_CFG[0]24LOAD_CFG[1]25

STO_CFG[0]33

STO_CFG[1]34

STO_CFG[2]35

STO_CFG[3]27

STO_PRIO29

STO_OVCH

23

STO_RDY

22

STO_OVDIS21

EN_SLEEP

39

VLOAD

Cannot beleft
floating

EN_STO_FT

31

VVINT

HIGH

- Pulled up to VINT or floating: allows charges flowing directly from SRC to STO
when SRC is above 5V.
- Pulled down to GND: normal operation.

EN_STO_CH

20

VLOAD

HIGH

- Pulled up to LOAD or floating: enables the charging of the battery- Pulled down to GND: disables the charging of the battery

EN_HP

28

VVINT

HIGH

- Pulled up to VINTor floating: HIGH POWER MODE enabled- Pulled down to GND: HIGH POWER MODE disabled

Used for the configuration of the threshold voltages (VOVDIS, VCHRDY and VOVCH) for the energy storage element
when STO_CFG[3:0] are set to custom mode (optional). Must be left floating if not used.

- Pulled up to LOAD: SLEEP STATE enabled- Pulled down to GND: SLEEP STATE disabled

Other

GND

4, 5, 6,
10, 14,16, 26Ground connection, best possible connection to PCB ground plane.

Exposedpad

Table 2: Configuration and Ground Pins

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3. Absolute Maximum Ratings
Parameter

4. Thermal Resistance
Value

Package

θJA

θJC

Unit

Voltage on LOAD, STO, SRC, BUFSRC, LIN,
LOUT, ZMPP, BAL, CS_IN, EN_SLEEP,
EN_STO_CH-0.3 V to 5.5 V

QFN 40pin

TBD

TBD

°C/W

Voltage on VINT, T_MPP[1:0], R_MPP[2:0],
LOAD_CFG[1:0], STO_CFG[3:0], STO_PRIO,STO_OVCH, STO_OVDIS, STO_RDY, EN_HP-0.3 V to 2.75 V

Operating junction temperature-40 °C to 125 °C

Storage temperature-65 °C to 150 °C

Table 4: Thermal Resistance

ESD HBM voltage> 2000 V

ESD CDM voltage> 500 V

Table 3: Absolute Maximum Ratings
ESD CAUTION
ESD (ELECTROSTATIC DISCHARGE) SENSITIVE DEVICE
These devices have limited built-in ESD protection and damage may thus occur on devices subjected to high-energy
ESD. Therefore, proper EESD precautions should be taken to avoid performance degradation or loss of functionality

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DATASHEET

5. Typical Electrical Characteristics at 25 °C
SymbolParameter

Conditions

Min

Typ

Max

Unit

Power Conversion
PSRC,CS

Source power required for cold
start

VSRC

Input voltage of the energy source

RZMPP

VSTO > Vchrdy
VSTO < Vchrdy
During cold start

µW

6

µW

0.275

After cold start

MPPT ratio

3

0.1

See Table 10

4.5

V

4.5

V

60, 65, 70, 75, 80, 85 or 90, depending on
R_MPP[2:0] configuration%

Timing
TMPP,EVAL

Duration of a MPP evaluation

50% ofTable 11200% of
Table 11ms

TMPP,PERIODTime between two MPP evaluations

50% ofTable 11200% of
Table 11s

Storage element
VOVCH

Maximum voltage accepted on thestorage element before disabling its
charging

VCHRDY

Minimum voltage required on thestorage element before asserting
the ST_STO

VOVDIS

Minimum voltage accepted on thestorage element before entering
into SHUTDOWN STATEV

see Table 8

Depends on STO_CFG[3:0] configuration

V

V

Load Output Voltage

ILOAD,MAX

VLOAD

LOAD current drive capability

VLOAD = 1.8V
VSTO > 1.6V
HP_EN = H

60

VLOAD = 2.5V
VSTO > 1.6V
HP_EN = H

60

VLOAD = 3.3V
VSTO > 1.8V
HP_EN = H

60

see Table 9

Depends on LOAD_CFG[1:0] configuration

V

2.2

V

875

nA

Output voltage

mA

Internal supply & Quiescent Current
VVINT

Internal voltage supply
VSTO = 3.7V
VLOAD = 2.5V
EN_SLEEP = L
EN_HP = L

IQ

Quiescent current on STO

SymbolLogic Level

LOW

HIGH

ST_STO

Logic output levels on the status STO pin

GND

VSTO

ST_LOAD

Logic output levels on the status LOAD pin

GND

VLOAD

ST_STO_RDY

Logic output levels on the status STO_READY pin

GND

VLOAD

ST_STO_OVDIS

Logic output levels on the status STO_OVDIS pin

GND

VLOAD

Logic output pins

Table 5: Typical Electrical Characteristics

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6. Recommended Operation Conditions
SymbolParameter

Min

Typ

Max

Unit

External Components
LDCDC

Inductor of the DCDC converter

10µH

Capacitor decoupling the SRC terminal

131

CSRC

22

µF

CINT

Capacitor decoupling the VINT terminal

1

10

µF

CLOAD

Capacitor decoupling the LOAD terminal

13

1

47

µF

CSTO

Optional - Capacitor on STO if no storage element
is connected (see Section 9.9.1)

1001

RZMPP

Optional - Used for the configuration of the ZMPP
tracking function

10

Section
9.7

100K

Ω

1

Section
9.4

100

MΩ

5

µF

STO_OVCH

Configuration of VOVCH in custom mode

STO_OVDIS

Configuration of VOVDIS in custom mode

STO_RDY

Configuration of VCHRDY in custom mode

SymbolLogic Level

LOW

HIGH

R_MPP[2:0]

Configuration pins for the MPP evaluation

GND

VINT

T_MPP[1:0]

Configuration pins for the MPP timing

GND

VINT

LOAD_CFG[1:0]

Configuration pins for the LOAD voltage

GND

VINT

STO_CFG[3:0]

Configuration pins for the STO voltage

GND

VINT

STO_PRIO

Configuration pin for the controller

GND

VINT

EN_STO_FT

Configuration pin for the controller

GND

VINT

EN_SLEEP

Configuration pin for the controller

GND

LOAD

Logic input pins

EN_STO_CH

Configuration pin for the controller

GND

LOAD

EN_HP

Configuration pin for the controller

GND

VINT

Table 6: Recommended Operation Conditions
1.Consider all component tolerance and deratings. Typically, DC-bias derating has a major impact on capacitance on ceramic capacitors.

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DATASHEET

7. Functional Block Diagram

LDCDC

VINT

LOUT

BUFSRC

LIN

CSRC

VINT

CINT

LOAD
GND or VINT
GND or VINTLOAD

R_MPP[2:0]

ZMPP

CLOAD

DCDC

T_MPP[1:0]

MPP
Control

Optional

VSTO

RZMPP

SOURCE

STO
SRC

Balance

VINT
CS_IN

Cold-start

5V

Supercap.
orBatteryBAL+

ST_LOAD
ST_STO
GND or VINT
GND or VINTSTO_CFG[3:0]

ST_STO_RDY

State
Monitor

LOAD_CFG[1:0]
STO

ST_STO_OVDIS

+
-

VSTO

Controller
EN_STO_FT

Optional

VINT
R4

STO_PRIO+

EN_SLEEP-STO_OVDISR3LOAD

STO_RDY
R2

EN_STO_CH
EN_HP

+
-

GND or VINT
GND or VINT
GND or LOAD
GND or LOAD
GND or VINTSTO_OVCH

POR

R1

Vref

Clock

GND

Figure 3: Functional Block Diagram

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DATASHEET

LDCDC

M7

LOUT

BUFSRC

LIN

CSRC

VINT

CINT
M3

SOURCE

M6

M8

LOAD

M1

SRC

CLOAD
M2

M4

M5

M9

STO

STORAGEELEMENT

Figure 4: Simplified Schematic View of the AEM10330

8. Theory of Operation
8.1. DCDC Converter
The DCDC converter converts the voltage available at BUFSRC
or at STO to a level suitable for charging the storage element
STO or to regulate the LOAD and the internal supply VINT.
The switching transistors of the DCDC converter are M2 or
M3, M4, M5 and M6. Thanks to M7, M8 and M9, thecontroller selects between LOAD, STO and VINT respectively
as the converter output. M1 selects the source as main input
of energy. The internal supply VINT is regulated with priority
over LOAD. STO is selected as an output only when neither
VINT nor LOAD needs to be supplied. The converter has two
possible inputs: BUFSRC or STO. BUFSRC is used by default as
an input via M3. If the energy available on SRC is not sufficient
to maintain the LOAD or VINT voltage, for instance because ofa sudden current peak on LOAD, the converter uses STO
instead as an input via M2 to keep LOAD and VINT regulated.

DCDC Converter Mode

The reactive power component of this converter is theexternal inductor LDCDC. Periodically, the MPP control circuit
disconnects the source from the BUFSRC pin with thetransistor M1 in order to let the harvester on SRC rise to its
open-circuit voltage VOC and measure it. This is done to define
the optimal voltage level VMPP, which is determined byapplying the MPP ratio on VOC. BUFSRC is decoupled by thecapacitor CSRC, which smooths the voltage against the current
pulses pulled by the DCDC converter. The storage element isconnected to the STO pin.
Depending on its input voltage and its output voltage, the
DCDC converter will work as a boost converter, a buckconverter or a buck-boost converter. The maximum powerthat can be harvested and supplied to the output LOAD
depends on the power mode (HIGH POWER MODE or LOW
POWER MODE), which is configured through the EN_HP pin(see Section 9.1).

Input Voltage / Output Voltage

Boost

VIN < VOUT - 250 mV

Buck

VIN > VOUT + 250 mV

Buck - Boost

VOUT - 250 mV < VIN < VOUT + 250 mV

Table 7: DCDC Converter Modes

8.2. Cold-Start Circuit
The AEM10330 is able to coldstart if the voltage on CS_IN isabove 0.275 V. The minimum available power is:- 3 µW if VSTO is above VCHRDY.

CS_IN is typically connected to SRC to allow the AEM10330 tocoldstart from the energy available on the harvester.
Nevertheless, any other energy source can be connected to
CS_IN as long as it meets the electrical specifications
constraints described in Sections 5 and 6.

- 6 µW if VSTO is below VCHRDY.

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AEM10330

DATASHEET

8.3. AEM10330 States Description
Reset Stateafter 680 ms

VSRC > 275mV&
PSRC > 3μW
Wake-Up
State
VINT > 2.2V
Start State(VSTO > VCHRDY) & (STO_PRIO = H)OR(VSTO > VCHRDY) & (VLOAD > VLOAD,TYP) & (STO_PRIO = L)

Shutdown
State

EN_SLEEP = H&
VLOAD > VLOAD,MIN&
VINT > 2.2V

VSTO < VOVDIS

Sleep State

Supply StateVSTO > VOVDISEN_SLEEP = L
OR
VLOAD < VLOAD,MIN
OR
VINT < 2.2V

Figure 5: Diagram of the AEM10330 States

8.3.1. Reset, Wake Up and Start States

8.3.1.1. Storage Element Priority

The RESET STATE is a state where all nodes are deeply
discharged and there is no available energy to be harvested.
As soon as the required cold start voltage of 275 mV and asparse amount of power of just 3 µW become available on
CS_IN (usually connected to SRC), the AEM10330 switches to
WAKE-UP STATE, and energy is extracted from SRC to make
VVINT rise to 2.2 V. When VVINT reaches those 2.2 V, theAEM10330 switches to START STATE. In START STATE, two
scenarios are possible: in the first scenario, STO_PRIO is HIGH,
the storage element connected to STO has the priority on the
one connected to LOAD. In the second scenario, STO_PRIO isreset and the LOAD has the priority.

This paragraph covers the AEM10330 behavior when
STO_PRIO is pulled up to VINT, so that the storage element
connected on STO has priority over LOAD.

When the AEM10330 is in RESET STATE, WAKE-UP STATE or
START STATE, the DCDC converter’s input is always BUFSRC:
STO is never used as input. This guarantees that the storage
element is not used until a minimum amount of energy has
been stored in it.

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4

Supercapacitor as a Storage Element
If the storage element is a supercapacitor, it may be fullydischarged at first and thus need to be charged from 0 V. The
DCDC converter charges STO from the input source (SRC).
When VSTO reaches VCHRDY, the circuit enters SUPPLY STATE.
Battery as a Storage Element
If the storage element is a battery, but its voltage is lower
than VCHRDY, then the storage element needs to be charged
first until it reaches VCHRDY. Once VSTO reaches VCHRDY, or if
the battery was initially charged above VCHRDY, the circuit
enters SUPPLY STATE.

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8.3.1.2. Load Priority

8.3.3. Shutdown State

If STO_PRIO is connected to GND, the AEM charges first theLOAD to VLOAD,MAX (see Table 9) using energy from the source(SRC). This allows to first supply the application circuit
connected to LOAD. If the storage element was initiallycharged above VCHRDY, the circuit enters SUPPLY STATE assoon as LOAD reaches VLOAD,TYP. If the storage element is asupercapacitor or a battery which voltage is lower than
VCHRDY, the AEM keeps regulating LOAD between VLOAD,MAX
and VLOAD,TYP. Meanwhile, any excess charges on the source
is used to charge the storage element until it reaches VCHRDY.
Once VSTO exceeds VCHRDY, the circuit enters into SUPPLYSTATE.

If the storage element gets depleted (VSTO < VOVDIS), theAEM10330 goes to SHUTDOWN STATE. As long as the
AEM10330 is in this state, the ST_STO_OVDIS is HIGH. In
SHUTDOWN STATE, if VSTO recovers within 680 ms, theAEM10330 goes back to SUPPLY STATE. This prevents false
detection of the storage element being empty because of a
LOAD current peak.

This configuration is useful when a large storage element isconnected to STO and a smaller one is connected to LOAD: theapplication starts as soon as CLOAD is charged and does nothave to wait for the large storage element on STO to be
charged.

8.3.2. Supply StateIn SUPPLY STATE, four scenarios are possible:- There is enough power provided by the source (SRC)to keep VLOAD near VLOAD,TYP with a small hysteresis
and VVINT at 2.2 V. The excessive power is used tocharge the storage element on STO. In that case, thecircuit remains in SUPPLY STATE. If STO is fully
charged, LOAD will be maintained at VLOAD,MAX
instead of VLOAD,TYP. If all nodes are fully charged, the
DCDC converter is disabled to prevent over-charging
the storage element, and the SRC pin is set to highimpedance.
- If the circuit connected to LOAD consumes moreenergy than the energy that the AEM10330 is able toextract from the source, the LOAD circuit will be
supplied by the storage element connected to the
STO terminal. In this case, the circuit stays in SUPPLYSTATE.
- Due to a lack of power from the source, VSTO falls
below VOVDIS. In this case, the circuit enters
SHUTDOWN STATE as explained in Section 8.3.3.
- If EN_SLEEP is HIGH and conditions (shown on Figure5) on VLOAD and VVINT are satisfied, the AEM enters
SLEEP STATE (see section 8.3.4).

8.3.4. Sleep StateSLEEP STATE reduces the AEM10330 quiescent current by
disabling the DCDC converter and by reducing the controller
clock frequency. If VVINT or VLOAD fall below their regulation
value, the AEM10330 temporarily exits SLEEP STATE to wakeup the DCDC converter and supply VINT or LOAD. Exiting
SLEEP STATE and waking up the DCDC converter takes up to
1 ms. Depending on the expected LOAD current, CLOAD value
must be adapted to act as an energy buffer during the 1 ms
required to wake up the DCDC converter. Therefore, this state
may be enabled when LOAD current is small, and be disabled
if a high LOAD current is expected. As the DCDC is disabled, noenergy is harvested from SRC while in SLEEP STATE, so thatthe storage element connected to STO is no longer charged.
LOAD and VINT are the only nodes that are still supplied andregulated when the AEM10330 is in SLEEP STATE. This modeis useful to limit the current drawn on STO when theapplication circuit has detected that the power available on
SRC is so low that it wouldn’t compensate the AEM10330
internal circuit power consumption (see Table 5).
The AEM10330 enters SLEEP STATE if all the following
conditions are satisfied:- EN_SLEEP pin pulled up to LOAD (H)- VVINT > 2.2 V- VLOAD > VLOAD,TYP
The AEM10330 leaves SLEEP STATE and switches back to
SUPPLY STATE if one of the following conditions is satisfied:- EN_SLEEP pin pulled down to GND (L)- VVINT < 2.2 V- VLOAD < VLOAD,TYP
The AEM10330 will then stay in SUPPLY STATE until the SLEEPSTATE conditions are all satisfied again.

8.4. Maximum Power Point Tracking
During SUPPLY STATE, SHUTDOWN STATE and START STATE,
the voltage on SRC is regulated by an internal Maximum
Power Point Tracking (MPPT) module. The MPPT module
evaluates VMPP, the voltage at which the source provides thehighest possible power, as a given fraction of the open-circuit
voltage of the source VOC. This ratio is set by the R_MPP[2:0]DS-AEM10330-v1.4.0
DS-AEM10330-v1.4

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terminals according to Table 10. The sampling period andduration are set according to Table 11 by the T_MPP[1:0]
terminals. The AEM10330 supports any VMPP levels in therange from 100 mV to 4.5 V. It offers a choice of seven values
for the VMPP / VOC fraction. It can also match the input
impedance of the DCDC converter with an impedanceconnected to the ZMPP terminal as explain as explained in
section 9.7.

8.5. Balancing for Dual-Cell Supercapacitor
The balancing circuit allows the user to balance the internal
voltage of the dual-cell supercapacitor connected to STO inorder to avoid damaging the supercapacitor because ofexcessive voltage on one cell.
If BAL is connected to GND, the balancing circuit is disabled.
This configuration must be used if a battery, a capacitor or asingle-cell supercapacitor is connected on STO.

If BAL is connected to the node between both cells of asupercapacitor, the balancing circuit compensates for any
mismatch of the two cells that could lead to the over-chargeof one of two cells. The balancing circuit ensures that BAL
remains close to VSTO / 2. This configuration must be used if adual-cell supercapacitor is connected to STO, and that thissupercapacitor requires cells balancing.
The balancing circuit works as follows, with VBAL the voltage
on the BAL pin:V

STO : the AEM10330 enables a switch- V BAL  -----------

2

between BAL and GND to discharge the bottom
supercapacitor cell to GND (up to 20 mA).
V

STO
- V BAL  ----------: the AEM10330 enables a switch2

between STO and BAL to discharge the top
supercapacitor cell to the bottom supercapacitor cell(up to 20 mA).

NOTE: the balancing feature is optimized for supercapacitors,
for use with other storage elements (batteries, etc.), pleasecontact e-peas support.

DS-AEM10330-v1.4.0
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9. System Configuration
9.1. High Power / Low Power Mode
When EN_HP is pulled to VINT, the DCDC converter isconfigured to HIGH POWER MODE. This allows higher
currents to be extracted from the DCDC converter input (SRCor STO) to the DCDC converter output (LOAD or STO). Figure 6
shows the maximum current that the DCDC converter can
supply to LOAD, depending on the storage voltage VSTO, forevery available load voltage VLOAD, for both HIGH POWER
MODE and LOW POWER MODE.

Figure 6: Maximum LOAD Current Depending on VSTO and on VLOAD

9.2. Storage Element Configuration
Through four configuration pins (STO_CFG[3:0]), the user can
set a particular operating mode from a range that covers mostapplication requirements, without any dedicated external
component as shown in Table 8. The three threshold levels
are defined as:

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4- VOVCH: maximum voltage accepted on the storage
element before disabling its charging.
- VCHRDY: minimum voltage required on the storage
element before starting to supply the LOAD (if
STO_PRIO is HIGH) and entering supply state after
start-up.

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DATASHEET- VOVDIS: minimum voltage accepted on the storage
element before considering the storage element as
depleted, thus setting ST_STO LOW.
A large-size storage element is not mandatory on STO:
- If the harvested energy source is permanently
available and covers the application needs orConfiguration pins
STO_CFG[3:0]
L

L

L

L

- If the application does not need to store energy when
the harvested energy source is not available
The storage element may then be replaced by an external
capacitor CSTO with a minimum value of 100 μF.

CAUTION: running the AEM10330 without this 100 μF
minimum capacitance on STO will permanently damage thecircuit.

Storage element thresholdvoltages
VOVDIS

VCHRDY

VOVCH

3.00 V

3.50 V

4.05 V

Typical use
LiCoO2 battery, Li-Po battery, Lithium Titanate (3.8 V) battery (long life).

L

L

L

H

2.80 V

3.10 V

3.60 V

LiFePO4 battery, Lithium capacitor (LiC).

L

L

H

L

1.85 V

2.40 V2.70 V

Dual-cell NiMH battery, Lithium-Titanate (2.4V) battery.

L

L

H

H

0.20 V

1.00 V

4.65 V

Dual-cell supercapacitor.

L

H

L

L

0.20 V

1.00 V

2.60 V

Single-cell supercapacitor.

L

H

L

H

1.00 V

1.20 V

2.95 V

Single-cell supercapacitor.

L

H

H

L

1.85 V

2.30 V

2.60 V

Lithium-Titanate battery (2.4V).

L

H

H

H

H

L

L

L

Custom Mode (single-cell NiMH battery, LiC, etc.)1.
1.10 V

1.25 V

1.50 V

Ni-Cd single-cell battery.

H

L

L

H

2.20 V

2.50 V

3.00 V

Ni-Cd dual-cell battery.

H

L

H

L

1.45 V

2.00 V

4.65 V

Dual-cell supercapacitor.

H

L

H

H

1.00 V

1.20 V

2.60 V

Single-cell supercapacitor.

H

H

L

L

2.00 V

2.30 V

2.60 V

Solid State battery.

H

H

L

H

3.00 V

3.50 V

4.35 V

LiCoO2 battery, Li-Po battery, Lithium Titanate (3.8 V) battery.

H

H

H

L

2.60 V2.70 V

4.00 V

Tadiran TLI.

H

H

H

H

2.60 V

3.50 V

3.90 V

Tadiran HLC.

Table 8: Storage Element Configuration Pins
1. An example of a single-cell NiMH batteries optimized custom mode setting can be found at Section 10.2.

DS-AEM10330-v1.4.0
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9.3. Load Configuration
The LOAD output voltage VLOAD can be configured thanks to
the LOAD_CFG[1:0] configuration pins covering mostapplication cases (see Table 9). VLOAD is regulated to
VLOAD,TYP. However, if VLOAD falls below VLOAD,MID, thecontroller forces STO as an input of the DCDC converter tosupply LOAD.
When the AEM10330 is in SUPPLY STATE:- VLOAD < VLOAD,MID: the AEM10330 charges CLOAD bytransferring the energy available on the storage
element STO (if VSTO is above VOVDIS), even if energy
is available on SRC.

- VLOAD,TYP is the typical average voltage to be
expected on the LOAD pin.
- ST_LOAD reflects VLOAD, with an hysteresis between
VLOAD,MIN and VLOAD,TYP:- ST_LOAD is HIGH when VLOAD > VLOAD,TYP.
- ST_LOAD is LOW when VLOAD < VLOAD,MIN.
- As a reminder, the order of priority in which thenodes are recharged is as follows:- VINT always has the highest priority, as it ismandatory to keep the AEM10330 internal
circuit supplied.
- LOAD has the second highest priority, to keep
the application circuit supplied.

- VLOAD,MID < VLOAD < VLOAD,MAX:- STO has the lowest priority, as the storage
element is used to store the excessive energy
from SRC.

- If energy is available on SRC, the AEM10330
uses it to charge CLOAD.
- If no energy is available on SRC, the AEM10330
uses the energy available on STO to charge
CLOAD.
Configuration pins
LOAD_CFG[1:0]

LOAD output voltage
VLOAD,MIN

VLOAD,MID

VLOAD,TYPVLOAD,MAX

L

L

3.15 V

3.23 V

3.28 V3.34 VL

H

2.35 V

2.47 V

2.50 V2.53 VH

L

1.64 V

1.75 V

1.79 V

1.82 V

H

H

1.14 V

1.16 V

1.20 V

1.23 V

Table 9: Load Configuration Pins

9.4. Custom Mode Configuration

VOVCH, VCHRDY and, VOVDIS are defined thanks to R1, R2, R3
and R4, which can be determined within the following
constraints:

VSTO- RT = R1 + R2 + R3 + R4
- 1M  R T  100M

Optional

STO_OVDIS1V- R 1 = R T  ---------------

STO_RDY

1V - – --------------1V - R 2 = R T   ----------------

R4

R3

R2
STO_OVCH

V CHRDYV OVCH

1V - – ----------------1V - - R 3 = R T   ---------------V OVDISV CHRDY

1V - 
- R 4 = R T   1 – ---------------
V OVDISR1

Figure 7: Custom Mode Settings

When STO_CFG[3:0] = LHHH, the custom mode is selected
and all four configuration resistors must be wired as shown in
Figure 7.

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4

V OVCHThe resistors should have high values to make the additional
power consumption negligible. Moreover, the following
constraints must be respected to ensure the functionality of
the chip:- V CHRDY + 0.05V  V OVCH  4.5V
- V OVDIS + 0.05V  V CHRDY  V OVCH – 0.05V- 1V  V OVDIS

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DATASHEET

9.5. Disable Storage Element Charging
Pulling down EN_STO_CH pin to GND disables the charging of
the storage element connected to STO from SRC. This can bedone for example to protect the storage element when thesystem detects that the environment temperature is too low
or too high to safely charge the storage element.

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4

AEM10330

While EN_STO_CH is pulled down, VINT and LOAD can still be
supplied either from SRC or from STO.
To enable charging the storage element on STO, EN_STO_CH
must be pulled up to LOAD or left floating (pin is pulled up
internally).
Please note that STO will still be charged to VCHRDY during the
START STATE

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9.6. MPPT Configuration- 10 Ω ≤ RZMPP ≤ 100 KΩ

The MPPT module is configured through the following pins:

Optional- R_MPP[2:0] allows for configuring the VMPP / VOC
tracking ratio, that has to be chosen according to thecharacteristics of the source. Please note that if theselected mode is ZMPP, an external resistor must be
added to the circuit as explained in Section 9.7.

RZMPP

SOURCE- T_MPP[1:0] allows for configuring the duration of an
MPP evaluation and the time between two MPP
evaluations.
Configuration pins

MPPT ratio

R_MPP[2:0]

VMPP / VOC

L

L

L

60%

L

L

H

65%

L

H

L

70%

L

H

H

75%

H

L

L

80%

H

L

H

85%

H

H

L

90%

H

H

H

ZMPP

Table 10: MPP Ratio Configuration Pins
Configuration pins
T_MPP[1:0]

MPPT timing
Sampling
duration

Sampling
periodLL

5.19 ms

280 msL

H

70.8 ms

4.5 s

H

L

280 ms17.9 sH

H

1.12 s71.7 sTable 11: MPP Timing Configuration Pins

9.7. ZMPP Configuration

SRC

CS_IN

Co

Figure 8: RZMPP Connection to the AEM10330

9.8. Source to Storage Element FeedThroughWhen the harvester connected to SRC delivers a high amountof power, the AEM might not be able to pull enough current
to regulate VSRC to the MPP voltage. The voltage on SRC thusincreases, eventually above 5V. To maximize the energy
extracted in that case, the AEM30330 can be configured tocreate a direct feed-through current path from SRC to STO
when VSRC is above 5V. This is measured when the AEM ispulling current from the source (not during an MPP
evaluation).
If the MPPT module detects that VSRC is higher than 4 V and
EN_STO_FT is set, the SRC is monitored. From that moment, if
the AEM10330 detects that VSRC rises above 5 V and if thestorage element is not fully charged, the switch between the
SRC and STO pins is closed until VSRC drops below 5 V or until
the storage element is fully charged.
This feature is enabled by pulling up EN_STO_FT pin to VINT.
However, it is disabled if the storage element is fully charged,
or when a MPP evaluation is occurring. Therefore the circuit
must still be protected from any overshoot voltage on SRC
above 5.5 V, for instance by a zener diode.

Instead of working at a ratio of the open-circuit voltage, theAEM10330 can regulate the input impedance of the DCDC
converter so that it matches a constant impedance RZMPP
connected to the ZMPP pin. In this case, the AEM10330
regulates VSRC at a voltage that is the product of the ZMPP
resistance RZMPP and the current available at the SRC input.

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4

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DATASHEETAEM10330

9.9. External Components
Refer to Figure 18 to have an illustration of the external
components wiring.

9.9.3. External Capacitors Information
9.9.3.1. CSRC

9.9.1. Storage Element Information
The energy storage element of the AEM10330 can be arechargeable battery, a supercapacitor or a capacitor. The
size of the storage element must be determined so that its
voltage does not fall below VOVDIS even during current peaks
pulled by the application circuit connected to LOAD. If theinternal resistance of the storage element cannot sustain thisvoltage limit, it is advisable to decouple the battery with acapacitor.
If the application expects a disconnection of the battery (e.g.
because of a user removable connector), the PCB should
include a capacitor CSTO of at least 100 μF connected between
STO and GND. The leakage current of the storage element
should be small as leakage currents directly impact thequiescent current of the whole subsystem.

This capacitor acts as an energy buffer at the input of the
DCDC converter. It prevents large voltage fluctuations when
the DCDC converter is switching. The recommended nominal
value is 22 µF.

9.9.3.2. CINTThis capacitor acts as an energy buffer for the internal voltage
supply. The recommended nominal value is 10 µF.

9.9.3.3. CLOAD
This capacitor acts as an energy buffer for LOAD. It also
reduces the voltage ripple induced by the current pulses
inherent to the switched behavior of the converter. The
recommended value is at least 13 µF (considering derating
and tolerance).

9.9.2. External Inductor Information
The AEM10330 operates with one standard miniatureinductor. LDCDC must sustain a peak current of at least 1 A anda switching frequency of at least 10 MHz. Low equivalent
series resistance (ESR) favors the power conversion efficiencyof the DCDC converter. The recommended value is 10 µH.

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10. Typical Application Circuits
10.1. Example Circuit 1
LDCDC

CSRC
22uF

LOUT

BUFSRC

LIN

10uH

VINT
VINT

VINT

R_MPP[2]VINT

R_MPP[1]GND

R_MPP[0]GND

T_MPP[1]VINT

T_MPP[0]

CINT
10uF

LOAD
CLOAD
47uF

VSTO

AEM10330

ZMPP

PV cell

SRC

STO

CS_IN

Supercapacitor

BAL
GND

STO_CFG[3]GND

STO_CFG[2]VINT

STO_CFG[1]VINT

STO_CFG[0]Microcontroller
Radio Transceiver

1.2F

ST_LOAD
ST_STO
ST_STO_RDY

GND

LOAD_CFG[1]VINT

LOAD_CFG[0]ST_STO_OVDISSTO_OVDISSTO_RDY
STO_OVCH

EN_STO_FT

VINT

STO_PRIO

VINT

EN_SLEEPGND

EN_STO_CH

GND

EN_HP

GND

GND

Figure 9: Typical Application Circuit 1

The circuit is an example of a system with solar energy
harvesting. It uses a pre-defined operating mode that uses
standard components, and a supercapacitor as energy
storage.

- The balancing pin of the dual-cell supercapacitor isconnected to BAL.

- Energy source: PV cell.

- LOAD_CFG[1:0] = LH: the microcontroller and theradio transceiver are supplied by the LOAD terminal,
which is regulated at VLOAD = 2.50 V.

- R_MPP[2:0] = HHL: the MPP tracker ratio is set to90%.

- STO_PRIO is connected to VINT: at start-up STO will
be charged and before LOAD.

- T_MPP[1:0] = LH: the MPP sampling period is 4.5 s
and the MPP sampling duration is 70.8 ms.

- EN_SLEEP is connected to GND: the AEM10330 will
never switch to SLEEP STATE.

- STO_CFG[3:0] = LLHH: the storage element is a dualcell supercapacitor, with:- EN_STO_CH is connected to VINT: the charging of thestorage element on STO is enabled.

- VOVCH = 4.65 V- VCHRDY = 1.00 V- VOVDIS = 0.20 V

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4- EN_HP is connected to GND: the DCDC converter is in
LOW POWER MODE.
- EN_STO_FT is connected to VINT: SRC to STO feedthrough is enabled when VSRC is above 5 V.

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10.2. Example Circuit 2
LDCDC

CSRC
22uF

LOUT

BUFSRC

LIN

10uH

VINT
VINT

GND

R_MPP[2]VINT

R_MPP[1]GND

R_MPP[0]VINT

T_MPP[1]GND

T_MPP[0]ZMPP

PV Cell

SRC

CINT
10uF

LOAD
CLOAD
47uF

AEM10330

VSTO
STO

Microcontroller
Radio Transceiver

NiMH
Battery

CS_IN
BAL
GND

STO_CFG[3]VINT

STO_CFG[2]VINT

STO_CFG[1]VINT

STO_CFG[0]ST_LOAD
ST_STO
ST_STO_RDY

VSTO

VINT

LOAD_CFG[1]GND

LOAD_CFG[0]ST_STO_OVDIS

R4
1 MΩ

EN_STO_FT

VINT

STO_PRIO

VINT

Control From
Application Circuit

EN_SLEEPR3
15 MΩ

STO_OVDISSTO_RDYR2
11 MΩ

STO_OVCH

EN_STO_CH

GND

EN_HP

VINT

GND

R1
68 MΩ

Figure 10: Typical Application Circuit 2
1V - – ----------------1V -   15M- R 3 = R T   ---------------

The circuit is an example of a system with solar energy
harvesting. It uses a rechargeable NiMH battery as storage
element. The voltage thresholds are set by the custom mode.

V OVDISV CHRDY

1V -   1M
- R 4 = R T   1 – ---------------
V OVDIS- Energy source: PV cell.
- R_MPP[2:0] = LHL: the MPP ratio is set to 70%.
- T_MPP[1:0] = HL: the MPP sampling period is 17.9 s
and the MPP sampling duration is 280 ms.
- STO_CFG[3:0] = LHHH: the storage element is a NiMH
rechargeable battery, used with custom mode:- VOVDIS = 1.00 V- VCHRDY = 1.20 V- VOVCH = 1.40 V- Custom mode resistor divider calculations (values
have been chosen to match E24 series value):- R T = 95M- BAL is not used (not a dual-cell storage element) so it
is connected to GND.
- LOAD_CFG[1:0] = HL: the micro-controller and theradio transceiver are supplied by the LOAD terminal,
which is regulated at VLOAD = 1.79 V.
- STO_PRIO is connected to VINT: at start-up STO will
be charged and before LOAD.
- EN_SLEEP is controlled by the application circuit,typically by a microcontroller GPIO output.
- EN_STO_CH is connected to LOAD: the charging of
the storage element present on STO is enabled.

1V- R 1 = R T  -------------- 68M- EN_HP is connected to VINT: the DCDC converter is in
HIGH POWER MODE.

1V - – --------------1V   11M- R 2 = R T   ----------------

- EN_STO_FT is connected to VINT: SRC to STO feedthrough is enabled when VSRC is above 5 V.

V OVCHV CHRDY

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V OVCH

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NOTE: for LiC (Lithium-ion Capacitor) storage elements, orothers that would not be covered by STO_CFG[3:0] presets,
please apply the same equations as in the above example todetermine custom mode resistors values. E24 series values fortypical storage elements can be found in the AEM10330
Configuration Tool spreadsheet, to be downloaded on e-peas
website.

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DATASHEET

11. Circuit Behavior
11.1. Wake-up state, Start state and Supply state
SRC
5

STO

WAKE UP
STATE

VINT

LOAD

START
STATE

SUPPLY
STATE

Vovch

4

Voltage [V]Vchrdy
3
2
1
0

0

2

4

6

8

10

12

14

Time [s]1

ST LOAD

0
1

ST STOST STO RDY
ST STO OVDIS

0
1
0
1
0

Figure 11: Wake-up state, Start state and Supply state- STO_CFG[3:0] = LLLL- VOVDIS = 3.00 V- VCHRDY = 3.50 V- VOVCH = 4.05 V- SRC: 5 mA current source with 3 V voltage
compliance- LOAD_CFG[1:0] = LL (VLOAD,TYP = 3.28 V)- EN_HP = H (high power mode)- R_MPP[2:0] = LLL (60%)- EN_STO_CH = H (storage element charge enabled)- T_MPP[1:0] = LL (5.19 ms / 280 ms)- STO_PRIO = H (storage element charged in priority
after startup)- CSTO = 10 mF

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4- EN_SLEEP = L (sleep mode disabled)

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11.2. Supply state, Shutdown state and Reset state
SRC
5

STO

VINT

SUPPLYSTATELOAD
SHUTDOWN
STATE

RESET
STATE

Vovch

4

Voltage [V]VchrdyVovdis

3
2
1
0

0

5

10

15

20

25

30

Time [s]1

ST LOAD

0
1

ST STOST STO RDY
ST STO OVDIS

0
1
0
1
0

Figure 12: Supply State, Shutdown state and Reset state- SRC: left floating force the storage element on STO todischarge- STO_CFG[3:0] = LLLL- VOVDIS = 3.00 V- EN_HP = H (high power mode)- VCHRDY = 3.50 V- VOVCH = 4.05 V- LOAD_CFG[1:0] = LL (VLOAD,TYP = 3.28 V)- R_MPP[2:0] = LLL (60%)- T_MPP[1:0] = LL (5.19 ms / 280 ms)- CSTO = 10 mF

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4- STO_PRIO = H (storage element charged in priority
after startup)- EN_STO_CH = H (storage element charge enabled)- EN_SLEEP = L (sleep mode disabled)- 10 kΩ connected between LOAD and GND

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12. Performance Data
12.1. DCDC Conversion Efficiency From SRC to STO in Low Power ModeLP mode, ISRC = 100 μA

LP mode, ISRC = 1 mA

100

90

90

80

80

70

70

60

60

Eﬃciency [%]Eﬃciency [%]

100

50
40
30

10

40
30

VST O = 1.25 V
VST O = 2.30 V
VST O = 3.60 V
VST O = 4.10 V

2050

VST O = 1.25 V
VST O = 2.30 V
VST O = 3.60 V
VST O = 4.10 V

20
10

0

0
0.0

0.5

1.0

1.5

2.0

2.5
VSRC [V ]

3.0

3.5

4.0

4.5

0.0

0.5

1.0

1.5

2.0

2.5
VSRC [V ]

3.0

3.5

4.0

4.5

LP mode, ISRC = 10 mA

100
90
80

Eﬃciency [%]

70
60
50
40
30

VST O = 1.25 V
VST O = 2.30 V
VST O = 3.60 V
VST O = 4.10 V

20
10
0
0.0

0.5

1.0

1.5

2.0

2.5
VSRC [V ]

3.0

3.5

4.0

4.5

Figure 13: DCDC Efficiency from SRC to STO for 1 mA and 10 mA in Low Power Mode

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12.2. DCDC Conversion Efficiency From SRC to STO in High Power Mode
HP mode, ISRC = 100 μA

90

90

80

80

70

70

60
50
40
30

10
0

0.0

0.5

1.0

2.0
2.5
3.0
VSRC [V ]

3.5

4.0

50
40

10
0

4.5

80

70

70
Eﬃciency [%]

90

80

60
50
40
VST O = 1.25 V
VST O = 2.30 V
VST O = 3.60 V
VST O = 4.10 V

20
10
0

0.0

0.5

1.0

1.5

2.0
2.5
3.0
VSRC [V ]

0.0

0.5

1.0

3.5

4.0

4.5

1.5

2.0
2.5
3.0
VSRC [V ]

3.5

4.0

4.5

HP mode, ISRC = 50 mA

100

90

30

VST O = 1.25 V
VST O = 2.30 V
VST O = 3.60 V
VST O = 4.10 V

20

HP mode, ISRC = 10 mA

100

Eﬃciency [%]

1.5

60

30

VST O = 1.25 V
VST O = 2.30 V
VST O = 3.60 V
VST O = 4.10 V

20

HP mode, ISRC = 1 mA

100

Eﬃciency [%]Eﬃciency [%]

100

60
50
40
30

VST O = 1.25 V
VST O = 2.30 V
VST O = 3.60 V
VST O = 4.10 V

20
10
0

0.0

0.5

1.0

1.5

2.0
2.5
3.0
VSRC [V ]

3.5

4.0

4.5

Figure 14: DCDC Efficiency from SRC to STO for 10 mA and 50 mA in High Power Mode

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12.3. DCDC Conversion Efficiency From STO to LOAD in Low Power ModeLP mode, VLOAD = 1.20 V

90

90

80

80

70

70

60

60

50
40
30

50
40
30

20

20

VST O = 1.25 V
VST O = 2.50 V
VST O = 3.60 V

100100 μALP mode, VLOAD = 1.80 V

100

Eﬃciency [%]Eﬃciency [%]

100

1 mA

10 mA

VST O = 1.25 V
VST O = 2.50 V
VST O = 3.60 V

10

100 mA0100 μA

1 mA

ILOAD [A]
100

10 mA

100 mAILOAD [A]LP mode, VLOAD = 3.30 V

90
80

Eﬃciency [%]

70
60
50
40
30
20

VST O = 1.25 V
VST O = 2.50 V
VST O = 3.60 V

100100 μA

1 mA

10 mA

100 mAILOAD [A]Figure 15: DCDC Efficiency from STO to LOAD in Low Power Mode

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12.4. DCDC Conversion Efficiency From STO to LOAD in High Power Mode
HP mode, VLOAD = 1.20 V

90

90

80

80

70

70

60

60

50
40
30

50
40
30

20

20

VST O = 1.25 V
VST O = 2.50 V
VST O = 3.60 V

100100 μAHP mode, VLOAD = 1.80 V

100

Eﬃciency [%]Eﬃciency [%]

100

1 mA

10 mA

VST O = 1.25 V
VST O = 2.50 V
VST O = 3.60 V

10

100 mA0100 μA

1 mA

ILOAD [A]
100

10 mA

100 mAILOAD [A]HP mode, VLOAD = 3.30 V

90
80

Eﬃciency [%]

70
60
50
40
30
20

VST O = 1.25 V
VST O = 2.50 V
VST O = 3.60 V

100100 μA

1 mA

10 mA

100 mAILOAD [A]Figure 16: DCDC Efficiency from STO to LOAD in High Power Mode

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12.5. Quiescent Current

Quiescent Current [μA]2.0
Sleep mode, Low Power
Sleep mode, High Power
Active mode, Low Power
Active mode, High Power

1.5

1.0

0.5

0.0

1.0

1.5

2.0

2.5
VST O [V ]

3.0

3.5

4.0

Figure 17: Quiescent Current

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13. Schematic
Optional

2

U1A

Optional

ZMPP

3

1

7
CSRC
22uF
10V
0603

17
CLOAD
47uF
6.3V
0603

AEM10330

RZMPP

Harvester

LOAD

8

SRC

VINT

BUFSRC

CINT
10uF
6.3V
0402

CSTO
100uF
6.3V
1206

Storage
Element

Optional

11
12
15

VINT
GND

32
30

U1B

R4

R_MPP[2]R_MPP[1]R_MPP[0]STO_OVDIS

T_MPP[1]T_MPP[0]21

R3
STO_RDY

22

VINT
GND

25
24

GND
VINT
VINT
VINT

27
35
34
33

GND
GND
GND
VINT
GND

28
20
31
29
39

LOAD_CFG[1]LOAD_CFG[0]R2
STO_OVCH

23

STO_CFG[3]STO_CFG[2]STO_CFG[1]STO_CFG[0]EN_HP
EN_STO_CH
EN_STO_FT
STO_PRIO
EN_SLEEPR1

ST_LOAD
ST_STO
ST_STO_RDY
ST_STO_OVDIS

36
40
37
38

to application
circuit

4
5
6
10
16
14
26
41

LOUT

18

GND
GND
GND
GND
GND
GND
GND
GND

BAL

VINT
VINT
GND

AEM10330

STO

19

LIN

LDCDC
10μH
9

STO

VINT

13

CS_IN

STO

Application
CircuitFigure 18: Schematic Example
Designator

Description

Quantity

Manufacturer

Link

U1

AEM10330 - Symbol QFN 40-pin

1e-peasorder at sales@e-peas.com

LDCDC

Power inductor 10 µH - 1.76A

1

Murata

DFE252010F-100M

CLOAD

Ceramic Cap 47 µF, 6.3V, 20%, X5R 0603

1

Murata

GRM188R60J476ME15

CINT

Ceramic Cap 10 µF, 6.3V, 20%, X5R 0402

1

Murata

GRM155R60J106ME15

CSRC

Ceramic Cap 22 µF, 10V, 20%, X5R 0603

1

Murata

GRM188R61A226ME15D

CSTO (optional)

Ceramic Cap 100 μF, 6.3V, 20%, X5R 1206

1

TDK

C3216X5R1A107M160AC

Table 12: Minimal Bill of Materials

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14. Layout
14.1. Guidelines
Good layout practices are mandatory in order to obtain goodstability and best efficiency with the AEM10330. It also allows
for minimizing electromagnetic interferences generated by
the AEM10330 DCDC converter.
The following list, while not exhaustive, shows the main
attention points when routing a PCB with the AEM10330:- The switching nodes (LIN and LOUT) must be kept as
short as possible, with minimal track resistance andminimal track capacitance. Low resistance isobtained by keeping track length as short as possible
and track width as large as possible between LDCDC
and the AEM10330 pins. Minimal capacitance isobtained by keeping distance between LIN/LOUT andother signals. We recommend removing the groundplane, the power plane and the bottom layer groundpour under LDCDC footprint, as well as adding
distance between LIN/LOUT and the top groundpour, as shown on Figure 19.
- The DCDC decoupling capacitors (CSRC - CLOAD - CSTO)
must be placed as close as possible to the AEM10330,
with direct connection and minimum track resistancefor the corresponding power nodes (BUFSRC, LOAD
and STO).
- The GND return path between the DCDC decoupling
capacitors (CSRC - CLOAD - CSTO) and the AEM10330
thermal pad, which is the AEM10330 main GND
connection, must be as direct and short as possible.
This is preferably done on the top layer whenpossible, otherwise by internal/bottom plane, using
low resistance vias to decrease layer-to-layer
connection resistance.

DS-AEM10330-v1.4.0
DS-AEM10330-v1.4- The external DC power connections (SRC, LOAD andSTO) must be connected to the AEM10330 with low
resistance tracks.
- Connection between VINT and CINT must be
moderately short for AEM10330 stability, eventhough this pins does not carry large currents. Samefor connection between CINT to GND.
- If used, ZMPP must be connected to the AEM10330
with a low resistance track, according to the
expected SRC power.
- The BAL pin connection track must be able to handle
at least 40 mA.
- The custom mode setting pins STO_OVDIS, STO_RDY
and STO_OVCH are high impedance analog inputs
typically connected to a resistive divider with highresistor values, making those three nodes prone to
pickup noise. Thus it is recommended to keep thoseas short as possible and as far as possible to noise
sources such as DCDC switching nodes.
- The configuration pins and the status pins haveminimal layout restrictions. CS_IN maximum current
is below 1 mA, so its layout restrictions are minimal
as well.

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Figure 19: Layout Example for the AEM10330 and its Passive Components

NOTE: schematic, symbol and footprint for the e-peas
component can be ordered by contacting e-peas support teamat support@e-peas.com

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15. Package Information
15.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm)

5.000 ± 0.05

5.000 ± 0.05

0.800 ± 0.05

3.200 ± 0.05

5.000 ± 0.05

10.320 ± 0.05 Typ.

0.200 ± 0.05

3.200 ± 0.05

0.400 ± 0.05 BSC

0.203 ± 0.05

40

Figure 20: QFN 40-pin 5x5mm Drawing (All Dimensions in mm)

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15.2. Board Layout
0.400 BSC

5.000

4.150

3.200

0.750

0.200

3.200
4.150
5.00
Figure 21: Recommended Board Layout for QFN40 package (All Dimensions in mm)

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16. Revision History
Revision

Date

Description

0.0

January, 2021

Creation of the document. Preliminary version.

1.0

June, 2021

First version of the document

1.1

August, 2021

Minor modifications

1.2

March, 2023--

Various aesthetic improvements.
Explanations about BAL circuit.
Section with precisions about the use of CS_IN.
Removed LOAD_CFG[2] and related configurations.
New “behavior” oscilloscope graphs with improved description.
Moved various states description sections as sub-sections of a global section.
Supply State description: explanation about SRC being set to high impedance
when all nodes are fully charged.
Updated "Typical use" of storage element vs STO_CFG[3:0] configuration.
Replaced "asserted/de-asserted" by "HIGH/LOW".
Changed CSRC from 15µF/0402 to 22µF/0603.
Updated "Recommended Operation Conditions" with minimum capacitor
values including derating and tolerances.
Removed wong dimenson from package dimensions figure.

-

Updated efficiency graphs.
Created section for pinout.
Updated schematics with new symbol.
Digital levels High/Low: replaced 0/1 notation by L/H.
Fixed example circuits errors.
Fixed typos and aesthetic issues.
Added layout guidelines with clearer layout examples.

-

1.3

November, 2023

1.4

February, 2024

Fixed wrong HIGH level of ST_STO in “Power and Status Pins” table.

Table 13: Revision History

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