3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32CDATASHEET

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1
Rev.2.0

GD25B32C

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Content
1. FEATURES ............................................................................................................................................................ 4
2. GENERAL DESCRIPTION ................................................................................................................................. 5
3. MEMORY ORGANIZATION ............................................................................................................................. 7
4. DEVICE OPERATION ......................................................................................................................................... 8
5. DATA PROTECTION ........................................................................................................................................... 9
6. STATUS REGISTER ............................................................................................................................................ 11
7. COMMANDS DESCRIPTION ............................................................................................................................ 13
7.1. WRITE ENABLE (WREN) (06H) .................................................................................................................. 16
7.2. WRITE DISABLE (WRDI) (04H) .................................................................................................................. 16
7.3. WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................. 16
7.4. READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) ..................................................................... 177.5. WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H) ................................................................... 17
7.6. READ DATA BYTES (READ) (03H) ............................................................................................................. 18
7.7. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) ............................................................... 18
7.8. DUAL OUTPUT FAST READ (3BH) ............................................................................................................ 19
7.9. QUAD OUTPUT FAST READ (6BH) ............................................................................................................ 20
7.10. DUAL I/O FAST READ (BBH) ..................................................................................................................... 20
7.11. QUAD I/O FAST READ (EBH) ..................................................................................................................... 22
7.12. QUAD I/O WORD FAST READ (E7H) ........................................................................................................ 23
7.13. SET BURST WITH WRAP (77H) .................................................................................................................. 24
7.14. PAGE PROGRAM (PP) (02H) ....................................................................................................................... 25
7.15. QUAD PAGE PROGRAM (32H) ................................................................................................................... 26
7.16. FAST PAGE PROGRAM (FPP) (F2H) ........................................................................................................... 27
7.17. SECTOR ERASE (SE) (20H) .......................................................................................................................... 28
7.18. 32KB BLOCK ERASE (BE) (52H) ................................................................................................................. 29
7.19. 64KB BLOCK ERASE (BE) (D8H) ................................................................................................................ 29
7.20. CHIP ERASE (CE) (60/C7H) .......................................................................................................................... 30
7.21. DEEP POWER-DOWN (DP) (B9H) ............................................................................................................... 30

7.22. RELEASE FROM DEEP POWER-DOWN OR HIGH PERFORMANCE MODE AND READ DEVICE ID (RDI) (ABH) ............. 31
7.23. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ............................................................................ 32
7.24. DUAL I/O READ MANUFACTURE ID/ DEVICE ID (92H) ........................................................................ 33
7.25. QUAD I/O READ MANUFACTURE ID/ DEVICE ID (94H)........................................................................ 33
7.26. READ IDENTIFICATION (RDID) (9FH) ...................................................................................................... 34
7.27. HIGH PERFORMANCE MODE (HPM) (A3H) ............................................................................................. 35
7.28. READ UNIQUE ID (4BH) .............................................................................................................................. 36
7.29. PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................ 36
7.30. PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................ 37
7.31. ERASE SECURITY REGISTERS (44H) ....................................................................................................... 372
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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

7.32. PROGRAM SECURITY REGISTERS (42H) ............................................................................................... 38
7.33. READ SECURITY REGISTERS (48H) ........................................................................................................ 39
7.34. ENABLE RESET (66H) AND RESET (99H) ................................................................................................ 39
7.35. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) .............................................................. 40
8. ELECTRICAL CHARACTERISTICS ................................................................................................................ 45
8.1. POWER-ON TIMING ...................................................................................................................................... 45
8.2. INITIAL DELIVERY STATE ........................................................................................................................... 45
8.3. ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 45
8.4. CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 46
8.5. DC CHARACTERISTICS ................................................................................................................................ 47
8.6. AC CHARACTERISTICS ................................................................................................................................ 50
9. ORDERING INFORMATION.............................................................................................................................. 57
9.1. VALID PART NUMBERS ................................................................................................................................ 57
10. PACKAGE INFORMATION ............................................................................................................................. 60
10.1. PACKAGE SOP8 208MIL ............................................................................................................................. 60
10.2. PACKAGE DIP8 300MIL .............................................................................................................................. 61
10.3. PACKAGE USON8 (3X4MM) ...................................................................................................................... 62
10.4. PACKAGE WSON8 (6*5MM) ....................................................................................................................... 63
11. REVISION HISTORY ......................................................................................................................................... 64

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

1. FEATURES♦ 32M-bit Serial Flash♦ Program/Erase Speed-4096K-byte-256 bytes per programmable page

-Page Program time: 0.6ms typical-Sector Erase time: 50ms typical-Block Erase time: 0.15/0.25s typical-Chip Erase time: 15s typical♦ Standard, Dual, Quad SPI-Standard SPI: SCLK, CS#, SI, SO-Dual SPI: SCLK, CS#, IO0, IO1-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3♦ Flexible Architecture-Sector of 4K-byte-Block of 32/64K-byte♦ High Speed Clock Frequency♦ Low Power Consumption-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s-Quad I/O Data transfer up to 480Mbits/s-Continuous Read With 8/16/32/64-byte Wrap

♦ Software Write Protection-1μA typical stand-by active current-1μA typical power down current♦ Advanced Security Features-128-bit Unique ID for each device-3*1024-Byte Security Registers With OTP Locks-Discoverable parameters (SFDP) register-Write protect all/portion of memory via software-Top or Bottom, Sector or Block selection♦ Cycling endurance♦ Single Power Supply Voltage♦ Data Retention♦ Package Information-Minimum 100,000 Program/Erase Cycles-20-year data retention typical

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

2. GENERAL DESCRIPTIONThe GD25B32C (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports
the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2, and I/O3. The Dual I/Odata is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of
480Mbits/s.

CONNECTION DIAGRAM
CS#

1

8

VCC

CS#

1

SO
(IO1)

2

7

IO3

SO
(IO1)

2

IO2

3

6

SCLK

IO2

VSS

4

5

SI
(IO0)

VSS

Top View

8

VCC

7

IO3

3

6

SCLK

4

5

SI
(IO0)

Top View

8 - LEAD SOP/DIP

8 - LEAD USON/WSONPIN DESCRIPTION
Pin Name

I/O

DescriptionCS#
SO (IO1)I
I/O

Chip Select Input
Data Output (Data Input Output 1)

IO2
VSS
SI (IO0)

I/O

Data Input Output 2

I/O

GroundData Input (Data Input Output 0)

SCLK
IO3
VCC

I
I/O

Serial Clock Input
Data Input Output 3
Power Supply

Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

IO2

StatusRegister

IO3High Voltage
Generators

SCLK
CS#

SPI
Command &Control Logic

Page Address
Latch/Counter

Flash
MemoryColumn Decode And
256-Byte Page Buffer

SI(IO0)SO(IO1)

Byte Address
Latch/Counter

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Write Protect Logic
and Row Decode

BLOCK DIAGRAM

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

3. MEMORY ORGANIZATION
GD25B32C
Each device has

Each block has

Each sector has

Each page has

4M

64/32K

4K

256

bytes

16K

256/128

16

-

pages

1024
64/128

16/8
-

-

-

sectors
blocksUNIFORM BLOCK SECTOR ARCHITECTURE
GD25B32C 64K Bytes Block Sector Architecture
Block

SectorAddress range1023

3FF000H

3FFFFFH

63

-----

-----

-----

62

1008
1007
-----

3F0000H
3EF000H-----

3F0FFFH
3EFFFFH
-----

-----

992
---------

3E0000H---------

3E0FFFH---------

-----

-----

-----

-------------------------------47----02F000H----02FFFFH

2----3231----020000H
01F000H----020FFFH
01FFFFH

1----1615----010000H
00F000H----010FFFH
00FFFFH

0

-----

-----

-----

0

000000H

000FFFH-----

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

4. DEVICE OPERATIONSPI ModeStandard SPI
The GD25B32C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data islatched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPIThe GD25B32C supports Dual SPI operation when using the “Dual Output Fast Read” (3BH), “Dual I/O Fast
Read” (BBH) and “Read Manufacture ID/ Device ID Dual I/O” (92H) commands. These commands allow
data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI
command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPIThe GD25B32C supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast
Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred
to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI andSO pins become bidirectional I/O pins: IO0 and IO1.

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

5. DATA PROTECTION
The GD25B32C provide the following data protection methods:♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:- Power-Up- Write Disable (WRDI)- Write Status Register (WRSR)- Page Program (PP)- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of thememory array that can be read but not change.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
Table1.0 GD25B32C Protected area size (CMP=0)
Status Register Content
BP4 BP3 BP2 BP1 BP0
×
×
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
×
×
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
×
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
×
1
1
1
1
0

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Memory Content
BlocksNONE
63
62 to 63
60 to 63
56 to 63
48 to 63
32 to 6300 to 1
0 to 30 to 70 to 15
0 to 31
0 to 63
63
63
63
63
63
0
0
0
0
0

Addresses
NONE
3F0000H-3FFFFFH
3E0000H-3FFFFFH
3C0000H-3FFFFFH
380000H-3FFFFFH
300000H-3FFFFFH
200000H-3FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
3FF000H-3FFFFFH
3FE000H-3FFFFFH
3FC000H-3FFFFFH
3F8000H-3FFFFFH
3F8000H-3FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH

9Rev.2.0

Density
NONE
64KB
128KB
256KB
512KB
1MB
2MB
64KB
128KB
256KB
512KB
1MB
2MB
4MB
4KB
8KB
16KB
32KB
32KB
4KB
8KB
16KB
32KB
32KB

PortionNONE
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
Top Block
Top Block
Top Block
Top Block
Top BlockBottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Table1.1. GD25B32C Protected area size (CMP=1)
Status Register Content
BP4 BP3 BP2 BP1 BP0
×
×
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
×
×
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
×
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
×
1
1
1
1
0

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Memory Content
BlocksALL
0 to 62
0 to 61
0 to 59
0 to 55
0 to 47
0 to 31
1 to 63
2 to 63
4 to 63
8 to 63
16 to 63
32 to 63
NONE
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63

Addresses
000000H-3FFFFFH
000000H-3EFFFFH
000000H-3DFFFFH
000000H-3BFFFFH
000000H-37FFFFH
000000H-2FFFFFH
000000H-1FFFFFH
010000H-3FFFFFH
020000H-3FFFFFH
040000H-3FFFFFH
080000H-3FFFFFH
100000H-3FFFFFH
200000H-3FFFFFH
NONE
000000H-3FEFFFH
000000H-3FDFFFH
000000H-3FBFFFH
000000H-3F7FFFH
000000H-3F7FFFH
001000H-3FFFFFH
002000H-3FFFFFH
004000H-3FFFFFH
008000H-3FFFFFH
008000H-3FFFFFH

10
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Density
4MB
4032KB
3968KB
3840KB
3584KB
3MB
2MB
4032KB
3968KB
3840KB
3584KB
3MB
2MB
NONE
4092KB
4088KB
4080KB
4064KB
4064KB
4092KB
4088KB
4080KB
4064KB
4064KB

PortionALL
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 3/4
Lower 1/2
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
Upper 3/4
Upper 1/2
NONE
L-1023/1024
L-511/512
L-255/256
L-127/128
L-127/128
U-1023/1024
U-511/512
U-255/256
U-127/128
U-127/128

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

6. STATUS REGISTER
S23

S22

S21

S20

S19

S18

S17

S16

Reserved

DRV1

DRV0

HPF

Reserved

Reserved

Reserved

Reserved

S15

S14

S13

S12

S11

S10

S9

S8

SUS1

CMP

LB3

LB2

LB1

SUS2

QE

SRP1

S7

S6

S5

S4

S3

S2

S1

S0

SRP0

BP4

BP3

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, whenWIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 theinternal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status
Register, Program or Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status Register(WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memoryarea (as defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE)commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware
Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block Protect (BP2,
BP1, and BP0) bits are 0 and CMP=0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0
0

×

1

0

Status Register
Software Protected

Description
The Status Register can be written to after a Write Enablecommand, WEL=1.(Default)

Power Supply Lock-Down(1) Status Register is protected and can not be written to again until
the next Power-Down, Power-Up cycle.
(2)

1
1
One Time Program(2)Status Register is permanently protected and can not be written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile bit in the Status Register that allows Quad operation. The default
value of QE bit is 1 and it cannot be changed, so that the Quad IO2 and IO3 pins are enabled all the time.

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Dual and Quad Serial Flash

GD25B32C

LB3, LB2, LB1 bits.
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) thatprovide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0,
the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register
instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become
read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection
table for details. The default setting is CMP=0.
SUS1, SUS2 bits.
The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing
an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program
Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH)
command as well as a power-down, power-up cycle.
HPF bit.
The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit
sets to 1, it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is
not in High Performance Mode.
DRV1, DRV0 bits
The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0

Driver Strength

00

100%

01
10
11

75% (default)
50%
25%

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant biton the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted into the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, thismight be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last
bit of the command sequence has been shifted in. For the commands of Read, Fast Read, Read Status Register
or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by adata-out sequence. All read instruction can be completed after any bit of the data-out sequence is being shifted
out, and then CS# must be driven high to return to deselected status.
For the commands of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary,otherwise the command is rejected, and is not executed. That means CS# must be driven high when the numberof clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if CS# is driven highat any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name

Byte 1

Byte 2

Write Enable
Write Disable
Volatile SR Write Enable
Read Status Register-1
Read Status Register-2
Read Status Register-3
Write Status Register-1
Write Status Register-2
Write Status Register-3
Read Data
Fast Read
Dual Output Fast Read

06H
04H
50H
05H
35H
15H
01H
31H
11H
03H
0BH
3BH

(S7-S0)(S15-S8)(S23-S16)
S7-S0
S15-S8
S23-S16
A23-A16
A23-A16
A23-A16

Dual I/O Fast Read

BBH

A23-A8 (2)Quad Output Fast Read

6BH

Quad I/O Fast Read

EBH

A23-A16
A23-A0
M7-M0 (4)A23-A0
M7-M0 (4)A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16

Quad I/O Word Fast
Read (7)Page Program
Quad Page Program
Fast Page Program
Sector Erase
Block Erase (32K)
Block Erase (64K)
Chip Erase
Enable Reset
Reset

E7H
02H
32H
F2H
20H
52H
D8H
C7/60H
66H
99H

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Byte 3

Byte 4

Byte 5

Byte 6n-Bytes(continuous)(continuous)(continuous)

A15-A8
A15-A8
A15-A8
A7-A0
M7-M0 (2)A15-A8

A7-A0
A7-A0
A7-A0
(D7-D0) (1)A7-A0

dummy (5)

(D7-D0) (3)dummy (6)

(D7-D0) (3)A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8

A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0

13
Rev.2.0(D7-D0)
dummy
dummy
(Next
byte)
dummy
(Next
byte)
(Next
byte)
D7-D0
D7-D0 (3)
D7-D0

(Next byte) (continuous)(D7-D0) (continuous)
D7-D0 (1) (continuous)(Next byte) (continuous)(D7-D0) (3) (continuous)(Next byte) (continuous)(Next byte) (continuous)
Next byte
Next byte
Next byte

continuous
continuous
continuous

3.3V Uniform Sector
Dual and Quad Serial Flash
Command Name

Byte 1

Byte 2Set Burst with Wrap

77H

dummy (9)W7-W0

Program/Erase Suspend
Program/Erase Resume
Release From DeepPower-Down,
And Read Device ID

75H
7AH

GD25B32C

Byte 3

Byte 4

Byte 5

dummy

dummy

dummy

(DID7DID0)

90H

00H

00H

00H

(MID7MID0)92H

A23-A8Manufacturer/
Device ID by Quad I/O

94H

A23-A0,
M7-M0

Read Identification

9FH

High Performance Mode
Read Serial Flash
Discoverable Parameter
Erase Security
Registers (8)Program Security
Registers (8)Read Security
Registers (8)A3H(MID7MID0)
dummy

5AH

A23-A16

A15-A8

A7-A0

44H

A23-A16

A15-A8

A7-A0

42H

A23-A16

A15-A848H

A23-A16

A15-A8

Release From DeepPower-Down
Deep Power-Down
Manufacturer/
Device ID
Manufacturer/
Device ID by Dual I/O

ABH

Byte 6n-Bytes(continuous)

ABH
B9H(DID7DID0)

A7-A0,(MID7-MID0)
M7-M0(DID7-DID0)
(10)
dummy
(MID7- MID0)(DID7-DID0)(JDID15(JDID7JDID8)
JDID0)dummy
dummy(continuous)(continuous)(continuous)

dummy(D7-D0)(continuous)

A7-A0

D7-D0

D7-D0

continuous

A7-A0

dummy

(D7-D0)(continuous)

NOTE:(1) Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)(2) Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9

A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1(3) Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)

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14
Rev.2.0(continuous)3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C(4) Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3(5) Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)(6) Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)(7) Fast Word Read Quad I/O Data: the lowest address bit must be 0.
(8) Security Registers Address:
Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address.
(9) Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, x, x)(10) Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3, …)Table Of ID Definitions:
GD25B32C
Operation Code

MID7-MID0

ID15-ID8

ID7-ID0

9FH
90H/92H/94H

C8
C8

40

16
15

ABH

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

7.1. Write Enable (WREN)(06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN)
command sequence: CS# goes low → sending the Write Enable command → CS# goes high.
Figure 1. Write Enable Sequence Diagram
CS#
CS#
SCLK
SCLK

0
0

1
1

2
2

3
3

4
4

5
5

6
6

7
7

CommandCommand
06H
06H
High-Z

SI
SI
SO
SO

High-Z

7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable commandsequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset byfollowing condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands.
Figure 2. Write Disable Sequence Diagram
CS#
CS#
SCLK
SCLK

0
0

1
1

2
2

3
3

4
4

5
5

6
6

7
7

CommandCommand
04H
04H
High-ZSI
SI
SO

High-Z

SO

7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change
the system configuration and memory protection schemes quickly without waiting for the typical non-volatile
bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile
Status Register command must be issued prior to a Write Status Register command, and any other commands
cannot be inserted between them. Otherwise, Write Enable for Volatile Status Register will be cleared. The
Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for
the Write Status Register command to change the volatile Status Register bit values.

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Figure 3. Write Enable for Volatile Status Register Sequence Diagram
CS#
CS#
SCLK

0

1

2

3

4

5

6

7

SCLK

0

1

2

3

4

5

6

7

Command(50H)
Command(50H)

SI
SI
SO

High-Z

SO

High-Z

7.4. Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be readat any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to thedevice. It is also possible to read the Status Register continuously. For command code “05H” / “35H” / “15H”,
the SO will output Status Register bits S7~S0 / S15-S8 / S16-S23.
Figure 4. Read Status Register Sequence Diagram

CS#
CS#
SCLK
SCLK

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SI
SI
SO
SO

Command
05HCommandor 35H or 15H
05H or 35H or 15H
High-Z
High-Z

7

Register0/1/2
5Register0/1/2
4 3 2 1

6

7 6
MSB

5

4

MSB

3

2

1

Register0/1/2
0

7

6

0MSB
7 6

5 Register0/1/2
4 3 2 1

0

7

5

0

7

4

3

2

1

MSB

7.5. Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S23, S20, S19, S18, S17, S16, S15, S10, S1and S0 of the Status Register. CS# must be driven high after the eighth of the data byte has been latched in.
If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the selftimed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is inprogress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write
In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. Whenthe cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only.

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Figure 5. Write Status Register Sequence Diagram
CS#
SCLK
CS#
SCLK
SI

5

6

7

8

9 10 11 12 13 14 15

3 4 5
Command678

9 10 11 12 13 14 15
Status Register in

7

6

0

1

2

0

1

2

3

4

01H/31H/11H
CommandSO
SI

01H/31H/11H

1

0

Register in
MSB Status
High-Z
7 6 5 4 3 2 1

0

MSB

SO

4

5

3

2

High-Z7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-induring the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read
Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
CS#
SCLK
CS#
SCLK
SI

Figure 6. Read Data Bytes Sequence Diagram

28 29 30 31 32 33 34 35 36 37 38 39

0

1

2

5

6

7

8

9 10

0

1

2Command
3 4 5

6

7

8

9 10
28 29 30 31 32 33 34 35 36 37 38 39
24-bit address

3

4

03H

23 22 21

3

2

SI
SO

CommandHigh-Z
03H

24-bit address
MSB
23 22 21
3 2

SO

High-Z

MSB

1

0

1 0 7
MSB

6

5

Data Out1
4 3 2 1

0

7

6

5

Data Out1
4 3 2 10

MSB

Data Out2
Data Out2

7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed bya 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Thenthe memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automaticallyincremented to the next higher address after each byte of data is shifted out.

18
18

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Figure 7. Read Data Bytes at Higher Speed Sequence Diagram
CS#
CS#
SCLK
SCLK
SI

0

1

2

5

6

7

8

9 10

0

1

2 3 4 5
Command

6

7

8

9 10
28 29 30 31
24-bit address

CS#
SCLK
SI
SCLK
SI
SO

4

0BH
CommandHigh-Z
0BH

SI
SO
CS#
SO

3

28 29 30 31

23 22 213 2
24-bit address

1

0

23 22 21

1

0

3

2

High-Z32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
34 35 36
32 33Dummy
Byte37 38 39 40 41 42 43 44 45 46 47
76

5 4 3 2
Dummy Byte

1

0

7

6

5

1

0

4

3

2

SO

Data Out1
7 6 5 4 3 2
MSB
Data Out1
7 6 5 4 3 2
MSB

1

0

1

0

Data Out2
7 6 5MSB Data Out2
7 6
MSB

5

7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cyclefrom SI and SO. The command sequence is shown in followed Figure 8. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shiftedout.
CS#
Figure 8. Dual Output Fast Read Sequence Diagram
CS#
SCLK
SCLK
SI
SI
SO
CS#
SO
CS#
SCLK
SI
SCLK
SI
SO
SO

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0

1

2

5

6

7

8

9 10

0

1

2 3 4 5
Command

6

7

8

9 10
28 29 30 31
24-bit address

3

4

3BH
CommandHigh-Z
3BH

28 29 30 31

23 22 213 2
24-bit address

1

0

23 22 21

1

0

2

3

High-Z32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
32 33Dummy
34 35 Clocks
36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks

6

4

2

0

6

4

2

0

Data Out2
Data Out1
76 54 32 10 76 54 32 10
MSB
Data Out2
Data Out1 MSB
7 5 3 1 7 5 3 1
MSB
MSB

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6
7
7

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cyclefrom IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure 9. The first byte addressedcan be at any location. The address is automatically incremented to the next higher address after each byte ofdata is shifted out.
Figure 9. Quad Output Fast Read Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

8

7

9 10

24-bit address

Command
IO0
IO1

High-Z
High-Z

IO3

High-Z

SCLK

3

23 22 21

6BH

IO2

CS#

28 29 30 31

2

1

0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks

IO0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

IO3

7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4

7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cyclefrom SI and SO. The command sequence is shown in followed Figure10. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shiftedout.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)= (1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require theBBH command code. The command sequence is shown in followed Figure11. If the “Continuous Read Mode”
bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning tonormal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuingnormal command.

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3.3V Uniform Sector
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GD25B32C

Figure 10. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
CS#
0
0

SCLK
SCLK

1
1

2
2

3
3

4
4

5
5

6
6

7
7

CommandCommand
BBH
BBH

SI(IO0)SI(IO0)SO(IO1)
SO(IO1)
CS#
CS#
SCLK
SCLK

8
8

9
16 17
17 18
18 19
19 20
20 21
21 22
22 23
23
9 10
10 11
11 12
12 13
13 14
14 15
15 16

6
6

4
4

0
0

6
6

4
4

0
0

6
6

4
4

2
2

0
0

6
6

7
7

5
1
3 1
5 3
A23-16
A23-16

7
7

5
1
3 1
5 3
A15-8
A15-8

7
7

5
5 3
3
A7-0
A7-0

1
1

7
7 5
5
Dummy
M7-4
M7-4 Dummy

2
2

2
2

23
23 24
24 25
25 26
26 27
27 28
28 29
29 30
30 31
31 32
32 33
33 34
34 35
35 36
36 37
37 38
38 39
39

SI(IO0)SI(IO0)

6
6

4
4

0
0

6
6

4
4

0
0

6
6

4
4

0
0

6
6

4
4

0
0

6
6

SO(IO1)
SO(IO1)

7
7

5
5 3
3 1
1
Byte1
Byte1

7
7

5
5 3
3 1
1
Byte2
Byte2

7
7

5
5 3
3 1
1
Byte3
Byte3

7
7

5
5 3
3 1
1
Byte4
Byte4

7
7

2
2

2
2

2
2

2
2

Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4 = (1, 0))
CS#
CS#
SCLK
SCLK

CS#
CS#
SCLK
SCLK

0
0

1
1

2
2

3
3

4
4

5
5

6
6

7
7

8
8

9
15
9 10
10 11
11 12
12 13
13 14
14 15

6
6

4
4

2
2

0
0

6
6

4
4

2
2

0
0

6
6

4
4

2
2

0
0

6
6

7
7

5
1
3 1
5 3
A23-16
A23-16

7
7

5
1
3 1
5 3
A15-8
A15-8

7
7

5
3
5 3
A7-0
A7-0

1
1

7
5
7 5
M7-4
M7-4 Dummy

4
4

Dummy

15
15 16
16 17
17 18
18 19
19 20
20 21
21 22
22 23
23 24
24 25
25 26
26 27
27 28
28 29
29 30
30 31
31

SI(IO0)SI(IO0)

6
6

4
4

0
0

6
6

4
4

0
0

6
6

4
4

0
0

6
6

4
4

0
0

6
6

SO(IO1)
SO(IO1)

7
7

5
1
5 3
3 1
Byte1
Byte1

7
7

5
1
3 1
5 3
Byte2
Byte2

7
7

5
1
3 1
5 3
Byte3
Byte3

7
7

5
1
5 3
3 1
Byte4
Byte4

7
7

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2
2

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3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

7.11. Quad I/O Fast Read (EBH)The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock
by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed
Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be
set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)= (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require theEBH command code. The command sequence is shown in followed Figure13. If the “Continuous Read Mode”
bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning
to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuingnormal command.
Figure 12. Quad I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
CS#

0
0

1
1

2
2

3
3

4
4

5
5

6
6

7
7

8
8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

4
4

0
0

4
4

0
0

4
4

0
0

4
4

0
0

4
4

0
0

4
4

0
0

4
4

IO1
IO1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

IO2
IO2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

7 3 7 37 3 7 3
Byte1 Byte2
Byte1 Byte2

7
7

SCLK
SCLK

CommandCommand
EBH
EBH

IO0
IO0

IO3
IO3

7 3 7 3 7 3 7 3
7 3 7 3 7 3 7 3
A23-16 A15-8 A7-0 M7-0
A23-16 A15-8 A7-0 M7-0

Dummy
Dummy

Figure 13. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0))
CS#
CS#

8
8

9 10 11 12 13 14 15
9 10 11 12 13 14 15

0
0

1
1

2
2

3
3

4
4

5
5

6
6

7
7

IO0
IO0

4
4

0
0

4
4

0
0

4
4

0
0

4
4

0
0

4
4

0
0

4
4

0
0

4
4

IO1
IO1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

1
1

5
5

IO2
IO2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

2
2

6
6

7 3 7 37 3 7 3
Byte1 Byte2
Byte1 Byte2

7
7

SCLK
SCLK

IO3
IO3

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7 3 7 3 7 3 7 3
7 3 7 3 7 3 7 3
A23-16 A15-8 A7-0 M7-0
A23-16 A15-8 A7-0 M7-0

22Rev.2.0

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Dummy

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burstwith Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable ordisable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, thedata being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14.
The first byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set toenable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)= (1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not
require the E7H command code. The command sequence is shown in followed Figure15. If the “Continuous
Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus
returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before
issuing normal command.
Figure 14. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#

0

1

2

3

4

5

6

7

IO0

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

SCLK

A23-16 A15-8 A7-0 M7-0

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23
Rev.2.08

9 10 11 12 13 14 15

Dummy

Byte1 Byte2

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Figure 15. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
8

9 10 11 12 13 14 15

0

1

2

3

4

5

6

7

IO0

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

SCLK

A23-16 A15-8 A7-0 M7-0

Dummy

Byte1 Byte2

Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set
Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable
or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, thedata being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
7.13. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word
Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI
mode.
The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send
24 dummy bits → Send 8 bits “Wrap bits” → CS# goes high.
W6, W5

W4=0

W4=1 (default)
Wrap Around
Wrap Length

Wrap Around

Wrap Length

0, 0

Yes

8-byte

No

N/A

0, 1
1, 0
1, 1

Yes
Yes
Yes

16-byte32-byte64-byte

No
No
No

N/A
N/A
N/A

If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and“Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within
any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
command should be issued to set W4=1.

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3.3V Uniform Sector
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GD25B32C

Figure 16. Set Burst with Wrap Sequence Diagram
CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

x

x

x

x

x

x

4

x

IO1

x

x

x

x

x

x

5

x

IO2

x

x

x

x

x

x

6

x

IO3

x

x

x

x

x

x

x

x

SCLK

Command
IO0

77H

W6-W4

7.14. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Programcommand.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, threeaddress bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,all transmitted data that goes beyond the end of the current page are programmed from the start address of thesame page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for theentire duration of the sequence. The Page Program command sequence: CS# goes low → sending Page Programcommand → 3-byte address on SI → at least 1 byte data on SI → CS# goes high. The command sequence isshown in Figure17. If more than 256 bytes are sent to the device, previously latched data are discarded and thelast 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes
are sent to device, they are correctly programmed at the requested addresses without having any effects on theother bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latchedin; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register may be read to check the value of the Write inProgress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1, and BP0) is not executed.

25

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3.3V Uniform Sector
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GD25B32C

Figure 17. Page Program Sequence Diagram
CS#
5

6

7

8

24-bit address

02H

23 22 21

3

2

Data Byte 1
0 7

1

MSB

6

5

4

3

2

1

2078

CommandSI

28 29 30 31 32 33 34 35 36 37 38 39

9 10

2079

4

2077

3

2076

2

2075

1

2074

0

SCLK

1

0

0

2073

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2072

MSB

CS#

7

6

SCLK
SI

Data Byte 3

Data Byte 2
7

6

5

4

3

MSB

2

1

0 7

6

5

4

3

2

MSB

Data Byte 256
1

0

5

4

3

2

MSB

7.15. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3.
To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit before sending thePage Program command. The quad Page Program command is entered by driving CS# Low, followed by thecommand code (32H), three address bytes and at least one data byte on IO pins.
The command sequence is shown in Figure18. If more than 256 bytes are sent to the device, previously latcheddata are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.
While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of theWrite In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1, and BP0) is not executed.

26

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3.3V Uniform Sector
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GD25B32C

Figure 18. Quad Page Program Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

8

7

9 10

Command24-bit address

0

4

0

4

0

4

0

5

1

5

1

5

1

5

1

IO2

6

2

6

2

6

2

6

2

IO3

7

3

7

3

7

3

7

3

537

542

543

3

23 22 2132H2

Byte1 Byte2
0 4

538

IO0

28 29 30 31 32 33 34 35 36 37 38 39

1

MSB

IO1

540

541

Byte11 Byte12

Byte253

IO0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

5

1

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

6

2

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

7

3

SCLK

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

536

539

CS#

Byte256

7.16. Fast Page Program (FPP) (F2H)
The Fast Page Program (FPP) command is used to program the memory. A Write Enable (WREN) commandmust previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Programcommand.
The Fast Page Program (FPP) command is entered by driving CS# Low, followed by the command code, threeaddress bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,all transmitted data that goes beyond the end of the current page are programmed from the start address of thesame page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for theentire duration of the sequence.
The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address
on SI → at least 1 byte data on SI → CS# goes high.
The command sequence is shown in Figure19. If more than 256 bytes are sent to the device, previously latcheddata are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Fast Page Program (FPP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when

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3.3V Uniform Sector
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GD25B32C

it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit isreset.
A Fast Page Program (FPP) command is not executed when it is applied to a page protected by the Block
Protect (BP4, BP3, BP2, BP1, BP0).
Figure 19. Fast Page Program Sequence Diagram
CS#

8

7

24-bit address

2

0 7

6

5

4

3

1

0 7

6

5

4

3

2

1

1

0

1

0

0

7

6

7

6

MSB

5

4

3

2

Data Byte 256
1

MSB

MSB

2

MSBData Byte 256

Data Byte 3

Data Byte 2

7 6 (20H)
5 4 3
7.17. Sector Erase (SE)2078

Data Byte 2

Data Byte 1

2079

MSB Data Byte 3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
48 49 50 51 52 53 54 55
40 41 42 43 44 45 46 47MSB
MSB

SI

1

2078

2

3

2076

23 22 21

2077

54 55
52 53
40 41 42 43Command
44 45 46 47 48 49 50 5124-bit
address
F2H

2075

23 22 217 8 9 10
MSB

6

2074

F2H
4 5

2075

3

2073

2

Data Byte 1

3 2 1 0 7 6 5 4 3 2 1 0
32 33 34 35 36 37 38 39
28 29 30 31
MSB

2074

1

28 29 30 31 32 33 34 35 36 37 38 39

9 10

2077

6

2076

5

2079

SCLK

4

2072

0

SCLK
CS#

SI
CS#

3

Command

SI
CS#

SI
SCLK

2

2073

1

2072

0

SCLK

0

4

5

MSB

3

2

The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE)command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any addressinside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire
duration of the sequence.
The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on
SI → CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bitof the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon
as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector
Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit.
The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase(SE) command appliedCS#
to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (seeTable1&1a) is not executed.
29 30 310 1 2 3 4 5 6 7 8 9
SCLK

Figure 20. Sector Erase Sequence Diagram

SCLK
SI

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24 Bits Address

Command

SI
CS#

20H
0

1

2

3

4

5

6

23 22
MSB
7 8 9

1

0

29 30 31

24 Bits Address

Command

20H

2

23 22
MSB

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7.18. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte
address on SI → CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write inProgress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit isreset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 21. 32KB Block Erase Sequence Diagram
CS#
SCLK
CS#
SI
SCLK

0

1

2

5

6

7

8

9

0

1

2Command
3 4 5

6

7

8

924 Bits Address
29 30 313

452H
CommandSI

52H

7.19. 64KB Block Erase (BE) (D8H)

29 30 31

23 22
2 1
MSB
24 Bits Address

0

23 22
MSB

0

2

1

The 64KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte
address on SI → CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write inProgress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit isreset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
CS#

SCLK
CS#
SI
SCLK
SI

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Figure 22. 64KB Block Erase Sequence Diagram
0

1

2

5

6

7

8

9

0

1

2Command
3 4 5

6

7

8

924 Bits Address
29 30 313

4

D8H
Command
D8H

29 30 31

23 22
2 1
MSB
24 Bits Address

0

1

0

23 22
MSB

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7.20. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) commandmust previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command isentered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The
command sequence is shown in Figure23. CS# must be driven high after the eighth bit of the command code
has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the selftimed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all
Block Protect (BP2, BP1, and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors
are protected.
Figure 23. Chip Erase Sequence Diagram
CS#
SCLK
SI

0

1

2

3

4

5

6

7

Command
60H or C7H

7.21. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption
mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while
the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands.
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle
currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode canonly be entered by executing the Deep Power-Down (DP) command. Once the device has entered the DeepPower-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device
ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read
Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by thecommand code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS#
goes high. The command sequence is shown in Figure24. CS# must be driven high after the eighth bit of thecommand code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon
as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the DeepPower-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.

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Figure 24. Deep Power-Down Sequence Diagram
CS#
SCLK
CS#
SI
SCLK

tDP

0 1 2 3 4 5 6 7
CommandStand-by mode Deep Power-down modetDP

0 1 2 B9H
3 4 5 6 7
CommandSI

Stand-by mode Deep Power-down mode

B9H

7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose
command. It can be used to release the device from the Power-Down state or High Performance Mode or obtain
the devices electronic identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued bydriving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure25.
Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will
resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1
time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated bydriving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure26.
The Device ID value for the GD25B32C is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is thesame as previously described, and shown in Figure26, except that after CS# is driven high it must remain highfor a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal
operation and other command will be accepted. If the Release from Power-Down / Device ID command isissued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored andCS#will not have any effects on the current cycle.
0

1

2

3

4

5

6

7

t RES1

6

7

t RES1Figure 25. SCLK
Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
SI
SCLK
SI

Command
0

1

2 ABH
3 4

5

Deep Power-down mode
CommandABH
Deep Power-down mode

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Figure 26. Release Power-Down/Read Device ID Sequence Diagram
CS#
CS#
0
0

1
1

2
2

3
3

4
4

5
5

6
6

7
7

8
8

29
38
32 33
33 34
34 35
35 36
36 37
37 38
29 30
30 31
31 32

9
9

SCLK
SCLK
SI
SI

SO
SO

tt RES2
RES2

3
3 DummyDummy Bytes
Bytes
23
22
2
23 22
1
2 1
MSB
MSB

CommandCommand
ABH
ABH

High-Z
High-Z

0
0

MSB
MSB

7
7

6
6

DeviceDevice ID
ID
5
2
3 2
4 3
5 4

1
1

0
0

Deep
Deep Power-downPower-down Mode
Mode Stand-by
Stand-by Mode
Mode

7.23. Read Manufacture ID/Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 27. Read Manufacture ID/Device ID Sequence Diagram
CS#
CS#
0
0

SCLK
SCLK

2
2

3
3

4
4

5
5

6
6

7
7

8
8

23
23 22
22 21
21

90H
90H
High-Z
High-Z

SO
SO

32
32

9
9 10
10

28
28 29
29 30
30 31
31

24-bit24-bit address
address

CommandCommand

SI
SI

CS#
CS#

1
1

3
3

2
2

33
40 41
46 47
47
41 42
42 43
43 44
44 45
45 46
38 39
39 40
33 34
34 35
35 36
36 37
37 38

SCLK
SCLK
SI
SI
SO
SO

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7
7 6
6
MSB
MSB

Manufacturer
Manufacturer ID
ID
5
1
2 1
3 2
4 3
5 4

0
7 6
6
0 7
MSB
MSB

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ID
3
4
5
2
5 4 3 2

1
1

0
0

1
1

0
0

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GD25B32C

7.24. Dual I/O Read Manufacture ID/Device ID (92H)
The Dual I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down /Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID bydual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure28. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 28. Read Manufacture ID/Device ID Dual I/O Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

6

4

2

0

6

5

3

1

7

CommandSI(IO0)92H

SO(IO1)

7

A23-16

4

2

0

6

5

3

1

7

A15-8

4

2

0

6

5

3

1

7

A7-0

4

2

0

5

3

1

M7-0

CS#
SCLK

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SI(IO0)

6

SO(IO1)

7

4

2

0

6

4

2

0

6

5

3

1

7

5

3

1

7

MFR ID

Device ID

4

2

0

6

4

2

0

6

5

3

1

7

5

3

1

7

MFR ID(Repeat)Device ID(Repeat)

4

2

0

6

4

2

0

5

3

1

7

5

3

1

MFR ID(Repeat)Device ID(Repeat)7.25. Quad I/O Read Manufacture ID/Device ID (94H)
The Quad I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down /Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID byquad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a
24-bit address (A23-A0) of 000000H , and 4 dummy clocks. After which, the Manufacturer ID and the Device
ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure29. If the
24-bit address is initially set to 000001H, the Device ID will be read first.

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Figure 29. Read Manufacture ID/Device ID Quad I/O Sequence Diagram
CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

4

0

4

0

4

0

4

0

4

0

4

0

IO1

5

1

5

1

5

1

5

1

5

1

5

1

IO2

6

2

6

2

6

2

6

2

6

2

6

2

IO3

7

3

7

3

7

3

7

3

7

3

7

3

SCLK

Command

IO0

94H

A23-16 A15-8 A7-0 M7-0

CS#

Dummy

MFR ID DID

24 25 26 27 28 29 30 31

SCLK

IO0

4

0

4

0

4

0

4

0

IO1

5

1

5

1

5

1

5

1

6

2

6

2

6

2

6

2

7

3

7

3

7

3

7

3

IO2
IO3

MFR ID DID MFR ID DID(Repeat)(Repeat)(Repeat)(Repeat)

7.26. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by
two bytes of device identification. The device identification indicates the memory type in the first byte, and thememory capacity of the device in the second byte. The Read Identification (RDID) command while an Eraseor Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read
Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted
in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data
Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in
Figure30. The Read Identification (RDID) command is terminated by driving CS# to high at any time during
data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, thedevice waits to be selected, so that it can receive, decode and execute commands.

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Figure 30. Read Identification ID Sequence Diagram
CS#
CS#
SCLK
SCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

9FH
9FH
CommandCommand

SI
SI
SO
SO

MSB
MSB

CS#
CS#
SCLK
SCLK

Manufacturer ID
Manufacturer ID
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SI
SI
SO
SO

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Capacity
Memory TypeCapacity
Memory TypeMSB
JDID7-JDID0
JDID15-JDID8MSBMSBJDID15-JDID8MSB JDID7-JDID0

7.27. High Performance Mode (HPM) (A3H)
The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fR and fC2 in AC Electrical Characteristics). This command allows precharging of internal charge pumps so the voltages required for accessing the flash memory array are readily
available. The command sequence: CS# goes low → Sending A3H command → Sending 3-dummy byte →CS# goes high. See Figure31. After the HPM command is executed, the device will maintain a slightly higher
standby current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH)
can be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will
also release the device from HPM mode back to standard SPI standby state.
Figure 31. High Performance Mode Sequence Diagram
CS#
CS#
SCLK
SCLK
SI
SI
SO
SO

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0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9CommandCommand
A3H
A3H

29 30 31
29 30 313 Dummy Bytes
3 Dummy Bytes
2 1 0
23 22
2 1 0
23 22
MSB
MSB

t HPM
t HPM

High Performance ModeHigh Performance Mode

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7.28. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device.
The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of asystem.
The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command → 3-Byte
Address (000000H) → Dummy Byte → 128bit Unique ID Out → CS# goes high.
Figure 32. Read Unique ID Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

7

9 10

28 29 30 31

24-bit address(000000H)
23 22 21
3 2

Command

SI

8

4BH

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI

Dummy Byte
7

6

5

4

3

SO

2

1

0
7 6
MSB

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

7.29. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/
block erase operation and then read data from any other sector or block. The Write Status Register command(01H/31H/11H) and Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H,
D8H, C7H, 60H) and Page Program command (02H / 32H) are not allowed during Program/Erase suspend.
Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum oftime of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is ongoing. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by thedevice. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1
immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device andrelease the suspend state. The command sequence is show below.

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Figure 33. Program/Erase Suspend Sequence Diagram
CS#
SCLK
CS#
SI
SCLK

0

1

2

5

6

7

tSUS

0

1

Command2 3 4 5
75H

6

7

tSUS

3

4

High-Z
Command

SO
SI

75H

Accept read command

High-ZSO

Accept read command

7.30. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation
after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if
the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register
will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or
Block will complete the erase operation or the page will complete the program operation. The Program/Erase
Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in
Figure34.
CS#

Figure 34. Program/Erase Resume Sequence Diagram

SCLK
CS#
SI
SCLK
SO
SI

0

1

2

5

6

7

0

1

Command2 3 4 5
7AH

6

7

3

4

Command

Resume Erase/Program

7AH

SO

Resume Erase/Program

7.31. Erase Security Registers (44H)
The GD25B32C provides three 1024-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other important
information separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command→ CS# goes high. The command sequence is shown in Figure35. CS# must be driven high after the eighth bitof the command code has been latched in; otherwise the Erase Security Registers command is not executed. As
soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated.
While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of theWrite in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP
protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; theErase Security Registers command will be ignored.

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Address

A23-A16

A15-A12

A11-A10

A9-A0

Security Register #1

00H

0001

00

Don’t care

Security Register #2

00H

0010

00

Don’t care

Security Register #3

00H

0011

00

Don’t care

Figure 35. Erase Security Registers command Sequence Diagram
CS#
0

SCLK
CS#

1

0

SCLK
SI

1

2

3

4

5

6

Command3 4 5 6
44H

2

7

7

CommandSI

8

929 30 31

24 Bits Address
8 9
29 30 31
2 1 0
23 22
MSB
24 Bits Address
2

23 22
MSB

44H

7.32. Program Security Registers (42H)

10

The Program Security Registers command is similar to the Page Program command. It allows from 1 to 1024
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is inprogress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write inProgress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address

A23-A16

A15-A12

A11-A10

A9-A0

Security Register #1
Security Register #2

00H
00H

0001
0010

00
00

Byte Address
Byte Address

Security Register #3

00H

0011

00

Byte AddressCS#

Figurecommand
Diagram
35 36 37 38 39
1 2Program
3 4 5Security
6 7 8Registers
9 10
28 29 30Sequence
31 32 33 34
0 36.

SCLK
CS#
2 Command
3 4 5 635 Byte36 37
9 1024-bit address
28 29 30 31 32 33 34
1 38 39
Data
1

3

2

5

23 22 213 2 1 0 7
42H
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
MSB
MSB

6

5

2075

4

2076

2077

3

2

0 7

1

MSB

2072

24-bit address

2073

2074

2075

2076

2077

2078

2079

1

52 53
51 Byte
44 45
43Byte40 41 42
3 54 55
Data
2 46 47 48 49 50
Data
0

7

6

5

4

3

2

1

0

SCLK
SI

MSB

7

6

1

2

3

4

5

6

7

MSB

Data Byte 2
5MSB

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4

3

2

1

0 7

6

1

2

3

4

5

6

0 7

MSB

Data Byte 3
5

4

3

2

1

0

7
MSB

MSB

38
Rev.2.0

6

Data Byte 256

Data Byte 256
50Data Byte 1

2072

2073

MSB

Command

CS#

CS#
SCLK

2

3

4

6

2074

8

23 22 21

42H

SI

SI

7

2079

1

2078

0

SCLK
SI

4

3

2

1

0

0

3.3V Uniform Sector
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GD25B32C

7.33. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command I is followed by a
3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Thenthe memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automaticallyincremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches thelast byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high.
Address

A23-A16

A15-A12

A11-A10

A9-A0

Security Register #1

00H

0001

00

Byte Address

Security Register #2
Security Register #3

00H
00H

0010
0011

00
00

Byte Address
Byte Address

Figure 37. Read Security Registers command Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

8

7

28 29 30 31

24-bit address

Command

SI

9 10

48H

3

23 22 212

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI

Dummy Byte
7

6

5

4

SO

3

2

1

0
7 6
MSB

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

7.34. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return
to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write
Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read
Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low → Sending Enable Reset command → CS#
goes high → CS# goes low → Sending Reset command → CS# goes high. Once the Reset command is acceptedby the device, the device will take approximately tRST / tRST_E to reset. During this period, no command
will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program
operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit
and the SUS bit in Status Register before issuing the Reset command sequence.

39

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Figure 38. Enable Reset and Reset command Sequence Diagram
CS#
CS#
SCLK
SCLK
SI

0

1

2

5

6

7

0

1

2

5

6

7

0

1

2 3 4 5
Command

6

7

0

1

2 3 4 5
Command

6

7

3

4

66H
Command

SI
SO

3

4

99H
Command

66H

99H

High-Z
High-ZSO

7.35. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing thefunctional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDECStandard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216.
Figure 39.CS#
Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
SCLK
SCLK

0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

SI
SI
SO

24-bit address

5AH
Command23 22 2124-bit address
3 2

1

0

5AH
High-Z23 22 211

0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
72
6 Dummy5 4 3Byte

1

0

SI

7

6

1

0

SO

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2

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI
SO

3

High-Z

SO
CS#
CS#
SCLK

Command

5

4

3

2

Data Out1
Data Out2
4 Out13 2 1 0 7 6
7 6 5Data
5 Out2Data
MSB
MSB
7 6 5 4 3 2 1 0 7 6 5
MSB
MSB

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Dual and Quad Serial Flash

GD25B32C

Table3. Signature and Parameter Identification Data Values
Description

Comment

53H
46H
44H
50H
00H
01H
01H

53H
46H
44H
50H
00H
01H
01H

07H

31:24

FFH

FFH

08H

07:00

00H

00H

Start from 0×00H

09H

15:08

00H

00H

Start from 0×01H

0AH

23:16

01H

01H

How many DWORDs
in the Parameter Table

0BH

31:24

09H

09H

0CH
0DH
0EH

07:00
15:08
23:16

30H
00H
00H

30H
00H
00H

0FH

31:24

FFH

FFH

10H

07:00

C8H

C8H

Start from 0×00H

11H

15:08

00H

00H

Start from 0×01H

12H

23:16

01H

01H

How many DWORDs in the
Parameter Table

13H

31:24

03H

03H

14H
15H
16H

07:00
15:08
23:16

60H
00H
00H

60H
00H
00H

17H

31:24

FFH

FFH

SFDF Minor Revision Number
SFDF Major Revision Number
Number of Parameters HeadersStart from 00H
Start from 01H
Start from 00H
Contains 0×FFH and
can never be changed
00H: It indicates a JEDEC
specified header

Parameter Table Minor Revision
NumberParameter Table Major Revision
NumberParameter Table Length(in double word)
Parameter Table Pointer (PTP)
UnusedID Number(GigaDevice Manufacturer ID)
Parameter Table Minor Revision
NumberParameter Table Major Revision
NumberParameter Table Length(in double word)

Fist address of JEDEC Flash
Parameter Table
Contains 0×FFH and
can never be changed
It is indicates GigaDevice
manufacturer ID

Parameter Table Pointer (PTP)

Fist address of GigaDevice
Flash Parameter Table

UnusedContains 0×FFH and
can never be changed

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Data

07:00
15:08
23:16
31:24
07:00
15:08
23:16

Fixed:50444653H

ID number (JEDEC)

Data

00H
01H
02H
03H
04H
05H
06H

SFDP Signature

UnusedAdd(H) DW Add(Byte)(Bit)

41
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Table4. Parameter Table (0): JEDEC Flash Parameter Tables
Description

Comment

00: Reserved;
01: 4KB erase;
Block/Sector Erase Size
10: Reserved;
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
Write Enable Instruction
Requested for Writing to Volatile 1: Volatile status bit(BP status register bit)
Status Registers

Add(H) DW Add(Byte)
(Bit)

Data

Data

01:00

01b

02

1b

03

0b

0: Use 50H Opcode,
Write Enable Opcode Select for 1: Use 06H Opcode,
Writing to Volatile Status
Note: If target flash status
Registers
register is Nonvolatile, then bits
3 and 4 must be set to 00b.

04

0bContains 111b and can never bechanged

07:05

111b

15:08
16

20H
1b

18:17

00b

19

0b

20
21
22
23
31:24
31:00

1b
1b
1b
1b
FFH
FFH
01FFFFFFH

04:00

00100b

07:05

010b

15:08

EBH

20:16

01000b

23:21

000b

31:24

6BH

04:00

01000b

07:05

000b

15:08

3BH

Unused4KB Erase Opcode(1-1-2) Fast Read
Address Bytes Number used inaddressing flash array
Double Transfer Rate (DTR)
clocking(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
UnusedUnusedFlash Memory Density(1-4-4) Fast Read Number of
Wait states(1-4-4) Fast Read Number ofMode Bits(1-4-4) Fast Read Opcode(1-1-4) Fast Read Number of
Wait states(1-1-4) Fast Read Number ofMode Bits(1-1-4) Fast Read Opcode(1-1-2) Fast Read Number of
Wait states(1-1-2) Fast Read Number ofMode Bits(1-1-2) Fast Read Opcode

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0=Not support, 1=Support
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support

00000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support
00000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support
00000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support

30H

31H

32H

33H
37H:34H
38H
39H
3AH
3BH
3CH
3DH

42
Rev.2.0

E5H

20H

F1H

44H
EBH
08H
6BH
08H
3BH

3.3V Uniform Sector
Dual and Quad Serial Flash
Description(1-2-2) Fast Read Number of
Wait states(1-2-2) Fast Read Numberof Mode Bits
(1-2-2) Fast Read Opcode(2-2-2) Fast Read
Unused(4-4-4) Fast Read
UnusedUnusedUnused(2-2-2) Fast Read Number of
Wait states(2-2-2) Fast Read Number ofMode Bits(2-2-2) Fast Read Opcode
Unused(4-4-4) Fast Read Number of
Wait states(4-4-4) Fast Read Number ofMode Bits(4-4-4) Fast Read Opcode
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector Type 4 erase Opcode

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Comment
00000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support
0=not support; 1=support
0=not support; 1=support

00000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support

00000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support
Sector/block size=2^N bytes
0×00b: this sector type don’t exist
Sector/block size=2^N bytes
0×00b: this sector type don’t exist
Sector/block size=2^N bytes
0×00b: this sector type don’t exist
Sector/block size=2^N bytes
0×00b: this sector type don’t exist

43
Rev.2.0

GD25B32C
Add(H) DW Add(Byte)
(Bit)

Data

Data

20:16

00010b

23:21

010b

31:24
00
03:01
04
07:05
31:08
15:00

BBH
0b
111b
0b
111b
0×FFH
0×FFH

20:16

00000b

23:21

000b

31:24
15:00

FFH
0×FFH

20:16

00000b

23:21

000b

4BH

31:24

FFH

FFH

4CH

07:00

0CH

0CH

4DH

15:08

20H

20H

4EH

23:16

0FH

0FH

4FH

31:24

52H

52H

50H

07:00

10H

10H

51H

15:08

D8H

D8H

52H

23:16

00H

00H

53H

31:24

FFH

FFH

3EH
3FH
40H
43H:41H
45H:44H
46H
47H
49H:48H
4AH

42H
BBH
EEH
0×FFH
0×FFH
00H
FFH
0×FFH
00H

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Table5. Parameter Table (1): GigaDevice Flash Parameter Tables
Description
Vcc Supply Maximum Voltage

Vcc Supply Minimum Voltage
HW Reset# pin
HW Hold# pin
Deep Power Down Mode
SW Reset
SW Reset Opcode
Program Suspend/Resume
Erase Suspend/Resume
UnusedWrap-Around Read mode
Wrap-Around Read mode
OpcodeComment
2000H=2.000V
2700H=2.700V
3600H=3.600V
1650H=1.650V
2250H=2.250V
2350H=2.350V
2700H=2.700V
0=not support; 1=support
0=not support; 1=support
0=not support; 1=support
0=not support; 1=support
Should be issue Reset
Enable(66H) before Reset cmd.
0=not support; 1=support
0=not support; 1=support

DW Add
(Bit)

Data

Data

61H:60H

15:00

3600H

3600H

63H:62H

31:16

2700H

2700H

00
01
02
03
65H:64H

44
Rev.2.0

11:04
12
13
14
15

0=not support; 1=support

08H: support 8B wrap-aroundread
Wrap-Around Read data length 16H: 8B & 16B
32H: 8B & 16B & 32B
64H: 8B & 16B & 32B & 64B
Individual block lock0=not support; 1=support
Individual block lock bit
0=Volatile; 1=Nonvolatile(Volatile/Nonvolatile)
Individual block lock Opcode
Individual block lock Volatile
0=protect; 1=unprotect
protect bit default protect status
Secured OTP
0=not support; 1=support
Read Lock0=not support; 1=support
Permanent Lock0=not support; 1=support
UnusedUnusedhttp://www.elm-tech.com

Add(H)(Byte)0b0b1b1b1001 1001b
F99CH
(99H)
1b
1b
1b
1b

66H

23:16

77H

77H

67H

31:24

64H

64H

00

0b

01

0b

09:02

FFH

10

0b

EBFCH

11
12
13
15:14
31:16

1b
0b
1b
11b
FFFFH

FFFFH

6BH:68H

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Vcc(max)

Chip Selection is not allowed
Vcc(min)Vcc(max)tVSL

Chip Selection is not allowed

Device is fully
accessible

VWI
Vcc(min)

Device is fully
accessible Time

tVSL
VWI

Table6. Power-Up Timing And Write Inhibit Threshold
SymbolParameter

Time

Min

tVSL

VCC(min) To CS# Low

1.8

VWI

Write Inhibit Voltage VCC(min)

1.5

Max

Unit
ms

2.5

V

8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status
Register bits are set to 0, except DRV0 bit (S21) and QE bit (S9) are set to 1.
8.3. ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Operating Temperature

20ns
Vss

Unit

-40 to 85-40 to 105°C-40 to 125-65 to 150-0.6 to VCC+0.4-2.0 to VCC+2.0

Storage Temperature
Applied Input/Output Voltage
Transient Input/Output Voltage (note: overshoot)
VCC

Value

-0.6 to 4.2

20ns

20ns

Figure 39. Maximum Negative/positive
Vcc + 2.0V Overshoot Diagram

Maximum Negative Overshoot Waveform

Maximum Positive Overshoot Waveform

Vss-2.0V

Vcc

20ns 20ns 20ns

20ns

Vss

45

20ns20ns

Vcc + 2.0V

Vss-2.0V
Vcc

20ns

20ns

45

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45
Rev.2.0

20ns

°C
V
V
V

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

8.4. CAPACITANCE MEASUREMENT CONDITIONS
SymbolParameter

Min

Typ

Max

Unit

Conditions

CIN

Input Capacitance6

pF

VIN=0V

COUT

Output Capacitance8pF

VOUT=0V

5

pF
ns

Input Pulse Voltage

0.1VCC to 0.8VCC

V

Input Timing Reference Voltage

0.2VCC to 0.7VCC
0.5VCCV
V

Load Capacitance
Input Rise And Fall timeCL30

Output Timing Reference Voltage

Figure 40. Input Test Waveform and Measurement Level Diagram
0.8VCC

Input timing reference level

0.1VCC

0.7VCC
0.2VCC

Output timing reference level
AC Measurement Level

Note: Input pulse rise and fall time are <5ns

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46
Rev.2.0

0.5VCC3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

8.5. DC CHARACTERISTICS(T= -40°C~85°C, VCC=2.7~3.6V)

SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

μA

ILO

Output Leakage Current

±2

μA

ICC1

Standby Current

CS#=VCC, VIN=VCC or VSS

1

5

μA

ICC2

Deep Power-Down Current

CS#=VCC, VIN=VCC or VSS

1

5

μA

CLK=0.1VCC/0.9VCC at 120MHz,
Q=Open(*1,*2,*4 I/O)

15

20

mA

CLK=0.1VCC/0.9VCC at 80MHz,
Q=Open(*1,*2,*4 I/O)

13

18

mA

ICC3

Operating Current (Read)

ICC4
ICC5

Operating Current (PP)
CS#=VCC
Operating Current (WRSR) CS#=VCC

25
25

mA
mA

ICC6
ICC7
ICC8

Operating Current (SE)Operating Current (BE)Operating Current (CE)

25
25
25

mA
mA
mA

ICC9
VIL
VIH

High Performance Current
Input Low Voltage
Input High Voltage

1.2
0.2VCC
VCC+0.4

mA
V
V

VOL
VOH

Output Low Voltage
Output High Voltage

0.2

V
V

CS#=VCC
CS#=VCC
CS#=VCC
0.6-0.5
0.7VCC
IOL=100μA
IOH=-100μA

VCC-0.2

Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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47
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C(T= -40°C~105°C, VCC=2.7~3.6V)

SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

±2
±2

μA
μA

ILI
ILO

Input Leakage Current
Output Leakage Current

ICC1

Standby Current

CS#=VCC, VIN=VCC or VSS

1

20

μA

ICC2

Deep Power-Down Current

CS#=VCC, VIN=VCC or VSS

1

20

μA

CLK=0.1VCC/0.9VCC at 80MHz,
Q=Open(*1,*2,*4 I/O)

15

20

mA

CLK=0.1VCC/0.9VCC at 60MHz,
Q=Open(*1,*2,*4 I/O)

13

18

mA

ICC3

Operating Current (Read)

ICC4

Operating Current (PP)

CS#=VCC

25

mA

ICC5
ICC6

Operating Current (WRSR) CS#=VCC
Operating Current (SE)
CS#=VCC

25
25

mA
mA

ICC7
ICC8
ICC9

Operating Current (BE)Operating Current (CE)High Performance Current

25
25
1.5

mA
mA
mA

VIL
VIH
VOL

Input Low Voltage
Input High Voltage
Output Low Voltage

IOL=100μA

0.2VCC
VCC+0.4
0.2

V
V
V

VOH

Output High Voltage

IOH=-100μA

CS#=VCC
CS#=VCC
0.6-0.5
0.7VCC
VCC-0.2

Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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48
Rev.2.0V3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C(T= -40°C~125°C, VCC=2.7~3.6V)

SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

±2
±2

μA
μA

ILI
ILO

Input Leakage Current
Output Leakage Current

ICC1

Standby Current

CS#=VCC, VIN=VCC or VSS

1

25

μA

ICC2

Deep Power-Down Current

CS#=VCC, VIN=VCC or VSS

1

25

μA

CLK=0.1VCC/0.9VCC at 80MHz,
Q=Open(*1,*2,*4 I/O)

15

20

mA

CLK=0.1VCC/0.9VCC at 60MHz,
Q=Open(*1,*2,*4 I/O)

13

18

mA

ICC3

Operating Current (Read)

ICC4

Operating Current (PP)

CS#=VCC

25

mA

ICC5
ICC6

Operating Current (WRSR) CS#=VCC
Operating Current (SE)
CS#=VCC

25
25

mA
mA

ICC7
ICC8
ICC9

Operating Current (BE)Operating Current (CE)High Performance Current

25
25
1.5

mA
mA
mA

VIL
VIH
VOL

Input Low Voltage
Input High Voltage
Output Low Voltage

IOL=100μA

0.2VCC
VCC+0.4
0.2

V
V
V

VOH

Output High Voltage

IOH=-100μA

CS#=VCC
CS#=VCC
0.6-0.5
0.7VCC
VCC-0.2

Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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49
Rev.2.0V3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

8.6. AC CHARACTERISTICS(T= -40°C~85°C, VCC=2.7~3.6V, CL=30pf)

SymbolfC
fC1
fC2

Parameter

Min.

Typ.

Serial Clock Frequency For: Dual I/O (BBH), Quad I/O(EBH),
Quad Output(6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 3.0V-3.6V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O (EBH),
Quad Output(6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O With High
Performance Mode), on 2.7V-3.6V power supply

Max.

Unit.

104

MHz

80

MHz

120

MHz

80

MHz

fR

Serial Clock Frequency For: Read (03H) Read ID (90H, 9FH and
ABH), Read Status Register (05H and 35H)tCLH

Serial Clock High Time

4

ns

tCLL

Serial Clock Low Time

4

ns

tCLCH Serial Clock Rise Time (Slew Rate)

0.1

V/ns

tCHCL Serial Clock Fall Time (Slew Rate)tSLCH CS# Active Setup Time

0.1
5

V/ns
ns

tCHSH CS# Active Hold TimetSHCH CS# Not Active Setup TimetCHSL CS# Not Active Hold Time

5
5
5

ns
ns
ns

tSHSL CS# High Time (Read/Write)tSHQZ Output Disable TimetCLQX Output Hold Time

20

ns
ns
ns

6
1.2

tDVCH Data In Setup TimetCHDX Data In Hold TimetCLQV Clock Low To Output Valid
tDP

2
2

CS# High To Deep Power-Down ModetRES1 CS# High To Standby Mode Without Electronic Signature Read
tRES2 CS# High To Standby Mode With Electronic Signature ReadtSUS CS# High To Next Command After SuspendtRStRSTtRST_EtW

Latency Between Resume And Next Suspend
CS# High To Next Command After Reset(Except From Erase)CS# High To Next Command After Reset (From Erase)

7

ns
ns
ns

20

μs

20
20
20

μs
μs
μs

30
12

μs
μs
ms

100

tBP1

Write Status Register Cycle Time
Byte Program Time (First Byte)

5
30

30
50

ms
μs

tBP2
tPP
tSE

Additional Byte Program Time (After First Byte)
Page Programming Time
Sector Erase Time (4K Bytes)

2.5
0.6
50

12
2.4
300

μs
ms
ms

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50
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash
SymbolParameter

GD25B32C
Min.

Typ.

Max.

Unit.

tBE1

Block Erase Time (32K Bytes)

0.15

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.25

2.0

s

tCE
Note:

Chip Erase Time (GD25B32C)

15

30

s

1. Typical value tested at TA= 25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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51
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C(T= -40°C~105°C, VCC=2.7~3.6V, CL=30pf)

SymbolfC
fC1
fC2

Parameter

Min.

Typ.

Serial Clock Frequency For: Dual I/O (BBH), Quad I/O(EBH),
Quad Output(6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 3.0V-3.6V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O (EBH),
Quad Output(6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O With High
Performance Mode), on 2.7V-3.6V power supply

fR

Serial Clock Frequency For: Read (03H) Read ID (90H, 9FH and
ABH), Read Status Register (05H and 35H)

tCLH
tCLL

Serial Clock High Time
Serial Clock Low Time

Max.

Unit.

80

MHz

70

MHz

80

MHz

60

MHz

4
4

ns
ns

tCLCH Serial Clock Rise Time (Slew Rate)

0.2

V/ns

tCHCL Serial Clock Fall Time (Slew Rate)

0.2

V/ns

tSLCH CS# Active Setup TimetCHSH CS# Active Hold Time

5
5

ns
ns

tSHCH CS# Not Active Setup TimetCHSL CS# Not Active Hold TimetSHSL CS# High Time (Read/Write)

5
5
20

ns
ns
ns

tSHQZ Output Disable TimetCLQX Output Hold Time
tDVCH Data In Setup Time

6
0.7
2

tCHDX Data In Hold TimetCLQV Clock Low To Output ValidtDP CS# High To Deep Power-Down Mode

7
20

ns
ns
μs

tRES1 CS# High To Standby Mode Without Electronic Signature Read20

μs

tRES2 CS# High To Standby Mode With Electronic Signature ReadtSUS CS# High To Next Command After SuspendtRS Latency Between Resume And Next Suspend

20
20

μs
μs
μs
μs
ms
ms

tRST

2

ns
ns
ns

100

tRST_EtW

CS# High To Next Command After Reset(Except From Erase)CS# High To Next Command After Reset (From Erase)
Write Status Register Cycle Time

5

30
12
30

tBP1
tBP2

Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)

30
2.5

60
15

μs
μs

tPP
tSE

Page Programming Time
Sector Erase Time (4K Bytes)

0.6
50

4
400

ms
ms

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52
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash
SymbolParameter

GD25B32C
Min.

Typ.

Max.

Unit.

tBE1

Block Erase Time (32K Bytes)

0.2

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.3

3.0

s

tCE
Note:

Chip Erase Time (GD25B32C)

15

70

s

1. Typical value tested at TA = 25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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53
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C(T= -40°C~125°C, VCC=2.7~3.6V, CL=30pf)

SymbolfC
fC1
fC2

Parameter

Min.

Typ.

Serial Clock Frequency For: Dual I/O (BBH), Quad I/O(EBH),
Quad Output(6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 3.0V-3.6V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O (EBH),
Quad Output(6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O With High
Performance Mode), on 2.7V-3.6V power supply

fR

Serial Clock Frequency For: Read (03H) Read ID (90H, 9FH and
ABH), Read Status Register (05H and 35H)

tCLH
tCLL

Serial Clock High Time
Serial Clock Low Time

Max.

Unit.

80

MHz

70

MHz

80

MHz

60

MHz

4
4

ns
ns

tCLCH Serial Clock Rise Time (Slew Rate)

0.2

V/ns

tCHCL Serial Clock Fall Time (Slew Rate)

0.2

V/ns

tSLCH CS# Active Setup TimetCHSH CS# Active Hold Time

5
5

ns
ns

tSHCH CS# Not Active Setup TimetCHSL CS# Not Active Hold TimetSHSL CS# High Time (Read/Write)

5
5
20

ns
ns
ns

tSHQZ Output Disable TimetCLQX Output Hold Time
tDVCH Data In Setup Time

6
0.7
2

tCHDX Data In Hold TimetCLQV Clock Low To Output ValidtDP CS# High To Deep Power-Down Mode

7
20

ns
ns
μs

tRES1 CS# High To Standby Mode Without Electronic Signature Read20

μs

tRES2 CS# High To Standby Mode With Electronic Signature ReadtSUS CS# High To Next Command After SuspendtRS Latency Between Resume And Next Suspend

20
20

μs
μs
μs
μs
ms
ms

tRST

2

ns
ns
ns

100

tRST_EtW

CS# High To Next Command After Reset(Except From Erase)CS# High To Next Command After Reset (From Erase)
Write Status Register Cycle Time

5

30
12
40

tBP1
tBP2

Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)

30
2.5

80
30

μs
μs

tPP
tSE

Page Programming Time
Sector Erase Time (4K Bytes)

0.6
50

6
500

ms
ms

http://www.elm-tech.com

54
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash
SymbolParameter

GD25B32C
Min.

Typ.

Max.

Unit.

tBE1

Block Erase Time (32K Bytes)

0.2

2.0

s

tBE2

Block Erase Time (64K Bytes)

0.3

4.0

s

tCE
Note:

Chip Erase Time (GD25B32C)

20

80

s

1. Typical value tested at TA = 25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

55
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial FlashCS#
CS#tCHSL
CS# tCHSL
SCLK
tCHSL
tDVCH
SCLK
tDVCH
SCLK
SI
tDVCH
SI
SO
SI
SO

GD25B32CtSHSL

Figure41. Serial Input Timing
tSLCH

tCHSH

tSLCH

tCHSH

tSLCH

tCHDX

tCHSH
tCLCH

tCHDX

tCLCH

tCHDX
MSB
High-Z
MSB
High-Z

tCLCH

MSB

tSHSL
tSHCH
tSHSL
tSHCH
tCHCL
tSHCH
tCHCL
LSB

tCHCL

LSB
LSB

High-ZSO

Figure42. Output Timing
CS#
CS#
SCLK
CS#tCLQV
SCLK
tCLQX
tCLQV
SCLK
tCLQV
SO tCLQX
SO tCLQX
SI
SO
SI

tCLQV
tCLQX
tCLQV

tCLH

tSHQZ

tCLH
tCLLtCLH

tSHQZ

tCLL

tCLQX
tCLQV

LSB

tCLL

LSB

tCLQX

LSB

Least significant address bit (LIB) in
Least significant address bit (LIB) inSI

Least significant address bit (LIB) in

Figure43. Resume to Suspend Timing

CS#
CS#
CS#

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ResumeCommand
ResumeCommand
ResumeCommand

tRS
tRS
tRS

56
Rev.2.0

SuspendCommand
SuspendCommand
SuspendCommandtSHQZ

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

9. ORDERING INFORMATIONGD xx xx xx x x x x x

Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
S: Pb Free + Halogen Free Green Package + SRP1 Function
Temperature Range
I: Industrial(-40°C to +85°C)
J: Industrial (-40°C to +105°C)
E: Industrial (-40°C to +125°C)
F: Industrial+ (-40°C to +85°C)**
3: Automotive (-40°C to +85°C)*
2: Automotive (-40°C to +105°C)*
A: Automotive (-40°C to +125°C)*
Package Type
S: SOP8 208mil
P: DIP8 300mil
N: USON8 (3x4mm)
W: WSON8 (6×5mm)
Generation
C: C Version
Density
32: 32M bit
Series
B: 3V, 4KB Uniform Sector, default x4I/O
Product Family
25: SPI NOR Flash* Please contact GigaDevice sales for automotive products.
** F grade has implemented additional test flows to ensure higher product quality than I grade.

http://www.elm-tech.com

57
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

9.1. Valid Part Numbers
Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40°C to +85°C)
Product Number
GD25B32CSIG
GD25B32CSIS
GD25B32CPIG
GD25B32CPIS
GD25B32CNIG
GD25B32CNIS
GD25B32CWIGGD25B32CWIS

Density

Package Type

32Mbit

SOP8 208mil

32MbitDIP8 300mil

32Mbit

USON8 (3x4mm)

32Mbit

WSON8 (6x5mm)

Temperature Range J: Industrial (-40°C to +105°C)
Product Number

Density

Package Type

GD25B32CSJG
GD25B32CSJS

32Mbit

SOP8 208mil

32MbitDIP8 300mil

32Mbit

USON8 (3x4mm)

32Mbit

WSON8 (6x5mm)

GD25B32CPJG
GD25B32CPJS
GD25B32CNJG
GD25B32CNJS
GD25B32CWJG
GD25B32CWJS

Temperature Range E: Industrial (-40°C to +125°C)
Product Number
GD25B32CSEG
GD25B32CSES
GD25B32CPEG
GD25B32CPES
GD25B32CNEG
GD25B32CNES
GD25B32CWEG
GD25B32CWES

http://www.elm-tech.com

Density

Package Type

32Mbit

SOP8 208mil

32MbitDIP8 300mil

32Mbit

USON8 (3x4mm)

32Mbit

WSON8 (6x5mm)

58
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

Temperature Range F: Industrial (-40°C to +85°C)
Product Number
GD25B32CSFG
GD25B32CSFS
GD25B32CPFG
GD25B32CPFS
GD25B32CNFG
GD25B32CNFS
GD25B32CWFG
GD25B32CWFS

http://www.elm-tech.com

Density

Package Type

32Mbit

SOP8 208mil

32MbitDIP8 300mil

32Mbit

USON8 (3x4mm)

32Mbit

WSON8 (6x5mm)

59
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

10. PACKAGE INFORMATION
10.1 Package SOP8 208MIL

D
5

8

E

E1

L
1

4

“A”

L1

�

b
A2

A

c

Detail “A”

A1

e

b

Base Metal

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.05

1.70

0.31

0.15

5.13

7.70

5.18

Nom

-

0.15

1.80

0.41

0.20

5.23

7.90

5.28

Max

2.16

0.25

1.90

0.51

0.25

5.33

8.10

5.38

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.

http://www.elm-tech.com

60
Rev.2.0

e

L

L1

0°

0.50
1.27

0.85

�

1.31

8°

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

10.2 Package DIP8 300MIL

1

4

E

E1

c

�

8

5

eA

D

A

A2

A1
L

e

b1
b

Dimensions
Symbol

A

A1

A2

b

b1

C

D

E

E1

Min

-

0.38

3.00

1.14

0.36

0.20

9.02

7.62

6.10

Nom

-

-

3.30

1.52

0.46

0.25

9.27

7.87

6.35

Max

3.88

-

3.50

1.78

0.56

0.35

9.59

8.26

6.60

Unit
mm

Note: Both the package length and width do not include the mold flash.

http://www.elm-tech.com

61
Rev.2.0

e

2.54

L

eA

�

2.92

8.45

0°

3.30

8.90

-

3.81

9.35

11°

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

10.3 Package USON8 (3x4mm)c

D
PIN 1#

E

A1
A
Side View

Top View

D1
4

E1

5

e
or

b

8

1

Bottom View

Note(4)L

Dimensions
Symbol

A

A1

c

b

D

D1

E

E1

Min

0.50

0.00

0.10

0.25

2.90

0.10

3.90

0.70

Nom

0.55

0.02

0.15

0.30

3.00

0.20

4.00

0.80

Max

0.60

0.05

0.20

0.35

3.10

0.30

4.10

0.90

Unit
mm

e

L
0.50

0.80

0.60
0.70

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity �0.08mm. Package edge tolerance�0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.

http://www.elm-tech.com

62
Rev.2.0

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

10.4 Package WSON8 (6*5mm)c

DPIN 1#E

A1
A

Top View

Side View

D2
4

5

e

E2

b

1

8

L
Bottom View
Dimensions
Symbol

A

A1

c

b

D

D2

E

E2

Min

0.70

0.00

0.180

0.35

5.90

3.30

4.90

3.90

Nom

0.75

0.02

0.203

0.40

6.00

3.40

5.00

4.00

Max

0.80

0.05

0.250

0.50

6.10

3.50

5.10

4.10

Unit
mm

e

L
0.50

1.27

0.60
0.75

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ���������������������������������������
63
4. The lead shape may be of little difference according to different package lead frames. These lead
http://www.elm-tech.com
Rev.2.0
shapes are compatible with each other.

3.3V Uniform Sector
Dual and Quad Serial Flash

GD25B32C

11. REVISION HISTORY
Version No

Description

Page

Date

All

2014-10-160.0

Initial Preliminary Release

1.0

Initial Release2014-10-22

1.1

Modify Package WSON 8 (6*5mm)

2015-6-11

1.2

Modify AC CHARACTERISTICS: tCHCL Min.0.2 V/ns Change to
0.1 V/nstCLCH Min.0.2 V/ns Change to 0.1 V/ns
Modify POWER-ON TIMING

2015-11-17

1.3

Modify AC CHARACTERISTICS: add tRST_R & tRST_P & tRST_E
Modify POWER-ON TIMING: TVSL Min 10us Change to 5ms

2015-12-18

1.4

Modify Package SOP8

2016-5-13

1.5

Modify tVSL from 5ms to 1.8ms
Modify VWI from 1~2.5V to 1.5~2.5V
Modify ICC4 –ICC8 from 20mA to 25mA
Modify ICC9 from 400~700uA to 0.6~1.2mA
Add tRS, of which the min value is100us
Delete tRST_P and tRST_E. Add tRST, of which the max value is 30usUpdate the description of all packages
Add “Page” column to the Revision History

2018-5-21

1.6

Add 4BH command
Modify the sequence diagram of 42H command
Modify Ordering Information

2018-9-11

1.7

Modify tSE max value from 200/300ms to 300ms
Modify tBE1 max value from 0.8/1.6s to 1.6s
Modify tBE2 max value from 1.2/2.0s to 2.0s

2018-12-4

1.8

Update Ordering Information

2019-6-3

1.9

Add AC/DC CHARACTERISTICS @-40°C~105°C@-40°C~125°C
Update Ordering Information

2019-8-2

2.0

Update Ordering Information

2019-9-9

http://www.elm-tech.com

64
Rev.2.0

3.3V
Uniform Sector
Uniform Sector
Dual
andQuad
Quad
SerialFlash
Dual and
SerialFlash

GD25B32C
GD25B32E

Important NoticeThis document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the propertyof their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product,
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document toproperly design, program, and test the functionality and safety of any application made of this information and any resulting
product. Except for customized products which has been expressly identified in the applicable agreement, the Products aredesigned, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only.
The Products are not designed, intended, or authorized for use as components in systems designed or intended for theoperation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control
instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical
devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substancesmanagement, or other uses where the failure of the device or Product could cause personal injury, death, property or
environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, andcustomers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold theCompany as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and otherliabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves theright to make changes, corrections, modifications or improvements to this document and the Products andservices described herein at any time, without notice.

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6551
Rev.2.0