Copyright NTT and Mitsubishi Electric Corporation 2000

Camellia: A 128-Bit Block Cipher
Suitable for Multiple Platforms
Kazumaro Aoki† Tetsuya Ichikawa‡ Masayuki Kanda†
Mitsuru Matsui‡ Shiho Moriai† Junko Nakajima‡ Toshio Tokita‡† Nippon Telegraph and Telephone Corporation
1-1 Hikarinooka, Yokosuka, Kanagawa, 239-0847 Japan{maro,kanda,shiho}@isl.ntt.co.jp‡ Mitsubishi Electric Corporation
5-1-1 Ofuna, Kamakura, Kanagawa, 247-8501 Japan{ichikawa,matsui,june15,tokita}@iss.isl.melco.co.jp
July 13, 2000

Abstract.
We present a new 128-bit block cipher called Camellia. Camellia
supports 128-bit block size and 128-, 192-, and 256-bit keys, i.e. the same interface
speciﬁcations as the Advanced Encryption Standard (AES). Eﬃciency on both software and hardware platforms is a remarkable characteristic of Camellia in addition
to its high level of security. It is conﬁrmed that Camellia provides strong security
against diﬀerential and linear cryptanalysis. Compared to the AES ﬁnalists, i.e.
MARS, RC6, Rijndael, Serpent, and Twoﬁsh, Camellia oﬀers at least comparable
encryption speed in software and hardware. An optimized implementation of Camellia in assembly language can encrypt on a Pentium III (800MHz) at the rate of morethan 276 Mbits per second, which is much faster than the speed of an optimized DES
implementation. In addition, a distinguishing feature is its small hardware design.
The hardware design, which includes both encryption and decryption, occupies approximately 11K gates, which is the smallest among all existing 128-bit block ciphers
as far as we know.

Copyright NTT and Mitsubishi Electric Corporation 2000

Contents
1 Introduction

1

2 Design Rationale
2.1 F -function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 P -function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 s-boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 F L- and F L−1 -functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Key Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3
3
3
3
3
4

3 Performance Figures
3.1 Software Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Hardware Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

55
7

4 Software Implementation Techniques
10
4.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Data Randomization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Hardware Evaluations
19
5.1 Type 1: Fast Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Type 2: Small Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Type 3: Small Implementation (Special Case for FPGA) . . . . . . . . . . . . . . 21
6 Security
6.1 Diﬀerential and Linear Cryptanalysis . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Truncated Diﬀerential Cryptanalysis . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Truncated Linear Cryptanalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Cryptanalysis with Impossible Diﬀerential . . . . . . . . . . . . . . . . . . . . . .
6.5 Boomerang Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Higher Order Diﬀerential Attack . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Interpolation Attack and Linear Sum Attack . . . . . . . . . . . . . . . . . . . .
6.8 No Equivalent Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Slide Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Related-key Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Statistical Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Implementation Attacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Brute Force Attacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24
24
25
27
27
27
28
28
29
29
29
29
30
30

7 Conclusion

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Copyright NTT and Mitsubishi Electric Corporation 2000

1

Introduction

This paper presents a 128-bit block cipher called Camellia, which was jointly developed by NTT
and Mitsubishi Electric Corporation. Camellia supports 128-bit block size and 128-, 192-, and256-bit key lengths, and so oﬀers the same interface speciﬁcations as the Advanced Encryption
Standard (AES). The design goals of Camellia are as follows.
High level of security. The recent advances in cryptanalytic techniques are remarkable. A
quantitative evaluation of security against powerful cryptanalytic techniques such as diﬀerential
cryptanalysis [BS93] and linear cryptanalysis [M94] is considered to be essential in designing any
new block cipher. We evaluated the security of Camellia by utilizing state-of-art cryptanalytic
techniques. We have conﬁrmed that Camellia has no diﬀerential and linear characteristics that
hold with probability more than 2−128 . Moreover, Camellia was designed to oﬀer security against
other advanced cryptanalytic attacks including higher order diﬀerential attacks [K95, JK97],
interpolation attacks [JK97, A00], related-key attacks [B94, KSW96], truncated diﬀerential attacks [K95, MT99], boomerang attacks [W99], and slide attacks [BW99, BW00].
Eﬃciency on multiple platforms. As cryptographic systems are needed in various applications, encryption algorithms that can be implemented eﬃciently on a wide range of platforms
are desirable, however, few 128-bit block ciphers are suitable for both software and hardware
implementation. Camellia was designed to oﬀer excellent eﬃciency in hardware and software
implementations, including gate count for hardware design, memory requirements in smart card
implementations, as well as performance on multiple platforms.
Camellia consists of only 8-by-8-bit substitution tables (s-boxes) and logical operations thatcan be eﬃciently implemented on a wide variety of platforms. Therefore, it can be implemented
eﬃciently in software, including the 8-bit processors used in low-end smart cards, 32-bit processors widely used in PCs, and 64-bit processors. Camellia doesn’t use 32-bit integer additions andmultiplications, which are extensively used in some software-oriented 128-bit block ciphers. Such
operations perform well on platforms providing a high degree of support, e.g., Pentium II/III or
Athlon, but not as well on others. These operations can cause a longer critical path and larger
hardware implementation requirements.
The s-boxes of Camellia are designed to minimize hardware size. The four s-boxes areaﬃne equivalent to the inversion function in the ﬁnite ﬁeld GF(28 ). Moreover, we reduced theinversion function in GF(28 ) to a few GF(24 ) arithmetic operations. It enabled us to implement
the s-boxes by fewer gate counts.
The key schedule is very simple and shares part of its procedure with encryption. It supports
on-the-key subkey generation and subkeys are computable in any order. The memory requirement for generating subkeys is quite small; an eﬃcient implementation requires about 32-byte
RAM for 128-bit keys and about 64-byte RAM for 192- and 256-bit keys.
Future developments. NTT and Mitsubishi Electric Corporation will propose Camellia in
response to the call for contributions from ISO/IEC JTC 1/SC 27, aiming at its being adopted
as an international standard. We will submit Camellia to NESSIE (New European Schemes for
Signature, Integrity, and Encryption) project as a strong cryptographic primitive.
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Outline of the paper. This paper is organized as follows: Section 2 describes the rationale
behind Camellia’s design. Section 3 discusses the performance of Camellia. Section 4 contains
the techniques for software implementation. In Section 5 we discuss our hardware evaluations.
In Section 6 we evaluated Camellia’s strength against known attacks. We conclude in Section 7.
For the speciﬁcation of Camellia, please see the separate document titled “Speciﬁcation of
Camellia – a 128-bit Block Cipher.” We will follow the deﬁnitions and notation given in thisseparate paper.

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2

Design Rationale

2.1

F -function

The design strategy of the F -function of Camellia follows that of the F -function of E2 [KMA+ 98].
The main diﬀerence between E2 and Camellia is the adoption of the 1-round (conservative) SPN(Substitution-Permutation Network), not the 2-round SPN, i.e. S-P-S. When the 1-round SPN
is used as the round function in a Feistel cipher, the theoretical evaluation of the upper boundof diﬀerential and linear characteristic probability becomes more complicated, but the speed
under the same level of “real” security is expected to be improved. See Section 6 for detailed
discussions on security.

2.2

P -function

The design rationale of the P -function is similar to that of the P -function of E2. That is, for computational eﬃciency, it should be represented using only bytewise exclusive-ORs and for security
against diﬀerential and linear cryptanalysis, its branch number should be optimal [KTM+ 99].
From among the linear transformations that satisfy these conditions, we chose one considering
highly eﬃcient implementation on 32-processors [AU00] and high-end smart cards, as well as
8-bit processors.

2.3

s-boxes

As the s-boxes we adopted functions aﬃne equivalent to the inversion function in GF(28 ) for
enhanced security and small hardware design.
It is well known that the smallest of the maximum diﬀerential probability of functions in
GF(28 ) was proven to be 2−6 , and the smallest of the maximum linear probability of functions in
GF(28 ) is conjectured to be 2−6 . There is a function aﬃne equivalent to the inversion function
in GF(28 ) that achieves the best known of the maximum diﬀerential and linear probabilities,
2−6 . We choose this kind of functions as s-boxes. Moreover, the high degree of the Boolean
polynomial of every output bit of the s-boxes makes it diﬃcult to attack Camellia by higher order
diﬀerential attacks. The two aﬃne functions that are performed at the input and output of theinversion function in GF(28 ) complicates the expressions of the s-boxes in GF(28 ), which makes
interpolation attacks ineﬀective. Making the four s-boxes diﬀerent slightly improves security
against truncated diﬀerential cryptanalysis [MT99].
For small hardware design, the elements in GF(28 ) can be represented as polynomials with
coeﬃcients in the subﬁeld GF(24 ). In other words, we can implement the s-boxes by using a few
operations in the subﬁeld GF(24 ) [MIYY88]. Two aﬃne functions at the input and output of
the inversion function in GF(28 ) also play a role in complicating the expressions of the s-boxes
in GF(24 ).

2.4

F L- and F L−1 -functions

F L- and F L−1 -functions are “inserted” between every 6 rounds of a Feistel network to provide
non-regularity across rounds. One of the goals for such a design is to thwart future unknown
attacks. It is one of merits of regular Feistel networks that encryption and decryption procedures
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are the same except for the order of the subkeys. In Camellia, F L/F L−1 -function layers areinserted every 6 rounds, but this property is still preserved.
The design criteria of F L- and F L−1 -functions are similar to those of the F L-function of
MISTY [M97]. The diﬀerence between MISTY and Camellia is the addition of 1-bit rotation.
This is expected to make bytewise cryptanalysis harder, but it has no negative impact on
hardware size or speed. The design criteria are that these functions must be linear for any ﬁxed
key and that their forms depend on key values. Since these functions are linear as long as the key
is ﬁxed, they do not make the average diﬀerential and linear probabilities of the cipher higher.
Moreover, these functions are fast in both software and hardware since they are constructed bylogical operations such as AND, OR, XOR, and rotations.

2.5

Key Schedule

The design criteria of the key schedule are as follows.
1. It should be simple and share part of its procedure with encryption/decryption.
2. Subkey generation for 128-, 192- and 256-bit keys can be performed by using the same keyschedule (circuit). Moreover, the key schedule for 128-bit keys can be performed by using
a part of this circuit.
3. Key setup time should be shorter than encryption time.
In cases where large amounts of data are processed with a single secret key, the setup time
for key scheduling may be unimportant. On the other hand, in applications in which the
key is changed frequently, key agility is a factor. One basic component of key agility is key
setup time.
4. It should support on-the-ﬂy subkey generation.
5. On-the-ﬂy subkey generation should be computable in the same way in both encryption
and decryption.
Some ciphers have separate key schedules for encryption and decryption. In otherciphers, e.g., Rijndael [DR98] or Serpent [ABK98], subkeys are computable in the forward
direction only and require unwinding for decryption.
6. There should be no equivalent keys.
7. There should be no related-key attacks or slide attacks.
Criteria 1 and 2 mainly address small hardware requirements, Criteria 3, 4, and 5 are advantageous in terms of practical applications, and Criteria 6 and 7 are for security.
The memory requirement for generating subkeys is quite small. An eﬃcient implementationof Camellia for 128-bit keys requires 16 bytes (=128 bits) for the original secret key, KL , and 16
bytes (=128 bits) for the intermediate key, KA . Thus the required memory is 32 bytes. Similarly,
an eﬃcient implementation of Camellia for 192- and 256-bit keys needs only 64 bytes.

4Copyright NTT and Mitsubishi Electric Corporation 2000

3

Performance Figures

3.1

Software Implementations

Table 1 summarizes the current software implementations of Camellia. The table shows that
Camellia can be eﬃciently implemented on low-end smart cards, and 32-bit and 64-bit processors.
We use the abbreviations M (mega) for 106 and m (milli) for 10−3 in the table.
Note that the table only shows “point” data. This means that we can implement a programthat requires less memory but works less eﬃciently. Future results may show “continuous” data.
Optimization level. When we coded programs, we tried to use the techniques described in
Section 4. However, since we did not have enough time to try all combinations of the techniques,
our numbers are probably not the best.
We think that C implementation is not important, since we can normally use assembly
language instead if it is available. Moreover, optimizing a C program means reverse engineering
the C compiler, since we often perform the following cycle when optimizing C code.
Step 1: Program or modify C code.
Step 2: Produce assembly code using a C compiler.
Step 3: Check the assembly code and go to Step 1 if not appropriate.
Step 4: Measure timing, and go to Step 1 if not satisﬁed.
When optimizing a program, we try to predict what assembly code the compiler will produce
from the C code. We think that this approach is ineﬃcient and so did not try to optimize C
code.
How to measure speed. It is diﬃcult to measure speed on modern processors since there
are many elements, for example, status of cache, that are beyond the users control and thatinﬂuence speed. We decided to measure speed under the following conditions and assumptions:• All codes and data are correctly aligned.
• Input and output texts and codes are preloaded to the ﬁrst level cache.
• Branch predictions are correct.
• Setup function (except for on-the-ﬂy implementations) generates subkey-dependent constants from the secret key, and the constants are used by encryption or decryption function.
• Encryption (decryption) function except for on-the-ﬂy implementations can encrypt (decrypt) an integral number of blocks.
• We measured the speed many times, and chose the best result to eliminate cache hit misses
and other uncontrollable factors.
• We averaged the speed numbers for large block encryption, but the values include all
overheads including loop and function calls.

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Table 1: Camellia software performance
Processor Language Key len.
Timinga
Dynamicb
Codec
Tabled
e
f
g
h
e
g
e
g
(bits) Setup ( ) Enc. ( ) Setup Enc. Setup Enc.
P IIIiAssembly

P IIj ANSI Ck
Alphal Assembly

128
192
256
128
128
192
256
128

8051m

128

Assembly

160 (4.4M) 371 (242M)
222 (3.2M) 494 (181M)
226 (3.1M) 494 (181M)
263 (1.1M) 577 (67M)
118 (5.7M) 339 (252M)
176 (3.7M) 445 (192M)
176 (3.7M) 445 (192M)
158 (4.2M) 326 (262M)
0 (0)10217 (10m)

a

28
28
28
44
48
48
48
48

36
36
36
64
48
48
48
48

0

32

1,046 2,150 8,224
1,469 3,323 8,240
1,485 3,323 8,240
1,600 3,733 4,128
1,132 3,076 16,528
1,668 4,000 16,528
1,676 4,000 16,528
1,600 2,928 16,512
0

702

288

Number of cycles needed for setup or encryption.
Dynamically used memory in bytes including stack area, excluding text and key area, which is usually
located in RAM.
c
Code size in bytes, which is sometimes located in ROM.
d
Table size in bytes, which is sometimes located in ROM.
e
Key schedule may be included.
fSeconds for 8051, and keys/s for other processors.
g
Numbers of this column is the same as decryption, since Camellia is symmetric between encryption anddecryption.
hSeconds for 8051, and b/s for other processors.
i
IBM PC/AT compatible PC, Intel Pentium III (700MHz), 256KB on-die L2 cache, FreeBSD 4.0R, 128MB
main memory.
j
IBM PC/AT compatible PC, Intel Pentium II (300MHz), 512KB L2 cache, MS-Windows 95, 160MB main
memory.
k
Microsoft Visual C++ 6 with the optimization options /G6 /Zp16 /ML /Ox /Ob2.
l
COMPAQ Professional Workstation XP1000, Alpha 21264 (667MHz), Compaq Tru64 UNIX 4.0F, 2GB
main memory.
mIntel 8051 (12MHz; 1 cycle = 12 oscillator periods) simulator on Unix.
b

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3.2

Hardware Performance

Tables 4 through 7 summarize the hardware performance of 128bit-key Camellia on ASIC (Application Speciﬁc Integrated Circuit) and FPGA (Field Programmable Gate Array). Table 2
shows the environment of our hardware design and evaluation.

Table 2: Hardware evaluation environment (ASIC, FPGA)
Language(ASIC, FPGA) Verilog-HDL
Simulator(ASIC, FPGA) Verilog-XL
Design library (ASIC) Mitsubishi Electric 0.35µ CMOS ASIC library(FPGA) Xilinx XC4000XL series
Login synthesis (ASIC) Design Compiler version 1998.08(FPGA) Synplify version 5.3.1 and ALLIANCE version 2.1i

We evaluated Type 1 through Type 3 logic. Table 3 shows the top priorities of the logic types.

Table 3: Hardware design policies (outline)
TypeTop priority
Outline of logic
Type 1 Fast implementation from the viewpoint of Enc(Dec) speed
Figure 1
Type 2 Small implementation from the viewpoint of total logic size
Figure 2
Type 3
Small implementation (special case for FPGA)
Figure 3

The details of each type are described in Section 5.

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Table 4: Hardware performance (Type 1: Fast implementation [ASIC(0.35µ CMOS)])
Algorithm
Area[Gate]
Key setup Critical- Throughput
a
b
c
name
Enc.&Dec. Key expan. Total logic time[ns] path[ns]d [Mb/s]
DES
42,204
12,201
54,405—55.11
1161.31
Triple-DES
124,888
23,207
128,147—
157.09407.40MARS
690,654
2,245,096 2,935,754 1740.99 567.49
225.55RC6
741,641
901,382 1,643,037 2112.26 627.57
203.96
Rijndael
518,508
93,708612,834
57.39
65.64
1950.03
Serpent
298,533
205,096503,770
114.07 137.40
931.58
Twoﬁsh200,165
231,682
431,857
16.38 324.80
394.08
Camellia
216,91155,907
272,81924.36 109.35
1170.55aincluding output registers
including subkey registerscincluding buﬀers for fan-out adjustmentdCritical path of data encryption (or decryption)b

Table 5: Hardware performance (Type 2: Small implementation [ASIC(0.35µ CMOS)])
Algorithm
Area[Gate]
Key setup Critical- Throughput
name Enc.&Dec.a Key sched.b Total logic c time[ns] path[ns]d [Mb/s]
Camellia

6,367

4,979

11,350

110.2

27.67

220.28aincluding output registers and data selector
including subkey registers and a part of key expansion logiccincluding buﬀers for fan-out adjustmentdCritical path of data encryption (or decryption)b

Table 6: Hardware performance (Type 2: Small implementation [FPGA(XC4000XL series)])
Algorithm Area[CLBs] Critical- Throughput
name
Total
path[ns]a [Mb/s]
Camellia
1,296
78.815
77.34
aCritical path of data encryption (or decryption)

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Table 7: Hardware performance (Type 3: Small implementation [FPGA(XC4000XL series)])
Algorithm Area[CLBs] Critical- Throughput
name
Total
path[ns]a [Mb/s]
Camellia874
49.957122.01aCritical path of data encryption (or decryption)

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4

Software Implementation TechniquesThis section describes how to implement Camellia eﬃciently in software. In most cases, animplementation can be divided into two parts: setup including key schedule and data randomization, that is, encryption or decryption. We ﬁrst describe how to optimize the setup code, andthen describe how to optimize the data randomization code.
This section describes speciﬁc techniques for 8-, 32-, or 64-bit processors. However, a technique for 8-bit processors may be applicable to 32- or 64-bit processors and a technique for 32-bit
processors may be applicable to 64-bit processors. Other word sizes may need to be considered.
We assume that you ﬁrst implement Camellia using the speciﬁcation as it is. This section
will optimize the resulting code.
Note that in this section “word” means the natural size of the target processor. For example,
the words of IA-32 without MMX technology, IA-32 with MMX technology and Alpha are 32-,64-, and 64-bits long respectively.

4.1
4.1.1

Setup
Store All Subkeys

Store all subkeys into memory once you generate them if you have suﬃcient memory, and use
the stored subkeys for data randomization.
4.1.2

Subkey Generation Order

You do not have to compute subkeys in order. For example, when you compute subkeys for a
128-bit key, ﬁrst compute the subkeys that only depend on KL , and then compute subkeys that
only depend on KA . This reduces the number of registers or memory for storing KA .
4.1.3

XOR Cancellation Property in Key Schedule

The key schedule of Camellia is based on the Feistel structure. Between the 2nd round and the
3rd round, KL is XORed to an intermediate value. This structure causes cancellations of KL .
More precisely, the input of the 3rd round can be computed by the following equations.
(right half)(left half)(right half)(left half)

=
=
=
=

F (KLL , Σ1 )
F (KLR ⊕ (right half), Σ2 )KRR ⊕ F (KLL ⊕ KRL , Σ1 )KRL ⊕ F (KLR ⊕ (right half), Σ2 )for 128-bit keysfor 192- and 256-bit keys

Using the above equations, we can eliminate 3 and 2 XORs in L for 128- and 192/256-bit keys,
respectively, compared to the straightforward implementation of the speciﬁcation.
4.1.4

Rotation Bits for KL , KR , KA , and KB

You do not need to keep KL , KR , KA , and KB , but you should keep their rotated values whengenerating subkeys. You can generate subkeys by rotating the kept values by a sum of integral
multiples of 16 ± 1 bits.
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kl5 and kl6 Generation from k11 and k12

4.1.5

For 192- and 256- bit keys, you can use word-oriented rotation to generate (kl5 , kl6 ) from(k11 , k12 ), since (kl5 , kl6 ) equals (k11 , k12 )<<<32 . This saves a few instructions compared to general rotation.
4.1.6

On-the-ﬂy Subkey Generation

You can generate subkeys on-the-ﬂy. All subkeys are one of the rotated values of KL , KR ,KA , and KB . Thus, you ﬁrst generate KL , KR , KA , and KB , and then rotate them to get thesubkeys. Refer to Section 4.1.4 for the rotated numbers of bits for KL , KR , KA , and KB .
4.1.7

128-bit key and 192/256-bit key

If your code does not need to use key sizes larger than 128 bits, you do not need to generate
KB . That is, you can omit the computations for the last two F -functions.
4.1.8

How to Rotate an Element in Q

8-bit processor. As stated in Section 4.1.4, the amount of rotation in bits is a sum of integral
multiples of 16 ± 1. Thus, you can rotate an element in Q by 16 ± 1 bits by rotating 1-bit leftor right followed by a 2-byte move.
32-bit processor. Consider the use of a double precision shift instruction: shrd or shld if
you are programming on IA-32.
F -function

4.1.9

Key schedule includes F -functions, but the main usage of the F -function is for data randomization. Refer to Section 4.2.
4.1.10

Keyed Functions

Camellia has three keyed functions: bitwise XOR, bitwise OR, and bitwise AND. Consider theuse of a self-modifying code, if possible.

4.2

Data Randomization

4.2.1

Endian Conversion

Camellia prefers big endian. Thus, the code for little endian processors needs additional codefor endian conversions.
The most straightforward implementation converts the endian when loading a register frommemory and storing a register to memory. Only F L- and F L−1 -functions are endian dependent.
More precisely, only the 1-bit rotation in F L- or F L−1 -function is endian dependent. This meansthat you can convert endians just before or just after the 1-bit rotation with the appropriate

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subkey generation scheme. A combination of computing endian conversion and 1-bit rotation
may increase the performance of Camellia. Details are described in Section 4.2.2.
Some processors have a special instruction for endian conversion. For example, IA-32 (after
80486) has bswap instruction. Use these instructions. However, do not use the byte swap
technique described in [C98, Appendix A]. The technique reduces the code size, but it is not
fast, since the memory load and store instruction incurs long latency.
As described above, the endian problem only eﬀects the 1-bit rotation of a 32-bit word.
Thus, we do not need full 64-bit word endian conversion.
The following are general methods to realize endian conversion for 32-bit register x. In
the following techniques, you can use either ∪ or ⊕ instead of + in the equations, and you canswitch the computational order between shifts including rotations and ANDs with an appropriate
conversion of masked constants.
Straightforward.
x ← (x24 ) + ((x ∩ 0xff00)

8 ) + ((x8 ) ∩ 0xff00) + (x24 )The technique has high parallelism.
Minimum operations without rotation.
x ← (x16 ) + (x16 )x ← ((x ∩ 0xff00ff)

8 ) + ((x8 ) ∩ 0xff00ff)

Using rotations.
x ← ((x ∩ 0xff00ff)>>>8 ) + ((x<<<8 ) ∩ 0xff00ff)
Using SSE. New Intel Pentium family processors including Pentium III have a very eﬀective
instruction for reordering data, which is called pshufw [I99]. 5 instructions including pshufw
are suﬃcient to convert endian for 64-bit data.
4.2.2

1-bit Rotation in Little Endian Interpretation

As described in Section 4.2.1, we do not need endian conversion when loading and storing texts
if we can eﬃciently implement 1-bit rotation in F L- and F L−1 -functions.
Assuming x to be a 32-bit register that contains little endian data to be rotated by 1-bit, we
can compute 1-bit rotation by the following equation.
x ← ((2x) ∩ 0xfefefefe) + ((x>>>15 ) ∩ 0xfefefefe)(1)

Of course, this technique requires an appropriate changes to subkey setup and other functions.
Note that + in Equation (1) can be replaced with ∪ or ⊕, and computing 2x can be done by,<<1 or addition with x itself, and you can switch the computational order between shifts
1 <including rotations and ANDs with an appropriate conversion of masked constants.
Conﬁrm whether your processor has ANDNOT instruction, such as pandn in IA-32 and bic
in Alpha. In this case, you do not need to prepare the constant, 0xfefefefe.
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4.2.3

Whitening

The key additions kw2 and kw4 can be combined into other keyed operations using the following
equations.
(x ⊕ k) ⊕ y = (x ⊕ y) ⊕ k,(x ⊕ k) ⊕ l = x ⊕ (k ⊕ l),(x ⊕ k) ∩ l = (x ∩ l) ⊕ (k ∩ l),(2)(x ⊕ k)<<<1 = (x<<<1 ) ⊕ (k<<<1 ),(x ⊕ k) ∪ l = (x ∪ l) ⊕ (k ∩ l),where x, y, k, l are bit strings. Adjust subkeys at setup to eliminate 2 XORs in L.
4.2.4

Key XOR

Using Equations (2), you can move key XORs to any place if the movement does not go throughthe S-function. For example, changing F -function computation P (S(X ⊕ k)) to P (S(X)) ⊕ k
may improve instruction scheduling.
4.2.5

S-function

s1 is deﬁned by the arithmetics in GF(28 ). However, do not compute GF(28 ) arithmetics; instead
precompute and hard-code a table in your program, see Table 4 in the speciﬁcation.
We strongly suggest that you also precompute and hard-code s2 , s3 , and s4 tables in addition
to s1 , if you have suﬃcient memory and 8-bit rotation is expensive. If you do not have suﬃcient
memory, the data of s2 , s3 , and s4 can be generated from the table for s1 using one rotation(See Section 4.5 in the speciﬁcation).
If you have suﬃcient memory, and cost of table lookup is heavy, as is true for the current Javavirtual machines, consider the use of a two s-box combined table, for example (s1 (y1 ), s2 (y2 )).
4.2.6

P -function

32-bit processor. Let (ZL , ZR ) = ((z1 , z2 , z3 , z4 ), (z5 , z6 , z7 , z8 )) be the input of P -function ) = ((z  , z  , z  , z  ), (z  , z  , z  , z  )) be the output of P -function.
and (ZL , ZR
1 2 3 45 6 7 8From Figure 5 in the speciﬁcation, you can see that P -function can be computed as follows.
ZL ← ZL ⊕ (ZR <<<8 )ZR ← ZR ⊕ (ZL <<<16 )ZL ← ZL ⊕ (ZR >>>8 )ZR ← ZR ⊕ (ZL >>>8 )ZL ← ZR


ZR
← ZL

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The critical path of this computation is long. We can modify the computation as follows.
ZL
ZL
ZL
ZL
ZL

←
←
←
←
←

ZL ⊕ ZR
ZL >>>8
ZL ⊕ ZRZL <<<8
ZR

ZR
ZR
ZR
ZR
ZR

ZR

←
←
←
←
←
←

ZR <<<8
ZR <<<8
ZR ⊕ ZLZR <<<16
ZR ⊕ ZLZL

The critical path of the above computation is decreased. It seems that the technique requires one
additional rotation, however, you can probably combine the ﬁrst step of the above computationand S-function without any additional cost.
8-bit processor (orthogonal mnemonics). If the instruction in your processor can XOR
any combination of registers and has suﬃcient registers, you can compute P -function by using
just 16 XORs using Figure 5 in the speciﬁcation.
8-bit processor (accumulator based). If your processor is accumulator based, minimizing
the number of XORs is not always a good idea, since the computation may require register loadfrom memory and store into memory many times. The following computation is optimized foran accumulator based processor.
z8 ← z1 ⊕ z4 ⊕ z5 ⊕ z6 ⊕ z7
z4 ← z8 ⊕ z1 ⊕ z2 ⊕ z3
z7 ← z4 ⊕ z2 ⊕ z7 ⊕ z8
z3 ← z7 ⊕ z1 ⊕ z2 ⊕ z4
z6 ← z3 ⊕ z1 ⊕ z6 ⊕ z7
z2 ← z6 ⊕ z1 ⊕ z3 ⊕ z4
z5 ← z2 ⊕ z4 ⊕ z5 ⊕ z6
z1 ← z5 ⊕ z2 ⊕ z3 ⊕ z4
When indexing zi costs many operations, the following is useful.
σ ← z1 ⊕ z2 ⊕ z3 ⊕ z4 ⊕ z5 ⊕ z6 ⊕ z7 ⊕ z8

z1 ← σ ⊕ z2 ⊕ z5z2 ← σ ⊕ z3 ⊕ z6
z3 ← σ ⊕ z4 ⊕ z7
z4 ← σ ⊕ z1 ⊕ z8

z5 ← σ ⊕ z3 ⊕ z4 ⊕ z5
z6 ← σ ⊕ z1 ⊕ z4 ⊕ z6
z7 ← σ ⊕ z1 ⊕ z2 ⊕ z7
z8 ← σ ⊕ z2 ⊕ z3 ⊕ z8
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4.2.7

Substitution and Permutation

This section describes how to eﬃciently compute P ◦ S compared to independently computing
S and P .
64-bit processor. If your processor has a suﬃciently large ﬁrst level cache, use the techniquedescribed in [RDP+ 96]. The technique prepares the following tables deﬁned by Equations (3).
SP1 (y1 )SP2 (y2 )SP3 (y3 )SP4 (y4 )
SP5 (y5 )
SP6 (y6 )SP7 (y7 )
SP8 (y8 )

=
=
=
=
=
=
=
=

(s1 (y1 ), s1 (y1 ), s1 (y1 ),0, s1 (y1 ),0,0, s1 (y1 ))(0, s2 (y2 ), s2 (y2 ), s2 (y2 ), s2 (y2 ), s2 (y2 ),0,0)(s3 (y3 ),0, s3 (y3 ), s3 (y3 ),0, s3 (y3 ), s3 (y3 ),0)(s4 (y4 ), s4 (y4 ),0, s4 (y4 ),0,0, s4 (y4 ), s4 (y4 ))(0, s2 (y5 ), s2 (y5 ), s2 (y5 ),0, s2 (y5 ), s2 (y5 ), s2 (y5 ))(s3 (y6 ),0, s3 (y6 ), s3 (y6 ), s3 (y6 ),0, s3 (y6 ), s3 (y6 ))(s4 (y7 ), s4 (y7 ),0, s4 (y7 ), s4 (y7 ), s4 (y7 ),0, s4 (y7 ))(s1 (y8 ), s1 (y8 ), s1 (y8 ),0, s1 (y8 ), s1 (y8 ), s1 (y8 ),0)(3)

Next, compute the following equation:(z1 , z2 , z3 , z4 , z5 , z6 , z7 , z8 ) ←8SPi (yi )i=1This technique requires the following operations.
# of table lookups# of XORs
Size of table (KB)8
7
16

If the ﬁrst cache of the target processor is moderately large, replace a few of the tablesdeﬁned by Equations (3) with the tables below.
SPα (y)SPβ (y)SPγ (y)SPδ (y)====(s1 (y), s1 (y), s1 (y), s1 (y), s1 (y), s1 (y), s1 (y), s1 (y))(s2 (y), s2 (y), s2 (y), s2 (y), s2 (y), s2 (y), s2 (y), s2 (y))(s3 (y), s3 (y), s3 (y), s3 (y), s3 (y), s3 (y), s3 (y), s3 (y))(s4 (y), s4 (y), s4 (y), s4 (y), s4 (y), s4 (y), s4 (y), s4 (y))(4)

Then, mask the necessary byte positions. This technique requires the following operations if
you use just tables of Equations (4).
# of table lookups# of XORs# of ANDs
Size of table (KB)

8
7
8
8

When implementing this technique on Alpha architecture [C98], and if the number of registers
is insuﬃcient for storing constants for masking operation, use zap or zapnot instructions.

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If your processor can eﬃciently copy half bits of a register to the other half, for example, punpckldq/punpckhdq or pshufw instructions in IA-32 [I99] which are realized after Pentium with MMX technology and Pentium III, respectively, prepare SP1 , SP2 , SP3 , and SP4
deﬁned in Equations (3). Then, compute the following equation:(z1 , z2 , z3 , z4 , z5 , z6 , z7 , z8 ) ←

4


8


SPi (yi ) ⊕ ν(

i=1

SPi−4 (yi )),i=5where ν denotes the operation that copies the ﬁrst 4 bytes to the last 4 bytes. This techniquerequires the following operations.
# of table lookups# of XORs# of νs
Size of table (KB)

8
7
1
8

32-bit processor. [AU00] shows eﬃcient implementations of Camellia-type substitution andpermutation networks. One of the techniques prepares the following tables deﬁned by Equations (5):0)
SP1110 (y) = (s1 (y), s1 (y), s1 (y),0, s2 (y), s2 (y), s2 (y))
SP0222 (y) = ((5)
0, s3 (y), s3 (y))
SP3033 (y) = (s3 (y),0, s4 (y))
SP4404 (y) = (s4 (y), s4 (y),Then, compute as follows:
D ← SP1110 (y8 ) ⊕ SP0222 (y5 ) ⊕ SP3033 (y6 ) ⊕ SP4404 (y7 )U(z1 , z2 , z3 , z4 )(z5 , z6 , z7 , z8 )← SP1110 (y1 ) ⊕ SP0222 (y2 ) ⊕ SP3033 (y3 ) ⊕ SP4404 (y4 )← D⊕U← (z1 , z2 , z3 , z4 ) ⊕ (U >>>8 )This technique requires the following operations.
# of table lookups# of XORs# of rotations
Size of table (KB)

8
8
1
4

[AU00] also shows an implementation that is suitable for a processor in which rotation is very
costly. The technique prepares the following tables in addition to tables deﬁned by Equations (5):SP1001 (y)SP2200 (y)SP0330 (y)SP0044 (y)

=
=
=
=

(s1 (y),0,0, s1 (y))(s2 (y), s2 (y),0,0)(
0, s3 (y), s3 (y),0)(
0,0, s4 (y), s4 (y))

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Then, compute as follows:
D ← SP1110 (y8 ) ⊕ SP0222 (y5 ) ⊕ SP3033 (y6 ) ⊕ SP4404 (y7 )(z1 , z2 , z3 , z4 )(z5 , z6 , z7 , z8 )← D ⊕ SP1110 (y1 ) ⊕ SP0222 (y2 ) ⊕ SP3033 (y3 ) ⊕ SP4404 (y4 )← D ⊕ SP1001 (y1 ) ⊕ SP2200 (y2 ) ⊕ SP0330 (y3 ) ⊕ SP0044 (y4 )This technique requires the following operations.
# of table lookups# of XORs
Size of table (KB)
4.2.8

12
11
8

Making Indices for s-box

You can make an index for s-box by simply using shifts and ANDs. However, several processors
have special instructions for making an index, for example, movzx in IA-32 [I99] and extbl in
Alpha [C98].
movzx is a fast operation in P6, but it can be used only for the two least signiﬁcant bytes.
A straightforward implementation uses eax, ebx, ecx, and edx registers for storing (Lr , Rr ),and 2 rotations are used for making indices; 2 rotations are used for recovering byte order inthe registers every round. However, you can remove 2 rotations for recovering byte order every
round if you prepare rotated tables. Note that the byte order in registers returns to a naturalorder every 4 rounds.

4.3

General Guidelines

This section describes general guidelines. The guidelines are useful to optimize Camellia as wellas other block ciphers. Please refer to the optimization manuals for each processor.
Avoid misaligned data accesses. Almost all processors penalize misaligned data access.
Align data to the word boundary.
Avoid partial data accesses. Most processors have a function to access a smaller part thanword size. However, this function may cause a penalty. Do not access partial data, even
if you do not need full size of word and you have suﬃcient memory.
Be careful of the size of the cache. If the program or its data exceeds the size of the cache,the speed of the program will signiﬁcantly decrease. Loop unrolling and table expansion
are good techniques to speed up the program, but do not exceed the size of the cache.
Use intrinsic functions. Several compilers support intrinsic functions. For example, when
you use Microsoft Visual C++ version 6 compiler on IA-32, and declare “#pragma
intrinsic( lrotl)” and use “ lrotl”, the compiler generates rotation instructions inassembly language. Refer to the manual of the compiler that you use for details.
Measuring precise speeds is diﬃcult. The running time of your code depends on manyfactors: cache hit misses, OS interrupts, and so on. Furthermore, the cryptographic
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Copyright NTT and Mitsubishi Electric Corporation 2000

properties, for example, the number of blocks to be encrypted, also eﬀect the runningtime.
A few processors have an instruction to get the time stamp. For example, IA-32 (after
Pentium) has rdtsc [I99] and Alpha has rpcc [C98]. It is a good idea to use the timestamp counter for measuring speeds, but you should not directly apply these instructions
to out-of-order architectures such as P6 and EV6.
If you want to measure speed precisely, consult good guidebooks. For example, if you
use Pentium family processors, refer to [F00].

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5

Hardware Evaluations

In Section 3, we showed evaluation results of hardware implementations (ASIC, FPGA) of 128bit key Camellia. In this Section, we describe the design policies of the three types of logic
evaluated in Section 3. The details of each type are described below.

5.1

Type 1: Fast Implementation

Plaintext / Ciphertext
Encryption
andDecryption
Logic

Subkey Registers

Critical Path of Data Encryption(or Decryption)

In Type 1, we evaluate the hardware implementation (ASIC) where the goal is to achieve thefastest encryption and decryption speed with no consideration of logic size. Figure 1 outlines
the Type 1 logic. Table 8 shows the basic Type 1 components.

Key Expansion
Logic

Key

Critical Path of Key Expansion

OutputRegisters

Ciphertext / Plaintext

Figure 1: Outline of Type 1 (ASIC)

Table 8: The basic Type 1 components
Encryption and Data randomizing logic for encryption and decryption,
decryption logic which consists of combinational logic.
Output register Register for the encryption (decryption) data.
Key expansion logic Logic in which subkeys are generated from key,which consists of combinational logic.
Subkey register Register for the output data of key expansion logic.

The design policies of these basic components are listed below.
1. “Encryption and decryption logic” and “Key expansion logic”(a) Loop architecture is not introduced.
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Copyright NTT and Mitsubishi Electric Corporation 2000(b) Pipeline architecture is not introduced.
(c) Substitution tables (s-boxes) are designed by logic synthesis tool.
Note that other encryption algorithms (AES ﬁnalists, DES and Triple-DES) are evaluatedin Section 3, and some of them use arithmetic operations (addition, multiplication, etc).
For arithmetic operations, we use faster ones in the library of Synopsys Design Ware Basic
Library[Synopsys (1998)].
2. “Output register” and “Subkey register”(a) The size of Output register is one block (=128 bits).
(b) The size of Subkey register is the total length of all subkeys in the algorithm.
Under the above design policies, we evaluated Camellia and other algorithms on ASIC devices. The results are summarized in Table 4 in Section 3. “Throughput” is deﬁned as follows:
Throughput[b/s] =5.2

Block size(128 [bits]).
Critical path of data encryption(decryption)[sec]Type 2: Small Implementation

Key

Critical Path of Data Encryption(or Decryption)

Plaintext / Ciphertext
Key Scheduling Logic
anda part of
Key Expansion Logic

Data Selector

One Round of
Encryption and Decryption
Logicwith sharing a part of(or all of) Key Expansion Logic

Subkey Registers

Output Registers

Ciphertext / Plaintext

Figure 2: Outline of Type 2 (ASIC, FPGA)

The design policies of these basic components are as follows.
20

Critical Path of Key Expansion

In Type 2, we evaluate the hardware implementations (ASIC, FPGA) with the goal of achieving
the smallest logic in encryption (and decryption). Figure 2 outlines the Type 2 logic. Table 9shows the basic Type 2 components.

Copyright NTT and Mitsubishi Electric Corporation 2000

Table 9: The basic Type 2 components
Data randomizing logic for one round operation of encryption anddecryption, which includes (a part of) key expansion logic, andconsists of combinational logics.
Output register Register for the output (and pending) data.
Data selector
Selector which selects either en(de)cryption data or output data.
Key scheduling logic Logic in which subkeys are generated using (a part of)
key expansion logic in encryption and decryption logic andconsists of combinational logics.
Subkey register Register for the output data of key scheduling logic.
Encryption anddecryption logic

1. “Encryption and decryption logic” and “Key scheduling logic”(a) Loop architecture is introduced.
(b) Pipeline architecture is not introduced.
(c) Substitution tables (s-boxes) are optimized by hand.
(d) Key scheduling logic consists (a part of) key expansion logic and control logic.
2. “Output register”, “Subkey register” and “Data selector”(a) The size of Output register is one block (=128 bits).
(b) The size of Subkey register is that of the subkeys used in Encryption and decryption
logic.
(c) Data selector is 2-1 selector, whose size is one block (=128 bits).
Under the above design policies, we evaluated Camellia on ASIC and FPGA. The results are
summarized in Table 5 (ASIC) and Table 6 (FPGA) in Section 3. “Throughput” is deﬁned asfollows:
Throughput[b/s] =5.3

Block size(128 [bits]).
Critical path of data encryption(decryption)[sec] × round number

Type 3: Small Implementation (Special Case for FPGA)In Type 3, we evaluated the hardware implementation (FPGA) as a special case of Type 2.
In Type 3, we assume that all subkeys are given and are loaded into FPGA internal memory.
Figure 3 outlines the Type 3 logic. Table 10 shows the basic Type 3 components.
The design policies of these basic components are as follows.
1. “Encryption and decryption logic”(a) Loop architecture is introduced (which consists of one round operation).
(b) Pipeline architecture is not introduced.
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Data Selector

One Round of
Encryption
andDecryption
Logic

Subkey Memory

Critical Path of Data Encryption(or Decryption)

Plaintext / Ciphertext

Subkeys

Output Registers

Ciphertext / Plaintext

Figure 3: Outline of Type 3 (FPGA)

Table 10: The basic Type 3 components
Encryption and Data randomizing logic for one round operation of encryption anddecryption logic decryption, which includes (a part of) key expansion logic, andconsists of combinational logic.
Output register Register for the output (and pending) data.
Data selector Selector which selects either en(de)cryption data or output data.
Subkey memory Memory for the subkeys loaded from outside.

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Copyright NTT and Mitsubishi Electric Corporation 2000(c) Substitution tables (s-boxes) are optimized by hand.
2. “Output register”, “Subkey memory” and “Data selector”(a) The size of Output register is one block (=128 bits).
(b) The size of Subkey memory is the length of all subkeys in the algorithm.
(c) Data selector is 2-1 selector whose size is one block (=128 bits).
Under the above design policies, we evaluated Camellia on an FPGA. The results are summarizedin Table 7 (FPGA). “Throughput” is deﬁned as follows:
Throughput[b/s] =Block size(128 [bits]).
Critical path of data encryption(decryption)[sec] × round number

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6

Security

6.1

Diﬀerential and Linear Cryptanalysis

The most well-known and powerful approaches to attacking many block ciphers are diﬀerential
cryptanalysis, proposed by Biham and Shamir [BS93], and linear cryptanalysis, introduced by
Matsui [M94]. There are several methods of evaluating security against these attacks, where
there is a kind of “duality” relation between them [M95, CV95]: in other words, the security
against both attacks can be evaluated in similar ways.
It is known that the upper bounds of diﬀerential/linear characteristic probabilities can, forseveral block ciphers, be estimated using the minimum numbers of diﬀerential/linear active
s-boxes in some consecutive rounds. Kanda [K00] shows the minimum numbers of diﬀerential/linear active s-boxes for Feistel ciphers with conservative SPN (S-P) round function. Hereafter, we assume that linear transformation P is bijective.
Deﬁnition 1 The branch number B of linear transformation P is deﬁned by
B = min(wH (x) + wH (P (x))),x=0where wH (x) denotes the bytewise Hamming weight of x.
Deﬁnition 2 A diﬀerential active s-box is deﬁned as an s-box given a non-zero input diﬀerence.
A linear active s-box is deﬁned as an s-box given a non-zero output mask value.
Theorem 1 The minimum number of diﬀerential/linear active s-boxes in any eight consecutive
rounds is equal or larger than 2B + 1.
Deﬁnition 3 For any given ∆x, ∆y, Γx, Γy ∈ GF(2m ), the diﬀerential/linear probabilities ofsi -box: GF(2m ) → GF(2m ) are deﬁned as:#{x ∈ GF(2m )|si (x) ⊕ si (x ⊕ ∆x) = ∆y}2mm#{x ∈ GF(2 )|x · Γx = si (x) · Γy}Pr[x · Γx = si (x) · Γy] =x2m

Pr[si (x) ⊕ si (x ⊕ ∆x) = ∆y] =x

Deﬁnition 4 Let ps and qs be the maximum diﬀerential/linear probabilities of all s-boxes{s1 , s2 , . . .}.
ps = max max Pr[si (x) ⊕ si (x ⊕ ∆x) = ∆y]i∆x=0,∆y x

qs = max max (2 Pr[x · Γx = si (x) · Γy] − 1)2iΓy=0,Γxx

Theorem 2 Let D and L be the minimum numbers of total diﬀerential/linear active s-boxes.
L
Then, the maximum diﬀerential/linear characteristic probabilities are bounded by pD
s and qs ,respectively.

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With the above-mentioned techniques, we prove that Camellia oﬀers immunity to these
attacks by showing the upper bounds of maximum diﬀerential/linear characteristic probabilities,
since Camellia is a Feistel cipher whose round function uses the S-P round function.
In the case of Camellia, the maximum diﬀerential/linear probabilities of the s-boxes are
ps = qs = 2−6 .
The branch number of the linear transformation (P -function) is 5, i.e.
B = 5.
Letting p, q be the maximum diﬀerential/linear characteristic probabilities of Camellia reduced
to 16-round without F L- and F L−1 -functions, respectively, we havep ≤ ps2(2B+1) = (2−6 )22 = 2−132

and q ≤ qs2(2B+1) = (2−6 )22 = 2−132

from Theorems 1 and 2. Both probabilities are below the security threshold of 128-bit blockciphers: 2−128 . It follows that there is no eﬀective diﬀerential characteristic or linear characteristic for Camellia reduced to more than 15 rounds without F L- and F L−1 -functions. Since
F L- and F L−1 -functions are linear for any ﬁxed key, they do not make the average diﬀerential/linear probabilities of the cipher higher. Hence, it is proven that Camellia oﬀers enoughsecurity against diﬀerential and linear attacks.
Note that the result above are based on Theorems 1 and 2. Both theorems deal with generalcases of Feistel ciphers with SPN round function, so we expect that Camellia is actually moresecure than shown by the result above. As supporting evidence, we counted the number of active
s-boxes of Camellia with reduced rounds. The counting algorithm is similar to that describedin [M99] except following three items.
• Prepare the table for the number of active s-boxes instead of transition probability table.
• Count the number of active s-boxes instead of computing transition probability.
• F L- and F L−1 -functions set all elements to the minimum number of active s-boxes in thetable. This means that the algorithm gives consideration to existence of weak subkeys inserted to F L- and F L−1 -functions, since there may be some possibility of connecting every
later diﬀerential/linear characteristic with the previous one with the highest probability,
which is equivalent to the minimum number of active s-boxes.
As a result, we conﬁrmed that 12-round Camellia with F L- and F L-functions has no diﬀerential/linear characteristic with probability higher than 2−128 (see Tables 11 and 12).

6.2

Truncated Diﬀerential Cryptanalysis

The attacks using truncated diﬀerentials were introduced by Knudsen [K95]. He deﬁned themas diﬀerentials where only a part of the diﬀerence can be predicted. The notion of truncateddiﬀerentials introduced by him is wide, but with a byte-oriented cipher it is natural to study
bytewise diﬀerentials as truncated diﬀerentials [MT99].

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# of rounds
Estimation basedon Th. 1 and 2
Camellia

1

2

3

4

2−12

2−30

5

6

7

12
2−96
(2) (5)
(7)
(11)
(16)
−6
−12
−42
−54
−66
−72
−72
−78
−108
−120
1 2
2
2
2
2
2
2
2
2
2
2−132
(0) (1) (2) (7) (9) (11) (12) (12) (13) (18) (20) (22)−1
without F L/F L - 1 2−6 2−12 2−36 2−54 2−66 2−78 2−90 2−108 2−126 2−132
functions(0) (1) (2) (6) (9) (11) (13) (15) (18) (21) (22)Note: The numbers in brackets are the number of active s-boxes.
2−42

8

9

10

11

2−66

Table 11: Upper bounds of diﬀerential characteristic probability of Camellia# of rounds
Estimation basedon Th. 1 and 2
Camellia

1

2

3

4

2−12

2−30

5

6

12
2−96
(2) (5)
(7)
(11)
(16)
1 2−6 2−12 2−36 2−54 2−66 2−72 2−72 2−78 2−102 2−120 2−132(0) (1) (2) (6) (9) (11) (12) (12) (13) (17) (20) (22)without F L/F L−1 - 1 2−6 2−12 2−36 2−54 2−66 2−78 2−84 2−108 2−120 2−132
functions(0) (1) (2) (6) (9) (11) (13) (14) (18) (20) (22)Note: The numbers in brackets are the number of active s-boxes.
2−42

7

8

9

10

11

2−66

Table 12: Upper bounds of linear characteristic probability of Camellia

The maximum diﬀerential probability is considered to provide the strict evaluation of security against diﬀerential cryptanalysis, but computing its value is impossible in general, since a
diﬀerential is a set of all diﬀerential characteristics with the same input diﬀerence and the same
output diﬀerence for a Markov cipher [LMM91]. On the other hand, a truncated diﬀerential
can be regarded as a subset of the diﬀerential characteristics which are exploitable in cryptanalysis. For some ciphers, e.g., byte-oriented ciphers, the probability of truncated diﬀerential
can be computed easily and correctly, and it gives a more strict evaluation than the maximum
diﬀerential characteristic probability.
A truncated diﬀerential cryptanalysis of reduced-round variants of E2 was presented by Matsui and Tokita at FSE’99 [MT99]. Their analysis was based on the “byte characteristic,” wherethe values to the diﬀerence in a byte are distinguished between non-zero and zero. They found a
7-round byte characteristic, which leads to a possible attack on an 8-round variant of E2 without
IT -Function (the initial transformation) and F T -Function (the ﬁnal transformation). The best
attack of E2 shown in [MSAK00] breaks an 8-round variant of E2 with either IT -Function or
F T -Function using 294 chosen plaintexts. In [MSAK00] we also show the attack which distinguishes a 7-round variant of E2 with IT - and F T -Functions from a random permutation using
291 chosen plaintexts.
Camellia is a byte-oriented cipher similar to E2, and it is important to evaluate its security
against truncated diﬀerential cryptanalysis. We searched for truncated diﬀerentials using an
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algorithm similar to the one described in [MT99, MSAK00]. The main diﬀerence of the round
function between E2 and Camellia is the adoption of the 1-round SPN not the 2-round SPN,
i.e. S-P-S. In the search for truncated diﬀerentials of E2, we used about 2−8 as the probabilityof diﬀerence cancellation in byte at the XOR of Feistel network. However, the round functionof Camellia doesn’t have the second s-boxes-layer, and the cancellation sometimes occurs withprobability 1. As a result, more than 10-round Camellia is indistinguishable from a random
permutation both with/without F L-/F L−1 -function layers.

6.3

Truncated Linear Cryptanalysis

We introduce a new cryptanalysis called truncated linear cryptanalysis.
Due to the duality between diﬀerential and linear cryptanalysis, we can evaluate security
against truncated linear cryptanalysis by using a similar algorithm to that above. To put it
concretely, we can perform the search by replacing the matrix of P -function with the transposed matrix. As a result, more than 10-round Camellia is indistinguishable from a random
permutation without F L-/F L−1 -function layers.

6.4

Cryptanalysis with Impossible Diﬀerential

The impossible diﬀerential means the diﬀerential which holds with probability 0, or the diﬀerential which never exists. Using such an impossible diﬀerential, it is possible to narrow down thecandidates of the subkey. It is known that there is at least one 5-round impossible diﬀerential in
any Feistel network with a bijective round function. Since Camellia has the Feistel network (withF L- and F L−1 -functions inserted between every 6 rounds) and the round function is bijective,
Camellia has 5-round impossible diﬀerentials. We have not found impossible diﬀerentials withmore than 6 rounds. Moreover, we expect F L- and F L−1 -functions make attacking Camellia
using impossible diﬀerentials diﬃcult, since the functions change diﬀerential paths depending on
key values. In consequent, Camellia with full rounds will not be broken by cryptanalysis using
impossible diﬀerentials.

6.5

Boomerang Attack

Boomerang attack [W99] requires 2 diﬀerentials. Let the probability of the diﬀerentials be p∆
and p∇ . An boomerang attack that is superior than exhaustive key search requiresp∆ p∇ ≥ 2−64 .

(6)

Using Table 11, there is no combination that satisﬁes Inequality (6) for Camellia without F Land F L−1 -functions. The best boomerang probability for Camellia without F L- and F L−1 functions reduced to 8-round is bounded by 2−66 that is obtained by p∆ = 2−12 (3 rounds) andp∇ = 2−54 (5 rounds). Since attackable rounds for Camellia without F L- and F L−1 -functions isbounded by much shorter than the speciﬁcation of Camellia, 18, Camellia seems secure against
a boomerang attack.

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6.6

Higher Order Diﬀerential Attack

Higher order diﬀerential attack is generally applicable to ciphers that can be represented as
Boolean polynomials of low degree. All intermediate bits in the encryption process can be
represented as Boolean polynomials, i.e. polynomials GF(2)[x1 , x2 , . . . , xn ] in the bits of theplaintext: {x1 , x2 , . . . , xn }. In the higher order diﬀerential attack described in [JK97, Theorem 1], if the intermediate bits are represented by Boolean polynomials of degree at least d, the(d + 1)-th order diﬀerential of the Boolean polynomial becomes 0.
For the degrees of Boolean polynomials of the s-boxes of Camellia, the functions aﬃneequivalent to the inversion function in GF(28 ) are adopted as the s-boxes. It is known that thedegree of the Boolean polynomial of every output bit of the inversion function in GF(28 ) is 7, but
the degree for the s-boxes of Camellia is not trivial, since aﬃne functions are added at the input
and output. We conﬁrmed that the degree of the Boolean polynomial of every output bit of thes-boxes is 7 by ﬁnding Boolean polynomial for every output bit of the s-boxes. In Camellia, it isexpected that the degree of an intermediate bit in the encryption process increases as the data
pass through many s-boxes. For example, the degree becomes 73 > 128 after passing throughthree s-boxes. Therefore, we expect that higher order diﬀerential attacks fail against Camellia
with full rounds.
Hori and Kaneko showed that 5-round E2 without IT - and F T -functions can be broken byusing the ﬁrst order diﬀerential [HK98]. However, we consider their attack to be similar to the
traditional diﬀerential attack rather than the above-mentioned higher order diﬀerential attack.
That is, the main point of their technique is to ﬁnd the pairs of plaintext and ciphertext whichyield a nontrivial constant at some intermediate round. In other words, this means that an
attacker traces diﬀerential paths. In consequence, we believe that the immunity of Camellia to
Hori et al.’s attack is comparable to the immunity to traditional diﬀerential attack described in
Section 6.1.

6.7

Interpolation Attack and Linear Sum Attack

The interpolation attack proposed in [JK97] is typically applicable to attacking ciphers that use
simple algebraic functions.
The principle of interpolation attack is that, roughly speaking, if the ciphertext is represented
as a polynomial or rational expression of the plaintext whose number of unknown coeﬃcientsis N , the polynomial or rational expression can be constructed using N pairs of plaintexts andciphertexts. Once the attacker constructs the polynomial or rational expression, he can encrypt
any plaintext into the corresponding ciphertext or decrypt any ciphertext into the corresponding
plaintext for the key without knowing the key. Since N determines the complexity and thenumber of pairs required for the attack, it is important to make N as large as possible. If N is
so large that it is impractical for the attackers to gather N plaintext-ciphertext pairs, the cipher
is secure against interpolation attack.
Linear sum attack [A00] is a generalization of the interpolation attack [JK97]. A practicalalgorithm that evaluates the security against linear sum attack was proposed in [A00]. We
searched for linear relations between any plaintext byte and any ciphertext byte over GF(28 )using the algorithm. Table 13 summarizes the results.
Table 13 shows that Camellia is secure against linear sum attack including interpolation

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Table 13: Smallest number of unknown coeﬃcients for 128-, 192-, and 256-bit keys
whitening×1 + round×r (r < 4)whitening×1 + round×4
More rounds

1
255
256

attack. It also implies that Camellia is secure against Square attack [DKR97] followed by [A00,
Theorem 3].

6.8

No Equivalent Keys

Since the set of subkeys generated by the key schedule contain the original secret key, there
is no equivalent set of subkeys generated from distinct secret keys. Therefore, we expect that
there are no distinct secret keys both of which encrypt each of many plaintexts into the same
ciphertext.

6.9

Slide Attack

In [BW99, BW00] the slide attacks were introduced, based on earlier work in [B94, K93]. In
particular it was shown that iterated ciphers with identical round functions, that is, equal
structures and equal subkeys in the round functions, are susceptible to slide attacks.
In Camellia, F L- and F L−1 -functions are “inserted” between every 6 rounds of a Feistel
network to provide non-regularity across rounds. Moreover, from the viewpoint of the keyschedule, slide attacks seems to be very unlikely to succeed (See Section 6.10).

6.10

Related-key Attack

We are convinced that the key schedule of Camellia makes related-key attacks [B94, KSW96] very
diﬃcult. In these attacks, an attacker must be able to get encryptions using several related keys.
If the relation between, say, two keys, is known then if the corresponding relations between thesubkeys can be predetermined, it might become possible to predict how the keys would encrypta pair of diﬀerent plaintexts. However, since the subkeys depend on KA and KB , which are theresults of encryption of a secret key, and if an attacker wants to change the secret key, he can’t
get KA and KB desired, and vice versa, these subkey relations will be very hard to control andpredict.

6.11

Statistical Tests

Most of statistical characteristics depends on the diﬀerential attack and other cryptanalytic
attacks. For example, it is frequently discussed how many ciphertext bits are complemented
when one plaintext bit is complemented. According to the deﬁnition and the property of thediﬀerential distribution table, the resistance to diﬀerential attacks implies that the number ofcomplemented bits is about a half. Of course, we may ﬁnd a statistical weakness, if we have29

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enough computational resource. However, none in the world has an eﬃcient resource to compute
such a statistical measure for a 128-bit block cipher.
Note that the following. It is frequently tested for a round function, because of the limited
computational resource. However, we think that it is not signiﬁcant, because we can constructa cipher that does not show good statistical properties for the round function but shows good
statistical properties for a cipher and we can also construct a cipher that shows good statisticalproperties for the round function but does not show good statistical properties for a cipher.

6.12

Implementation Attacks

It is well known that a poor implementation can leak information by timing attacks [K96] orpower analysis attacks [KJJ99]. Using the classiﬁcation proposed in [DR99], Camellia is in thegroup of “favorable” algorithms, since it uses only logical operations and table-lookups and ﬁxed
rotations.
On the other hand, Chari et al. [CJRR99] claims that all AES candidates are susceptible topower analysis attacks. As these two papers contradict with each other, how to resist against
power analysis attacks is not known, since study on power analysis attacks has just begun. We
think that Camellia should be protected by the hardware techniques and should not be evaluatedby the security directly derived from the speciﬁcation, considering the current art. We hope thatthe study on power analysis attack will be progressed in the near future.

6.13

Brute Force Attacks

Most brute force attacks are applicable to any deterministic block cipher, and the corresponding
complexity depends on only the block size or key size∗ , regardless of its design. Camellia has
a block size of 128-bit and allows for the three key sizes of 128-, 192-, and 256-bit. In thediscussions below, k denotes the key size in bits.
Exhaustive key search. In exhaustive key search, if an attacker gets one pair of plaintext
and ciphertext encrypted in ECB mode, he can ﬁnd the correct key by encrypting the plaintext
with all 2k possible keys.
A weakness in the key scheduling of the cipher can help improve the eﬃciency of exhaustive
key search attack [K94], but we have not found such a weakness in Camellia. The complexityof the exhaustive key search is estimated to be about 2k−1 encryptions on average. Thus, therequired complexity for exhaustive key search is 2127 , 2191 , and 2255 encryptions for Camellia
with 128-, 192-, and 256-bit keys, respectively. Therefore, Camellia’s security against exhaustive
key search is adequate.
Time-memory trade-oﬀ attack. There are some words that are often used in plaintexts.
If an attacker encrypts such a plaintext block using 2k keys and store them in space for 2k
ciphertexts, then after he gets the corresponding ciphertext, he only has to look it up to ﬁnd∗

Strictly speaking, the computation time required for the attack depends on the performance of the blockcipher. However, the performance only aﬀects the encryption time and only changes the time complexity by
negligible factor.

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the corresponding key. This attack is called table attack. In this attack, after 2k encryption isdone, the attack complexity is much smaller than is true for exhaustive key search.
Time-memory trade-oﬀ attack [H80, KM96] can drastically reduce both time complexity on
intercepted ciphertexts of exhaustive key search and space complexity of table attack. However,both attacks require precomputation equivalent to the time complexity of exhaustive key search.
The key sizes supported by Camellia are long enough for security against exhaustive key searchby today’s technology.
Dictionary attack. In dictionary attack, an attacker collects plaintext-ciphertext pairs under
the same key and put them in a “dictionary”. When the attacker can see only a ciphertext
encrypted by the key, he can check if it is in the dictionary. If it is, he has already the plaintext.
Since the block size of Camellia is 128 bits, dictionary attack would require the space for 2128
diﬀerent plaintext blocks to allow the attackers to encrypt or decrypt arbitrary messages underan unknown key. The success probability depends on the space for the dictionary, and as
the block size is larger, the required space to achieve the same success probability increases
exponentially. The 128-bit block cipher Camellia has enough security against this attack.
Matching ciphertext attack. In matching ciphertext attack [K98, Theorem 2], when about
the square root of all ciphertexts are available identical ciphertext blocks can be expected withprobability more than 12 by the “birthday paradox” for some modes of operations such as ECB,
CBC, and CFB modes. Then, valuable information about the plaintexts can be derived. Notethat this attack is dependent of the key size. Since the block size of Camellia is 128 bits, thethreat to this attack is small, if encryption of as many as 264 blocks under the same key is not
performed.

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7

Conclusion

We have presented Camellia, the rationale behind its design, its suitability for both softwareand hardware implementation, and the results of our cryptanalyses.
The performances shown in this paper leave room for further optimizations. The latest
performance results will be posted on the Camellia home page: http://info.isl.ntt.co.jp/
camellia/.
We have analyzed Camellia and found no important weakness. The cipher has a conservative
design and any practical attacks against Camellia would require a major breakthrough in thearea of cryptanalysis. We think that Camellia is a very strong cipher, which matches the securityof the existing best block ciphers.

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