2009/3/27～2009/4/3

Introduction of Fabless Methodology inElectronics by EDA Tools and Foundries

R. K. Pokharel, H. Kanaya, and K. Yoshida(with Assistance of Prof. Yassura’ Group)
Yoshida Laboratory (http://yossvr0.ed.kyushu-u.ac.jp/)
Department of Electrical and Electronic Engineering
Graduate School of Information Science and Electrical Engineering
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Kyusyu University

Driving Force: Wireless Technologies
Wireless LAN、Cell Phone、Cordless Telephone、IC Card, ITS, DSRC
Camera
車線監視カメラ

路側表示器（出口）Antenna

路側無線装置（アンテナ）

通信開始 装置

車両検知器
発進制御機

Electronic-Toll Collection System.

Wireless LAN

Ｓａｔｅｌｌｉｔｅ Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ

Cell Phone Cordless Phone
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The Design House Phenomenon

Recent models
for business

Fabless Company-Designs IC at home andoutsource the fabrication.

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Fabless Design Model still prosper for 3040 years

IC Insights top 20 rankings in 2008

Fablessvendor

Even in the worst downturns,
Fabless company and Fabless vendor ⇒ High growth rates

4IC Insights, USA

Scope & Trend
Intel (USA),
Samsung (Korea),
TI (USA) etc.
Technology node

Vertically integrated (1980s)
・ Owned and operated their own silicon wafer fabrication plant.
・ Developed their own process technology.
・ Performed assembly and test for their chips.

Running cost

EDA: CAD Tools
Collaboration

Horizontal (international) specialization

Fabless (LSI Deign)
LSI Design only, First TAT, New company, Venture company
Necessity of research and development resources for LSI Design

Foundry (LSI fabrication)

VisionHave a deep sub-micron semiconductor fabrication plant(Fabless Vendor)

ofEJU
S
5T

Foundry for Integrated Circuits (ICs)GaAs, GaN, InP, SiC, SiGe, SOI, CMOS

Trade-off between NF, cost, performance,
frequency of applications and so on.

6Comparison between GaAs and CMOS

GaAs :--Low noise at higher frequencies--Faster switching speed-- High cost

CMOS:-- Low cost-- SiO2 is one of the best insulators-- Hole mobility that leads to fabricate PMOSFET for CMOS logic (digital circuits).

SOI: Silicon on Insulator--Layered silicon-parasitic capacitancesperformance improvement--Hole mobility reduces

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RF-MEMS(RF Microelectromechanical Systems)
Applications in RF-LSI: Switches, switchedcapacitors and varactors, high Q-inductors
Other Applications are antennas, tunable filters andphase shifters.
Recent trend is in Digital RF processor—using noinductors in RF front end.

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Japanese Trends in RF-MEMS
Industry

Academia

In Japan-Integrated MEMS (MEMS + CMOS)
Research Society was established on 2008 (oneyear before).
Slogan: More than Moore by True MEMS
Success in LSI???
Reason: Digital RF Processor

9Our Private Opinion
RF-MEMS should compete with Digital RF Processor
Who will be the winner?
Guess: Digital RF Processor due to low cost

CMOS is best solution for
university level research.
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Roadmap of CMOS Technologies
Only logic

11Comparison between Digital and Analog

High Cost of Conventional Analog Circuits

Spiral Inductors—Does not reduce withdeep sub-micron CMOS

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Foundry CostShuttle Service- TWO WAYS in Japan
Through VDEC

Through private companies
We use this option.
Chip COST (in ¥)CMOS 0.18um Mixed signal
CMOS 90nm Mixed signal
CMOS 65nm Mixed signal

2.5M (+Packaging)
5mm x 5mm
(Chip size)

5M (+Packaging)
7.5M (+Packaging)
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Foundry at University Level Research
z 0.18 um CMOS : Because it is cheaper andacademic discount is available.
zApplications: below 12 GHz
9 Ultra-wideband (UWB) applications
9 Multi-standard systems
9 Software-defined radio or so on.
Millimeter-wave applications: 90 nm CMOS but cost14Cost Estimation for Fabrication(Material Cost)
Using 0.18 um CMOS
2 times/year(2.5m +1.5m) * 2 =8 M Yen
Approximately US$ 80,000

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CAD Tools
Design Tools:
Schematic Design
zAgilent-ADS
zAgilent-Momentum,
EMDS (EM software)

Layout Design
zCadence-Assura,
VirtusozCadence-Spectre, spice etc
EM Simulation:
Ansoft: HFSS, FDTD (3D)16
MATLAB (with SimuLink)

Fixed Cost Estimation (Additional**)(CAD Tools )Cost per Unit License (¥)
Agilent Tools: 8 M
Cadence Tools: 9 M
EM Tools:4M
MATLAB:
1M
Additional Cost/license : 22 M
At least 3 license, additional total cost : 66 M = US$660,000
Additional** does not include the cost for those tools
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in the list provided by E-JUST officers.

Lab Facilities of Testing

Probe Station

Spectrum
Analyzer

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Lab Facilities of Testing50Ω cable

Cascade Microtech
Probe
LSI chip

Air Coplanar Probe

Spiral inductor

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Additional Cost for Equipments(Fixed Cost)
Cost per Unit License (¥)
Probe station: 10 M
Noise Figure Meter: 5 M
Source Signal Analyzer: 11 M
Extra for DC source, probes etc: 2 MTotal = 28 M = US$ 280,000

Additional** does not include the cost for thoseequipments in the list provided by E-JUST officers.20

Total Cost Estimation
Fixed cost ( Additional CAD tools) = US$ 660,000
Fixed cost ( Additional Equipments) = US$ 280,000
Fixed cost ( Fixed Cost providedby E-JUST officers)=US$ 554,748

Total Fixed Costs = US$1,494,748
Material cost (Chip Fabrication)/year(Using 0.18 um CMOS)= US$ 80,000
Overhead Cost/year= US$20,000
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Total Costs = US$1,794,848 for first year.

Digital Laboratory Setup (I)EDA TOOLS:Application

EDA Tools

High Level

CyberWorkBench, Comet,

Front-End

VCS, NC-Verilog, VCX MX, Riveira-Pro, Composer IF, Analog
HSPICE IF etc

Pre-layout

Design Analyzer, DC ultra, HDL compiler, DFTcompiler, power compiler, VHDL compiler

Backend

IC compiler, Calibre, Cadence link, IC compiler

Cost: Approximately US$ 593,44522

Digital Laboratory Setup (II)Test Equipments:
LSI Tester

LSI Testers (512 pin, 256 pin, WS only etc)

OtherParameter Analyzer, Signal Generator, Laserpair equipments, Signal analyzer, network
Equipments analyzer, Oscilloscope, Logic analyzer, datagenerator, digital multimeter, dc sources etc.

Cost: Approximately US$ 900,000
Total cost for Digital Lab setup= US$ 1,493,445
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Block diagram of CMOS-LSI System for WirelessCommunications
Antenna

Receiving part Mixer

VGA

LPF

A/D

digital

ＬＮＡ
PLL

proc.

ＰＡ

PHY

Mixer

Buff

LPF

D/A

TransmittingWith Collaboration

Direct Conversion Receiver Type
1-Chip:SoC Implementation (System on Chip)
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Prototype Design [Part-II]
Ultra-wide band (UWB)
systems
5mm

zLNA, mixer, ADC, DAC
For MIMO-MESHProjectzMixer, VCOs, 1-bit ADC
zTest chips.
5mm25

Measuring system of communication distance
RF-ID@2.45GHz (IMSband)

PC
Antenna

Reader-Writer

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MIMO System: Originality and Dominancy
MIMO-MESH, Pico-MESH
Conventional MESH Device

MESH Point

More than 10kg
Limitation= 2~3 hubs

DeviceImage

RF front end + IP Core

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Conclusion
zMicrowave Circuits-Filters, Antenna etc.
zRF and Analog Integrated Circuits (RFIC)
Applications:
For MIMO,PICO and UWBDetail:Thank you for you kind Attention!

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