Ⅱ-9. Instrumentation

RIKEN Accel. Prog. Rep. 47 (2014)

Development of the fast interlock system at the BigRIPS separator
K. Yoshida,*1 K. Tanaka, *1 K. Kusaka, *1 Y. Yanagisawa, *1 and T. Kubo*1
A beam interlock system is particularly important forprotecting beam line devices from the failure of magnets
and other devices. The failure of beam line magnets canlead to the miss-steering of the beam and the beam might
hit the beam pipe or other devices mounted along the beamline. If the beam power is high, such unexpected beamirradiation can cause serious damage to devices. The 238Ubeam with an energy of 345 MeV/nucleon and the intensityof 1 particle µA can melt stainless steel even in 1 ms if it isfocused at a diameter of 2 mm. In order to prevent damage,the beam should be stopped as soon as possible. The BeamInterlock System (BIS)1,2) is installed at RIBF for thispurpose. The BIS monitors the normal operation of devices
and sends a beam-stop signal to the beam chopper installedat the exit of the ion source when a device fails. The beamchopper stops the beam within a few microseconds uponreceiving a stop signal. The total response time of theexisting BIS is only several milliseconds since the system
uses Programmable Logic Unit (PLC) as signal processing.
To cope with high-power beams extracted from theSuperconducting Ring Cyclotron (SRC) at RIBF, theresponse time of the existing interlock system is currently
inadequate and hence, a new interlock system with a fast
response is developed.
A prototype of the fast interlock system with 4 analog
inputs and 8 logic inputs has been developed to evaluate thespeed of the response. In order to achieve a fast responsetime, a compact RIO system (cRIO), cRIO-9075 of
National Instrument Co. Ltd. is utilized as the processingunit. The cRIO consists of a CPU and a field-programmablegate array (FPGA) that are closely related to each other. The
FPGA allows a fast response between the input and output
and the CPU provides versatile control of the unit. A fastsampling ADC module, NI-9222 with 500 k sample/sec, isused for analog inputs, and fast digital I/O modules,
NI-9401 with 100 ns propagation delay, are used for logicalinputs and outputs. Fig. 1 shows the block diagram of theinterlock logic. As seen in the figure, an analog input isdigitized in the ADC and compared with pre-defined upperand lower limits; the fault output is produced if the digitizedvalue exceeds those limits. The fault output is then masked
with an enable/disable flag and latched in a Set-Reset
flip-flop in order to hold a fault situation. A logic input isexclusive-or'ed with a polarity flag and latched in the sameway. The values in the flip-flops are or'ed together toproduce a failure output. These control logics are stored in
the FPGA of the cRIO and executed at a fast speed. TheCPU of the cRIO is used as the interface to thecomprehensive control system of the BigRIPS3) that utilizes
EPICS4) as the base. Statuses of faults and digitized valuesof the analog inputs are monitored by the control system ofthe BigRIPS. The upper and lower limit values of theanalog input and input masks are dynamically set from thecontrol system. The programming of cRIO is performed in aLabVIEW developer environment.
The response speed of the prototype of the fast interlock
system was measured with a test signal. A step signal wasinputted to the logical and analog input and the time delay
between the input and output signals was measured. The
response times are 0.2 µs for logical inputs and 5 µs foranalog inputs. These are sufficiently fast for the fastinterlock system. The prototype was also examined with theactual current monitor signal of the power supply of the first
dipole magnet at BigRIPS. The current monitor signal wasconnected to one of the analog inputs and the digitizedvalue was monitored. The digitized value was fluctuatedwithin 0.25% due to the noise that appeared in the monitor
signal. This is similar to the value compared with thehardware comparator built in the power supply to detect theoutput current drift.
Based on the successful test results on the prototype, thefast interlock system of the BigRIPS has been designed tomonitor the analog and logical signals from power suppliesof the 34 magnets placed at the primary beam line and theBigRIPS where a high-power primary beam is transported.
The system consists of 4 cRIOs and sends the beam stop
signal to the beam chopper as well as BIS. The fabricationof the system will be completed by the end of March 2014
and the system is expected to be operational by the end ofJuly 2014.
References
1) M. Komiyama, M. Fujimaki, and M. Kase, Proc. of 2nd Annu.
Meet. of Particle Accelerator Society of Japan and 30th LinearAccelerator Meet. In Japan, Tosu, 2005-7 (2005),p. 615.
2) M. Komiyama, et. al, RIKEN Accel. Prog. Rep., 41 (2008) 242.
3) K. Yoshida, RIKEN Accel. Prog. Rep., 44 (2011) 131 andreferences there in.
4) http://www.aps.anl.gov/epics/.

Fig. 1 Logic diagram of the prototype of the fastinterlock system.
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