ICM-40609-D

A TDK SmartMotion™ Solution Designed for Drone Market

GENERAL DESCRIPTIONFEATURES

The ICM-40609-D is a 6-axis MEMS MotionTracking
device that combines a 3-axis gyroscope and a 3-axis
accelerometer designed for the drone market. The
ICM-40609-D is form factor compatible with ourlegacy drone devices – making the transition to thelatest offering incredibly simple.
™

The ICM-40609-D takes advantage of a state-of-theart architecture design that enhances the IMU’s
performance and accuracy over temperature,making it the ideal drone solution to control thestability of the platform during long flight times that
may experience high temperature shifts.
The ICM-40609-D has a max ODR of 32 KHz, making
it the best sampling rate available in a consumer
device. The ability to capture data at such a highODR allows for customers to easily find any
anomalies or errors that need to be addressed
during flight. The accel Full Scale Range has also
been increased to 32g, allowing for substantial linear
movement to be easily tracked.
Other industry-leading features include on-chip 16bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts.
The device features I2C and SPI serial interfaces, a
VDD operating range of 1.71V to 3.6V, and aseparate VDDIO operating range of 1.71V to 3.6V.

•
•
•
•
•
•
•
•
•
•
•

Gyro Noise: 4.5mdps/√Hz
Gyro Offset Stability TC: ±10mdps/C
Gyro Sensitivity Error: ±0.5%
Gyro Sensitivity/temp: ±0.045%/C
Accel Noise: 100μg/√Hz
Accel Offset Stability TC: ±0.15mg/C
Accel Sensitivity Error: ±0.5%
Accel Sensitivity/temp: ±0.007%/C
Gyro + Accel Combo current: 0.77mA
Extended Accel Full Scale Range: 32g
Improved ODR Latency: 32KHz

Custom architecture for Improved Thermal
Gradient Behavior•

Best-in-class accuracy over temperature

Increased ODR/FSR for max data collection••

32g Accel Full Scale Range
32 KHz ODR Sample Rate

Form Factor Compatible with Legacy Products••

Easily transition from ICM-20602 and MPU-6500
Only minor pinout changes required

APPLICATIONS•PART NUMBER

Drones, Flight Controller

PACKAGE SIZETARGET MARKETSFULL SCALE RANGE

MPU-6500

3x3x0.9mm 24-pin QFNVarious±2000dps/16g

ICM-20602

3x3x0.75mm 16-pin LGA

Various±2000dps/16g

ICM-42688-P

2.5x3 14mm-pin LGA

Robotics/HMD/IoT/Drones±2000dps/16g

ICM-40609-D

3x3x0.91mm 24-pin LGA

Enhanced Drone
Performance±2000dps/32g

InvenSense, Inc. reserves the right to change
specifications and information herein without
notice unless the product is in mass production
and the datasheet has been designated by
InvenSense in writing as subject to a specified
Product / Process Change Notification Method
regulation.

InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A+1(408) 988–7339
invensense.tdk.com

ODR & SAMPLE SYNCH

G: 8KHz/ A: 4KHz
16-bit
G: 8KHz/ A: 4KHz
16-bit32KHz
G: 19-bit / A: 18-bit
32KHz
16-bitDocument Number: DS-000330
Revision: 1.2
Rev. Date: 06/07/2022

STATUS

NR/ND
NR/ND
Active2H 2022

ICM-40609-D
TABLE OF CONTENTS

General Description ............................................................................................................................................ 1
Features .............................................................................................................................................................. 1
Applications ........................................................................................................................................................ 1

1

2

3

4

Introduction ........................................................................................................................................................ 8
1.1

Purpose and Scope .................................................................................................................................. 8

1.2

Product Overview .................................................................................................................................... 8

1.3

Applications ............................................................................................................................................. 8

Features .............................................................................................................................................................. 9
2.1

Gyroscope Features ................................................................................................................................. 9

2.2

Accelerometer Features .......................................................................................................................... 9

2.3

Additional Features.................................................................................................................................. 9Electrical Characteristics................................................................................................................................... 10
3.1

Gyroscope Specifications ....................................................................................................................... 10

3.2

Accelerometer Specifications ................................................................................................................ 11

3.3

Electrical Specifications ......................................................................................................................... 12

3.4

I2C Timing Characterization ................................................................................................................... 14

3.5

SPI Timing Characterization – 4-Wire SPI Mode .................................................................................... 15

3.6

SPI Timing Characterization – 3-Wire SPI Mode .................................................................................... 16

3.7

Absolute Maximum Ratings ................................................................................................................... 17

Applications Information .................................................................................................................................. 18
4.1

Pin Out Diagram and Signal Description ................................................................................................ 18

4.2

Typical Operating Circuit........................................................................................................................ 19

4.3

Bill of Materials for External Components ............................................................................................. 20

4.4

System Block Diagram ........................................................................................................................... 21

4.5

Overview ................................................................................................................................................ 21

4.6

Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning .............................................. 21

4.7

Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ....................................... 21

4.8

I2C and SPI Host Interface ...................................................................................................................... 21

4.9

Self-Test ................................................................................................................................................. 21

4.10

Clocking ............................................................................................................................................. 22

4.11

Sensor Data Registers ........................................................................................................................ 22

4.12Interrupts........................................................................................................................................... 22

4.13

Digital-Output Temperature Sensor .................................................................................................. 22

4.14

Bias and LDOs .................................................................................................................................... 22

4.15

Charge Pump ..................................................................................................................................... 22

4.16

Standard Power Modes ..................................................................................................................... 23

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ICM-40609-D
5

6

7Signal Path ........................................................................................................................................................ 24
5.1

Notch Filter ............................................................................................................................................ 24

5.2

Anti-Alias Filter ...................................................................................................................................... 25

5.3

User Programmable Offset .................................................................................................................... 27

5.4

UI Filter Block ......................................................................................................................................... 28

5.5

ODR And FSR Selection .......................................................................................................................... 33

FIFO................................................................................................................................................................... 36
6.1

Packet Structure .................................................................................................................................... 36

6.2

FIFO Header ........................................................................................................................................... 37

6.3

Maximum FIFO Storage ......................................................................................................................... 38

6.4

FIFO Configuration Registers ................................................................................................................. 38

Programmable Interrupts ................................................................................................................................. 40
7.1

8

9

Wake-On Motion Interrupt.................................................................................................................... 40

Digital Interface ................................................................................................................................................ 41
8.1

I2C and SPI Serial Interfaces ................................................................................................................... 41

8.2

I2C Interface ........................................................................................................................................... 41

8.3

I2C Communications Protocol ................................................................................................................ 41

8.4

I2C Terms ................................................................................................................................................ 43

8.5

SPI Interface ........................................................................................................................................... 44

Assembly .......................................................................................................................................................... 45
9.1

Orientation of Axes ................................................................................................................................ 45

9.2

Package Dimensions .............................................................................................................................. 46

10Part Number Package Marking ......................................................................................................................... 48

11

Use Notes ......................................................................................................................................................... 49

12

13

11.1

Accelerometer Mode Transitions ...................................................................................................... 49

11.2

Accelerometer Low Power (LP) Mode Averaging Filter Setting ........................................................ 49

11.3

Settings for I2C, and SPI Operation .................................................................................................... 49

11.4

Notch Filter and Anti-Alias Filter Operation ...................................................................................... 49

11.5

Register Values Modification............................................................................................................. 49

Register Map .................................................................................................................................................... 50
12.1

User Bank 0 Register Map ................................................................................................................. 50

12.2

User Bank 1 Register Map ................................................................................................................. 51

12.3

User Bank 2 Register Map ................................................................................................................. 52

12.4

User Bank 4 Register Map ................................................................................................................. 52

User Bank 0 Register Map – Descriptions......................................................................................................... 53
13.1

DEVICE_CONFIG ................................................................................................................................ 53

13.2

DRIVE_CONFIG .................................................................................................................................. 53

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ICM-40609-D
13.3

INT_CONFIG....................................................................................................................................... 54

13.4

FIFO_CONFIG ..................................................................................................................................... 54

13.5

TEMP_DATA1 .................................................................................................................................... 54

13.6

TEMP_DATA0 .................................................................................................................................... 55

13.7

ACCEL_DATA_X1................................................................................................................................ 55

13.8

ACCEL_DATA_X0................................................................................................................................ 55

13.9

ACCEL_DATA_Y1 ................................................................................................................................ 55

13.10

ACCEL_DATA_Y0 ................................................................................................................................ 55

13.11

ACCEL_DATA_Z1 ................................................................................................................................ 56

13.12

ACCEL_DATA_Z0 ................................................................................................................................ 56

13.13

GYRO_DATA_X1................................................................................................................................. 56

13.14

GYRO_DATA_X0................................................................................................................................. 56

13.15

GYRO_DATA_Y1 ................................................................................................................................. 56

13.16

GYRO_DATA_Y0 ................................................................................................................................. 57

13.17

GYRO_DATA_Z1 ................................................................................................................................. 57

13.18

GYRO_DATA_Z0 ................................................................................................................................. 57

13.19

TMST_FSYNCH ................................................................................................................................... 57

13.20

TMST_FSYNCL .................................................................................................................................... 57

13.21

INT_STATUS ....................................................................................................................................... 58

13.22

FIFO_COUNTH ................................................................................................................................... 58

13.23

FIFO_COUNTL .................................................................................................................................... 58

13.24

FIFO_DATA......................................................................................................................................... 59

13.25

INT_STATUS2 ..................................................................................................................................... 59

13.26

SIGNAL_PATH_RESET ........................................................................................................................ 59

13.27

INTF_CONFIG0 ................................................................................................................................... 59

13.28

INTF_CONFIG1 ................................................................................................................................... 61

13.29

PWR_MGMT0 .................................................................................................................................... 61

13.30

GYRO_CONFIG0 ................................................................................................................................. 62

13.31

ACCEL_CONFIG0 ................................................................................................................................ 63

13.32

GYRO_CONFIG1 ................................................................................................................................. 64

13.33

GYRO_ACCEL_CONFIG0 ..................................................................................................................... 65

13.34

ACCEL_CONFIG1 ................................................................................................................................ 66

13.35

TMST_CONFIG ................................................................................................................................... 66

13.36

WOM_CONFIG................................................................................................................................... 67

13.37

FIFO_CONFIG1 ................................................................................................................................... 67

13.38

FIFO_CONFIG2 ................................................................................................................................... 67

13.39

FIFO_CONFIG3 ................................................................................................................................... 68

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ICM-40609-D

14

15

13.40

FSYNC_CONFIG .................................................................................................................................. 68

13.41

INT_CONFIG0..................................................................................................................................... 69

13.42

INT_CONFIG1..................................................................................................................................... 69

13.43

INT_SOURCE0 .................................................................................................................................... 70

13.44

INT_SOURCE1 .................................................................................................................................... 70

13.45

INT_SOURCE3 .................................................................................................................................... 71

13.46

INT_SOURCE4 .................................................................................................................................... 71

13.47

FIFO_LOST_PKT0 ............................................................................................................................... 71

13.48

FIFO_LOST_PKT1 ............................................................................................................................... 72

13.49

SELF_TEST_CONFIG ........................................................................................................................... 72

13.50

WHO_AM_I ....................................................................................................................................... 72

13.51

REG_BANK_SEL .................................................................................................................................. 73

User Bank 1 Register Map – Descriptions......................................................................................................... 74
14.1

SENSOR_CONFIG0 ............................................................................................................................. 74

14.2

GYRO_CONFIG_STATIC2 .................................................................................................................... 74

14.3

GYRO_CONFIG_STATIC3 .................................................................................................................... 74

14.4

GYRO_CONFIG_STATIC4 .................................................................................................................... 75

14.5

GYRO_CONFIG_STATIC5 .................................................................................................................... 75

14.6

GYRO_CONFIG_STATIC6 .................................................................................................................... 75

14.7

GYRO_CONFIG_STATIC7 .................................................................................................................... 75

14.8

GYRO_CONFIG_STATIC8 .................................................................................................................... 76

14.9

GYRO_CONFIG_STATIC9 .................................................................................................................... 76

14.10

GYRO_CONFIG_STATIC10 .................................................................................................................. 76

14.11

XG_ST_DATA...................................................................................................................................... 77

14.12

YG_ST_DATA...................................................................................................................................... 77

14.13

ZG_ST_DATA ...................................................................................................................................... 77

14.14

TMSTVAL0 ......................................................................................................................................... 77

14.15

TMSTVAL1 ......................................................................................................................................... 77

14.16

TMSTVAL2 ......................................................................................................................................... 78

14.17

INTF_CONFIG4 ................................................................................................................................... 78

14.18

INTF_CONFIG5 ................................................................................................................................... 78

User Bank 2 Register Map – Descriptions......................................................................................................... 79
15.1

ACCEL_CONFIG_STATIC2 ................................................................................................................... 79

15.2

ACCEL_CONFIG_STATIC3 ................................................................................................................... 79

15.3

ACCEL_CONFIG_STATIC4 ................................................................................................................... 79

15.4

XA_ST_DATA ...................................................................................................................................... 79

15.5

YA_ST_DATA ...................................................................................................................................... 80

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ICM-40609-D
15.6
16

ZA_ST_DATA ...................................................................................................................................... 80

User Bank 4 Register Map – Descriptions......................................................................................................... 81
16.1

ACCEL_WOM_X_THR......................................................................................................................... 81

16.2

ACCEL_WOM_Y_THR ......................................................................................................................... 81

16.3

ACCEL_WOM_Z_THR ......................................................................................................................... 81

16.4

OFFSET_USER0 .................................................................................................................................. 81

16.5

OFFSET_USER1 .................................................................................................................................. 82

16.6

OFFSET_USER2 .................................................................................................................................. 82

16.7

OFFSET_USER3 .................................................................................................................................. 82

16.8

OFFSET_USER4 .................................................................................................................................. 82

16.9

OFFSET_USER5 .................................................................................................................................. 83

16.10

OFFSET_USER6 .................................................................................................................................. 83

16.11

OFFSET_USER7 .................................................................................................................................. 83

16.12

OFFSET_USER8 .................................................................................................................................. 83

17

Reference ......................................................................................................................................................... 84

18

Revision History ................................................................................................................................................ 85

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ICM-40609-D
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram ................................................................................................................................. 14
Figure 2. 4-Wire SPI Mode-3 Bus Timing Diagram ....................................................................................................... 15
Figure 3. 4-Wire SPI Mode-0 Bus Timing Diagram ....................................................................................................... 15
Figure 4. 3-Wire Mode-3 SPI Bus Timing Diagram ....................................................................................................... 16
Figure 5. 3-Wire Mode-0 SPI Bus Timing Diagram ....................................................................................................... 16
Figure 6. Pin Out Diagram for ICM-40609-D 3x3.0x0.91 mm LGA ............................................................................... 18
Figure 7. ICM-40609-D Application Schematic (I2C Interface to Host) ........................................................................ 19
Figure 8. ICM-40609-D Application Schematic (SPI Interface to Host) ........................................................................ 19
Figure 9. ICM-40609-D System Block Diagram ............................................................................................................ 21
Figure 10. ICM-40609-D Signal Path ............................................................................................................................ 24
Figure 11. FIFO Packet Structure ................................................................................................................................. 36
Figure 12. Maximum FIFO Storage .............................................................................................................................. 38
Figure 13. START and STOP Conditions ....................................................................................................................... 41
Figure 14. Acknowledge on the I2C Bus ....................................................................................................................... 42
Figure 15. Complete I2C Data Transfer ........................................................................................................................ 42
Figure 16. Typical SPI Master/Slave Configuration ...................................................................................................... 44
Figure 17. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................ 45

TABLE OF TABLES
Table 1. Gyroscope Specifications ............................................................................................................................... 10
Table 2. Accelerometer Specifications ........................................................................................................................ 11
Table 3. D.C. Electrical Characteristics ......................................................................................................................... 12
Table 4. A.C. Electrical Characteristics ......................................................................................................................... 13
Table 5. I2C Timing Characteristics............................................................................................................................... 14
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ................................................................................. 15
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ................................................................................. 16
Table 8. Absolute Maximum Ratings ........................................................................................................................... 17
Table 9. Signal Descriptions ......................................................................................................................................... 18
Table 10. Bill of Materials ............................................................................................................................................ 20
Table 11. Standard Power Modes for ICM-40609-D.................................................................................................... 23
Table 12. I2C Terms ...................................................................................................................................................... 43

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ICM-40609-D
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on
the ICM-40609-D Single-Interface MotionTracking device. The device is housed in a small 3x3x0.91 mm 24-pin LGA
package.

1.2 PRODUCT OVERVIEWThe ICM-40609-D is a 6-axis MotionTracking device that combines a 3-axis gyroscope, and a 3-axis accelerometerin a small 3x3x0.91 mm (24-pin LGA) package. It also features a 2 KB FIFO that can lower the traffic on the serial
bus interface and reduce power consumption by allowing the system processor to burst read sensor data and thengo into a low-power mode. ICM-40609-D, with its 6-axis integration, enables manufacturers to eliminate the costly
and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion
performance for consumers.
The gyroscope supports eight programmable full-scale range settings from ±15.625 dps to ±2000 dps, and theaccelerometer supports four programmable full-scale range settings from ±4g to ±32g.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The device features I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.71V to 3.6V.
The host interface can be configured to support I2C slave or SPI slave modes. The I2C interface supports speeds up
to 1 MHz, and the SPI interface supports speeds up to 24 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers
with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to afootprint and thickness of 3x3x0.91 mm (24-pin LGA), to provide a very small yet high-performance low-costpackage. The device provides high robustness by supporting 20,000g shock reliability.

1.3 APPLICATIONS•••

DronesRobotics
IoT Applications

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ICM-40609-D
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-40609-D includes a wide range of features:•

Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec•

Low Noise (LN) power mode support•

Digitally programmable low-pass filters•

Factory calibrated sensitivity scale factor•

Self-test

2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-40609-D includes a wide range of features:•

Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±4g, ±8g, ±16g and±32g•

Low Noise (LN) and Low Power (LP) power modes support•

User-programmable interrupts•

Wake-on-motion interrupt for low power operation of applications processor•

Self-test

2.3 ADDITIONAL FEATURES
ICM-40609-D includes the following additional features:•

2KB FIFO buffer enables the applications processor to read the data in bursts•

User-programmable digital filters for gyroscope, accelerometer, and temperature sensor•

Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold•

1 MHz I2C / 24 MHz SPI slave host interface•

Digital-output temperature sensor•

Smallest and thinnest LGA package for portable devices: 3 x 3 x 0.91 mm (24-pin LGA)•

20,000g shock tolerant•

MEMS structure hermetically sealed and bonded at wafer level•

RoHS and Green compliant

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ICM-40609-D
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

GYROSCOPE SENSITIVITY

Full-Scale Range

GYRO_FS_SEL=0
GYRO_FS_SEL =1

±2000

º/s

±1000

º/s

2
2

GYRO_FS_SEL =2

±500

º/s

2

GYRO_FS_SEL =3

±250

º/s

2

GYRO_FS_SEL =4

±125

º/s

2

GYRO_FS_SEL =5

±62.5

º/s

2

GYRO_FS_SEL =6±31.25º/s

2

GYRO_FS_SEL =7±15.625

º/s

2

16

bits

2

Gyroscope ADC Word Length
GYRO_FS_SEL=0
GYRO_FS_SEL =1

16.4

LSB/(º/s)232.8

LSB/(º/s)

2

GYRO_FS_SEL =265.5

LSB/(º/s)

2

GYRO_FS_SEL =3131

LSB/(º/s)

2

GYRO_FS_SEL =4262

LSB/(º/s)

2

GYRO_FS_SEL =5524.3

LSB/(º/s)

2

GYRO_FS_SEL =61048.6

LSB/(º/s)

2

GYRO_FS_SEL =72097.2

LSB/(º/s)

2

Sensitivity Scale Factor Initial Tolerance

25°C

±0.5

%

1

Sensitivity Scale Factor Variation Over
Temperature-40°C to +85°C±0.045%/ºC

3Nonlinearity

Best fit straight line; 25°C

±0.1

%

3

±1

%

3

Sensitivity Scale Factor

Cross-Axis Sensitivity
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance

Board-level, 25°C

±1

º/s

3

ZRO Variation vs. Temperature-40°C to +85°C±0.01º/s/ºC

3

OTHER PARAMETERS
Rate Noise Spectral Density@ 10 Hz0.0045º/s /√Hz

1

Total RMS Noise

Bandwidth = 100 Hz

0.045º/s-rms

4

Gyroscope Mechanical Frequencies
Low Pass Filter Response
Gyroscope Start-Up Time
Output Data Rate

25
ODR < 1kHz

5ODR ≥ 1kHzTime from gyro enable to gyro drive ready5

Table 1. Gyroscope Specifications
Notes:
1.
2.

3.
4.

Tested in production.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Calculated from Rate Noise Spectral Density.

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12.5

27

30

29

KHz

1

500

Hz

2

995

Hz
ms
Hz

2
3
2

32000

ICM-40609-D
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

ACCELEROMETER SENSITIVITYACCEL_FS_SEL =0±32g

ACCEL_FS_SEL =1

±16

g

2
2

ACCEL_FS_SEL =2

±8

g

2

ACCEL_FS_SEL =3

±4

g

2

Output in two’s complement format

16

bits

2

ACCEL_FS_SEL =0

1,024

LSB/g

2

ACCEL_FS_SEL =1

2,048

LSB/g

2

ACCEL_FS_SEL =2

4,096

LSB/g

2

ACCEL_FS_SEL =3
Component-level

8,192

LSB/g

2

±0.5

%

1

Sensitivity Change vs. Temperature-40°C to +85°C±0.007%/ºC

3Nonlinearity

Best Fit Straight Line, ±2g

±0.1

%

3

±1

%

3

Full-Scale Range

ADC Word Length

Sensitivity Scale Factor

Sensitivity Scale Factor Initial Tolerance

Cross-Axis Sensitivity
ZERO-G OUTPUT
Initial Tolerance

Board-level, all axes

±40

mg

3

Zero-G Level Change vs. Temperature-40°C to +85°C

±0.15

mg/ºC

3

100

µg/√Hz1

OTHER PARAMETERS
Power Spectral Density@ 10 HzRMS Noise

Bandwidth = 100 Hz

Low-Pass Filter Response
Accelerometer Startup Time
Output Data Rate
Notes:
1.
2.
3.
4.

1.00

ODR < 1kHz

5ODR ≥ 1kHz
From sleep mode to valid data

5
1.5625

Tested in production.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Calculated from Power Spectral Density.

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4

Hz

2

995

Hz
ms
Hz

2
3
2

10

Table 2. Accelerometer Specifications

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mg-rms500

32000

ICM-40609-D
3.3 ELECTRICAL SPECIFICATIONS
3.3.1

D.C. Electrical Characteristics

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

VDD

1.71

1.8

3.6

V

1

VDDIO

1.71

1.8

3.6

V

1

SUPPLY VOLTAGESSUPPLY CURRENTS
Low-Noise Mode

6-Axis Gyroscope + Accelerometer

0.77

mA

2

3-Axis Accelerometer

0.27

mA

2

3-Axis Gyroscope

0.61

mA

2

Accelerometer Low -Power Mode
(Gyroscope disabled)

200Hz ODR, 1x averaging

0.06

mA

2

Full-Chip Sleep ModeAt 25ºC

11µA

2

Specified Temperature Range

TEMPERATURE RANGE
Performance parameters are not applicablebeyond Specified Temperature Range

°C

1

-40

Table 3. D.C. Electrical Characteristics
Notes:
1.
2.

Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.

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ICM-40609-D
3.3.2

A.C. Electrical Characteristics

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONSMIN

SUPPLIES
Monotonic ramp. Ramp rate is 10% to 90% of
the final value

Supply Ramp Time

TYP

0.01

Power Supply Noise

UNITS

3

ms
mV
peak-peak

10

Operating Range
25°C Output
ADC Resolution
ODR
Room Temperature Offset
Stabilization Time
Sensitivity
Sensitivity for FIFO data

Ambient

Start-up time for register read/write

From power-up

TEMPERATURE SENSOR

With Filter
25°C

-40

25
-5

Untrimmed

016

132.482.07

POWER-ON RESET
AP_AD0 = 0
AP_AD0 = 1

I2C ADDRESSI2C ADDRESS

85

CI, Input Capacitance

1

ms

1

0.3*VDDIO

V

8000
5
14000

V

RLOAD=1 MΩ;

VOL.INT, INT Low-Level Output Voltage
Output Leakage Current

OPEN=1, 0.3 mA sink
Current
OPEN=1tINT, INT Pulse Width

int_tpulse_duration= 0 , 1 (100us, 8us ) ;V
0.1*VDDIO

V

0.1

V

100

VIH, HIGH-Level Input Voltage

nA

8

100

µs

-0.5 V

0.3*VDDIO

V

0.7*VDDIOVDDIO +
0.5 V

VVhys, Hysteresis

0.1*VDDIO
3 mA sink current0

VOL=0.4 V
VOL=0.6 V

Clock Frequency Initial Tolerance
Frequency Variation over Temperature

20+0.1Cb

V

1

mA
mA

100
Cb bus capacitance in pf

nA
300

ns

INTERNAL CLOCK SOURCE
CLKSEL=`2b00 or gyro inactive; 25°C
-3

+3

%

1

CLK_SEL=`2b01 and gyro active; 25°C

+1

%

1

CLK_SEL=`2b00 or gyro inactive; -40°C to +85°C

±3

%

1

CLK_SEL=`2b01 and gyro active; -40oC to +85oC

±2

%

1

-1

Table 4. A.C. Electrical Characteristics
Expected results based on design, will be updated after characterization. Not guaranteed in production.
Guaranteed by design.
To be Production tested.

Document Number: DS-000330
Revision: 1.2

V
0.4

3
6

Output Leakage Current
tof, Output Fall Time from VIHmax to VILmax

1

I2C I/O (SCL, SDA)

VIL, LOW-Level Input Voltage

VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current

1

pF

DIGITAL OUTPUT (SDO, INT1, INT2)
0.9*VDDIO

VOL1, LOW-Level Output Voltage

1

1
3
2
2
3
2
1
1

< 10
RLOAD=1 MΩ;

11101000
1101001

VIL, Low Level Input Voltage

VOH, High Level Output Voltage

NOTES

°C
LSB
bits
Hz
°C
µs
LSB/°C
LSB/°CDIGITAL INPUTS (FSYNC, SCLK, SDI, CS)
0.7*VDDIO

VIH, High Level Input Voltage

Notes:
1.
2.
3.

MAX

Page 13 of 86

ICM-40609-D
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS

CONDITIONS

I2C TIMING

I2C FAST-MODE PLUSMIN

TYPICALfSCL, SCL Clock Frequency

MAX

UNITS

NOTES

1

MHz

1

tHD.STA, (Repeated) START Condition Hold Time

0.26

µs

1

tLOW, SCL Low Period

0.5

µs

1

tHIGH, SCL High Period

0.26

µs

1

tSU.STA, Repeated START Condition Setup Time

0.26

µs

1

tHD.DAT, SDA Data Hold Time

0

µs

1

tSU.DAT, SDA Data Setup Time50

tr, SDA and SCL Rise TimeCb bus cap. from 10 to 400 pF

tf, SDA and SCL Fall TimeCb bus cap. from 10 to 400 pF

120
120

ns

1

ns

1

ns

1

tSU.STO, STOP Condition Setup Time

0.5

µs

1

tBUF, Bus Free Time Between STOP and START
Condition

0.5

µs

1

Cb, Capacitive Load for each Bus LinepF

1

tVD.DAT, Data Valid Time

< 400
0.45

µs

1

tVD.ACK, Data Valid Acknowledge Time

0.45

µs

1

Table 5. I2C Timing Characteristics
Notes:
1.

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tf

SDA

tSU.DAT

tr
70%
30%

70%
30%

tf
SCL
S

SDA

SCL

tHD.STA

tr
70%
30%

70%
30%

tHD.DAT
1/fSCLtLOW

1st clock cycle

tBUF

tHD.STAtSU.STA
Sr

70%
30%

tSU.STO

tVD.ACK
9th clock cycle

Figure 1. I2C Bus Timing Diagram

Document Number: DS-000330
Revision: 1.2

9th clock cycle

tHIGH

70%
30%

A

continued below at

tVD.DAT

Page 14 of 86

P

S

A

ICM-40609-D
3.5 SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

24

MHz

1

SPI TIMING
Default

fSPC, SCLK Clock FrequencytLOW, SCLK Low Period

24.5

ns

1

tHIGH, SCLK High Period

24.5

ns

1

tSU.CS, CS Setup Time

39

ns

1

tHD.CS, CS Hold Time

18

ns

1

tSU.SDI, SDI Setup Time

13

ns

1

tHD.SDI, SDI Hold Time

8

ns

1

tVD.SDO, SDO Valid Time

Cload = 20 pF

tHD.SDO, SDO Hold Time

Cload = 20 pF

21.5
9.5
28

tDIS.SDO, SDO Output Disable Time

ns

1

ns

1

ns

1

Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1.
2.

CS

SCLK

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
Based on other parameter values
70%
30%

tSU;CS

SDI

70%
30%

70%
30%

tHIGH

1/fCLKMSB OUT

70%
30%

Figure 3. 4-Wire SPI Mode-0 Bus Timing Diagram

Page 15 of 86

tDIS;SDO

tHD;SDO

Figure 2. 4-Wire SPI Mode-3 Bus Timing Diagram

Document Number: DS-000330
Revision: 1.2

tHD;CSLSB INMSB INtVD;SDO

SDO

tRise

tLOW

tHD;SDItSU;SDItFall

LSB OUTICM-40609-D
3.6 SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

24

MHz

1

SPI TIMING
Default

fSPC, SCLK Clock FrequencytLOW, SCLK Low Period

24.5

ns

1

tHIGH, SCLK High Period

24.5

ns

1

tSU.CS, CS Setup Time

39

ns

1

tHD.CS, CS Hold Time

5

ns

1

tSU.SDIO, SDIO Input Setup Time

13

ns

1

tHD.SDIO, SDIO Input Hold Time

8

ns

1

tVD.SDIO, SDIO Output Valid Time

Cload = 20 pF

tHD.SDIO, SDIO Output Hold Time

Cload = 20 pF

18.5
9.5
28

tDIS.SDIO, SDIO Output Disable Time

ns

1

ns

1

ns

1

Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation)

Notes:
1.
2.

CS

SCLK

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
Based on other parameter values
70%
30%

tSU;CS

SDIO

I

O

70%
30%

70%
30%

tHIGH
tSU;SDIO

1/fCLK

tFall

tRise

tLOW

tHD;SDIOLSB INMSB INtVD;SDIOMSB OUT

70%
30%

Figure 5. 3-Wire Mode-0 SPI Bus Timing Diagram

Page 16 of 86

tDIS;SDIOtHD;SDIO

Figure 4. 3-Wire Mode-3 SPI Bus Timing Diagram

Document Number: DS-000330
Revision: 1.2

tHD;CSLSB OUTICM-40609-D
3.7 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These arestress ratings only and functional operation of the device at these conditions is not implied. Exposure to theabsolute maximum ratings conditions for extended periods may affect device reliability.
PARAMETERRATING

Supply Voltage, VDD-0.5V to +4V

Supply Voltage, VDDIO-0.5V to +4V

Input Voltage Level (FSYNC, SCL, SDA)

-0.5V to VDDIO + 0.5V

Acceleration (Any Axis, unpowered)

20,000g for 0.2 ms

Operating Temperature Range-40°C to +85°C

Storage Temperature Range-40°C to +125°C
2 kV (HBM);

Electrostatic Discharge (ESD) Protection

200V (MM)JEDEC Class II (2),125°C

Latch-up±100 mA
Table 8. Absolute Maximum Ratings

Document Number: DS-000330
Revision: 1.2

Page 17 of 86

ICM-40609-D
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTIONPIN NUMBERPIN NAME

8VDDIOPIN DESCRIPTION

9

AD0 / SDO

11

RESV

12

INT1 / INT

13

VDD

Power supply voltage

18

GND

19

INT2 / FSYNC

20

RESV

Power supply groundINT2: Interrupt 2
FSYNC: Frame sync input; Connect to GND if FSYNC selected but
FSYNC signal not input
Reserved, connect to GND

22

nCS

Chip select (SPI mode only)

23

SCL / SCLK

Digital I/O supply voltage
AD0: I2C Slave Address LSB
SDO: SPI serial data output (4-wire mode)
RESV: Connect to GND
INT1: Interrupt 1
INT: Interrupt if all interrupts mapped to pin 12

SCL: I2C serial clock
SCLK: SPI serial clock

24

SDA / SDI / SDIO

1 – 7, 10, 14 – 17, 21

NC

SDA: I2C serial data
SDI: SPI serial data input (4-wire mode)
SDIO: SPI serial data I/O (3-wire mode)
No Connect pins. Do not connect.

SDA / SDI / SDIOSCL / SCLK

nCS

NC

RESV

INT2 / FSYNC

24

23

22

21

20

19

Table 9. Signal DescriptionsNC

1

18 GND

NC

2

17 NC

NC

3

NC

4

NC

5

14 NC

NC

6

13 VDD
7

8

9

10

11

12

NC

VDDIO

SDO / AD0

NC

RESV

INT1 / INT

ICM-40609-D

16 NC
15 NC

Figure 6. Pin Out Diagram for ICM-40609-D 3x3.0x0.91 mm LGA

Document Number: DS-000330
Revision: 1.2

Page 18 of 86

ICM-40609-D
4.2 TYPICAL OPERATING CIRCUITRESVINT2 /
FSYNC

20

19

21 NC

nCS
22

23

SDA / SDI /SDIO
24

SCL / SCLK

VDDIO

SCL
SDA

GND

NC

1

18

NC

2

17 NC
16 NC

NC

3

NC

4

NC

5

14 NC

NC

6

13 VDD

1.71 – 3.6VDC

11

12
INT1

NC 10

RESV

SDO / AD0

9

8

NC
VDDIO

7

ICM-40609-D

15 NC

C1, 0.1 µF

1.71 – 3.6VDC

C2, 2.2 µF

C3, 10 nF

AD0

Figure 7. ICM-40609-D Application Schematic (I2C Interface to Host)

Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.

nCS

NC

RESV

INT2 /
FSYNC

22

21

20

19

23

SDA / SDI /SDIO
24

SCL / SCLK

nCS

SCLK
SDI / SDIO

GND

NC

1

18

NC

2

17 NC

NC

3

NC

4

NC

5

14 NC

NC

6

13 VDD

11

12
INT1

NC 10

9
SDO / AD0

1.71 – 3.6VDC

RESV

8

7

NC
VDDIO

ICM-40609-D

16 NC
15 NC

C1, 0.1 µF

1.71 – 3.6VDC

C2, 2.2 µF

C3, 10 nF

SDO

Figure 8. ICM-40609-D Application Schematic (SPI Interface to Host)

Document Number: DS-000330
Revision: 1.2

Page 19 of 86

ICM-40609-D
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTSCOMPONENTLABELSPECIFICATIONQUANTITYVDD Bypass Capacitors

C1
C2

X7R, 0.1µF ±10%
X7R, 2.2µF ±10%

1
1

VDDIO Bypass Capacitor

C3

X7R, 10nF ±10%

1Table 10. Bill of Materials

Document Number: DS-000330
Revision: 1.2

Page 20 of 86

ICM-40609-D
4.4 SYSTEM BLOCK DIAGRAM

Figure 9. ICM-40609-D System Block Diagram

Note: The block diagram in Figure 9 is an example. Please refer to the pin-out (section 4.1) for other configuration
options.

4.5 OVERVIEWThe ICM-40609-D is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•

Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
I2C and SPI serial communications interfaces to Host
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes

4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONINGThe ICM-40609-D includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes.
When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detectedby a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is
proportional to the angular rate. This voltage is digitized using on-chip Analog-to-Digital Converters (ADCs) to
sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±15.625, ±31.25, ±62.5,±125, ±250, ±500, ±1000, and ±2000 degrees per second (dps).

4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONINGThe ICM-40609-D includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacementof a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The ICM-40609-D
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. Whenthe device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The
accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The fullscale range of the digital output can be adjusted to ±4g, ±8g, ±16g and ±32g.

4.8 I2C AND SPI HOST INTERFACEThe ICM-40609-D communicates to the application processor using an I2C, or SPI serial interface. The ICM-40609-D
always acts as a slave when communicating to the application processor.

4.9 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for eachmeasurement axis can be activated by means of the gyroscope and accelerometer self-test registers.

Document Number: DS-000330
Revision: 1.2

Page 21 of 86

ICM-40609-D
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The
output signal is used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, thepart has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to havefailed self-test.

4.10 CLOCKING
The ICM-40609-D has a flexible clocking scheme, allowing the following internal clock sources to be used for theinternal synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various
control circuits and registers.
a) An internal relaxation oscillatorb) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available
sourceThe only setting supporting specified performance in all modes is option b). It is recommended that option b) be
used when using internal clock source.

4.11 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They
are read-only registers and are accessed via the serial interface. Data from these registers may be read anytime.

4.12 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include theinterrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock
sources); (2) new data is available to be read (from the FIFO and Data registers); (3) accelerometer event
interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be read from the Interrupt Status
register.

4.13 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-40609-D die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
Temperature data value from the sensor data registers can be converted to degrees centigrade by using thefollowing formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigradeby using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25

4.14 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the
ICM-40609-D.

4.15 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.

Document Number: DS-000330
Revision: 1.2

Page 22 of 86

ICM-40609-D
4.16 STANDARD POWER MODES
Table 11 lists the user-accessible power modes for ICM-40609-D.
MODE
1
2
3
4
5
6

NAME
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode

GYRO
Off
Drive On
Off
Off
On
On

Table 11. Standard Power Modes for ICM-40609-D

Document Number: DS-000330
Revision: 1.2

Page 23 of 86

ACCEL
Off
Off
Duty-Cycled
On
Off
On

ICM-40609-D
5 SIGNAL PATH
Figure 10 shows a block diagram of the signal path for ICM-40609-D.

ADC

Decimation
Filter(32kHz)Gyro Only
Notch Filter

Anti-Alias
Filter (AAF)

0

0
1

1

User
Programmable
OffsetUI Filter Block(order, BW, ODR)

SensorRegisters
FSR Selection

GYRO_NF_DIS

AAF_DIS

Figure 10. ICM-40609-D Signal Path

The signal path starts with independent 16-bit ADCs for each axis of gyroscope and accelerometer. The ADC output
goes through a Decimation Filter that has fixed bandwidth of 32 kHz for ICM-40609-D. Other components of thesignal path are described below in further detail.

5.1 NOTCH FILTERThe Notch Filter is supported only for the gyroscope signal path. The following steps can be used to program thenotch filter. Note that the notch filter is specific to each axis in the gyroscope, so the X, Y, and Z axis can be
programmed independently.
5.1.1

Frequency of Notch Filter (each axis)

To operate the Notch filter, two parameters NF_COSWZ, and NF_COSWZ_SEL must be programmed for eachgyroscope axis.
Parameters NF_COSWZ are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ (register bank 1, register
0x0Fh & register 0x12h), GYRO_Y_NF_COSWZ (register bank 1, register 0x10h & register 0x12h),
GYRO_Z_NF_COSWZ (register bank 1, register 0x11h & register 0x12h). Note that the parameters have 9-bit values
across two different registers.
Parameters NF_COSWZ_SEL are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ_SEL (register bank
1, register 0x12h, bit 3), GYRO_Y_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 4), GYRO_Z_NF_COSWZ_SEL(register bank 1, register 0x12h, bit 5).
Each value must be calculated using the steps described below and programmed into the corresponding register
locations mentioned above.
fdesired is the desired frequency of the Notch Filter in kHz. The lower bound for fdesired is 1 kHz, and the upperbound is 3 kHz. Operating the notch filter outside this range is not supported.
Step1: COSWZ = cos(2*pi*fdesired/32)
Step2:
If abs(COSWZ)≤0.875
NF_COSWZ = round[COSWZ*256]
NF_COSWZ_SEL = 0
else
NF_COSWZ_SEL = 1
if COSWZ > 0.875
NF_COSWZ = round [8*(1-COSWZ)*256]
else if COSWZ < -0.875
NF_COSWZ = round [-8*(1+COSWZ)*256]
end
End

Document Number: DS-000330
Revision: 1.2

Page 24 of 86

UI InterfaceICM-40609-D
5.1.2

Bandwidth of Notch Filter (common to all axes)

The notch filter allows the user to control the width of the notch from eight possible values using a 3-bit parameter
GYRO_NF_BW_SEL in register bank 1, register 0x13h, bits 6:4. This parameter is common to all three axes.
GYRO_NF_BW_SEL

Notch Filter Bandwidth (Hz)

0

1449

1

680

2

329

3

162

4

80

5

40

6

20

7
10
The notch filter can be selected or bypassed by using the parameter GYRO_NF_DIS in register bank 1, register
0x0Bh, bit 0 as shown below.
GYRO_NF_DIS

Function0

Enable notch filter

1

Disable notch filter

5.2 ANTI-ALIAS FILTER
Anti-alias filters for gyroscope and accelerometer can be independently programmed to have bandwidths ranging
from 10 Hz to 995 Hz. To program the anti-alias filter for a required bandwidth, use the table below to map the
bandwidth to register values as shown:
a.
b.
c.
d.
e.
f.

Register bank 2, register 0x03h, bits 6:1, ACCEL_AAF_DELT: Code from 1 to 63 that allows
programming the bandwidth for accelerometer anti-alias filter
Register bank 2, register 0x04h, bits 7:0 and Bank 2, register 0x05h, bits 3:0,
ACCEL_AAF_DELTSQR: Square of the delt value for accelerometer
Register bank 2, register 0x05h, bits 7:4, ACCEL_AAF_BITSHIFT: Bitshift value for accelerometerused in hardware implementation
Register bank 1, register 0x0Ch, bits 5:0, GYRO_AAF_DELT: Code from 1 to 63 that allows
programming the bandwidth for gyroscope anti-alias filter
Register bank 1, register 0x0Dh, bits 7:0 and Bank 1, register 0x0Eh, bits 3:0,
GYRO_AAF_DELTSQR: Square of the delt value for gyroscope
Register bank 1, register 0x0Eh, bits 7:4, GYRO_AAF_BITSHIFT: Bitshift value for gyroscope usedin hardware implementation

Document Number: DS-000330
Revision: 1.2

Page 25 of 86

ICM-40609-D
3dB Bandwidth (Hz)
42
84
126
170
213
258
303
348
394
441
488
536
585
634
684
734
785
837
890
943
997
1051
1107
1163
1220
1277
1336
1395
1454
1515
1577
1639
1702
1766
1830
1896
1962
2029
2097
2166

Document Number: DS-000330
Revision: 1.2

ACCEL_AAF_DELT; ACCEL_AAF_DELTSQR; ACCEL_AAF_BITSHIFT;GYRO_AAF_DELT GYRO_AAF_DELTSQR GYRO_AAF_BITSHIFT
1
1
15
2
4
13
3
9
12
4
16
11
5
25
10
6
36
10
7
49
9
8
64
9
9
81
9
10
100
8
11
122
8
12
144
8
13
170
8
14
196
7
15
224
7
16
256
7
17
288
7
18
324
7
19
360
6
20
400
6
21
440
6
22
488
6
23
528
6
24
576
6
25
624
6
26
680
6
27
736
5
28
784
5
29
848
5
30
896
5
31
960
5
32
1024
5
33
1088
5
34
1152
5
35
1232
5
36
1296
5
37
1376
4
38
1440
4
39
1536
4
40
1600
4

Page 26 of 86

ICM-40609-D
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

2235
2306
2377
2449
2522
2596
2671
2746
2823
2900
2978
3057
3137
3217
3299
3381
3464
3548
3633
3718
3805
3892
3979

1696
1760
1856
1952
2016
2112
2208
2304
2400
2496
2592
2720
2816
2944
3008
3136
3264
3392
3456
3584
3712
3840
3968

4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3

The anti-alias filter can be selected or bypassed for the gyroscope by using the parameter GYRO_AAF_DIS in
register bank 1, register 0x0Bh, bit 1 as shown below.
GYRO_AAF_DIS

Function0

Enable gyroscope anti-aliasing filter

1

Disable gyroscope anti-aliasing filter

The anti-alias filter can be selected or bypassed for the accelerometer by using the parameter ACCEL_AAF_DIS in
register bank 2, register 0x03h, bit 0 as shown below.
ACCEL_AAF_DIS

Function0

Enable accelerometer anti-aliasing filter

1

Disable accelerometer anti-aliasing filter

5.3 USER PROGRAMMABLE OFFSET
Gyroscope and accelerometer offsets can be programmed by the user by using registers OFFSET_USER0, through
OFFSET_USER8, in bank 0, registers 0x77h through 0x7Fh (bank 4) as shown below.

Document Number: DS-000330
Revision: 1.2

Page 27 of 86

ICM-40609-D
REGISTER ADDRESSREGISTER NAME

BITS

0x77h

OFFSET_USER0

7:0

0x78h

OFFSET_USER10x79h

OFFSET_USER2

7:0

0x7Ah

OFFSET_USER3

7:0

0x7Bh

OFFSET_USER40x7Ch

OFFSET_USER5

7:0

0x7Dh

OFFSET_USER6

7:0

0x7Eh

OFFSET_USER7

0x7Fh

OFFSET_USER8

3:0
7:4

3:0
7:4

3:0
7:4
7:0

FUNCTION
Lower bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Lower bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Lower bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Upper bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Upper bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.

5.4 UI FILTER BLOCKThe UI filter block can be programmed to select filter order and bandwidth independently for gyroscope andaccelerometer.
Gyroscope filter order can be selected by programming the parameter GYRO_UI_FILT_ORD in register bank 0,
register 0x51h, bits 3:2, as shown below.
GYRO_UI_FILT_ORD

Filter Order00

1st order01

2nd order10

3rd order

11

Reserved

Accelerometer filter order can be selected by programming the parameter ACCEL_UI_FILT_ORD in register bank 0,
register 0x53h, bits 4:3, as shown below.

Document Number: DS-000330
Revision: 1.2

ACCEL_UI_FILT_ORD

Filter Order00

1st order01

2nd order10

3rd order

11

Reserved

Page 28 of 86

ICM-40609-D
Gyroscope and accelerometer filter 3dB bandwidth can be selected by programming the parameter
GYRO_UI_FILT_BW in register bank 0, register 0x52h, bits 3:0, and the parameter ACCEL_UI_FILT_BW in registerbank 0, register 0x52h, bits 7:4, as shown below. The values shown in bold correspond to low noise and the values
shown in italics correspond to low latency. User can select the appropriate setting based on the application
requirements for power and latency. Corresponding Noise Bandwidth (NBW) and Group Delay values are also
shown.
1st Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay

5.4.1

3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR

1
2
3
4
5
6
15
7
8
9
10
11

ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

0

1

2

3

498.3
249.1
99.6
49.8
24.9
12.5
12.5

227.2
113.6
90.9
90.9
90.9
90.9
90.9

188.9
94.4
75.5
75.5
75.5
75.5
75.5

111.0
55.5
44.4
44.4
44.4
44.4
44.4

4
5
8400.04194.12096.31048.1524.0
92.4 59.6
46.2 29.8
37.0 23.8
37.0 23.8
37.0 23.8
37.0 23.8
37.0 23.8

6

7

14

15

48.8 23.9
24.4 11.9
19.5 9.6
19.5 9.6
19.5 9.6
19.5 9.6
19.5
9.6

262.0
131.0
104.8
104.8
104.8
104.8
104.8

2096.31048.1
419.2
209.6
104.8
52.4
52.4

NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR

1
2
3
4
5
6
15
7
8
9
10
11

ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

0

1

2

3

551.1
280.5
112.2
56.1
28.1
14.1
14.1

230.8
115.4
92.4
92.4
92.4
92.4
92.4

196.3
98.2
78.5
78.5
78.5
78.5
78.5

126.5
63.3
50.6
50.6
50.6
50.6
50.6

4
5
8831.74410.62204.61102.2551.1
108.9 75.8
54.5 37.9
43.6 30.3
43.6 30.3
43.6 30.3
43.6 30.3
43.6 30.3

6

7

14

15

64.1
32.1
25.7
25.7
25.7
25.7
25.7

34.1
17.1
13.7
13.7
13.7
13.7
13.7

275.6
137.8
110.3
110.3
110.3
110.3
110.3

2204.61102.2
440.9
220.5
110.3
55.2
55.2

Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR

1

Document Number: DS-000330
Revision: 1.2

ODR(Hz)
32000

0

1

2

Page 29 of 86

3

4

5
0.1

6

7

14

15

ICM-40609-D
2
3
4
5

16000
8000
4000
2000
1000
500
200
100
50
25
12.5

6
15
7
8
9
10
11
5.4.2

0.1
0.2
0.4
0.8
0.6
1.1
2.7
5.3
10.5
21.0
21.0

1.8
3.6
4.4
4.4
4.4
4.4
4.4

2.0
4.0
5.0
5.0
5.0
5.0
5.0

2.8
5.5
6.8
6.8
6.8
6.8
6.8

3.1
6.1
7.6
7.6
7.6
7.6
7.6

4.1
8.1
10.2
10.2
10.2
10.2
10.2

4.7
9.3
11.7
11.7
11.7
11.7
11.7

8.1
16.2
20.3
20.3
20.3
20.3
20.3

1.5
3.0
3.8
3.8
3.8
3.8
3.8

0.2
0.4
1.0
1.9
3.8
7.5
7.5

2nd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay

GYRO/ACCEL_ODR

1
2
3
4
5
6
15
7
8
9
10
11

ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

Document Number: DS-000330
Revision: 1.2

3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
0
1
2
3
4
5
6
7
14

493.3
246.7
98.7
49.3
24.7
12.3
12.3

230.7
115.3
92.3
92.3
92.3
92.3
92.3

191.6
95.8
76.6
76.6
76.6
76.6
76.6

117.5
58.8
47.0
47.0
47.0
47.0
47.0

Page 30 of 86

8400.04194.12096.31048.1524.0
97.1 59.6
48.5 29.8
38.8 23.8
38.8 23.8
38.8 23.8
38.8 23.8
38.8 23.8

48.0 21.3
24.0 10.6
19.2 8.5
19.2 8.5
19.2 8.5
19.2 8.5
19.2
8.5

262.0
131.0
104.8
104.8
104.8
104.8
104.8

15

2096.31048.1
419.2
209.6
104.8
52.4
52.4

ICM-40609-D
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR

1
2
3
4
5
6
15
7
8
9
10
11

ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

0

551.1
259.6
103.9
52.0
26.0
13.0
13.0

1

2

223.7
111.9
89.5
89.5
89.5
89.5
89.5

3

189.9
95.0
76.0
76.0
76.0
76.0
76.0

4

122.7
61.4
49.1
49.1
49.1
49.1
49.1

5

8831.74410.62204.61102.2551.1
102.8 64.7
51.4 32.4
41.2 25.9
41.2 25.9
41.2 25.9
41.2 25.9
41.2 25.9

6

7

52.5 23.7
26.3 11.9
21.0 9.5
21.0 9.5
21.0 9.5
21.0 9.5
21.0
9.5

14

15

275.6
137.8
110.3
110.3
110.3
110.3
110.3

2204.61102.2
440.9
220.5
110.3
55.2
55.2

Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODRODR(Hz)

1
2
3
4
5

32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

6
15
7
8
9
10
11

Document Number: DS-000330
Revision: 1.2

0

1

2

3

4

5

6

7

14

15

6.1
12.2
15.3
15.3
15.3
15.3
15.3

12.0
24.0
30.0
30.0
30.0
30.0
30.0

1.5
3.0
3.8
3.8
3.8
3.8
3.8

0.2
0.4
1.0
1.9
3.8
7.5
7.5

0.1
0.1
0.2
0.4
0.8
0.7
1.3
3.3
6.5
12.9
25.7
25.7

2.1
4.1
5.1
5.1
5.1
5.1
5.1

2.4
4.7
5.8
5.8
5.8
5.8
5.8

Page 31 of 86

3.2
6.4
8.0
8.0
8.0
8.0
8.0

3.7
7.3
9.1
9.1
9.1
9.1
9.1

5.2
10.4
12.9
12.9
12.9
12.9
12.9

ICM-40609-D
5.4.3

3rd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_UI_FILT_BW
0
1
2
3
4
5
6
7
14

GYRO/ACCEL_ODRODR(Hz)

1
2
3
4
5

32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

492.9
246.4
98.6
49.3
24.6
12.3
12.3

GYRO/ACCEL_ODRODR(Hz)NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
0
1
2
3
4
5
6
7
14

1
2
3
4
5

32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

6
15
7
8
9
10
11

6
15
7
8
9
10
11

Document Number: DS-000330
Revision: 1.2

551.1
252.0
100.8
50.4
25.2
12.6
12.6

234.7
117.4
93.9
93.9
93.9
93.9
93.9

221.3
110.7
88.6
88.6
88.6
88.6
88.6

195.8
97.9
78.3
78.3
78.3
78.3
78.3

188.5
94.3
75.4
75.4
75.4
75.4
75.4

118.9
59.5
47.6
47.6
47.6
47.6
47.6

120.1
60.1
48.1
48.1
48.1
48.1
48.1

Page 32 of 86

8400.04194.12096.31048.1524.0
97.9 60.8
48.9 30.4
39.2 24.3
39.2 24.3
39.2 24.3
39.2 24.3
39.2 24.3

8831.74410.62204.61102.2551.1
100.0 62.9
50.0 31.5
40.0 25.2
40.0 25.2
40.0 25.2
40.0 25.2
40.0 25.2

46.8
23.4
18.7
18.7
18.7
18.7
18.7

48.6
24.3
19.5
19.5
19.5
19.5
19.5

25.2
12.6
10.1
10.1
10.1
10.1
10.1

26.4
13.2
10.6
10.6
10.6
10.6
10.6

262.0
131.0
104.8
104.8
104.8
104.8
104.8

275.6
137.8
110.3
110.3
110.3
110.3
110.3

15

2096.31048.1
419.2
209.6
104.8
52.4
52.4

15

2204.61102.2
440.9
220.5
110.3
55.2
55.2

ICM-40609-DGroup Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODRODR(Hz)

1
2
3
4
5

32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5

6
15
7
8
9
10
11

0

1

2

3

4

5

6

7

14

15

6.6
13.2
16.5
16.5
16.5
16.5
16.5

8.2
16.3
20.4
20.4
20.4
20.4
20.4

14.1
28.1
35.2
35.2
35.2
35.2
35.2

1.5
3.0
3.8
3.8
3.8
3.8
3.8

0.2
0.4
1.0
1.9
3.8
7.5
7.5

0.1
0.1
0.2
0.4
0.8
0.8
1.6
4.0
8.0
15.9
31.8
31.8

2.3
4.6
5.8
5.8
5.8
5.8
5.8

2.7
5.4
6.8
6.8
6.8
6.8
6.8

4.0
7.9
9.8
9.8
9.8
9.8
9.8

4.6
9.2
11.4
11.4
11.4
11.4
11.4

5.5 ODR AND FSR SELECTION
Gyroscope ODR can be selected by programming the parameter GYRO_ODR in register bank 0, register 0x4Fh, bits
3:0 as shown below.

Document Number: DS-000330
Revision: 1.2

GYRO_ODR

Gyroscope ODR Value

0000

Reserved0001

32 kHz0010

16 kHz

0011

8 kHz

0100

4 kHz

0101

2 kHz

0110

1 kHz (default)

0111

200 Hz1000

100 Hz

1001

50 Hz

1010

25 Hz

1011

12.5 Hz

1100

Reserved

1101

Reserved

1110

Reserved

1111

500 HzPage 33 of 86

ICM-40609-D
Gyroscope FSR can be selected by programming the parameter GYRO_FS_SEL in register bank 0, register 0x4Fh,
bits 7:5 as shown below.
GYRO_FS_SEL

Gyroscope FSR Value000±2000 dps

001

±1000 dps

010

±500 dps

011±250 dps

100±125 dps

101±62.5 dps

110±31.25 dps

111±15.625 dps

Accelerometer ODR can be selected by programming the parameter ACCEL_ODR in register bank 0, register 0x50h,
bits 3:0 as shown below.

Document Number: DS-000330
Revision: 1.2

ACCEL_ODR

Accelerometer ODR Value

0000

Reserved0001

32 kHz0010

16 kHz

0011

8 kHz

0100

4 kHz

0101

2 kHz

0110

1 kHz (default)

0111

200 Hz1000

100 Hz

1001

50 Hz

1010

25 Hz

1011

12.5 Hz1100

6.25 Hz1101

3.125 Hz1110

1.5625 Hz

1111

500 HzPage 34 of 86

ICM-40609-D
Accelerometer FSR can be selected by programming the parameter ACCEL_FS_SEL in register bank 0, register
0x50h, bits 7:5 as shown below.

Document Number: DS-000330
Revision: 1.2

ACCEL_FS_SEL

Accelerometer FSR Value

000

±32g

001

±16g

010

±8g

011

±4g

100

Reserved

101

Reserved

110

Reserved

111

Reserved

Page 35 of 86

ICM-40609-D
6 FIFOThe ICM-40609-D contains a 2 KB FIFO register that is accessible via the serial interface. The FIFO configuration
register determines which data is written into the FIFO. Possible choices include gyroscope data, accelerometer
data, temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data arecontained in the FIFO.

6.1 PACKET STRUCTURE
The following figure shows the FIFO packet structures supported in ICM-40609-D.

Header(1 byte)Header(1 byte)Header(1 byte)Accelerometer Data
(6 bytes)

Gyroscope Data
(6 bytes)

Accelerometer Data
(6 bytes)

Temperature Data
(1 byte)Temperature Data
(1 byte)Packet 1

Packet 2

Gyroscope Data
(6 bytes)
Temperature Data
(1 byte)TimeStamp(2 bytes)
Packet 3

Figure 11. FIFO Packet Structure

The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.
Packet 1: Individual data is packaged in Packet 1 as shown below.
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07

Document Number: DS-000330
Revision: 1.2

Content
FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]Temperature[7:0]

Page 36 of 86

ICM-40609-D
Packet 2: Individual data is packaged in Packet 2 as shown below.
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07

Content
FIFO Header
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]Temperature[7:0]

Packet 3: Individual data is packaged in Packet 3 as shown below.
Byte

Content

0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F

FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]Temperature[7:0]
TimeStamp[15:8]
TimeStamp[7:0]

6.2 FIFO HEADER
The following table shows the structure of the 1-byte FIFO header.
BIT FIELD

ITEM

7HEADER_MSG

6HEADER_ACCEL

5HEADER_GYRO

3:2

HEADER_TIMESTAMP_FSYNC

1

HEADER_ODR_ACCEL

Document Number: DS-000330
Revision: 1.2

DESCRIPTION
1: FIFO is empty
0: Packet contains sensor data
1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN
must be 1
0: Packet does not contain accel sample
1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN mustbe 1
0: Packet does not contain gyro sample
00: Packet does not contain timestamp or FSYNC time data
01: Reserved
10: Packet contains ODR Timestamp
11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC(only if FIFO_TMST_FSYNC_EN is 1)
1: The ODR for accel is different for this accel data packet compared to the previous
accel packet

Page 37 of 86

ICM-40609-D
0

HEADER_ODR_GYRO

0: The ODR for accel is the same as the previous packet with accel
1: The ODR for gyro is different for this gyro data packet compared to the previous
gyro packet
0: The ODR for gyro is the same as the previous packet with gyro

Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set.

6.3 MAXIMUM FIFO STORAGE
The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As
shown in the figure below, the physical FIFO size is 2048 bytes. A number of bytes equal to the packet size selected(see section 6.1) is reserved to prevent reading a packet during write operation. Additionally, a read cache 2
packets wide is available.
When there is no serial interface operation, the read cache is not available for storing packets, being fed by theserial interface clock.
When serial interface operation happens, depending on the operation length and the packet size chosen, either 1
or 2 of the packet entries in read cache may become available for storing packets. In that case the total storage
available is up to the maximum number of packets that can be accommodated in 2048 bytes + 1 packet size,
depending on the packet size used.
Due to the non-deterministic nature of system operation, driver memory allocation should always be the largest
size of 2080 bytes.

FIFO 2048 Bytes

2 Packet Size

Read Cache

2048 Bytes – 1 packet size

1 Packet Size

Reserved to prevent reading apacket during write operation

Figure 12. Maximum FIFO Storage

6.4 FIFO CONFIGURATION REGISTERS
The following control bits in bank 0, register 0x5Fh determine what data is placed into the FIFO. The values ofthese bits may change while the FIFO is being filled without corruption of the FIFO.
BIT

NAME

3

FIFO_TMST_FSYNC_EN

1

FIFO_GYRO_EN

0

FIFO_ACCEL_EN

Document Number: DS-000330
Revision: 1.2

FUNCTION
0: FIFO will only contain ODR timestamp information
1: FIFO can also contain FSYNC time and FSYNC tag for one ODR after an
FSYNC event
0: Default setting; Gyroscope data not placed into FIFO
1: Enables gyroscope data packets of 6-bytes to be placed in FIFO
0: Default setting; Accelerometer data not placed into FIFO
1: Enables accelerometer data packets of 6-bytes to be placed in FIFO

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ICM-40609-D
Configuration register settings above impact FIFO header and FIFO packet size as follows:
FIFO_ACCEL_EN

FIFO_GYRO_EN

1
1
1
0
0

1
1
0
1
0

Document Number: DS-000330
Revision: 1.2

FIFO_TMST_FSYNC_EN
0
1
X
X
X

Page 39 of 86

HeaderPacket size

8’b_0110_10xx
8’b_0110_1xxx
8’b_0100_00xx
8’b_0010_00xx
No FIFO writes

16 Bytes
16 Bytes
8 Bytes
8 Bytes
No FIFO writes

ICM-40609-D
7 PROGRAMMABLE INTERRUPTS
The ICM-40609-D has a programmable interrupt system that can generate an interrupt signal on the INT pins.
Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There
are two interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register
section. The following configuration options are available for the interrupts•••

INT1 and INT2 can be push-pull or open drain
Level or pulse mode
Active high or active low

7.1 WAKE-ON MOTION INTERRUPTThe ICM-40609-D provides motion detection capability. A qualifying motion sample is one where the high passed
sample from any axis has an absolute value exceeding a user-programmable threshold. The following steps explain
how to configure the Wake-on-Motion Interrupt.
•

Wake on Motion configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. WOM_MODE1 (Register 0x57h in Bank 0)•

Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond•

Initialize Wake on Motion hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Set WOM_INT_MODE to 0 (Register 0x57h in Bank 0)
6. Set WOM_MODE to 1 (Register 0x57h in Bank 0)
7. Set WOM_MODE1 to 1 (Register 0x57h in Bank 0)
8. Wait 1 millisecond
9. Enable all 3 axes as WOM sources for INT1 by setting bits 2:0 in register INT_SOURCE1(Register 0x66h in Bank 0) to 1. Or if INT2 is selected for WOM, enable all 3 axes as WOM
sources by setting bits 2:0 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1.
10. Wait 50 milliseconds•

Output registers
1. Read interrupt register (Register 0x37h in Bank 0) for WOM_X_INT
2. Read interrupt register (Register 0x37h in Bank 0) for WOM_Y_INT
3. Read interrupt register (Register 0x37h in Bank 0) for WOM_Z_INT

Document Number: DS-000330
Revision: 1.2

Page 40 of 86

ICM-40609-D
8 DIGITAL INTERFACE
8.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-40609-D can be accessed using I2C at 1 MHz or SPI at 24 MHz. SPI
operates in 3-wire or 4-wire mode. Pin assignments for serial interfaces are described in Section 4.1.

8.2 I2C INTERFACEI2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or aslave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ICM-40609-D always operates as a slave device when communicating to the system processor, which thus acts
as the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the ICM-40609-D is b110100X, which is 7 bits long. The LSB bit of the 7-bit address isdetermined by the logic level on pin AP_AD0. This allows two ICM-40609-Ds to be connected to the same I2C bus.
When used in this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low)
and the address of the other should be b1101001 (pin AP_AD0 is logic high).

8.3 I2C COMMUNICATIONS PROTOCOLSTART (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined asa HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to bebusy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the
SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.

SDA

SCL

S

P

START condition

STOP condition

Figure 13. START and STOP Conditions

Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per datatransfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA
and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it
can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready,and releases the clock line (refer to the following figure).

Document Number: DS-000330
Revision: 1.2

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ICM-40609-D
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BYRECEIVER (SDA)
acknowledge
SCL FROM
MASTER

1

2

8

9
clock pulse for
acknowledgement

START
condition

Figure 14. Acknowledge on the I2C Bus

Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by
an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to
the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave
device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the
SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by themaster with a STOP condition (P), thus freeing the communications line. However, the master can generate a
repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to
HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take placewhen SCL is low, with the exception of start and stop conditions.

SDA

SCL

1–7

8

9

1–7

8

9

1–7

8

9

S

P

START ADDRESS
condition

ACK

R/W

DATA

ACK

DATA

ACK

STOP
condition

Figure 15. Complete I2C Data Transfer

To write the internal ICM-40609-D registers, the master transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when the clock is high), the ICM-40609-D acknowledges thetransfer. Then the master puts the register address (RA) on the bus. After the ICM-40609-D acknowledges thereception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal,and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, themaster can continue outputting data rather than transmitting a stop signal. In this case, the ICM-40609-D
automatically increments the register address and loads the data to the appropriate register. The following figures
show single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave

S

AD+W

Document Number: DS-000330
Revision: 1.2

RA
ACK

DATA
ACK

P
ACK

Page 42 of 86

ICM-40609-D
Burst Write Sequence
Master
Slave

S

AD+W

RA
ACK

DATA
ACK

DATA
ACK

P
ACK

To read the internal ICM-40609-D registers, the master sends a start condition, followed by the I2C address and awrite bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM40609-D, the master transmits a start signal followed by the slave address and read bit. As a result, the ICM-40609D sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bitfrom master. The NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The
following figures show single- and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave

S

AD+W

RA
ACK

S

AD+R

NACK

ACK

ACK

P

DATA

Burst Read Sequence
Master
Slave

S

AD+W

RA
ACK

S
ACK

AD+R

ACK
ACK

DATA

NACK
DATA

8.4 I2C TERMS
Signal
S
AD
W
R
ACK
NACK
RA
DATA
P

Description
Start Condition: SDA goes from high to low while SCL is highSlave I2C address
Write bit (0)Read bit (1)Acknowledge: SDA line is low while the SCL line is high at the 9th clock
cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-40609-D internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is highTable 12. I2C Terms

Document Number: DS-000330
Revision: 1.2

Page 43 of 86

PICM-40609-D
8.5 SPI INTERFACEThe ICM-40609-D supports 3-wire or 4-wire SPI for the host interface. The ICM-40609-D always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input(SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip
Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is activeat a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices
are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interferewith any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first
byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first
byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The following 7 bits
contain the Register Address. In cases of multiple-byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
R/W

A6

A5

A4

A3

A2

A1

LSB
A0

D4

D3

D2

D1

LSB
D0

SPI Data format
MSB
D7
6.

D6

D5

Supports Single or Burst Read/Writes.
SCLK

SPI Master

SDIO
CS1

nCS

SPI Slave 1

CS2

SCLK
SDIO
nCS

SPI Slave 2

Figure 16. Typical SPI Master/Slave Configuration

Document Number: DS-000330
Revision: 1.2

Page 44 of 86

ICM-40609-D
9 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS)
gyros packaged in LGA package.

9.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figure.
+Z

+Y

+Z
+Y

+X

+X

Figure 17. Orientation of Axes of Sensitivity and Polarity of Rotation

Document Number: DS-000330
Revision: 1.2

Page 45 of 86

ICM-40609-D
9.2 PACKAGE DIMENSIONS
24 Lead LGA (3x3x0.91) mm NiAu pad finish

Document Number: DS-000330
Revision: 1.2

Page 46 of 86

ICM-40609-D
DIMENSIONS IN MILLIMETERSSYMBOLS
A
A1
A2
D
E
W
L
e
n
D1
E1
SD
SE
b
e1
n1
aaa
bbb
ddd
eee
fff
H
P
S

Document Number: DS-000330
Revision: 1.2

MIN
0.85

2.9
2.9
0.15
0.25

---

Page 47 of 86

NOM
0.91
0.105
0.8
3
3
0.2
0.3
0.4
24
2
2
0.2
0.2
------0.1
0.2
0.08----0.1
0.2
0.184

MAX
0.97
REF
REF
3.1
3.1
0.25
0.35
BSC
BSC
BSC
BSC
BSC
---

REF
REF
REF

ICM-40609-D
10 PART NUMBER PACKAGE MARKINGThe part number package marking for ICM-40609-D devices is summarized below:
Part Number
ICM-40609-D

Part Number Package Marking
I469D

TOP VIEWPart Number
Lot Traceability CodeI469D
XXXXXX
YYWW

Y Y = Year CodeW W = Work Week

Document Number: DS-000330
Revision: 1.2

Page 48 of 86

ICM-40609-D
11 USE NOTES
11.1 ACCELEROMETER MODE TRANSITIONSWhen transitioning from accelerometer Low Power (LP) mode to accelerometer Low Noise (LN) mode, if ODR is
6.25 Hz or lower, software should change ODR to a value of 12.5 Hz or higher, because accelerometer LN mode
does not support ODR values below 12.5 Hz.
When transitioning from accelerometer LN mode to accelerometer LP mode, if ODR is greater than 500 Hz,
software should change ODR to a value of 500Hz or lower, because accelerometer LP mode does not support ODRvalues above 500 Hz.

11.2 ACCELEROMETER LOW POWER (LP) MODE AVERAGING FILTER SETTING
Software drivers provided with the device use Averaging Filter setting of 16x. This setting is recommended formeeting Android noise requirements in LP mode, and to minimize accelerometer offset variation whentransitioning from LP to Low Noise (LN) mode. 1x averaging filter can be used by following the setting configuration
shown in section 14.38.

11.3 SETTINGS FOR I2C, AND SPI OPERATION
Upon bootup the device comes up in SPI mode. The following settings should be used for I2C, and SPI operation.
Register Field
I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address
0x13, bank 0)
SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address
0x13, bank 0)

I2C Driver
Setting

SPI Driver
Setting

1

0

1

5

11.4 NOTCH FILTER AND ANTI-ALIAS FILTER OPERATION
Use of Notch Filter and Anti-Alias Filter is supported only for Low Noise (LN) mode operation. The host is
responsible for keeping the UI path in LN mode while Notch Filter and Anti-Alias Filter are turned on.

11.5 REGISTER VALUES MODIFICATIONThe only register settings that user can modify during sensor operation are for ODR selection, FSR selection, andsensor mode changes (register parameters GYRO_ODR, ACCEL_ODR, GYRO_FS_SEL, ACCEL_FS_SEL, GYRO_MODE,
ACCEL_MODE). User must not modify any other register values during sensor operation. The following proceduremust be used for other register values modification.
•••

Turn Accel and Gyro Off
Modify register values
Turn Accel and/or Gyro On

Document Number: DS-000330
Revision: 1.2

Page 49 of 86

ICM-40609-D
12 REGISTER MAP
This section lists the register map for the ICM-40609-D, for user banks 0, 1, 2, 4.

12.1 USER BANK 0 REGISTER MAP
Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

11

17

DEVICE_CONFIG

R/W

13

19

DRIVE_CONFIG

R/W

14

20

INT_CONFIG

Bit7

Bit6

Bit5

Bit4

-

Bit3

Bit2

SPI_MODE-I2C_SLEW_RATE

R/W-

INT2_DRIVE_CIRCUITFIFO_MODE

INT2_MODE

22

FIFO_CONFIG

R/W

29

TEMP_DATA1

SYNCR

1E

30

TEMP_DATA0SYNCRTEMP_DATA[7:0]1F

31

ACCEL_DATA_X1

SYNCR

ACCEL_DATA_X[15:8]

20

32

ACCEL_DATA_X0

SYNCR

ACCEL_DATA_X[7:0]21

33

ACCEL_DATA_Y1

SYNCR

ACCEL_DATA_Y[15:8]

22

34

ACCEL_DATA_Y0

SYNCR

ACCEL_DATA_Y[7:0]2335

ACCEL_DATA_Z1

SYNCR

ACCEL_DATA_Z[15:8]

24

36

ACCEL_DATA_Z0

SYNCR

ACCEL_DATA_Z[7:0]25

37

GYRO_DATA_X1

SYNCR

GYRO _DATA_X[15:8]

26

38

GYRO _DATA_X0

SYNCR

GYRO _DATA_X[7:0]27

39

GYRO _DATA_Y1

SYNCR

GYRO _DATA_Y[15:8]

28

40

GYRO _DATA_Y0

SYNCR

GYRO _DATA_Y[7:0]2941

GYRO _DATA_Z1

SYNCR

GYRO_DATA_Z[15:8]

2A

42

GYRO _DATA_Z0

SYNCR

GYRO_DATA_Z[7:0]2B

43

TMST_FSYNCH

SYNCR

TMST_FSYNC_DATA[15:8]

2C

44

TMST_FSYNCLSYNCRRESET_DONE_INT

PLL_RDY_INTDATA_RDY_I
NT

R/C

2E

46

FIFO_COUNTHR

FIFO_COUNT[15:8]

2F

47

FIFO_COUNTLR

FIFO_COUNT[7:0]30

48

FIFO_DATA

R

37

55

INT_STATUS2

R/C

ABORT_AND_RESET

75

SIGNAL_PATH_RESET

W/C

4C

76

INTF_CONFIG0

R/W

4D

77

INTF_CONFIG1

R/W

EN_TEST_MODE

4E

78

PWR_MGMT0

R/W

-

4F

79

GYRO_CONFIG0

R/W

50

80

ACCEL_CONFIG0

51

81

GYRO_CONFIG1

52

82

GYRO_ACCEL_CONFIG0

R/W

ACCEL_UI_FILT_BW

53

83

ACCEL_CONFIG1

R/W-

FIFO_HOLD_L
AST_DATA_E
N

FIFO_COUNT_REC

FIFO_COUNT_ENDIANSENSOR_DAT
A_ENDIAN

TEMP_DISACCEL_FS_SEL-

R/W

TEMP_FILT_BW-

95

FIFO_CONFIG1

R/W

60

96

FIFO_CONFIG2

R/W

61

97

FIFO_CONFIG3R/W

AGC_RDY_IN
T

WOM_Z_INT

WOM_Y_INT

WOM_X_INTTMST_STROBE

FIFO_FLUSH-

CLKSELACCEL_MODE

ACCEL_ODR
GYRO_UI_FILT_ORD

GYRO_DEC2_M2_ORD

GYRO_UI_FILT_BW

FIFO_WM_G
T_TH-

GYRO_MODE

ACCEL_UI_FILT_ORD

FIFO_RESUM
E_PARTIAL_R
D

UI_SIFS_CFG

GYRO_ODRTMST_TO_RE
GS_EN

-

-

-

IDLE

R/W

5F

FIFO_FULL_I
NT

ACCEL_LP_CL
K_SEL

-

-

R/W

Document Number: DS-000330
Revision: 1.2-

GYRO_FS_SEL

WOM_CONFIG

FIFO_THS_IN
T

FIFO_DATA
-

4B

87

INT1_POLARITY

TMST_FSYNC_DATA[7:0]
UI_FSYNC_IN
T

INT_STATUS

57

INT1_DRIVE_CIRCUIT

-

45

R/W

INT1_MODE

TEMP_DATA[15:8]

2D

TMST_CONFIG

SOFT_RESET_CONFIGSPI_SLEW_RATE

INT2_POLARI
TY

16

84

Bit0

-

1D

54

Bit1

-

ACCEL_DEC2_M2_ORD

TMST_RESTMST_DELTA_EN

WOM_INT_MODE

WOM_MODEFIFO_TMST_F
SYNC_ENFIFO_TEMP_ENTMST_FSYNC_EN

Page 50 of 86

TMST_EN

WOM_MODE1
FIFO_GYRO_EN

FIFO_WM[7:0]--

FIFO_WM[11:8]

FIFO_ACCEL_ENICM-40609-D
Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

62

98

FSYNC_CONFIG

R/W

63

99

INT_CONFIG0

R/W

Bit7

Bit6

Bit5

-

Bit4

Bit3

FSYNC_UI_SEL--UI_DRDY_INT_CLEAR

64

100

INT_CONFIG1

R/W-

INT_TPULSE_DURATION

65

101

INT_SOURCE0

R/W-

UI_FSYNC_IN
T1_EN

66

102

INT_SOURCE1

R/W

68

104

INT_SOURCE3

R/W

69

105

INT_SOURCE4

R/W

6C

108

FIFO_LOST_PKT0

R

6D

109

FIFO_LOST_PKT1

R

70

112

SELF_TEST_CONFIG

R/W

75

117

WHO_AM_I

R

76

118

REG_BANK_SEL

R/W

FIFO_THS_INT_CLEAR

INT_TDEASSE
RT_DISABLE

INT_ASYNC_RESET

PLL_RDY_INT
1_EN

RESET_DONE_INT1_ENUI_FSYNC_IN
T2_EN

PLL_RDY_INT
2_EN

RESET_DONE_INT2_EN

Bit1

Bit0

FSYNC_UI_FL
AG_CLEAR_S
EL

FSYNC_POLARITY

FIFO_FULL_INT_CLEAR-UI_DRDY_INT
1_EN

-

Bit2

UI_DRDY_INT
2_EN-

FIFO_THS_IN
T1_EN

FIFO_FULL_I
NT1_ENUI_AGC_RDY_INT1_EN

WOM_Z_INT
1_EN

WOM_Y_INT
1_EN

WOM_X_INT
1_EN

FIFO_THS_IN
T2_EN

FIFO_FULL_I
NT2_ENUI_AGC_RDY_INT2_EN

WOM_Z_INT
2_EN

WOM_Y_INT
2_EN

WOM_X_INT
2_EN

EN_GZ_ST

EN_GY_ST

EN_GX_ST

FIFO_LOST_PKT_CNT[15:8]
FIFO_LOST_PKT_CNT[7:0]
ACCEL_ST_P
OWER

EN_AZ_ST

EN_AY_ST

EN_AX_ST

WHOAMI-BANK_SEL

12.2 USER BANK 1 REGISTER MAP
Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

03

03

SENSOR_CONFIG0

R/W

0B

11

GYRO_CONFIG_STATIC2

R/W

Bit7

Bit6
-

Bit5

Bit4

Bit3

Bit2

ZG_DISABLE

YG_DISABLE

XG_DISABLE

ZA_DISABLE

-

0C

12

GYRO_CONFIG_STATIC3

R/W

0D

13

GYRO_CONFIG_STATIC4

R/W

0E

14

GYRO_CONFIG_STATIC5

R/W

0F

15

GYRO_CONFIG_STATIC6

R/W

GYRO_X_NF_COSWZ[7:0]1016

GYRO_CONFIG_STATIC7

R/W

GYRO_Y_NF_COSWZ[7:0]1117GYRO_CONFIG_STATIC8

R/W

12

18

GYRO_CONFIG_STATIC9

R/W

13

19

GYRO_CONFIG_STATIC10

R/W

-

Bit0

YA_DISABLE

XA_DISABLE

GYRO_AAF_D
IS

GYRO_NF_DI
S

GYRO_AAF_DELT
GYRO_AAF_DELTSQR[7:0]
GYRO_AAF_BITSHIFTGYRO_AAF_DELTSQR[11:8]

GYRO_Z_NF_COSWZ[7:0]
GYRO_Z_NF_
COSWZ_SEL[
0]

-

-

GYRO_Y_NF_
COSWZ_SEL[
0]

GYRO_X_NF_
COSWZ_SEL[
0]

GYRO_NF_BW_SEL

GYRO_Z_NF_
COSWZ[8]GYRO_Y_NF_
COSWZ[8]5F

95

XG_ST_DATA

R/W

XG_ST_DATA

96

YG_ST_DATA

R/W

YG_ST_DATA

61

97

ZG_ST_DATA

R/W

ZG_ST_DATA

62

98

TMSTVAL0R

TMST_VALUE[7:0]63

99

TMSTVAL1

R

64

100

TMSTVAL2

R

7A

122

INTF_CONFIG4

R/W

7B

123

INTF_CONFIG5R/W

GYRO_X_NF_
COSWZ[8]GYRO_HPF_O
RD_IND

GYRO_HPF_BW_IND

60

Document Number: DS-000330
Revision: 1.2

Bit1

TMST_VALUE[15:8]-

TMST_VALUE[19:16]-

Page 51 of 86

SPI_AP_4WIR
E
PIN19_FUNCTION-ICM-40609-D
12.3 USER BANK 2 REGISTER MAP
Addr
(Hex)

Addr
(Dec.)

Register Name

Serial
I/F

Bit7

03

03

ACCEL_CONFIG_STATIC2

R/W

-

04

04

ACCEL_CONFIG_STATIC3

R/W

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0
ACCEL_AAF_
DIS

ACCEL_AAF_DELTACCEL_AAF_DELTSQR[7:0]0505

ACCEL_CONFIG_STATIC4

R/W

3B

59

XA_ST_DATA

R/W

ACCEL_AAF_BITSHIFTXA_ST_DATAACCEL_AAF_DELTSQR[11:8]

3C

60

YA_ST_DATA

R/W

YA_ST_DATA

3D

61

ZA_ST_DATA

R/W

ZA_ST_DATA

12.4 USER BANK 4 REGISTER MAP
Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

4A

74

ACCEL_WOM_X_THR

R/W

WOM_X_TH

4B

75

ACCEL_WOM_Y_THR

R/W

WOM_Y_TH

4C

76

ACCEL_WOM_Z_THR

R/W

WOM_Z_TH

77

119

OFFSET_USER0R/W

GYRO_X_OFFUSER[7:0]

78

120

OFFSET_USER1

R/W

79

121

OFFSET_USER2

R/W

7A

122

OFFSET_USER3

R/W

7B

123

OFFSET_USER4

R/W

7C

124

OFFSET_USER5

R/W

7D

125

OFFSET_USER6

R/W

7E

126

OFFSET_USER7

R/W

7F

127

OFFSET_USER8

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

GYRO_Y_OFFUSER[11:8]

Bit2

Bit1

GYRO_X_OFFUSER[11:8]
GYRO_Y_OFFUSER[7:0]
GYRO_Z_OFFUSER[7:0]

ACCEL_X_OFFUSER[11:8]

GYRO_Z_OFFUSER[11:8]
ACCEL_X_OFFUSER[7:0]
ACCEL_Y_OFFUSER[7:0]

ACCEL_Z_OFFUSER[11:8]

ACCEL_Y_OFFUSER[11:8]
ACCEL_Z_OFFUSER[7:0]

Detailed register descriptions are provided in the sections that follow. Please note the following regarding Clock
Domain for each register:
1.

Clock Domain: SCLK_UI means that the register is controlled from the UI interface

Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used
to determine the default value of reserved register fields, and unless otherwise noted this default value must be
maintained even if the values of other register fields are modified by the user.

Document Number: DS-000330
Revision: 1.2

Page 52 of 86

Bit0

ICM-40609-D
13 USER BANK 0 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within USR Bank 0.
Note: The device powers up in sleep mode.

13.1 DEVICE_CONFIG
Name: DEVICE_CONFIG
Address: 17 (11h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:5 4
SPI_MODE
3:1
0

SOFT_RESET_CONFIG

FUNCTION
Reserved
SPI mode selection
0: Mode 0 and Mode 3 (default)
1: Mode 1 and Mode 2
Reserved
Software reset configuration
0: Normal (default)
1: Enable reset
After writing 1 to this bitfield, wait 1ms for soft reset to be effective, before
attempting any other register access13.2 DRIVE_CONFIG
Name: DRIVE_CONFIG
Address: 19 (13h)Serial IF: R/W
Reset value: 0x05
Clock Domain: SCLK_UI
BIT NAME
7:6 -

5:3

I2C_SLEW_RATE

2:0

SPI_SLEW_RATE

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
Controls slew rate for output pin 14 in I2C mode only
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
100: 2ns-6ns
101: < 2ns
110: Reserved
111: Reserved
Controls slew rate for output pin 14 in SPI mode, and for all other output
pins
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
100: 2ns-6ns
101: < 2ns
110: Reserved
111: Reserved

Page 53 of 86

ICM-40609-D
13.3 INT_CONFIG
Name: INT_CONFIG
Address: 20 (14h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_OIS1
BIT NAME
7:6 5

INT2_MODE

4

INT2_DRIVE_CIRCUIT

3

INT2_POLARITY2

INT1_MODE

1

INT1_DRIVE_CIRCUIT0

INT1_POLARITY

FUNCTION
Reserved
INT2 interrupt mode
0: Pulsed mode
1: Latched mode
INT2 drive circuit
0: Open drain
1: Push pull
INT2 interrupt polarity
0: Active low (default)
1: Active highINT1 interrupt mode
0: Pulsed mode
1: Latched mode
INT1 drive circuit
0: Open drain
1: Push pull
INT1 interrupt polarity
0: Active low (default)
1: Active high13.4 FIFO_CONFIG
Name: FIFO_CONFIG
Address: 22 (16h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 FIFO_MODE

5:0-

FUNCTION
00: Bypass Mode (default)
01: Stream-to-FIFO Mode
10: STOP-on-FULL Mode
11: STOP-on-FULL Mode
Reserved

13.5 TEMP_DATA1
Name: TEMP_DATA1
Address: 29 (1Dh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 TEMP_DATA[15:8]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Upper byte of temperature data

Page 54 of 86

ICM-40609-D
13.6 TEMP_DATA0
Name: TEMP_DATA0
Address: 30 (1Eh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 TEMP_DATA[7:0]

FUNCTION
Lower byte of temperature data

Temperature data value from the sensor data registers can be converted to degrees centigrade by using thefollowing formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigradeby using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25

13.7 ACCEL_DATA_X1
Name: ACCEL_DATA_X1
Address: 31 (1Fh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_X[15:8]

FUNCTION
Upper byte of Accel X-axis data

13.8 ACCEL_DATA_X0
Name: ACCEL_DATA_X0
Address: 32 (20h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_X[7:0]

FUNCTION
Lower byte of Accel X-axis data

13.9 ACCEL_DATA_Y1
Name: ACCEL_DATA_Y1
Address: 33 (21h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_Y[15:8]

FUNCTION
Upper byte of Accel Y-axis data

13.10 ACCEL_DATA_Y0
Name: ACCEL_DATA_Y0
Address: 34 (22h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI

Document Number: DS-000330
Revision: 1.2

Page 55 of 86

ICM-40609-D
BIT
7:0

NAME
ACCEL_DATA_Y[7:0]

FUNCTION
Lower byte of Accel Y-axis data

13.11 ACCEL_DATA_Z1
Name: ACCEL_DATA_Z1
Address: 35 (23h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_Z[15:8]

FUNCTION
Upper byte of Accel Z-axis data

13.12 ACCEL_DATA_Z0
Name: ACCEL_DATA_Z0
Address: 36 (24h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_Z[7:0]

FUNCTION
Lower byte of Accel Z-axis data

13.13 GYRO_DATA_X1
Name: GYRO_DATA_X1
Address: 37 (25h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_X[15:8]

FUNCTION
Upper byte of Gyro X-axis data

13.14 GYRO_DATA_X0
Name: GYRO_DATA_X0
Address: 38 (26h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_X[7:0]

FUNCTION
Lower byte of Gyro X-axis data

13.15 GYRO_DATA_Y1
Name: GYRO_DATA_Y1
Address: 39 (27h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Y[15:8]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Upper byte of Gyro Y-axis data

Page 56 of 86

ICM-40609-D
13.16 GYRO_DATA_Y0
Name: GYRO_DATA_Y0
Address: 40 (28h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Y[7:0]

FUNCTION
Lower byte of Gyro Y-axis data

13.17 GYRO_DATA_Z1
Name: GYRO_DATA_Z1
Address: 41 (29h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Z[15:8]

FUNCTION
Upper byte of Gyro Z-axis data

13.18 GYRO_DATA_Z0
Name: GYRO_DATA_Z0
Address: 42 (2Ah)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Z[7:0]

FUNCTION
Lower byte of Gyro Z-axis data

13.19 TMST_FSYNCH
Name: TMST_FSYNCH
Address: 43 (2Bh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

TMST_FSYNC_DATA[15:8]

FUNCTIONStores the upper byte of the time delta from the rising edge of FSYNC tothe latest ODR until the UI Interface reads the FSYNC tag in the status
register

13.20 TMST_FSYNCLName: TMST_FSYNCL
Address: 44 (2Ch)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

TMST_FSYNC_DATA[7:0]

Document Number: DS-000330
Revision: 1.2

FUNCTIONStores the lower byte of the time delta from the rising edge of FSYNC tothe latest ODR until the UI Interface reads the FSYNC tag in the status
registerPage 57 of 86

ICM-40609-D
13.21 INT_STATUS
Name: INT_STATUS
Address: 45 (2Dh)
Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
6

UI_FSYNC_INT

5

PLL_RDY_INT

4RESET_DONE_INT

3

DATA_RDY_INT

2

FIFO_THS_INT

1

FIFO_FULL_INT0

AGC_RDY_INT

FUNCTION
Reserved
This bit automatically sets to 1 when a UI FSYNC interrupt is generated. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when a PLL Ready interrupt is generated. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when software reset is complete. The bit
clears to 0 after the register has been read.
This bit automatically sets to 1 when a Data Ready interrupt is generated.
The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer reaches the thresholdvalue. The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to
0 after the register has been read.
This bit automatically sets to 1 when an AGC Ready interrupt is generated.
The bit clears to 0 after the register has been read.

13.22 FIFO_COUNTH
Name: FIFO_COUNTH
Address: 46 (2Eh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

FIFO_COUNT[15:8]

FUNCTION
High Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_REC setting.
Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH
and FIFO_COUNTL.

13.23 FIFO_COUNTLName: FIFO_COUNTL
Address: 47 (2Fh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

FIFO_COUNT[7:0]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Low Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_REC setting.
Reading this byte latches the data for both FIFO_COUNTH, and
FIFO_COUNTL.

Page 58 of 86

ICM-40609-D
13.24 FIFO_DATA
Name: FIFO_DATA
Address: 48 (30h)Serial IF: R
Reset value: 0xFF
Clock Domain: SCLK_UI
BIT NAME
7:0 FIFO_DATAFUNCTIONFIFO data port

13.25 INT_STATUS2
Name: INT_STATUS2
Address: 55 (37h)Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:3 2
WOM_Z_INT
1
WOM_Y_INT
0
WOM_X_INTFUNCTION
Reserved
Wake on Motion Interrupt on Z-axis, clears on read
Wake on Motion Interrupt on Y-axis, clears on read
Wake on Motion Interrupt on X-axis, clears on read

13.26 SIGNAL_PATH_RESET
Name: SIGNAL_PATH_RESET
Address: 75 (4Bh)
Serial IF: W/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 3

ABORT_AND_RESET

2

TMST_STROBE

1
0

FIFO_FLUSH-

FUNCTION
Reserved
When this bit is set to 1, the signal path is reset by restarting the ODR
counter and signal path controls
When this bit is set to 1, the time stamp counter is latched into the timestamp register. This is a write on clear bit.
When set to 1, FIFO will get flushed.
Reserved

13.27 INTF_CONFIG0
Name: INTF_CONFIG0
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x30
Clock Domain: SCLK_UI
BIT NAME

7

FIFO_HOLD_LAST_DATA_EN

FUNCTION
Setting 0 corresponds to the following:
Sense Registers from Power on Reset till first sample:•

Invalid Samples Value: -32768

Sense Registers after first sample received:

Document Number: DS-000330
Revision: 1.2

Page 59 of 86

ICM-40609-D••Sense Registers Valid Sample Values:o Range limited from -32766 to +32767 when FSYNC tag is
disabled, or for sensor not selected for FSYNC tago Range limited from -32765 to +32767 (odd values) for
sensor selected for FSYNC tag, and FSYNC is taggedo Range limited from -32766 to +32766 (even values) for
sensor selected for FSYNC tag, but FSYNC is not tagged
Sense Registers Invalid Sample Values:o -32768 when FSYNC tag is disabled, or for sensor notselected for FSYNC tag, or for sensor selected for FSYNC
tag but FSYNC is not taggedo -32767 for sensor selected for FSYNC tag, and FSYNC istaggedFIFO:••Invalid Sample Value: -32768
Valid Sample Values: -32766 to +32767

Setting 1 corresponds to the following:
Sense Registers from Power on Reset till first sample:•

Invalid Samples Value: 0

Sense Registers after first sample received:••

Sense Registers Valid Sample Values:o Range limited from -32768 to +32767 when FSYNC tag is
disabled, or for sensor not selected for FSYNC tago Range limited from -32767 to +32767 (odd values) for
sensor selected for FSYNC tag, and FSYNC is taggedo Range limited from -32768 to +32766 (even values) for
sensor selected for FSYNC tag, but FSYNC is not tagged
Sense Registers Invalid Sample Values:o Registers hold last valid sample until new one arrives

FIFO:

6

FIFO_COUNT_REC

5

FIFO_COUNT_ENDIAN

4

SENSOR_DATA_ENDIAN

3:2
1:0

UI_SIFS_CFG

Document Number: DS-000330
Revision: 1.2• Invalid Sample Value: Copy last valid sample• Valid Sample Values: -32768 to +32767
0: FIFO count is reported in bytes
1: FIFO count is reported in records (1 record = 16 bytes for header + gyro +accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel +temp sensor data)
0: FIFO count is reported in Little Endian format
1: FIFO count is reported in Big Endian format (default)
0: Sensor data is reported in Little Endian format
1: Sensor data is reported in Big Endian format (default)
Reserved
0x: Reserved

Page 60 of 86

ICM-40609-D
10: Disable SPI
11: Disable I2CInvalid Data Generation: FIFO/Sense Registers may contain invalid data under the following conditions:a) From power on reset to first ODR sample of any sensor (accel, gyro, temp sensor)b) When any sensor is disabled (accel, gyro, temp sensor)c) When accel and gyro are enabled with different ODRs. In this case, the sensor with lower ODR will
generate invalid samples when it has no new data.
Invalid data can take special values or can hold last valid sample received. For -32768 to be used as a flag forinvalid accel/gyro samples, the valid accel/gyro sample range is limited in such case as well. Bit 7 of INTF_CONFIG0
controls what values invalid (and valid) samples can take as shown above.

13.28 INTF_CONFIG1
Name: INTF_CONFIG1
Address: 77 (4Dh)
Serial IF: R/W
Reset value: 0x91
Clock Domain: SCLK_UI
BIT NAME
7:6 EN_TEST_MODE
5:4 3

ACCEL_LP_CLK_SEL

2

-

1:0

CLKSELFUNCTION
Enables test mode. Must be set to 01 for normal device operation.
Reserved
0: Accelerometer LP mode uses Wake Up oscillator clock
1: Accelerometer LP mode uses RC oscillator clock
Reserved
00: Always select internal RC oscillator
01: Select PLL when available, else select RC oscillator (default)
10: Reserved
11: Disable all clocks

13.29 PWR_MGMT0
Name: PWR_MGMT0
Address: 78 (4Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5

TEMP_DIS

4

IDLE

3:2

GYRO_MODE

FUNCTION
Reserved
0: Temperature sensor is enabled (default)
1: Temperature sensor is disabled
If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro
are powered off.
Nominally this bit is set to 0, so when Accel and Gyro are powered off,the chip will go to OFF state, since the RC oscillator will also be powered off
00: Turns gyroscope off (default)
01: Places gyroscope in Standby Mode
10: Reserved
11: Places gyroscope in Low Noise (LN) Mode
Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning
from OFF to any of the other modes, do not issue any register writes for
200µs.

Document Number: DS-000330
Revision: 1.2

Page 61 of 86

ICM-40609-D
1:0

ACCEL_MODE

00: Turns accelerometer off (default)
01: Turns accelerometer off
10: Places accelerometer in Low Power (LP) Mode
11: Places accelerometer in Low Noise (LN) Mode
When transitioning from OFF to any of the other modes, do not issue any
register writes for 200µs.

13.30 GYRO_CONFIG0
Name: GYRO_CONFIG0
Address: 79 (4Fh)
Serial IF: R/W
Reset value: 0x07
Clock Domain: SCLK_UI
BIT NAME

7:5

GYRO_FS_SEL

4

-

3:0

GYRO_ODR

Document Number: DS-000330
Revision: 1.2

FUNCTION
Full scale select for gyroscope UI interface output
000: ±2000dps (default)
001: ±1000dps
010: ±500dps
011: ±250dps
100: ±125dps
101: ±62.5dps
110: ±31.25dps
111: ±15.625dps
Reserved
Gyroscope ODR selection for UI interface output
0000: Reserved
0001: 32kHz
0010: 16kHz
0011: 8kHz
0100: 4kHz
0101: 2kHz
0110: 1kHz (default)
0111: 200Hz
1000: 100Hz
1001: 50Hz
1010: 25Hz
1011: 12.5Hz
1100: Reserved
1101: Reserved
1110: Reserved
1111: 500Hz

Page 62 of 86

ICM-40609-D
13.31 ACCEL_CONFIG0
Name: ACCEL_CONFIG0
Address: 80 (50h)Serial IF: R/W
Reset value: 0x07
Clock Domain: SCLK_UI
BIT NAME

7:5

ACCEL_FS_SEL

4

-

3:0

ACCEL_ODRDocument Number: DS-000330
Revision: 1.2

FUNCTION
Full scale select for accelerometer UI interface output
000: ±32g (default)
001: ±16g
010: ±8g
011: ±4g
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Reserved
Accelerometer ODR selection for UI interface output
0000: Reserved
0001: 32kHz (LN mode)
0010: 16kHz (LN mode)
0011: 8kHz (LN mode)
0100: 4kHz (LN mode)
0101: 2kHz (LN mode)
0110: 1kHz (LN mode) (default)
0111: 200Hz (LP or LN mode)
1000: 100Hz (LP or LN mode)
1001: 50Hz (LP or LN mode)
1010: 25Hz (LP or LN mode)
1011: 12.5Hz (LP or LN mode)
1100: 6.25Hz (LP mode)
1101: 3.125Hz (LP mode)
1110: 1.5625Hz (LP mode)
1111: 500Hz (LP or LN mode)

Page 63 of 86

ICM-40609-D
13.32 GYRO_CONFIG1
Name: GYRO_CONFIG1
Address: 81 (51h)Serial IF: R/W
Reset value: 0x1A
Clock Domain: SCLK_UI
BIT NAME

7:5

TEMP_FILT_BW

4

-

3:2

GYRO_UI_FILT_ORD

1:0

GYRO_DEC2_M2_ORD

Document Number: DS-000330
Revision: 1.2

FUNCTION
Sets the bandwidth of the temperature signal DLPF
000: DLPF BW = 4000Hz; DLPF Latency = 0.125ms (default)
001: DLPF BW = 170Hz; DLPF Latency = 1ms
010: DLPF BW = 82Hz; DLPF Latency = 2ms
011: DLPF BW = 40Hz; DLPF Latency = 4ms
100: DLPF BW = 20Hz; DLPF Latency = 8ms
101: DLPF BW = 10Hz; DLPF Latency = 16ms
110: DLPF BW = 5Hz; DLPF Latency = 32ms
111: DLPF BW = 5Hz; DLPF Latency = 32ms
Reserved
Selects order of GYRO UI filter
00: 1st Order
01: 2nd Order
10: 3rd Order
11: Reserved
Selects order of GYRO DEC2_M2 Filter
00: Reserved
01: Reserved
10: 3rd Order
11: Reserved

Page 64 of 86

ICM-40609-D
13.33 GYRO_ACCEL_CONFIG0
Name: GYRO_ACCEL_CONFIG0
Address: 82 (52h)Serial IF: R/W
Reset value: 0x11
Clock Domain: SCLK_UI
BIT NAME

7:4

3:0

ACCEL_UI_FILT_BW

GYRO_UI_FILT_BW

Document Number: DS-000330
Revision: 1.2

FUNCTION
LN Mode:Bandwidth for Accel LPF
0 BW=ODR/2
1 BW=max(400Hz, ODR)/4 (default)
2 BW=max(400Hz, ODR)/5
3 BW=max(400Hz, ODR)/8
4 BW=max(400Hz, ODR)/10
5 BW=max(400Hz, ODR)/16
6 BW=max(400Hz, ODR)/20
7 BW=max(400Hz, ODR)/40
8 to 13: Reserved
14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(400Hz, ODR)
15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(200Hz, 8*ODR)LP Mode:0 Reserved
1 1x AVG filter (default)
2 to 5 Reserved
6 16x AVG filter
7 to 15 Reserved
LN Mode:Bandwidth for Gyro LPF
0 BW=ODR/2
1 BW=max(400Hz, ODR)/4 (default)
2 BW=max(400Hz, ODR)/5
3 BW=max(400Hz, ODR)/8
4 BW=max(400Hz, ODR)/10
5 BW=max(400Hz, ODR)/16
6 BW=max(400Hz, ODR)/20
7 BW=max(400Hz, ODR)/40
8 to 13: Reserved
14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(400Hz, ODR)
15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(200Hz, 8*ODR)Page 65 of 86

ICM-40609-D
13.34 ACCEL_CONFIG1
Name: ACCEL_CONFIG1
Address: 83 (53h)Serial IF: R/W
Reset value: 0x15
Clock Domain: SCLK_UI
BIT NAME
7:5 4:3

ACCEL_UI_FILT_ORD

2:1

ACCEL_DEC2_M2_ORD

0-

FUNCTION
Reserved
Selects order of ACCEL UI filter
00: 1st Order
01: 2nd Order
10: 3rd Order
11: Reserved
Order of Accelerometer DEC2_M2 filter
00: Reserved
01: Reserved
10: 3rd order
11: Reserved
Reserved

13.35 TMST_CONFIG
Name: TMST_CONFIG
Address: 84 (54h)Serial IF: R/W
Reset value: 0x20
Clock Domain: SCLK_UI
BIT NAME
7:5 4

TMST_TO_REGS_EN

3

TMST_RES

2

TMST_DELTA_EN

1

TMST_FSYNC_EN

0

TMST_EN

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
0: TMST_VALUE[19:0] read always returns 0s
1: TMST_VALUE[19:0] read returns timestamp value
Time Stamp resolution: When set to 0 (default), time stamp resolution is 1
µs. When set to 1, resolution is 16µs
Time Stamp delta enable: When set to 1, the time stamp field contains themeasurement of time since the last occurrence of ODR.
Time Stamp register FSYNC enable (default). When set to 1, the contents of
the Timestamp feature of FSYNC is enabled. The user also needs to selectFIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the
FIFO.
0: Time Stamp register disable
1: Time Stamp register enable (default)

Page 66 of 86

ICM-40609-D
13.36 WOM_CONFIG
Name: WOM_CONFIG
Address: 87 (57h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 3

WOM_INT_MODE

2

WOM_MODE

1:0

WOM_MODE1FUNCTION
Reserved
0: Set WoM interrupt on the OR of all enabled accelerometer thresholds
1: Set WoM interrupt on the AND of all enabled accelerometer threshold
0: Initial sample is stored. Future samples are compared to initial sample
1: Compare current sample to previous sample
00: Reserved
01: Set to 1 for WOM interrupt configuration
10: Reserved
11: Reserved

13.37 FIFO_CONFIG1
Name: FIFO_CONFIG1
Address: 95 (5Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
6

FIFO_RESUME_PARTIAL_RD

5

FIFO_WM_GT_TH

4
3
2
1
0

FIFO_TMST_FSYNC_EN
FIFO_TEMP_EN
FIFO_GYRO_EN
FIFO_ACCEL_EN

FUNCTION
Reserved
0: Partial FIFO read disabled, requires re-reading of the entire FIFO
1: FIFO read can be partial, and resume from last read point
Trigger FIFO watermark interrupt on every ODR (DMA write) if
FIFO_COUNT ≥ FIFO_WM_TH
Reserved
Must be set to 1 for all FIFO use cases when FSYNC is used
Enable temperature sensor packets to go to FIFO
Enable gyroscope packets to go to FIFO
Enable accelerometer packets to go to FIFO

13.38 FIFO_CONFIG2
Name: FIFO_CONFIG2
Address: 96 (60h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

FIFO_WM[7:0]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_REC setting. FIFO_WM_EN must be zero before writing thisregister. Interrupt only fires once. This register should be set to non-zerovalue, before choosing this interrupt source.

Page 67 of 86

ICM-40609-D
13.39 FIFO_CONFIG3
Name: FIFO_CONFIG3
Address: 97 (61h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 3:0

FIFO_WM[11:8]

FUNCTION
Reserved
Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_REC setting. FIFO_WM_EN must be zero before writing thisregister. Interrupt only fires once. This register should be set to non-zerovalue, before choosing this interrupt source.

Note: Do not set FIFO_WM to value 0.

13.40 FSYNC_CONFIG
Name: FSYNC_CONFIG
Address: 98 (62h)Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
7-

6:4

FSYNC_UI_SEL

3:2

-

1

FSYNC_UI_FLAG_CLEAR_SE
L

0

FSYNC_POLARITY

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
000: Do not tag FSYNC flag
001: Tag FSYNC flag to TEMP_OUT LSB
010: Tag FSYNC flag to GYRO_XOUT LSB
011: Tag FSYNC flag to GYRO_YOUT LSB
100: Tag FSYNC flag to GYRO_ZOUT LSB
101: Tag FSYNC flag to ACCEL_XOUT LSB
110: Tag FSYNC flag to ACCEL_YOUT LSB
111: Tag FSYNC flag to ACCEL_ZOUT LSB
Reserved
0: FSYNC flag is cleared when UI sensor register is updated
1: FSYNC flag is cleared when UI interface reads the sensor register LSB of
FSYNC tagged axis
0: Start from Rising edge of FSYNC pulse to measure FSYNC interval
1: Start from Falling edge of FSYNC pulse to measure FSYNC interval

Page 68 of 86

ICM-40609-D
13.41 INT_CONFIG0
Name: INT_CONFIG0
Address: 99 (63h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5:4

UI_DRDY_INT_CLEAR

3:2

FIFO_THS_INT_CLEAR

1:0

FIFO_FULL_INT_CLEARFUNCTION
Reserved
Data Ready Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
FIFO Threshold Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
FIFO Full Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read

13.42 INT_CONFIG1
Name: INT_CONFIG1
Address: 100 (64h)Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
7
6

INT_TPULSE_DURATION5

INT_TDEASSERT_DISABLE

4

INT_ASYNC_RESET

3:0-

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
Interrupt pulse duration
0: Interrupt pulse duration is 100µs. Use only if ODR < 4kHz. (Default)
1: Interrupt pulse duration is 8 µs. Required if ODR ≥ 4kHz, optional for ODR< 4kHz.
Interrupt de-assertion duration
0: The interrupt de-assertion duration is set to a minimum of 100µs. Use
only if ODR < 4kHz. (Default)
1: Disables de-assert duration. Required if ODR ≥ 4kHz, optional for ODR <4kHz.
User should change setting to 0 from default setting of 1, for proper INT1
and INT2 pin operation
Reserved

Page 69 of 86

ICM-40609-D
13.43 INT_SOURCE0
Name: INT_SOURCE0
Address: 101 (65h)Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
7
6

UI_FSYNC_INT1_EN

5

PLL_RDY_INT1_EN

4

RESET_DONE_INT1_EN

3

UI_DRDY_INT1_EN

2

FIFO_THS_INT1_EN

1

FIFO_FULL_INT1_EN

0

UI_AGC_RDY_INT1_EN

FUNCTION
Reserved
0: UI FSYNC interrupt not routed to INT1
1: UI FSYNC interrupt routed to INT1
0: PLL ready interrupt not routed to INT1
1: PLL ready interrupt routed to INT1
0: Reset done interrupt not routed to INT1
1: Reset done interrupt routed to INT1
0: UI data ready interrupt not routed to INT1
1: UI data ready interrupt routed to INT1
0: FIFO threshold interrupt not routed to INT1
1: FIFO threshold interrupt routed to INT1
0: FIFO full interrupt not routed to INT1
1: FIFO full interrupt routed to INT1
0: UI AGC ready interrupt not routed to INT1
1: UI AGC ready interrupt routed to INT1

13.44 INT_SOURCE1
Name: INT_SOURCE1
Address: 102 (66h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:3 2

WOM_Z_INT1_EN

1

WOM_Y_INT1_EN

0

WOM_X_INT1_EN

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
0: Z-axis WOM interrupt not routed to INT1
1: Z-axis WOM interrupt routed to INT1
0: Y-axis WOM interrupt not routed to INT1
1: Y-axis WOM interrupt routed to INT1
0: X-axis WOM interrupt not routed to INT1
1: X-axis WOM interrupt routed to INT1

Page 70 of 86

ICM-40609-D
13.45 INT_SOURCE3
Name: INT_SOURCE3
Address: 104 (68h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
6

UI_FSYNC_INT2_EN

5

PLL_RDY_INT2_EN

4

RESET_DONE_INT2_EN

3

UI_DRDY_INT2_EN

2

FIFO_THS_INT2_EN

1

FIFO_FULL_INT2_EN

0

UI_AGC_RDY_INT2_EN

FUNCTION
Reserved
0: UI FSYNC interrupt not routed to INT2
1: UI FSYNC interrupt routed to INT2
0: PLL ready interrupt not routed to INT2
1: PLL ready interrupt routed to INT2
0: Reset done interrupt not routed to INT2
1: Reset done interrupt routed to INT2
0: UI data ready interrupt not routed to INT2
1: UI data ready interrupt routed to INT2
0: FIFO threshold interrupt not routed to INT2
1: FIFO threshold interrupt routed to INT2
0: FIFO full interrupt not routed to INT2
1: FIFO full interrupt routed to INT2
0: UI AGC ready interrupt not routed to INT2
1: UI AGC ready interrupt routed to INT2

13.46 INT_SOURCE4
Name: INT_SOURCE4
Address: 105 (69h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:3 2

WOM_Z_INT2_EN

1

WOM_Y_INT2_EN

0

WOM_X_INT2_EN

FUNCTION
Reserved
0: Z-axis WOM interrupt not routed to INT2
1: Z-axis WOM interrupt routed to INT2
0: Y-axis WOM interrupt not routed to INT2
1: Y-axis WOM interrupt routed to INT2
0: X-axis WOM interrupt not routed to INT2
1: X-axis WOM interrupt routed to INT2

13.47 FIFO_LOST_PKT0
Name: FIFO_LOST_PKT0
Address: 108 (6Ch)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 FIFO_LOST_PKT_CNT[7:0]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Low byte, number of packets lost in the FIFO

Page 71 of 86

ICM-40609-D
13.48 FIFO_LOST_PKT1
Name: FIFO_LOST_PKT1
Address: 109 (6Dh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 FIFO_LOST_PKT_CNT[15:8]

FUNCTION
High byte, number of packets lost in the FIFO

13.49 SELF_TEST_CONFIG
Name: SELF_TEST_CONFIG
Address: 112 (70h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
76

ACCEL_ST_POWER

5
4
3
2
1
0

EN_AZ_ST
EN_AY_ST
EN_AX_ST
EN_GZ_ST
EN_GY_ST
EN_GX_ST

FUNCTION
Reserved
Set to 1 for accel self-test
Otherwise set to 0; Set to 0 after self-test is completed
Enable Z-accel self-test
Enable Y-accel self-test
Enable X-accel self-test
Enable Z-gyro self-test
Enable Y-gyro self-test
Enable X-gyro self-test

13.50 WHO_AM_I
Name: WHO_AM_I
Address: 117 (75h)Serial IF: R
Reset value: 0x3B
Clock Domain: SCLK_UI
BIT NAME
7:0 WHOAMI

FUNCTION
Register to indicate to user which device is being accessed

Description:
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default
value of the register is 0x3B. This is different from the I2C address of the device as seen on the slave I2C controller
by the applications processor.

Document Number: DS-000330
Revision: 1.2

Page 72 of 86

ICM-40609-D
13.51 REG_BANK_SEL
Note: This register is accessible from all register banks
Name: REG_BANK_SEL
Address: 118 (76h)Serial IF: R/W
Reset value: 0x00
Clock Domain: ALL
BIT NAME
7:3 -

2:0

BANK_SEL

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
Register bank selection
000: Bank 0 (default)
001: Bank 1010: Bank 2011: Bank 3
100: Bank 4
101: Reserved
110: Reserved
111: Reserved

Page 73 of 86

ICM-40609-D
14 USER BANK 1 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within USR Bank 1.

14.1 SENSOR_CONFIG0
Name: SENSOR_CONFIG0
Address: 03 (03h)Serial IF: R/W
Reset value: 0x40
Clock Domain: SCLK_UI
BIT NAME
7:6 5

ZG_DISABLE

4

YG_DISABLE

3

XG_DISABLE

2

ZA_DISABLE

1

YA_DISABLE

0

XA_DISABLE

FUNCTION
Reserved
0: Z gyroscope is on
1: Z gyroscope is disabled
0: Y gyroscope is on
1: Y gyroscope is disabled
0: X gyroscope is on
1: X gyroscope is disabled
0: Z accelerometer is on
1: Z accelerometer is disabled
0: Y accelerometer is on
1: Y accelerometer is disabled
0: X accelerometer is on
1: X accelerometer is disabled

14.2 GYRO_CONFIG_STATIC2
Name: GYRO_CONFIG_STATIC2
Address: 11 (0Bh)
Serial IF: R/W
Reset value: 0x03
Clock Domain: SCLK_UI
BIT NAME
7:2 1

GYRO_AAF_DIS

0

GYRO_NF_DIS

FUNCTION
Reserved
0: Enable Anti-Aliasing/Low Pass Filter
1: Disable Anti-Aliasing/Low Pass Filter (default)
0: Enable Notch Filter
1: Disable Notch Filter (default)

14.3 GYRO_CONFIG_STATIC3
Name: GYRO_CONFIG_STATIC3
Address: 12 (0Ch)
Serial IF: R/W
Reset value: 0x3F
Clock Domain: SCLK_UI
BIT NAME
7:6 5:0

GYRO_AAF_DELT

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details

Page 74 of 86

ICM-40609-D
14.4 GYRO_CONFIG_STATIC4
Name: GYRO_CONFIG_STATIC4
Address: 13 (0Dh)
Serial IF: R/W
Reset value: 0x81
Clock Domain: SCLK_UI
BIT NAME
7:0

GYRO_AAF_DELTSQR[7:0]

FUNCTION
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details

14.5 GYRO_CONFIG_STATIC5
Name: GYRO_CONFIG_STATIC5
Address: 14 (0Eh)
Serial IF: R/W
Reset value: 0x3F
Clock Domain: SCLK_UI
BIT NAME
7:4

GYRO_AAF_BITSHIFT

3:0

GYRO_AAF_DELTSQR[11:8]

FUNCTION
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details

14.6 GYRO_CONFIG_STATIC6
Name: GYRO_CONFIG_STATIC6
Address: 15 (0Fh)
Serial IF: R/W
Reset value: 0xEA
Clock Domain: SCLK_UI
BIT NAME
7:0

GYRO_X_NF_COSWZ[7:0]

FUNCTION
Used for gyroscope X-axis notch filter frequency selection
See section 5.1 for details

14.7 GYRO_CONFIG_STATIC7
Name: GYRO_CONFIG_STATIC7
Address: 16 (10h)Serial IF: R/W
Reset value: 0x28
Clock Domain: SCLK_UI
BIT NAME
7:0

GYRO_Y_NF_COSWZ[7:0]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Used for gyroscope Y-axis notch filter frequency selection
See section 5.1 for details

Page 75 of 86

ICM-40609-D
14.8 GYRO_CONFIG_STATIC8
Name: GYRO_CONFIG_STATIC8
Address: 17 (11h)Serial IF: R/W
Reset value: 0x07
Clock Domain: SCLK_UI
BIT NAME
7:0

GYRO_Z_NF_COSWZ[7:0]

FUNCTION
Used for gyroscope Z-axis notch filter frequency selection
See section 5.1 for details

14.9 GYRO_CONFIG_STATIC9
Name: GYRO_CONFIG_STATIC9
Address: 18 (12h)Serial IF: R/W
Reset value: 0x01
Clock Domain: SCLK_UI
BIT NAME
7:6 5

GYRO_Z_NF_COSWZ_SEL[0]4GYRO_Y_NF_COSWZ_SEL[0]3GYRO_X_NF_COSWZ_SEL[0]2GYRO_Z_NF_COSWZ[8]1

GYRO_Y_NF_COSWZ[8]0GYRO_X_NF_COSWZ[8]FUNCTION
Reserved
Used for gyroscope Z-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope Y-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope X-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope Z-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope Y-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope X-axis notch filter frequency selection
See section 5.1 for details

14.10 GYRO_CONFIG_STATIC10
Name: GYRO_CONFIG_STATIC10
Address: 19 (13h)Serial IF: R/W
Reset value: 0x11
Clock Domain: SCLK_UI
BIT NAME
7
6:4

GYRO_NF_BW_SEL

3:1

GYRO_HPF_BW_IND

0

GYRO_HPF_ORD_IND

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
Selects bandwidth for gyroscope notch filter
See section 5.1 for details
Selects HPF 3dB cutoff frequency bandwidth
See section 5.6 for details
Selects HPF filter order (see section 5.6 for details)
0: 1st order HPF
1: 2nd order HPF

Page 76 of 86

ICM-40609-D
14.11 XG_ST_DATA
Name: XG_ST_DATA
Address: 95 (5Fh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 XG_ST_DATA
X-gyro self-test data

14.12 YG_ST_DATA
Name: YG_ST_DATA
Address: 96 (60h)Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 YG_ST_DATA
Y-gyro self-test data

14.13 ZG_ST_DATA
Name: ZG_ST_DATA
Address: 97 (61h)Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ZG_ST_DATA
Z-gyro self-test data

14.14 TMSTVAL0
Name: TMSTVAL0
Address: 98 (62h)Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

TMST_VALUE[7:0]

FUNCTION
When TMST_STROBE is programmed, the current value of the internalcounter is latched to this register. Allows the full 20-bit precision of the timestamp to be read back.

14.15 TMSTVAL1
Name: TMSTVAL1
Address: 99 (63h)Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

TMST_VALUE[15:8]

Document Number: DS-000330
Revision: 1.2

FUNCTION
When TMST_STROBE is programmed, the current value of the internalcounter is latched to this register. Allows the full 20-bit precision of the timestamp to be read back.

Page 77 of 86

ICM-40609-D
14.16 TMSTVAL2
Name: TMSTVAL2
Address: 100 (64h)Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 3:0 TMST_VALUE[19:16]

FUNCTION
Reserved
When TMST_STROBE is programmed, the current value of the internalcounter is latched to this register. Allows the full 20-bit precision of the timestamp to be read back.

14.17 INTF_CONFIG4
Name: INTF_CONFIG4
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x02
Clock Domain: SCLK_UI
BIT NAME
7:2 1

SPI_AP_4WIRE

0-

FUNCTION
Reserved
0: AP interface uses 3-wire SPI mode
1: AP interface uses 4-wire SPI mode (default)
Reserved

14.18 INTF_CONFIG5
Name: INTF_CONFIG5
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x24
Clock Domain: SCLK_UI
BIT NAME
7:3 2:1

PIN19_FUNCTION

0-

Document Number: DS-000330
Revision: 1.2

FUNCTION
Reserved
Selects among the following functionalities for pin 9
00: INT2
01: FSYNC
10: Reserved
11: Reserved
Reserved

Page 78 of 86

ICM-40609-D
15 USER BANK 2 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within USR Bank 2.

15.1 ACCEL_CONFIG_STATIC2
Name: ACCEL_CONFIG_STATIC2
Address: 03 (03h)Serial IF: R/W
Reset value: 0x7F
Clock Domain: SCLK_UI
BIT NAME
7
6:1

ACCEL_AAF_DELT0

ACCEL_AAF_DIS

FUNCTION
Reserved
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
0: Enable accelerometer anti-aliasing filter
1: Disable accelerometer anti-aliasing filter (default)

15.2 ACCEL_CONFIG_STATIC3
Name: ACCEL_CONFIG_STATIC3
Address: 04 (04h)Serial IF: R/W
Reset value: 0x81
Clock Domain: SCLK_UI
BIT NAME
7:0

ACCEL_AAF_DELTSQR[7:0]

FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details

15.3 ACCEL_CONFIG_STATIC4
Name: ACCEL_CONFIG_STATIC4
Address: 05 (05h)Serial IF: R/W
Reset value: 0x3F
Clock Domain: SCLK_UI
BIT NAME
7:4

ACCEL_AAF_BITSHIFT

3:0

ACCEL_AAF_DELTSQR[11:8]

FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details

15.4 XA_ST_DATA
Name: XA_ST_DATA
Address: 59 (3Bh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 XA_ST_DATA
X-accel self-test data

Document Number: DS-000330
Revision: 1.2

Page 79 of 86

ICM-40609-D
15.5 YA_ST_DATA
Name: YA_ST_DATA
Address: 60 (3Ch)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 YA_ST_DATA
Y-accel self-test data

15.6 ZA_ST_DATA
Name: ZA_ST_DATA
Address: 61 (3Dh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ZA_ST_DATA
Z-accel self-test data

Document Number: DS-000330
Revision: 1.2

Page 80 of 86

ICM-40609-D
16 USER BANK 4 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within USR Bank 4.

16.1 ACCEL_WOM_X_THR
Name: ACCEL_WOM_X_THR
Address: 74 (4Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

WOM_X_TH

FUNCTION
Threshold value for the Wake on Motion Interrupt for X-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg

16.2 ACCEL_WOM_Y_THR
Name: ACCEL_WOM_Y_THR
Address: 75 (4Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

WOM_Y_TH

FUNCTION
Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg

16.3 ACCEL_WOM_Z_THR
Name: ACCEL_WOM_Z_THR
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

WOM_Z_TH

FUNCTION
Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg

16.4 OFFSET_USER0
Name: OFFSET_USER0
Address: 119 (77h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

GYRO_X_OFFUSER[7:0]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Lower bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

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ICM-40609-D
16.5 OFFSET_USER1
Name: OFFSET_USER1
Address: 120 (78h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4

GYRO_Y_OFFUSER[11:8]

3:0

GYRO_X_OFFUSER[11:8]

FUNCTION
Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
Upper bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

16.6 OFFSET_USER2
Name: OFFSET_USER2
Address: 121 (79h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

GYRO_Y_OFFUSER[7:0]

FUNCTION
Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

16.7 OFFSET_USER3
Name: OFFSET_USER3
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

GYRO_Z_OFFUSER[7:0]

FUNCTION
Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

16.8 OFFSET_USER4
Name: OFFSET_USER4
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4

ACCEL_X_OFFUSER[11:8]

3:0

GYRO_Z_OFFUSER[11:8]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Upper bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

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ICM-40609-D
16.9 OFFSET_USER5
Name: OFFSET_USER5
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

ACCEL_X_OFFUSER[7:0]

FUNCTION
Lower bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.

16.10 OFFSET_USER6
Name: OFFSET_USER6
Address: 125 (7Dh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

ACCEL_Y_OFFUSER[7:0]

FUNCTION
Lower bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.

16.11 OFFSET_USER7
Name: OFFSET_USER7
Address: 126 (7Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4

ACCEL_Z_OFFUSER[11:8]

3:0

ACCEL_Y_OFFUSER[11:8]

FUNCTION
Upper bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
Upper bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.

16.12 OFFSET_USER8
Name: OFFSET_USER8
Address: 127 (7Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0

ACCEL_Z_OFFUSER[7:0]

Document Number: DS-000330
Revision: 1.2

FUNCTION
Lower bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.

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ICM-40609-D
17 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:• Manufacturing Recommendationso Assembly Guidelines and Recommendationso PCB Design Guidelines and Recommendationso MEMS Handling Instructionso ESD Considerations
o Reflow Specificationo Storage Specificationso Package Marking Specificationo Tape & Reel Specificationo Reel & Pizza Box Labelo Packaging
o Representative Shipping Carton Label• Complianceo Environmental Complianceo DRC Complianceo Compliance Declaration Disclaimer

Document Number: DS-000330
Revision: 1.2

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ICM-40609-D
18 REVISION HISTORY
Revision Date

Revision

Description

08/01/2019

1.0

Initial Release10/24/2019

1.1

Updated Section 9

06/07/2022

1.2

Formatting updates

Document Number: DS-000330
Revision: 1.2

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ICM-40609-D

This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility
is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits
and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed
nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims
or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is
not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication orotherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied.
Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or soldin the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life
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instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2019—2022 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps,
DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company andproduct names may be trademarks of the respective companies with which they are associated.

©2019—2022 InvenSense. All rights reserved.

Document Number: DS-000330
Revision: 1.2

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