ICM-42670-P Datasheet
High Performance 6-Axis MotionTrackingTM IMU
ICM-42670-P HIGHLIGHTS

ICM-42670-P FEATURESThe ICM-42670-P is a high performance 6-axis MEMS
MotionTracking device that combines a 3-axis
gyroscope and a 3-axis accelerometer. It has aconfigurable host interface that supports I3CSM, I2C, andSPI serial communication, features up to 2.25 Kbytes
FIFO and 2 programmable interrupts with ultra-lowpower wake-on-motion support to minimize system
power consumption.
The ICM-42670-P supports the lowest gyro and accel
sensor noise in this IMU class, and has the highest
stability against temperature, shock (up to 20,000g) or
SMT/bend induced offset as well as immunity against
out-of-band vibration induced noise.
Other industry-leading features include on-chip APEX
Motion Processing engine for gesture recognition, andpedometer, along with programmable digital filters,
and an embedded temperature sensor.
The device supports a VDD operating range of 1.71V to
3.6V, and a separate VDDIO operating range from 1.71V
to 3.6V.

•
•
•
•
•
•
•

•

APPLICATIONS
•
•
•
•
•
•
•
•

BLOCK DIAGRAM

Low-Noise mode 6-axis current consumptionof 0.55 mA
Low-Power mode support for always-on
experience
Sleep Mode Current Consumption: 3.5µA
User selectable Gyro Full-scale range (dps):± 250/500/1000/2000
User selectable Accelerometer Full-scale
range (g): ± 2/4/8/16
User-programmable digital filters for gyro,
accel, and temp sensor
APEX Motion Functions: Pedometer, Tilt
Detection, Low-g Detection, Freefall
Detection, Wake on Motion, Significant
Motion Detection
Host interface: 12.5 MHz I3CSM, 1 MHz I2C,
24 MHz SPI

Wearables (Fitness Bands, SmartWatches,
Healthcare wearables)
Hearables (True Wireless Headsets)
Gaming Controllers
Smart Home Appliances
Smart TV remotes
DronesRobotics
Augmented Reality/Virtual Reality

ORDERING INFORMATIONPARTTEMP RANGE

ICM-42670-P†−40°C to +85°C

PACKAGE
2.5x3mm 14-Pin
LGA†Denotes RoHS and Green-Compliant Package

InvenSense Inc. reserves the right to change specifications
and information herein without notice unless the productis in mass production and the datasheet has been
designated by InvenSense in writing as subject to a
specified Product / Process Change Notification Method
regulation.

InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A+1(408) 988–7339
invensense.tdk.com

Document Number: DS-000451
Revision: 1.1
Rev. Date: 05/23/2022

ICM-42670-P
TABLE OF CONTENTS
ICM-42670-P Highlights ...................................................................................................................................... 1
Block Diagram ..................................................................................................................................................... 1
ICM-42670-P Features ........................................................................................................................................ 1
Applications ........................................................................................................................................................ 1
Ordering Information ......................................................................................................................................... 1
Introduction ........................................................................................................................................................ 8
Purpose and Scope .................................................................................................................................. 8
Product Overview .................................................................................................................................... 8
Applications ............................................................................................................................................. 8
Features .............................................................................................................................................................. 9
Gyroscope Features ................................................................................................................................. 9
Accelerometer Features .......................................................................................................................... 9
Motion Features ...................................................................................................................................... 9
Additional Features .................................................................................................................................. 9Electrical Characteristics ................................................................................................................................... 10
Gyroscope Specifications ....................................................................................................................... 10
Accelerometer Specifications ................................................................................................................ 11
Electrical Specifications ......................................................................................................................... 12
I2C Timing Characterization ................................................................................................................... 14
SPI Timing Characterization – 4-Wire SPI Mode .................................................................................... 15
SPI Timing Characterization – 3-Wire SPI Mode .................................................................................... 16
Absolute Maximum Ratings ................................................................................................................... 17
Applications Information .................................................................................................................................. 18
Pin Out Diagram and Signal Description ................................................................................................ 18
Typical Operating Circuit........................................................................................................................ 19
Bill of Materials for External Components ............................................................................................. 20
System Block Diagram ........................................................................................................................... 20
Overview ................................................................................................................................................ 20
Three-Axis MEMS Gyroscope................................................................................................................. 20
Three-Axis MEMS Accelerometer .......................................................................................................... 20
I3CSM, I2C and SPI Host Interface ............................................................................................................ 21
Self-Test ................................................................................................................................................. 21
Sensor Data Registers ........................................................................................................................ 21
Interrupts........................................................................................................................................... 21
Digital-Output Temperature Sensor .................................................................................................. 21
Bias and LDOs .................................................................................................................................... 21
Charge Pump ..................................................................................................................................... 21
Standard Power Modes ..................................................................................................................... 22
Signal Path ........................................................................................................................................................ 23
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FIFO................................................................................................................................................................... 24
Packet Structure .................................................................................................................................... 24
FIFO Header ........................................................................................................................................... 26
Maximum FIFO Storage ......................................................................................................................... 27
Programmable Interrupts ................................................................................................................................. 28
APEX Motion Functions .................................................................................................................................... 29
Digital Interface ................................................................................................................................................ 30
I3CSM, I2C and SPI Serial Interfaces ......................................................................................................... 30
I3CSM Interface ....................................................................................................................................... 30
I2C Interface ........................................................................................................................................... 32
I2C Communications Protocol ................................................................................................................ 32
I2C Terms ................................................................................................................................................ 34
SPI Interface ........................................................................................................................................... 35
Assembly........................................................................................................................................................... 36
Orientation of Axes ........................................................................................................................... 36
Package Dimensions .......................................................................................................................... 37
Device Package in Tape and Reel ..................................................................................................................... 38
Part Number Package Marking ......................................................................................................................... 39
Use Notes ......................................................................................................................................................... 40
Gyroscope Power On to Power Off Transition .................................................................................. 40
Accessing MREG1, MREG2 And MREG3 Registers ............................................................................................ 41
Register Map .................................................................................................................................................... 42
User Bank 0 Register Map ................................................................................................................. 42
User Bank MREG1 Register Map ....................................................................................................... 43
User Bank MREG2 Register Map ....................................................................................................... 44
User Bank MREG3 Register Map ....................................................................................................... 44
User Bank 0 Register Map – Descriptions......................................................................................................... 46
MCLK_RDY ......................................................................................................................................... 46
DEVICE_CONFIG ................................................................................................................................ 46
SIGNAL_PATH_RESET ........................................................................................................................ 47
DRIVE_CONFIG1 ................................................................................................................................ 48
DRIVE_CONFIG2 ................................................................................................................................ 49
DRIVE_CONFIG3 ................................................................................................................................ 50
INT_CONFIG ....................................................................................................................................... 51
TEMP_DATA1 .................................................................................................................................... 51
TEMP_DATA0 .................................................................................................................................... 52
ACCEL_DATA_X1 ................................................................................................................................ 52
ACCEL_DATA_X0 ................................................................................................................................ 52
ACCEL_DATA_Y1 ................................................................................................................................ 52
ACCEL_DATA_Y0 ................................................................................................................................ 53
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ACCEL_DATA_Z1 ................................................................................................................................ 53
ACCEL_DATA_Z0 ................................................................................................................................ 53
GYRO_DATA_X1................................................................................................................................. 53
GYRO_DATA_X0................................................................................................................................. 53
GYRO_DATA_Y1 ................................................................................................................................. 54
GYRO_DATA_Y0 ................................................................................................................................. 54
GYRO_DATA_Z1 ................................................................................................................................. 54
GYRO_DATA_Z0 ................................................................................................................................. 54
TMST_FSYNCH ................................................................................................................................... 54
TMST_FSYNCL .................................................................................................................................... 55
APEX_DATA4 ..................................................................................................................................... 55
APEX_DATA5 ..................................................................................................................................... 55
PWR_MGMT0 .................................................................................................................................... 56
GYRO_CONFIG0 ................................................................................................................................. 57
ACCEL_CONFIG0 ................................................................................................................................ 58
TEMP_CONFIG0 ................................................................................................................................. 59
GYRO_CONFIG1 ................................................................................................................................. 59
ACCEL_CONFIG1 ................................................................................................................................ 60
APEX_CONFIG0 .................................................................................................................................. 60
APEX_CONFIG1 .................................................................................................................................. 61
WOM_CONFIG ................................................................................................................................... 62
FIFO_CONFIG1 ................................................................................................................................... 62
FIFO_CONFIG2 ................................................................................................................................... 63
FIFO_CONFIG3 ................................................................................................................................... 63
INT_SOURCE0 .................................................................................................................................... 64
INT_SOURCE1 .................................................................................................................................... 64
INT_SOURCE3 .................................................................................................................................... 65
INT_SOURCE4 .................................................................................................................................... 65
FIFO_LOST_PKT0 ............................................................................................................................... 66
FIFO_LOST_PKT1 ............................................................................................................................... 66
APEX_DATA0 ..................................................................................................................................... 66
APEX_DATA1 ..................................................................................................................................... 66
APEX_DATA2 ..................................................................................................................................... 66
APEX_DATA3 ..................................................................................................................................... 67
INTF_CONFIG0 ................................................................................................................................... 67
INTF_CONFIG1 ................................................................................................................................... 68
INT_STATUS_DRDY ............................................................................................................................ 68
INT_STATUS ....................................................................................................................................... 69
INT_STATUS2 ..................................................................................................................................... 69
INT_STATUS3 ..................................................................................................................................... 69
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FIFO_COUNTH ................................................................................................................................... 70
FIFO_COUNTL .................................................................................................................................... 70
FIFO_DATA......................................................................................................................................... 70
WHO_AM_I ....................................................................................................................................... 70
BLK_SEL_W ........................................................................................................................................ 71
MADDR_W......................................................................................................................................... 71
M_W .................................................................................................................................................. 71
BLK_SEL_R ......................................................................................................................................... 71
MADDR_R .......................................................................................................................................... 72
M_R ................................................................................................................................................... 72
User Bank MREG1 Register Map – Descriptions............................................................................................... 73
TMST_CONFIG1 ................................................................................................................................. 73
FIFO_CONFIG5 ................................................................................................................................... 74
FIFO_CONFIG6 ................................................................................................................................... 75
FSYNC_CONFIG .................................................................................................................................. 76
INT_CONFIG0 ..................................................................................................................................... 76
INT_CONFIG1 ..................................................................................................................................... 77
SENSOR_CONFIG3 ............................................................................................................................. 77
ST_CONFIG ........................................................................................................................................ 78
SELFTEST ............................................................................................................................................ 79
INTF_CONFIG6 ................................................................................................................................... 79
INTF_CONFIG10 ................................................................................................................................. 79
INTF_CONFIG7 ................................................................................................................................... 80
OTP_CONFIG...................................................................................................................................... 80
INT_SOURCE6 .................................................................................................................................... 81
INT_SOURCE7 .................................................................................................................................... 81
INT_SOURCE8 .................................................................................................................................... 82
INT_SOURCE9 .................................................................................................................................... 82
INT_SOURCE10 .................................................................................................................................. 83
APEX_CONFIG2 .................................................................................................................................. 84
APEX_CONFIG3 .................................................................................................................................. 85
APEX_CONFIG4 .................................................................................................................................. 86
APEX_CONFIG5 .................................................................................................................................. 87
APEX_CONFIG9 .................................................................................................................................. 88
APEX_CONFIG10 ................................................................................................................................ 89
APEX_CONFIG11 ................................................................................................................................ 90
ACCEL_WOM_X_THR......................................................................................................................... 91
ACCEL_WOM_Y_THR ......................................................................................................................... 91
ACCEL_WOM_Z_THR ......................................................................................................................... 91
OFFSET_USER0 .................................................................................................................................. 91
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OFFSET_USER1 .................................................................................................................................. 92
OFFSET_USER2 .................................................................................................................................. 92
OFFSET_USER3 .................................................................................................................................. 92
OFFSET_USER4 .................................................................................................................................. 92
OFFSET_USER5 .................................................................................................................................. 93
OFFSET_USER6 .................................................................................................................................. 93
OFFSET_USER7 .................................................................................................................................. 93
OFFSET_USER8 .................................................................................................................................. 93
ST_STATUS1 ....................................................................................................................................... 94
ST_STATUS2 ....................................................................................................................................... 94
FDR_CONFIG ...................................................................................................................................... 95
APEX_CONFIG12 ................................................................................................................................ 96
User Bank MREG2 Register Map – Descriptions............................................................................................... 97
OTP_CTRL7 ........................................................................................................................................ 97
User Bank MREG3 Register Map – Descriptions............................................................................................... 98
XA_ST_DATA ...................................................................................................................................... 98
YA_ST_DATA ...................................................................................................................................... 98
ZA_ST_DATA ...................................................................................................................................... 98
XG_ST_DATA...................................................................................................................................... 98
YG_ST_DATA ...................................................................................................................................... 98
ZG_ST_DATA ...................................................................................................................................... 99
SmartMotion Product Family ......................................................................................................................... 100
Reference ....................................................................................................................................................... 101
Revision History .............................................................................................................................................. 102

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ICM-42670-P
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram .................................................................................................................................14
Figure 2. 4-Wire SPI Bus Timing Diagram ....................................................................................................................15
Figure 3. 3-Wire SPI Bus Timing Diagram ....................................................................................................................16
Figure 4. Pin Out Diagram for ICM-42670-P 2.5x3.0x0.76 mm LGA ............................................................................18
Figure 5. ICM-42670-P Application Schematic (I3CSM / I2C Interface to Host) .............................................................19
Figure 6. ICM-42670-P Application Schematic (SPI Interface to Host) ........................................................................19
Figure 7. ICM-42670-P System Block Diagram.............................................................................................................20
Figure 8. ICM-42670-P Signal Path ..............................................................................................................................23
Figure 9. FIFO Packet Structure ...................................................................................................................................24
Figure 10. Maximum FIFO Storage ..............................................................................................................................27
Figure 11. START and STOP Conditions .......................................................................................................................32
Figure 12. Acknowledge on the I2C Bus .......................................................................................................................33
Figure 13. Complete I2C Data Transfer ........................................................................................................................33
Figure 14. Typical SPI Master/Slave Configuration ......................................................................................................35
Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................36
Figure 16. ICM-42670-P Device Package in Tape and Reel ..........................................................................................38
Figure 17. Tape Dimensions with ICM-42670-P Device Package .................................................................................38

TABLE OF TABLES
Table 1. Gyroscope Specifications ...............................................................................................................................10
Table 2. Accelerometer Specifications ........................................................................................................................11
Table 3. D.C. Electrical Characteristics .........................................................................................................................12
Table 4. A.C. Electrical Characteristics .........................................................................................................................13
Table 5. I2C Timing Characteristics...............................................................................................................................14
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) .................................................................................15
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) .................................................................................16
Table 8. Absolute Maximum Ratings ...........................................................................................................................17
Table 9. Signal Descriptions .........................................................................................................................................18
Table 10. Bill of Materials ............................................................................................................................................20
Table 11. Standard Power Modes for ICM-42670-P ....................................................................................................22
Table 12. I3CSM CCC Commands...................................................................................................................................32
Table 13. I2C Terms ......................................................................................................................................................34

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ICM-42670-P

INTRODUCTIONPURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on
the ICM-42670-P Single-Interface MotionTracking device. The device is housed in a small 2.5x3x0.76 mm 14-pin
LGA package.

PRODUCT OVERVIEWThe ICM-42670-P is a 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis accelerometer ina small 2.5x3x0.76 mm (14-pin LGA) package. It also features up to 2.25 Kbytes FIFO that can lower the traffic on
the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data
and then go into a low-power mode. ICM-42670-P, with its 6-axis integration, enables manufacturers to eliminate
the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing
optimal motion performance for consumers.
The gyroscope supports four programmable full-scale range settings from ±250 dps to ±2000 dps and theaccelerometer supports four programmable full-scale range settings from ±2g to ±16g.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The device features I3CSM, I2C, and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.71V to 3.6V.
The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface
supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I2C
interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz.
The device provides high robustness by supporting 20,000g shock reliability.

APPLICATIONS
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•
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Wearables (Fitness Bands, SmartWatches, Healthcare wearables)
Hearables (True Wireless Headsets)
Gaming Controllers
Smart Home Appliances
Smart TV remotes
DronesRobotics
Augmented Reality/Virtual Reality

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ICM-42670-P

FEATURESGYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-42670-P includes a wide range of features:
•
•
•
•
•

Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of±250, ±500, ±1000, and ±2000 degrees/sec
Low Noise (LN) power mode support
Digitally programmable low-pass filters
Factory calibrated sensitivity scale factor
Self-test

ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-42670-P includes a wide range of features:
•
•
•
•
•

Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2g, ±4g, ±8g and±16g
Low Noise (LN) and Low Power (LP) power modes support
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test

MOTION FEATURES
ICM-42670-P includes the following motion features, also known as APEX (Advanced Pedometer and Event
Detection – neXt gen)
•
•
•
•
•
•

Pedometer: Tracks step count and issues a step detect Interrupt.
Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmabletime.
Low-g Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a
programmable threshold and stays below the threshold for a programmable time.
Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration.
Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmablethreshold. This motion event can be used to enable device operation from sleep mode.
Significant Motion Detector (SMD): Detects significant motion based on accelerometer data.

ADDITIONAL FEATURES
ICM-42670-P includes the following additional features:
•
•
•
•
•
•
•
•

Up to 2.25 Kbytes FIFO buffer enables the applications processor to read the data in bursts
User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
12.5M Hz I3CSM (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode) / 1 MHz I2C / 24 MHz SPI
slave host interface
Digital-output temperature sensor
Smallest and thinnest LGA package for portable devices: 2.5x3x0.76 mm (14-pin LGA)
20,000g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant

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ICM-42670-P

ELECTRICAL CHARACTERISTICSGYROSCOPE SPECIFICATIONS
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

UNITS

NOTES

±2000

º/s

±1000
±500
±250

º/s
º/s
º/s

2
2

16
16.4

bits
LSB/(º/s)

GYRO_UI_FS_SEL=3

32.8
65.5
131

LSB/(º/s)
LSB/(º/s)
LSB/(º/s)

Sensitivity Scale Factor Initial Tolerance
Sensitivity Scale Factor Variation Over
Temperature
Nonlinearity
Cross-Axis Sensitivity

25°C

±1

%

1, 7

-40°C to +85°C; Board-Level±0.007%/ºC

3, 6Best fit straight line; 25°C; Board-Level
Board-level

±0.1
±2

%
%

3, 6
3, 6

Initial ZRO Tolerance

25°C

±1

º/s

1, 7

ZRO Variation vs. Temperature-40°C to +85°C; Board-LevelOTHER PARAMETERS@ 10 Hz±0.015º/s/ºC

3, 6

0.007

º/s /√Hz1º/s-rms
kHz
Hz
ms
Hz

4
1
2
3, 8
2

GYROSCOPE SENSITIVITY
GYRO_UI_FS_SEL=0
GYRO_UI_FS_SEL=1

Full-Scale Range

GYRO_UI_FS_SEL=2
GYRO_UI_FS_SEL=3

Gyroscope ADC Word Length

Sensitivity Scale Factor

Output in two’s complement format
GYRO_UI_FS_SEL=0
GYRO_UI_FS_SEL=1
GYRO_UI_FS_SEL=2

TYP

MAX

2
2
2, 5
2
2
2
2

ZERO-RATE OUTPUT (ZRO)

Rate Noise Spectral Density
Total RMS Noise
Gyroscope Mechanical Frequencies
Low Pass Filter Response
Gyroscope Start-Up Time
Output Data Rate

Bandwidth = 100 Hz
25
16
Time from gyro enable to gyro drive ready

0.07
28

30
180

30
12.5

1600

Table 1. Gyroscope Specifications
Notes:
1.
2.
3.
4.
5.
6.
7.
8.

Tested in production at component-level.
Guaranteed by design.
Derived from validation or characterization of parts, not tested in production.
Calculated from Rate Noise Spectral Density.
20-bits data format supported in FIFO, see section 6.1.
Board-level spec values depend on specific board design. For design information of boards used for device characterization, that forms
the basis of the spec values reported here, please contact your local TDK InvenSense FAE.
Value after factory test and trim.
Measurement conditions: Gyroscope ODR = 1600Hz; Register field GYRO_UI_FILT_BW set to 000 (low pass filter bypassed).

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ICM-42670-P
ACCELEROMETER SPECIFICATIONS
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

UNITS

NOTES

±16

g

±8
±4

g
g

2
2

ACCEL_UI_FS_SEL=3
Output in two’s complement format
ACCEL_UI_FS_SEL=0

±2
16
2,048

g
bits
LSB/g

ACCEL_UI_FS_SEL=1
ACCEL_UI_FS_SEL=2
ACCEL_UI_FS_SEL=3

4,096
8,192
16,384

LSB/g
LSB/g
LSB/g

25°C

±1

%

1, 7

-40°C to +85°C; Board-Level

ACCELEROMETER SENSITIVITYACCEL_UI_FS_SEL=0
Full-Scale Range

ACCEL_UI_FS_SEL=1
ACCEL_UI_FS_SEL=2

ADC Word Length

Sensitivity Scale Factor

Sensitivity Scale Factor Initial
Tolerance
Sensitivity Change vs. Temperature

MIN

TYP

MAX

2
2
2, 5
2
2
2
2

Nonlinearity
Cross-Axis Sensitivity

Best Fit Straight Line, ±2g; Board-Level
Board-level

±0.01
±0.1
±1

%/ºC
%
%

3, 6
3, 6
3, 6

Initial Tolerance
Zero-G Level Change vs. Temperature

ZERO-G OUTPUT
25°C-40°C to +85°C; Board-Level

±25
±0.15

mg
mg/ºC

1, 7
3, 6

OTHER PARAMETERS
Power Spectral Density@ 10 Hz100µg/√Hz1

RMS Noise
Low Pass Filter Response
Accelerometer Startup Time
Output Data Rate

Bandwidth = 100 Hz

1.0

mg-rms
Hz
ms
Hz

4
2
3, 8
2

16
From sleep mode to valid data

180
101.5625

1600

Table 2. Accelerometer Specifications
Notes:
1.
2.
3.
4.
5.
6.
7.
8.

Tested in production at component-level.
Guaranteed by design.
Derived from validation or characterization of parts, not tested in production.
Calculated from Power Spectral Density.
20-bits data format supported in FIFO, see section 6.1.
Board-level spec values depend on specific board design. For design information of boards used for device characterization, that forms
the basis of the spec values reported here, please contact your local TDK InvenSense FAE.
Value after factory test and trim.
Measurement conditions: Accelerometer ODR = 1600Hz; Register field ACCEL_UI_FILT_BW set to 000 (low pass filter bypassed).

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ICM-42670-P
ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics

3.3.1

Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

1.71
1.71

1.8
1.8

3.6
3.6

V
V

1
1

SUPPLY VOLTAGES
VDD
VDDIO
SUPPLY CURRENTS
6-Axis Gyroscope + Accelerometer

0.55

mA

2

3-Axis Accelerometer

0.20

mA

2

3-Axis Gyroscope

0.42

mA

2

Full-Chip Sleep ModeAt 25ºC

3.5

µA

2

Specified Temperature Range

TEMPERATURE RANGE
Performance parameters are not applicablebeyond Specified Temperature Range°C

1

Low-Noise Mode-40

Table 3. D.C. Electrical Characteristics
Notes:
1.
2.

Guaranteed by design.
Derived from validation or characterization of parts, not tested in production.

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ICM-42670-P
3.3.2

A.C. Electrical Characteristics

Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

SUPPLIES
Supply Ramp Time

Valid power-on RESET

0.1

Power Supply Noise

3

ms

1

mV
peak-peak

1

°C
LSB
bits
Hz
°C

1
3
2
2, 4
3

0.64

sec

2

129
2.01

LSB/°C
LSB/°C

1
1

1

ms

1

10
TEMPERATURE SENSOR

Operating Range
25°C Output
ADC Resolution
ODR
Room Temperature Offset
Stabilization Time (fixed number of clock
cycles)Sensitivity
Sensitivity for FIFO data

Ambient

Start-up time for register read/write

From power-up-40Output in two’s complement format

85
0
16

With Filter
25°C

1.5625-3

TrimmedTrimmed

125
1.95

1600
3

126.9
1.983

POWER-ON RESETI2C ADDRESSAP_AD0 = 0
AP_AD0 = 1

I2C ADDRESS

1101000
1101001

DIGITAL INPUTS (FSYNC, SCLK, SDI, CS)
0.7*VDDIO

VIH, High Level Input Voltage

V

VIL, Low Level Input Voltage

0.3*VDDIO

CI, Input Capacitance<10
DIGITAL OUTPUT (SDO, INT1, INT2)
0.9*VDDIO

VOH, High Level Output Voltage

RLOAD=1 MΩ;

VOL1, LOW-Level Output Voltage

RLOAD=1 MΩ;

VOL.INT, INT Low-Level Output Voltage
Output Leakage Current

OPEN=1, 0.3 mA sink
Current
OPEN=1tINT, INT Pulse Width

int_tpulse_duration= 0 , 1 (100us, 8us ) ;

V

1

pF

V
0.1*VDDIO

V

0.1

V

100

1

nA

8

100

µs

VIL, LOW-Level Input Voltage-0.5V

0.3*VDDIOV

VIH, HIGH-Level Input Voltage

0.7*VDDIOVDDIO +
0.5V

V

I2C I/O (SCL, SDA)

Vhys, Hysteresis

0.1*VDDIO

VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current

3 mA sink current0

VOL=0.4 V
VOL=0.6 V

3
6Output Leakage Current
tof, Output Fall Time from VIHmax to VILmax

Clock Frequency Initial Tolerance
Frequency Variation over Temperature

20+0.1Cb

1

nA
300

ns

INTERNAL CLOCK SOURCE
CLKSEL=`2b00 or gyro inactive; 25°C
-3

+3

%

1

CLKSEL=`2b01 and gyro active; 25°C

+1

%

1

CLKSEL=`2b00 or gyro inactive; -40°C to +85°C

±3

%

1

CLKSEL=`2b01 and gyro active; -40oC to +85oC

±1

%

1

-1

Expected results based on design, will be updated after characterization. Not tested in production.
Guaranteed by design.
Production tested.
Temperature sensor ODR is the higher value between gyroscope and accelerometer ODR.

Page 13 of 103
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Revision: 1.1

V
mA
mA

100
Cb bus capacitance in pf

Table 4. A.C. Electrical Characteristics
Notes:
1.
2.
3.
4.

V
0.4

ICM-42670-P
I2C TIMING CHARACTERIZATION
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Slew Rate can be
configured by the user using register DRIVE_CONFIG2.
PARAMETERSI2C TIMINGfSCL, SCL Clock Frequency

CONDITIONSI2C FAST-MODE PLUS

MIN

tHD.STA, (Repeated) START Condition Hold Time

TYP

MAX

UNITS

NOTES

1

MHz

1

µs

1

µs

1

µs
µs
µs

1
1
1

ns

0.26
0.5
0.26
0.26

tLOW, SCL Low PeriodtHIGH, SCL High PeriodtSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time

050

tSU.DAT, SDA Data Setup Time
tSU.STO, STOP Condition Setup TimetBUF, Bus Free Time Between STOP and START
Condition
Cb, Capacitive Load for each Bus Line

0.5

µs

1
1

0.5

µs

1

pF

1

µs
µs

1
1

550
0.45
0.45

tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time
Table 5. I2C Timing Characteristics
Notes:
1.

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets

tf
SDA

tSU.DAT

tr

70%
30%

70%
30%
continued below at

tf
SCL

tr
70%
30%

S

tHD.STA

tVD.DAT
70%
30%

tHD.DAT
1/fSCLtLOW

1st clock cycle

9th clock cycle

tHIGH

tBUF
SDA

70%
30%

A

tSU.STA

tHD.STA

SCL

70%
30%

Sr

tSU.STO

tVD.ACK
9th clock cycle

Figure 1. I2C Bus Timing Diagram

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P

S

A

ICM-42670-P
SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Slew Rate can be
configured by the user using register DRIVE_CONFIG3.
PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

24

MHz

1

SPI TIMING
fSPC, SCLK Clock Frequency

Default

tLOW, SCLK Low Period

17

ns

1

tHIGH, SCLK High Period

17

ns

1

tSU.CS, CS Setup Time

17

ns

1

tHD.CS, CS Hold Time

5

ns

1

tSU.SDI, SDI Setup Time

13

ns

1

ns

1

ns

1

ns

1

ns

1

tHD.SDI, SDI Hold Time

8

tVD.SDO, SDO Valid Time

Cload = 20 pF

tHD.SDO, SDO Hold Time

Cload = 20 pF

18.5
3.5

tDIS.SDO, SDO Output Disable Time

18.5
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation)

Notes:
1.

CS

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets

70%
30%

tFall

tSU;CS
SCLK

tHIGH

70%
30%

tLOW

tHD;SDILSB INMSB INtVD;SDOSDOMSB OUT70%
30%

Page 15 of 103

tDIS;SDO

tHD;SDO

Figure 2. 4-Wire SPI Bus Timing Diagram

Document Number: DS-000451
Revision: 1.1

tHD;CS

70%
30%

tSU;SDI

SDI

tRise

1/fCLKLSB OUTICM-42670-P
SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Slew Rate can be
configured by the user using register DRIVE_CONFIG3.
PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

24

MHz

1

SPI TIMING
fSPC, SCLK Clock Frequency

Default

tLOW, SCLK Low Period

17

ns

1

tHIGH, SCLK High Period

17

ns

1

tSU.CS, CS Setup Time

17

ns

1

tHD.CS, CS Hold Time

5

ns

1

tSU.SDIO, SDIO Input Setup Time

13

ns

1

ns

1

ns

1

ns

1

ns

1

tHD.SDIO, SDIO Input Hold Time

8

tVD.SDIO, SDIO Output Valid Time

Cload = 20 pF

tHD.SDIO, SDIO Output Hold Time

Cload = 20 pF

18.5
3.5

tDIS.SDIO, SDIO Output Disable Time

18.5

Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1.

CS

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets

70%
30%

tFall

tSU;CS
SCLK

tHIGH

tRise

1/fCLK

tHD;CS

70%
30%

tSU;SDIO

SDIO

I

O

70%
30%

tLOW

tHD;SDIOLSB INMSB INtVD;SDIOMSB OUT

70%
30%

Figure 3. 3-Wire SPI Bus Timing Diagram

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tDIS;SDIOtHD;SDIOLSB OUTICM-42670-P
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to theabsolute maximum ratings conditions for extended periods may affect device reliability.
PARAMETERRATING

Supply Voltage, VDD-0.5V to 4V

Supply Voltage, VDDIO-0.5V to 4V

Input Voltage Level (FSYNC, SCL, SDA)

-0.5V to VDDIO + 0.5 V

Acceleration (Any Axis, unpowered)

20,000g for 0.2 ms

Operating Temperature Range-40°C to +85°C

Storage Temperature Range-40°C to +125°C
2 kV (HBM);

Electrostatic Discharge (ESD) Protection

500V (CDM)
JEDEC Class II (2),125°C

Latch-up±100 mA
Table 8. Absolute Maximum Ratings

Page 17 of 103
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ICM-42670-P

APPLICATIONS INFORMATIONPIN OUT DIAGRAM AND SIGNAL DESCRIPTIONPIN NUMBERPIN NAME

PIN DESCRIPTION
AP_SDO: AP SPI serial data output (4-wire mode);
AP_AD0: AP I3CSM / I2C slave address LSB
No Connect or Connect to GND or Connect to VDDIO

1

AP_SDO / AP_AD0

2

RESV

3

RESV

4

INT1 / INT

5

VDDIO

No Connect or Connect to GND or Connect to VDDIO
INT1: Interrupt 1 (Note: INT1 can be push-pull or open drain)
INT: All interrupts mapped to pin 4
IO power supply voltage

6

GND

Power supply ground

7

FSYNC

Frame sync input; Connect to GND if FSYNC not used

8

VDD

Power supply voltage

9

INT2

INT2: Interrupt 2 (Note: INT2 can be push-pull or open drain)

10

RESV

No Connect or Connect to GND or Connect to VDDIO

11

RESV

12

AP_CS

13

AP_SCL / AP_SCLKNo Connect or Connect to GND or Connect to VDDIOAP SPI Chip select (AP SPI interface); Connect to VDDIO if using AP
I3CSM / I2C interface
AP_SCL: AP I3CSM / I2C serial clock; AP_SCLK: AP SPI serial clock14

AP_SDA / AP_SDIO /AP_SDI

AP_SDA: AP I3CSM / I2C serial data; AP_SDIO: AP SPI serial data I/O(3-wire mode); AP_SDI: AP SPI serial data input (4-wire mode)

AP_SDA / AP_SDIO / AP_SDI

AP_SCL / AP_SCLK

AP_CS

14

13

12

Table 9. Signal Descriptions

11

RESV

10

RESV

3

9

INT2

4

8

AP_SDO / AP_AD0

1

RESV

2

RESV
INT1 / INT

+Y

VDD

FSYNC

GND

VDDIO

+X

Figure 4. Pin Out Diagram for ICM-42670-P 2.5x3.0x0.76 mm LGA
Page 18 of 103
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Revision: 1.1

+Y

+Z

7

6

5

ICM-42670-P+Z+X

ICM-42670-P
TYPICAL OPERATING CIRCUIT

RESV

14

AP_SCL

AP_SDA

AP_AD0

13

VDDIO

12
11

1

2

10

ICM-42670-P
RESV
INT1 / INT

3

9

4

8

RESV
RESV

INT2
– 3.6VDC

5

6

VDD

7

FSYNC

GND

VDDIO

C1, 0.1 mF

C2, 2.2 mF– 3.6VDC
C3, 10 nF

Figure 5. ICM-42670-P Application Schematic (I3CSM / I2C Interface to Host)
Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.

AP_SCLKRESV

AP_SDIO /AP_SDI

AP_SDO

AP_CS

14

13

12

1

2

11

RESV

10

RESV

ICM-42670-P
RESV
INT1 / INT

3

9

4

8

INT2
– 3.6VDC

5

6

VDD

7

FSYNC

GND

VDDIO

C1, 0.1 mF

C2, 2.2 mF– 3.6VDC
C3, 10 nF

Figure 6. ICM-42670-P Application Schematic (SPI Interface to Host)

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ICM-42670-P
BILL OF MATERIALS FOR EXTERNAL COMPONENTSCOMPONENTLABELSPECIFICATIONQUANTITYVDD Bypass Capacitors

C1
C2

X7R, 0.1µF ±10%
X7R, 2.2µF ±10%

1
1

VDDIO Bypass Capacitor

C3

X7R, 10nF ±10%

1Table 10. Bill of Materials

SYSTEM BLOCK DIAGRAM

Figure 7. ICM-42670-P System Block Diagram
Note: The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration options.

OVERVIEWThe ICM-42670-P is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•

Three-axis MEMS gyroscopeThree-axis MEMS accelerometer
I3CSM, I2C, and SPI serial communications interfaces to Host
Self-Test
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes

THREE-AXIS MEMS GYROSCOPE
The ICM-42670-P includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes.
When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detectedby a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is
proportional to the angular rate. This voltage is digitized using on-chip Analog-to-Digital Converter (ADC) to sample
each axis. The full-scale range of the gyro sensor may be digitally programmed to ±250, ±500, ±1000, and ±2000
degrees per second (dps).

THREE-AXIS MEMS ACCELEROMETERThe ICM-42670-P includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacementof a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The ICM-42670-P
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. Whenthe device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The
accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The fullscale range of the digital output can be adjusted to ±2g, ±4g, ±8g and ±16g.

Page 20 of 103
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ICM-42670-P
I3CSM, I2C AND SPI HOST INTERFACEThe ICM-42670-P communicates to the application processor using an I3CSM, I2C, or SPI serial interface. The ICM42670-P always acts as a slave when communicating to the application processor.

SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for eachmeasurement axis can be activated by means of the gyroscope and accelerometer self-test registers. When the
self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output
signal is used to observe the self-test response. The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits, the part has passed self-test.
When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.

SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They
are read-only registers and are accessed via the serial interface. Data from these registers may be read any time.

INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include theinterrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) new data is available to be read (from the FIFO and Data registers); (2)accelerometer event interrupts; (3) FIFO watermark; (4) FIFO full. The interrupt status can be read from theInterrupt Status register.

DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-42670-P die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
Temperature sensor ODR is the higher value between gyroscope and accelerometer ODR.

BIAS AND LDOS
The bias and LDO section generate the internal supply and the reference voltages and currents required by the
ICM-42670-P.

CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.

Page 21 of 103
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ICM-42670-P
STANDARD POWER MODES
The following table lists the user-accessible power modes for ICM-42670-P.
MODE
1
2
3
4
5
6

NAME
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode

GYRO
Off
Drive On
Off
Off
On
On

Table 11. Standard Power Modes for ICM-42670-P

Page 22 of 103
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Revision: 1.1

ACCEL
Off
Off
Duty-Cycled
On
Off
On

ICM-42670-P

SIGNAL PATH
The following figure shows a block diagram of the signal path for ICM-42670-P.

Low-Noise Mode
ADC

Anti-Alias
Filter (AAF)

1st Order
LPF
ODR
Selection

Low-Power Mode (Accel Only)

Average

SensorRegisters

UI Interface

FSR Selection
ACCEL_MODE

Figure 8. ICM-42670-P Signal Path

The signal path starts with ADCs for the gyroscope and accelerometer. Low-Noise Mode and Low-Power Mode
options are available for the accelerometer and are selectable using register field ACCEL_MODE. Only Low-NoiseMode is available for gyroscope.
In Low-Noise Mode, the ADC output is sent through an Anti-Alias Filter (AAF). The AAF is a filter with fixedcoefficients (not user configurable), also the AAF cannot be bypassed. The AAF is followed by a 1st Order Low Pass
Filter (LPF) with user selectable filter bandwidth options using register fields ACCEL_UI_FILT_BW and
GYRO_UI_FILT_BW.
In Low-Power Mode, the accelerometer ADC output is sent through an Average filter, with user configurable
average filter setting using register field ACCEL_UI_AVG.
The output of 1st Order LPF in Low-Noise Mode, or Average filter in Low-Power Mode is subject to ODR selection,with user selectable ODR using register fields GYRO_ODR and ACCEL_ODR. This is followed by Full Scale Range(FSR) selection based on user configurable settings for register fields GYRO_UI_FS_SEL and ACCEL_UI_FS_SEL.

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ICM-42670-P

FIFO
The ICM-42670-P contains up to 2.25Kbyte FIFO register that is accessible via the serial interface. Shared SRAM isused for FIFO and APEX features. Default configuration of the device provides 1Kbyte FIFO and rest of the SRAM isused for APEX. User may disable APEX features to extend FIFO size to 2.25 Kbytes using register field
APEX_DISABLE in register SENSOR_CONFIG3.
User can configure the FIFO Data Rate (FDR) to control the rate at which FIFO packets are written to the FIFO.
Register field FDR_SEL in register FDR_CONFIG (register 0x66h in Bank MREG1) provides FDR control, based on
settings for FIFO packet rate decimation factor. User must disable sensors when initializing FDR_SEL value or
making changes to it.

PACKET STRUCTURE
Figure 9 shows the FIFO packet structures supported in ICM-42670-P. Base data format for gyroscope andaccelerometer is 16-bits per element. 20-bits data format support is included in one of the packet structures.
When 20-bits data format is used, gyroscope data consists of 19-bits of actual data and the LSB is always set to 0,
accelerometer data consists of 18-bits of actual data and the two lowest order bits are always set to 0. When 20bits data format is used, the only FSR settings that are operational are ±2000 dps for gyroscope and ±16g foraccelerometer, even if the FSR selection register settings are configured for other FSR values. The corresponding
sensitivity scale factor values are 131 LSB/dps for gyroscope and 8192 LSB/g for accelerometer.

Header(1 byte)Header(1 byte)Header(1 byte)Header(1 byte)Accelerometer Data
(6 bytes)

Gyroscope Data
(6 bytes)

Accelerometer Data
(6 bytes)

Accelerometer Data
(6 bytes)

Temperature Data
(1 byte)Temperature Data
(1 byte)Packet 1

Packet 2

Gyroscope Data
(6 bytes)

Gyroscope Data
(6 bytes)

Temperature Data
(1 byte)Temperature Data
(2 bytes)

TimeStamp(2 bytes)

TimeStamp(2 bytes)

Packet 3
20-bit Extension(3 bytes)
Packet 4
Figure 9. FIFO Packet Structure

The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.

Page 24 of 103
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ICM-42670-P
Packet 1: Individual data is packaged in Packet 1 as shown below.
BYTE

CONTENT

0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07

FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]Temperature[7:0]

Packet 2: Individual data is packaged in Packet 2 as shown below.
BYTE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07

CONTENTFIFO Header
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]Temperature[7:0]

Packet 3: Individual data is packaged in Packet 3 as shown below.
BYTE

CONTENT

0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F

FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]Temperature[7:0]
TimeStamp[15:8]
TimeStamp[7:0]

Page 25 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
Packet 4: Individual data is packaged in Packet 4 as shown below.
BYTE

CONTENT

0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12

FIFO Header
Accel X [19:12]
Accel X [11:4]
Accel Y [19:12]
Accel Y [11:4]
Accel Z [19:12]
Accel Z [11:4]
Gyro X [19:12]
Gyro X [11:4]
Gyro Y [19:12]
Gyro Y [11:4]
Gyro Z [19:12]
Gyro Z [11:4]
Temperature[15:8]
Temperature[7:0]
TimeStamp[15:8]
TimeStamp[7:0]
Accel X [3:0]
Gyro X [3:0]
Accel Y [3:0]
Gyro Y [3:0]0x13

Accel Z [3:0]

Gyro Z [3:0]

FIFO HEADER
The following table shows the structure of the 1byte FIFO header.
BIT FIELD

ITEM

7HEADER_MSG

6HEADER_ACCEL

5HEADER_GYRO

4

HEADER_20

3:2

HEADER_TIMESTAMP_FSYNC

1

HEADER_ODR_ACCEL

0HEADER_ODR_GYRODESCRIPTION
1: FIFO is empty
0: Packet contains sensor data
1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN must be 1
0: Packet does not contain accel sample
1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must be 1
0: Packet does not contain gyro sample
1: Packet has a new and valid sample of extended 20-bit data for gyro and/or accel
0: Packet does not contain a new and valid extended 20-bit data
00: Packet does not contain timestamp or FSYNC time data
01: Reserved
10: Packet contains ODR Timestamp
11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC (only if
FIFO_TMST_FSYNC_EN is 1)
1: The ODR for accel is different for this accel data packet compared to the previous accel
packet0: The ODR for accel is the same as the previous packet with accel
1: The ODR for gyro is different for this gyro data packet compared to the previous gyro
packet0: The ODR for gyro is the same as the previous packet with gyro

Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set.

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ICM-42670-P
MAXIMUM FIFO STORAGE
The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As
shown in Figure 10, the physical FIFO size is 1 Kbytes or 2.25 Kbytes (depending on APEX_DISABLE setting as
described above). A number of bytes equal to the packet size selected (see section 6.1) is reserved to prevent
reading a packet during write operation. Additionally, a read cache 2 packets wide is available.
The total storage available is up to the maximum number of packets that can be accommodated in 1 Kbytes (or2.25 Kbytes) plus 40 cache bytes. Note: the cache can hold 5 packets instead of 2 in the specific case when thepacket size is 8bytes and the FIFO mode is Stop-on-full.

FIFO 1Kbytes or 2.25Kbytes

2 Packet Size

Read Cache

1Kbytes or 2.25Kbytes –1 Packet Size
Reserved to prevent reading apacket during write operation

Figure 10. Maximum FIFO Storage

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Revision: 1.1

packet sizeICM-42670-P

PROGRAMMABLE INTERRUPTS
The ICM-42670-P has a programmable interrupt system that can generate an interrupt signal on the INT pins.
Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There
are two interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register
section. The following configuration options are available for the interrupts•••

INT1 and INT2 can be push-pull or open drain
Level or pulse mode
Active high or active low

Additionally, ICM-42670-P includes In-band Interrupt (IBI) support for the I3CSM interface.

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ICM-42670-P

APEX MOTION FUNCTIONSThe APEX (Advanced Pedometer and Event Detection – neXt gen) features of ICM-42670-P consist of:
•
•
•
•
•
•

Pedometer: Tracks step count and issues a step detect Interrupt.
Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmabletime.
Low-g Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a
programmable threshold and stays below the threshold for a programmable time.
Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration.
Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmablethreshold. This motion event can be used to enable device operation from sleep mode.
Significant Motion Detector (SMD): Detects significant motion based on accelerometer data.

Shared SRAM is used for FIFO and APEX features. Default configuration of the device provides 1Kbyte FIFO and restof the SRAM is used for APEX. User may disable APEX features to extend FIFO size to 2.25 Kbytes using register
field APEX_DISABLE in register SENSOR_CONFIG3.

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ICM-42670-P

DIGITAL INTERFACEI3CSM, I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-42670-P can be accessed using I3CSM at 12.5 MHz (data rates up to
12.5 Mbps in SDR mode, 25 Mbps in DDR mode), I2C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire
mode. Pin assignments for serial interfaces are described in Section 4.1.

I3CSM INTERFACEI3CSM is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3C SM isintended to improve upon the I2C interface, while preserving backward compatibility. The I3CSM capability of thisdevice is compliant with Version 1.0 of the MIPI Alliance Specification for I3CSM.
I3CSM carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point topoint), but provides the higher data rates, simpler pads, and lower power of SPI. I3C SM adds higher throughput fora given frequency, in-band interrupts (from slave to master), dynamic addressing.
ICM-42670-P supports the following features of I3CSM:
•
•
•
•
•
•
•

SDR data rate up to 12.5 Mbps
DDR data rate up to 25 Mbps
Dynamic address allocation
In-band Interrupt (IBI) support
Support for asynchronous timing control mode 0
Error detection (CRC and/or Parity)
Common Command Code (CCC)

The ICM-42670-P always operates as an I3CSM slave device when communicating to the system processor, which
thus acts as the I3CSM master. I3CSM master controls an active pullup resistance on SDA, which it can enable anddisable. The pullup resistance may be a board level resistor controlled by a pin, or it may be internal to the I3C SM
master.
The following table shows I3CSM Common Command Code (CCC) commands supported by the device.
Required or
Optional per I3C
v1.0

CCC Description
1

ENEC, broadcast mode. (Enable Events)

2

Supported by
ICM-42670-P
Yes

DISEC, broadcast mode. (Disable Events)

Required
Required

3

ENTAS0, broadcast mode. (Enter Activity State 0)

Required

Yes

4

ENTAS1, broadcast mode. (Enter Activity State 1)

No

5

ENTAS2, broadcast mode. (Enter Activity State 0)

Optional
Optional

6

ENTAS3, broadcast mode. (Enter Activity State 0)

Optional

No

7

RSTDAA, broadcast mode. (Reset dynamic address assignment)

RequiredYes

8

ENTDAA, broadcast mode. (Enter dynamic address assignment)

RequiredYes

9

DEFSLVS, broadcast mode. (Define list of slaves)

No

10

SETMWL, broadcast mode. (Set Max Write Length)

Optional
Required

Yes

11

SETMRL, broadcast mode. (Set Max Read Length)

RequiredYes

12

ENTTM, broadcast mode. (Enter Test Mode)

Optional

No

13

ENTHDR0, broadcast mode. (Enter HDR DDR mode)

Optional

Yes

14

ENTHDR1, broadcast mode. (Enter HDR TSP mode)

Optional

No

15

ENTHDR2, broadcast mode. (Enter HDR TSL mode)

Optional

No

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Yes

No

ICM-42670-P
16

SETXTIME, broadcast mode. (Exchange Timing Information)
Defining byte = 0x7F (ST)

Optional

No

Defining byte = 0xBF (DT)

Optional

No

16.3

Defining byte = 0xDF (Enter Async Mode 0)

Optional

Yes

16.4

Defining byte = 0xEF (Enter Async Mode 1)

Optional

No

16.5

Defining byte = 0xF7 (Enter Async Mode 2)

OptionalNo

16.6

Optional

No

16.8

Defining byte = 0xFB (Enter Async Mode 3)
Defining byte = 0xFD (Async Trigger for Async Mode
3)
Defining byte = 0x3F (TPH)

Optional

No

16.9

Defining byte = 0x9f (TU)

Optional

No

Optional

No

16.1
16.2

16.7

16.10

Optional

No

17

Defining byte = 0x8F (ODR)
Defining byte = 0xff (disable all timing control
16.11
function)
ENEC, direct mode. (Enable Events)

Required

Yes

18

DISEC, direct mode. (Disable Events)

Required

Yes

19

ENTAS0, direct mode. (Enter Activity State 0)

Required

Yes

ENTAS1, direct mode. (Enter Activity State 1)

Optional

No

21

ENTAS2, direct mode. (Enter Activity State 2)

Optional

No

22

ENTAS3, direct mode. (Enter Activity State 3)

Optional

No

23

RequiredYes

Optional

Yes

25

RSTDAA, direct mode. (Reset dynamic address assignment)
SETDASA, direct mode. (Set Dynamic address from static
address)
SETNEWDA, direct mode. (Set new dynamic address)

Required

Yes

26

SETMWL, direct mode. (Set Max Write Length)

Required

Yes

27

SETMRL, direct mode. (Set Max Read length)

Required

Yes

28

GETMWL, direct mode. (Get Max write length)

RequiredYes

29

GETMRL, direct mode. (Get Max Read length)

RequiredYes

GETPID, direct mode. (Get provisional ID)

RequiredYes

31

GETBCR, direct mode. (Get Bus Characteristics Register)

Required

Yes

32

GETDCR, direct mode. (Get Device Characteristics Register)

RequiredYes

33

GETSTATUS, direct mode. (Get Device Status)

Required

Yes

34

GETACCMST, direct mode. (Get Accept Mastership)

Optional

No

35

SETBRGTGT, direct mode. (Set Bridge Targets)

Optional

No

36

GETMXDS, direct mod. (Get Max Data Speed)

Optional

Yes

37

GETHDRCAP, direct mode. (Get HDR capability)

Optional

Yes

38

SETXTIME, direct mode. (Set Exchange Timing information)

20

24

30

Optional

Yes

38.1

Defining byte = 0x7F (ST)

Optional

No

38.2

Defining byte = 0xBF (DT)

Optional

No

38.3

Defining byte = 0xDF (Enter Async Mode 0)

Optional

Yes

38.4

Defining byte = 0xEF (Enter Async Mode 1)

OptionalNo

38.5

Defining byte = 0xF7 (Enter Async Mode 2)

Optional

No

Defining byte = 0xFB (Enter Async Mode 3)
Defining byte = 0xFD (Async Trigger for Async Mode
3)

Optional

No

38.6
38.7

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Optional

NoICM-42670-P
38.8

Defining byte = 0x3F (TPH)

Optional

No

38.9

Defining byte = 0x9f (TU)

Optional

No

Optional

No

Optional

Yes

Optional

Yes

38.10

39

Defining byte = 0x8F (ODR)
Defining byte = 0xff (disable all timing control
38.11
function)
GETXTIME, direct mode. (Get Exchange Timing Information)
Table 12. I3CSM CCC Commands

I2C INTERFACEI2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or aslave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ICM-42670-P always operates as a slave device when communicating to the system processor, which thus acts
as the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the ICM-42670-P is b110100X, which is 7 bits long. The LSB bit of the 7-bit address isdetermined by the logic level on pin AP_AD0. This allows two ICM-42670-Ps to be connected to the same I2C bus.
When used in this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low)
and the address of the other should be b1101001 (pin AP_AD0 is logic high).

I2C COMMUNICATIONS PROTOCOLSTART (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined asa HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to bebusy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the
SDA line while SCL is HIGH (see Figure 11).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.

SDA

SCL
S

P

START condition

STOP condition

Figure 11. START and STOP Conditions

Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per datatransfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA
and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it
can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is readyand releases the clock line (refer to Figure 12).
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ICM-42670-P

DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BYRECEIVER (SDA)
acknowledge
SCL FROM
MASTER

1

2

8

9

clock pulse for
acknowledgement

START
condition

Figure 12. Acknowledge on the I2C Bus

Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by
an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to
the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave
device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the
SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by themaster with a STOP condition (P), thus freeing the communications line. However, the master can generate a
repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to
HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take placewhen SCL is low, with the exception of start and stop conditions.

SDA

SCL

1–7

8

9

1–7

8

9

1–7

8

9

S
START ADDRESS
condition

P
R/W

ACK

DATA

ACK

DATA

ACK

STOP
condition

Figure 13. Complete I2C Data Transfer

To write the internal ICM-42670-P registers, the master transmits the start condition (S), followed by the I 2C
address and the write bit (0). At the 9th clock cycle (when the clock is high), the ICM-42670-P acknowledges thetransfer. Then the master puts the register address (RA) on the bus. After the ICM-42670-P acknowledges thereception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal,and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, themaster can continue outputting data rather than transmitting a stop signal. In this case, the ICM-42670-P
automatically increments the register address and loads the data to the appropriate register. The following figures
show single and two-byte write sequences.

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ICM-42670-P
Single-Byte Write Sequence
Master
Slave

S

AD+W

RA
ACK

DATA

P

ACK

ACK

Burst Write Sequence
Master
Slave

S

AD+W

RA
ACK

DATA

DATA

ACK

ACK

P
ACK

To read the internal ICM-42670-P registers, the master sends a start condition, followed by the I 2C address and awrite bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM42670-P, the master transmits a start signal followed by the slave address and read bit. As a result, the ICM-42670P sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bitfrom master. The NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The
following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave

S

AD+W

RA
ACK

S

AD+R

NACK

ACK

ACK

P

DATA

Burst Read Sequence
Master
Slave

S

AD+W

RA
ACK

S
ACK

AD+R

ACK
ACK

DATA

NACK
DATA

I2C TERMS
SIGNALDESCRIPTIONS
ADStart Condition: SDA goes from high to low while SCL is highSlave I2C address

W
R
ACK

Write bit (0)Read bit (1)Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle

NACK
RA
DATA

Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-42670-P internal register address
Transmit or received dataP

Stop condition: SDA going from low to high while SCL is highTable 13. I2C Terms

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PICM-42670-P
SPI INTERFACEThe ICM-42670-P supports 3-wire or 4-wire SPI for the host interface. The ICM-42670-P always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input(SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip
Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is activeat a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices
are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interferewith any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first
byte contains the Register Address, and the following byte(s) contain(s) the SPI data. The first bit of thefirst byte contains the Read/Write bit and indicates the Read (1) operation. The following 7 bits containthe Register Address. In cases of multiple-byte Reads, data is two or more bytes:
Register Address format
MSB
R/W

A6

A5

A4

A3

A2

A1

LSB
A0

D1

LSB
D0

SPI Data format
MSB
D7
6.

D6

D5

D4

D3

D2

Supports Single or Burst Read/Writes.
SCLK
SDIO

SPI Master

CS1

nCS

SPI Slave 1

CS2

SCLK
SDIO

SPI Slave 2

nCS

Figure 14. Typical SPI Master/Slave Configuration

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ICM-42670-P

ASSEMBLY
This section provides general guidelines for assembling Micro Electro-Mechanical Systems (MEMS) devices
packaged in LGA package.

ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figure.
+Z

+Y

+Z
+Y

+X

+X

Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation

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ICM-42670-P
PACKAGE DIMENSIONS
14 Lead LGA (2.5x3x0.76) mm NiAu pad finish

DIMENSIONS IN MILLIMETERS
Total Thickness
Substrate Thickness
Mold Thickness
Body Size

SYMBOLS
A
c
A3

MIN
0.71

NOM
0.76
0.1
0.65

MAX
0.81
REF
REF

E

2.45

2.50

2.55

D

2.95

3.00

3.05

Lead Width

b

0.20

0.25

0.30

Lead Length

L3
e

0.425

0.475
0.5

0.525

Lead Pitch
Lead Count
Edge Pin Center to Center
Body Center to Contact Pin
Package Edge Tolerance

14
e*3

1.5

e*2

1

e/2

0.25
0.05

Pad-End to Package Tolerance

0.05

0.1

0.15

Mold Flatness

0.1

Coplanarity

0.08

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ICM-42670-P

DEVICE PACKAGE IN TAPE AND REEL
ICM-42670-P devices are packaged in the tape and reel as shown in the figures below.

Figure 16. ICM-42670-P Device Package in Tape and Reel

Figure 17. Tape Dimensions with ICM-42670-P Device Package

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ICM-42670-P

PART NUMBER PACKAGE MARKINGThe part number package marking for ICM-42670-P devices is summarized below:
PART NUMBER
ICM-42670-P

PART NUMBER PACKAGE MARKINGI460P

TOP VIEWPart Number
Lot Traceability CodeI460P
XXXXXX
YYWW

Y Y = Year CodeW W = Work Week

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ICM-42670-P

USE NOTESGYROSCOPE POWER ON TO POWER OFF TRANSITION
After powering the gyroscope off, a period of > 20ms should be allowed to elapse before it is powered back on.

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ICM-42670-P

ACCESSING MREG1, MREG2 AND MREG3 REGISTERS
The following procedure must be used to access registers in user banks MREG1, MREG2, and MREG3.
MREG1, MREG2, and MREG3 registers are accessed indirectly, using the following registers in Bank 0 (_W registers
for Write, _R registers for Read)
•
•
•
•
•
•

BLK_SEL_W
MADDR_W
M_W
BLK_SEL_R
MADDR_R
M_R

For MREG1 write access, BLK_SEL_W must be set to 0x00. For MREG2 write access, BLK_SEL_W must be set to0x28. For MREG3 write access, BLK_SEL_W must be set to 0x50.
For MREG1 read access, BLK_SEL_R must be set to 0x00. For MREG2 read access, BLK_SEL_R must be set to 0x28.
For MREG3 read access, BLK_SEL_R must be set to 0x50.
User must ensure BLK_SEL_W and BLK_SEL_R are set to 0x00 after completing MREG1, MREG2, or MREG3 access.
Example: To write a value to an MREG1 register at address 0x14 use the following steps:••••

BLK_SEL_W must be set to 0
MADDR_W must be set to 0x14 (address of the MREG1 register being accessed)
M_W must be set to the desired value
Wait for 10 µs

Example: To read the value of an MREG1 register at address 0x14 use the following steps:
•
•
•
•
•

BLK_SEL_R must be set to 0
MADDR_R must be set to 0x14 (address of the MREG1 register being accessed)
Wait for 10µs
Read register M_R to access the value in MREG1 register 0x14
Wait for 10 µs

Host must not access any other register for 10 µs once MREG1, MREG2 or MREG3 access is kicked off.
Additionally, please note the following for MREG1, MREG2 or MREG3 register accesses:
•
•

•
•
•

User must check that register field MCLK_RDY is at value 1, to confirm that internal clock is running before
initiating MREG register access.
MREG1, MREG2, or MREG3 read and write operations cannot happen in all power modes. Sleep mode, and
Accelerometer low power mode with WUOSC do not support MREG1, MREG2 or MREG3 access. When insleep mode or accelerometer LP mode with WUOSC, MREG1, MREG2 or MREG3 read/write operations
require the user to power on the RC oscillator using register field IDLE from register PWR_MGMT0.
It can take up to 10 µs for MREG1, MREG2 or MREG3 read/write operations to be effective. No register
access must be performed during this period
Multiple serial protocol transactions are needed for a single data byte transfer, please refer to the examples
provided.
Data transfers through indirect access are only supported for single byte transfers and burst data transfer
is not supported for read or write operations.

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ICM-42670-P

REGISTER MAP
This section lists the register map for the ICM-42670-P, for user banks 0, MREG1, MREG2 and MREG3.

USER BANK 0 REGISTER MAP
ADDR
(HEX)

ADDR
(DEC)

REGISTER NAMESERIALI/F

0000

MCLK_RDY

R

BIT7

BIT6

BIT5

BIT4

BIT3

-

BIT2

BIT1

MCLK_RDYSPI_AP_4WIR
E

01

01

DEVICE_CONFIG

R/W

02

02

SIGNAL_PATH_RESET

R/W

03

03

DRIVE_CONFIG1

R/W-

I3C_DDR_SLEW_RATE

I3C_SDR_SLEW_RATE

0404

DRIVE_CONFIG2R/W-

I2C_SLEW_RATE

ALL_SLEW_RATE

05

05

DRIVE_CONFIG3

R/W

06

06

INT_CONFIG

R/W

-

BIT0

SOFT_RESET_
DEVICE_CON
FIG

-

-

-

SPI_MODEFIFO_FLUSH--SPI_SLEW_RATE
INT2_DRIVE_CIRCUIT

INT2_MODE

INT2_POLARI
TY

09

09

TEMP_DATA1

R

0A

10

TEMP_DATA0RTEMP_DATA[7:0]0B

11ACCEL_DATA_X1

R

ACCEL_DATA_X[15:8]

INT1_DRIVE_CIRCUIT

INT1_MODE

INT1_POLARITY

TEMP_DATA[15:8]

0C

12

ACCEL_DATA_X0

R

ACCEL_DATA_X[7:0]0D

13ACCEL_DATA_Y1

R

ACCEL_DATA_Y[15:8]

0E

14

ACCEL_DATA_Y0

R

ACCEL_DATA_Y[7:0]0F

15ACCEL_DATA_Z1

R

ACCEL _DATA_Z[15:8]

10

16

ACCEL _DATA_Z0

R

ACCEL _DATA_Z[7:0]1117GYRO _DATA_X1

R

GYRO _DATA_X[15:8]

12

18

GYRO _DATA_X0

R

GYRO _DATA_X[7:0]1319GYRO _DATA_Y1

R

GYRO_DATA_Y[15:8]

14

20

GYRO _DATA_Y0

R

GYRO_DATA_Y[7:0]1521

GYRO_DATA_Z1

R

GYRO_DATA_Z[15:8]

16

22

GYRO_DATA_Z0

R

GYRO_DATA_Z[7:0]1723

TMST_FSYNCH

R

TMST_FSYNC_DATA[15:8]
TMST_FSYNC_DATA[7:0]1824

TMST_FSYNCL

R

1D

29

APEX_DATA4R

FF_DUR[7:0]1E

30

APEX_DATA5R

FF_DUR[15:8]

1F

31

PWR_MGMT0

R/W

ACCEL_LP_CL
K_SEL

20

32

GYRO_CONFIG0

R/W

21

33

ACCEL_CONFIG0

R/W

22

34

TEMP_CONFIG0

R/W

-

23

35

GYRO_CONFIG1

R/W

24

36

ACCEL_CONFIG1

R/W

25

37

APEX_CONFIG0

R/W

26

38

APEX_CONFIG1

R/W

27

39

WOM_CONFIG

R/W

28

40

FIFO_CONFIG1

R/W

29

41

FIFO_CONFIG2

R/W

2A

42

FIFO_CONFIG3

R/W

-

IDLE

-

GYRO_UI_FS_SEL-

GYRO_ODR-ACCEL_UI_FS_SEL-

ACCEL_ODR

GYRO_MODE

ACCEL_MODE

TEMP_FILT_BW--

GYRO_UI_FILT_BW

ACCEL_UI_AVG--

SMD_ENABL
E

FF_ENABLE

TILT_ENABLE-

ACCEL_UI_FILT_BW

DMP_POWE
R_SAVE_EN

DMP_INIT_E
N

PED_ENABLE-

WOM_INT_DUR

DMP_MEM_RESET_EN-DMP_ODR

WOM_INT_MODE-

WOM_MODEWOM_ENFIFO_MODEFIFO_BYPASSFIFO_WM[7:0]
-

2B

43

INT_SOURCE0

R/W

ST_INT1_EN

FSYNC_INT1_
EN

2C

44

INT_SOURCE1

R/W-

I3C_PROTOC
OL_ERROR_I
NT1_EN2D

45

INT_SOURCE3

R/W

ST_INT2_EN

FSYNC_INT2_
EN

2E

46

INT_SOURCE4R/W-

I3C_PROTOC
OL_ERROR_I
NT2_ENFIFO_WM[11:8]
PLL_RDY_INT
1_EN

RESET_DONE_INT1_EN-

PLL_RDY_INT
2_EN

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RESET_DONE_INT2_EN-

DRDY_INT1_
EN

FIFO_THS_IN
T1_EN

FIFO_FULL_I
NT1_EN

AGC_RDY_IN
T1_EN

SMD_INT1_E
N

WOM_Z_INT
1_EN

WOM_Y_INT
1_EN

WOM_X_INT
1_EN

DRDY_INT2_
EN

FIFO_THS_IN
T2_EN

FIFO_FULL_I
NT2_EN

AGC_RDY_IN
T2_EN

SMD_INT2_E
N

WOM_Z_INT
2_EN

WOM_Y_INT
2_EN

WOM_X_INT
2_EN

ICM-42670-P
ADDR
(HEX)

ADDR
(DEC)

REGISTER NAMESERIAL
I/F

BIT7

BIT6

BIT5

BIT4

BIT3

2F

47

FIFO_LOST_PKT0

R

FIFO_LOST_PKT_CNT[7:0]30

48

FIFO_LOST_PKT1

R

FIFO_LOST_PKT_CNT[15:8]

3149

APEX_DATA0R

STEP_CNT[7:0]3250

APEX_DATA1R

STEP_CNT[15:8]

33

51

APEX_DATA2

R

34

52

APEX_DATA3

R

35

53

INTF_CONFIG0

R/W

36

54

INTF_CONFIG1

R/W

39

57

INT_STATUS_DRDY

R/C

3A

58

INT_STATUS

R/C

3B

59

INT_STATUS2

R/C

BIT2

BIT1

BIT0

STEP_CADENCE
FIFO_COUNT_FORMAT-FIFO_COUNT_ENDIANDMP_IDLESENSOR_DAT
A_ENDIAN

ACTIVITY_CLASS--

I3C_SDR_EN

I3C_DDR_EN

CLKSELDATA_RDY_I
NT

ST_INTFSYNC_INT

PLL_RDY_INTRESET_DONE_INT-

FIFO_THS_IN
T

SMD_INTSTEP_DET_IN
T

STEP_CNT_O
VF_INT

TILT_DET_IN
T

-

3C

60

INT_STATUS3

R/C

-

3D

61

FIFO_COUNTHR

FIFO_COUNT[15:8]

3E

62

FIFO_COUNTLR

FIFO_COUNT[7:0]

3F

63

FIFO_DATAR

FIFO_DATA

75

117

WHO_AM_I

R

WHOAMI

79

121

BLK_SEL_W

R/W

BLK_SEL_W

7A

122

MADDR_W

R/W

MADDR_W

7B

123

M_W

R/W

M_W

7C

124

BLK_SEL_R

R/W

BLK_SEL_R

7D

125

MADDR_R

R/W

MADDR_R

7E

126

M_R

R/W

M_R

FIFO_FULL_I
NT

AGC_RDY_IN
T

WOM_X_INT

WOM_Y_INT

WOM_Z_INT

FF_DET_INT

LOWG_DET_I
NT-

USER BANK MREG1 REGISTER MAP
ADDR
(HEX)

ADDR
(DEC)

REGISTER NAMESERIAL
I/F

00

00

TMST_CONFIG1

R/W

01

01

FIFO_CONFIG5

R/W

02

02

FIFO_CONFIG6

R/W

03

03

FSYNC_CONFIG

R/W

04

04

INT_CONFIG0

R/W

BIT7

BIT6

BIT5

FIFO_WM_G
T_TH

-

BIT3

BIT2

BIT1

BIT0

TMST_ON_S
REG_EN

TMST_RESTMST_DELTA_EN

TMST_FSYNC_EN

TMST_ENFIFO_RESUM
E_PARTIAL_R
D

FIFO_HIRES_EN

FIFO_TMST_F
SYNC_ENFIFO_GYRO_EN

FIFO_ACCEL_EN

FIFO_EMPTY_INDICATOR_
DIS

-

-

05

INT_CONFIG1

R/W

-

06

06

SENSOR_CONFIG3

R/W-

APEX_DISABL
E

13

19

ST_CONFIG

R/W-

ST_NUMBER_SAMPLE

14

20

SELFTESTR/W

GYRO_ST_EN

ACCEL_ST_E
N

23

35

INTF_CONFIG6

R/W

25

37

INTF_CONFIG10

R/W

28

40

INTF_CONFIG7

R/W

2B

43

OTP_CONFIG

R/W-

FSYNC_UI_FL
AG_CLEAR_S
EL-

UI_DRDY_INT_CLEAR05

RCOSC_REQ_
ON_FIFO_TH
S_DIS

-

FSYNC_UI_SEL

INT_TPULSE_DURATIONFIFO_THS_INT_CLEAR

INT_ASYNC_
RESET

FSYNC_POLARITY

FIFO_FULL_INT_CLEAR-

ACCEL_ST_LIM

GYRO_ST_LIM-

I3C_TIMEOU
T_EN

ASYNCTIME0_DIS

I3C_IBI_BYTE_EN

I3C_IBI_EN-

I3C_DDR_WR
_MODE

-

2F

47

INT_SOURCE6

R/W

FF_INT1_EN

LOWG_INT1_
EN

30

48

INT_SOURCE7

R/W

FF_INT2_EN

LOWG_INT2_EN-

OTP_COPY_MODE-

STEP_DET_IN
T1_EN

STEP_CNT_O
FL_INT1_EN

TILT_DET_IN
T1_EN

-

STEP_DET_IN
T2_EN

STEP_CNT_O
FL_INT2_EN

TILT_DET_IN
T2_EN

-

Page 43 of 103
Document Number: DS-000451
Revision: 1.1

BIT4

ICM-42670-P
ADDR
(HEX)

ADDR
(DEC)

REGISTER NAMESERIAL
I/F

31

49

INT_SOURCE8

R/W

32

50

INT_SOURCE9

R/W

33

51

INT_SOURCE10

R/W

44

68

APEX_CONFIG2

R/W

LOW_ENERGY_AMP_TH_SEL

45

69

APEX_CONFIG3

R/W

PED_AMP_TH_SEL

46

70

APEX_CONFIG4

R/W

47

71

APEX_CONFIG5

R/W

48

72

APEX_CONFIG9

R/W

BIT7

BIT6
-

I3C_PROTOC
OL_ERROR_I
BI_EN

FF_IBI_EN

-

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

FSYNC_IBI_E
N

PLL_RDY_IBI_ENUI_DRDY_IBI_ENFIFO_THS_IBI_ENFIFO_FULL_IB
I_EN

AGC_RDY_IBI_EN

LOWG_IBI_E
N

SMD_IBI_EN

WOM_Z_IBI_EN

WOM_Y_IBI_EN

WOM_X_IBI_EN

ST_DONE_IBI_EN

STEP_DET_IB
I_EN

STEP_CNT_O
FL_IBI_EN

TILT_DET_IBI_EN

DMP_POWER_SAVE_TIME_SEL
PED_STEP_CNT_TH_SEL

PED_STEP_DET_TH_SEL

PED_SB_TIMER_TH_SEL

TILT_WAIT_TIME_SEL

PED_HI_EN_TH_SEL

LOWG_PEAK_TH_HYST_SEL

HIGHG_PEAK_TH_HYST_SEL

FF_DEBOUNCE_DURATION_SELSENSITIVITY_
MODE

SMD_SENSITIVITY_SEL

49

73

APEX_CONFIG10

R/W

LOWG_PEAK_TH_SEL

LOWG_TIME_TH_SEL

4A

74

APEX_CONFIG11R/W

HIGHG_PEAK_TH_SEL

HIGHG_TIME_TH_SEL

4B

75

ACCEL_WOM_X_THR

R/W

WOM_X_TH

4C

76

ACCEL_WOM_Y_THR

R/W

WOM_Y_TH

4D

77

ACCEL_WOM_Z_THR

R/W

WOM_Z_TH

4E

78

OFFSET_USER0R/W

GYRO_X_OFFUSER[7:0]4F

79

OFFSET_USER1

R/W

50

80

OFFSET_USER2R/W

GYRO_Y_OFFUSER[11:8]

GYRO_X_OFFUSER[11:8]

51

81

OFFSET_USER3

R/W

52

82

OFFSET_USER4

R/W

53

83

OFFSET_USER5

R/W

54

84

OFFSET_USER6

R/W

55

85

OFFSET_USER7

R/W

56

86

OFFSET_USER8

R/W

63

99

ST_STATUS1

R

64

100

ST_STATUS2

R

66

102

FDR_CONFIG

R/W-

FDR_SEL67

103

APEX_CONFIG12

R/W

FF_MAX_DURATION_SEL

FF_MIN_DURATION_SEL

GYRO_Y_OFFUSER[7:0]
GYRO_Z_OFFUSER[7:0]
ACCEL_X_OFFUSER[11:8]

GYRO_Z_OFFUSER[11:8]
ACCEL_X_OFFUSER[7:0]
ACCEL_Y_OFFUSER[7:0]

ACCEL_Z_OFFUSER[11:8]

ACCEL_Y_OFFUSER[11:8]
ACCEL_Z_OFFUSER[7:0]-

ST_INCOMPLETEACCEL_ST_P
ASS

ACCEL_ST_D
ONE

AZ_ST_PASS

AY_ST_PASS

AX_ST_PASS-

GYRO_ST_PA
SS

GYRO_ST_DO
NE

GZ_ST_PASS

GY_ST_PASS

GX_ST_PASS-

USER BANK MREG2 REGISTER MAP
ADDR
(HEX)

ADDR
(DEC)

REGISTER NAMESERIAL
I/F

06

06

OTP_CTRL7

R/W

BIT7

BIT6

BIT5

BIT4

-

BIT3

BIT2

BIT1

BIT0

OTP_RELOAD-

OTP_PWR_D
OWN

-

BIT3

BIT2

BIT1

BIT0

USER BANK MREG3 REGISTER MAP
ADDR
(HEX)

ADDR
(DEC)

REGISTER NAMESERIAL
I/F

00

00

XA_ST_DATAR

XA_ST_DATA

01

01

YA_ST_DATAR

YA_ST_DATA

02

02

ZA_ST_DATAR

ZA_ST_DATA

03

03

XG_ST_DATAR

XG_ST_DATA

04

04

YG_ST_DATAR

YG_ST_DATA

05

05

ZG_ST_DATAR

ZG_ST_DATA

BIT7

BIT6

Page 44 of 103
Document Number: DS-000451
Revision: 1.1

BIT5

BIT4

ICM-42670-P
Detailed register descriptions are provided in the sections that follow.
Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used
to determine the default value of reserved register fields, and unless otherwise noted this default value must be
maintained even if the values of other register fields are modified by the user.
In the sections that follow, some register fields are described as can be changed on-the-fly even if sensor is on.
These are the only register fields that can be changed on-the-fly even if sensor is on. Register fields not describedas such must not be changed on-the-fly if sensor is on.

Page 45 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P

USER BANK 0 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank 0.
Note: The device powers up in sleep mode.

MCLK_RDY
Name: MCLK_RDY
Address: 00 (00h)Serial IF: R
Reset value: 0x00 at power-up, changes to 0x01 after OTP load is completed
BIT
NAME
FUNCTION
7:4 Reserved
0: Indicates internal clock is currently not running
3
MCLK_RDY
1: Indicates internal clock is currently running
2:0 Reserved

DEVICE_CONFIG
Name: DEVICE_CONFIG
Address: 01 (01h)Serial IF: R/W
Reset value: 0x04
BIT
NAME
7:3 2

SPI_AP_4WIRE

1

-

0

SPI_MODEFUNCTION
Reserved
0: AP interface uses 3-wire SPI mode
1: AP interface uses 4-wire SPI mode
Reserved
SPI mode selection
0: Mode 0 and Mode 3
1: Mode 1 and Mode 2
If device is operating in non-SPI mode, user is not allowed to change thepower-on default setting of this register. Change of this register setting will
not take effect till AP_CS = 1.

Page 46 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
SIGNAL_PATH_RESET
Name: SIGNAL_PATH_RESET
Address: 02 (02h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:5 4

SOFT_RESET_DEVICE_CON
FIG

3

-

2

FIFO_FLUSH

1:0-

FUNCTION
Reserved
Software Reset (auto clear bit)
0: Software reset not enabled
1: Software reset enabled
Reserved
When set to 1, FIFO will get flushed.
FIFO flush requires the following programming sequence:• Write FIFO_FLUSH =1• Wait for 1.5 µs• Read FIFO_FLUSH, it should now be 0
Host can only program this register bit to 1.
Reserved

Page 47 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
DRIVE_CONFIG1
Name: DRIVE_CONFIG1
Address: 03 (03h)Serial IF: R/W
Reset value: 0x2B
BIT
NAME
7:6 -

5:3

I3C_DDR_SLEW_RATE

FUNCTION
Reserved
Controls slew rate for output pin 14 when device is in I3CSM DDR protocol.
While in I3CSM operation, the device automatically switches to use
I3C_DDR_SLEW_RATE after receiving ENTHDR0 ccc command from the host.
The device automatically switches back to I3C_SDR_SLEW_RATE after thehost issues HDR_EXIT pattern.
000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns
001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns
010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns
011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns
100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns
101: MAX: 2 ns
110: Reserved
111: Reserved
This register field should not be programmed in I3C/DDR mode.
Controls slew rate for output pin 14 in I3CSM SDR protocol.
After device reset, I2C_SLEW_RATE is used by default. If I3CSM feature isenabled, the device automatically switches to use I3C_SDR_SLEW_RATE
after receiving 0x7E+W message (an I3CSM broadcast message).

2:0

I3C_SDR_SLEW_RATE

000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns
001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns
010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns
011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns
100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns
101: MAX: 2 ns
110: Reserved
111: Reserved
This register field should not be programmed in I3C/DDR mode

Page 48 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
DRIVE_CONFIG2
Name: DRIVE_CONFIG2
Address: 04 (04h)Serial IF: R/W
Reset value: 0x0D
BIT
NAME
7:6 -

5:3

I2C_SLEW_RATE

FUNCTION
Reserved
Controls slew rate for output pin 14 in I2C mode.
After device reset, the I2C_SLEW_RATE is used by default. If the 1st write
operation from host is an SPI transaction, the device automatically switches
to SPI_SLEW_RATE. If I3CSM feature is enabled, the device automaticallyswitches to I3C_SDR_SLEW_RATE after receiving 0x7E+W message (an I3C
broadcast message).
000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns
001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns
010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns
011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns
100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns
101: MAX: 2 ns
110: Reserved
111: Reserved
This register field should not be programmed in I3C/DDR mode
Configure drive strength for all output pins in all modes (SPI3, SPI4, I 2C,
I3CSM) excluding pin 14.

2:0

ALL_SLEW_RATE

000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns
001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns
010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns
011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns
100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns
101: MAX: 2 ns
110: Reserved
111: Reserved
This register field should not be programmed in I3C/DDR mode

Page 49 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
DRIVE_CONFIG3
Name: DRIVE_CONFIG3
Address: 05 (05h)Serial IF: R/W
Reset value: 0x05
BIT
NAME
7:3 -

2:0

SPI_SLEW_RATE

FUNCTION
Reserved
Controls slew rate for output pin 14 in SPI 3-wire mode. In SPI 4-wire mode
this register controls the slew rate of pin 1 as it is used as an output in SPI 4wire mode only. After chip reset, the I2C_SLEW_RATE is used by default forpin 14 pin. If the 1st write operation from the host is an SPI3/4 transaction,
the device automatically switches to SPI_SLEW_RATE.
000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns
001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns
010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns
011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns
100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns
101: MAX: 2 ns
110: Reserved
111: Reserved
This register field should not be programmed in I3C/DDR mode

Page 50 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
INT_CONFIG
Name: INT_CONFIG
Address: 06 (06h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:6 5

INT2_MODE

4

INT2_DRIVE_CIRCUIT

3

INT2_POLARITY2

INT1_MODE

1

INT1_DRIVE_CIRCUIT0

INT1_POLARITY

FUNCTION
Reserved
INT2 interrupt mode
0: Pulsed mode
1: Latched mode
INT2 drive circuit
0: Open drain
1: Push pull
INT2 interrupt polarity
0: Active low
1: Active highINT1 interrupt mode
0: Pulsed mode
1: Latched mode
INT1 drive circuit
0: Open drain
1: Push pull
INT1 interrupt polarity
0: Active low
1: Active high

TEMP_DATA1
Name: TEMP_DATA1
Address: 09 (09h)Serial IF: R
Reset value: 0x80
BIT
NAME
7:0 TEMP_DATA[15:8]

FUNCTION
Upper byte of temperature data

Page 51 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
TEMP_DATA0
Name: TEMP_DATA0
Address: 10 (0Ah)
Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 TEMP_DATA[7:0]

FUNCTION
Lower byte of temperature data

Temperature data value from the sensor data registers can be converted to degrees centigrade by using thefollowing formula:•

Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25

Temperature data stored in FIFO can be an 8-bit or 16-bit quantity, depending on packet format. It can beconverted to degrees centigrade by using the following formulas:••

8-bit quantity: Temperature in Degrees Centigrade = (TEMP_DATA / 2) + 25; where TEMP_DATA refers to
the 8 MSBs of the 16-bit word coming from the temperature sensor. In this mode the 8 LSBs are set to ‘0’.
16-bit quantity: Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25

ACCEL_DATA_X1
Name: ACCEL_DATA_X1
Address: 11 (0Bh)
Serial IF: R
Reset value: 0x80
BIT
NAME
7:0 ACCEL_DATA_X[15:8]

FUNCTION
Upper byte of Accel X-axis data

ACCEL_DATA_X0
Name: ACCEL_DATA_X0
Address: 12 (0Ch)
Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 ACCEL_DATA_X[7:0]

FUNCTION
Lower byte of Accel X-axis data

ACCEL_DATA_Y1
Name: ACCEL_DATA_Y1
Address: 13 (0Dh)
Serial IF: R
Reset value: 0x80
BIT
NAME
7:0 ACCEL_DATA_Y[15:8]

FUNCTION
Upper byte of Accel Y-axis data

Page 52 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
ACCEL_DATA_Y0
Name: ACCEL_DATA_Y0
Address: 14 (0Eh)
Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 ACCEL_DATA_Y[7:0]

FUNCTION
Lower byte of Accel Y-axis data

ACCEL_DATA_Z1
Name: ACCEL_DATA_Z1
Address: 15 (0Fh)
Serial IF: R
Reset value: 0x80
BIT
NAME
7:0 ACCEL_DATA_Z[15:8]

FUNCTION
Upper byte of Accel Z-axis data

ACCEL_DATA_Z0
Name: ACCEL_DATA_Z0
Address: 16 (10h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 ACCEL_DATA_Z[7:0]

FUNCTION
Lower byte of Accel Z-axis data

GYRO_DATA_X1
Name: GYRO_DATA_X1
Address: 17 (11h)Serial IF: R
Reset value: 0x80
BIT
NAME
7:0 GYRO_DATA_X[15:8]

FUNCTION
Upper byte of Gyro X-axis data

GYRO_DATA_X0
Name: GYRO_DATA_X0
Address: 18 (12h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 GYRO_DATA_X[7:0]

FUNCTION
Lower byte of Gyro X-axis data

Page 53 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
GYRO_DATA_Y1
Name: GYRO_DATA_Y1
Address: 19 (13h)Serial IF: R
Reset value: 0x80
BIT
NAME
7:0 GYRO_DATA_Y[15:8]

FUNCTION
Upper byte of Gyro Y-axis data

GYRO_DATA_Y0
Name: GYRO_DATA_Y0
Address: 20 (14h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 GYRO_DATA_Y[7:0]

FUNCTION
Lower byte of Gyro Y-axis data

GYRO_DATA_Z1
Name: GYRO_DATA_Z1
Address: 21 (15h)Serial IF: R
Reset value: 0x80
BIT
NAME
7:0 GYRO_DATA_Z[15:8]

FUNCTION
Upper byte of Gyro Z-axis data

GYRO_DATA_Z0
Name: GYRO_DATA_Z0
Address: 22 (16h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 GYRO_DATA_Z[7:0]

FUNCTION
Lower byte of Gyro Z-axis data

TMST_FSYNCH
Name: TMST_FSYNCH
Address: 23 (17h)Serial IF: SYNCRReset value: 0x00
BIT
NAME
7:0

TMST_FSYNC_DATA[15:8]

FUNCTIONStores the upper byte of the time delta from the rising edge of FSYNC tothe latest ODR until the UI Interface reads the FSYNC tag in the status
registerPage 54 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
TMST_FSYNCLName: TMST_FSYNCL
Address: 24 (18h)Serial IF: SYNCRReset value: 0x00
BIT
NAME
7:0

TMST_FSYNC_DATA[7:0]

FUNCTIONStores the lower byte of the time delta from the rising edge of FSYNC tothe latest ODR until the UI Interface reads the FSYNC tag in the status
register

APEX_DATA4
Name: APEX_DATA4
Address: 29 (1Dh)
Serial IF: R
Reset value: 0x00
BIT
NAME

FUNCTION
Lower byte of Freefall Duration

7:0

FF_DUR[7:0]

The duration is given in number of samples and it can be converted to
freefall distance in meters by applying the following formula:
FF_DISTANCE = 0.5*9.81*(FF_DUR*DMP_ODR_S)^2
Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds.

APEX_DATA5
Name: APEX_DATA5
Address: 30 (1Eh)
Serial IF: R
Reset value: 0x00
BIT
NAME

FUNCTION
Upper byte of Freefall Duration

7:0

FF_DUR[15:8]

The duration is given in number of samples and it can be converted to
freefall distance in meters by applying the following formula:
FF_DISTANCE = 0.5*9.81*(FF_DUR*DMP_ODR_S)^2
Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds.

Page 55 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
PWR_MGMT0
Name: PWR_MGMT0
Address: 31 (1Fh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME

7

ACCEL_LP_CLK_SEL

6:5

-

4

IDLE

FUNCTION
0: Accelerometer LP mode uses Wake Up oscillator clock. This is the lowest
power consumption mode and it is the recommended setting.
1: Accelerometer LP mode uses RC oscillator clock
This field can be changed on-the-fly even if accel sensor is on
Reserved
If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro
are powered off.
Nominally this bit is set to 0, so when Accel and Gyro are powered off,the chip will go to OFF state, since the RC oscillator will also be powered off
This field can be changed on-the-fly even if a sensor is on
00: Turns gyroscope off
01: Places gyroscope in Standby Mode
10: Reserved
11: Places gyroscope in Low Noise (LN) Mode

3:2

GYRO_MODE

Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning
from OFF to any of the other modes, do not issue any register writes for
200 µs.
This field can be changed on-the-fly even if gyro sensor is on
00: Turns accelerometer off
01: Turns accelerometer off
10: Places accelerometer in Low Power (LP) Mode
11: Places accelerometer in Low Noise (LN) Mode
When selecting LP Mode please refer to ACCEL_LP_CLK_SEL setting, bit[7] ofthis register.

1:0

ACCEL_MODE

Before entering LP mode and during LP Mode the following combinations of
ODR and averaging are not permitted:
1) ODR=1600 Hz or ODR=800 Hz: any averaging.
2) ODR=400 Hz: averaging=16x, 32x or 64x.
3) ODR=200 Hz: averaging=64x.
When transitioning from OFF to any of the other modes, do not issue any
register writes for 200 µs.
This field can be changed on-the-fly even if accel sensor is on

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ICM-42670-P
GYRO_CONFIG0
Name: GYRO_CONFIG0
Address: 32 (20h)Serial IF: R/W
Reset value: 0x06
BIT
NAME
7
-

6:5

4

3:0

FUNCTION
Reserved
Full scale select for gyroscope UI interface output

GYRO_UI_FS_SEL

00: ±2000 dps
01: ±1000 dps
10: ±500 dps
11: ±250 dps-

This field can be changed on-the-fly even if gyro sensor is on
Reserved
Gyroscope ODR selection for UI interface output

GYRO_ODR

0000: Reserved
0001: Reserved
0010: Reserved0011: Reserved
0100: Reserved
0101: 1.6k Hz
0110: 800 Hz
0111: 400 Hz
1000: 200 Hz
1001: 100 Hz
1010: 50 Hz
1011: 25 Hz
1100: 12.5 Hz
1101: Reserved
1110: Reserved
1111: Reserved
This field can be changed on-the-fly even if gyro sensor is on

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ICM-42670-P
ACCEL_CONFIG0
Name: ACCEL_CONFIG0
Address: 33 (21h)Serial IF: R/W
Reset value: 0x06
BIT
NAME
7
-

6:5

4

3:0

FUNCTION
Reserved
Full scale select for accelerometer UI interface output

ACCEL_UI_FS_SEL

00: ±16g
01: ±8g
10: ±4g
11: ±2g-This field can be changed on-the-fly even if accel sensor is on
Reserved
Accelerometer ODR selection for UI interface output

ACCEL_ODR

0000: Reserved
0001: Reserved
0010: Reserved0011: Reserved
0100: Reserved
0101: 1.6 kHz (LN mode)
0110: 800 Hz (LN mode)
0111: 400 Hz (LP or LN mode)
1000: 200 Hz (LP or LN mode)
1001: 100 Hz (LP or LN mode)
1010: 50 Hz (LP or LN mode)
1011: 25 Hz (LP or LN mode)
1100: 12.5 Hz (LP or LN mode)
1101: 6.25 Hz (LP mode)
1110: 3.125 Hz (LP mode)
1111: 1.5625 Hz (LP mode)This field can be changed on-the-fly when accel sensor is on

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ICM-42670-P
TEMP_CONFIG0
Name: TEMP_CONFIG0
Address: 34 (22h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7
-

6:4

3:0

TEMP_FILT_BW-

FUNCTION
Reserved
Sets the bandwidth of the temperature signal DLPF
000: DLPF bypassed
001: DLPF BW = 180 Hz
010: DLPF BW = 72 Hz
011: DLPF BW = 34 Hz
100: DLPF BW = 16 Hz
101: DLPF BW = 8 Hz
110: DLPF BW = 4 Hz
111: DLPF BW = 4 Hz
This field can be changed on-the-fly even if sensor is on
Reserved

GYRO_CONFIG1
Name: GYRO_CONFIG1
Address: 35 (23h)Serial IF: R/W
Reset value: 0x31
BIT
NAME
7:3 -

2:0

GYRO_UI_FILT_BW

FUNCTION
Reserved
Selects GYRO UI low pass filter bandwidth
000: Low pass filter bypassed
001: 180 Hz
010: 121 Hz
011: 73 Hz
100: 53 Hz
101: 34 Hz
110: 25 Hz
111: 16 Hz
This field can be changed on-the-fly even if gyro sensor is on

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ICM-42670-P
ACCEL_CONFIG1
Name: ACCEL_CONFIG1
Address: 36 (24h)Serial IF: R/W
Reset value: 0x41
BIT
NAME
7
-

FUNCTION
Reserved
Selects averaging filter setting to create accelerometer output inaccelerometer low power mode (LPM)
000: 2x average
001: 4x average
010: 8x average
011: 16x average
100: 32x average
101: 64x average
110: 64x average
111: 64x average

6:4

ACCEL_UI_AVG

3-This field cannot be changed when the accel sensor is in LPM
Reserved
Selects ACCEL UI low pass filter bandwidth

ACCEL_UI_FILT_BW

000: Low pass filter bypassed
001: 180 Hz
010: 121 Hz
011: 73 Hz
100: 53 Hz
101: 34 Hz
110: 25 Hz
111: 16 Hz

2:0

This field can be changed on-the-fly even if accel sensor is on

APEX_CONFIG0
Name: APEX_CONFIG0
Address: 37 (25h)Serial IF: R/W
Reset value: 0x08
BIT
NAME
7:4 3
DMP_POWER_SAVE_EN

2

DMP_INIT_EN

1

-

0

DMP_MEM_RESET_EN

FUNCTION
Reserved
When this bit is set to 1, power saving is enabled for DMP algorithms
When this bit is set to 1, DMP runs DMP SW initialization procedure. Bit isreset by hardware when the procedure is finished. All other APEX features
are ignored as long as DMP_INIT_EN is set.
This field can be changed on-the-fly even if accel sensor is on.
Reserved
When this bit is set to 1, it clears DMP SRAM for APEX operation or Self-test
operation.

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ICM-42670-P
APEX_CONFIG1
Name: APEX_CONFIG1
Address: 38 (26h)Serial IF: R/W
Reset value: 0x02
BIT
NAME
7
6

5

4

3

SMD_ENABLE

FF_ENABLE

TILT_ENABLE

PED_ENABLE

2

-

1:0

DMP_ODRFUNCTION
Reserved
0: Significant Motion Detection not enabled
1: Significant Motion Detection enabledThis field can be changed on-the-fly even if accel sensor is on
0: Freefall Detection not enabled
1: Freefall Detection enabledThis field can be changed on-the-fly even if accel sensor is on
0: Tilt Detection not enabled
1: Tilt Detection enabledThis field can be changed on-the-fly even if accel sensor is on
0: Pedometer not enabled
1: Pedometer enabledThis field can be changed on-the-fly even if accel sensor is on
Reserved
00: 25 Hz
01: 400 Hz
10: 50 Hz
11: 100 Hz
The ACCEL_ODR field must be configured to an ODR equal or greater to the
DMP_ODR field, for correct device operation.
This field can be changed on-the-fly even if accel sensor is on

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ICM-42670-P
WOM_CONFIG
Name: WOM_CONFIG
Address: 39 (27h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:5 -

4:3

WOM_INT_DUR

FUNCTION
Reserved
Selects Wake on Motion interrupt assertion from among the following
options
00: WoM interrupt asserted at first overthreshold event
01: WoM interrupt asserted at second overthreshold event
10: WoM interrupt asserted at third overthreshold event
11: WoM interrupt asserted at fourth overthreshold event
This field can be changed on-the-fly even if accel sensor is on, but it cannot
be changed if WOM_EN is already enabled
0: Set WoM interrupt on the OR of all enabled accelerometer thresholds
1: Set WoM interrupt on the AND of all enabled accelerometer thresholds

2

WOM_INT_MODE
This field can be changed on-the-fly even if accel sensor is on, but it cannot
be changed if WOM_EN is already enabled
0: Initial sample is stored. Future samples are compared to initial sample
1: Compare current sample to previous sample

10

WOM_MODEWOM_EN

This field can be changed on-the-fly even if accel sensor is on, but it cannot
be changed if WOM_EN is already enabled
0: WOM disabled
1: WOM enabledThis field can be changed on-the-fly even if accel sensor is on

FIFO_CONFIG1
Name: FIFO_CONFIG1
Address: 40 (28h)Serial IF: R/W
Reset value: 0x01
BIT
NAME
7:2 1

FIFO_MODE

0

FIFO_BYPASSFUNCTION
Reserved
FIFO mode control
0: Stream-to-FIFO Mode
1: STOP-on-FULL Mode
FIFO bypass control
0: FIFO is not bypassed
1: FIFO is bypassed

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ICM-42670-P
FIFO_CONFIG2
Name: FIFO_CONFIG2
Address: 41 (29h)Serial IF: R/W
Reset value: 0x00
BIT
NAME

7:0

FIFO_WM[7:0]

FUNCTION
Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing
this register. Interrupt only fires once. This register should be set to nonzero value, before choosing this interrupt source.
This field should be changed when FIFO is empty to avoid spurious
interrupts.

FIFO_CONFIG3
Name: FIFO_CONFIG3
Address: 42 (2Ah)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:4 -

3:0

FIFO_WM[11:8]

FUNCTION
Reserved
Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing
this register. Interrupt only fires once. This register should be set to nonzero value, before choosing this interrupt source.
This field should be changed when FIFO is empty to avoid spurious
interrupts.

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ICM-42670-P
INT_SOURCE0
Name: INT_SOURCE0
Address: 43 (2Bh)
Serial IF: R/W
Reset value: 0x10
BIT
NAME
7

ST_INT1_EN

6

FSYNC_INT1_EN

5

PLL_RDY_INT1_EN

4

RESET_DONE_INT1_EN

3

DRDY_INT1_EN

2

FIFO_THS_INT1_EN

1

FIFO_FULL_INT1_EN

0

AGC_RDY_INT1_EN

FUNCTION
0: Self-Test Done interrupt not routed to INT1
1: Self-Test Done interrupt routed to INT1
0: FSYNC interrupt not routed to INT1
1: FSYNC interrupt routed to INT1
0: PLL ready interrupt not routed to INT1
1: PLL ready interrupt routed to INT1
0: Reset done interrupt not routed to INT1
1: Reset done interrupt routed to INT1
0: Data Ready interrupt not routed to INT1
1: Data Ready interrupt routed to INT1
0: FIFO threshold interrupt not routed to INT1
1: FIFO threshold interrupt routed to INT1
0: FIFO full interrupt not routed to INT1
1: FIFO full interrupt routed to INT1
To avoid FIFO FULL interrupts while reading FIFO, this bit should be disabled
while reading FIFO
0: UI AGC ready interrupt not routed to INT1
1: UI AGC ready interrupt routed to INT1

INT_SOURCE1
Name: INT_SOURCE1
Address: 44 (2Ch)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7
I3C_PROTOCOL_ERROR_IN
6
T1_EN
5:4 3

SMD_INT1_EN

2

WOM_Z_INT1_EN

1

WOM_Y_INT1_EN

0

WOM_X_INT1_EN

FUNCTION
Reserved
0: I3CSM protocol error interrupt not routed to INT1
1: I3CSM protocol error interrupt routed to INT1
Reserved
0: SMD interrupt not routed to INT1
1: SMD interrupt routed to INT1
0: Z-axis WOM interrupt not routed to INT1
1: Z-axis WOM interrupt routed to INT1
0: Y-axis WOM interrupt not routed to INT1
1: Y-axis WOM interrupt routed to INT1
0: X-axis WOM interrupt not routed to INT1
1: X-axis WOM interrupt routed to INT1

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ICM-42670-P
INT_SOURCE3
Name: INT_SOURCE3
Address: 45 (2Dh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7

ST_INT2_EN

6

FSYNC_INT2_EN

5

PLL_RDY_INT2_EN

4

RESET_DONE_INT2_EN

3

DRDY_INT2_EN

2

FIFO_THS_INT2_EN

1

FIFO_FULL_INT2_EN

0

AGC_RDY_INT2_EN

FUNCTION
0: Self-Test Done interrupt not routed to INT2
1: Self-Test Done interrupt routed to INT2
0: FSYNC interrupt not routed to INT2
1: FSYNC interrupt routed to INT2
0: PLL ready interrupt not routed to INT2
1: PLL ready interrupt routed to INT2
0: Reset done interrupt not routed to INT2
1: Reset done interrupt routed to INT2
0: Data Ready interrupt not routed to INT2
1: Data Ready interrupt routed to INT2
0: FIFO threshold interrupt not routed to INT2
1: FIFO threshold interrupt routed to INT2
0: FIFO full interrupt not routed to INT2
1: FIFO full interrupt routed to INT2
0: AGC ready interrupt not routed to INT2
1: AGC ready interrupt routed to INT2

INT_SOURCE4
Name: INT_SOURCE4
Address: 46 (2Eh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7
I3C_PROTOCOL_ERROR_IN
6
T2_EN
5:4 3

SMD_INT2_EN

2

WOM_Z_INT2_EN

1

WOM_Y_INT2_EN

0

WOM_X_INT2_EN

FUNCTION
Reserved
0: I3CSM protocol error interrupt not routed to INT2
1: I3CSM protocol error interrupt routed to INT2
Reserved
0: SMD interrupt not routed to INT2
1: SMD interrupt routed to INT2
0: Z-axis WOM interrupt not routed to INT2
1: Z-axis WOM interrupt routed to INT2
0: Y-axis WOM interrupt not routed to INT2
1: Y-axis WOM interrupt routed to INT2
0: X-axis WOM interrupt not routed to INT2
1: X-axis WOM interrupt routed to INT2

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ICM-42670-P
FIFO_LOST_PKT0
Name: FIFO_LOST_PKT0
Address: 47 (2Fh)
Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 FIFO_LOST_PKT_CNT[7:0]

FUNCTION
Low byte, number of packets lost in the FIFO

FIFO_LOST_PKT1
Name: FIFO_LOST_PKT1
Address: 48 (30h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 FIFO_LOST_PKT_CNT[15:8]

FUNCTION
High byte, number of packets lost in the FIFOAPEX_DATA0
Name: APEX_DATA0
Address: 49 (31h)Serial IF: SYNCRReset value: 0x00
BIT
NAME
7:0 STEP_CNT[7:0]

FUNCTION
Pedometer Output: Lower byte of Step Count measured by pedometer

APEX_DATA1
Name: APEX_DATA1
Address: 50 (32h)Serial IF: SYNCRReset value: 0x00
BIT
NAME
7:0 STEP_CNT[15:8]

FUNCTION
Pedometer Output: Upper byte of Step Count measured by pedometer

APEX_DATA2
Name: APEX_DATA2
Address: 51 (33h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0

STEP_CADENCE

FUNCTION
Pedometer Output: Walk/run cadency in number of samples. Format is u6.2.
e.g. At 50 Hz ODR and 2 Hz walk frequency, the cadency is 25 samples andthe register will output 100.

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ICM-42670-P
APEX_DATA3
Name: APEX_DATA3
Address: 52 (34h)Serial IF: R
Reset value: 0x04
BIT
NAME
7:3 2

DMP_IDLE

1:0

ACTIVITY_CLASSFUNCTION
Reserved
0: Indicates DMP is running
1: Indicates DMP is idle
Pedometer Output: Detected activity
00: Unknown
01: Walk
10: Run11: Reserved

INTF_CONFIG0
Name: INTF_CONFIG0
Address: 53 (35h)Serial IF: R/W
Reset value: 0x30
BIT
NAME
7
6

FIFO_COUNT_FORMAT

5

FIFO_COUNT_ENDIAN

4

SENSOR_DATA_ENDIAN

3:0-

FUNCTION
Reserved
0: FIFO count is reported in bytes
1: FIFO count is reported in records (1 record = 16 bytes for header + gyro +accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel +temp sensor data)
This bit applies to FIFO Count and Lost Packet Count
0: Reported in Little Endian format
1: Reported in Big Endian format
0: Sensor data is reported in Little Endian format
1: Sensor data is reported in Big Endian format
Reserved

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ICM-42670-P
INTF_CONFIG1
Name: INTF_CONFIG1
Address: 54 (36h)Serial IF: R/W
Reset value: 0x4D
BIT
NAME
7:4 3

2

1:0

I3C_SDR_EN

I3C_DDR_EN

CLKSELFUNCTION
Reserved
0: I3CSM SDR mode not enabled
1: I3CSM SDR mode enabled
Device will be in pure I2C mode if {I3C_SDR_EN, I3C_DDR_EN} = 00
0: I3CSM DDR mode not enabled
1: I3CSM DDR mode enabledThis bit will not take effect unless I3C_SDR_EN = 1.
00: Always select internal RC oscillator
01: Select PLL when available, else select RC oscillator (default)
10: Reserved
11: Disable all clocks

INT_STATUS_DRDY
Name: INT_STATUS_DRDY
Address: 57 (39h)Serial IF: R/C
Reset value: 0x00
BIT
NAME
7:1 0

DATA_RDY_INT

FUNCTION
Reserved
This bit automatically sets to 1 when a Data Ready interrupt is generated.
The bit clears to 0 after the register has been read.

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ICM-42670-P
INT_STATUS
Name: INT_STATUS
Address: 58 (3Ah)
Serial IF: R/C
Reset value: 0x10
BIT
NAME
7

ST_INT

6

FSYNC_INT5

PLL_RDY_INT

4RESET_DONE_INT

3

-

2

FIFO_THS_INT

1

FIFO_FULL_INT0

AGC_RDY_INT

FUNCTION
This bit automatically sets to 1 when a Self Test done interrupt is generated.
The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when an FSYNC interrupt is generated. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when a PLL Ready interrupt is generated. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when software reset is complete. The bit
clears to 0 after the register has been read.
Reserved
This bit automatically sets to 1 when the FIFO buffer reaches the thresholdvalue. The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to 0
after the register has been read.
This bit automatically sets to 1 when an AGC Ready interrupt is generated.
The bit clears to 0 after the register has been read.

INT_STATUS2
Name: INT_STATUS2
Address: 59 (3Bh)
Serial IF: R/C
Reset value: 0x00
BIT
NAME
7:4 3
SMD_INT2
WOM_X_INT
1
WOM_Y_INT0
WOM_Z_INTFUNCTION
Reserved
Significant Motion Detection Interrupt, clears on read
Wake on Motion Interrupt on X-axis, clears on read
Wake on Motion Interrupt on Y-axis, clears on read
Wake on Motion Interrupt on Z-axis, clears on read

INT_STATUS3
Name: INT_STATUS3
Address: 60 (3Ch)
Serial IF: R/C
Reset value: 0x00
BIT
NAME
7:6 5
STEP_DET_INT
4
STEP_CNT_OVF_INT
3
TILT_DET_INT
2
FF_DET_INT
1
LOWG_DET_INT
0-

FUNCTION
Reserved
Step Detection Interrupt, clears on read
Step Count Overflow Interrupt, clears on read
Tilt Detection Interrupt, clears on read
Freefall Interrupt, clears on read
LowG Interrupt, clears on read
Reserved

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ICM-42670-P
FIFO_COUNTH
Name: FIFO_COUNTH
Address: 61 (3Dh)
Serial IF: R
Reset value: 0x00
BIT
NAME
7:0

FIFO_COUNT[15:8]

FUNCTION
High Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_FORMAT setting.
Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH
and FIFO_COUNTL.

FIFO_COUNTLName: FIFO_COUNTL
Address: 62 (3Eh)
Serial IF: R
Reset value: 0x00
BIT
NAME
7:0

FIFO_COUNT[7:0]

FUNCTION
Low Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_REC setting.
Reading this byte latches the data for both FIFO_COUNTH, and
FIFO_COUNTL.

FIFO_DATA
Name: FIFO_DATA
Address: 63 (3Fh)
Serial IF: R
Reset value: 0xFF
BIT
NAME
7:0 FIFO_DATAFUNCTIONFIFO data port

WHO_AM_I
Name: WHO_AM_I
Address: 117 (75h)Serial IF: R
Reset value: 0x67
BIT
NAME
7:0 WHOAMI

FUNCTION
Register to indicate to user which device is being accessed

Description:
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default
value of the register is 0x67. This is different from the I 2C address of the device as seen on the slave I2C controller
by the applications processor.

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ICM-42670-P
BLK_SEL_W
Name: BLK_SEL_W
Address: 121 (79h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

BLK_SEL_W

FUNCTION
Block address for accessing MREG1 or MREG2 register space for register
write operation

MADDR_W
Name: MADDR_W
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

MADDR_W

FUNCTION
To write to a register in MREG1 or MREG2 space, set this register field to theaddress of the register in MREG1 or MREG2 space.

M_W
Name: M_W
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

M_W

FUNCTION
To write a value to a register in MREG1 or MREG2 space, that value must be
written to M_W.

BLK_SEL_R
Name: BLK_SEL_R
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

BLK_SEL_R

FUNCTION
Block address for accessing MREG1 or MREG2 register space for register
read operation

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ICM-42670-P
MADDR_R
Name: MADDR_R
Address: 125 (7Dh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

MADDR_R

FUNCTION
To read the value of a register in MREG1 or MREG2 space, set this register
field to the address of the register in MREG1 or MREG2 space.

M_R
Name: M_R
Address: 126 (7Eh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

M_R

FUNCTION
To read the value of a register in MREG1 or MREG2 space, that value isaccessed from M_R.

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ICM-42670-P

USER BANK MREG1 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank MREG1. The procedure foraccessing MREG1 registers is described in section 13.

TMST_CONFIG1
Name: TMST_CONFIG1
Address: 00 (00h)Serial IF: R/W
Reset value: 0x02
BIT
NAME
7:5 -

4

TMST_ON_SREG_EN

3

TMST_RES

2

TMST_DELTA_EN

1

TMST_FSYNC_EN

0

TMST_ENFUNCTION
Reserved
0: TMST_FSYNCH and TMST_FSYNCL registers report the delta time fromFSYNC to next ODR
1: TMST_FSYNCH and TMST_FSYNCL registers report: absolute timestampwhen FSYNC even is not present; delta time from FSYNC to next ODR when
FSYNC event is present
Time Stamp resolution: When set to 0 (default), time stamp resolution is 1
µs. When set to 1, resolution is 16 µs
Time Stamp delta enable: When set to 1, the time stamp field contains themeasurement of time since the last occurrence of ODR.
Time Stamp register FSYNC enable (default). When set to 1, the contents of
the Timestamp feature of FSYNC is enabled. The user also needs to selectFIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the
FIFO.
0: Time Stamp register disable
1: Time Stamp register enable

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ICM-42670-P
FIFO_CONFIG5
Name: FIFO_CONFIG5
Address: 01 (01h)Serial IF: R/W
Reset value: 0x20
BIT
NAME
7:6

-

5

FIFO_WM_GT_TH

4

FIFO_RESUME_PARTIAL_RD

3

FIFO_HIRES_EN

2

FIFO_TMST_FSYNC_EN

1

FIFO_GYRO_EN

0

FIFO_ACCEL_EN

FUNCTION
Reserved
0: Trigger FIFO Watermark interrupt when FIFO_COUNT =FIFO_WM
1: Trigger FIFO Watermark interrupt on every ODR if FIFO_COUNT= FIFO_WM
0: FIFO is read in packets. If a partial packet is read, then thesubsequent read will start from the beginning of the un-readpacket.
1: FIFO can be read partially. When read is resumed, FIFO bytes
will continue from last read point. The SW driver is responsible forcascading previous read and present read and for maintaining
frame boundaries.
0: 20-bit resolution not enabled in the FIFO packet readout
1: 20-bit resolution enabled in the FIFO packet readout
0: TMST in the FIFO cannot be replaced by the FSYNC timestamp
1: Allows the TMST in the FIFO to be replaced by the FSYNC
timestamp
0: Gyro packets not enabled to go to FIFO
1: Enables Gyro packets to go to FIFO
0: Accel packets not enabled to go to FIFO
1: Enables Accel packets to go to FIFO

Page 74 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
FIFO_CONFIG6
Name: FIFO_CONFIG6
Address: 02 (02h)Serial IF: R/W
Reset value: 0x00
BIT
NAME

FUNCTION

7:5-

Reserved

4

FIFO_EMPTY_INDICATOR_DIS

0: 0xFF is sent out as FIFO data when FIFO is empty.
1: The last FIFO data is sent out when FIFO is empty.

3:1-

Reserved

0

RCOSC_REQ_ON_FIFO_THS_DIS

0: When the FIFO is operating in ALP+WUOSC mode and thewatermark (WM) interrupt is enabled, the FIFO wakes up thesystem oscillator (RCOSC) as soon as the watermark level isreached. The system oscillator remains enabled until a HostFIFO read operation happens. This will temporarily cause asmall increase in the power consumption due to the enablingof the system oscillator.
1: The system oscillator is not automatically woken-up by the
FIFO/INT when the WM interrupt is triggered. The side effectis that the host can receive invalid packets until the systemoscillator is off after it has been turned on for other reasons
not related to a WM interrupt.
The recommended setting of this bit is ‘1’ before entering andduring all power modes excluding ALP with WUOSC. This is inorder to avoid having to do a FIFO access/flush before entering
sleep mode. During ALP with WUOSC it is recommended to set
this bit to ‘0’. It is recommended to reset this bit back to ‘1’
before exiting ALP+WUOSC with a wait time of 1 ODR or
higher.

Page 75 of 103
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Revision: 1.1

ICM-42670-P
FSYNC_CONFIG
Name: FSYNC_CONFIG
Address: 03 (03h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7
-

6:4

FSYNC_UI_SEL

3:2

-

1

FSYNC_UI_FLAG_CLEAR_SEL

0

FSYNC_POLARITY

FUNCTION
Reserved
000: Do not tag FSYNC flag
001: Tag FSYNC flag to TEMP_OUT LSB
010: Tag FSYNC flag to GYRO_XOUT LSB
011: Tag FSYNC flag to GYRO_YOUT LSB
100: Tag FSYNC flag to GYRO_ZOUT LSB
101: Tag FSYNC flag to ACCEL_XOUT LSB
110: Tag FSYNC flag to ACCEL_YOUT LSB
111: Tag FSYNC flag to ACCEL_ZOUT LSB
Reserved
0: FSYNC flag is cleared when UI sensor register is updated
1: FSYNC flag is cleared when UI interface reads the sensor register LSB of
FSYNC tagged axis
0: Start from Rising edge of FSYNC pulse to measure FSYNC interval
1: Start from Falling edge of FSYNC pulse to measure FSYNC interval

INT_CONFIG0
Name: INT_CONFIG0
Address: 04 (04h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:6 -

5:4

UI_DRDY_INT_CLEAR

3:2

FIFO_THS_INT_CLEAR

1:0

FIFO_FULL_INT_CLEARFUNCTION
Reserved
Data Ready Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read
01: Clear on Status Bit Read
10: Clear on Sensor Register Read
11: Clear on Status Bit Read OR on Sensor Register read
FIFO Threshold Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read OR on FIFO data 1 byte read
FIFO Full Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read OR on FIFO data 1 byte readPage 76 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
INT_CONFIG1
Name: INT_CONFIG1
Address: 05 (05h)Serial IF: R/W
Reset value: 0x10
BIT
NAME
7
6

INT_TPULSE_DURATION

5

-

4

INT_ASYNC_RESET

3:0-

FUNCTION
Reserved
Interrupt pulse duration
0: Interrupt pulse duration is 100 µs
1: Interrupt pulse duration is 8 µs
Reserved
0: The interrupt pulse is reset as soon as the interrupt status register is read
if the pulse is still active.
1: The interrupt pulse remains high for the intended duration independentof when the interrupt status register is read. This is the default andrecommended setting. In this case, when in ALP with the WUOSC clock, theclearing of the interrupt status register requires up to one ODR period after
reading.
Reserved

SENSOR_CONFIG3
Name: SENSOR_CONFIG3
Address: 06 (06h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7
6
APEX_DISABLE
5:0 -FUNCTION
Reserved
1: Disable APEX features to extend FIFO size to 2.25 Kbytes
Reserved

Page 77 of 103
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Revision: 1.1

ICM-42670-P
ST_CONFIG
Name: ST_CONFIG
Address: 19 (13h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7
-

6

FUNCTION
Reserved
This bit selects the number of sensor samples that should be used to process
self-test

ST_NUMBER_SAMPLE
0: 16 samples
1: 200 samples
These bits control the tolerated ratio between self-test processed values andreference (fused) ones for accelerometer

5:3

ACCEL_ST_LIM
000 to 110: Reserved
111: 50%
These bits control the tolerated ratio between self-test processed values andreference (fused) ones for gyroscope

2:0

GYRO_ST_LIM
000 to 110: Reserved
111: 50%

Page 78 of 103
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ICM-42670-P
SELFTESTName: SELFTEST
Address: 20 (14h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7

GYRO_ST_EN

6

ACCEL_ST_EN

5:0-

FUNCTION
1: Enable gyro self-test operation. Host needs to program this bit to 0 to
move device out of self-test mode. If host programs this bit to 0 while
ST_BUSY = 1 and ST_DONE = 0, the current running self-test operation is
terminated by host.
1: Enable accel self-test operation. Host needs to program this bit to 0 to
move device out of self-test mode. If host programs this bit to 0 while
ST_BUSY = 1 and ST_DONE = 0, the current running self-test operation is
terminated by host.
Reserved

INTF_CONFIG6
Name: INTF_CONFIG6
Address: 35 (23h)Serial IF: R/W
Reset value: 0x7C
BIT
NAME
7:5 4

I3C_TIMEOUT_EN

3

I3C_IBI_BYTE_EN

2

I3C_IBI_EN

1:0-

FUNCTION
Reserved
0: I2C/I3CSM timeout function not enabled
1: I2C/I3CSM timeout function enabled
0: I3CSM IBI payload function not enabled
1: I3CSM IBI payload function enabled
0: I3CSM IBI function not enabled
1: I3CSM IBI function enabled
Reserved

INTF_CONFIG10
Name: INTF_CONFIG10
Address: 37 (25h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7

ASYNCTIME0_DIS

6:0-

FUNCTION
0: I3CSMAsynchronous Mode 0 timing control is enabled
1: I3CSM Asynchronous Mode 0 timing control is disabled
Reserved

Page 79 of 103
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ICM-42670-P
INTF_CONFIG7
Name: INTF_CONFIG7
Address: 40 (28h)Serial IF: R/W
Reset value: 0x0C
BIT
NAME
7:4 -

3

2:0

I3C_DDR_WR_MODE-

FUNCTION
Reserved
This bit controls how I3CSM slave treats the 1st 2-byte data from host in a
DDR write operation.
0: (a) The 1st-byte in DDR-WR configures the starting register address where
the write operation should occur. (b) The 2nd-byte in DDR-WR is ignored anddropped. (c) The 3rd-byte in DDR-WR will be written into the register withaddress specified by the 1st-byte. Or, the next DDR-RD will be starting fromthe address specified by the 1st-byte of previous DDR-WR.
1: (a) The 1st-byte in DDR-WR configures the starting register address where
the write operation should occur. (b) The 2nd-byte in DDR-WR will be
written into the register with address specified by the 1st-byte.
Reserved

OTP_CONFIG
Name: OTP_CONFIG
Address: 43 (2Bh)
Serial IF: R/W
Reset value: 0x06
BIT
NAME
7:4 3:2

OTP_COPY_MODE

1:0-

FUNCTION
Reserved
00: Reserved
01: Enable copying OTP block to SRAM
10: Reserved
11: Enable copying self-test data from OTP memory to SRAM
Reserved

Page 80 of 103
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ICM-42670-P
INT_SOURCE6
Name: INT_SOURCE6
Address: 47 (2Fh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7

FF_INT1_EN

6

LOWG_INT1_EN

5

STEP_DET_INT1_EN

4

STEP_CNT_OFL_INT1_EN

3

TILT_DET_INT1_EN

2:0-

FUNCTION
0: Freefall interrupt not routed to INT1
1: Freefall interrupt routed to INT1
0: Low-g interrupt not routed to INT1
1: Low-g interrupt routed to INT1
0: Step detect interrupt not routed to INT1
1: Step detect interrupt routed to INT1
0: Step count overflow interrupt not routed to INT1
1: Step count overflow interrupt routed to INT1
0: Tilt detect interrupt not routed to INT1
1: Tile detect interrupt routed to INT1
Reserved

INT_SOURCE7
Name: INT_SOURCE7
Address: 48 (30h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7

FF_INT2_EN

6

LOWG_ INT2_EN

5

STEP_DET_INT2_EN

4

STEP_CNT_OFL_INT2_EN

3

TILT_DET_INT2_EN

2:0-

FUNCTION
0: Freefall interrupt not routed to INT2
1: Freefall interrupt routed to INT2
0: Low-g interrupt not routed to INT2
1: Low-g interrupt routed to INT2
0: Step detect interrupt not routed to INT2
1: Step detect interrupt routed to INT2
0: Step count overflow interrupt not routed to INT2
1: Step count overflow interrupt routed to INT2
0: Tilt detect interrupt not routed to INT2
1: Tile detect interrupt routed to INT2
Reserved

Page 81 of 103
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ICM-42670-P
INT_SOURCE8
Name: INT_SOURCE8
Address: 49 (31h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:6 5

FSYNC_IBI_EN

4

PLL_RDY_IBI_EN

3

UI_DRDY_IBI_EN

2

FIFO_THS_IBI_EN

1

FIFO_FULL_IBI_EN

0

AGC_RDY_IBI_EN

FUNCTION
Reserved
0: FSYNC interrupt not routed to IBI
1: FSYNC interrupt routed to IBI
0: PLL ready interrupt not routed to IBI
1: PLL ready interrupt routed to IBI
0: UI data ready interrupt not routed to IBI
1: UI data ready interrupt routed to IBI
0: FIFO threshold interrupt not routed to IBI
1: FIFO threshold interrupt routed to IBI
0: FIFO full interrupt not routed to IBI
1: FIFO full interrupt routed to IBI
0: AGC ready interrupt not routed to IBI
1: AGC ready interrupt routed to IBI

INT_SOURCE9
Name: INT_SOURCE9
Address: 50 (32h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
I3C_PROTOCOL_ERROR_IBI
7_EN6

FF_IBI_EN

5

LOWG_IBI_EN

4

SMD_IBI_EN

3

WOM_Z_IBI_EN

2

WOM_Y_IBI_EN

1

WOM_X_IBI_EN

0

ST_DONE_IBI_EN

FUNCTION
0: I3C protocol error interrupt not routed to IBI
1: I3CSM protocol error interrupt routed to IBI
0: Freefall interrupt not routed to IBI
1: Freefall interrupt routed to IBI
0: Low-g interrupt not routed to IBI
1: Low-g interrupt routed to IBI
0: SMD interrupt not routed to IBI
1: SMD interrupt routed to IBI
0: Z-axis WOM interrupt not routed to IBI
1: Z-axis WOM interrupt routed to IBI
0: Y-axis WOM interrupt not routed to IBI
1: Y-axis WOM interrupt routed to IBI
0: X-axis WOM interrupt not routed to IBI
1: X-axis WOM interrupt routed to IBI
0: Self-test done interrupt not routed to IBI
1: Self-test done interrupt routed to IBISMPage 82 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
INT_SOURCE10
Name: INT_SOURCE10
Address: 51 (33h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:6 5

STEP_DET_IBI_EN

4

STEP_CNT_OFL_IBI_EN

3

TILT_DET_IBI_EN

2:0-

FUNCTION
Reserved
0: Step detect interrupt not routed to IBI
1: Step detect interrupt routed to IBI
0: Step count overflow interrupt not routed to IBI
1: Step count overflow interrupt routed to IBI
0: Tilt detect interrupt not routed to IBI
1: Tile detect interrupt routed to IBIReserved

Page 83 of 103
Document Number: DS-000451
Revision: 1.1

ICM-42670-P
APEX_CONFIG2
Name: APEX_CONFIG2
Address: 68 (44h)Serial IF: R/W
Reset value: 0xA2
BIT
NAME

7:4

3:0

LOW_ENERGY_AMP_TH_S
EL

DMP_POWER_SAVE_TIME_SEL

FUNCTION
Threshold to select a valid step. Used to increase step detection for slow
walk use case.
0000: 30 mg
0001: 35 mg
0010: 40 mg
0011: 45 mg
0100: 50 mg
0101: 55 mg
0110: 60 mg
0111: 65 mg
1000: 70 mg
1001: 75 mg
1010: 80 mg (default)
1011: 85 mg
1100: 90 mg
1101: 95 mg
1110: 100 mg
1111: 105 mg
Duration of the period while the DMP stays awake after receiving a WOM
event.
0000: 0 seconds
0001: 4 seconds
0010: 8 seconds (default)
0011: 12 seconds
0100: 16 seconds
0101: 20 seconds
0110: 24 seconds
0111: 28 seconds
1000: 32 seconds
1001: 36 seconds
1010: 40 seconds
1011: 44 seconds
1100: 48 seconds
1101: 52 seconds
1110: 56 seconds
1111: 60 seconds

Page 84 of 103
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Revision: 1.1

ICM-42670-P
APEX_CONFIG3
Name: APEX_CONFIG3
Address: 69 (45h)Serial IF: R/W
Reset value: 0x85
BIT
NAME

FUNCTION
Threshold of step detection sensitivity.
Low values increase detection sensitivity: reduce miss-detection.
High values reduce detection sensitivity: reduce false-positive.

7:4

PED_AMP_TH_SEL

0000: 30 mg
0001: 34 mg
0010: 38 mg
0011: 42 mg
0100: 46 mg
0101: 50 mg
0110: 54 mg
0111: 58 mg
1000: 62 mg (default)
1001: 66 mg
1010: 70 mg
1011: 74 mg
1100: 78 mg
1101: 82 mg
1110: 86 mg
1111: 90 mg
Minimum number of steps that must be detected before step count isincremented.
Low values reduce latency but increase false positives.
High values increase step count accuracy but increase latency.

3:0

PED_STEP_CNT_TH_SEL

0000: 0 steps
0001: 1 step
0010: 2 steps
0011: 3 steps
0100: 4 steps
0101: 5 steps (default)
0110: 6 steps
0111: 7 steps
1000: 8 steps
1001: 9 steps
1010: 10 steps
1011: 11 steps
1100: 12 steps
1101: 13 steps
1110: 14 steps
1111: 15 steps

Page 85 of 103
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Revision: 1.1

ICM-42670-P
APEX_CONFIG4
Name: APEX_CONFIG4
Address: 70 (46h)Serial IF: R/W
Reset value: 0x51
BIT
NAME

FUNCTION
Minimum number of steps that must be detected before step event issignaled.
Low values reduce latency but increase false positives.
High values increase step event validity but increase latency.

7:5

4:2

PED_STEP_DET_TH_SEL

PED_SB_TIMER_TH_SEL

000: 0 steps
001: 1 step
010: 2 steps (default)
011: 3 steps
100: 4 steps
101: 5 steps
110: 6 steps
111: 7 steps
Duration before algorithm considers that user has stopped taking steps.
000: 50 samples
001: 75 sample
010: 100 samples
011: 125 samples
100: 150 samples (default)
101: 175 samples
110: 200 samples
111: 225 samples
Threshold to classify acceleration signal as motion not due to steps.
High values improve vibration rejection.
Low values improve detection.

1:0

PED_HI_EN_TH_SEL
00: 87.89 mg
01: 104.49 mg (default)
10: 132.81 mg
11: 155.27 mg

Page 86 of 103
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Revision: 1.1

ICM-42670-P
APEX_CONFIG5
Name: APEX_CONFIG5
Address: 71 (47h)Serial IF: R/W
Reset value: 0x80
BIT
NAME

7:6

5:3

2:0

TILT_WAIT_TIME_SEL

LOWG_PEAK_TH_HYST_SEL

HIGHG_PEAK_TH_HYST_SEL

FUNCTION
Minimum duration for which the device should be tilted before signaling
event.
00: 0s
01: 2s
10: 4s (default)
11: 6sHysteresis value added to the low-g threshold after exceeding it.
000: 31 mg (default)
001: 63 mg
010: 94 mg
011: 125 mg
100: 156 mg
101: 188 mg
110: 219 mg
111: 250 mg
Hysteresis value subtracted from the high-g threshold after exceeding it.
000: 31 mg (default)
001: 63 mg
010: 94 mg
011: 125 mg
100: 156 mg
101: 188 mg
110: 219 mg
111: 250 mg

Page 87 of 103
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ICM-42670-P
APEX_CONFIG9
Name: APEX_CONFIG9Address: 72 (48h)Serial IF: R/W
Reset value: 0x00
BIT
NAME

7:4

FF_DEBOUNCE_DURATION_
SEL

3:1

SMD_SENSITIVITY_SEL

0

SENSITIVITY_MODE

FUNCTION
Period after a freefall is signaled during which a new freefall will not be
detected. Prevents false detection due to bounces.
0000: 0 ms
0001: 1250 ms
0010: 1375 ms
0011: 1500 ms
0100: 1625 ms
0101: 1750 ms
0110: 1875 ms
0111: 2000 ms
1000: 2125 ms (default)
1001: 2250 ms
1010: 2375 ms
1011: 2500 ms
1100: 2625 ms
1101: 2750 ms
1110: 2875 ms
1111: 3000 ms
Parameter to tune SMD algorithm robustness to rejection, ranging from 0
to 4 (values higher than 4 are reserved).
Low values increase detection rate but increase false positives.
High values reduce false positives but reduce detection rate (especially fortransport use cases).
Default value is 0.
Pedometer sensitivity mode
0: Normal (default)
1: Slow walkSlow walk mode improves slow walk detection (<1 Hz) but the number offalse positives may increase.

Page 88 of 103
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ICM-42670-P
APEX_CONFIG10
Name: APEX_CONFIG10
Address: 73 (49h)Serial IF: R/W
Reset value: 0x00
BIT
NAME

7:3

2:0

LOWG_PEAK_TH_SEL

LOWG_TIME_TH_SEL

FUNCTION
Threshold for accel values below which low-g state is detected.
00000: 31 mg (default)
00001: 63 mg
00010: 94 mg
00011: 125 mg
00100: 156 mg
00101: 188 mg
00110: 219 mg
00111: 250 mg
01000: 281 mg
01001: 313 mg
01010: 344 mg
01011: 375 mg
01100: 406 mg
01101: 438 mg
01110: 469 mg
01111: 500 mg
10000: 531 mg
10001: 563 mg
10010: 594 mg
10011: 625 mg
10100: 656 mg
10101: 688 mg
10110: 719 mg
10111: 750 mg
11000: 781 mg
11001: 813 mg
11010: 844 mg
11011: 875 mg
11100: 906 mg
11101: 938 mg
11110: 969 mg
11111: 1000 mg
Number of samples required to enter low-g state.
000: 1 sample (default)
001: 2 samples
010: 3 samples
011: 4 samples
100: 5 samples
101: 6 samples
110: 7 samples
111: 8 samples

Page 89 of 103
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ICM-42670-P
APEX_CONFIG11
Name: APEX_CONFIG11
Address: 74 (4Ah)
Serial IF: R/W
Reset value: 0x00
BIT
NAME

7:3

2:0

HIGHG_PEAK_TH_SEL

HIGHG_TIME_TH_SEL

FUNCTION
Threshold for accel values above which high-g state is detected.
00000: 250 mg (default)
00001: 500 mg
00010: 750 mg
00011: 1000 mg
00100: 1250 mg
00101: 1500 mg
00110: 1750 mg
00111: 2000 mg
01000: 2250 mg
01001: 2500 mg
01010: 2750 mg
01011: 3000 mg
01100: 3250 mg
01101: 3500 mg
01110: 3750 mg
01111: 4000 mg
10000: 4250 mg
10001: 4500 mg
10010: 4750 mg
10011: 5000 mg
10100: 5250 mg
10101: 5500 mg
10110: 5750 mg
10111: 6000 mg
11000: 6250 mg
11001: 6500 mg
11010: 6750 mg
11011: 7000 mg
11100: 7250 mg
11101: 7500 mg
11110: 7750 mg
11111: 8000 mg
Number of samples required to enter high-g state.
000: 1 sample (default)
001: 2 samples
010: 3 samples
011: 4 samples
100: 5 samples
101: 6 samples
110: 7 samples
111: 8 samples

Page 90 of 103
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ICM-42670-P
ACCEL_WOM_X_THR
Name: ACCEL_WOM_X_THR
Address: 75 (4Bh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

WOM_X_TH

FUNCTION
Threshold value for the Wake on Motion Interrupt for X-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9 mg

ACCEL_WOM_Y_THR
Name: ACCEL_WOM_Y_THR
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

WOM_Y_TH

FUNCTION
Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9 mg

ACCEL_WOM_Z_THR
Name: ACCEL_WOM_Z_THR
Address: 77 (4Dh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

WOM_Z_TH

FUNCTION
Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9 mg

OFFSET_USER0
Name: OFFSET_USER0
Address: 78 (4Eh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

GYRO_X_OFFUSER[7:0]

FUNCTION
Lower bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

Page 91 of 103
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ICM-42670-P
OFFSET_USER1
Name: OFFSET_USER1
Address: 79 (4Fh)
Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:4

GYRO_Y_OFFUSER[11:8]

3:0

GYRO_X_OFFUSER[11:8]

FUNCTION
Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
Upper bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

OFFSET_USER2
Name: OFFSET_USER2
Address: 80 (50h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

GYRO_Y_OFFUSER[7:0]

FUNCTION
Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

OFFSET_USER3
Name: OFFSET_USER3
Address: 81 (51h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

GYRO_Z_OFFUSER[7:0]

FUNCTION
Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

OFFSET_USER4
Name: OFFSET_USER4
Address: 82 (52h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
7:4

ACCEL_X_OFFUSER[11:8]

3:0

GYRO_Z_OFFUSER[11:8]

FUNCTION
Upper bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5 mg.
Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.

Page 92 of 103
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ICM-42670-P
OFFSET_USER5
Name: OFFSET_USER5
Address: 83 (53h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

ACCEL_X_OFFUSER[7:0]

FUNCTION
Lower bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5 mg.

OFFSET_USER6
Name: OFFSET_USER6
Address: 84 (54h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

ACCEL_Y_OFFUSER[7:0]

FUNCTION
Lower bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5 mg.

OFFSET_USER7
Name: OFFSET_USER7
Address: 85 (55h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
7:4

ACCEL_Z_OFFUSER[11:8]

3:0

ACCEL_Y_OFFUSER[11:8]

FUNCTION
Upper bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5 mg.
Upper bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5 mg.

OFFSET_USER8
Name: OFFSET_USER8
Address: 86 (56h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:0

ACCEL_Z_OFFUSER[7:0]

FUNCTION
Lower bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5 mg.

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ICM-42670-P
ST_STATUS1
Name: ST_STATUS1
Address: 99 (63h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:6 5
ACCEL_ST_PASS
4
ACCEL_ST_DONE
3
AZ_ST_PASS
2
AY_ST_PASS
1
AX_ST_PASS0-

FUNCTION
Reserved
1: Accel self-test passed for all the 3 axes
1: Accel self-test done for all the 3 axes
1: Accel Z-axis self-test passed
1: Accel Y-axis self-test passed
1: Accel X-axis self-test passed
Reserved

ST_STATUS2
Name: ST_STATUS2
Address: 100 (64h)Serial IF: R
Reset value: 0x00
BIT
NAME
7
-

6

ST_INCOMPLETE

5
4
3
2
1
0

GYRO_ST_PASS
GYRO_ST_DONE
GZ_ST_PASS
GY_ST_PASS
GX_ST_PASS-

FUNCTION
Reserved
1: Self-test is incomplete.
This bit is set to 1 if the self-test was aborted.
One possible cause of aborting the self-test may be the detection ofsignificant movement in the gyro when the self-test for gyro and/or accel isbeing executed.
1: Gyro self-test passed for all the 3 axes
1: Gyro self-test done for all the 3 axes
1: Gyro Z-axis self-test passed
1: Gyro Y-axis self-test passed
1: Gyro X-axis self-test passed
Reserved

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ICM-42670-P
FDR_CONFIG
Name: FDR_CONFIG
Address: 102 (66h)Serial IF: R/W
Reset value: 0x00
BIT
NAME
7:4 -

3:0

FDR_SEL

FUNCTION
Reserved
FIFO packet rate decimation factor. Sets the number of discarded FIFO
packets. User must disable sensors when initializing FDR_SEL value or
making changes to it.
0xxx: Decimation is disabled, all packets are sent to FIFO
1000: 1 packet out of 2 is sent to FIFO
1001: 1 packet out of 4 is sent to FIFO
1010: 1 packet out of 8 is sent to FIFO
1011: 1 packet out of 16 is sent to FIFO
1100: 1 packet out of 32 is sent to FIFO
1101: 1 packet out of 64 is sent to FIFO
1110: 1 packet out of 128 is sent to FIFO
1111: 1 packet out of 256 is sent to FIFO

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ICM-42670-P
APEX_CONFIG12
Name: APEX_CONFIG12
Address: 103 (67h)Serial IF: R/W
Reset value: 0x00
BIT
NAME

7:4

3:0

FF_MAX_DURATION_SEL

FF_MIN_DURATION_SEL

FUNCTION
Maximum freefall length. Longer freefalls are ignored.
0000: 102 cm (default)
0001: 120 cm
0010: 139 cm
0011: 159 cm
0100: 181 cm
0101: 204 cm
0110: 228 cm
0111: 254 cm
1000: 281 cm
1001: 310 cm
1010: 339 cm
1011: 371 cm
1100: 403 cm
1101: 438 cm
1110: 473 cm
1111: 510 cm
Minimum freefall length. Shorter freefalls are ignored.
0000: 10 cm (default)
0001: 12 cm
0010: 13 cm
0011: 16 cm
0100: 18 cm
0101: 20 cm
0110: 23 cm
0111: 25 cm
1000: 28 cm
1001: 31 cm
1010: 34 cm
1011: 38 cm
1100: 41 cm
1101: 45 cm
1110: 48 cm
1111: 52 cm

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ICM-42670-P

USER BANK MREG2 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank MREG2. The procedure foraccessing MREG2 registers is described in section 13.

OTP_CTRL7
Name: OTP_CTRL7
Address: 06 (06h)Serial IF: RWS
Reset value: 0x06 (initial reset value is 0x0C, it changes to 0x06 after OTP load completes)
BIT
NAME
FUNCTION
7:4 Reserved
3
OTP_RELOAD
Setting this bit to 1 triggers OTP copy operation.
2
Reserved
0: Power up OTP to copy from OTP to SRAM
1: Power down OTP
1
OTP_PWR_DOWN
0-This bit is automatically set to 1 when OTP copy operation is complete.
Reserved

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ICM-42670-P

USER BANK MREG3 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank MREG3. The procedure foraccessing MREG3 registers is described in section 13.

XA_ST_DATA
Name: XA_ST_DATA
Address: 00 (00h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 XA_ST_DATAFUNCTION
Accel X-axis factory trimmed self-test response.

YA_ST_DATA
Name: YA_ST_DATA
Address: 01 (01h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 YA_ST_DATAFUNCTION
Accel Y-axis factory trimmed self-test response.

ZA_ST_DATA
Name: ZA_ST_DATA
Address: 02 (02h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 ZA_ST_DATAFUNCTION
Accel Z-axis factory trimmed self-test response.

XG_ST_DATA
Name: XG_ST_DATA
Address: 03 (03h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 XG_ST_DATAFUNCTION
Gyro X-axis factory trimmed self-test response.

YG_ST_DATA
Name: YG_ST_DATA
Address: 04 (04h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 YG_ST_DATAFUNCTION
Gyro Y-axis factory trimmed self-test response.

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ICM-42670-P
ZG_ST_DATA
Name: ZG_ST_DATA
Address: 05 (05h)Serial IF: R
Reset value: 0x00
BIT
NAME
7:0 ZG_ST_DATAFUNCTION
Gyro Z-axis factory trimmed self-test response.

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ICM-42670-P

SMARTMOTION PRODUCT FAMILY
ICM-42670-P is a member of the SmartMotion™ family of MEMS motion sensors with 1-, 2-, 3-, 6-, 7-, and 9-axis
IMU platforms addressing the emerging need of many mass-market consumer applications via improved
performance, accuracy, and intuitive motion and gesture-based interfaces.
For more information, please visit invensense.tdk.com.

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ICM-42670-P

REFERENCE
Please refer to the following application notes for additional information.
•

InvenSense MEMS Handling Application Note (AN-IVS-0002A-00) for the following information:oManufacturing Recommendationso▪ Assembly Guidelines and Recommendations▪ PCB Design Guidelines and Recommendations▪ MEMS Handling Instructions▪ ESD Considerations▪ Reflow Specification▪ Storage Specifications▪ Package Marking Specification▪ Tape & Reel Specification▪ Reel & Pizza Box Label▪ Packaging▪ Representative Shipping Carton Label
Compliance▪
▪
▪

Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer•

Understanding IMU Sensor Offset (AN-000257)•

ICM-42607x DMP Mode Accelerometer and Gyroscope Self-Test (AN-000258)•

ICM-42607x/42670x Products PCB Board Design Guide (AN-000262)•

TDK InvenSense IMU Calibration Application Note (AN-000265)•

ICM-42607x/42670x Accelerometer Low Power Mode Implementation (AN-000266)•

ICM-42607x and ICM-42670x Errata (AN-000273)

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ICM-42670-P

REVISION HISTORYREVISION DATEREVISIONDESCRIPTION

04/15/2021

1.0

Initial Release

05/23/2022

1.1

Added Note 8 (Tables 1 and 2); Added Device Package in Tape and Reel (Section 11)

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ICM-42670-P

This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility
is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits
and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed
nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims
or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is
not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication orotherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied.
Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or soldin the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life
threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear
instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2022 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP,
AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and productnames may be trademarks of the respective companies with which they are associated.

©2022 InvenSense. All rights reserved.

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