CDR with loop filter
86G CDR 1:2 Demux
Type: ModulePage 1

Technology: SiGefT /fmax : 225/300 GHz

Metallization: 4Ref.-No.:R1020

Brief description:

The CDR consists of an input amplifier, a PD withdata recovery, a 1:2 demultiplexing functionality
and a delay line. Two output clocks providing thedriving clock frequency and clock/2 are available
for easier data processing off chip. The externalloop filter (LF) is dimensioned for operation with a54GHz TLC VCO and its expected tuning sensitivity. The loop filter settings have to be customizedafter measurement of the exact VCO characteristic by the customer. Standard setup is the CDR
module with the loop filter board on top of it. A
separate VCO module (not in shipment) has to beconnected by the customer. Note that the VCO
output must be connected to the CDR clock input via an attenuator in order to protect the CDRclock input.

Electrical data:
Parameter
General operating conditions
Junction temperature range
Ambient temperature range
Current consumption of CDR
Current consumption of LF
Power supplies
Power supply of CDR
Power supplies of LF

SymbolMinTyp00Max

Unit+125+50◦

Remark/Condition

1100
4×20CCmAmAVee-5.0

VV 1p
V 1n
V 2p
V 2n+5.0-5.0+9.5-0.5

VVVV

initial values, tunable
initial values, tunable

VVV
VV
V

required for operation
required for operation◦

Absolute maximum ratingsof LF power supplies

LF voltage window 1
LF voltage window 2
PLL operation with TLC VCO
Input data rate of CDR
Expected PLL locking range
Expected PLL bandwidth
Push-button from upP to GND

V 1p
V 1n
V 2p
V 2n
V 1p-V 1nV 2p-V 2n0.0-10.00.0-16.0+10.0+10.0+10.00.0+16.0
0.0+10.0+10.0

86±2005BW

Gbit/sMHzMHzopenGND
LF output voltage (Vtune )VO+4.6+6.4

V

Expected VCO tuning voltage(Vtune )VI0+18V

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MICRAMTM Microelectronic GmbH
Design&Engineering

when PLL is locked
temporaryfor obtaining PLL lock
single ended, valid for
initial values of V 2p and V 2nsingle ended,
expected for TLC VCO

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CDR with loop filter
86G CDR 1:2 Demux

Page 2

Parameter
RF data inputs of CDR(DataInP, DataInN)
Input amplitude

SymbolMin

Typ

VIH-VIL

150

300

Operating voltage window
Input resistanceRF clock inputs of CDR(ClkInP, ClkInN)
Input amplitude

VI
R-700

VIH-VIL

150

Operating voltage window
Input resistance
RF data outputs of CDR(DataOut0P, DataOut0N)(DataOut1P, DataOut1N),
Output amplitude

VI
R-700

Max300

Unit

Remark/ConditionmVsingle ended,peak-to-peaksingle ended

65mVΩ

300mV65mVΩ

VOH-VOL280

mV

Output resistanceRF clock outputs of CDR(ClkP, ClkN)
Output amplitude

R65Ω

VOH-VOL

280

mV

Output frequency
Output resistance
RF half clock outputs of CDR(ClkHalfP, ClkHalfN)
Output amplitude

f
R

26.75
65

GHz
Ω

VOH-VOL

280

mV

Output frequency
Output resistancefR

13.37565

GHzΩ

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300

MICRAMTM Microelectronic GmbH
Design&Engineering

single ended,peak-to-peaksingle ended

single ended,peak-to-peaksingle ended,peak-to-peakEquals input frequency

single ended,peak-to-peakHalf input frequency

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CDR with loop filter
86G CDR 1:2 Demux

Page 3Signal definitions:Definition of Voltage Levels and Amplitudes

Ground level

Operating Voltage Window(always relates to one I/O terminal (single ended))Max

OperatingVoltage
Window

arbitrary bias levels and signal amplitudes allowed

Min

Ground level
Single−ended
sig_p(normal)

VIH/VOH

VIL/VOL(VIH+VIL)/2(VOH+VOL)/2Common mode

sig_n(complement)
amplitude peak−to−peak(VOH−VOL)(VIH−VIL)
Differential
sig_p − sig_n0

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amplitude peak−to−peak
2 (VOH−VOL)
2 (VIH−VIL)

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CDR with loop filter
86G CDR 1:2 Demux

Page 4

PLL block diagram:
PLL with CDR, LF board and external VCO
Data Outputs

push−button

V1n

V2nVeeDataOut1N

100 DataInN
1012

DataOut1P

Data Input

DataOut0N

10010 DataInP
1C2upPupP50 Ω100 ClkInN
101plugRFCdRref

RG
CdVn
optional Jumper
default: not set

R2

Ro Vtune
01

1001+ Vp OP2
Vref

Ca1

Rref

Ca4Ca2

R4Ca5

Ca1
R P2

Ca3(not in shipment)

1100
00
11Ca1

R3
C2

11 1100
00 1100 1100
00 111100 1100 1100

1100
00attenuator
11Ca3

R1ext

ClkHalfP

ClkHalfN

ClkP

ClkN

CDR module

Ca1+ Vp OP1

upN

upN

Ca3

R P1
Vn

downP

downP

R2

Ca2

R1ext

downN

downN

10010 ClkInP
1V2n

V1n

11 1100
00 1100 1100
00 111100 1100 1100
DataOut0P

1100
00
11Ca3

Loop filter

Vsupp

V1pV2pClock Outputs
V1p

Vsupp

100 Vrf
101V2p0
10Vtune 10
1Vsupn

VCOVsupn

Connecting the modules:

Connect the CDR / Loop filter module and the VCO as shown in the PLL block diagram.
Please make sure to insert an attenuator if necessary to protect the clock input of the CDR. Exceeding
the maximal allowed clock input value will damage the CDR permanently. The factor of attenuation
depends on the output signal amplitude given by the VCO. Please determine first the VCO output
amplitude and the necessary attenuation before connecting the VCO to the CDR.
Plug connectors:

Following pins provided by the plug connectors shown in the picture below must be connected:
Plug
S1S2
S6S6S6S6S6S6S6S6S6S6Copyright 2003-2006
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Pin on plug
3412345678
910Connection
VeePush-button to GND
V 2p
V 2p
V 2n
V 2n
V 1p
V 1p
V 1n
V 1n
GND
GND

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CDR with loop filter
86G CDR 1:2 DemuxPage 5

All other pins should be not connected, so the plug connectors S3, S4 and S5 are not connected atall. These pins maintain connections to the CDR chip resp. loop filter, but are not necessary for PLL
operation.

Plugs and potentiometers on the loop filter board.
Cooling:

It is recommended to apply cooling plates for the system, especially for the VCO.
Power up sequence:

1. Connect CDR, loop filter and VCO to GND.
2. Set all power supplies to 0V and connect VCO, CDR and loop filter to power supply.
3. Apply the specified VCO supply voltages. (Read in the VCO specification the voltage values andthe exact rules for the VCO power up sequence.)
4. Apply V 1n, V 1p, V 2n and V 2p to the loop filter board. Take care not to exceed the 10V voltage
window for V 1p-V 1n resp. V 2p-V 2n.
5. Apply Vee to the CDR block.
6. Wait until temperature of the system settles, so that circuit parameters are constant.
Copyright 2003-2006
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Tel.: +49-234-9708-300

CDR with loop filter
86G CDR 1:2 DemuxPage 6Power down sequence:

Disconnect the power supplies in opposite direction to the power up sequence, that is:
1. Decrease CDR supply Vee to 0V.
2. Decrease loop filter supplies V 1n, V 1p, V 2n and V 2p to 0V. Take care not to exceed the 10V
voltage window for V 1p-V 1n resp. V 2p-V 2n.
3. Decrease VCO supplies to 0V. (Read in the VCO specification the exact rules for the VCO power
down sequence.)
4. Disconnect all supply leads.
Operation:

First of all the customer has to perform a measurement of the VCO alone and determine thespecific tuning voltage Vtune that gives the desired VCO output frequency. Then the output voltage
range of the loop filter has to be adjusted so that the desired Vtune is settled roughly in the middle ofit.
After applying the input signal to the data input of the CDR, press the push-button to acquire
PLL lock. If the PLL doesn’t lock, the PLL is in a condition where the loop filter cannot deliver
the VCO tuning voltage Vtune which is necessary for the required frequency. This can occur in theinitial condition of the loop filter, because the specified loop filter supply voltages V 2p and V 2n are
initial values that have to be adjusted to customer’s VCO. So the customer should perform first anadjustment of the loop filter before closing the phase locked loop.
In the following is described how the loop filter output voltage range can be adjusted.
The PLL block diagram above shows that the loop filter consists of two opamp stages. The secondstage is an amplifier of factor 0.22, which additionally produces a shift of output voltage range. Theoutput voltage range is shifted by means of adjusting the reference voltage Vref of the second opamp
stage, that is the potential on positive opamp input. Assuming an ideal output operating point of
the first loop filter stage, i.e. 0V, the output operating point of the second stage is described byVtune = 1.22 × Vref . Vtune in this equation is the middle value of the available VCO tuning voltage
range, that covers about ±600mV around this middle value. The equation shows that shifting Vref
will shift the available VCO input voltage range accordingly.
The reference voltage Vref can be adjusted in two manners:
1. The supplies V 2p and V 2n of the second loop filter stage can be shifted, always maintaining thevoltage window V 2p-V 2n = 10V. If the potentiometer P2 stays in default setting, i.e. RP 2 = Rref ,Vref is just the midpoint of the supplies:
Vref = (V 2p − V 2n)/2.
Take care not to overstep the specified absolute maximum ratings of V 2p and V 2n. If it shouldbe necessary to set V 2n > 0, please remove the protection diode which is placed on the loop filter
board between V 2n and ground.
2. The potentiometer P2 can be tuned, which gives the reference voltage:
Vref = V 2n + (V 2p − V 2n) × Rref /(Rref + RP 2 ).
Rref has the value 560Ω, and RP 2 can be tuned between 0 and 1kΩ. The default setting is
RP 2 = Rref .
Ident-No.: 13,5,12

Copyright 2003-2006
All Rights reserved

MICRAMTM Microelectronic GmbH
Design&Engineeringwww.micram.com
Tel.: +49-234-9708-300