NHUMB11/1/2 series

80 V, 100 mA PNP/PNP resistor-equipped double transistors
Rev. 1 — 23 July 2020

Product data sheet

1. General description
PNP/PNP Resistor-Equipped double Transistor (RET) family in a very small SOT363 (SC-88)
Surface-Mounted Device (SMD) plastic package.
Table 1. Product overview
R1
Type number

R2

PackagekΩkΩ

Nexperia

JEITA

NPN/NPN
complement:

NPN/PNP
complement:

NHUMB1110

10

SOT363

SC-88

NHUMH11

NHUMD3NHUMB12222

NHUMH1NHUMD2NHUMB247

47

NHUMH2NHUMD12

2. Features and benefits
•
•
•
•
•
•
•

100 mA output current capability
High breakdown voltage
Built-in resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
AEC-Q101 qualified

3. Applications••••

Digital applications
Cost saving alternative for BC856 series in digital applications
Controlling IC inputs
Switching loads

4. Quick reference data
Table 2. Quick reference data
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Min

Typ

Max

Unit

open base

-

-

-80

V

-

-

-100

mA

Per transistor
VCEO

collector-emitter voltage

IO

output current

NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors

5. Pinning information
Table 3. Pinning
Pin

SymbolDescription

1

GND1

GND (emitter) TR1

2

I1

input (base) TR1

3

O2

output (collector) TR2

4

GND2

GND (emitter) TR2

5

I2

input (base) TR2

6

O1

output (collector) TR1

Simplified outline
65

4Graphic symbol
O1

I2

R1

1

2

3

GND2

R2
TR2

TR1
R2

GND1

R1

I1

O2

aaa-019790

6. Ordering information
Table 4. Ordering information
Type number
Package
NHUMB11

Name

Description

VersionSC-88

plastic surface-mounted package; 6 leads

SOT363NHUMB1NHUMB27. Marking
Table 5. Marking
Type number

Marking code [1]

NHUMB11

2B%

NHUMB16C%

NHUMB26E%[1]% = placeholder for manufacturing site code

NHUMB11_1_2_SER

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NHUMB11/1/2 series

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80 V, 100 mA PNP/PNP resistor-equipped double transistors

8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Min

Max

Unit

VCBO

collector-base voltage

open emitter

-

-80

V

VCEO

collector-emitter voltage

open base

-

-80

V

VEBO

emitter-base voltage

open collector

-

-10

V

VI

input voltage
NHUMB11

-40

+10

V

NHUMB1

-60

+10

V

NHUMB2

-80

+10

V

Per transistor

IO

output current

-

-100

mA

Ptot

total power dissipation

Tamb ≤ 25 °C

[1]

-

235

mW

Ptot

total power dissipation

Tamb ≤ 25 °C

[1]

-

350

mW

Tj

junction temperature

-

150

°C

Tamb

ambient temperature

-55

150

°C

Tstg

storage temperature

-65

150

°C

Per device[1]

Device mounted on an FR4 Printed-Circuit-Board (PCB); single-sided copper; tin-plated and standard footprint.
aaa-031893

400
Ptot
(mW)
300

200

100

0
-75

-25

25

75

125
175
Tamb (°C)

FR4 PCB, single-sided copper, standard footprint
Fig. 1.

Per device: Power derating curve SOT363 (SC-88)

NHUMB11_1_2_SER

Product data sheet

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80 V, 100 mA PNP/PNP resistor-equipped double transistors

9. Thermal characteristics
Table 7. Thermal characteristics
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Min

Typ

Max

Unit

-

-

532

K/W

-

-

150

K/W

-

-

358

K/W

Per transistor
Rth(j-a)thermal resistance from junction to ambient

Rth(j-sp)

thermal resistance from junction to solder point

in free air[1]

Per device
Rth(j-a)[1]

thermal resistance from junction to ambientin free air[1]

Device mounted on an FR4 Printed-Circuit-Board (PCB); single-sided copper; tin-plated and standard footprint.
aaa-031894

103
duty cycle = 1

Zth(j-a)
(K/W)

0.75

102

0.33

0.50
0.20

0.10
0.05
10

0.02

0.01

0

1
10-5

10-4

10-3

10-2

10-1

1

10

102

tp (s)

103

FR4 PCB, single-sided copper, tin-plated and standard footprint
Fig. 2.

Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values

NHUMB11_1_2_SER

Product data sheet

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NHUMB11/1/2 series

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80 V, 100 mA PNP/PNP resistor-equipped double transistors

10. Characteristics
Table 8. Characteristics
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Min

Typ

Max

Unit

V(BR)CBO

collector-basebreakdown voltage

IC = -100 µA; IE = 0 A

-80

-

-

V

V(BR)CEOcollector-emitter
breakdown voltage

IC = -2 mA; IB = 0 A

-80

-

-

V

ICBO

collector-base cut-off
current

VCB = -80 V; IE = 0 A

-

-

-100

nA

ICEO

collector-emitter cut-off VCE = -60 V; IB = 0 A
current
VCE = -60 V; IB = 0 A; Tj = 150 °C

-

-

-100

nA

-

-

-5

µA

-

-

-600

µA

NHUMB1

-

-

-270

µA

NHUMB2

-

-

-130

µA

50

-

-

70

-

-

Per transistor

IEBO

emitter-base cut-off current
NHUMB11hFE

VEB = -7 V; IC = 0 A

DC current gain
NHUMB11

VCE = -5 V; IC = -10 mA

NHUMB1

100--

VCEsatNHUMB2collector-emittersaturation voltage

IC = -10 mA; IB = -0.5 mA

-

-

-100

mV

VI(off)off-state input voltage

VCE = -5 V ; IC = -100 µA

-

-1.15

-0.8

V

VI(on)

on-state input voltage
VCE = -0.3 V ; IC = -10 mA

-2.5

-1.8

-

V

NHUMB1

-3

-2.3

-

V

NHUMB2

-5

-3.3

-

V

NHUMB11

7

10

13

kΩ

NHUMB1

15.4

22

28.6

kΩ

NHUMB2

33

47

61

kΩ

[1]

0.8

1

1.2

[2]

-

150

-

MHz

-

-

3

pF

NHUMB11R1[1]bias resistor 1 (input)

R2/R1

bias resistor ratio

fTtransition frequency

VCE = -5 V; IC = -10 mA; f = 100 MHz

Cc

collector capacitance

VCB = -10 V; IE = ie = 0 A; f = 1 MHz

[1]
[2]

See section "Test information" for resistor calculation and test conditions
Characteristics of built-in transistor

NHUMB11_1_2_SER

Product data sheet

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NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors
aaa-031534

103
hFE

102

(1)

-0.10

(2)

IC
(A)

(3)

aaa-031535

IB = -0.70 mA-0.56 mA

-0.08

-0.35 mA
-0.28 mA

-0.04
1
-10-1

-1

-10

IC (mA)-102

Fig. 3.

-0.21 mA

-0.02

VCE = -5 V
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C

0-0.49 mA

-0.42 mA

-0.06

10

-0.63 mA

-0.14 mA
-0.07 mA
0

-1

-2

-3

-4

VCE (V)-5

Tamb = 25 °C

NHUMB11: DC current gain as a function ofcollector current; typical values

Fig. 4.

aaa-031536-102

NHUMB11: Collector current as a function ofcollector-emitter voltage; typical values
aaa-031537-10VI(on)(V)

VI(off)
(V)

-10

(1)

-1
(1)

-1

(2)
(3)

(2)
(3)

-10-1
-10-1

-1

-10

IC (mA)

-102

-10-1
-10-1

VCE = -0.3 V(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C
Fig. 5.

Product data sheet-10

IC (mA)-102

VCE = -5 V
(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C

NHUMB11: On-state input voltage as a functionof collector current; typical values

NHUMB11_1_2_SER-1Fig. 6.

NHUMB11: Off-state input voltage as a functionof collector current; typical values

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NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors
aaa-031538-1

aaa-031539

7

VCEsat
(V)

Cc
(pF)

-10-1

5

(1)
(2)
(3)

3
-10-2

Fig. 7.

-1-10

IC (mA)-102

IC/IB = 20
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C

1

NHUMB11: Collector-emitter saturation voltage Fig. 8.
as a function of collector current; typical values

NHUMB11: Collector capacitance as a functionof collector-base voltage; typical values

0

-20

-40

-60

VCB (V)-80

f = 1 MHz
Tamb = 25 °C

aaa-031540

103
hFE

(1)

102

aaa-031541-0.100(2)

IB = -0.70 mA

IC
(A)

(3)

-0.56 mA

-0.075-0.63 mA
-0.49 mA

-0.42 mA
-0.35 mA

10-0.050-0.28 mA
-0.21 mA

1
-10-1

-1

-10

IC (mA)-102-0.07 mA

VCE = -5 V
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C
Fig. 9.

0

Product data sheet

0

-1

-2

-3

-4

VCE (V)-5

Tamb = 25 °C

NHUMB1: DC current gain as a function ofcollector current; typical values

NHUMB11_1_2_SER-0.14 mA

-0.025

Fig. 10. NHUMB1: Collector current as a function ofcollector-emitter voltage; typical values

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NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors
aaa-031542-102

aaa-031543-10

VI(on)(V)(1)

VI(off)
(V)

(2)

-10
(3)

-1
(1)

-1

(2)
(3)

-10-1
-10-1

-1

-10

IC (mA)

-102

-10-1
-10-1

VCE = -0.3 V(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C

-1

-10

IC (mA)-102

VCE = -5 V
(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C

Fig. 11. NHUMB1: On-state input voltage as a functionof collector current; typical values

Fig. 12. NHUMB1: Off-state input voltage as a functionof collector current; typical values

aaa-031544-1

aaa-031545

3.5

VCEsat
(V)

Cc
(pF)
3.0

-10-1

(1)

2.5

(2)
(3)

2.0

-10-2
-10-1

1.5
-1

IC/IB = 20
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C-10

IC (mA)

-102
1.0

0

-20

-40

-60

VCB (V)-80

f = 1 MHz
Tamb = 25 °C

Fig. 13. NHUMB1: Collector-emitter saturation voltage
Fig. 14. NHUMB1: Collector capacitance as a function of
as a function of collector current; typical values
collector-base voltage; typical values

NHUMB11_1_2_SER

Product data sheet

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NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors
aaa-031546

103
hFE

(1)

102

(2)

-0.10

(3)

IC
(A)

aaa-031547

IB = -0.60 mA-0.54 mA

-0.08

-0.48 mA
-0.36 mA

-0.06

10

-0.42 mA
-0.30 mA

-0.24 mA
-0.04
1
-10-1

-0.18 mA
-0.12 mA

-1

-10

IC (mA)-102

VCE = -5 V
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C-0.02-0.06 mA
0

0

-1

-2

-3

-4

VCE (V)-5

Tamb = 25 °C

Fig. 15. NHUMB2: DC current gain as a function ofcollector current; typical values
aaa-031548-102

Fig. 16. NHUMB2: Collector current as a function ofcollector-emitter voltage; typical values
aaa-031549-10

VI(on)(V)

VI(off)
(V)

-10

(1)

-1
(1)

-1

(2)
(3)

(2)
(3)

-10-1
-10-1

-1

-10

IC (mA)-102

VCE = -0.3 V(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C

Product data sheet

-1

-10

IC (mA)-102

VCE = -5 V
(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C

Fig. 17. NHUMB2: On-state input voltage as a functionof collector current; typical values

NHUMB11_1_2_SER

-10-1
-10-1

Fig. 18. NHUMB2: Off-state input voltage as a functionof collector current; typical values

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NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors
aaa-031550-1

aaa-031551

12
VCEsat
(V)

Cc
(pF)
8

-10-1

(1)
(2)
(3)

4

-10-2
-10-1

-1

-10

IC (mA)-102

0

IC/IB = 20
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C

0

-20

-40

-60

VCB (V)-80

f = 1 MHz
Tamb = 25 °C

Fig. 19. NHUMB2: Collector-emitter saturation voltage
as a function of collector current; typical values

Fig. 20. NHUMB2: Collector capacitance as a function ofcollector-base voltage; typical values of built-in
transistor
aaa-031554

103

fT
(MHz)

102

10
-10-1

-1

-10

IC (mA)-102

f = 100 MHz
VCE = -5 V
Tamb = 25 °C
Fig. 21. Transition frequency as a function of collector current; typical values of built-in transistor

NHUMB11_1_2_SER

Product data sheet

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NHUMB11/1/2 series

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80 V, 100 mA PNP/PNP resistor-equipped double transistors

11. Test information
Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC)
standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use inautomotive applications.

Resistor calculation•

Calculation of bias resistor 1 (R1)•

Calculation of bias resistor ratio (R2/R1)n.c.

II1; II2

R1

II3; II4
R2

GND
aaa-020083

Fig. 22. PNP transistor: Resistor test circuit

Resistor test conditions
Table 9. Resistor test conditions
Type number

R1 (kΩ)R2 (kΩ)

Test conditions
II1

II2

II3

II4

Per transistor
NHUMB111010-800 μA-1.1 mA

350 μA

450 μANHUMB12222-550 μA-750 μA

150 μA

230 μANHUMB247

47-250 μA-350 μA

55 μA

105 μANHUMB11_1_2_SER

Product data sheet

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NHUMB11/1/2 series

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80 V, 100 mA PNP/PNP resistor-equipped double transistors

12. Package outline
2.2
1.8
6

2.2 1.35
2.0 1.15

1.1
0.8
5

4

2

3

0.45
0.15

pin 1
index

1

0.3
0.2

0.65
1.3

0.25
0.10

Dimensions in mm

14-10-03

Fig. 23. Package outline SOT363 (SC-88)

13. Soldering
2.65

solder lands
2.35 1.5

0.4 (2×)

0.6 0.5(4×) (4×)

solder resist
solder paste

0.5
(4×)

0.6
(2×)

occupied area

0.6
(4×)

Dimensions in mm
1.8

sot363_fr

Fig. 24. Reflow soldering footprint for SOT363 (SC-88)

1.5
solder lands
0.3 2.5

4.5

1.5

solder resist
occupied area
Dimensions in mm

1.3

preferred transport
direction during soldering

1.3
2.45
5.3

sot363_fw

Fig. 25. Wave soldering footprint for SOT363 (SC-88)

NHUMB11_1_2_SER

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NHUMB11/1/2 series

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80 V, 100 mA PNP/PNP resistor-equipped double transistors

14. Revision history
Table 10. Revision history
Data sheet ID

Release date Data sheet status

ChangenoticeSupersedes

NHUMB11_1_2_SER v.1

20200723--

NHUMB11_1_2_SER

Product data sheet

Product data sheet

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NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death orsevere property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment orapplications and therefore such inclusion and/or use is at the customer's own
risk.

15. Legal information
Data sheet status
Document status[1][2]

Product
status [3]Definition

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.

Objective [short]data sheet

Development

This document contains data fromthe objective specification for
product development.

Preliminary [short]data sheet

Qualification

This document contains data fromthe preliminary specification.

Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.

Product [short]data sheet

Production

This document contains the productspecification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating orcompleting a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.

Definitions
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full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
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and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
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the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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NHUMB11_1_2_SER

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 23 July 2020

© Nexperia B.V. 2020. All rights reserved

14 / 15

NHUMB11/1/2 series

Nexperia

80 V, 100 mA PNP/PNP resistor-equipped double transistors

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking.......................................................................... 2
8. Limiting values............................................................. 3
9. Thermal characteristics............................................... 4
10. Characteristics............................................................ 5
11. Test information........................................................ 11
12. Package outline........................................................ 12
13. Soldering................................................................... 12
14. Revision history........................................................13
15. Legal information......................................................14© Nexperia B.V. 2020. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 23 July 2020

NHUMB11_1_2_SER

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 23 July 2020

© Nexperia B.V. 2020. All rights reserved

15 / 15