Thin-film lateral phase-change memory driven by poly-Si MOS transistor
enabling both low cost and high-programming gigabyte-per-second throughput
Y. Sasago, M. Kinoshita, H. Minemura, Y. Anzai, M. Tai, K. Kurotsuchi,
S. Morita, T. Takahashi, T. Takahama, T. Morimoto, T. Mine, A. Shima, and T. Kobayashi
Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-Koigakubo, Kokubunji, Tokyo 185-8601, JAPAN
Tel: +81-42-323-1111; Fax: +81-42-327-7773; E-mail: yoshitaka.sasago.tx@hitachi.com
Abstract
A phase-change memory (PCM) driven by
poly-Si MOS transistors was fabricated. The thinphase-change-material layer deposited directly on
the channel silicon layer in the PCM enables
low-current reset operation (45 μA) compared tothe conventional memory structure. With the aidof this low reset current, this memory-cell configuration enables both a poly-Si MOS-driven stackable memory array and large degree pr ogramming
parallelization. A contactless simple cell structure
makes it possible to reduce the cell size to 4F 2 andthe number of process steps. Low cost and gig abyte-per-second programming throughput are thus
made possible by this stackable phase-change
memory.
Key words: thin-film phase-change memory,poly-Si MOS, stackable
Introduction
Flash memory and phase-change-memory(PCM) technology have been studied extensively[1 – 5]. Some of them can be used in fabricating a
stacked-layered memory with ultra-high density
suitable for solid-state disks or storage-class
memory. Recent results including some on planar
flash memory [6] are summarized in Table 1. Flashmemory realizes high density according to thestate-of-the-art “2x nm” design rule, but its
high-voltage operation makes it difficult to r educecell size further. Three-dimensional flash memory,
such as BiCS flash [1], faces the same issue. PCM
is the most promising cand idate because of its low
operating voltage, scalability, and high progra mming speed. However, so far, the large reset cu rrent of conventional PCM requires a large selection device such as a transistor or diode on thesilicon substrate and thus pr events reduction ofPCM cell size. In addition, the large reset current
limits the degree of parallelization. In this work,
we fabricated a PCM with a poly-Si MOS transistor and a thin-film phase-change layer directly
deposited on a channel poly-Si. In this PCM, thesectional area perpendicular to the current path in
the phase-change layer can be reduced by decreasing film thickness irrespectively of the photo-lithographic limitation. Reset current was thus

reduced. As a result, the PCM can be driven by apoly-Si selection MOS transistor. Since it is notnecessary to utilize the selection device on a sil icon substrate for each memory cell, the PCM canbe stacked to achieve ultra high density. A contactless, simple memory structure enables us toreduce cell size and number of process steps. The
low reset current of 45 μA and the reset time of 30
ns can achieve gigabyte-per-second programming
throughput.

Table 1. Memory technology
This work Ref. [6]MemoryPCM
poly-Si
MOS

Ref. [1]Flash memory
2D bulk poly-Si
MOS
MOS

Ref. [5]Ref. [4]PCM
OTS
Poly-Si
diode

Scalability
Reset current 45 μA

140 μA

StackableStructure and operation
Figure 1 shows the structure and operation
principle of the developed PCM. The gate oxide,channel poly-Si, and the phase-change material
are deposited on the poly-Si gates. The poly-Sitransistors are connected serially. A channel
poly-Si layer and a phase-change layer are connected in the lateral direction and separated in the
direction perpendicular to Fig. 1. In the set/reset
operations, a negative off-voltage is applied to thegate at the selected cell, and a positive on -voltage
is applied to the gates at the unselected cells.
When the set/reset pulse voltage is a pplied to thedrain, the current flows through the phase -changefilm at the selected cell, and resistive switchingoccurs. The results of an electro -thermal simulation of the reset operation are also shown in Fig. 1.
The temperature at the phase-change layer at theselected cell is increased by Joule heating; thus, areset operation is produced. In the same way, byapplying a voltage suitable for the reading oper ation to the drain, the resistance of thephase-change film at the selected cell can be d etermined.

(a)

(b)

(a)

Interlayer dielectric
gate

SiO2
Phase-change layer

Gateoxide

SiO2

Channel SiGate

GateGate(c)(d)Phase-change film

SiO2
Poly-Si channel

Drain(Vd)

Source(0 V)

gategate
SiO2

Gate (Vg)

100 nmFigure 2. Process flow of lateral PCM array(b)Melting region

Poly-Si channel

Gate

GateGate

Electro-thermal simulation at reset current
Set (crystal) ⇔ Reset (amorphous)
Figure 1. Device structure and operation of the PCM

Fabrication process flow
The fabrication process flow of the memory a rray is shown in Fig. 2. After a silicon film is d eposited on SiO 2 layer, the film is patterned. Thestripe line/space pattern of the gate poly -Si isformed as shown in Fig. 2(a). Next, silicon oxide
is deposited (Fig. 2(b)) and planarized by CMP(Fig. 2(c)). Next, the gate oxide and channel sil icon layers were deposited. A thin film ofphase-change material is then deposited on thechannel poly-Si. Because a low-thermal-budget
process is used for poly-Si MOS, the thermal
budget for the crystallization and dopant activ ation of poly-Si does not affect the phase -change
film in a stacking memory array. The cha nnel
poly-Si and phase-change material are patternedand, finally, the contacts for the gates andsource/drain at both sides of the lateral serial cells
are formed (Fig. 2(d)).

Poly-Si MOS transistor
On-current of the poly-Si MOS transistor issignificantly affected by the unevenness of thegate oxide/channel interface. The simulated resultsfor on-current are shown in Fig. 3. The recess ofthe gate or interlayer dielectric should be less than
5 nm, which was achieved in the device, as shownin Fig. 2. The on-current is also strongly dependent on gate-space distance. Figure 4 shows
gate-space-distance dependence of the on-currentof the poly-Si MOS. The on-current increases withdesign-rule scaling (i.e., decreasing gate -spacedistance). According to the specification of thedevice, gate-space distance should be less than 50
nm.
10Flatsurface

9Si channel
gate

8On current (arb. unit)

Phase-change material

76
SiO2 recess

543 Gate recess
2100

123

4

56

7

8

9Unevenness (nm)Figure 3. Effect of unevenness on Ion of poly-SiMOS transistor

10On current (arb. unit)

101
simulation
Gate-space distance100

The reset current of the device was 45 μA with
30-ns pulse width, as shown in Fig. 6, which ismuch lower than our previous result (Ref. [4] inTable 1). This low-current reset current isachieved by reducing the cross sectional area ofcurrent path with using thin film phase -change
layer. Under the assumption that the chip current
is 10 mA, this result corresponds to 1 -GB/s programming throughput.

10-1 allowed
103

050

100

150

200

Gate-space distance (nm)Figure 4. Gate-space dependence of poly-Si-MOStransistor on current

Characteristics of phase change memory
Figure 5 shows the current-voltage characteristics of the set/reset state of the cell. Each memory
cell consists of a parallel connection of the tra nsistor and the phase-change device; therefore, thedrain current is the sum of their currents. By a pplying a negative voltage to the gate, the transi stor
current is reduced, and the current through thephase-change film is detectable. The resistanceratio between the set and reset states is a t least ten.
It was found that the high -resistance reset state
was switched to low-resistance set state by a nnealing at 200°C for 3 minutes, indicating that theswitching mechanism of the cell is a crystal-amorphous phase change.
Off state

Poly-Si MOS

On state

Pulse width: 30 ns

101

Drain current (arb. unit)

Set (crystal)
102

Reset (amorphous)
Poly-Si MOS
0510Gate Voltage (V)50

Cycle endurance up to 100 times with the resistance ratio of over 10 was confirmed as shownin Fig. 7. The breakdown of the PCM was not observed.
103
Reset (amorphous)102

Set (crystal)

0204060
80
Number of cycles

100Figure 7. Endurance characteristics

After annealing-5203040Reset current (μA)

Figure 6. Reset characteristics

1001001010110310145 μA

102

100 0

Resistance (arb.unit)

10-2

Resistance (arb.unit)

experiment

15

Figure 5. I-V characteristics of the reading operation

The number of cycles is considered to be a ffected by the stability of the interface between thephase-change layer and channel silicon layer. Accordingly, we checked the stability at the inte rface
by measuring interdiffusion. We observed no diffusion of silicon or GeSbTe at the interface b etween the poly-Si channel and GeSbTe after
10-minute annealing at 730℃ as shown in Fig. 8.
The temperature of the phase-change layer reachesthe melting point, that is, 630 ℃ , during the reset
operation. This result shows that the interface between the silicon and the phase-change layer hasenough stability for cycle endurance of over 10 6 .

Phase-change layer
Channel poly-Si

Concentration (cm -3)

1023

Silicon

Ge

1021

Gate

SbAfter annealing
1019 730℃, 10 min.
1017
10Te

Gate

PCM array

Gate

Thermalbudget

SiO2
Phase-change layer
Channel poly-Si
Gate oxideGateGatePhase-changematerial

PCM array
Gate SiO

215

1.15

1.2

1.25
depth (μm)

1.3

1.35
Figure 10. Stacking of PCM array

Figure 8. Diffusion of Si and GeSbTe

The retention characteristics of the reset state
were also measured as shown in Fig. 9 and areclearly similar to those of conventional PCM d evices [2]. We assumed that the retention time isdetermined by the characteristics of thephase-change material and is independent of thedevice structure of the memory cell. In otherwords, the developed cell structure itself does notaffect the retention characteristics.
10Noirmalized Resistance

110°C

10.1
100

101102
103
104
Time (s)Figure 9. Retention characteristics

105The PCM device we developed utilizes apoly-Si MOS transistor, that is, not a silicon su bstrate device, as a selection device; therefore,
stacking of the memory array is possible. Of
course, a low-thermal-budget process is necessary
for fabricating poly-Si MOS transistor so as not todeteriorate the underlying phase -change layer. The
stacking memory array makes it possible to realize
an ultra-low-bit-cost PCM device suitable forstorage application.

Summary
A stackable serially connected thin-film lateral-phase-change memory (PCM) with a poly-Si
MOS transistor was fabricated. This PCM device
achieves both low bit cost and high programming
throughput and successfully performs set/reset
operation.
References[1] R. Katsumata et al., Symp. on VLSI Tech., pp.
136–137 (2009).
[2] I. S. Kim et al., Symp. on VLSI Tech., pp. 203–204(2010).
[3] G. Servalli, IEDM Tech. Dig., pp. 113–116 (2009).
[4] Y. Sasago et al., Symp. on VLSI Tech., pp. 24 –25(2009).
[5] DerChang Kau et al., IEDM Tech. Dig., pp.
617–620 (2009).
[6] Choong-Ho Lee et al., IEDM Tech. Dig., pp.
98–101 (2010).