White Paper

An Introduction to:

Non-Volatile
Memory© Swissbit AG 2024 – All rights reserved.

1. Abstract
NAND flash is a very cost competitive non-volatilememory technology. With the introduction of
3D-NAND, NAND based storage media have become
serious contenders to replace magnetic rotatingstorage media in terms of system cost.
However, there are still several challenges to be met,
as cost-efficient NAND flashes with high densities
based on MLC, TLC or even QLC technologies are
increasingly prone to causing failures during field
operation, especially in harsh environments.
Continuously decreasing reliability and endurance incomparison to SLC flash is the result.
Endurance, lifetime and reliability of NAND flash
based storage media depends very much on thequality of the flash memory controller and its
firmware, which manages the intrinsic physicalproperties and weaknesses.

Table of Contents
1. Abstract
2. Introduction
3. NAND Flash Memory
4. NAND Flash Structure
5. SLC, MLC, TLC & QLC
6. NAND Flash Weaknesses
7. 3D NAND

2. Introduction
This paper provides an overview of NAND flash
technology, which is the most widely used storage
technology in today’s non-volatile memory basedstorage systems.
NAND flash memory is explained in detail, startingwith the transistor, and then covering its structureand functionality. The handling of program, readand erase processes is considered with regard todifferent technologies, including 3D flash. The
shortcomings and challenges of NAND flash are also
explained, in conjunction with the solutions
necessary to overcome them.

23. NAND Flash Memory
NAND flash is based on standard transistors withadditional parts to store data instead of only
switching voltage.
Therefore this paper starts with an introduction totransistors – the most important components in thesemiconductor industry.

If a positive voltage is applied between drain andsource, a current can flow between the twoterminals. However, when V < Vth no current canflow, even if a positive voltage is applied between
drain and source. The transistor therefore acts as anelectrical switch that can be turned on and off
depending on the voltage.

Transistor
A MOSFET transistor (Metal Oxide Semiconductor Field
Effect transistor) can be seen as an electrical switch
in which the current flow between two terminals(called source and drain) is controlled by a third
terminal (gate).
A MOSFET transistor can be structured in two different
ways: a p-type substrate and n-type source anddrain regions, or an n-type substrate and p-typesource and drain regions. The first type is ann-channel transistor, while the second type is ap-channel transistor. A process technology in which
the two types of transistors are present is CMOS
(Complementary Metal Oxide Transistor).

Figure 2: MOSFET where voltage is applied to the gate > threshold. Transistor is switched on and current can flow between
source and drain when Vds > 0V

Floating Gate and NAND Flash Cell
A NAND flash cell is an n-channel MOSFET with anadditional programming layer inserted between thecontrol gate (CG) and the silicon substrate. This layer
is electrically isolated from all the other terminals of
the cell and is called the Floating Gate (FG).

Figure 1: n-type MOSFET transistor

An n-type region is an area of the silicon that has asurplus of electrons, and a p-type region has a lackof electrons. This can be achieved by injecting
elements with a surplus of electrons or inducing alack of them using elements such as Arsenic or Boronin a process called “doping implantation”.

Figure 3: NAND flash cell with floating gate

For an n-channel transistor to allow current to flow
between drain and source, a positive voltage V > Vthmust be applied to the gate. Vth is the “thresholdvoltage” of the transistor. When V > Vth is applied,the electric field generated attracts the electrons
toward the gate terminal and a conductive channel
is formed between source and drain.

3

Programming a NAND Flash bit

Reading a NAND Flash bit

By applying a high voltage to the CG (about +20V)
while source and drain are grounded, the electrons
in the channel can gain enough energy to overcome
the oxide barrier and move from the channel into
the floating gate.

Whenever electric charge is stored in the floating
gate, the behavior of the NAND cell is influenced. In
fact, the charge trapped in the floating gate during
the programming operation determines an increasein the threshold voltage, whose entity depends on
the number of electrons present in the floatinggate. This shift in Vth can be converted into a bit of
information.

This is the so-called Fowler–Nordheim tunneling
effect of trapping electrons in the floating gate is
the programming operation of a flash device(sometimes called the “write” operation). Since thefloating gate is electrically isolated it can store
electric charge permanently even if the power isremoved from the flash device.

Figure 5: Charactreristic of an erased and programmed bit

Figure 4: When programming a cell electrons move from thechannel to the FG

Applying voltage Vgs = 0V between the control gate
and source has different effects on the two bits. In
the case of the programmed bit no current Ids canflow between source and drain because Vgs < Vth_program, while for the erased bit a current can flow
because Vgs > Vth_erase. The presence or absenceof current Ids is then converted into a bit of
information.
Conventionally:
Bit = 0 for the programmed bit
Bit = 1 for the erased bit

Erasing a NAND Flash bit
The erase operation extracts the electrons trapped in
the floating gate and brings the threshold voltage ofa programmed cell back below zero (Vth_erase <0V). As a result, a bit flips from 0 to 1. To enable this,a high voltage (about +20V) has to be applied to thesubstrate of the cell while the control gate isgrounded. The erase operation also exploits the
Fowler–Nordheim tunneling effect.

Figure 6: Erase operation of a cell

4

4. NAND Flash Structure

Page and Block

NAND cells are organized hierarchically, as shown
below.

Strings are organized in blocks, in which each stringis connected to a separate line called a bitline (BL<i>in Fig. 9). All cells with the same position in thestring are connected through the control gates by aline called wordline (WL<j> in Fig. 9). Depending on
the flash device, the cells on the same wordline canbe organized in one or two pages.
A page is the minimum selectable array area to beread and programmed. A block is the minimum
selectable area in the erase operation.
Typical page size is between 2KB and 16KB.

Figure 7: Physical structure of a NAND flash cell

Block size=(# of pages in a block)*(page size)

StringA string is a series connection of NAND cells in which
the source of one cell is connected to the drain of
the next one. Depending on the NAND technology astring typically consists of different amounts of
NAND cells (see Fig. 8). Each string has two selecttransistors – on the top and at the bottom, whose
gates are connected to DSL and SSL lines – that allow
the selection of the desired strings during different
NAND operations (read, program, erase).

Figure 9: NAND flash block

Figure 8: NAND flash string

5

PlanePage program operation

A plane contains a certain number of blocks that areconnected via the same Bit lines. Blocks have
independent word lines to access all pages forindividual read or write operations. All blocks andtherefore all cells on one plane share the same
substrate (see Fig. 10).

To write a page into a block the data received
through the flash interface is transferred into thepage buffer. The page buffer transfers the data to be
programmed onto the bit lines, while the row
decoder selects the block and the word line
addressed by the flash controller (Fig. 11). In all otherblocks word lines and select transistors are deselected. The selected word line is biased to around20V. Only the cells on the word line whose (Bit Line)bit is on 0 (i.e. gnd) experience an electric field sufficient to be programmed. However, the cells with 1(i.e. Vcc) on the bit line do not get programmed. The
unselected word lines in the selected block arebiased to a Vpass voltage (~10V) that minimizes the
program disturbance on all unselected cells of theblock.

Figure 10: NAND flash plane with PBs and row decoder

Each plane has a dedicated row decoder, which isconnected through DSL, SSL and word lines to eachblock in the plane. The row decoder selects a wordline depending on the physical address information
received from the flash controller. Each plane also
has a dedicated page buffer, which is the dedicatedcircuitry to read/program data from/to the array.

Figure 11: NAND flash plane program (only one page per WL)

Flash dieA flash die consists of one or more planes, and the
peripheral circuitry that is needed to perform all theread/write/erase operations.
Typically, in dies with multiple planes it is possible
to perform read and write operations simultaneously
on different planes, which increases performance.

6

Block Erase Operation

Page Read Operation

The erase operation can only be performed block byblock.

The word line of the page to be read is applied witha voltage of 0V and the other unselected word lines
belonging to the same block are biased at Vpass (Fig.
12). Vpass is a voltage that has to be higher than theVth of the programmed bits of the string (typicallyVpass is around 5V) so that they behave like passtransistors and do not affect the read operation of
the selected word line. All bit lines are precharged to~1V by the page buffer and then left floating. Only
the erased bit with its bias conditions can draw
current and discharge the bit lines while bit lines ofprogrammed cells remain charged (Fig. 13). The page
buffer samples the status of the bit lines after acertain delay, generating a 0 for the programmed
bits and a 1 for the erased ones.

To erase a selected block all the word lines in theblock need to be biased at 0V and the substrate at
20V. The substrate of a block in one plane is equal to
all the other blocks of that plane (see Fig. 11) andtherefore the word lines of the unselected blocks
that should not be erased and are left floating.

Figure 12: NAND flash page read bias

Figure 13: NAND flash page read time diagram7

5. SLC, MLC, TLC, QLC
By controlling the quantity of charge trapped in the
floating gate of the cell it is possible to accurately
control its threshold level and store more than one
bit of information in a cell.
Based on this characteristic, different families of
NAND flash devices can be defined.

SLC (Single Level Cell)
SLC flash can store one bit of information in eachcell. A negative threshold voltage corresponds to a 1,
and a positive threshold voltage corresponds to a 0.
SLC memory has the advantage of faster write
speeds, lower power consumption and higher cell
endurance. Programming is faster, because with
only one possible threshold state for the programmed
bit (Vth > 0V) less accuracy and consequently lesstime is needed to control the final threshold level.
However, because SLC memory stores only one bit
per cell, the cost per bit is high. Due to faster transfer
speeds and expected higher endurance, SLC flash
technology is used in high-performance memory
cards. SLC is now used for applications wherereliability, endurance and speed are essential.
Examples are applications in the fields of industrial
automation, networking and robotics.

Programming MLC (Multi Level Cell)
In order to write two bits of information to one cell,four different threshold levels should be achieved.
The two bits per cell belong to two different pages(i.e. two different physical addresses) called the“lower” and “upper” page (or the “fast” and “slow”page). As a first step, the lower page is programmed
in an SLC-like mode, as only one bit per cell ispresent (see Fig. 14). In step two (see Fig. 15), theupper page is programmed, and the bit of the upper
page combined with the current lower bit status
defines the final threshold level target of each cell(see Fig. 16).

Figure 14:Programming the lower page

MLC (Multi Level Cell)
MLC can store two bits of data, which means thatfour different Vth states are possible. The erased
state has, like to SLC, a negative Vth, and the otherthree states have a different positive Vth level. The
advantage of MLC is that it stores more data per celland is therefore much cheaper than SLC. Conversely,
MLC has a lower write performance because thedifferences between the thresholds are lower andtherefore more accuracy is required to program thecells. Furthermore, the bit error rate (i.e. bits thatfail to read correctly) is higher and endurance islower – the smaller threshold distances make it
more likely that some bits will end up in the adjacentstate. To solve this issue a higher error correction
capability is required for MLC devices.

Figure 15:Programming the upper page

8

TLC (Triple Level Cell)
TLC can store three bits per cell, resulting in eight
different states and eight different Vth levels. The
resulting higher error rate requires advanced error
correction algorithms. TLC uses the ISPP technique,but with finer Vpulse steps to achieve greater
accuracy. The primary benefit of TLC is its lower cost
per bit of storage due to the higher data density.
With improvement in technology, todays industrial
grade TLC flash shows the same endurance andreliability like the outdated MLC flash. It is therefore
currently the standard for applications in theautomotive industry.

QLC (Quad Level Cell)
In a QLC NAND four bits can be stored in each cell,which corresponds to 16 different threshold levels.
With its limitations regarding endurance andtemperature range, QLC is currently only suitable for
consumer devices or read extensive applications intemperature controlled environments.

Figure 16: Lower and upper page programming states

In order to achieve the tight control of the thresholdvoltage of the cells required by the MLC operation,an Incremental Step Pulse Programming (ISPP)
technique is used. With ISPP at each programming
pulse the voltage on the control gate is increased bya ΔVpulse, which causes an equivalent incremental
increase of the threshold voltage of the cell ΔVth.
This means that the cells are exposed to evenly
increasing voltage pulses (ΔVpulse), and after eachincreased pulse the state of the cell is verified. All
the cells that have reached the desired Vth statestop getting additional programming pulses. This
process continues until all cells have reached theirtarget Vth state. SLC also uses the ISPP technique,but the ΔVpulse of each pulse is much larger than thepulses for MLC because the required control of the
program distribution width can be less accurate.
This results in faster programming operation.

Figure 17: SLC, MLC and TLC Vth and their different states

pSLC (pseudo Single Level Cell)A pSLC NAND is a standard MLC/ TLC QLC NAND where
only one out of two bits is used. In other words, pSLC
is a particular usage model of an MLC/ TLC/ QLC flash.
By storing only one bit per cell, endurance, reliability
and data retention are increased. The parametersdescribed are significantly better if compared tohigher density flashes and are close to true SLC while
the costs are significatly lower.

96. NAND Flash Weaknesses
The endurance and reliability of NAND flash devices
are impacted by several different intrinsic effects
that are becoming more critical as the technology
nodes shrink. The following provides a brief overview
of the main issues.

Program/ Erase (P/E) Cycles)
A NAND flash cell can sustain only a limited numberof program and erase cycles. The high voltages thatare required during program and erase operations
cause a small amount of damage to the cell withevery cycle. As a consequence, the cell becomes
harder to erase. Furthermore, the isolation
characteristics of the two oxides that isolate thefloating gate worsen. This reduces the capability of
the cell to retain the electrons that are stored in the
floating gate, resulting in a degradation of the dataretention performance. When the maximum numberof P/E cycles allowed by the specification is reached,
the flash is said to have reached End of Life (EOL).

Program Disturb
Program disturb takes place during page
programming, and causes some charge to becollected in the FGs of cells that should not be
programmed. The effect is to soft-program bits, i.e.
to increase the threshold of erased bits for SLC
devices or those in the lower programmed
distributions for MLC and TLC. If the amount of the
disturb is sufficient to move a bit beyond the readreference voltage (see Fig. 18 for an SLC read), thatbit will cause a bit read failure in a next-page read
operation.

Data Retention
Data retention is the ability of a cell to retain thestored information (i.e. the electrons in the FG)
across time – by definition it refers only to a
programmed bit. A leakage of electrons from thefloating gate causes a shift toward the erase state of
the programmed bits. If the threshold shift amountis so high that a bit crosses the read reference
voltage, that bit will fail a subsequent read
operation. Data retention performance can besignificantly reduced by read/write or hightemperatures. Data retention performance of MLC
and TLC devices is considerably lower than SLC.

Figure 18: Program disturb effect in SLC NAND Flash

Referring to Fig. 19 below, when programming bit B,
the disturb mainly affects the bits on the same wordline that do not have to be programmed (bits A andC, for instance), because they are biased at the samehigh gate voltage (~20V). Cells on unselected
wordlline of the same block (WL<1:j> in Fig. 18) arealso disturbed, but less strongly than on the selected
wordline because the applied voltage is lower (Vpass~10V).

Figure 19: Program disturb

10

Program disturb only affects the bits in the same
block of a page that is programmed. All the otherblocks are not impacted. Furthermore, program
disturb is not a permanent effect. After an erase
cycle cells that were previously disturbed will
program and erase normally.

Cell-to-cell interference
The effect by which programming one cell disturbs
the adjacent ones is called cell-to-cell interference.
The reason is that the electrons stored in the floatinggate of the programmed bits modify the potential of
the nearby floating gates. This causes a shift of thethreshold voltage toward programmed values. In a
NAND flash block each cell of the block is surroundedby eight adjacent cells (excluding those at theboundary of the block, as in Fig. 20). If we suppose
cell A to be erased and to program all of the eightadjacent cells the disturb can be significant enoughto cause bit A to be programmed in a subsequent
read.

Read Disturb
As with program disturb, read disturb also causes ashift to a higher value in the threshold voltage ofthe cells in the block in which a page is read.
Because the voltages involved in the read operations
are much lower than during programming, many
read cycles are needed to cause a read failure(normally more than 10K). Read disturb is not
permanent, and the cells that were disturbed
previously will program and erase normally after an
erase cycle.

Bad Blocks
NAND flash devices are commonly delivered withsome blocks (typically one to two percent of thetotal block number) that are not working correctly
due to manufacturing defects. These blocks arecalled bad blocks, and should not be used. As wellas these intrinsic bad blocks, some additional badblocks may occur during the lifetime of the device,caused by failures during program or erase
operations. The flash controller manages thehandling of these new bad blocks, transferring thevalid data to a new block and marking the failingones as bad.

Figure 20: Cell-to-cell interferenceThis disturb is proportional to the coupling
capacitance of cell A toward the adjacent ones, andso it is more evident in recent technologies where
distances between cells are very small, creating
bigger coupling capacitances. MLC and TLC NAND arealso more affected by this than SLC NAND, because
the tolerated threshold shift is lower. To avoid
programming patterns like the one described above(or at least to reduce the probability) it is necessary
to use a randomizer to scramble data. Moreover, thedevices require page programming in sequential
order so the coupling effect can be taken into
account during each program operation.

11

3D NAND Architecture

4. 3D NAND
To overcome the scaling limitations of 2D NAND flash,a new technology was introduced in which thememory cells are stacked vertically in multiple
layers. This emerging technology is called 3D NAND.
It has been developed to achieve higher densities ata lower cost per bit.

Meanwhile all 3D NAND devices changed fromfloating gate to charge trap technonoly.
In charge trap the storage layer is formed using an
insulator, normally a layer of silicon nitride. Using
an insulator as the means of storage enables the
manufacturing process to be simplified.
3D NAND has some significant advantages over 2D
NAND flash:
•
•

•

•

It uses more relaxed technology nodes
3D architecture is less affected by cell-to-cellinterference, allowing tighter distributions andgreater enduranceLess cell-to-cell interference enables fasterprogramming
by
using
a
single-passprogramming algorithm where two or three
pages for MLC and TLC can be written
simultaneously
Single-pass programming is more energy
efficient than single-page programming

Figure 21: 2D vs 3D NAND flash

However, there are some drawbacks:•••

Higher endurance is achieved at a higher Error
Correction Code (ECC) requirements cost
The usage of charge trap technology can lead tolower data retention characteristics
Longer erase time12

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