Supporting information for

Modulation of Thermoelectric Power Factor via Radial
Dopant Inhomogeneity in B-doped Si Nanowires
Fuwei Zhuge1, Takeshi Yanagida1, Naoki Fukata2, Ken Uchida3, Masaki Kanai1, Kazuki
Nagashima1, Gang Meng1, Yong He1, Sakon Rahong1, Xiaomin Li4 and Tomoji Kawai1

1. Institute of Scientific and Industrial Research, Osaka University, 8-1 Mihogaoka, Ibaraki, Osaka 567-0047,
Japan
2. National Institute for Material Science, 1-1 Namiki, Tsukuba, Ibaraki, 305-0044, Japan
3. Department of Electrical Engineering, Keio University, 3-14-1 Hiyoshi Kouhokuku Yokohama 223-8522,
Japan
4. Shanghai Institute of ceramics, Chinese Academy of Sciences, Shanghai 200050, China

Contents:
1.

Device configuration for Seebeck coefficient measurement

2.

Diameter calibration of Si nanowires by SEM and TEM

3.

System error estimation

4.

Resistivity distribution of VLS grown B-doped Si nanowires

5.

Seebeck coefficient of homogeneously doped Si

6.

FET mobility evaluation by back-gate configuration

7.

Simulation of carrier redistribution under dopant inhomogeneity

8.

Additional supporting results from surface etching9.

TEM images of δ-doped Si nanowire

S1

1. Device configuration for Seebeck coefficient measurement
Figure S1 (a) shows the device configuration to measure the resistivity (ρ) and Seebeckcoefficient (S) for B-doped silicon nanowires. The micro-heater, 2 resistive thermometers andseveral additional electrodes for 4-probe method were fabricated. The device was fabricated on Si
substrates with 300nm SiO2 layer. The electrodes were composed of Pt, which provided an ohmic
contact with the present B-doped Si nanowires.

Figure S1. a) The nanowire device configuration for resistivity and Seebeck coefficient measurements. b), c) andd) show the typical data of thermovoltage (∆V) measurement, temperature (∆T) calibration and linear regression
between ∆V~∆T for thermopower S. The source voltages of microheater for these measurements were varied from
5 to 7V to induce different temperature gradient. e) shows the example of Seebeck measurements on highly
resistive nanowires.

Seebeck coefficient values were determined by using the microheater and the thermometerelectrodes. During measurements, the microheater was heated up to induce a temperature gradient byapplying a constant voltage. The thermovoltage (∆V) along the Si nanowire was then recorded byusing the thermometer electrodes (with the thermometer-2 grounded). Subsequently, the temperature
difference (∆T) was measured by tracking the resistivity variation of the two Pt thermometers. Figure
S1 (b) and (c) show the extracted thermovoltage and temperature data under various source voltages
on the micro-heater. A linear fit of the measured ∆V and ∆T was then used to determine the Seebeckcoefficient value of the Si nanowire, S=-∆V/∆T, as shown in figure S1 (d). We note that the final S
reported in this study was further corrected by subtracting the thermopower of Pt electrodes (SPt~-

S2

5µV/K),1 although its contribution was almost negligible in the present experimental range. To
perform above measurements, a cryostat system equipped with microprobes and Keithley 4200SCS(with preamplifier KI4200) was used. The high input impedance of the voltage measurement system(>1018Ω) allowed reliable Seebeck measurement even on those highly resistive nanowires, as shownin figure S1 (e). The estimated offset voltage and noise level in the measured voltage signal was
generally 10~150µV and <30µV. Before the measurements, the cryostat was evacuated to a pressure
below 0.1Pa.
To extract the temperature difference ∆T on Si nanowires, the temperature coefficient ofresistivity (TCR) of Pt thermometer of ~0.35% was used. This value was obtained by averaging dataon different devices. The raw resistance data from different thermometers was shown in figure S2.
The measured TCR value was found slightly lower than the standard value (~0.385%) of high purity
Pt on Al2O3 substrates.2

(a)

29.0

y = 0.1067x + 30.507
R² = 0.9989

36.0

Rthermometer(Ω)

28.5

Rthermometer (Ω)(b) 37.0

y = 0.085x + 23.895
R² = 0.9993

28.0
27.5
27.0

34.0
33.0

TCR=0.356%

26.5

35.0

26.0

TCR=0.35%

32.0
0

20

40

60

80

0

Temperature (OC)

20

40

60

80

Temperature (oC)

Figure S2. a), b) The TCR calibration of Pt thermometers using the measured temperature dependent resistance inthe range of 300~330K. The measured TCR was ~0.35% by referencing to the extrapolated resistance at 0oC.

2. Diameter calibration of Si nanowires by SEM and TEM
In this study, we measure the diameter of Si nanowires by SEM (JEOL JSM 7001F). To evaluate
the accuracy of this estimation, we compare the SEM data with the size measured from TEM
observation for the same nanowires. To be able to do this, the nanowire device was made on asuspended Si3N4 membrane. The fabrication process and corresponding results were shown in Figure
S3. The Si3N4 was 50nm thin, which was sufficient for the transmission of electron beam. By
comparing the SEM and TEM observation, we have obtained the correlation between the two, asshown in Figure S3 (f). As can be seen, the diameter sizes measured by SEM were over-estimated by~2.8nm in the average, when compared with TEM data.

S3

Figure S3. (a) Fabrication procedure of Si nanowire devices on Si3N4 membrane substrate for TEM observation.
(b), (c) and (d) show the SEM images of fabricated Si nanowire devices on Si3N4 membrane. Image (e) shows thecorresponding TEM image taken at the same position with (d). Figure (f) shows the comparison between SEM andTEM measurements on the estimated diameters of Si nanowires.

3. System error estimation
3.1 Resistivity
The electrical resistivity ρ was determined from the measured nanowire resistance R and diameterd via ρ=Rπd2/4L, where L is nanowire length between electrodes. Since the resistance contribution
from the contact (Si/Pt) was generally eliminated by the 4-probe method, the major error in theresistivity determination came from the measurement accuracy of diameter. From the calibration
shown in Figure S3, we expected a ~5% overestimation in the diameter (+2.8nm for a 50nm).
3.2 Seebeck coefficient
Both the thermovoltage and temperature measurements determine the overall error of estimation
for the Seebeck coefficient values. The standard error for voltage measurements depended on the
impedance match between the nanowire and measurement system. With the high impedance
Keithley 4200SCS, this error was found to be less than ~5% in our system. The temperature
measurements depended on the accuracy of the resistance measurement of thermometer. In our
experiments, the standard error for the 4-probe resistance measurement on Pt thermometer was foundaround 0.002~0.01Ω. Considering the total resistance of the thermometer (30~50Ω), an uncertaintyof <0.03K was estimated for the temperature measurement. Such accuracy was comparable with thecommercial thermocouples based on resistivity calibration. Considering these factors and theS4variation of TCR of Pt thermometers (0.35±0.025%) among different devices, we estimated an
overall error of ~10% in the measured Seebeck coefficient data. This percentage error has beenreflected in the figures in manuscript.

4. Resistivity distribution of VLS grown B-doped Si nanowires
We were able to obtain the statistical information of electrical resistivity of present VLS grown Si
nanowires by measuring over 60 nanowire devices. Figure S4 shows the nanowire resistivity data
versus the diameter. The frequency distribution of resistivity data was shown in the inset. As seen in
the figure, the present Si nanowire exhibited the wide distribution in the electrical resistivity, ranging
from 3×10-3Ωcm to 6×102Ωcm. Especially, there was no significant size dependence on the nanowire
resistivity data. In this case, the impurity scattering from ionized dopant atoms still dominates overthe surface scattering, and the size effect (including the quantum effect) on resistivity seems to be
negligible within the present experimental conditions.3

Figure S4. Nanowire resistivity data as a function of the diameter for the present B-doped Si nanowires. The inset
shows the frequency of resistivity data ranging from 10-3 to 103Ωcm.

5. Seebeck coefficient of homogeneously doped Si
The Seebeck coefficient S of semiconductor is generally consisted of both the electronic andphonon drag part, S=Sd+Sph. The electronic part Sd can be obtained by solving the Boltzmanntransport equation based on the known electronic band structure of Si. The second phonon drag term

Sph comes from the phonon-electron interaction, and is usually described as Sph=βvphlph/µeT.4, 5 In thisformula, vph and lph are respectively the velocity and mean free path (MFP) of phonons, µe is theelectron mobility, and β is the interaction coefficient.4 The mean free path of phonons can be
S5modulated by the presence of surface/interface or impurities scatterings. In Si nanostructures, lph isusually greatly reduced due to the strong space confinement. Thus, Sph contribution to the total S
tends to be minor. Considering the average diameter of present nanowires (~50nm) and lph in bulk Si(~1µm),5 we expected Sph was decreased by 20 times in our nanowires. This would lead to anegligible Sph of ~20µV/K even in the most resistive Si nanowires. With the minor contribution ofSph, the total S in Si nanowires can be then approximated by the electronic part Sd. By solving theBoltzmann transport equation, Sd has been well modeled and can be expressed by the Mott relation.
For non-degenerate semiconductors, it was further simplified asܵௗ =݇஻ ‫ܧ‬ி − ‫ܧ‬௏
5
൬
+ߣ+ ൰
2
݁
݇஻ ܶ

where kB is the Boltzmann constant, EF and EV are respectively the energy of Fermi level and valenceband edge, λ is the scattering factor and is -1/2 when the phonon scattering dominates impurity
scattering during hole transport.4 In this work, the above non-degenerate assumption was used for the
Si nanowires with carrier concentration of less than 1x1018cm-3.
From the above equation, the Seebeck coefficient of Si can be described by the Fermi level, which
can be further derived from the carrier concentration p by using the well-known relation: p=NV*exp(-(EF-EV)/kBT), where NV is the effective density of states in valence band. Hence, the theoretical
relation of Sd~p can be simply obtained by conducting the above calculation under various doping
levels. To obtain the desired Sd~ρ relation as the measured results, the carrier concentration p was
further replaced by the electrical resistivity ρ=pµe by using the empirical hole mobility of B-doped
Si,6ߤ = ߤ଴ ݁

௣
ି ௣೎

+

ߤ௠௔௫ − ߤ଴ߤଵ−ఈ
1 + (‫݌‬/‫ܥ‬௥ )1 + (‫ܥ‬௦ /‫)݌‬ఉAll the parameters used in this calculation were listed in table S1, which were obtained from thenumerical fitting of the experimental measured hole mobility in bulk Si.6 A good consistency can befound between the calculated Se~ρ relation and the earlier reported data on homogeneously B-doped
Si (Figure 2 of the main manuscript).

Table S1. A list of the parameters used for the calculation of Se~ρ relation.
Parameter

Nv

µ0
19

µmax

µ1

Cr

Cs
20

α

β

pc

Value

1.04x10

44.9

470.5

29.0

2.23x106.10x10

0.719

2.00

9.23x1016

Unit

cm-3

cm2/Vscm2/Vscm2/Vs

cm-3

cm-3

/

/

cm-3

S6

17

6. FET mobility evaluation under back-gate configuration

Figure S5. (a) Illustration of the back-gate configuration for the determination of hole mobility in Si nanowires.
(b) Typical examples of field effect measurements on B-doped Si nanowires under a small source-drain bias of
Vds=0.02V. (c) A comparison between the device capacitance estimation from the analytical method (with various

dielectric constant assumed) and FEM simulation. (d) and (e) shows the extracted hole mobility plotted versus the
nanowire diameter and the derived carrier concentration.

The hole mobility of Si nanowire was estimated by performing FET measurements using the backgate configuration (shown in Figure S5 (a)). The typical gate modulated drain current Ids for aheavily and a lightly B-doped Si nanowires are shown in Figure S5 (b). The hole mobility in Si
nanowirewasdetermined

from

the

slope

of

dIds/dVg

around

the

zero

bias,

as

µh=(dIds/dVg)*L2/(CgnVds), where L is the nanowire length, Cgn is the gate-nanowire capacitance.7, 8
As shown in the figure, the observed gate dependences of present Si nanowires were consistent withthe behaviors of p-type semiconductors. Under negative biased gate voltage, holes were induced
within the nanowire, which increased the source-drain current. However, with the small physicaldimension of nanowires, the direct measurement of Cgn is usually very challenging. Here, we used
the analytical approximation based on the metallic cylinder-on-plate model.9 The capacitance of anembedded metallic nanowire can be written as Cgn=2πε0εrL/cosh-1(1/2+dox/d), where ε0, εr, d, t are

S7

respectively the vacuum permittivity, dielectric constant, nanowire diamter and the thickness of gate
oxide.8 Under the metallic approximation, such method can be only applied to those heavily doped Si
nanowires. Especially, due to the dielectric discontinuity in the back-gate configuration, an effective
dielectric constant εeff=2.2 has to be used for the dielectric oxide of SiO2 (εSiO2=3.9).8 This treatment
has been proved to provide good approximations to the real device capacitance as that from finite
element method (FEM) simulations. 10 A representative comparison between the analytical method
and the FEM simulation was shown in figure S4-c, and the careful examination of the dielectric
constant is very important in the analytical method, as shown in Figure S5 (c).
Figure S5 (d) shows the hole mobility data as a function of the nanowire diameter. In contrast to
the case of InAs nanowires,11 there was no clear diameter dependence for the present Si nanowires.
In figure S5 (e), the extracted mobility was further plotted as a function of the carrier concentration,
which was calculated by the measured resistivity and mobility, as p=1/ρµe. The result shows theclear trend, which is consistent with the impurity scattering limited carrier mobility in the heavily
doped range (where the carriers are degenerated), and the hole mobility solely decreases withincreasing the doping concentration.

7. Carrier redistribution under dopant inhomogeneity
In the presence of dopant inhomogeneity (heavily doped outer shell and lightly doped inner core),
the activated carriers (holes in this case) would exhibit the non-uniform spatial distribution within
the nanowire. As seen in pn junction, the carrier diffusion should occur across the inhomogeneous
region until the Fermi level is aligned. By considering the diffusion and drift current, we performed
simple calculations to simulate the carrier redistribution within our nanowires. The results of thedopant and hole distribution, the electrical field and potential profiles were shown in Figure S6.
Since we do not have the dopant profile data in our Si nanowires, the present simulations can give
only qualitative information. The finite element analysis was performed for above simulations. Si
nanowire with the diameter of 100nm was simulated. First, a diffusion model was used to approachthe dopant profile of B atoms in Si nanowires. The initial dopant concentration at the core wasassumed to be 1016cm-3, while the surface dopant concentration was set to be constant as 1020cm-3. A
diffusion constant of D=5x10-16cm2/s for B atom in Si and a diffusion time of 600s was used in thesimulation to approximate the experiment conditions.12 The obtained dopant profile exhibited thecharacteristic of a heavily doped outer shell and the lightly doped inner core, as shown in Figure S6(a). To simulate the hole redistribution, the electrostatic model was used. The surface potential of
nanowire was assumed to be 0. The results indicated that the active hole concentration in the coreregion of nanowire was increased by an order compared to the initial doping level.
S8

Figure S6. (a) Simulated radial profile of the dopant atoms and active holes. (b) The corresponding electrical fieldand potential profile in the same simulation.

In above simulations, the initial dopant profile would significantly influence the carrier
redistribution in the equilibrium states. Here, we assumed the difference in the four orders ofmagnitude for the concentration of the surface and core dopant atoms, which came from the different
incorporation efficiency from the nanowire surface and catalyst.13 Since the wide distribution of over5 orders on the nanowire resistivity was observed in our experiments, the above initial assumption on
the dopant profile was expected to be reasonable.

8. Additional results for surface etching experiments
In Table 1 of the main manuscript, we showed the data of enhanced hole mobility after slightly
removing the surface layer. The corresponding SEM morphology and the details of field effectmeasurements were shown in Figure S7. The increased slope of dIds/dVg in Figure S7 (d), whencompared with Figure S7 (c), directly indicates the higher hole mobility of the inner core than theouter layer. Considering that the hole mobility in present Si nanowires were generally limited by the
impurity scattering, this result can therefore be the evidence as to the presence of heavily doped outershell and the lightly doped inner core for the present VLS grown B-doped Si nanowire.
Figure S8 shows the resistance variation results of Si nanowires when we performed various
surface etching steps. All resistance data of Si nanowires were normalized to the nanowire length,

Rnormalized=R/L=4ρ/πd2. The dash lines in the figure were used to indicate the expected results from
uniform dopant profiles- i.e. constant resistivity. A fixed surface density of states Dit=1x1012cm-2
was assumed on the Si nanowire after the SC1 surface etching.14 The surface depletion effect was

S9considered by following the earlier reference.15 As seen in the figure, the samples with the smaller
diameter or the lighter doping concentration showed the more significant surface effects on themeasured electrical properties. However, even considering the surface depletion, our experimentresults of surface etching showed the apparent deviation from the expectation of uniform dopant
profile. From many similar etching experiments, we conclude that the thin surface layer in present
VLS grown B-doped Si nanowires plays a major role on the transport carriers for total electricalconduction.

Figure S7. Additional details for the surface etching experiment shown in table 1 of the main manuscript: (a), (b)the morphology and (c), (d) the transconductance measurement.

Figure S8. The resistance (normalized) variation after surface etching (each marker here corresponds to the same
nanowire device). The dash lines are used to indicate the expectations from uniform dopant profile, by considering
different doping concentration but a fixed surface states of Dit~1x1012cm-2.

S10

9. TEM images of δ-doped Si nanowire
Figure S9 shows the TEM images of δ-doped Si nanowires, which were fabricated by growing aheavily B-doped Si layer on non-doped VLS grown Si nanowires. The lattice fringe and diffraction
pattern in figure S9 b and c suggested that the nanowires were <111> oriented. From the images ofseveral nanowires, the surface shell layer on δ-doped Si nanowires was estimated to be around
2~5nm.

Figure S9. (a), (b) and (c), the low, high magnification TEM image and selective area electron diffraction (SAED)
pattern of a δ-doped Si nanowire.

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