Challenges towards Cambrian Explosionin the Post-Moore Era
Project Overview
Slowdown and inevitable end in exponential scaling ofprocessor performance, the end of Moore’s Law ispredicted to occur around 2025-2030. The system FLOPS
will cease to improve, resulting in serious consequencesfor IT, especially supercomputing.
We claim that data-oriented parameters, such as
bandwidth and capacity, or BYTES, are the newparameters that will allow continuous improvement evenafter computing performance or FLOPS ceases toimprove. This will lead to so-called Cambrian explosion incomputer architecture and algorithms including the newcomputational principles.
Such transition from FLOPS to BYTES will lead to
disruptive changes in the overall systems fromapplications, algorithms, software to architecture.

Post-Moore
Research Platform
Top Supercomputers
TSUBAME3.0(Tokyo Tech)
Oakforest-PACS(U-Tokyo/Tsukuba)

Post-Moore Applications

Post-Moore Numerical Methods and Algorithms
Innovative Software
Frameworks for
Cambrian Explosion ofComputation Science

Innovative
High-Performance
Numerical
Algorithms

Ultra Low-power
Computation using
Reduced-Precision
and Auto-Tuning

Innovative Machine
Learning for
ComputationScience

Post-Moore Programming and System Software
System Software for
Post-Moore Deep
Memory Hierarchy

Programming Modeland Implementation on
New Computation
Principle

Non-Neumann
Computation Systemand Programming Modelby Wired-Logic

Super Building Block
Architecture
Next-Gen Optical NW
Prototype

Post-Moore High-Performance Architecture
Creation of Post-Moore
Unified Architecture by
Innovation of Communication
Performance and Methods

Created of New-Generation
Computer Architecture on
New Computation Principle

Architecture

Programming & System Software

Numerical Methods & Algorithms

Unified Architecture:
In the Post-Moore era, processor chips,
memory, NW will not be implemented on asingle technology. The key technology is fora methodology to integrate various
heterogeneous device into a system.

Exploiting Deeper Memory
Hierarchy:
System software should be exploit deeper
memory hierarchy including heterogeneous
types of memory. Topics include schedulingsuch memory hierarchy, fault tolerance withNVM.

Framework to Support Cambrian
Explosion in Architecture:
Framework for software algorithm will bereconsidered based on byte-centric metricfocused in novel architectures in Cambrian
explosion.

Next-Gen Architecture based on
New Principle:
For IT infrastructures in extreme big-data era,novel device architectures including
3D-stacked devices, non-volatile devices,
nano-photonics devices. New computational
principle is required to exploit them tocompose new architecture in the post-Moore
era.

Programming Model on New
Principle:
Design and implementation of novel
programming model are required to on
support new computation principle withextremely high BW memory and network.
Towards non von Neumann system:
To support improvement of BW metrics,
computation system and compilers arerequired to support non von Neumannmodel. Support for customizable logic will beincluded.

Post-Moore’s Era Supercomputing(PMES17) Workshop
Co-located with SC17
Nov 13, 2017
Co-Chaired by
Satoshi Matsuoka (Tokyo Tech)
Jeffrey S. Vetter (ORNL)
To explore the scientific issues, challenges, and opportunities
for supercomputing beyond the scaling limits of Moore's Law

https://sites.google.com/view/pmes17/

Innovative Numerical Algorithms:
Numerical algorithms should be restructured
to support new architectures, including
dense matrices, iterative stencils,
eigen/singular value solver, etc.
Ultra Low Power using ReducedPrecision:
In order to achieve ultra low power,trans-precision and approximate computing
will be pursued, while securing precision ofthe solution. Auto-tuning techniques areapplied.
Innovative Machine Learning for
Computational Science:
Machine learning itself should be adapted
to new explosively variant architecture. Also
machine-learning based mathematicalmodels are developed for highperformance/precise simulations.

Project Leader: Satoshi Matsuoka (Tokyo Tech)
Hideharu Amano (Keio Univ), Kengo Nakajima (Univ of Tokyo),
Koji Inoue (Kyushu Univ), Kenjiro Taura (Univ of Tokyo),
Kentaro Sano (Tohoku Univ), Takeshi Iwashita (Hokkaido Univ),
Takahiro Katagiri (Nagoya Univ), Takashi Shimokawabe (Univ of Tokyo)
Toshihiro Hanawa (Univ of Tokyo), Toshio Endo (Tokyo Tech)
S. Matsuoka et al. : From FLOPS to BYTES: Disruptive Change in
High-Performance Computing towards the Post-Moore Era. ACM Computing Frontiers 2016, Invited paper.

http://www.gsic.titech.ac.jp/sc17