White Paper

An Introduction to:

Error
Correction
Coding© Swissbit AG 2024 – All rights reserved.

1. Abstract
This paper explains the basic concepts behind error
correction and highlights a brief history of different
error correction codes discussing and alaysing theadvantages and disadvantages of the following
three methods most common to NAND flash
technology.
The Bose-Chaudhuri-Hocquenghem (BCH) codes are
discussed in detail, as they are used in flash memory
controllers for SLC and MLC NAND flash. Low-Density
Parity-Check (LDPC) codes are used today for TLC andQLC flash, which requires more powerful codes.
Finally Generalized Concatenated (GC) codes are
dicussed as this method found exclusively in Swissbit
modules is especially suited for industrial storage orapplications requiring high reliability.

Table of Contents
1. Abstract
2. Introduction
3. History of Error Correction Codes
4. Abbreviations and Concepts
5. Bose-Chadhuri-Hocquenghem Codes
6. Low Density Parity Check Codes
7. Generalized Concatenated Codes
8. Conclusion

2. Introduction
As the integration size of NAND flash memory shrinks
and more bits can be stored in a cell, the error
correction requirements for flash memory controllers
are increasing with each new generation of flash.
Error correction has become one of the mostimportant tasks of flash memory controllers. For
quite a number of years, error correction based on
Bose-Chaudhuri-Hocquenghem (BCH) codes was theprevalent choice. Yet, as flash error rates continue togrow with higher density flashes, the error correction
capability of the controllers has to be increased. Thishas become increasingly difficult when considering
cost, area and power limitations.

3. History of Error Correction Codes2

correction were:
In the 1940s Richard Hamming developed theHamming Code. At the time the computers stored
information on punch cards. However, this system
was error-prone, because it was common for cards
to get bent or miss-punched, causing flipped bits
and a failing system.
Hamming searched for a solution with parity bits. A
parity bit (or check bit), is a bit added to a string ofbinary code to ensure that the total number of 1-bitsin the string is even or odd. In the event of a single
bit error, one parity bit added to the end of themessage allows the system to detect the error
because the parity bit no longer matches thesequence. While this allows detecting an error, it
could not identify the exact error location andcorrect it.
Hamming found a method to also correct a single bit
error by adding three parity bits to four bits of data,
introducing the so-called 7:4 Hamming code. In Fig.
1 the basic principle is outlined. Each parity bit (P1,P2, P3) is related to three data bits, shown in thesame circle. An incorrect data bit will cause at least
two parity bits not to match the data. By considering
which parity bits do not fit, the incorrect data bit
can be located and corrected. In case only one parity
bit does not match, the parity bit itself is the one bitthat has flipped during transmission and therefore
should be corrected to its inverse value.

1949 - Golay CodeThe binary Golay code is a type of linear error
correcting code used in digital communications
which was introduced by the work of Golay [1].
1954 - Reed-Muller CodeThe Reed-Muller codes are a family of linear errorcorrecting codes developed by Irving S. Reed andDavid E. Muller [2].
1959-1961 - Bose–Chaudhuri–Hocquenghem (BCH)
This code was invented by French Mathematician
Alexis Hocquenghem and independently by Raj Boseand Dr. Ray-Chaudhuri. These codes are the mostimportant cyclic block codes.
1960 - Reed-Solomon (RS) CodeReed-Solomon codes (RS codes for short) are a classof cyclic block codes. They are used in channel
coding to detect and correct transmission or memory
errors as part of a forward error correction. They area special case of no binary BCH-Codes [3].
1960 - Low-Density Parity-Check (LDPC) CodeAlso known as the Gallager Codes which weredeveloped by Robert G. Gallager in his doctoral
dissertation [4].
1967-1969 - Berlekamp Massey Algorithm
A decoding algorithm for large distance RS code
invented by Elwyn Berlekamp and James Massey.
1990-1991 - Turbo Codes
Turbo codes were developed in the early 90s andwere the first practical codes to closely approach thechannel capacity, a theoretical maximum for thecode rate at which reliable communication is still
possible given a specific noise level. Revolutionary
for the times, many experts in the field did not
believe reported results. Only when the performancewas confirmed did engineers start considering othertypes of iterative signal processing.

Figure 1: Basic outline of Hamming’s 7:4 ECC method to identify
and correct bit errors by using 3 parity bits for each block of 4

Further milestones throughdata bits. the history of error

Before Turbo Codes emerged, the most efficient ECC
was a serial concatenation code RSV based on anouter Reed-Solomon ECC combined with an inner
Viterbi decoded short constraint length convolutional
code. Turbo codes are used extensively intelecommunications, specifically 3G, 4G and LTE as
well as NASA missions.

4. Abbreviations and Concepts

3The bit error rate (BER) is defined as

It is also the probability of a single bit being
erroneous. This number is entirely depending on the
flash memory, its technology, temperature, age anduse. The uncorrectable bit error rate is defined as

Like the BER, it is also the probability of an
uncorrectable bit. On the system-level, theuncorrectable block error rate (UBLER), which again
is also the probability of a block or frame error isdefined as:

The relation of the bit error rate to the uncorrectable
bit error rate or uncorrectable block error rate is theperformance of the error correction.

5. Bose-Chaudhuri-Hocquenghem Codes
In coding theory, Bose-Chaudhuri-Hocquenghem(BCH) codes form a class of cyclic codes that are
constructed using polynomials over a finite field. It
is the best algorithm with respect to correcting
binary-symmetric channel (BSC) errors.
A key feature of BCH codes is that they allow control
over the number of symbol errors correctable by thecode. It is even possible to design binary BCH codesthat can correct multiple bit errors without extreme
computing power. BCH error correction decodeswith ease through an algebraic method known as
syndrome decoding. This not only simplifies thedesign of the decoder but also allows for small low
power electronic hardware.
With a relatively standard implementation, BCH
codes were most commonly found in satellite
communications, compact disc players, DVDs, andSolid State Drives until TLC and QLC technology
became widespread with 3D flash.

Technical Background
The Decoding of BCH code is performed in threemain steps:•••

The Syndrome is calculated from the received
codeword.
Error location polynomial is determined bysolving the so-called key equation. The
equation can be solved by the BMA-Algorithm.
(Berlekamp-Massey Algorithm)
Error locations are identified by exhaustive
search. The most commonly used algorithm iscalled Chien Search.

After these steps, the errors can be corrected.
Essentially, the minimum code distance determines
the correction capability.

4Advantages of BCH Codes•••

BCH codes have a relatively straight forward
implementation
They allow for control over the number ofsymbol errors correctable by the code
Decode with ease, which in turn, allows for low
power electronic hardware

Disadvantages of BCH Codes••

Soft decoding algorithms (e.g. Viterbi, stackalgorithm) for BCH codes have a very highcomputational complexity
Bad code rate for higher error correction
capabilities

5. Low-Density Parity Check CodeDeveloped in the 1960s, low-density parity-check(LDPC) codes, which are also known as Gallager
codes, in honor of Robert G. Gallager, who developed
the concept in his doctoral dissertation at theMassachusetts Institute of Technology, were
impractical to implement at that time [4].

In these classes of codes, there are hundreds ofdifferent codes that can remarkably differ in theircorrection capability. For example, BCH codes can be
designed to correct 20 bit-errors in a 2K block ofdata, which is a rather poor performance, and BCH
codes can be designed to correct 120 bit-errors in a
2K block of data, a very respectable performance.
This illustrates that it is not sufficient to mention
just the class of code, BCH, but also the performancein respect to what amount of erroneous bits can becorrected in a single codeword. The same applies for
an LDPC code.
The class of code highlights the underlying principles
and its construction, but it does not reveal its
performance. This can be instantly recognized in Fig.
2, where the performance of different LDPC codes isshown for a limited signal-to-noise ratio via
simulation.
Fig. 2 indicates that there are LDPC codes withexcellent performance and LDPC codes with poor
performance. Therefore, just relying on the term
LDPC to expect a stellar performance is amisinterpretation of the term.

LDPC codes are a class of linear block codes for error
correction. After they had been almost forgotten, apublication in the year 2001 demonstrated that they
could operate close to the Shannon limit and thatthey could be efficiently implemented as irregular
LDPC codes [5]. This resulted in an increase inpopularity leading to their presence in several
communication standards, like e.g. DVB-S2 and
DV-T2 where an LDPC code is wrapped by an outererror correction - for the two mentioned standards
that is a BCH code, to correct sporadic errors that are
made by the LDPC decoder.

Technical Background
LDPC has become the flash industry´s term for themost powerful error correction codes and it isassumed that a flash memory controller featuring an
LDPC-based error correction will always be able toprovide the maximum performance in terms ofcorrection. This is simply not the case. Just as it is
the case for BCH codes, an LDPC code is not a single
code but a family or class of codes.

Figure 2: Frame error rates over signal-to-noise ratio for different LDPC implementations for short codewords. The colors show
different optimizations: the random graphs (green), girth optimized (blue), and neighborhood optimized (red) graphs are allof identical degree structure [6]..

5In contrast to a BCH code, the performance in termsof correctable bits in a codeword is very hard tospecify. For the BCH code, this value can be calculated
and is valid for all codewords – regardless of theerror distribution. Unlike for the BCH code, theamount of errors an LDPC code can correct in acodeword is varying from codeword to codeword. As
a consequence, there might be codewords where an
LDPC code is able to correct 200 bit-errors in a 2K
codeword and there might be a codeword where an
LDPC code can only correct 40 bit-errors in a 2K
codeword. Not only can the number of correctableerrors in a codeword vary, but this number cannot
be determined analytically. The implications of thatare significant. It translates directly into the fact thatthe correction performance cannot be guaranteed
through mathematical calculation.
Instead of analytically determining the numbers ofcorrectable errors for every codeword, theperformance is measured by simulation. Every
performance indication of an LDPC code in any
product today is based on simulation. As has been
pointed out earlier, the varying number ofcorrectable errors in codewords leads to the fact that
only a simulation of every single codeword will
make it possible to determine an exact amount ofcorrectable errors. This simulation is highly timeconsuming. In chapter 5.2 the time needed for a full
simulation of all possible codewords for a standard
LDPC implementation is calculated. As it is clearly
obvious, this exceeds every development-time ofany known system.
In order to simulate the performance nevertheless,several assumptions are taken. One of them is theassumption that the structure of the code andespecially of the decoder allows the prediction ofcertain weaknesses in the decoder. An important
step to modeling iterative decoding is to represent
codes in a graphical way. Therefore, decoding inmost LDPC implementations is done iteratively on abipartite graph by a so-called message-passing
algorithm. In the graph, information is exchanged
between neighboring nodes by passing messages on
the edges [5]. The performance of LDPC codes issimulated by measuring the performance on a set of
so-called “error-prone” patterns that are applied tothe decoder or its graph respectively.

The reason for this is that the performance of LDPC
codes under iterative decoding algorithms in theerror floor region is closely related to the structure of
the code’s Tanner graph. These “error-prone”
patterns are different for the type of channel: They
are called “stopping sets” for the binary erasurechannel (BSE) [7], while they are called “trappingsets” [8], “near codewords” [9] or “pseudo
codewords” [10] in case of the Binary Symmetric
Channel (BSC) and the Additive White Gaussian Noise(AWGN) channel. The effect of trapping sets can beseen for all curves in Fig. 2 to the right of the value
5.5 on the SNR, the x-axis. After the LDPC code issimulated with these patterns, it is assumed thatthe worst correction capability, i.e. the codewords
where the LDPC code can correct the fewest errors, isknown and that the correction capability in all othercodewords is better. There is a certain likelihoodthat this is true, maybe even for the majority ofcodewords, but it is definitely not a certainty.
In scientific terms, in the field of statistics, thismethod of estimating is called importance sampling:

It is a general technique for estimating properties ofa particular distribution, while only having samples
generated from a different distribution than the
distribution of interest [11]. The result of this can beseen in Fig. 3. Towards the right side of the figure,the solid line represents the codewords that haveactually been simulated. As the slope of the curve is
steep, this region is called the waterfall region – theregion where LDPC codes outperform any othercodes. Yet underneath the solid line, starting from a
UBLER of 10-10 and less, it is not certain which
performance the code will deliver. As mentioned,
the JEDEC defines a frame error rate less than 10-16 forenterprise-class flash storage. From Fig. 3, it is easily
understandable that it is not possible to guarantee
less than 10-16 when it´s only possible to simulate
down to a frame error rate of 10-10 and the rest isbased on estimation.

6

To verify this frame error rate, it is necessary tosimulate at least 40 x 1016 codewords. Assuming acode rate of

For each 4K codeword results in a data size of
3.6 x 104bits. The total data volume to be simulated
is then:If we then assume a simulation throughput of,
the time needed for the simulation can be obtainedby dividing the data by the data-throughput. The
total time to simulate all codewords is:

Figure 3: LDPC performance

In summary, the performance of an LDPC code isdetermined by simulating the codewords to a certain
limit and then applying a very limited set of testpatterns that are suspected to be the most difficult
to decode. After these have been decoded, it isassumed that this is the minimum error correction
performance that can be expected in all of the otheruntested codewords as well. As this is only an
estimate and there is no proof that this is correct,
the complete performance cannot be guaranteed.

Advantages of LDPC•

Disadvantages of LDPC•

Calculation of LDPC Simulation Time•
This chapter will go through a rough calculation of
the time needed to verify an LDPC implementationand its error correction capability in order toguarantee that a certain amount of errors can becorrected in every single codeword.

LDPC codes can be very performant in terms oferror correction

The location of the error floor can only be
estimated, therefore the performance of thecode can only be estimated
The class of code, LDPC, is often the only
reference given. As a result, it is hard to
distinguish which LDPC code with what level of
performance is actually implemented.

The JEDEC standard for Solid-State Drive (SSD)
recommends an uncorrectable bit error rate of lessthan 10-15 for client applications and of less than 10-16
for enterprise solutions [12]. Therefore, we require aframe error rate of 10-16.

7

5. Generalized Concatenated CodeIt was mentioned earlier that Digital Video Broadcast
standard uses a concatenation of an LDPC code anda BCH code. This is one of the two main methods ofcode concatenation, where the system of the innerencoder, transmission channel, and the inner
decoder are seen as a super channel for an outercode. The outer code is designed to correct theresidual errors of the inner code [13].

This means that it is possible to mathematicallyguarantee a correction performance for every single
codeword which implies in return that it is possible
to guarantee a defined performance regarding
uncorrectable block error rates on system level.

The other method is the so-called generalized code
concatenation. It combines several outer and inner
codes and optimizes the properties of the overall
code. As a result, it is possible to combine theadvantages of the inner and outer codes in order toreduce decoding complexity for example [13].
The GC code uses a combination of an inner BCH
code and an outer Reed-Solomon (RS) code. The
immense advantage that this code-construction
offers is in one particular aspect very similar to a
BCH-code: the number of correctable errors in eachcodeword can be analytically determined. Thisimplies that for every codeword, the error correction
can guarantee a level of correction performance. As
for all of the available flash memories a guaranteed
bit error rate is specified, it is possible to guarantee
a reliable operation within specified parameters.

Figure 4: GCC performance simulation (4K codeword size, 0.9
code rate)

Soft Decoding

Technical BackgroundThe soft-decoding of the GCC utilizes so-called logarithmic likelihood ratio (LLR) tables that containprobabilistic reliability information for the bits of a
specific NAND flash device at a specific lifecycle condition. LLR tables are used by the soft decoder of theerror correction engine to increase the probability tosuccessfully correct false bits.

The GC codewords are arranged in a matrix. The rowsof the matrix are protected by nested BCH codes,
whereas the columns are protected by a RS code [13].
The first one is the inner code whereas the latter one
is the outer code. A similar construction waspresented in [14] for magnetic storage systems.
Generalized concatenated codes are suited for highcode rate applications with low-complexity
decoding algorithms [15].

To obtain LLR-values of a specific type of flash memory, a sample is first brought to the desired lifecycle(for instance the maximum program- and erase-cycle number and the maximum data retention time).
Then by applying three different readings startingfrom a calibrated reference voltage the populationof bits is divided into 5 zones, as can be seen in Fig.
5. Readings at R+/-δ are normally called soft readings.

In contrast to LDPC codes, the residual error rates for
GC codes can be determined analytically [16], which
is important for applications where a low probabilityof failure has to be guaranteed.

Figure 5: Cell threshold voltages for single-level cell (SLC) flash
memory8

Z0 and Z3 are the areas with higher reliability and Z1and Z2 those with lower reliability (i.e. where more
likely error bits are located). For each zone the ratio
between the logarithmic of the probability to have0s or 1s is calculated

Figure 6: Cell threshold voltages

So that a table like the following can be filled

In MLC, TLC or QLC based devices where multiplereferences are used the same process is applied toeach reference.
Depending on the architecture used by the error
correction, additional readings can be performed togain even more information about the area withlower reliability.

When the soft decoder tries to recover a failing page,
the flash controller first performs several soft
readings for that page. Using the additional
information, it is now possible to identify whichzone each bit belongs to and to assign it to its
specific LLR value. With this additional reliability
information, the soft decoder can significantly
enhance the correction power of an ECC.
Different strategies can be implemented for thegeneration and usage of LLR tables.
LLR tables can be generated during a characterization
phase in which flashes of the same technology aretested. Another approach is to generate and update
LLR tables during operation within the storage device
by using dedicated sample data. That approachshould track accurately the lifecycle of the device.
Sample data is a dedicated portion of flash data inwhich a known pattern is written. By definition, tobuild LLR tables, the information about which are
the failing bits should be available thus they cannot
be extracted by reading the data stored in theapplication.
Both approaches have pros and cons and dependingon the application one or the other or even both canbe used.
Since LLR tables provide reliability information for
the flash device used in the application manydifferent tables should be generated to cover theentire lifecycle of the device. For this reason tables
at different cycling conditions, data retention, read
disturb and temperature are collected and stored.

9Calibration
During the operating lifetime and in case of
uncorrectable errors read from the flash memory,the controller executes a calibration which shifts
read-threshold levels of the memory.
On the transistor level, reading data from a NAND
flash memory cell means to compare the thresholdvoltage of the cell with a reference voltage. The
result of this operation is “0” if the threshold ishigher than the reference voltage or “1” otherwise.
There are many disturbs that impact the thresholdvoltage of a cell: program- and erase-cycling, read
disturb, data retention, temperature variation, etc.
The threshold shift due to above disturbs can cause
the cell threshold to cross the reference voltage thus
resulting in an error during a read operation. The
operation that tries to restore the best reading
conditions by changing the reference voltage toreduce error bits is called calibration.
As depicted in Fig. 7, calibration changes thereference voltage to eliminate, or reduce as much as
possible, the number of error bits. Since different
blocks or pages can experience different disturbs,
optimal calibration result found for one page can
not necessarily be applied to another page.

While at the beginning of the lifetime of a flash
memory the expectancy value of the raw bit error
rate lies below 1e-04, it moves over the lifetime of thememory towards 1e-03 and more. The calibration
process counters this and moves the expectancy
value of the raw bit error rate back to a lower value.
Calibration is a time-consuming task and could limit
read performance if used too frequently. Hence, it isnormally done when the number of error bits is
close or above the correction capability of the error
correction.
The frequency of this situation is increasing towards
the NAND’s end of life.
Advantages of the GCC
•
•
•

•

Hard- and soft-decision error correctionAnalytical determination of correction performance
LLR based soft-decoding (LLR tables obtained
from flash characterization or from in-systemdata based on pilot data)
Correction strength is a residual from (calibration, GCC hard/soft decoding, tuned read parameters, flash channel model)

Disadvantages of the GCC•

Some LDPC codes show better results in forhigher bit error rates while showing worse
results for lower bit error rates

Figure 7: Calibration process

If that is the case, the calibration process should be
repeated. NAND flash devices do not automaticallytrack threshold variations. Instead, the flash
controller is expected to decide when calibration isneeded and to execute the suitable sequence of
operations. The effects can be seen in Fig. 8.

Conclusion
This paper led through the history of error correction
to the codes that are relevant in the field of NAND
flash memory today.
For a long time, the BCH codes were predominantly
found in the error correction modules. In recent
years, the market has mainly moved towards LDPC
based error correction. Although these codes can be
powerful, they can have drawbacks for industrial
applications or applications with higher demands
for reliability. To overcome these drawbacks, GC
codes found in certain Swissbit modules boast
guaranteed correctional performance.

Figure 8: Effects of Calibration10

List of Sources[1]
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I. Reed, “A class of multiple-error-correcting codes and the decoding scheme,” Transactions of the
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[3]
I. S. Reed and G. Solomon, “Polynomial codes over certain finite fields. In: Journal of the Society for
Industrial and Applied Mathematics,” SIAM J., pp. 300-304, 1960.
[4]
R. G. Gallager, “Low-Density Parity-Check Codes,” IRE Transactions on Information Theory, pp. 21-28,
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parity-check codes,” Electronic Notes in Theoretical Computer Science, no. vol. 74, 2003.
[10]
P. O. Vontobel and R. Koetter, “Graph-cover decoding and finite-length analysis of message-passing
iterative decoding of LDPC codes,” IEEE Transactions of Information Theory, 2005.
[11]
Wikipedia, “Importance sampling,” [Online]. Available: https://en.wikipedia.org/wiki/Importance_
sampling. [Accessed 22 Decemeber 2023].
[12]
d. JESD218, “Solid-State Drive (SSD) Requirements Endurance Test Method,,” JEDEC Solid State
Technology Association, 2010.
[13]
J. Freudenberger, U. Kaiser and J. Spinner, “Concatenated code constructions for error correction in
non-volatile memories,” International Symposium on Signals, Systems and Electronics (ISSSE), pp. 1-6, Oct
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[14]
J. Spinner and J. Freudenberger, “Design and Implementation of a Pipelined Decoder for Generalized
Concatenated Codes Format,” in SBCCI ‘14 Proceedings of the 27th Symposium on Integrated Circuits andSystems Design Article No. 35, Aracaju, Brazil, 2014.
[15]
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11

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