Application Note

DIGITAL OUTPUT TRANSDUCERS
AND ∑Δ CONVERSIONDavid Jobling, ASIC Development Group Manager
Fabrice Salvi, Senior Analog ASIC Design Engineer
Cyprien Brun, Development Engineer
Pascal Maeder, Global Product Manager Drives
Thomas Hargé, Global Product Manager Renewable Energies
Mathieu Béguin, Marketing Engineer
Contents

0
1
2
3
4
5
6
7

Abstract				1Introduction				1LEM digital open-loop transducers		2
Analog to digital conversion
with ∑Δ modulators
2-3
Filter and performance choiceson the user side		
4-5-6
Physical interfaces
6-7-8-9
Delay vs filter: example		
10
References			10

List of figures

Fig. 1: Principle of Open-Loop
technology				1Fig. 2: LEM HG2 ASIC			1
Fig. 3: HO xxx-NPW			2
Fig. 4: Illustration of digital conversion
with ∑Δ modulator				2Fig. 5: Transfer function			2
Fig. 6: LEM provides bitstream		2
Fig.7: First-order ∑Δ modulator		3

ABSTRACTThis application note supports users of LEM open-loop Hall effectcurrent transducers in which analog to digital (A:D) conversion
is performed with an on-board sigma-delta modulator giving a
1-bit serial Bitstream output. The transducers concerned include
the HLSR xx-PW, HO xxx-NPW, HO xxx-SW and HO xxx-PW
families. The addition of a sigma-delta modulator to the traditional
accurate and compact analog transducers has many advantages:
few connections are needed and the user completes the A:D
conversion by choosing the filter used on the bitstream for the bestcompromise between resolution and response time, according to
the application.

1. INTRODUCTION: LEM ADVANCED OPEN-LOOPTECHNOLOGYLEM has a large family of analog open loop transducers in which
Hall cell technology is integrated with dedicated signal processing
to guarantee their accuracy and reliability. The transducers provide
the smallest, lightest and most cost effective measurement solution
while also having low power consumption.

Fig. 8: Noise in the ∑Δ A:D process		4
Fig. 9: Response of different sinc filters		5
Fig. 10: Application example with
Decimation Ratio and filter order		5
Fig. 11: 2W CMOS (Single-ended)

7
Fig. 2: LEM HG2 ASIC

Fig. 12 : Manchester coded data		8
Fig. 13 : Four wire RS422 and LVDS
interfaces.		
		9Fig. 14: Simulation Filter (sinc 2)

10

Fig. 15: Simulation Filter (sinc 3)

10
Fig. 1: Principle of Open-Loop technology

Table 1: HO 150-NPW performances:
Performance = f (OSR, SINC K FILTER, BANDWIDTH) 6
Table 2: Single-ended CMOS
levels wiring				7Table 3 : Manchester interfaces wiring		7
Table 4 : Four wire RS422 CLK OUT and
CLK IN connections				8N°ANE220518/2

The principle is shown in figure 1: a primary current flowing in a
conductor creates a magnetic field which is concentrated in the air
gap of a magnetic circuit. The Hall cell output VH is proportional tothe current measured. After signal processing the buffered output
VOUT is an exact analog representation of the primary current. To
optimize performance the Hall cells and signal processing circuits
are combined in a single CMOS ASIC (Application Specific Integrated
Circuit).

LEM DIGITAL OPEN-LOOP TRANSDUCERS

2. LEM DIGITAL OPEN-LOOP TRANSDUCERS: OVERVIEW
LEM has made a significant step forward by adding a second order sigma-delta modulator to an
improved ASIC used in a new family of transducers (figure 3). The transducer output is a bitstream
where the density of 1’s depends on the current measured, as illustrated in figure 4.
Fig. 3: HO xxx-NPW

F i g . 4: I l l u s t r a t i o n o fdigital conversion with ∑Δ
modulator

101110110010001001001110111011001000100101101111011110101001001000010000000

The detail of the transfer function is shown in figure 5. This shows the average density of 1’s on ascale from 0 to 1, and the same output if it is filtered and represented as a 16-bit word on a scalefrom 0 to 65’535 (decimal). Figure 5 also show the equivalent output from an analog transducer.
The performance of both transducer types is specified over the range +/- IPM, corresponding to an
average density of 1’s from 0.1 to 0.9 for the digital transducer and an output voltage of 0.1 to 0.9of the supply voltage for the analog type.
Digital Output
Digital Output
16-bit resolution [0,1] Normalized
32’76826’214
10’486-10’485-26’213

1.00

5.0 V
4.5 V

0.90
0.66

Fig. 5: Transfer function

3.3 V

0.50

0

-3 2’767

Analog Output
(V)

2.5 V

0.34

1.7 V

0.10

0.5 V
0.0 V

0.00
-IPM

-IPN

0

IPN

IP

IPM

The digital filter is implemented by the user, see figure 6. The advantage is that the number ofconnections to the transducer is minimized; each user can decide the filter(s) best suited to theapplication and the output format can be selected to match the system requirements.
LEM Digital Current
Transducer

IP01100011010
LEM
Transducer

LEM side

Digital Filter

Digital Filter

Out

Fig. 6: LEM provides bitstream

User side

3. ANALOG TO DIGITAL CONVERSION WITH ∑Δ MODULATORSIn general LEM current transducers are used either in control systems or measurement applications.
When there is an analog output it is generally followed by conversion to a digital representation inorder to use powerful control algorithms or for data storage. Including the A:D conversion in thetransducer is therefore advantageous for the user in many applications.

Page 2

ANALOG TO DIGITAL CONVERSION WITH ∑Δ MODULATORS

A:D converters fall into 2 broad categories: ‘Nyquist-rate’ and ‘oversampled’. In Nyquist-rate
converters the analog input is sampled at a minimum rate of 2x the input frequency and theinstantaneous value of the input is converted immediately to a digital word. In oversampledconverters the sampling rate is higher. The number of bits in each sample may be reduced. In
the case of the ∑Δ converters in the LEM transducers the analog input is typically sampled at
10.7 MHz and the digital output consists of a single bit. Therefore, in contrast to the Nyquist-rate
converter, many samples must be used in a digital filter to know accurately the value of the input.
Oversampled converters offer many advantages over Nyquist-rate, on condition that thetechnology used allows a high enough clock frequency to permit oversampling:i)		
They are well adapted to the inexpensive CMOS processes used in LEM transducers. The
precision analog components needed for Nyquist-rate converters are not available; on the other
hand, the high clock frequencies needed for oversampling can readily be generated;ii)
In all A:D converters there is quantization noise due to the difference between the quantizeddigital output and the exact value of the analog input. In ∑Δ converters this noise is pushed above
the frequency of the sampled analog input;iii)
In the LEM families of transducers only the ∑Δ modulator which generates the single bit
bitstream is implemented; the digital filter is provided by the user. This choice was made for two
reasons:		a.
As with traditional analog transducers, few connections are needed;		b.
The user can optimize the digital filter – or more than one filter – according to the			needs of a given application.
Analoginput, x

Differential
Integrator+

1-bit ADC
(comparator )-Bitstream
output, y

Clock

a)

1-bit DAC
(connection)

Fig. 7: first-order ∑Δ modulator

Q: Quantization
noise
Integrator
X

b)

+
-

ADC
(X – Y)/(1 –z -1)

X -Y

1/(1 – z-1)

1/z

(X – Y)/(z -1 ) + Q
Y

Y = (X – Y)/(z -1 ) + Q
from which:
Y = XZ-1 + Q(1 – z-1)

A first-order ∑Δ modulator is shown in figure 7a and its z-domain analysis in figure 7b. The output
is the (delayed) input plus the quantization noise Q multiplied by (1 – z-1). The term in brackets
is equivalent to differentiation, so quantization noise at low frequencies (in the signal band) is
attenuated. The high frequency noise passed by differentiation will be removed in the user’s digital
filter.
LEM transducers use a second-order ∑Δ modulator in which a second first-order modulator isembedded at the position of the ADC of figure 7. This gives several performance advantages: fora detailed analysis the reader is referred to a standard text on the subject, such as reference (1).

Page 3

FILTER AND PERFORMANCE CHOICES ON THE USER SIDE

4. FILTER AND PERFORMANCE CHOICES ON THE USER SIDEAs described above, LEM digital transducers output a bitstream containing noise whose filteredvalue corresponds to the analog input. The user processes the bitstream in a digital filter which
rejects the high frequency noise.
The noise at different stages in the complete A:D process is shown in figure 8. At (a) there is always
white noise from the analog front-end of the transducer, limited to half the sampling frequency. At (b)quantization noise is added, but only at high frequencies. (c) shows the output noise in an example
in which the digital filter has a low cut-off frequency, which is good for precision; in this case thenoise at the output is the same as when a traditional analog transducer is used with an equivalentfilter. In (d) a wide band filter is used at the output, the response time is fast and the extra noise is
not a drawback since this type of output is used to detect out-of-range currents. The versatility of
the LEM digital transducers is due to being able to connect both the (c) and (d) filter types to thesame bitstream.
(a): Analog
input

Modulator in
LEM transducer(b): Bitstream

Filter, decimationby the user(c, d): Digital
outputfSfd(a) White noise in analogi nput(b) Bitstream: addition of noisefrom the modulation process(c) Digital output with a low
decimation frequency f d(d) Digital output with a highdecimation frequency f d

Fig. 8: Noise in the ∑Δ A:D conversion process.

Typically a sinc filter of order K is used. A first-order filter which has sampled N input bits gives
as an output the average value of those bits; a Kth order filter is make by cascading K first-orderfilters – see reference 1. Figure 9 shows the frequency response of different sinc filters in which N= 384 bits and the bit rate is 10.7 Mb/s.
As with any filter, the order and bandwidth are chosen to optimize system performance. A narrow
bandwidth gives lowest noise (or highest resolution) at the expense of response time, and viceversa. In the example of figure 10 the bitstream is processed twice: in a 20 kHz filter which gives
a resolution of 12 bits for accurate measurement of the primary current and in a wideband filter todetect excess currents with a response time of 5 μs. Additionally the transducer internal OCD (overcurrent detect) output allows detection of short circuits with a response time of only 2.7 µs.

Page 4

FILTER AND PERFORMANCE CHOICES ON THE USER SIDE

Fig. 9: Response of different sinc filters.

LEM Digital Current Transducer

User side01100…

sinc 3; DR = 512

Control loop function
BW = 5.5 kHz; 11.5 bits

sinc 2; DR = 16

Out of range detection
tr = 2.5 + 3.0 = 5.5 µs

Over Current
Detection (OCD)

Short- circuit
tr = 2.7 µs

DATA
Hall

01100…
M

Function targeted
Performances obtained

OCD

Fig. 10: Application example with Decimation Ratio and filter order:
influence on response time and resolution

Packets of N bits are sampled one at a time and processed with some previous packets in thedigital filter. Due to the high modulator oversampling ratio, the digital filter output can be processed
every N bits with no loss of information within the band of interest. An output from the filter may beobtained after every N bits, and N, equal to fs/fd in figure 8, is known as the Decimation Ratio (DR).
The latency of filter depends on its architecture. Take a simple case where the output is sampled
after each packet of N bits. For a clock period TCLK the output is delayed by 2 x DR x TCLK for asinc2 and 3 x DR x TCLK for a sinc3 filter. In table 1 the bit rate at the transducer output is 10.7 Mb/s,so TCLK is 0.1 us. The combination of DR, filter choice and bit rate leads to the response time, thebandwidth and the effective resolution of each of the signal paths connected to the bitstream. The
response times are somewhat faster than the delayed output given above. Partly this is because thestandard LEM definition has been used, where the response time is between 90% of the input andoutput signals. It is further improved by reading the filter output continuously, instead of sampling
it after each packet of N bits.

Page 5

FILTER AND PERFORMANCE CHOICES ON THE USER SIDE

SINC
K

Order

31

21

11

Bit
rate
Mb/
s

Over
Sampling
Ratio (DR)M

Product
responsetime ( s)FilterResponsetime ( s)Over Current
Detection
(OCD)
( s)

Filterbandwidth
-3dB
(kHz)

LEM
effective
resolution(Bit)

Comments

0.7

10242
5122
2562
1282
64
32
16
82

.5
.5
.5
.5
2.51
2.59
2.54
.5

287.1
143.6
71.8
35.9
7.92
.0
.5
2.22

2.72
2.75
2.71
2.72
.7
2.78
2.7
.7

.7
.5
1.0
1.9
43.8
7.6
175.2
350.4

12.0
11.5
10.9
10.3
9.8
8.7
7.3
5.7

Better accuracy

0.7

10242
5122
2562
1282
64
32
16
82

.5
.5
.5
.5
2.51
2.56
2.53
.5

191.4
95.7
47.9
23.9
2.02
.0
.0
1.52

2.73
2.76
2.71
2.72
.7
2.7
2.7
.7

.3
.7
3.3
6.7
53.3
106.7
213.3
426.7

11.9
11.3
10.7
10.1
9.4
8.1
6.4
4.7

Better response time

.5
.5
.5
.5
2.56
2.53
2.51
.5

95.7
47.9
23.9
12.0
.0
.0
.5
0.72

2.74
2.78
2.71
2.73
2.76
2.7
2.7
.7

.3
.7
7.3
4.6
9.2
138.4
276.9
553.7

9.2

0.7

10242
5122
2562
1282
64
32
16
82

8.3
7.3
6.3
5.2
4.2
3.3
2.5

Fast response time

Table 1: HO 150-NPW performances: Performance = f (DR, SINC K FILTER, BANDWIDTH)

The resolution of the complete system including the analog part of the transducer, the sigma-delta
modulator and the digital filter is limited either by the quantization noise inherent to the system orby the analog noise from the Hall cells and amplifiers. For fast response times (for example witha DR = 16 and a sinc2 filter) the resolution is defined by the system and will be the same with anytransducer. If the filter is changed to sinc3 and the DR is increased the effective resolution is improved
but will be limited to 11 – 13 bits (depending on the sensor sensitivity) by analog noise. The term
“Effective” resolution is used because for system convenience the filter may output a word with alength of 16 bits or 2 x 8 bits. However only the most significant bits corresponding to the effective
resolution contain useful information, the less significant bits contain noise.
The filters used with LEM transducers may be implemented in DSP circuits or microprocessors,
giving the user complete flexibility in the design choice.

5. PHYSICAL INTERFACES
To transmit the bitstream LEM offers the choice between several physical interfaces. They fall into
3 categories:			i)Single-ended, see section 5.1;
			ii)
Differential Manchester, see section 5.2;
			iii)
Fully differential clock and data, see section 5.3.
In all cases the bit rate is 10.7 Mb/s if the internal clock of the transducer is used. If an external
clock is used the frequency range of 5 – 10.1 Mhz or 11.4 - 12.5 MHz is allowed, with the restrictionthat 10.7 MHz must be avoided (see the transducer datasheet for details).

Connection diagramm for HO xxx_PW; SW & NPW

Page 6

Connection diagramm for HLSR xx-PW

PHYSICAL INTERFACES

5.1 2W CMOS (Single-ended)
Clock and data are single-ended CMOS levels (UC and GND); the clock may be an input or an
output. This is suitable for short connections, up to some 10’s of centimeters, above which EMC
issues may become important. The maximum allowed capacitive load is 30 pF. The pin allocation
for an HLSR xx-PW, HO xxx-NPW, HO xxx-PW, HO xxx-SW transducer is shown in Table 2 andthe timing diagram in figure 10.
Pin Name
Configuration
2W CMOS(Single-ended)
CLK Out

2W CMOS(Single-ended)
CLK InProduct Name

GND

+UC

P2

P1

P7

P6

P5

OCD

HO xxx-NPW-X0XX
HO xxx-PW-X0XX
HO xxx-SW-X0XX

GND

+UC

Dout

CLK

NC

NC

GND
or NC

OCD

HLSR xx-PW-X0X

GND

+UC

Dout

CLK

-

-

-

-

HO xxx-NPW-X8XX
HO xxx-PW-X8XX
HO xxx-SW-X8XX

GND

+UC

Dout

CLK

NC

NC

GND
or NC

OCD

HLSR xx-PW-X8X

GND

+UC

Dout

CLK

-

-

-

-

Table 2: 2W CMOS (Single-ended) wiring

DOUT

Fig. 11: 2W CMOS (Single-ended)

5.2 2W RS422 or LVDS Manchester (IEEE 802.3) differential signals
This interface is suitable for transmission over longer distances in transducers where only two
output connections are available. In this case the clock and data are combined as a Manchestercoded signal. This is output on one transducer pin (P2) and its complement on another (P1). The
differential signal thus generated is compatible with the RS422 or LVDS standards. By keeping thetwo signal tracks physically close, EMC effects - both transmitted and received - can be kept to alow level. The pin allocation for both transducer families is shown in Table 3 and the timing diagramin figure 12.
Pin Name
Configuration

Product Name

GND

+UC

P2

P1

P7

P6

P5

OCD

RS422
MANCHESTERHO xxx-NPW-X1XX
HO xxx-PW-X1XX
HO xxx-SW-X1XX

GND

+UC

Dout

CLK

NC

NC

GND
or NC

OCD

HLSR xx-PW-X1X

GND

+UC

Dout

CLK

-

-

-

-

HO xxx-NPW-X3XX
HO xxx-PW-X3XX
HO xxx-SW-X3XX

GND

+UC

Dout

CLK

NC

NC

GND
or NC

OCD

HLSR xx-PW-X3X

GND

+UC

Dout

CLK

-

-

-

-

LVDS
MANCHESTER

Table 3: Manchester interfaces wiring

Page 7

PHYSICAL INTERFACES

DOUT
DOUT
Fig. 12: Manchester coded data

With a RS422 output the 1 and 0 levels are nominally UC and GND respectively and the connections
are not loaded, unless a load is needed for matching. With an LVDS output the common mode
voltage is nominally 1.25 V and the differential voltage is 350 mV peak. A floating 100 ohm load
must be provided between the differential DOUT signals.
One disadvantage however with a Manchester coded signal is that clock and data must berecoveredat the receiver side. This can be done in a FPGA or a DSP with dedicated hardware blocks.

5.3 4W CLK Out and CLK In; RS422, with direct connection and withcapacitor coupling, and LVDS standards.
In the HO xxx-NPW, HO xxx-SW AND HO xxx-PW transducers both clock and data are available
as differential signals. The transducers can be configured such that the signals are compatible with
the RS422 or LVDS standards. As with the differential Manchester output these formats create little
EMC interference. The earlier timing diagram of figure 11 applies also to these interfaces. The 1 and0 levels described for RS422 and LVDS in Section 5.2 also apply.
When the common mode level between 0.35 x UC and 0.75 UC, an external clock is provided for
the LEM transducer in RS422 mode (‘CLK IN’) a direct connection to the clock pins may be made.
If the absolute values of the incoming signal are not known the clocks may be connected with acapacitor coupling and the LEM transducer will provide the correct common-mode voltage.
Pin Name
Configuration

Product Name

GND

+UC

P2

P1

P7

P6

P5

OCD

4W RS422
CLK Out

HO xxx-NPW-X4XX
HO xxx-PW-X4XX
HO xxx-SW-X4XX

GND

+UC

Dout

Dout

CLK

CLK

GND
or NC

OCD

4W RS422
CLK In(Mode C)HO xxx-NPW-XCXX
HO xxx-PW-XCXX
HO xxx-SW-XCXX

GND

+UC

Dout

Dout

CLK

CLK

+UC

OCD

4W RS422
CLK In(Mode D)HO xxx-NPW-XDXX
HO xxx-PW-XDXX
HO xxx-SW-XDXX

GND

+UC

Dout

Dout

CLK

CLK

+UC

OCD

GND

+UC

Dout

Dout

CLK

CLK

GND
or NC

OCD

GND

+UC

Dout

Dout

CLK

CLK

+UC

OCD

4W LVDSCLK Out
4W LVDS
CLK InHO xxx-NPW-X2XX
HO xxx-PW-X2XX
HO xxx-SW-X2XX
HO xxx-NPW-XAXX
HO xxx-PW-XAXX
HO xxx-SW-XAXX

Table 4: 4W RS422 or LVDS, CLK Out and CLK Inconnections

Page 8

Dout Single

PHYSICAL INTERFACES

CLK

P5

P6

P7

GND +UCP2

P1

100 Ohm
not mandator

Dout

P1

CLK

OCD
P4
100 Ohm
not mandator

Dout

P2

Dout

+UC

GND

GND +UC

+Uc

CLK
P7

+UC

CLK
P6

CLK_Single

RS422 RECEIVER
_
+

GND

GND
or NC
P5

P4

CLK_Single

+
_

OCD

+
_

Dout

RS422 RECEIVER+_

RS422 RECEIVER

Dout Single

RS422 RECEIVER

4W RS422 CLK In with capacitor coupling

RS422 RECEIVER

P8

P7

P6

P5

P1

P2

P3

P4

GND

+UC

Dout
Dout

100 pF
mandatory

UC or GND
or nc

CLK

OCD

CLK_Single

CLK

_
+

100 Ohm
not mandatory

Dout Single+_
RS422 RECEIVER

P7
100 Ohmmandatory
P1

Dout

Dout

GND

+UC

P2

3.5 mA+_

GND +UCLDVS DRIVER+_

Dout Single

LVDS RECEIVER

P4

CLK

+Uc

CLK

3.5 mAP5

P6P7

GND +UCP2

P1

100 Ohmmandatory

Dout

P6

CLK_Single

OCD

CLK

CLK_Single

+UC

P5

+
_

GND

P4

CLK

OCD

GND
or NC

3.5 mADout

LVDS RECEIVER

3.5 mA+_

Dout Single

RS422 RECEIVER

Fig. 13: Four wire RS422 and LVDS interfaces. The load resistors are optional in all the RS422 examples.

Page 9

DELAY VS FILTER

6. DELAY VS FILTER: EXAMPLE
As described in section 4, the combination of DR, filter choice and bit rate determines the response
time, the bandwidth and the effective resolution of each of the signal paths connected to the
bitstream.
The following simulations illustrate this trade-off in the time domain to optimize system performance:a narrow bandwidth gives lowest noise (or highest resolution) at the expense of response time, andvice versa.
The “digital delay” between the primary signal and the output signal due the filter is constant ineach case. This property makes easy to correct for the delay by shifting the signal in time.
DR

DR

DR

Fig. 14: Simulation
Filter (sinc2), DR vs.
Delay

Constant delay
Correct value

DR

DR

DR

Fig. 15: Simulation
Filter (sinc3), DR vs.
Delay

7. REFERENCES(1): Understanding Delta-Sigma Data Converters’; Schreier and Temes; Wiler Interscience; ISBN
0-471-46585-2.

DIGITAL OUTPUT TRANSDUCERS AND ∑Δ CONVERSION

101110110010001001001110111011001000100101101111011110101001001000010000000

Page 10