TECHNICAL DATA SHEET

Quartz 7053
8-channel A/D & D/A PCIe board
with Xilinx Zynq UltraScale+ RFSoC - Gen 3Quartz PCIe board brings
RFSoC performance toPC platforms▪ High-bandwidth data streaming▪ Waveform signal generator▪ Analog I/O for digital recording andplayback▪ Communication receiver and transmitter▪ Sensor interfaces▪ Electronic Warfare transponder

The Quartz ® 7053 is a high-performance PCIe board based on theXilinx ® Zynq ® UltraScale+™ RFSoC. The RFSoC integrates eight RFclass A/D and D/A converters into the Zynq’s multiprocessor
architecture, creating a multichannel data conversion and processing
solution on a single chip.
The 7053 brings RFSoC performance to PCIe with a complete system on a board.
Complementing the RFSoC’s on-chip resources are the 7053’s sophisticated clocking section
for single board and multiboard synchronization, a low-noise front end for RF input andoutput, up to 16 GBytes of DDR4, a PCIe interface, a GPS receiver, a gigabit serial opticalinterface capable of supporting user installed protocols and general purpose serial andparallel signal paths to the FPGA.
The 7053 board design places the RFSoC as the cornerstone of the architecture. Allcontrol and data paths are accessible by the RFSoC’s programmable logic and processing
system. A full suite of Mercury-developed IP and software functions utilize thisarchitecture to provide data capture, timing, and interface solutions for many of the mostcommon application requirements.

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Quartz 7053

FEATURES▪ Incorporates Xilinx® Zynq® UltraScale+™ RFSoC▪ 16 GB of DDR4 SDRAM▪ On-board GPS receiver▪ PCI Express (Gen. 1, 2 and 3) interface up to x8▪ LVDS connections to the RFSoC for custom I/O▪ Optional front panel dual optical MPO interface for gigabit
serial communication▪ Unique QuartzXM eXpress Module enables migration tocustom form factors▪ Navigator® BSP for software development▪ Navigator® FDK for custom IP development▪ Free lifetime applications support

EXTENDABLE IP DESIGN

diagrams, all source code and complete IP core documentation
is included. Developers can integrate their own IP along with thefactory-installed functions or use the Navigator kit tocompletely replace the Mercury IP with their own.
The Navigator Board Support Package (BSP), the companion
product to the Navigator FDK, provides a complete C-callable
library for control of the 7053’s hardware and IP. The Navigator
FDK and BSP libraries mirror each other where each IP function
is controlled by a matching software function, simplifying thejob of keeping IP and software development synchronized.
The Navigator BSP includes support for Xilinx's PetaLinux runningon the ARM Cortex-A53 processors. When running under
PetaLinux, the Navigator BSP libraries enable complete control ofthe 7053 either from applications running locally or on the ARMs,or using the Navigator API control and command from remotesystem computers.

For applications that require specialized functions, users caninstall their own custom IP for data processing. Mercury’sNavigator FPGA Design Kit (FDK) includes the board’s entire
FPGA design as a block diagram that can be edited in Xilinx’s
Vivado® IP Integrator. In addition to the IP Integrator block

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Balun

Balun

RF In 8

RF Out 1

RF Out 2Balun

JTAG

Antenna InBalun

RF Out 7

RF Out 8Balun

Balun

RF In 7

RF Out 6Balun

RF In 6Balun

BalunRF Out 5Balun

RF In 5Balun

Balun

RF In 4Balun

Balun

RF In 3

RF Out 3Balun

RF Out 4Balun

RF In 1

Timing Bus
Generator

RF In 2Gate / Trigger

Reference Sync

Reference Clk

Sample Clk

Frequency
Synthesizer

RF Out 2
through 7

RF In 2through 7

SysRef

D/A Clocks

A/D Clocks

GPS

D/A Output
1 -8

A/D Input
1 -8

Programmable
Logic

ZYNQ
UltraScale+
RFSoC FPGA64

DDR4
SDRAM
4/8 GB

GTY

LVDS

GTY

Processing
System

GTR

GTR

GTR

GTR

JTAG

POWER
Battery
MANAGEMENTManagement

Model 7053 Quartz PCIeVPX VBAT

Battery

X8DDR4SDRAM
4/8 GBConfig
FLASH

X24X864RS-232

1 GigEUSB 3PowerManagement

Model 6003 QuartzXM eXpress Module9.85 GHz
14-BIT
D/A & DUC
Channels
1-85 GHz
14-bitA/D & DDC
Channels
1-8

RF Signal
Chain

Clock
Management

SD
Card

AXI4 Clock

LVDS GPIO

PCIeGen. 3 X8RS-232

1 GigEUSB 312 V

Gate

Sync

X8 25 Gb/sec Optical
Transceiver(Optional)

12 V

toTiming Bus
Generator

Sample Clock
SysRef

MPO

LVDS
GPIO

PCIe

RS-232

1 GigEUSB 312V
PowerSync
Bus

TECHNICAL DATA SHEET
Quartz 7053

7053 BLOCK DIAGRAM

Click on a block for more information.

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Quartz 7053

A/D CONVERTER STAGE

MEMORY RESOURCES

The board's analog interface accepts analog IF or RF inputs on eight
front panel MMCX connectors with transformer-coupling into the RF
signal chain of the RFSoC. Inside the RFSoC, the analog signals arerouted to eight 5 GSPS, 14-bit A/D converters. Each converter has
built-in digital downconverters with programmable 1x, 2x, 3x, 4x 5x,6x, 8x, 10x, 12x, 16x, 20x, 24x, or 40x decimation and independenttuning. The A/D digital outputs are delivered into the Zynq’s
programmable logic and processor system for signal processing,data capture or for routing to other resources.

The 7053 architecture supports 8 GB of DDR4 SDRAM memory
accessible from the Programmable Logic. User-installed IP,
which, along with the Mercury-supplied DDR4 controller core
within the FPGA can take advantage of the memory for custom
applications. An 8 GB bank of DDR4 SDRAM is available to theProcessing System as program memory and storage.

In addition to the A/D’s built-in decimation, an additional stageof IP-based decimation provides another 16x stage of data
reduction, ideal for applications that need to stream data fromall eight A/Ds.

D/A CONVERTER STAGE
The RFSoC’s eight D/A converters accept baseband real orcomplex data streams from the FPGA’s programmable logic.
Each 9.85 GSPS, 14-bit D/A includes a digital upconverter withindependent tuning and interpolations of 1x, 2x, 3x, 4x, 5x, 6x,8x, 10x, 12x, 16x, 20x, 24x, or 40x. Each D/A output istransformer coupled to a coax connection located on the frontpanel.

CLOCKING AND SYNCHRONIZATIONThe 7053 front panel includes inputs for sample clock,reference clock, reference sync and gate/trigger. In addition tothe front panel, a multi-pin Sync Bus connector on the rear of
the board provides a single cable connection to the Model 9103
High-Speed System Synchronization and Distribution Amplifier
for synchronizing up to 8 7053s in larger, multichannel systems.

PCI EXPRESS INTERFACEThe Model 7053 includes an industry-standard interface fullycompliant with PCI Express Gen. 1, 2 and 3 bus specifications.
Supporting PCIe links up to x8, the interface includes multiple
DMA controllers for efficient transfers to and from the module.

GPSA GPS receiver provides time and position information to theFPGA and ARM processors. This information can be used for
precise data tagging. The GPS provides a 1 PPS and a reference
clock to the FPGA.

EXPANDABLE I/O
The Model 7053 supports up to eight 25 Gb/sec full duplex
optical lanes to a pair of front panel MPO connectors. With theinstallation of a user-provided serial protocol, the opticalinterface enables gigabit communications between boards
independent of the PCIe interface. Twelve pairs of LVDSconnections are provided between the FPGA and a card edge
connector for custom I/O. In addition to the front panel analog
I/O connectors, the 7053 includes connectors for USB 3, 1 GigE,
RS-232, JTAG and a GPS antenna.

The on-board timing bus generator uses these signals, inaddition to a frequency synthesizer, to create the required A/Dand D/A clocks and a SysRef for operation of the data
converters. The timing bus generator supports an internal clockmode where the sample clock is driven by the programmablefrequency synthesizer and no additional clock needs to beprovided. In an alternate mode, the on-board sample clock canbe synchronized to a 10 MHz reference clock received through afront panel connector. The Model 7053 can also accept anexternal sample clock through this front panel connector. Thismode bypasses the on-board sample clock. A multifunction
gate/trigger input is available on the front panel for external
control of data acquisition and playback.

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Quartz 7053

FLEXIBLE MODULAR DESIGN
While the Quartz 7053 follows the form factor of a standard PCIeboard, the unique modular design of Mercury’s Model 6003
QuartzXM eXpress Module provides the flexibility to deploy thissolution in many different situations. The heart of the QuartzXM
is a system on module containing all of the key components
including the RFSoC, DDR4 SDRAM, and power and clock
management.
In the case of the 7053, the QuartzXM is mounted on a PCIe carrier
which complements the design with a timing bus generator, analog
signal conditioning, a GPS receiver and an 8x 25 Gbps opticaltransceiver. As a module and carrier board set, the 7053 becomes acomplete, ready-to-deploy PCIe solution.

The Model 6003 QuartzXM can also be mounted on othercarriers available from Mercury to support standard form
factors, or for applications that require a non-standard
footprint, Mercury supports the module with a design kit forusers to engineer and build their own custom carrier. As acomplete and tested module, the QuartzXM encapsulates bestin-class electrical and mechanical design, eliminating some of
the most challenging aspects of embedded circuit design andallowing the user to focus on the application specific carrier
design.

QuartzXM eXpress Module

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TECHNICAL DATA SHEET
Quartz 7053

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.
The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design
Suite includes the complete Vivado project folder for each Jadeproduct with all design files for the factory-installed FPGA IP.
Vivado’s IP Integrator is a graphical design entry tool that visuallypresents the complete block diagram of all IP blocks so thedeveloper can access every component of the Jade design.
Developers can quickly import, delete, and modify IP blocks andchange interconnection paths using simple mouse operations.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP coreis a mouse click away, and fully consistent with Xilinx IP cores.
The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational
control of all hardware functions on the board and IP functionsin the FPGA. The BSP structure is designed to complement thefunctions of the FDK by maintaining a one-to-one relationshipbetween FDK and BSP components. For each IP block found in
the FDK library, a matching software module can be found in
the BSP. This organization simplifies the creation and editingof software to support new IP functions and modifications toexisting IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade boardand Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEET
Quartz 7053

SPECIFICATIONS

D/A Converters

Gate/Trigger

Field Programmable Gate Array▪ Quantity: 8▪ Sampling Rate: (standard) 8.92 GHz▪ Source: Programmable throughsoftware or external source▪ With -2 speed grade (option 002): 9.85 GHz▪ Location: Front panel (for externalsource)

Type: (standard) Xilinx Zynq
UltraScale+ RFSoC XCZU47DR▪ Option -048: Xilinx Zynq
UltraScale+ RFSoC XCZU48DR▪ Resolution: 14 bits

▪ Connector Type: MMCX

Speed: (standard) -1 speed grade

Digital Upconverters▪ Level: TTL▪ Option -002: -2 speed grade▪ Quantity: 1 per D/AGPS▪ Interpolation Range: 1x, 2x, 3x, 4x,5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x,
and 40x (not all interpolations aresupported by default IP)▪ Source: On-board▪ LO Tuning Freq. Resolution: 48bits

Sync BusRFSoC RF Signal Chain
Analog Inputs▪ Quantity: 8▪ Connectors: MMCX
▪ Location: Front panel▪ Input Type: Transformer-coupled▪ Transformer Type: Mini-Circuits
TCM1-83X+▪ Full Scale Input: +10 dBm into 50 ΩA/D Converters▪ Quantity: 8▪ Sampling Rate: 5.0 GHz▪ Resolution: 14 bits
Digital Downconverters▪ Quantity: 1 per A/D▪ Decimation Range: 1x, 2x, 3x, 4x,5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x,
and 40x (not all decimations aresupported by default IP)▪ LO Tuning Freq. Resolution: 48bits, 0 to ƒs▪ Signals: Sample Clock, Reference
Clock, Reference Sync,Gate/Trigger

Sample Clock▪ Location: Rear edge of card

▪ Source: On-board programmableclock source or external clocksource▪ Connector Type: Multi-pin, highspeed differential▪ Location: Front panel (for externalsource)▪ Level: -10 dBm to +10 dBm frontpanel▪ Speed: 1.5 GHz
ARM Cortex-R5:

Reference Clock▪ Quantity: 2▪ Source: On-board oscillator, onboard GPS, or external source▪ Speed: 600 MHz▪ Location: Front panel (for externalsource)

Reference Sync

▪ Quantity: 8▪ Source: Programmable throughsoftware or external source▪ Transformer Type: Mini-Circuits
TCM1-83X+

ARM Cortex-A53:▪ Quantity: 4Analog Outputs▪ Input Type: Transformer-coupled

RFSoC Processing System▪ Connector Type: MMCX

▪ Connector Type: MMCX

▪ Location: Front panel▪ Connector Type: SMA▪ Filter: 80% pass band, 89 dB stopband attenuation▪ Filter: 80% passband, 89 dB stopband attenuation▪ Connectors: MMCX

▪ Antenna Connector Location:
Front panel▪ Level: -10 dBm to +24 dBm▪ Location: Front panel (for externalsource)▪ Connector Type: MMCX
▪ Level: TTL

Custom FPGA I/OParallel: 12 pairs of LVDS connections
between the FPGA and a top
accessible ribbon cable connector
Optical (Option -110): 8X full duplex
lanes @ 25 Gb/sec available on front
panel MPOs

MemoryProcessing System:▪ Type: DDR4 SDRAM▪ Size: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)

▪ Full Scale Output: 0 dBm into 50 Ωmrcy.com8TECHNICAL DATA SHEET
Quartz 7053

Programmable Logic:Options

Description▪ Size: 8 GB

-002

-2 FPGA speed grade, -1 standard▪ Speed: 1200 MHz (2400 MHz DDR)

-048

XCZU48DR FPGA (XCZU47DR is standard)▪ FPGA Configuration FLASH: 2x 1 Gb QSPI-110

MPO 8X optical interface-701

Air-cooled, Level L1▪ Type: DDR4 SDRAM

PCI-Express Interface
PCI Express Bus: Gen. 1, 2 or 3: x4 or x8

Environmental

Contact Mercury for compatible option combinations.

ACCESSORY PRODUCTS

Option -701: L1 (air-cooled)▪ Operating Temp: 0° to 50° CModelDescription▪ Storage Temp: –40° to 100° C

2172

Cable Kit: MMCX to SMA▪ Relative Humidity: 0 to 95%, non-condensing

5903

High- Speed System Synchronization and Distribution
AmplifierPhysicalDimensions:2-slot PCIe
▪ Width: 1.6 in. (40.6 mm)

LIFETIME SUPPORT FOR QUARTZ PRODUCTS▪ Depth: 8.5 in. (215.9 mm)

Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reducedcosts, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

▪ Height: 4.9 in. (124.5 mm)

ORDERING INFORMATION
ModelDescription

7053

8-Channel A/D & D/A Zynq UltraScale+ RFSoC Gen 3Processor - PCIe

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury InternationalLearn more

Avenue Eugène-Lance, 38PO Box 584
CH-1212 Grand-Lancy 1Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF7053

Visit: mrcy.com/go/MP7053+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Quartz and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2022 Mercury Systems, Inc. 1-0-102822-DS-Q7053

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