Parallel Processing Using FPGAs
Shaswot Shresthamali
Department of Electronics and Communication Engineering,
Sagarmatha Engineering College, Tribhuvan University
Sanepa, Lalitpur
shaswot@sagarmatha.edu.np
Abstract—This
document
introduces
FPGAs(FieldProgrammable Gate Arrays) and highlights their parallel
processing capability. FPGAs are reprogrammable hardware
chips for implementation of digital logic. Their reconfigurability
is attributable to the presence of configurable logic slices andinterconnects. The possibility of hardware configuration inFPGAs allows the designer to design multiple modules that run
parallel and independently to each other. This paper discusses
how FPGAs offer true hardware parallelism and deliberates onsome areas which benefit from FPGAs’ parallel processing suchas DSP (Digital Signal Processing), Data Acquisition andProcessing, Text Parsing and Image/Video Processing. To
demonstrate the possibility and the consequent advantages ofparallel processing, a matrix multiplier was designed for aSpartan-3E FPGA with the help of High Level Synthesis (HLS)
tools. Two possible solutions, with and without parallel
processing, were obtained which are briefly discussed here.
Index Terms—FPGA, Parallel Processing, Spartan-3E FPGA,DSP, HLS.

I. INTRODUCTION
The sheer volume of information to be processed in today’s
world has risen exponentially with time. This has led to thedevelopment of faster processor cores with higher clock
speeds. Now the paradigm is shifting to multi-core processors.
A good example of this would be Intel’s i3, i5 and i9
processors with multiple cores on a single chip.
Although parallel processing is possible using multiple
cores, their cost and power consumption are major issues intheir practical application. Achieving parallel processing usinga single microprocessor with a single core is an avenue thathas been extensively researched. Numerous pipelining
algorithms have been developed to achieve the fastest
throughput – however, the fact remains that a single processor
can execute only one instruction at a time.
In contrast, FPGAs (Field Programmable Gate Arrays) canoffer true parallelism in processing. They can be configured tohave multiple processors functioning in parallel.
Another fundamental difference between FPGAs andmicroprocessor processing is in the approach to processing.
Microprocessors are almost exclusively based on the Von
Nuemann architecture or the Harvard architecture. Both thesearchitectures have a common feature in that the processors
have to fetch data and the instructions to process the data i.e.
they use a stored program concept. However, FPGA
processing is purely hardware based processing – there is no
fetching of instructions required; the program description

determines the configuration of the hardware itself i.e. theprocessing is implemented in hardware rather than software.
A. Introduction to FPGAFPGAs are configurable silicon chips that can be
configured to mimic any type of digital circuitry. They consistof CLBs (Configurable Logic Blocks) and highly flexible
programmable interconnects.
The CLBs consist of LUTs (Look-Up Tables), wide
multiplexers and storage elements (usually D flip-flops). TheLUTs (usually with three to five inputs) can be configured toperform any Boolean function. The use of multiplexers allow
for combination of LUTs to increase the input width of theCLB.
The interconnections between different CLBs is
accomplished using an interconnect matrix or a global routingmatrix. These interconnect matrices are configurable andallows for high flexibility in the interconnection between
different CLBs.
FPGAs also come with configurable IOBs (Input OutputBlocks) to comply with a large number of standards like
LVTTL, LVCMOS, HSTL etc.
Modern FPGAs have other silicon hardcores built in tofacilitate better designs and higher speeds. For instance, theSpartan-6 FPGAs from Xilinx consist of DCM (Digital ClockManager), block RAM, gigabit transceivers, and theDSP48A1 slice in addition to the CLBs and IOBs. It supports
upto 147K logic cell density, 3.2 Gigabits/sec integrated serialtransceivers.
FPGAs are configured using HDL (Hardware DescriptionLanguage) such as Verilog, VHDL or System Verilog. TheHDL is synthesized and then implemented onto the FPGA
using mapping and PAR (Place and Route) tools.
Another method for generation of HDL codes is via HLS.
The generation of synthesizable HDL codes from high level
languages such as C, C++ or System C is termed as HLS.
Xilinx Vivado HLS 2013.4 is one such HLS tool. Xilinx
Vivado HLS 2013.4 is used to convert high level descriptionsof a design into Register Transfer Language (RTL) netlist
which is then implemented on the FPGA.
The use of HLS for generation of synthesizable HDL
allows the designer to create multiple ‘solutions’ for a defined
design objective, allowing the designer to explore design
trade-offs and arrive at an optimal solution.
II. PARALLEL PROCESSING USING FPGASFPGAs exhibit true parallel process execution. Each
independent task is assigned to a different area of the chip.
Each task performs autonomously without having to shareresources with other simultaneous processes. Adding moreparallel threads will not affect any of the existing processes
either. The amount of parallelism in FPGA is limited only by
the amount of physical chip space available.
A. Hardware Flexibility
Implementing designs in FPGAs means that the designer isdesigning the hardware using FPGA. They are not restricted toany predetermined hardware architecture or function. An
FPGA allows the designer to program product features andfunctions, adapt to new standards, and reconfigure hardware
for specific applications even after the product has been
installed in the field – hence the name “fieldprogrammable”.[1]Since FPGA configuration implies actual hardwareconfiguration, the designer has many options on which tocustomize the design. The I/O pins can be configured
according to the designer’s convenience. Even the data bus
width can be made arbitrarily wide depending upon the design.
The FPGA Architecture provides the flexibility to create a
massive array of application specific ALUs that enable both
instruction and data level parallelism. Because data flows
between operators, there are no inefficiencies like processor
cache misses; FPGA data can be streamed between operators.
The parallelism offered by FPGA architecture can be easily
seen in HPC (High Performance Computing) – relevant
parameters like Internal ALU bandwidth is in the order of terabytes/sec(TB/sec)
 Integer operation throughputs are in the order of Teraoperations/sec (TOPS) Floating point operations are in the order ofgigaflops/sec (GFLOPS) [2].
B. FPGAs as Co-processors
Instead of completely replacing CPUs, FPGAs can also
play the role of co-processors. The use of such co-processors
can unload some of the burden from CPUs for specificprocessing tasks. FPGAs are attractive co-processors becauseof the potential for tailored design and parallelism. FPGAs arealso very interesting in regard to power consumption as they
consume significantly less power, yet have performancecomparable to conventional CPUs. This makes FPGAs goodcandidates for implementing cores in multi-core systems
where certain data processing tasks can be off loaded from themain CPU [3].
C. Design Trade-offs
FPGAs have uncommitted logic resources along withothers that can help developers directly steer module-tomodule hardware infrastructure and trade off resources andperformance by selecting the appropriate level of parallelism
to implement an algorithm [4]. One can trade between speed
and power consumption when designing with FPGAs. This
makes it very popular in low power applications.

D. System Latency
Use of FPGAs also decreases a lot of latency time that isinevitable in processors. Significant amount of time isconsumed when moving data between memories (like RAMand cache) and between ALU and memory. The cycles used inprocessors for data transfer between memory elements andALU can be utilized effectively for processing in FPGAs.
FPGAs can bypass a lot of other system latency. With aconventional processor, a system might be receiving data via aTCP socket onto an Ethernet chip, but that then has to go
through a MAC layer, then a North Bridge chip, then onto theprocessor main bus, then an interrupt has be flagged, then all
the data has to be transferred into the user space. All thesethings can of course be done very quickly but there arenonetheless a lot of steps to go through that do not apply toFPGAs [5].
III. APPLICATION OF FPGA PARALLEL PROCESSING
FPGAs were originally used as glue logic but now theirfunctionality and application has taken giant strides in therecent years. Their parallel processing capability has madethem a popular tool in various areas.
A. Digital Signal Processing(DSP)
DSP requires massive amounts of parallel computation.
This makes it very suitable for its implementation in FPGAs.
Now-a-days, most FPGAs have built in DSP slices to assist inDSP. Some of the major areas where DSP can beimplemented using parallel processing of FPGAs arediscussed as follows.
1) MAC (Multiply and Accumulate) Blocks: DSP use
MAC blocks extensively. A DSP expression usually is of theform:Y[k] = ∑c[k].x[k]The multiplication of a coefficient c[n] with an input
sequence x[n] is accomplished by using a shift-and-add
approach in microprocessors. An FPGA outperforms a DSP
processor by performing multiplication and accumulation
steps in parallel. Even more optimized implementation ofMAC can be achieved by using distributed arithmetic [6] – [8]and FPGAs.
2) FFT:FFT that is accomplished using butterfly
techniques benefit from using parallel processing. The various
butterfly stages can be computed in parallel to get to the resultfaster.
High-speed FFT cores have become an essential requirement
for real time spectral monitoring and analysis. As themonitoring bandwidth grows with higher frequency spectrums,systems must be designed to convert time domain signal tofrequency domain faster – necessitating faster FFT operations.
In most modern systems, parallel FFTs run parallel at
extremely high sample rates (12.5 Gigasamples/sec) taking
advantage of wideband A/D converters.

3) Digital Filters: Digital filtering requires significant
amounts of multiply/accumulate operations. FIR and IIR
filters use shift registers and tap delays that can be easily
realized using the resources in FPGAs. Direct Form I andDirect Form II realization of IIR filters benefit immenselyfrom parallel processing capability of FPGAs.
B. Data Acquisition/Logging(DASs) Data Acquisition Systems consist of multiple
inputs that need to be processed. A processor is unable tocapture the data from various inputs and sensors
simultaneously. It uses pipelining and memory buffering toachieve this. In addition, each different input will require adifferent type of processing – hence the processor will have toload new instructions for each sensor’s input data.
Using FPGAs can overcome many of the shortcomings ofusing a single processor for DAS systems. The FPGA can be
configured to have independent signal processing ALUs foreach of the sensor inputs. In addition, the large number of pins
available in an FPGA combined with its hardware
configurability allows it to accept and process the signals frommultiple sources simultaneously.
C. Text Parsing
The parallelism of FPGAs is perfectly suited for high speed
text parsing where multiple newsfeed must be screened for ahuge number of keywords.
Using processors to achieve this would be quite inefficientand would require multiple processors. This would not only
increase the cost of the system but also the power
consumption.
As the number of keywords to be identified increases, theprocessor performance degrades appreciably as compared toFPGAs. While precise figures vary with implementation, aCPU will take approximately 100 times longer than FPGAs toparse a text for fifty expressions. [5]
D. Image/Video Processing
Although the power of CPUs has increased, image andvideo processing still require algorithms that are accelerated
by DSP, RISC and FPGAs.
Image and video data occupies a large bandwidth andusually requires parallel processing. Dataflow architectures
are usually based on this requirement and are designed so as
to unburden the image and video processing load from theCPU. Processes such as filtering, colour correction and noise
suppression are computationally intensive, requiring highbandwidth and parallel processing. This can be implemented
using FPGAs as coprocessors to CPUs to deliver faster results
and more efficient use of resources.
IV. RESULTS
To demonstrate the advantages of using FPGAs for parallel
processing, a 32-bit signed integer 3x3 matrix multiplication
was implemented in a Xilinx Spartan-3E XC3S5000E-FG3204 FPGA.

Xilinx Vivado HLS 2013.4 was used to generate the RTL
description followed by its synthesis. Two different solutions
were generated for the possible synthesis and implementationof the design. In solution 1, no pipelining was implemented.
The second solution, solution 2, used the pipeline directive toensure maximum hardware parallelism during theimplementation of the hardware. The synthesis estimates areillustrated in Tables I, II and III.
It is very clear from the synthesis estimates that the latencyof the multiplier has been reduced dramatically from 133
clock cycles in the first solution to just nine clock cycles in thesecond solution (Table II). This has been achieved at the costof more hardware. For instance, while only three multipliers
are employed in the first solution, the second solution employs
81 multipliers (Table III).
In short, in Solution 2, the use of multiple multipliers andother associated hardware in parallel allowed for fastercomputation of results.
TABLE I
TIMING ESTIMATESClockDefault

Solution 1

Solution 2

Target20.00 ns

20.00 ns

Estimated

16.94 ns

16.94 ns

TABLE IILATENCY ESTIMATES
Solution 1
LatencyInterval

Solution 2

Minimum

133 clock cycles

9 clock cycles

Maximum

133 clock cycles

9 clock cycles

Minimum

134 clock cycles

6 clock cycles

Maximum

134 clock cycles

6 clock cycles

TABLE IIIRESOURCE UTILIZATION ESTIMATES
Solution 1

Solution 2

18K Block RAM

00

Flip Flops

155

1445

LUTs

137

1638

18x18 Multipliers

381

V. CONCLUSION
The use of FPGAs for implementing digital systems
provides designers with a high degree of flexibility. A
designer who implement designs in FPGAs has the advantage
to reconfigure the hardware in order to trade between
performance and resource utilization depending upon thedesign resources and constraints. Power consumption,
processing speed and chip area can each be traded for anotherto come to an optimized solution.
Computer architecture is changing towards heterogeneous
multi-core systems to achieve computational parallelism on

the massive amounts of input data. This is a challenge for both
hardware and software designers.
FPGAs have a considerable share of the silicon market andare finding more areas of applications every day. FPGAs will
dominate a lot of the applications where application specific
ALUs will be required. Their hardware configurability andparallel computational capability will play a critical role in theimplementation of multi-core computational paradigm.
FPGAs already have demonstrated their success inapplication specific processing systems owing to theirparallelism and high speed computation. Although FPGAs
may not replace CPUs completely, they will play a very
important role as co-processors to increase the computational
ability of processors.
ACKNOWLEDGMENT
I wish to acknowledge the Department of Electronics
Engineering at Sagarmatha Engineering College, Sanepa forproviding me with the resources to help me prepare this paper.
I am grateful towards Mr. Deepesh Man Shakya for hisadvice, support and encouragement.
I also wish to thank Mr. Dil Bahadur Chettri for his
valuable comments.
REFERENCES[1] Altera
Websiteon
FPGA.
[Online].
Available:
http://www.altera.com/products/fpga.html[2] Prasanna Sundararajan, High Performance Computing Using FPGAs.
[3] Rene Mueller, Jens Teubner and Gustavo Alonso, Data Processing onFPGAs.

[4] Shuai Chey, Jie Liz, Jeremy W. Sheaffery, Kevin Skadrony and John
Lachz, Accelerating Computer-Intensive Applications with GPUs andFPGAs[5] AutomatedTraderWebsite.
[Online].
Available:
http://www.automatedtrader.net/articles/spotlight/514/fpgas-_-parallelperfection.html[6] G.R. Goslin, A Guide to Using FPGAs for Application-Specific Digital
Signal Processing. Available: www.xilinx.com/appnotes.dspguide.pdf[7] L. Minster, The Role of Distributed Arithmetic in FPGA-based signal
processing, Available: http://home.att.net/~pcuenin/theory1.pdf[8] B. New, A distributed arithmetic approach by designing scalable DSP
chips, EDN, Aug. 17, 1995.

Shaswot Shresthamali was born in
Kathmandu, Nepal, in 1989. Hereceived his B.E. degree in electronics
and communication engineering fromTribhuvan University, Nepal in 2012.
Following his graduation, he joined theDepartment of Electronics andCommunication
EngineeringinSagarmatha Engineering College as an Assistant Lecturer. In2013, he started ‘Xilinx Research Laboratory’ in Sagarmatha
Engineering College of which he is also the Lab Coordinator.
He is presently an Assistant Professor and the Research
Coordinator of Sagarmatha Engineering College.
His current research interests include Audio Digital Signal
Processing, FPGAs, Programmable Logic and VLSI Design.
He is also a member of IEEE Solid State Circuits Society as
well as the IEEE Robotics and Automation Society.