TECHNICAL DATA SHEET

Quartz 7050
8-channel A/D & D/A PCIe board
with Xilinx Zynq UltraScale+ RFSoC - Gen 1

Quartz PCIe board brings
RFSoC performance toPC platforms▪ High-bandwidth data streaming▪ Waveform signal generator▪ Analog I/O for digital recording andplayback▪ Communication receiver and transmitter▪ Sensor interfaces▪ Electronic Warfare transponder

The Quartz ® 7050 is a high-performance PCIe board based on theXilinx ® Zynq ® UltraScale+™ RFSoC. The RFSoC integrates eight RFclass A/D and D/A converters into the Zynq’s multiprocessor
architecture, creating a multichannel data conversion and processing
solution on a single chip.
The 7050 brings RFSoC performance to PCIe with a complete system on a board.
Complementing the RFSoC’s on-chip resources are the 7050’s sophisticated clocking section
for single board and multiboard synchronization, a low-noise front end for RF input andoutput, up to 16 GBytes of DDR4, a PCIe interface, a GPS receiver, a gigabit serial opticalinterface capable of supporting user installed protocols and general purpose serial andparallel signal paths to the FPGA.
The 7050 board design places the RFSoC as the cornerstone of the architecture. Allcontrol and data paths are accessible by the RFSoC’s programmable logic and processing
system. A full suite of Mercury-developed IP and software functions utilize thisarchitecture to provide data capture, timing, and interface solutions for many of the mostcommon application requirements.

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TECHNICAL DATA SHEET
Quartz 7050

FEATURES▪ Incorporates Xilinx® Zynq® UltraScale+™ RFSoC▪ 16 GB of DDR4 SDRAM▪ On-board GPS receiver▪ PCI Express (Gen. 1, 2 and 3) interface up to x8▪ LVDS connections to the RFSoC for custom I/O▪ Optional front panel dual optical MPO interface for gigabit
serial communication▪ Unique QuartzXM eXpress Module enables migration tocustom form factors▪ Navigator® BSP for software development▪ Navigator® FDK for custom IP development▪ Free lifetime applications support

EXTENDABLE IP DESIGN

diagrams, all source code and complete IP core documentation
is included. Developers can integrate their own IP along with thefactory-installed functions or use the Navigator kit tocompletely replace the Mercury IP with their own.
The Navigator Board Support Package (BSP), the companion
product to the Navigator FDK, provides a complete C-callable
library for control of the 7050’s hardware and IP. The Navigator
FDK and BSP libraries mirror each other where each IP function
is controlled by a matching software function, simplifying thejob of keeping IP and software development synchronized.
The Navigator BSP includes support for Xilinx's PetaLinux runningon the ARM Cortex-A53 processors. When running under
PetaLinux, the Navigator BSP libraries enable complete control ofthe 7050 either from applications running locally or on the ARMs,or using the Navigator API control and command from remotesystem computers.

For applications that require specialized functions, users caninstall their own custom IP for data processing. Mercury’s
Navigator FPGA Design Kit (FDK) includes the board’s entire
FPGA design as a block diagram that can be edited in Xilinx’s
Vivado® IP Integrator. In addition to the IP Integrator block

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Balun

Balun

Balun

Balun

Balun

Balun

Balun

Balun

Balun

Balun

Balun

Balun

Balun

RF In 5

RF In 6

RF In 7

RF In 8

RF Out 1

RF Out 2

RF Out 3

RF Out 4

RF Out 5RF Out 6

RF Out 7

RF Out 8

JTAG

Antenna InBalun

RF In 3Balun

RF In 4Balun

RF In 1

Timing Bus
Generator

RF In 2Gate / Trigger

Reference Sync

Reference Clk

Sample Clk

Frequency
Synthesizer

RF Out 2
through 7

RF In 2through 7

SysRef

D/A Clocks

A/D Clocks

GPS

D/A Output
1 -8

A/D Input
1 -8

Programmable
Logic

ZYNQ
UltraScale+
RFSoC FPGA64

GTY

LVDS

GTY

Processing
System

GTR

GTR

GTR

GTR

JTAG

POWER
Battery
MANAGEMENTManagement

Model 7050 Quartz PCIeVPX VBAT

Battery

X8DDR4SDRAM
4/8 GB
Config
FLASH

X24

X864

RS-232

1 GigEUSB 3PowerManagement

Model 6001 QuartzXM eXpress Module

6.4 GHz
14-BIT
D/A & DUC
Channels
1-8

4.0 GHz
12-bitA/D & DDC
Channels
1-8RF Signal
ChainClockManagement

DDR4SDRAM
4/8 GBSD
Card

AXI4 Clock

LVDS GPIO

PCIeGen. 3 X8RS-232

1 GigEUSB 312 V

Gate

Sync

X8 25 Gb/sec OpticalTransceiver(Optional)

12 V

toTiming Bus
Generator

Sample Clock
SysRef

MPO

LVDS
GPIO

PCIe

RS-232

1 GigEUSB 312V
PowerSync
Bus

TECHNICAL DATA SHEET
Quartz 7050

7050 BLOCK DIAGRAM

Click on a block for more information.

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TECHNICAL DATA SHEET
Quartz 7050

A/D CONVERTER STAGE

MEMORY RESOURCES

The board's analog interface accepts analog IF or RF inputs on eight
front panel MMCX connectors with transformer-coupling into the RF
signal chain of the RFSoC. Inside the RFSoC, the analog signals arerouted to eight 4 GSPS, 12-bit A/D converters. Each converter has
built-in digital downconverters with programmable 1x, 2x, 4x or 8x
decimation and independent tuning. The A/D digital outputs aredelivered into the Zynq’s programmable logic and processor systemfor signal processing, data capture or for routing to otherresources.

The 7050 architecture supports up to 8 GB of DDR4 SDRAM
memory accessible from the Programmable Logic. Userinstalled IP, which, along with the Mercury-supplied DDR4controller core within the FPGA can take advantage of thememory for custom applications. An 8 GB bank of DDR4 SDRAM
is available to the Processing System as program memory andstorage.

In addition to the A/D’s built-in decimation, an additional stageof IP-based decimation provides another 16x stage of datareduction, ideal for applications that need to stream data fromall eight A/Ds.

The 7050 includes an industry-standard interface fullycompliant with PCI Express Gen. 1, 2 and 3 bus specifications.
Supporting PCIe links up to x8, the interface includes multiple
DMA controllers for efficient transfers to and from the module.

D/A CONVERTER STAGEGPSThe RFSoC’s eight D/A converters accept baseband real orcomplex data streams from the FPGA’s programmable logic.
Each 6.4 GSPS, 14-bit D/A includes a digital upconverter withindependent tuning and interpolations of 1x, 2x, 4x and 8x. Each
D/A output is transformer coupled to a coax connection locatedon the front panel.

A GPS receiver provides time and position information to theFPGA and ARM processors. This information can be used for
precise data tagging. The GPS provides a 1 PPS and a reference
clock to the FPGA.

CLOCKING AND SYNCHRONIZATIONThe 70503 front panel includes inputs for sample clock,reference clock, reference sync and gate/trigger. In addition tothe front panel, a multi-pin Sync Bus connector on the rear of
the board provides a single cable connection to the Model 9103
High-Speed System Synchronization and Distribution Amplifier
for synchronizing up to 8 7050s in larger, multichannel systems.

PCI EXPRESS INTERFACEEXPANDABLE I/O
The 7050 supports up to eight 25 Gb/sec full duplex opticallanes to a pair of front panel MPO connectors. With theinstallation of a user-provided serial protocol, the opticalinterface enables gigabit communications between boards
independent of the PCIe interface. Twelve pairs of LVDS
connections are provided between the FPGA and a card edge
connector for custom I/O. In addition to the front panel analog
I/O connectors, the 7050 includes connectors for USB 3, 1 GigE,
RS-232, JTAG and a GPS antenna.

The on-board timing bus generator uses these signals, inaddition to a frequency synthesizer, to create the required A/Dand D/A clocks and a SysRef for operation of the data
converters. The timing bus generator supports an internal clockmode where the sample clock is driven by the programmablefrequency synthesizer and no additional clock needs to beprovided. In an alternate mode, the on-board sample clock canbe synchronized to a 10 MHz reference clock received through afront panel connector. The Model 7053 can also accept anexternal sample clock through this front panel connector. Thismode bypasses the on-board sample clock. A multifunction
gate/trigger input is available on the front panel for external
control of data acquisition and playback.

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TECHNICAL DATA SHEET
Quartz 7050

FLEXIBLE MODULAR DESIGN
While the Quartz 7050 follows the form factor of a standard 3U
OpenVPX board, the unique modular design of Mercury’s 6001
QuartzXM eXpress Module provides the flexibility to deploy thissolution in many different situations. The heart of the QuartzXM
is a system on module containing all of the key components
including the RFSoC FPGA, DDR4 SDRAM, and power and clock
management.
In the case of the 7050, the QuartzXM is mounted on a 3U
OpenVPX carrier which complements the design with a timing
bus generator, analog signal conditioning, a GPS receiver and an
8x 28 Gbps optical transceiver. As a module and carrier board
set, the 7050 becomes a complete, ready to deploy 3U OpenVPX

solution available for a range of operating environments fromcommercial to rugged and conduction-cooled.
The 6001 QuartzXM can also be mounted on other carriers
available from Mercury to support standard form factors; or for
applications that require a non-standard footprint, Mercury
supports the module with a design kit for users to engineer andbuild their own custom carrier. As a complete and tested
module, the QuartzXM encapsulates best-in-class electrical andmechanical design, eliminating some of the most challenging
aspects of embedded circuit design and allowing the user tofocus on the application specific carrier design.

QuartzXM eXpress Module

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TECHNICAL DATA SHEETQuartz 7050

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.
The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design
Suite includes the complete Vivado project folder for each Jade
product with all design files for the factory-installed FPGA IP.
Vivado’s IP Integrator is a graphical design entry tool that visuallypresents the complete block diagram of all IP blocks so thedeveloper can access every component of the Jade design.
Developers can quickly import, delete, and modify IP blocks andchange interconnection paths using simple mouse operations.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on thepowerful AXI4 standard. multilevel documentation for each IP coreis a mouse click away, and fully consistent with Xilinx IP cores.
The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational
control of all hardware functions on the board and IP functionsin the FPGA. The BSP structure is designed to complement thefunctions of the FDK by maintaining a one-to-one relationshipbetween FDK and BSP components. For each IP block found in
the FDK library, a matching software module can be found in
the BSP. This organization simplifies the creation and editingof software to support new IP functions and modifications toexisting IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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6TECHNICAL DATA SHEET
Quartz 7050

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayedsignals. With the Signal Viewer users can install the Jade boardand Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEET
Quartz 7050

SPECIFICATIONS
Field Programmable Gate Array
Type: (standard) Xilinx Zynq
UltraScale+ RFSoC XCZU27DR1FFVG1517I▪ 3 dB Passband: 10 MHz to 3700
MHz▪ Connector Type: MMCX

D/A Converters

GPS▪ Quantity: 8▪ Source: On-board▪ Sampling Rate: 6.4 GHz▪ Level: TTL▪ Option -028: Xilinx Zynq
UltraScale+ RFSoC XCZU28DR1FFVG1517I▪ Resolution: 14 bits

▪ Antenna Connector Location:
Front panel

Digital Upconverters▪ Connector Type: SMA

Speed: (standard) -1 speed grade▪ Quantity: 1 per D/ASync Bus▪ Option -002: -2 speed grade(2FFVG1517-1)▪ Interpolation Range: 1x, 2x, 4x and8x▪ Signals: Sample Clock, Reference
Clock, Reference Sync, Gate/Trigger▪ LO Tuning Freq. Resolution: 48bits▪ Location: Rear edge of card

RFSoC RF Signal Chain
Analog Inputs▪ Connector Type: Multi-pin, highspeed differential▪ Quantity: 8▪ Filter: 80% pass band, 89 dB stopband attenuation▪ Connectors: MMCX

Sample Clock▪ Location: Front panel

ARM Cortex-A53:▪ Input Type: Transformer-coupled▪ Source: On-board programmableclock source or external clock source▪ Quantity: 4▪ Transformer Type: Mini-Circuits
TCM1-83X+▪ Location: Front panel (for externalsource)

ARM Cortex-R5:▪ Full Scale Input: +10 dBm into 50 Ω

▪ Connector Type: MMCX

▪ Quantity: 2▪ 3 dB Passband: 10 MHz to 3700 MHz▪ Speed: 600 MHz

A/D Converters▪ Level: -10 dBm to +10 dBm frontpanel▪ Quantity: 8Reference Clock▪ Sampling Rate: 4.0 GHz▪ Source: On-board oscillator, onboard GPS, or external source▪ Resolution: 12 bits
Digital Downconverters▪ Quantity: 1 per A/D▪ Decimation Range: 1x, 2x, 4x and 8x▪ LO Tuning Freq. Resolution: 48bits, 0 to ƒs▪ Filter: 80% passband, 89 dB stopband attenuation
Analog Outputs▪ Quantity: 8▪ Connectors: MMCX
▪ Location: Front panel▪ Input Type: Transformer-coupled▪ Transformer Type: Mini-Circuits
TCM1-83X+▪ Full Scale Output: 0 dBm into 50 Ωmrcy.com▪ Location: Front panel (for externalsource)▪ Connector Type: MMCX

RFSoC Processing System▪ Speed: 1.5 GHz

Custom FPGA I/OParallel: 12 pairs of LVDS connections
between the FPGA and a top
accessible ribbon cable connector
Optical (Option -110): 8X full duplex
lanes @ 25 Gb/sec available on front
panel MPOs

Memory▪ Level: -10 dBm to +24 dBm

Processing System:Reference Sync

▪ Type: DDR4 SDRAM▪ Source: Programmable throughsoftware or external source▪ Size: (standard) 4 GB

▪ Location: Front panel (for externalsource)▪ Connector Type: MMCX
▪ Level: TTL
Gate/Trigger▪ Source: Programmable throughsoftware or external source▪ Location: Front panel (for externalsource)▪ Option -151: 8 GB
▪ Speed: 1200 MHz (2400 MHzDDR)Programmable Logic:▪ Type: DDR4 SDRAM▪ Size: (standard) 4 GB
▪ Option -151: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)
▪ FPGA Configuration FLASH: 2x 1
Gb QSPI

8TECHNICAL DATA SHEET
Quartz 7050

PCI-Express Interface

Options

Description-701

Air-cooled, Level L1

PCI Express Bus: Gen. 1, 2 or 3: x4 or x8

Environmental

Contact Mercury for compatible option combinations.

Option -701: L1 (air-cooled)▪ Operating Temp: 0° to 50° C

ACCESSORY PRODUCTS▪ Storage Temp: –40° to 100° C▪ Relative Humidity: 0 to 95%, non-condensing

PhysicalDimensions:2-slot PCIe
▪ Width: 1.6 in. (40.6 mm)

Model

Description

2172

Cable Kit: MMCX to SMA

5903

High- Speed System Synchronization and Distribution
Amplifier▪ Depth: 8.5 in. (215.9 mm)

LIFETIME SUPPORT FOR QUARTZ PRODUCTS▪ Height: 4.9 in. (124.5 mm)

ORDERING INFORMATION
ModelDescription

7050

8-Channel A/D & D/A PCIe board with Zynq UltraScale+
RFSoC - Gen 1Options

Description-002-2 FPGA speed grade, -1 standard-028

XCZU28DR FPGA (XCZU27DR is standard)-110

MPO 8X optical interface-151

8GB processor system memory, 8 GB programmable
logic memory

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costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
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For technical details, contact:mrcy.com/go/CF7050

Visit: mrcy.com/go/MP7050+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Quartz and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2022 Mercury Systems, Inc. 1-0-102822-DS-Q7050

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