ADF-Q25
Quad 250Msps, 16-bit ADC Receiver

Real Time, High Performance Acquisition Solutions

Real TimThe ADF-Q25 is DEG’s fastest 16-bit ADC, FPGA mezzanine card(FMC) module. By compressing four 250Msps, 16-bit ADCs onto
an FMC, DEG continues to deliver the widest range of high perfor• Four 250Msps, 16-bit ADC’smance, high density FMC ADC modules to the embeded computing• 900MHz Full Power Input B/Wmarketplace. Based on VITA 57 specifications, the ADF-Q25 enables• FMC/VITA 57 Form Factor

direct coupling of unparalleled analog-to-digital conversion per-• Air and Conduction-Cooled

formance with the VME/VXS/AMC/VPX/PCI-E FPGA carrier of yourchoice. DEG has designed this product and associated HDL firmware to work with both Xilinx and Altera FPGAs.

• Extremely Dense Digitization• Works with Altera & Xilinx FPGA’s• Industry Standard Form Factor• Rugged and Reliable

The ADF-Q25 is based on the Analog Devices AD9467, analog-todigital converter and emerging FMC form factor. The ADF-Q25
design and flexible configuration options, enable system designers
to rapidly and cost-effectively build compact and rugged systems
with up to eight, high-resolution channels on a single high performance processor board. This flexible approach reduces overall
power consumption, footprint and cost, while increasing ruggedness• 50Msps to 250Msps• 900 Mhz Input Bandwidth• 12.1 ENOB, Fin = 140Mhz• 8 Channels in Single VXS/VPX Slotand reliability.

ADF-Q25 Details
The front panel of the ADF-Q25 has a micro-connector
CMM220 and an HDMI connector. The micro-connector
supports six 50 connections. A breakout cable converts the micro-connector ports to male SMA connectors. These connectors provide 4 analog inputs, A/D
sampling clock/external reference clock input, andtrigger input. The front panel HDMI connector supports four uncommitted differential connections withthe host (LVDS or other). Data rate up to 5Gsps
supported.

Analog Input
The analog input is single-ended with a full-scale of1.84Vpp. The analog input signal bandwidth extends
up to 300MHz and depends on FMC version. See
Table.

Clockssignal. An auto-trigger function enables signal capture
without an external trigger. A user can set the trigger
threshold within a wide range, with 1mV resolution.
See Table.

ADCLink
FMC modules are distinct and separate from theFPGA devices that support them. Initiation and controlof the ADF-Q25 is accomplished with ADCLink. Board
support packages are required for each unique hostcard.The capabilities of ADCLink include: onboard/external reference/external clock selection, internal
sampling frequency, trigger threshold.

ADF-Q25 Performance Specifications
Analog Specification

Assembly

Number of Channels

4

Input Impedance

50 , AC-coupled

Input Bandwidth

1MHz - 150MHz (Version 20)
150 MHz - 300MHz (Version 21)

Full Scale Input

1.84 Vp-p, 12.3dBm max
17.6 dBm damage level

Sampling Clock Range

50MHz - 250MHz

Onboard Reference_ 1ppmInitial calibration +_ 0.5ppm
Stability +External Reference

Square (preferred) or Sine waveform
Level 0dBm to 10dBm
Frequency 10MHz *N, N=1, 2..., 10
Phase noise level <155dBc/Hz,100Mhz,

Onboard Frequency
Synthesizer

Output frequencies 50MHz,100MHz
150MHz, 200MHz, 250MHz

Triggers

Trigger Input

Trigger input must be 200mV to 2V p-p signal Risetime of less than 10 ns is recommended. A trigger
event is initiated by a positive transition on the trigger

Square (preferred) or Sine waveform
Range 0.2V - 2Vp-p

Trigger Threshold

Range (-2.048)V - +2.048V
Resolution 1mV

The user can provide a sampling clock to A/D converters or use the onboard frequency synthesizer toprovide the clock. The clock input is designed toaccept either an external sampling clock signal orexternal reference for the on-board synthesizer.
Functionality of the input is set by the user. The frequency synthesizer can be locked to an on-board
reference or an external one provided through the clock
input connector. Reference input from the FMC connector is also supported. The reference input must bea sine or square (preferred) wave, with an amplitude
range of 0dBm to +10dBm. Several output frequencies
predefined from the onboard synthesizer, see Table.
Custom values can be synthesized as well.

Delphi Engineering Group, Inc.
www.delphieng.com

ADF-Q25 Environmentals

ADF-Q25
ADF-Q25-C
ADF-Q25-R
ADF-Q25-RC
ADF-Q25-CC
ADF-Q25-CCC

ADF-Q25 Block Diagram(949)791-4101(949)791-4100