TECHNICAL DATA SHEET

Quartz 6350
8-channel A/D & D/A in a rugged small form factor enclosure
with Xilinx Zynq UltraScale+ RFSoC - Gen 1

Ideal for deployment
in harsh environments▪ High-bandwidth data streaming▪ Waveform signal generator▪ Analog I/O for digital recording andplayback▪ Communication receiver and transmitter▪ Sensor interfaces▪ Electronic Warfare transponder

The Quartz ® 6350 is a high-performance, small form factor system
based on the Xilinx Zynq UltraScale+ RFSoC. The RFSoC integrates
eight RF-class A/D and D/A converters into the Zynq’s multiprocessor
architecture, creating a multichannel data conversion and processing
solution on a single chip.
The 6350 delivers RFSoC performance in small footprint with a complete system in aruggedized enclosure ideal for deployment in harsh environments. Complementing the
RFSoC’s on-chip resources are the 6350’s sophisticated clocking section, a low-noise
front end for RF input and output, 16 GBytes of DDR4, a gigabit serial optical interface
capable of supporting dual 100 GigE connections, an optional GPS receiver, and general
purpose I/O signal paths to the FPGA.

ARCHITECTURE
The 6350 design places the RFSoC as the cornerstone of the architecture. All control anddata paths are accessible by the RFSoC’s programmable logic and processing system. A
full suite of Mercury-developed IP and software functions utilize this architecture toprovide data capture, processing and waveform generating solutions for many of the mostcommon application requirements.

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TECHNICAL DATA SHEET
Quartz 6350

FEATURES

EXTENDABLE IP DESIGN▪ Small form factor rugged enclosure

For applications that require specialized functions, users caninstall their own custom IP for data processing. Mercury’s
Navigator FPGA Design Kit (FDK) includes the board’s entire
FPGA design as a block diagram that can be edited in Xilinx’s
Vivado® IP Integrator. In addition to the IP Integrator block
diagrams, all source code and complete IP core documentation
is included. Developers can integrate their own IP along with thefactory-installed functions or use the Navigator kit tocompletely replace the Mercury IP with their own.

▪ Conduction-cooled▪ Designed to the IP67 specification for dust and water
immersion▪ Sealed military-grade circular connectors▪ Incorporates Xilinx® Zynq® UltraScale+™ RFSoC▪ 16 GB of DDR4 SDRAM▪ On-board GPS receiver▪ Optional dual 100 GigE UDP optical interface▪ Optional fan cooling for benchtop use▪ Navigator® BSP for software development▪ Navigator® FDK for custom IP development▪ Free lifetime applications support

DESIGNED FOR HARSH ENVIRONMENTS
The Model 6350 delivers the signal and processing performance of
the Quartz RFSoC family in a Small Form Factor (SFF) rugged
package. Optimized for SWaP (size, weight and power), the 6350
measures 3.53” H 5.65” W 9.57” D and weighs in at just under 8pounds.

The Navigator Board Support Package (BSP), the companion
product to the Navigator FDK, provides a complete C-callable
library for control of the 6350’s hardware and IP. The Navigator
FDK and BSP libraries mirror each other where each IP function
is controlled by a matching software function, simplifying thejob of keeping IP and software development synchronized.
The Navigator BSP includes support for Xilinx's PetaLinux runningon the ARM Cortex-A53 processors. When running under
PetaLinux, the Navigator BSP libraries enable complete control of
the 6350 either from applications running locally or on the ARMs,
or using the Navigator API control and command from remotesystem computers.

Designed for use in rugged environments, the 6350 is designed to
the IP67 specification for dust and water immersion. It’s internal ‘Ibeam’ construction creates a chassis that is both extremely
rugged and efficient for moving heat out of the box, making it
ideal for deployment in the harshest environments and wellmatched to conduction-cooled installations. The 6350 can also be
used with an optional fan plate for desktop development.

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Sample Clk

Balun

Balun

Balun

Balun

Balun

RF Out 4

RF Out 5

RF Out 6

RF Out 7

RF Out 8

Antenna In

Balun

Balun

RF In 8

RF Out 3Balun

RF In 7

Balun

Balun

RF In 6

Balun

Balun

RF In 5

RF Out 1Balun

RF Out 2Balun

RF In 3Balun

RF In 4Balun

RF In 1

Timing Bus
Generator

RF In 2Gate / Trigger

Reference Sync

Reference Clk

Frequency
Synthesizer

A/D Clocks

RF Out 2
through 7

RF In 2through 7

SysRef

D/A Clocks

GPS

D/A Output
1 -8

A/D Input
1 -8

Programmable
Logic

ZYNQ
UltraScale+
RFSoC FPGA

64

DDR4
SDRAM
4/8 GB

GTY

LVDS

Processing
System

GTR

JTAG

POWER
Battery
MANAGEMENTManagement

Model 6350 Quartz

VPX VBAT

Battery

X8

12

64

Config
FLASH

DDR4
SDRAM
4/8 GBUSS 2.0

RS-232

SGMII

Power
Management

Model 6001 QuartzXM eXpress Module

6.4 GHz
14-BIT
D/A & DUC
Channels
1-8

4.0 GHz
12-bitA/D & DDC
Channels
1-8

RF Signal
Chain

Clock
Management

EMMC
Memory12 V

PowerSupply24 V

CircularConnector

CircularConnector

CircularConnector

Circular
RS-485 Connector

USB 2.0

Circular
JTAG Connector

RS-232

1 GigE

Dual
100 GigE

DriverDriverDriver

ENET PHY

X8 25 Gb/sec Optical
Transceiver(Optional)

12 V

TECHNICAL DATA SHEET
Quartz 6350

6350 BLOCK DIAGRAM

Click on a block for more information.

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TECHNICAL DATA SHEET
Quartz 6350

A/D CONVERTER STAGE

MEMORY RESOURCES

The 6350 accepts analog IF or RF inputs on eight front panel
coax connectors. These inputs are transformer-coupling into
the RF signal chain of the RFSoC. Inside the RFSoC, the analog
signals are routed to eight 4 GSPS, 12-bit A/D converters. Eachconverter has built-in digital downconverters with
programmable 1x, 2x, 4x or 8x decimation and independent
tuning. The A/D digital outputs are delivered into the Zynq’s
programmable logic and processor system for signal
processing, data capture or for routing to other resources.

The 6350 architecture supports 8 GBytes of DDR4 SDRAM memory
accessible from the Programmable Logic. User-installed IP, which,along with the Mercury-supplied DDR4 controller core within the
FPGA can take advantage of the memory for custom applications. An
additional 8 GBytes bank of DDR4 SDRAM is available to theProcessing System as program memory and storage.

In addition to the A/D’s built-in decimation, an additional stageof IP-based decimation provides another 16x stage of data
reduction, ideal for applications that need to stream data fromall eight A/Ds.

D/A CONVERTER STAGE
The RFSoC’s eight D/A converters accept baseband real orcomplex data streams from the FPGA’s programmable logic.
Each 6.4 GSPS, 14-bit D/A includes a digital upconverter withindependent tuning and interpolations of 1x, 2x, 4x and 8x. Each
D/A output is transformer-coupled to a coax connection locatedon the front panel.

100 GIGE INTERFACEThe Model 6350 supports eight 25 Gb/sec full duplex opticallanes to a miniature rugged circular connector. With the dual
built-in 100 GigE UDP interfaces or installation of a user
provided serial protocol, this optical interface enables a highspeed gigabit data streaming path between the box and data
storage or processing subsystems.

GPS
A GPS receiver provides time and position information to the
FPGA and ARM processors. This information can be used for
precise data tagging. The GPS provides a 1 PPS and 10 MHz
reference clock to the FPGA.

CLOCKING AND SYNCHRONIZATION
An on-board timing bus generator uses a programmable frequency
synthesizer to generate the sample clock and all required timing
signals. The on-board sample clock can also be locked to areference clock received through a front panel coax connector. A
multifunction gate/trigger input is also available on the front panel
for external control of data acquisition and playback.

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Quartz 6350

OPTIMIZED IP
While capturing this much raw data is not feasible, the A/Ds'
built-in digital down converters can reduce this data
throughput in many applications to a rate reasonable for thedata streaming and storage components downstream in thesystem.

Xilinx has created an integrated processing solution in the RFSoC
that is unprecedented. The key to unlocking the potential of the
RFSoC is efficient operation using optimized IP and application
software. Mercury helps streamline the process from development
to deployed application by providing a full suite of built-infunctions. These address the data flow and basic processing
needed for some of the most common applications.

In some applications capturing the raw, full bandwidth data is
crucial. The 6350’s dual 100 GigE UDP engine provides a highbandwidth path for moving data off of the board (shown withlight blue arrows). Along with the built-in data acquisition IP,
the 6350 can stream two full bandwidth A/D data streams overoptical cable to a downstream storage or processing
subsystem.

Several example applications using the Model 6350 are described
below. For each example, the board’s included IP is all that isneeded to demonstrate the application and may satisfy the fullset of requirements for any particular application. These
applications can also be the starting point for adding additional
IP from the Navigator IP library or for adding custom IP.

The 6350’s built-in IP functions also provide paths for capturing
data in the DDR4 SDRAM memory for retrieval by the ARM
processing system or the FPGA programmable logic (shownwith dark blue arrows) and for sending data over the ARM’s 1
GigE interface (shown in yellow arrows).

EXAMPLE 1 - HIGH BANDWIDTH DATA STREAMING
The RFSoC's eight 4 GSPS A/Ds are capable of producing an
aggregate data rate of 64 GB/sec when all channels are enabled.

RF In

DDR SDRAM
Memory Control
IP Block

A/Ds
Data
Acquisition
IP Block

ARM
Processing
SystemD/As
Zync UltraScale+ RFSoC

Dual 100 GigE
UDP IP Block

DDR
SDRAM

Data & Control/Status
8x 25 Gb/sec
OpticalTransceivers

1 GigE
100 GigE Out 1

Data
Streaming

100 GigE Out 2

Model 6350

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Quartz 6350

EXAMPLE 2 - ANALOG LOOPBACK AND WAVEFORM
GENERATORThe 6350’s IP supports multiple D/A signal source options. A
simple loopback path allows samples received by the A/Ds to be
output through the D/As (shown with a dark blue arrow) . A CW
signal generator produces a sine output with programmablefrequency (shown with a yellow arrow). A chirp generator, ideal

for radar applications, outputs sweep signals with
programmable frequency, ramp, phase offset, gain offset andlength (shown with a light blue arrow). The generators also
include flexible trigger options with both internal and external
triggering.

DDR
SDRAM
RF In

RF OutCW Signal
Generator
IP Block

A/Ds

D/As

M
U
X

ARM
Processing
SystemControl/Status

1 GigE

Chirp
Generator
IP Block

Zync UltraScale+ RFSoC
Model 6350

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Quartz 6350

CONNECTIONS
The front panel of Model 6350 has the following
connectors:▪ Eight SMA connectors labeled IN 1-8, which
provide A/D input to the A/D converters on the6350.
▪ Eight SMA connectors labeled OUT 1-8, which
provide D/A output from the D/A converters on the
6350.

Quartz 6350 Front Panel

The rear panel of Model 6350 has the following
connectors:▪ GATE: Provides a trigger input. This trigger input
is DC-coupled and compatible with the LVTTL
levels, but is 5V tolerant.
▪ REF: Provides an input for an external 10 MHz
reference. This signal can be used to lock the onboard sample clock synthesizer to an externalreference.
▪ USB 2.0 / RS485: Interfaces to the RFSoC
processor's USB 2.0 Port 0.
▪ 1000 BASE-T: Provides an Ethernet connection
to the 6350 at 1000 Base-T mode.
▪ JTAG / RS-232: Used to download to the FPGA
and program QSPI configuration memory.

Quartz 6350 Rear Panel▪ 24V DC IN: Provides power to the 6350.
▪ 2 x 100GbE: Provides an optical connector forthe 6350.
▪ GPS: For input of an antenna RF signal for the
onboard GPS receiver.

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TECHNICAL DATA SHEET
Quartz 6350

NAVIGATOR DESIGN SUITE
For applications that require specialized functions, the Navigator
Design Suite allows customers to fully utilize the processing
power of the FPGA. It includes an FPGA design kit for integrating
custom IP into the factory-shipped design, and a board support
package for creating host applications for control of all hardware
and FPGA IP-based functions.
The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design
Suite includes the complete Vivado project folder for each Jade
product with all design files for the factory-installed FPGA IP.
Vivado’s IP Integrator is a graphical design entry tool that visuallypresents the complete block diagram of all IP blocks so thedeveloper can access every component of the Jade design.
Developers can quickly import, delete, and modify IP blocks andchange interconnection paths using simple mouse operations.

Navigator FDK includes an IP core library of more than 100
functions representing a wealth of resources for DSP, data
formatting, timing, and streaming operations, all based on the
powerful AXI4 standard. multilevel documentation for each IP coreis a mouse click away, and fully consistent with Xilinx IP cores.
The Navigator Board Support Package (BSP) provides
software support for Jade boards. It enables operational
control of all hardware functions on the board and IP functionsin the FPGA. The BSP structure is designed to complement thefunctions of the FDK by maintaining a one-to-one relationshipbetween FDK and BSP components. For each IP block found in
the FDK library, a matching software module can be found in
the BSP. This organization simplifies the creation and editingof software to support new IP functions and modifications toexisting IP cores.

Navigator IP FPGA Design viewed in IP Integrator

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Quartz 6350

Because all Jade boards are shipped with a full suite of built-in
IP functions and numerous software examples, new applications
can be developed by building on the provided software
examples or built entirely new with the BSP extensive libraries.
All BSP libraries are provided as C-language source for fullaccess and code transparency.

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The Navigator BSP includes the Signal Viewer, a full-featured
analysis tool, that displays data in time and frequency domains.
Built-in measurement functions display 2nd and 3rd harmonics,
THD (total harmonic distortion), and SINAD (signal to noise anddistortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed
signals. With the Signal Viewer users can install the Jade board
and Navigator BSP and start viewing analog signals immediately.

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TECHNICAL DATA SHEET
Quartz 6350

SPECIFICATIONS
Field Programmable Gate Array

Digital Upconverters

Type: (standard) Xilinx Zynq UltraScale+ RFSoC XCZU27DR▪ Quantity: 1 per D/A▪ Option -028: Xilinx Zynq UltraScale+ RFSoC XCZU28DR▪ Interpolation Range: 1x, 2x, 4x, and 8x

Speed: (standard) -1 speed grade▪ LO Tuning Freq. Resolution: 48 bits

▪ Option -002: -2 speed grade▪ Filter: 80% pass band, 89 dB stop-band attenuation

RFSoC RF Signal Chain

Sample Clock

Analog Inputs▪ Source: On-board programmable clock▪ Quantity: 8

Reference Clock▪ Location: Front panel (IN 1-8)

▪ Source: On-board oscillator, on-board GPS, or externalsource▪ Connector Type: SMA▪ Input Type: Transformer-coupled▪ Transformer Type: Mini-Circuits TCM1-83X+▪ Full Scale Input: +10 dBm into 50 ohms
▪ 3 dB Passband: 10 MHz to 3700 MHz
A/D Converters▪ Quantity: 8▪ Sampling Rate: 4.0 GHz▪ Resolution: 12 bits
Digital Downconverters▪ Quantity: 1 per A/D▪ Decimation Range: 1x, 2x, 4x, and 8x▪ LO Tuning Freq. Resolution: 48 bits, 0 to ƒs▪ Filter: 80% pass band, 89 dB stop-band attenuation▪ External Source Location: Rear panel (REF)▪ Connector Type: SMA▪ Level: -10 dBm to +24 dBm
Gate/Trigger▪ Source: Programmable through software or external
connector▪ External Source Location: Rear Panel (GATE)▪ Connector Type: SMA▪ Level: TTL

GPS
Source: On-board
Antenna Connector Location: Rear panel (GPS)Connector Type: SMA

RFSoC Processing System

Analog Outputs

ARM Cortex-A53:▪ Quantity: 8▪ Quantity: 4▪ Location: Front panel (OUT 1-8)

▪ Speed: 1.5 GHz▪ Connector Type: SMA

ARM Cortex-R5:▪ Output Type: Transformer-coupled▪ Quantity: 2▪ Transformer Type: Mini-Circuits TCM1-83X+▪ Speed: 600 MHz▪ Full Scale Output: 0 dBm into 50 ohms

Processor I/O:

▪ 3 dB Passband: 10 MHz to 3700 MHz

Interfaces: USB 2.0 and RS-485

D/A Converters▪ Location: Rear panel (USB2.0/RS485)▪ Quantity: 8▪ Connector Type: Circular, Glenair Mighty Mouse Series▪ Sampling Rate: 6.4 GHz

Interface: 1 GigE▪ Resolution: 14 bits

▪ Location: Rear Panel (1000BASE-T)▪ Connector Type: Circular, Glenair Mighty Mouse Series

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TECHNICAL DATA SHEET
Quartz 6350

Interface: RS-232

Physical▪ Location: Rear Panel (JTAG/RS-232)

Dimensions:▪ Connector Type: Circular, Glenair Mighty Mouse Series▪ Depth: 243.08 mm (9.57 in)

FPGA I/O▪ Height: 89.66 mm (3.53 in)

Optical (Option -110): 8X full duplex optical lanes @ 25 Gb/sec▪ Width: 143.51 mm (5.65 in)▪ Location: Rear panel (2x 100GbE)

Weight: 8 lbs.

▪ Connector Type: circular, Glenair SuperNine Series▪ Protocol: Factory-installed dual 100 GigE UDP IP coresprovides greater than 24 GB/sec data transfers, otherprotocols supported with user-installed IP

JTAG
Location: Rear Panel (JTAG/RS-232)
Connector Type: Circular, Glenair Mighty Mouse Series

MemoryPower:
Voltage: +12 to +28 VDC (+24 VDC nominal)
Location: Rear Panel (24VDC IN)
Connector Type: Circular, Glenair Mighty Mouse Series
Maximum Power Consumption: 46.62 Watts

ORDERING INFORMATION
Model

Description

6350

8-channel A/D & D/A in a rugged small form factor
enclosure with Zynq UltraScale+ RFSoC
Processor - Gen 1

Options

Description▪ Type: eMMC

-002

-2 FPGA speed grade, -1 standard▪ Size: 64 GB-028

XCZU28DR FPGA (XCZU27DR is standard)

Programmable Logic:-110

MPO 8X optical interface▪ Type: DDR4 SDRAM-151

8GB processor system memory, 8 GB programmable
logic memory-703

Air-cooled, Level L3

Processing System:▪ Type: DDR4 SDRAM▪ Size: (standard) 4 GB
▪ Option -151: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)

▪ Size: (standard) 4 GB
▪ Option -151: 8 GB
▪ Speed: 1200 MHz (2400 MHz DDR)FPGA Configuration FLASH:▪ Type: QSPI NOR Flash

Contact Mercury for compatible option combinations.

ACCESSORY PRODUCTS
Model

Description

2187

6350 Accessories▪ Operating Temp: –20° to 60° C (with 50° C cold plate)

OptionDescription▪ Storage Temp: –50° to 100° C-150

Development cable set without optical cable▪ Relative Humidity: 0 to 100%-151

Development cable set with optical cable-701

Top cover plate with built-in fan, replaces standard top
plate for benchtop cooling▪ Size: 2x 1 Gb

Environmental
Option -703: Level L3 (conduction-cooled)mrcy.com

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TECHNICAL DATA SHEET
Quartz 6350

LIFETIME SUPPORT FOR QUARTZ PRODUCTS
Mercury offers worldwide customers shorter development time,
reliable, rugged solutions for a variety of environments, reduced
costs, and mature software development tools. We offer freelifetime support from our engineering staff, which customers
can depend on through phone and email, as well as software
updates. Take advantage of our 40 years of experience indelivering high-performance radar, communications, SIGINT,
EW, and data acquisition MIL-Aero solutions worldwide.

Corporate Headquarters
50 Minuteman Road
Andover, MA 01810 USA+1 978.967.1401 tel+1 866.627.6951 tel+1 978.256.3599 fax

International Headquarters
Mercury International

Learn more

Avenue Eugène-Lance, 38
PO Box 584
CH-1212 Grand-Lancy 1
Geneva, Switzerland

For technical details, contact:mrcy.com/go/CF6350

Visit: mrcy.com/go/MP6350+41 22 884 5100 tel

The Mercury Systems logo and the following are trademarks or registered trademarks of Mercury Systems, Inc.: Mercury Systems, Innovation That
Matters, Quartz and Navigator. Other marks used herein may be trademarks or registered trademarks of their respective holders. Mercury believes
this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject
to change without notice.
© 2022 Mercury Systems, Inc. 1-0-101822-DS-Q6350

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