J. of Mult.-Valued Logic & Soft Computing, Vol. 20, pp. 595–623
Reprints available directly from the publisher
Photocopying permitted by license only

©2013 Old City Publishing, Inc.
Published by license under the OCP Science imprint,
a member of the Old City Publishing Group.

Flexible Ferroelectric-Capacitor Elementfor Low Power and Compact
Logic-in-Memory Architectures
S HOTA I SHIHARA , N ORIAKI I DOBATA , M ASANORI H ARIYAMAAND M ICHITAKA K AMEYAMA
Graduate School of Information Sciences, Tohoku University,
Aramaki-aza-Aoba 6-6-05, Aoba, Sendai, Miyagi, 980-8579, Japan
E-mail: ishihara@ecei.tohoku.ac.jp, hariyama@ecei.tohoku.ac.jp,
kameyama@ecei.tohoku.ac.jp
Received: November 9, 2011. Accepted: March 8, 2012.

The “Von Neumann bottleneck” and large standby power become serious problems in recent deep-sub-micron technology. To solve these
problems, this paper presents ferroelectric-based logic circuits called
Flexible Ferroelectric-Capacitor (FFC) elements for logic-in-memoryarchitectures. In an FFC element, storage and a logic function are integrated on non-volatile ferro-electric-capacitors to achieve low power
and area-efficiency. Moreover, the FFC elements are designed to flexibly change the access transistor network to achieve high functionality
and programmability to change the function. In this paper, FFC elements for binary logic and for multiple-valued logic are proposed. The
FFC elements are evaluated using HSPICE simulations and comparedto the equivalent CMOS circuits. Both of the FFC elements for binary
logic and for multiple-valued logic consume no power in the standby
state, and reduce the transistor count and the dynamic energy consumption by respectively more than 94% and more than 65%.
Keywords: Non-volatile storage, non-volatile logic, multiple-valued logic, nondestructive operation, capacity-based logic, programmable logic, power gating,content-addressable memory (CAM), FeRAM.

This paper is an extension of conference paper [2].

595

596

S HOTA I SHIHARA et al.

1 INTRODUCTIONAs technology scaling proceeds and the scales of VLSI systems becomelarge, the “Von Neumann bottleneck” and large standby power become serious problems. The “Von Neumann bottleneck” is the communication bottleneck between memories and logic modules, which limits the throughput.
Logic-in-memory architecture is proposed to solve the “Von Neumann bottleneck”. In logic-in-memory architectures, storage functions are distributed
over a logic-circuit plane, and highly effective use of internal memory bandwidth is achieved. However, conventional logic-in-memory VLSIs generally
become complicated because of the hardware overhead involved in distributing storage elements [5]. Another problem is the standby power caused by theleakage current. To reduce the standby power, low-power embedded applications tend to require frequent power ON and OFF cycles. However, SRAMbased VLSIs lose their stored data when the power is OFF. In order to retain
the stored data, the data is rolled out to an external non-volatile memory suchas the EEPROM or FLASH memory before power down, and reloaded thedata into the VLSI after power up. This approach creates performance andpower overhead. In VLSI, it is difficult to frequently power ON and OFF
to reduce the standby power. To solve this problem, the use of on-chip nonvolatile memory is necessary [1–4].
A ferroelectric-based logic circuit called the Complementary
Ferroelectric-Capacitor (CFC) element has been proposed [6]. It is
designed for logic-in-memory architectures to solve the “Von Neumannbottleneck” and reduce the standby power. The CFC element is based on
binary logic, and in the CFC element, non-volatile storage and a logic
function are integrated on Ferroelectric-Capacitors (FCs) by the capacitive
coupling effect under the control of the external input and stored bit. The
disadvantage of the CFC element is that a single CFC element only can
execute simple functions such as two-input-AND or two-input-OR. In order
to execute more complex functions, multiple CFC elements are combined.
For example, an XOR function is implemented by two CFC elements forContent Addressable Memory (CAM), which is a typical logic-in-memoryarchitecture. Such complex functions increase the number of transistors andFCs, and results in a large area and a high dynamic power consumption.
To solve these problems, this paper proposes low-power and highfunctional ferroelectric-based logic circuits called Flexible FerroelectricCapacitor (FFC) elements for logic-in-memory architectures. Like the CFC
element, non-volatile storage and logic functions are also integrated on FCs.
The difference between the CFC element and the FFC element is that the FFC
element can flexibly change the access transistor network to achieve highfunctionality with a small number of transistors and FCs. In this paper, twoF ERROELECTRIC -C APACITOR E LEMENT

597

types of FFC elements are proposed, and both of them consume no power inthe standby state. One is the FFC element for binary logic. A single FFC element for binary logic can perform as a binary non-volatile memory cell, andcan execute five kinds of two-input binary logic functions, two kinds of threeinput binary logic functions and one kind of binary arithmetic function. Compared to the equivalent CMOS circuit, the transistor count and the dynamic
energy consumption are reduced by 95% and 66%, respectively. Compared tothe equivalent CFC-based circuit, the transistor count, the FC count and the
dynamic energy consumption are reduced by 43%, 50% and 27%, respectively. The other is the FFC element for multiple-valued logic. It introduces
the multiple-valued storage and logic techniques into the FFC element forbinary logic, and has a higher functionality with the same structure. A single
FFC element for multiple-valued logic can perform as a three-valued nonvolatile memory cell, and can execute six kinds of two-input multiple-valued
logic functions, two kinds of three-input multiple-valued logic functions andone kind of binary arithmetic function. Compared to the equivalent CMOS
circuit, the transistor count and the dynamic energy consumption are reduced
by 96% and 65%, respectively. Compared to the equivalent CFC-based circuit, the transistor count, the FC count and the dynamic energy consumption
are reduced by 60%, 67% and 45%, respectively.

2 PRINCIPLE OF FERROELECTRIC CAPACITORSAn FC is obtained from a regular capacitor by replacing the dielectric with aferroelectric material, as shown in Figure 1(a). Figure 1(b) is the symbol of
an FC. An FC has two directions of the remnant-polarization, and is used asa variable capacitor. The capacitance of the FC is determined by the direction of the remnant-polarization and the direction of Electric Potential Difference (EPD) applied across the FC. An FC has a feature that its capacitance is large when the direction of the remnant-polarization and that of theTopelectrodeFerroelectricmaterial
Bottomelectrode(a) Structure.

FIGURE 1
Ferroelectric capacitor.

(b) Symbol.

598

S HOTA I SHIHARA et al.

EPD directions
applied across the FCs

EPD directions
applied across the FCs

VDD

VSS

VDD

t0

t1

t0

S=0
+

-

EPD: large

VSS
t1

S=1

S=1
+

-

EPD: small
VG ≈ VSS

+

-

S=0
+

-

EPD: small EPD: large
VG ≈ VDD

OFF(Out = 0)

ON(Out = 1)(a) Stored value: “0”.

(b) Stored value: “1”.

FIGURE 2
FC-based memory cell.

EPD applied across the FC are the same. On the contrary, the capacitance of
the FC is small when the direction of the remnant-polarization and that of
the EPD applied across the FC are opposite. The direction of the remnantpolarization is the stored data of the FC, and the direction of the EPD applied
across the FC is an external input. An FC has a coercive voltage. If the direction of the EPD applied across the FC is opposite to that of the remnantpolarization and the amount of the EPD is larger than the coercive voltage,
the remnant-polarization of the FC changes to the opposite direction. This iscalled destructive operation. Otherwise, the remnant-polarization of the FC
does not change. This is called non-destructive operation.
In order to explain the behavior of the FC, consider the FC-based memory
cell shown in Figure 2. The memory cell executes a non-destructive operation[6]. The memory cell has two FCs, and the remnant-polarization directionsof the FCs are set to be complementary. The data representation of the stored
data of the left FC is S, and that of the right FC is S. The gate voltage ofthe pass transistor VG is generated by the capacitive coupling effect, and VG
determines the state of the pass transistor. The states “OFF” and “ON” of thepass transistor correspond to the stored data “0” and “1”, respectively.
Figure 2(a) shows the memory cell which stores value “0”. Values S0
and S1 in the figure denote the remnant-polarization direction of the left FC
and that of the right FC, respectively. The pair of the remnant-polarization
directions is the stored data. To store value “0”, the remnant-polarization of
the left FC and that of the right FC are respectively set to left and right inadvance. To read the stored data, VDD and VSS are applied to terminals t0
and t1 , respectively. The gate voltage of the pass transistor VG is generated
by the capacitive coupling effect of the two FCs, and VG determines the state(ON/OFF) of the pass transistor. Since the relationship among the terminal

F ERROELECTRIC -C APACITOR E LEMENT

599

voltages is Vt0 >= VG >= Vt1 , the direction of the EPD applied across each
FC is always left. In the left FC, the directions of the remnant-polarization
direction and the EPD applied across the FC are the same. Therefore, thecapacitance of the FC is small. In the right FC, the directions of the remnantpolarization direction and the EPD applied across the FC are opposite. Therefore, the capacitance of the FC is large. Since the gate voltage of the pass transistor VG is generated by the capacitive coupling effect, the EPD between theelectrodes of the left FC is large and that of the right FC is small. Therefore,
voltage VG is approximately the same as voltage VSS. As a result, the gate
voltage of the pass transistor is lower than the threshold voltage, and the passtransistor is OFF. The output Out is “0”, and is the same as the stored bit S.
In this way, the operation is non-destructive. The reason is as follows. In theleft FC, the direction of the EPD applied across the FC is the same as that of
the remnant-polarization. Therefore, the remnant-polarization of the left FC
does not change. In the right FC, although the direction of the EPD applied
across the FC is opposite to that of the remnant-polarization, the amount of
the EPD is small and is not larger than the coercive voltage. Therefore, theremnant-polarization of the right FC does not change.
Figure 2(b) shows the memory cell which stores value “1”. In the left
FC, the directions of the remnant-polarization direction and the EPD applied
across the FC are opposite. Therefore, the capacitance of the FC is large. In
the right FC, the directions of the remnant-polarization direction and the EPD
applied across the FC are the same. Therefore, the capacitance of the FC issmall. Since the gate voltage of the pass transistor VG is generated by thecapacitive coupling effect, the EPD between the electrodes of the left FC issmall and that of the right FC is large. Therefore, voltage VG is approximately
the same as voltage VDD. As a result, the gate voltage of the pass transistor
is higher than the threshold voltage, and the pass transistor is ON. The output
Out is “1”, and is the same as the stored bit S. Similarly to the memory cellstoring value “0”, the memory cell storing value “1” also executes a nondestructive operation.

3 FFC ELEMENT
3.1 Architecture
Figure 3 shows the function of a general logic-in-memory circuit such as an
FFC element. It executes a logic function between the external input In andthe stored input S. The obtained result is the output Out. Figures 4 and 5shows the examples of the logic-in-memory circuits composed of FFC elements. The function of a single FFC element is shown in Figure 6. An FFC
element performs as a logic element, a storage element and a pass switch.

600

S HOTA I SHIHARA et al.

In (External input)
Storageelement

S (Stored data)

Logic
element

Out

FIGURE 3
Function of a logic-in-memory circuit.

Inn-1

In1

In0

Fn-1 (XOR mode)

F1 (XOR mode)

F0 (XOR mode)

Sn-1

S1

S0
Precharge
controlOut…
…

FIGURE 4
CAM word circuit composed of FFC elements.
In0

In1

F0 S0

F1 S1

FFC element

Precharge
controlPrechargetransistor

Out = (F0+F1)F2

Wired OR

In2
Wired ANDF2 S2Evaluatetransistor

FIGURE 5
General structure of logic-in-memory circuit composed of FFC elements.

The logic element executes a switching function between the external input
In and the internal input S which is stored in the storage element. If the resultof the logic element is “1”, the pass switch turns ON. Otherwise, the pass
switch turns OFF. Note that, the FFC element can execute various kinds of

F ERROELECTRIC -C APACITOR E LEMENT

601

In (External input)
Storageelement
S (Stored data)

Logic
element

FIGURE 6
Function of an FFC element.

functions, and the executed function can be changed dynamically. The logicalAND and OR operations between the results of the FFC elements can be
implemented by the connections of the FFC elements. Additional prechargeand evaluate transistors are used to control precharge and evaluate phases
based on dynamic-logic style.
3.2 FFC Element for Binary Logic
An FC-based memory can also be implemented as Figure 7(a)(i), and Figure 7(a)(ii) is its equivalent circuit. Note that the white arrows and the blackarrows on the FCs represent S = 0 and S = 1, respectively. The stored bit of
the pair of FCs is S = 0, and it specifies that the remnant-polarization direction of each FC is left. In this case, the output Out is “0”, and is the same as
the stored bit S = 0. Figure 7(b)(i) shows the case where the FCs are readfrom right, and Figure 7(b)(ii) is its equivalent circuit. In this case, the output Out is “1”, and is different from the stored bit S = 0. The stored valuesof Figures 7(a)(i) and 7(b)(i) are the same, but different outputs are obtained.
This is because the different reading paths cause the different directions of thevoltages applied to the FCs. Since the output Out depends on both the direction of the remnant-polarization of the FCs and the direction of the voltage
applied across the FCs, Out depends not only on the stored data but also on
the reading path. The proposed FFC exploits this feature to execute complex
functions with a small number of FCs.
Figure 8 shows the structure of an FFC element. Like the CFC element, thetwo ferroelectric capacitors store a pair of complementary data and the FFC

602

S HOTA I SHIHARA et al.

EPD direction
applied acrossthe FC+

VSS t1VDD-

Remnantpolarization
direction
applied acrossthe FC+VDD t0

VSS

t0

t1

S=0
+

-

OFF
(Out = 0)

S=1

-

+

-

OFF
(Out = 0)(i) FC-based circuit.

(ii) Equivalent circuit.

(a) Reading FCs from left.

-

t0 VDD

+

+

VSS
t1

VDD

VSS

t0

t1

S=1
-

-

ON
(Out = 1)

S=0

+

-

+

ON
(Out = 1)(i) FC-based circuit.

(ii) Equivalent circuit.

(b) Reading FCs from right.

FIGURE 7
Relationship between the reading path and the output Out.

t2

t6

t0
t3
t1

t4

+

-

-

+

t8
t5

t7
t9

FIGURE 8
Structure of the FFC element.

element also executes a non-destructive operation. The difference between
CFC and FFC elements is that the FFC element can change the access transistor network flexibility to achieve a high flexibility using a small number oftransistors and FCs.
The modes of the FFC element for binary logic are as follows, where I0
and I1 are binary external inputs and where S is a binary stored bit. ModesF ERROELECTRIC -C APACITOR E LEMENT

603

BI MEM, AND, OR and COMP are the same functions as those of the CFC
element and the other modes are newly added functions.
BI MEM:BI XOR:

Binary non-volatile memory cell for storing S.
I0 ⊕ S.
Binary CAM cell.
I0 · S.
I0 · S.
I0 + S.
I0 + S.
I0 · S (i f I1 = 0),
 I0 · S (i f I1 = 1).
I0 + S (i f I1 = 0),I0 + S (i f I1 = 1).
Bit-serial comparator.
Carry logic.

BI AND:
BI AND-INV:
BI OR:BI OR-INV:BI MUX-AND:
BI MUX-OR:
BI COMP:

Figures 9(a) and (b) show the BI XOR mode of the FFC element. In thismode, the FFC element executes I0 ⊕ S, where I0 is an external input andS is the stored bit. The idea behind the BI XOR mode of the FFC element
is to read the FCs through different paths depending on the external input
I0 . As mentioned above, different reading paths cause the different direction

VI0
VI0

VDD

VI0

VDD
VI0

VSS

+

-

-

+

OFF

VSS

VDD
S

VI0

VI0

+

VSS

S
-

+

-

Out = S
Out = S(ii) Equivalent circuit.

(i) FFC logic element.
(a) I0 = 0.

VI0
VDD
VI0

VDD

VI0
VI0

VSS

+
-

-

VDD
S

VI0

VI0

VSS

+

Out = S

-

S
+

-

+

OFF

(i) FFC logic element.
(b) I0 = 1.

FIGURE 9
BI XOR mode of the FFC element.

VSS

Out = S(ii) Equivalent circuit.

604

S HOTA I SHIHARA et al.

I0

S

Out

0
0
1
1

0
1
0
1

0(=S)
1(=S)
1(=S)
0(=S)

TABLE 1
Truth table of BI XOR mode of the FFC elementof the voltage applied to the FCs. Since the output Out depends on both
the direction of the voltage applied across the FCs and the direction of theremnant-polarization of the FCs, Out depends on both the reading path andthe stored data. The different reading paths allow us to execute more complex
functions with a smaller number of FCs. The external input I0 controls thestate (ON/OFF) of transistors in the reading paths. In other words, the turnON transistors in Figure 9(a)(i) are different from those in Figure 9(b)(ii).
VI0 is the voltage of logical value I0 . When I0 is “0”, VI0 is VSS. When I0 is“1”, VI0 is VDD. As shown in Figure 9(a), when I0 = 0, the output Out is thesame as S. As shown in Figure 9(b), when I0 = 1, the output Out is the sameas S. As a result, as shown in Table 1, the BI XOR mode of the FFC element
executes A ⊕ S. The BI XOR mode of the FFC element also performs as abinary CAM cell. In a binary CAM cell storing either “0” or “1”, when thevalue of the input and that of the store value are the same, the output is “0”;when the value of the input and that of the store value are different, the output
is “1”. The truth tables of the CAM cell and that of the BI XOR mode are thesame.
Figure 10 shows the BI AND mode of the FFC element. In this mode, theFFC element executes I0 · S. Figure 10(b) shows the equivalent circuit when
I0 = 0. In this case, voltage VI0 is VSS. Therefore, the gate voltage of the passtransistor is VSS, and then the pass transistor is OFF. As a result, the output
Out is “0” regardless of the stored value. Figure 10(c) shows the equivalentcircuit when I0 = 1. In this case, voltage VI0 is VDD, and then the output Out
is the same as the stored bit S. Thus, only if I0 and S are “1” is the output Out“1”. In other words, the FFC element executes I0 · S.
Figure 11 shows the BI AND-INV mode of the FFC element. In thismode, the FFC element executes I0 · S. The difference between the BI ANDINV and in BI AND modes of the FFC element is that they use different
reading paths.
Figure 12 shows the BI OR mode of the FFC element. In this mode, theFFC element executes I0 + S. Figure 12(b) shows the equivalent circuit when
I0 = 0. In this case, voltage VI0 is VSS, and then the output Out is the same as
the stored bit S. Figure 12(c) shows the equivalent circuit when I0 = 1. In thisF ERROELECTRIC -C APACITOR E LEMENT

VDD
VI0
VDD VSS
VSS

605

VSS
+

-

-

+

VI0
VDD VSS
VSS

OFF

Out = I0 S(a) FFC element.

VI0(=VSS)

VSS
S

+

VI0(=VDD)

S
-

+

VSS

S
-

+

S
-

Out = 0+-Out = S(b) Equivalent circuit when I0 = 0.

(c) Equivalent circuit when I0 = 1.

FIGURE 10
BI AND mode of the FFC element.

VSS

VDD

VI0
VSS VDD
VSS

+

-

-

+

VI0
VSS VDDVSS

Out = I0 S

OFF(a) FFC element.

VI0

VSS
S
-

S
+

-

+

Out = I0 S(b) Equivalent circuit.

FIGURE 11
BI AND-INV mode of the FFC element.

606

S HOTA I SHIHARA et al.

VDD
VDD
VDD VSS
VI0

VSS
+

-

-

+

VDD
VDD VSS
VI0

OFF

Out = I0+S(a) FFC element.

VDD

VI0(=VSS)S+

VDD

VI0(=VDD)

S
-

+

S
-

+

Out = SS-+-

Out = 1(b) Equivalent circuit when I0 = 0.

(c) Equivalent circuit when I0 = 1.

FIGURE 12
BI OR mode of the FFC element.

case, voltage VI0 is VDD. Therefore, the gate voltage of the pass transistor is
VDD, and then the pass transistor is OFF. As a result, the output Out is “0”regardless of the stored value. If either I0 or S is “1”, the output Out is “1”.
In other words, the FFC element executes I0 + S.
Figure 13 shows the BI OR-INV mode of the FFC element. In this mode,
the FFC element executes I0 · S. The difference between the BI OR-INV andin BI OR modes of the FFC element is that they use different reading paths.
Figure 14 shows the BI MUX-AND mode of the FFC element. In thismode, the FFC element executes (I1 · (I0 · S)) + (I1 · (I0 · S)). Figure 14(a)

VDD
VSS
VDD
VSS VDD
VI0

VI0

VDD
+
-

-

VDD
VSS VDD

S
+

-

+

VI0

+

Out = I0+S

S
-

OFF
(a) FFC element.

FIGURE 13
BI OR-INV mode of the FFC element.

Out = I0+S(b) Equivalent circuit.

F ERROELECTRIC -C APACITOR E LEMENT

607

I1
I0
SRAM

S

AND

S

AND

I0 and S

0

Out

MUX

I0

I0 and S

1(a) Equivalent CMOS circuit.

VI1
VI1

VI0

VI1

VI0
VI1

VSS

+
-

-

VSS

VI0
S

VI1

VI1

+

VSS

+

S
-

+

-

Out = I0 S

OFF

Out = 0(ii) Equivalent circuit.

(i) FFC logic element.
(b) I1 = 0.

VI1
VI1

VI0

VI1

VI0

+

-

VI1

VSS
Out = I0 S

S

VI1

VI1
-

VSS

VI0
VSS

+

-

S
+

-

+

OFF
Out = I0 S(ii) Equivalent circuit.

(i) FFC logic element.
(c) I1 = 1.

FIGURE 14
BI MUX-AND mode of the FFC element.

shows the equivalent CMOS circuit. The external input I1 selects the reading
path. As shown in Figure 14(b), when I1 = 0, the FFC elements is in the
BI AND mode which executes I0 · S. As shown in Figure 14(c), when I1 = 1,
the FFC elements is in the BI AND-INV mode which executes I0 · S.
Figure 15 shows the BI MUX-OR mode of the FFC element. In this mode,
the FFC element executes (I1 · (I0 + S)) + (I1 · (I0 + S)). Figure 15(a) showsthe equivalent CMOS circuit. The external input I1 selects the reading path.
As shown in Figure 15(b), when I1 = 0, the FFC elements is in the BI OR
mode which executes I0 + S. As shown in Figure 15(c), when I1 = 1, theFFC elements is in the BI OR-INV mode which executes I0 + S.
Figure 16 shows the BI COMP mode of the FFC element. In thismode, the FFC element compares two k-bit binary numbers: I0 =k−2
k−1 k−200(Ik−10 , I0 , · · · , I0 ) and I1 = (I1 , I1 , · · · , I1 ) in a bit-serial manner, and608

S HOTA I SHIHARA et al.

I1
I0
SRAM

S

OR

S

OR

I0 and S

0

Out

MUX

I0

I0 and S

1(a) Equivalent CMOS circuit.

VI1

VDD

VI1

VDD
VI1

+

VI1

VI0

-

-

VI0

VDD
S

VI1

VI1

+

S

+

VI0

-

+

-

Out = I0+S
Out = I0+S(ii) Equivalent circuit.

(i) FFC logic element.
(b) I1 = 0.

VI1
+

VI1

VDD

-

VI1
-

S

VI1

VI1

VI0

VI0

VDD

VI1

VDD

-

VI0

+

S
+

-

+

Out = I0+S
Out = I0+S(ii) Equivalent circuit.

(i) FFC logic element.
(c) I1 = 1.

FIGURE 15
BI MUX-OR mode of the FFC element.
n

I0
Sn

n

I1

S

n-1

Register(a) CMOS bit-serial comparator.

VDD

VDD

n

n

I1
VDD VSS

+

-

-

+

I0
VSS VDDn(b) FFC element.

I1

Sn

I0
+

-

EPD

FIGURE 16
BI COMP mode of the FFC element.

n

I0

n

n

I1

n

I1

Sn
+

-

EPD

(c) Equivalent circuit.

F ERROELECTRIC -C APACITOR E LEMENT
n

I0
0
0
1
1

n

I1
0
1
0
1

609

n

S
n-1

S (unchange)01
n-1
S (unchange)

TABLE 2
Truth table of a bit-serial comparator

generates the output S = (Sk−1 , Sk−2 , · · · , S0 ), where I0n , I1n and S n represents the (n + 1)th bits of I0 , I1 and S, respectively. Table 2 shows thetruth table of a bit-serial comparator. Note that the register in the equivalent
CMOS circuit is removed in the FFC element by exploiting the following
write scheme of the FCs. When the EPD applied across an FC is +V D D, thedirection of the remnant-polarization of the FC is set to left. When the EPD
applied across an FC is −V D D, the direction of the remnant-polarization of
the FC is set to right. When the EPD applied across an FC is 0, the directionof the remnant-polarization of the FC is unchanged. By exploiting this featureof an FC, the FFC in BI COMP mode performs as a bit-serial comparator as
follows. When I0n < I1n , the stored bit S n is set to “0”. When I0n > I1n , S n
is set to “1”. When I0n = I1n , S n is unchanged. As a result, the function of
the BI COMP mode of the FFC element is the same as that of the bit-serial
comparator.
In addition to the bit-serial comparator, the BI COMP mode of the FFC
element also performs as a carry logic of a bit-serial adder since the truth
table of the bit-serial comparator and that of the carry logic are similar. As
shown in Figure 17, the function of the bit-serial adder is I0 + I1 in a bitserial manner. Table 2(a) shows the truth table of the carry logic, and the truth
table can be transform into Table 2(b) which is similar to the truth table of

n

I0
n
I1

Sum logic(based on CMOS)

Sum

n-1

S

n

I1
FIGURE 17
Bit-serial adder.

Carry logic(using an
FFC element)nn-1(Carry)610

S HOTA I SHIHARA et al.
(a) Relationship between I0n , I1n and
Sn .
n

I0
0
0
1
1

n

n

I1
0
1
0
1

(b) Relationship between I0n , I1n and
Sn .

n

n

S (Carry )0n-1
S (unchange)n-1
S (unchange)
1

n

I0
0
0
1
1

n

I1
0
1
0
1

n

S (Carry )n-1
S (unchange)01
n-1
S (unchange)

TABLE 3
Truth table of the carry logic

the BL COMP mode of the FFC element. Exploiting this similarity, the carrylogic can be implemented using BI COMP mode of the FFC element. Notethat S n−1 is generated by reading the store data of the FCs. Figure 18 shows
the carry logic implemented using BI COMP mode of the FFC element.
3.3 FFC element for Multiple-Valued Logic
The circuit of the FFC element for multiple-valued logic is the same as thatfor binary logic. The feature of the multiple-valued FFC element is that an
FFC element stores a three-valued data. Figure 19 shows the fundamental
principle of a multiple-valued FFC element. Values S1 and S2 denote thepolarization directions of the left FC and the right FC, respectively. Depend-

n

I0
Sn

n

I1

S

n-1

Register(a) CMOS carry logic.

VDD

VDD

n

n

I1
VDD VSS
n
1

I

+

-

-

+

I0

n

n

I1

VSS VDD+-

EPD(b) FFC element.

I1

Sn

n

I0

n

I0
Sn
+

-

EPD

(c) Equivalent circuit.

FIGURE 18
Carry logic implemented using BI COMP mode of the FFC element.

F ERROELECTRIC -C APACITOR E LEMENT

611

EPD directions
applied across the FCs

VIm

VSS

t0

t1

S0=1

S1=0

+

+

-

-

EPD: small EPD: large
VG ≈ VIm
Out =1 Im > 0
0 Otherwise(a) Logical threshold value = 0

VIm

VSS

VIm

VSS

t0

t1

t0

t1

S0=0

S1=0

S0=1

S1=1

+

+

+

+

-

-

-

-

EPD: middle EPD: middle

EPD: middle EPD: middle

VG = VIm / 2

VG = VIm / 2

Out =1 Im > 0.5
0 Otherwise

Out =(i) Set (S0, S1) = (0, 0)

1 Im > 0.5
0 Otherwise(ii) Set (S0, S1) = (1, 1)(b) Logical threshold value = 0.5.

VIm

VSS

t0

t1

S0=0

S1=1

+

+

-

EPD: large-

EPD: small
VG ≈ VSS

Out = 0(c) Logical threshold value = 1.

FIGURE 19
Fundamental principle of a multiple-valued FFC element.

ing on S1 and S2, there exists three threshold functions whose thresholdvoltages are different from each other. Note that the same value is stored
in Figure 19(b) by two different sets (S1, S2) = (0, 0) and (1, 1). The logical value of the stored bit is S ∈ 0, 0.5, 1; the logical value of the external

612

S HOTA I SHIHARA et al.

Logical threshold value

Im

Out

0
0
0
0.5
0.5
0.5
1
1
1

0
0.5
1
0
0.5
1
0
0.5
1

0
1
1
0
0
1
0
0
0

TABLE 4
Truth table of the MUL THR mode of the FFC element

input is Im ∈ 0, 0.5, 1; the logical value of the output is Out ∈ 0, 1. The circuit executes the following threshold function, and Table 4 shows the truth
table.

Out =

1
0

Im > S
otherwise.

(1)

To execute the threshold function, voltage VIm is applied to terminal t0 , andvoltage VSS is applied to terminal t1 . Voltage VIm is the voltage of Im . Whenthe logical value of a signal is “0”, the voltage of the signal is VSS. When the
logical value of a signal is “0.5”, the voltage of the signal is VDDL which
is lower than VDD. When the logical value of a signal is “1”, the voltage ofthe signal is VDD. Figures 19(a), (b) and (c) are arranged in an increasingorder of the logical threshold value. Note that the white arrows, the grayarrows and the black arrows on the FCs represent S = 0, S = 0.5 and S = 1,
respectively.
Figure 19(a) shows the FC-based circuit in which the threshold voltage
is smallest, and the logical value of the stored bit S is “0”. In Figure 19(a),the direction of the remnant-polarization of the left FC is right, and that of
the right FC is left. Since the direction of the EPD applied across each FC isleft, the capacitance of the left FC is much larger than that of the right FC.
Since the gate voltage of the pass transistor VG is generated by the capacitive
coupling effect, the EPD applied across the left FC is much smaller than thatof the right FC. Therefore, voltage VG is approximately the same as voltage
VIm . As a result, if Im > 0, the pass transistor is ON and then Out is “1”.
Otherwise, the pass transistor is OFF and then Out is “0”.
Figure 19(b) shows the FC-based circuits in which the threshold voltages
are larger than Figure 19(a), and the logical values of the stored bit S are“0.5”. In the following, the set (S0, S1) = (0, 0) is used for the threshold

F ERROELECTRIC -C APACITOR E LEMENT

613

function since it executes a non-destructive operation, and the set (S0, S1) =(1, 1) does not. In Figure 19(b)(i), the direction of the remnant-polarizationof the left FC and that of the right FC are the same. Since the direction of the
EPD applied across each FC is left, the capacitance of the left FC and that of
the right FC are the same. Since the gate voltage of the pass transistor VG isgenerated by the capacitive coupling effect, the EPD applied across the left
FC is the same as that applied across the right FC. Therefore, voltage VG isapproximately the same as voltage VIm /2. As a result, if Im > 0.5, the passtransistor is ON and then Out is “1”. Otherwise, the pass transistor is OFF
and then Out is “0”. Similarly, in Figure 19(b)(ii), voltage VG is approximately the same as voltage VIm /2. As a result, if Im > 0.5, the pass transistor
is ON and then Out is “1”. Otherwise, the pass transistor is OFF and then Out
is “0”. In a typical manner, Figure 19(b)(ii) executes a destructive operation
when VIm is VDD for the following reason. In the left FC and the right FC,
the direction of the EPD applied across the each FC is opposite to that of
the remnant-polarization of the FC. When VIm is VDD, the amount of EPD
is larger than the coercive voltage. Therefore, the remnant-polarization directions of the FCs are changed. Note that, if VIm is VSS or VDDL, the amountof EPD is smaller than the coercive voltage; therefore, 19(b)(ii) executes a
non-destructive operation.
Figure 19(c) shows the FC-based circuit in which the threshold voltage islarger than Figure 19(b), and the logical value of the stored bit S is “1”. In
Figure 19(c), the direction of the remnant-polarization of the left FC is left,
and that of the right FC is right. Since the direction of the EPD applied acrosseach FC is left, the capacitance of the left FC is much smaller than that of theright FC. Since the gate voltage of the pass transistor VG is generated by thecapacitive coupling effect, the EPD applied across the left FC is much larger
than that of the right FC. Therefore, voltage VG is approximately the same as
voltage VSS. As a result, Out is always “0” regardless of the value of Im .
The modes of the FFC element for multiple-valued logic are as follows,
where Ib is an binary external input, Im is an three-valued external input andSm is a three-valued stored bit.
MUL MEM:MUL THR:MUL XOR:MUL AND:
MUL AND-INV:

Three-valued non-volatile memory for storing S.
Three-valued threshold logic.
Extension of the BI AND mode with addition of astored value “don’t care”.
Ternary CAM cell.
Extension of the BI AND mode with addition of astored value “don’t care”.
Extension of the BI AND-INV mode with addition ofa stored value “don’t care”.

614

S HOTA I SHIHARA et al.

MUL OR:

Extension of the BI OR mode with addition of astored value “don’t care”.
Extension of the BI OR-INV mode with addition of astored value “don’t care”.
Extension of the BI MUL-AND mode with additionof a stored value “don’t care”.
Extension of the BI MUX-OR mode with addition ofa stored value “don’t care”.
Same function of the BI COMP mode.

MUL OR-INV:
MUL MUX-AND:
MUL MUX-OR:
MUL COMP:

Figure 20 shows the MUL THR mode of the FFC element. In this mode,
the FFC element performs as a three-valued threshold logic gate. Its equivalent circuit is the same as Figure 19, and the function is the same as Eq. 1.
For the stored value “0.5”, the remnant-polarization directions of the FCs are
set to be the same as that of Figure 19(b)(i). This is because Figure 19(b)(i)
executes a non-destructive operation even when VIm is VDD.
Figure 21 shows the MUL XOR mode of the FFC element. The external
input is a binary signal, and the stored bit a three-valued data. This mode isan extension of the BI XOR mode with the addition of a stored value “0.5”.
Table 5 shows the truth table of this mode. In addition to values “0” and “1”,the FCs store value “0.5”. Value “0.5” value performs as a don’t care, andvalue “0.5” stored in the FCs causes the output Out to be “0” regardless of thevalue of the external input Ib . When the stored value is either “0” or “1”, thebehavior of the MUL XOR mode is the same as the BI XOR mode. Figures
21(a)(i) and 21(b)(i) show the behaviors of the MUL XOR mode when thestored value is “0.5”. Note that the gray arrows on the FCs represent S = 0.5.
Figure 21(a)(i) shows the behavior when Ib is “0”. The equivalent circuit of
Figure 21(a)(i) is the same as Figure 19(b)(i). Since VDDL is corresponds
to the voltage of logical value “0.5”, the value “0.5” is not larger than thestored value “0.5”. Therefore, the output Out is “0”. Figure 21(a)(ii) shows

VDD

VSS

VIm
VDD VSS
VSS

+
-

+

VIm
VDD VSS
VSS

OFF

Out
(a) FFC element.

FIGURE 20
MUL THR mode of the FFC element.

VIm

VSS
S0
+

S1
-

+

-

Out
(b) Equivalent circuit.

F ERROELECTRIC -C APACITOR E LEMENT

VI0

VDDL

VI0

VDDL
VI0

VI0

VSS

+

-

-

+

615

VSS

VDDL
VI0

S0

VI0
+

VSS

OFF

S1
-

+

-

Out = 0Out = 0(ii) Equivalent circuit.

(i) FFC logic element.
(a) S = 0.5 and I0 = 0.

VI0

VDDL

VI0

VDDL
VI0

VI0

VSS

+
-

-

VSS

VDDL
VI0

S0

VI0
VSS

+

-

S1

+

-

+

OFF

Out = 0Out = 0(ii) Equivalent circuit.

(i) FFC logic element.
(b) S = 0.5 and I0 = 1.

FIGURE 21
MUL XOR mode of the FFC element.

the behavior when Ib is “1”. The equivalent circuit of Figure 21(b)(i) is thesame as Figure 19(b)(ii). Similarly to 21(a)(i), the output Out is “0”. As aresult, the output Out to be “0” regardless of the value of the external input Ib .
Note that the MUL XOR mode executes a non-destructive operation even if
the equivalent circuit of Figure 21(b)(i) is the same as Figure 19(b)(ii), sincea low voltage VDDL is used as the apply voltage to the FCs. The MUL XOR
mode of the FFC logic also performs as a ternary CAM cell. A binary CAM
cell stores either value “0” or value “1”. In addition to values “0” and “1”, aternary CAM cell [8] stores value “0.5”. Value “0.5” is a don’t care, is used

S

I0

Out

0
0
1
1
0.5
0.5

0
1
0
1
0
1

0
1
1
0
0
0

TABLE 5
Truth table of the MUL XOR mode of the FFC element

616

S HOTA I SHIHARA et al.

for a wild-card operation. The wild-card operation means that value “0.5”stored in a cell causes the output Out be “0” regardless of the value of theexternal input. As a result, the truth table of the ternary CAM cell is the sameas that of the MUL XOR mode.
Similarly to the MUL XOR mode, modes MUL AND, MUL ANDINV, MUL OR, MUL OR-INV, MUL MUX-AND and MUL MUX-OR are
respectively extensions of modes BI AND, BI AND-INV, BI OR, BI ORINV, BI MUX-AND and BI MUX-OR with addition of a stored value “don’tcare”.

4 SIMULATION
The proposed logic is designed using a 0.35μm-CMOS/0.6μm-ferroelectriccapacitor process. We compare an FFC element with the equivalent CMOS
circuit and the equivalent CFC-based circuit by using an HSPICE simulation.
The supply voltage and the temperature are set to 4.0V and 25˚C, respectively.
Table 6 summarizes the comparison results among a binary FFC element,
the equivalent CMOS circuit and the equivalent CFC-based circuit. The structures of the equivalent CMOS circuit and the equivalent CFC-based circuit
are shown in Figures 22 and 23, respectively. The equivalent CFC-based circuit is modified from the original CFC element to achieve the same function as the binary FFC element. Compared to the equivalent CMOS circuit,the transistor count and the energy consumption are respectively reduced by
95% and 66% with almost the same delay. Because FCs are placed directly
on top of the CMOS transistors, the area overhead of the FCs is very small
and the area of the CFC element is approximately proportional to the transistor count. Therefore, the area is greatly reduced in the FFC element becauseof its small transistor count. Moreover, the FFC element greatly reduces the

Binary FFC(Proposed)

CMOS

CFC

Transistor count

167

14

8

Ferroelectric capacitor count

0

4

2

Delay [ps]

599

545

601

Energy / operation [fJ]

1067

502

364

92407

0

Standby power [fW]
Volatility

Volatile Non-volatile0
Non-volatile

TABLE 6Comparison result among a binary FFC element, the equivalent CMOS circuit and the equivalent
CFC-based circuit

F ERROELECTRIC -C APACITOR E LEMENT

t0

t1

SRAM
S

RegisterS

617

Bit-serial comparator

Mode select signal

MUX

FIGURE 22
Equivalent CMOS circuit of a binary FFC element.

t0

t1

t2

t3

t4
t5
t6
S

S

t7
t8
FIGURE 23
Equivalent CFC-based circuit of a binary FFC element.

standby power, because no permanent voltage supply is required for holding
the stored data. Compared to the equivalent CFC-based circuit, the transistor
count, the FC count and the energy consumption are respectively reduced by
43%, 50% and 27% with 11% delay overhead. The small energy consumptionof the FFC element is because of its small transistor and FC counts.
Table 7 summarizes the comparison result among a multiple-valued FFC
element, the equivalent CMOS-based circuit and the equivalent CFC-based

618

S HOTA I SHIHARA et al.

Multiplevalued FFC(Proposed)

CMOS

CFC

Transistor count

217

20

8

Ferroelectric capacitor count

0

6

2

Delay [ps]

831

1005

1363

Energy / operation [fJ]

1330

838

463

Standby power [fW]

1191420Volatility

0Volatile Non-volatile

Non-volatile

TABLE 7Comparison result among a multiple-valued FFC element, the equivalent CMOS circuit and theequivalent CFC-based circuit

circuit. The structures of the equivalent CMOS circuit and the equivalent
CFC-based circuit are shown in Figures 24 and 25, respectively. The equivalent CFC-based circuit is based on binary logic and executes the same function as the multiple-valued FFC element. Compared to the equivalent CMOS
circuit, the transistor count and the energy consumption are reduced by 96%
and 65%, respectively. The delay overhead of the FFC element is 64%, andthe reason is as follows. When the logic value of either the input of the FFC
or the logic value of the stored data is “0.5”, even if the case that the pass transistor is set to “ON” and its gate voltage is larger than the threshold voltage,
the gate voltage is much smaller than “VDD”. In this case, the pass transistor
is not completely “ON”, and the delay increases. Compared to the equivalent

t1

SRAM

SRAM
S1

S0

RegisterS0

Threshold
logic

t0

Bit-serial comparator

Mode select signal 0~2

MUX

Mode select signal 4

MUX

MUX

FIGURE 24
Equivalent CMOS circuit of a multiple-valued FFC element.

Mode select signal 3

F ERROELECTRIC -C APACITOR E LEMENT
t0

t1

t2

t3

t9

619
t10

t11

t4
t5
t6
S0

S0

S1

t7
t8

FIGURE 25
Equivalent CFC-based circuit of a multiple-valued FFC element.

CFC-based circuit, the transistor count, the FC count and the energy consumption are respectively reduced by 60%, 67% and 45% with 36% delay
overhead. The small energy consumption of the FFC element is because of
its small transistor and FC counts.

5 IMPLEMENTATION ISSUESIn this paper, the proposed circuit is designed using a 0.35um-CMOS/0.6umferroelectric-capacitor process. The supply voltage is 3.3V which is higher
than the recently scaled CMOS processes. In the scaled CMOS processes, thesupply voltages are difficult to make lower compared to the 90 nm process,since the threshold voltages of MOSFETs are set to high voltages for inhibiting the standby power increase. For example, the standard supply voltage ina 90nm process is 1.0V, and in a scaled process such as 65nm is increased
to 1.2V. In recently FCs, the operating voltage is 1.3V [9] which is near the
standard supply voltage of MOSFET in a 65nm technology node. Moreover,many studies of low voltage techniques for FCs are undergoing [9–11], andthe operating voltage of FCs is expected to become lower in the future.
Typical FC-based circuits suffer from reliability issues and perform
destructive operations. To solve these problems by circuit design, the CFC
element has been proposed [6]. The reliable technique proposed in the CFC
element can be used in the proposed FFC element. Reference [6] has proposed a restore scheme to achieve high durability for the repetitive execute
cycles. The restore scheme is executed after the operation. In this scheme, theapplied voltages to the FCs are inverted from that in the operation, in orderto recover the remnant-polarization charge in the FCs. This scheme provides

620

S HOTA I SHIHARA et al.

Area of non-volatilememory devices
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000000000000000000000000000000000000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0
000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 00 00 00 00 00 00 00 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
0000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000 000 000 000 000 000 000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0 000000000000000000000000000000000000000
00 000 000 000 000 000 000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000000000000000000000000000000000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
0000000000000000000000000000000000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Area of MOSFETs

Total area of the architecture
FIGURE 26
Total area of a logic-in-memory architecture.

a high durability for the repetitive execute cycles. This technique also can beused in the proposed circuit to achieve high reliability.
The benefits of FC-based architectures compared to the spin-based architectures are low-power and high-speed [12]. Different from spin-based
devices, the FC is capacitance-based device, and then no direct current flows
in operation. As a result, low power is achieved. Moreover, the merit of small
switching charge of the FC enables the high-speed. The drawback of FCbased architectures compared to the spin-based architectures is assumed tobe the area, since spin-based devices is expected to become smaller than the
FC in the scaled processes. However, the total area of a logic-in-memoryarchitecture based on the proposed circuit is determined by the larger one of
the area of the non-volatile memory devices and the area of the MOSFETs.
This is because these non-volatile memory devices are placed directly on the
top of the MOSFETs, as shown in Figure 26. When the proposed circuit isdesigned using a 0.35μm-CMOS/0.6μm-ferroelectric-capacitor process, thearea of the MOSFETs is about five times larger than that of the FCs, anddetermines the area of the architecture. In this case, the area of the FC-basedarchitecture and that of the spin-based architecture are the same. Even inscaled processes, this trend will likely continue for a long time until the circuit area of MOSFETs is larger than that of FCs.
In addition, the proposed circuit is used for the capacitance-based nonvolatile devices, and not only for the FC. The FC is one type of capacitancebased non-volatile devices that we can use. In the future, more advanced
capacitance-based memory devices than the FC will probably be proposed.
In those devices, the proposed circuit will be more useful. Moreover, theproposed circuit structure can be also applied to other storage devices. For

F ERROELECTRIC -C APACITOR E LEMENT

621

example, spin-based devices can be used instead of FCs, and the functionof an FFC element can be implemented by using resistive voltage division
instead of capacitive coupling effect.

6 CONCLUSION
This paper proposed low-power and high-functional ferroelectric-based logic
circuits called FFC elements for logic-in-memory architectures, in order tosolve the “Von Neumann bottleneck” and reduce the standby power. In an
FFC element, storage and a logic function are integrated on the ferroelectriccapacitors, and the FFC element is suitable for logic-in-memory architectures
which can solve the “Von Neumann bottleneck”. The storage of the FFC
element is non-volatile, and the standby power is greatly reduced because
no permanent voltage supply is required to hold the stored data. Moreover,
for area efficiency, the FFC element can flexibly change the access transistor
network and introduces the multiple-valued storage and logic techniques, inorder to achieve high functionality with a small number of transistors andFCs.
The proposed FFC element can be exploited in SIMD (Single Instruction
Multiple Data) architectures such as for image processing as shown in Figures 27 and 28. In SIMD architectures, the area of the control circuit is small,and the large proportion of the area is occupied by the processing elements.
Therefore, the efficient implementation for processing elements is important. Since each processing element consists of the circuits for the storageand logic functions, the FFC elements are suitable for its implementation.
This is because the FFC elements integrate the storage and logic functions.
In the FFC-based SIMD architecture shown in Figure 27, each processing
element executes a word. Since the processing elements are controlled by

FFC-based processing element
FFC-based processing element

Control circuit
FFC-based processing element
FFC-based processing element
FFC-based processing element

呍呍呍

呍呍呍

呍呍呍

呍呍呍

呍呍呍

呍呍呍

FIGURE 27
SIMD architecture exploiting FFC elements.

Interconnection network (Local)

FFC-based processing element

Interconnection network (Local)

Control circuit

622

S HOTA I SHIHARA et al.
In0

In1

F0 S0

F1 S1

FFC element

Precharge
controlPrechargetransistor

…

Out

…
Wired OR

In2
Wired AND

F2 S2

…
…
…

…
Evaluatetransistor

FIGURE 28
FFC-based processing element.

the same control circuit, the same operation is simultaneously performed ona large number of words. As a result, word-parallelism is achieved. Moreover, as shown in Figure 28, a processing element consists of FFC elements,and each FFC element has its own storage and logic function. Therefore, thesame operation is simultaneously performed on a large number of bits in aword, and bit-parallelism is achieved, like Content-Addressable Memories(CAMs).
ACKNOWLEDGMENT
This work is supported by VLSI Design and Education Center (VDEC) the
University of Tokyo in collaboration with Cadence Design Systems Inc. andSynopsys Inc. This work is partially supported by ROHM CO., LTD.
REFERENCES[1] Hariyama, M., Ishihara, S., Idobata, N., and Kameyama, M. (2008). Non-volatile MultiContext FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. In
Proc. International Conference on Engineering of Reconfigurable Systems & Algorithms(ERSA), pages 309–310.

F ERROELECTRIC -C APACITOR E LEMENT

623[2] Ishihara, S., Idobata, N., Hariyama, M., and Kameyama, M. (2009). A Fine-Grain SIMD
Architecture Based on Flexible Ferroelectric- Capacitor Logic. In Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pages 271–
274.
[3] Ishihara, S., Idobata, N., Hariyama, M., and Kameyama, M. (2010). A Switch Block Architecture for Multi-Context FPGAs Based on Ferroelectric-Capacitor Functional Pass-Gate
Using Multiple/Binary Valued Hybrid Signals. IEICE Trans. Inf. & Syst., E87-D(8), pages
2134–2144.
[4] Ishihara, S., Idobata, N., Nakatani, Y., Hariyama, M., and Kameyama, M. (2011). A
Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional PassGates Using Multiple/Binary Valued Hybrid Signals. Journal of Multiple-Valued Logicand Soft Computing, 17(5-6), pages 553–580.
[5] Kimura, H., Hanyu, T., Kameyama, M., Fujimori, Y., Nakamura, T., and Takasu, H. (2003).
Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI. In
IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers,
pages 160–161.
[6] Kimura, H., Hanyu, T., Kameyama, M., Fujimori, Y., Nakamura, T., and Takasu, H. (2004).
Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI.
IEEE Journal of Solid-State Circuits, 39(6), pages 919–925.
[7] Noda, H., Nakajima, M., Dosaka, K., Nakata, K., Higashida, M., Yamamoto, O., Mizumoto, K., Tanizaki, T., Gyohten, T., Okuno, Y., Kondo, H., Shimazu, Y., Arimoto, K.,
Saito, K., and Shimizu, T. (2007). The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. IEEE Journal of Solid-State Circuits,42(1), pages 183–192.
[8] Pagiamtzis, K., and Sheikholeslami, A. (2004). Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey. IEEE J. Solid-State Circuits, 41(3), pages
712–727.
[9] Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara,R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H.,
Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., Nitayama, A. (2010). A scalable
shield-bitline-overdrive technique for 1.3V Chain FeRAM. In IEEE International SolidState Circuits Conference Digest of Technical Papers (ISSCC), pages 262–263.
[10] Qazi, M., Clinton, M., Bartling, S., Chandrakasan, A.P. (2011). A low-voltage 1Mb
FeRAM in 0.13m CMOS featuring time-to-digital sensing for expanded operating marginin scaled CMOS. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 208–210.
[11] Qazi, M., Clinton, M., Bartling, S., Chandrakasan, A.P. (2012). A Low-Voltage 1 Mb
FRAM in 0.13 um CMOS featuring time-to-digital sensing for expanded operating margin.
IEEE Journal of Solid-State Circuits, 47(1), pages 141–150.
[12] Takashima, D. (2011). Overview of FeRAMs: Trends and Perspectives. In Proc. NonVolatile Memory Technology Symposium (NVMTS), pages 36–41.