ELTRAN® ; Novel SOI Wafer Technology
Takao Yonehara and Kiyofumi Sakaguchi
ELTRAN Business Center, Canon Inc.,
6770 Tamura, Hiratsuka, Kanagawa, 254-0013, Japan
http://www.canon.com/eltran/

Abstractinch) diameter; and SOI thickness uniformityof +_ 1.1%, which is even better than that of 8inch wafers, has been achieved.

®

ELTRAN (Epitaxial Layer TRANsfer) wafers
are the first and to date only manufacturable
and commercially available SOI (silicon-on-insulator) wafers formed by bonding and etching-back porous Si in conjunction with hydrogen annealing. These wafers were developed
and have been produced since 1990 by Canon
Inc., Japan. The newest technique established
for wafer fabrication is highly reproducible splitting within the porous Si layer by means of awater jet, which allows the seed wafer to bereused several times to reduce manufacturingcosts. The thicknesses of both the SOI and theburied oxide layers are precisely controlled overa very wide range, from the extremely thin
10nm to as thick as 2-3µm, with thickness uniformity of less than +_ 5%. No COPs (Crystaloriginated Particles or Pits) are generated in theactive SOI layers by the epitaxial growth process. The buried oxides are thermally grown on
epitaxial Si layers and have no pinholes. An
atomically-flat surface is achieved in the SOI
wafers by means of a newly developed processof annealing in hydrogen. Wafer sizes havebeen successfully expanded to 300-mm (12-

1. Introduction
SOI (silicon-on-insulator) technology has
been at somewhat of a standstill for quite along time, but now we are finally approachinga long-awaited period, with CMOS (complementary metal oxide semiconductor) applications of thin-film SOI wafers in particular about
to reach a stage where they can be put to practical use. In the future it is anticipated that there
will be new developments in the area of mainstream CMOS-LSI (large-scale integration) thatwill enable devices to be achieved for low
power, high-speed logic and communications.
Mass production trials of CMOS-LSIs employing SOI wafers were launched before the turnof the century for the purpose of enabling SOI
to be adopted as the newest semiconductor IC
technology for the 21st century.
SOI-Epi wafersTM of ELTRAN ® (Epitaxial
Layer TRANsfer) wafers are SOI wafers originally developed by Canon; they are BESOI (bondand etch-back SOI) wafers that make use of

COP

Bulk Wafer

Epitaxial Wafer

COP
SOI
SiO2

SOI Wafer

Fig.1 COPs in bulk wafer, epitaxial wafer, SOI wafer and SOI-Epi wafer.

10

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SOI-Epi Wafer

the selective etching of porous Si 1,2). The fabrication method used involves combining the
BESOI process with epitaxial growth on porous
silicon that is capable of being etched with ultra-high selectivity and surface-smoothingachieved by hydrogen annealing. Another special feature of the method is that the bonded
wafer is split into two at the porous Si layer,with one part becoming the ELTRAN® wafer andthe other part being reused. This is importantbecause along with product quality, reducing
wafer manufacturing costs is one of the mostimportant requirements for expanding the SOI
market further.
At present, with the goal of showing thefuture potential of our SOI wafers, we are striving to develop 300mm-diameter wafers andsub-50nm ultra-thin films, as well as wafer recycling techniques aimed at reducing costs.

2. Special Features of ELTRAN®
a. SOI-Epi WafersTM
Figure 1 shows the characteristic featuresof bulk wafers and epitaxial wafers used incurrent Si processes, along with SOI wafers andthe SOI-Epi wafersTM that we have proposed.
The reason that epitaxial wafers have come to
be used is that the size of devices has approached that of COPs (0.1 〜 0.2µm), and
COPs cause degraded reliability of the gate
oxide films of devices. In SOI devices, thin-film
thicknesses have become comparable in size
to, or even smaller than, COPs, and thus COPs
are far more damaging to SOI devices than tobulk wafers. If an SOI wafer is immersed in HF
solution, the buried oxide film underneath becomes directly etched through the COPs, whichis easy to detect; such a defect is called an “HF
defect”. The density of HF defects must be no
more than about 0.1 /cm2. It is anticipated that
this value will drop down to around 0.01 /cm2
with further advances in miniaturization in the
future. It is thus considered that technology

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Epitaxial Si

before surface smoothing
Seed Wafer

SOI
SiO2

Porous Si

Bonding
Seed Wafer
Reuse
Handle Si Wafer

Polishing

H2 Annealing

Handle Si Wafer

Splitting in Porous Si

afer
Seed W

Water
Jet

Etching & H2 Annealing
Si

Handle Si Wafer

Fig.2 Surface smoothening of SOI wafers by polishing and H2 annealing.

whereby an epitaxial layer is used as the SOI
layer, i.e. COP-free SOI-Epi waferTM technology,
should be useful as far as thin-film SOI devices
are concerned.

b. Surface-Smoothing Techniques
Figure 2 shows the surface smoothnessof SOI wafers. Regardless of the manufacturing technique used, the surface just after the
SOI structure has been formed is much rougher
than that of a polished bulk wafer. This roughness could be removed by CMP (chemical mechanical polishing) to achieve a smoothness
comparable to that of a polished bulk wafer.
This would, however create problems of reduced film thickness, degraded wafer thickness
uniformity, and less control stability during mass
production. These problems would be particularly prominent in ultra-thin-film SOI wafers.
With ELTRAN®, however, the hydrogen anneal-

Si

SiO2

Fig.3 ELTRAN® process flow based on seed wafer reusage.

sphere7) seals its surface pores and smoothes
its surface, thus allowing a high quality epitaxial
Si layer to be formed on top of it.
2) The enormous surface area8) of porous Si contributes to extremely high etching selectivity ofas high as 100,000.
3) The splitting plane can be specified by controlling the internal stress9-11) of porous Si.
Figure 3 depicts the ELTRAN® process flow.
The anodization involves passing a current
through a solution of HF and ethanol with thesingle-crystal Si wafer as the anode in order toform microscopic pores of a few nm in diameter on the surface of the wafer at a density of〜1011 /cm2. The reaction occurs at the far endof the pores, meaning that the pores progressively elongate into the inside of the wafer. By
varying the current density it is easy to create aporous layer that has a multi-layered structure,

an example of which is shown in Fig. 4. In thisexample, the layer of porous Si closest to thesurface was formed using a low current density, after which the current density was raised
and a second layer of different porosity wasformed. It can be seen from the figure that thefirst layer of porous Si contains microscopic
pores of a few nm in diameter. A second layer
containing pores with diameters 2 〜 3 times
greater is formed below this first layer.
Dry oxidation of the porous Si is then carried out at a low temperature of 400˚C12). This
results in oxidization of about 1〜 3nm of theinner walls of the pores, thus preventing thestructure of the porous Si from changing under high-temperature treatment.
The porous Si is then baked at 1000 〜
1100˚C in a hydrogen atmosphere in a CVD(chemical vapor deposition) epitaxial reactor.

ing process reduces the surface roughness (Rrms)of approximately 10nm by a factor of about
100, and as a result even the atomic steps canbe observed 3). Moreover, this new surface
smoothing method enables the film thickness
to be reduced to less than 1nm4).
1st porous Si

3. Process
Even though porous Si5) was first discovered back in 19566), the ELTRAN® manufacturing process represents the only case where ause for porous Si in industrial manufacturing
has been successfully found. This process comprises a number of sub-processes that harmoniously unite the three special features of porous Si, which are as follows:
1) Annealing porous Si in a hydrogen atmo-

2nd porous Si

200nm

Fig.4 Cross-sectional micrographs of double-layered porous Si formed by changing anodic current.

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100nm(a)(b)

Fig.5 Porous Si surface (a) before and (b) after H2 pre-baking.

Figure 5 shows SEM micrographs taken froman oblique angle before and after the hydrogen pre-baking7). It can be seen that the prebaking causes the pores in the porous Si surface to close up to the extent that the poredensity drops from about 1011/cm2 to less than
104 /cm2, and hence the surface is smoothed.
The pre-baking enhances surface diffusion,
which causes the surface pores to close up. A
pre-injection method13) was further devised
whereby a small additional amount of Si is provided from the gas phase during the hydrogenpre-baking. As of the present, we have achieved
a secco-etch defect density of the order of only
10 1 /cm 2 . After the pre-injection, epitaxial

method9-11, 15) is used to split the bonded wafer
parallel to its surface close to the interface between the two layers This procedure is described in detail below.
After splitting, the first porous Si layer remains on the handle wafer side; this layer isuniform in thickness across the whole wafer.
The handle wafer part is then etched using asolution containing a mixture of HF, H2O2 andH2O8). The etching characteristics of porous Si
and non-porous Si are shown in Fig. 6. It canbe seen that with the use of the HF/H2O2/H2O
mixture, once a certain incubation period has
passed, the porous Si is etched virtually all at
once. The selectivity of this etching is as highin a sideways direction. Eventually, the porous
structure can no longer support itself and collapses. Since each wall between neighboring
pores is etched from both sides, the thicknessof epitaxial Si that must be etched is effectively
half of the thickness of the wall, which is at
most about 10nm. This means that it is possible to uniformly etch porous Si layers morethan 10µm thick across the whole surface of
the wafer, and since the selectivity is as high as
100,000, there is virtually no degradation of
the thickness uniformity in the SOI layer.
If heat treatment in a hydrogen-containing atmosphere is now carried out, the roughsurface (Fig. 7(a)) just after selective etching becomes smoothed as shown in Fig. 7(b)3). The
surface roughness was measured by AFM(atomic force microscopy). For a 1µm × 1µm
region, the hydrogen annealing reduced theroot mean square roughness to about 0.1nm,
which is at least as good as that of the polished bulk wafer. Moreover, even the atomic
steps could be seen, showing that smoothness
down to the atomic scale was achieved.
After splitting, residual porous Si is removed from the seed wafer, which can thenbe recycled and put back into the ELTRAN®
manufacturing process again and again. Thisis described in detail in the next section.

4. Seed Wafer Reusage

growth is carried out at about
900 〜 1000˚C.
a. Cost Simulation
HF/H2O2
HF/HNO3/CH3COOH
HF
Next, the surface of the epiThe basic ELTRAN® concept
310
taxial Si layer is thermally oxiof ‘split/recycle/reuse’ involves
dized. The resulting oxide film will
reusage of the seed wafer. It can
2
10
become the BOX (buried oxide)
be seen from the ELTRAN ®
PorousSifilm of the SOI wafer.
manufacturing process that the1
10
The surface of the thermallyseed wafer itself is ultimately not0grown oxide film and the Si
used in any part of the SOI wa10
handle wafer that will become
fer. This is a special feature ofSi-1
the supporting substrate are next
ELTRAN ® wafers not found in
10
cleaned, and then the surfaces ofany other SOI wafers. This fea-2
the two wafers are pushed toture arises because 1) the seed
10gether at room temperature,
wafer is not used as the handle-3
10
upon which they bond to one anwafer, and 2) the SOI layer
0
1
2
3
4
5
10
10
10
10
10
10
other by van der Waals forces.
comes from the epitaxial layerTime (min)After that, heat treatment is carrather than from part of the seedFig.6 Etching characteristics of porous Si (closed symbols) and nonporous Si (open symbols) obtained
ried out to form covalent bonds through immersion in HF/HNO /CH COOH (triangles), HF/H O (circles) and HF (rectangles) as a wafer. The special features of33
2 2
and thus strengthen the bond- function of etching period.
SOI-Epi wafersTM come to the14)
ing between the two surfaces .
fore all the more due to thisas 100,000, meaning that the etching does not
Moreover, using a quartz wafer as the handle
technique for reducing the manufacturing
cause any degradation of the thickness uniforwafer makes it possible to manufacture lightcosts. Turning to the handle wafer, a new
mity of the SOI layer. The etching solution pentransparent ELTRAN® wafers.
handle wafer is put into the manufacturing proetrates into the pores of the porous Si by capThe porous Si layer in the bonded wafer
cess each time an SOI wafer is produced; theillarity, and then etches the walls of the pores
has a double-layer structure. A water-jet
epitaxial layer is also grown anew each time,

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(Eqn.1)
Here, Y is the SOI wafer material cost, H isthe price of the handle wafer, S is the price ofthe seed wafer, R is the price of reclaiming theseed wafer, and n is the number of times that

200nm

200nm

(a)

(b)

Fig.7 High-resolution, oblique-view micrographs of (a) as-etched ELTRAN® wafers and (b) H2-annealed ELTRAN® wafers.

1st Porous Si

2nd Porous Si

Seed Wafer

the seed wafer is used.
As n increases, according to the above
equation:(Eqn.2)
In other words, the SOI wafer material cost
becomes the price of the handle wafer plus theprice of reclaiming the seed wafer, and the original price of the seed wafer is essentially irrelevant.

0

-0.1

Ram an Shift (cm-1)

b. Double Porous Si Layers 9-11)

Porosity
~40%

-0.2

-0.3
Porosity
~50%

-0.4

-0.5

-6

-4

-2

2

0

4

6

8

Fig.8 Raman shift depth profile around the 2nd porous Si with different porosity of 40% and 50% just before splitting.

Stacked Porous Si

Uniform Porous Si

Seed Wafer

Seed Wafer"Zipper"
2nd Layer
1st Layer
Si Epi Layer
Oxide

Handle Wafer

Handle Wafer

Fig.9 Schematic drawings of crack propagation in double- and single-layered porous Si.

and of course the thermally grown oxide filmthat becomes the BOX is formed anew eachtime by oxidizing the epitaxial layer. In this way,
because each completed SOI wafer is always
made entirely of new materials, there is no degradation in the product quality of the SOI wa-

fers even if the seed wafer is reused again andagain.
We next examine the extent of the reduction in wafer material costs due to this repeatedreuse of the seed wafers. The following equation represents the wafer material costs when

Raman spectroscopy was used to measure
the strain around the second porous Si layer
just before splitting for two wafers with second porous Si layers of different porosity (40%and 50%). The porosity of the first porous Si
layer was the same for both wafers. The Raman
shift depth-profiles observed in both wafers
were similar (Fig. 8). It can be seen that the
Raman shift showed a maximum negative value
in the second porous Si layer close to the interface between the two layers. Moreover, thisshift was larger in magnitude when the porosity of the second layer was the higher of thetwo values. The splitting plane corresponds tothe position of maximum negative Raman shift
in the depth direction. In other words, splitting
occurs at the plane where the stress is at a maximum.
This shows that the porosity of the second porous Si layer is an extremely importantfactor in successfully restricting the splitting
plane to be within a certain limited region. Figure 9 shows schematic drawings of the progression of the splitting plane for a single-layered porous Si of uniform porosity and doublelayered porous Si comprising two layers of different porosity. Splitting can occur at any depth
if the porosity is uniform throughout the porous Si layer, meaning that the progression of
the splitting plane cannot be controlled andcracks may reach as far as the seed wafer orthe epitaxial layer. With double-layered porous
Si, however, splitting occurs close to the interface between the two layers. As a result, thelayers act to protect the seed wafer and theepitaxial Si layer respectively, thus providing adefinitive means for raising yield.
We next evaluated the stress values in the

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(004) Lattice Space
expansion

Si-sub. contraction

close to the interface between the
two layers. In other words, it is the‘force’ to reduce this strain energythat is the ‘driving force’ that makes
splitting progress uniformly with the
splitting plane remaining close to theinterface.

Oxidation
Epitaxyc. Water Jet Splitting10,11,15)

through a Si wafer. This is why it is thoughtthat the fluid wedge peeling effect is the dominant factor in the splitting of the bonded wafer. Due to the ability of a fluid to change its
shape, the water jet penetrates as far as theperiphery of the bonding interface and causesa buildup of pressure, meaning that the water
hammer pressure is felt across a broad regionof the wafer periphery. Unlike with a solid
wedge, there is not a single point of contact
with the wafer edge, and so splitting can takeplace without stress being concentrated in one
particular place, meaning that cracking of thewafer periphery can be prevented.
In addition, with the solid wedge themechanism is such that splitting is made toproceed by applying a force only to the wafer
edge. This means that as the splitting proceeds,
the wafer is forced to change shape excessively.
This entails a risk of damage, in particular to
the thin-film SOI layer and the buried oxide film
layer. In the worst case, the wafer may even be
broken during splitting. In contrast, with thewater jet the mechanism is such that the wedge
is constantly changing in shape, and thus pressure is exerted across the entire region where
the splitting is proceeding. This means that the

A water jet is used to split thebonded wafer near the interface between the first and second porous Si
layers. We have tried a wide range of
Splittingdifferent splitting methods: thermal
stress, oxidation from the edge of theporous Si, application of ultrasonic
Seed Wafer
waves, insertion of a solid wedge, andinsertion of a fluid wedge using a water jet. Of these methods, thermal
stress had virtually no effect and oxi-0.15 -0.1 -0.05
00.05 0.1
dation caused serious warping of the(degree)wafer. With ultrasonic waves, splitting across the whole wafer was possible, but reproducibility and controllability were poor. Splitting across theFig.10 X-ray diffraction rocking curves of each wafer type before andafter splitting processes.
whole wafer was also possible withboth the solid wedge and the fluid
two layers with the aim of understanding thewedge methods,
splitting mechanism. Figure 10 shows the Xbut the use of a
ray rocking curves before and after splitting.
solid wedge caused
By splitting, the first and second porous Si laywafer damage, as
ers go to the handle wafer side and the seed
will be described inwafer side respectively. For both porous Si laydetail below. Coners, the diffraction peak due to the layers apsidering the probproaches that of the respective substrate, showlems encountereding that there is very little residual stress. It iswith these methods,
thought that this is because the internal stress
we decided toin each of the porous Si layers is released when
adopt the water jet
the layers are split from one another and, as amethod. It is
result, the lattice strain is eased. It was foundthought that whenthat after this release of stress, the ‘in-plane
the bonded wafer isstress’ (here and in the following ‘in-plane
split using a water
stress’ refers to the stress in a plane parallel tojet, the primary
the wafer surface) had dropped from 1.35 ×mechanism is not
109 dyn/cm2 to 1.31×108 dyn/cm2 for the first
cutting but rather Fig.11 Side-view photograph during splitting.
peeling by the fluidlayer and from 1.90 × 109 dyn/cm2 to 2.88 ×
wedge produced by
108 dyn/cm2 for the second layer.
the water jet. The setup we are currently using
splitting can be made to proceed with virtually
The difference in stress between the firstin actual practice involves a straight water jet
no deformation of the wafer. This will be an
and second porous Si layers causes distortion
designed for semiconductor manufacturing, in
extremely advantageous feature when wafer
in a confined region around the interface bewhich only high-purity water may be used.
diameters are increased to 300mm. For the reatween the two, causing strain energy to accuSplitting with a jet pressure of 20 〜
sons described above, we concluded that amulate and thus a high-energy state to be gen60MPa is possible if the nozzle bore is designed
water jet offered the optimum method for theerated. Once splitting starts to occur in this reto be 0.1mm. With this small a bore, however,bonded wafer splitting process, focusing on thegion, the leading edge of the split progresses
the water hammer pressure is on the order of‘fluid wedge’ effect of the water jet in reachin such a way as to reduce the accumulated
0.24 〜 0.43kgf, which is insufficient to cut
ing this decision.
strain energy, and so the splitting plane remains
Seed Wafer

Handle Wafer

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Table 1 ELTRAN® quality achieved (up to 3rd generation) by water jet splitting

ELTRAN®

Water Jet
1st

2nd

3rd

Thickness (SOI /BOX)[nm]100/100

100/100

100/100

100/100

LLS[/wafer]

21.0

19.4

32.8

21.4

∆tSOI
+
- [%]

+
- 2.37+- 2.21+- 2.68+- 2.67

∆tBOX
+
- [%]

+
- 1.00+- 1.08+- 1.05+- 0.80Surface Roughness/Ra
1 m 1 m[nm]

0.107

0.106

0.101

0.121

0.032

0.037

0.043

0.023

434

440

764

692

HF Defect[cm-2]
Secco Defect[cm-2]For the ELTRAN® Epi-B-SOI wafer, a lifetime ofa few hundred microseconds was obtained
throughout the whole of the thin-film SOI layer,
which value was much higher than those ofother SOI wafers 18). It has recently been reported that a “pure” 1/f noise characteristic isobserved in partially depleted floating-body
SOI-MOSFETs fabricated on ELTRAN® wafers,
while floating-body induced pre-kink excess
noise is found in devices formed on other commercially available bonded SOI wafers19). Thisdifference is indicative of the higher quality of
the ELTRAN® obtained by forming the surface
and active SOI layers through epitaxial growthand hydrogen annealing.

6. Scalable Potential
Since our wafers are disc-shaped, from theviewpoint of splitting process efficiency we
decided to adopt a setup whereby the bonded
wafer is clamped in a rotating holder and thewater jet is projected while rotating the wafer.
Figure 11 shows a photograph taken from theside during the splitting process. Due to therotation, the splitting plane progresses in a spiral fashion. To control the progression of the
splitting plane, the nozzle is gradually moved
from the wafer periphery towards the center.
This means that the splitting region can be prevented from progressing unnecessarily, and thus
spiral splitting of high reproducibility can beachieved by incorporating a sequence whereby
the nozzle is gradually moved towards the center of the wafer while controlling the splitting
region.
The mass-production version of the water jet equipment (which uses the ‘cassette-tocassette’ method) has been installed in the production line. The equipment consists of a wafer aligner, a wafer-flipping part, a wafer-cleaning part, a splitting chamber, a loader for loading the bonded wafers, two unloaders for the
split wafers and a double-arm robot fortransfering the wafers. The chamber contains
a splitting part equipped with a rotating holder
as described above. By combining such measures as high accuracy and cleanliness, it waspossible to make the water jet splitting equipment such that it could withstand being usedin the ELTRAN® manufacturing process.
Due to the precise control of the stress inthe porous Si and the fluid wedge effect of thewater jet described above, a bonded wafer
splitting yield of a consistently high value wasachieved even when each seed wafer was used

three times, and in fact it has even become possible to use each seed wafer a fourth time.

5. Quality
Table 1 shows a list of parameters that are
extremely important to the quality of SOI wafers and the corresponding values for ELTRAN®
wafers. The ELTRAN® quality achieved in thepast is shown along with that for three generations of ELTRAN® wafers made using thecurrent splitting/recycling process. It can be seenthat the numbers of HF defects for the three
generations of wafers made using the current
process (0.037, 0.043 and 0.023 /cm2 respectively) are all under 0.05 /cm2. Moreover, thenumbers of secco-etch defects are 440, 764
and 692 /cm2 respectively, which figures arecomparable to those obtained in the past. It
can thus be seen from the table that the quality of the ELTRAN® wafers produced using thecurrent splitting/recycling process is by nomeans inferior to that achieved in the past. It
can also be seen that there is no degradationin product quality even if splitting and recyclingof the seed wafer is carried out repeatedly. Thisis due to the basic ‘seed wafer reusage’ concept unique to ELTRAN ®. Because ELTRAN ®
wafers, regardless of the generation, always
consist of a handle wafer that is introduced into
the manufacturing process anew every timeand an epitaxial Si layer that is grown anew
every time (along with an SiO2 layer formed bythermal oxidation of the surface of this epitaxial
Si layer), it has been possible to manufacture
ELTRAN® wafers with a consistently high product quality.
Electrical properties using ELTRAN® wafers
with such high qualities have been reported.

We first reported that we had successfullysmoothed our SOI wafers by hydrogen annealing to achieve a surface roughness comparable
to that of commercially available Si wafers in
19943). However, Si etching during the hydrogen annealing causes degradation of thickness
uniformity in the SOI layer, and so it is necessary to restrict the amount of such etching. The
etching rate is greatly affected by things likethe equipment setup and the purity of the gas
used. The use of a vertical-type annealing furnace holds the SOI layer thickness reduction
during the hydrogen annealing to less than
1nm, and this makes it possible to manufacture SOI wafers with an extremely thin SOI layer(average thickness approximately 10 nm) having an excellent thickness uniformity of+_ 1.75nm. The SOI layer thickness uniformity isthus determined almost exclusively by that of
the epitaxial Si layer, i.e. it remains more or lessunchanged during the hydrogen annealing. The
thickness uniformity of epitaxial Si layers produced by epitaxial reactors is being continually
improved, due to the demands not only of SOI
but of all Si processes, and it has been reported
that film thickness uniformity of better than+
_ 1% has been achieved with an epitaxial reactor designed for use with 300-mm Si wafers. It
is expected that as wafers of increasingly larger
diameters are produced, further improvementsin thickness uniformity will be made.
As described above, ELTRAN® wafers are
SOI-Epi wafersTM having the special feature ofbeing COP-free, and their low HF defect density attests to this feature. Nevertheless, thenumber of HF defects increases when the HF
solution permeates into any weak points in the
SOI layer, and so it is expected that the number of such defects should vary according to

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the thickness of the SOI layer. It has been confirmed that extremely high product quality ofless than 0.05 HF defects/cm2 is maintained for
SOI layer thicknesses as low as 30nm16). Thisshows that we have already achieved productquality - in terms of both thickness uniformityand HF defect density - that will meet the needsof the new era of ultra-thin 20〜100nm films,
this thickness range being the 2011 target indicated in the 2000 SIA-ITRS.
Device characteristics attesting to the excellent SOI layer thickness uniformity and highcrystal product quality of ELTRAN® wafers havebeen reported in various journals and confer-

Fig.12 300mm-diameter ELTRAN® Wafer.

ences17). For gate lengths of less than 0.1µm,
ultra-thin (4nm) film MOSFETs can suppress
threshold value roll-off and S-value degradation due to short channel effects. For this to beachieved, however, it is very important for ultra-thin films to be highly uniform in thickness.
The usage of conventional equipment, i.e.,
an epitaxial reactor and an annealing furnace,means that the ELTRAN ® manufacturingmethod can easily be applied to larger-diameter wafers. The anodization, bonding, splitting and etching equipment used in the manufacturing process, all of which we designed anddeveloped ourselves, is now able to handle
300mm-diameter wafers. This has already been
demonstrated by using it to manufacture
300mm ELTRAN® wafers (see Fig. 12). In manufacturing, moreover, we achieved thickness uniformity of 147nm+_1.6nm16), which is even better than that of our 200 mm wafers.

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References

7. Summary
Since ELTRAN® wafers are COP-free SOIEpi wafersTM, they have an extremely low HF
defect density. They also have SOI layers ofhighly uniform thickness, achieved through a
combination of extremely good epitaxial Si layer
thickness uniformity, selective etching of porous Si with remarkably high selectivity, and adramatic reduction in the amount of Si etching that occurs during hydrogen annealing of
the SOI surface. As a result, good thickness uniformity is achieved even in wafers with an SOI
thickness of only 10 nm. We have successfully
automated all of the ELTRAN® manufacturing
equipment, andcompleted otherpreparations necessary for mass
production. In sodoing, we haveachieved a consistent level of product quality. Moreover, we have determined that no
new technicalproblems are incurred in applying
the manufacturi n g p ro c e s s t o
300mm-diameter
wafers, because
epitaxial-growthbased SOI technology can be
adopted in existing and commonly used Si wafer manufacturing equipment.
In the future, to enable SOI to be widelyused in mainstream CMOS and logic devices,
analog devices, memories and systems on chips,
we will need to achieve product quality comparable to that of conventional bulk and epitaxial wafers at a reasonable price-level so thatsufficient device development can be carriedout. At the same time, it will be necessary toallow for the risks associated with R&D activities and prior investment of SOI wafer producers. In other words, for the SOI market to expand, SOI wafer manufacturers and device
manufacturers will need to join forces and work
together to construct an effective mass production system.

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