Mosaic Hardware Manual
Version 1.7.0

mosaic Hardware Manual
Version 1.7.0
September 7, 2022
© Copyright 2000-2022 Septentrio nv/sa. All rights reserved.

Septentrio
Greenhill Campus, Interleuvenlaan 15i
3001 Leuven, Belgium

http://www.septentrio.com
Phone:+32 16 300 800
Fax:+32 16 221 640@septentrio

222

1 Table of contents
1

TABLE OF CONTENTS ................................................................................................... 3

2

DOCUMENT CHANGE LOG .......................................................................................... 7

3

MOSAIC GNSS MODULE .............................................................................................. 8

3.1

Overview................................................................................................................... 8

3.2

Mechanical ............................................................................................................. 10

3.3

Absolute Maximum Ratings ................................................................................. 10

3.4
Electrical Characteristics in Operational Conditions ........................................ 11
3.4.1
Power Supply ........................................................................................................ 11
3.4.2
I/O .......................................................................................................................... 11
3.5Power Consumption .............................................................................................. 12

3.6

Environmental ....................................................................................................... 12

4

PINOUT AND I/O DESCRIPTION................................................................................ 13

4.1

Power Supply ......................................................................................................... 14

4.2
Antenna(s) .............................................................................................................. 14
4.2.1
Main Antenna........................................................................................................ 14
4.2.2
Auxiliary Antenna ................................................................................................. 15
4.2.3
Typical Application ................................................................................................ 16
4.3
COM Ports ............................................................................................................... 17
4.3.1
Typical Application ................................................................................................ 174.4
USB Device Interface ............................................................................................. 18
4.4.1
Typical Application ................................................................................................ 18
4.5
Ethernet .................................................................................................................. 19
4.5.1
Typical Application ................................................................................................ 19
4.6
SD Memory Card .................................................................................................... 20
4.6.1
Typical Application ................................................................................................ 21
4.6.2
Data Logging ......................................................................................................... 21
4.7
Clock Frequency Reference .................................................................................. 22
4.7.1
Using the internal TCXO ....................................................................................... 22
4.7.2
Using and external frequency reference ............................................................ 22
3

3
3

4.8

Event/TimeSync inputs ......................................................................................... 23

4.9

PPS output .............................................................................................................. 24

4.10 General Purpose Output (GPx) ............................................................................ 24
4.11 LEDs ......................................................................................................................... 25
4.12 Standby ................................................................................................................... 25
4.13 RTC ........................................................................................................................... 27
5

MOSAIC INTEGRATION .............................................................................................. 28

5.1
Minimal Design ...................................................................................................... 28
5.1.1
Single-Antenna Modules ...................................................................................... 29
5.1.2
Dual-Antenna Modules ........................................................................................ 30
5.2

Electrical Recommendations ............................................................................... 30

5.3

Decoupling.............................................................................................................. 31

5.4Power States .......................................................................................................... 31

5.5
Layout Recommendations ................................................................................... 32
5.5.1
Coplanarity ............................................................................................................ 32
5.5.2
Power ..................................................................................................................... 32
5.5.3
Antenna Inputs ..................................................................................................... 32
5.5.4
Avoiding Self-Interference.................................................................................... 33
6

PRODUCT HANDLING ................................................................................................ 34

6.1

ESD Precautions ..................................................................................................... 34

6.2

ROHS/WEEE NOTICE ............................................................................................... 34

6.3
Packaging ............................................................................................................... 35
6.3.1
Packing List Label.................................................................................................. 36
6.3.2
MSL Level Label..................................................................................................... 36
6.4
Storage .................................................................................................................... 37
6.4.1
Note for Small Quantities .................................................................................... 37
6.5

Sticker and Identification ..................................................................................... 37

6.6
Soldering ................................................................................................................. 38
6.6.1
Solder Mask........................................................................................................... 38
6.6.2
Reflow Profile ........................................................................................................ 38
7

DEVELOPMENT KIT .................................................................................................... 40
4

4
4

7.1

Header Types ......................................................................................................... 40

7.2

Powering the DevKit ............................................................................................. 40

7.3

Antenna Connectors ............................................................................................. 41

7.4

LEDs and General Purpose Output Pins ............................................................. 42

7.5

COM Ports ............................................................................................................... 43

7.6

PPS Out and Event Inputs..................................................................................... 44

7.7

Ethernet .................................................................................................................. 447.8

USB Dev ................................................................................................................... 44

7.9

USB Host ................................................................................................................. 44

7.10 REF IN ...................................................................................................................... 45
7.11 Buttons ................................................................................................................... 45
7.12 SD Card Socket ....................................................................................................... 45
8

EVALUATION KIT: MOSAIC-GO .................................................................................. 46

8.1
Interfaces ............................................................................................................... 46
8.1.1
USB......................................................................................................................... 46
8.1.2
RSV USB ................................................................................................................. 46
8.1.3
RF_IN1 and RF_IN2 ................................................................................................ 46
8.1.4
TF Card ................................................................................................................... 47
8.1.5
6-pin Connector .................................................................................................... 47
8.1.6
4-pin Connector .................................................................................................... 47
8.2
Accessories ............................................................................................................. 47
8.2.1
6-pin COM1 Open-Ended Cable .......................................................................... 48
8.2.2
4-pin COM2 Open-Ended Cable .......................................................................... 48
8.3

LEDs ......................................................................................................................... 48

8.4

Powering the mosaic-go ....................................................................................... 48

APPENDIX A LED STATUS INDICATORS ......................................................................... 49
APPENDIX B

SYSTEM NOISE FIGURE AND C/N0 .......................................................... 51

APPENDIX CMOSAIC-H RF GAIN ADJUSTMENT .......................................................... 52

APPENDIX DEMC CONSIDERATIONS ........................................................................... 54
555APPENDIX E

PAD LIST .................................................................................................... 57666

Document Change Log

2 Document Change Log
Document
Release
1.1.0
1.2.0

ReleaseDate
Oct 2019
Jun 2020

1.3.0
1.4.0

Jul 2020
Dec 2020

1.5.0

Sep 2021

1.6.0

Mar 2022

1.7.0

Sep 2022

Main Changes
First published version
Extended the description of the standby mode
Added description of the MODULE_RDY pin
Added power state diagram
Extended and clarified the “Product Handling” section
Added a note that the RTC_XTALI pin must be tied to ground
Added description of the dual-antenna mosaic-H
Added complete pad list in appendix
Added frequency plan in the “Overview” section
Added description of the mosaic-go evaluation kit
Added “mosaic-H RF Gain Adjustment” appendix
Added documentation of the GPLED2 pin (pin #M3)
Added mosaic-CLAS frequency plan
Extended and clarified the “Product Handling” section (packaging,storage and soldering recommendations)7

7
7

mosaic GNSS Module

3 mosaic GNSS Module
3.1 Overview
Septentrio’s mosaic modules are low-power multi-band multi-constellation GNSS receiver
packaged in a 31x31mm LGA module. The internal block diagram is shown below.

The module operates from a single 3V3 power supply (VDD_3V3).
The ANT_1 input pad receives the RF signal from the main antenna. On dual-antenna
modules (mosaic-H), a second antenna input is available (ANT_2) for the auxiliary antenna.
A 3V to 5.5V DC voltage can be applied to the main antenna from the VANT pin, obviating
the need for an external antenna supply. The internal bias control circuit detects
overcurrent conditions (>150mA) and protects the module in case of short circuit. See
section 4.2.
The module can use its internal TCXO as frequency reference, but also accepts an externalfrequency reference on the REF_I pin (mosaic-T only). See section 4.7.
Two event timer pins and a PPS output are available (1.8V LVTTL). See section 4.8.
The module features a rich set of communication interfaces:• Four serial ports (3.3V LVTTL), three of them with hardware flow control. See
section 4.3.
• USB. See section 4.4.
8

88

mosaic GNSS Module•••

Ethernet (the PHY is external to the module). See section 4.5.
SDCard interface for logging to an external SD card. See section 4.6.
GPIO and LEDs output. See section 4.10.

The table below summarizes the main differences between the mosaic models in termsof hardware features. The frequency bands in blue are supported.
mosaic
model

#Ants

Time &
Freq sync

mosaic-X5

1

No

mosaic-Sx

1

No

mosaic-T

1

YesmosaicCLAS

1

No

Supported Frequency Bands per Antenna

mosaic-H can be configured in two different band plans,
applicable to both antennas:

mosaic-H

2

No

By default, mosaic-H operates in band plan #1, with theE5b/B2b/B2I band enabled. Band plan #2, with B3 enabledinstead of E5b/B2b/B2I, is selected when the BDSB3I signal isenabled with the setSignalTracking user command.

999mosaic GNSS Module

3.2 Mechanical

AC1

A1

All dimensions in millimeters.
Weight = 6.8g

LGA Details
Land pitch
Land diameter
Pin 1 markSpecification
1.27 mm
0.6 mm
Bottom: the A1 pad is missing
Top: A1 marked by the hole in the shield
Nickle/Gold
23 x 23, three outer rows
239

Land plating
Array
Number of terminals

3.3 Absolute Maximum Ratings
The following conditions should never be exceeded, even momentarily, as it may cause
permanent damage to the module.
Parameter

Comment

Min

Max

Units

VDD_3V3 voltage
VDD_BAT voltage
VANT voltage
3V3_LVTTL input pin voltage

See 4.1
See 4.12
See 4.2

-0.3
-0.3
-0.3
-0.3

3.6
3.6
5.5
VDD_3V3+0.3

V
V
V
V
10

10
10

mosaic GNSS Module

EVENT input voltage
RF input power at ANT_1
RF input power at ANT_2
REF_I level
Output pins drive current
Storage temperature
Operational temperature

See 4.8
See 4.2
See 4.2
See 4.7

-0.3

-55
-40

1V8_OUT+0.3
20
10
1.7
10
+85
+85

V
dBm
dBm
Vp-p
mA
°C
°C

3.4 Electrical Characteristics in Operational Conditions
3.4.1 Power Supply
Parameter

Comment

Min

Typ

Max

Units

VDD_3V3 voltage
VDD_BAT voltage
VANT voltage
USB_VBUS1 voltage
1V8_OUT output voltage
2V8_OUT output voltage
VDD_3V3 current
VDD_BAT input current
USB_VBUS1 input current
1V8_OUT output current
2V8_OUT output current
VANT input current

See 4.1
See 4.12
See 4.2
See 4.4

3.135
3.135
3.0
4.4
1.764
2.744
160

3.3
3.3
3.3
5.0
1.8
2.8
210
0.03
10

3.465
3.465
5.5
5.5
1.836
2.856
500
1
50
120
100
150

V
V
V
V
V
V
mA
mA
mA
mA
mA
mA

See 4.4

3.4.2 I/O
Parameter
VIH, 1.8V inputs
VIL, 1.8V inputs
Input capacitance
1.8V inputs
Pull-down, 1.8V inputs
VOH, 1.8V outputs
VOL, 1.8V outputs
VIH, 3.3V inputs
VIL, 3.3V inputs
Pull-up, 3.3V inputs
Pull-up, nRST_IN
VOH, 3.3V outputs
VIL, 3.3V outputs
REF_I input level
REF_I input capacitance
REF_I input frequency
REF_O output level

Comment

Min

Typ

Max

Units

0.3*1V8_OUT

VV
pF

0.7*1V8_OUT
2.0

7.2 mA
7.2 mA

Except nRST_IN
1 mA
1 mA

80
0.75*1V8_OUT
0.7*VDD_3V3
068
9.6
VDD_3V3-0.15

210

515

100
9.8

0.4
VDD_3V3
0.3*VDD_3V3
150
10
0.15
1.7

0.5

See 4.7.1

8
10
1.2

kOhm
V
V
V
V
kOhm
kOhm
V
V
Vp-p
pF
MHz
Vp-p
11

11
11

mosaic GNSS Module

3.5 Power Consumption
The module is powered through the VDD_3V3 pins, see section 4.1.
The power consumption depends on the set of GNSS signals enabled and on thepositioning mode. The following tables list the average power consumption for someconfigurations, while tracking all satellites in view from an open sky, and with the module
at room temperature. The current is applicable to a supply voltage of 3.3V.
Single-Antenna Modules
GNSS Signals
GPS L1 C/A
GPS L1/L2
GPS/GLONASS L1/L2
GPS/GLONASS L1/L2+GALILEO L1/E5a+BeiDou B1C/B2a (phase 3)
GPS/GLONASS L1/L2+GALILEO L1/E5a+BeiDou B1C/B2a (phase 3)
GPS/GLONASS L1/L2 + L-band
All signals from all GNSS constellations
All signals from all GNSS constellations+L-band
All signals from all GNSS constellations+L-bandDual-Antenna Modules
GNSS Signals
GPS L1 C/A
GPS L1/L2
All signals from all GNSS constellations

Positioning
ModeStand-Alone (1Hz)
RTK (1Hz)
RTK (1Hz)
RTK (1Hz)

Power
(mW)
550
670
695
850

Current
(mA)
167
203
211
258

RTK (100 Hz)

930

282

PPP (1Hz)
Static (1Hz)
Static(1Hz)

760
910
980

230
276
297

Static (100Hz)

1080

327

Positioning
Mode
RTK+heading (10Hz)
RTK G +heading(10Hz)
RTK+heading (10Hz)

Power
(mW)
680
900

Current
(mA)
206
273

1060

321

Enabling wideband interference mitigation with the setWBIMitigation command adds 70
mW.
Note that the currents given in the above tables are average values. To account for peakcurrents, the minimum power supply drive capability should be 500 mA.

3.6 Environmental
Operational: -40 to +85 °C
Storage:-55 to +85 °C

12

12
12

Pinout and I/O Description

4 Pinout and I/O Description
The module provides 239 LGA pads, configured as follows.

The following sections describe all the non-reserved pads. Pads are grouped by functions.
A complete pad list can be found in Appendix E.
Conventions:••••

Pin Type: I=Input, O=Output, P=Power, Ctrl=Control, Clk=Reference clock
PU: pulled up
PD: pulled down
K: keeper input type

13

13
13

Pinout and I/O Description

4.1 Power Supply
The module is powered through the VDD_3V3 pins.
Pin Name
VDD_3V3

Type
P,I

Level
3.3V +/-5%

Description
Main power supply input

GND

Gnd

0

GroundVDD_BAT

P,I

3.3V +/-5%“Always-on” supply.

nRST_IN

Ctrl,PU

3V3_LVTTLMODULE_RDY

O

3V3_LVTTL

Reset input, active negative. Module is in reset when low. Shortlow pulses of less than 1 µs are ignored.
Level is high when module is operating, and low when in standby
or reset.

1V8_OUT
SYNC

P,O
I

1.8V
1V8_LVTTL

Comment
All VDD_3V3 pins must be tied
together.
All GND pins must be connected to
ground.
Must be tied to VDD_3V3 unless anexternal power switch is available.
See section 4.12.
Internally debounced, can be directly
connected to a push-button.
Level becomes high about 300
milliseconds
after
powering/
unresetting the module.

1.8V output, see below
Reserved. Must always be connected to 1V8_OUT.

Note that the 2V8_OUT and 2V8_IN pins are exclusively reserved to power the internal
TCXO. See section 4.7.
The 1V8_OUT pin is a DC output (120mA max current) which can, for example, be used to
power level-shifters for the 1V8_LVTTL signals (EVENT and PPS), see for example section
4.8.
The module can also control an external power switch, to enable standby mode. See
section 4.12 for details.
See also the power state diagram in section 5.4.

4.2 Antenna(s)4.2.1 Main Antenna
The main antenna (which is the only antenna on single-antenna modules) is directly
connected to the ANT_1 pad. The ANT_1 input is ESD-protected in the module and carriesa DC-voltage to power the antenna, avoiding the need for an external bias-tee. This DCvoltage is imposed to the module via the VANT pad.
In case of an overcurrent condition (e.g. short circuit in antenna cable), the module will
first limit the current to about 150 mA and then switch off the antenna supply in about 10
ms. It will periodically retry to switch on the antenna supply until the overcurrent
condition has disappeared.
Pin Name
ANT_1

Type
RF

Level

Description
RF input for main antennaComment

VANT

P,I

3–5.5VDC supply to the ANT_1 antenna. Max current 150mA. DC supply
is turned off if overcurrent is detected.
If those pads are not connected or if they are tied to GND, there
is no DC voltage at the ANT_1 pad.

The two VANT pads should be tied
together.

14

14
14

Pinout and I/O Description

4.2.1.1 ANT_1 Electrical Specifications
DC biasEquivalent DC series impedance at
the ANT_1 pin
Antenna current limit
ANT_1 pre-amplification gain range1
ANT_1 receiver noise figure2(NFrx, see Appendix B)

RF nominal input impedance
VSWR

DC level provided with the VANT pad
2.5 Ohms typical, 3.0 Ohms max
150 mA
Single-antenna modules: 15-50 dB (AGC gain: 15-50dB)
Dual-antenna modules: 15-35dB (AGC gain: 30-50dB)
8.5 dB with 15 dB net pre-amplification
18 dB with 25 dB net pre-amplification
26 dB with 35 dB net pre-amplification
35 dB with 45 dB net pre-amplification
50 Ohms< 2:1 in all the supported frequency bands

Never inject an external DC voltage into the ANT_1 pad as it may damage the module. For
instance, when using a splitter to distribute the antenna signal to several GNSS receivers,
make sure that no more than one output of the splitter passes DC. Use DC-blocks
otherwise.

4.2.2 Auxiliary Antenna
In dual-antenna modules, the auxiliary antenna is connected to the ANT_2 pad. In singleantenna modules, ANT_2 is not used and must be tied to ground.
Pin Name
ANT_2

Type
RF

Level

Description
RF input for auxiliary antennaComment
To be tied to ground in single-antenna
modules

Contrary to the ANT_1 pad, ANT_2 is not ESD-protected and it carries no DC voltage. ESD
protection and biasing must be performed externally. See section 4.2.3.2.

4.2.2.1 ANT_2 Electrical Specifications
DC biasANT_2 pre-amplification gain range1
ANT_2 receiver noise figure(NFrx, see Appendix B)
RF nominal input impedance
VSWR

None, ANT_2 is AC-coupled
15-35 dB (i.e. AGC gain: 30-50dB)
6 dB with 15 dB net pre-amplification
14.5 dB with 25 dB net pre-amplification
21 dB with 35 dB net pre-amplification
50 Ohms< 2:1 in all the supported frequency bands

The pre-amplification gain is the total gain of the distribution network in front of the module. Typically, thisequals antenna active LNA gain minus coax losses in the applicable GNSS bands. The pre-amplification gain
can be computed from the AGC gain reported by the module in the ReceiverStatus SBF block and shownin the web interface or the RxControl GUI. The conversion formula from the reported AGC gain to the preamplification gain is:
Pre-amp gain[dB] = 65 - AGCgain[dB]
So, if the receiver reports an AGC gain of 30dB, the pre-amplification gain is 35dB.
1

2 The listed noise figure is at room temperature. Add 2 dB for the noise figure at the worst temperature corner(85°C)
15

15
15

Pinout and I/O Description

4.2.3 Typical Application
4.2.3.1 Single Antenna Modules
The ANT_1 input is DC-biased and ESD-protected, so that no external component isneeded. Make sure to connect the ANT_2 pad to ground.

Refer to 5.5.3 for RF-routing recommendations.

4.2.3.2 Dual-Antenna Modules
The main antenna connects to ANT_1 and the auxiliary antenna to ANT_2. ANT_1 is DCbiased and ESD-protected, while ANT_2 is AC-coupled and unprotected. A recommended
application circuit is shown below. With this circuit, the DC bias from the ANT_1 pad isshared between the two antennas. Note that the combined current drawn by bothantennas must not exceed 150mA in that case.

Refer to 5.5.3 for RF-routing recommendations.
If the pre-amplification gain is higher than 35dB, it is recommended to put attenuators in
the RF path. See Appendix C for instructions.
In addition, the ANT_1 and ANT_2 pre-amplification must not differ by more than 5dB. It
is recommended to use the same antenna type for the main and auxiliary antennas, and,as much as possible, to use antenna cables of the same type and length. In case this is
not possible, the strongest signal needs to be attenuated, as also described in Appendix
C.
16

16
16

Pinout and I/O Description

4.3 COM Ports
The module provides four serial COM ports. Three of them (COM1 to COM3) support
RTS/CTS hardware flow control:
Pin Name
TXD1
RXD1
RTS1

Type
O
I, PU
O

Level
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL

Description
Serial COM1 transmit line (inactive state is high)Serial COM1 receive line (inactive state is high)Serial COM1 RTS line.

CTS1

I, PU

3V3_LVTTL

Serial COM 1 CTS line.

TXD2
RXD2
RTS2

O
I, PU
O

3V3_LVTTL
3V3_LVTTL
3V3_LVTTL

Serial COM2 transmit line (inactive state is high)Serial COM2 receive line (inactive state is high)Serial COM2 RTS line.

CTS2

I, PU

3V3_LVTTL

Serial COM3 CTS line.

TXD3
RXD3
RTS3

O
I, PU
O

3V3_LVTTL
3V3_LVTTL
3V3_LVTTL

Serial COM3 transmit line (inactive state is high)Serial COM3 receive line (inactive state is high)Serial COM3 RTS line.

CTS3

I, PU

3V3_LVTTL

Serial COM3 CTS line.

TXD4
RXD4

O
I, PU

3V3_LVTTL
3V3_LVTTL

Serial COM4 transmit line (inactive state is high)Serial COM4 receive line (inactive state is high)Comment

The module drives this pin low when
ready to receive data
Must be driven low when ready toreceive data from the module.

The module drives this pin low when
ready to receive data
Must be driven low when ready toreceive data from the module.

The module drives this pin low when
ready to receive data
Must be driven low when ready toreceive data from the module.

Unused COM-port signals can be left floating. Flow control is disabled by default.
The COM port settings (baud rate, flow control, etc) are set with the setCOMSettings usercommand. The maximum baud rate is 4Mbits/s.
The LVTTL RXD and CTS inputs of the module shall not be driven while its VDD_3V3 input
supply is not present.

4.3.1 Typical Application
An example of a circuit to convert the COM1 signals to RS232 level is shown below. In
green, the signals to be connected to the mosaic pins. The RTS1 and CTS1 signals can beleft unconnected if hardware flow control is not required.
It is recommended to use the same 3V3 source to supply the RS232 transceiver and the
VDD_3V3 pins of the module, to ensure that the transceiver outputs are not driven whenthe module is not powered.

17

17
17

Pinout and I/O Description

4.4 USB Device Interface
The following pins are used for accessing the module over USB in USB-device mode.
Pin Name
USB_VBUS1

USB_DEV_N
USB_DEV_P

Type
P,I

I/O
I/O

Level
4.40V to
5.5V

USB
USB

Description
USB VBUS input.
This pin cannot be used to power the module.
Maximal current drawn by the module is 50 mA.

Comment
This pin powers the integrated PHY ofthe USB interface.

Note: if USB is unused, this pin shall be left floating
USB data signal, negative
USB data signal, positive

USB is configured in USB 2.0 mode (high speed, 480Mbps max).

4.4.1 Typical Application
An example of an USB application circuit with ESD protection is shown below. The user
shall make sure to use an ESD-protection and common mode choke compatible with highspeed USB if this is desired, for instance the USBLC6-2 from ST and DLP31SN121ML2L
from Murata.

18

18
18

Pinout and I/O Description

4.5 Ethernet
The module supports full duplex 10/100 Base-T Ethernet communication. The Ethernet
PHY and magnetics are to be implemented on the host board. Connection with the PHY
is through the RMII interface available on the following pins:
Pin Name
RMII_CLKMDIOMDCRMII_RXD1
RMII_RXD0RMII_CRSDVRMII_RXERRMII_TXENRMII_TXD0RMII_TXD1nRST_LAN

Type
O
I/O
O
I, PU
I, PU
I, PU
I, PU
O
O
O
O

Level
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL

Description
LAN PHY ClockLAN PHY control data
LAN PHY control clock
LAN PHY receive data 1
LAN PHY receive data 0
LAN PHY CRSLAN PHY RX error
LAN PHY transmit enable
LAN PHY transmit data 0
LAN PHY transmit data 1
LAN reset (low to reset the PHY)

Comment

When connecting this pin to enable an
Ethernet PHY, add a 10k pull-down.

If Ethernet is not used, all these pins should be left unconnected.
Hostname: the module hostname is based on the last seven digits of the serial number.
For example, the hostname of the module shown below is mosaic-X5-3054938.

4.5.1 Typical Application
An application circuit using the KSZ8041NLI PHY and a Würth 74990111217 RJ45
connector with integrated magnetics is given below. In green, the signals to be connectedto the mosaic pins.

19

19
19

Pinout and I/O Description

It is recommended to use the same 3V3 source to supply the PHY and the VDD_3V3 pinsof the module, to ensure that the PHY output pins are not driven when the module is not
powered.
The module also supports other PHYs. An up-to-date list of supported PHY’s can be foundin Septentrio’s Knowledge Base pages :https://customersupport.septentrio.com/s/article/which-ethernet-phy-does-mosaic-support

4.6 SD Memory Card
The module can interface to an external SD memory card through the pins listed in thetable below.
Pin Name
SD_CLK
SD_CMD
SD_DAT0
LOGBUTTON

Type
O
O
I/O
I, PU

Level
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL

Description
SD card CLK line
SD card CMD line
SD card DAT0 line
Toggle logging on/off or mount/unmount the disk. See below

Comment

20

20
20

Pinout and I/O Description

4.6.1 Typical Application
The module supports the 1-bit SD transfer mode with 3V3 signaling. An example circuit
to a 9-pin SD memory card socket is shown below. The maximum clock frequency(SD_CLK) is 33.000 MHz.

4.6.2 Data Logging
Driving the LOGBUTTON pin low for 100 ms to 5 seconds toggles logging on and off.
Driving the LOGBUTTON pin low for more than 5 seconds and then releasing it unmounts
the SD card if it was mounted, or mounts it if it was unmounted. The SD card mount status
can be checked with the LOGLED pin (see Appendix A).
As the name suggests, the LOGBUTTON is typically interfaced to a mechanical button(though this could also be e.g. an open-collector output or a push-pull output). The
module debounces the signal in software, so no external debouncing circuit is required.
See instructions in the Reference Guide for details on how to configure SD card logging.
The module is compatible with SD cards of up to 32GB. The file system is FAT32.
When powering off the module while logging, the last seconds of data may be lost. To
avoid data losses, it is advised to first unmount the SD card. This can be done in severalways:
1. By entering the command “exeManageDisk, DSK1, Unmount” before turning off
the module (see the Reference Guide for a description of all the user commands).
2. By driving the LOGBUTTON pin low for at least 5 seconds before turning off themodule.
3. By driving the ONOFF pin low for at least 50ms. This puts the module in standby,from where it can be safely switched off. See sections 4.12 and 5.4 for details.

21

21
21

Pinout and I/O Description

4.7 Clock Frequency Reference
The module can use its internal TCXO frequency reference, or can accept an externalfrequency reference, bypassing the internal TCXO.
Pin Name
REF_I

Type
Clk

Level
0.5-1.7Vp-p

REF_O
2V8_OUT

Clk
P,O

1.2Vp-p
2.8V

2V8_IN

P,I

2.8V

VTUNE

I

Description
Main frequency reference input, DC-decoupled, input capacitanceis 8 pF
Frequency reference output from the internal TCXO
2.8V supply output for the internal TCXO.

2.8V supply input for the internal TCXO. Typically connected to
2V8_OUT.
Reserved

Comment
See section 4.7.2.
See section 4.7.1.
Do not power any external device fromthis pin. It is only intented to connect
to 2V8_IN.

Leave unconnected.

4.7.1 Using the internal TCXO
To have the module run on its own TCXO:• REF_I must be connected to REF_O (those pins are next to each other);• 2V8_IN must be connected to 2V8_OUT (those pins are next to each other). Do not
use the 2V8_OUT for another purpose and do not apply another 2.8V supply to
2V8_IN than the one from 2V8_OUT.
The 10-MHz signal from the internal TCXO is available at the REF_O pin, with peak-to-peakamplitude of 1.2V. The waveform is illustrated in the oscilloscope screen capture below.

4.7.2 Using and external frequency reference
To use an external frequency reference:• 2V8_IN must be tied to ground• REF_O and 2V8_OUT are not used and should be left unconnected• The 10-MHz reference must be fed into the REF_I pin. It is preferably a sine wave
or a band-limited square wave. If CMOS or LVTTL signals are used, it isrecommended to filter them at the source with an RC filter with a pole near 100
MHz. The level at the REF_I input has to be between 0.5 and 1.7 Vp-p. If a higher
signalling voltage is divided with a resistive divider, the impedance level shall be
22

22
22

Pinout and I/O Description

sufficiently low to avoid excessive level drop because of the filtering of the divider
with the input capacitance of the REF_I input (8 pF). Below an example circuit. The
module has a build-in DC-decoupling capacitor.

Support for an external frequency reference is not available in all mosaic models. It is only
available on those models where the FreqSync permission is enabled. Using an externalreference without corresponding permission will cause the module to block most SBF
output.

4.8 Event/TimeSync inputs
The module features two event inputs, which can be used to time tag external events witha time resolution of 20ns.
Pin Name
EVENTA
EVENTB

Type
I, PD
I, PD

Level
1V8_LVTTL
1V8_LVTTL

Description
Event A or TimeSync input. The pull-down is about 200 kOhm.
Event B or TimeSync input. The pull-down is about 200 kOhm.

Comment
Leave unconnected if not used
Leave unconnected if not used

Use the setEventParameters user command to configure the EVENTx pins (e.g. to set thepolarity). Note that this feature is not available on all mosaic models. It requires theTimedEvent permission to be enabled. For correct detection, the minimum time between
two events on the same EVENTx pin must be at least 5ms, and there must be no morethan 20 events in any interval of 100ms, all EVENTx pins considered.
If the TimeSync permission is enabled in your mosaic model, the event inputs can also be
configured as TimeSync source using the setTimeSyncSource command. When an event
pin is configured as TimeSync source, the mosaic module expects to see a one-pulse-persecond (1PPS) signal on that pin. It will then synchronize its internal time base (i.e. thetime at which GNSS measurements are sampled) to that 1PPS signal. TimeSync is typicallyused in conjunction with ExtFreq (see section 4.7.2) to fully synchronize the moduleinternal time base with the time of an external clock.
Note that there is a delay of 15 to 50 ns between the PPS pulse at the EVENT pin and themodule internal time base. That delay is dependent on the phase difference between the
10 MHz frequency at the REF_I pin and the PPS pulse at the EVENT pin. It is possible tomeasure this delay by synchronizing the PPS OUT pulse with the internal time base, withthe setPPSParameters,,,,RxClock command.

23

23
23

Pinout and I/O Description

Note the timing signals use 1.8V logic. If 3.3V logic would be required, the EVENT-signals
can be generated via a resistive divider, considering the integrated pull-down (see 3.4.2).
They could as well be created via a level shifter, using the 1V8_OUT output from themodule to supply the module side.

4.9 PPS output
Pin Name
PPSO

Type
O

Level
1V8_LVTTL

Description
PPS output. Max output current: 10 mA. Polarity and rate user
selectable. During start up, this pin is in high-Z mode.
See Reference Guide for operating instructions.
Default pulse duration: 5ms.

Comment

The polarity, frequency and pulse width can be set with the setPPSParameters
command.
The PPSO signal uses 1.8V logic. It can be level-shifted if 3.3V logic is required (e.g. with
SN74AVC4T245RSV).
The PPSO signal is briefly driven high during startup of the module (for about 1 ms), thengets high-impedant while the module is starting up. It finally gets driven to the intended
level (low or high depending on the user-selected PPS polarity) after a few seconds. If thisstart-up behavior is undesirable, it can be shielded by a buffer (or level shifter) with an
output enable. The output enable can be controlled with the MODULE_RDY pin of themodule. The MODULE_RDY signal gets high about 300ms after applying power to
VDD_3V3. The input and output of the buffer should be pulled-up or pulled-down
depending on the desired inactive state of the PPSO signal.

4.10 General Purpose Output (GPx)
The GP1 and GP2 pins are general purpose digital outputs, of which the level can be
programmed with the setGPIOFunctionality command.
Pin Name
GP1
GP2

Type
O
O

Level
3V3_LVTTL
3V3_LVTTL

Description
General purpose output. GP1 in setGPIOFunctionality command.
General purpose output. GP2 in setGPIOFunctionality command.

Comment

24

24
24

Pinout and I/O Description

During the first seconds after powering up the module, these pins are in tristate. Use an
external pull-down or pull-up resistor to have the desired level during boot.
The GPx pins can drive a maximum current of 10mA.

4.11 LEDs
The LED pins can be used to monitor the module status. They can be used to drive
external LEDs. It is assumed that the LED lights up when the electrical level of thecorresponding pin is high. See also Appendix A.
Pin Name
GPLED

Type
O

Level
3V3_LVTTLGPLED2O

3V3_LVTTLLOGLEDO

3V3_LVTTL

Description
First general purpose LED.
Max output current: 10 mA; output impedance: 20 Ohms
Second general purpose LED.
Max output current: 10 mA; output impedance: 20 Ohms
Internal logging status indicator.
Max output current: 10 mA; output impedance: 20 Ohms

Comment

During boot, i.e. during the first seconds after powering the module, the state of the LEDs
is not defined. Use a pull-down or pull-up resistor to force a desired state.
An example of a circuit with a 10k pull-down and a driver is shown below.

4.12 Standby
It is of course possible to power off the module by switching off the VDD_3V3 and VDD_BAT
supplies. However, this abrupt power interruption could cause data losses when logging
on an external SD card.
The module also supports standby mode, where it controls an external power switch andturns itself off in a controlled way. This functionality involves the following pins:
Pin Name
VDD_3V3

Type
P,I

Level
3.3V +/-5%

Description
Main power supply input, controlled by the external power switch

VDD_BAT

P,I

3.3V +/-5%

ONOFF

I, PU

3V3_LVTTL

Always-on power supply, which must remain available when
VDD_3V3 is turned off by the external power switch
Typically connected to a push-button to toggle between active
and standby mode. Toggling occurs when the ONOFF pin is driven
low for at least 50ms.

Comment
All VDD_3V3 pins must be tied
together.

Internally debounced

25

25
25

Pinout and I/O Description
PMIC_ON_REQ

O

3V3_LVTTLMODULE_RDY

O

3V3_LVTTL

Typically connected to the control pin of an external power switch.
The power switch is expected to enable VDD_3V3 when
PMIC_ON_REQ is high, and to disable VDD_3V3 when it is low.
Level is high when module is operating, and low when in standby
or reset.

Level becomes high about 300
milliseconds after powering up,
unresetting, or waking up after
standbyThe external power switch is optional. When not using an external power switch, always
connect VDD_BAT together with VDD_3V3.
An example optional circuit with an external power switch and an on/off push-button isshown below.

The module can be put in standby by either:• Entering the exePowerMode, standby user command;• Driving the ONOFF pin low for at least 50ms (i.e. pressing the button for at least50ms).
After standby is requested, the module terminates all running processes, unmounts theexternal SD card (if applicable) to avoid any log file corruption, and drives the
PMIC_ON_REQ pin low to turn off the main power supply (VDD_3V3). The module power
consumption in standby is <5mW. The current state of the module (standby or active) canbe monitored with the MODULE_RDY pin. MODULE_RDY is low during standby.
When in standby, driving the ONOFF pin low for at least 50ms wakes up the module. The
module drives the PMIC_ON_REQ high, and restarts in the configuration stored in the bootconfiguration file.
The ONOFF pin is internally pulled up and has a built-in debouncing circuit.
Do not drive a non-zero voltage into input pins (pins type “I” in the tables in chapter 3)
when the module is in standby, i.e. when the VDD_3V3 supply is turned off.

26

26
26

Pinout and I/O Description

Note that the ONOFF pin can also be used without external power switch (i.e. when
VDD_3V3 is tied to VDD_BAT). The module will then stop all software and unmount theexternal SD card, but will not enter low power consumption. It will automatically wake up
again after about 2 minutes.
See also section 5.4.

4.13 RTC
The RTC_XTALI and RTC_XTALO pins are reserved to connect an external 32.768 kHz
crystal.
Pin Name
RTC_XTALITypeI

RTC_XTALO

O

Level

Description
Crystal oscillator input terminal
Crystal oscillator output terminal

Comment
Future functionality, connect to ground in present
version of the module
Future functionality, leave unconnected in present
version of the module

Note that this functionality is currently not available. RTC_XTALI should be tied to ground,and RTC_XTALO left floating:

27

27
27

mosaic Integration

5 mosaic Integration
5.1

Minimal Design

A minimal design for single-antenna and dual-antenna modules is shown below. In bothcases:• All ground pins and the pins marked “Reserved_GND” are connected to ground(GND).
• A 3.3VDC supply is provided to the VDD_3V3 pins and to the VDD_BAT pin. A 22µF
decoupling capacitor is recommended.
• To provide power to the antenna(s), the VANT pins are also connected to the 3.3V
supply.
• The 2V8_IN and 2V8_OUT pins are connected, as no external frequency referenceis used (see section 4.7).
• The REF_I and REF_O pins are connected for the same reason.
• 1V8_OUT is connected to SYNC (this must always be the case).
• Pin A3 (RTC_XTALI) needs to be connected to ground.
• All other pins are left unconnected.
For easier debugging during host design development, it is recommended to always routeat least one of the COM ports to test pads or a test header.

28

28
28

mosaic Integration

5.1.1 Single-Antenna Modules
In single antenna mosaic modules, the ANT_2 pin (V23) must be tied to ground.

29

29
29

mosaic Integration

5.1.2 Dual-Antenna Modules
The main antenna connects to ANT_1 (AC20) and the auxiliary antenna connects to ANT_2(V23). DC supply is provided through the ANT_1 pin, and the biasing circuit to supply theauxiliary antenna is shown (see also section 4.2.3.2).
L:
TVS:

Inductor self resonant near 1400MHz, e.g. Würth 744786139A.
Transient voltage suppression diode, SESD0402X1BN-0010-098 or equivalent.

Note that the combined current drawn by both antennas must not exceed 150mA.

5.2 Electrical Recommendations•

All ground pins must be connected.

•

Do not drive a non-zero voltage into input pins (pins type “I” in the tables in chapter4) when the module is not powered or when it is in standby (see section 4.12).

•

When pull-up/down resistors are needed, use 10 k.

•

Unused pins (e.g. pins of an unused interface) must be left unconnected unlessexplicitly mentioned otherwise.
30

30
30

mosaic Integration•

Many pins are reserved, which means that their functionality is proprietary or isnot supported yet by the firmware. Reserved pins are marked “Reserved_NC” and“Reserved_GND”. The Reserved_NC pins must be left unconnected. The
Reserved_GND pin (i.e. only AB7) must be tied to ground.

5.3 Decoupling
The VDD_3V3 supply shall be decoupled with at least a 22 µF capacitor with proper voltage
rating. The other supply terminals don’t need external decoupling.

5.4 Power States
The module can be in three different states: off, active or standby.

When off, the module is completely turned off. In active state, it is operating with allfunctions active. Standby state is similar to off, the main difference being in the transition
from the active state:• When going from active to off, recent data logged to an external SD card may belost (see section 4.6).
• When going from active to standby, all logging tasks are terminated and the SD
card is cleanly unmounted.
The standby state is optional and only available if the host design supports it. See section
4.12 for details.

31

31
31

mosaic Integration

5.5 Layout Recommendations
5.5.1 Coplanarity
It is important to avoid warpage of the motherboard on which the module will besoldered. More in particular:• Use a symmetrical layer stack• Make sure layers opposite from the center of the board have a similar amount ofcopper (copper-balancing).
• Avoid iron-based soldered shielding cans in the proximity of mosaic• If the motherboard thickness is 1.2 mm or less, it needs to be supported during
reflow.

5.5.2 PowerThe power trace to the VDD_3V3 terminals should be sufficiently wide to avoid excessive
voltage drop. The resistance of the trace to the power supply shall be less than(<minimum supply voltage> - 3.135V)/0.5A.
Use a ground plane.

5.5.3 Antenna Inputs
The antenna input traces shall be routed as a 50-ohm coplanar waveguide with ground,
as in the picture below. It is best to use stitching vias every few mm for good groundcoherence. The width of the trace to set the impedance to 50 ohm can be calculated with
online tools (e.g. https://chemandy.com/calculators/coplanar-waveguide-with-groundcalculator.htm). Usually it is best to use the top-layer for the coplanar waveguide and thesecond layer for ground.

The antenna trace to ANT_1 can be directly routed to the desired type of coax connector,
as all protection circuitry is integrated in mosaic.
For the dual-antenna module, beware that the ANT_2 pin is not protected, and a TVS diodeis recommended. See reference design in section 4.2.3.2.

32

32
32

mosaic Integration

5.5.4 Avoiding Self-Interference
Antenna input connections are sensitive to interference from higher harmonics of othersignals on the board. Even clock signals of just a few MHz can produce harmful harmonics
at GNSS frequencies (1155-1300 MHz and 1540-1610 MHz).
It is best to keep antenna input traces short, to reduce the area in which signals can bepicked up. Stitching vias at the input trace could be arranged as a via fence to shield itfrom interference.
Furthermore, it is important to avoid digital signals in the MHz-range (SDIO, RMII, MDIO,…)
from running close to antenna inputs.
If an external frequency reference is used, it will get close to the antenna input becauseof the proximity of the REF_I and ANT_1 pad. This is not a problem if it doesn’t have many
harmonics. It can however cause issues if the reference signal is originating from a highspeed buffer or comparator. This can be avoided at circuit level, by filtering the signal withan RC-filter near the source (see section 4.7.2).
Most self-interference issues relate to radiated interference into a collocated GNSSantenna. The following applies when the GNSS antenna is closer than 1 meter fromelectronics which are not in a shielded box:•

The SDIO, RMII and MDIO signals of mosaic can cause harmful radiatedinterference if not properly routed. In designs with a collocated antenna, thesesignals shall preferably be routed in an inner layer of the board, shielded by groundplanes or a ground copper pour at top and bottom layers, connected with stitchingvias. This approach puts them in a Faraday cage. Also avoid passing these signals
though an unshielded board-to-board connector if there is no shielding at systemlevel, like a metal housing or shielding can.

•The same holds for other high-speed digital signals in other electronics on themotherboard, like memory busses and clock signals. They should also be routed
in an inner layer, flanked with cupper pours connected to ground.

•

Large processor and memory chips sometimes already radiate via the bondwires
inside their package. Connectors like SD card sockets and radio-module sockets
also tend to radiate. It’s best to put these components at the side of the board
facing away from the collocated antenna. In this way the ground-layer will shieldthem. Alternatively, they could be placed underneath an EMI shielding can. Thereis less of a concern if the associated clock frequencies have no harmonics in the
GNSS bands.

See also Appendix D.

33

33
33

Product Handling

6 Product Handling
6.1 ESD Precautions
The mosaic module is sensitive to electrostatic discharge (ESD). Although it has a limited protection,
it should only be manipulated in an ESD-safe environment and using ESD-safe tools andequipment. These tools are typically marked with the following symbol:

The mosaic module should be stored and handled in the original package (preferably) or in a
conductive foam shorting all pads.

6.2 ROHS/WEEE NOTICE
Septentrio receivers and modules are compliant with the latest WEEE, RoHS and REACH
directives. For more info see www.septentrio.com/en/environmental-compliance.

34

34
34

Product Handling

6.3 Packaging
Mosaic modules are delivered on a tray in a dry pack, with 27 modules per tray.

Package contents:
•
•
•
•
•
•

27 mosaic modules
1 humidity indicator
1 desiccator bag
Packing list Label
Process lot label
MSL level label

35

35
35

Product Handling

6.3.1 Packing List Label
The labeling gives product information:
•
•
•
•
•
•

Product: mosaic variant with hardware revision
Quantity: number of modules in the bag
PN: Septentrio Part Number
MPN: Manufacurer Part Number
MPL: Manufacturer Product Lot
Date: Packaging Date

6.3.2 MSL Level Label
The labeling gives information about:••

Moisture Sensitivity Level and Floor Life
Storage conditions

36

36
36

Product Handling

6.4 Storage
Dry-pack shelf life is according to JEDEC standard J-STD-033 with 12 months at < 40°C and< 90% relative humidity (RH). After the 12-month period, baking is recommended prior to
reflow on customer boards.
The moisture sensitivity level (MSL) is 3.
If the dry pack has been opened for more than 168 hours or can no longer be considered
dry, the modules must be baked according to JEDEC standard J-STD-033 Table 4-1
Reference Conditions for Drying Mounted or Unmounted SMD Packages. The
recommended baking condition is 25 hours at 90°C <= 5% RH.
Oxidation Risk: Baking may cause oxidation and/or intermetallic growth of theterminations, which if excessive can result in solderability problems during board
assembly. The cumulative bake time at a temperature greater than 90°C and up to 125°C
should not exceed 96 hours.
Bake temperatures higher than 125°C are not allowed.
The 27-position tray cannot sustain baking temperature. The mosaic modules have to be
baked separately from the shipment tray.

6.4.1 Note for Small Quantities
For small quantities requested for prototype usage, Septentrio or Septentrio distributors
may not be able to supply the modules in dry-pack packaging. In that case, the customer
should consider that the components have exceeded their floor life. To prevent damaging
the modules during soldering, they need to be baked prior to any reflow.

6.5 Sticker and Identification
Pin A1The 2D barcode contains the module hardware version and serial number, e.g:
MOSAIC-X5GRB-0051-1000-BA3P2SN19293054938
The serial number is also printed under the barcode.

37

37
37

Product Handling

6.6 Soldering
6.6.1 Solder Mask
Non-soldermask defined (NSMD) pads are recommended, with a clearance of 75µm
between the copper pad and the solder mask, as shown in the below figure. The copper
pads are in green, the (negative) solder mask is in pink. Dimension in millimeters.

The GND and VDD_3V3 pins are an exception in this respect. They can be soldermaskdefined, allowing to route them using a plane.

6.6.2 Reflow Profile
Reflow soldering is the soldering method recommended to assemble mosaic modules.
The recommended temperature profile is specified with the graphic below. Refer also to“IPC-7530A: Guidelines for Temperature Profiling for Mass Soldering Processes (Reflow
and Wave)”.
The final reflow profile shall be based on leadfree process and depends on parameterssuch as the soldering paste, host board parameters (shape, thickness, etc…) and ovencapabilities.
Exceeding the maximum soldering temperature in the recommended soldering profile
may permanently damage the module.

38

38
38

Product Handling

RegionRamp up
Soak time
Time Above Liquidus (TAL)
Peak temperature
Cooling rate

Guideline
max 2 ℃/sec
60-120 sec
45-80 sec
245 ℃
max 4°C/sec

Don’t use glue underneath the component, as this might lift the component andjeopardize bonding. Cleaning the module (water, ultrasonic, solvent,…) is not allowed as it
could affect its performance.
The recommended stencil thickness is 0.125mm (5mil). The final stencil aperture design
and thickness must be adjusted to the customer’s specific manufacturing processes. In
any case, the stencil thickness shall not be less than 0.1mm (4mil).
Mount the part with the largest available placement nozzle, attached to the center of theshield. Use the slowest possible speed of the pick and place machine.
When implemented on a double-sided PCB, the mosaic module has to be assembled
during the final reflow cycle and cannot be reflowed when located on the bottom side of
the board.
If the motherboard thickness is 1.2mm or less, it is recommended to support the assembly
during the reflow process to minimize bow of the motherboard.

39

39
39

Development Kit

7 Development Kit
GP
PPS/EVENTSANTENNAAUX

ANTENNA
MAIN

POWER

ETH
RS232
COM
1&2
USB Dev

RS232
COM
3&4

USB Host

COM(3V3)

REF INThe mosaic Development Kit is composed of the mosaic module soldered on an interface
PCB (GTB-0051), itself plugged on the DevKit board (DEV-0043).
DevKit Part Number: 410331P3161 (including antenna and accessories).

7.1 Header Types
All headers have a pitch of 2.54mm, with the exception of J500 (PPS/EVENTS) and J501
(GP). Those headers have a 2mm pitch.

7.2 Powering the DevKit
There are two ways to power the DevKit:
1. From the USB Dev connector (J205). This allows powering the board from a PC orfrom a standard phone-charger adapter. The supported USB voltage range is 4.5V5.5V.
2. Using the POWER connector (J203). The supported voltage range is 5-36V.

40

40
40

Development Kit

When powering from the USB Dev connector, it is recommended to use the USB cableprovided with the DevKit. Low-quality USB cables often suffer from excessive voltage
drop, preventing correct operation.
It is safe to provide power to both connectors in parallel. The DevKit will use the sourcewith the highest voltage.
Make sure that a jumper is placed on header J200, as shown below. Otherwise the DevKit
will be powered, but not the mosaic module.

To measure the power consumption of the mosaic module (excluding the contribution
from the DevKit and the antenna, but including a small contribution from the interface
board, remove the jumper on J200 and connect the two pins to the probes of a multimeterin current-sensing mode. Measure the current flowing between the two pins and multiply
it by 3.3V to obtain the power consumption. It is recommended to set the multimeter inhigh ampere setting to keep the voltage drop as low as possible.

7.3 Antenna Connectors
There is no antenna connector on the DevKit. The antenna(s) must be connected directly
to the u.FL or MMCX antenna connector on the mosaic interface board.
The DC voltage (5V or 3.3V) at the antenna connectors is determined by the position of
the jumper on header J204, as shown below.

41

41
41

Development Kit

Vant = 5V

Vant = 3.3V

The jumper can be removed if the antenna does not need to be powered by the module.
In that case, there is no DC voltage at the antenna connector.

7.4 LEDs and General Purpose Output Pins

- POWER- GPLED- LOGLED

The POWER LED lights when the DevKit is powered.
The GPLED and LOGLED are connected to the homonymous pins of the mosaic module.
See section 4.11 for the pinout, and Appendix A for a description of the LED behavior. The
GPLED2 LED is not available on the DevKit.
The 3.3V GP1 and GP2 outputs are available on the J501 header (2x8 2mm-pitch DIL).

GP1

GP2

42

42
42

Development Kit

7.5 COM Ports
COM 1

COM 3

COM 2

COM 4

By default, the four COM ports of the mosaic module are routed to the four DB9
connectors of the DevKit. Electrical levels on the BD9 conform to the RS232 standard.
RTS/CTS lines are supported only on COM2 and COM3 (the mosaic has RTS/CTS lines on
COM1 as well, but they are not routed to the DevKit). Connection to a PC is done througha null-modem cable.

GND
RTS (O)NC
RX (I)TX (O)CTS (I)

Alternatively, 3.3V TTL signals are available through four 6-pin 2.54mm pitch headers, as
shown below. The pinout is compatible with standard FTDI 6-pin SIL connectors. To routea COM port to the 6-pin header instead of the BD9 connector, a jumper must be placedon J800 (COM1), J801 (COM2), J804 (COM3) and/or J805 (COM4). Only those COM ports
for which the jumper is placed are routed to the 6-pin header. The other COM ports arestill routed to the DB9 connectors, using the RS232 levels.

COM1
COM2
COM3
COM4

Note that, when using the DB9 connectors, the baud rate must not be larger than
230400baud. This limitation does not apply to the TTL signals.

43

43
43

Development Kit

7.6 PPS Out and Event Inputs

EVENTBPPSOUT

EVENTA

The PPSout pin of header J500 (2x8 2mm-pitch DIL) is connected to the PPSO pin of themosaic module through a 1.8V to 3.3V level shifter. The PPS level at the header is 3.3V.
The EVENTA and EVENTB pins of J500 are connected to the EventA and EventB pins of themosaic through a level shifter to 1.8V. The voltage level at the header pins must be
between -0.5V and +6V. These pins are pulled-down by a 100kOhm resistor.

7.7 Ethernet
The DevKit supports 10/100 Base-T Ethernet.
through the Ethernet connector.

It is not possible to power the DevKit

The development kit is compliant with EU EMC standards (EN303413) provided the
Ethernet interface is disabled (with the setEthernetMode user command). When the
Ethernet interface is enabled, harmonics from the RMII interface slightly violate thisregulation, as they radiate via the 60-pins board-to-board connector.
It is up to theintegrator to take the necessary precautions to avoid EMC violations in this case (e.g. use
shielded box).

7.8 USB Dev
That connector can be attached to a PC to power the DevKit and to communicate with themodule over its USB port.

7.9 USB Host
Reserved.

44

44
44

Development Kit

7.10 REF IN
The REF IN SMA connector can be used to feed the module with an external 10-MHz
sinusoidial frequency reference.

Input impedance:
Input level:

50 .
between -10dBm and +14dBm (0.2Vp-p to 3.2Vp-p).

7.11 Buttons

nRST
GND
LOGGING

Pressing the nRST button drives the nRST pin of the mosaic low, which resets the module.
Pressing the LOGGING button drives the LOGBUTTON pin of the mosaic low. This can beused to enabled and disable logging, as described in section 4.6.
The buttons are also connected to J601 and J602 2-pin headers (see above picture).
Connecting the nRST or LOGGING pins of these headers to ground is the same as pressing
the respective button.

7.12 SD Card Socket
The module can log files on the micro SD Card in this socket.
description of the SD Card logging on the mosaic module.

See section 4.6 for a

45

45
45

Evaluation Kit: mosaic-go

8 Evaluation Kit: mosaic-go

The mosaic-go Evaluation Kit is composed of the mosaic module soldered on an interface
board inside a metallic housing.
Mosaic-go part number:Single-antenna version, incorporating mosaic-X5: 410386 (including accessories).
Dual-antenna version, incorporating mosaic-H: 410397 (including accessories).
Dimensions: 71 x 59 x 12 mm ± 1 mm
Weight:58 g ± 1 g

8.1 Interfaces
8.1.1 USB
This micro-B connector is used to access the mosaic-go over USB.
It can also be used to power the mosaic-go. See also section 8.4.

8.1.2 RSV USB
This connector is reserved and should not be used.

8.1.3 RF_IN1 and RF_IN2
These are the main and auxiliary antenna connectors, connected to the ANT_1 and ANT_2
pins of the internal mosaic. See section 4.2 for details.

46

46
46

Evaluation Kit: mosaic-go

Mosaic-go provides a 5V DC supply to both antenna connectors. In the dual-antenna
version, a circuit similar to the one in section 4.2.3.2 is used. The combined main andauxiliary antenna power consumption must not exceed 150mA.
Note that RF_IN2 is only available on the dual-antenna mosaic-go.

8.1.4 TF Card
Socket for a micro SD Card. See section 4.6 for details.

8.1.5 6-pin Connector
Type: GH connector, 1.25mm pitch, 6 way. Mating connector housing: GHR-06V-S
Pin Name
VCC
GND
TXD1
RXD1
PPS
EVENT

Direction
PWR
Out
In
Out
In

Level
4.75V-5.5V
0
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL
3V3_LVTTL

Description
Main power supply
GroundSerial COM1 transmit line
Serial COM1 receive line
PPS output
Event timer input

Comment

Directly connects to TXD1 of internal mosaic, see 4.3
Directly connects to RXD1 of internal mosaic, see 4.3
PPSO from mosaic converted to 3.3V, see 4.9
Connects to EVENTA of mosaic through a 3V3 to 1V8level translator. See 4.8

8.1.6 4-pin Connector
Type: GH connector, 1.25mm pitch, 4 way. Mating connector housing: GHR-04V-S
Pin Name
NRST

Direction
In

Level
3V3_LVTTL

Description
Reset input

TXD2
RXD2
GND

Out
In

3V3_LVTTL
3V3_LVTTL
0

Serial COM2 transmit line
Serial COM2 receive line
GroundComment
Directly connects to nRST_IN of internal mosaic,
see 4.1
Directly connects to TXD2 of internal mosaic, see 4.3
Directly connects to RXD2 of internal mosaic, see 4.3

8.2 Accessories
The following accessories are delivered with mosaic-go:
Accessory
6-pin COM1 open-ended cable
4-pin COM2 open-ended cable
USB cable
Help user guide card

Comment
GH connector in one side and open ended in otherside. See wire color code below.
GH connector in one side and open ended in otherside. See wire color code below.
Micro-B USB cable
A small printed card which includes the basic how-to
guide and QR code to access Septentrio support
information.

47

47
47

Evaluation Kit: mosaic-go

8.2.1 6-pin COM1 Open-Ended Cable
Pin Name
VCC
GND
TX1
RX1
PPS
EVENT

Wire Colorredyellow
blue
green
white
black

8.2.2 4-pin COM2 Open-Ended Cable
Pin Name
NRST
TXD2
RXD2
GND

Wire Color
red
green
white
black

8.3 LEDs
The multi-color RGB LED is used to monitor the mosaic-go status. See Appendix A for
details.
LEDs
GPLED
LOGLED
POWER

Color
Component
Blue
Green
Red

Short Description
General purpose LED.
Internal logging status indicator.
On when mosaic-go is powered.

8.4 Powering the mosaic-go
There are two ways to power the mosaic-go. The nominal input power supply is 5V.
•

From the USB connector. This allows powering the board from a PC or from astandard phone-charger adapter. The supported USB voltage range is 4.5V-5.5V.

•

Using the VCC pin of the 6-pin connector. The supported voltage range is 4.75V5.5V.

It is safe to connect both supplies at the same time. Mosaic-go will use the source with thehighest voltage.
Note that the power consumption is about 50% higher than the power consumption of
the mosaic module alone (see section 3.5).
48

48
48

LED Status Indicators

Appendix A

LED Status Indicators

The LED pins can be used to monitor the module status. They can be used to drive
external LEDs. It is assumed that the LED lights when the electrical level of thecorresponding pin is high.
The general-purpose LEDs (GPLED and GPLED2 pins) are configured with thesetLEDMode command. The default configuration is:• GPLED: configured as PVTLED by default;• GPLED2: configured as RTKLED by default.
The following LED modes are supported.
GPLED mode

LED Behaviour

PVTLED

LED lights when a PVT solution is available.

RTKLED

LED is off if the PVT is not in RTK mode, blinks in float RTK and is solidon in fixed RTK.

DIFFCORLED

Differential correction indicator. In rover PVT mode, this LED reports
the number of satellites for which differential corrections have been
provided in the last received differential correction message (RTCM
or CMR).
LED behaviour
LED is off
blinks fast andcontinuously (10 times per
second)blinks once, then pauses
blinks twice, then pauses
blinks 3 times, then pauses
blinks 4 times, then pauses
blinks 5 times, then pauses

Number of satellites with corrections
No differential correction message received
0

1, 2
3, 4
5, 6
7, 8
9 or more

The LED is solid ’ON’ when the module is outputting differential
corrections as a static base station.
TRACKLED
LED behaviour
blinks fast andcontinuously (10 times per
second)blinks once, then pauses
blinks twice, then pauses
blinks 3 times, then pauses
blinks 4 times, then pauses
blinks 5 times, then pauses

Number of satellites in tracking
0

1, 2
3, 4
5, 6
7, 8
9 or more

49

49
49

LED Status Indicators

The LOGLED reports the SD card mount status and logging activity.
LED

LED Behaviour

LOGLED

LED is off when the SD card is not present or not mounted.
LED is on when the SD card is present and mounted. Short blinks
indicate logging activity.

50

50
50

System Noise Figure and C/N0

Appendix B

System Noise Figure and C/N0

The system noise figure, in dB, can be calculated as:
NFsys = 10*log10(10NFant/10 + (10NFrx/10-1)/10Gpreamp/10)
where• NFant is the antenna LNA noise figure, in dB;• NFrx is the module noise figure, in dB, as in section 4.2;
• Gpreamp is the net pre-amplification in front of the module, in dB.
For example, with a 2.5-dB antenna LNA noise figure, 30-dB antenna LNA gain and 15-dB
cable loss, Gpreamp = 30dB-15dB = 15dB and NRrx is 8.5dB (see table in section 4.2). In
this case, the system noise figure is:
NFsys = 10.log10(102.5/10+ (108.5/10-1)/1015/10) = 2.95 dB.

The C/N0, in dB-Hz, of a GNSS signal received at a power P can be computed by:
C/N0 = P - 10.log10(Tant + 290*(10NFsys/10-1)) + 228.6 dB
where• P is the received GNSS signal power including the gain of the antenna passive
radiating element, in dBW (e.g. -155dBW)• Tant is the antenna noise temperature, in Kelvin. Typically Tant = 130K for an opensky antenna.
• 228.6 is -10*log10(kB) with kB =1.38e-23 J/K the Boltzmann constant.

Note that, when connecting the ANT_1 RF input directly to a GNSS simulator, theapplicable value for NFsys is 8.5 dB and Tant=290K.

51

51
51

mosaic-H RF Gain Adjustment

Appendix C

mosaic-H RF Gain Adjustment

This appendix in only applicable to the dual-antenna mosaic-H module.
The pre-amplification in front of the mosaic-H is required to be between 15 and 35 dB(AGC gain reported by the receiver between 30 and 50dB). This is net pre-amplification,equal to the active gain of the antenna minus losses in the coax cables at 1.6 GHz. Above
35 dB of pre-amplification, the cross-talk of the auxiliary antenna into the main antenna
could degrade performance.
Applications which work with high gain antennas shall use in-line attenuators. These canbe implemented on the PCB as indicated in the figure below.

•••

TVS diode: use SESD0402X1BN-0010-098 or equivalentInductor L: select an inductor which is self-resonant between 1350 and 1450
MHz, with at least 300 mA current rating, e.g. Würth 744786139A
Avoid stubs at the RF path. The inductors, TVS diodes and R1 resistors shall bevery close to the RF trace, and have short grounding if applicable.

If the target attenuation is A dB, the resistors R1 and R2 can be dimensioned as follows,rounding to the nearest E123 value:
1 + 10−𝐴⁄20
𝑅1 = 50.
𝑂ℎ𝑚
1 − 10−𝐴⁄20
5000. 𝑅1
𝑅2 = 2𝑂ℎ𝑚
𝑅1 − 2500
The table below shows R1 and R2 values for some common attenuations:
Attenuation [dB]
6
10
20

3

R1 [Ohm]
150
100
56

R2 [Ohm]
39
68
220

E12 series multipliers of a power of ten: 1.0, 1.2, 1.5, ,1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, 8.2

52
52

52

mosaic-H RF Gain Adjustment

In case a 10-dB attenuator is inserted, the supported net pre-amplification range would
be 25-45 dB. If the design is intended for one particular target configuration, for instancewith 45 dB pre-amplification, it is recommended to optimize the attenuator towards a 25
dB net pre-amplification in front of the module. In the example of a 45 dB preamplification, a 20 dB attenuation shall be targeted.
The difference in pre-amplification in front of the main and auxiliary inputs of the module
shall be less than 5 dB. Higher mismatch could induce cross-talk between the signals ofboth antennas, which could get significant compared to typical errors induced byreflections and antenna non-idealities. When using identical antennas for the main andauxiliary input, differences between pre-amplification usually relate to differences in cable
lengths. For example, RG58 cable will typically have between 0.5 and 0.8 dB/m loss at the
GNSS operating frequencies (consider 1.6 GHz). Therefore, RG58 cable length differences
beyond 6 m could cause issues.
In applications with limited asymmetry between both pre-amplifications (<5 dB), it isrecommended to route the stronger signal to the main antenna input and the weakersignal to the auxiliary antenna input of the module. The circuit in section 4.2.3.2 is thensufficient.
In applications with a more substantial asymmetry, an attenuator circuit is to be inserted
to reduce the strongest signal to the level of the weaker one. An example is shown in the
figure below, in which case the strongest signal would be at the AUX connector. R1 andR2 shall be dimensioned as explained earlier, targeting an attenuation equal to the
expected difference between the pre-amplifications.

53

53
53

EMC Considerations

Appendix D

EMC Considerations

In applications in which the electronics are collocated with the GNSS antenna, cross-talk
could be a major concern. GNSS signals are very weak and easily interfered by radiatedharmonics of digital signals.
The most useful indicator of the signal reception quality is the C/N0 of the satellites inview. The C/N0 can be viewed in the RxControl graphical interface by clicking View / Carrier
to Noise Plot. In open-sky conditions, the C/N0 values should reach up to 50 dB-Hz for thestrong signals on L1 and L5, and up to 45 dB-Hz on L2, as illustrated below.

If the maximum C/N0 is lower than expected, interference and cross-talk from nearby
electronics is likely, and the source of the problem needs to be identified. This is where
the RF spectrum monitor built in the GNSS receiver comes in handy. The spectrum
monitor can be accessed in RxControl under the View / Spectrum View menu. The spectrum
can also be monitored offline if the BBSamples SBF blocks are logged.
The figure below shows a clean open-sky L1-band spectrum. The bump at 1575MHz
corresponds to the GNSS signals at the L1/E1 frequency, and is normal.

54

54
54

EMC Considerations

An example of interference is shown below.
This particular interference at about1598 MHz falls in the GLONASS L1 band and slightly degrades the L1 C/N0 of some
GLONASS satellites.

Try to keep personal computers and other equipment more than 2 meters away from theantenna while assessing electromagnetic compatibility of the integration.
RxControl also allows to observe the time domain signal. This should look like white
Gaussian noise as illustrated below.

55

55
55

EMC Considerations

Intermittent interference (µs-scale) has little impact if its duty cycle is below 10%. For
example, these short pulses from a digital circuit close to the antenna are essentiallyharmless.

If interference is detected, look for the root cause by switching off devices. Typical sourcesof interference are:• Unshielded flat cables carrying digital signals or power signals towards digital
circuits. Particularly, cable joints tend to radiate.
• High-speed digital devices, such as application processors, modems and cameras.
• Digital signals on the application board (e.g. clock signals, SDIO signals).
If spectral peaks are observed in the spectrum, this usually relates to radiated harmonics.
The source can be identified by looking for an integer relation between the observed
spectral peaks and the system frequencies. For example, peaks at 1200 and 1248 MHz
are an indication of an interfering source at 48 MHz as this maps to the 25th and 26th
harmonic of a 48 MHz signal. This may correspond to the frequency of a microcontroller
in the application.
Integration cross-talk can be solved in a number of ways:• Shift the clock frequency of the interfering signal to avoid the GNSS bands.
• Use shielding tape with conductive adhesive.
• Shield radiating circuits, preferably all around.
• Put digital signals in inner layers of the application board.
• Change the antenna location by experimentation.
• Enable the interference mitigation feature of the GNSS receiver. Narrow spectral
peaks can be eliminated with the notch filters (see the setNotchFilteringcommand). Intermittent wide-band cross-talk can often be eliminated with thewide band interference canceller (see the setWBIMitigation command).
The mosaic module has been designed to minimize radiation and can be used close to anantenna without additional shielding.
It is up to the integrator to ensure EMC regulations of the end-product are met. For
this please respect the guidelines of section 5.5.4.

56

56
56

Pad List

Appendix E
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15

RTC_XTALO
RTC_XTALI
GND
USB_DEV_P
USB_DEV_N
GND
USB_VBUS1
Reserved_NC
ONOFF
nRST_IN
MODULE_RDY
Reserved_NC
GPLED
GND
GND
GND
VDD_3V3
VDD_3V3
VDD_3V3
GND
GND
GND
RXD1
LOGLED
Reserved_NC
GND
GND
GND
GND
VDD_BAT
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
GND
Reserved_NC
Reserved_NC
PMIC_ON_REQ
GND
VDD_3V3
VDD_3V3
VDD_3V3
GND
Reserved_NC
Reserved_NC
RTS1
Reserved_NC
Reserved_NC
GND
Reserved_NC
Reserved_NC
GND
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
GND

Pad List
C16
C17
C18
C19
C20
C21
C22
C23
D1
D2
D3
D21
D22
D23
E1
E2
E3
E21
E22
E23
F1
F2
F3
F21
F22
F23
G1
G2
G3
G21
G22
G23
H1
H2
H3
H21
H22
H23
J1
J2
J3
J21
J22
J23
K1
K2
K3
K21
K22
K23
L1
L2
L3
L21
L22
L23
M1
M2
M3
M21

GND
GND
VDD_3V3
VDD_3V3
VDD_3V3
Reserved_NC
Reserved_NC
GND
TXD1
GND
RXD4
GND
GND
GND
CTS1
GND
TXD4
GND
GND
GND
RXD2
nRST_LAN
Reserved_NC
GND
GND
GND
RTS2
GND
Reserved_NC
GND
Reserved_NC
GND
TXD2
RMII_TX1
Reserved_NC
GND
GND
GND
CTS2
RMII_TX0
Reserved_NC
GND
GND
GND
RXD3
GND
LOGBUTTON
GND
GND
GND
RTS3
RMII_TXEN
GP2
GND
GND
GND
TXD3
RMII_RXER
GPLED2
GND

M22
M23
N1
N2
N3
N21
N22
N23
P1
P2
P3
P21
P22
P23
R1
R2
R3
R21
R22
R23
T1
T2
T3
T21
T22
T23
U1
U2
U3
U21
U22
U23
V1
V2
V3
V21
V22
V23
W1
W2
W3
W21
W22
W23
Y1
Y2
Y3
Y21
Y22
Y23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10

GND
2V8_INCTS3
RMII_CRSDVReserved_NC
GND
GND
2V8_OUT
GND
GND
GND
GND
GND
VANT
Reserved_NC
RMII_RXD0
GND
GND
GND
VANT
Reserved_NC
RMII_RXD1
Reserved_NC
GND
GND
GND
Reserved_NC
GND
Reserved_NC
GND
GND
GND
Reserved_NC
MDC
Reserved_NC
GND
GND
ANT_2
Reserved_NC
MDIO
Reserved_NC
GND
GND
GND
SD1_DATA0
GND
Reserved_NC
GND
GND
GND
SD1_CLKRMII_CLK
Reserved_NC
GP1
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC

AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23

Reserved_NC
Reserved_NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SD1_CMD
GND
GND
GND
GND
GND
Reserved_GND
GND
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Reserved_NC
Reserved_NC
SYNC
1V8_OUT
Reserved_NC
EVENTA
EVENTB
PPSO
Reserved_NC
Reserved_NC
Reserved_NC
Reserved_NC
GND
VTUNE
GND
REF_O
REF_I
GND
GND
ANT_1
GND
GND
GND

57

57
57