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PAPER

Special Section on Reconfigurable Systems

Architecture of an Asynchronous FPGA for
Handshake-Component-Based Design
Yoshiya KOMATSU†a) , Nonmember, Masanori HARIYAMA† , Member, and Michitaka KAMEYAMA† , Fellow

SUMMARY
This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent-based design is suitable for large-scale, complex asynchronous
circuit because of its understandability. This paper proposes an areaeﬃcient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding
is employed to construct circuits robust to delay variation because the data
paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results showthat the proposed FPGA can implement handshake components eﬃciently.
key words: FPGA, reconfigurable LSI, self-timed circuit, asynchronous
circuit1.

Introduction

Recent technology scaling enables designs with billions oftransistors. On the other hand, the increased complexity ofcircuits leads to two problems. The first is the cost problem. The process development cost has increased the expense of the fabrication cost of chips. Also, design costand verification cost become serious problem. The second is performance problem. Currently, most digital circuits
are synchronous circuits which operate based on clock signals. As the number of transistors integrated on a chip has
increased, clock distribution network has become complex
and its power consumption has become large. In addition,
it becomes severe challenge to increase clock frequency because clock signal should be distributed all over a chip.
To solve the first problem, Field-programmable gate arrays (FPGAs) are widely used to implement special-purpose
processors. Since users can program logic functions andinterconnections of FPGAs directly, it is easy to develop
special-purpose processors. In addition, FPGAs are costeﬀective because they are produced in large quantities.
To solve the second problem, asynchronous circuit isattracting attention. In asynchronous circuit, data transfer isdone by handshaking using a request signal and an acknowledge signal. Since no clock signal is necessary, problems
caused by clock distribution network do not arise. However,the problem is that it is diﬃcult to design asynchronous circuits.
As the design methods for asynchronous circuits,handshake-component-based design [1] was proposed. In
Manuscript received November 10, 2012.
Manuscript revised March 8, 2013.
†
The authors are with the Graduate School of Information Sciences, Tohoku University, Sendai-shi, 980–8579 Japan.
a) E-mail: ykomatsu@ecei.tohoku.ac.jp
DOI: 10.1587/transinf.E96.D.1632

handshake-component-based design, asynchronous circuits
are designed by connecting handshake components. Sincevarious handshake components such as for data processing
and data path control are defined, it is easy to design asynchronous data path and its controller. Therefore, handshakecomponent-based design is suitable for applications that
contain complex data processing. Besides, Balsa [2] is proposed as a design methodology that uses handshake components. Balsa is a hardware description language and it
allows circuit designers not to pay attention to low-level details such as control of handshake. Moreover, there are synthesis tools that generate handshake circuits which consistof handshake components and standard cell netlists from
Balsa descriptions. Using Balsa, circuit designer can easily implement complex large-scale circuits such as a DMA
controller [2] and a microprocessor [3]. Thus, handshakecomponent-based design is suitable for complex large-scale
asynchronous circuits.
To solve the cost and performance problems, someasynchronous FPGAs has been proposed [4]–[10]. Asynchronous FPGAs developed by Cornell University [4], [5],Achronix [6] and the University of Tokyo [7] employ finegrained pipelined architecture to achieve high throughput.
References [8]–[10] propose asynchronous FPGA architecture focusing on low power consumption. The asynchronous
FPGA proposed in [8], [10] combine two handshake protocols to reduce energy consumption caused by data operations and transmissions. Reference [9] proposes autonomous power-gating scheme based on handshake protocol. However, conventional asynchronous FPGAs cannot
implement handshake components eﬃciently since their architecture only support simple handshake sequence specialized for simple data processing and transferring. Therefore,
it is diﬃcult to design control-intensive application on conventional FPGAs.
In this paper, we propose an FPGA architecture thatis suitable for handshake-component-based asynchronous
circuit. The proposed architecture implements handshakecomponents that are defined in Balsa eﬃciently. Therefore,
the proposed FPGA is suitable for implementing complex
applications. Small frequently-used handshake components
are implemented on a Logic Block (LB), and other handshake components are implemented using more than one
LB. As handshake components can be mapped directly on
the proposed architecture, circuit designers can utilize existing CAD tools that generate a netlist of handshake components. Therefore, a design method for the proposed FPGA

c 2013 The Institute of Electronics, Information and Communication Engineers
Copyright KOMATSU et al.: ARCHITECTURE OF AN ASYNCHRONOUS FPGA FOR HANDSHAKE-COMPONENT-BASED DESIGN

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is established.
2.

Handshake-Component-Based Asynchronous Circuit Design

2.1

Handshake Component

In asynchronous circuit, synchronization between circuits
is done by handshaking with a request signal and an acknowledge signal. Figure 1 shows a four-phase handshakesequence. First, active port sets the request wire to “1”as shown in Fig. 1 (a). Second, passive port sets the acknowledge wire to “1” as shown in Fig. 1 (b). Third, active
port sets the request wire to “0” as shown in Fig. 1 (c). Finally, passive sets the acknowledge wire to “0” as shown in
Fig. 1 (d) and wire values return to initial state. Data signals
are sent along with request signals or acknowledge signals.
To design asynchronous circuits, various design
methodologies has been proposed. Petrify [11] is an asynchronous circuit synthesis tool that uses a Signal Transition
Graph (STG) [12]. STG describes transition sequences ofwires. Therefore, STG is suitable to describe control circuits. However, it is diﬃcult to design circuits which contain many wires. Another design methodology uses asynchronous circuit elements called handshake components.
Asynchronous circuits are constructed by connecting handshake components. Handshake components were created foruse in the synthesis of the language Tangram [1] created byPhilips Research. Figure 2 shows handshake components.
Handshake components constitute a handshake circuit. Eachhandshake component has ports and is connected to anotherhandshake component through a channel. Communication
between handshake components is done by sending request
signal from the “active” port and acknowledge signal fromthe “passive” port. Depending on the kind of handshakecomponents, data signals are sent along with request signals or acknowledge signals. The number of ports of ahandshake component and the width of data signal can bevaried. There are 46 handshake components [13] and eachhandshake component is used for data processing or data
path control. Figure 3 shows a Sequence component. Sequence component has an activate port and N activateOut
ports. Sequence component starts handshaking sequentiallyfrom activateOut0 to activateOutN − 1. Then, handshakecomponent connected to each activateOut port is activated.
In this manner, Sequence component controls process sequence. Figure 4 shows signal transitions of a Sequence
component. Arrows denote dependencies between signaltransitions. The behavior of a Sequence component which
has two activateOut ports is described as follows:
1. activate.req is set to “1”
2. activateOut0.req is set to “1”
3. activateOut0.ack is set to “1”
4. activateOut0.req is set to “0”5. activateOut0.ack is set to “0”Fig. 3Fig. 1

A four-phase handshake sequence.

Fig. 2

Handshake components and channels.

Fig. 4

Sequence component.

Behavior of a Sequence component.

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Fig. 5

Handshake components for a data path controller.

Fig. 7

Fig. 6

A simple handshake circuit (4 bit counter).
Fig. 8

6. activateOut1.req is set to “1”
7. activateOut1.ack is set to “1”
8. activate.ack is set to “1”
9. activate.req is set to “0”
10. activateOut1.req is set to “0”
11. activateOut1.ack is set to “0”
12. activate.ack is set to “0”As seen above, handshake components execute complex
handshake sequences. However, handshake circuits are easily understandable and manageable because a function ofeach handshake component is clear and each handshake issymbolized by a channel and ports. Asynchronous circuitswith complex process control are designed using handshakecomponents shown in Fig. 5. Figure 6 shows an example ofa handshake circuit.
Also, there are tools that translate high-level circuit description into handshake circuit to synthesize asynchronous
circuit. Thus, handshake-component-based design is suitable for complex and large-scale asynchronous circuits.
2.2

A bundled-data channel.

Implementation of Handshake Components

Circuit synthesis is done by replacing each handshake component with corresponding asynchronous circuit. Therefore,
implementations in diﬀerent technologies are obtained byproviding circuit libraries. In asynchronous circuit, a hazard
is serious problem [14]. A hazard is a unwanted glitch on asignal and it causes a malfunction. To guarantee correct operation of implemented application, asynchronous circuitsthat corresponds to handshake components should be haz-A four-phase dual-rail channel.

ard free.
In handshake-component-based design, implementations in diﬀerent asynchronous data encodings are obtainedby changing circuit libraries. Asynchronous data encoding
schemes are mainly classified into
• Single-rail encoding (ex. bundled-data encoding)• Dual-rail encoding (ex. four-phase dual-rail encoding)Bundled-data encoding is the most common method in the
single-rail encoding. Figure 7 shows a bundled-data channel. The value is encoded as in a synchronous circuit using N wires to denote an N-bit number, and control signals are encoded using dedicated wires denoted by REQ and
ACK. Therefore, a channel which contains N-bit data consists of N + 2 wires. Bundled-data encoding requires the
explicit insertion of matching delays in a control signal oriented in the same direction as data signal. This is because
the control signal is never received before the bundled value
is valid. For FPGAs, since the data path is programmable,
complex programmable delay elements are required. As aresult, bundled-data encoding is not suitable for FPGAs.
Four-phase dual-rail (FPDR) encoding is the mostcommon method in dual-rail encodings. Figure 8 shows a
FPDR channel. The FPDR encoding encodes a bit and acontrol signal oriented in the same direction as data signal
onto two wires. Table 1 shows the code table of four-phasedual-rail encoding. The data value “0” is encoded as (0, 1)
and “1” is encoded as (1, 0). Moreover, the spacer is encoded as (0, 0). Figure 9 shows the example where data val-

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Table 1

Code table of four-phase dual-rail encoding.

Fig. 9

Example of four-phase dual-rail encoding.
Fig. 10Overall architecture.

ues “0”, “0” and “1” are transferred. The main feature isthat the sender sends spacer after a data value. The receiverknows the arrival of a data value by detecting the changeof either bit: “0” to “1”. In the FPDR encoding, the value
is made implicit in a control signal and no delay insertionis therefore required [14]. Hence, the FPDR encoding isrobust to delay variations and the ideal one for FPGAs in
which the data path is programmable. In the dual-rail encoding, to transfer an N-bit value, 2N + 1 wires are required.
Therefore, the FPDR encoding is employed in the proposedarchitecture.
3.

Architecture

3.1

Overall Architecture

Figure 10 shows the overall architecture of the proposed
FPGA and Fig. 11 shows the programmable interconnection
resources (Connection Blocks and Switch Blocks) aroundan LB. The FPGA consists of mesh-connected cells likeconventional FPGAs. As shown in Fig. 10, each cell includes an LB, two Connection Blocks (CBs) and a Switch
Block (SB). The upper CB connects SBs to N1, N2 and S
terminals of two LBs, and the bottom CB connects SBs to
E1, E2 and W terminals. The proposed architecture canimplement 39 out of 46 handshake components defined in
Balsa manual [13]. Handshake components that have multiple ports or wide data path can be implemented using several LBs. As mentioned in Sect. 2.2, the FPDR encoding
is employed for asynchronous data encoding. Because the
FPDR encoding is employed, three wires are required for adata bit. Two wires are used for a data encoded in FPDR
encoding, and one wire for a request signal and an acknowledge signal. The proposed FPGA is based on Quasi-DelayInsensitive (QDI) model which assumes that gate delays andwire delays are unknown, and signal transitions occur at thesame time at all end-points in wire forks [14], [15].
As shown in Fig. 11, an SB consists of diamondswitches and Req/Ack modules. Diamond switches allow
a data signal on a track to connect to other tracks. Figure 12
shows the structure of the Req/Ack module. The Req/Ack
module consists of switches, an OR gate and the Muller Celement [14]. It allows a control signal on a track to con-Fig. 11

Programmable interconnection resources around an LB.

Fig. 12Structure of an Req/Ack module.

nect to other tracks. In addition, two control signals can bemerged using a C-element or an OR gate. The LB accesses
nearby communication resources through CBs, which connects input and output terminals of the LB to SBs throughprogrammable switches.

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Fig. 14

Fig. 133.2

Structure of an LB.

Logic Block Structure
Fig. 153.2.1

Structure of a BinaryFunction module.

Overall Structure of a Logic Block

Figure 13 shows an LB of the proposed architecture. The
proposed FPGA architecture can implement 39 handshakecomponents. The LB consists of a BinaryFunction module,
a Variable module, a Sequence module, a CallMUX module,a Case module, and an Encode module. An Input switch
module and an Output switch module connect modules to
CBs. As mentioned in previous section, circuit synthesis isdone by replacing each handshake component with corresponding asynchronous circuit. Thus, asynchronous circuits
can be implemented on a conventional FPGA by replacing
each handshake component with a combination of LUTs.
As mentioned in Sect. 2.2, asynchronous circuits that implement handshake components should be hazard free. However, it is diﬃcult to implement hazard free asynchronous
circuits using LUTs because delay time of SBs and CBs affects circuit operations. Therefore, in the proposed architecture, each LB includes dedicated circuits for implementing
handshake components.
3.2.2

BinaryFunction component.

BinaryFunction Module Structure

In handshake-component-based design, logical operation
and arithmetic operation are denoted by BinaryFunction
components as shown in Fig. 14. As mentioned in Sect. 3.1,
the proposed architecture employs the FPDR encodingthat encodes a bit and a control signal onto two wires.
Therefore, acknowledge signals of BinaryFunctionIn0,
BinaryFunctionIn1 and BinaryFunctionOut port are sentalong with data signals. In the proposed architecture, a BinaryFunction module is used to implement a BinaryFunction component. Figure 15 shows a structure of a BinaryFunction module. the module consists of an FPDR 4-input
LUT and logic gates that detect arrival of valid data andspacers. When valid signals arrive at the LUT In, Data valid
becomes “1” and the LUT starts to operate. The result of the
LUT is stored in the Variable module. Then, LUT ready is
set to “1” and the LUT stops its operation. Figure 16 shows
the structure of the LUT. For simplicity, instead of the 4input LUT which is used in the actual LB, a 2-input LUT
is shown. The LUT is implemented based on [4] and [14].
A BinaryFunction module can implement a BinaryFunction
component with two 2-bit inputs or a BinaryFunction component with a 1-bit and a 3-bit input. A complex BinaryFunction component can be implemented by combining BinaryFunction modules.
3.2.3

Variable Module Structure

Figure 17 shows a Variable component that stores data. In
the proposed architecture a Variable component is imple-

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1637(a) Out.T generating circuit.

Fig. 18

Structure of a 2-bit Variable module.

(b) Out.F generating circuit.
Fig. 16

LUT structure.

Fig. 19

Fig. 17Structure of a Variable element.

Variable component.

mented using a Variable module shown in Fig. 18. The Variable module stores 2-bit data. The VarIn port is used tostore 2-bit data and VarOut0 and VarOut1 ports are used
to read 2-bit data. The Variable module mainly consists of
Variable elements that store data, AND gates that generate
output signals and C-elements. Figure 19 shows a structureof a Variable element. As shown in Fig. 20, Writing data is
performed in the following sequence:
1. A valid data arrives at VarIn and the data is stored in
Variable elements
2. Var0 ready and Var1 ready become “1”
3. VarIn.ack becomes “1”
4. A spacer arrives at VarIn
5. Var0 ready and Var1 ready become “0”6. VarIn.ack becomes “0”Figure 21 shows signal transitions of a Variable module ina read operation. Reading data from the VarOut0 port isperformed in the following sequence:

Fig. 20

Behavior of a Variable module in a write operation.

Fig. 21

Behavior of a Variable module in a read operation.

1. VarOut0.req is set to “1”
2. AND gates connected to VarOut0 output the datastored in Variable elements
3. VarOut0.req is set to “0”4. AND gates output spacer
Reading data from the VarOut1 port is performed in a similar manner. In addition, a Variable module and a BinaryFunction module are used to implement BinaryFunction
component. Figure 22 shows signal transitions of a BinaryFunction module and a Variable module. The behavior as a

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Fig. 23

Structure of a Sequence module.

Fig. 22 Behavior of a BinaryFunction module and a Variable module asa BinaryFunction component.

BinaryFunction component is described as follows:
1. A valid data arrives at an LUT In of a BinaryFunction
module2. Data spacer and Data valid become “1”
3. LUT starts operation following the rise of Data valid
4. The Variable element connected to the LUT stores thedata and then LUT ready is set to “1”
5. VarOut0[0] outputs valid data, and LUT out outputs aspacer
6. A spacer arrives at the LUT in
7. Data spacer and Data valid become “0”
8. LUT ready becomes “0”9. VarOut0 0 outputs a spacer
3.2.4

Fig. 24Structure of a T-element.

Fig. 25

Structure of a S/T-element.

Sequence Module Structure

Figure 23 shows a structure of a Sequence module. The Sequence module mainly consists of a T-element and an S/Telement. Figures 24 and 25 show detailed structure of a Telement and an S/T-element. A Sequence module can implement a Sequence component and a Concur component asshown in Figs. 26 and 27. Sequence component and Concur component are used to control a process sequence of acircuit. A Sequence module can implement two activateOut
ports. Usually, a Sequence component is implemented by aS-element and a Concur component is implemented by two
T-element and a C-element as shown in Fig. 28. In the proposed architecture, a Sequence component is implemented
by S/T-element and a Concur component is implemented byT-element, S/T-element and C-element. When a Sequence
component is implemented, activate.req, activateOut0.req,
activateOut0.ack and activateOut1.req in Fig. 26 correspondtoS equenceActivate.req,
S equence0.req,
sequence0.ack and S equence1.req in Fig. 23.
Since
activate.ack and activateOut1.ack are connected as shownin Fig. 28 (a), there is no dedicated wires in a Sequence module. Figure 29 shows signal transitions of a Sequence module as a Sequence component. The behavior as a Sequence
component is described as follows:
1. S equenceActivate.req is set to “1”Fig. 26

Sequence component.

Fig. 27

Concur component.

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1639(a) Sequence component.
Fig. 30

Behavior of a Sequence module as a Concur component.

(b) Concur component.
Fig. 28

Structure of Sequence component and Concur component.
Fig. 31

CallMUX component.

• FalseVariable.ack is set to “1” following the riseof S equence0.ack and Concur1.ack• S equence0.req is set to “0” following the rise of
S equence0.ack• Concur1.req is set to “0” following the rise ofConcur1.ack
5. • S equenceActivate.req is set to “0” following therise of FalseVariable.ack• S equence0.ack is set to “0” following the fall of
S equence0.req• Concur1.ack is set to “0” following the fall ofConcur1.req
6. FalseVariable.ack is set to “0”4.

Fig. 29

Behavior of a Sequence module as a Sequence component.

2. S equence0.req is set to “1”
3. S equence0.ack is set to “1”
4. S equence0.req is set to “0”5. S equence0.ack is set to “0”6. S equence1.req is set to “1”
7. S equenceActivate.req is set to “0”8. S equence1.req is set to “0”When a Concur component is implemented, activate.req,
activate.ack,
activateOut0.req,
activateOut0.ack,
activateOut1.req and activateOut1.ack in Fig. 27 correspond to S equenceActivate.req, FalseVariable.ack,
Concur1.req andS equence0.req,
sequence0.ack,
Concur1.ack in Fig. 23. Figure 30 shows signal transitionsof a Sequence module as a Concur component. The behavior as a Concur component is described as follows:
1. S equenceActivate.req is set to “1”2. S equence0.req and Concur1.req are set to “1”
3. • S equence0.ack is set to “1” following the rise of
S equence0.req• Concur1.ack is set to “1” following the rise ofConcur1.req

A Sequence module is also used to implement Loop component and While component.
3.2.5

CallMUX Module Structure

A CallMUX module implements a CallMUX component
shown in Fig. 31. The CallMUX component is used to integrate input channels into a output channel. Figure 32 showsa structure of a CallMUX module. CallMUX module implements four input ports. Every input and output ports cantransfer 1-bit data. Figure 33 shows signal transitions of a
CallMUX module as a CallMUX component. The behavior
when a data arrives at the CallMUXIn0 port is described asfollows:
1. A valid data arrives at CallMUXIn0 port
2. CallMUXOut outputs the value that CallMUXIn0 re-

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Fig. 34

Fig. 32

Fig. 33

Case component.

Structure of a CallMUX module.

Behavior of a CalMUX module as a CallMUX component.

ceived
3. CallMUXOut.ack is set to “1”
4. CallMUXIn0.ack is set to “1”
5. A spacer arrives at CallMUXIn0 port
6. CallMUXOut outputs a spacer
7. CallMUXOut.ack is set to “0”8. CallMUXIn0.ack is set to “0”Fig. 35

Structure of a Case module.

CallMUX module can also implement Call component,
Continue component and ContinuePush component.
3.2.6

Case Module Structure

A Case module implements a Case component shown in
Fig. 34. Case component selects one of the CaseOut ports
according to a value that CaseIn port received, and starts
handshaking. Figure 35 shows a structure of a Case module.
A Case module implements four CaseOut ports. Figure 36
shows signal transitions of a Case module as a Case component. The behavior when data “0” arrives at the CaseIn port
is described as follows:
1. Data “0” arrives at CaseIn port
2. CaseOut0.req is set to “1”
3. CaseOut.ack is set to “1”
4. CaseIn.ack is set to “1”
5. A spacer arrives at CaseIn port
6. CaseOut0.req is set to “0”7. CaseOut.ack is set to “0”8. CaseIn.ack is set to “0”Case module can also implement CaseDEMUX component,

Fig. 36

Behavior of a Case module as a Case component.

CaseFetch component, DecisionWait component, PassivatorPush component and SynchPush component.
3.2.7

Encode Module Structure

An Encode module implements an Encode component
shown in Fig. 37. When handshake through EncodeInk port
starts, EncodeOut outputs a data “k”. Figure 38 shows astructure of an Encode module. An Encode module implements four EncodeIn ports. Figure 39 shows signal transitions of an Encode module. The behavior when handshakethrough EncodeIn0 ports starts is described as follows:
1. EncodeIn0.req is set to “1”
2. EncodeOut outputs the data “0”KOMATSU et al.: ARCHITECTURE OF AN ASYNCHRONOUS FPGA FOR HANDSHAKE-COMPONENT-BASED DESIGN

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Fig. 37

Fig. 38

Encode component.

Structure of an Encode module.
Fig. 40

An implementation of a complex Variable component.

handshake components. Therefore, the number of the transistors of the proposed FPGA is small because of resource
sharing.
3.3 Implementation of Complex Handshake Components
Fig. 39

Table 2Behavior of an Encode module.

Handshake components and its corresponding resources.

3. EncodeOut.ack is set to “1”
4. EncodeIn0.ack is set to “1”
5. EncodeIn0.req is set to “0”6. EncodeOut outputs spacers
7. EncodeOut.ack is set to “0”8. EncodeIn0.ack is set to “0”As shown in Table 2, each module implements several

In the proposed architecture, each LB contains modules
to implement handshake components. However, to keepa structure of LB simple, handshake components that canbe implemented using an LB is limited. Therefore, in the
proposed architecture, frequently-used simple handshakecomponents are implemented using an LB, and rarely-usedlarge-scale handshake components are implemented using
multiple LBs and programmable interconnections. As a example of complex handshake components, an implementation of Variable component that stores Width-bit data isshown below. In general, Variable component has a passive
port that receives a Width-bit data and N passive ports to
output Width-bit data as shown in Fig. 17. In the proposedarchitecture, an LB contains a Variable module that stores
2-bit data. Also, a Variable module has a 2-bit input port
and two 2-bit output ports. Therefore,
  

N
Width
×
(1)
2
2
LBs are required to implement a Variable component with
N Width-bit output ports as shown in Fig. 40.

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1642(a) Synchronous 4-bit counter.

Fig. 41
Table 3

LB of a conventional architecture.

Transistor count of a cell and its breakdown.

(b) Synchronous 4-bit counter with conditional branch.
Fig. 42cuits.

Synchronous circuits equivalent to asynchronous evaluation cir-Table 44.

Evaluation results of transistor counts.
(a) Results of 4-bit counter.

Evaluation

The proposed FPGA is implemented in e-Shuttle 65 nm
CMOS process with 1.2 V supply. The circuits are evaluated by pre-layout simulation with HSPICE. Therefore,
parasitic capacitance and resistance of programmable interconnection resources are not considered in evaluation
results. For comparison, The conventional asynchronous
FPGA architecture is implemented. Figure 41 shows the
LB structure of the conventional FPDR FPGA architecture.
The LB of the conventional FPGA mainly consists of an
LUT, an asynchronous register, an FPDR multiplexer and an
FPDR demultiplexer [14]. In the conventional asynchronous
FPGA, applications are designed combining seven building
blocks [5].
Table 3 shows the comparison result of the cells of
the proposed architecture and the conventional architecture.
Since the proposed architecture contains modules for handshake components, the transistor count of a cell is increasedby 62%.
The next evaluation shows the implementation resultsof a 4-bit counter and a 4-bit counter with conditional
branch. Figure 42 shows equivalent synchronous circuits ofthe test applications. Table 4 shows the comparison of cellcounts and transistor counts. The benchmark circuits consistof cells and each cell includes an LB, an SB and two CBs
as shown in Fig. 10. In the case of 4-bit counter, the numberof cells is reduced by 21%. However, the transistor countis increased by 27% compared to the conventional architecture as shown in Table 4 (a). On the other hand, as shown in
Fig. 4 (b) the numbers of cells and transistors are reduced by(b) Results of 4-bit counter with conditional branch.

45% and 11% in the case of 4-bit counter with conditional
branch. This is because handshake-component-based design
can eﬃciently implement applications that include data pathcontrol such as conditional branch.
Table 5 shows the comparison of energy consumptions
per operation to count up. Compared to the conventional architecture, the energy consumptions is reduced by 9% and
27% respectively. The results show that the proposed architecture is suitable for applications with complex sequencecontrol.
Table 6 shows the comparison of throughputs. The
throughput is defined by the number of operations per second. Compared to the conventional architecture, throughputs are decreased by 51% and 41% respectively. This isbecause handshake components execute complex handshakesequence.

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Table 5count up.

Evaluation results of energy consumptions per operation to

Table 6

5.

Evaluation results of throughputs.

Conclusions

This paper presented an architecture of an asynchronous
FPGA for handshake-component-based design. The proposed FPGA architecture implements handshake components eﬃciently. Thus, the proposed architecture is suitable for the synthesis tools that generate netlists consistof handshake components, such as Balsa. In addition, thehandshake-component-based design is suitable for applications that have complex data path controls. Therefore,
the proposed architecture is suitable to implement complex
large-scale asynchronous circuits.
As a future work, hybrid architecture of the conventional asynchronous FPGA and the proposed asynchronous
FPGA can be considered. The conventional asynchronousarchitecture is simple and it can achieve high throughput. On the other hand, the proposed architecture is suitable for applications that have complex data path controls.
Therefore, employing the conventional architecture in data
path and the proposed architecture in sequence controller,
low power, small area and high throughput implementation
would be achieved.
Acknowledgment
This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with
STARC, e-Shuttle, Inc., Fujitsu Ltd., Cadence Design Systems Inc. and Synopsys Inc. This work is supported by JSPS
KAKENHI Grant Number 25·5513.
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Yoshiya Komatsu
received the B.E. degree
in Information Engineering and M.S. degree inInformation Sciences from Tohoku University,
Sendai, Japan, in 2009 and 2011, respectively.
He is currently working toward the Ph.D. degreein Graduate School of Information Sciences, Tohoku University. His research interests include
reconfigurable computing and asynchronous architecture.

IEICE TRANS. INF. & SYST., VOL.E96–D, NO.8 AUGUST 2013

1644

Masanori Hariyama
received the B.E.
degree in electronic engineering, M.S. degree
in Information Sciences, and Ph.D. in Information Sciences from Tohoku University, Sendai,
Japan, in 1992, 1994, and 1997, respectively.
He is currently an associate professor in Graduate School of Information Sciences, Tohoku
University. His research interests include VLSI
computing for real-world application such as
robots, high-level design methodology for VLSIs and reconfigurable computing.

Michitaka Kameyama
received the B.E.,
M.E. and D.E. degrees in Electronic Engineering from Tohoku University, Sendai, Japan, in
1973, 1975, and 1978, respectively. He is currently Dean and a Professor in the Graduate
School of Information Sciences, Tohoku University. His general research interests are intelligent integrated systems for real-world applications and robotics, advanced VLSI architecture, and new-concept VLSI including multiplevalued VLSI computing. Dr.Kameyama received the Outstanding Paper Awards at the 1984, 1985, 1987 and 1989
IEEE International Symposiums on Multiple-Valued Logic, the Technically
Excellent Award from the Society of Instrument and Control Engineers ofJapan in 1986, the Outstanding Transactions Paper Award from the IEICE
in 1989, the Technically Excellent Award from the Robotics Society ofJapan in 1990, and the Special Award at the 9th LSI Design of the Year in
2002. Dr. Kameyama is an IEEE Fellow.