DEVELEOPMENT OF A SINGLE-CHIP RF FRONT-END LSI FOR WIRELESS LANWITH TRANSMISSION LINE BASED MATCHING CIRCUITS
R. K. Pokharel, A. Imada, H. Kanaya, and K. Yoshida
Department of Electronics, Kyushu University
744 Motooka, Nishi-ku Fukuoka 819-0395, Japan
Email: pokharel@ed.kyushu-u.ac.jp

Abstract: In Direct Conversion Receiver (DCR) architecture, the design of mixer is one of the most important steps
for a high-performance DCR because it involves the issues of flicker (1/f) noise and conversion gain simultaneously.
So, minimizing 1/f noise while achieving high gain without sacrificing linearity for high performance DCR is one of
the critical issues. A method to reduce noise factor of a down-conversion mixer by 5-6 dB and to increase
conversion gain by 5-6 dB simultaneously has been proposed. In order to reduce the chip size, on-chip CPW lines
has been employed to realize on-chip impedance matching circuits which saves 30-40% chip area than those using
the spiral inductors. Finally, RF front-end which consists of on-chip CPW matching circuits, LNA, VCO, and downconversation mixer has been designed and fabricated on TSMC BiCMOS SiGe 0.35 µm one-poly three-metals
technology. A few of the measured results to verify the design theory are presented.

1. INTRODUCTION
As evidence from the recent and rapid growth of 3G
cellular phones, wireless LAN, RFID tags, ETC (ETC:
Electronic-Toll Collection) systems and so on, there are
ever increasing demands of high performance, small
size, and high speed microwave devices, circuits,
components to meet the existing and future demands ofwireless systems [1]-[5]. Therefore, the design ofanalog circuits has become important in CMOS-LSI
technology for not only in optical regime, but also for
microwave frequency band. These high-frequency
analog LSI circuits (here after RFIC: Radio Frequency
Integrated Circuits) design differs from theconventional low-frequency analog circuits because
spiral inductors are indispensable in designing
amplifiers, mixers, VCOs, or impedance-matchingcircuits that results in the miniaturization of RFIC
components a difficult task. Therefore, the void due tothe lack of a new design theory for miniaturization ofeach component and to reduce numbers of the systemcomponents using microwave circuit design rules [6]has been felt for a long time for on-chip realization.
The applications of the distributed elements made oftransmission lines were reported in the CMOS or
BiCMOS RF-LSI chip [7]-[9]. The CPW lines was
exploited as an inductor and used to design aconventional-type matching circuit for an LNA [7] inmicrowave-band frequency, and they were also used as
an inductor in GaAs based monolithic microwave
integrated circuit (MMIC) for millimeter-wave devices[8], [9]. However, the application of CPW lines as an
inductor takes larger space than a conventional spiralinductor [7]. Some of the present authors have also
implemented the CPW superconducting impedancematching circuit for interconnecting an antenna andduplexer [10], [11] and LSI chips [12], [13].
On the other hand, the direct conversion receiver(DCR) has been attracting much attention in systemarchitecture level due to its simplicity and low cost
fabrication of a single-chip realization for wirelesstransceivers. However, many design issues such as
noise, gain, linearity has been critical issues and they
are yet to be solved.
The design of mixer is one of the most important
steps for high-performance DCR because it involves theissue of flicker (1/f) noise and conversion gain
simultaneously. CMOS transistors suffer from high 1/f
noise which is inversely proportional to the device area.
So, minimizing 1/f noise while achieving high gain
without sacrificing linearity for high performance DCR
is one of the critical issues. Because of the conversion
loss in passive mixers, active mixers are usually
preferred in DCR. Among the active mixtures, doublebalanced mixers based on the Gilbert cell structure has
been widely studied and employed in wirelesstransceivers.
In this research, we have designed one-chip RF frontend which is composed of LNA, down conversion
mixer (DCM), voltage-controlled oscillator (VCO) and(impedance and noise) on-chip matching circuits for
WLAN applications (IEEE802.11b). A method to
reduce noise figure of DCM and to increase conversion
gain without sacrificing linearity has been proposed.
Furthermore, a new-type of VCO that employs on-chip

CPW line resonators has been proposed. Finally, onechip of the designed RF front-end was fabricated on
TSMC BiCMOS SiGe 0.35 µm 1-poly 3-metals
technology and measured.
2. SYSTEM ARCHITECHTURE AND DESIGN OF
EACH COMPONENTS
Fig. 1 shows the block diagram of single chip directconversion transceiver, which is composed of diodeswitch, LNA, power amplifier (PA), DCM, and upconversion mixer (UCM). In the figure, LNA and PA
are with input and output matching circuits. The design
value of the input impedance and output impedance are50Ω for general purpose.
Matching & Filter Circuit

Present work
DCM

ANT
LNA

VCO
0

50Ω

180

SW
PA

UCM
1-ChipFig. 1. Block diagram of direct conversion transceiver.

∆l = −

Vcc

160.5+j580Ω

50Ω

To Mix_RF
CPW

Input matchingcircuit

RX_IN

Outputmatching circuit
K

CPW

Fig. 2. Schematic of LNA with on-chip matchingcircuits.
Z’L A Z’S
Z0

Compensation circuit
Amp.

(Z1, θ)

K0,1
A’

λ/4

2.1 Design of LNA with on-chip CPW matching circuits
Fig. 2 shows the schematic of the designed LNA withon-chip noise and impedance matching circuits. The
designed value of the Max gain of the LNA and noise
figure (NF) is 19 dB and less than 3dB (@2.45 GHz),
respectively. Each VCC and VDD of the 0.35µm BiCMOS
process is 3.3V.
The presented matching circuit is based on the theoryof the n-pole Chebyshev bandpass filter (BPF) [6]. The
BPF consists of distributed transmission lines and
impedance inverters (K-inverters, Ki,i+1). In usual
wireless LAN cards, impedance matching is usuallyrealized by off-chip bonding wires and sometimes onchip spiral inductors. Realization of matching circuits
using off-chip bonding wires is a difficult task because
it needs a trial and error process. On the other hand,conventional matching circuit using spiral inductors
occupies large on-chip space and it has also encountersself-resonance in microwave frequency band which
permits its use beyond that frequency.
Fig. 3 shows the equivalent circuit diagram of thepresented matching circuit. YL (=GL+jBL) is the input
admittance of the amplifier and ∆l is the line length inorder to compensate the jBL. Z1 and K0,1 are thecharacteristic impedance of the quarter wavelength line
and K inverter, respectively. The design parameters are
given by,GL -jBL∆lYL
YL ≡ GL + jBL

Fig. 3. Circuit model of the proposed matching circuit
using λ/4 transmission lines.

Z1 =

BL

ω0 C

,

π

w
,
4 g1 g 2GL

K 0,1 = w

Z 0 x1 ⎛π ⎞, ⎜ x1 = Z1 ⎟g 0 g1 ⎝
4 ⎠

⎫
⎪
⎪
⎪
⎪
⎬
⎪
⎪
⎪
⎪⎭

(1)

where, C is the capacitance per unit length of thetransmission line, and w and gi are the normalized
bandwidth and normalized filter element, respectively[6]. The reactance slope parameter (x1) is for the series
resonance circuit. The design parameters of the CPW
matching circuit are f0=2.45 GHz and w=100 MHz,
which is used as an IEEE 802.11b application.
2.2 Design of Low Noise and High Gain DCM
In DCR architecture, mixer is the main contributor ofnoise and the overall performance of the receiver ishighly affected by the noise performance of mixer. The
design of mixer involves the issue of flicker (1/f) noiseand conversion gain simultaneously. In this research, ahighly efficient method to decrease noise factor of amixer and to increase its conversion gain and linearity,
simultaneously is proposed, which will be discussed
here after. The 1/f component of the output noise
current is given as follows [14]:(2)( STLO )

2K f

(3)

Wef Lef C ox f

Where T is the LO period, S is the slope of LO signal
at switching instant, and I is the bias current of eachpair. In a commutating mixer where a large LO
amplitude is applied, the low-frequency noise of theswitches is resulted. According to Eq. (2), one way oflowering a mixer flicker noise is reducing the width of
the noise pulses. This requires the increasing the slopeof the LO signal normalized to its frequency [S.T], or
reducing the flicker noise component of the switchingtransistors (vn). The latter is not a good solution because
it requires the increasing size of the switches [Wef in Eq.
3]. If Wef is increased, it increases the higher parasitic
capacitance at the common source of the switches,
resulting in 1/f noise indirect translation to the output.
On the other hand, LO voltage amplitude is limited tothe supply voltage of the signal generator, andincreasing its slope at high frequency directly relates tohigher power consumption in LO buffers. Furthermore,
1/f noise is improved if the height of the noise pulses isdecreased. This could be only accomplished by
reducing the bias current of the mixer switches as theheight of the noise pulses is equal to 2I.
One of the earliest approaches to reduce the height of
the noise pulses is to employ the current injection
method at the source terminal of the switchingtransistors. However, this technique suffers from a few
important drawbacks. First, reducing the bias current of
the switches raises the impedance seen at their source(1/gms), allowing more RF current to be shunted by theparasitic capacitance at that node. This reduces themixer bandwidth and degrades linearity. Later, current
reuse-scheme is employed to reduce the white noise
figure. In this method, the ratio of the injected fixedcurrent to the bias current is usually kept small,
improving the switches 1/f noise by only a small
amount.
In [15], dynamic current injection method has been
proposed to inject a dynamic current equal to the bias
current of each pair at only the switching event. This issufficient to eliminate the output flicker noise
component completely. In this technique, a dynamic
current is injected through a control circuit as shown in
Fig. 4 only at the switching event. This effectively
reduces the height of the noise pulses at the output tozero and eliminates the flicker noise component.
Otherwise no current is injected and the mixer operates
normally resulting improvement in power consumption
significantly compared to its counterpart such as static

current injection method. However, one of thedisadvantages of this method is RF signal loss throughthe control circuits. This problem is overcome byinserting 4 inductors at switching transistors as shownin Fig. 4 and simulated results in Fig. 5 where thesimulated performance of the proposed mixer isimproved by about 5-6 dB. Noise figure is reduced andconversion gain is improved by equal amount. By
introducing four resonating inductors in the switchingstage, it also reduces the RF current flowing to thecontrol circuit, thus higher conversion gain is possible
at resonant condition.
Vdd

LOLO+

LO+

Added L (1.2 nH)

Vp

Dynamic current
injection [2]
RF-

RF+

Fig. 4. Schematic of proposed double-balanced mixers
using dynamic current injection method and four tuned
inductors at switching stage transistors.
Conversion Gain [ dB ]vn =( 4 I vn )1
122
Proposed DBM

More than 5 dB

8Conventional DBM
4

0
-30

-25

-20

-15

-10

Input Power [ dBm ](a) Conversion gain improvement
30

Conventional DBM

Noise Figure [ dB ]i0, n =

25

More than 5 dB

20

Proposed
15
-30

-25

-20

-15

-10

Input Power [ dBm ](b) Noise performance improvement
Fig. 5. Simulated performance improvement of the
proposed mixture.

2.3 Design of VCO using On-Chip CPW Resonator
A conventional VCO consists of a resonator which isrealized by spiral inductors and MIM capacitors (LCresonators) [16]. In this paper, the resonator portion is
replaced by on-chip CPW line resonator. Fig. 6 shows
structure of CPW resonator on LSI process, where thewidth of signal line is 5 µm and gap between the line
and ground plane is 5 µm. The length of the resonator is
6700 µm so that its resonant frequency is to be 2.4 GHz
under the given parameters of LSI process.

Fig. 8. One of the advantages of using CPW resonators
is that it takes 30% less on-chip space than that of aconventional VCO using LC resonator.
The comparison of simulated parameters between the
VCOs using CPW resonator and LC resonator is shownin Table 1. From the table, it is noted that the VCO
using CPW resonator has advantages in terms of chiparea and frequency turning range (FTR). On the other
hand, it has the adverse performance in terms of
consumption power and phase noise.
Table 1. Comparison of simulated parameters between
two VCOs. [FTR=frequency tuning range]

Close up
GroundSignalGroundFig. 6. Structure of CPW resonator on LSI process.

LC resonator

CPW
resonator

1.6

1.0

2.456

2.789

10

24

15.5

44.6

-126

-118

2.2x10-7

1.8x10-7

Amplitude[V]
Centre[GHz]
FTR [%]LC resonator

CPW resonator

Consumption
power [mW]Phase noise[dBc/Hz]
Area

2

[m ]

Metal3CPW PAD
(50Ω)

100µm

(a)
(b)
Fig. 7. Schematics of designed VCO using (a) LC
resonator (b) proposed CPW resonator.
20µm

CPW resonator

5µmFig. 9. Chip photo of conductor backed CPW.
0100[μｍ]Spiral Inductor(a)(b)
Fig. 8. Layout of the designed VCO using (a) LC
resonator (b) proposed CPW resonator.
Fig. 7 shows the schematics of the designed VCO. In
the design, widely used CMOS cross-coupled structureis used. In Fig. 7(a), the VCO using LC resonator isshown and that of using the proposed CPW resonator isshown in Fig. 7(b). Layouts of both VCO are shown in-5|S11|, |S21| (dB)

100 [μｍ]

S21

-10
-15

S11

-20
-25

2

4
6
Frequency (GHz)EM-Sim.
Exp.
8

10

Fig. 10. Frequency responses of the CPW meanderline.

3. FABRICATED CHIP AND MEASUREDRESULTS
3.1 CPW Line Structure and Losses
K-inverter is fabricated using shunt meander
structure so that they can be used to exploit the vacant
space inside the chip. Fig. 9 shows a photo of CPW line
circuits. The conductance of the metal is 4.1x107 S/m.
The signal width and the interval between the slots of
the CPW transmission line are 5 µm and 15 µm,
respectively. Fig. 10 shows the comparison of thefrequency responses of the K-inverter. Insertion loss(S21) of the EM-simulated result is almost in agreementwith that of the experimental result.
Fig. 11 shows the microphotograph of a single-chip
LNA and DCM for 2.4 GHz-band wireless LAN
applications, and the proposed impedance-matchingcircuit interconnecting between them and at the input of
the LNA.
Unused K-inverters, and
CPW lines

is about 47 Ω compared with 50 Ω of the designed
value (@2.45 GHz). Similarly, the measured imaginary
part is about –9 Ω compared to the +2 Ω of thedesigned value.

Fig. 13. Chip photo of proposed mixer connected withproposed VCO using CPW resonator. (Chip size =1.3mm x 1.7 mm including the matching circuits andbiasing circuits at RF terminal).
YOKOGAWA: 2006/07/28 20:28:17

Voltage [ mV ]100 ns/div

Mixer

Inputmatchingcircuit

LNA
Matching circuit between
LNA and mixer

Fig. 11. Microphotograph of SiGe BiCMOS reciever
front-end. (Chip size: 2mm x 3.5 mm)

Input Impedance [ Ohm]

80

Real parts60

P-P(C1)
Freq(C1)

199 mV
9.98 MHz(C1)

64.5756mVTime [ ns ]Fig. 14. Output of mixer sinusoidal waveformconfirming the operation of the mixer measured bydigital oscilloscope through a high-impedance probe (IFfrequency =10 MHz).

Simulation
Measured

40
20
0
-20
Imaginary parts

-40
-60
-80

1

2

3

4

Fig. 12. Input impedance of the designed chip.

Fig. 15. An example of VCO output measured byspectrum analyzer.

Fig. 12 shows the comparison of the measured andsimulation results of the input impedance of thefabricated chip. In the figure, the measured results arein good agreement with the designed value. For
example, the measured real part of the input impedanceFig. 13 shows a chip photo of proposed down
conversion mixers and its measured results in time
domain is shown in Fig. 14. This shows the operation of
the fabricated mixer. Similarly, Fig. 15 shows themeasured results of proposed VCO which confirms ofFrequency [ GHz ]its operation. The detail measurement results will bepresented in future study.
4. CONCLUSION
RF front-end which consists of integrated on-chip
CPW line impedance and noise matching circuits, LNA,
down conversion mixer and VCO is designed andfabricated on TSMC 0.35 µm SiGe BiCMOS process.
An effective method to reduce noise figure andsimultaneously to increase conversion gain of the mixer
without sacrificing linearity and consumption powerhas been proposed. In order to reduce the chip size foron-chip realization, on-chip CPW lines has been
employed to realize on-chip impedance and noise
matching circuits which saves 30-40% chip area thanthose using the spiral inductors. Some of thepreliminary measured results of each element of thechip have been presented. Improvement of phase noiseand consumption power of VCO is one the mostimportant issues which is to be solved in near future.
ACKNOWLDGEMENT
This work is supported by VLSI Design and
Education Center (VDEC), The University of Tokyo
with the collaboration with Agilent Technologies andCadence Corporation.
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