IEICE TRANS. ELECTRON., VOL.E89–C, NO.12 DECEMBER 2006

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PAPER

Special Section on Emerging Microwave Techniques

Design and Verification of On-Chip Impedance-Matching Circuit
Using Transmission-Line Theory for 2.4 GHz-Band WirelessReceiver Front-End
Haruichi KANAYA† , Ramesh K. POKHAREL†a) , Members, Fuminori KOGA† , Nonmember,and Keiji YOSHIDA† , Member

SUMMARY
Recently, spiral inductors have widely been used insteadof resistors in the design of matching circuits to enhance the thermal
noise performance of a wireless transceiver. However, such elements usually have low quality factor (Q) and may encounter the self-resonance inmicrowave-frequency band which permits its use in higher frequencies,
and on the other hand, they occupy the large on-chip space. This paper
presents a new design theory for the impedance-matching circuits for asingle-chip SiGe BiCMOS receiver front-end for 2.4 GHz-band wireless
LAN (IEEE 802.11b). The presented matching circuits are composed of
conductor-backed coplanar waveguide (CPW) meander-line resonators and
impedance (K) inverter. The prototype front-end receiver is designed, fabricated and tested. A few of the measured results to verify the design theory
are presented.
key words: CPW line, impedance-matching circuit, 2.4 GHz-band wirelessLAN, λ /4 resonator, transmission-line theory

1.

Introduction

The explosive increase in the number of wireless communication equipments in the recent years enables the researchers
to pay considerable eﬀorts in the characteristics improvement of a wireless receiver front-end. In the mobile communication system, RF-CMOS LSI is a key technology inorder to make size reduction and cost performance [1]–[3].
Although the performance of the CMOS chip has a limitation in the high frequency and high-speed applications, SiGe
bipolar technology has a better frequency performance compared to CMOS at relatively low price compared to GaAs
device [4], [5].
In the RF section of LSI chip, an impedance-matchingcircuit is necessary for interconnecting each part of thefront-end such as low-noise amplifier (LNA), power amplifier (PA), duplexer, mixers, and so on, and lumped circuit elements are usually used. Among them, spiral inductors andMIM capacitors are preferred instead of resistors to enhance
the thermal noise performance. However, they cannot be
used at high frequency range because of the self-resonanceand stray impedances, and on the other hand, they also occupy large on-chip space.
Distributed elements made of transmission lines are
particularly eﬀective when their size becomes smaller, as
Manuscript received March 4, 2006.
Manuscript revised June 28, 2006.
†
The authors are with Kyushu University, Fukuoka-shi, 8190395 Japan.
a) E-mail: pokharel@ed.kyushu-u.ac.jp
DOI: 10.1093/ietele/e89–c.12.1888

the frequency in use increases. Among the transmission
lines, coplanar waveguide (CPW) line is easy to fabricate
by the LSI technology compared to its counter part such as
microstrip or strip lines because the signal line and groundplane exist on the same plane [6].
The applications of the distributed elements made oftransmission lines were reported in the CMOS or BiCMOS
RF-LSI chip [6]–[9]. The CPW lines was exploited as an
inductor and used to design a conventional-type matchingcircuit for a LNA [6] in microwave-band frequency, andthey were also used as an inductor in GaAs based monolithic microwave integrated circuit (MMIC) for millimeterwave devices [7]. However, the application of CPW lines as
an inductor takes larger on-chip space than a conventional
spiral inductor [6]. Furthermore, CPW structures are implemented as phase controllers [8] and as open or short stubs
for impedance-matching circuit for SiGe LSI chip in the
Ka-band [9]. Some of the present authors have also implemented the CPW superconducting impedance-matching circuit for interconnecting an antenna and duplexer [10], [11].
In this paper, the design theory of the CPW impedancematching circuit using the impedance (K) inverter andquarter-wavelength (λ/4) meanderline resonator for a singlechip SiGe BiCMOS receiver front-end for 2.4 GHz wireless LAN applications (IEEE 802.11b) is presented using acommercial electromagnetic (EM) and SPICE co-simulator(ADS2004A; Agilent Technologies). The receiver front-end
consists of a LNA and down-conversion mixer (DCM) thatuses double-balanced topology. The presented theory is verified by comparing the simulation with the results measured
on a RF-LSI chip fabricated in TSMC 0.35 µm one-poly
three-metal BiCMOS technology.
2.

Design of LNA and DCM in 0.35 µm BiCMOS Process

2.1 Design of LNA and DCM with On-Chip ImpedanceMatching Circuits
Figure 1 shows the block diagram of single chip transmitter(T x) and receiver (Rx) amplifiers, which are composed ofdiode switch, LNA and PA with input and output matchingcircuits. The designed input and output impedances are 50 Ω
for general purpose. We can combine the input and output

c 2006 The Institute of Electronics, Information and Communication Engineers
Copyright KANAYA et al.: DESIGN AND VERIFICATION OF ON-CHIP IMPEDANCE-MATCHING CIRCUIT

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Fig. 3Fig. 1

Circuit model of one-pole BPF using K-inverter.

Block diagram of single chip direct-conversion transceiver.
Fig. 4Equivalent circuit model of the filter of Fig. 2 at the center part.

2.2 Design Theory of Matching Circuit(a) Schematic of the designed LNA.

(b) Schematic of the designed DCM.
Fig. 2

Schematic of the designed LNA and DCM.

matching circuits and bandpass filter (BPF) together.
Figure 2 shows the schematics of the designed LNA
and DCM. The DCM employs the double-balanced topology. A passive transformer is used as balun at the IF outputof the mixer in the design. The designed value of the Max
gain of the LNA and noise figure (NF) is 19 dB and lessthan 3 dB (@2.45 GHz) respectively. Similarly, the target
conversion gain, NF, IF of the design mixer are 12 dB, lessthan 6 dB, and 15 MHz respectively. Each VCC and VDD of
the 0.35 µm BiCMOS process is 3.3 V.

In the present work, main focus is given in the design andverification of the on-chip impedance-matching circuit for areceiver front-end using the transmission-line theory.
The present matching circuit is based on the theory of
the n-pole Chebyshev bandpass filter (BPF) [12]. The BPF
consists of distributed transmission lines and impedance inverters (K inverters, Ki,i+1 ). In usual wireless LAN cards,
an oﬀ-chip dielectric filter is usually used as an external
BPF and impedance matching is usually realized by oﬀ-chipbonding wires and sometimes on-chip spiral inductors. Realization of matching circuits using oﬀ-chip bonding wires
is a diﬃcult task because it needs a trial and error process. On the other hand, as also previously explained, conventional matching circuit using spiral inductors occupies
large on-chip space and it also encounters self-resonancein microwave frequency band which permits its use beyond
that frequency. Therefore, this paper employs a one-stage
BPF as a matching circuit which can be realized inside achip. The design formulae for a one-stage BPF using theimpedance inverters (K inverters) shown in Fig. 3 are,

√
Z0 x1
(1)
K0,1 = w
g0 g1

√
x1 Z0
(2)
K1,2 = w
g1 g2


ω
ω0
−
X1 = x1(3)ω0ωHere, Z0 is the characteristic impedance, X1 is the reactance in the series resonator with a reactance slope parameter x1 , w is the normalized bandwidth (ω2 − ω1 )/ω0 , and gi
is the filter parameter [12].
The equivalent circuit of the filter in Fig. 3 at the center
part is shown in Fig. 4. Hence, the resistance ratio and thequality-factor (Q)value are given by,
RL
Z0 2
g0
Z1 G L =
 =
2
RS
g2
K0,1

(4)

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Fig. 6Equivalent circuit model seen from A-A .

Fig. 5 Circuit model of the proposed matching circuit using λ/4 transmission line.

Q=x1
g0 g1 g2
=w (g0 + g2 )
g0
1+
g2

x1
Z0


 =
2
RS + RL
K0,1(5)

Next, we will explain a miniaturization design method
for matching circuit employing a λ/4 transmission line. Figure 5 shows a new distributed impedance matching circuit
proposed by the present authors using a K-inverter and a λ/4transmission line. Here YL is the input admittance of thereceiver front-end (say, of LNA) and is given by,
1≡ G L + jBL
ZL
RL
XL, BL = − 2
GL = 22
RL + XLRL + XL2
YL =

(6)

(7)

Furthermore, in Fig. 5, if ZL is the impedance of the line
looking from A-A of the K-inverter and Z s is impedancelooking from λ/4 line towards K-inverter, then ZL and RS
can be expressed in terms of the characteristics impedanceZ1 and the electrical length θ of the λ/4 transmission line asfollows:
ZL = Z12G L + jX1 ≡ RL + jXLwhere,



X1 = −Z1 cot θ  x1

(8)


ω
ω0
−
;
ω0
ω


∂X 
= π4 Z1 : the reactance slope parameter of thex1 = ω20 ∂ωω=ω0series resonant circuit at ω = ω0 ;RL = Z12G L ;
RS =

2
K0,1

Z0

To make this structure identical to the 1-pole BPF, theresonant conditions can be found by substituting above values in Eqs. (4) and (5), respectively as,
RL
Z0 2
g0
Z1 G L =
 =
2
RS
g2
K0,1

In the compensation circuit, ∆l is determined by Eq. (7)in such a way that the susceptance BL of the LNA is canceledout. Here, C (F/m) is the capacitance per unit length of the
distributed transmission line.
ZL2 XLBL=∆l = −
ω0C ω0C(R2L + XL2 )Fig. 7 Smith chart representation of the circuit model of the presented
matching circuit using λ/4 line and K-inverter.

.

It is assumed in Eq. (8) that the input impedance of
the LNA is suﬃciently larger than Z0 so that |YL |  Y0 .
Hence, the equivalent circuit at A-A can be modified to thatin Fig. 6.

Q=

x1
x1
g0 g1 g2
Z0
=
= 2 
RS + RLw (g0 + g2 )
g0
K0,1
1+
g2

(9)
(10)

Here, please note that Eqs. (4), (5) and (9) and (10) are
identical to each other, respectively. When these two equations are solved for K0,1 and Z1 , we can eventually obtain
the design formulae for the proposed matching circuit as follows:
π w
Z1 =
(11)
4 g1 g2G L


√
Z0 x1
π 
K0,1 = w,
x1 = Z1
(12)
g0 g1
4
π
(13)
x1 = Z1
4
Therefore, impedance matching is possible with thecharacteristic impedance (Z1 ) of the λ/4 transmission line
and K0,1 and on the other hand, it can realize BPF characteristics simultaneously. Also, it is found from Eq. (12) thatthe desired bandwidth can be obtained by varying w. If noise
matching is used, the above can also be applied by letting YL∗= Yopt(Yopt is the admittance minimizing the noise).
The physical interpretation of the design theory for presented matching circuit in Smith chart is illustrated in Fig. 7.
For example, ZL∗ is the conjugate of input impedance of thereceiver front-end (ZL = 1/YL ) (say of LNA) and its positionis shown by point x in the Smith chart. The insertion of the
λ/4-transmission line converts the high impedance to very
low, and its position is represented by x in the Smith chart.
By using negative capacitance (−C), now its position will

KANAYA et al.: DESIGN AND VERIFICATION OF ON-CHIP IMPEDANCE-MATCHING CIRCUIT

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be shifted to new position, y and again due to the K-inverter,
the 50 Ω-matching can be designed. A compensation circuit to achieve −C is realized by making the length of thetransmission line slightly shorter than λ/4.
In this paper, the input impedance of the receiver frontend is very high (160.5+j580 Ω), so matching circuit is designed using K-inverter. Due to this reason, the design theory using J-inverter is only introduced here, and detail study
has been left for the future.
Furthermore, when the input impedance of the amplifier (ZL = RL + jXL ) is smaller than Z0 , the design parameters
using the J-inverter can be derived in the similar way and are
given by,⎧⎪∆ = − ωX0LL
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨ Y1 = 1 = π w
,
(14)
Z1
4 g1 g2 RL
⎪
⎪
⎪
⎪
⎪
⎪
√
⎪
Y
b
π
⎪
⎩ J0,1 = w g0g1 ,b1 = 4 Y1
0 1

Fig. 8

Sectional view of the used 0.35 µm BiCMOS process.

where, L is the inductance per unit length of the transmission line, and w and gi are the normalized bandwidth andnormalized filter element, respectively. ∆ is the line length
in order to compensate the jXL . The susceptance (Y1 ) andthe reactance slope parameter (b1 ) are for the shunt resonant
circuit [12].
3.

Design of Passive Elements and Accuracy of CoSimulation of SPICE-Type and EM-Simulator

In this paper, we use one of the most widely used tools
known as Advanced Design System (ADS2004A, Agilent
Technologies) in designing of CMOS or BiCMOS circuits
and Momentum (Agilent Technologies) for electromagnetic
characterization of passive elements. The ADS is a SPICEtype circuit simulator and Momentum is an electromagnetic simulator based on the method of moments. The CoSimulation option uses both circuit-type simulation and EM
simulation simultaneously to provide an interesting option
to design and simulate CMOS or BiCMOS circuits with EM
characterization of passive devices in LSI chip.
In order to evaluate the accuracy of EM simulator,
we fabricate the on-chip spiral inductor, and compare the
SPICE models and experimental results with EM simulation
results in this Section.
3.1 Design of Spiral Inductor
We use the 0.35 µm BiCMOS process in TSMC, which has
1 Poly and 3 metal structures and the thickness of the top
metal is 3.1 µm as shown in Fig. 8. The conductance of themetal and εr of the SiO2 are 4.1 × 107 S/m and 4.1, respectively. Figure 9 shows the layout and chip photograph of
the EM simulation of the spiral inductor with guard ring and
CPW pads (Total IND), and open dummy. The open dummyis necessary to estimate the value of the inductor to be discussed latter. Please note that a small stub at the center CPW
pad (dummy pad of right side) in Fig. 9(a) is to compensate

Fig. 9 EM simulation layouts (a) and photographs (b) of the spiral inductor and open dummy.

the interconnect between metal 2 terminal of the spiral inductor and the pad. The line width and spacing of the spiral inductor is 10 µm each other. The CPW pad is 100 µm
square and designed in such as way that its characteristic
impedance is to be 50 Ω. The microwave characteristics aremeasured by using air coplanar probe (Cascade Microtech,
GSG150) and vector network analyzer (HP, HP8722C).
The measured data must be de-embedded in order toremove the parasitic eﬀects of interconnects, pads and contacts surrounding the device [13]. At first, we measure
S -parameters of total IND and open dummy. Next, S parameters are transformed into Y-parameter, and removed
the parallel circuits and parasitic elements as follows[Y]spiral = [Y]total − [Y]dummy(15)

Finally, [Y]spiral is converted to Z-parameters, and inductances (L) and quality factors (Q) are calculated as follows

L = Im(Zin )/(2π f ).
(16)
Q = Im(Zin )/Re(Zin − 50)
Figure 10 shows the frequency dependences of inductance and Q-value of the T =5.5 spiral inductor, where “T ” is

IEICE TRANS. ELECTRON., VOL.E89–C, NO.12 DECEMBER 2006

1892(a) L of smaller spiral inductor (T =5.5)

Fig. 11 Chip photo of the conductor backed CPW transmission line.
(line length =13 mm)(b) Q-value of smaller spiral inductor (T =5.5)
Fig. 10Frequency dependence of L and Q-value of the spiral inductors.
Fig. 12Chip photo of meander inductor of the K-inverter.

the turn number of the spiral inductor. In the figure, “Model”
means that of the SPICE models. The EM simulation results are consistent with the experimental results than thatof the SPICE models. This verifies the importance of cosimulation during LSI design using the SPICE tools in order to model the spiral inductors. Therefore, co-simulation
technique is used to model the spiral inductors in BiCMOS
circuit throughout this paper. As evidenced in Fig. 10, themodel spiral inductor (T =5.5) has a self-resonance around
5.5 GHz, and does not work as an inductor beyond that frequency.
3.2 Design of Transmission Lines
The components of a CPW matching circuit are designed
and simulated by the EM simulator (Momentum, Agilent
technologies) in this section. Please note that the presented
matching circuit is composed of K-inverter and λ/4 resonator, both of them are realized on CPW meander structures. The design parameters of the matching circuit are
f0 =2.45 GHz and w=4% (100 MHz/2.45 GHz), which isbased on the IEEE 802.11b Standards. In order to avoid
the loss in the Si substrate, we covered the lowest metal(metal1) in all area of the CPW structure, namely conductor
backed CPW. Figure 11 shows the chip photo of the conductor backed CPW resonator with CPW PAD. The signal

Fig. 13line.

Frequency responses of the conductor-backed CPW meander

width and the interval between the slots of the CPW transmission line are 5 µm and 15 µm, respectively so that its
characteristic impedance is to be 50 Ω. For size reduction,
the λ/4 line (line length = 13 mm) is bended into meander
structure. Similarly, Fig. 12 shows the chip photo of the Kinverter with CPW PAD.
Figure 13 shows the comparison of the frequency responses of λ/4 conductor-backed CPW line which is con-

KANAYA et al.: DESIGN AND VERIFICATION OF ON-CHIP IMPEDANCE-MATCHING CIRCUIT

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Fig. 14Frequency dependence of the inductance (L) of the K inverter.

Fig. 15 Microphotograph of SiGe BiCMOS receiver front-end. (Chipsize: 2 mm × 3.5 mm)

structed on meander structure. Insertion loss (S 21 ) of the
EM-simulated result is almost in agreement with that of theexperimental result. Figure 14 shows the frequency dependence of the inductance (L) of the K-inverter, calculated
from the impedance matrix. Experimental value is almostin agreement with that of the EM-simulation result. This
ensures the validity of EM simulation in designing the distributed circuits using CPW transmission lines.
4.

Fabricated Chip and Measured Results

Figure 15 shows the microphotograph of a single-chip SiGe
BiCMOS LNA and DCM for 2.4 GHz-band wireless LAN
applications, and the proposed impedance-matching circuit
interconnecting between them and at the input of the LNA.
The chip is fabricated in TSMC0.35 µm one-poly threemetal BiCMOS technology.
The input and output pads have coplanar configurations
so that characteristic impedances are 50 Ω. Spiral inductors are used to apply DC power into the transistors and theLO (Local) ports of the mixer. There is a dummy metalin the center of the chip in order to suppress the RF noise.
There are also unused K-inverters and CPW lines which occupies more than 1/4th space in the fabricated chip (chipsize: 2 mm × 3.5 mm).
Figure 16 shows the simulation results in the case ofwith and without the matching circuit between the LNA and
DCM. The results confirm that the conversion gain of themixer has been increased due to the matching circuit by theamount of voltage gain of the LNA in linear region. Please
note that designed voltage gain of the LNA and the conversion gain of the DCM are 19 dB and 12 dB, respectively.
About 1.5 dB-loss can be attributed to the loss in CPW lines
at 2.45 GHz as noted from Fig. 13.
Figure 17 shows the comparison of the measured andsimulation results of the input impedance of the fabricatedchip. In the figure, the measured results are in good agreement with the designed value. For example, the measured
real part of the input impedance is about 47 Ω comparedwith 50 Ω of the designed value (@2.45 GHz). Similarly,
the measured imaginary part is about −9 Ω compared to theFig. 16 Simulation results of the conversion gain of the mixer with andwithout the matching circuit between LNA and mixer. (P RF represents the
input power at RF port and Conv gain is the conversion gain of the mixer).

Fig. 17

Input impedance of the fabricated chip.

+2 Ω of the designed value. This ensures that the validity ofthe presented method in designing the on-chip impedancematching circuit using λ/4 CPW line and K-inverter.
Figure 18 shows the comparison of on-chip area occupied by the matching circuit designed using spiral inductors based on the conventional method and the presented
theory, respectively. In the comparison, the size of MIM
capacitor which is a part of the matching circuit and also
work as a D.C. block capacitor, are approximately the same,

IEICE TRANS. ELECTRON., VOL.E89–C, NO.12 DECEMBER 2006

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to the lumped element matching circuit.
The accuracy of co-simulation technology in designing
the passive circuits in LSI chip is also discussed by comparing the simulation results with the experiment, and it showsthat EM simulation is superior to the SPICE models of the
spiral inductor.
When we design the receiver front-end such as LNA or
mixer, the main target is not only to obtain maximum gain,
but also maximum eﬃciency, minimum distortion, minimum noise figure, and so on, which depend on the specifications on demand. These optimum matching conditions
are also realized by using the presented method instead ofthe lumped circuit element.
(a)

(b)

Fig. 18 Comparison of on-chip area occupied by matching circuit (a)Layout of spiral inductors (total=13.8 nH) required for matching designed by conventional theory. (size=370 µm × 790 µm) (b) Layout of λ/4
CPW line and K-inverter for matching designed by the presented theory.
(size=240 µm × 780 µm)

and therefore ignored in the size comparison. In Fig. 18(a),the layout of the spiral inductors required for the matchingof the designed receiver front-end is shown whose size is
370 µm × 790 µm in the TSMC 0.35 µm BiCMOS foundry.
In the figure, two spiral inductors were used to realize therequired L and there should be at least 4 µm space left between the inductor’s active areas according to the foundry’s
design rules. For the same purpose, the required space takenby the matching circuit by the presented theory is shownin Fig. 18(b) where the size is only 240 µm × 780 µm, thus
saving the valuable chip area about by 30%. If the operating frequency increases, this ratio becomes more eﬀective.
However, comparison of the presented method with thoseusing by a combination of a short transmission line for phaseshift and a quarter-wavelength transformer has not been investigated yet and will be taken as one of the priority works
in the near future.
5.

Conclusions

Design methodology of impedance-matching circuit for asingle chip SiGe BiCMOS receiver front-end which is composed of λ/4 CPW meander resonators and K-inverter is presented and verified by comparing the simulation results withmeasured results on a designed chip fabricated in TSMC
0.35 µm SiGe BiCMOS technology. The CPW lines are realized by meander structures so that they can be fabricatedinside a chip and their shape can be adjusted in order to exploit the vacant space on the substrate eﬀectively. It takes
less space than that of the spiral inductors. A rough comparison shows that the matching circuit designed by the proposed method takes about 30% less space than that of the
spiral inductors (@2.45 GHz). If the operating frequency increases, this ratio becomes more eﬀective. Another beautyof the transmission-line based matching circuit is the freedom of selection of the higher bandwidth, which is superior

Acknowledgement
This work was partly supported by a Grant-in-Aid for Encouragement of Young Scientists (B) from the Japan Society
for the Promotion of Science (JSPS). This work was partly
supported by VLSI Design and Education Center (VDEC),
the University of Tokyo in collaboration with CADENCE
Corporation. This work was partly in collaboration with
Fukuoka Laboratory for Emerging and Enabling Technology of SoC (FLEETS).
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Haruichi Kanaya
was born in Yamaguchi,
Japan, in 1967. He received the B.S. (Physics)
degree from Yamaguchi University in 1990, andthe M.E. (Applied Physics) and D.E. degrees
from Kyushu University in 1992 and 1994, respectively. In 1994, he became a Research Fellow (PD) of the Japan Society for the Promotion of Science. In 1998, he was a visiting
scholar at the Massachusetts Institute of Technology (MIT), USA. He is currently engaged in
the study and design of RF CMOS System LSI
and superconducting microwave devices, as an Associate Professor in the
Department of Electronics, Graduate School of Information Science andElectrical Engineering, and also System LSI Research center, Kyushu University. Dr. Kanaya is a member of the Institute of Electrical and Electronics Engineers (IEEE).

Ramesh K. Pokharel
received the B.S. degree from Aligarh Muslim University, Aligarh,
India in 1994 and the M.E. and Doctorate degrees from the University of Tokyo, Japan in2000 and 2003, respectively all in electrical engineering. In 1994, he joined Institute of Engineering, Tribhuwan University, Nepal as a research associate. In 1995, he moved to Nepal
Telecommunications Corporation. He had been
a post-doctoral research fellow with the Department of Electrical Engineering and Electronics,
Aoyama Gakuin University, Japan from April 2003 to March 2005. Since
April 2005, he has been a research associate with the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University, Fukuoka, Japan. His current research interests
include the passive filter components, resonators and development of RF
CMOS system LSI. He is a member of the IEEE and IEE of Japan (IEEJ).
Dr. Pokharel was a recipient of the Monbu-Kagakusho Scholarship of theJapanese Government (1997–2003) and an excellent research presentation
award from the University of Tokyo in 2003.

Fuminori Koga
was born in Fukuoka,
Japan, in 1981. He received the B.E. and M.E.
degrees from Kyushu University in 2004 and2006, respectively all in electronic engineering.
Since April 2006, he has been engaged in the
study and design of RF CMOS System LSI with
ROHM Corporation.

Keiji Yoshida
was born in Fukuoka, Japan,
in 1948. He received the B.E., M.E. and
Dr. Eng. degrees from Kyushu University in
1971, 1973 and 1978, respectively. He is currently engaged in the study of applications of superconducting thin films to microwave and optical devices and design of RF-LSI chips for
SoC, as a Professor in the Department of Electronics, Graduate School of Information Scienceand Electrical Engineering, Kyushu University.
Dr. Yoshida is a member of the Institute of Electrical and Electronics Engineers (IEEE) and the Japan Society of Applied
Physics.