IF013
RFIT2007-IEEE International Workshop on Radio-Frequency Integration Technology, Dec. 9-11, 2007, Singapore

Design of 1.1 GHz Highly Linear Digitally-Controlled Ring
Oscillator with Wide Tuning Range
A. Tomar, R. K. Pokharel, O. Nizhnik, H. Kanaya, and K. Yoshida
Graduate School of Information Science and Electrical Engineering
Kyushu University, Fukuoka 819-0395, Japan
tween inverter delay stages and vary the value of theresistance of the transmission gate with the control
voltage applied to the transmission gate which has
drawback of frequency saturation for higher voltages sothat it provides low control voltage range. In Ref. [4],[5], digital control but asymmetrical stages were usedwhich reduces the output voltage swing that makes thecircuit sensitive to the phase noise. In Ref. [6], parallel
resistors were used in transmission gate and control theresistance by changing digital control. It provides highload resistances means more power dissipation. And
also resistance becomes saturated at high control logic
so that linearity worsens.
This paper proposes a new architecture for 8-bit digitally-controlled ring oscillator. This architecture provides symmetrical load, high linearity and very large
output voltage swing which overcomes the problem ofRef. [4], [5]. The output frequency of the DCO is controlled by the varying the driving current according to
the input control bits.

Abstract: This paper presents a simple architecture for
8-bit digital controlled oscillator (DCO) on 3-stages ring
topology in TSMC 0.35um CMOS technology. A new
schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low
power consumption as compared to conventional one. The
control digit changes the driving current that provides
large tuning range from 333 MHz to 1472 MHz with very
good linearity. The output voltage swing is constant andabove 3volt (>90% of the supply voltage i.e. 3.3V). The
presented circuit shows the fast response to the output
frequency transition and this takes less than one clock period and without showing any ringing or damping during
frequency transition. The proposed DCO has simulated
phase noise of –106dBc/Hz @1Mhz and 63.4 mw power
consumption at 1.1 GHz central frequency.
Index Terms — ring oscillator, DCO, inverter, phasenoise, linearity.

I. INTRODUCTION
In recent years, CMOS technology is scaling down
resulting to a very low control voltage that leads to theavailability of only very steep slope [1], and this complicates the implementation of conventional RF circuitsin CMOS technology, often causes instability and theportability issues. Furthermore, low voltage and thinmetal interconnects which are achieved in a scaleddown CMOS process are advantageous to digital circuits but the same becomes disadvantages to RF circuits
due to reduced voltage headroom, low inductor’s quality factor, and reduced gate oxide reliability. Therefore,
RF circuits such as RF oscillators need to be realized
employing digitally controlled logics for future generation wireless technology.
In conventional wireless systems, two types of oscillators i.e. ring oscillator and LC-tank oscillator are often used to generate a local frequency in a phase-locked
loop (PLL) [2]. The former is often used in MHz frequency applications because of its compactness, as spiral inductors are usually not necessary in a ring topology. In GHz frequency applications, the later is usually
preferred because of its improved noise performanceand lower power consumption.
As a ring oscillator is more compact than LC-tank
oscillator, designing a ring oscillator for GHz frequency
applications is the main area of interest in this paper. In
Ref. [3], the architecture uses transmission gate be-

II. DESIGN OF CONVENTIONAL RING OSCILLATOR
A basic ring oscillator uses odd number of inverters.
An example of three-stages ring oscillator [2] is shownin Fig 1. Each inverter in the oscillator is used as a delay cell. The frequency of oscillation for identical cell isgiven by Equation (1).

f osc

1
2 N Td(1)

Where Td is the delay of each inverter cell and N isnumber of identical cell. From Equation (1), the period
or frequency of oscillation is varied either by changing
the number of inverter stages in the ring or varying the
propagation delay of inverter. The delay of each inverter cell is further expressed as,Td

C L .'V
Id(2)

Where CL is load capacitance, V is the output voltage
swing and Id is the driving current to the load. It isclearly noted from the Equation (2) that the frequency

1-4244-1308-7/07/$25.00 ©2007 IEEE82

of oscillation without changing number of stages can bevaried either by changing the load capacitance or driving current to the load. The propagation delay of inverter is proportional to Width to Length (W/L) ratio of
the transistor as increment in width increases the capacitance and decreases the resistance that makes time
constant equal and frequency remains constant. The
load capacitance (CL) at the output node of inverter canbe expressed by Equation (3) [7].
C L C gsM 3  C gsM 4  CdbM 1  CdbM 2(3)
 C gdM 1  C gdM 2  C w

Fig. 3 shows the tristate inverter circuit used in the
proposed DCO. The proposed tristate inverter uses fourtransistors whose numbers are equal to the conventional
one but differs in topology. In conventional inverters,
four inverters gate are connected in series.
In the proposed inverter, it has control input D that
controls the signal propagation from input to the output
through transistors M1 and M3 or M2 and M4 depending on the input level Low (0), High (1), respectively.
When D=0, the output will no longer connected to the
input and none of the transistors M3, M4 conducts. The
size of the transistors are selected to provide equal delay through both the paths. The W/L ratio of all thetransistors are listed in Table 1.

Where, suffices g, s, b represent gate, source andbody (substrate) of transistors M1, M2 and M3, respectively. Similarly, Cw represents wire capacitance. The
load capacitance can be changed by using MIM capacitor or MOS transistor at the output node of inverter. But
it cannot be much useful in sub-micron technology as
wired capacitance have significant portion in load capacitance, which in turn, limits the maximum oscillating frequency [6] of an oscillator. Thus, this approach
would not be much useful to achieve wide turning
range of an oscillator. Controlling delay by changing
the driving current (Id) would support for wide tuning
range and also provides high linearity which is utilized
in the presented DCO.
M1

Table 1 Size of the transistors in tristate inverter.
NameofTransistors
Size ratio

M1

M2

M3

M4

2.5

1.0

2.5

1.0

D0b
D0

M3

M5

D1b
M2

M4

M6

D1
Fig. 1. 3-stages conventional ring oscillator [2].

III. DESIGN OF PROPOSED DCO

D7b

A. Topology of DCO
The schematic of the proposed 3-stages digital controlled ring oscillator is shown in Fig 2. The circuit has
8 control bits (D0-D7). All the stages are identical andmake a ring for an individual bit. For 8 bits, 8 rings
with different W/L ratio are made in parallel by connecting them at the output of each delay cell. Each ringis made with identical stages to provide equal delay.
One of the advantages of the proposed method is that itprovides symmetrical load unlikely in ref. [3-5]. The
output frequency of the oscillator depends on the control bits. The proposed schematic has used newly proposed tristate inverter for the delay cell.

D7
Fig .2. Schematic of proposed DCO

M1
M2

(a)

B. Tristate Inverter DCO Cell

M3

M4

M1

M3
B

M2

M4
(b)

Fig. 3. Proposed tristate inverter (a) and its equivalent circuit
when control bit is 1 (b).

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The proposed tristate inverter cell can be approximated as transmission gate followed by an inverter
when D=1. Equivalent circuit of the proposed inverter
when D=1 is shown in Fig. 3(b).
For one delay cell calculation the signal starts propagating at node Vin and terminates at node Vout throughnode B. Hence, from the equivalent circuit of Fig. 3(b),the delay of the tristate inverter cell can be interpreted
in to two parts: inverter delay and transmission gate delay. The total delay of the circuit is given by,
Td TINV  TTG(4)

4vout, Vout, V

3

n

I0 x

N 1

§W ·

¦ ¨© L ¸¹ B
n

0

0
0.0

2.0

2.5

3.0

3.5

IV. SIMULATION RESULTS
The proposed DCO was designed by means of ADS(Agilent Co., ADS 2004A) using TSMC 0.35 um
CMOS process parameters, and supply voltage of thisprocess is 3.3 V.
The comparison of voltage transfer characteristics ofproposed and conventional tristate inverter circuit areplotted using same size transistor and same supply voltage in Fig. 5 where the proposed DCO has very sharptransition region. Simulated shows that proposed
tristate inverter has 20-30% power reduction from
2GHz to 250MHZ frequency. It also shows thesignificant improvement of 10% in speed.
The proposed DCO was simulated for all the possiblecombination of control code. The frequency range of
the DCO is from 333Mhz to 1472Mhz. The frequency
versus input control words is shown in Fig. 6, where it
is noted that the proposed DCO possess the high linearity for the wide range of frequency.
Frequency [ MHz ]

1600
1400
1200
1000
800
600
400
200
0
0

Vdd

Vdd
TG

Vss

32

64

96

128

160

192

224

256

Control code

Fig. 6. Relationship between central frequency and input control code showing linearity of the designed DCO.
TG
The simulated output waveform of the selected control input signal is shown in Fig 7. This clearly shows
the large output voltage swing (>3V). The proposed
DCO also changes the output frequency within one
clock period without any ringing at the output voltage
also output voltage swing is constant. Phase noise was

CLA
Vss

1.5

n

TTG 0.69 RTG C LB
Where RTG is the resistance of the transmission gate,approximately constant during switching but inversely
proportional to the W/L ratio of the transistors and CLb
is the load capacitance at the output node of transmission gate.
The equivalent circuit representing delay control mechanism of the proposed DCO is shown in Fig. 4 where
inverter transistors are shown by current sources,
transmission gate as a constant delay cell (TG) and control input is represented by switches in current sources.
The load capacitance (CLA ) of the inverter is constantbecause all the transistor are connected to that node irrespective of the number of control bits status. According to the control code (D0-D7), switches turns on or
off and set the value of current which controls the delay
and in turn, the oscillating frequency.

TG

1.0

Vin

Where I0 = Current flowing for W/L=1, Bn is the statusof the control bits i.e. Bn =1 if switch is on, and Bn = 0
if switch is off. It was also explained before that output
frequency is controlled by changing ID in the proposed
DCO as it provides high linearity for a very wide tuning
range in comparison to the change in load capacitanceas earlier employed in [4].
The transmission gate can be represented as a constant RC delay cell [7] where the delay for the transmission gates is given by,

Vdd

0.5

Fig. 5. Comparison of voltage transfer characteristics of the
proposed tristate inverter and conventional tristate.

(5)nConventional
inverter1

Hence, inverter cell delay (TINV) is calculated by
Equation (2) where the driving current (Id ) is given by
Equation (5) for the proposed oscillator.
Id

Proposed
inverter2

VssFig. 4. Equivalent circuit of delay control unit.

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Table II
Comparison of power consumption of the proposed DCO with other published works.

also calculated for the proposed circuit. The phase noiseis -106dBc/Hz @1MHz at 1.1 GHz central frequency
which is shown in Fig. 8. The dependence of power
consumption with center frequency is shown in Fig. 9
where it draws total current of 19 mA for 3.3 V DC
supply at 1.1 GHz frequency. The comparison of power
consumption with other published DCOs on the similar
technology was illustrated in Table 2 where the proposed DCO is least power consumption among three.
m1
time=46.70nsec
vout1=2.451 V
3.0

m3
m2
time=47.43nsec
vout1=2.512 V

2.0
1.5

m4

0.5
0.0
46

50

0.35μm@3.3V
18-214(MHz)
18mW@
200MHz0.35μm@3.3V
45 - 450(MHz)
100mW@
450MHzThis work was partly supported by a grant ofKnowledge Cluster Initiative implemented by Ministry of Education, Culture, Sports, Science and Technology (MEXT). This work was also partly supported by
VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent Corporation.

0

vout2.pnmx,
dBc ]
Phase
noise [ dBc

0.35μm@3.3V
333-1472(MHz)
17.5mW@
450MHzACKNOWLEDGEMENT

Fig 7. Transition of frequency from 1.3GHz to 1.02GHz.

m1
nois e fre q= 965.4kHz
vout2.pnm x=-106.1 dBc
m1

-100

REFERENCES-150[1] A. Matsuzawa, “Analog IC technologies for future wireless systems,” IEICE Trans. Electron., vol. 89-C, no. 4,
pp. 446-454, April 2006.
[2] L. Dai and R. Harjani, Design of high-performance
CMOS voltage controlled oscillator, Kluwer Academic
Publishers, 2003.
[3] R. A. Nicodimus, S. Takagi, and N. Fujii, “Wide turning
range voltage-controlled ring oscillator,” IEICE Trans
Electron., vol.-E86, no. 6, pp. 1085-1088, June 2003.
[4] C.F. Chan, O.Choy. “A low power digital controlled
oscillator” INt.J. ELECTRONICS.,pp. vol.88,no.4,463466, 2001.
[5] P.-L. Chen, C.-C. Chung, and C.-Y. Lee, “A portable
digitally controlled oscillator using novel varactors,”
IEEE Trans. on Circuits and Systems-II, vol. 52, no. 5,
pp. 233-237, 2005.
[6] S. M. Rezaul Hasan, and Nazmul Ula, “A 16-bit CMOS
digitally controlled oscillator using a novel control
scheme,” 49th IEEE International Symposium on Circuits
and Systems (2006 MWSCAS’06), vol. 1, pp. 680-684,
Aug. 2006.
[7] J. M. Rabaey, Digital Integrated Circuits: a Design Perspective. Prentice-Hall, Inc., 1996.
[8] C.C.Chung and C.-Y. Lee, “An all digital phase-locked
loop for high speed clock generation,” IEEE J. SolidState Circuits, vol. 38, no. 2, pp. 347-351, Feb.2003.

-200

1E9

2E9
1E9

1E8
1E8

1E7
1E7

1E6
1E6

1E5
1E5

1E4
1E4

1E3

1E3

Noise nois
Frequency
e fre q, Hz[ Hz ]Fig. 8. Simulated phase noise of the proposed DCO for 1.1
GHz central frequency.
120

Power consumption [ mW ]Ref. [8]54time, nsec

-50

Ref. [5]A high-linearity 8-bit digitally-controlled oscillator(DCO) is designed on a ring topology using TSMC
0.35 um CMOS process parameters. One of the advantages of the ring topology over a LC-tank oscillator isthat it does not contain any spiral inductor so that thechip size is very small. It consumes 19 mA current at
3.3 V supply voltage and simulated phase noise is 106dBc/Hz (@1MHz). Verification of the simulated
results would be carried out in near future.

m3
time=51.48nsec
vout1=2.023 V

1.0

Proposed

V. CONCLUSION

m1 m2

2.5

vout1, V

OutputfrequencyPowerconsumptionm4
time=52.46nsec
vout1=2.030 V

3.5

\

Items
Function
Process

100
80
60
40
20
0
300

600

900

1200

1500

Frequency [ MHz ]Fig. 9. Dependence of power consumption on central
frequency.

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