Design of Coplanar Waveguide On-Chip Impedance-Matching
Circuit for Wireless Receiver Front-End
H. Kanaya, R. K. Pokharel, F. Koga, Z. Arima, S. Kim, and K. Yoshida
Department of Electronics, Graduate School of Information Science and Electrical Engineering,
Kyushu University, Fukuoka 812-8581, Japan
Abstract — Recently, spiral inductors have widely beenused instead of resistors in the design of matching circuits toenhance the thermal noise performance of a wirelesstransceiver. However, such elements usually have low quality
factor (Q) and may encounter the self-resonance inmicrowave-frequency band which permits its use in higher
frequencies, and on the other hand, they occupy the large onchip space. This paper presents a new design theory for theimpedance-matching circuits for a single-chip SiGe BiCMOS
receiver front-end for 2.4 GHz-band wireless LAN (IEEE802.11b). The presented matching circuits are composed ofconductor-backed coplanar waveguide (CPW) meanderline
resonators and impedance (K) inverter. The prototype frontend receiver is fabricated and measured. A few of themeasured results to verify the design theory are presented.
Index Terms — CPW line, impedance-matching circuit,receiver front-end, transmission-line theory.

I. INTRODUCTION
In the RF section of LSI chip, impedance-matchingcircuits are necessary for interconnecting each part such as
low-noise amplifier (LNA), power amplifier (PA),duplexer, mixers, and so on, and lumped elements areusually used for the design of matching circuits. Amongthe lumped elements, spiral inductors are preferred instead of resistors to enhance the thermal noise
performance [1],[2]. However, they cannot be used at highfrequency range because of the self-resonance and stray
impedances. On the other hand, they also occupy large onchip space.
Distributed elements made of transmission lines are
particularly effective when their size becomes smaller, as
the operating frequency increases. Distributed elements
using transmission lines have already been implemented
in GaAs based monolithic microwave integrated circuit(MMIC). However, it is necessary to fabricate the on-chip
matching circuit based on distributed element, in order tooperate the RF-CMOS or RF-BiCOMS LSI in the highfrequency region.
Among various transmission lines, coplanar waveguide(CPW) line is easy to fabricate on the LSI chip because
the signal line and ground plane exist on the same plane.
In our previous studies [3],[4], some of the present authors

proposed a design method of the CPW super-conducting
impedance-matching circuit for interconnecting anantenna and duplexer.
In this paper, the design theory of the CPW impedancematching circuits for single-chip SiGe BiCMOS LNA anddown-conversion mixer (DCM) for wireless LAN (@2.4GHz-band) is presented using a commercial
electromagnetic (EM) and SPICE co-simulator(ADS2004A; Agilent Technologies), and verified bycomparing the simulation with the results measured on afabricated chip.
II. DESIGN OF LNA AND DCM WITH ON-CHIP IMPEDANCEMATCHING CIRCUIT
Fig. 1 shows the block diagram of single-chip directconversion transceiver which is composed of diode switch,LNA, PA, down-conversion mixer (DCM), and upconversion mixer (UCM). In the figure, the LNA and PA
are with input and output matching circuits. The design
value of the input impedance and output impedance are50Ω for general purpose.
Fig. 2 shows the schematics of the designed LNA andDCM. The DCM employs the double-balanced topology.
The designed value of the Max gain of the LNA and noisefigure (NF) is 17 dB and less than 3dB (@2.45 GHz)
respectively. Similarly, the target conversion gain, NF, IFof the design mixer are 12 dB, less than 5 dB, and 15
MHz respectively. Each VCC and VDD of this process is3.3V.
Matching & Filter Circuit

Present work
DCM

ANTLNA

VCO
050Ω

180SW
PAUCM
1-ChipFig. 1. Block diagram of single chip direct-conversion transceiver.

Vcc

To Mix_RF

Input matchingcircuit

RX_IN50Ω

CPW

Outputmatching circuit
KCPW(a) Schematic of the designed LNA.

VDD
RL

RL+IF-+VLO

Mix_RF-Mix_RF+
LSLS(b) Schematic of the designed DCM .
Fig. 2. Schematic of the designed LNA and DCM.

due to K-inverter

S(1,1)x’)
1,1(SZ*L

yx

Z0

Impedance inversion
due λ/4 tr. line
freq (5.000GHz t o 5.000GHz)

freq (5.000GHz to 5.000GHz)

(a)
GCZ0A

K0,1

(Z1, θz)

YLA’(b)Compensation circuit

λ/4G-jBYL∆l

YL=G+jB

Quarter wavelengthtransmission line

Fig. 3. Design and circuit model of impedance-matching circuit (a) Smith
chart representation (b) circuit model using λ/4 CPW line and K-inverter.

In the present work, main focus is given on the designof the on-chip impedance-matching circuit for a receiver
front-end using the transmission-line theory and itsverification. The presented matching circuit is composedof the CPW meander lines and impedance inverter (Kinverter) or admittance inverter (J-inverter).
Fig. 3 shows the circuit model of the quarter
wavelength (λ/4) matching circuits using K-inverter andits physical interpretation in Smith chart. Z1, Y1 and θx are
the characteristic impedance, characteristic admittance andelectrical length of the λ/4 line, respectively.
In Fig 3(a), Smith chart representation of the design
theory of the matching circuit using λ/4 CPW line and Kinverter is illustrated. For example, Z*L is the conjugate ofinput impedance of LNA (ZL=1/YL) and its position isshown by point x in the Smith chart.
The insertion of the λ/4-transmission line convertes theimpedance to admittance, and its position is represented
by x’. By using negative capacitance (-C), now itsposition will be shifted to new position, y and again due toK-inverter, the 50Ω-matching can be designed. Acompensation circuit to achieve –C is realized by making
the length of the transmission line slighly shorter than λ/4.
In Fig. 3(b), an equivalent circuit representing thematching circuit is shown and its design parameters arecomputed by,⎧B⎪ ∆l = −ω0C⎪⎪
π w,
⎨ Z1 =4 g1 g 2 G⎪⎪
Z 0 x1 ⎛π ⎞, ⎜ x1 = Z 1 ⎟⎪ K 0,1 = w
g 0 g1 ⎝4 ⎠⎩(1)

where, C is the capacitance per unit length of thetransmission line, and w and gi are the normalized
bandwidth and normalized filter element, respectively.
∆l is the line length in order to compensate the jB. Thereactance (X1) and the reactance slope parameter (x1) arefor the series resonance circuit [5]. One of the advantagesof the presented method over lumped parameters is theindependent selection of bandwidth, w in Eq. 1.
III. FABRICATED CHIP AND SIMULATION RESULTS
Fig 4 shows the microphotograph of a single-chip SiGe
BiCMOS LNA and DCM for 2.4 GHz-band wireless LAN
applications, and the proposed impedance-matchingcircuit interconnecting between them and at the input ofthe LNA. The chip is fabricated in TSMC0.35 µm onepoly three-metal BiCMOS technology.
The input and output pads have coplanar configurations
so that characteristic impedances are 50Ω. Spiralinductors are used to apply DC power into the transistors
and the LO ports of the mixer. There is a dummy metal in
the center of the chip in order to suppress the RF noise.

There are also unused K-inverters and CPW lines whichoccupies more than 1/4th space in the fabricated chip (chipsize: 2mm x 3.5 mm).
Fig. 5 shows the simulation results in the case of withand without the matching circuit between the LNA andDCM. The results confirm that the conversion gain of themixer has been increased due to the matching circuit by
the amount of voltage gain of the LNA in linear region.
Please note that designed voltage gain of the LNA and theconversion gain of the DCM are 17 dB and 12 dB,respectively.

lowest metal (metal1) in all area of the CPW structure,
namely conductor backed CPW. The conductance of themetal is 4.1x107 S/m. The signal width and the interval
between the slots of the CPW transmission line are 5 µm
and 15 µm, respectively. For size reduction, the λ/4 line
was bended into meander structure.

Unused K-inverters, andCPW lines

Fig. 6. Microphotograph of the K-inverter.(Taken out from anotherfabricated chip which is not shown in Fig. 4.).

0Inputmatchingcircuit

LNA

Fig. 4. Microphotograph of SiGe BiCMOS reciever front-end. (Chip size:2mm x 3.5 mm)

Conv_gain [dB]S21-10Matching circuit between
LNA and mixer

30-5|S11|, |S21| (dB)

Mixer-15

With matching circuit

S11-20EM-Sim.
Exp.

25-25

2015

Without matching circuit

46Frequency (GHz)

810Fig. 7. Frequency responses of the CPW meanderline.

105-4024-35-30-25-20-15

3.5-10

P_RF [dBm]IV. MEASURED RESULTS
K-inverter is fabricated using shunt meander structure[5]. Fig. 6 shows microphotograph of K-inverter circuits
which is designed using equation (1) and simulated by theEM simulator (Momentum, Agilent technologies). The
design parameters of the matching circuit are f0=2.45 GHz
and w=100 MHz, which is based upon IEEE 802.11b. Inorder to avoid the loss in the Si-substrate, we covered the3L (nH)Fig. 5. Simulation results of the conversion gain of the mixer with andwithout the matching circuit between LNA and mixer.

EM-Sim.
Exp.

2.5
2
1.5
1

24
6Frequency (GHz)

810Fig. 8. Frequency dependence of the inductance (L) of the K-inverter

The input and output microwave characteristics aremeasured by using air coplanar probes (GSG 150;
Cascade Microtech Inc.) and computed controlled vector
network analyzer (HP-8722; HP). Fig. 7 shows thecomparison of the frequency responses of the K-inverter.
Insertion loss (S21) of the EM-simulated result is almost inagreement with that of the experimental result. Fig. 8
show the frequency dependence of the inductance (L) ofthe K-inverter, calculated from the impedance matrix.
Experimental value is almost in agreement with that of theEM-simulation result.

Input Impedance [ Ohm]

80

Real parts

60

Simulation
Measured40200-20
Imaginary parts-40

ACKNOWLEDGEMENT-60-80fabricated in TSMC0.35 µm SiGe BiCMOS technology.
The CPW lines are realized by meander structures so thatthey can be fabricated inside a chip and their shape can be
adjusted in order to exploit the vacant space on thesubstrate effectively. It takes less space than that of thespiral inductors. A rough comparison shows that thematching circuit designed by the proposed method takes
30% less space than that of the spiral inductors(@2.45GHz). If the operating frequency increases, thisratio becomes more effective. Another beauty of thetransmission-line based matching circuit is theindependent selection of the higher bandwidth, which issuperior to the lumped element matching circuit.
When we design the receiver front-end such as LNA ormixer, the main target is not only to obtain maximum gain,
but also maximum efficiency, minimum distortion,
minimum noise figure, and so on, which depend on thespecifications on demand. These optimum matchingconditions are also realized by using the presented method
instead of the lumped circuit element.

1

2

3

4

Frequency [ GHz ]Fig. 9. Input impedance of the fabricated chip.

Fig. 9 shows the comparison of the measured andsimulation results of the input impedance of the fabricatedchip. In the figure, the measured results are in goodagreement with the designed value. For example, themeasured real part of the input impedance is about 47 Ωcompared with 50 Ω of the designed value (@2.45 GHz).
Similarly, the measured imaginary part is about –9 Ω
compared to the +2 Ω of the designed value. This ensuresthat the validity of the presented method for the designingof the impedance-matching circuit using λ/4 CPW lineand K-inverter.
V. CONCLUSION
Design methodology of impedance-matching circuit fora single chip SiGe BiCMOS receiver front-end which iscomposed of λ/4 CPW meander resonators and K-inverter
is presented and verified by comparing the simulation
results with measured results on a designed chipThis work was partly supported by a Grant-in-Aid for
Encouragement of Young Scientists (B) from the Japan
Society for the Promotion of Science (JSPS). This work
was partly supported by VLSI Design and Education
Center (VDEC), the University of Tokyo in collaboration
with CADENCE Corporation. This work was partly incollaboration with Fukuoka Laboratory for Emerging andEnabling Technology of SoC (FLEETS).
REFERENCES[1][2][3][4][5]

D. L. Harame, et, al., ”Currrent status and future trends ofSiGe BiCMOS technology,” IEEE. Trans. Electron Device,vol. 48, pp. 2575-2594, 2001.
A. Matsuzawa, “RF-SoC-expectations and requiredconditions”, IEEE. Trans. Microwave Theory Tech., vol. 50,
pp. 245-253, 2002.
K. Yoshida, T. Takahashi, H. Kanaya, T. Uchiyama, and Z.
Wang, “Superconducting slot antenna with broadband
impedance matching circuit,” IEEE Trans. Appl.
Supercond., vol. 11, pp. 103-106, 2001.
Y. Tsutsumi, H. Kanaya, and K. Yoshida, “Design andperformance of an electrically small slot loop antenna witha miniaturized superconducting matching circuit”, IEEE
Trans. Appl. Supercond., vol. 15, no. 2, pp. 1120-1123,
June 2005.
G. Matthaei, L. Young, and E. M. T. Jones, Microwave
filters, impedance-matching networks, and coupling
structures. Ney York: McGraw-Hill, 1964, pp. 427-440.