CLRC663

High performance multi-protocol NFC frontend CLRC663 and
CLRC663 plus
Rev. 5.2 — 2 July 2021
171152

1

Product data sheet
COMPANY PUBLIC

General description
CLRC663, the high performance multi-protocol NFC frontend.
The CLRC663 multi-protocol NFC frontend IC supports the following operating modes• Read/write mode supporting ISO/IEC 14443 type A and MIFARE Classic
communication mode
• Read/write mode supporting ISO/IEC 14443B
1• Read/write mode supporting JIS X 6319-4 (comparable with FeliCa)• Passive initiator mode according to ISO/IEC 18092• Read/write mode supporting ISO/IEC 15693• Read/write mode supporting ICODE EPC UID/ EPC OTP• Read/write mode supporting ISO/IEC 18000-3 mode 3/ EPC Class-1 HF
The CLRC663’s internal transmitter is able to drive a reader/writer antenna designed
to communicate with ISO/IEC 14443A and MIFARE Classic IC-based cards andtransponders without additional active circuitry. The digital module manages the complete
ISO/IEC 14443A framing and error detection functionality (parity and CRC).
The CLRC663 supports MIFARE Classic with 1 kB memory, MIFARE Classic with 4 kB
memory, MIFARE Ultralight, MIFARE Ultralight C, MIFARE Plus and MIFARE DESFire
products. The CLRC663 supports higher transfer speeds of the MIFARE product family
up to 848 kbit/s in both directions.
The CLRC663 supports layer 2 and 3 of the ISO/IEC 14443B reader/writercommunication scheme except anticollision. The anticollision needs to be implemented in
the firmware of the host controller as well as in the upper layers.
The CLRC663 is able to demodulate and decode FeliCa coded signals. The FeliCa
receiver part provides the demodulation and decoding circuitry for FeliCa coded signals.
The CLRC663 handles the FeliCa framing and error detection such as CRC. The
CLRC663 supports FeliCa higher transfer speeds of up to 424 kbit/s in both directions.
The CLRC663 is supporting the P2P passive initiator mode in accordance with ISO/IEC
18092.
The CLRC663 supports the vicinity protocol according to ISO/IEC15693, EPC UID and
ISO/IEC 18000-3 mode 3/ EPC Class-1 HF.
The following host interfaces are supported:• Serial Peripheral Interface (SPI)• Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)2• I C-bus interface (two versions are implemented: I2C and I2CL)The CLRC663 supports the connection of a secure access module (SAM). A dedicatedseparate I2C interface is implemented for a connection of the SAM. The SAM can be
1 In the following, the word FeliCa is used for JIS X 6319-4

CLRC663

NXP Semiconductors

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
used for high secure key storage and acts as a very performant crypto-coprocessor. A
dedicated SAM is available for connection to the CLRC663.
In this document, the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based
contactless card.

CLRC663

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2

Features and benefits• Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property
licensing rights• High performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s• Supports ISO/IEC 14443 type A, MIFARE Classic, ISO/IEC 14443 B and FeliCa reader
modes• P2P passive initiator mode in accordance with ISO/IEC 18092• Supports ISO/IEC15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3/ EPC Class-1
HF• Supports MIFARE Classic product encryption by hardware in read/write mode
Allows reading cards based on MIFARE Ultralight, MIFARE Classic with 1 kB memory,
MIFARE Classic with 4 kB memory, MIFARE DESFire EV1, MIFARE DESFire EV2 andMIFARE Plus ICs• Low-Power Card Detection• Compliance to EMV contactless protocol specification on RF level can be achieved• Supported host interfaces:– SPI up to 10 Mbit/s
2– I C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus
– RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage
supply2• Separate I C-bus interface for connection of a secure access module (SAM)• FIFO buffer with size of 512 bytes for highest transaction performance• Flexible and efficient power-saving modes including hard power down, standby andlow-power card detection• Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz crystal• 3.0 V to 5.5 V power supply (CLRC66301, CLRC66302)
2.5 V to 5.5 V power supply (CLRC66303)• Up to 8 free programmable input/output pins
• Typical operating distance in read/write mode for communication to a ISO/IEC 14443
type A and MIFARE Classic card up to 12 cm, depending on the antenna size andtuning• Two package options are available for the CLRC66303:
1. HVQFN32: Package with wettable flanks easing the soldering process and quality
control of soldered parts
2. VFBGA36: Smallest package with optimized pin configuration for simple PCB layout• The version CLRC66303 offers a more flexible configuration for Low-Power Card
detection compared to the CLRC66301 and CLRC66302 with the new register
LPCD_OPTIONS. In addition, the CLRC66303 offers new additional settings for the
Load Protocol which fit very well to smaller antennas. The CLRC66303 is therefore therecommended version for new designs.

CLRC663

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

3

Applications• Industrial• Access control• Gaming

CLRC663

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

4

Quick reference data

Table 1. Quick reference data CLRC66301 and CLRC66302
SymbolParameter

VDD

supply voltage

VDD(PVDD)

PVDD supply voltage

VDD(TVDD)

TVDD supply voltage

Conditions
[1]

Typ

Max

Unit

3.0

5.0

5.5

V

3.0

5.0

VDD

V

3.0

5.0

5.5

V

-

8

40

nA

Ipd

power-down current

IDD

supply current

-

17

20

mA

IDD(TVDD)

TVDD supply current

-

100

250

mA

Tamb

operating ambient temperature

-25

+25

+85

°C

Tstg

storage temperature

-55

+25

+125

°C

Min

Typ

Max

Unit

2.5

5.0

5.5

V

2.5

5.0

VDD

V

2.5

5.0

5.5

V

-

8

40

nA

-

17

20

mA

recommended operation

-

180

350

mA

absolute limiting value

-

-

500

mA

[1]
[2]

PDOWN pin pulled HIGH

[2]

Min

no supply voltage applied

VDD(PVDD) must always be the same or lower voltage than VDD.
Ipd is the sum of all supply currents

Table 2. Quick reference data CLRC66303
SymbolParameter

VDD

supply voltage

VDD(PVDD)

PVDD supply voltage

VDD(TVDD)

TVDD supply voltage

Ipd

power-down current

IDD

supply current

IDD(TVDD)

TVDD supply current

Conditions[1]

PDOWN pin pulled HIGH

[2]

Tamb

operating ambient temperature device mounted on PCB whichallows sufficient heat dissipation for
the actual power dissipation of thedevice

-40

+25

+105

°C

Tstg

storage temperature

-55

+25

+125

°C

[1]
[2]

no supply voltage applied

VDD(PVDD) must always be the same or lower voltage than VDD.
Ipd is the sum of all supply currents

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

5

Ordering information

Table 3. Ordering information
Type number
CLRC66301HN,551

Package
Name

Description

Version

HVQFN32

Plastic thermal enhanced very thin quad flat package; noleads; 32 terminals + 1 central ground; body 5 × 5 × 0.85mm, MSL2,
Delivered in one tray, MOQ (Minimum order quantity): 490
pcs

SOT617-1

CLRC66301HN, 557

Plastic thermal enhanced very thin quad flat package; noleads; 32 terminals + 1 central ground; body 5 × 5 × 0.85mm, MSL2,
Delivered in five trays; MOQ: 5x 490 pcs

CLRC66302HN,157

Plastic thermal enhanced very thin quad flat package; noleads; 32 terminals + 1 central ground; body 5 × 5 × 0.85mm, MSL1,
Delivered in five trays; MOQ: 5x 490 pcs

CLRC66302HN,151

Plastic thermal enhanced very thin quad flat package; noleads; 32 terminals + 1 central ground; body 5 × 5 × 0.85mm, MSL1,
Delivered in 1 tray; MOQ: 490 pcs

CLRC66302HN,118

Plastic thermal enhanced very thin quad flat package; noleads; 32 terminals + 1 central ground; body 5 × 5 × 0.85mm, MSL1,
Delivered on reel with 6000 pieces; MOQ: 6000 pcs

CLRC66303HNE

Plastic thermal enhanced very thin quad flat package; noleads; 32 terminals + 1 central ground; body 5 × 5 × 0.85mm, MSL2, wettable flanks
Delivered in one tray, MOQ (Minimum order quantity): 490
pcs

CLRC66303HNY

Plastic thermal enhanced very thin quad flat package; noleads; 32 terminals + 1 central ground; body 5 × 5 × 0.85mm, MSL2, wettable flanks
Delivered on reel with 6000 pieces; MOQ: 6000 pcs

CLRC66303A0EV

CLRC663

Product data sheet
COMPANY PUBLICVFBGA36very thin fine-pitch ball grid array package; 36 terminals,
0.5mm pitch, 3.5mm x 3.5mm x 0.8mm body, MSL3
Delivered on reel with 5000 pieces; MOQ: 5000 pcs

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

6

Block diagram
The analog interface handles the modulation and demodulation of the antenna signals forthe contactless interface.
The contactless UART manages the protocol dependency of the contactless interface
settings managed by the host.
The FIFO buffer ensures fast and convenient data transfer between host and thecontactless UART.
The register bank contains the settings for the analog and digital functionality.
REGISTER BANKANTENNAANALOG
INTERFACECONTACTLESS
UART

FIFO
BUFFERSERIAL UARTSPI
I2C-BUSHOST
001aaj627

Figure 1. Simplified block diagram of the CLRC663

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25 PVDD

26 IFSEL0/OUT4

27 IFSEL1/OUT5

28 IF029 IF130 IF2

terminal 1
index area

31 IF332 IRQ

Pinning information

TDO/OUT01

TDI/OUT1

2

24 SDA

TMS/OUT2

3

TCK/OUT34SIGIN/OUT7

5

SIGOUT

6

19 XTAL1DVDD

718 TVDD

VDD

8

17 TX1(1)

23 SCL
22 CLKOUT/OUT621 PDOWNTVSS 16

20 XTAL2

TX2 15

VMID 14

RXN 13

RXP 12

AUX2 11AVDD

9heatsink

AUX1 107001aam004

Transparent top view

1. VSS - heat sink connection
Figure 2. Pinning configuration HVQFN32 (SOT617-1)

7.1 Pin description HVQFN32
Table 4. Pin description
Pin

SymbolType

Description

1

TDO / OUT0O

test data output for boundary scan interface / general purpose output 0

2

TDI / OUT1

I/O

test data input boundary scan interface / general purpose output 1

3

TMS / OUT2

I/O

test mode select boundary scan interface / general purpose output 2

4

TCK / OUT3

I/O

test clock boundary scan interface / general purpose output 3

5

SIGIN /OUT7

I/O

Contactless communication interface output. / general purpose output 7

6

SIGOUTO

Contactless communication interface input.

7

DVDD

PWR

digital power supply buffer

8

VDD

PWR

power supply

9

AVDD

PWR

analog power supply buffer

10

AUX1

O

auxiliary outputs: Pin is used for analog test signal

11

AUX2

O

auxiliary outputs: Pin is used for analog test signal

12

RXP

I

receiver input pin for the received RF signal.

13

RXN

I

receiver input pin for the received RF signal.

14

VMID

PWR

internal receiver reference voltage

15

TX2

O

transmitter 2: delivers the modulated 13.56 MHz carrier

16

TVSS

PWR

transmitter ground, supplies the output stage of TX1, TX2

17

TX1

O

transmitter 1: delivers the modulated 13.56 MHz carrier

CLRC663

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[1]

[1]

[1]

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Table 4. Pin description...continued
Pin

SymbolType

Description

18

TVDD

PWR

transmitter voltage supply

19

XTAL1

I

crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin isalso the input for an externally generated clock (fosc = 27.12 MHz)

20

XTAL2

O

crystal oscillator output: output of the inverting amplifier of the oscillator

21

PDOWN

I

Power Down (RESET)

22

CLKOUT / OUT6O

clock output / general purpose output 6

23

SCL

O

Serial Clock line

24

SDA

I/O

Serial Data Line

25

PVDD

PWR

pad power supply

26

IFSEL0 / OUT4I

host interface selection 0 / general purpose output 4

27

IFSEL1 / OUT5

I

host interface selection 1 / general purpose output 5

28

IF0

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
2
2
I C, I C-L

29

IF1

I/O

interface pin, multifunction pin: Can be assigned to host interface SPI, I C, I C-L

30

IF2

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
2
2
I C, I C-L

31

IF3

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
2
2
I C, I C-L

32

IRQ

O

interrupt request: output to signal an interrupt event

33

VSS

PWR

ground and heat sink connection

[1]

2

2

This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.

7.2 Pin description VFBGA36
Table 5. Pin description VFBGA36
SymbolPin

Type

Description

IF2

A1

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I C,
2
I C-L

IF1

A2

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I C,
2
I C-L

IF0

A3

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I C,
2
I C-L

IFSEL1A4

I

host interface selection 1 / general purpose output 5

PVDD

A5

PWR

pad power supply

PDOWN

A6

I

Power Down (RESET)

IRQ

B1

O

interrupt request: output to signal an interrupt event

TDI / OUT1

B2

I/O

test data input boundary scan interface / general purpose output 1

TMS / OUT2

B3

I/O

test mode select boundary scan interface / general purpose output 2

TDO / OUT0

B4

O

test data output for boundary scan interface / general purpose output 0

SCL

B5

I

Serial Clock line

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2

2

2

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Table 5. Pin description VFBGA36...continued
SymbolPin

Type

Description

XTAL2

B6

O

crystal oscillator output: output of the inverting amplifier of the oscillator

IF3

C1

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I C,
2
I C-L

TCK / OUT2

C2

I/O

test clock boundary scan interface / general purpose output 3

GND

C3

PWR

ground and heat sink connection

CLKOUT / OUT6

C4

O

clock output / general purpose output 6

SDA

C5

I/O

Serial Data Line

XTAL1

C6

I

crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin isalso the input for an externally generated clock (fosc = 27.12 MHz)

DVDD

D1

PWR

digital power supply buffer

SIGIN /OUT7

D2

I/O

Contactless communication interface output. / general purpose output 7

GND

D3

PWR

ground and heat sink connection

GND

D4

PWR

ground and heat sink connection

GND

D5

PWR

ground and heat sink connection

TVDD

D6

PWR

transmitter voltage supply

VDD

E1

PWR

power supply

AUX1

E2

O

auxiliary output: Pin is used for analog test signal

SIGOUT

E3

O

Contactless communication interface input.

AUX2

E4

O

auxiliary output: Pin is used for analog test signal

IFSEL0E5Ihost interface selection 0 / general purpose output 4

TX1

E6

O

transmitter 1: delivers the modulated 13.56 MHz carrier

AVDD

F1

PWR

analog power supply buffer

RXP

F2

I

receiver input pin for the received RF signal.

RXN

F3

I

receiver input pin for the received RF signal.

VMID

F4

PWR

internal receiver reference voltage

TX2

F5

O

transmitter 2: delivers the modulated 13.56 MHz carrier

TVSS

F6

PWR

transmitter ground, supplies the output stage of TX1, TX2

[1]

2

[1]

[1]

[1]

This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

8

Functional description
SAM interface
I2C,
LOGICAL

SDA
SCL

FIFO
512 Bytes

EEPROM
8 kByteSPI

host interfaces

RESET
LOGIC

IFSEL1IFSEL0

PDOWN

I2 C

IF0

REGISTERS

IF1

UART

IF2

STATEMACHINES

IF3
SPI

TCK
TDI
TMS
TDO

ANALOGUE FRONT-END

BOUNDARY
SCAN

VOLTAGEREGULATOR
3/5 V =>
1.8 V
DVDD

VOLTAGEREGULATOR
3/5 V =>
1.8 V
AVDD

POR

RNG

VDD
VSS
PVDD
TVDD
TVSS
AVDD
DVDD

TIMER0..3

INTERRUPTCONTROLLER

IRQ

TIMER4(WAKE-UP
TIMER)

TX
CODEC

CRC

SIGIN/SIGOUT
CONTROL

SIGIN

RX
DECOD
CLCOPROSIGPROSIGOUT

ADC

LFO

PLL

RX

TX

OSC

RXP
VMID RXN

TX2
TX1

XTAL2
XTAL1

CLKOUT
AUX1
AUX2

001aam005

Figure 3. Detailed block diagram of the CLRC663

8.1 Interrupt controller
The interrupt controller handles the enabling/disabling of interrupt requests. All of theinterrupts can be configured by firmware. Additionally, the firmware has possibilities totrigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0
and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En
and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt
controller register is implemented.
The CLRC663 indicates certain events by setting bit IRQ in the register Status1Reg andadditionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt thehost using its interrupt handling capabilities. This allows the implementation of efficient
host software.
Table 4. shows the available interrupt bits, the corresponding source and the condition
for its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, inregister IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer
underflows.

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The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the statechanges from sending data to transmitting the end of the frame pattern, the transmitter
unit sets the interrupt bit automatically.
The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is
detected.
The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of thecommand register changes to idle.
The register WaterLevel defines both - minimum and maximum warning levels - counting
from top and from bottom of the FIFO by a single value.
The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, thatmeans the FIFO data number has reached the top level as configured by the register
WaterLevel and bit WaterLevelExtBit.
The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, thatmeans the FIFO data number has reached the bottom level as configured by the register
WaterLevel.
The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART
during receive. This is indicated by any bit set to logic 1 in register Error.
The bit LPCDIRQ in register IRQ0 indicates a card detected.
The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by thecontactless UART during receiving.
The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt
source when enabled.
Table 6. Interrupt sources

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Interrupt bit

Interrupt source

Is set automatically, whenTimer0IRQ

Timer Unit

the timer register T0 CounterVal underflows

Timer1IRQ

Timer Unit

the timer register T1 CounterVal underflows

Timer2IRQ

Timer Unit

the timer register T2 CounterVal underflows

Timer3IRQ

Timer Unit

the timer register T3 CounterVal underflows

TxIRQ

Transmittera transmitted data stream ends

RxIRQ

Receivera received data stream ends

IdleIRQ

Command Registera command execution finishes

HiAlertIRQ

FIFO-buffer pointerthe FIFO data number has reached the top level asconfigured by the register WaterLevel

LoAlertIRQ

FIFO-buffer pointerthe FIFO data number has reached the bottom level asconfigured by the register WaterLevel

ErrIRQ

contactless UART

a communication error had been detected

LPCDIRQ

LPCD

a card was detected when in low-power card detection
mode

RxSOFIRQ

Receiverdetection of a SOF or a subcarrier

GlobalIRQ

all interrupt sources

will be set if another interrupt request source is set

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8.2 Timer module
Timer module overview
The CLRC663 implements five timers. Four timers -Timer0 to Timer3 - have an input
clock that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived
from the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Eachtimer implements a counter register which is 16 bit wide. A reload value for the counteris defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo.
The fifth timer Timer4 is intended to be used as a wake-up timer and is connected to theinternal LFO (Low Frequency Oscillator) as input clock source.
The TControl register allows the global start and stop of each of the four timers Timer0
to Timer3. Additionally, this register indicates if one of the timers is running or stopped.
Each of the five timers implements an individual configuration register set defining timer
reload value (e.g. T0ReloadHi, T0ReloadLo), the timer value (e.g. T0CounterValHi,
T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g.
T0Control).
The external host may use these timers to manage timing relevant tasks. The timer unit
may be used in one of the following configurations:• Time-out counter• Watch-dog counter• Stop watch• Programmable one-shot timer• Periodical trigger
The timer unit can be used to measure the time interval between two events or toindicate that a specific event has occurred after an elapsed time. The timer register
content is modified by the timer unit, which can be used to generate an interrupt to allow
a host to react on this event.
The counter value of the timer is available in the registers T(x)CounterValHi,
T(x)CounterValLo. The content of these registers is decremented at each timer clock.
If the counter value has reached a value of 0000h and the interrupts are enabled for thisspecific timer, an interrupt will be generated as soon as the next clock is received.
If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit
Timer(x)IRQ can be set and reset by the host controller. Depending on the configuration,
the timer will stop counting at 0000h or restart with the value loaded from registers
T(x)ReloadHi, T(x)ReloadLo.
The counting of the timer is indicated by bit TControl.T(x)Running.
The timer can be started by setting bits TControl.T(x)Running andTControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow andclearing TControl.T(x)Running.
Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start. This can be
useful if dedicated protocol requirements need to be fulfilled.

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8.2.1 Timer modes
8.2.1.1 Time-Out- and Watch-Dog-Counter
Having configured the timer by setting register T(x)ReloadValue and starting the countingof Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit
decrements the T(x)CounterValue Register beginning with the configured start event. If
the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received
from the card), the timer unit stops (no interrupt is generated).
If no stop event occurs, the timer unit continues to decrement the counter registers until
the content is zero and generates a timer interrupt request at the next clock cycle. This
allows indicating to a host that the event did not occur during the configured time interval.
8.2.1.2 Wake-up timer
The wake-up Timer4 allows to wake-up the system from standby after a predefined time.
The system can be configured in such a way that it is entering the standby mode again incase no card had been detected.
This functionality can be used to implement a low-power card detection (LPCD). For
the low-power card detection, it is recommended to set T4Control.T4AutoWakeUp
and T4Control.T4AutoRestart, to activate the Timer4 and automatically set the system
in standby. The internal low frequency oscillator (LFO) is then used as input clock
for this Timer4. If a card is detected, the host-communication can be started. If bit
T4Control.T4AutoWakeUp is not set, the CLRC663 will not enter the standby mode again
in case no card is detected but stays fully powered.
8.2.1.3 Stop watch
The elapsed time between a configured start- and stop event may be measured by the
CLRC663 timer unit. By setting the registers T(x)ReloadValueHi, T(x)ReloadValueLo thetimer starts to decrement as soon as activated. If the configured stop event occurs, thetimer stops decrementing. The elapsed time between start and stop event can then be
calculated by the host dependent on the timer interval TTimer:(1)
If an underflow occurred which can be identified by evaluating the corresponding IRQ bit,the performed time measurement according to the formula above is not correct.
8.2.1.4 Programmable one-shot timer
The host configures the interrupt and the timer, starts the timer and waits for the interrupt
event on pin IRQ. After the configured time, the interrupt request will be raised.
8.2.1.5 Periodical trigger
If the bit T(x)Control.T(x)AutoRestart is set and the interrupt is activated, an interrupt
request will be indicated periodically after every elapsed timer period.

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8.3 Contactless interface unit
The contactless interface unit of the CLRC663 supports the following read/write operating
modes:• ISO/IEC14443 type A and MIFARE Classic• ISO/IEC14443B• FeliCa• ISO/IEC15693/ICODE• ICODE EPC UID• ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

BATTERY/POWER SUPPLYREADER IC

ISO/IEC 14443 A CARDMICROCONTROLLER
reader/writer

001aal996

Figure 4. Read/write mode

A typical system using the CLRC663 is using a microcontroller to implement the higher
levels of the contactless communication protocol and a power supply (battery or external
supply).

8.3.1 Communication mode for ISO/IEC 14443 type A and for MIFARE Classic
The physical level of the communication is shown in the following figure:(1)

ISO/IEC 14443 A
READER(2)

ISO/IEC 14443 A CARD
001aam268

1. Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s
2. Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106
kbit/s to 848 kbit/s
Figure 5. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFAREClassic

The physical parameters are described in the following table:
Table 7. Communication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic
Communication
direction

Signal typereader side
Reader to card (senddata from the CLRC663 modulation
to a card)
bit encoding
fc = 13.56 MHz
bit rate [kbit/s]

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Transfer speed
106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

100 % ASK

100% ASK

100% ASK

100% ASK

modified Miller
encoding

modified Miller
encoding

modified Miller
encoding

modified Miller
encoding

fc / 128fc / 64

fc / 32

fc / 16

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Table 7. Communication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic...continued
Communication
direction

Signal type

Card to reader(CLRC663 receives
data from a card)

Transfer speed
106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

card sidemodulationsubcarrier load
modulationsubcarrier load
modulationsubcarrier load
modulationsubcarrier load
modulationsubcarrier
frequency

fc / 16

fc / 16

fc / 16

fc / 16bit encoding

Manchester
encoding

BPSK

BPSK

BPSK

The CLRC663 connection to a host is required to manage the complete ISO/IEC 14443
type A and MIFARE Classic communication protocol. The following figure shows the datacoding and framing according to ISO/IEC 14443 type A and MIFARE Classic.
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data

8-bit data
odd
paritystart bit is 1

8-bit data
odd
parityodd
parityISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
8-bit data
start bit is 0

evenparity8-bit data

odd
parity8-bit data
odd
parityburst of 32
subcarrier clocks

even parity at theend of the frame
001aak585

Figure 6. Data coding and framing according to ISO/IEC 14443 A

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part3 and handles parity generation internally according to the transfer speed.

8.3.2 ISO/IEC14443 type B functionality
The physical level of the communication is shown in the following figure:(1)

ISO/IEC 14443 B
READER(2)

ISO/IEC 14443 B CARD
001aal997

1. Reader to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s
2. Card to reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106
kbit/s to 848 kbit/s
Figure 7. ISO/IEC 14443 type B communication diagram

The physical parameters are described in the following table:

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Table 8. Communication overview for ISO/IEC 14443 B reader/writer
Communication
direction

Signal type106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

10 % ASK

10 % ASK

10 % ASK

10 % ASK

NRZ

NRZ

NRZ

NRZ

128 / fc

64 / fc

32 / fc

16 / fc

card sidemodulationsubcarrier load
modulationsubcarrier load
modulationsubcarrier load
modulationsubcarrier load
modulationsubcarrier
frequency

fc / 16

fc / 16

fc / 16

fc / 16bit encoding

BPSK

BPSK

BPSK

BPSK

reader side
Reader to card (senddata from the CLRC663 modulation
to a card)
bit encoding
fc = 13.56 MHz
bit rate [kbit/s]
Card to reader(CLRC663 receives
data from a card)

Transfer speed

The CLRC663 connected to a host is required to manage the complete ISO/IEC 14443 B
protocol. The following figure shows the ISO/IEC 14443B SOF and EOF.
Start of Frame (SOF)
sequence
9.44 µs
UNMODULATED (SUB)CARRIER''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0''''1'' ''1''

DATA

End of Frame (EOF)
sequence
9.44 µs

LAST CHARACTER''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0''

UNMODULATED (SUB)CARRIER
001aam270

Figure 8. SOF and EOF according to ISO/IEC 14443 B

8.3.3 FeliCa functionality
The FeliCa mode is the general reader/writer to card communication scheme according
to the FeliCa specification. The communication on a physical level is shown in thefollowing figure:

FeliCa READER(PCD)

1. PCD to PICC 8-30 % ASK
Manchester Coded,baudrate 212 to 424 kbaud
2. PICC to PCD, > Load modulation
Manchester Coded,baudrate 212 to 424 kbaud

FeliCa CARD(PICC)

001aam271

Figure 9. FeliCa read/write communication diagram

The physical parameters are described in the following table:

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Table 9. Communication overview for FeliCa reader/writer
Communication
direction

Transfer speed FeliCa

FeliCa higher transfer
speeds212 kbit/s

424 kbit/s

reader sidemodulation

8 % to 30 % ASK

8 % to 30 % ASK

bit encoding

Manchester encoding

Manchester encoding

bit rate

fc/64

fc/32

Load modulation

Load modulation

Manchester encoding

Manchester encoding

Signal type

Reader to card (senddata from the CLRC663
to a card)
fc = 13.56 MHz

Card to reader (CLRC663 card side load
receives data from a
modulation
card)
bit encoding

The CLRC663 needs to be connected to a dedicated host to be able to support thecomplete FeliCa protocol.
8.3.3.1 FeliCa framing and coding
Table 10. FeliCa framing and coding
Preamble (Hex.)
00

00

00

Len

Sync
(Hex.)
00

00

00

B2

n-DataCRC

4D

To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2 bytes sync bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following Len byte indicates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the host controller has to send the Len- and databytes to the CLRC663's FIFO-buffer. The preamble and the sync bytes are generated by
the CLRC663 automatically and must not be written to the FIFO by the host controller.
The CLRC663 performs internally the CRC calculation and adds the result to the data
frame.

8.3.4 ISO/IEC15693 functionality
The physical parameters are described in the following table:
Table 11. Communication overview for ISO/IEC 15693 reader/writer reader to label

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Communication
direction

Signal type

Reader to label(send data from the
CLRC663 to a card)

Transfer speed
fc / 8192 kbit/s

fc / 512 kbit/s

reader sidemodulation

10 % to 30 % ASK or
100 % ASK

10 % to 30 % ASK 90 %to 100 % ASK

bit encoding

1/256

1/4

data rate

1.66 kbit/s

26.48 kbit/s

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Table 12. Communication overview for ISO/IEC 15693 reader/writer label to reader
Communication
direction

Signal type Transfer speed

Label to reader(CLRC663
receives datafrom a card)
fc = 13.56 MHz

card sidemodulation

not supported

not supported single (dual)
subcarrier
load
modulation
ASK

bit length
(μs)

-

-

37.76 (37.46) 18.88

bit encoding --Manchester
codingManchester
codingsubcarrier
frequency[MHz]-fc / 32 (fc /28)

fc / 32[1]

6.62 (6.67) kbit/s 13.24 kbit/s

-

[1]

26.48
52.96 kbit/s(26.69) kbit/s
singlesubcarrier
load
modulation
ASK

Fast inventory (page) read command only (ICODE proprietary command).

pulse
modulated
carrier~9.44 µs
~18.88 µs

0 1 2 3 4

. . . 2 . . . . . . . . . .
2
5~4,833 ms. . . . . . . . . . 2 2 2 25 5 5 52 3 4 5001aam272

Figure 10. Data coding according to ISO/IEC 15693. standard mode reader to label

8.3.5 EPC-UID/UID-OTP functionality
The physical parameters are described in the following table:
Table 13. Communication overview for EPC/UID

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Communication
direction

Signal typeTransfer speed

Reader to card
(send data from the
CLRC663 to a card)

reader side modulation 10 % to 30 % ASK

Card to reader(CLRC663 receives
data from a card)

card side modulation

single subcarrier load
modulation

bit length

18.88 μs

bit encoding

Manchester coding

26.48 kbit/s
bit encoding

RTZ

bit length

37.76 μs

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Data coding and framing according to EPC global 13.56 MHz ISM (industrial, scientificand medical) Band Class 1 Radio Frequency Identification Tag Interface Specification(Candidate Recommendation, Version 1.0.0).

8.3.6 ISO/IEC 18000-3 mode 3/ EPC Class-1 HF functionality
The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this document. For adetailed explanation of the protocol, refer to the ISO/IEC 18000-3 mode 3/ EPC Class-1
HF standard.
8.3.6.1 Data encoding ICODE
The ICODE protocols have mainly three different methods of data encoding:• "1" out of "4" coding scheme• "1" out of "256" coding scheme• "Return to Zero" (RZ) coding scheme
Data encoding for all three coding schemes is done by the ICODE generator.
The supported EPC Class-1 HF modes are:
• 2 pulse for 424 kbit subcarrier• 4 pulse for 424 kbit subcarrier• 2 pulse for 848 kbit subcarrier• 4 pulse for 848 kbit subcarrier

8.3.7 ISO/IEC 18092 mode
The CLRC663 supports Passive Initiator Communication mode at the transfer speeds
106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the ISO/IEC 18092 standard.
• Passive communication mode means that the target answers to an initiator commandin a load modulation scheme. The initiator is active in terms of generating the RF field.
• Initiator: generates RF field at 13.56 MHz and starts the ISO/IEC 18092
communication.
• Target: responds to initiator command either in a load modulation scheme in Passive
communication mode or using a self-generated and self-modulated RF field for Active
Communication mode.
8.3.7.1 Passive communication mode
Passive communication mode means that the target answers to an initiator command ina load modulation scheme. The initiator is active meaning generating the RF field.

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1. initiator starts communication
at selected transfer speed
host

NFC INITIATOR

NFC TARGET

2. targets answers using
load modulated dataat the same transfer speed

powered togenerate RF fieldhost

powered for
digital processing

001aan217

Figure 11. Passive communication mode

Table 14. Communication overview for Passive communication mode
Communication
direction

106 kbit/s

212 kbit/s

424 kbit/s

Initiator → target

According to ISO/IEC
14443A
100 % ASK, Modified Miller
Coded

According to FeliCa, 8 % to 30 % ASK
Manchester Coded

Target → initiator

According to ISO/IEC
14443A subcarrier load
modulation, Manchester
Coded

According to FeliCa, > 12 % ASK
Manchester Coded

The contactless UART of CLRC663 and a dedicated host controller are required tohandle the ISO/IEC 18092 passive initiator protocol.
8.3.7.2 ISO/IEC 18092 framing and coding
The ISO/IEC 18092 framing and coding in Passive communication mode is defined in the
ISO/IEC 18092 standard.
Table 15. Framing and coding overview
Transfer speed

Framing and Coding

106 kbit/s

According to the ISO/IEC 14443 type A and MIFARE
scheme212 kbit/s

According to the FeliCa scheme

424 kbit/s

According to the FeliCa scheme

8.3.7.3 ISO/IEC 18092 protocol support
The ISO/IEC 18092 protocol is not described in this document. For a detailed explanationof the protocol, refer to the ISO/IEC 18092 standard.

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8.4 Host interfaces
8.4.1 Host interface configuration
2

2

The CLRC663 supports direct interfacing of various hosts as the SPI, I C, I CL andserial UART interface type. The CLRC663 resets its interface and checks the current
host interface type automatically having performed a power-up or resuming from power
down. The CLRC663 identifies the host interface by the means of the logic levels on
the control pins after the Cold Reset Phase. This is done by a combination of fixed
pin connections.The following table shows the possible configurations defined by
IFSEL1,IFSEL0:
Table 16. Connection scheme for detecting the different interface types
Pin

Pin Symbol

UART

SPI

I C

2

I C-L

2

28

IF0

RX

MOSI

ADR1

ADR1

29

IF1

n.c.

SCK

SCL

SCL

30

IF2

TX

MISO

ADR2

SDA

31

IF3

PAD_VDD

NSS

SDA

ADR2

26

IFSEL0VSS

VSS

PAD_VDD

PAD_VDD

27

IFSEL1VSS

PAD_VDDVSS

PAD_VDD

8.4.2 SPI interface
8.4.2.1 General
READER IC
SCK
MOSI
MISO
NSS

IF1
IF0
IF2
IF3
001aal998

Figure 12. Connection to host with SPIThe CLRC663 acts as a slave during the SPI communication. The SPI clock SCK has tobe generated by the master. Data communication from the master to the slave uses theLine MOSI. Line MISO is used to send data back from the CLRC663 to the master.
A serial peripheral interface (SPI compatible) is supported to enable high-speed
communication to a host. The implemented SPI compatible interface is according to a
standard SPI interface. The SPI compatible interface can handle data speed of up to
10 Mbit/s. In the communication with a host, CLRC663 acts as a slave receiving datafrom the external host for register settings and to send and receive data relevant for thecommunication on the RF interface.
NSS (Not Slave Select) enables or disables the SPI interface. When NSS is logical high,the interface is disabled and reset. Between every SPI command, the NSS must go to
logical high to be able to start the next command read or write.
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On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI
line shall be stable on rising edge of the clock line (SCK) and is allowed to change on
falling edge. The same is valid for the MISO line. Data is provided by the CLRC663 on
the falling edge and is stable on the rising edge.The polarity of the clock is low at SPI
idle.
8.4.2.2 Read data
To read out data from the CLRC663 by using the SPI compatible interface, the following
byte order has to be used.
The first byte that is sent defines the mode (LSB bit) and the address.
Table 17. Byte Order for MOSI and MISO
byte 0byte 1byte 2byte 3 to n-1 byte n

byte n+1

MOSI

address 0

address 1

address 2……..

address n

00h

MISO

X

data 0

data 1……..

data n - 1

data nRemark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.3 Write data
To write data to the CLRC663 using the SPI interface, the following byte order has tobe used. It is possible to write more than one byte by sending a single address byte
(see.8.5.2.4).
The first send byte defines both, the mode itself and the address byte.
Table 18. Byte Order for MOSI and MISO
byte 0byte 1byte 23 to n-1

byte nbyte n + 1

MOSI

address 0

data 0

data 1……..

data n - 1

data n

MISO

X

X

X

……..

X

X

Remark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.4 Address byte
The address byte has to fulfill the following format:
The LSB bit of the first byte defines the used mode. To read data from the CLRC663, theLSB bit is set to logic 1. To write data to the CLRC663, the LSB bit has to be cleared. The
bits 6 to 0 define the address byte.
NOTE: When writing the sequence [address byte][data0][data1][data2]..., [data0] is
written to address [address byte], [data1] is written to address [address byte + 1] and[data2] is written to [address byte + 2].
Exception: This auto increment of the address byte is not performed if data is written to
the FIFO address
Table 19. Address byte 0 register; address MOSI

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7

6

5

4

3

2

1

0

address 6

address 5

address 4

address 3

address 2

address 1

address 0

1 (read)0 (write)

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Table 19. Address byte 0 register; address MOSI...continued
7

6

5

4

3

2

1

0

MSB

LSB

8.4.2.5 Timing Specification SPIThe timing condition for SPI interface is as follows:
Table 20. Timing conditions SPI
SymbolParameter

Min

Typ

Max

Unit

tSCKL

SCK LOW time

50

-

-

ns

tSCKH

SCK HIGH time

50

-

-

ns

th(SCKH-D)

SCK HIGH to data input hold time

25

-

-

ns

tsu(D-SCKH)

data input to SCK HIGH set-up time

25

-

-

ns

th(SCKL-Q)

SCK LOW to data output hold time

-

-

25

ns

t(SCKL-NSSH)SCK LOW to NSS HIGH time

0

-

-

ns

tNSSH

NSS HIGH time

50

-

-

ns

tNSSH

tSCKL

tSCKH

tSCKL

SCK

tsu(D-SCKH)

th(SCKL-Q)
th(SCKH-D)

MOSI

MSB

LSB

MISO

MSB

LSB
t(SCKL-NSSH)

NSS
aaa-016093

Figure 13. Connection to host with SPI

Remark: To send more bytes in one data stream, the NSS signal must be LOW during
the send process. To send more than one data stream, the NSS signal must be HIGH
between each data stream.

8.4.3 RS232 interface
8.4.3.1 Selection of the transfer speeds
The internal UART interface is compatible to an RS232 serial interface. The levels
supplied to the pins are between VSS and PVDD. To achieve full compatibility of thevoltage levels to the RS232 specification, an RS232 level shifter is required.
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Table 22 describes examples for different transfer speeds and relevant register settings.
The resulting transfer speed error is less than 1.5 % for all described transfer speeds.
The default transfer speed is 115.2 kbit/s.
To change the transfer speed, the host controller has to write a value for the new transfer
speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set
the transfer speed in the SerialSpeedReg.
Table 21 describes the settings of BR_T0 and BR_T1.
Table 21. Settings of BR_T0 and BR_T1
BR_T0

0

1

2

3

4

5

6

7

factor BR_T0

1

1

2

4

8

16

32

64

range BR_T1

1 to 32

33 to 64

33 to 64

33 to 64

33 to 64

33 to 64

33 to 64

33 to 64

Table 22. Selectable transfer speeds
Transfer speed (kbit/s)

Serial SpeedReg

Transfer speed accuracy (%)(Hex.)
7.2

FA

-0.25

9.6

EB

0.32

14.4

DA

-0.25

19.2

CB

0.32

38.4

AB

0.32

57.6

9A

-0.25

115.2

7A

-0.25

128

74

-0.06

230.4

5A

-0.25

460.8

3A

-0.25

921.6

1C

1.45

1228.815

0.32

The selectable transfer speeds as shown are calculated according to the following
formulas:if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
(BR_T0 - 1)
if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2
Remark: Transfer speeds above 1228.8 kBits/s are not supported.
8.4.3.2 Framing
Table 23. UART framing

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Bit

LengthValueStart bit (Sa)

1 bit

0

Data bits

8 bit

Data

Stop bit (So)

1 bit

1

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Remark: For data and address bytes, the LSB bit has to be sent first. No parity bit isused during transmission.
Read data: To read out data using the UART interface, the flow described below has tobe used. The first send byte defines both the mode itself and the address. The Trigger on
pin IF3 has to be set, otherwise no read of data is possible.
Table 24. Byte Order to Read Data
Modebyte 0byte 1RX

address-

TX-

data 0ADDRESS
RX

Sa

A0

A1

A2

A3

A4

A5

A6

RD/
NWR

So

DATA
TX

Sa

D0

D1

D2

D3

D4

D5

D6

D7

So

001aam298

Figure 14. Example for UART Read

Write data:
To write data to the CLRC663 using the UART interface, the following sequence has tobe used.
The first send byte defines both, the mode itself and the address.
Table 25. Byte Order to Write Data
Modebyte 0byte 1RX

address 0

data 0TX

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ADDRESS
RX

Sa

A0

A1

A2

A3

A4

DATA

A5

A6

RD/
NWR

So

Sa

D0

RD/
NWR

So

D1

D2

D3

D4

D5

D6

D7

So

ADDRESS
TX

Sa

A0

A1

A2

A3

A4

A5

A6

001aam299

Figure 15. Example diagram for a UART write

Remark: Data can be sent before address is received.
2

8.4.4 I C-bus interface
8.4.4.1 General2

An Inter IC (I C) bus interface is supported to enable a low cost, low pin count serial bus
2interface to the host. The implemented I C interface is mainly implemented according to2
the NXP Semiconductors I C interface specification, rev. 3.0, June 2007. The CLRC663
can act as a slave receiver or slave transmitter in standard mode, fast mode and fastmode plus.
2

The following features defined by the NXP Semiconductors I C interface specification,
rev. 3.0, June 2007 are not supported:• The CLRC663 I2C interface does not stretch the clock• The CLRC663 I2C interface does not support the general call. This means that the
CLRC663 does not support a software reset• The CLRC663 does not support the I2C device ID• The implemented interface can only act in slave mode. Therefore no clock generation
and access arbitration is implemented in the CLRC663.
• High-speed mode is not supported by the CLRC663
PULL-UPNETWORKPULL-UPNETWORKMICROCONTROLLER

READER IC
SDA
SCL
001aam000

2

Figure 16. I C-bus interface

The voltage level on the I2C pins is not allowed to be higher than PVDD.
SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.
2
Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the I Cbus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in thefast mode+.
22

If the I C interface is selected, a spike suppression according to the I C interface
specification on SCL and SDA is automatically activated.
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For timing requirements, refer to Table 256.
2

8.4.4.2 I C Data validity
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state
or LOW state of the data line shall only change when the clock signal on SCL is LOW.

SDA

SCL
data line stable;
data validchangeof dataallowed001aam300

2

Figure 17. Bit transfer on the I C-bus
2

8.4.4.3 I C START and STOP conditions
2

To handle the data transfer on the I C-bus, unique START (S) and STOP (P) conditions
are defined.
A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL
is HIGH.
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is
HIGH.
The master always generates the START and STOP conditions. The bus is considered to
be busy after the START condition. The bus is considered to be free again a certain timeafter the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
In this respect, the START (S) and repeated START (Sr) conditions are functionallyidentical. Therefore, the S symbol will be used as a generic term to represent both the
START and repeated START (Sr) conditions.

SDA

SDA

SCL

SCL
S

P

START condition

STOP condition
001aam301

Figure 18. START and STOP conditions2

8.4.4.4 I C byte format
Each byte has to be followed by an acknowledge bit. Data is transferred with the
MSB first, see Figure 18. The number of transmitted bytes during one data transfer isunrestricted but shall fulfill the read/write cycle format.

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2

8.4.4.5 I C Acknowledge
An acknowledge at the end of one data byte is mandatory. The acknowledge-related
clock pulse is generated by the master. The transmitter of data, either master or slave,
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull
down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or arepeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not
generating an acknowledge on the last byte that was clocked out by the slave. The slavetransmitter shall release the data line to allow the master to generate a STOP (P) or
repeated START (Sr) condition.
DATA OUTPUTBY TRANSMITTER
not acknowledge
DATA OUTPUTBY RECEIVERER
acknowledge
SCL FROM
MASTER

1

2

8

9

S

clock pulse for
acknowledgement

START
condition

001aam302

2

Figure 19. Acknowledge on the I C- bus

P
MSB

acknowledgement
signal from slaveacknowledgement
signal from receiverSrbyte complete,interrupt within slave
clock line held low whileinterrupts are serviced
S
or
Sr

1

2

7

8

9
ACK

1

2

3-8

9
ACK

Sr
or
P
001aam303

2

Figure 20. Data transfer on the I C- bus
2

8.4.4.6 I C 7-bit addressing
2

During the I C-bus addressing procedure, the first byte after the START condition is used
to determine which slave will be selected by the master.
2

Alternatively the I C address can be configured in the EEPROM. Several address
numbers are reserved for this purpose. During device configuration, the designer has toensure, that no collision with these reserved addresses in the system is possible. Check2
the corresponding I C specification for a complete list of reserved addresses.
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For all CLRC663 devices, the upper 5 bits of the device bus address are reserved by
NXP and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address
2
can be freely configured by the customer in order to prevent collisions with other I C
2devices by using the interface pins (refer to Table 16) or the value of the I C address
EEPROM register (refer to Table 38).
MSB
Bit 6

LSB
Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

slave address

Bit 0

R/W

001aam304

Figure 21. First byte following the START procedure2

8.4.4.7 I C-register write access2

To write data from the host controller via I C to a specific register of the CLRC663, thefollowing frame format shall be used.
The read/write bit shall be set to logic 0.
2

The first byte of a frame indicates the device address according to the I C rules. The
second byte indicates the register address followed by up to n-data bytes. In case theaddress indicates the FIFO, in one frame all n-data bytes are written to the FIFO register
address. This enables for example a fast FIFO access.
2

8.4.4.8 I C-register read accessTo read out data from a specific register address of the CLRC663, the host controller
shall use the procedure:First a write access to the specific register address has to be performed as indicated in
the following frame:
2

The first byte of a frame indicates the device address according to the I C rules. The
second byte indicates the register address. No data bytes are added.
The read/write bit shall be logic 0.
Having performed this write access, the read access starts. The host sends the device
address of the CLRC663. As an answer to this device address, the CLRC663 respondswith the content of the addressed register. In one frame n-data bytes could be readusing the same register address. The address pointing to the register is incremented
automatically (exception: FIFO register address is not incremented automatically).
This enables a fast transfer of register content. The address pointer is incremented
automatically and data is read from the locations [address], [address+1], [address+2]...
[address+(n-1)]
In order to support a fast FIFO data transfer, the address pointer is not incremented
automatically in case the address is pointing to the FIFO.
The read/write bit shall be set to logic 1.

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Write Cycle
I2C slave address
A7-A0

SA

0
(W)

Ack

Frontend IC register
address A6-A0

0

Ack

DATA
[7..0][0..n]

Ack

SO
Read Cycle

I2C slave address
A7-A0

SA

0
(W)

Ack

0

Frontend IC register
address A6-A0

Ack

SO

Optional, if the previous access was on the same register address
0..n
1
(R)

I2C slave address
A7-A0

SA

Ack

[0..n]

sent by master

DATA[7..0]Ack

DATA[7..0]NackSO

sent by slave

001aam305

Figure 22. Register read and write access2

8.4.4.9 I CL-bus interface
The CLRC663 provides an additional interface option for connection of a SAM. This2
logical interface fulfills the I C specification, but the rise/fall timings will not be compliant
22
to the I C standard. The I CL interface uses standard I/O pads, and the communication
speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of2
I C. The SCL levels are generated by the host in push/pull mode. The RC663 does notstretch the clock. During the high period of SCL, the status of the line is maintained by abus keeper.
The address is 01010xxb, where the last two bits of the address can be defined by theapplication. The definition of these bits can be done by two options. With a pin, where
the higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the
EEPROM configuration in Section 8.7.
2

Table 26. Timing parameter I CL

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Parameter

Min

Max

Unit

fSCL

0

5

MHz

tHD;STA

80

-

ns

tLOW

100

-

ns

tHIGH

100

-

ns

tSU;SDA80-

ns

tHD;DAT

050

nstSU;DAT

020

nstSU;STO

80

-

ns

tBUF

200

-

ns

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2

The pull-up resistor is not required for the I CL interface. Instead, a on chip buskeeper
2
is implemented in the CLRC663 for SDA of the I CL interface. This protocol is intended
to be used for a point-to-point connection of devices over a short distance and does
not support a bus capability.The driver of the pin must force the line to the desired
logic voltage. To avoid that two drivers are pushing, the line at the same time following
regulations must be fulfilled:
SCL: As there is no clock stretching, the SCL is always under control of the Master.
SDA: The SDA line is shared between master and slave. Therefore the master and theslave must have the control over the own driver enable line of the SDA pin. The following
rules must be followed:• In the idle phase, the SDA line is driven high by the master• In the time between start and stop condition, the SDA line is driven by master or slavewhen SCL is low. If SCL is high, the SDA line is not driven by any device• To keep the value on the SDA line a on chip, buskeeper structure is implemented forthe line

8.4.5 SAM interface
8.4.5.1 SAM functionality
The CLRC663 implements a dedicated I2C or SPI interface to integrate a MIFARE SAM(Secure Access Module) in a very convenient way into applications (e.g. a proximity
reader).
The SAM can be connected to the microcontroller to operate like a cryptographic
coprocessor. For any cryptographic task, the microcontroller requests an operation fromthe SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface
to the connected reader IC.
The MIFARE SAM supports an optimized method to integrate the SAM in a very
efficient way to reduce the protocol overhead. In this system configuration, the SAM is
integrated between the microprocessor and the reader IC, connected by one interface
to the reader IC and by another interface to the microcontroller. In this application, themicrocontroller accesses the SAM using the T=1 protocol and the SAM accesses thereader IC using an I2C interface. The I2C SAM address is always defined by EEPROM
register. Default value is 0101100. As the SAM is directly communicating with reader IC,
the communication overhead is reduced. In this configuration, a performance boost of up
to 40 % can be achieved for a transaction time.
The MIFARE SAM supports applications using MIFARE product-based cards. For multiapplication purposes, an architecture connecting the microcontroller additionally directly
to the reader IC is recommended. This is possible by connecting the CLRC663 on
one interface (SAM Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/
T1AR1070) and by connecting the microcontroller to the S2C or SPI interface.

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T=1

µC

SAM
AV2.6

I2C

READERIC

I2C

Readeraaa-002963

Figure 23. I2C interface enables convenient MIFARE SAM integration

8.4.5.2 SAM connection
The CLRC663 provides an interface to connect a SAM dedicated to the CLRC663. Both2
2interface options of the CLRC663, I C, I CL or SPI can be used for this purpose. Theinterface option of the SAM itself is configured by a host command sent from the host to
the SAM.
2

The I CL interface is intended to be used as connection between two ICs over a short2
distance. The protocol fulfills the I C specification, but does support a single device
connected to the bus only.
The SPI block for SAM connection is identical with the SPI host interface block.
The pins used for the SAM SPI are described in the following table:
Table 27. SPI SAM connection
SPI functionality

PIN

MISO

SDA2

SCL

SCL2

MOSI

IFSEL1NSSIFSEL08.4.6 Boundary scan interface
The CLRC663 provides a boundary scan interface according to the IEEE 1149.1. This
interface allows testing interconnections without using physical test probes. This is doneby test cells, assigned to each pin, which override the functionality of this pin.
To be able to program the test cells, the following commands are supported:
Table 28. Boundary scan command

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Value(decimal)CommandParameter inParameter out

0bypass--1

preloaddata (24)-2sample-data (24)3

ID code (default)-

data (32)4USER code-

data (32)

5

Clamp

-

-

6

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Table 28. Boundary scan command...continued
Value(decimal)CommandParameter inParameter out

7extestdata (24)data (24)8interface on/off

interface (1)-9register access readaddress (7)data (8)10register access write

address (7) - data (8)-The Standard IEEE 1149.1 describes the four basic blocks necessary to use thisinterface: Test Access Port (TAP), TAP controller, TAP instruction register, TAP dataregister;
8.4.6.1 Interface signals
The boundary scan interface implements a four line interface between the chip and theenvironment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test
Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast
signals, TDI to TDO generate a serial line called Scan path.
Advantage of this technique is that independent of the numbers of boundary scan
devices the complete path can be handled with four signal lines.
The signals TCK, TMS are directly connected with the boundary scan controller. Because
these signals are responsible for the mode of the chip, all boundary scan devices in one
scan path will be in the same boundary scan mode.
8.4.6.2 Test Clock (TCK)The TCK pin is the input clock for the module. If this clock is provided, the test logic
is able to operate independent of any other system clocks. In addition, it ensures thatmultiple boundary scan controllers that are daisy-chained together can synchronously
communicate serial test data between components. During normal operation, TCK
is driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 forextended periods of time. While TCK is stopped at 0 or 1, the state of the boundary scan
controller does not change and data in the Instruction and Data Registers is not lost.
The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking
occurs if the pin is not driven from an external source.
8.4.6.3 Test Mode Select (TMS)
The TMS pin selects the next state of the boundary scan controller. TMS is sampled on
the rising edge of TCK. Depending on the current boundary scan state and the sampledvalue of TMS, the next state is entered. Because the TMS pin is sampled on the risingedge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on thefalling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the boundary scan controller
state machine to the Test-Logic-Reset state. When the boundary scan controller enters
the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instruction,
IDCODE. Therefore, this sequence can be used as a reset mechanism.
The internal pull-up resistor on the TMS pin is enabled.

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8.4.6.4 Test Data Input (TDI)The TDI pin provides a stream of serial information to the IR chain and the DR chains.
TDI is sampled on the rising edge of TCK and, depending on the current TAP state andthe current instruction, presents this data to the proper shift register chain. Because the
TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects thevalue on TDI to change on the falling edge of TCK.
The internal pull-up resistor on the TDI pin is enabled.
8.4.6.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the
DR chains. The value of TDO depends on the current TAP state, the current instruction,and the data in the chain being accessed. In order to save power when the port is not
being used, the TDO pin is placed in an inactive drive state when not actively shifting out
data. Because TDO can be connected to the TDI of another controller in a daisy-chain
configuration, the IEEE Standard 1149.1 expects the value on TDO to change on thefalling edge of TCK.
8.4.6.6 Data register
According to the IEEE1149.1 standard, there are two types of data register defined:
bypass and boundary scan
The bypass register enable the possibility to bypass a device when part of the scanpath.Serial data is allowed to be transferred through a device from the TDI pin to the
TDO pin without affecting the operation of the device.
The boundary scan register is the scan-chain of the boundary cells. The size of thisregister is dependent on the command.
8.4.6.7 Boundary scan cell
The boundary scan cell opens the possibility to control a hardware pin independent of its
normal use case. Basically the cell can only do one of the following: control, output andinput.

TDI

TAP
TCK

IC2

LOGIC

Boundary scan cell

LOGIC

IC1

TDO

TDI

TMS

TAP
TCK

TDO
TMS
001aam306

Figure 24. Boundary scan cell path structure

8.4.6.8 Boundary scan path
This chapter shows the boundary scan path of the CLRC663.

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Table 29. Boundary scan path of the CLRC663
Number (decimal)

Cell

Port

Function

23

BC_1

-

Control22

BC_8

CLKOUT

Bidir

21

BC_1

-

Control

20

BC_8

SCL2

Bidir

19

BC_1

-

Control

18

BC_8

SDA2

Bidir

17

BC_1

-

Control

16

BC_8

IFSEL0

Bidir

15

BC_1

-

Control

14

BC_8

IFSEL1

Bidir

13

BC_1

-

Control

12

BC_8

IF0

Bidir

11

BC_1

-

Control

10

BC_8

IF1

Bidir

9

BC_1

-

Control

8

BC_8

IF2

Bidir

7

BC_1

IF2

Output2

6

BC_4

IF3

Input

5

BC_1

-

Control

4

BC_8

IRQ

Bidir

3

BC_1

-

Control

2

BC_8

SIGIN

Bidir

1

BC_1

-

Control0

BC_8

SIGOUT

Bidir

Refer to the CLRC663 BSDL file.
8.4.6.9 Boundary Scan Description Language (BSDL)All of the boundary scan devices have a unique boundary structure which is necessary toknow for operating the device. Important components of this language are:• available test bus signal• compliance pins• command register• data register• boundary scan structure (number and types of the cells, their function and theconnection to the pins.)
2

The CLRC663 is using the cell BC_8 for the IO-Lines. The I C Pin is using a BC_4 cell.
For all pad enable lines, the cell BC1 is used.
The manufacturer's identification is 02Bh.
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• attribute IDCODEISTER of CLRC663: entity is "0001" and -- version• "0011110010000010b" and -- part number (3C82h)• "00000010101b" and -- manufacturer (02Bh)• "1b"; -- mandatory
The user code data is coded as followed:• product ID (3 bytes)• version
These four bytes are stored as the first four bytes in the EEPROM.
8.4.6.10 Non-IEEE1149.1 commands
Interface on/offWith this command, the host/SAM interface can be deactivated and the Read and Writecommand of the boundary scan interface is activated. (Data = 1). With Update-DR, thevalue is taken over.
Register Access ReadAt Capture-DR, the actual address is read and stored in the DR. Shifting the DR isshifting in a new address. With Update-DR, this address is taken over into the actual
address.
Register Access Write
At the Capture-DR, the address and the data is taken over from the DR. The data is
copied into the internal register at the given address.

8.5 Buffer
8.5.1 Overview
A 512 × 8-bit FIFO buffer is implemented in the CLRC663. It buffers the input and output
data stream between the host and the internal state machine of the CLRC663. Thus, it
is possible to handle data streams with lengths of up to 512 bytes without taking timing
constraints into account. The FIFO can also be limited to a size of 255 bytes. In this case
all the parameters (FIFO length, Watermark...) require a single byte only for definition. In
case of a 512 byte FIFO length, the definition of this value requires 2 bytes.

8.5.2 Accessing the FIFO buffer
When the μ-Controller starts a command, the CLRC663 may, while the command is inprogress, access the FIFO-buffer according to that command. Physically only one FIFObuffer is implemented, which can be used in input and output direction. Therefore the μController has to take care, not to access the FIFO buffer in a way that corrupts the FIFO
data.

8.5.3 Controlling the FIFO buffer
Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might bereset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits
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are set to logic 0, the actually stored bytes are not accessible any more and the FIFO
buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)
again.

8.5.4 Status Information about the FIFO buffer
The host may obtain the following data about the FIFO-buffers status:• Number of bytes already stored in the FIFO-buffer. Writing increments, reading
decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl
Register in 512 byte mode)• Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according
to the value of the water level in register WaterLevel (Register 02h bit [2], Register 03h
bit[7:0])• Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl
according to the value of the water level in register WaterLevel (Register 02h bit [2],Register 03h bit[7:0])• FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was alreadyfull: ErrIRQ in register IRQ0.
WaterLevel is one single value defining both HiAlert (counting from the FIFO top) andLoAlert (counting from the FIFO bottom). The CLRC663 can generate an interrupt signal
if:• LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert in
the register FIFOControl changes to 1.
• HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert in
the register FIFOControl changes to 1.
The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register
WaterLevel) or less can be stored in the FIFO-buffer. It is generated according to thefollowing equation:(2)
The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or lessare actually stored in the FIFO-buffer. It is generated according to the following equation:(3)

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8.6 Analog interface and contactless UART
8.6.1 General
The integrated contactless UART supports the external host online with framing anderror checking of the protocol requirements up to 848 kbit/s. An external circuit can beconnected to the communication interface pins SIGIN and SIGOUT to modulate anddemodulate the data.
The contactless UART handles the protocol requirements for the communication
schemes in co-operation with the host. The protocol handling itself generates bit- andbyte-oriented framing and handles error detection like Parity and CRC according to thedifferent contactless communication schemes.
The size, the tuning of the antenna, and the supply voltage of the output drivers have an
impact on the achievable field strength. The operating distance between reader and carddepends additionally on the type of card used.

8.6.2 TX transmitter
The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz carrier modulated by anenvelope signal for energy and data transmission. It can be used to drive an antenna
directly, using a few passive components for matching and filtering, see Section 14. The
signal on TX1 and TX2 can be configured by the register DrvMode, see Section 9.8.1.
The modulation index can be set by the TxAmp.
Following figure shows the general relations during modulationinfluenced by set_clk_mode

envelope

TX ASK100

TX ASK10(1)(2)

1: Defined by set_cw_amplitude.
2: Defined by set_residual_carrier.

time
001aan355

Figure 25. General dependences of modulation

Note: When changing the continuous carrier amplitude, the residual carrier amplitude
also changes, while the modulation index remains the same.
The registers Section 9.8 and Section 9.10 control the data rate, the framing duringtransmission and the setting of the antenna driver to support the requirements at thedifferent specified modes and transfer speeds.
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Table 30. Settings for TX1 and TX2
TxClkMode(binary)

Tx1 and TX2 output

Remarks

000

High impedance

-

001

0

output pulled to 0 in any case010

1

output pulled to 1 in any case110

RF high side pushopen-drain, only high side (push) MOS suppliedwith clock, clock parity defined by invtx; lowside MOS is off

101

RF low side pullopen-drain, only low side (pull) MOS suppliedwith clock, clock parity defined by invtx; highside MOS is off

111

13.56 MHz clock derived
from 27.12 MHz quartz
divided by 2

push/pull Operation, clock polarity defined by
invtx; setting for 10 % modulation

Register TXamp and the bits for set_residual_carrier define the modulation index:
Table 31. Setting residual carrier and modulation index by
TXamp.set_residual_carrier

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set_residual_carrier (decimal) residual carrier [%]modulation index [%]

0

99

0.5

1

98

1.0

2

96

2.0

3

94

3.1

4

91

4.7

5

89

5.8

6

87

7.0

7

86

7.5

8

85

8.1

9

84

8.7

10

83

9.3

11

82

9.9

12

81

10.5

13

80

11.1

14

79

11.7

15

78

12.4

16

77

13.0

17

76

13.6

18

75

14.3

19

74

14.9

20

72

16.3

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Table 31. Setting residual carrier and modulation index by
TXamp.set_residual_carrier...continued
set_residual_carrier (decimal) residual carrier [%]modulation index [%]

21

70

17.6

22

68

19.0

23

65

21.2

24

60

25.0

25

55

29.0

26

50

33.3

27

45

37.9

28

40

42.9

29

35

48.1

30

30

53.8

31

25

60.0

Note: At VDD(TVDD) <5 V and residual carrier settings <50 %, the accuracy of themodulation index may be low in dependency of the antenna tuning impedance
8.6.2.1 Overshoot protection
The CLRC663 provides an overshoot protection for 100 % ASK to avoid overshoots
during a PCD communication. Therefore two timers overshoot_t1 and overshoot_t2 canbe used.
During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits isprovided to the output driver. Followed by an amplitude denoted by set_residual_carrier
bits with the duration of overshoot_t2.
7.0
(V)
5.0

3.0

1.0

-1.0
2.50

3.03

3.56

4.10
time ( s)001aan356

Figure 26. Example 1: overshoot_t1 = 2d; overhoot_t2 = 5d.

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7.0
(V)
5.0

3.0

1.0

-1.0

0

1

2

3

4

time ( s)5001aan357

Figure 27. Example 2: overshoot_t1 = 0d; overhoot_t2 = 5d

8.6.2.2 Bit generator
The default coding of a data stream is done by using the Bit-Generator. It is activatedwhen the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator
encodes the data stream byte-wise and can apply the following encoding steps to eachdata byte.
1. Add a start-bit of specified type at beginning of every byte
2. Add a stop-bit and EGT bits of a specified type. The maximum number of EGT bit is 6,
only full bits are supported
3. Add a parity-bit of a specified type
4. TxLastBits (skips a given number of bits at the end of the last byte in a frame)
5. Encrypt data-bit (MIFARE Classic encryption)
It is not possible to skip more than 8 bit of a single byte!
By default, data bytes are always treated LSB first.

8.6.3 Receiver circuitry
8.6.3.1 General
The CLRC663 features a versatile quadrature receiver architecture with fully differential
signal input at RXP and RXN. It can be configured to achieve optimum performance forreception of various 13.56 MHz based protocols.
For all processing units various adjustments can be made to obtain optimum
performance.
8.6.3.2 Block diagram
The following figure shows the block diagram of the receiver circuitry. The receiving
process includes several steps. First the quadrature demodulation of the carrier signal of
13.56 MHz is done. Several tuning steps in this circuit are possible.

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fully/quasi-differential

rcv_hpcf<1:0>
rcv_gain<1:0>

rx_p

mixer

rx_n

mix_out_i_p

out_i_p

mix_out_i_n

out_i_n2-stage BBA

I-clksrx_p
rx_n

13.56 MHzI/O CLOCKGENERATION

clk_27 MHz

DATA

TIMING
GENERATION
ADC

clk_27 MHz

Q-clksrx_p

mix_out_q_p

rx_n

mix_out_q_n2-stage BBA

out_q_p

Adc_data_readyDATA

out_q_n

mixer

rcv_gain<1:0>
fully/quasi-differential

rcv_hpcf<1:0>001aan358

Figure 28. Block diagram of receiver circuitry

The receiver can also be operated in a single ended mode. In this case, the
Rcv_RX_single bit has to be set. In the single ended mode, the two receiver pins RXP
and RXN need to be connected together and will provide a single ended signal to thereceiver circuitry.
When using the receiver in a single ended mode, the receiver sensitivity is decreased
and the achievable reading distance might be reduced, compared to the fully differential
mode.
Table 32. Configuration for single or differential receiverMode

rcv_rx_single

pins RXP and RXN

Fully differential

0

provide differential signal from differential antenna byseparate rx-coupling branches

Quasi differential

1

connect RXP and RXN together and provide single
ended signal from antenna by a single rx-couplingbranchThe quadrature-demodulator uses two different clocks, Q-clock and I-clock, with aphase shift of 90° between them. Both resulting baseband signals are amplified, filtered,digitized and forwarded to a correlation circuitry.
The typical application is intended to implement the Fully differential mode andwill deliver maximum reader/writer distance. The Quasi differential mode can beused together with dedicated antenna topologies that allow a reduction of matchingcomponents at the cost of overall reading performance.
During low-power card detection the DC levels at the I- and Q-channel mixer outputs
are evaluated. This requires that mixers are directly connected to the ADC. This can be
configured by setting the bit Rx_ADCmode in register Rcv (38h).

8.6.4 Active antenna concept
Two main blocks are implemented in the CLRC663. A digital circuitry, comprising statemachines, coder and decoder logic and an analog circuitry with the modulator andantenna drivers, receiver and amplification circuitry. For example, the interface between
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these two blocks can be configured in the way, that the interfacing signals may be routed
to the pins SIGIN and SIGOUT. The most important use of this topology is the active
antenna concept where the digital and the analog blocks are separated. This opens thepossibility to connect e.g. an additional digital block of another CLRC663 device with asingle analog antenna frontend.
READER IC(DIGITAL)SIGIN

SIGOUTSIGOUT

SIGIN

READER IC(ANTENNA)
001aam307

Figure 29. Block diagram of the active Antenna concept

The Table 33and Table 34 describe the necessary register configuration for the use caseactive antenna concept.
Table 33. Register configuration of CLRC663 active antenna concept (DIGITAL)
Register

Value (binary)

Description

SigOut.SigOutSel

0100

TxEnvelope

Rcv.SigInSel

10
11

Receive over SigIn (ISO/IEC14443A)
Receive over SigIn (Generic Code)

DrvCon.TxSel

00

Low (idle)

Table 34. Register configuration of CLRC663 active antenna concept (Antenna)
Register

Value (binary)

Description

SigOut.SigOutSel

0110
0111

Generic Code (Manchester)Manchester with Subcarrier (ISO/IEC14443A)

Rcv.SigInSel

01

Internal

DrvCon.TxSel

10

External (SigIn)

RxCtrl.RxMultiple

1

RxMultiple on

The interface between these two blocks can be configured in the way, that the interfacing
signals may be routed to the pins SIGIN and SIGOUT (see Figure 30).
This topology supports, that some parts of the analog part of the CLRC663 may beconnected to the digital part of another device.
The switch SigOutSel in registerSigOut can be used to measure signals. This isespecially important during the design-in phase or for test purposes to check thetransmitted and received data.
However, the most important use of SIGIN/SIGOUT pins is the active antenna concept.
An external active antenna circuit can be connected to the digital circuit of the CLRC663.
SigOutSel has to be configured in that way that the signal of the internal Miller Coderis sent to SIGOUT pin (SigOutSel = 4). SigInSel has to be configured to receive
Manchester signal with subcarrier from SIGIN pin (SigInSel = 1).
It is possible, to connect a passive antenna to pins TX1, TX2 and RX (via the appropriate
filter and matching circuit) and at the same time an active antenna to the pins SIGOUT
and SIGIN. In this configuration, two RF-parts may be driven (one after another) by asingle host processor.
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SIGOUT

TX bit stream

tri-state
LOW
HIGH
TX envelope
TX active
S3C signal
RX envelope
RX active
RX bit signal

CODER

DIGITAL MODULE

RX bit stream

DECODER0
1
2
Sigpro_in_sel 3
[1:0]

0, 1
2
SIGOUTSel[4:0]
3
4
5
6
7
8
9

tri-stateinternal analog block
SIGIN over envelope
SIGIN generic

No_nodulation
TX envelope
SIGIN
RFU

0
1
2
3 TxCon.TxSel[1:0]

MODULATORDRIVER

TX2
TX1

ANALOG MODULESUBCARRIER
DEMODULATORDEMODULATOR

SIGIN

RXN
RXP

001aam001

Figure 30. Overview SIGIN/SIGOUT Signal Routing

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8.6.5 Symbol generator
The symbol generator is used to create various protocol symbols. These can be e.g.
SOF or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol
symbols like the CS symbol as used by the ICODE EPC protocol.
Symbols are defined by means of the symbol definition registers and the mode registers.
Four different symbols can be used. Two of them, Symbol0 and Symbol1 have amaximum pattern length of 16 bit and feature a burst length of up to 256 bits of either
logic "0" or logic "1". The Symbol2 and Symbol3 are limited to 8-bit pattern length and do
not support a burst.
The definition of symbol patterns is done by writing the bit sequence of the pattern tothe appropriate register. The last bit of the pattern to be sent is located at the LSB ofthe register. By setting the symbol length in the symbol-length register (TxSym10Len
and TxSym32Len), the definition of the symbol pattern is completed. All other bits at bitposition higher than the symbol length in the definition register are ignored. (Example:
length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define the symbol pattern,
bit5 is sent first)
Which symbol-pattern is sent can be configured in the TxFrameCon register. Symbol0,
Symbol1 and Symbol2 can be sent before data packets, Symbol1, Symbol2 and Symbol3
can be sent after data packets. Each symbol is defined by a set of registers. Symbols are
configured by a pair of registers. Symbol0 and Symbol1 share the same configurationand Symbol2 and Symbol3 share the same configuration. The configuration includes
setting of bit-clock- and subcarrier-frequency, as well as selection of the pulse type/lengthand the envelope type.

8.7 Memory
8.7.1 Memory overview
The CLRC663 implements three different memories: EEPROM, FIFO and Registers.
At startup, the initialization of the registers which define the behavior of the IC is
performed by an automatic copy of an EEPROM area (read/write EEPROM section1
and section2, register reset) into the registers. The behavior of the CLRC663 can bechanged by executing the command LoadProtocol, which copies a selected default
protocol from the EEPROM (read-only EEPROM section4, register Set Protocol area)
into the registers.
The read/write EEPROM section2 can be used to store any user data or predefined
register settings. These predefined settings can be copied with the command"LoadRegister" into the internal registers.
The FIFO is used as Input/Out buffer and is able to improve the performance of a systemwith limited interface speed.

8.7.2 EEPROM memory organization
The CLRC663 has implemented an EEPROM non-volatile memory with a size of 8
kB. The EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be
programmed at a time. Defined purposes had been assigned to specific memory areas
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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plusof the EEPROM, which are called Sections. Five sections 0..4 with different purpose do
exist.
Table 35. EEPROM memory organization
SectionPage

Byte
addresses

AccessrightsMemory content

0000 to 31r

product information and configuration

32 to 63r/w

product configuration

1

1 to 264 to 191

r/w

register reset2

3 to 95

192 to 6143

r/w

free

3

96 to 111

6144 to 7167

w

MIFARE Classic key

4

112 to 127

7168 to 8191

r

Register Set Protocol (RSP)The following figure shows the structure of the EEPROM:
Section 0:

Production and config

Section 1:

Register reset

Section 2:

Free

Section 3:

MIFARE Classic
key area (MKA)

Section 4_TX:

RSP-Area for TX

Section 4_RX:

RSP-Area for RX
001aan359

Figure 31. Sector arrangement of the EEPROM

8.7.2.1 Product information and configuration - Page 0
The first EEPROM page includes production data as well as configuration information.
Table 36. Production area (Page 0)
Address(Hex.)

0

100

ProductID08

Unique Identifier

10

ManufacturerData

18

ManufacturerData

2

3

4

5

VersionUnique Identifier

6

7

Manufacturer
Data

ProductID: Identifier for this CLRC663 product or derivative, only address 01h shall be
evaluated for identifying the Product CLRC663, address 00h and 02h shall be ignored bysoftware.
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Please note, that the silicon version CLRC66301, CLRC66302, CLRC66303 andderivatives can be identified on register address 7Fh, it is not coded in the EEPROM
production area.
Table 37. Product ID overview of CLRC663 family
Address 01h

Product ID

CLRC66301h

MFRC631C0h

MFRC63080h

SLRC61020h

Version: This register indicates the version of the EEPROM initialization data during
production.
Unique IDentifier: Unique serial number code for this device
Manufacturer Data: This data is programmed during production. The content is notintended to be used by any application and might not be constant for different devices.
Therefore the content needs to be considered to be undefined.
Table 38. Configuration area (Page 0)
Address 0(Hex.)
2

20

I C_Address

28

RxCRCPreset

30

-

38

-

1

2

Interface

3

4

5

6

I C SAM_Address DefaultProtRx

DefaultProtTx-

TxCRCPreset

-

-

-

-

2

-

7

-

2

I C-Address2

Two possibilities exist to define the address of the I C interface. This can be done either
by configuring the pins IF0, IF2 (address is then 10101xx, xx is defined by the interface
2
pins IF0, IF2) or by writing value into the I C address area. The selection, which of this2
2-information pin configuration or EEPROM content - is used as I C-address is done at
EEPROM address 21h (Interface, bit4)
InterfaceThis section describes the interface byte configuration.
Table 39. Interface byte
Bit
access rights

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7

6

5

4

3

2

2

I C_HSP--I2C_Address

Boundary Scan

Host

r/w

RFU

RFU

r/w

r/w

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Table 40. Interface bits
Bit

SymbolDescription

7

2

I C_HSP

when cleared, the high-speed mode is used
when set, the high speed+ mode is used (default)

6, 5

RFU

-

4

I C_Address2

when cleared, the pins are used (default)
when set, the EEPROM is used3

Boundary
Scanwhen set, the boundary scan interface is ON (default)
when cleared, the boundary scan is OFF

2 to 0Host

000b - RS232
2001b - I C
010b - SPI
2
011b - I CL
1xxb - pin selection

2

I C_SAM_Address
2

The I C SAM Address is always defined by the EEPROM content.
The Register Set Protocol (RSP) Area contains settings for the TX registers (16 bytes)
and for the RX registers (8 bytes).
Table 41. Tx and Rx arrangements in the register set protocol area
SectionSection 4 TX

Tx0

Tx1

TX2

Tx3

Section 4 TX

Tx4

Tx5

TX6

TX7

Section 4 Rx

RX0

RX1

RX2

RX3

RX4

RX5

RX6

RX7

Section 4 Rx

RX8

RX9

RX10

RX11

RX12

RX13

RX14

RX15

TxCrcPreset
The data bits are sent by the analog module and are automatically extended by a CRC.

8.7.3 EEPROM initialization content LoadProtocol
The CLRC663 EEPROM is initialized at production with values which are used to reset
certain registers of the CLRC663 to default settings by copying the EEPROM content
to the registers. Only registers or bits with "read/write" or "dynamic" access rights are
initialized with this default values copied from the EEPROM.
Note that the addresses used for copying reset values from EEPROM to registers are
dependent on the configured protocol and can be changed by the user.
Table 42. Register reset values (Hex.) (Page0)
Address0 (8)Function

Product ID

00

XX

Function

Unique Identifier

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1 (9)

2 (A)

see table 34 XX

3 (B)

4 (C)

5 (D)

VersionUnique Identifier

XX

XX

XX

6 (E)

7 (F)

XX

XX
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Table 42. Register reset values (Hex.) (Page0)...continued
Address

0 (8)

1 (9)

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

7 (F)

08

XX

XX

XX

XX

XX

XX

XX

XX

Function

TrimLFO

Factory trim values

10

XX

XX

XX

XX

XX

XX

XX

XX

Function

Factory trim values

18....

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

Factory trim values....38XXXX

The register reset values are configuration parameters used after startup of the IC.
They can be changed to modify the default behavior of the device. In addition to theseregister reset values, is the possibility to load settings for various users implemented
protocols.The load protocol command is used for this purpose.
Table 43. Register reset values (Hex.)(Page1 and page 2)
Address
40

48

50

58

60

68

70

78

0 (8)

1 (9)

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

7 (F)

Command

HostCtrl

FiFoControl

WaterLevel

FiFoLength

FiFoData

IRQ0

IRQ1

40

00

80

05

00

00

00

00

IRQ0EnIRQ1EnError

StatusRxBitCtrl

RxCollTControlT0Control

10

00

00

00

00

00

00

00

T0ReloadHi T0ReloadLo T0Counter
ValHi

T0Counter
ValLo

T1Control

T1ReloadHi T1ReloadLo T1Counter
ValHi

00

80

00

00

00

00

80

00

T1Counter
ValLo

T2Control

T2ReloadHi T2ReloadLo T2Counter
ValHi

T2Counter
ValLo

T3Control

T3ReloadHi

00

00

00

80

00

00

00

00

T3ReloadLo T3Counter
ValHi

T3Counter
ValHi

T4Control

T4ReloadHi T4ReloadLo T4Counter
ValHi

T4Counter
ValLo

80

00

00

00

00

80

00

00

DrvModeTxAmp

DrvConTxl

TxCRC
PresetRxCRC
PresetTxDataNum TxModWith

86

15

11

06

18

18

08

27

TxSym10
BurstLen

TxWaitCtrl

TxWaitLo

FrameConRxSofD

RxCtrlRxWaitRxThres
hold

00

C0

12

CF

00

04

90

3F

Rcv

RxAna

RFU

SerialSpeed LFO_trimm

PLL_Ctrl

PLL_Div

LPCD_QMin

12

0A

00

7A

80

04

20

48

LPCD_
QMax

LPCD_IMin

LPCD _
result_I

LPCD _
result_Q

PadEn

PadOutPadIn

SigOut

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Table 43. Register reset values (Hex.)(Page1 and page 2)...continued
Address

0 (8)

1 (9)

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

7 (F)

80

12

88

00

00

00

00

00

00

TxBitModRFU

TxDataCon

TxDataMod

TxSymFreq

TxSym0H

TySym0L

TxSym1H

20

xx

04

50

40

00

00

00

TxSym1L

TxSym2

TxSym3TxSym10Le TxSym32Le TxSym32Bu TxSym10M
ngth
ngth
rstCtrlod

TxSym32M
od

0x00

0x00

0x00

0x00

0x00

0x50

RxBitModRxEOFSym RxSyncValH RxSyncValL RxSyncMod RxMod

RXCorrFabCal

0x02

0x00

0x08

0xB2

88

90

98

0x00

0x01

0x00

0x00

0x00

0x08

8.8 Clock generation
8.8.1 Crystal oscillator
The clock applied to the CLRC663 acts as time basis for generation of the carrier sentout at TX and for the quadrature mixer I and Q clock generation as well as for the coderand decoder of the synchronous system. Therefore stability of the clock frequency is an
important factor for proper performance. To obtain highest performance, clock jitter has tobe as small as possible. This is best achieved by using the internal oscillator buffer withthe recommended circuitry.
READER IC
XTAL1

XTAL2

27.12 MHz

001aam308

Figure 32. Crystal connection

Table 44. Crystal requirements recommendations

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SymbolParameter

fxtal

Conditions

Min

Typ

max

Unit

crystal frequency

-

27.12

-

MHz

Δfxtal/fxtal

relative crystal
frequency variation

-250

-

+250

ppm

ESR

equivalent series
resistance

-

50

100

Ω

CL

load capacitance

-

10

-

pF

Pxtal

crystal power
dissipation

-

50

100

μW

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8.8.2 IntegerN PLL clock line
The CLRC663 is able to provide a clock with configurable frequency at CLKOUT from
1 MHz to 24 MHz (PLL_Ctrl and PLL_DIV). There it can serve as a clock source to a
microcontroller which avoids the need of a second crystal oscillator in the reader system.
Clock source for the IntegerN-PLL is the 27.12 MHz crystal oscillator.
Two dividers are determining the output frequency. First a feedback integer-N divider
configures the VCO frequency to be N × fin/2 (control signal pll_set_divfb). As supported
Feedback Divider Ratios are 23, 27 and 28, VCO frequencies can be 23 × fin / 2 (312MHz), 27 × fin / 2 (366 MHz) and 28 × fin / 2 (380 MHz).
The VCO frequency is divided by a factor which is defined by the output divider(pll_set_divout). The following table shows the accuracy achieved for various frequencies(integer multiples of 1 MHz and some typical RS232 frequencies) and the divider ratios to
be used. The register bit ClkOutEn enables the clock at CLKOUT pin.
The following formula can be used to calculate the output frequency:
fout = 13.56 MHz × PLLDiv_FB /PLLDiv_Out
Table 45. Divider values for selected frequencies using the integerN PLL
Frequency [MHz]

4

6

8

10

12

20

24

1.84323.6864

PLLDiv_FB

23

27

23

28

23

28

23

28

28

PLLDiv_Out

78

61

39

38

26

19

16

206

103

accuracy [%]

0.04

0.03

0.04

0.08

0.04

0.08

0.04

0.01

0.01

8.8.3 Low Frequency Oscillator (LFO)
The CLRC663 family implements an Low-Frequency Oscillator (LFO). Timer T4 can be
configured to use a clock generated by this LFO as input clock, and can be configured
as wakeup counter. As wakeup counter, the timer T4 allows to wake up the system in
regular time intervals which allows to design a reader that is regularly polling for cardpresence or implements a low-power card detection (LPCD).
The LFO is trimmed during chip production to run at 16 kHz. Unless a high accuracyof the LFO is required by the application, and the device is operated in an environment
with changing ambient temperatures, trimming of the LFO is not required. For a typicalapplication making use of the LFO for wake-up from power saving mode, the trim value
set during production can be used.
Optional trimming to achieve a higher accuracy of the 16 kHz LFO clock is supported bya digital state machine which compares LFO-clock to a reference clock generated by theconnected 27.12Mhz crystal. As reference clock frequency for trimming of the LFO, a
13.56 MHz clock (27.12Mhz divided by 2 ) input clock to one of the timers T0,T1,T2 or T3
is used.
One of the timers T0,T1,T2,T3 with an input clock of 13,56 MHz crystal clock is used tocount one clock period of the LFO. For an LFO Clock running at 16KHz this would resultin 848 wakeup timer clocks of timer Tx (T0, T1, T2, T3). Therefrore, the timer count value
Tx at the end of a trimming cycle is expected to be 176 (wakeup timer is counting down:
1023-848=175, +/- 1 tolerance is accepted). The trim cycle is executed once in the T4
timer cycle. Therefore the T4 autoload value shall be bigger than 0x05 to ensure that
one trimming cycle takes place before T4 expires. The Tx timer value is reloaded to 1023

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during the start of an Auto trim cycle. This happens every time, once after the T4 timer
underflows.
At the end of each trim cycle, the timer value is checked:• Timer Tx value < 174: LFO Frequency is too low and the trim value is incremented by 1
on T4 Timer event• Timer Tx value > 176: LFO Frequency is too high and the trim value is decremented by
1 on T4 Timer event• Timer Tx value is within 174 and 176: LFO Frequency = 16 KHz and trimming
procedure is stopped
The cycle proceeds until the autotrimm function is stopped (Timer Tx value is within 174
and 176).
In addition, the trimming cycle can be aborted by sending an IDLE Command from thehost to cancel the current command execution. T3 is not allowed to be used in case
T4AutoLPCD is set in parallel. It is not required to configure a TXStart condition with
underflow. The T0/1/2/3 timer will typically not underflow. It may happen if the LPO clock
is very slow, but it is not required to take an action to generate this event.

8.9 Power management
8.9.1 Supply concept
The CLRC663 is supplied by VDD (Supply Voltage), PVDD (Pad Supply) and TVDD
(Transmitter Power Supply). These three voltages are independent from each other.
To connect the CLRC663 to a Microcontroller supplied by 3.3 V, PVDD and VDD shall be
at a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at
TVDD results in a higher field strength.
Independent of the voltage it is recommended to buffer these supplies with blocking
capacitances close to the terminals of the package. VDD and PVDD are recommended tobe blocked with a capacitor of 100 nF min, TVDD is recommended to be blocked with 2
capacitors, 100 nF parallel to 1.0 μF
AVDD and DVDD are not supplied input pins. They are output pins and shall beconnected to blocking capacitors 470 nF each.

8.9.2 Power reduction mode
8.9.2.1 Power-down
A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal
1.8 V voltage regulators for the analog and digital core supply as well as the oscillator.
All digital input buffers are separated from the input pads and clamped internally (except
pin PDOWN itself). The output pins are switched to high impedance. HardPowerDown isperforming a reset of the IC. All registers will be reset, the Fifo will be cleared.
To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This
starts the internal start-up sequence.

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8.9.2.2 Standby mode
The standby mode is entered immediately after setting the bit PowerDown in the register
Command. All internal current sinks are switched off. Voltage references and voltage
regulators are set into standby mode.
In opposition to the power-down mode, the digital input buffers are not separated by the
input pads and keep their functionality. The digital output pins do not change their state.
During standby mode, all registers values, the FIFO’s content and the configuration itself
keeps its current content.
To leave the standby mode, the bit PowerDown in the register Command is cleared. This
triggers the internal start-up sequence. The reader IC is in full operation mode again
when the internal start-up sequence is finalized.
A value of 55h must be sent to the CLRC663 using the RS232 interface to leave the2standby mode. This is must at RS232, but cannot be used for the I C/SPI interface. Then
read accesses shall be performed at address 00h until the device returns the content of
this address. The return of the content of address 00h indicates that the device is readyto receive further commands and the internal start-up sequence is finalized.
8.9.2.3 Modem off mode
When the ModemOff bit in the register Control is set the antenna transmitter and thereceiver are switched off.
To leave the modem off mode, clears the ModemOff bit in the register Control.

8.9.3 Low-Power Card Detection (LPCD)
The low-power card detection is an energy saving mode in which the CLRC663 is not
fully powered permanently.
The LPCD works in two phases. First the standby phase is controlled by the wake-up
counter (WUC), which defines the duration of the standby of the CLRC663. Second
phase is the detection-phase. In this phase, the values of the I and Q channel aredetected and stored in the register map. (LPCD_I_Result, LPCD_Q_Result).This time
period can be handled with Timer3. The value is compared with the min/max values in
the registers (LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax). If it exceeds thelimits, an LPCDIRQ is raised.
After the command LPCD the standby of the CLRC663 is activated, if selected.
The wake-up Timer4 can activate the system after a given time. For the LPCD, it isrecommended to set T4AutoWakeUp and T4AutoRestart, to start the timer and then go tostandby. If a card is detected, the communication can be started. If T4AutoWakeUp is not
set, the IC will not enter Standby mode in case no card is detected.

8.9.4 Reset and start-up time
A 10 μs constant high level at the PDOWN pin starts the internal reset procedure.
The following figure shows the internal voltage regulator:

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VDD
PVDD

1.8 V
GLITCHFILTER

PDown

INTERNAL VOLTAGE
REGULATOR
1.8 V

VSS

AVDD

DVDD

VSS
001aan360

Figure 33. Internal PDown to voltage regulator logic

When the CLRC663 has finished, the reset phase and the oscillator has entered a stableworking condition the IC is ready to be used.

8.10 Command set
8.10.1 General
The behavior is determined by a state machine capable to perform a certain set ofcommands. By writing a command-code to the command register, the command is
executed.
Arguments and/or data necessary to process a command, are exchanged via the FIFO
buffer.
• Each command that needs a certain number of arguments will start processing only
when it has received the correct number of arguments via the FIFO buffer.
• The FIFO buffer is not cleared automatically at command start. It is recommended towrite the command arguments and/or the data bytes into the FIFO buffer and start thecommand afterwards.
• Each command may be stopped by the host by writing a new command code into thecommand register e.g.: the Idle-Command.

8.10.2 Command set overview
Table 46. Command set
CommandNo.

Parameter (bytes)

Short description

Idle

00h

-

no action, cancels current command execution

LPCD

01h

-

low-power card detection

LoadKey02h(keybyte1),(keybyte2), (keybyte3),(keybyte4), (keybyte5),(keybyte6);

reads a MIFARE Classic key (size of 6 bytes) from
FIFO buffer ant puts it into Key buffer

MFAuthent

03h60h or 61h, (block address), (cardserial number byte0),(card serial
number byte1), (card serial number
byte2),(card serial number byte3);

performs the MIFARE Classic authentication

AckReq04h-

performs a query, an Ack and a Req-Rn for ISO/IEC
18000-3 mode 3/ EPC Class-1 HF

Receive05h-

activates the receive circuit

Transmit

06h

bytes to send: byte1, byte2,....

transmits data from the FIFO buffer

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Table 46. Command set...continued
CommandNo.

Parameter (bytes)

Short description

Transceive

07h

bytes to send: byte1, byte2,....

transmits data from the FIFO buffer and automatically
activates the receiver after transmission finished

WriteE208h

addressH, addressL, data;

gets one byte from FIFO buffer and writes it to theinternal EEPROM

WriteE2Page

09h(page Address), data0,[data1 ..data63];

gets up to 64 bytes (one EEPROM page) from the FIFO
buffer and writes it to the EEPROM

ReadE20Ah

addressH, address L, length;

reads data from the EEPROM and copies it into the
FIFO buffer

LoadReg

0Ch(EEPROM addressH), (EEPROM
addressL), RegAdr, (number ofRegister to be copied);reads data from the internal EEPROM and initializes
the CLRC663 registers. EEPROM address needs to bewithin EEPROM sector 2

LoadProtocol

0Dh(Protocol number RX), (Protocol
number TX);

reads data from the internal EEPROM and initializes the
CLRC663 registers needed for a Protocol change

LoadKeyE2

0Eh

KeyNr;

copies a key from the EEPROM into the key bufferStoreKeyE2

0Fh

KeyNr, byte1,byte2, byte3, byte4,
byte5,byte6;

stores a MIFARE Classic key (size of 6 bytes) into the
EEPROM

ReadRNR

1Ch-

Copies bytes from the Random Number generator into
the FIFO until the FiFo is fullSoft Reset

1Fh-

resets the CLRC663

8.10.3 Command functionality
8.10.3.1 Idle command
Command (00h);
This command indicates that the CLRC663 is in idle mode. This command is also used toterminate the actual command.
8.10.3.2 LPCD command
Command (01h);
This command performs a low-power card detection and/or an automatic trimming of
the LFO. After wake-up from standby, the values of the sampled I and Q channels arecompared with the min/max threshold values in the registers. If it exceeds the limits, an
LPCD_IRQ will be raised. After the LPCD command the standby is activated, if selected.
8.10.3.3 Load key command
Command (02h), Parameter1 (key byte1),..., Parameter6 (key byte6);
Loads a MIFARE Classic key (6 bytes) for Authentication from the FIFO into the cryptounit.
Abort condition: Less than 6 bytes written to the FIFO.

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8.10.3.4 MFAuthent command
Command (03h), Parameter1 (Authentication command code 60h or 61h), Parameter2(block address), Parameter3 (card serial number byte0), Parameter4 (card serial number
byte1), Parameter5 (card serial number byte2), Parameter6 (card serial number byte3);This command handles the MIFARE Classic authentication in Reader/Writer mode toensure a secure communication to any MIFARE classic card.
When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there isaccess to the FIFO, the bit WrErr in the Error register is set.
This command terminates automatically when the MIFARE Classic card is authenticatedand the bit MFCrypto1On is set to logic 1.
This command does not terminate automatically, when the card does not answer,
therefore the timer should be initialized to automatic mode. In this case, beside the bit
IdleIRQ the bit TimerIRQ can be used as termination criteria. During authentication
processing the bits RxIRQ and TxIRQ are blocked. The Crypto1On shows if theauthentication was successful. The Crypto1On is always valid.
In case, there is an error during authentication, the bit ProtocolErr in the Error register is
set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0.
8.10.3.5 AckReq command
Command (04h);
Performs a Query (Full command must be written into the FIFO); an Ack and a ReqRn
command. All answers to the command will be written into the FIFO. The error flag iscopied after the answer into the FIFO.
This command terminates automatically and the then active state is idle.
8.10.3.6 Receive command
Command (05h);
The CLRC663 activates the receiver path and waits for any data stream to be received,
according to its register settings. The registers must be set before starting this commandaccording to the used protocol and antenna configuration. The correct settings have to bechosen before starting the command.
This command terminates automatically when the received data stream ends. This
is indicated either by the end of frame pattern or by the length byte depending on theselected framing and speed.
Remark: If the bit RxMultiple in the RxModeReg register is set to logic 1, the Receive
command does not terminate automatically. It has to be terminated by activating anyother command in the CommandReg register (see Section 9.17.6).
8.10.3.7 Transmit command
Command (06h); data to transmit
The content of the FIFO is transmitted immediately after starting the command. Before
transmitting the FIFO, all relevant registers have to be set to transmit data.
This command terminates automatically when the FIFO gets empty. It can be terminatedby any other command written to the command register.
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8.10.3.8 Transceive command
Command (07h); data to transmit
This command transmits data from FIFO buffer and automatically activates the receiverafter a transmission is finished.
Each transmission process starts by writing the command into CommandReg.
Remark: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will
never leave the receiving state, because the receiving will not be cancelled automatically.
8.10.3.9 WriteE2 command
Command (08h), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (data);
This command writes one byte into the EEPROM. If the FIFO contains no data, thecommand will wait until the data is available.
Abort condition: Address-parameter outside of allowed range 0x00 – 0x7F.
8.10.3.10 WriteE2PAGE command
Command (09h), Parameter1 (page address), Parameter2..65 (data0, data1...data63);This command writes up to 64 bytes into the EEPROM. The addresses are not allowed
to wrap over a page border. If this is the case, this additional data be ignored and stays
in the fifo. The programming starts after 64 bytes are read from the FIFO or the FIFO isempty.
Abort condition: Insufficient parameters in FIFO; Page address parameter outside ofrange 0x00 – 0x7F.
8.10.3.11 ReadE2 command
Command (0Ah), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (length);
Reads up to 256 bytes from the EEPROM to the FIFO. If a read operation exceeds theaddress 1FFFh, the read operation continues from address 0000h.
Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.
8.10.3.12 LoadReg command
Command (0Ch), Parameter1 (EEPROM addressH),Parameter2 (EEPROM addressL),Parameter3 (RegAdr), Parameter4 (number);Read a defined number of bytes from the EEPROM and copies the value into theRegister set, beginning at the given address RegAdr.
Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.
8.10.3.13 LoadProtocol command
Command (0Dh), Parameter1 (Protocol number RX), Parameter2 (Protocol number TX);
Reads out the EEPROM Register Set Protocol Area and overwrites the content of the
Rx- and Tx- related registers. These registers are important for a Protocol selection.
Abort condition: Insufficient parameter in FIFO

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Table 47. Predefined protocol overview RX[1]

ProtocolNumber(decimal)Protocol

Receiver speed[kbits/s]

Receiver Coding

00

ISO/IEC14443 A

106Manchester SubC

01

ISO/IEC14443 A

212

BPSK

02

ISO/IEC14443 A

424

BPSK

03

ISO/IEC14443 A

848

BPSK

04

ISO/IEC14443 B

106

BPSK

05

ISO/IEC14443 B

212

BPSK

06

ISO/IEC14443 B

424

BPSK

07

ISO/IEC14443 B

848

BPSK

08

FeliCa212

Manchester

09

FeliCa424

Manchester

10

ISO/IEC15693

26

SSC

11

ISO/IEC15693

52

SSC

12

ISO/IEC15693

26

DSC

13

EPC/UID

26

SSC

14

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF

212

2/424

15

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF

106

4/424

16

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF

424

2/848

17

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF

212

4/848

18

Jewel

-

-

[1]

For more protocol details, please refer to Section 8.

[1]

Table 48. Predefined protocol overview TX

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ProtocolNumber(decimal)ProtocolTransmitter speed[kbits/s]

Transmitter Coding

00

ISO/IEC14443 A

106

Miller01

ISO/IEC14443 A

212

Miller02

ISO/IEC14443 A

424Miller03

ISO/IEC14443 A

848

Miller04

ISO/IEC14443 B

106

NRZ

05

ISO/IEC14443 B

212

NRZ

06

ISO/IEC14443 B

424

NRZ

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[1]...continued

Table 48. Predefined protocol overview TX
ProtocolNumber(decimal)ProtocolTransmitter speed[kbits/s]

Transmitter Coding

07

ISO/IEC14443 B

848

NRZ

08

FeliCa212

Manchester

09

FeliCa424

Manchester

10

ISO/IEC15693

26

1/4

11

ISO/IEC15693

26

1/4

12

ISO/IEC15693

1,66

1/256

13

EPC/UID

53

Unitray

14

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF-

based on Tari value,
ASK, PIE

15

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF-

based on Tari value,
ASK, PIE

16

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF-

based on Tari value,
ASK, PIE

17

ISO/IEC 18000-3 mode 3/
EPC Class-1 HF-

based on Tari value,
ASK, PIE

18

Jewel

-

-

[1]

For more protocol details, please refer to Section 8.

8.10.3.14 LoadKeyE2 command
Command (0Eh), Parameter1 (key number);Loads a MIFARE Classic key for authentication from the EEPROM into the crypto 1 unit.
Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MIFARE Classic key
area.
8.10.3.15 StoreKeyE2 command
Command (0Fh), Parameter1 (KeyNr), Parameter2(keybyte1), Parameter3(keybyte2),Parameter4(keybyte3), Parameter5(keybyte4), Parameter6(keybyte5), Parameter7(keybyte6);
Stores MIFARE Classic keys into the EEPROM. The key number parameter indicatesthe first key (n) in the MKA that will be written. If more than one MIFARE Classic key isavailable in the FIFO then the next key (n+1) will be written until the FIFO is empty. If an
incomplete key (less than 6 bytes) is written into the FIFO, this key will be ignored andwill remain in the FIFO.
Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA;
8.10.3.16 GetRNR command
Command (1Ch);This command is reading Random Numbers from the random number generator of the
CLRC663. The Random Numbers are copied to the FIFO until the FIFO is full.
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8.10.3.17 SoftReset command
Command (1Fh);
This command is performing a soft reset. Triggered by this command all the default
values for the register setting will be read from the EEPROM and copied into the register
set.

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9

CLRC663 registers
9.1 Register bit behavior
Depending on the functionality of a register, the access conditions to the register canvary. In principle, bits with same behavior are grouped in common registers. The accessconditions are described in the table below:
Table 49. Behavior of register bits and their designation
Abbreviation Behavior

Description

r/w

read and write These bits can be written and read via the host interface. Since
they are used only for control purposes, the content is not
influenced by the state machines but can be read by internal
state machines.

dy

dynamic

These bits can be written and read via the host interface. They
can also be written automatically by internal state machines, forexample Command register changes its value automatically after
the execution of the command.

r

read only

These register bits indicate hold values which are determined byinternal states only.

w

write only

Reading these register bits always returns zero.

RFU-

These bits are reserved for future use and must not be changed.
In case of a required write access, it is recommended to read out
this bits, modify other bits of the register and write back only themodified bits (read-modify-write).

Table 50. CLRC663 registers overview
Address

Register name

Function00hCommandStarts and stops command execution

01h

HostCtrl

Host control register

02h

FIFOControl

Control register of the FIFO

03h

WaterLevel

Level of the FIFO underflow and overflow warning

04h

FIFOLength

Length of the FIFO

05h

FIFOData

Data In/Out exchange register of FIFO buffer

06h

IRQ0

Interrupt register 0

07h

IRQ1

Interrupt register 1

08h

IRQ0EnInterrupt enable register 009h

IRQ1EnInterrupt enable register 1

0Ah

Error

Error bits showing the error status of the last command execution

0Bh

StatusContains status of the communication

0Ch

RxBitCtrl

Control register for anticollision adjustments for bit oriented protocols

0Dh

RxCollCollision position register

0Eh

TControlControl of Timer 0..3

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Table 50. CLRC663 registers overview...continued
Address

Register name

Function

0Fh

T0Control

Control of Timer010h

T0ReloadHi

High register of the reload value of Timer011h

T0ReloadLo

Low register of the reload value of Timer012h

T0CounterValHi

Counter value high register of Timer013h

T0CounterValLo

Counter value low register of Timer0

14h

T1Control

Control of Timer1

15h

T1ReloadHi

High register of the reload value of Timer1

16h

T1ReloadLo

Low register of the reload value of Timer1

17h

T1CounterValHi

Counter value high register of Timer1

18h

T1CounterValLo

Counter value low register of Timer1

19h

T2Control

Control of Timer2

1Ah

T2ReloadHi

High byte of the reload value of Timer2

1Bh

T2ReloadLo

Low byte of the reload value of Timer2

1Ch

T2CounterValHi

Counter value high byte of Timer2

1Dh

T2CounterValLo

Counter value low byte of Timer2

1Eh

T3Control

Control of Timer3

1Fh

T3ReloadHi

High byte of the reload value of Timer3

20h

T3ReloadLo

Low byte of the reload value of Timer3

21h

T3CounterValHi

Counter value high byte of Timer3

22h

T3CounterValLo

Counter value low byte of Timer3

23h

T4Control

Control of Timer4

24h

T4ReloadHi

High byte of the reload value of Timer425h

T4ReloadLo

Low byte of the reload value of Timer426h

T4CounterValHi

Counter value high byte of Timer427h

T4CounterValLo

Counter value low byte of Timer4

28h

DrvModeDriver mode register

29h

TxAmp

Transmitter amplifier register

2Ah

DrvConDriver configuration register

2Bh

Txl

Transmitter register

2Ch

TxCrcPreset

Transmitter CRC control register, preset value

2Dh

RxCrcPreset

Receiver CRC control register, preset value

2Eh

TxDataNum

Transmitter data number register

2Fh

TxModWidth

Transmitter modulation width register

30h

TxSym10BurstLen

Transmitter symbol 1 + symbol 0 burst length register

31h

TXWaitCtrl

Transmitter wait control

32h

TxWaitLo

Transmitter wait low

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Table 50. CLRC663 registers overview...continued
Address

Register name

Function

33h

FrameCon

Transmitter frame control

34h

RxSofD

Receiver start of frame detection

35h

RxCtrlReceiver control register

36h

RxWaitReceiver wait register

37h

RxThreshold

Receiver threshold register

38h

Rcv

Receiver register

39h

RxAna

Receiver analog register

3Ah

RFU

No function implemented for CLRC66301 and CLRC66302

LPCD_Options

For CLRC66303: Options for LPCD configuration

3Bh

SerialSpeed

Serial speed register

3Ch

LFO_Trimm

Low-power oscillator trimming register

3Dh

PLL_Ctrl

IntegerN PLL control register, for microcontroller clock output adjustment

3Eh

PLL_DivOut

IntegerN PLL control register, for microcontroller clock output adjustment

3Fh

LPCD_QMin

Low-power card detection Q channel minimum threshold

40h

LPCD_QMax

Low-power card detection Q channel maximum threshold

41h

LPCD_IMin

Low-power card detection I channel minimum threshold

42h

LPCD_I_Result

Low-power card detection I channel result register

43h

LPCD_Q_Result

Low-power card detection Q channel result register

44h

PadEn

PIN enable register

45h

PadOutPIN out register

46h

PadIn

PIN in register

47h

SigOutEnables and controls the SIGOUT Pin

48h

TxBitModTransmitter bit mode register

49h

RFU

-

4Ah

TxDataCon

Transmitter data configuration register

4Bh

TxDataMod

Transmitter data modulation register

4Ch

TxSymFreq

Transmitter symbol frequency

4Dh

TxSym0H

Transmitter symbol 0 high register

4Eh

TxSym0L

Transmitter symbol 0 low register

4Fh

TxSym1H

Transmitter symbol 1 high register

50h

TxSym1L

Transmitter symbol 1 low register

51h

TxSym2

Transmitter symbol 2 register

52h

TxSym3

Transmitter symbol 3 register

53h

TxSym10Len

Transmitter symbol 1 + symbol 0 length register

54h

TxSym32Len

Transmitter symbol 3 + symbol 2 length register

55h

TxSym10BurstCtrl

Transmitter symbol 1 + symbol 0 burst control register

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Table 50. CLRC663 registers overview...continued
Address

Register name

Function

56h

TxSym10Mod

Transmitter symbol 1 + symbol 0 modulation register

57h

TxSym32ModTransmitter symbol 3 + symbol 2 modulation register

58h

RxBitMod

Receiver bit modulation register

59h

RxEofSym

Receiver end of frame symbol register

5Ah

RxSyncValH

Receiver synchronisation value high register

5Bh

RxSyncValL

Receiver synchronisation value low register

5Ch

RxSyncMod

Receiver synchronisation mode register

5Dh

RxMod

Receiver modulation register

5Eh

RxCorrReceiver correlation register

5Fh

FabCalCalibration register of the receiver, calibration performed at production

48h-5Fh

RFU

-

7Fh

VersionVersion and subversion register

9.2 Command configuration
9.2.1 Command
Starts and stops command execution.
Table 51. Command register (address 00h)
Bit

7

6

5

4

3

2

SymbolStandby

Modem
Off

RFU

CommandAccessrights

dy

r/w

-

dy

1

0

Table 52. Command bits
Bit

SymbolDescription

7

Standby

Set to 1, the IC is entering power-down mode.

6

ModemOffSet to logic 1, the receiver and the transmitter circuit is powering
down.

5

RFU

-

4 to 0Command

Defines the actual command for the CLRC663.

9.3 SAM configuration register
9.3.1 HostCtrl
Via the HostCtrl Register the interface access right can be controlled
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Table 53. HostCtrl register (address 01h);
Bit

7

6

5

4

3

2

1

0

SymbolRegEn

BusHostBusSAMRFU

SAMInterface

SAMInterface

RFU

RFU

Accessrights

dy

r/w

r/w

-

r/w

r/w

-

-

Table 54. HostCtrl bits
Bit

SymbolDescription

7

RegEn

If this bit is set to logic 1, the register HostCtrl_reg can be changed
at the next register access. The next write access clears this bit
automatically.

6

BusHostSet to logic 1, the bus is controlled by the host. This bit cannot be set
together with the bit BusSAM. This bit can only be set if the bit RegEn
is previously set.

5

BusSAM

Set to logic 1, the bus is controlled by the SAM. This bit cannot be
set together with BusHost. This bit can only be set if the bit RegEn ispreviously set.

4

RFU

-

3 to 2

SAMInterface

0h:SAM Interface switched off
1h:SAM Interface SPI active
2
2h:SAM Interface I CL active
2
3h:SAM Interface I C active

1 to 0RFU-

9.4 FIFO configuration register
9.4.1 FIFOControl
FIFOControl defines the characteristics of the FIFO
Table 55. FIFOControl register (address 02h);
Bit

7

6

5

4

3

2

1

0

SymbolFIFOSize

HiAlert

LoAlert

FIFOFlush

RFU

WaterLevelExtBit

FIFOLengthExtBits

Accessrights

r/w

r

r

w

-

r/w

r

Table 56. FIFOControl bits

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Bit

SymbolDescription

7

FIFOSize

Set to logic 1, FIFO size is 255 bytes;
Set to logic 0, FIFO size is 512 bytes.
It is recommended to change the FIFO size only, when the FIFO
content had been cleared.

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Table 56. FIFOControl bits...continued
Bit

SymbolDescription

6

HiAlertSet to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following equation:
HiAlert = (FIFOSize - FIFOLength) <= WaterLevel

5

LoAlertSet to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following conditions:
LoAlert =1 if FIFOLength <= WaterLevel

4

FIFOFlush

Set to logic 1 clears the FIFO buffer. Reading this bit will always
return 0

3

RFU

-

2

WaterLevelExtBit

Defines the bit 8 (MSB) for the waterlevel (extension of register
WaterLevel). This bit is only evaluated in the 512-byte FIFO mode.
Bits 7..0 are defined in register WaterLevel.

1 to 0

FIFOLengthExtBits

Defines the bit9 (MSB) and bit8 for the FIFO length (extension of
FIFOLength). These two bits are only evaluated in the 512-byte
FIFO mode. The bits 7..0 are defined in register FIFOLength.

9.4.2 WaterLevel
Defines the level for FIFO under- and overflow warning levels.This register is extendedby 1 bit in FIFOControl in case the 512-byte FIFO mode is activated by setting bit
FIFOControl.FIFOSize.
Table 57. WaterLevel register (address 03h);
Bit

7

6

5

4

SymbolAccessrights

3

2

1

0

r/w

r/w

r/w

WaterLevelBits
r/w

r/w

r/w

r/w

r/w

Table 58. WaterLevel bits

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Bit

SymbolDescription

7 to 0

WaterLevelBits

Sets a level to indicate a FIFO-buffer state which can be readfrom bits HighAlert and LowAlert in the FifoControl. In 512-byte
FIFO mode, the register is extended by bit WaterLevelExtBit in the
FIFOControl. This functionality can be used to avoid a FIFO buffer
overflow or underflow:
The bit HiAlert bit in FIFO Control is read logic 1, if the number ofbytes in the FIFO-buffer is equal or less than the number defined by
the waterlevel configuration.
The bit LoAlert bit in FIFO control is read logic 1, if the number ofbytes in the FIFO buffer is equal or less than the number defined by
the waterlevel configuration.
Note: For the calculation of HiAlert and LoAlert, see register
description of these bits (see section Section 9.4.1).

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9.4.3 FIFOLength
Number of bytes in the FIFO buffer. In 512-byte mode, this register is extended by
FIFOControl.FifoLength.
Table 59. FIFOLength register (address 04h); reset value: 00h
Bit

7

6

5

4

3

SymbolFIFOLength

Accessrights

dy

2

1

0

Table 60. FIFOLength bits
Bit

SymbolDescription

7 to 0

FIFOLength

Indicates the number of bytes in the FIFO buffer. In 512-byte mode
this register is extended by the bits FIFOLength in the FIFOControl
register. Writing to the FIFOData register increments, reading
decrements the number of available bytes in the FIFO.

9.4.4 FIFOData
In- and output of FIFO buffer. Contrary to any read/write access to other addresses,
reading or writing to the FIFO address does not increment the address pointer. Writing
to the FIFOData register increments, reading decrements the number of bytes present in
the FIFO.
Table 61. FIFOData register (address 05h);
Bit

7

6

5

SymbolAccessrights

4

3

2

1

0

dy

dy

dy

dy

FIFOData
dy

dy

dy

dy

Table 62. FIFOData bits
Bit

SymbolDescription

7 to 0

FIFOData

Data input and output port for the internal FIFO buffer. Refer to
Section 8.5.

9.5 Interrupt configuration registers
The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid
the unintended modification of bits.
The mechanism of changing register contents requires the following consideration:
IRQ(x).Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Dependingon the content of IRQ(x).Set, a write of a 1 to positions 0 to 6 either clears or sets thecorresponding bit. With this register, the application can modify the interrupt status which
is maintained by the CLRC663.
Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written
to a bit position 6...0 will trigger the setting or clearance of this bit as defined by bit 7.
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Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt
request register

9.5.1 IRQ0 register
Interrupt request register 0.
Table 63. IRQ0 register (address 06h); reset value: 00h
Bit

7

SymbolSet

Accessrightsw

6

5

HiAlertIRQ LoAlertIRQ
dy

4

3

2

1

0

IdleIRQ

TxIRQ

RxIRQ

ErrIRQ

RxSOF
IRQ

dy

dy

dy

dy

dy

dy

Table 64. IRQ0 bits
Bit

SymbolDescription

7

Set

1: writing a 1 to a bit position 6..0 sets the interrupt request
0: Writing a 1 to a bit position 6..0 clears the interrupt request

6

HiAlertIRQ Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert,
HiAlertIRQ stores this event.

5

LoAlertIRQ Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert,
LoAlertIRQ stores this event.

4

IdleIRQ

Set, when a command terminates by itself e.g. when the Commandchanges its value from any command to the Idle command. If an unknown
command is started, the Command changes its content to the idle state andthe bit IdleIRQ is set. Starting the Idle command by the Controller does not
set bit IdleIRQ.

3

TxIRQ

Set, when data transmission is completed, which is immediately after thelast bit is sent.

2

RxIRQ

Set, when the receiver detects the end of a data stream.
Note: This flag is no indication that the received data stream is correct. The
error flags have to be evaluated to get the status of the reception.

1

ErrIRQ

Set, when the one of the following errors is set:
FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr.

0

RxSOFlrq

Set, when a SOF or a subcarrier is detected.

9.5.2 IRQ1 register
Interrupt request register 1.
Table 65. IRQ1 register (address 07h)
Bit

7

SymbolSet

Accessrightsw

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6

5

4

GlobalIRQ LPCD_IRQ Timer4IRQ
dy

dy

dy

3

2

1

0

Timer3IRQ

Timer2IRQ

Timer1IRQ

Timer0IRQ

dy

dy

dy

dy

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Table 66. IRQ1 bits
Bit

SymbolDescription

7

Set

1: writing a 1 to a bit position 5..0 sets the interrupt request
0: Writing a 1 to a bit position 5..0 clears the interrupt request

6

GlobalIRQ

Set, if an enabled IRQ occurs.

5

LPCD_IRQ Set if a card is detected in Low-power card detection sequence.

4

Timer4IRQ Set to logic 1 when Timer4 has an underflow.

3

Timer3IRQ Set to logic 1 when Timer3 has an underflow.

2

Timer2IRQ Set to logic 1 when Timer2 has an underflow.

1

Timer1IRQ Set to logic 1 when Timer1 has an underflow.

0Timer0IRQ Set to logic 1 when Timer0 has an underflow.

9.5.3 IRQ0En register
Interrupt request enable register for IRQ0. This register allows defining if an interrupt
request is processed by the CLRC663.
Table 67. IRQ0En register (address 08h)
Bit

7

6

5

Symbol

IRQ_Inv

Hi AlertIRQEn

Accessrights

r/w

r/w

4

LoAlertIRQEn IdleIRQEn
r/w

3

2

1

0

TxIRQEn

RxIRQEn

ErrIRQEn

RxSOF
IRQEn

r/w

r/w

r/w

r/w

r/w

Table 68. IRQ0En bits
Bit

SymbolDescription

7

IRQ_Inv

Set to one the signal of the IRQ pin is inverted

6

Hi AlerIRQEn

Set to logic 1, it allows the High Alert interrupt Request (indicated by the
bit HiAlertIRQ) to be propagated to the GlobalIRQ

5

Lo AlertIRQEn Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the
bit LoAlertIRQ) to be propagated to the GlobalIRQ

4

IdleIRQEn

Set to logic 1, it allows the Idle interrupt request (indicated by the bit
IdleIRQ) to be propagated to the GlobalIRQ

3TxIRQEn

Set to logic 1, it allows the transmitter interrupt request (indicated by the
bit TxtIRQ) to be propagated to the GlobalIRQ

2RxIRQEn

Set to logic 1, it allows the receiver interrupt request (indicated by the bit
RxIRQ) to be propagated to the GlobalIRQ

1ErrIRQEn

Set to logic 1, it allows the Error interrupt request (indicated by the bit
ErrorIRQ) to be propagated to the GlobalIRQ

0

RxSOFIRQEn Set to logic 1, it allows the RxSOF interrupt request (indicated by the bit
RxSOFIRQ) to be propagated to the GlobalIRQ

9.5.4 IRQ1En
Interrupt request enable register for IRQ1.
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Table 69. IRQ1EN register (address 09h);
Bit
SymbolAccessrights7

6

5

IRQPushPull IRQPinEn LPCD_IRQEn
r/w

r/w

r/w

4

3

2

1

0

Timer4
IRQEn

Timer3
IRQEn

Timer2
IRQEn

Timer1
IRQEn

Timer0
IRQEn

r/w

r/w

r/w

r/w

r/w

Table 70. IRQ1EN bits
Bit

SymbolDescription

7

IRQPushPull

Set to 1 the IRQ-pin acts as PushPull pin, otherwise it acts as
OpenDrain pin

6

IRQPinEN

Set to logic 1, it allows the global interrupt request (indicated by the bit
GlobalIRQ) to be propagated to the interrupt pin

5

LPCD_IRQEN

Set to logic 1, it allows the LPCDinterrupt request (indicated by the bit
LPCDIRQ) to be propagated to the GlobalIRQ

4Timer4IRQEn

Set to logic 1, it allows the Timer4 interrupt request (indicated by the bit
Timer4IRQ) to be propagated to the GlobalIRQ

3Timer3IRQEn

Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit
Timer3IRQ) to be propagated to the GlobalIRQ

2Timer2IRQEn

Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit
Timer2IRQ) to be propagated to the GlobalIRQ

1Timer1IRQEn

Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit
Timer1IRQ) to be propagated to the GlobalIRQ

0Timer0IRQEn

Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit
Timer0IRQ) to be propagated to the GlobalIRQ

9.6 Contactless interface configuration registers
9.6.1 Error
Error register.
Table 71. Error register (address 0Ah)
Bit

7

6

5

4

3

2

1

0

SymbolEE_ErrFiFoWrErr

FIFOOvl

MinFrameErr

NoDataErr

CollDetProtErr

IntegErr

Accessrights

dy

dy

dy

dy

dy

dy

dy

dy

Table 72. Error bits

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Bit

SymbolDescription

7

EE_ErrAn error appeared during the last EEPROM command. For
details see the descriptions of the EEPROM commands

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Table 72. Error bits...continued
Bit

SymbolDescription

6

FIFOWrErr Data was written into the FIFO, during a transmission of a possible
CRC, during "RxWait", "Wait for data" or "Receiving" state, or during anauthentication command. The Flag is cleared when a new CL command isstarted. If RxMultiple is active, the flag is cleared after the error flags havebeen written to the FIFO.

5

FIFOOvl

Data is written into the FIFO when it is already full. The data that is alreadyin the FIFO remains untouched. All data that is written to the FIFO after thisFlag is set to 1 will be ignored.

4

Min
FrameErr

A valid SOF was received, but afterwards less than 4 bits of data werereceived.
Note: Frames with less than 4 bits of data are automatically discarded andthe RxDecoder stays enabled. Furthermore no RxIRQ is set. The same isvalid for less than 3 bytes, if the EMD suppression is activatedNote: MinFrameErr is automatically cleared at the start of a receive ortransceive command. In case of a transceive command, it is cleared at thestart of the receiving phase ("Wait for data" state)

3

NoDataErr Data should be sent, but no data is in FIFO

2

CollDetA collision has occurred. The position of the first collision is shown in theregister RxColl.
Note: CollDet is automatically cleared at the start of a receive or transceive
command. In case of a transceive command, it is cleared at the start of thereceiving phase ("Wait for data" state).
Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1.

1

ProtErr

A protocol error has occurred. A protocol error can be a wrong stop bit,a missing or wrong ISO/IEC14443B EOF or SOF or a wrong number ofreceived data bytes. When a protocol error is detected, data reception is
stopped.
Note: ProtErr is automatically cleared at start of a receive or transceive
command. In case of a transceive command, it is cleared at the start of thereceiving phase ("Wait for data" state).
Note: When a protocol error occurs the last received data byte is not written
into the FIFO.

0

IntegErr

A data integrity error has been detected. Possible cause can be a wrong
parity or a wrong CRC. In case of a data integrity error the reception iscontinued.
Note: IntegErr is automatically cleared at start of a Receive or Transceive
command. In case of a Transceive command, it is cleared at the start of thereceiving phase ("Wait for data" state).
Note: If the NoColl bit is set, also a collision is setting the IntegErr.

9.6.2 Status
Status register.
Table 73. Status register (address 0Bh)
Bit

7

6

5

4

3

Symbol--Crypto1On--

ComState

Accessrights

RFU

RFU

dy

RFU

RFU

r

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Table 74. Status bits
Bit

SymbolDescription

7 to 6-RFU

5Crypto1On Indicates if the MIFARE Classic Crypto is on. Clearing this bit is switching
the MIFARE Cassic Crypto off. The bit can only be set by the MFAuthent
command.

4 to 3-RFU

2 to 0

ComState

ComState shows the status of the transmitter and receiver state machine:
000b ... Idle
001b ... TxWait
011b ... Transmitting
101b ... RxWait
110b ... Wait for data
111b ... Receiving
100b ... not used

9.6.3 RxBitCtrl
Receiver control register.
Table 75. RxBitCtrl register (address 0Ch);
Bit

7

6

SymbolValuesAfterColl

Accessrights

r/w

5

4

r/w

2

NoCollRxAlign
r/w

3

r/w

r/w

1

0

RxLastBitsw

w

w

Table 76. RxBitCtrl bits

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Bit

SymbolDescription

7

ValuesAfterColl

If cleared, every received bit after a collision is replaced by a zero. Thisfunction is needed for ISO/IEC14443 anticollision

6 to 4

RxAlign

Used for reception of bit oriented frames: RxAlign defines the bit position
length for the first bit received to be stored. Further received bits are
stored at the following bit positions.
Example:RxAlign = 0h - the LSB of the received bit is stored at bit 0, the second
received bit is stored at bit position 1.
RxAlign = 1h - the LSB of the received bit is stored at bit 1, the second
received bit is stored at bit position 2.
RxAlign = 7h - the LSB of the received bit is stored at bit 7, the second
received bit is stored in the following byte at position 0.
Note: If RxAlign = 0, data is received byte-oriented, otherwise bitoriented.

3

NoCollIf this bit is set, a collision will result in an IntegErr

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Table 76. RxBitCtrl bits...continued
Bit

SymbolDescription

2 to 0RxLastBits

Defines the number of valid bits of the last data byte received in bitoriented communications. If zero the whole byte is valid.
Note: These bits are set by the RxDecoder in a bit-oriented
communication at the end of the communication. They are reset at startof reception.

9.6.4 RxColl
Receiver collision register.
Table 77. RxColl register (address 0Dh);
Bit

7

6

5

4

3

2

SymbolCollPosValid

CollPos

Accessrightsr

r

1

0

Table 78. RxColl bits
Bit

SymbolDescription

7

CollPos
Valid

If set to 1, the value of CollPos is valid. Otherwise no collision is detected or
the position of the collision is out of the range of bits CollPos.

6 to 0CollPos

These bits show the bit position of the first detected collision in a received
frame (only data bits are interpreted). CollPos can only be displayed for the
first 8 bytes of a data stream.
Example:00h indicates a bit collision in the 1st bit
01h indicates a bit collision in the 2nd bit
08h indicates a bit collision in the 9th bit (1st bit of 2nd byte)
3Fh indicates a bit collision in the 64th bit (8th bit of the 8th byte)
These bits shall only be interpreted in Passive communication mode at 106
kbit/s or ISO/IEC 14443 type A and read /write mode for MIFARE Classic or
ISO/IEC 15693/ICODE SLI read/write mode if bit CollPosValid is set.
Note: If RxBitCtrl.RxAlign is set to a value different to 0, this value isincluded in the CollPos.
Example: RxAlign = 4h, a collision occurs in the 4th received bit (which is
the last bit of that UID byte). The CollPos = 7h in this case.

9.7 Timer configuration registers
9.7.1 TControl
Control register of the timer section.
The TControl implements a special functionality to avoid the not intended modification ofbits.
Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified.
Example: writing FFh sets all bits 7..4, writing F0h does not change any of the bits 7..4
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Table 79. TControl register (address 0Eh)
Bit
SymbolAccessrights7

6

T3Running T2Running
dy

dy

5

4

3

2

1

0

T1Running

T0Running

T3StartStopNow

T2StartStopNow

T1StartStopNow

T0StartStopNow

dy

dy

w

w

w

w

Table 80. TControl bits
Bit

SymbolDescription

7

T3Running

Indicates Timer3 is running.If the bit T3startStopNow is set/reset, thisbit and the timer can be started/stopped

6

T2Running

Indicates Timer2 is running. If the bit T2startStopNow is set/reset, thisbit and the timer can be started/stopped

5

T1Running

Indicates tTmer1 is running. If the bit T1startStopNow is set/reset, thisbit and the timer can be started/stopped

4

T0Running

Indicates Timer0 is running. If the bit T0startStopNow is set/reset, thisbit and the timer can be started/stopped

3

T3StartStop
Now

The bit 7 of TControl T3Running can be modified if set

2

T2StartStop
Now

The bit 6of TControl T2Running can be modified if set

1

T1StartStop
Now

The bit 5of TControl T1Running can be modified if set

0

T0StartStop
Now

The bit 4 of TControl T0Running can be modified if set

9.7.2 T0Control
Control register of the Timer0.
Table 81. T0Control register (address 0Fh);
Bit

7

6

Symbol

T0StopRx-

Accessrights

r/w

RFU

5

4

3

2

1

0

T0Start

T0AutoRestart

-

T0Clk

r/w

r/w

RFU

r/w

Table 82. T0Control bits

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Bit

SymbolDescription

7

T0StopRx

If set, the timer stops immediately after receiving the first 4 bits. If
cleared the timer does not stop automatically.
Note: If LFO Trimming is selected by T0Start, this bit has no effect.

6

-

RFU

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Table 82. T0Control bits...continued
Bit

SymbolDescription

5 to 4

T0Start00b: The timer is not started automatically
01 b: The timer starts automatically at the end of the transmission
10 b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11 b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge)

3

T0AutoRestart 1: the timer automatically restarts its count-down from
T0ReloadValue, after the counter value has reached the value zero.
0: the timer decrements to zero and stops.
The bit Timer1IRQ is set to logic 1 when the timer underflows.

2

-

RFU

1 to 0T0Clk

00 b: The timer input clock is 13.56 MHz.
01 b: The timer input clock is 211,875 kHz.
10 b: The timer input clock is an underflow of Timer2.
11 b: The timer input clock is an underflow of Timer1.

9.7.2.1 T0ReloadHi
High byte reload value of the Timer0.
Table 83. T0ReloadHi register (address 10h);
Bit

7

6

5

4

3

Symbol

T0Reload Hi

Accessrights

r/w

2

1

0

Table 84. T0ReloadHi bits
Bit

SymbolDescription

7 to 0T0ReloadHi

Defines the high byte of the reload value of the timer. With the start
event, the timer loads the value of the registers T0ReloadValHi,
T0ReloadValLo. Changing this register affects the timer only at thenext start event.

9.7.2.2 T0ReloadLo
Low byte reload value of the Timer0.
Table 85. T0ReloadLo register (address 11h);
Bit

7

6

5

4

3

Symbol

T0ReloadLo

Accessrightsr/w

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Table 86. T0ReloadLo bits
Bit

SymbolDescription

7 to0

T0ReloadLo

Defines the low byte of the reload value of the timer. With thestart event, the timer loads the value of the T0ReloadValHi,
T0ReloadValLo. Changing this register affects the timer only at thenext start event.

9.7.2.3 T0CounterValHi
High byte of the counter value of Timer0.
Table 87. T0CounterValHi register (address 12h)
Bit

7

6

5

4

3

Symbol

T0CounterValHi

Accessrights

dy

2

1

0

1

0

Table 88. T0CounterValHi bits
Bit

SymbolDescription

7to0

T0Counter
ValHi

High byte value of the Timer0.
This value shall not be read out during reception.

9.7.2.4 T0CounterValLo
Low byte of the counter value of Timer0.
Table 89. T0CounterValLo register (address 13h)
Bit

7

6

5

4

3

Symbol

T0CounterValLo

Accessrightsdy

2

Table 90. T0CounterValLo bits
Bit

SymbolDescription

7 to 0T0CounterValLo

Low byte value of the Timer0.
This value shall not be read out during reception.

9.7.2.5 T1Control
Control register of the Timer1.
Table 91. T1Control register (address 14h);
Bit

7

6

Symbol

T1StopRx-

Accessrightsr/w

RFU

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5

4

3

2

T1Start

T1AutoRestart

-

T1Clk

r/w

r/w

RFU

r/w

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Table 92. T1Control bits
Bit

SymbolDescription

7

T1StopRx

If set, the timer stops after receiving the first 4 bits. If cleared, thetimer is not stopped automatically.
Note: If LFO trimming is selected by T1start, this bit has no effect.

6

-

RFU

5 to 4

T1Start00b: The timer is not started automatically
01 b: The timer starts automatically at the end of the transmission
10 b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11 b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge)

3

T1AutoRestart Set to logic 1, the timer automatically restarts its countdown from
T1ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the timer decrements to zero and stops.
The bit Timer1IRQ is set to logic 1 when the timer underflows.

2

-

RFU

1 to 0

T1Clk

00 b: The timer input clock is 13.56 MHz
01 b: The timer input clock is 211,875 kHz.
10 b: The timer input clock is an underflow of Timer0
11 b: The timer input clock is an underflow of Timer2

9.7.2.6 T1ReloadHi
High byte (MSB) reload value of the Timer1.
Table 93. T0ReloadHi register (address 15h)
Bit

7

6

5

4

3

Symbol

T1ReloadHi

Accessrights

r/w

2

1

0

Table 94. T1ReloadHi bits
Bit

SymbolDescription

7 to 0T1ReloadHi

Defines the high byte reload value of the Timer 1. With the start event,the timer loads the value of the T1ReloadValHi and T1ReloadValLo.
Changing this register affects the Timer only at the next start event.

9.7.2.7 T1ReloadLo
Low byte (LSB) reload value of the Timer1.
Table 95. T1ReloadLo register (address 16h)
Bit

7

6

5

4

3

Symbol

T1ReloadLo

Accessrightsr/w

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Table 96. T1ReloadLo bits
Bit

SymbolDescription

7 to 0T1ReloadLo

Defines the low byte of the reload value of the Timer1. Changing thisregister affects the timer only at the next start event.

9.7.2.8 T1CounterValHi
High byte (MSB) of the counter value of byte Timer1.
Table 97. T1CounterValHi register (address 17h)
Bit

7

6

5

4

3

SymbolT1CounterValHi

Accessrights

dy

2

1

0

1

0

1

0

Table 98. T1CounterValHi bits
Bit

SymbolDescription

7 to 0T1Counter
ValHi

High byte of the current value of the Timer1.
This value shall not be read out during reception.

9.7.2.9 T1CounterValLo
Low byte (LSB) of the counter value of byte Timer1.
Table 99. T1CounterValLo register (address 18h)
Bit

7

6

5

4

3

SymbolT1CounterValLo

Accessrightsdy

2

Table 100. T1CounterValLo bits
Bit

SymbolDescription

7 to 0T1Counter
ValLo

Low byte of the current value of the counter 1.
This value shall not be read out during reception.

9.7.2.10 T2Control
Control register of the Timer2.
Table 101. T2Control register (address 19h)
Bit

7

6

Symbol

T2StopRx-

Accessrightsr/w

RFU

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5

4

3

2

T2StartT2AutoRestart

-

T2Clk

r/w

r/w

RFU

r/w

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Table 102. T2Control bits
Bit

SymbolDescription

7

T2StopRx

If set the timer stops immediately after receiving the first 4 bits. If
cleared indicates, that the timer is not stopped automatically.
Note: If LFO Trimming is selected by T2Start, this bit has no effect.

6

-

RFU

5 to 4

T2Start00 b: The timer is not started automatically.
01 b: The timer starts automatically at the end of the transmission.
10 b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge).
11 b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge).

3

T2AutoRestart Set to logic 1, the timer automatically restarts its countdown from
T2ReloadValue, after the counter value has reached the value
zero. Set to logic 0 the timer decrements to zero and stops. The bit
Timer2IRQ is set to logic 1 when the timer underflows

2

-

RFU

1 to 0T2Clk

00 b: The timer input clock is 13.56 MHz.
01 b: The timer input clock is 212 kHz.
10 b: The timer input clock is an underflow of Timer0
11b: The timer input clock is an underflow of Timer1

9.7.2.11 T2ReloadHi
High byte of the reload value of Timer2.
Table 103. T2ReloadHi register (address 1Ah)
Bit

7

6

5

4

3

Symbol

T2ReloadHi

Accessrights

r/w

2

1

0

Table 104. T2ReloadHi bits
Bit

SymbolDescription

7 to 0T2ReloadHi

Defines the high byte of the reload value of the Timer2. With thestart event, the timer load the value of the T2ReloadValHi and
T2ReloadValLo. Changing this register affects the timer only at thenext start event.

9.7.2.12 T2ReloadLo
Low byte of the reload value of Timer2.
Table 105. T2ReloadLo register (address 1Bh)
Bit

7

6

5

4

3

Symbol

T2ReloadLo

Accessrightsr/w

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Table 106. T2ReloadLo bits
Bit

SymbolDescription

7 to 0T2ReloadLo

Defines the low byte of the reload value of the Timer2. With thestart event, the timer load the value of the T2ReloadValHi and
T2RelaodVaLo. Changing this register affects the timer only at thenext start event.

9.7.2.13 T2CounterValHi
High byte of the counter register of Timer2.
Table 107. T2CounterValHi register (address 1Ch)
Bit

7

6

5

4

3

Symbol

T2CounterValHi

Accessrights

dy

2

1

0

1

0

Table 108. T2CounterValHi bits
Bit

SymbolDescription

7 to 0T2Counter
ValHi

High byte current counter value of Timer2.
This value shall not be read out during reception.

9.7.2.14 T2CounterValLoReg
Low byte of the current value of Timer 2.
Table 109. T2CounterValLo register (address 1Dh)
Bit

7

6

5

4

3

Symbol

T2CounterValLo

Accessrightsdy

2

Table 110. T2CounterValLo bits
Bit

SymbolDescription

7 to 0T2Counter
ValLo

Low byte of the current counter value of Timer1Timer2.
This value shall not be read out during reception.

9.7.2.15 T3Control
Control register of the Timer 3.
Table 111. T3Control register (address 1Eh)
Bit

7

6

Symbol

T3StopRx-

Accessrightsr/w

RFU

CLRC663

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5

4

3

2

T3StartT3AutoRestart

-

T3Clk

r/w

r/w

RFU

r/w

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Table 112. T3Control bits
Bit

SymbolDescription

7

T3StopRx

If set, the timer stops immediately after receiving the first 4 bits. If
cleared, indicates that the timer is not stopped automatically.
Note: If LFO Trimming is selected by T3Start, this bit has no effect.

6

-

RFU

5 to 4

T3Start00b - timer is not started automatically
01 b - timer starts automatically at the end of the transmission
10 b - timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11 b - timer is used for LFO trimming with underflow (Start/Stop on
PosEdge).

3

T3AutoRestart Set to logic 1, the timer automatically restarts its countdown from
T3ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the timer decrements to zero and stops.
The bit Timer1IRQ is set to logic 1 when the timer underflows.

2

-

RFU

1 to 0T3Clk

00 b - the timer input clock is 13.56 MHz.
01 b - the timer input clock is 211,875 kHz.
10 b - the timer input clock is an underflow of Timer0
11 b - the timer input clock is an underflow of Timer1

9.7.2.16 T3ReloadHi
High byte of the reload value of Timer3.
Table 113. T3ReloadHi register (address 1Fh);
Bit

7

6

5

4

3

Symbol

T3ReloadHi

Accessrights

r/w

2

1

0

Table 114. T3ReloadHi bits
Bit

SymbolDescription

7 to 0T3ReloadHi

Defines the high byte of the reload value of the Timer3. With thestart event, the timer load the value of the T3ReloadValHi and
T3ReloadValLo. Changing this register affects the timer only at thenext start event.

9.7.2.17 T3ReloadLo
Low byte of the reload value of Timer3.
Table 115. T3ReloadLo register (address 20h)
Bit

7

6

5

4

3

Symbol

T3ReloadLo

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Table 116. T3ReloadLo bits
Bit

SymbolDescription

7 to 0T3ReloadLo

Defines the low byte of the reload value of Timer3. With thestart event, the timer load the value of the T3ReloadValHi and
T3RelaodValLo. Changing this register affects the timer only at thenext start event.

9.7.2.18 T3CounterValHi
High byte of the current counter value the 16-bit Timer3.
Table 117. T3CounterValHi register (address 21h)
Bit

7

6

5

4

3

Symbol

T3CounterValHi

Accessrights

dy

2

1

0

1

0

Table 118. T3CounterValHi bits
Bit

SymbolDescription

7 to 0T3Counter
ValHi

High byte of the current counter value of Timer3.
This value shall not be read out during reception.

9.7.2.19 T3CounterValLo
Low byte of the current counter value the 16-bit Timer3.
Table 119. T3CounterValLo register (address 22h)
Bit

7

6

5

4

3

Symbol

T3CounterValLo

Accessrightsdy

2

Table 120. T3CounterValLo bits
Bit

SymbolDescription

7 to 0T3Counter
ValLo

Low byte current counter value of Timer3.
This value shall not be read out during reception.

9.7.2.20 T4Control
The wake-up timer T4 activates the system after a given time. If enabled, it can start thelow-power card detection function.
Table 121. T4Control register (address 23h)
Bit
Symbol

7

6

5

4

3

2

T4Running

T4StartStopNow

T4AutoTrimm

T4AutoLPCD

T4AutoRestartT4AutoWakeUp

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Table 121. T4Control register (address 23h)...continued
Bit

7

6

5

4

3

2

Accessrights

dy

w

r/w

r/w

r/w

r/w

1

0
r/w

Table 122. T4Control bits
Bit

SymbolDescription

7

T4Running

Shows if the timer T4 is running. If the bit T4StartStopNow is set,
this bit and the timer T4 can be started/stopped.

6

T4StartStopNow

if set, the bit T4Running can be changed.

5

T4AutoTrimm

If set to one, the timer activates an LFO trimming procedure when it
underflows. For the T4AutoTrimm function, at least one timer (T0 to
T3) has to be configured properly for trimming (T3 is not allowed if
T4AutoLPCD is set in parallel).

4

T4AutoLPCD

If set to one, the timer activates a low-power card detection
sequence. If a card is detected an interrupt request is raised andthe system remains active if enabled. If no card is detected the
CLRC663 enters the Power down mode if enabled. The timer is
automatically restarted (no gap). Timer 3 is used to specify the time
where the RF field is enabled to check if a card is present. Therefore
you may not use Timer 3 for T4AutoTrimm in parallel.

3

T4AutoRestart

Set to logic 1, the timer automatically restarts its countdown from
T4ReloadValue, after the counter value has reached the value
zero. Set to logic 0 the timer decrements to zero and stops. The bit
Timer4IRQ is set to logic 1 at timer underflow.

2

T4AutoWakeUp If set, the CLRC663 wakes up automatically, when the timer T4 hasan underflow. This bit has to be set if the IC should enter the Powerdown mode after T4AutoTrimm and/or T4AutoLPCD is finished andno card has been detected. If the IC should stay active after one ofthese procedures, this bit has to be set to 0.

1 to 0

T4Clk

00b - the timer input clock is the LFO clock
01b - the timer input clock is the LFO clock/8
10b - the timer input clock is the LFO clock/16
11b - the timer input clock is the LFO clock/32

9.7.2.21 T4ReloadHi
High byte of the reload value of the 16-bit timer 4.
Table 123. T4ReloadHi register (address 24h)
Bit

7

6

5

4

3

Symbol

T4ReloadHi

Accessrightsr/w

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Table 124. T4ReloadHi bits
Bit

SymbolDescription

7 to 0T4ReloadHi

Defines high byte for the reload value of timer 4. With the start event,the timer 4 loads the T4ReloadVal. Changing this register affects thetimer only at the next start event.

9.7.2.22 T4ReloadLo
Low byte of the reload value of the 16-bit timer 4.
Table 125. T4ReloadLo register (address 25h)
Bit

7

6

5

4

3

Symbol

T4ReloadLo

Accessrights

r/w

2

1

0

Table 126. T4ReloadLo bits
Bit

SymbolDescription

7 to 0T4ReloadLo

Defines the low byte of the reload value of the timer 4. With the start
event, the timer loads the value of the T4ReloadVal. Changing thisregister affects the timer only at the next start event.

9.7.2.23 T4CounterValHi
High byte of the counter value of the 16-bit timer 4.
Table 127. T4CounterValHi register (address 26h)
Bit

7

6

5

4

3

Symbol

T4CounterValHi

Accessrights

dy

2

1

0

Table 128. T4CounterValHi bits
Bit

SymbolDescription

7 to 0T4CounterValHi

High byte of the current counter value of timer 4.

9.7.2.24 T4CounterValLo
Low byte of the counter value of the 16-bit timer 4.
Table 129. T4CounterValLo register (address 27h)
Bit

7

6

5

4

3

Symbol

T4CounterValLo

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Table 130. T4CounterValLo bits
Bit

SymbolDescription

7 to 0T4CounterValLo

Low byte of the current counter value of the timer 4.

9.8 Transmitter driver configuration registers
9.8.1 DrvMode
Table 131. DrvMode register (address 28h)
Bit

7

6

5

4

3

2

1

Symbol

Tx2Inv

Tx1Inv--

TxEn

TxClk Mode

Accessrights

r/w

r/w

RFU

RFU

r/w

r/w

0

Table 132. DrvMode bits
Bit

SymbolDescription

7

Tx2Inv

Inverts transmitter 2 at TX2 pin

6

Tx1Inv

Inverts transmitter 1 at TX1 pin

5

RFU

4

-

RFU

3

TxEn

If set to 1 both transmitter pins are enabled

2 to 0TxClkMode

Transmitter clock settings. Codes 011b and 0b110 are not supported.
This register defines, if the output is operated in open-drain, push-pull,at high impedance or pulled to a fix high or low level.

9.8.2 TxAmp
With the set_cw_amplitude register, output power can be traded off against power supply
rejection. Spending more headroom leads to better power supply rejection ration andbetter accuracy of the modulation degree.
With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register
overrides the settings made by set_cw_amplitude.
Table 133. TxAmp register (address 29h)
Bit

7

6

5

Symbolset_cw_amplitude-

set_residual_carrier

Accessrights

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RFU

r/w

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3

2

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Table 134. TxAmp bits
Bit

SymbolDescription

7 to 6

set_cw_amplitude

Allows reducing the output amplitude of the transmitter by a fix
value.
Four different preset values that are subtracted from TVDD
can be selected:
0: TVDD -100 mV
1: TVDD -250 mV
2: TVDD -500 mV
3: TVDD -1000 mV

5

RFU

-

4 to 0

set_residual_ carrier

Set the residual carrier percentage. refer to section
Section 8.6.2.

9.8.3 TxCon
Table 135. TxCon register (address 2Ah)
Bit

7

6

5

4

3

2

1

0

SymbolOvershootT2

CwMax

TxInv

TxSel

Accessrights

r/w

r/w

r/w

r/w

Table 136. TxCon bits
Bit

SymbolDescription

7 to 4

OvershootT2

Specifies the length (number of carrier clocks) of the additional
modulation for overshoot prevention. Refer to section Section 8.6.2.1.

3

Cwmax

Set amplitude of continuous wave carrier to the maximum.
If set, set_cw_amplitude in Register TxAmp has no influence on thecontinuous amplitude.

2

TxInv

If set, the resulting modulation signal defined by TxSel is inverted

1 to 0

TxSel

Defines which signal is used as source for modulation
00b ... no modulation
01b ... TxEnvelope
10b ... SigIn
11b ... RFU

9.8.4 Txl
Table 137. Txl register (address 2Bh)
Bit

7

6

5

4

3

2

1

SymbolOvershootT1

tx_set_iLoad

Accessrightsr/w

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Table 138. Txl bits
Bit

SymbolDescription

7 to 4

OvershootT1

Overshoot value for Timer1. Refer to Section Section 8.6.2.1.

3 to 0tx_set_iLoad

Factory trim value, sets the expected Tx load current. This value isused to control the modulation index in an optimized way dependent
on the expected TX load current.

9.9 Transmitter CRC configuration registers
9.9.1 TxCrcPreset
Table 139. TXCrcPreset register (address 2Ch)
Bit

7

6

5

4

3

2

1

0

SymbolRFU

TXPresetVal

TxCRCtype

TxCRCInvert

TxCRCEn

Accessrights

-

r/w

r/w

r/w

r/w

Table 140. TxCrcPreset bits
Bit

SymbolDescription

7

RFU

-

6 to 4

TXPresetVal

Specifies the CRC preset value for transmission (see following table).

3 to 2TxCRCtypeDefines which type of CRC (CRC8/CRC16/CRC5) is calculated:• 00h -- CRC5
• 01h -- CRC8
• 02h -- CRC16• 03h -- RFU

1

TxCRCInvert

if set, the resulting CRC is inverted and attached to the data frame(ISO/IEC 3309)

0

TxCRCEn

if set, a CRC is appended to the data stream

Table 141. Transmitter CRC preset value configuration

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TXPresetVal[6...4]

CRC16

CRC8

CRC5

0h

0000h

00h

00h

1h

6363h

12h

12h

2h

A671h

BFh

-

3h

FFFEh

FDh

-

4h

-

-

-

5h

-

-

-

6h

User definedUser definedUser defined

7h

FFFFh

FFh

1Fh

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Remark: User-defined CRC preset values can be configured by EEPROM (see section
Section 8.7.2.1, Table 38.

9.9.2 RxCrcCon
Table 142. RxCrcCon register (address 2Dh)
Bit

7

6

5

4

3

2

1

0

SymbolRxForceCRCWrite

RXPresetVal

RXCRCtype

RxCRCInvert

RxCRCEn

Accessrights

r/w

r/w

r/w

r/w

r/w

Table 143. RxCrcCon bits
Bit

SymbolDescription

7

RxForceCrc
Write

If set, the received CRC byte(s) are copied to the FIFO.
If cleared CRC Bytes are only checked, but not copied to the FIFO.
This bit has to be always set in case of a not byte aligned CRC (e.g.
ISO/IEC 18000-3 mode 3/ EPC Class-1HF)

6 to 4

RXPresetVal

Defines the CRC preset value (Hex.) for transmission. (see following
table).

3 to 2RxCRCtypeDefines which type of CRC (CRC8/CRC16/CRC5) is calculated:• 00h -- CRC5
• 01h -- CRC8
• 02h -- CRC16• 03h -- RFU

1

RxCrcInvert

If set, the CRC check is done for the inverted CRC.

0

RxCrcEnIf set, the CRC is checked and in case of a wrong CRC an error flag isset. Otherwise the CRC is calculated but the error flag is not modified.

Table 144. Receiver CRC preset value configuration
RXPresetVal[6...4]

CRC16

CRC8

CRC5

0h

0000h

00h

00h

1h

6363h

12h

12h

2h

A671h

BFh

-

3h

FFFEh

FDh

-

4h

-

-

-

5h

-

-

-

6h

User definedUser definedUser defined

7h

FFFFh

FFh

1Fh

9.10 Transmitter data configuration registers

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9.10.1 TxDataNum
Table 145. TxDataNum register (address 2Eh)
Bit
Symbol

7

6

5

4

3

RFU

RFU-

RFU-

KeepBitGrid

DataEnTxLastBits

r/w

r/w

r/w

Accessrights2

10

Table 146. TxDataNum bits
Bit

SymbolDescription

7 to 5RFU-

4KeepBitGrid

If set, the time between consecutive transmissions starts is a multipleof one ETU. If cleared, consecutive transmissions can even start
within one ETU

3

DataEnIf cleared - it is possible to send a single symbol pattern.
If set - data is sent.

2 to 0TxLastBits

Defines how many bits of the last data byte to be sent. If set to 000b,
all bits of the last data byte are sent.
Note - bits are skipped at the end of the byte.
Example - Data byte B2h (sent LSB first).
TxLastBits = 011b (3h) => 010b (LSB first) is sent
TxLastBits = 110b (6h) => 010011b (LSB first) is sent

9.10.2 TxDATAModWidth
Transmitter data modulation width register
Table 147. TxDataModWidth register (address 2Fh)
Bit

7

6

5

4

3

SymbolDModWidth

Accessrights

r/w

2

1

0

Table 148. TxDataModWidth bits

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Bit

SymbolDescription

7 to 0DModWidth

Specifies the length of a pulse for sending data with enabled pulse
modulation. The length is given by the number of carrier clocks + 1.
A pulse can never be longer than from the start of the pulse to theend of the bit. The starting position of a pulse is given by the settingof TxDataMod.DPulseType. Note: This register is only used if Miller
modulation (ISO/IEC 14443A PCD) is used. The settings are also
used for the modulation width of start and/or stop symbols.

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9.10.3 TxSym10BurstLen
If a protocol requires a burst (an unmodulated subcarrier) the length can be defined withthis TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl.
Table 149. TxSym10BurstLen register (address 30h)
Bit

7

6

5

4

3

2

1

0

SymbolRFU

Sym1Burst Len

RFU

Sym0Burst Len

Accessrights

-

r/w

-

r/w

Table 150. TxSym10BurstLen bits
Bit

SymbolDescription

7

RFU

-

6 to 4

Sym1BurstLen Specifies the number of bits issued for symbol 1 burst. The 3 bits
encodes a range from 8 to 256 bit:
00h - 8bit
01h - 16bit
02h - 32bit
03h - 48bit
04h - 64bit
05h - 96bit
06h - 128bit
07h - 256bit

3

RFU

2 to 0Sym0BurstLen Specifies the number of bits issued for symbol 0 burst. The 3 bits
encodes a range from 8 to 256 bit:
00h - 8bit
01h - 16bit
02h - 32bit
03h - 48bit
04h - 64bit
05h - 96bit
06h - 128bit
07h - 256bit-

9.10.4 TxWaitCtrl
Table 151. TxWaitCtrl register (address 31h); reset value: C0h
Bit

7

6

SymbolTxWaitStart

TxWaitEtu

TxWait HighTxStopBitLength

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4

3

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Table 152. TXWaitCtrl bits
Bit

SymbolDescription

7

TxWaitStart

If cleared, the TxWait time is starting at the End of the send data
(TX).
If set, the TxWait time is starting at the End of the received data
(RX).

6

TxWaitEtu

If cleared, the TxWait time is TxWait × 16/13.56 MHz.
If set, the TxWait time is TxWait × 0.5 / DBFreq (DBFreq is thefrequency of the bit stream as defined by TxDataCon).

5 to 3TxWait HighBit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB.

2 to 0

TxStopBitLength

Defines stop-bits and EGT (= stop-bit + extra guard time EGT) to
be sent:
0h: no stop-bit, no EGT
1h: 1 stop-bit, no EGT
2h: 1 stop-bit + 1 EGT
3h: 1 stop-bit + 2 EGT
4h: 1 stop-bit + 3 EGT
5h: 1 stop-bit + 4 EGT
6h: 1 stop-bit + 5 EGT
7h: 1 stop-bit + 6 EGT
Note: This is only valid for ISO/IEC14443 Type B

9.10.5 TxWaitLo
Table 153. TxWaitLo register (address 32h)
Bit

7

6

5

4

3

SymbolTxWaitLo

Accessrights

r/w

2

1

0

Table 154. TxWaitLo bits
Bit

SymbolDescription

7 to 0

TxWaitLo

Defines the minimum time between receive and send or between two
send data streams
Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl
register)!
See also TxWaitEtu and TxWaitStart.

9.11 FrameCon
Table 155. FrameCon register (address 33h)
Bit

7

6

5

4

SymbolTxParityEn

RxParityEn--

StopSym

StartSym

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RFU

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2

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Table 156. FrameCon bits
Bit

SymbolDescription

7

TxParityEn

If set, a parity bit is calculated and appended to each byte
transmitted.

6

RxParityEn

If set, the parity calculation is enabled. The parity is not transferred to
the FIFO.

5 to 4-RFU

3 to 2StopSymDefines which symbol is sent as stop-symbol:• 0h: No symbol is sent
• 1h: Symbol0 is sent
• 2 h symbol1 is sent
• 3h Symbol2 is sent

1 to 0StartSym

Defines which symbol is sent as start-symbol:• 0h: No Symbol is sent
• 1h: Symbol0 is sent
• 2 h: Symbol1 is sent
• 3h: Symbol2 is sent

9.12 Receiver configuration registers
9.12.1 RxSofD
Table 157. RxSofD register (address 34h)
Bit

7

6

5

4

3

2

1

0

SymbolRFU

SOF_En

SOFDetected

RFU

SubC_En

SubC_Detected

SubC_Present

Accessrights

-

r/w

dy

-

r/w

dy

r

Table 158. RxSofD bits
Bit

SymbolDescription

7 to 6RFU-

5

SOF_EnIf set and a SOF is detected an RxSOFIRQ is raised.

4

SOF_Detected

Shows that a SOF is or was detected. Can be cleared by SW.

3

RFU

-

2

SubC_EnIf set and a subcarrier is detected an RxSOFIRQ is raised.

1

SubC_Detected

Shows that a subcarrier is or was detected. Can be cleared by SW.

0

SubC_Present

Shows that a subcarrier is currently detected.

9.12.2 RxCtrl
Table 159. RxCtrl register (address 35h)
Bit
Symbol

7

6

5

4

3

RxAllowBits

RxMultiple

RxEOFType

EGT_Check

EMD_Sup

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Table 159. RxCtrl register (address 35h)...continued
Bit

7

6

5

4

3

Accessrights

r/w

r/w

r/w

r/w

r/w

2

1

0

r/w

Table 160. RxCtrl bits
Bit

SymbolDescription

7

RxAllowBits

If set, data is written into FIFO even if CRC is enabled, and nocomplete byte has been received.

6

RxMultiple

If set, RxMultiple is activated and the receiver will not terminate
automatically (refer Section Section 8.10.3.6.
If set to logic 1, at the end of a received data stream an error byte isadded to the FIFO. The error byte is a copy of the Error register.

5

RxEOFType

0: EOF as defined in the RxEOFSymbolReg is expected.
1: ISO/IEC14443B EOF is expected.
Note: Clearing this bit to 0 and clearing bit 0 and bit 1 in the
RxEOFSymbolReg disables the EOF check.

4

EGT_CheckIf set to 1, the EGT is checked and if it is too longa protocol error is set. (This is only valid for ISO/IEC14443 Type B).

3

EMD_Sup

Enables the EMD suppression according to ISO/IEC14443. If an error
occurs within the first three bytes, these three bytes are assumed to
be EMD, ignored and the FIFO is reset. A collision is treated as anerror as well If a valid SOF was received, the EMD_Sup is set and aframe of less than 3 bytes had been received. RX_IRQ is not set inthis EMD error cases. If RxForceCRCWrite is set, the FIFO should not
be read out before three bytes are written into.

2 to 0Baudrate

Defines the baud rate of the receiving signal.
2h: 26 kBd
3h: 52 kBd
4h: 106 kBd
5h: 212 kBd
6h: 424 kBd
7h: 847 kBd
all remaining values are RFU

9.12.3 RxWait
Selects internal receiver settings.
Table 161. RxWait register (address 36h)
Bit

7

6

5

4

3

SymbolRxWaitEtu

RxWaitAccessrightsr/w

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Table 162. RxWait bits
Bit

SymbolDescription

7

RXWaitEtu

If set to 0, the RxWait time is RxWait × 16/13.56 MHz.
If set to 1, the RxWait time is RxWait × (0.5/DBFreq).

6 to 0

RxWaitDefines the time after sending, where every input is ignored.

9.12.4 RxThreshold
Selects minimum threshold level for the bit decoder.
Table 163. RxThreshold register (address 37h)
Bit

7

6

5

4

3

2

1

SymbolMinLevel

MinLevelP

Accessrights

r/w

r/w

0

Table 164. RxThreshold bits
Bit

SymbolDescription

7 to 4

MinLevel

Defines the MinLevel of the reception.
Note: The MinLevel should be higher than the noise level in the system.

3 to 0

MinLevelP

Defines the MinLevel of the phase shift detector unit.

9.12.5 Rcv
Table 165. Rcv register (address 38h)
Bit

7

6

5

4

3

2

1

0

Symbol

Rcv_Rx_single

Rx_ADCmode

SigInSel

RFU

CollLevel

Accessrights

r/w

r/w

r/w

-

r/w

Table 166. Rcv bits

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Bit

SymbolDescription

7

Rcv_Rx_single

Single RXP Input Pin Mode;
0: Fully Differential
1: Quasi-Differential

6

Rx_ADCmode

Defines the operation mode of the Analog Digital Converter (ADC)
0: normal reception mode for ADC
1: LPCD mode for ADC

5 to 4SigInSel

Defines input for the signal processing unit:
0h - idle
1h - internal analog block (RX)2h - signal in over envelope (ISO/IEC14443A)
3h - signal in over s3c-generic

3 to 2RFU

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Table 166. Rcv bits...continued
Bit

SymbolDescription

1 to 0CollLevel

Defines the strength of a signal to be interpreted as a collision:
0h - Collision has at least 1/8 of signal strength
1h - Collision has at least 1/4 of signal strength
2h - Collision has at least 1/2 of signal strength
3h - Collision detection is switched off

9.12.6 RxAna
This register allows setting the gain (rcv_gain) and high pass corner frequencies(rcv_hpcf).
Table 167. RxAna register (address 39h)
Bit

7

6

5

4

3

2

1

0

SymbolVMid_r_sel

RFU

rcv_hpcf

rcv_gainAccessrights

r/w

-

r/w

r/w

Table 168. RxAna bits
Bit

SymbolDescription

7, 6

VMid_r_sel

Factory trim value, needs to be 0.

5, 4

RFU

3, 2

rcv_hpcf

The rcv_hpcf [1:0] signals allow 4 different settings of the base band
amplifier high pass cut-off frequency from ~40 kHz to ~300 kHz.

1 to 0rcv_gainWith rcv_gain[1:0] four different gain settings from 30 dB and 60
dB can be configured (differential output voltage/differential input
voltage).

Table 169. Effect of gain and high-pass corner register settings

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rcv_gain(Hex.)

rcv_hpcf(Hex.)fl (kHz)fU (MHz)

gain (dB20)

bandwidth
(MHz)

03

00

38

2.3

60

2.3

03

01

79

2.4

59

2.3

03

02

150

2.6

58

2.5

03

03

264

2.9

55

2.6

02

00

41

2.3

51

2.3

02

01

83

2.4

50

2.3

02

02

157

2.6

49

2.4

02

03

272

3.0

41

2.7

01

00

42

2.6

43

2.6

01

01

84

2.7

42

2.6

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Table 169. Effect of gain and high-pass corner register settings...continued
rcv_gain(Hex.)

rcv_hpcf(Hex.)fl (kHz)fU (MHz)

gain (dB20)

bandwidth
(MHz)

01

02

157

2.9

41

2.7

01

03

273

3.3

39

3.0

00

00

43

2.6

35

2.6

00

01

85

2.7

34

2.6

00

02

159

2.9

33

2.7

00

03

276

3.4

30

3.1

9.13 Clock configuration
9.13.1 SerialSpeed
This register allows setting speed of the RS232 interface. The default speed is set to115.2 kbit/s. The transmission speed of the interface can be changed by modifying
the entries for BR_T0 and BR_T1. The transfer speed can be calculated by using thefollowing formulas:
BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)
The framing is implemented with 1 start bit, 8 data bits and 1 stop bit. A parity bit is not
used. Transfer speeds above 1228.8 kbit/s are not supported.
Table 170. SerialSpeed register (address3Bh); reset value: 7Ah
Bit

7

6

5

4

3

2

Symbol

BR_T0

BR_T1

Accessrights

r/w

r/w

1

0

Table 171. SerialSpeed bits
Bit

Symbol Description

7 to 5 BR_T0

BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)

4 to 0 BR_T1

BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)

Table 172. RS232 speed settings
Transfer speed (kbit/s)

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SerialSpeed register content (Hex.)

7.2

FA

9.6

EB

14.4

DA
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Table 172. RS232 speed settings...continued
Transfer speed (kbit/s)

SerialSpeed register content (Hex.)

19.2

CB

38.4

AB

57.6

9A

115.2

7A

128.0

74

230.4

5A

460.8

3A

921.6

1C

1228.815

9.13.2 LFO_Trimm
Table 173. LFO_Trimm register (address 3Ch)
Bit

7

6

5

4

3

Symbol

LFO_trimm

Accessrights

r/w

2

1

0

Table 174. LFO_Trimm bits
Bit

SymbolDescription

7 to 0

LFO_trimm

Trimm value. Refer to Section Section 8.8.3.
Note: If the trimm value is increased, the frequency of the oscillator
decreases.

9.13.3 PLL_Ctrl Register
The PLL_Ctrl register implements the control register for the IntegerN PLL. Two stages
exist to create the ClkOut signal from the 27.12 MHz input. In the first stage, the 27.12
MHz input signal is multiplied by the value defined in PLLDiv_FB and divided by two, andthe second stage divides this frequency by the value defined by PLLDIV_Out.
Table 175. PLL_Ctrl register (address3Dh)
Bit

7

6

5

4

3

2

1

0

Symbol

ClkOutSel

ClkOut_En

PLL_PD

PLLDiv_FB

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Table 176. PLL_Ctrl register bits
Bit

SymbolDescription

7 to 4

CLkOutSel• 0h - pin CLKOUT is used as I/O• 1h - pin CLKOUT shows the output of the analog PLL• 2h - pin CLKOUT is hold on 0
• 3h - pin CLKOUT is hold on 1
• 4h - pin CLKOUT shows 27.12 MHz from the crystal• 5h - pin CLKOUT shows 13.56 MHz derived from the crystal• 6h - pin CLKOUT shows 6.78 MHz derived from the crystal• 7h - pin CLKOUT shows 3.39 MHz derived from the crystal• 8h - pin CLKOUT is toggled by the Timer0 overflow• 9h - pin CLKOUT is toggled by the Timer1 overflow• Ah - pin CLKOUT is toggled by the Timer2 overflow• Bh - pin CLKOUT is toggled by the Timer3 overflow• Ch...Fh - RFU

3

ClkOut_En

Enables the clock at Pin CLKOUT2

PLL_PD

PLL power down

1-0

PLLDiv_FB

PLL feedback divider

Table 177. Setting of feedback divider PLLDiv_FB [1:0]
Bit 1

Bit 0

Division0023 (VCO frequency 312 MHz)01

27 (VCO frequency 366 MHz)1

028 (VCO frequency 380 Mhz)

1

1

23 (VCO frequency 312 Mhz)

9.13.4 PLLDiv_Out
Table 178. PLLDiv_Out register (address 3Eh)
Bit

7

6

5

4

3

SymbolPLLDiv_Out

Accessrights

r/w

2

1

0

Table 179. PLLDiv_Out bits
Bit

SymbolDescription

7 to 0

PLLDiv_Out

PLL output divider factor; refer to Section Section 8.8.2.

Table 180. Setting for the output divider ratio PLLDiv_Out [7:0]

CLRC663

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Value

Division

0

RFU

1

RFU
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Table 180. Setting for the output divider ratio PLLDiv_Out [7:0]...continued
Value

Division

2

RFU

3

RFU

4

RFU

5

RFU

6

RFU

7

RFU

8

8

9

9

10

10

...

...

253

253

254

254

255

255

9.14 Low-power card detection configuration registers
The LPCD registers contain the settings for the low-power card detection. The setting
for LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers
LPCD_QMin, LPCD_QMax and LPCD_IMin each.

9.14.1 LPCD_QMin
Table 181. LPCD_QMin register (address 3Fh)
Bit

7

6

5

4

3

2

SymbolLPCD_IMax.5

LPCD_IMax.4

LPCD_QMin

Accessrights

r/w

r/w

r/w

1

0

Table 182. LPCD_QMin bits

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Bit

SymbolDescription

7, 6

LPCD_IMax

Defines the highest two bits of the higher border for the LPCD. If themeasurement value of the I channel is higher than LPCD_IMax, an
LPCD interrupt request is indicated by bit IRQ0.LPCDIRQ.

5 to 0

LPCD_QMin

Defines the lower border for the LPCD. If the measurement value ofthe Q channel is higher than LPCD_QMin, an LPCDinterrupt request
is indicated by bit IRQ0.LPCDIRQ.

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9.14.2 LPCD_QMax
Table 183. LPCD_QMax register (address 40h)
Bit

7

6

5

4

3

2

SymbolLPCD_IMax.3

LPCD_IMax.2

LPCD_QMax

Accessrights

r/w

r/w

r/w

1

0

Table 184. LPCD_QMax bits
Bit

SymbolDescription

7

LPCD_IMax.3

Defines the bit 3 of the high border for the LPCD. If themeasurement value of the I channel is higher than LPCD IMax, an
LPCD IRQ is raised.

6

LPCD_IMax.2

Defines the bit 2 of the high border for the LPCD. If themeasurement value of the I channel is higher than LPCD IMax, an
LPCD IRQ is raised.

5 to 0

LPCD_QMax

Defines the high border for the LPCD. If the measurement value ofthe Q channel is higher than LPCD QMax, an LPCD IRQ is raised.

9.14.3 LPCD_IMin
Table 185. LPCD_IMin register (address 41h)
Bit

7

6

5

SymbolLPCD_IMax.1

LPCD_IMax.0

LPCD_IMin

Accessrights

r/w

r/w

4

3

2

1

0

r/w

Table 186. LPCD_IMin bits
Bit

SymbolDescription

7 to 6

LPCD_IMax

Defines lowest two bits of the higher border for the low-power card
detection (LPCD). If the measurement value of the I channel is higher
than LPCD IMax, an LPCD IRQ is raised.

5 to 0

LPCD_IMin

Defines the lower border for the low power card detection. If themeasurement value of the I channel is lower than LPCD IMin, an
LPCD IRQ is raised.

9.14.4 LPCD_Result_I
Table 187. LPCD_Result_I register (address 42h)
Bit

7

6

SymbolRFU-

RFU-

LPCD_Result_I

Accessrights--r

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5

4

3

2

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Table 188. LPCD_Result_I bits
Bit

SymbolDescription

7 to 6RFU-

5 to 0

LPCD_Result_I Shows the result of the last low-power card detection (I-Channel).

9.14.5 LPCD_Result_Q
Table 189. LPCD_Result_Q register (address 43h)
Bit

7

6

5

4

3

2

SymbolRFU

LPCD_
IRQ_Clr

LPCD_Reslult_Q

Accessrights

-

r/w

r

1

0

Table 190. LPCD_Result_Q bits
Bit

SymbolDescription

7

RFU

-

6

LPCD_IRQ_Clr

If set no LPCD IRQ is raised any more until the next low-powercard detection procedure. Can be used by software to clear theinterrupt source.

5 to 0

LPCD_Result_Q

Shows the result of the last low power card detection (QChannel).

9.14.6 LPCD_Options
This register is available on the CLRC66303 only. For silicon versions CLRC66301 and
CLRC66302 this register on address 3AH is RFU.
Table 191. LPCD_Options register (address 3Ah)
Bit

7

Symbol

6

5

4

RFU
-

Accessrights32

1

0LPCD_TX_HIGH

LPCD_FILTERLPCD_Q_UNSTABLE

LPCD_I_UNSTABLE

r/w

r/w

r

r

Table 192. LPCD_Options
Bit

SymbolDescription

7 to 4RFU-

3LPCD_TX_HIGH

If set, the TX-driver will be the same as VTVDD during LPCD. This will allow fora better LPCD detection range (higher transmitter output voltage) at the cost ofa higher current consumption. If this bit is cleared, the output voltage at the TX
drivers will be = TVDD- 0.4V. If this bit is set, the output voltage at the TX drivers
will be = VTVDD.

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Table 192. LPCD_Options...continued
Bit

SymbolDescription

2

LPCD_FILTER

If set, The LPCD decision is based on the result of a filter which allows toremove noise from the evaluated signal in I and Q channel. Enabling LPCD_FILTER allows compensating for noisy conditions at the cost of a longer RF-ON
time required for sampling. The total maximum LPCD sampling time is 4.72us.

1

LPCD_Q_UNSTABLE

If bit 2 of this register is set, bit 1 indicates that the Q-channel ADC value waschanging during the LPCD measuring time. Note: Only valid if LPCD_FILTER (bit2) = 1. This information can be used by the host application for configuration ofe.g. the threshold LPCD_QMax or inverting the TX drivers.

0

LPCD_I_UNSTABLE

If bit 2 of this register is set, bit 0 Indicates that the I-channel ADC value waschanging during the LPCD measuring time. Note: Only valid if LPCD_FILTER(bit2) = 1. This information can be used by the host application for configurationof e.g. the threshold LPCD_IMax or inverting the TX drivers.

9.15 Pin configuration
9.15.1 PadEn
Table 193. PadEn register (address 44h)
Bit

7

6

5

4

3

2

1

0

SymbolSIGIN_
EN / OUT7

CLKOUT_
EN / OUT6IFSEL1_
EN / OUT5IFSEL0_EN / OUT4

TCK_EN /OUT 3

TMS_EN /OUT2

TDI_EN /OUT1

TDO_EN /OUT0

Accessrights

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

Table 194. PadEn bits

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Bit

SymbolDescription

7

SIGIN_EN / OUT7

Enables the output functionality on SIGIN (pin 5). The pin isthen used as output.

6

CLKOUT_EN / OUT6

Enables the output functionality of the CLKOUT (pin 22). The
pin is then used as output. The CLKOUT function is switched
off.

5

IFSEL1_EN / OUT5

Enables the output functionality of the IFSEL1 (pin 27). The
pin is then used as output.

4

IFSEL0_EN / OUT4

Enables the output functionality of the IFSEL0 (pin 26). The
pin is then used as output.

3

TCK_EN / OUT3

Enables the output functionality of the TCK (pin 4) of theboundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has nofunction.

2

TMS_EN / OUT2

Enables the output functionality of the TMS (pin 2) of theboundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has nofunction.

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Table 194. PadEn bits...continued
Bit

SymbolDescription

1

TDI_EN / OUT1

Enables the output functionality of the TDI (pin 1) of theboundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has nofunction.

0

TDO_EN / OUT0

Enables the output functionality of the TDO(pin 3) of theboundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has nofunction.

9.15.2 PadOut
Table 195. PadOut register (address 45h)
Bit

7

6

5

SymbolSIGIN_OUT

CLKOUT_OUT

Accessrights

r/w

r/w

4

3

2

1

0

TDI_OUTTDO_OUT

r/w

r/w

r/w

IFSEL1_OUT IFSEL0_OUT TCK_OUT TMS_OUT
r/w

r/w

r/w

Table 196. PadOut bits
Bit

SymbolDescription

7

SIGIN_OUT

Output buffer of the SIGIN pin

6

CLKOUT_OUT

Output buffer of the CLKOUT pin

5

IFSEL1_OUT

Output buffer of the IFSEL1 pin

4

IFSEL0_OUT

Output buffer of the IFSEL0 pin

3

TCK_OUT

Output buffer of the TCK pin

2

TMS_OUT

Output buffer of the TMS pin

1

TDI_OUT

Output buffer of the TDI pin0

TDO_OUT

Output buffer of the TDO pin

9.15.3 PadIn
Table 197. PadIn register (address 46h)
Bit

7

6

5

4

3

2

1

0

SymbolSIGIN_IN

CLKOUT_IN

IFSEL1_IN

IFSEL0_IN

TCK_INTMS_IN

TDI_IN

TDO_IN

Accessrights

r

r

r

r

r

r

r

r

Table 198. PadIn bits

CLRC663

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Bit

SymbolDescription

7

SIGIN_IN

Input buffer of the SIGIN pin

6

CLKOUT_IN

Input buffer of the CLKOUT pin

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Table 198. PadIn bits...continued
Bit

SymbolDescription

5

IFSEL1_IN

Input buffer of the IFSEL1 pin

4

IFSEL0_IN

Input buffer of the IFSEL0 pin

3

TCK_IN

Input buffer of the TCK pin

2

TMS_IN

Input buffer of the TMS pin

1

TDI_IN

Input buffer of the TDI pin

0

TDO_IN

Input buffer of the TDO pin

9.15.4 SigOut
Table 199. SigOut register (address 47h)
Bit

7

6

5

4

3

2

1

Symbol

Pad
Speed

RFU

SigOutSel

Accessrights

r/w

-

r/w

0

Table 200. SigOut bits

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Bit

SymbolDescription

7

PadSpeed

If set, the I/O pins are supporting a fast switching mode.The fast mode
for the I/O’s will increase the peak current consumption of the device,especially if multiple I/Os are switching at the same time. The power
supply needs to be designed to deliver this peak current.

6 to 4RFU-

3 to 0

SIGOutSel

0h, 1h - The pin SIGOUT is 3-state
2h - The pin SIGOUT is 0
3h - The pin SIGOUT is 1
4h - The pin SIGOUT shows the TX-envelope
5h - The pin SIGOUT shows the TX-active signal
6h - The pin SIGOUT shows the S3C (generic) signal
7h - The pin SIGOUT shows the RX-envelope(only valid for ISO/IEC 14443A, 106 kBd)
8h - The pin SIGOUT shows the RX-active signal
9h - The pin SIGOUT shows the RX-bit signal
0Ah ...0Fh: RFU

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9.16 Protocol configuration registers
9.16.1 TxBitMod
Table 201. TxBitMod register (address 48h)
Bit

7

6

5

4

3

2

1

0

SymbolTxMSBFirstRFU

TxParity
Type

RFU

TxStopBitType

RFU

TxStartBitType

TxStartBitEn

Accessrights

r/w

-

r/w

-

r/w

-

r/w

r/w

Table 202. TxBitMod bits
Bit

SymbolDescription

7

TxMSBFirst

If set, data is interpreted MSB first for data transmission. If cleared,
data is interpreted LSB first.

6

RFU

-

5

TxParityType

Defines the type of the parity bit. If set to 1, odd parity is calculated,otherwise even parity is calculated.

4

RFU

-

3

TxStopBitType Defines the type of the stop-bit (0b: logic zero / 1b: logic one).

2

RFU

1

TxStartBitType Defines the type of the start-bit (0b: logic zero / 1b: logic one).

0

TxStartBitEn

If set to 1, a start-bit will be sent.

9.16.2 TxDataCon
Table 203. TxDataCon (address 4Ah)
Bit

7

6

5

4

3

2

1

SymbolDCodeTypeDSCFreq

DBFreqAccessrights

r/w

r/w

r/w

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Table 204. TxDataCon bits
Bit

SymbolDescription

7 to 4

DCodeTypeSpecifies the type of encoding of data to be used:
0h - no special coding
1h - collider datastream is decoded
2h - RFU 3h - RFU
4h - return to zero code - pulse at first position
5h - return to zero code - pulse at 2nd position
6h - return to zero code - pulse at 3rd position
7h - return to zero code - pulse at 4th position
8h - 1 out of 4 coding
9h - 1 out of 256 code (range 0 - 255) [ICODE SLI]
Ah - 1 out of 256 code (range 0 - 255; 00h is encoded with nomodulation, value 256 not used) [ICODE 1]
Bh - 1 out of 256 code (range 0 - 255; 00h is encoded with a pulse on
last position) [ICODE quite value]
Ch- Pulse internal encoded (PIE) [ISO/IEC 18000-3 mode 3/ EPC
Class-1HF]
Dh - RFU
Eh - RFU
Fh - RFU

3

DSCFreq

Specifies the subcarrier frequency of the used envelope.
0h - 424 kHz
1h - 848 kHz
Note: This setting is only relevant, if an envelope is used which
involves a subcarrier, e.g. Manchester with subcarrier coding.

2 to 0

DBFreqSpecifies the frequency of the bit stream:
0h - RFU
1h - RFU
2h - 26 kHz
3h - 53 kHz
4h - 106 kHz
5h - 212 kHz
6h - 424 kHz
7h - 848 kHz

9.16.3 TxDataMod
Table 205. TxDataMod register (address 4Bh)
Bit

7

6

SymbolFrame step

DMillerEn

DPulseType

DInvertDEnvType

Accessrights

r/w

r/w

r/w

r/w

r/w

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5

4

3

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Table 206. TxDataMod bits
Bit

SymbolDescription

7

Framestep

If set to 1, at every start of transmission, each byte of data is sent
in a separate frame. SOF and EOF are appended to the data byte
according to the framing settings. After one byte is transmitted, theTxEncoder waits for a new start trigger to continue with the next byte
(trigger is generated automatically). If set to 0, transmission is donein the used way, where after a start trigger all data bytes are sent andthe framing is done for the complete data stream only once.

6

DMillerEn

If set, pulse modulation is applied according to modified miller code.
Note: This bit is intended to be set if DPulseType is 1h.

5 to 4

DPulseTypeSpecifies which type of pulse modulation is selected.
0 h - no pulse modulation
1h - pulse starts at beginning of bit
2h - pulse starts at beginning of second bit half
3h - pulse starts at beginning of third bit quarter
Note: If DMillerEn is set, DPulseType must be set to 1h.

3DInvertIf set the envelope of data is inverted.

2 to 0DEnvType

Specifies the type of envelope used for transmission of data packets.
The selected envelope type is applied to the pseudo bit stream.
0h - Direct output
1h - Manchester code
2h - Manchester code with subcarrier
3h - BPSK
4h - RZ (pulse of half bit length at beginning of second half of bit)
5h - RZ (pulse of half bit length at beginning of bit)
6h - RFU
7h - RFU

9.16.4 TxSymFreq
Table 207. TxSymFreq (address 4Ch)
Bit

7

6

5

4

3

2

1

SymbolS32SCFreq

S32BFreq

S10SCFreq

S10BFreq

Accessrights

r/w

r/w

r/w

r/w

0

Table 208. TxSymFreq bits

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Bit

SymbolDescription

7

S32SCFreq

Specifies the frequency of the subcarrier of symbol2 and symbol3:
0b ... 424 kHz
1b ... 848 kHz

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Table 208. TxSymFreq bits...continued
Bit

SymbolDescription

6 to 4

S32BFreq

Specifies the frequency of the bit stream of symbol2 and symbol3:000b ... RFU
001b ... RFU
010b ... 26 kHz
011b ... 53 kHz
100b ... 106 kHz
101b ... 212 kHz
110b ... 424 kHz
111b ... 848 kHz

3S10SCFreq

Specifies the frequency of the subcarrier of symbol0 and symbol1:
0b ...424 kHz
1b ...848 kHz

2 to 0S10BFreq

Specifies the frequency of the bit stream of symbol0 and symbol1:000b ... RFU
001b ... RFU
010b ... 26 kHz
011b ... 53 kHz
100b ... 106 kHz
101b ... 212 kHz
110b ... 424 kHz
111b ... 848 kHz

9.16.5 TxSym0
The two Registers TxSym0_H and TxSym0_L create a 16-bit register that contains thepattern for Symbol0.
Table 209. TxSym0_H (address 4Dh)
Bit

7

6

5

4

3

SymbolSymbol0_H

Accessrights

r/w

2

1

0

1

0

Table 210. TxSym0_H bits
Bit

SymbolDescription

7 to 0

Symbol0_H

Higher 8 bits of symbol definition for Symbol0.

Table 211. TxSym0_L (address 4Eh)
Bit

7

6

5

4

3

SymbolSymbol0_L

Accessrightsr/w

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Table 212. TxSYM0_L bits
Bit

SymbolDescription

7 to 0

Symbol0_L

Lower 8 bits of symbol definition for Symbol0.

9.16.6 TxSym1
The two Registers TxSym1_H and TxSym1_L create a 16 bit register that contains thepattern for Symbol1.
Table 213. TxSym1_H (address 4Fh)
Bit

7

6

5

4

3

SymbolSymbol1_H

Accessrights

r/w

2

1

0

1

0

1

0

Table 214. TxSym1_H bits
Bit

SymbolDescription

7 to 0

Symbol1_H

Higher 8 bits of symbol definition for Symbol1.

Table 215. TxSym1_L (address 50h)
Bit

7

6

5

4

3

SymbolSymbol1_L

Accessrightsr/w

2

Table 216. TxSym1_L bits
Bit

SymbolDescription

7 to 0

Symbol1_L

Lower 8 bits of symbol definition for Symbol1.

9.16.7 TxSym2
Table 217. TxSYM2 (address 51h)
Bit

7

6

5

4

3

SymbolSymbol2

Accessrightsr/w

2

Table 218. TxSym2 bits

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Bit

SymbolDescription

7 to 0

Symbol2

Symbol definition for Symbol2.

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9.16.8 TxSym3
Table 219. TxSym3 (address 52h)
Bit

7

6

5

4

3

SymbolSymbol3

Accessrights

r/w

2

1

0

2

1

0

Table 220. TxSym3 bits
Bit

SymbolDescription

7 to 0

Symbol3

Symbol definition for Symbol3.

9.16.9 TxSym10Len
Table 221. TxSym10Len (address 53h)
Bit

7

6

5

4

3

SymbolSym1Len

Sym0LenAccessrightsr/w

r/w

Table 222. TxSym10Len bits
Bit

SymbolDescription

7 to 4

Sym1LenSpecifies the number of valid bits of the symbol definition of Symbol1.
The range is from 1 bit (0h) to 16 bits (Fh).

3 to 0Sym0LenSpecifies the number of valid bits of the symbol definition of Symbol0.
The range is from 1 bit (0h) to 16 bits (Fh).

9.16.10 TxSym32Len
Table 223. TxSym32Len (address 54h)
Bit

7

SymbolRFU

Accessrights

-

6

5

4

2

RFU

Sym3Len
r/w

3

r/w

r/w

-

1

0

Sym2Len
r/w

r/w

r/w

Table 224. TxSym32Len bits

CLRC663

Product data sheet
COMPANY PUBLIC

Bit

SymbolDescription

7

RFU

-

6 to 4

Sym3LenSpecifies the number of valid bits of the symbol definition of Symbol3.
The range is from 1 bit (0h) to 8 bits (7h).

3

RFU

-

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Table 224. TxSym32Len bits...continued
Bit

SymbolDescription

2 to 0Sym2LenSpecifies the number of valid bits of the symbol definition of Symbol2.
The range is from 1 bit (0h) to 8 bits (7h).

9.16.11 TxSym10BurstCtrl
Table 225. TxSym10BurstCtrl register (address 55h)
Bit

7

6

5

4

3

2

1

0

SymbolRFU

Sym1BurstType

Sym1BurstOnly

Sym1BurstEn

RFU

Sym0Burst
Type

Sym0B
urstOnly

Sym0B
urstEnAccessrights

-

r/w

r/w

r/w

-

r/w

r/w

r/w

Table 226. TxSym10BurstCtrl bits
Bit

SymbolDescription

7

RFU

-

6

Sym1BurstType

Specifies the type of the burst of Symbol1 (logical zero / logical
one).

5

Sym1BurstOnly

If set to 1 Symbol1 consists only of a burst and no symbol
pattern.

4

Sym1BurstEn

Enables the burst of symbol 1 of the length defined in
TxSym10BurstLen.

3

RFU

-

2

Sym0BurstType

Specifies the type of the burst of symbol 0 (logical zero / logical
one).

1

Sym0BurstOnly

If set to 1, symbol 0 consists only of a burst and no symbol
pattern.

0

Sym0BurstEn

Enables the burst of symbol 0 of the length defined in
TxSym10BurstLen.

9.16.12 TxSym10Mod Reg
Table 227. TxSym10Mod register (address 56h)
Bit

7

6

5

4

3

2

1

SymbolRFU

S10MillerEn

S10PulseType

S10Inv

S10EnvType

Accessrights

-

r/w

r/w

r/w

r/w

0

Table 228. TxSym10Mod bits

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Bit

SymbolDescription

7

RFU

-

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Table 228. TxSym10Mod bits...continued
Bit

SymbolDescription

6

S10MillerEn

If set, pulse modulation is applied according to modified miller code.
Note: This bit shall be set only if S10PulseType is set to 1h.

5 to 4

S10PulseType Specifies which type of pulse modulation is selected:
0h - no pulse modulation
1h - pulse starts at beginning of bit
2h - pulse starts at beginning of second bit half
3h - pulse starts at beginning of third bit quarter3

S10Inv

If set. the output of Symbol0 and Symbol1 is inverted.

2 to 0S10EnvTypeSpecifies the type of envelope used for transmission of Symbol0
and Symbol1. The pseudo bit stream is logically combined with theselected envelope type.
0h - Direct output
1h - Manchester code
2h - Manchester code with subcarrier
3h - BPKSK
4h - RZ return zero, pulse of half bit length at beginning of second halfof bit5h - RZ return zero, pulse of half bit length at beginning of second halfof bit6h - RFU
7h - RFU

9.16.13 TxSym32Mod
Table 229. TxSym32Mod register (address 57h)
Bit

7

6

5

4

3

2

1

SymbolRFU

S32MillerEn

S32PulseType

S32Inv

S32EnvType

Accessrights

-

r/w

r/w

r/w

r/w

0

Table 230. TxSym32Mod bits

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Bit

SymbolDescription

7

RFU

-

6

S32MillerEn

If set, pulse modulation is applied according to modified miller code.
Note: This bit shall be set only if S32PulseType is set to 1h.

5 to 4

S32PulseType Specifies which type of pulse modulation is selected:
0h - no pulse modulation
1h - pulse starts at beginning of bit
2h - pulse starts at beginning of second bit half
3h - pulse starts at beginning of third bit quarter3

S32Inv

If set. the output of Symbol2 and Symbol3 is inverted.

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Table 230. TxSym32Mod bits...continued
Bit

SymbolDescription

2 to 0S32EnvTypeSpecifies the type of envelope used for transmission of symbol 0
and symbol 1. The bit stream is logically combined with the selectedenvelope type.
0h - Direct output
1h - Manchester code
2h - Manchester code with subcarrier
3h - BPSK
4h - RZ return zero, pulse of half bit length at beginning of second halfof bit)5h - RZ return zero, pulse of half bit length at beginning of bit)
6h to 7h RFU

9.17 Receiver configuration
9.17.1 RxBitMod
Table 231. RxBitMod (address 58h)
Bit

7

6

5

4

3

2

1

0

SymbolRFU

RFU

RxStopOnInvPar

RxStopOnLength

RxMSBFirst

RxStopBitEn

RxParityType

RFU

Accessrights

-

-

r/w

r/w

r/w

r/w

r/w

-

Table 232. RxBitMod bits

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Bit

SymbolDescription

7 to 6RFU-

5

RxStopOnInvPar

If set to 1, inverse parity bit is a stop condition.

4

RxStopOnLength

If set to 1, data reception stops when the number of received
bytes reach the defined frame length. The value for theframe length is taken from the first data-byte received.

3

RxMSBFirst

If set to 1, data bytes are interpreted MSB first for data
reception, which means data is converted at the CLCoProinterface. If this bit is set to 0, data is interpreted LSB first.

2

RxStopBitEn

If set, a stop-bit is expected and will be checked andextracted from data stream. Additionally on detection ofa stop-bit a reset signal for the demodulator is generator
to enable a resynchronization of the demodulator. If the
expected stop-bit is incorrect, a frame error flag is set andthe reception is aborted.
Note: A stop bit is always considered to be a logic 1

1

RxParityType

Defines which type of the parity-bit is calculated:
If cleared: Even parity
If set: Odd parity

0

RFU

-

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9.17.2 RxEofSym
Table 233. RxEofSym (address 59h)
Bit

7

6

5

4

3

SymbolRxEOFSymbol

Accessrights

r/w

2

1

0

Table 234. RxEOFSym bits
Bit

SymbolDescription

7 to 0RxEOF
SymbolThis value defines the pattern of the EOF symbol with a maximum
length of 4 bit. Every tuple of 2 bits of the RxEOFSymbol encodes
one bit of the EOF symbol. A 00 tuple closes the symbol. In this way
symbols with less than 4 bits can be defined, starting with the bit0
and bit1. The leftmost active symbol pattern is processed first, whichmeans the pattern is expected first. If the bit0 and bit1 are both zero,
the EOF symbol is disabled. The following mapping is defined:
0h - no symbol bit
1h - zero value
2h - one value
3h - collision
Example:1Dh: Zero-Collision-ZeroE8h: No symbol because two LSBits are zero9.17.3 RxSyncValH
Table 235. RxSyncValH register (address5Ah)
Bit

7

6

5

4

3

SymbolRxSyncValH

Accessrights

r/w

2

1

0

Table 236. RxSyncValH bits
Bit

SymbolDescription

7 to 0RxSyncValH

Defines the high byte of the Start Of Frame (SOF) pattern, which must
be in front of the receiving data.

9.17.4 RxSyncValL
Table 237. RxSyncValL register (address 5Bh)
Bit

7

6

5

4

3

SymbolRxSyncValL

Accessrightsr/w

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Table 238. RxSyncValL bits
Bit

SymbolDescription

7 to 0RxSyncValL

Defines the low byte of the Start Of Frame (SOF) Pattern, which must
be in front of the receiving data.

9.17.5 RxSyncMod
Table 239. RxSyncMode register (address 5Ch)
Bit

7

6

5

4

3

2

1

0

SymbolSyncLen

SyncNegEdge

LastSyncHalf

SyncType

Accessrights

r/w

r/w

r/w

r/w

Table 240. RxSyncMod bits
Bit

SymbolDescription

7 to 4

SyncLenDefines how many Bits of registers RxSyncValH and RxSyncValL arevalid. For ISO/IEC 14443B set to 0.

3

SyncNegEdge Is used for SOF with no correlation peak. The first negative edge ofthe correlation is used for defining the bit grid.

2

LastSyncHalf

The last Bit of the Sync mode has only half of the length compared toall other bits. (ISO/IEC 18000-3 mode 3/ EPC Class-1HF).

1 to 0

SyncType

0: all 16 bits of SyncVal are interpreted as burst.
1: a nibble of bits is interpreted as one bit in following way:{data, coll} data = zero or one; coll = 1 means a collision on this bit.
Note: if Coll = 1 the value of data is ignored.
2: the synchronization is done at every start bit of each byte (type B)
3: RFU

9.17.6 RxMod
Table 241. RxMod register (address 5Dh)
Bit

7

6

5

4

3

2

1

0

SymbolRFU

RFU

PreFilter

RectFilter

SyncHigh

CorrInv

FSK

BPSK

Accessrights

-

-

r/w

r/w

r/w

r/w

r/w

r/w

Table 242. RxMod bits

CLRC663

Product data sheet
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Bit

SymbolDescription

7 to 6-RFU

5PreFilter

If set 4 samples are combined to one data. (average).

4

RectFilter

If set, the ADC-values are changed to a more rectangular wave
shape.

3

SyncHigh

Defines if the bit grid is fixed at maximum (1) or at minimum (0) valueof the correlation.

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Table 242. RxMod bits...continued
Bit

SymbolDescription

2

CorrInv

Defines a logical for Manchester coding:
0: subcarrier / no subcarrier.

1

FSK

If set to 1, the demodulation scheme is set to FSK.

0

BPSK

If set to 1, the modulation scheme is BPSK.

9.17.7 RxCorr
Table 243. RxCorr register (address 5Eh)
Bit

7

SymbolAccessrights6

5

CorrFreqr/w

4

3

CorrSpeed
r/w

r/w

r/w

2

1

0

CorrLen

RFU

r/w

-

Table 244. RxCorr bits
Bit

SymbolDescription

7, 6

CorrFreq

0h - 212 kHz
1h - 424 kHz
2h - 848 kHz
3h - 848 kHz

5, 4

CorrSpeed

Defines the number of clocks used for one correlation.
0h - ISO/IEC 14443
1h - ICODE 53 kBd, FeliCa 424 kBd
2h - ICODE 26 kBd, FeliCa 212 kBd
3h - RFU

3

CorrLenDefines the length of the correlation data. (64 or 32 values).
If set the lengths of the correlation data is 32 values. (ISO/IEC
18000-3 mode 3/ EPC Class-1HF, 2 Pulse Manchester 848 kHz
subcarrier).

2 to 0RFU-

9.17.8 FabCali
Table 245. FabCali register (address 5Fh)
Bit

7

6

5

4

3

SymbolFabCali

Accessrights

r/w

2

1

0

Table 246. FabCali bits

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Bit

SymbolDescription

7 to 0FabCali

Fabrication calibration of the receiver.
NOTE: do not change boot value.

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9.18 Version register
9.18.1 Version
Table 247. Version register (address 7Fh)
Bit

7

6

5

4

3

2

1

SymbolVersion

SubVersion

Accessrightsrr

0

Table 248. Version bits
Bit

SymbolDescription

7 to 4

VersionIncludes the version of the CLRC663 silicon.
CLRC66301: 0x1
CLRC66302: 0x1
CLRC66303: 0x1

3 to 0

SubVersion

Includes the subversion of the CLRC663 silicon.
CLRC66301: 0x8
CLRC66302: 0x8 -No difference of the silicon between versions
CLRC66301 and CLRC66302
CLRC66303: 0xA
LPCD_OPTIONS register had been added compared to earlier
version of the CLRC663. Default configuration for LoadProtocol
updated for improved performance. User EEPROM initialized withdata. Transmitter driver allows higher ITVDD than lower SubVersions.

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10 Limiting values
Table 249. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
SymbolParameter

VDD

Conditions

Min

Max

Unit

supply voltage

-0.5

+6.0

V

VDD(PVDD)

PVDD supply voltage

-0.5

+6.0

V

VDD(TVDD)

TVDD supply voltage

-0.5

+6.0

V

IDD(TVDD)

TVDD supply current

CLRC66301, CLRC66302

-

250

mA

CLRC66303

-

500

mA

Vi(RXP)

input voltage on pin RXP

-0.5

+2.0

V

Vi(RXN)

input voltage on pin RXN

-0.5

+2.0

V

Ptot

total power dissipation

-

1125

mW

;

-2000

2000

V

[2]

-500

500

V

-

+150

°C

-55

+150

°C

VESD

per package

electrostatic discharge voltage human body model (HBM)
1500 Ω, 100 pF[1]

charge device model (CDM)
Tj(max)maximum junction
temperature

Tstg

storage temperature

[1]
[2]

no supply voltage applied

According to ANSI/ESDA/JEDEC JS-001.
According to ANSI/ESDA/JEDEC JS-002.

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11 Recommended operating conditions
Exposure of the device to other conditions than specified in the Recommended Operating
Conditions section for extended periods may affect device reliability.
Electrical parameters (minimum, typical and maximum) of the device are guaranteed only
when it is used within the recommended operating conditions.
Table 250. Operating conditions CLRC66301, CLRC66302
SymbolParameter

VDD

supply voltage

Conditions
[1]

Min

Typ

Max

Unit

3.0

5.0

5.5

V

3.0

5.0

5.5

V

VDD(TVDD)

TVDD supply voltage

VDD(PVDD)

PVDD supply voltage

all host interfaces

3.0

5.0

5.5

V

Tj(max)maximum junction
temperature

-

-

-

+125

°C

Tamb

operating ambient
temperaturein still air with exposed pin soldered on a 4
layer JEDEC PCB

-25

+25

+85

°C

Tstg

storage temperatureno supply voltage applied, relative humidity
45...75%

-45

+25

+125

°C

Min

Typ

Max

Unit

2.5

5.0

5.5

V

2.5

5.0

5.5

V

all host interfaces except I2C interface

2.5

5.0

5.5

V

all host interfaces incl. I2C interface

3.0

5.0

5.5

V

[1]

VDD(PVDD) must always be the same or lower than VDD.

Table 251. Operating conditions CLRC66303
SymbolParameter

VDD

supply voltage

VDD(TVDD)

TVDD supply voltage

VDD(PVDD)

PVDD supply voltage

Conditions[1]

Tj(max)maximum junction
temperature

-

-

-

+125

°C

Tamb

operating ambient
temperature

HVQFN32 package, in still air with exposed
pin soldered on a 4 layer JEDEC PCB

-40

+25

+105

°C

VFBGA36 package, in still air with exposed
pin soldered on a 4 layer JEDEC PCB

-40

+25

+85

°C

no supply voltage applied, relative humidity
45...75%

-45

+25

+125

°C

Tstg
[1]

storage temperature

VDD(PVDD) must always be the same or lower than VDD.

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12 Thermal characteristics
12.1 Thermal characteristics HVQFN32
Table 252. Thermal characteristics
Symbol Parameter

Conditions

Package

Typ

Unit

Rth(j-a)in still air with exposed pin soldered on a 4
layer JEDEC PCB

HVQFN32 40

K/W

thermal resistance from junction toambient

12.2 Thermal characteristics VFBGA36
Table 253. Thermal characteristics
Symbol Parameter

Conditions

Package

Typ

Unit

Rth(j-a)in still air with exposed pin soldered on a 4
layer JEDEC PCBVFBGA36

65

K/W

thermal resistance from junction toambient

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13 Characteristics
Table 254. Characteristics
SymbolParameter

Conditions

Min

Typ

Max

Unit

IDD = AVDD+DVDD; modemon (transmitter andreceiver are switched on)

-

17

20

mA

IDD = AVDD+DVDD; modem
off (transmitter andreceiver are switched off)

-

0.45

0.5

mA

Current consumption
IDD

supply current

IDD(PVDD)

PVDD supply current

no load on digital pins,
leakage current only

-

0.5

5

μA

IDD(TVDD)

TVDD supply current

CLRC66301HN,
CLRC66302HN

-

100

250

mA

CLRC66303HN

-

250

350

mA

ambient temp = +25 °C

-

40

400

nA

ambient temp = -40°C...
+85°C

-

1.5

2.1

μA

CLRC66303: ambient temp
= +105 °C

-

3.5

5.2

μA

ambient temp = 25 °C,
IVDD+ITVDD+ IPVDD

-

3

6

μA

ambient temp = -40°C...
+105°C, Istby = IVDD+ITVDD+
IPVDD

-

5.25

26

-

3.3

6.3

μA

LPCD_TX_HIGH = 0,

-

12

-

μA

LPCD_TX_HIGH = 1

-

23

-

LPCD_TX_HIGH = 0;
TVDD=5.0 V
T=25°C;

-

10

-

μs

LPCD_TX_HIGH = 1;
TVDD=5.0 V; T=25°C

-

50

-

μs

Ipd

Istby

power-down current

standby current

ILPCD(sleep) LPCD sleep current

All OUTx pins floating

All OUTx pins floating

All OUTx pins floating
LFO active, no RF field on,
ambient temp = 25 °C

ILPCD(average)LPCD average current

tRFON

RF-on time during LPCD

[1]All OUTx pins floating,
TxLoad = 50 ohms.
LPCD_FILTER = 0; Rfon
duration = 10 us, RF-off
duration 300ms; VTVDD =3.0V; Tamb = 25°C; ILPCD =IVDD+ITVDD+ IPVDD

Buffer capacitors on AVDD,DVDD
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Table 254. Characteristics...continued
SymbolParameter

Conditions

Min

Typ

Max

Unit

CL

external buffer capacitor

AVDD

220

470

-

nF

CL

external buffer capacitor

DVDD

220

470

-

nF

0.0

50

500

nA

0.3 x VDD(PVDD)V

I/O pin characteristics SIGIN/OUT7, SIGOUT, CLKOUT/OUT6,IFSEL0/OUT4, IFSEL1/OUT5, TCK/OUT3, TMS/OUT2, TDI/
OUT1, TDO/OUT0, IRQ, IF0, IF1, IF2, SCL2, SDA2
ILI

input leakage current

output disabled

VIL

low-level input voltage

-0.5

-

VIH

high-level input voltage

0.7 x
VDD(PVDD)

VDD(PVDD)VDD(PVDD) + 0.5 VVOL

low-level output voltage

0.0

0.0

VOH

high-level output voltage

Ciinput capacitanceIf pins are used as output
OUTx, IOH = 4 mA driving
current for each pin

0.4

V

VDD(PVDD)-0.4 VDD(PVDD)VDD(PVDD)

V

0.0

2.5

4.5

pF

Pin characteristics PDOWN
VIL

low-level input voltage

0.0

0.0

0.4

V

VIH

high-level input voltage

0.6 x VPVDD

VDD(PVDD)VDD(PVDD)

V

50

72

120

KΩ

Pull-up resistance for TCK, TMS, TDI, IF2
Rpu

pull-up resistancePin characteristics AUX 1, AUX 2
Vo

output voltage

0.0

-

1.8

V

CL

load capacitance

0.0

-

400

pF

Pin characteristics RXP, RXN
Vi(p)input voltage

0

1.65

1.8

V

Ci

input capacitance

2

3.5

5

pF

Vmod(pp)modulation voltage

-

2.5

-

mV

Vss(TVSS)-VDD(TVDD)V

CLRC66301, CLRC66302:
T=25°C, VDD(TVDD) = 5.0V

-

1.5

-

Ω

CLRC66303: T=25°C,
VDD(TVDD) = 5.0V

-

1.2

-

Ω

configured to 27.12 MHz

-

27.12

-

MHz

-

50

-

%

-

1.0

-

V

Vmod(pp) = Vi(pp)(max) - Vi(pp)(min)

Pins TX1 and TX2
Vo

output voltage

Rooutput resistance

Clock frequency Pin CLKOUT
fclk

clock frequency

δclkclock duty cycle

Crystal connection XTAL1, XTAL2
Vo(p-p)peak-to-peak output
voltage

CLRC663

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pin XTAL1

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Table 254. Characteristics...continued
SymbolParameter

Conditions

Min

Typ

Max

Unit

Vi

input voltage

pin XTAL1

0.0

-

1.8

V

Ci

input capacitancepin XTAL1

-

3

-

pF

ISO/IEC14443 compliancy

27.12-14kHz

27.12

27.12+14kHz

MHz

Crystal requirements
fxtal

crystal frequency

ESR

equivalent series
resistance

-

50

100

Ω

CL

load capacitance

-

10

-

pF

Pxtal

crystal power dissipation

-

50

100

μW

-

2

100

nA

-

+0.3 VDD(PVDD)

V

2Input characteristics I/O Pin Characteristics IF3-SDA in I C configuration
ILI

input leakage current

VIL

LOW-level input voltage

-0.5

VIH

HIGH-level input voltage

0.7 VDD(PVDD) -VDD(PVDD) + 0.5 V

VOL

LOW-level output voltage IOL = 3 mA

-

-

0.3

V

IOL

LOW-level output current

VOL = 0.4 V; Standard
mode, Fast mode

4

-

-

mA

VOL = 0.6 V; Standard
mode, Fast mode

6

-

-

mA

Standard mode, Fastmode, CL < 400 pF

-

-

250

ns

Fast mode +; CL < 550 pF

-

-

120

ns

tf(o)

output fall time

output disabledtSP

pulse width of spikes thatmust be suppressed by
the input filter

0

-

50

ns

Ci

input capacitance

-

3.5

5

pF

CL

load capacitanceStandard mode

-

-

400

pF

Fast mode

-

-

550

pF

-

-

year

-

-

cycle

tEER

EEPROM data retention
time

Tamb = +55 °C

10

NEEC

EEPROM endurance(number of programming
cycles)under all operating
conditions

5 x 10[1]

5

Ipd is the total current for all supplies.

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Vmod

Vi(p-p)(max)VMID

Vi(p-p)(min)13.56 MHz
carrier

0V

001aak012

Figure 34. Pin RX input voltage

13.1 Timing characteristics
Table 255. SPI timing characteristics
SymbolParametertSCKL

Conditions

Min

Typ

Max Unit

SCK LOW time

50

-

-

ns

tSCKH

SCK HIGH time

50

-

-

ns

th(SCKH-D)

SCK HIGH to data input hold SCK to changing MOSI
time

25

-

-

ns

tsu(D-SCKH)

data input to SCK HIGH setup timechanging MOSI to SCK

25

-

-

ns

th(SCKL-Q)

SCK LOW to data output
hold time

SCK to changing MISO

-

-

25

ns

t(SCKL-NSSH)SCK LOW to NSS HIGH time

0

-

-

ns

tNSSH

NSS HIGH time

50

-

-

ns

before communication

Remark: To send more bytes in one data stream, the NSS signal must be LOW during
the send process. To send more than one data stream, the NSS signal must be HIGH
between each data stream.
2

Table 256. I C-bus timing in fast mode and fast mode plus
SymbolParameter

Conditions

Fast mode

Fast mode
Plus

Unit

Min

Max

Min

Max

0

400

0

1000

kHz

after this period, the first 600
clock pulse is generated

-

260

-

ns

fSCL

SCL clock frequency

tHD;STA

hold time (repeated) START conditiontSU;STA

set-up time for a repeated START
condition

600

-

260

-

ns

tSU;STO

set-up time for STOP condition

600

-

260

-

ns

tLOW

LOW period of the SCL clock

1300

-

500

-

ns

tHIGH

HIGH period of the SCL clock

600

-

260

-

ns

tHD;DATdata hold time

0

900

-

450

ns

tSU;DATdata set-up time

100

-

-

-

ns

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2

Table 256. I C-bus timing in fast mode and fast mode plus...continued
SymbolParameter

Conditions

Fast mode

Fast mode
Plus

Min

Max

Min

Max

Unit

tr

rise time

SCL signal

20

300

-

120

ns

tf

fall time

SCL signal

20

300

-

120

ns

tr

rise time

SDA and SCL signals

20

300

-

120

ns

tf

fall time

SDA and SCL signals

20

300

-

120

ns

tBUF

bus free time between a STOP and
START condition

1.3

-

0.5

-

μs

SDA
tf

tSU;DAT
tLOW

tSP

tf

tr

tHD;STA

tBUF

SCL
tr
tHD;STAStHIGHtHD;DATtSU;STOtSU;STA
Sr

P

S
001aaj635

2

Figure 35. Timing for fast and standard mode devices on the I C-bus

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14 Application information
A typical application diagram using a complementary antenna connection to the
CLRC663 is shown in the following figure.
The antenna tuning and RF part matching is described in the application note [1] and [2].
VDD

PVDD
TVDD
25
18

8
AVDD

9

13
14

PDOWN
MICROPROCESSOR

host
interface

IRQ

DVDD

21
28-31

17

READER IC

16

32

15

CRXN

RXN
VMID

R1 C
vmid

TX1

R2
C1

L0

TVSS
TX2

Ra

C0

C2

C0

C2
Ra

antenna
Lant

L0

C1

14

7

12
33
VSS

19

RXP

20

XTAL1

XTAL2

R3

R4

CRXP

27.12 MHz

001aam269

Figure 36. Typical application antenna circuit diagram

14.1 Antenna design description
The matching circuit for the antenna consists of an EMC low pass filter (L0 and C0), a
matching circuitry (C1 and C2), and a receiving circuits (R1 = R3, R2 = R4, C3 = C5
and C4 = C6;), and the antenna itself. The receiving circuit component values need to
be designed for operation with the CLRC663. A re-use of dedicated antenna designs
done for other products without adaptation of component values will result in degraded
performance.

14.1.1 EMC low pass filter
The MIFARE product-based system operates at a frequency of 13.56 MHz. Thisfrequency is derived from a quartz oscillator to clock the CLRC663 and is also thebasis for driving the antenna with the 13.56 MHz energy carrier. This will not only
cause emitted power at 13.56 MHz but will also emit power at higher harmonics. Theinternational EMC regulations define the amplitude of the emitted power in a broadfrequency range. Thus, an appropriate filtering of the output signal is necessary to fulfill
these regulations.
Remark: The PCB layout has a major influence on the overall performance of the filter.

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14.1.2 Antenna matching
Due to the impedance transformation of the given low pass filter, the antenna coil has tobe matched to a certain impedance. The matching elements C1 and C2 can be estimatedand have to be fine-tuned depending on the design of the antenna coil.
The correct impedance matching is important to provide the optimum performance.
The overall quality factor has to be considered to guarantee a proper ISO/IEC 14443
communication scheme. Environmental influences have to be considered as well as
common EMC design rules.
For details, refer to the NXP application notes.

14.1.3 Receiving circuit
The internal receiving concept of the CLRC663 makes use both side-bands of thesubcarrier load modulation of the card response via a differential receiving concept (RXP,
RXN). No external filtering is required.
It is recommended using the internally generated VMID potential as the input potentialof pin RX. This DC voltage level of VMID has to be coupled to the Rx-pins via R2 andR4. To provide a stable DC reference voltage capacitances C4, C6 has to be connected
between VMID and ground. Refer to Figure 36.
Considering the (AC) voltage limits at the Rx-pins the AC voltage divider of R1 + C3 andR2 as well as R3 + C5 and R4 has to be designed. Depending on the antenna coil design
and the impedance matching, the voltage at the antenna coil varies from antenna design
to antenna design. Therefore the recommended way to design the receiving circuit is to
use the given values for R1(= R3), R2 (= R4), and C3 (= C5) from the above mentioned
application note, and adjust the voltage at the RX-pins by varying R1(= R3) within thegiven limits.
Remark: R2 and R4 are AC-wise connected to ground (via C4 and C6).

14.1.4 Antenna coil
The precise calculation of the antenna coils’ inductance is not practicable but theinductance can be estimated using the following formula. We recommend designing anantenna either with a circular or rectangular shape.

(4)• I1 - Length in cm of one turn of the conductor loop
• D1 - Diameter of the wire or width of the PCB conductor respectively• K - Antenna shape factor (K = 1.07 for circular antennas and K = 1.47 for squareantennas)• L1 - Inductance in nH• N1 - Number of turns• Ln: Natural logarithm function
The actual values of the antenna inductance, resistance, and capacitance at 13.56
MHz depend on various parameters such as:
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• antenna construction (Type of PCB)
• thickness of conductor• distance between the windings• shielding layer• metal or ferrite in the near environment
Therefore a measurement of those parameters under real life conditions, or at least arough measurement and a tuning procedure are highly recommended to guarantee areasonable performance. For details, refer to the above mentioned application notes.

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15 Package outline
15.1 Package outline HVQFN32
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm

B

D

SOT617-1

A

terminal 1
index area

A
E

A1

c
detail X

C

e1
e

1/2 e

16

L

y

y1 C

v M C A B
w M C

b

9

17

8

e

e2

Eh
1/2 e

1
terminal 1
index area

24
32

25

Dh

X

0

2.5
scale

DIMENSIONS (mm are the original dimensions)
UNIT
mm

A(1)
max.

A1

b

1

0.05
0.00

0.30
0.18

5 mm

c

D (1)

Dh

E (1)

Eh

0.2

5.1
4.9

3.25
2.95

5.1
4.9

3.25
2.95

e

e1

0.5

3.5

e2

L

v

w

y

y1

3.5

0.5
0.3

0.1

0.05

0.05

0.1

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCESOUTLINE
VERSION

IEC

JEDEC

JEITA

SOT617-1---

MO-220---

CLRC663

information provided in this document is subject to legal disclaimers.
Figure 37. Package outline SOT-617-1 All(HVQFN32)

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PROJECTION

ISSUE DATE
01-08-08
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15.2 Package outline and PCB design information VFBGA36

Figure 38. VFBGA36 Package outline

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Figure 39. VFBGA36 Package outline notes

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Figure 40. VFBGA36 PCB design: Solder mask opening pattern

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Figure 41. VFBGA36 PCB design: I/O pads and solderable area

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Figure 42. VFBGA36 PCB design: Solder paste stencil

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16 Marking
16.1 Marking HVQFN32
Table 257. Marking code
Type number

Marking code

CLRC66303HN
Line A

66303

Line B

Diffusion Batch ID, " ", Assembly sequence ID

Line C

contains information about diffusion center(“Z” = SSMC), assembly center (“S” = ATKH),
RHF classification (“D” = dark green), datecode (“718” = YWW) and maturity level(“X” = engineering samples, “Y” = customer
qualification samples, “1“ = released product)

A:5
B:5
C:7

0

5
aaa-035755

Figure 43. HVQFN32 Package marking

16.2 Marking VFBGA36
Table 258. Marking code: VFBGA36
Type number

Marking code

CLRC663A0EV

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Line A

6633

Line B

Diffusion Batch ID, Assembly sequence ID

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A:4
B:5
C:5

0

5
aaa-035760

Figure 44. VFBGA36 Package marking

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17 Handling information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.

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18 Packing information
Moisture Sensitivity Level (MSL) evaluation has been performed according to SNWFQ-225B rev.04/07/07 (JEDEC J-STD-020C).
An MSL corresponds to a certain out-of-bag time (or floor life). If semiconductor
packages are removed from their sealed dry-bags and not soldered within their out-ofbag time, they must be baked prior to reflow soldering, in order to remove any moisturethat might have soaked into the package.
For MSL3:
168h out-of-pack floor life at maximum ambient temperature, conditions < 30°C / 60 %RH.
For MSL2:• 1 year out-of-pack floor life at maximum ambient temperature, conditions < 30°C / 60 %RH.
For MSL1:• No out-of-pack floor live spec. required. Conditions: <30°C / 85 % RH.
The straps around the package ofstacked trays inside the plano-box
have sufficient pre-tension to avoid
loosening of the trays.

strap 46 mm from cornertray

ESD warning preprinted
chamfer

barcode label (permanent)

PIN 1

barcode label (peel-off)chamfer
QA sealPIN 1Hyatt patent preprinted
In the traystack (2 trays)
only ONE tray type* allowed*one supplier and one revision number.

printed plano box

001aaj740

Figure 45. Packing information 1 tray

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strap 46 mm from the corner
PQ-label (permanent)bag

dry-agent
relative humidity indicator

preprinted:
recycling symbol
moisture caution label
ESD warningtray

manufacturer bag info
chamfer

ESD warning preprinted
PQ-label (permanent)

PIN 1
PLCC52dry-pack ID preprinted

chamfer

strap

PIN 1

chamfer

QA sealprinted plano box

PIN 1

aaa-004952

Figure 46. Packing information 5 tray

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BC

BB

BA

BA

BD

BD

BC
0.50

section BC-BC
scale 4:1

BB
A B C

0.50

section BA-BA
scale 4:1

3.00

1.55

2.50

end lock

AJ

AJ

AR

AR

side lock

AN

AK
AL

AL

AK

detail AC
scale 20:1

section BD-BD
scale 4:1

3.32

1.10

(0.30)A B C

vacuum cell

AM

AM

0.35

14.20±0.08+10°/S SQ.

1.20

12.80-5°/S SQ.

0.56(0.64)(14.40+5°/S SQ.)

(1.45)

16.60±0.08+7°/S SQ.
13.85±0.08+12°/S SQ.

section AJ-AJ
scale 2:1

section AL-AL
scale 5:1

section AK-AK
scale 5:1

ANsection AN-AN
scale 4:1

section AM-AM
scale 4:1

section AR-AR
scale 2:1
aaa-004949

Figure 47. Tray details

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ASSY REEL + LABELS
tape(see: HOW TO SECURE)

see: ASSY REEL + LABELS

guard bandØ 330x12/16/24/32 (hub 7'')label side

embossed
ESD logotape(see: HOW TO SECURE)

circular sprocket holes
opposite the label side of reelprinted plano-box

cover tapeembossed
ESD logocarrier tape

Ø 330x16/24/32/44 (hub 4'')
Ø 330x44 (hub 6'')

Ø 180x12/16/24
enlongated

PIN1 has to bein quadrant 1

circular
PIN1

PIN1

SO

PLCC

enlongated

PIN1
1

PIN1
2

3 4
BGA
bare die

QFP

product orientationin carrier tapeunreeling direction(HV)QFN(HV)SON(H)BCC

product orientation ONLY for turned
products with 12nc ending 128
PIN1
SO
PIN1

QFP

HOW TO SECURE LEADER END TO THE GUARD BAND,
HOW TO SECURE GUARD BAND

PIN1
1

2

PIN1
3 4 PIN1
for SOT765
BGA
for SOT505-2 ending 125
bare dieending 125(HV)QFN(HV)SON(H)BCC

tapeslotlabel side

trailer

trailer : lenght of trailer shall be 160 mm min.
and covered with cover tapeleader : lenght of trailer shall be 400 mm min.
and covered with cover tapecircular sprocket hole side
guard band

leaderQA sealtape(with pull tabs on both ends)

preprinted ESD warninglape double-backed
onto itself on both ends

PQ-label(permanent)
dry-pack ID preprinted

guard band

aaa-004950

Figure 48. Packing information Reel
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Notes
This page intentionally left blank

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19 Appendix
19.1 LoadProtocol command register initialization
The RF configuration is loaded with the command Load Protocol. The tables below
show the register configuration as performed by this command for each of the protocols.
Antenna specific configurations are not covered by this register settings.
The CLRC66301 and CLRC66302 is not initialized for any antenna configuration. For thisproduct the antenna configuration needs to be done by firmware.
The CLRC66303 antenna configuration in the user EEPROM is described in the chapter
Section 19.2.
Table 259. ISO/IEC14443-A 106 / MIFARE Classic (Protocol Number 00)

CLRC663

Product data sheet
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Value for register

Value (hex)

TxBitMod

20

RFU

00

TxDataCon

04

TxDataMod

50

TxSymFreq

40

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L

00

TxSym200

TxSym300

TxSym10Len

00

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

50

RxBitMod

02

RxEofSym

00

RxSyncValH

00

RxSyncValL

01

RxSyncMod

00

RxMod

08

RxCorr80

FabCalB2

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Table 260. ISO/IEC14443-A 212/ MIFARE Classic (Protocol Number 01)
Value for register

Value (hex)

TxBitMod

20

RFU

00

TxDataCon

05

TxDataMod

50

TxSymFreq

50

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L

00

TxSym200

TxSym300

TxSym10Len

00

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

50

RxBitMod

22

RxEofSym

00

RxSyncValH

00

RxSyncValL

00

RxSyncMod

00

RxMod

0D

RxCorr80

FabCalB2

Table 261. ISO/IEC14443-A 424/ MIFARE Classic (Protocol Number 02)

CLRC663

Product data sheet
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Value for register

Value (hex)

TxBitMod

20

RFU

00

TxDataCon

06

TxDataMod

50

TxSymFreq

60

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L00
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Table 261. ISO/IEC14443-A 424/ MIFARE Classic (Protocol Number 02)...continued
Value for register

Value (hex)

TxSym200

TxSym300

TxSym10Len

00

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

50

RxBitMod

22

RxEofSym

00

RxSyncValH

00

RxSyncValL

00

RxSyncMod

00

RxMod

0D

RxCorr80

FabCalB2

Table 262. ISO/IEC14443-A 848/ MIFARE Classic (Protocol Number 03)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

20

RFU

00

TxDataCon

07

TxDataMod

50

TxSymFreq

70

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L

00

TxSym200

TxSym300

TxSym10Len

00

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

50

RxBitMod

22

RxEofSym00
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Table 262. ISO/IEC14443-A 848/ MIFARE Classic (Protocol Number 03)...continued
Value for register

Value (hex)

RxSyncValH

00

RxSyncValL

00

RxSyncMod

00

RxMod

0D

RxCorr80

FabCalB2

Table 263. ISO/IEC14443-B 106 Classic (Protocol Number 04)
Value for register

Value (hex)

TxBitMod

09

RFU

00

TxDataCon

04

TxDataMod

08

TxSymFreq

04

TxSym0H

00

TxSym0L

03

TxSym1H

00

TxSym1L

01

TxSym200

TxSym300

TxSym10Len

AB

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

08

TxSym32Mod

00

RxBitMod

04

RxEofSym

00

RxSyncValH

00

RxSyncValL

00

RxSyncMod

02

RxMod

CLRC66301, CLRC66302: 1D
CLRC663003: 0D

CLRC663

Product data sheet
COMPANY PUBLIC

RxCorr80

FabCalB2

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 264. ISO/IEC14443-B 212 Classic (Protocol Number 05)
Value for register

Value (hex)

TxBitMod

09

RFU

00

TxDataCon

05

TxDataMod

08

TxSymFreq

05

TxSym0H

00

TxSym0L

03

TxSym1H

00

TxSym1L

01

TxSym200

TxSym300

TxSym10Len

AB

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

08

TxSym32Mod

00

RxBitMod

04

RxEofSym

00

RxSyncValH

00

RxSyncValL

00

RxSyncMod

02

RxMod

CLRC66301, CLRC66302: 1D
CLRC66303: 0D

RxCorr80

FabCalB2

Table 265. ISO/IEC14443-B 424, (Protocol Number 06)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

09

RFU

00

TxDataCon

06

TxDataMod

08

TxSymFreq

06

TxSym0H

00

TxSym0L

03

TxSym1H00
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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 265. ISO/IEC14443-B 424, (Protocol Number 06)...continued
Value for register

Value (hex)

TxSym1L

01

TxSym200

TxSym300

TxSym10Len

AB

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

08

TxSym32Mod

00

RxBitMod

04

RxEofSym

00

RxSyncValH

00

RxSyncValL

00

RxSyncMod

02

RxMod

CLRC66301, CLRC66302: 1D
CLRC66303: 0D

RxCorr80

FabCalB2

Table 266. ISO/IEC14443-B 848, (Protocol Number 07)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

09

RFU

00

TxDataCon

07

TxDataMod

08

TxSymFreq

07

TxSym0H

00

TxSym0L

03

TxSym1H

00

TxSym1L

01

TxSym200

TxSym300

TxSym10Len

AB

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

08

TxSym32Mod00
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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 266. ISO/IEC14443-B 848, (Protocol Number 07)...continued
Value for register

Value (hex)

RxBitMod

04

RxEofSym

00

RxSyncValH

00

RxSyncValL

00

RxSyncMod

02

RxMod

CLRC66301, CLRC66302: 1D
CLRC66303: 0D

RxCorr80

FabCalB2

Table 267. JIS X 6319-4 (FeliCa) 212, (Protocol Number 08)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

80

RFU

00

TxDataCon

05

TxDataMod

01

TxSymFreq

05

TxSym0H

B2

TxSym0L

4D

TxSym1H

00

TxSym1L

00

TxSym200

TxSym300

TxSym10Len

0F

TxSym32Len

00

TxSym10BurstCtrl

01

TxSym10Mod

01

TxSym32Mod

00

RxBitMod18

RxEofSym

00

RxSyncValH

B2

RxSyncValL

4D

RxSyncMod

F0

RxMod

19

RxCorr20

FabCalB0
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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 268. JIS X 6319-4 (FeliCa) 424, (Protocol Number 09)
Value for register

Value (hex)

TxBitMod

80

RFU

00

TxDataCon

06

TxDataMod

01

TxSymFreq

06

TxSym0H

B2

TxSym0L

4D

TxSym1H

00

TxSym1L

00

TxSym200

TxSym300

TxSym10Len

0F

TxSym32Len

00

TxSym10BurstCtrl

01

TxSym10Mod

01

TxSym32Mod

00

RxBitMod18

RxEofSym

00

RxSyncValH

B2

RxSyncValL

4D

RxSyncMod

F0

RxMod

19

RxCorr50

FabCalB0

Table 269. ISO/IEC15693 SLI 1/4 - SSC- 26, (Protocol Number 10)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

00

RFU

00

TxDataCon

83

TxDataMod

04

TxSymFreq

40

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L00
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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 269. ISO/IEC15693 SLI 1/4 - SSC- 26, (Protocol Number 10)...continued
Value for register

Value (hex)

TxSym2

84

TxSym3

02

TxSym10Len

00

TxSym32Len

37

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod00

RxEofSym

1D

RxSyncValH

00

RxSyncValL

01

RxSyncMod

00

RxMod

24

RxCorr60

FabCalF0

Table 270. ISO/IEC15693 SLI 1/4 - SSC- 53, (Protocol Number 11)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

00

RFU

00

TxDataCon

83

TxDataMod

04

TxSymFreq

40

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L

00

TxSym2

84

TxSym3

02

TxSym10Len

00

TxSym32Len

37

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod00

RxEofSym

1D
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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 270. ISO/IEC15693 SLI 1/4 - SSC- 53, (Protocol Number 11)...continued
Value for register

Value (hex)

RxSyncValH

00

RxSyncValL

01

RxSyncMod

00

RxMod

24

RxCorr40

FabCalF0

Table 271. SO/IEC15693 SLI 1/256 - DSC, (Protocol Number 12)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

00

RFU

00

TxDataCon

83

TxDataMod

04

TxSymFreq

40

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L

00

TxSym2

81

TxSym3

02

TxSym10Len

00

TxSym32Len

37

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod00

RxEofSym

1D

RxSyncValH

00

RxSyncValL

01

RxSyncMod

00

RxMod

26

RxCorr60

FabCalF0

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CLRC663

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Table 272. EPC/UID - SSC -26, (Protocol Number 13)
Value for register

Value (hex)

TxBitMod

80

RFU

00

TxDataCon

44

TxDataMod00

TxSymFreq

44

TxSym0H

08

TxSym0L

22

TxSym1H

08

TxSym1L

28

TxSym2

8A

TxSym3

02

TxSym10Len

BB

TxSym32Len

37

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod08

RxEofSym

0B

RxSyncValH

00

RxSyncValL

00

RxSyncMod

08

RxMod

04

RxCorr50

FabCalF0

Table 273. EPC-V2 - 2/424 (Protocol Number 14)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

80

RFU

00

TxDataCon

C5

TxDataMod00

TxSymFreq

05

TxSym0H

68

TxSym0L

41

TxSym1H

01

TxSym1LA1
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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 273. EPC-V2 - 2/424 (Protocol Number 14)...continued
Value for register

Value (hex)

TxSym200

TxSym300

TxSym10Len

8E

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod08

RxEofSym

0B

RxSyncValH

00

RxSyncValL

01

RxSyncMod

04

RxMod

0C

RxCorr40

FabCalF0

Table 274. EPC-V2 - 4/424, (Protocol Number 15)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

80

RFU

00

TxDataCon

C5

TxDataMod00

TxSymFreq

05

TxSym0H

68

TxSym0L

41

TxSym1H

01

TxSym1LA1

TxSym200

TxSym300

TxSym10Len

8E

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod08

RxEofSym

0B
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CLRC663

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Table 274. EPC-V2 - 4/424, (Protocol Number 15)...continued
Value for register

Value (hex)

RxSyncValH

00

RxSyncValL

01

RxSyncMod

04

RxMod

0C

RxCorr50

FabCalF0

Table 275. EPC-V2 - 2/848, (Protocol Number 16)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

80

RFU

00

TxDataCon

C5

TxDataMod00

TxSymFreq

05

TxSym0H

68

TxSym0L

41

TxSym1H

01

TxSym1LA1

TxSym200

TxSym300

TxSym10Len

8E

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod08

RxEofSym

0B

RxSyncValH

00

RxSyncValL

01

RxSyncMod

04

RxMod

0C

RxCorr88

FabCalF0

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 276. EPC-V2 - 4/848, (Protocol Number 17)
Value for register

Value (hex)

TxBitMod

80

RFU

00

TxDataCon

C5

TxDataMod00

TxSymFreq

05

TxSym0H

68

TxSym0L

41

TxSym1H

01

TxSym1LA1

TxSym200

TxSym300

TxSym10Len

8E

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

00

RxBitMod08

RxEofSym

0B

RxSyncValH

00

RxSyncValL

01

RxSyncMod

04

RxMod

0C

RxCorr80

FabCalF0

Table 277. Jewel, (Protocol Number 18)

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

Value (hex)

TxBitMod

00

RFU

00

TxDataCon

04

TxDataMod

D0

TxSymFreq

40

TxSym0H

00

TxSym0L

00

TxSym1H

00

TxSym1L00
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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 277. Jewel, (Protocol Number 18)...continued
Value for register

Value (hex)

TxSym200

TxSym300

TxSym10Len

00

TxSym32Len

00

TxSym10BurstCtrl

00

TxSym10Mod

00

TxSym32Mod

50

RxBitMod

02

RxEofSym

00

RxSyncValH

00

RxSyncValL

01

RxSyncMod

00

RxMod

08

RxCorr80

FabCalF0

19.2 CLRC66303 EEPROM configuration
The CLRC66303 user EEPROM had been initalized with useful values for configurationof the chip using a typical 65x65mm antenna. These values stored in EEPROM can beused to configure the CLRC66303 with the command LoadReg.Typically, some of thisentries will be required to be modified compared to the preset values to achieve the best
RF performance for a specific antenna.
The registers 0x28...0x39 are relevant for configuration of the Antenna. For eachsupported protocol, a dedicated preset configuration is available. To ensure compatibility
between products of the CLRC663 family, all products of the family use the samedefault settings which are initialized in EEPROM, even if some of this protocols are notsupported by the product family member and cannot be used.
Alternatively, the registers can be initialized by individual register write commands.
Table 278. ISO/IEC14443-A 106 / MIFARE Classic

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

DrvMode

C0

8E

TxAmp

C1

12

DrvCon

C2

39

TxI

C3

0A

TXCrcPreset

C4

18

RXCrcPreset

C5

18

TxDataNum

C60F

TxModWidth

C721

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CLRC663

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Table 278. ISO/IEC14443-A 106 / MIFARE Classic...continued
Value for register

EEPROM address (hex)Value (hex)

TxSym10BurstLen

C800

TxWaitCtrl

C9

C0

TxWaitLoCA

12

TxFrameCon

CB

CF

RxSofD

CC

00

RxCtrlCD

04

RxWaitCE

90

RxThreshold

CF

5C

Rcv

D0

12

RxAna

D1

0A

Table 279. ISO/IEC14443-A 212/ MIFARE Classic
Value for register

EEPROM address (hex)Value (hex)

DrvMode

D4

8E

TxAmp

D5

D2

DrvCon

D6

11

TxI

D7

0A

TXCrcPreset

D818

RXCrcPreset

D918

TxDataNum

DA

0F

TxModWidth

DB

10

TxSym10BurstLen

DC

00

TxWaitCtrl

DD

C0

TxWaitLo

DE

12

TxFrameCon

DF

CF

RxSofD

E000

RxCtrlE1

05

RxWaitE2

90

RxThreshold

E3

3C

Rcv

E4

12

RxAna

E5

0B

Table 280. ISO/IEC14443-A 424/ MIFARE Classic

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

DrvModeE88F

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CLRC663

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Table 280. ISO/IEC14443-A 424/ MIFARE Classic...continued
Value for register

EEPROM address (hex)Value (hex)

TxAmp

E9

DE

DrvCon

EA

11

TxI

EB

0F

TXCrcPreset

EC

18

RXCrcPreset

ED

18

TxDataNum

EE

0F

TxModWidthEF

07

TxSym10BurstLen

F000

TxWaitCtrl

F1

C0

TxWaitLo

F2

12

TxFrameCon

F3

CF

RxSofD

F400

RxCtrlF506

RxWaitF6

90

RxThreshold

F7

2B

Rcv

F8

12

RxAna

F9

0B

Table 281. ISO/IEC14443-A 848/ MIFARE Classic

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0100

8F

TxAmp

0101

DB

DrvCon

0102

21

TxI

0103

0F

TXCrcPreset

0104

18

RXCrcPreset

0105

18

TxDataNum

0106

0F

TxModWidth

0107

02

TxSym10BurstLen

0108

00

TxWaitCtrl

0109

C0

TxWaitLo

010A

12

TxFrameCon

010B

CF

RxSofD

010C

00

RxCtrl010D

07

RxWait010E

90

RxThreshold

010F

3A

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CLRC663

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Table 281. ISO/IEC14443-A 848/ MIFARE Classic...continued
Value for register

EEPROM address (hex)Value (hex)

Rcv

0110

12

RxAna

0111

0B

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0114

8F

TxAmp

0115

0E

DrvCon

0116

09

TxI

0117

0A

TXCrcPreset

0118

7B

RXCrcPreset

0119

7B

TxDataNum

011A

08

TxModWidth

011B

00

TxSym10BurstLen

011C

00

TxWaitCtrl

011D

01

TxWaitLo

011E

00

TxFrameCon

011F

05

RxSofD

0120

00

RxCtrl0121

34

RxWait0122

90

RxThreshold

0123

6F

Rcv

0124

12

RxAna

0125

03

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0128

8F

TxAmp

0129

0E

DrvCon

012A

09

TxI

012B

0A

TXCrcPreset

012C

7B

RXCrcPreset

012D

7B

TxDataNum

012E

08

TxModWidth

012F

00

TxSym10BurstLen

0130

00

Table 282. ISO/IEC14443-B 106

Table 283. ISO/IEC14443-B 212

CLRC663

Product data sheet
COMPANY PUBLIC

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CLRC663

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Table 283. ISO/IEC14443-B 212...continued
Value for register

EEPROM address (hex)Value (hex)

TxWaitCtrl

0131

01

TxWaitLo

0132

00

TxFrameCon

0133

05

RxSofD

0134

00

RxCtrl0135

35

RxWait0136

90

RxThreshold

0137

3F

Rcv

0138

12

RxAna

0139

03

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0140

8F

TxAmp

0141

0F

DrvCon

0142

09

TxI

0143

0A

TXCrcPreset

0144

7B

RXCrcPreset

0145

7B

TxDataNum

0146

08

TxModWidth

0147

00

TxSym10BurstLen

0148

00

TxWaitCtrl

0149

01

TxWaitLo

014A

00

TxFrameCon

014B

05

RxSofD

014C

00

RxCtrl014D

36

RxWait014E

90

RxThreshold

014F

3F

Rcv

0150

12

RxAna

0151

03

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0154

8F

TxAmp

0155

10

Table 284. ISO/IEC14443-B 424

Table 285. ISO/IEC14443-B 848

CLRC663

Product data sheet
COMPANY PUBLIC

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CLRC663

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Table 285. ISO/IEC14443-B 848...continued
Value for register

EEPROM address (hex)Value (hex)

DrvCon

0156

09

TxI

0157

0A

TXCrcPreset

0158

7B

RXCrcPreset

0159

7B

TxDataNum

015A

08

TxModWidth

015B

00

TxSym10BurstLen

015C

00

TxWaitCtrl

015D

01

TxWaitLo

015E

00

TxFrameCon

015F

05

RxSofD

0160

00

RxCtrl0161

37

RxWait0162

90

RxThreshold

0163

3F

Rcv

0164

12

RxAna

0165

03

Table 286. JIS X 6319-4 (FeliCa) 212

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0168

8F

TxAmp

0169

17

DrvCon

016A

01

TxI

016B

06

TXCrcPreset

016C

09

RXCrcPreset

016D

09

TxDataNum

016E

08

TxModWidth

016F

00

TxSym10BurstLen

0170

03

TxWaitCtrl

0171

80

TxWaitLo

0172

12

TxFrameCon

0173

01

RxSofD

0174

00

RxCtrl0175

05

RxWait0176

86

RxThreshold

0177

3F

Rcv

0178

12

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 286. JIS X 6319-4 (FeliCa) 212...continued
Value for register

EEPROM address (hex)Value (hex)

RxAna

0179

02

Table 287. JIS X 6319-4 (FeliCa) 424
Value for register

EEPROM address (hex)Value (hex)

DrvMode

0180

8F

TxAmp

0181

17

DrvCon

0182

01

TxI

0183

06

TXCrcPreset

0184

09

RXCrcPreset

0185

09

TxDataNum

0186

08

TxModWidth

0187

00

TxSym10BurstLen

0188

03

TxWaitCtrl

0189

80

TxWaitLo

018A

12

TxFrameCon

018B

01

RxSofD

018C

00

RxCtrl018D

06

RxWait

018E

86

RxThreshold

018F

3F

Rcv

0190

12

RxAna

0191

02

Table 288. ISO/IEC15693 SLI 1/4 - SSC- 26

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0194

89

TxAmp

0195

10

DrvCon

0196

09

TxI

0197

0A

TXCrcPreset

0198

7B

RXCrcPreset

0199

7B

TxDataNum

019A

08

TxModWidth

019B

00

TxSym10BurstLen

019C

00

TxWaitCtrl

019D

88

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Table 288. ISO/IEC15693 SLI 1/4 - SSC- 26...continued
Value for register

EEPROM address (hex)Value (hex)

TxWaitLo

019E

A9

TxFrameCon

019F

0F

RxSofD

01A0

00

RxCtrl01A1

02

RxWait01A2

9C

RxThreshold

01A3

74

Rcv

01A4

12

RxAna

01A5

07

Table 289. ISO/IEC15693 SLI 1/4 - SSC-53
Value for register

EEPROM address (hex)Value (hex)

DrvMode

01A8

89

TxAmp

01A9

10

DrvCon

01AA

09

TxI

01AB

0A

TXCrcPreset

01AC

7B

RXCrcPreset

01AD

7B

TxDataNum

01AE

08

TxModWidth

016F

00

TxSym10BurstLen

01B0

00

TxWaitCtrl

01B1

88

TxWaitLo

01B2

A9

TxFrameCon

01B3

0F

RxSofD

01B400

RxCtrl01B503

RxWait01B69C

RxThreshold

01B7

74

Rcv

01B8

12

RxAna

01B9

03

Table 290. ISO/IEC15693 SLI 1/256 - DSC

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

DrvMode

01C0

8E

TxAmp

01C1

10

DrvCon01C201

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Table 290. ISO/IEC15693 SLI 1/256 - DSC...continued
Value for register

EEPROM address (hex)Value (hex)

TxI

01C3

06

TXCrcPreset

01C4

7B

RXCrcPreset

01C5

7B

TxDataNum

01C6

08

TxModWidth

01C7

00

TxSym10BurstLen

01C8

00

TxWaitCtrl

01C9

88

TxWaitLo

01CA

A9

TxFrameCon

01CB

0F

RxSofD

01CC

00

RxCtrl

01CD

02

RxWait01CE

10

RxThreshold

01CF

44

Rcv

01D0

12

RxAna

01D1

06

Value for register

EEPROM address (hex)Value (hex)

DrvMode

01D4

8F

TxAmp

01D5

10

DrvCon

01D6

01

TxI

01D7

06

TXCrcPreset

01D8

74

RXCrcPreset

01D9

7B

TxDataNum

01DA

18

TxModWidth

01DB

00

TxSym10BurstLen

01DC

00

TxWaitCtrl

01DD

50

TxWaitLo

01DE

5C

TxFrameCon

01DF

0F

RxSofD

01E0

00

RxCtrl01E1

03

RxWait01E2

10RxThreshold

01E3

4E

Rcv

01E4

12

RxAna

01E5

06

Table 291. EPC/UID - SSC -26

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Product data sheet
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Table 292. EPC-V2 - 2/424
Value for register

EEPROM address (hex)Value (hex)

DrvMode

01E8

8F

TxAmp

01E9

10

DrvCon

01EA

09

TxI

01EB

0A

TXCrcPreset

01EC

11

RXCrcPreset

01ED

91

TxDataNum

01EE

09

TxModWidth

01EF

00

TxSym10BurstLen

01F0

00

TxWaitCtrl

01F1

80

TxWaitLo

01F2

12

TxFrameCon

01F3

01

RxSofD01F400

RxCtrl01F503

RxWait01F6

A0

RxThreshold

01F7

56

Rcv

01F8

12

RxAna

01F9

0F

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0200

8F

TxAmp

0201

10

DrvCon

0202

09

TxI

0203

0A

TXCrcPreset

0204

11

RXCrcPreset

0205

91

TxDataNum

0206

09

TxModWidth

0207

00

TxSym10BurstLen

0208

00

TxWaitCtrl

0209

80

TxWaitLo

020A

12

TxFrameCon

020B

01

RxSofD

020C

00

RxCtrl020D

03

RxWait020E

A0

Table 293. EPC-V2 - 4/424

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Table 293. EPC-V2 - 4/424...continued
Value for register

EEPROM address (hex)Value (hex)

RxThreshold

020F

56

Rcv

0210

12

RxAna

0211

0F

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0214

8F

TxAmp

0215

D0

DrvCon

0216

01

TxI

0217

0A

TXCrcPreset

0218

11

RXCrcPreset

0219

91

TxDataNum

021A

09

TxModWidth

021B

00

TxSym10BurstLen

021C

00

TxWaitCtrl

021D

80

TxWaitLo

021E

12

TxFrameCon

021F

01

RxSofD

0220

00

RxCtrl0221

05

RxWait0222

A0

RxThreshold

0223

26

Rcv

0224

12

RxAna

0225

0E

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0228

8F

TxAmp

0229

D0

DrvCon

022A

01

TxI

022B

0A

TXCrcPreset

022C

11

RXCrcPreset

022D

91

TxDataNum

022E

09

TxModWidth

022F

00

Table 294. EPC-V2 - 2/848

Table 295. EPC-V2 - 4/848

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Product data sheet
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Table 295. EPC-V2 - 4/848...continued
Value for register

EEPROM address (hex)Value (hex)

TxSym10BurstLen

0230

00

TxWaitCtrl

0231

80

TxWaitLo

0232

12

TxFrameCon

0233

01

RxSofD

0234

00

RxCtrl0235

05

RxWait0236

A0

RxThreshold

0237

26

Rcv

0238

12

RxAna

0239

0E

Value for register

EEPROM address (hex)Value (hex)

DrvMode

0240

8E

TxAmp

0241

15

DrvCon

0242

11

TxI

0243

06

TXCrcPreset

0244

18

RXCrcPreset

0245

18

TxDataNum

0246

0F

TxModWidth

0247

20

TxSym10BurstLen

0248

00

TxWaitCtrl

0249

40

TxWaitLo

024A

09

TxFrameCon

024B

4F

RxSofD

024C

00

RxCtrl024D

04

RxWait024E

8F

RxThreshold

024F

32

Rcv

0250

12

RxAna

0251

0A

Table 296. Jewel

Table 297. ISO/IEC14443 - B 106 EMVCo Optimized

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

DrvMode0254

8F

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 297. ISO/IEC14443 - B 106 EMVCo Optimized...continued

CLRC663

Product data sheet
COMPANY PUBLIC

Value for register

EEPROM address (hex)Value (hex)

TxAmp

0255

0E

DrvCon

0256

09

TxI

0257

0A

TXCrcPreset

0258

7B

RXCrcPreset

0259

7B

TxDataNum

025A

08

TxModWidth

025B

00

TxSym10BurstLen

025C

00

TxWaitCtrl

025D

01

TxWaitLo

025E

00

TxFrameCon

025F

05

RxSofD

0260

00

RxCtrl0261

34

RxWait0262

90

RxThreshold

0263

9F

Rcv

0264

12

RxAna

0265

03

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20 Abbreviations
Table 298. Abbreviations

CLRC663

Product data sheet
COMPANY PUBLIC

AcronymDescription

ADC

Analog-to-Digital Converter

BPSK

Binary Phase Shift Keying

CRC

Cyclic Redundancy Check

CW

Continuous Wave

EGT

Extra Guard Time

EMC

Electro Magnetic Compatibility

EMD

Electro Magnetic Disturbance

EOF

End Of Frame

EPC

Electronic Product CodeETU

Elementary Time Unit

GPIO

General Purpose Input/Output

HBM

Human Body Model

I C

2Inter-Integrated Circuit

IRQ

Interrupt Request

LFO

Low Frequency Oscillator

LPCD

Low-Power Card Detection

LSB

Least Significant Bit

MISO

Master In Slave Out

MOSI

Master Out Slave In

MSB

Most Significant Bit

NRZ

Not Return to ZeroNSS

Not Slave Select

PCD

Proximity Coupling Device

PLL

Phase-Locked Loop

RZ

Return To ZeroRX

Receiver

SAM

Secure Access Module

SOF

Start Of Frame

SPI

Serial Peripheral Interface

SW

SoftwareTTimerTiming of the clk period

TX

Transmitter

UART

Universal Asynchronous Receiver Transmitter

UID

Unique Identification

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Table 298. Abbreviations...continued

CLRC663

Product data sheet
COMPANY PUBLIC

AcronymDescription

VCO

Voltage Controlled Oscillator

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21 References[1]
Application note AN11019
CLRC663, MFRC630, MFRC631, SLRC610 Antenna Design Guide[2]
Application note AN11783
CLRC663 plus Low Power Card Detection

CLRC663

Product data sheet
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22 Revision history
Table 299. Revision history
Document ID

Release date

Data sheet status

Change notice

Supersedes

CLRC663 v.5.2

20210702

Product data sheet-

CLRC663 v.5.1

Modifications:• Table 250 "Operating conditions CLRC66301, CLRC66302": operating ambient temperatures
corrected

CLRC663 v.5.1

20210112

Modifications:• Table 3 "Ordering information ": type number CLRC66302HN, 151 added• Table 35 "EEPROM memory organization": corrected Section 4: 112 to 127• Section 8.10.3.10 "WriteE2PAGE command": corrected into Parameter2..65• Table 49 "Behavior of register bits and their designation": description of RFU updated• Table 150 "TxSym10BurstLen bits": updated• Table 180 "Setting for the output divider ratio PLLDiv_Out [7:0]": value 255 added• Table 200 "SigOut bits": description of Bit 3 to 0 updated

CLRC663 v.5.0

20201127

Modifications:• Section 5 "Ordering information": MSL corrected• Table 29 "Boundary scan path of the CLRC663": Cell BC_4 corrected

CLRC663 v.4.9

20200701

Product data sheet-

CLRC663 v.4.8

CLRC663 v.4.8

20191028

Product data sheet-

CLRC663 v.4.7

CLRC663 v.4.7

20180912

Product data sheet-

CLRC663 v.4.6

CLRC663 v.4.6

20180516

Product data sheet-

CLRC663 v.4.5

CLRC663 v.4.5

20171219

Product data sheet-

CLRC663 v.4.4

CLRC663 v.4.4

20170502

Product data sheet-

CLRC663 v.4.3

CLRC663 v.4.3

20170220

Product data sheet-

CLRC663 v.4.2

CLRC663 v.4.2

20160427

Product data sheet-

CLRC663 v.4.1

CLRC663 v.4.1

20160211

Product data sheet-

CLRC663 v.4.0

CLRC663 v.4.0

20151029

Product data sheet-

CLRC663 v.3.9

CLRC663 v.3.9

20150722

Product data sheet-

CLRC663 v.3.8

CLRC663 v.3.7

20140206

Product data sheet-

CLRC663 v.3.7

CLRC663 v.3.7

20140204

Product data sheet-

CLRC663 v.3.6

CLRC663 v.3.6

20130910

Product data sheet-

CLRC663 v.3.5

CLRC663 v.3.5

20120905

Product data sheet-

CLRC663 v.3.4

CLRC663 v.3.4

20120717

Product data sheet-

CLRC663 v.3.3

CLRC663 v.3.3

20120402

Product data sheet-

CLRC663 v.3.2

CLRC663 v.3.2

20120202

Product data sheet-

CLRC663 v.3.1

CLRC663 v.3.1

20110926

Product data sheet-

CLRC663 v.3.0

CLRC663 v.3.0

20110919

Product data sheet-

CLRC663 v.2.0

CLRC663 v.2.0

20110615

Preliminary data sheet-

CLRC663 v.1.0

CLRC663 v.1.0

20110308

Objective data sheet--

CLRC663

Product data sheet
COMPANY PUBLIC

Product data sheet

Product data sheet--

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23 Legal information
23.1 Data sheet status
Document status[1][2]

Product status[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for productdevelopment.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

23.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may resultin modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have noliability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet isintended for quick reference only and should not be relied upon to containdetailed and full information. For detailed and full information see therelevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with theshort data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors productis deemed to offer functions and qualities beyond those described in the
Product data sheet.

23.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does notgive any representations or warranties, expressed or implied, as to theaccuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special orconsequential damages (including - without limitation - lost profits, lostsavings, business interruption, costs related to the removal or replacementof any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any otherlegal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limitedin accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without

CLRC663

Product data sheet
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications andproducts using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, orthe application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid adefault of the applications and the products or of the application or use bycustomer’s third party customer(s). NXP does not accept any liability in thisrespect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.

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No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shalluse the product without NXP Semiconductors’ warranty of the product forsuch automotive applications, use and specifications, and (b) whenevercustomer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and useof the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to otheropen and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and makethe ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may

CLRC663

Product data sheet
COMPANY PUBLIC

be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.

23.4 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC
14443 Type B software enabled and islicensed under Innovatron’s Contactless
Card patents license for ISO/IEC 14443 B.
RATP/InnovatronTechnology

The license includes the right to use the IC
in systems and/or end-user equipment.

Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the
Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right
infringed by implementation of any of those standards. Purchase of NXP
Semiconductors IC does not include a license to any NXP patent (or otherIP right) covering combinations of those products with other products,
whether hardware or software.

23.5 Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.
2

I C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
DESFire — is a trademark of NXP B.V.
ICODE and I-CODE — are trademarks of NXP B.V.
MIFARE Plus — is a trademark of NXP B.V.
MIFARE Ultralight — is a trademark of NXP B.V.
MIFARE Classic — is a trademark of NXP B.V.
NXP — wordmark and logo are trademarks of NXP B.V.
FeliCa — is a trademark of Sony Corporation.

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

TablesTab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Tab. 31.
Tab. 32.
Tab. 33.
Tab. 34.
Tab. 35.
Tab. 36.
Tab. 37.
Tab. 38.
Tab. 39.
Tab. 40.
Tab. 41.
Tab. 42.

Quick reference data CLRC66301 and
CLRC66302 .......................................................5
Quick reference data CLRC66303 .................... 5
Ordering information ..........................................6
Pin description ...................................................8
Pin description VFBGA36 ................................. 9Interrupt sources ............................................. 12
Communication overview for ISO/IEC
14443 type A and read/write mode for
MIFARE Classic .............................................. 15
Communication overview for ISO/IEC
14443 B reader/writer ......................................17
Communication overview for FeliCa reader/
writer ................................................................18
FeliCa framing and coding .............................. 18
Communication overview for ISO/IEC
15693 reader/writer reader to label ................. 18
Communication overview for ISO/IEC
15693 reader/writer label to reader ................. 19
Communication overview for EPC/UID ............19
Communication overview for Passive
communication mode ...................................... 21
Framing and coding overview ......................... 21
Connection scheme for detecting thedifferent interface types ...................................22
Byte Order for MOSI and MISO ...................... 23
Byte Order for MOSI and MISO ...................... 23
Address byte 0 register; address MOSI ...........23
Timing conditions SPI ..................................... 24
Settings of BR_T0 and BR_T1 ........................25
Selectable transfer speeds ..............................25
UART framing ................................................. 25
Byte Order to Read Data ................................ 26
Byte Order to Write Data ................................ 26
Timing parameter I2CL ................................... 31
SPI SAM connection ....................................... 33
Boundary scan command ............................... 33
Boundary scan path of the CLRC663 ..............36
Settings for TX1 and TX2 ............................... 40
Setting residual carrier and modulationindex by TXamp.set_residual_carrier .............. 40
Configuration for single or differential
receiver ............................................................43
Register configuration of CLRC663 active
antenna concept (DIGITAL) .............................44
Register configuration of CLRC663 active
antenna concept (Antenna) ............................. 44
EEPROM memory organization ...................... 47
Production area (Page 0) ................................47
Product ID overview of CLRC663 family ......... 48
Configuration area (Page 0) ............................48
Interface byte .................................................. 48
Interface bits ....................................................49
Tx and Rx arrangements in the register set
protocol area ................................................... 49
Register reset values (Hex.) (Page0) .............. 49

CLRC663

Product data sheet
COMPANY PUBLIC

Tab. 43.
Tab. 44.
Tab. 45.
Tab. 46.
Tab. 47.
Tab. 48.
Tab. 49.
Tab. 50.
Tab. 51.
Tab. 52.
Tab. 53.
Tab. 54.
Tab. 55.
Tab. 56.
Tab. 57.
Tab. 58.
Tab. 59.
Tab. 60.
Tab. 61.
Tab. 62.
Tab. 63.
Tab. 64.
Tab. 65.
Tab. 66.
Tab. 67.
Tab. 68.
Tab. 69.
Tab. 70.
Tab. 71.
Tab. 72.
Tab. 73.
Tab. 74.
Tab. 75.
Tab. 76.
Tab. 77.
Tab. 78.
Tab. 79.
Tab. 80.
Tab. 81.
Tab. 82.
Tab. 83.
Tab. 84.
Tab. 85.
Tab. 86.
Tab. 87.
Tab. 88.
Tab. 89.
Tab. 90.
Tab. 91.
Tab. 92.
Tab. 93.

Register reset values (Hex.)(Page1 andpage 2) ............................................................ 50
Crystal requirements recommendations .......... 51
Divider values for selected frequencies
using the integerN PLL ................................... 52
Command set ..................................................55
Predefined protocol overview RX .................... 59
Predefined protocol overview TX .................... 59
Behavior of register bits and theirdesignation ...................................................... 62
CLRC663 registers overview ...........................62
Command register (address 00h) ....................65
Command bits ................................................. 65
HostCtrl register (address 01h); ...................... 66
HostCtrl bits .....................................................66
FIFOControl register (address 02h); ............... 66
FIFOControl bits .............................................. 66
WaterLevel register (address 03h); ................. 67
WaterLevel bits ................................................67
FIFOLength register (address 04h); reset
value: 00h ........................................................68
FIFOLength bits .............................................. 68
FIFOData register (address 05h); ................... 68
FIFOData bits ..................................................68
IRQ0 register (address 06h); reset value:
00h .................................................................. 69
IRQ0 bits ......................................................... 69
IRQ1 register (address 07h) ............................69
IRQ1 bits ......................................................... 70
IRQ0En register (address 08h) ....................... 70
IRQ0En bits .....................................................70
IRQ1EN register (address 09h); ......................71
IRQ1EN bits .................................................... 71
Error register (address 0Ah) ............................71
Error bits ..........................................................71
Status register (address 0Bh) ......................... 72
Status bits ....................................................... 73
RxBitCtrl register (address 0Ch); .................... 73
RxBitCtrl bits ................................................... 73
RxColl register (address 0Dh); ........................74
RxColl bits ....................................................... 74
TControl register (address 0Eh) ...................... 75
TControl bits ....................................................75
T0Control register (address 0Fh); ................... 75
T0Control bits ..................................................75
T0ReloadHi register (address 10h); ................ 76
T0ReloadHi bits ...............................................76
T0ReloadLo register (address 11h); ................ 76
T0ReloadLo bits .............................................. 77
T0CounterValHi register (address 12h) ........... 77
T0CounterValHi bits ........................................ 77
T0CounterValLo register (address 13h) .......... 77
T0CounterValLo bits ........................................77
T1Control register (address 14h); ................... 77
T1Control bits ..................................................78
T0ReloadHi register (address 15h) ................. 78

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Tab. 94. T1ReloadHi bits ...............................................78
Tab. 95. T1ReloadLo register (address 16h) .................78
Tab. 96. T1ReloadLo bits .............................................. 79
Tab. 97. T1CounterValHi register (address 17h) ........... 79
Tab. 98. T1CounterValHi bits ........................................ 79
Tab. 99. T1CounterValLo register (address 18h) .......... 79
Tab. 100. T1CounterValLo bits ........................................79
Tab. 101. T2Control register (address 19h) .................... 79
Tab. 102. T2Control bits ..................................................80
Tab. 103. T2ReloadHi register (address 1Ah) .................80
Tab. 104. T2ReloadHi bits ...............................................80
Tab. 105. T2ReloadLo register (address 1Bh) ................ 80
Tab. 106. T2ReloadLo bits .............................................. 81
Tab. 107. T2CounterValHi register (address 1Ch) .......... 81
Tab. 108. T2CounterValHi bits ........................................ 81
Tab. 109. T2CounterValLo register (address 1Dh) .......... 81
Tab. 110. T2CounterValLo bits ........................................81
Tab. 111. T3Control register (address 1Eh) .................... 81
Tab. 112. T3Control bits ..................................................82
Tab. 113. T3ReloadHi register (address 1Fh); ................ 82
Tab. 114. T3ReloadHi bits ...............................................82
Tab. 115. T3ReloadLo register (address 20h) .................82
Tab. 116. T3ReloadLo bits .............................................. 83
Tab. 117. T3CounterValHi register (address 21h) ........... 83
Tab. 118. T3CounterValHi bits ........................................ 83
Tab. 119. T3CounterValLo register (address 22h) .......... 83
Tab. 120. T3CounterValLo bits ........................................83
Tab. 121. T4Control register (address 23h) .................... 83
Tab. 122. T4Control bits ..................................................84
Tab. 123. T4ReloadHi register (address 24h) ................. 84
Tab. 124. T4ReloadHi bits ...............................................85
Tab. 125. T4ReloadLo register (address 25h) .................85
Tab. 126. T4ReloadLo bits .............................................. 85
Tab. 127. T4CounterValHi register (address 26h) ........... 85
Tab. 128. T4CounterValHi bits ........................................ 85
Tab. 129. T4CounterValLo register (address 27h) .......... 85
Tab. 130. T4CounterValLo bits ........................................86
Tab. 131. DrvMode register (address 28h) ......................86
Tab. 132. DrvMode bits ................................................... 86
Tab. 133. TxAmp register (address 29h) .........................86
Tab. 134. TxAmp bits ...................................................... 87
Tab. 135. TxCon register (address 2Ah) ......................... 87
Tab. 136. TxCon bits ....................................................... 87
Tab. 137. Txl register (address 2Bh) ...............................87
Tab. 138. Txl bits .............................................................88
Tab. 139. TXCrcPreset register (address 2Ch) ............... 88
Tab. 140. TxCrcPreset bits ..............................................88
Tab. 141. Transmitter CRC preset value configuration ....88
Tab. 142. RxCrcCon register (address 2Dh) ................... 89
Tab. 143. RxCrcCon bits ................................................. 89
Tab. 144. Receiver CRC preset value configuration ....... 89
Tab. 145. TxDataNum register (address 2Eh) .................90
Tab. 146. TxDataNum bits .............................................. 90
Tab. 147. TxDataModWidth register (address 2Fh) ........ 90
Tab. 148. TxDataModWidth bits ...................................... 90
Tab. 149. TxSym10BurstLen register (address 30h) ....... 91
Tab. 150. TxSym10BurstLen bits .................................... 91
Tab. 151. TxWaitCtrl register (address 31h); reset
value: C0h ....................................................... 91
CLRC663

Product data sheet
COMPANY PUBLIC

Tab. 152. TXWaitCtrl bits ................................................ 92
Tab. 153. TxWaitLo register (address 32h) ..................... 92
Tab. 154. TxWaitLo bits ...................................................92
Tab. 155. FrameCon register (address 33h) ................... 92
Tab. 156. FrameCon bits .................................................93
Tab. 157. RxSofD register (address 34h) ........................93
Tab. 158. RxSofD bits ..................................................... 93
Tab. 159. RxCtrl register (address 35h) .......................... 93
Tab. 160. RxCtrl bits ........................................................94
Tab. 161. RxWait register (address 36h) .........................94
Tab. 162. RxWait bits ...................................................... 95
Tab. 163. RxThreshold register (address 37h) ................ 95
Tab. 164. RxThreshold bits ............................................. 95
Tab. 165. Rcv register (address 38h) ..............................95
Tab. 166. Rcv bits ........................................................... 95
Tab. 167. RxAna register (address 39h) ......................... 96
Tab. 168. RxAna bits .......................................................96
Tab. 169. Effect of gain and high-pass corner registersettings ............................................................ 96
Tab. 170. SerialSpeed register (address3Bh); reset
value: 7Ah ....................................................... 97
Tab. 171. SerialSpeed bits .............................................. 97
Tab. 172. RS232 speed settings ..................................... 97
Tab. 173. LFO_Trimm register (address 3Ch) .................98
Tab. 174. LFO_Trimm bits ...............................................98
Tab. 175. PLL_Ctrl register (address3Dh) .......................98
Tab. 176. PLL_Ctrl register bits .......................................99
Tab. 177. Setting of feedback divider PLLDiv_FB[1:0] ................................................................. 99
Tab. 178. PLLDiv_Out register (address 3Eh) ................ 99
Tab. 179. PLLDiv_Out bits .............................................. 99
Tab. 180. Setting for the output divider ratio PLLDiv_
Out [7:0] .......................................................... 99
Tab. 181. LPCD_QMin register (address 3Fh) .............. 100
Tab. 182. LPCD_QMin bits ............................................100
Tab. 183. LPCD_QMax register (address 40h) ............. 101
Tab. 184. LPCD_QMax bits ...........................................101
Tab. 185. LPCD_IMin register (address 41h) ................ 101
Tab. 186. LPCD_IMin bits ............................................. 101
Tab. 187. LPCD_Result_I register (address 42h) ..........101
Tab. 188. LPCD_Result_I bits ....................................... 102
Tab. 189. LPCD_Result_Q register (address 43h) ........ 102
Tab. 190. LPCD_Result_Q bits ..................................... 102
Tab. 191. LPCD_Options register (address 3Ah) .......... 102
Tab. 192. LPCD_Options ...............................................102
Tab. 193. PadEn register (address 44h) ....................... 103
Tab. 194. PadEn bits .....................................................103
Tab. 195. PadOut register (address 45h) ...................... 104
Tab. 196. PadOut bits ................................................... 104
Tab. 197. PadIn register (address 46h) .........................104
Tab. 198. PadIn bits ...................................................... 104
Tab. 199. SigOut register (address 47h) ....................... 105
Tab. 200. SigOut bits .....................................................105
Tab. 201. TxBitMod register (address 48h) ................... 106
Tab. 202. TxBitMod bits ................................................ 106
Tab. 203. TxDataCon (address 4Ah) ............................ 106
Tab. 204. TxDataCon bits ............................................. 107
Tab. 205. TxDataMod register (address 4Bh) ............... 107
Tab. 206. TxDataMod bits ............................................. 108

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Tab. 207. TxSymFreq (address 4Ch) ............................ 108
Tab. 208. TxSymFreq bits ............................................. 108
Tab. 209. TxSym0_H (address 4Dh) .............................109
Tab. 210. TxSym0_H bits .............................................. 109
Tab. 211. TxSym0_L (address 4Eh) ............................. 109
Tab. 212. TxSYM0_L bits .............................................. 110
Tab. 213. TxSym1_H (address 4Fh) ............................. 110
Tab. 214. TxSym1_H bits .............................................. 110
Tab. 215. TxSym1_L (address 50h) .............................. 110
Tab. 216. TxSym1_L bits .............................................. 110
Tab. 217. TxSYM2 (address 51h) ................................. 110
Tab. 218. TxSym2 bits .................................................. 110
Tab. 219. TxSym3 (address 52h) ..................................111
Tab. 220. TxSym3 bits .................................................. 111
Tab. 221. TxSym10Len (address 53h) .......................... 111
Tab. 222. TxSym10Len bits ...........................................111
Tab. 223. TxSym32Len (address 54h) .......................... 111
Tab. 224. TxSym32Len bits ...........................................111
Tab. 225. TxSym10BurstCtrl register (address 55h) ..... 112
Tab. 226. TxSym10BurstCtrl bits ...................................112
Tab. 227. TxSym10Mod register (address 56h) ............ 112
Tab. 228. TxSym10Mod bits ..........................................112
Tab. 229. TxSym32Mod register (address 57h) ............ 113
Tab. 230. TxSym32Mod bits ..........................................113
Tab. 231. RxBitMod (address 58h) ............................... 114
Tab. 232. RxBitMod bits ................................................ 114
Tab. 233. RxEofSym (address 59h) .............................. 115
Tab. 234. RxEOFSym bits .............................................115
Tab. 235. RxSyncValH register (address5Ah) ............... 115
Tab. 236. RxSyncValH bits ............................................115
Tab. 237. RxSyncValL register (address 5Bh) ...............115
Tab. 238. RxSyncValL bits ............................................ 116
Tab. 239. RxSyncMode register (address 5Ch) ............ 116
Tab. 240. RxSyncMod bits ............................................ 116
Tab. 241. RxMod register (address 5Dh) ...................... 116
Tab. 242. RxMod bits .................................................... 116
Tab. 243. RxCorr register (address 5Eh) ...................... 117
Tab. 244. RxCorr bits .................................................... 117
Tab. 245. FabCali register (address 5Fh) ......................117
Tab. 246. FabCali bits ................................................... 117
Tab. 247. Version register (address 7Fh) ...................... 118
Tab. 248. Version bits ....................................................118
Tab. 249. Limiting values .............................................. 119
Tab. 250. Operating conditions CLRC66301,
CLRC66302 ...................................................120
Tab. 251. Operating conditions CLRC66303 .................120
Tab. 252. Thermal characteristics ................................. 121
Tab. 253. Thermal characteristics ................................. 121
Tab. 254. Characteristics ...............................................122
Tab. 255. SPI timing characteristics .............................. 125
Tab. 256. I2C-bus timing in fast mode and fast mode
plus ................................................................ 125
Tab. 257. Marking code .................................................136
Tab. 258. Marking code: VFBGA36 .............................. 136

CLRC663

Product data sheet
COMPANY PUBLIC

Tab. 259. ISO/IEC14443-A 106 / MIFARE Classic(Protocol Number 00) ....................................144
Tab. 260. ISO/IEC14443-A 212/ MIFARE Classic(Protocol Number 01) ....................................145
Tab. 261. ISO/IEC14443-A 424/ MIFARE Classic(Protocol Number 02) ....................................145
Tab. 262. ISO/IEC14443-A 848/ MIFARE Classic(Protocol Number 03) ....................................146
Tab. 263. ISO/IEC14443-B 106 Classic (Protocol
Number 04) ................................................... 147
Tab. 264. ISO/IEC14443-B 212 Classic (Protocol
Number 05) ................................................... 148
Tab. 265. ISO/IEC14443-B 424, (Protocol Number06) ................................................................. 148
Tab. 266. ISO/IEC14443-B 848, (Protocol Number07) ................................................................. 149
Tab. 267. JIS X 6319-4 (FeliCa) 212, (Protocol
Number 08) ................................................... 150
Tab. 268. JIS X 6319-4 (FeliCa) 424, (Protocol
Number 09) ................................................... 151
Tab. 269. ISO/IEC15693 SLI 1/4 - SSC- 26, (Protocol
Number 10) ................................................... 151
Tab. 270. ISO/IEC15693 SLI 1/4 - SSC- 53, (Protocol
Number 11) ................................................... 152
Tab. 271. SO/IEC15693 SLI 1/256 - DSC, (Protocol
Number 12) ................................................... 153
Tab. 272. EPC/UID - SSC -26, (Protocol Number 13) ... 154
Tab. 273. EPC-V2 - 2/424 (Protocol Number 14) .......... 154
Tab. 274. EPC-V2 - 4/424, (Protocol Number 15) ......... 155
Tab. 275. EPC-V2 - 2/848, (Protocol Number 16) ......... 156
Tab. 276. EPC-V2 - 4/848, (Protocol Number 17) ......... 157
Tab. 277. Jewel, (Protocol Number 18) .........................157
Tab. 278. ISO/IEC14443-A 106 / MIFARE Classic ........ 158
Tab. 279. ISO/IEC14443-A 212/ MIFARE Classic ......... 159
Tab. 280. ISO/IEC14443-A 424/ MIFARE Classic ......... 159
Tab. 281. ISO/IEC14443-A 848/ MIFARE Classic ......... 160
Tab. 282. ISO/IEC14443-B 106 .....................................161
Tab. 283. ISO/IEC14443-B 212 .....................................161
Tab. 284. ISO/IEC14443-B 424 .....................................162
Tab. 285. ISO/IEC14443-B 848 .....................................162
Tab. 286. JIS X 6319-4 (FeliCa) 212 ............................ 163
Tab. 287. JIS X 6319-4 (FeliCa) 424 ............................ 164
Tab. 288. ISO/IEC15693 SLI 1/4 - SSC- 26 ..................164
Tab. 289. ISO/IEC15693 SLI 1/4 - SSC-53 ................... 165
Tab. 290. ISO/IEC15693 SLI 1/256 - DSC ....................165
Tab. 291. EPC/UID - SSC -26 ...................................... 166
Tab. 292. EPC-V2 - 2/424 .............................................167
Tab. 293. EPC-V2 - 4/424 .............................................167
Tab. 294. EPC-V2 - 2/848 .............................................168
Tab. 295. EPC-V2 - 4/848 .............................................168
Tab. 296. Jewel ............................................................. 169
Tab. 297. ISO/IEC14443 - B 106 EMVCo Optimized .... 169
Tab. 298. Abbreviations .................................................171
Tab. 299. Revision history ............................................. 174

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CLRC663

NXP Semiconductors

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

FiguresFig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.

Simplified block diagram of the CLRC663 .........7
Pinning configuration HVQFN32(SOT617-1) ........................................................8
Detailed block diagram of the CLRC663 ......... 11
Read/write mode ............................................. 15
Read/write mode for ISO/IEC 14443 type A
and read/write mode for MIFARE Classic ........15
Data coding and framing according to ISO/IEC 14443 A ................................................... 16
ISO/IEC 14443 type B communication
diagram ............................................................16
SOF and EOF according to ISO/IEC 14443
B ...................................................................... 17
FeliCa read/write communication diagram ...... 17
Data coding according to ISO/IEC 15693.
standard mode reader to label ........................ 19
Passive communication mode .........................21
Connection to host with SPI ............................22
Connection to host with SPI ............................24
Example for UART Read ................................ 26
Example diagram for a UART write .................27
I2C-bus interface ............................................. 27
Bit transfer on the I2C-bus .............................. 28
START and STOP conditions ..........................28
Acknowledge on the I2C- bus ......................... 29
Data transfer on the I2C- bus ......................... 29
First byte following the START procedure ....... 30
Register read and write access .......................31
I2C interface enables convenient MIFARE
SAM integration ...............................................33
Boundary scan cell path structure ................... 35

CLRC663

Product data sheet
COMPANY PUBLIC

Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
Fig. 31.
Fig. 32.
Fig. 33.
Fig. 34.
Fig. 35.
Fig. 36.
Fig. 37.
Fig. 38.
Fig. 39.
Fig. 40.
Fig. 41.
Fig. 42.
Fig. 43.
Fig. 44.
Fig. 45.
Fig. 46.
Fig. 47.
Fig. 48.

General dependences of modulation .............. 39
Example 1: overshoot_t1 = 2d; overhoot_t2= 5d. ................................................................ 41
Example 2: overshoot_t1 = 0d; overhoot_t2= 5d ................................................................. 42
Block diagram of receiver circuitry .................. 43
Block diagram of the active Antennaconcept ............................................................ 44
Overview SIGIN/SIGOUT Signal Routing ........45
Sector arrangement of the EEPROM .............. 47
Crystal connection ...........................................51
Internal PDown to voltage regulator logic ........55
Pin RX input voltage ..................................... 125
Timing for fast and standard mode deviceson the I2C-bus .............................................. 126
Typical application antenna circuit diagram ... 127
Package outline SOT-617-1 (HVQFN32) ...... 130
VFBGA36 Package outline ............................131
VFBGA36 Package outline notes ..................132
VFBGA36 PCB design: Solder mask
opening pattern ............................................. 133
VFBGA36 PCB design: I/O pads andsolderable area ............................................. 134
VFBGA36 PCB design: Solder paste
stencil ............................................................ 135
HVQFN32 Package marking ......................... 136
VFBGA36 Package marking ......................... 137
Packing information 1 tray .............................139
Packing information 5 tray .............................140
Tray details ....................................................141
Packing information Reel .............................. 142

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Contents
1
General description ............................................ 1
2
Features and benefits .........................................3
3
Applications .........................................................4
4
Quick reference data .......................................... 55
Ordering information .......................................... 66
Block diagram ..................................................... 7
7
Pinning information ............................................ 8
7.1
Pin description HVQFN32 ................................. 8
7.2
Pin description VFBGA36 ..................................98
Functional description ......................................11
8.1
Interrupt controller ............................................11
8.2
Timer module ...................................................13
8.2.1
Timer modes ....................................................148.2.1.1
Time-Out- and Watch-Dog-Counter ................. 14
8.2.1.2
Wake-up timer ................................................. 14
8.2.1.3
Stop watch .......................................................148.2.1.4
Programmable one-shot timer ......................... 14
8.2.1.5
Periodical trigger ..............................................14
8.3
Contactless interface unit ................................ 15
8.3.1
Communication mode for ISO/IEC 14443
type A and for MIFARE Classic ....................... 15
8.3.2
ISO/IEC14443 type B functionality .................. 16
8.3.3
FeliCa functionality .......................................... 17
8.3.3.1
FeliCa framing and coding .............................. 18
8.3.4
ISO/IEC15693 functionality ..............................18
8.3.5
EPC-UID/UID-OTP functionality ...................... 19
8.3.6
ISO/IEC 18000-3 mode 3/ EPC Class-1 HF
functionality ...................................................... 20
8.3.6.1
Data encoding ICODE ..................................... 20
8.3.7
ISO/IEC 18092 mode ...................................... 20
8.3.7.1
Passive communication mode ......................... 20
8.3.7.2
ISO/IEC 18092 framing and coding ................. 21
8.3.7.3
ISO/IEC 18092 protocol support ......................21
8.4
Host interfaces .................................................22
8.4.1
Host interface configuration ............................. 22
8.4.2
SPI interface .................................................... 22
8.4.2.1
General ............................................................ 22
8.4.2.2
Read data ........................................................ 23
8.4.2.3
Write data ........................................................ 23
8.4.2.4
Address byte ....................................................23
8.4.2.5
Timing Specification SPI ..................................24
8.4.3
RS232 interface ............................................... 24
8.4.3.1
Selection of the transfer speeds ...................... 24
8.4.3.2
Framing ............................................................25
8.4.4
I2C-bus interface ............................................. 27
8.4.4.1
General ............................................................ 27
8.4.4.2
I2C Data validity .............................................. 28
8.4.4.3
I2C START and STOP conditions ....................28
8.4.4.4
I2C byte format ................................................28
8.4.4.5
I2C Acknowledge .............................................29
8.4.4.6
I2C 7-bit addressing ........................................ 29
8.4.4.7
I2C-register write access ................................. 30
8.4.4.8
I2C-register read access ................................. 30
8.4.4.9
I2CL-bus interface ........................................... 31
8.4.5
SAM interface .................................................. 32
8.4.5.1
SAM functionality ............................................. 32
CLRC663

Product data sheet
COMPANY PUBLIC

8.4.5.2
8.4.6
8.4.6.1
8.4.6.2
8.4.6.3
8.4.6.4
8.4.6.5
8.4.6.6
8.4.6.7
8.4.6.8
8.4.6.9
8.4.6.10
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2
8.6.3
8.6.3.1
8.6.3.2
8.6.4
8.6.5
8.7
8.7.1
8.7.2
8.7.2.1
8.7.3
8.8
8.8.1
8.8.2
8.8.3
8.9
8.9.1
8.9.2
8.9.2.1
8.9.2.2
8.9.2.3
8.9.3
8.9.4
8.10
8.10.18.10.28.10.38.10.3.1
8.10.3.2
8.10.3.3
8.10.3.4
8.10.3.5

SAM connection .............................................. 33
Boundary scan interface ..................................33
Interface signals .............................................. 34
Test Clock (TCK) ............................................. 34
Test Mode Select (TMS) ..................................34
Test Data Input (TDI) ....................................... 35
Test Data Output (TDO) .................................. 35
Data register .................................................... 35
Boundary scan cell .......................................... 35
Boundary scan path ........................................ 35
Boundary Scan Description Language(BSDL) ............................................................. 36
Non-IEEE1149.1 commands ............................37
Buffer ............................................................... 37
Overview .......................................................... 37
Accessing the FIFO buffer ...............................37
Controlling the FIFO buffer .............................. 37
Status Information about the FIFO buffer .........38
Analog interface and contactless UART .......... 39
General ............................................................ 39
TX transmitter .................................................. 39
Overshoot protection ....................................... 41
Bit generator .................................................... 42
Receiver circuitry ............................................. 42
General ............................................................ 42
Block diagram ..................................................42
Active antenna concept ................................... 43
Symbol generator ............................................ 46
Memory ............................................................ 46
Memory overview .............................................46
EEPROM memory organization .......................46
Product information and configuration Page 0 ............................................................. 47
EEPROM initialization content
LoadProtocol ....................................................49
Clock generation ..............................................51
Crystal oscillator .............................................. 51
IntegerN PLL clock line ................................... 52
Low Frequency Oscillator (LFO) ......................52
Power management .........................................53
Supply concept ................................................ 53
Power reduction mode .....................................53
Power-down ..................................................... 53
Standby mode ................................................. 54
Modem off mode ............................................. 54
Low-Power Card Detection (LPCD) ................. 54
Reset and start-up time ................................... 54
Command set .................................................. 55
General ............................................................ 55
Command set overview ................................... 55
Command functionality .................................... 56
Idle command .................................................. 56
LPCD command .............................................. 56
Load key command ......................................... 56
MFAuthent command .......................................57
AckReq command ........................................... 57

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CLRC663

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High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
8.10.3.6 Receive command ........................................... 57
8.10.3.7 Transmit command .......................................... 57
8.10.3.8 Transceive command .......................................58
8.10.3.9 WriteE2 command ........................................... 58
8.10.3.10 WriteE2PAGE command ..................................58
8.10.3.11 ReadE2 command ........................................... 58
8.10.3.12 LoadReg command ......................................... 58
8.10.3.13 LoadProtocol command ...................................58
8.10.3.14 LoadKeyE2 command ..................................... 60
8.10.3.15 StoreKeyE2 command .....................................60
8.10.3.16 GetRNR command .......................................... 60
8.10.3.17 SoftReset command ........................................ 61
9
CLRC663 registers ............................................ 62
9.1
Register bit behavior ....................................... 62
9.2
Command configuration ...................................65
9.2.1
Command ........................................................ 65
9.3
SAM configuration register .............................. 65
9.3.1
HostCtrl ............................................................ 65
9.4
FIFO configuration register .............................. 66
9.4.1
FIFOControl ..................................................... 66
9.4.2
WaterLevel ....................................................... 67
9.4.3
FIFOLength ......................................................68
9.4.4
FIFOData ......................................................... 68
9.5Interrupt configuration registers ....................... 68
9.5.1
IRQ0 register ................................................... 69
9.5.2
IRQ1 register ................................................... 69
9.5.3
IRQ0En register ............................................... 70
9.5.4
IRQ1En ............................................................ 70
9.6
Contactless interface configuration
registers ........................................................... 71
9.6.1
Error ................................................................. 71
9.6.2
Status ...............................................................72
9.6.3
RxBitCtrl ...........................................................73
9.6.4
RxColl .............................................................. 74
9.7
Timer configuration registers ........................... 74
9.7.1
TControl ........................................................... 74
9.7.2
T0Control ......................................................... 75
9.7.2.1
T0ReloadHi ...................................................... 76
9.7.2.2
T0ReloadLo ..................................................... 76
9.7.2.3
T0CounterValHi ................................................77
9.7.2.4
T0CounterValLo ............................................... 77
9.7.2.5
T1Control ......................................................... 77
9.7.2.6
T1ReloadHi ...................................................... 78
9.7.2.7
T1ReloadLo ..................................................... 78
9.7.2.8
T1CounterValHi ................................................79
9.7.2.9
T1CounterValLo ............................................... 79
9.7.2.10 T2Control ......................................................... 79
9.7.2.11 T2ReloadHi ...................................................... 80
9.7.2.12 T2ReloadLo ..................................................... 80
9.7.2.13 T2CounterValHi ................................................81
9.7.2.14 T2CounterValLoReg ........................................ 81
9.7.2.15 T3Control ......................................................... 81
9.7.2.16 T3ReloadHi ...................................................... 82
9.7.2.17 T3ReloadLo ..................................................... 82
9.7.2.18 T3CounterValHi ................................................83
9.7.2.19 T3CounterValLo ............................................... 83
9.7.2.20 T4Control ......................................................... 83
9.7.2.21 T4ReloadHi ...................................................... 84
9.7.2.22 T4ReloadLo ..................................................... 85
CLRC663

Product data sheet
COMPANY PUBLIC

9.7.2.23
9.7.2.24
9.8
9.8.1
9.8.2
9.8.3
9.8.4
9.9
9.9.1
9.9.2
9.10
9.10.19.10.29.10.39.10.49.10.5
9.11
9.12
9.12.1
9.12.29.12.39.12.49.12.59.12.69.13
9.13.19.13.29.13.39.13.49.14
9.14.19.14.29.14.39.14.49.14.59.14.69.15
9.15.1
9.15.29.15.39.15.49.16
9.16.1
9.16.29.16.39.16.49.16.59.16.69.16.79.16.89.16.99.16.109.16.119.16.129.16.13
9.17
9.17.1
9.17.2

T4CounterValHi ................................................85
T4CounterValLo ............................................... 85
Transmitter driver configuration registers .........86
DrvMode .......................................................... 86
TxAmp ..............................................................86
TxCon .............................................................. 87
Txl .................................................................... 87
Transmitter CRC configuration registers ..........88
TxCrcPreset ..................................................... 88
RxCrcCon ........................................................ 89
Transmitter data configuration registers ...........89
TxDataNum ......................................................90
TxDATAModWidth ............................................90
TxSym10BurstLen ........................................... 91
TxWaitCtrl ........................................................ 91
TxWaitLo .......................................................... 92
FrameCon ........................................................ 92
Receiver configuration registers ...................... 93
RxSofD .............................................................93
RxCtrl ............................................................... 93
RxWait ............................................................. 94
RxThreshold .....................................................95
Rcv ...................................................................95
RxAna .............................................................. 96
Clock configuration .......................................... 97
SerialSpeed ..................................................... 97
LFO_Trimm ...................................................... 98
PLL_Ctrl Register ............................................ 98
PLLDiv_Out ......................................................99
Low-power card detection configuration
registers ......................................................... 100
LPCD_QMin ...................................................100
LPCD_QMax ..................................................101
LPCD_IMin .....................................................101
LPCD_Result_I .............................................. 101
LPCD_Result_Q ............................................ 102
LPCD_Options ............................................... 102
Pin configuration ............................................ 103
PadEn ............................................................ 103
PadOut ...........................................................104
PadIn ..............................................................104
SigOut ............................................................ 105
Protocol configuration registers ..................... 106
TxBitMod ........................................................106
TxDataCon .....................................................106
TxDataMod .................................................... 107
TxSymFreq .................................................... 108
TxSym0 ..........................................................109
TxSym1 ..........................................................110
TxSym2 ..........................................................110
TxSym3 ..........................................................111
TxSym10Len ..................................................111
TxSym32Len ..................................................111
TxSym10BurstCtrl ..........................................112
TxSym10Mod Reg ......................................... 112
TxSym32Mod .................................................113
Receiver configuration ................................... 114
RxBitMod ....................................................... 114
RxEofSym ...................................................... 115

All information provided in this document is subject to legal disclaimers.

Rev. 5.2 — 2 July 2021
171152© NXP B.V. 2021. All rights reserved.

182 / 183

CLRC663

NXP Semiconductors

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
9.17.39.17.49.17.59.17.69.17.79.17.89.18
9.18.1
10
11
12
12.1
12.2
13
13.1
14
14.1
14.1.114.1.214.1.314.1.4
15
15.1
15.2
16
16.1
16.2
17
18
19
19.1
19.2
20
21
22
23

RxSyncValH ................................................... 115
RxSyncValL ....................................................115
RxSyncMod ....................................................116
RxMod ............................................................116
RxCorr ............................................................117
FabCali ...........................................................117
Version register ..............................................118
Version ........................................................... 118
Limiting values ................................................ 119
Recommended operating conditions ............ 120
Thermal characteristics .................................. 121
Thermal characteristics HVQFN32 ................ 121
Thermal characteristics VFBGA36 .................121
Characteristics ................................................ 122
Timing characteristics .................................... 125
Application information .................................. 127
Antenna design description ........................... 127
EMC low pass filter ....................................... 127
Antenna matching ..........................................128
Receiving circuit .............................................128
Antenna coil ...................................................128
Package outline ...............................................130
Package outline HVQFN32 ............................130
Package outline and PCB design
information VFBGA36 ....................................131
Marking .............................................................136
Marking HVQFN32 ........................................ 136
Marking VFBGA36 .........................................136
Handling information ...................................... 138
Packing information ........................................139
Appendix .......................................................... 144
LoadProtocol command register
initialization .................................................... 144
CLRC66303 EEPROM configuration ............. 158
Abbreviations .................................................. 171
References ....................................................... 173
Revision history .............................................. 174
Legal information ............................................ 175

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

© NXP B.V. 2021.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 July 2021
Document identifier: CLRC663
Document number: 171152