Product
Document

Published by
ams OSRAM GroupAS3953A
14443 High Speed Passive Tag
Interface
General Description

The AS3953A NFC interface IC (NFiC) delivers low cost, ultra low
power NFC Forum functionality to multiple different
applications. The AS3953A is a analog front-end with integrated
14443A data framing and SPI interface. It is designed to createa fast data link between an ISO 14443A reader device (PCD) anda microcontroller. The AS3953A is passively powered meaningthat it can be supplied from the PCD magnetic field, eliminating
the need of a continual external supply. This makes theAS3953A perfect for wireless communication to a low-power
battery powered device.
The AS3953A is used with an appropriate antenna coilconnected to the terminals LC1 and LC2, and behaves as anormal passive ISO 144443A tag (PICC). After the anti-collision
protocol is passed, the PCD sends a Wake-Up command, which
wakes up the microcontroller by sending an interrupt. From thispoint onwards, the AS3953A serves as a data link between the
microcontroller and the PCD. AS3953A can also operate as
NFCIP-1 target at 106 kbit/s.
The AS3953A includes an onboard EEPROM that can beaccessed either from the PCD or from the microcontroller via
the SPI interface. This built-in flexibility makes it ideal for two
types of applications:• Where personalization data is programmed by the PCD(even in case the SPI side is not powered) and it is laterread by microcontroller through SPI interface.
• Where log data is stored periodically by the
microcontroller and can then be read by the PCD evenwhen the microcontroller is not powered.
A regulated power supply voltage extracted from the PCD field
is also available on a pin and can be used as power supply forexternal circuitry. For example, an external microcontroller anda sensor could be powered from the PCD field combined withpass through data rates up to 848kbit/s, which means theAS3953A is ideal for contactless passive programming of MCU
systems. The AS3953A can also operate as a stand-alone ISO
14443A tag.
The AS3953A supports ISO 14443A up to Level-4, meaning acontactless smart card or an NFC forum compatible tag (TagType 4) can be built. Having a NFC Forum compatible taginterface allows the AS3953A to be used in an application wherea standard NFC enabled phone is used as a PCD.
Ordering Information and Content Guide appear at end ofdatasheet.

ams Datasheet[v1-05] 2019-Feb-15

Page 1Document FeedbackAS3953A − General Description

Key Benefits & Features
The benefits and features of AS3953A, 14443 High Speed
Passive Tag Interface are listed below:
Figure 1:
Added Value of Using AS3953A

Benefits

Features• NFC Forum compliance for fullinteroperability• ISO 14443A compliant to Level-4• Internal user memory for standalone
application• 1kbit EEPROM (108 bytes of user memory)• Allows zero-power standby• Configurable wake-up interrupt (after tag is selected orusing proprietary command)• Enables long battery life time, orbattery-less designs• Powered from external magnetic field with the possibility todraw up to 5mA• Allows supply of external circuitry• User configurable regulated voltage extracted from external
magnetic field• Data rate transmission up to the
maximum allowed by ISO 14443A
compliance• Bit rates from 106 kbit/s till 848 kbit/s• 7 byte UID• Easy and fast antenna design and
impedance matching• Integrated resonant capacitor• Guarantees no reset during reader (PCD)
modulation• Integrated buffer capacitor• Design flexibility, easy integration.
• Fits requirements for various embedded
applications and manage of external
microcontroller• 4-wire Serial Peripheral Interface (SPI) with 32 byte FIFO

• Fits supply requirements for various
applications, including industrial• Wide SPI power supply range (1.65V to 3.6V)• Flexibility for wide range of applications• Wide temperature range: -40ºC to 85ºC

• Small outline, compatibility to common
inlay and card manufacturing lines,
surface-mount assembly• Available as WLCSP 10-bumps, 10-pin MLPD (3mmx3mm)
and tested sawn wafers

Page 2Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − General Description

Applications
The device is ideal for applications like• Passive wake-up• Multipurpose HF interface to a controller• Low power or passive programming• Ultra low power data logger• RFID programmable configuration EEPROM• ISO 14443A smart card
• NFC Forum Tag Type 4• Bluetooth and Wi-Fi pairing

Block Diagram
The functional blocks of this device are shown below:
Figure 2:
AS3953A Block Diagram

VP_REG
VP_INT

AS3953A

Power
Manager

VP_SPI

VDD
LC1

IRQ
AFE

LC2

ams Datasheet[v1-05] 2019-Feb-15

Logic
POR

EEPROM

Level
Shifters

SPI
VSS

Page 3Document FeedbackAS3953A − Pin Assignment

Pin Assignment
Figure 3:
Pin Diagram (Top View)GND
VP_SPI1

VP_REG

2

LC1

3

LC2
VSS

10

IRQ

9

MISO

8

MOSI

4

7

SCLK

5

6

/SS

AS3953A
MLPD(Top view)

IRQ

/SS
A1

MOSI

MISO

A2

A3

LC2

LC1

B2

B3

SCLK
B1

VSS

VP_REG

10

9

8

7

6

IRQ

MISO

MOSI

SCLK

/SS

B4

VP_SPI

AS3953 A
WL-CSP(Top view)

C1

A4

C4

AS3953A die

Page 4Document Feedback

3

4

VSS

2

LC2

1

LC1

VP_REG0

VP_SPITEST(Bottom view)5ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Pin Assignment

Figure 4:
Pin Description

Pin Number
Pin Name

Pin Type0

TESTInternal use

No connection

C4

1

VP_SPI

Supply pad

Positive supply of SPI interface

2

B4

2

VP_REG

Analog output

Regulator output

3

B3

3

LC1

4

B2

4

LC2

5

C1

5

VSS

6

A1

6

/SS

7

B1

7

SCLK

8

A2

8

MOSI

9

A3

9

MISO

Digital output /tristate

Serial Peripheral Interface data
output

10

A4

10

IRQ

Digital output

Interrupt request output (active
high)

11

-

-

Exposed Pad

SupplyExposed pad to be connected to
ground (optional)

MLPD

WL-CSP

Die

-

-

1

ams Datasheet[v1-05] 2019-Feb-15

Description

Analog I/OConnection to tag coilSupply pad

Ground, die substrate potential
Serial Peripheral Interface enable(active low)

Digital input

Serial Peripheral Interface clock
Serial Peripheral Interface data
input

Page 5Document FeedbackAS3953A − Absolute Maximum Ratings

Absolute Maximum Ratings

Stresses beyond those listed in Absolute Maximum Ratings may
cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any
other conditions beyond those indicated in Electrical
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Figure 5:
Absolute Maximum Ratings

SymbolParameter

Min

Max

Units

Comments

Electrical Parameters
VDD

DC supply voltage

-0.5

5

V

VIN

Input pin voltage except
LC1 and LC2

-0.5

5

V

Input pin voltage pins LC1and LC2

-0.5

6.5

V

100

mA

100

mA

Peak current induced on
pins LC1 and LC2
Iscr

Input current(latchup immunity)-100

Jedec 78

Electrostatic Discharge
ESD

Electrostatic discharge±2kV

MIL 883 E method 3015
(Human Body Model)

Temperature Ranges and Storage Conditions
Tstrg

Storage temperature

Tbody

Package body temperature

RHNC

Relative humidity(non-condensing)Page 6
Document Feedback

-55

5

125

ºC

260

ºC

85

%

IPC/JEDEC J-STD-020
The reflow peak soldering
temperature (body temperature)is specified according IPC/JEDEC
J-STD-020 “Moisture/Reflow
Sensitivity Classification for
Non-hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded
packages is “Matte Tin” (100% Sn)

ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Absolute Maximum Ratings

SymbolParameter

MSL

Moisture sensitivity leveltstrg_DOF

Storage time for DOF/dieor wafers on foil

Tstrg_DOF

Storage temperature for
DOF/die or wafers on foil

RHopen_Relative humidity for
DOF/die or wafers on foil inopen package

DOF

RHUnopen_
DOF

Relative humidity for
DOF/die or wafers on foil inclosed package

ams Datasheet[v1-05] 2019-Feb-15

Min

Max

40

Comments

3

MLPD

1

WL-CSP

3
18

Units

monthsRefer to indicated date of packing

24

ºC

15

%

Opened package

60%

Unopened package

Page 7
Document FeedbackAS3953A − Electrical Characteristics

Electrical Characteristics

All in this specification defined tolerances for external
components need to be assured over the whole operation
conditions range and also over lifetime.

Operating Conditions
Figure 6:
Operating Conditions

SymbolParameter

Ilim

Limiter current

VVP_SPI

TAMB

Min

Typ

Max

Units

Note

30

mA

Till this current limiterclamps VLC1-LC2 to 5.0V

1.65

3.6

V

When logic powered from
RFID interface

1.8

3.6

V

When logic powered from
VP_SPI interface

-40

85

ºC

SPI power supply

Ambient temperature

DC/AC Characteristics for Digital Inputs and
Outputs
Figure 7:
CMOS Inputs: Valid for Input Pins /SS, MOSI, SCLK

SymbolParameter

Min

VIH

High level input voltage

0.7 * VP_
SPI

VIL

Low level input voltage

0.3 * VP_
SPI

V

ILEAK

Input leakage current

1

μA

Page 8Document Feedback

Typ

Max

Units

Note

V

ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Electrical Characteristics

Figure 8:
CMOS Outputs: Valid for Output Pins MISO, IRQ

SymbolParameter

Min

VOH

High level output
voltage0.85 * VP_
SPI

Typ

Max

Units
V

ISOURCE = 1mA
VP_SPI = 3V

VOL

Low level output
voltage

0.15*
VP_SPIV

CCL

Capacitive load

50

pF

RO

Output Resistance

400

Ω

RPD

Pull-down resistancepad MOSI

ams Datasheet[v1-05] 2019-Feb-15

Note

200

10

kΩ

Pull-down can be
enabled while MISO
output is in tristate. The
activation is controlled
by register setting

Page 9Document FeedbackAS3953A − Electrical Characteristics

Electrical Specification
VP_SPI = 3.0 V, Temperature 25ºC, unless noted otherwise.
Figure 9:
Electrical Specification

SymbolParameter

ISB_SPI

Standby consumption
on VP_SPIISB_SPI

Standby consumption
on VP_SPI

VLIM

Limiter voltage

Min

1.8

Typ

Max

Units

Note

65

100

nA

@ 25ºC- RF field not applied

2.2

2.7

μA

@ 25ºC- RF field applied

5.2

5.7

V

ILC = 30mA (DC)μA

Internal supply current
measured in test mode on
VREC, 13.56 MHz alternative
pulses with amplitude 2Vpp,
negative peak at VSS, forced
to LC1 and LC2

V

Set to 1.8V in EEPROM
Configuration word

IS

Supply current

VVP_REG

Regulated supply
voltage

VHF_PON

HF_PON threshold(rising VREG)

2.3

VPOR_HY

HF_PON hysteresis

0.8

VMOD

Modulator ON voltage
drop

250

1.65

1.8

2.01

V
Guaranteed by design onlyV
ILC = 1mA

1.2
V

ILC = 30mA

3.3

Resonance capacitor
for die

25.2

28

30.8

Resonance capacitor
for MLPD package

28.2

31.3

34.4

Resonance capacitor
for WL-CSP package

27

30

33

EEEN

EEPROM endurance

100000cyclesEERET

EEPROM retention

10

years

CR

pF

Measured at 10MHz, 3.0Vpp(2.5Vpp)
Guaranteed by design@ 125ºC

Page 10
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Detailed Description
Figure 10:
System Block Diagram

ISO 14443A
ReaderSPI
AS3953A

Microcontroller

Circuit
The AS3953A is composed of ISO 14443A PICC Analog
Front-end (PICC AFE), the ISO 14443A PICC Logic (PICC Logic),
EEPROM, SPI Interface, Level Shifters and Power Supply
Manager Block (Power Manager).
The PICC AFE is connected to an external tag coil, which forms
together with integrated resonant capacitor an LC tank with aresonance at the external electromagnetic field frequency of
13.56 MHz. The PICC AFE has a built in rectifier and regulators.
Output of internal regulator is called VP_INT. It is used to supply
the PICC AFE and usually also the LOGIC and EEPROM (throughPower Supply Manager). Output of external regulator VP_REG
is available on a pin to supply some external circuitry.
Power Manager is controlling power supply of Logic and
EEPROM. The two blocks can be supplied either from VP_INT orfrom VP_SPI (SPI power supply). In order to save current on VP_
SPI, VP_INT is used as power supply whenever it is available.
VP_SPI is only used when some activity is started over the SPI
and the VP_INT is too low to be used as a power supply.
The PICC Logic is responsible for PICC-to-PCD communication
up to the Level-4 (block transmission) of ISO 14443A. Thismeans that anti-collision and other low-level functionality are
implemented there.
The SPI Interface logic contains a 32 byte FIFO for blocktransmission data which is exchanged on Level-4 of ISO 14443A
communication. It also contains some control and display
registers.
The EEPROM is used to store the UID, the housekeeping data
(configuration and control bits) and user data. It can beaccessed from both sides (RFID and SPI).

ams Datasheet[v1-05] 2019-Feb-15

Page 11
Document FeedbackAS3953A − Detailed Description

PICC AFE
Figure 11 depicts main PICC AFE building blocks.
The PICC AFE is connected to external tag coil, which together
with the integrated resonant capacitor forms an LC tank withresonance at external electromagnetic field frequency (13.56
MHz). Figure 11 depicts the main PICC AFE building blocks.
Rectifier: Extracts DC power supply from AC voltage inducedon coil terminals.
Limiter: Limits the maximum voltage on coil terminals toprotect PICC AFE from destruction. At voltages that exceed
limiter voltage it starts to absorb current (acts as some sort ofshunt regulator).
Modulator Switch: Is used for communication PICC-to-PCD.
When switched on, it will draw current from coil terminals. Thismechanism is called load modulation. Variation of current in
the modulator switch (ON and OFF state) is seen as modulationby the PCD.
Demodulator: Is used for communication PICC-to-PCD. It
detects AM modulation of the PCD magnetic field. The
demodulator is designed to accept modulation according to
ISO 14443A; all standard bit rates from 106 kbit/s to 848 kbit/s
are supported. The modulation for bit rate 106 kbit/s is 100%,
whereas for other bit rates it may be less.
Clock Extractor: The clock extractor extracts a digital clock
signal from the PCD carrier field frequency which is used asclock signal by logic blocks.
HF_PON: Observes rectified regulated voltage VREC. When the
supply voltage is sufficiently high it enables operation of the
PICC AFE and the digital tag logic. A buffer capacitor and
HF_PON hysteresis guarantees that there is no reset during
reader (PCD) modulation.
Internal Regulator: Provides regulated voltage VP_INT to the
PICC AFE and in most cases also to EEPROM and logic blocks.
Typical regulated voltage VP_INT is 2.0V. A buffer capacitor isalso integrated.
External Regulator: Provides regulated voltage on external
pin VP_REG where it can be used to supply some external
circuitry. The regulated voltage and output resistance can be
adjusted using EEPROM settings (see Figure 37). Appropriate
external buffer capacitor is needed in case VP_REG is used in
the application. The current to be provided depends on reader
field strength, antenna size and Q factor, but it is limited tomaximum 5mA.
Bias: Provides bias currents and reference voltages to PICC AFE
analog blocks.

Page 12Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure 11:
PICC AFE Block Diagram

VP_REG

Rectifier

LimiterVREC

VP_INT

External
Regulator

Internal
Regulator

LC1
Modulator
Switch

BIAS

HF
PON

ISO 14443 A
LOGIC

LC2
Demodulator

AS3953A
Clock
Extractor

ams Datasheet[v1-05] 2019-Feb-15

Page 13Document FeedbackAS3953A − Detailed Description

Power Manager
Power manager is controlling the positive supply voltage of the
PICC Logic, EEPROM and SPI Interface (VDD). Its inputs are
VP_INT (rectified and regulated supply extracted from PCD
field) and the VP_SPI (SPI power supply from external).
In standby mode, when the AS3953A is not in a PCD field(condition is that rectified supply voltage is below HF_PON
threshold) and the SPI is not active (/SS is high) the VDD supply
is disconnected not to consume on VP_SPI. The only
consumption on VP_SPI is leakage of level shifters and SPI pins.
When the AS3953A is placed in a PCD field the VDD is connected
to VP_INT. This happens once the VP_INT level is above the
HF_PON threshold.
VP_SPI is connected to VDD only when the AS3953A is not in
the PCD field (rectified supply voltage is below HF_PON
threshold) and the SPI interface is activated by pulling /SS signal
low. The switch to VP_SPI is controlled by /SS signal. The
deactivation is delayed by 0.7ms min., thus the switch stays onin case the time between successive SPI activations is short.
During EEPROM writing, which is activated over the SPI, theswitch is also active.
At activation of the switch the time between the falling edgeof /SS signal and rising edge of SCLK has to be at least 50μs toallow charging of internal VDD buffer capacitor and expirationof POR signal. Please note that the only SPI operations, which
are allowed in this mode, are reading and writing of the EEPROM
and registers.
Figure 12:
Power Manager Concept

VP_INT
PON
VDD/SS
EEPROM
WRITE

Page 14Document Feedback

DELAY
VP_SPIams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

ISO 14443A Framing Mode
When Framing mode is selected the PICC logic performs receive
and transmit framing according to the selected ISO 14443A bit
rate.
During reception it recognizes the SOF, EOF and data bits,
performs parity and CRC check, organizes the received data inbytes and places them in the FIFO.
During transmit, it operates inversely, it takes bytes from FIFO,
generates parity and CRC bits, adds SOF and EOF and performs
data encoding.
Default bit rate in the Framing mode is fc/128 (~106 kbit/s).
Higher data rates may be configured by controller by writing
the Bit Rate Definition Register.
In order to respect the PCD-to-PICC frame delay according toISO14443-3 at data rate fc/128 bit the PICC logic synchronizes
the response to the beginning of the next response window,
but not earlier than window with n=9.
In this mode the EEPROM can be accessed via SPI when the RF
field is active.

ISO 14443A Level-4 Protocol Mode
When Level-4 Protocol mode is selected the PICC Logic
autonomously execute complete ISO 14443A Level-3
communication and certain commands of Level-4. This also
includes the anti-collision sequence during which the AS3953A
UID number is read by the PCD (7 bytes UID is supported), theAS3953A is brought in the selected state (ISO14443-4) in whichdata exchange between the AS3953A and the PCD can start. On
this level also a reading and writing of the AS3953A EEPROM ispossible.
In case the configuration bit irq_l4 is set an interrupt is
automatically sent to controller once the PICC Logic enters in
ACTIVE(*) state (after sending SAK on Cascade Level 2).

ams Datasheet[v1-05] 2019-Feb-15

Page 15
Document FeedbackAS3953A − Detailed Description

Support of ISO 14443A Level-4
ISO 14443A-4 commands RATS, PPS and DESELECT are
implemented in the PICC Logic. RATS and PPS define
communication parameters, which are going to be used in thefollowing data exchange by using the block transmission
protocol. The advantage of implementing PPS that defines thebit rate used for communication, is that all bit rate issues arehandled by the PICC Logic. The MCU gets the information about
the actual receive and transmit bit rate by reading a dedicateddisplay register. It has to be fast enough to serve receive andtransmit at the maximum bit rate.
Execution of the block transmission protocol is left to thecontroller. In case of receiving the block data from the PCD the
PICC Logic provides support by detecting and removing startbit, stop bit, parity bits and CRC. Parity bits and CRC are also
checked. When the block data is sent to the PCD the PICC Logic
calculates and inserts start bit, parity bits, CRC and stop bit.
DESELECT puts the PICC Logic in HALT state. An interrupt is sent
to controller upon reception of DESELECT command to inform
it that PCD stopped the Level-4 communication.
Additionally to supporting the ISO14443-4 transmitting
protocol the PICC Logic accepts also proprietary commands.
Proprietary commands are identified by setting the two MSB
bits of first transmitted byte to ‘01’ (This combination is not
used by ISO 14443A Level-4 protocol).
The following custom commands are implemented:• Wake-up: Sends a wake-up interrupt to controller• Read EEPROM: Reads data from EEPROM• Write EEPROM: Writes data to EEPROM
Support of ISO 14443A Optional Features• CID is supported• NAD is not supported• Historical bytes are not supported• Power level indication is not supported

Page 16Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Coding of UID
Anti-collision procedure is based on Unique Identification
Number (UID). The AS3953A supports double UID size (7 bytes).
First three bytes of UID are hard-wired inputs to the PICC Logic(uid<23:0>). Last 4 bytes of UID are stored in EEPROM UID word.
First Byte of UID (uid0)
First byte of UID is according to [ISO3] ISO/IEC 7816-6 IC
Manufacturer ID. It is coded on bits uid<7:0>. ams IC
Manufacturer ID is 3F(hex).
Second Byte of UID (uid1)
Second byte of UID – uid<15:8> is reserved for ams chip type
(IC Type). Every ams RFID tag IC has its own chip type attributed.
Therefore PCD which has read the RFID tag UID knows to which
tag IC it is talking.
The AS3953A IC type is 10(hex).
Third Byte of UID (uid2)
Third byte of UID – uid<23:16> is set to 00(hex). Figure below
defines the coding of the first three bytes of UID.
Figure 13:
Coding of First Three Bytes of UID

UID Byte

FL Signal Name

Value (hex)uid0

uid<7:0>3F

uid1

uid<15:8>

10

uid2

uid<23:16>00

The last 4 bytes of UID are read from EEPROM (UID word). Figure
below defines the last four bytes of UID.
Figure 14:
Coding of Last Four Bytes of UID

ams Datasheet[v1-05] 2019-Feb-15

UID Byte

UID Word Bits

uid3

b7-b0

uid4

b15-b8uid5

b23-b16

uid6

b31-b24

Page 17
Document FeedbackAS3953A − Detailed Description

Coding of ATQA, SAK and ATS
Several bits of responses ATQA, SAK and ATS are defined as“don’t care” in the ISO 14443A standard. Some others aredefined by optional choices in standard protocol. This section
defines how these bits are set by the AS3953A.
ATQA
ATQA is response to REQA and WUPA commands. Figure below
defines the ATQA coding.
Figure 15:
ATQA Coding
b16

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

UID size

Bit frame anti-collision

Bits b16 to b13 are RFU bits which must be set to ‘0’.
Bits b12 to b9 are proprietary coding and are set to ‘0’.
Bits b8 and b7 indicate double size UID.
Bit b6 is ‘RFU’ bit and is set to ‘0’.
For bit frame anti-collision, the code 00100 is chosen.
SAK
SAK is response to SELECT command. AS3953A UID has double
size, which defines SAK responses for Cascade Level 1 andCascade Level 2.
Cascade Level 1: According to ISO 14443-3, all bits except b3
are “don’t care” for Cascade Level 1. Figure below defines
Cascade Level 1 coding.
Figure 16:
Cascade Level1 Coding

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

Description

0

0

0

0

0

1

0

0

Cascade bit set: UID notcomplete

Page 18
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Cascade Level 2: According to ISO 14443-3 all bits except b6
and b3 are “don’t care” for Cascade Level 2.
If configuration bit16 [nl4] is set to logic ‘0’ (default state), theSAK on Cascade Level 2 reports that tag is compliant to level4(see figure below).
Figure 17:
Cascade Level 2 Coding (ISO/IEC14443-4 Compliant)

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

0

0

1

0

0

0

0

0

Description
UID complete, tag iscompliant toISO/IEC14443-4

If configuration bit16 [nl4] is set to logic ‘1’, the SAK on Cascade
Level 2 reports that tag is NOT compliant to Level-4 (see figure
below).
Figure 18:
Cascade Level 2 Coding (NOT ISO/IEC14443-4 Compliant)

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

Description

0

0

0

0

0

0

0

0

UID complete, tag is NOT
compliant toISO/IEC14443-4

If configuration bit15 [nfc] is set to logic ‘1’, the SAK on Cascade
Level 2 reports that tag is NFC passive target (see figure below).
Figure 19:

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

0

1

0

0

0

0

0

0

ams Datasheet[v1-05] 2019-Feb-15

Description
UID complete, tag iscompliant to NFCIP-1
transport protocol

Page 19
Document FeedbackAS3953A − Detailed Description

ATS
ATS is response to ISO 14443-4 command RATS. The content of
the ATS is used to inform the PCD about PICC capability (likethe maximum frame size, support of higher bit rates, etc.).
Several response fields of ATS are stored in EEPROM
configuration word. The AS3953A ATS is composed of following
5 bytes according to [ISO4]: TL, T0, TA(1), TB(1) and TC(1).
TL: This is the length byte. Since ATS is composed of 5 bytes, its
content is 0x05.Figure below defines the coding of the TL byte.
Figure 20:
TL Byte Coding

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

Description

0

0

0

0

0

1

0

1

Coding of ATS byte TL

T0: This is the format byte. Figure below defines the coding of
the T0 byte.
Figure 21:
T0 Byte Coding

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

Description

0

1

1

1

fsci<3>

fsci<2>

fsci<1>

fsci<0>Coding of ATS byte T0

TC(1)

TB(1)

TA(1)

FCSI
Bit b8 is set to ‘0’.
Bits b7 to b5 indicate presence of bytes TA(1), TB(1) and TC(1)and hence are all set to ‘1’.
Bits b4 to b1 are called FCSI and codes FCS. The FCS is maximum
size of a frame defined by PICC. It is defined by configuration
bits fsci<3:0>.

Page 20
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

TA(1): This codes the bit rate capability of PICC. Supported
higher bit rates of AS3953A are 212, 424 and 848 kbit/s.
However in specific applications, it is advised to report lower
capability to PCD (for example, due to the usage of slow
controller or low power application). Due to this reason theTA(1) response is configurable using configuration bits.
Figure 22:
TA(1) Byte Coding

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

Description

dr_sdrdr_
picc_8dr_
picc_4dr_
picc_2

0

dr_
pcd_8

dr_
pcd_4

dr_
pcd_2

Coding of ATS byte TA(1)DS (PICC to PCD)DR (PCD to PICC)
Bit b8 set to ‘0’ codes possibility of having different data rates
for each direction.
TB(1): The interface byte TB(1) conveys information to define
the frame waiting time and the start-up frame guard time. Theinterface byte TB(1) consists of two parts:• The most significant half-byte b8 to b5 is called FWI andcodes frame waiting time (FWT).
• The least significant half byte b4 to b1 is called SFGI andcodes a multiplier value used to define the SFGT. The SFGT
defines a specific guard time needed by the PICC before
it is ready to receive the next frame after it has sent theATS. SFGI is coded in the range from 0 to 14. The value of‘0’ indicates ‘No SFGT needed’.
The SFGT bits are fixed to default value which is 0x0, while the
FWI bits are defined by configuration bits fwi<3:0>. Figure
below defines the coding of the TB(1) byte.

Figure 23:
TB(1) Byte Coding

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

Description

fwi<3>

fwi<2>

fwi<1>

fwi<0>

00

0

0

Coding of ATS byte TB(1)FWI

ams Datasheet[v1-05] 2019-Feb-15

SFGI

Page 21
Document FeedbackAS3953A − Detailed Description

TC(1): The interface byte TC(1) specifies a parameter of the
protocol. The interface byte TC(1) consists of two parts:• The most significant bits b8 to b3 are set to 000000, allother values are ‘RFU’.
• The bits b2 and b1 define which optional fields in the
prolog field are supported by the PICC. The PCD is allowed
to skip fields that are supported by the PICC. Bit b2
indicates support of CID and b1 indicates support of NAD.
The AS3953A value is ‘10’ indicating “CID supported” and“NAD not supported”.
Figure below defines the coding of the TC(1) byte.
Figure 24:
TC(1) Byte Coding

b8
MSB

b7

b6

b5

b4

b3

b2

b1
LSB

Description

0

0

0

0

0

0

1

0

Coding of ATS byte TC(1)

CID

NAD

Proprietary Commands
Proprietary commands have the same format as blocks definedin ISO 14443-4 with the difference that optional NAD field isabandoned since NAD is not supported by the AS3953A. The
same format is used for commands sent by PCD and AS3953A
responses. Figure below defines the coding of the proprietarycommands.
Figure 25:
Proprietary Commands Coding

Prolog Field
PCB

[CID]

1 byte1 byteInformation Field

Epilog Field

INF

EDC
2 bytes

Prolog field consists of the mandatory Protocol Control Byte
and an optional Card Identifier Byte. Card identifier byte isaccording to ISO 14443-4 definition. Epilog field contains CRC
over transmitted block.

Page 22
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Prolog Field for Proprietary Commands
Figure below defines the coding of Prolog field for proprietarycommands.
Figure 26:
Prolog Field (proprietary commands)

Bit

Value

b8

0

b7

1

b6

0

b5

1

Function
01 indicates proprietary command

b4

Shall be set to this value, othervalues are ‘RFU’
CID following if bit is set to ‘1’

b3

1

b2

0

b1

1

Shall be set to this value, othervalues are ‘RFU’

The following proprietary commands are implemented:• Wake-Up: Sends a wake-up interrupt to controller• Read EEPROM: Reads data from EEPROM• Write EEPROM: Writes data to EEPROM
Wake-Up Command
Information field of Wake-Up command consists of one byte
only (see figure below). The AS3953A echoes back the same
information field.
Figure 27:
Wake-Up Command

01h
1byte
Figure below defines the coding of the AS3953A reply INF to
Wake-Up command.
Figure 28:
Wake-Up Reply

01h
1byte

ams Datasheet[v1-05] 2019-Feb-15

Page 23
Document FeedbackAS3953A − Detailed Description

Word Address Byte
Both proprietary commands related to EEPROM (Read andWrite) use Word Address byte to define the address of EEPROM
word that is accessed. Seven MSB bits of the Address Byte areused to define the address, while the last bit is “don’t care”.
Note(s): The valid range for the Word Address byte is from 0000
000xb to 0011 111xb (EEPROM words from 00h to 1Fh).
Read EEPROM
The Read EEPROM command is used to read data from the
EEPROM. The request information field contains the following
three bytes:• Command code byte (02h)• Address of the first word to be read
• Number of words to be read
Figure below defines coding of Read EEPROM command
information field.
Figure 29:
Read EEPROM Command02h

Address of First
Word to be Read

Number of Words(≤8) to be Read

1byte

1byte

1byte

If the request is normally processed, the reply information fieldcontains the status word 90h followed by the data. In case oferror, the information field only contains the error status byte.
The following rules apply:• In case the number of words to be read is higher than 8,
first eight words are read.
• In case the read protected word (its read lock bit is set) isaccessed, an all ‘0’ data is sent out.
• In case the reading starts at valid address and the numberof words to read is such that the reading would be done
beyond the EEPROM addressing space, all ‘0’ data isreturned for non-existing addresses.
• In case the reading starts at non-existing address, error
information field is returned.

Page 24
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure below defines the coding of the AS3953A reply
information field to Read EEPROM command, if command isnormally processed.
Figure 30:
Read EEPROM Reply (successful)

90h

Data

1byte

4 to 32 bytes

Figure below defines the coding of the AS3953A reply
information field to Read EEPROM command, in case of anerror.
Figure 31:
Read EEPROM Reply (error code)

Information Field

Comment61h

Error (no diagnostic)

Write EEPROM
The Write EEPROM command is used to write one EEPROM
word (32 bits). The request information field contains 6 bytes• Command code byte (04h)• Address of the word to be written• Four bytes (32 bits) of data to be written
Figure below defines coding of Write EEPROM command
information field.
Figure 32:
Write EEPROM Command04h

Address of Word to be
WrittenData

1 byte1 byte4 bytes

The AS3953A reply contains one byte informing whether thewriting of EEPROM was executed or whether there was an error.
Prior to actual programming of data in EEPROM, the control
logic checks whether there is enough power available. This isdone by performing so called power check during which adummy EEPROM programming is started. If the power check
fails, EEPROM programming is not performed and an error code
is sent. The EEPROM programming is a time consuming
operation. Therefore, if the EEPROM programming is executed,
the AS3953A reply comes after 8ms typical.

ams Datasheet[v1-05] 2019-Feb-15

Page 25
Document FeedbackAS3953A − Detailed Description

Figure below defines the coding of the AS3953A reply to Write
EEPROM command.
Figure 33:
Write EEPROM Reply

Information Field

Comment

90h

Writing is normally processed

61hWriting is not done due to coding
error (error in parity, CRC, nonexistentaddress…)

62h

Writing is not done since the word islocked64h

Writing is not done due to power
check failPassing of Block Data to Controller
After the PICC Logic has passed the anti-collision procedure andreplied with SAK on Cascade Level 2 it passes in ACTIVE(*) state.
On this level it expects that blocks received from the PCD havethe format according to ISO 14443A-4. The ISO 144443A Logic
recognizes the command by observing the first received byte.
Based on content of this byte command is either processed by
the AS3953A or the complete block data is put in the FIFO for
further processing by the controller. The figure below displays
the decision criteria.

Page 26
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure 34:
First Byte of the ISO 14443-4 PCD BlockFirst Byte
1110 0000

Comment

Action of PICC Logic
Replies with ATS (1)RATS1110 not(0000)

Block is put in FIFO

1101 xxxx

PPS

Replies with PPS response (second character is CID)(1)1100 x 010

DESELECT

Replies and go to Halt(see footnote 2)

Block is put in FIFO

1111 xxxx

WTX, S(PARAMETERS),RFU (2)Block is put in FIFO since controller needs it to
implement chaining

01xx xxxx

Proprietary command

Proprietary command is processed

00xx xxxx

I-block

10xx xxxx

R-block

1100 x not(010)

Block is put in FIFO

Note(s):
1. RATS and PPS are only processed by the AS3953A logic in case they are sent according to the ISO 14443-4 specification (RATS is firstcommand sent after entry in ACTIVE(*) state, optionally followed by PPS). In case RATS or PPS are sent once the AS3953A logic is in
PROTOCOL state the information received is saved into FIFO and not acted upon.
2. Compatible with old and new S(PARAMETERS) definition: Old: 1100 x000 is S(PARAMETERS) block according to the ISO 14443-4/AM2.
New: 1111 x000 is S(PARAMETERS) block according to the modification SC17/WG8.

As shown in Figure 34, the block data is put in the FIFO
whenever the two MSB bits are 00 or 10 and also in the casewhen the four MSB bits are 1111. Therefore the implemented
communication between the PCD and a tag implemented by
the AS3953A and a controller does not need to follow the Blocktransmission protocol defined in the ISO 14443-4.

Use of CID
As mentioned above the AS3953A decides depending oncontent of the first byte of received message to either execute
received message as a command or to put it in the FIFO. The
second byte of the message comprises a CID number which is
attributed by PCD. PCD will use CID number in case more PICCs
are brought to Level-4 of communication at the same time.
CID is only checked for messages (commands) that are executedby the AS3953A. In case CID does not match such a commandis rejected (no action is taken).
Messages that are based on first byte are put in FIFO and are
not filtered by CID. It is left to controller to check for the CID
and decide whether or not to reply (CID number is stored in the<RegisterName>RATS Register).

ams Datasheet[v1-05] 2019-Feb-15

Page 27
Document FeedbackAS3953A − Detailed Description

ISO 14443A Level-3 Protocol Mode
Level-3 Protocol mode is intended for implementation ofcustom protocols for which coding on Level-4 of ISO 14443A
communication according to Figure 34 is not appropriate. In
this mode Level-2 and Level-3 behavior of the PICC logic is
identical to ISO 14443A Level-4 Protocol mode, while on Level-4
all received data blocks are put in FIFO.
In case the configuration bit irq_l4 is set an interrupt is
automatically sent to controller once the PICC Logic enters in
ACTIVE(*) state (after sending SAK on Cascade Level 2).
In this mode the EEPROM can be accessed via SPI when the RF
field is active.

Transparent ModeIn the Transparent Mode the AS3953A logic is bypassed, AFE
input and output signals are directly available on SPI interface
pins when /SS signal is high.
• Modulator switch is controlled by pin MOSI (high is
modulator on)• Clock extractor output is sent to pin MISO
• Demodulator output is sent to pin IRQ
When /SS signal is low the SPI interface pins resume its normal
functionality.
In this mode the EEPROM can be accessed via SPI when the RF
field is active.

Page 28
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

EEPROM
The AS3953A contains an EEPROM block which can be accessedfrom both RFID and SPI interface. EEPROM contains 1024 bits
(128 bytes) organized in 32 words of 32 bits. Words in EEPROM
are number from 0 to 31(1F[hex]). Bits in a word are numberedfrom 0 to 31.
Most of the EEPROM is used to store user data (27 words – 864bits), five words are used to store some housekeeping
information (part of the AS3953A UID, configuration bits which
define the AS3953A operating options, lock bits, which control
the possibility to write EEPROM words).
Figure 35:
EEPROM Organization

Word Address[hex]

Content

AccessProperties

0

UID

RO

1

Fabrication Data

RO

2

Configuration Word

RW

3

Write Lock Word

OTP

4

Read Lock Word

OTP

5: 1F

User Data

RW

Access properties:
RO: Read only, writing to this word is not possible
RW: Reading and writing to this word is possible, writing is
disabled once the lock bit is set
OTP: One time programmable. A bit of this word once set to ‘1’
cannot be set back to ‘0’.

UID Word
The UID word contains four LSB bytes of 7 byte UID which isused during anti-collision and selection process. Every IC is
programmed by a unique number during fabrication process at
ams. For details on UID, please refer to Coding of UID.

Fabrication Data Word
This word stores some IC manufacturer data which is
programmed and locked during fabrication process at ams.

ams Datasheet[v1-05] 2019-Feb-15

Page 29
Document FeedbackAS3953A − Detailed Description

Configuration Word
The Configuration word is used to define the AS3953A
operating options. It is delivered by ams with default setting.
Figure 36:
Configuration Word (Bits 31 to 16)

Configuration
Bit

Name

Defaultb31

fsci<3>0b30

fsci<2>0b29

fsci<1>1

b28

fsci<0>0

b27

fwi<3>

0b26

fwi<2>

1

b25

fwi<1>

1

b24

fwi<0>

0b23

dr_sdr0

1: Only the same bit rate for both directions supported(TA(1) of ATS)b22

dr_picc_8

0

1: DR=8 PICC-to-PCD supported (848kbit/s) (TA(1) of
ATS)

b21

dr_picc_4

0

1: DR=4 PICC-to-PCD supported (424kbit/s) (TA(1) of
ATS)

b20

dr_picc_2

0

1: DR=2 PICC-to-PCD supported (212kbit/s) (TA(1) of
ATS)

b19

dr_pcd_8

0

1: DR=8 PCD-to-PICC supported (848kbit/s) (TA(1) of
ATS)

b18

dr_pcd_4

0

1: DR=4 PCD-to-PICC supported (424kbit/s) (TA(1) of
ATS)

b17

dr_pcd_2

0

1: DR=2 PCD-to-PICC supported (212kbit/s) (TA(1) of
ATS)

b16

nl4

0

1: SAK on Cascade Level 2 reports that tag is not ISO
14443-4 compatible

b15

nfc

0

1: SAK on Cascade Level 2 reports that tag is NFC passive
targetFunction

FSCI. Default value (2h) codes maximum size of frame
accepted by PICC to 32 bytes which is the size of the
FIFO. Please note that the AS3953A can support larger
frame sizes in case FIFO is read during the receiving.

FWI (default value (6h) defines frame waiting time of~19.3ms)

Notes:
1. Configuration bits b31 to b15 define AS3953A response to SAK and ATS command in ISO 14443A Protocol modes, while bits b14 tob0 actually change performance.
2. Incase both nl4 and nfc are set, the nl4 setting prevails.

Page 30
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure 37:
Configuration Word (Bits 14 to 0)

Configuration
Bit

Name

Default

Functionb14

irq_pu0

1: Send a power-up IRQ (after power-up initialization isfinished)b13

irq_l40

1: Send an IRQ at entry in ACTIVE(*) state (after sending
SAK on Cascade Level 2) (2)

b12

mod_1

0

b11

mod_0

0

b10

rxncrc0

1: Rx – CRC is not checked, CRC part of message is also
put in FIFO(3)

b9

rxbs

0

1: Rx – Bit stream mode, received bits are put in FIFO (noparity and CRC check) (3)b8txncrc0

1: Tx – Do not generate CRC (3)

b7

txbs

0

1: Tx – Bit stream mode, bits put in FIFO are sent withoutparity and CRC generation (3)b6fdel<1>0b5fdel<0>0b4

vreg<1>

000: ISO 14443A Level-4 Protocol mode
01: ISO 14443A Level-3 Protocol mode
10: Framing mode
11: Transparent mode

PCD-to-PICC delay adjustment (4)b3vreg<0>0b2

rreg<1>0

b1

rreg<0>

0

b0

dr8

0

00: 1.8V
10: 2.7V
01: 2.0V
11: 3.3V

External Regulated voltage (VP_
REG) setting

00: disabled
10: 50Ω
01: 100Ω
11: 25ΩExternal Regulator enable andoutput resistance setting

Reserved for internal use

Note(s):1. Configuration bits b31 to b15 define AS3953A response to SAK and ATS command in ISO 14443A Protocol mode, while bits b14 tob0 actually change performance.
2. Applicable in ISO 14443A Level-3 and Level-4 Protocol modes.
3. Applicable in ISO 14443A Level-3 Protocol mode and Framing mode, in Protocol mode applicable for frames which are put in FIFO.
4. Configuration bits fdel<1:0> are used to adjust frame delay time PCD-to-PICC. Delays caused by reader and tag resonant tanks and
AFE processing are compensated by PICC logic.Figure below defines PCD-to-PICC frame delay compensation using fdel bits.

ams Datasheet[v1-05] 2019-Feb-15

Page 31
Document FeedbackAS3953A − Detailed Description

Figure 38:
PCD-to-PICC Frame Delay Compensationfdel<1:0>

Delay [ns]Delay [Number of 13.56 MHz Periods]

00

442.5

6

01

295.0

4

10

147.5

2

11

590.0

8

OTP Words
Write and Read Lock Words are OTP (One Time Programmable).
This means that once they are set to ‘1’, they cannot be resetback to ‘0’. Since setting of OTP bits is an irreversible operation,
it is strongly recommended to perform it in controlledenvironment.

Write Lock Word
The Write Lock Word contains write lock bits. Each EEPROM
word has a corresponding lock bit in the Write Lock Word. Oncea certain lock bit is set to ‘1’, the content of corresponding word
cannot be modified any more (it becomes read only), EEPROM
Write commands issued either through PICC interface or
through SPI interface are rejected. The lock bit of a certain
number protects the word with the same number (e.g. b5 oflock word protects word 5). Since lock bits are OTP they cannot
be reset back to ‘0’ once they are set to ‘1’.Therefore once acertain word is locked it cannot be unlocked any more. The lock
bits for page 0 is “don’t care” since word 0 is always read only.
Please note that setting lock bit b2 locks the Lock Word itself,
therefore once this bit is set the lock configuration cannot be
modified any more.

Read Lock Word
The Read Lock Word contains read lock bits. Each EEPROM word
has a corresponding lock bit in the Read Lock Word. Once acertain lock bit is set to ‘1’, the content of corresponding word
cannot be read through PICC interface, it can only be readthrough SPI interface. The lock bit of a certain number protects
the word with the same number (e.g. b5 of lock word protects
word 5). Since lock bits are OTP they cannot be reset back to ‘0’
once they are set to ‘1’. Therefore once a certain word is locked
it cannot be unlocked any more. The lock bits for pages 0 to 4
are “don’t care”; these pages can be read through PICC interface
even in case their corresponding lock bits are set.

Page 32
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

SPI Interface
Communication between the AS3953A and controller is done
through a 4-wire Serial Peripheral Interface (SPI) and additional
interrupt signal. The AS3953A is an SPI slave device; it requests
controller attention by sending an interrupt (IRQ pin).
Figure 39:
SPI and Interrupt Signals

Name

SignalSignal Level

Description/SS

Digital input with pull-up

CMOS

SPI enable (active low)

MOSI

Digital input

CMOS

Serial data input

MISO

Digital output withtristate

CMOS

Serial data output

SCLK

Digital input

CMOS

Clock for serial communication

IRQ

Digital output

CMOS

Interrupt output pin

While signal /SS is high the SPI interface is in reset, while it is
low the SPI interface is enabled. It is recommended to keep
signal /SS high whenever the SPI interface is not in use. MOSI issampled at the falling edge of SCLK. All communication is donein blocks of 8 bits (bytes). First three bits of first byte transmitted
after high to low transition of /SS define SPI operation mode.
MSB bit is always transmitted first (valid for address and data).
Read and Write modes support address auto incrementing,which means that in case after the address and first data bytesome additional data bytes are sent (read), they are written to(read from) addresses incremented by ‘1’.
SPI interface supports the following modes:• Read and write of the SPI Interface internal registers• Read and write of the EEPROM• Read and write of the FIFO
• Sending direct commands
Please note that the only SPI operations, which are allowed
when logic and EEPROM are supplied from VP_SPI, are reading
and writing of EEPROM and registers (see also Power Manager).

ams Datasheet[v1-05] 2019-Feb-15

Page 33
Document FeedbackAS3953A − Detailed Description

Figure 40:
SPI Modes

MODE Pattern (communication bits)
MODE

MODE

Trailer

MODE Related Data

M2

M1

M0

C4

C3

C2

C1

C0

Register
Write

0

0

0

A4

A3

A2

A1

A0

Data byte (or more bytes incase of auto incrementing)Register
Read

0

0

1

A4

A3

A2

A1

A0

Data byte (or more bytes incase of auto incrementing)

EEPROM
Write

0

1

0

0

0

0

0

0

Word
Addressbyte

4 bytes ofword data
4 bytes ofword data (ormultiple words
in case of auto
incrementing

EEPROM
Read

0

1

1

1

1

1

1

1

Word
Address
byte

FIFO Load

1

0

0

0

0

0

0

0

One or more bytes of FIFO
data

FIFO Read

1

0

1

1

1

1

1

1

One or more bytes of FIFO
data

COMMAND
Mode

1

1

C5

C4

C3

C2

C1

C0

MISO output is usually in tristate, it is only driven when output
data is available. Due to this the MOSI and the MISO can be
externally shorted to create a bidirectional signal.
During the time the MISO output is in tristate, it is possible toswitch on a 10 kΩ pull-down by activating option bits miso_pd1
and miso_pd2 in IO Configuration Register.
Figure 41:
Signal to Controller
Separate SPI Input and Output Signals to Controller

MOSI

MOSI

MISO

Page 34
Document Feedback

MOSI

µC

AS3953A
MISO

Bi-directional Data IO Signal to Controller

AS3953A

I/O

µC

MISO

ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Writing of Data to Addressable Registers (Register
Write Mode)
Following figures show cases of writing a single byte andwriting multiple bytes with auto-incrementing address. Afterthe SPI operation mode bits, the address of register to be
written is provided. Then one or more data bytes are transferredfrom the SPI, always from the MSB to the LSB. The data byte is
written in register on falling edge of its last clock. In case thecommunication is terminated by putting /SS high before apacket of 8 bits composing one byte is sent, writing of thisregister is not performed. In case the register on the definedaddress does not exist or it is a read only register no write is
performed.
Note(s): When the AS3953A is powered via vp_SPI and not via
field; the registers and EEPROM can be readout. When CS is set
to low, after 50us of the falling edge, the Registers and the
EEPROM can be readout. Nevertheless, if there is no activity for
1ms, there is a timeout and the logic goes to sleep, hence losing
the values in the registers. (EEPROM values are retained).
Figure 42:
Writing of a Single Register

/SS

SCLK

MOSI

X

0

0

Three leading
bits indicate
Mode

0

A4

A3

A2

SCLK risingedge Data istransfered from
µC

A1

A0

D7

D6

D5

D4

SCLK fallingedge Data issampled

D3

D2

D1

X

D0

/SS risingedge signals
end of WRITE
Mode

Data is moved toAddress
A4-A0

Figure 43:
Writing of Register Data with Auto-Incrementing Address

/SS

SCLK

MOSI

X

0 0 0

A A A A A D D D D D D D D D D D D D D D D D D
4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6

Three leading
bits indicate
Mode

ams Datasheet[v1-05] 2019-Feb-15

Data is moved
to Address<A4-A0>

Data is moved toAddress<A4-A0> + 1

D D D D D D D D D D
1 0 7 6 5 4 3 2 1 0

Data is moved toAddress<A4-A0> + (n-1)

Data is moved toAddress<A4-A0> + n

X/SS raising edge
signals end of
WRITE Mode

Page 35
Document FeedbackAS3953A − Detailed Description

Reading of Data from Addressable Registers (Register
Read Mode)
After the SPI operation mode bits the address of register to beread has to be provided from the MSB to the LSB. Then one ormore data bytes are transferred to MISO output, always from
the MSB to the LSB. As in case of the write mode also the readmode supports auto-incrementing address.
MOSI is sampled at the falling edge of SCLK (like shown in thefollowing diagrams); data to be read from the AS3953A internalregister is driven to MISO pin on rising edge of SCLK and issampled by the master at the falling edge of SCLK.
In case the register on defined address does not exist all ‘0’ data
is sent to MISO.
In the following figure example for reading of single byte isgiven.
Figure 44:
Reading of a Single Register

/SS

SCLK

MOSI

X

0

0

MISO

A4

A3

A2

A1

SCLK risingedge Data istransferedfrom µC

X

A0
D
7

X

Three leading
bits indicate
Mode

Page 36
Document Feedback

1

SCLK fallingedge Data issampledD
6

SCLK risingedge Data is
moved from
Address<A4-A0>D
5D
4SCLK fallingedge Data istransfered to
µC

D
3

D
2

D
1

D
0

X

/SS risingedge signals
end of READ
Mode

ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Writing and Reading of EEPROM Through SPI
EEPROM data can be read and written also through SPI
interface. Due to possible conflict with RFID interface trying toaccess the EEPROM in ISO 14443A - level4 mode, access isgranted to SPI only in case the PICC AFE is not active.
In all other modes defined in Mode Definition Registers, the
EEPROM can be accessed via SPI when the RF field is active.
Activity of the PICC AFE can be checked by observing hf_pon
bit of RFID Status Display Register. In case PICC AFE is activatedwhile the EEPROM writing or reading operation is going on, thisoperation is interrupted, and l_ee_spi IRQ is sent.
Word Address Byte
Both EEPROM modes (Read and Write) use Word Address byte
to define the address of EEPROM word which is accessed. 7 MSB
bits of the Address Byte are used to define the address; while
the last bit is “don’t care” (utilized to synchronize EEPROM
access).
Note(s): The valid range for the Word Address byte is from 0000
000xb to 0011 111xb (EEPROM words from 00h to 1Fh).
Figure below defines the EEPROM Word Address byte.
Figure 45:
EEPROM Word Address Byte

EEPROM Word
Address

B7

B6

B5

B4

B3

B2

B1

B0

WA6

WA5

WA4

WA3

WA2

WA1

WA0

x

EEPROM Write
In order to program an EEPROM word six bytes have to be sent(mode byte, word address byte and 4 bytes of word data, all ofthem MSB first)). Actual programming of EEPROM is started withrising edge of /SS signal which terminated the EEPROM Writecommand. During EEPROM programming the controller is notallowed to start another SPI activity. Controller is informed
about the end of EEPROM programming by sending aninterrupt (an interrupt flag is set in the Auxiliary Interrupt
Register). I_eew flag is set in case EEPROM programming isnormally finished; in case of an error (writing to write protected
word, writing to non-existent address) an error flag (I_er_eew)
is set. Typical EEPROM programing time for one word is 8ms.
Note(s): Word data is sent MSB first which is opposite to RFIDEEPROM programming where LSB is sent first.

ams Datasheet[v1-05] 2019-Feb-15

Page 37
Document FeedbackAS3953A − Detailed Description

EEPROM Read
In order to read data from EEPROM first a mode byte is sent,
followed by the word address byte (MSB first). Then one or more
words of data with address auto incrementing (packets of 4
bytes) are transferred to MISO output, always from the MSB tothe LSB. MOSI is sampled at the falling edge of SCLK; data to beread from the AS3953A EEPROM is driven to MISO pin on risingedge of SCLK and is sampled by the master at the falling edgeof SCLK. In case the word on defined address does not exist all‘0’ data is sent to MISO.
Please note that SCLK frequency should not exceed 1MHz
during EEPROM Read (limited by EEPROM read access time).
Figure 46:
Reading of EEPROM Page

/SS

SCLK

MOSI

X

0 1 1 1 1

MISO

1W W W W W W W
1 1 A A A A A A A x
6 5 4 3 2 1 0

B B B B B B B B B B
3 3 2 2 2 2 2 2 2 2
1 0 9 8 7 6 5 4 3 2X

1µs minPage 38
Document FeedbackX

MSB Byte from
Address<WA6-WA0>XB B B B B B B B B B
9 8 7 6 5 4 3 2 1 0XLSB Byte from
Address<WA6-WA0>

ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Loading Transmitting Data into FIFO
Loading the transmitting data into the FIFO is similar to writing
data into an addressable registers. Difference is that in case ofloading more bytes all bytes go to the FIFO. The command mode
code 10 indicates FIFO operations. In case of loadingtransmitting data into FIFO all bits <C5 – C0> are set to ‘0’. Thena bit-stream, the data to be sent (1 to 32 bytes), can betransferred.
Figure 47 shows how to load the Transmitting data into the
FIFO.
Figure 47:
Loading of FIFO

/SS

SCLK

MOSI

X

1

0

10 patternindicates FIFO
mode

ams Datasheet[v1-05] 2019-Feb-15

0

0

0

SCLK risingedge Data istransferedfrom µC

00

SCLK fallingedge Data issampled

1 to 32
bytes

0Start ofpayload DataX

/SS rising edge
signals end of
COMMAND Mode

Page 39
Document FeedbackAS3953A − Detailed Description

Reading Received Data from FIFO
Reading received data from the FIFO is similar to reading datafrom an addressable registers. Difference is that in case ofreading more bytes they all come from the FIFO. The commandmode code 10 indicates FIFO operations. In case of reading thereceived data from the FIFO all bits <C5 – C0> are set to ‘1’. On
the following SCLK rising edges the data from FIFO appears as
in case of read data from addressable registers. In case thecommand is terminated by putting /SS high before a packet of
8 bits composing one byte is read that particular byte isconsidered read.

Direct Command Mode
Direct Command Mode has no arguments, so a single byte issent. SPI operation mode bits 11 indicate Direct Command
Mode. The following six bits define command code, sent MSB
to the LSB. The command is executed on falling edge of lastclock.
Figure 48:
Sending of a Direct Command

/SS

SCLK

MOSI

X

1

1

Two leading
ONE indicate
COMMAND
Mode

Page 40
Document Feedback

C5

C4

C3

SCLK risingedge Data istransfered from
µC

C2

C1

SCLK fallingedge Data issampled

C0

X/SS rising edge signals
start of commandexecution

ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

SPI Timing
Figure 49:
Timing Parameters

SymbolParameter

Min

Typ

Max

Units

Note

General Timing (VDD = VDD_IO = VDD_D = 3.3V, Temperature 25°C)
TSCLK=TSCLKL+TSCLKH, during
EEPROM read the SCLK period
has to be increased to 1μs (thislimitation is imposed by
EEPROM read access time)TSCLKSCLK period

200

ns

TSCLKLSCLK low80

ns

TSCLKHSCLK high

80

ns

TSSH

SPI reset (/SS high)

50

ns

TNCSL

/SS falling to SCLK
rising25

ns

First SCLK pulse

TNCSH

SCLK falling to /SSrising80

ns

Last SCLK pulse

TDIS

Data in setup time

10

ns

TDIH

Data in hold time

10

ns

Read Timing (VDD = VDD_IO = VDD_D = 3.3V, Temperature 25°C, CLOAD ≤ 50pF)
TDOD

Data out delay

20

ns

TDOHZ

Data out to highimpedance delay

20

ns

ams Datasheet[v1-05] 2019-Feb-15

Page 41
Document FeedbackAS3953A − Detailed Description

Figure 50:
SPI General Timing

/SS

...
t NCSLt SCLKHtSCLKLt NCSH

SCLK

...
tDIS

MOSI

tDIH
DATAI

...

DATAI

DATAI

...

MISO

Figure 51:
SPI Read Timing

/SS

...

SCLK

...

MOSI

...

DATAI

MISO

DATAO
t DOD

Page 42
Document Feedback

...

DATAO
tDOHZ

ams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Interrupt Interface
There are two interrupt registers implemented in the AS3953A(Main Interrupt Register and Auxiliary Interrupt Register). Main
Interrupt Register contains information about seven interrupt
sources, while one bit references to interrupt sources detailedin Auxiliary Interrupt Register.
When an interrupt condition is met the source of interrupt bit
is set in the Main Interrupt Register and the IRQ pin transitions
to high.
The controller then reads the Main Interrupt Register todistinguish between different interrupt sources. In case the bit
l_aux is pointing to the Auxiliary Interrupt Register, this register
also needs to be read. After an interrupt register (main or
auxiliary) is read its content is reset to ‘0’. Exception to this ruleis the bit pointing to auxiliary register. This bit is only cleared
when the auxiliary interrupt register is read. IRQ pin transitions
to high after the interrupt bit(s) which caused its transition tohigh has been read. Please note that there may be more than
one interrupt register bit set in case the controller did not
immediately read the Interrupt registers after the IRQ signal isset and another event causing interrupt occurred.

FIFO Water Level and FIFO Status Register
The AS3953A contains a 32 byte FIFO. In case of transmitting
the Control logic shifts data which was previously loaded by theexternal controller to the Framing Block and further to theTransmitter. During reception, the demodulated data is stored
in the FIFO and the external controller can download received
data.
Transmit and receive capability of the AS3953A is not limited
by of the FIFO size due to a FIFO water level interrupt system.
During transmission an interrupt is sent (interrupt due to FIFO
water level in the Main Interrupt Register) when the content ofdata in the FIFO which still need to be sent is lower than the
FIFO water level for transmit. The external controller can now
add more data in the FIFO. The same stands for receive mode.
In case the number of received bytes increases over the FIFO
water level for receive an interrupt is sent to inform the external
controller that data has to be downloaded from FIFO.
The external controller has to serve the FIFO faster than data istransmitted or received. A general rule is that the SCLK
frequency has to be at least double than the actual data rate inreceive or transmit.

ams Datasheet[v1-05] 2019-Feb-15

Page 43
Document FeedbackAS3953A − Detailed Description

FIFO water level is set to ¾ of FIFO for reception and to ¼ of
FIFO for transmission. This means that in case of getting aninterrupt during reception there are already 24 bytes in the
FIFO, which have to be read out to liberate space for following
data bytes. Same stands for transmission, water level interrupt
is sent when there are 8 bytes left in FIFO, therefore up to 24
additional bytes can be loaded.
During FIFO operation (FIFO read or FIFO load) the water level
detection system is blocked to avoid spurious water levelinterrupts (these might occur when for example number ofbytes has increased above water level during loading and
immediately after that dropped again below water level due toTx process which runs in parallel). Due to this the FIFO
loading/reading rate has to be higher than Tx / Rx bit rate, once
FIFO loading/reading is finished the /SS pin has to be pulled to
VDD (logic remains in FIFO load/read mode as long as /SSremains low).
In case loading/reading of FIFO is not much faster than Tx / Rx
processes low the following two cases have to be considered:• FIFO underflow IRQ is not blocked, in case loading in FIFO
is slower than transmission process the FIFO underflow
IRQ is produced.
• In case of slow FIFO loading it is possible that the content
of FIFO is increased above water level but it is below when
FIFO loading is finished. In such case a water level IRQ is
issued after termination of FIFO loading. Same stands for
FIFO reading.
• In case of slow FIFO loading it is possible that the content
of FIFO stays below water level during complete FIFO
loading operation. In such case water level IRQ is notissued after termination of FIFO loading. Same stands for
FIFO reading.
In case it is known that the receive data frame is smaller thanthe FIFO size the water level interrupt does not have to beserved. In such case the water level interrupt can be masked.
After data is received the external controller needs to know how
long the receive data string was before downloading data fromthe FIFO: This information is available in the FIFO Status Register
1 and FIFO Status Register 2 which display number of bytes in
the FIFO which were not read out.
The FIFO Status Register 2 additionally contains two bits whichindicate that the FIFO was not correctly served during reception
or transmission process (FIFO overflow and FIFO underflow).
FIFO overflow is set when too much data is written in FIFO. In
case this bit is set during reception the external controller did
not react on time on water level IRQ and more than 32 bytes
were written in the FIFO. The received data is corrupted in sucha case. During transmission this means that controller has
written more data than FIFO size. The data to be transmitted iscorrupted.

Page 44
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

FIFO underflow is set when data was read from empty FIFO. In
case this bit is set during reception the external controller readmore data than was actually received. During transmission thismeans that controller has failed to provide the quantity of data
defined in number of transmitted bytes registers on time.

ISO 14443A Frame Data in FIFO
Data in ISO 14443A frames is organized in bytes; each byte is
terminated by parity bit. Data bits in a byte are numbered fromb1 to b8 where b1 is LSB bit, LSB is sent first.
Data sent over SPI is also organized in bytes, bits in a byte aremarked D0 to D7, where D0 is LSB bit, MSB is sent first.
During receive the framing engine checks the parity bit andremoves it from data frame, only the data bytes are put in FIFO.
During transmission the process is inversed, only the data bytes
are put in FIFO, while the framing engine adds the parity bits.
The ISO 14443A data bits b1 to b8 are mapped to FIFO data bits
D0 to D7, which means that the order of receiving/transmitting
bits in a byte is inversed (the ISO 14443A bytes are sent LSB first
while the SPI bytes are sent MSB first).
The only exceptions to this rule are the Rx and Tx bit stream
modes. In these modes the meaning of byte is lost. In order tosimplify processing the order of bits is the same on ISO 14443A
and FIFO side.
This means that during reception with bit rxbs set the firstreceived bit is also the first bit read out of FIFO. In case the last
FIFO byte is not complete the bits which are not part of received
data are padded with ‘0’.
The same stands for transmission with bit txbs set: the first bit
written in FIFO is also the first bit sent.

Direct Commands
Figure 52:
List of Direct Commands

Command Byte
Value [hex]CommandC2, C3

Set Default

Puts the AS3953A in default state

C4, C5Clear

Stops all activities and clears FIFO

C8Transmit

Starts a transmit sequence

D0

Go2halt

Puts PICC logic in HALT state

ams Datasheet[v1-05] 2019-Feb-15

Comments

Page 45
Document FeedbackAS3953A − Detailed Description

Set Default
This direct command puts the AS3953A in the same state as
power-up initialization. All registers are initialized to the default
state.

Clear
This direct command stops all current activities (transmission
or reception) and clears FIFO.

Transmit
This direct command transmits the data stored in the FIFO. In
Protocol modes it is only accepted on Level-4 ofcommunication. Before triggering transmission using Transmit
command direct command Clear has to be sent, followed bydefinition of number of transmitted bytes and writing data to
be transmitted in FIFO.
Execution of this direct command is only enabled when theAS3953A antenna coil is in a PCD field (VP_INT is above HF_PON
threshold).

Go2halt
Puts PICC logic in HALT state.
Execution of this direct command is only enabled when theAS3953A antenna coil is in a PCD field (VP_INT is above HF_PON
threshold) and PICC Logic is in one of the two ISO 14443A
Protocol modes.

Registers
The 6-bit register addresses below are defined in thehexadecimal notation. The possible address range is from 00h
to 3Fh.
There are two types of registers implemented in the AS3953A:
configuration registers and display registers. The configuration
registers are used to configure the AS3953A. They can be
written and read through the SPI (RW). The display registers areread only (RO); they contain information about the AS3953A
internal state, which can be accessed through the SPI.

Page 46
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Overview of Registers
Figure 53:
List of the SPI Interface Internal Registers

Address [hex]Content

Type

00

IO Configuration Register

RW

01

Mode Definition Register

RW

02

Bit Rate Definition Register

RW

04

RFID Status Display Register

RO

05

RATS RegisterRO

08

Mask Main Interrupt Register

RW

09

Mask Auxiliary Interrupt Register

RW

0A

Main Interrupt RegisterRO

0B

Auxiliary Interrupt RegisterRO

0C

FIFO Status Register 1RO

0D

FIFO Status Register 2

RO

10

Number of Transmitted Bytes Register 1

RW

11

Number of Transmitted Bytes Register 2

RW

ams Datasheet[v1-05] 2019-Feb-15

Page 47
Document FeedbackAS3953A − Detailed Description

IO Definition Register
Figure 54:
IO Configuration Register

Address# 00h: IO Configuration

Type: RW

Bit

Name

Default

Function

Comments

7

miso_pd2x

1: Pull-down on MISO, when \SS
is low and MISO is not driven by
the AS3953A

6

miso_pd1x

1: Pull-down on MISO when \SS
is high

5

RFU

4

RFU

3

RFU

2

RFU

1

RFU

0

RFU

Note(s):1. This register is directly supplied by VP_SPI. Its initial state is unknown.

Page 48
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Mode Definition Registers
Figure 55:
Mode Definition Register

Address# 01h : Mode Definition
Bit

Name

Default

Type: RW

Function

Comments

00: ISO 14443A Level-4 Protocolmode
01: ISO 14443A Level-3 Protocolmode
10: Framing mode
11: Transparent mode

ISO mode in case of register
control;
If ISO 14443A Protocol modeis selected through registers,
logic is forced in Level-4
mode.

7

RFU

6

RFU

5

r_mod_1

See note (1)4r_mod_2

See note (1)3r_rxncrc

See note (1)1: Rx – CRC is not checked, CRC
part of message is also put in
FIFO

2

r_rxbsSee note (1)1: Rx – Bit stream mode,
received bits are put in FIFO (noparity and CRC check)1

r_txncrc

See note (1)1: Tx – Do not generate CRC

0

r_txbsSee note (1)1: Tx – Bit stream mode, bits put
in FIFO are sent without parity
and CRC generation

Applicable in ISO 14443A
Level-3 Protocol mode andFraming mode. In Protocolmode, applicable for frames
which are put in FIFO.

Note(s):1. Default value is loaded from EEPROM configuration word bits b12 to b7 during power-up initialization.

ams Datasheet[v1-05] 2019-Feb-15

Page 49
Document FeedbackAS3953A − Detailed Description

Figure 56:
Bit Rate Definition Register

Address# 02h: Bit Rate Definition

Type: RW

Bit

Name

Default

Comments

7

tx_rate30

6

tx_rate205

tx_rate1

0

4

tx_rate003

rx_rate302

rx_rate2

01

rx_rate1

00

rx_rate00

FunctionBit rate for Tx
For coding see figure below

Bit rate for Rx
For coding see figure below

Note(s):1. Default setting is set at power-up and after Set Default command. In ISO 14443A Level-4 Protocol mode, this value is rewritten after
receiving PPS command.

Page 50
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure below defines the coding of the Bit Rate.
Figure 57:
Bit Rate Coding

Rate3

Rate2

Rate1

Rate0

Bit Rate [kbit/s]

0

0

0

0

fc/128 (~106)

0

0

0

1

fc/64 (~212)

0

0

1

0

fc/32 (~424)

0

0

1

1

fc/16 (~848)

Comments

Other combinations RFU
Note(s):
1. In case a bit rate which is not supported is selected, the Tx / Rx operation is disabled.

Display Registers
Figure 58:
RFID Status Display Register

Address# 04h: RFID Status Display
Function

Type: R

Bit

Name

7

hf_pon

1: PICC AFE is active

AFE Power-on signal

6

state<2>

PICC Logic state

5

state<1>4

state<0>000: POWER OFF
001: IDLE
010: READY 011 – ACTIVE
101: HALT
110: READYX
111: ACTIVEX
100: L4

3

RFU

2

RFU

1

RFU

0

RFU

Comments

Note(s):1. The information read from this register can be false during reception (the logic state change during reception and the readout of
status can be done just at the moment when the status is changing).
2. The RFID Status Display Register is not a real register. By reading this register, controller has access to specific RFID logic internalsignals in order to observe its internal state.

ams Datasheet[v1-05] 2019-Feb-15

Page 51
Document FeedbackAS3953A − Detailed Description

Figure 59:
RATS Register

Address# 05h: RATS
Bit

Name

7

fsdi3

6

fsdi2

5

fsdi1

4

fsdi0

3

cid3

2

cid2

1

cid1

0

cid0

Type: R

Function

Comments

RATS FSDI bits

Displays maximum frame size that
PCD can handle (set by PCD in
RATS command)

RATS CID bits

Displays attributed CID number(set by PCD in RATS command)

Notes:
1. At power-up and after Set Default, content of this register is set to ‘0’.
2. The RATS Register is used only in ISO 14443A-4 Protocol mode. It contains information sent by PCD in RATS command. The register
informs the controller about maximum frame size that the PCD can handle and the attributed CID number.

Page 52
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Interrupt Register and Associated Registers
Figure 60:
Mask Main Interrupt Register

Address# 08h: Mask Main Interrupt
Bit

Name

7

M_pu

Default

Function

Comments

1

Mask power-up IRQ

This bit is set to ‘0’ during
power-up initialization in case
EEPROM configuration bit irq_pu
is set to ‘1’This bit is set to ‘0’ during
power-up initialization in case
EEPROM configuration bit irq_l4
is set to ‘1’6

M_wu_l41

Mask wake-up IRQ at entry in
ACTIVE(*) state

5

M_wu

0

Mask wake-up IRQ triggeredby sending Wake-Up
command

4

M_rxs

0

Mask IRQ due to start ofreceive

3

M_rxe

0

Mask IRQ due to end ofreceive

2

M_txe

0

Mask IRQ due to end oftransmission

1

M_wl

0

Mask IRQ due to FIFO water
level

0

RFU

0

Type: RW

Note(s):1. Default setting is set at power-up and after Set Default command.

ams Datasheet[v1-05] 2019-Feb-15

Page 53
Document FeedbackAS3953A − Detailed Description

Figure 61:
Mask Auxiliary Interrupt Register

Address# 09h: Mask Auxiliary Interrupt
Bit

Name

Default

Function

7

M_des

0

Mask IRQ due to reception of
DESELECT command6

M_er_fr0

Mask Framing error IRQ

5

M_er_par0

Mask Parity error IRQ

4

M_er_crc

0

Mask CRC error IRQ

3

M_er_fifo0

Mask FIFO error IRQ

2

M_eew

0

Mask IRQ due to successful
termination of EEPROM
programming1

M_er_eew0

Mask error during EEPROM
programming IRQ0

M_ee_spi0

Mask IRQ due to interruption of
EEPROM access due to PICC
interface activation

Type: RW
Comments

Note(s):1. Default setting is set at power-up and after Set Default command.

Page 54
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure 62:
Main Interrupt Register

Address# 0Ah: Main Interrupt
Function

Type: R

Bit

Name

Comments

7

I_pu

6

I_wu_l4

Wake-up IRQ at entry in ACTIVE(*) state

5

I_wu

Wake-up IRQ triggered by sending
Wake-Up command

4

I_rxs

IRQ due to start of receive

Applicable when receive frame isput in FIFO

3

I_rxe

IRQ due to end of receive

Applicable when receive frame isput in FIFO

2

I_txe

IRQ due to end of transmission

Applicable when data from FIFO is
sent
During receive informing that
FIFO is almost full and has to beread out.
During transmit informing that
FIFO is almost empty and that
additional data has to be send

Power-up IRQ

1

I_wl

IRQ due to FIFO water level

0

I_aux

IRQ due to event displayed in the
Auxiliary Interrupt Register

Notes:
1. At power-up and after Set Default command, content of this register is set to ‘0’.
2. After Main Interrupt Register is read, with the exception of bit0, the register content is set to ‘0’. The bit0 is set to ‘0’ only after thecorresponding interrupt register is read.

ams Datasheet[v1-05] 2019-Feb-15

Page 55
Document FeedbackAS3953A − Detailed Description

Figure 63:
Auxiliary Interrupt Register

Address# 0Bh : Auxiliary Interrupt

Type: R

Bit

Name

Function

Comments

7

I_des

IRQ due to reception of DESELECT
command6

I_er_fr

Framing error

5

I_er_parParity error

4

I_er_crc

CRC error

In case of parity or/and CRC error
the receive data is still put in FIFO,
error IRQ is additionally send.

3

I_er_fifo

FIFO error (overflow/underflow)

See FIFO Status Register 2

2

I_eew

IRQ due to successful termination of
EEPROM programming

In case EEPROM Write command
was sent through SPI

1

I_er_eew

Error during EEPROM programming(writing to write protected word,
writing to nonexistent address)

In case EEPROM Write command
was sent through SPI

0

I_ee_spi

IRQ due to interruption of EEPROM
access due to PICC interface activation

Notes:
1. At power-up and after Set Default command content of this register is set to 0.
2. After Auxiliary Interrupt Register has been read its content is set to 0.

Figure 64:
FIFO Status Register 1

Address# 0Ch: FIFO Status 1
Bit

Name

Function

Comments

Number of data bytes (binary coded) in
the FIFO which were not read out

Valid range is from 000000 to
100000000000 means that there are nodata bytes to be read out

7

RFU

6

RFU

5

fifo_b5

4

fifo_b4

3

fifo_b32

fifo_b2

1

fifo_b10

fifo_b0

Type: R

Note(s):1. At power-up and after direct commands Set Default and Clear content of this register is set to 0.

Page 56
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure 65:
FIFO Status Register 2

Address# 0Dh: FIFO Status 2
Bit

Name

7

Type: R

Function

Comments

RFU
Set when more bytes than theactual content of FIFO are read6

fifo_unf

FIFO underflow

5fifo_ovr

FIFO overflow

4

fifo_ncp

Last FIFO byte is not complete3

fifo_lb2

2

fifo_lb1

1

fifo_lb00

np_lb

Number of bits in last FIFO byte in caseit was not complete (fifo_npc=1)

MSB bits valid

Parity bit is missing in last byte

This is a framing error

Note(s):1. At power-up and after direct commands Set Default and Clear content of this register is set to 0

Definition of Number of Transmitted Bytes
Figure 66:Number of Transmitted Bytes Register 1

Address# 10h: Number of Transmitted Bytes 1
Bit

Name

7

RFU

6

RFU

5

RFU

4

Type: RW

Default

Function

Comments

ntx9

0

3

ntx8

0

Number of full bytes to betransmitted in one
command, MSB bits

Maximum supported number ofbytes is 1023

2

ntx7

0

1

ntx6

0

0

ntx5

0

Note(s):1. Default setting is set at power-up and after Set Default command.

ams Datasheet[v1-05] 2019-Feb-15

Page 57
Document FeedbackAS3953A − Detailed Description

Figure 67:
Number of Transmitted Bytes Register 2

Address# 11h: Number of Transmitted Bytes 2
Bit

Name

Default

7

ntx4

0

6

ntx3

0

5

ntx2

0

4

ntx1

0

3

ntx0

0

2

nbtx2

1

nbtx1

0

nbtx0

Type: RW

Function

Comments

Number of full bytes to betransmitted in one
command, LSB bits

Maximum supported number ofbytes is 1023

Number of bits in the splitbyte
000 means that all bytes all
full

Applicable in Level-3 Protocolmode in case configuration bit txbs
is set (bit stream Tx) Framing mode

Note(s):1. Default setting is set at power-up and after Set Default command.

Page 58
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Package Drawings & Markings

Package Drawings & Markings

The device is available in a MLPD (3mmx3mmx0.9mm) 10-pin,
WL-CSP 10-bumps package. Sorted and sawn wafers are alsoavailable.

Figure 68:
MLPD (3mmx3mmx0.9mm) 10-Pin Package Diagram

Symbol Min

RoHS

Green

A
A1
A3
L
b
D
E
e
D2
E2
aaa
bbb
ccc
ddd
eee
N

0.80
0
0.30
0.18

2.23
1.49
-

Nom

Max

0.90
0.02
0.20 REF
0.40
0.25
3.00 BSC
3.00 BSC
0.50 BSC
2.38
1.64
0.15
0.10
0.10
0.05
0.08
10

1.00
0.05
0.50
0.30

2.48
1.74
-

Note(s):
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Coplanarity applies to the exposed heat slug as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.

ams Datasheet[v1-05] 2019-Feb-15

Page 59
Document FeedbackAS3953A − Package Drawings & Markings

Figure 69:
WL-CSP 10-Bumps Package Diagram

RoHS

Green

Note(s):
1. ccc Coplanarity.
2. All dimensions are in μm.

Page 60
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Package Drawings & Markings

Figure 70:
Die 11-Pins

ams Datasheet[v1-05] 2019-Feb-15

Page 61
Document FeedbackAS3953A − Package Drawings & Markings

Figure 71:
Package Marking AS3953A-BDFT (MLPD)

AS39
53A
XXXX

Figure 72:
Package Marking AS3953A (WLCSP)

AS3953A
XXXX

Figure 73:
Package Code

XXXX
Tracecode

Page 62
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Delivery Frame Drawing

Delivery Frame Drawing
Figure 74:
Delivery Frame Drawing for ‘8” Cut Die on Foil in 12” Frame

Note(s):
1. Dimensions are in mm.

ams Datasheet[v1-05] 2019-Feb-15

Page 63
Document FeedbackAS3953A − Ordering & Contact Information

Ordering & Contact Information

The devices are available as standard products shown in figure
below.

Figure 75:
Ordering Information

Ordering CodePackage

Marking

Delivery Form

Delivery Quantity

AS3953A-BDFT

MLPD

AS3953A

Tape & Reel

6000 pcs/reelAS3953A-BDFM

MLPD

AS3953A

Mini Reels

500 pcs/reelAS3953A-BWLTWL-CSP

AS3953A

Tape & Reel

12000 pcs/reelAS3953A-BWLM

WL-CSP

AS3953A

Mini Reels

1000 pcs/reelAS3953A-BSDF

Sorted Wafer

NA

Tested Sawn Wafer
on Foil~ 10000 good die perwafer

Buy our products or get free samples online at:www.ams.com/ProductsTechnical Support is available at:www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:www.ams.com/Contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com

Page 64
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − RoHS Compliant & ams Green Statement

RoHS Compliant & ams GreenStatement

RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substancecategories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed tobe soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Greendefines that in addition to RoHS compliance, our products arefree of Bromine (Br) and Antimony (Sb) based flame retardants(Br or Sb do not exceed 0.1% by weight in homogeneousmaterial).
Important Information: The information provided in thisstatement represents ams AG knowledge and belief as of thedate that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes norepresentation or warranty as to the accuracy of suchinformation. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.

ams Datasheet[v1-05] 2019-Feb-15

Page 65
Document FeedbackAS3953A − Copyrights & Disclaimer

Copyrights & Disclaimer

Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patentindemnification provisions appearing in its General Terms ofTrade. ams AG makes no warranty, express, statutory, implied,or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use incommercial applications. Applications requiring extended
temperature range, unusual environmental requirements, orhigh reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically notrecommended without additional processing by ams AG foreach application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but notlimited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business orindirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow outof ams AG rendering of technical or other services.

Page 66
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Document Status

Document Status

Document Status

Product Preview

Preliminary Datasheet

Datasheet

Datasheet (discontinued)

ams Datasheet[v1-05] 2019-Feb-15

Product Status

Definition

Pre-Development

Information in this datasheet is based on product ideas in
the planning phase of development. All specifications aredesign goals without any warranty and are subject tochange without notice

Pre-Production

Information in this datasheet is based on products in thedesign, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject tochange without notice

Production

Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade

Discontinued

Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms ofTrade, but these products have been superseded andshould not be used for new designs

Page 67
Document FeedbackAS3953A − Revision Information

Revision Information

Changes from 1-04 (2015-Dec-28) to current revision 1-05 (2019-Feb-15)

Page

Updated figure 1

2

Updated figure 3

4

Updated figure 4

5Updated text under “Package Drawing & Markings”

59

Renamed figure 70 to “Die 11-Pins”

61

Updated figure 75

64

Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.

Page 68
Document Feedbackams Datasheet[v1-05] 2019-Feb-15

AS3953A − Content Guide

Content Guide

1
2
3
3

General Description
Key Benefits & Features
Applications
Block Diagram

4
6

Pin Assignment
Absolute Maximum Ratings

8
8
8
10

Electrical Characteristics
Operating Conditions
DC/AC Characteristics for Digital Inputs and Outputs
Electrical Specification

11
11
12
14
15
15
17
17
17
17
18
18
18
20
22
26
27
28
28
29
29
29
30
32
32
32
33
35

Detailed Description
Circuit
PICC AFE
Power Manager
ISO 14443A Framing Mode
ISO 14443A Level-4 Protocol Mode
Coding of UID
First Byte of UID (uid0)
Second Byte of UID (uid1)
Third Byte of UID (uid2)
Coding of ATQA, SAK and ATS
ATQA
SAK
ATS
Proprietary Commands
Passing of Block Data to Controller
Use of CID
ISO 14443A Level-3 Protocol Mode
Transparent Mode
EEPROMUID Word
Fabrication Data Word
Configuration Word
OTP Words
Write Lock Word
Read Lock WordSPI Interface
Writing of Data to Addressable Registers (Register Write
Mode)
Reading of Data from Addressable Registers (Register
Read Mode)
Writing and Reading of EEPROM Through SPI
Word Address Byte
Loading Transmitting Data into FIFO
Reading Received Data from FIFO
Direct Command ModeSPI Timing
Interrupt Interface
FIFO Water Level and FIFO Status Register
ISO 14443A Frame Data in FIFO

36
37
37
39
40
40
41
43
43
45

ams Datasheet[v1-05] 2019-Feb-15

Page 69
Document FeedbackAS3953A − Content Guide

Page 70
Document Feedback

45
46
46
46
46
46
47
48
49
51
53
57

Direct Commands
Set Default
Clear
Transmit
Go2halt
Registers
Overview of Registers
IO Definition Register
Mode Definition Registers
Display Registers
Interrupt Register and Associated Registers
Definition of Number of Transmitted Bytes

59
63
64
65
66
67
68

Package Drawings & Markings
Delivery Frame Drawing
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information

ams Datasheet[v1-05] 2019-Feb-15