WELCOME FROM THE MAYOR OF ORANGE COUNTY2

WELCOME FROM 67th ECTC GENERAL AND PROGRAM CHAIRSOn behalf of the Program Committee and Executive Committee, it is our pleasure to welcome you to the IEEE 67th Electronic Components
and Technology Conference (ECTC), held at the beautiful Walt Disney World Swan & Dolphin Resort, Lake Buena Vista, Florida, from May 30
to June 2, 2017. All ECTC meetings and events will be taking place in the Dolphin building of the resort. This premier international conferenceof the global microelectronic packaging industry is sponsored by the IEEE Components, Packaging, and Manufacturing Technology (CPMT)Society.
The ECTC Program Committee has selected 335 papers that will be presented in 36 oral sessions and five interactive presentation sessions,
including one interactive presentation session exclusively featuring papers by student authors. The oral sessions will feature selected papers
on key topics such as flip chip packaging, 3D/TSV technologies, wafer level packaging, design for RF performance and signal/power integrity,
thermal and mechanical modeling, optoelectronics packaging, and materials and reliability. Interactive presentation sessions will showcase papers
in a format that encourages more in-depth discussion and interaction with authors about their work. Authors from 22 countries are expected
to present their work at the 67th ECTC, covering ongoing technological challenges with established disciplines or emerging topics of interest forour industry, such as additive manufacturing, heterogeneous integration, and flexible and wearable electronics.
ECTC will also feature panel and special sessions with industry experts covering a number of important and emerging topic areas. On
Tuesday, May 30 at 10 a.m., Vikas Gupta and Pradeep Lall will chair a session on “Material and Package Reliability Needs/Challenges for Harsh
Environments.” That same day at 2 p.m., Bing Dang will chair a panel session on “Flexible Hybrid Electronics – Electronics Outside the Box,”
where a panel of experts will discuss how innovation in device integration and packaging will bring together thinned silicon die with printed
components to deliver electronics that conform to the shape of the human body and vehicles. Tuesday evening will also include the ECTC
Panel Session at 7:30 p.m. on “Panel Fan-Out Manufacturing: Why, When, and How?” chaired by CPMT President Jean Trewhella and Young
Gon Kim.
Babak Sabi, Corporate Vice President and Director of Assembly and Test Technology Development, Intel Corporation, will be giving theinvited keynote talk on “Advanced Packaging Opportunities and Challenges” at the ECTC Luncheon on Wednesday, May 31. Later that day
and continuing to build on the success of the first-ever CPMT Women’s Panel and Reception held at the 65th ECTC two years ago, this year’s
conference will also feature a panel discussion chaired by Kitty Pearsall on Wednesday, May 31, at 6:30 p.m. on “Emotional Intelligence (EI) –Link to Successful Leadership,” with participation from distinguished women leaders and technologists in our industry. All conference attendees
are invited. Also on Wednesday at 7:30 p.m., Luke England will chair the ECTC Plenary Session titled “Packaging for Autonomous Vehicle
Electronics,” featuring key technologists sharing their views on the evolutionary requirements for packaging and reliability challenges to support
widespread implementation of self-driving vehicles on the road. On Thursday, June 1 at 8 p.m., the CPMT Seminar titled “3D Printing Tools,
Technologies and Applications,” will be moderated by Venkatesh Sundaram and Yasumitsu Orii from the High-Density Substrates & Boards
Technical Committee of the CPMT Society.
Supplementing the technical program, ECTC also offers several Professional Development Courses (PDCs) and Technology Corner exhibits.
Co-located with the IEEE ITherm Conference this year, the 67th ECTC will offer 18 PDCs, organized by the PDC Committee chaired by
Kitty Pearsall. The PDCs will take place on Tuesday, May 30, and are taught by distinguished experts in their respective fields. The Technology
Corner will showcase the latest technologies and products offered by leading companies in the electronic components, materials, packaging,and services fields. More than 100 Technology Corner exhibits will be open starting at 9 a.m. on Wednesday and Thursday. ECTC also offers
attendees numerous opportunities for networking and discussion with colleagues during coffee breaks, daily luncheons, and nightly receptions.
Whether you are an engineer, a scientist, a manager, a student, or an executive, ECTC offers something unique for everyone in the
microelectronics packaging and components industry. We would like to take this opportunity to thank all our sponsors, exhibitors, authors,
speakers, PDC instructors, session chairs, program committee members, as well as all the volunteers who have helped to make the 67th ECTC
another resounding success. Once again, thank you for being a part of the 67th ECTC.

Henning BraunischGeneral ChairIntel Corporation

Mark D. Poliks
Program Chair
Binghamton University
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WELCOME FROM ECTC SPONSORING ORGANIZATIONOn behalf of CPMT, it is my great pleasure andprivilege to welcome you to the 67th ECTCin Lake Buena Vista, Florida at the spectacular
Walt Disney World Swan & Dolphin Resort!
The ECTC held its opening night 66 years ago
and it hasn’t missed a single year yet! Today,
ECTC has become the premier international
conference where professionals not only geta close-up look at every side of our industry,
but also share research and development intechnological breakthroughs across a wide
range of semiconductor packaging, electronics devices, design, materials,
manufacturing, and modeling.
The CPMT Society is proud to be a sponsor of ECTC and present these
program highlights:• Opening Day: Tuesday, May 30, in addition to the ever popular Professional
Development Courses there will be two special sessions: “Material andPackage Reliability Needs/Challenges for Harsh Environments” chaired byVikas Gupta and Pradeep Lall and “Flexible Hybrid Electronics – Electronics
Outside the Box” chaired by Bing Dang. In the evening I will co-chair the
ECTC CPMT Panel Session together with Young Gon Kim at 7:30 p.m.
on “Panel Fan-Out Manufacturing: Why, When, and How?” Tuesday’s
program highlights the breadth and depth that ECTC delivers each year.

• To encourage diversity, networking, and professional development, CPMT
will host a Women’s Panel and Reception Wednesday at 6:30 p.m. on“Emotional Intelligence – Link to Successful Leadership,” chaired by Kitty
Pearsall. All conference attendees are invited. CPMT will continue thewomen’s networking tables during the Wednesday and Thursday luncheons.
• On Thursday, June 1, CPMT will sponsor an award luncheon session topresent several prestigious IEEE and CPMT awards.
• After the traditional Gala reception on Thursday evening the CPMT HighDensity Substrates & Boards technical committee will host the seminar “3D
Printing Tools, Technologies and Applications,” moderated by Venkatesh
Sundaram and Yasumitsu Orii.
Friday will feature sessions on topics that range from the reliability of fan-out
WLP, automotive electronics and power module packaging to processing for
3D integration – all showing cutting edge advances in these critical areas.
Lastly I would like to take this opportunity to thank our dedicated volunteers
on the ECTC program committee for their hard work over the past year.
Also, appreciation goes to the session chairs, authors, speakers, and exhibitors
who are instrumental to making the 67th ECTC a great success. As always I
look forward to the impact all these technical and networking events will makeon the CPMT Society, our industry, and our members.
Here’s to four fast paced days of in-depth analysis, peer debate, and network
expansion!
Jean Trewhella, President, IEEE CPMT Society

CONFERENCE POLICIES AND GUIDELINES
BadgesConference attendees MUST wear the official conference badge to be admitted to all training courses, sessions, meals, Technology Corner exhibits andall conference sponsored social functions.
Medical Services
For emergency medical services, locate any hotel phone, whether in your room or elsewhere in the hotel, and follow its directions for emergencies.
Hotel “house” phones have been placed throughout the hotel and conference area for your convenience. If no phone can be located, please locate thenearest hotel staff or ECTC staff for assistance with your emergency. The closest available hotel staff person may be at the front desk.
Personal Property
The hotel’s safety deposit box is available for storing your valuables; particularly cash and jewelry. If there is a mini-safe in your room, you should
consider using it.
Smoking Policy
Smoking is NOT permitted in the hotel. Please follow hotel policies and signs regarding this. Smoking is also NOT permitted at any ECTC activities
including, but not limited to, functions, events, sessions, and / or seminars. Thank you for your consideration and cooperation.
Recording presentations via photos or video is prohibited.

ECTC Mobile App
ECTC is pleased to announce that a free mobile app is available again this year.
The app provides information on schedules for our technical program and PDCs as well
as exhibitors, sponsors, and general conference information and venue maps. The app
also features tools to set your schedule so you don’t miss presentations important toyou, social interaction functions, and the ability to provide ratings on presentations thatare used in selecting candidates for best paper awards. The app is available for iOS andAndroid devices from their respective app stores by searching “2017 ECTC”. Look
for login and password information on signage at ECTC! All Oral Session Paper
Ratings this year will be received only through this Mobile App.
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TABLE OF CONTENTS
Conference Policies & Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ECTC Mobile App Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ECTC Luncheon Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
iNEMI Committee Meetings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
CPMT Heterogeneous Integration Technology Roadmap Workshop . . . . . . . 5
Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PDC Instructors’ and Proctors’ Breakfast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Session Chairs & Speakers Breakfast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Speaker Prep Room . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Miscellaneous Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Luncheons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6
ECTC Special Session  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Applied Reliability Special Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CPMT Women’s Panel & Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ECTC Panel Session  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ECTC Plenary Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CPMT Seminar  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Professional Development Courses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ECTC Student Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8General Chair’s Speaker Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Technology Corner Reception  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867th ECTC Gala Reception  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Continuing Education Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2016 ECTC Best Paper Awards  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Texas Instruments Best Student Paper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Committee Meetings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Session 1: Fan-Out Packaging Process and Integration . . . . . . . . . . . . . . . . . . . . . 10

Session 2: TSV Process, Characterization and Applications . . . . . . . . . . . . . . . . . 10
Session 3: Flip Chip Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Session 4: Advanced Substrates and Integrated Devices . . . . . . . . . . . . . . . . . . . 11
Session 5: Emerging Sensors and Microsystems Packaging  . . . . . . . . . . . . . . . . . 11
Session 6: 5G, mmWave and Beyond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Session 7: Fan-Out Packaging Materials and Passives . . . . . . . . . . . . . . . . . . . . . . 12
Session 8: Singulation Process Developments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Session 9: Fine Pitch Flip Chip Process Technologies . . . . . . . . . . . . . . . . . . . . . . . 12
Session 10: Harsh Environment Interconnect Reliability . . . . . . . . . . . . . . . . . . . . 13
Session 11: Mechanical Modeling and Characterization of Interposers andInterconnections  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Session 12: Advanced Optical Components and Modules . . . . . . . . . . . . . . . . . 13
Session 13: Interconnect Advances in FO & WLP . . . . . . . . . . . . . . . . . . . . . . . . 14
Session 14: Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Session 15: Flip Chip and Embedding in Substrates . . . . . . . . . . . . . . . . . . . . . . . . 14
Session 16: 3D Materials and Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Session 17: Materials and Processes for Flexible and Wearable Devices . . . . . 15
Session 18: Warpage, Electromigration and Mechanical Characterization . . . . 15
Session 19: Recent Advances in FOWLP Technology . . . . . . . . . . . . . . . . . . . . . 16
Session 20: MEMS and Sensor Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Session 21: 3D Cu-Cu and Micro Bump Bonding Technologies . . . . . . . . . . . . . 16
Session 22: Solder Joint & Interconnect Reliability, Characterizationand Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Session 23: Additive Manufacturing and Panel-Level Packaging . . . . . . . . . . . . . . 17
Session 24: Novel Methods to Assess Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Session 25: Characterization and Reliability of Fan-Out & WLP . . . . . . . . . . . . . 18
Session 26: 3D Integration Processing and Reliability . . . . . . . . . . . . . . . . . . . . . . 18

Session 27: Advances in Thermal Compression and Wirebonding . . . . . . . . . . 18
Session 28: Advanced Materials for Reliability Improvement . . . . . . . . . . . . . . . 19
Session 29: Warpage Control and Substrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Session 30: RF Components and Module Integration . . . . . . . . . . . . . . . . . . . . . 19
Session 31: Auto Electronics Packaging and Power Modules . . . . . . . . . . . . . . . 20
Session 32: Reliability Challenges in 2.5D/3D Interconnect . . . . . . . . . . . . . . . . 20
Session 33: Advanced Bonding and Soldering Technology . . . . . . . . . . . . . . . . . 20
Session 34: Waveguide Devices and Chip-to-Fiber Packaging . . . . . . . . . . . . . . 21
Session 35: Thermomechanical and Thermal Characterization . . . . . . . . . . . . . 21
Session 36: Advances in Signal and Power Integrity . . . . . . . . . . . . . . . . . . . . . . . . 21
Session 37: Interactive Presentations 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Session 38: Interactive Presentations 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Session 39: Interactive Presentations 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Session 40: Interactive Presentations 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Session 41: Student Interactive Presentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Technology Corner Booth Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Technology Corner Exhibits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39
ECTC Executive Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ECTC Program Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-42
68th ECTC Call for Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Conference Sponsors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-45
Media Sponsors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Hotel Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
68th ECTC Dates and Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Conference at a Glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Conference organizers reserve the right to cancel or change this program without prior notice.

ECTC Luncheon
Keynote Speaker
Wednesday, May 31, 201712:00 Noon
Northern Hemisphere D-E

Advanced Packaging Opportunities
and Challenges
Presenter: Babak Sabi,
Corporate Vice President and Directorof Assembly and Test Technology
Development, Intel Corporation
Industry reliance on advanced packaging has been accelerating over the last
few years. This trend is expected to continue in the future. Heterogeneous
integration of multiple chips in a package supports Moore’s Law scaling and isdriving many challenges in package interconnect scaling, design environment,
optical integration, electrical/thermal performance, and test. Babak Sabi,
Corporate Vice President and Director of Assembly and Test Technology
Development at Intel Corporation, will address future challenges andopportunities for advanced multi-chip packaging.
Since 2009, Babak has been responsible for Intel’s packaging, assembly process,packaging materials, enabling technology, and test technology development.
Prior to leading Assembly and Test Technology Development, Babak led the
Corporate Quality Network within Intel’s Technology and Manufacturing
Group from 2002 to 2009. He also led a company-wide network of quality andreliability organizations responsible for product reliability, customer satisfaction,and quality business practices. Previously, Babak managed technology
development quality and reliability, and was responsible for silicon technology
certification, assembly, test, and board processes. Babak joined Intel in 1984,
the same year he received his Ph.D. in solid state electronics from The Ohio
State University.

IEEE CPMT Heterogeneous
Integration Technology Roadmap
Workshop
Tuesday, May 30, 2017 • 8:00 a.m. - 5:00 p.m.
Europe 4, Lobby Level
Our Industry has reinvented itself through multiple disruptive changes in technologies,
products and markets. With the rapid migration of logic, memory and applications tothe cloud infrastructures, the internet of things (IoT) to internet of everything (IOE),
smart devices every where, and autonomous automotive, the pace of innovation isincreasing to meet these challenges.
The Heterogeneous Integration Technology Roadmap (HIR), is sponsored by theIEEE CPMT Society, the Electron Devices Society (EDS), and Photonics Society
together with SEMI and ASME EPPD. It will address the future directions ofheterogeneous integration technologies and applications serving the future markets
and applications, so very crucial to our societies’ fields of interest and to our industries
and academic and research communities. In addition to HIR, two other roadmaps
are under development within IEEE: International Technology Roadmap for Wide
Band-Gap Semiconductors (ITRW) sponsored by the IEEE Power Electronics
Society (PELS), and International Technology Roadmap for Devices & Systems(IRDS), an IEEE Standards Association Industry Connection Program sponsored by
the Rebooting Computing Initiative. Collaboration is underway to harmonize acrossthe three roadmaps.
This HIR is our technology roadmap. The workshop will be held at the 2017 ECTC
conference. We invite all the ECTC participants to attend this important working
session for our profession and for our industry. The workshop is open to all.
Registration is not necessary. There is no fee for attendance.

iNEMI Technical & ResearchCommittee Meeting
Tuesday, May 30, 20179:30 a.m. - 5:30 p.m. • Oceanic 1- Lobby Level
By Invitation Only
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REGISTRATION, RECEPTIONS AND GENERAL INFORMATION
Registration

ECTC registration will be open at the ECTC Registration Desk
located in the Walt Disney World DOLPHIN Resort, ConferenceCenter, Lobby Level, outside of Australia 3.
Monday, May 29, 2017 • 3:00 p.m. – 5:00 p.m.
Tuesday, May 30, 2017 • 6:45 a.m. – 8:15 a.m.*(AM PD Courses & Special Session only)*
Tuesday, May 30, 2017 • 8:15 a.m. – 5:00 p.m.
(All conference attendees)
Wednesday, May 31, 2017 • 6:45 a.m. – 4:00 p.m.
Thursday, June 1, 2017 • 7:30 a.m. – 4:00 p.m.
Friday, June 2, 2017 • 7:30 a.m. – 12:00 Noon
*The above schedule for Tuesday will be vigorously enforced
to prevent students from being late for their courses. Please
make sure to take advantage of the 6:45am start time on
Tuesday, May 30 as registration becomes very congested prior
to the start of morning Professional Development Courses.

Door Registration Fees

Door Registration with Proceedings on USB driveIEEE Member JOINT Registration(full ECTC + ITHERM conference) . . . . . . . . . . . . . . . . . . . . . . . . $1100
IEEE Member Full Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $835
IEEE Member Speaker / Session Chair . . . . . . . . . . . . . . . . . . . . . . $730
IEEE Member One Day  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $550
IEEE Member Speaker One Day . . . . . . . . . . . . . . . . . . . . . . . . . . . $415
Exhibit Booth Attendant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $0
Non-Member JOINT Registration(full ECTC + ITHERM conference) . . . . . . . . . . . . . . . . . . . . . . . . $1310
Non-Member Full Registration  . . . . . . . . . . . . . . . . . . . . . . . . . . . $1025
Non-Member Speaker / Session Chair . . . . . . . . . . . . . . . . . . . . . $730
Non-Member One Day . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $550
Non-Member Speaker One Day  . . . . . . . . . . . . . . . . . . . . . . . . . . $415
Exhibit Booth Attendant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $0
Student . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  $315
Student Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  $315
Exhibits Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $25
Tuesday Professional Development Courses
IEEE Members and Non-Members
Tuesday AM or PM Course with Luncheon  . . . . . . . . . . . . . . . . . $500
Tuesday All-Day Courses with Luncheon  . . . . . . . . . . . . . . . . . .  $710
Tuesday Student All-Day Courses with Luncheon . . . . . . . . . . . . $130
Extra Luncheon Tickets for Each Day . . . . . . . . . . . . . . . . . . . . . . . . $65
Extra Proceedings with Registration . . . . . . . . . . . . . . . . . . . . . . .  $100

Professional Development Course Instructors Breakfast
PDC Instructors and Proctors are required to attend a briefing
breakfast.
7:00 a.m. Tuesday – PDC Instructors
and Proctor Briefing(Room Location: Asia 1, Lobby Level)

Session Chairs and Speakers Breakfast

Session Chairs and speakers are required to attend a complimentary
continental breakfast on the morning of their sessions/presentations.
At this time, presentations will be transferred to the conference PC,
which is loaded with Microsoft Windows and Office.
7:00 a.m. Wednesday thru Friday(Room Location: Northern Hemisphere E 3 & 4, 5th floor)

Speaker Prep Room

Speakers should prepare and review their digital presentations within
the allotted times below:
7:00 a.m. – 5:00 p.m., Tuesday – Friday(Room Location: Europe 2, lobby level)(It is extremely important to assure that your presentation, presentation
software and computer work flawlessly with the digital projector provided.)

MISCELLANEOUS INFORMATION
Hotel Concierge
The Hotel Concierge, located in the hotel lobby, can direct you tovarious types of entertainment or restaurants, or give suggestions forthat special night out. The Concierge can help to make your visit andconference experience a memorable one!
Message Center
Please use the hotel switchboard or the ECTC Registration Desk,
located on the lobby level in the Australia 3 Foyer, to leave and pickup
messages. The hotel phone number is +1 (407) 934-4000.
Press Room
Press Interviews will be scheduled on an as-requested basis. To
coordinate an interview with conference leadership or presenting
technical experts please contact ECTC Publicity Chair, Eric Perfecto, ateric.perfecto@globalfoundries.com or +1 (845) 475-1290.

LUNCHEONS
Tuesday, May 30, 201712:00 Noon
(Northern Hemisphere D /DE Corridor, 5th floor)
The Electronic Components
and Technology Conference
will sponsor a luncheon for all
Professional Development Courses
attendees, proctors and PDC
committee members.

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Wednesday, May 31, 201712:00 Noon
(Northern Hemisphere
D & E, 5th floor)
The Electronic Components andTechnology Conference will sponsor
a luncheon for conference attendees.
Best and Outstanding Papers will beawarded. The guest speaker will be
Babak Sabi, Corporate Vice President
and Director of Assembly and Test
Technology Development, Intel
Corporation.

Thursday, June 1, 201712:00 Noon
(Northern Hemisphere
D & E, 5th floor)
The IEEE Components, Packagingand Manufacturing Technology
Society will sponsor a luncheon for
conference attendees. The CPMT
awards will be presented.

Friday, June 2, 201712:00 Noon
(Northern Hemisphere
D & E, 5th floor)
The ECTC Program Chair willsponsor a luncheon for conference
attendees. You won’t want tomiss it!
There will be a raffle for attendees.

2017 ECTC SESSIONS & SEMINARS – Open to all conference attendees
2017 APPLIED RELIABILITY
SPECIAL SESSION

2017 CPMT WOMEN’S PANEL
AND RECEPTION

Material and Package Reliability
Needs/Challenges for Harsh
Environments

Emotional Intelligence (EI) – Link
to Successful Leadership

Tuesday, May 30, 2017
10:00 a.m. – 11:30 a.m.
Southern Hemisphere 1, 5th Floor

Chairs: Vikas Gupta - Texas Instruments, Inc.
and Pradeep Lall - Auburn University
Speakers:
1. Robert Smith, Boeing Research & Technology
2. Przemyslaw Jakub Gromala, Bosch
3. Steve Dunford, Schlumberger
4. Anton Z. Miric, Heraeus Deutschland GmbH& Co. KG
5. Nancy Stoffel, General Electric
6. Varughese Mathew, NXP Semiconductors

Wednesday, May 31, 2017
6:30 p.m. – 7:30 p.m.
Southern Hemisphere 1V, 5th Floor

Chair: Kitty Pearsall - Boss Precision, Inc.
Speakers:
1. Joanne Martin, JLM Consulting, LLC andformer Vice President, IBM Corporation
2. Rozalia Beica, Global Director New Business
Development, The Dow Chemical Company
3. Tanja Braun, Deputy Group Manager,
Fraunhofer Institute for Reliability andMicrointegration IZM

2017 ECTC SPECIAL SESSION

2017 ECTC PLENARY SESSION

Flexible Hybrid Electronics –Electronics Outside the Box

Packaging for Autonomous
Vehicle Electronics

Tuesday, May 30, 2017
2:00 p.m. – 3:30 a.m.

Wednesday, May 31, 20177:30 p.m. – 9:00 p.m.

Southern Hemisphere 1, 5th Floor

Chair: Bing Dang - IBM Corporation
Speakers:
1. Benjamin Leever, Air Force ResearchLaboratory, Materials & Manufacturing
Directorate
2. James L. Zunino, U.S. Army RDECOM
ARDEC
3. Robert Smith, Boeing Research & Technology
4. Girish Wable, Jabil
5. John Knickerbocker, IBM Corporation

Southern Hemisphere 11 & 111, 5th Floor

Chair: Luke England - GLOBALFOUNDRIES
Speakers:
1. Application and Market Projections – Venky
Sundaram,Georgia Institute of Technology
2. Powertrain Electronics – Brent Richardson,
Texas Instruments
3. Sensors – Frank Bertini, Velodyne
4. Data Processing – Dongji Xie, Nvidia
5. Wireless Communication – Raj Pendse,
Qualcomm Technologies, Inc.

2017 ECTC PANEL SESSION

2017 CPMT SEMINAR

Panel Fan-Out Manufacturing:
Why, When, and How?

3D Printing Tools, Technologies
and Applications

Tuesday, May 30, 20177:30 p.m. – 9:00 p.m.

Thursday, June 1, 2017
8:00 p.m. – 9:30 p.m.

Southern Hemisphere 11 & 111, 5th Floor

Southern Hemisphere 11 & 111, 5th Floor

Chairs: Jean Trewhella, CPMT President GLOBALFOUNDRIES and Young Gon Kim- Integrated Device Technology

Chairs: Venky Sundaram - Georgia Institute ofTechnology and Yasumitsu Orii - Nagase, Japan

Speakers:
1. Douglas Yu, TSMC
2. Tim Olson, DECA
3. Steffen Kroehnert, NANIUM
4. Rolf Aschenbrenner, IZM Fraunhofer
5. Steve Bezuk, Qualcomm Technologies, Inc.

Speakers:
1. Manos Tentzeris, Georgia Institute of Technology
2. Humair Mandavia, Zuken SOZO Center
3. Simon Fried, Nano Dimension Ltd.
4. Takeshi Sato, Fuji Machine Mfg. Co., Ltd.

7

PROFESSIONAL DEVELOPMENT COURSES • TUESDAY, MAY 30, 2017
All courses take place on the 5th floor unless otherwise noted.

8

Morning Courses 8:00 a.m. – 12:00 Noon

Afternoon Courses 1:30 p.m. – 5:30 p.m.

Northern Hemisphere E1
1. Achieving High Reliability of
Lead-Free Solder Joints – Material
Considerations
Course Leader: Ning-Cheng Lee – Indium Corporation

Northern Hemisphere E1
10. Flip Chip Technologies
Course Leaders: Eric Perfecto – GLOBALFOUNDRIES;
Shengmin Wen – Synaptics Inc.

Northern Hemisphere E2
2. Wafer Level Chip Scale Packaging
Course Leader: Luu Nguyen – Texas Instruments, Inc.

Northern Hemisphere E2
11. Package Failure Analysis – Failure
Mechanisms and Analytical Tools
Course Leaders: Rajen Dias – Amkor Technology andDeepak Goyal – Intel Corporation

Northern Hemisphere E3
3. LED Packaging, System, andReliability Considerations
Course Leader: Xuejun Fan – Lamar University

Northern Hemisphere E3
12. 3D IC Integration and 3D IC
Packaging
Course Leader: John Lau – ASM Pacific Technology Ltd.

Northern Hermisphere E4
4. Future of Device and Systems
Packaging: Strategic Technologies, Mfg.
Infrastructure, and Applications
Course Leader: Rao Tummala – Georgia Institute ofTechnology

Northern Hemisphere E4
13. Flexible Hybrid Electronics
Course Leader: Pradeep Lall – Auburn University

Americas Seminar
5. Polymers and Nanocomposites forElectronic and Photonic Packaging
Course Leaders: C. P. Wong – Georgia Institute ofTechnology; Daniel Lu – Henkel Corporation

Americas Seminar
14. Polymers for Electronic Packaging
Course Leader: Jeffrey Gotro – InnoCentrix, LLC

Southern Hemisphere 111
6. Integrated Thermal Packaging andReliability of Power Electronics
Course Leaders: Patrick McCluskey and Avram BarCohen – University of Maryland

Southern Hemisphere III
15. Emerging Interconnect and System
Integration Technologies
Course Leader: Muhannad Bakir – Georgia Institute ofTechnology

Southern Hemisphere IV
7. Fundamentals of Electrical
Design and Fabrication Processes ofInterposers, Including Their RDLs
Course Leaders: Ivan Ndip, Markus Wöhrmann, andMichael Töpper – Fraunhofer IZM

Southern Hemisphere IV
16. Package Failure Mechanisms,
Reliability, and Solutions
Course Leader: Darvin Edwards – Edwards
Enterprises

Southern Hemisphere V
8. Introduction to Mechanics Based
Quality and Reliability Assessment
Methodology
Course Leaders: Shubhada Sahasrabudhe andSandeep Sane – Intel Corporation

Southern Hemisphere V
17. Ageing of Polymers and the Influenceon Microelectronic Package Reliability
Course Leaders: Tanja Braun and Ole Hölck –Fraunhofer IZM

Southern Hemisphere I1
9. Thermo-Electric Coolers:
Characterization, Reliability, andModeling
Course Leader: Jaime Sanchez – Intel Corporation

Southern Hemisphere I1
18. Thermo-Electrical Co-Design of 3D
Chip Stacks
Course Leaders: Ankur Srivastava and Avram Bar-Cohen– University of Maryland, and Jim Wilson – Raytheon

ECTC STUDENT RECEPTION
Tuesday, May 30, 2017
5:00 p.m. - 6:00 p.m.
Host: Texas Instruments, Inc.
Outside at the Cabana Deck by Dolphin Pool;(Rain Back Up – Asia 1, Lobby Level)
ECTC welcomes our student attendees andstudent presenters who bring their research
results to our audience. The Student Reception
is an event where we provide guidance tostudents for their job search from industry
leaders. In addition to the Student Reception, in
the Student Interactive Presentation Session, we
provide one-on-one access to students and theirresearch to our audience. We encourage you
to attend the Student Interactive Presentation
Session on Friday. This reception is sponsoredby Texas Instruments.
GENERAL CHAIR’S SPEAKERS RECEPTION
Tuesday, May 30, 2017
6:00 p.m. - 7:00 p.m.
Outside at the Crescent Terrace on the Swan
Hotel side; (Rain Back Up – Northern Hemisphere
D / DE Corridor)
Invited session chairs and speakers arerequested to attend the reception.
TECHNOLOGY CORNER RECEPTION
Wednesday, May 31, 20175:30 p.m. - 6:30 p.m.
Northern Hemisphere A – C, 5th Floor
An Exhibitor Sponsored Reception will be held
in Northern Hemisphere A – C, 5th Floor. All
attendees and guests are invited.

Refreshment Breaks – 10:00 - 10:20 a.m. & 3:00 - 3:20 p.m.
Southern Hemisphere Foyer & Northern E Corridor

67th ECTC GALA RECEPTION
Thursday, June 1, 2017
6:30 p.m.
Outside at the Lake Terrace on the Swan Hotelside; (Rain Back Up – Northern Hemisphere D – E)
All badged attendees and guests are invited toattend our Gala Reception outside at the Lake
Terrace.

CONTINUING EDUCATION UNITSThe IEEE Components, Packaging, and Manufacturing
Technology Society (CPMT) has been authorized
to offer Continuing Education Units (CEUs) by theInternational Association for Continuing Education
and Training (IACET) for all Professional Development
Courses that will be presented at the 67th ECTC.
CEUs are recognized by employers for continuing
professional development as a formal measure ofparticipation and attendance in “non-credit” self-study
courses, tutorials, symposia, and workshops. Complete
details, including voluntary enrollment forms, will beavailable at the conference. All costs associated with
ECTC Professional Development Course CEUs will
be underwritten by the conference, i.e., there are no
additional costs for Professional Development Course
attendees to obtain CEU credit.

2016 ECTC BEST PAPER AWARDSBEST OF CONFERENCE PAPERS – 2016

The Electronic Components and Technology Conference is proud
to announce the “Best of Conference” papers selected from the66th ECTC proceedings. The authors of the Best Session Paper
share a check for US $2,500 and the authors of the Best Interactive
Presentation share a check for US $1,500. The winning authors also
receive a personalized plaque commemorating their achievement.

Best Session Paper

Session 2, Paper 5
High-Frequency Analysis of Embedded
Microfluidic Cooling Within 3-D ICs Using a TSV
TestbedHanju Oh, Xuchen Zhang, Gary S. May, and Muhannad S. Bakir –Georgia Institute of Technology

Best Interactive Presentation

Session 37, Paper 2
Constitutive Relations for Finite Element Modeling of
SnAgCu in Thermal Cycling –How Wrong We Were!
Thaer Alghoul, Dustin Watson, Nardeeka Adams, Saif Khasawneh, Farhan
Batieha, Chris Greene, and Peter Borgesen – Binghamton University

INTEL BEST STUDENT PAPER – 2016

The winning student receives a personalized plaque and a check for$2,500. The following paper was selected based on the Intel Best
Student Paper competition conducted at the 66th ECTC:
Session 30, Paper 2
Non-Linear Finite Element Analysis on Stacked
Die Package Subjected to Integrated Vapor-HygroThermal-Mechanical Stress
Jing Wang and Seungbae Park, Binghamton University

OUTSTANDING PAPERS – 2016

The winning authors for Conference Outstanding Session Paper
and Interactive Presentation receive a personalized plaquecommemorating their achievement and will share a check for
US $1,000.

Outstanding Session Paper

Session 13, Paper 4
Eternal Packages: Liquid Metal Flip Chip Devices
Assane Ndieguene, Pierre Albert, and Julien Sylvestre – Université deSherbrooke; Clément Fortin and Valérie Oberson – IBM Corporation

Outstanding Interactive Presentation

Session 39, Paper 16
20” x 20” Panel Size Glass IPD Interposer
Manufacturing
Yu-Hua Chen, Chun-Hsien Chien, Yu-Chung Hsieh, Wei-Ti Lin, Wen-Liang
Yeh, Chien-Chou Chen, Dyi-Chung Hu, Tzyy-Jang Tseng – Unimicron
Technology Corp.; Hobie Yun – Qualcomm Technologies, Inc.

TEXAS INSTRUMENTS OUTSTANDING STUDENT
INTERACTIVE PRESENTATION – 2016
The winning student receives a personalized plaque and a checkfor US $500. The following paper was selected based on the
Texas Instruments Outstanding Student Interactive Presentationcompetition conducted at the 66th ECTC:
Session 39, Paper 28
2D Grating Pitch Mapping of a Through Silicon Via(TSV) and Solder Ball Interconnect Region Using
Laser Diffraction
Todd Houghton, Michael Saxon, Zeming Song, Hoa Nguyen, Hanqing
Jiang, and Hongbin Yu - Arizona State University

COMMITTEE MEETINGS • ASSOCIATED COMMITTEE MEMBERS ONLY
Tuesday, May 30, 2017

Wednesday, May 31, 2017

Thursday, June 1, 2017

Friday, June 2, 20179:30 a.m. – 5:30 p.m.
INEMI Meeting
Oceanic 1, Lobby Level

7:00 a.m. – 8:00 a.m.
CPMT Materials & Processes TC
Europe 3, Lobby Level

7:00 a.m. – 8:00 a.m.
CPMT Region 8 Meeting
Europe 4, Lobby Level

7:00 a.m. – 8:00 a.m.
CPMT Nanotechnology TC
Europe 3, Lobby Level

8:00 a.m. – 5:30 p.m.
IEEE CPMT Heterogeneous
Integration Roadmap Workshop
Europe 4, Lobby Level

7:00 a.m. – 8:00 a.m.
CPMT Energy Electronics TC
Europe 4, Lobby Level

7:00 a.m. – 8:00 a.m.
CPMT RF & THz Technology TC
Europe 5, Lobby Level

7:00 a.m. – 8:00 a.m.
CPMT Thermal & Mechanical TC
Asia 1, Lobby Level

4:30 p.m. – 5:30 p.m.
CPMT Technical Committee Chairs
Europe 1, Lobby Level

7:00 a.m. – 8:00 a.m.
CPMT High Density Substrates &Boards TC
Europe 1, Lobby Level

1:30 p.m. – 4:30 p.m.
ECTC Executive Committee
Europe 3, Lobby Level

4:30 p.m. – 6:00 p.m.
CPMT Officers and Directors Meeting
Oceanic 1, Lobby Level

4:45 p.m. – 5:45 p.m.
ECTC Steering Committee
Europe 3, Lobby Level

9:00 p.m. – 10:30 p.m.
ECTC Interconnect Committee
Europe 4, Lobby Level

6:00 p.m. – 7:00 p.m.
Program Subcommittee Chairs &Assistant Chairs Reception
General Chair’s Suite(by invitation only)
9:00 p.m. – 10:30 p.m.
ECTC Opto Committee
Americas Seminar, 5th Floor

5:30 p.m. – 6:30 p.m.
ECTC 2017 Program Committee
Meeting
Southern Hemisphere 1, 5th Floor
8:00 p.m.
67th ECTC Governing/Executive
Committee Reception
General Chair’s Suite

9

Program Sessions: Wednesday, May 31, 8:00 a.m. - 11:40 a.m.
Session 1: Fan-Out Packaging Process
and Integration

Session 2: TSV Process,Characterization and Applications

Session 3: Flip Chip AssemblyCommittee:
Advanced Packaging

Committee:
Interconnections

Committee: Assembly & Manufacturing
Technology

Room: Southern Hemisphere I

Room: Southern Hemisphere II

Room: Southern Hemisphere III

Session Co-Chairs:
Beth Keser – Intel Corporation
Mike Ma – Amkor Technology Taiwan (ATT)

Session Co-Chairs:
Takafumi Fukushima – Tohoku University
Tom Gregorich – SanDisk

Session Co-Chairs:
Valerie Oberson – IBM Corporation
Mark Gerber – Advanced Semiconductor
Engineering Inc.

1. 8:00 AM - Development of a MultiProject Fan-Out Wafer Level Packaging
Platform
T. Braun, S. Raatz, U. Maass, M. van Dijk, H. Walter,
O. Hölck, K. F. Becker, M. Töpper, R. Aschenbrenner– Fraunhofer IZM; M. Wöhrmann, S. Voges, M. Huhn,
K. D. Lang – Technical University Berlin; M. Wietstruck,
R.F. Scholz, A. Mai, M. Kaynak – IHP

1. 8:00 AM - A Cost-Effective Via Last TSV
Technology Using Molten Solder Filling for
Automobile Application
Yuki Ohara, Yuki Inagaki, Masaki Matsui, and Kazushi
Asami – DENSO Corporation

1. 8:00 AM - Key Properties for Successful
Ultra Thin Die Pickup
Stefan Behler – Besi Switzerland AG; Teng Wang andArnita Podpod – IMEC

2. 8:25 AM - SLIM™, High Density Wafer
Level Fan-Out Package Development with
Submicron RDL
Youngrae Kim, JaeHun Bae, MinHwa Chang, AhRa Jo,
Ji Hyun Kim, SangEun Park, David Hiner, Mike Kelly,
and WonChul Do – Amkor Technology, Inc.

2. 8:25 AM - Accurate Depth Control of
Through-Silicon Vias by Substrate Integrated
Etch Stop Layers
Matthias Wietstruck, Steffen Marschmeyer, Marco
Lisker, Andreas Krueger, Dirk Wolansky, Philipp Kulse,
Alexander Goeritz, Thomas Voss, Andreas Mai, andMehmet Kaynak – IHP Microelectronics; Mesut Inac –Technical University Berlin

2. 8:25 AM - Fine Pitch Cu Pillar with Bondon Lead (BOL) Assembly Challenges for
Low Cost and High Performance Flip Chip
PackageNokibul Islam, Vinayak Pandey, and KyungOe Kim –STATS ChipPAC, Inc.

3. 8:50 AM - Development of Novel HighDensity System Integration Solutions in
FOWLP – Complex and Thin Wafer-Level SiP
and Wafer-Level 3D Packages
André Cardoso, Alberto Martins, Hugo Barros,
Elisabete Fernandes, Abel Janeiro, Paulo Cardoso, andLeonor Dias – NANIUM S.A.

3. 8:50 AM - Application of a Metallic Cap
Layer to Control Cu TSV Extrusion
Golareh Jalilvand, Omar Ahmed, Keenan Bosworth,Zhenlin Pei, Cullen Fitzgerald, and Tengfei Jiang –University of Central Florida

3. 8:50 AM - Improvement of C2W Collective
Bonding Reliability and UPH throughInnovations in Machine, Materials andMethods
Tomonori Nakamura, Farhan Shafiq, Tetsuya Otani,
Osamu Watanabe, Toru Maeda, and Yoshihito
Hagiwara – Shinkawa Ltd.; Keiji Honjo, Daichi Mori,
Outa Egashira, Daisuke Handa, and Tamotsu Owada– Dexerials

Refreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C10

4. 10:00 AM - Fan-Out Chip on Substrate
Device Interconnection Reliability Analysis
Ian Hu, Ying-Chih Lee, Wei-Hong Lai, Meng-Kai Shih,Chin-Li Kao, David Tarng, and Ching-Pin Hung – Advanced Semiconductor Engineering, Inc.

4. 10:00 AM - Development of TSV Electroplating Process for Via-Last Technology
Gilho Hwang and Kalaiselvan Ravanethran – Instituteof Microelectronics, A*STAR

4. 10:00 AM - Thermo-Compression Bonding
and Mass Reflow Assembly Processes of 3D
Logic Die Stacks
Pascale Gagnon, Christian Bergeron, Richard Langlois,
Stéphane Barbeau, Steve Whitehead, Katsuyuki
Sakuma, Raphael Robertazzi, Christy Tyberg,
Matthew Wordeman, and Michael Scheurmann – IBM
Corporation

5. 10:25 AM - Embedded Si Fan-Out: A
Low-Cost Wafer Level Packaging Technology
Without Molding and De-Bonding Processes
Daquan Yu, Zhenrui Huang, Zhiyi Xiao, Li Yang, andMin Xiang – Huatian Technology (Kunshan) Electronics
Co., Ltd.

5. 10:25 AM - Reliability Evaluation of
Copper (Cu) Through-Silicon Via (TSV)
Barrier and Dielectric Liner by Electrical
Characterization and Physical Failure
Analysis (PFA)
Jiawei Marvin Chan and Chuan Seng Tan – Nanyang
Technological University; Xu Cheng, Kheng Chooi Lee,and Werner Kanert – Infineon Technologies

5. 10:25 AM - Chip Shooter to Enable Fine
Pitch Flip Chip
Jie Fu, Manuel Aldrete, and Milind Shah – Qualcomm
Technologies, Inc.

6. 10:50 AM - Process Development andMaterial Characteristics of TSV-Less
Interconnection Technology for FOWLP
Wen-Wei Shen, Yu-Min Lin, Hsiang-Hung Chang, Tzu-Ying Kuo,
Huan-Chun Fu, Yuan-Chang Lee, Shu-Man Lee, Ang-Ying Lin,
Shin-Yi Huang, Tao-Chih Chang – Industrial Technology ResearchInstitute; Alvin Lee, Jay Su, Baron Huang, Dongshun Bai and Xiao
Liu – Brewer Science; Kuan-Neng Chen Chen – NCTU

6. 10:50 AM - Vertical Delay Modeling of
Copper/Carbon Nanotube Composites in a
Tapered Through Silicon Via
Madhav Rao – International Institute of Information
Technology Bangalore

6. 10:50 AM - Assembly Challenges for
75x75mm Large Body FCBGA with Emerging
High Thermal Interface Material (TIM)
Fletcher (Cheng-Piao) Tung, Max (Chin Yu) Lu,
Albert (Chang Yi) Lan, and Steward (Chi An) Pan –Siliconware Precision Industries Co., Ltd.

7. 11:15 AM - First Demonstration of Panel
Glass Fan-Out (GFO) Packages for High I/O
Density and High Frequency Multi-Chip
Integration
Tailong Shi, Vanessa Smet, Venky Sundaram, Rao Tummala,and Chintan Buch – Georgia Institute of Technology;
Yoichiro Sato – Asahi Glass Co., Ltd.; Lutz Parthier – Schott;Frank Wei and Cody Lee – Disco Corporation

7. 11:15 AM - Latency, Bandwidth andPower Benefits of the SuperCHIPS
Integration Scheme
SivaChandra Jangam, Saptadeep Pal, Adeel Bajwa,
Sudhakar Pamarti, Puneet Gupta, and SubramanianIyer – University of California, Los Angeles

7. 11:15 AM - Fine Pitch Interconnect
Rework for Lead-Free Flip Chip Packages
Malak Kanso, David Danovitch, and Elodie Nguena –Sherbrooke University; Richard Langlois and Christian
Bergeron – IBM Corporation

Program Sessions: Wednesday, May 31, 8:00 a.m. - 11:40 a.m.
Session 4: Advanced Substrates andIntegrated Devices

Session 5: Emerging Sensors andMicrosystems Packaging

Session 6: 5G, mmWave and Beyond

Committee:
Materials & Processing

Committee:
Emerging Technologies

Committee:
High-Speed, Wireless & Components

Room: Southern Hemisphere IV

Room: Southern Hemisphere V

Room: Americas Seminar

Session Co-Chairs:
Tieyu Zheng – Microsoft Corporation
Yu-Hua Chen – Unimicron

Session Co-Chairs:
Bharat Penmecha – Intel Corporation
Ramakrishna Kotlanka – Analog Devices

Session Co-Chairs:
Kemal Aygun – Intel Corporation
Lih-Tyng Hwang – National Sun Yat-Sen
University

1. 8:00 AM - A Novel Organic Substrate with
Enhanced Thermal Conductivity
Xiaoliang Zeng, Yimin Yao, Yougen Hu, Kun Guo, Jiajia
Sun, and Rong Sun – Shenzhen Institutes of Advanced
Technology; Jianbin Xu and Ching-Ping Wong –Chinese University Hong Kong

1. 8:00 AM - Phototriggerable, TransientElectronics: Component and Device
Fabrication
Gerald Gourdin, Oluwadamilola Phillips, Jared
Schwartz, Anthony Engler, and Paul Kohl – Georgia
Institute of Technology

1. 8:00 AM - First Demonstration of 28 GHz
and 39 GHz Transmission Lines and Antennas
on Glass Substrates for 5G Modules
Atom O. Watanabe, Muhammad Ali, Bijan Tehrani,
Jimmy Hester, P. Markondeya Raj, Venky Sundaram,
Manos M. Tentzeris, and Rao R. Tummala – Georgia
Institute of Technology; Hiroyuki Matsuura – NGKSpark Plug; Tomonori Ogawa – Asahi Glass Co., Ltd.

2. 8:25 AM - Infusing Inorganics into the
Subsurface of Polymer Redistribution Layer
Dielectrics for Improved Adhesion to Metals
Shreya Dwarakanath, Pulugurtha Markondeya Raj,
Collen Z. Leng, Venky Sundaram, Mark D. Losego, Rao
R Tummala, and Vanessa Smet – Georgia Institute ofTechnology

2. 8:25 AM - Novel High Temperature
Capacitive Pressure Sensor Utilizing SiC
Integrated Circuit Twin Ring Oscillators
Maximilian C. Scardelletti, Philip G. Neudeck, David J.
Spry, Roger D. Meredith, Jennifer L. Jordan, Norman
F. Prokop, Michael J. Krasowski, Glenn M. Beheim, andGary W. Hunter – NASA Glenn Research Center

2. 8:25 AM - Integrated Antenna-inPackage on Low-Cost Organic Substrate for
Millimeter-Wave Wireless Communication
Applications
Cheng-Yu Ho, Ming-Fong Jhong, Po-Chih Pan, ChenChao Wang, Chun-Yen Ting, and Chih-Yi Huang –Advanced Semiconductor Engineering, Inc.

3. 8:50 AM - Development of Solder Resist
with Improved Adhesion at HTSL (175 deg C
for 3000 Hours) and Crack resistance at TST
for Automotive IC Package
Chiho Ueta, Kazuya Okada, Toko Shiina, TadahikoHanada, and Nobuhito Itoh – Taiyo Ink Mfg. Co., Ltd.

3. 8:50 AM - An Experimental Magnesium
Ion Battery Cell Made of Flexible Materials
Todd Houghton, Gamal Eltohamy, and Hongbin Yu –Arizona State University

3. 8:50 AM - Aerosol-Jet Printed QuasiOptical Terahertz Filters
Christopher Oakley, Amanpreet Kaur, Jennifer
A. Byford, and Premjeet Chahal – Michigan State
University

Refreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C
4. 10:00 AM - Bondable Copper Substrates
With Silver Solid Solution Coatings for HighPower Electronic Applications
Yongjun Huo and Chin C. Lee – University ofCalifornia, Irvine

4. 10:00 AM - Fractal-Structured, Wearable
Soft Sensors for Control of a Robotic Wheelchair via Electrooculograms
Saswat Mishra, Yongkuk Lee, Dong Sup Lee, andWoon-Hong Yeo – Virginia Commonwealth University

4. 10:00 AM - High Performance Chip-Partitioned Millimeter Wave Passive Devices on
Smooth and Fine Pitch InFO RDL
Che-Wei Hsu, Chung-Hao Tsai, Jeng-Shien Hsieh,
Kuo-Chung Yee, Chuei-Tang Wang, and Douglas Yu –Taiwan Semiconductor Manufacturing Company, Ltd.

5. 10:25 AM - On-Chip Integrated SolidState Micro-Supercapacitor
Muhammad Amin Saleem, Rickard Andersson, andVincent Desmaris – Smoltek AB; Bo Song and C.P
Wong – Georgia Institute of Technology

5. 10:25 AM - Micro-Hermetic Packaging
Technology for Active Implantable NeuralInterfaces
Kaustubh Nagarkar, Nancy Stoffel, Eric Davis, andJeffrey Ashe – General Electric Co.; Xiaoxiao Hou andDavid Borton – Brown University

5. 10:25 AM - Directional Through Glass
Via (TGV) Antennas for Wireless Point-toPoint Interconnects in 3D Integration andPackagingSeahee Hwangbo, Hyowon An, Sheng-Po Fang, andYong-Kyu Yoon – University of Florida; Aric B. Shorey
and Abbas M. Kazmi – Corning, Inc.

6. 10:50 AM - Development of CPU Package
Embedded with Multilayer Thin Film
Capacitor for Stabilization of Power Supply
Tomoyuki Akahoshi, Daisuke Mizutani, Kei Fukui, Seigo
Yamawaki, Hidehiko Fujisaki, Manabu Watanabe, andMasateru Koide – Fujitsu Laboratories, Ltd.

6. 10:50 AM - Biopackaging of Minimally
Invasive Ultrasound Assisted Clot Lysis
Device for Stroke Treatment
Ramona Damalerio, Ming-Yuan Cheng, Weiguo
Chen, Liang Lou, and Songsong Zhang – Institute ofMicroelectronics, A*STAR

6. 10:50 AM - RF Characterization andModeling of 10 µm Fine-Pitch Cu-Pillar on a
High Density Silicon Interposer
Hélène Jacquinot, L. Arnaud, A. Garnier, F. Bana, J.C.
Barbe, and S. Cheramy – CEA-Leti

7. 11:15 AM - Panel-Based Integrated
Passive Device for RF Application
Ming Hung Chen, Tze Hsin Chiang, Jia Hao Zhang,
Hsu Chiang Shih, Sheng Chi Hsieh, Teck Chong Lee,and Chih Pin Hung – Advanced Semiconductor
Engineering, Inc.

7. 11:15 AM - A Low-Profile Flow Sensing
System for Monitoring of Cerebrospinal
Fluid with a New Ventriculoamniotic Shunt
Yanfei Chen, Stephanie Greene, Puneeth Shridhar,and Youngjae Chun – University of Pittsburgh;
Connor Howe and Woon-Hong Yeo – Virginia
Commonwealth University; Emery Stephen – MageeWomens Hospital of UPMC

7. 11:15 AM - Miniature 2.4-GHz Switched
Beamformer Module in IPD and its
Application to Very-Low-Profile 1D and 2D
Scanning Antenna Arrays
Chia-Hao Chen, Wei-Ting Fang, and Yo-Shen Lin –National Central University

11

Program Sessions: Wednesday, May 31, 1:30 p.m. - 5:10 p.m.
Session 7: Fan-Out Packaging Materials
and Passives

Session 8: Singulation Process
Developments

Session 9: Fine Pitch Flip Chip Process
Technologies

Committee:
Advanced Packaging

Committee:
Assembly & Manufacturing Technology

Committee:
Interconnections

Room: Southern Hemisphere I

Room: Southern Hemisphere III

Room: Southern Hemisphere II

Session Co-Chairs:
Luke England – GLOBALFOUNDRIESBora Baloglu – Amkor Technology

Session Co-Chairs:
Garry Cunningham – NGC
Li Jiang –Texas Instruments

Session Co-Chairs:
David Danovitch – University of Sherbrooke
Li Li – Cisco Systems, Inc.

1. 1:30 PM - Development of Liquid,
Granule, and Sheet Type Epoxy Molding
Compounds for Fan-Out Wafer Level
Package
Kenichi Ueno, Kazuhiro Dohi, Kazuyoshi Muranaka,
Akira Nakao, and Yuki Ishikawa – Sanyu Rec Co., Ltd.

1. 1:30 PM - Expanding Film and Process forHigh Efficiency 5 Sides Protection and FOWLP Fabrication
Kazutaka Honda, Naoya Suzuki, Toshihisa Nonaka,
Hirokazu Noma, and Yoshinobu Ozaki – Hitachi
Chemical Co., Ltd.

1. 1:30 PM - Cu-SnAg Interconnects
Evaluation for the Assembly at 10µm and
5µm Pitch
Divya Taneja, Marion Volpert, Gilles Lasfargues, Boris
Bouillard, Aurelie Vandeneynde, Tarik Chaira, Yannick
Goiran, David Henry, Bertrand Chambion, and Sylvie
Jarjayes – CEA-Leti; Fiqiri Hodaj – University Grenople
Alps, SIMAP

2. 1:55 PM - Ultra-Low Temperature FOWLP
Process for the Embedding of Low Thermal
Budget Sensors and Components Using SU-8
as Dielectric
Raquel Pinto, André Cardoso, Sara Ribeiro, and Carlos
Brandão – NANIUM S.A.; João Gaspar, Rizwan Gill,
Helder Fonseca, and Margaret Costa – INL; Filipe
Cardoso and Mariana Antunes – Magnomics

2. 1:55 PM - Laser Multi Beam Full Cut
Dicing of Wafer Level Chip-Scale Packages
Jeroen van Borkulo, Eric Tan, and Richard van der Stam
– ASM Pacific Technologies

2. 1:55 PM - Scaling Cu Pillars to 20µm Pitch
and Below: Strategic Role of Surface Finish
and Barrier Layers
Ting-Chia Huang, Vanessa Smet, Pulugurtha
Markondeya Raj, and Rao Tummala – Georgia Instituteof Technology; Robin Taylor, Gustavo Ramos, Rick
Nichols, Arnd Kilian, and Maja Tomic – Atotech

3. 2:20 PM - Integrated Copper Heat Slugs
and EMI Shields in Panel Laminate (LFO)
and Glass Fan-Out (GFO) Packages for HighPower RF ICs
Venky Sundaram, Bartlet Deprospo, Nahid Gezgin,
Atomu Watanabe, P. Markondeya Raj, Fuhan Liu,
Waylon Puckett, Samuel Graham, and Rao Tummala– Georgia Institute of Technology; Kyle Byers and Sean
Garrison – Honeywell

3. 2:20 PM - Plasma Dicing 300mm Framed
Wafers - Analysis of Improvement in Die
Strength and Cost Benefits for Thin Die
Singulation
Richard Barnett – SPTS Technologies, Ltd.

3. 2:20 PM - Thermal Compression Bonding:
Understanding Heat Transfer by in situ
Measurements and Modeling
Pieter Bex, Teng Wang, Vladimir Cherman, Melina
Lofrano, Giovanni Capuz, Erik Sleeckx, and Eric Beyne– IMEC

Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C

12

4. 3:30 PM - Implementation of Thick Copper Inductor Integrated into Chip Scaled
Package
S.B. Yang, C.C. Chen, W.L. Huang, T.L. Yang, G.C.
Huang, T.Y. Chou, C.C. Hsu, C.L. Chang, H.L. Huang,
C.C. Chou, C.Y. Ku, C.H. Chen, C.S. Chen, K.C. Liu,
Alex Kalnitsky, Marvin Liao – Taiwan Semiconductor
Manufacturing Company, Ltd.

4. 3:30 PM - Plasma Dicing Fully Integrated
Process-Flows Suitable for BEOL Advanced
Packaging Fabrications
Frank Wei and Tomotaka Tabuchi – DISCO
Corporation; Thierry Lazerand, Christopher Johnston,
Kenneth Mackenzie, and Marco Notarianni – PlasmaTherm, LLC

4. 3:30 PM - A Study on Nano-Sized Silica
Content and Size Effect in Non Conductive
Films (NCFs) for Ultra Fine-Pitch Cu-Pillar/
Sn-Ag Micro-Bump Interconnection
HanMin Lee, SeYong Lee, SeMin Cho, YoungHyun
Yu, Jong-Ho Park, and Kyung-Wook Paik – Korea
Advanced Institute of Science and Technology

5. 3:55 PM - Passive Devices Fabrication
on FOWLP and Characterization for RF
Applications
Chunmei Wang, King Jien Chui, Xiangyu Wang,
Teck Guan Lim, and Mingbin Yu – Institute ofMicroelectronics, A*STAR; Gilbert See and Gu Yu –Applied Materials

5. 3:55 PM - Stealth Dicing Challenges for
MEMS Wafer Applications
Daniel Ismael Cereno, and Sunil Wickramanayaka –Institute of Microelectronics, A*STAR

5. 3:55 PM - Accelerated SLID Bonding
for Fine-Pitch Interconnects with Porous
Microstructure
Jörg Meyer, Iuliana Panchenko, Steffen Bickel, and Laura
Wambera – Technical University Dresden; Wieland
Wahrmund and M. Jürgen Wolf – Fraunhofer IZM,
ASSID

6. 4:20 PM - Compression Molding
Encapsulants for Wafer-Level Embedded
Active Devices: Wafer Warpage Control by
Epoxy Molding Compounds
Kihyeok Kwon, Yoonman Lee, Junghwa Kim, Joo
Young Chung, Kyunghag Park, Yong-Yeop Kim,
Donghwan Lee, and Sang Kyun Kim – Samsung SDI

6. 4:20 PM - A Novel Pick-Up and Place
Process for FO-WLP Using Tape Expansion
Machine Device
Shinya Takyu, Naoya Okamoto, Tadatomo Yamada,Toshiaki Menjo, and Masatomo Nakamura – LINTEC
Corporation

6. 4:20 PM - Low Temperature Ni/Sn/Ni
Transient Liquid Phase Bonding for High
Temperature Packaging Application by
Imposing Temperature GradientYi Zhong, Wei Dong, Mingliang Huang, Haitao Ma,
and Ning Zhao – Dalian University of Technology; C.P.
Wong – Georgia Institute of Technology

7. 4:45 PM - Additive Manufacturing ofMagnetic Components for Heterogenous
Integration
Yi Yan, Lanbing Liu, Guo-Quan Lu, and Chao Ding
– Virginia Tech; Luu Nguyen and Jim Moss – Texas
Instruments, Inc.; Yunhui Mei – Tianjin University

7. 4:45 PM - Investigation of Production
Quality and Reliability Risk of ELK Wafer
WLCSP Package
Pei-Haw Tsao, T.M. Chen, Y. L. Kuo, C. M. Kuo, Steven
Hsu, M. J. Lii, and L. H. Chu – Taiwan Semiconductor
Manufacturing Company, Ltd.

7. 4:45 PM - Interfacial Reaction andMicrostructural Evolution between Au-Ge
Solder and Electroless Ni-W-P Metallisation inHigh Temperature Electronics Interconnects
Li Liu – Wuhan University of Technology, Wuhan, China; Jinzi Cui– Auburn University; Jing Wang – Wolfson School of Mechanical,
Electrical and Manufacturing Engineering, Loughborough University;
Zhaoxia Zhou and Changqing Liu – Loughborough University

Program Sessions: Wednesday, May 31, 1:30 p.m. - 5:10 p.m.
Session 10: Harsh Environment
Interconnect Reliability

Session 11: Mechanical Modeling andCharacterization of Interposers and Interconnections

Session 12: Advanced Optical
Components and Modules

Committee:
Applied Reliability

Committee: Thermal/Mechanical
Simulation & Characterization

Committee:
Optoelectronics

Room: Southern Hemisphere IV

Room: Southern Hemisphere V

Room: Americas Seminar

Session Co-Chairs:
Tim Chaudhry – Amkor Technology, Inc.
René Rongen – NXP Semiconductors

Session Co-Chairs:
Kuo-Ning Chiang – National Tsinghua
University
Tony Mak – Wentworth Institute of Technology

Session Co-Chairs:
Stephane Bernabe – CEA Leti
Shogo Ura – Kyoto Institute of Technology

1. 1:30 PM - Effect of Processing Variableson the Mechanical Reliability of Copper
Pillar SnAg/Cu Solder Joints
Mohammed Genanu, Babak Arfaei, and Eric Cotts– Binghamton University; Francis Mutuku and James
Wilcox – Universal Instruments; Eric Perfecto –GLOBALFOUNDRIES

1. 1:30 PM - Hybrid Approach to Conduct
Failure Prognostics of Automotive Electronic
Control Unit
Bulong Wu, Dae-Suk Kim, and Bongtae Han –University of Maryland; Alicja Palczynska, Przemyslaw
Jakub Gromala, and Alexandru Prisacaru – Robert
Bosch GmbH

1. 1:30 PM - Low Loss Channel-Shuffling
Polymer Waveguides: Design and Fabrication
Kohei Abe, Yutaro Oizumi, Yoichi Taira, and Takaaki
Ishigure – Keio University

2. 1:55 PM - Visualization of Microstructural
Evolution in Lead Free Solders During
Isothermal Aging Using Time-Lapse Imagery
Sudan Ahmed, Nianjun Fu, Jeffrey Suhling, and Pradeep
Lall – Auburn University

2. 1:55 PM - Semiconductor Power Package
Bonding Interconnects Reliability Simulation
under Transient Thermal Loads
Qiuxiao Qian, Roger Stout, and Yong Liu – ON
Semiconductor

2. 1:55 PM - A Very High-Density On-Board
Optical Module Realizing >1.3 Tb/s/inch²
Kazuya Nagashima, Toshinori Uemura, Atsushi Izawa,
Yozo Ishikawa, and Hideyuki Nasu – Furukawa Electric

3. 2:20 PM - Failure Mechanism and Kinetics
Studies of Electroless Ni-P Dissolution in PbFree Solder Joints under Electromigration
Pilin Liu, Alan Overson, Chaitra Chavali, and Deepak
Goyal – Intel Corporation

3. 2:20 PM - Correlation of Dielectric Film
Flex Fatigue Resistance and Package Resin
Cracking Failure
Joseph Ross, Nicolas Pizzuti, Steven Ostrander, andKamal Sikka – IBM Corporation

3. 2:20 PM - Design and Demonstration ofa Photonic Integrated Glass Interposer for
Mid-Board Optical Engines
Marcel Neitz and Sebastian Marx – Technical University
Berlin; Markus Wöhrmann and Henning Schröder –Fraunhofer IZM; Ruiyong Zhang and Mohamed Fikry– Amphenol FCI

Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C
4. 3:30 PM - Pad Cratering Based Failure
Criterion for the Life Prediction of Board
Level Cyclic Bending Test
Qiming Zhang, Jeffery C. C. Lo, and Shi-Wei Ricky Lee–Hong Kong University of Science and Technology

4. 3:30 PM - Development of FE Models andMeasurement of Internal Deformations ofFuze Electronics Using X-Ray MicroCT Datawith Digital Volume Correlation
Pradeep Lall and Nakul Kothari – Auburn University;
John Deep and Jason Foley – US Air Force ResearchLabs; Ryan Lowe – ARA Associates

4. 3:30 PM - Optoelectronic Chip Assembly
Process of Optical MCM
Masao Tokunari, Koji Masuda, Hsiang-Han Hsu,
Takashi Hisada, Shigeru Nakagawa, Richard Langlois,
Patrick Jacques, and Paul Fortier – IBM Corporation

5. 3:55 PM - Road Test and Reliability
Analysis of Electronic Modules
Dongji Xie, Joe Hai, Jack Huang, Manthos Economou,
and Zhongming Wu – Nvidia Corporation

5. 3:55 PM - Dynamic Stress Measurementsof Electronic Devices During Active
Operation
Markus Feisst, Eike Moeller, and Jürgen Wilde –University of Freiburg, IMTEK

5. 3:55 PM - 3D Packaging of Embedded
Opto-Electronic Die and CMOS IC Based on
Wet Etched Silicon Interposer
Chenhui Li, Barry Smalbrugge, Teng Li, Ripalta Stabile,and Oded Raz – Eindhoven University of Technology

6. 4:20 PM - Effects of the Inter-Metallic
Compounds Microstructure on ElectroMigration of Sn-Bi Solder System
Kei Murayama, Mitsuhiro Aizawa, and Takashi Kurihara– Shinko Electric Industries Company, Ltd.

6. 4:20 PM - Smart Packaging: A MicroSensor Array Integrated to a Flip-Chip
Package to Investigate the Effect of
Humidity in Microelectronic Packages
Aurore Quelennec, Umar Shafique, and Dominique
Drouin – Université de Sherbrooke; Éric Duchesne– IBM Corporation; Hélène Frémont – Université deBordeaux

6. 4:20 PM - Self-Alignment with Copper
Pillars Micro-Bumps for Positioning Optical
Devices at Submicronic Accuracy
Yézouma Dieudonné Zonou, Stéphane Bernabe,
Daivid Fowler, Mireille Francou, and Olivier Castany– CEA-Leti; Philippe Arguel, – Laboratory for Analysis
and Architecture of Systems, CNRS

7. 4:45 PM - Effect of Board and Package
Type on Board Level Vibration Using
Vibrational Spectrum Analysis
Jeroen Jalink, Romuald Roucou, Jeroen Zaal, Joachim
Lesventes, and Rene Rongen – NXP Semiconductors

7. 4:45 PM - Nondestructive, In Situ
Mapping of Die Surface Displacements in
Encapsulated IC Chip Packages Using X-Ray
Diffraction Imaging Techniques
Nima E. Gorji, Rajani K. Vijayaraghavan, and Patrick J.
McNally – Dublin City University; Brian K. Tanner –Durham University; Andreas N. Danilewsky – Albert
Ludwigs University

7. 4:45 PM - Thermal Management
Characterization of Microassemblied HighPower Distributed-Feedback Broad Area
Lasers Emitting at 975nm
Roberto Mostallino, Michel Garcia, Alexandre Larrue,
Yannick Robert, Eric Vinet, Michel Lecomte, Olivier
Parillaud, and Michel Krakowski – III-V Lab; Yannick
Deshayes and Laurent Bechou – University of Bordeaux13Program Sessions: Thursday, June 1, 8:00 a.m. - 11:40 a.m.
Session 13: Interconnect Advances in
FO & WLP

Session 14: Heterogeneous Integration

Session 15: Flip Chip and Embedding
in Substrates

Committee:
Interconnections

Committee: Advanced Packaging Joint with
Assembly & Manufacturing Technology

Committee:
Advanced Packaging

Room: Southern Hemisphere II

Room: Southern Hemisphere III

Room: Southern Hemisphere I

Session Co-Chairs:
Lei Shan – IBM Corporation
Dingyou Zhang – Qualcomm Technologies, Inc.

Session Co-Chairs:
John Knickerbocker – IBM Corporation
Chunho Kim – Medtronic Corporation

Session Co-Chairs:
Markus Leitgeb – AT&S
Steffen Kroehnert – Nanium S.A.

1. 8:00 AM - SLIM™ Advanced Fan-Out
Packaging for High Performance Multi-Die
SolutionsDavid Hiner, Moh Kolbehdari, Michael Kelly, Young
Rae Kim, Won Chul Do, JaeHun Bae, MinHwa Chang,and AhRa Jo – Amkor Technology, Inc.

1. 8:00 AM - A Versatile Platform Towards
High Reliability Compact Package for Digital
Chips
Christine Ferrandon, Laetitia Castagné, Brahim Kholti,
Guillaume Waltener, Vincent Puyal, Romain Lemaire,
Jean-Charles Souriau, and Gilles Simon – CEA-Leti;
Lionel Toffanin – ST Microelectronics; T. Lacrevaz –IMEP-LAHC Laboratory; J. P. Peltier – e2v

1. 8:00 AM - Solder Mobility for High-Yield
Self-Aligned Flip-Chip Assembly
Yves Martin, Swetha Kamlapurkar, Jae-Woong
Nah, Nathan Marchack, and Tymon Barwicz – IBM
Corporation

2. 8:25 AM - 28nm CPI (Chip/Package
Interactions) in Large Size eWLB (Embedded
Wafer Level BGA) Fan-Out Wafer Level
Packages
Kang Chen, Linda Chua, Won Kyung Choi, Seng Guan
Chow, and Seung Wook Yoon – STATS ChipPAC, Inc.

2. 8:25 AM - Glass Based 3D-IPD Integrated
RF ASIC in WLCSPTeck Chong Lee, Yung-Shun Chang, Sheng-Chi
Hsieh, Pao-Nan Lee, Yu-Chang Hsieh, and CheMing Hsu – Advanced Semiconductor Engineering,
Inc.; Long-Ching Wang and Lijuan Zhang – Marvell
Semiconductor

2. 8:25 AM - Large Scale Cryogenic
Integration Approach for Superconducting
High-Performance Computing
Rabindra Das, Vladimir Bolkhovsky, Sergey Tolpygo,
Pascale Gouker, Leonard Johnson, Eric Dauler, andMark Gouker – MIT Lincoln Laboratory

3. 8:50 AM - Multi DOE Study on 28nm
(RF) WLP Package to Investigate BLR
Performance of Large WLP Die with 0.35mm
Ball Pitch Array
Rey Alvarado, Beth Keser, Tong Cui, Ahmer Syed,
Steven Xu, and Brian Roggeman – Qualcomm
Technologies, Inc.

3. 8:50 AM - Breakthrough in Cu to Cu
Pillar-Concave Bonding on Silicon Substratewith Polymer Layer for Advanced Packaging,
3D, and Heterogeneous Integration
Yu-Tao Yang, Ting-Yang Yu, Shu-Chiao Kuo, andKuan-Neng Chen – National Chiao Tung University;
Tai-Yuan Huang, Kai-Ming Yang, Cheng-Ta Ko, Yu-Hua
Chen, and Tzyy-Jang Tseng – Unimicron

3. 8:50 AM - Dense and Highly Elastic
Compressible MicroInterconnects (CMIs) forElectronic Microsystems
Paul K. Jo, Muneeb Zia, Joe L. Gonzalez, and Muhannad
S. Bakir – Georgia Institute of Technology

Refreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C
4. 10:00 AM - Heterogeneous Interposer
Based Integration of Chips with Copper
Pillars and C4 Balls to Achieve High Speed
Interfaces for ADC Application
Andy Heinig, Michael Dittrich, Fabian Hopsch, andRobert Trieb – Fraunhofer IIS/EAS

4. 10:00 AM - New Resin Materials for HighPower Embedding
Michael Guyenot, Christiane Mager, and Roumen
Ratchev – Robert Bosch GmbH; Thomas Gottwald
and A. Khoshamouz – Schweizer Electronic; Sascha
Kreuer – Isola

5. 10:25 AM - A Novel 3D IC Wafer-Level
Package for New Wave MEMS
Che-Hau Huang, Ying-Te Ou, and Yung-Hui Wang –Advanced Semiconductor Engineering, Inc; Sebastian
Schuler-Wakins, Ralf Reichenbach, David Polityko, andUwe Hansen – Robert Bosch GmbH5. 10:25 AM - “FlexTrate®” - Scaled
Heterogeneous Integration on Flexible
Biocompatible Substrates Using FOWLPTak Fukushima, Arsalan Alam, Saptadeep Pal, Zhe
Wan, Siva Jangam, Goutham Ezhilarasu, Adeel Bajwa,
and Subramanian Iyer – University of California, Los
Angeles

5. 10:25 AM - Advanced Embedded
Packaging for Power Devices
Naoki Hayashi, Miki Nakashima, Hiroshi Demachi,
Shingo Nakamura, Tomoshige Chikai, Yukari Imaizumi,
Fumihiko Taniguchi, Yoshihiko Ikemoto, Mitsuru Ooida,
and Akito Yoshida – J-Devices Corporation

6. 10:50 AM - First Demonstration of
Photoresist Cleaning for Fine Line RDL
Yield Enhancement by an Innovative Ozone
Treatment Process for Panel Fan-Out andInterposers
Atul Gupta, Eric Snyder, Christiane Gottschalk, James Gunn, andKevin Wenzel – MKS Instruments; Hao Lu, Yuya Suzuki, Venky
Sundaram, and Rao Tummala – Georgia Institute of Technology

6. 10:50 AM - Metal Contamination
Evaluation of Via-Last Cu TSV Process Using
Notchless Si Etching and Wet Cleaning of theFirst Metal Layer
Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi,
and Masahiro Aoyagi – Advanced Industrial Scienceand Technology; Hidekazu Kikuchi, Azusa Yanagisawa,
and Akio Nakamura – LAPIS Semiconductor

6. 10:50 AM - Development of Large-Size
CPU Package Structure Using Embedded
Thin Film Capacitor Package Substrate
Masateru Koide, Kenji Fukuzono, and Manabu Watanabe –Fujitsu Advanced Technologies Limited; Daisuke Mizutani,
Tomoyuki Akahoshi, Seigo Yamawaki, and Kei Fukui– Fujitsu Laboratories, Ltd.; Hedehiko Fujisaki – Fujitsu
Interconnect Technologies Ltd.

7. 11:15 AM - Process and Reliability ofLarge Fan-Out Wafer Level Package Based
Package-on-Package
Srinivasa Rao Vempati, David Ho, Mian Zhi Ding,
Ser Choong Chong, Sharon Lim PS, Tai Chong
Chai, Daniel Ismael, and Ye Yong Liang – Institute ofMicroelectronics, A*STAR

7. 11:15 AM - A Highly-Miniaturized System
Integration Approach for an IOT ContactLess Power Module
Srikrishna Sitaraman, Shaoyong Wang, Tony Contreras,
Jian Wang, Mingjie Fan, Yuming Song, and Terry Bowen– Tyco Electronics

7. 11:15 AM - Laminate Chip Embedding
Technology - Impact of Material Choice andProcessing for Very Thin Die Packaging
Angela Kessler, Andreas Munding, Thorsten Scharf,
Boris Plikat, and Klaus Pressel – Infineon Technologies

4. 10:00 AM - Warpage and Thermal
Characterization of Fan-Out Wafer-Level
PackagingJohn Lau, Ming Li, DeWen Tian, Nelson Fan, Eric Kuah, Wu Kai, Margie
Li, JiYuen Hao, Ken Cheung – ASM Pacific Technology Ltd.; Zhang Li andKim Hwee Tan – Jiangyin Changdian Advanced Packaging Co., Ltd.; Rozalia
Beica – Dow Chemical; Yu-Hua Chen – Unimicron; Sze Pei Lim and Ning
Cheng Lee – Indium Corporation, Koh Sau Wee, Jiang Ran and Cao Xi –Huawei Technologies Co. Ltd.

14

Program Sessions: Thursday, June 1, 8:00 a.m. - 11:40 a.m.
Session 16: 3D Materials andProcessing

Session 17: Materials and Processes
for Flexible and Wearable Devices

Session 18: Warpage, Electromigrationand Mechanical Characterization

Committee:
Materials & Processing

Committee:
Emerging Technologies

Committee: Thermal/Mechanical
Simulation & Characterization

Room: Northern Hemisphere IV

Room: Southern Hemisphere V

Room: Americas Seminar

Session Co-Chairs:
Myung Jin Yim – Intel Corporation
Mikel Miller – Draper Laboratory

Session Co-Chairs:
C. S. Premachandran – GLOBALFOUNDRIESChelakara Vaidyanathan – Ciena Corporation

Session Co-Chairs:
Xuejun Fan – Lamar University
Jiantao Zheng – Qualcomm Technologies, Inc.

1. 8:00 AM - High Productive 3D Stacking
Process
Kazutaka Honda, Hirokazu Noma, Hitoshi Onozeki,
Shizu Fukuzumi, and Yoshinobu Ozaki – Hitachi
Chemical Co., Ltd.

1. 8:00 AM - Nanoparticle Based Printed
Sensors on Paper for Detecting Chemical
Species
Jack Lombardi, Mark Poliks, Wei Zhao, Shan Yan, Ning
Kang, Jing Li, Jin Luo, Chuan-Jian Zhong, Ziang Pan,
Madina L. Zabran, Sandeep S. Mittal, Kanad Ghose –State University of New York at Binghamton; Mihdhar
Almihdhar and Benjamin Hsiao – Stony Brook University

1. 8:00 AM - Model for Interaction of EMC
Formulation with Operating Current andReliability of Cu-Al Wirebonds Operating inHarsh Environments
Pradeep Lall, Shantanu Deshpande, and Yihua Luo –Auburn University; Luu Nguyen – Texas Instruments,
Inc.

2. 8:25 AM - Direct Bonding and Debonding
Approach of Ultrathin Glass Substrates forHigh Temperature Devices
Messaoud Bedjaoui and Sylvain Poulet – CEA-Leti

2. 8:25 AM - Phototriggerable TransientElectronics: Materials and Concepts
Oluwadamilola Phillips, Jared Schwartz, AnthonyEngler, Gerald Gourdin, and Paul Kohl – Georgia
Institute of Technology

2. 8:25 AM - Interfacial Delamanination of
Mold Compound in Fan-Out Packages
V.N.N. Trilochan Rambhatla, David Samet, P
Markondeya Raj, Satomi Kawamoto,, Rao R. Tummala,and Suresh K. Sitaraman – Georgia Institute ofTechnology

3. 8:50 AM - Wafer-Level Vacuum-Packaged
Piezoelectric Energy Harvesters Utilizing
Two-Step Three-Wafer Bonding
Nan Wang, Chengliang Sun, Li Yan Siow, Hongmiao
Ji, Darmayuda I Made, Peter Chang, Qingxin Zhang,
Yuandong Gu, and Lionel You Liang Wong – Instituteof Microelectronics, A*STAR

3. 8:50 AM - Synthesis of a Soft
Nanocomposite for Flexible, Wearable
Bioelectronics
Fabrice Fondjo and Jong-Hoon Kim – Washington
State University; Dong Sup Lee, Connor Howe, andWoon-Hong Yeo – Virginia Commonwealth University

3. 8:50 AM - Non-Linear Viscoelastic
Modeling of Epoxy Based Molding
Compound for Large Deformations
Encountered in Power Modules
Przemyslaw Gromala, Alexandru Prisacaru, andMateus Jeronimo – Robert Bosch GmbH; Hyun-Seop
Lee, Yong Sun, and Bongtae Han – University of
MarylandRefreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C
4. 10:00 AM - Advances in Thin Wafer
Debonding and Ultrathin 28-nm FinFET
Substrate Transfer
Alain Phommahaxay, Anne Jourdain, Goedele Potoms,
Greet Verbinnen, Erik Sleeckx, Eric Beyne, and Gerald
Beyer – IMEC; Alice Guerrero, Dongshun Bai, Kim
Yess, and Kim Arnold – Brewer Science

4. 10:00 AM - BiCMOS Integrated Microfluidic Packaging by Wafer Bonding for Labon-Chip Applications
Mesut Inac – Technical University Berlin; Arnaud
Pothier - Univeristy of Limoges/CNRS; Matthias
Wietstruck, Alexander Göritz, Barbaros Cetindogan,
Canan Baristiran-Kaynak, Steffen Marschmeyer,
Mirko Fraschke, Thomas Voss, Andreas Mai, Mehmet
Kaynak, and Cristiano Palego – IHP Microelectronics

4. 10:00 AM - Warpage Modeling and Characterization of the Viscoelastic Relaxation
for Cured Molding Process in Fan-Out Packages
Shu-Shen Yeh, Po-Yao Lin, Kuang-Chun Lee, JinHua Wang, Wen-Yi Lin, Ming-Chih Yew, Po-Chen
Lai, Shyue-Ter Leu, and Shin-Puu Jeng – Taiwan
Semiconductor Manufacturing Company, Ltd.

5. 10:25 AM - Thermally Reversible andCrosslinked Polyurethane Based on DielsAlder Chemistry for Ultrathin Wafer
Temporary Bonding at Low-Temperature
Jinhui Li, Qiang Liu, Guoping Zhang, and Rong Sun– Shenzhen Institutes of Advanced Technology;
Chingping Wong – Chinese University of Hong Kong;
Bin Zhao – Shanghai Micro Electronics Equipment

5. 10:25 AM - Enhanced Thermal
Performance Polyimide (PI) for Improved
Flexible Electronic Application
Manuela Loeblein, Theo Levert, Emiliano Pallecchi,
Siu Hon Tsang, and Edwin Hang Tong Teo – Nanyang
Technological University

5. 10:25 AM - Wafer Form Warpage
Characterization Based on Composite Factors
Including Passivation Films, Re-Distribution
Layers, Epoxy Molding Compound Utilized in
Innovative Fan-Out Package
Cheng-Hsiang Liu, Lu-Yi Chen, Chang-Lun Lu, HungChi Chen, Cheng-Yi Chen, and Shou-Chi Chang –Siliconware Precision Industries Co., Ltd.

6. 10:50 AM - Synchrotron X-Ray
Microdiffraction Investigation of Scaling
Effects on Plasticity and the Correlation to
TSV Extrusion
Laura Spinella, Jang-hi Im, and Paul Ho – Universityof Texas, Austin; Tengfei Jiang – University of Central
Florida; Nobumichi Tamura – Lawrence Berkeley
National Laboratory

6. 10:50 AM - Nanolaminated CoNiFe
Cores with Dip-Coated Fluoroacrylic
Polymer Interlamination Insulation:
Fabrication, Electrical Characterization, andPerformance Reliability
Minsoo Kim and Mark G. Allen – University ofPennsylvania; Jooncheol Kim – Georgia Institute ofTechnology

6. 10:50 AM - Co-Design for Low Warpageand High Reliability in Advanced Packagewith TSV-Free Interposer (TFI)
Faxing Che, Masaya Kawano, M.Z. Ding, Yong Han,
and S. Bhattacharya – Institute of Microelectronics,
A*STAR

7. 11:15 AM - Development of HighFrequency Device Using Glass or Fused Silica
with 3D Integration
Shintarou Takahashi, Yoichiro Sato, Kohei Horiuchi, andMotoshi Ono – Asahi Glass Co., Ltd.

7. 11:15 AM - Test-Protocol for Assessmentof Flexible Power Sources in Foldable
Wearable Electronics under Stresses of Daily
Motion During Operation
Pradeep Lall and Hao Zhang – Auburn University

7. 11:15 AM - Finite Elements forElectromigration Analysis
Elena E. Antonova and David C. Looman – ANSYS
Inc.

15

Program Sessions: Thursday, June 1, 1:30 p.m. - 5:10 p.m.
Session 19: Recent Advances in FOWLP
Technology

Session 20: MEMS and Sensor
Technologies

Session 21: 3D Cu-Cu and Micro Bump
Bonding Technologies

Committee:
Materials & Processing

Committee:
Advanced Packaging

Committee:
Interconnections

Room: Southern Hemisphere IV

Room: Southern Hemisphere I

Room: Southern Hemisphere II

Session Co-Chairs:
Praveen Pandojirao-S – Johnson & Johnson
Yi Li – Intel Corporation

Session Co-Chairs:
Joseph W. Soucy – Draper
Allyson Hartzell – Veryst Engineering

Session Co-Chairs:
Katsuyuki Sakuma – IBM Corporation
Ho-Young Son – SK Hynix

1. 1:30 PM - Innovative Excimer Laser Dual
Damascene Process for Ultra-Fine Line Multilayer Routing with 10µm Pitch Micro-Vias for
Wafer-Level and Panel-Level Packaging
Markus Woehrmann, Robert Gernhardt, Karin Hauck,
Michael Toepper, and Tanja Braun – Fraunhofer IZM;
Habib Hichri and Markus Arendt – Suss MicroTec;
Klaus-Dieter Lang – Technical University Berlin

1. 1:30 PM - Fabrication of 3D Hybrid Pixel
Detector Modules Based on TSV Processing
and Advanced Flip Chip Assembly of Thin
Read Out Chips

1. 1:30 PM - Morphology of LowTemperature All-Copper Interconnects
Formed by Dip Transfer
Luca Del Carro, Jonas Zuercher, Thomas Brunschwiler,
and Sebastian Gerke – IBM Corporation; Tom
Wildsmith – Intrinsiq Materials; Gustavo Ramos –Atotech

2. 1:55 PM - Forming a Vertical Interconnect
Structure Using Dry Film Processing for FanOut Wafer Level Packaging
Yew Wing Leong, Hsiang-Yao Hsiao, David Soon Wee
Ho, Boon Long Lau, and Huamao Lin – Institute ofMicroelectronics, A*STAR

2. 1:55 PM - A Novel Technology for
Creating Sensors and Actuators in Processor
Packages
Feras Eid, Qing Ma, Sasha Oster, Georgios Dogiamis,
Thomas Sounart, and Johanna Swan – Intel
Corporation

2. 1:55 PM - Enabling Chip-to-Substrate
All-Cu Interconnections: Design ofEngineered Bonding Interfaces for Improved
Manufacturability and Low-Temperature
Bonding

3. 2:20 PM - Embedded Trench
Redistribution Layers (RDL) by Excimer Laser
Ablation and Surface Planer Processes
Yuya Suzuki, Rao Tummala and Venky Sundaram– Georgia Institute of Technology; Habib Hichri,Markus Arendt, and Lee Seongkuk – Suss MicroTec;
Frank Wei, Ye Chen, and Kwon Sang Lee – Disco
Corporation; Ognian Dimov, Deepak Arora, andSanjay Malik – Fujifilm Electronic Materials

3. 2:20 PM - Stress-Compensating MEMS
Sensor Assembly
Harald Etschmaier, Anderson Singulani, and Coen Tak– ams AG; Kai Zoschke, Hermann Oppermann, andDanny Jaeger – Fraunhofer IZM

3. 2:20 PM - Low-Temperature and
Low-Pressure Cu-Cu Bonding by Pure Cu
Nanosolder Paste for Wafer-Level Packaging
Junjie Li, Tielin Shi, Xing Yu, Chaoliang Cheng, Jinhu
Fan, Guanglan Liao, and Zirong Tang – Huazhong
University of Science and Technology

Kai Zoschke, Hermann Oppermann, Thomas Fritzsch, Mario Rothermund,and Ulf Oestermann – Fraunhofer IZM; Pawel Grybos, Krzysztof Kasinski,
Piotr Maj, and Robert Szczygiel – AGH University of Science and Technology;
Steve Voges and Klaus-Dieter Lang – Technical University Berlin

Ninad Shahane, Kashyap Mohan, Antonia Antoniou, Pulugurtha Markondeya
Raj, Vanessa Smet, and Rao Tummala – Georgia Institute of Technology;
Gustavo Ramos, Arnd Kilian, and Robin Taylor – Atotech; Frank Wei – Disco
Corporation

Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C

16

4. 3:30 PM - Temporary Bonding and
Debonding Technologies for Fan-Out WaferLevel Packaging
Qi Wu, Xiao Liu, Kuo Han, Dongshun Bai, and Tony
Flaim – Brewer Science

4. 3:30 PM - 3D Monolithic Metal Orifice
Plate For SERS Application: A Showcase of
Low Cost MEMS Packaging
Ning Ge, Steven Simske, Jarrid Wittkopf, Kevin
Dooley, Anita Rogacs, Helen Holder, Steven Barcelo,
Robert Ionescu, and Dennis Lazaroff – Hewlett
Packard Inc.

4. 3:30 PM - Dual Damascene Compatible,
Copper Rich Alloy Based Surface Passivation
Mechanism for Achieving Cu-Cu Bonding at
150°C for 3D IC Integration
Asisa Kumar Panigrahi, Tamal Ghosh, Siva Rama
Krishna Vanjari, and Shiv Govind Singh – Indian Instituteof Technology, Hyderabad

5. 3:55 PM - Development and Evaluationof Carrier Glass Substrate for Fan-Out WLP/PLP Process
Kazutaka Hayashi, Shigeki Sawamura, and Shuhei
Nomura – Asahi Glass, Co., Ltd.; Naoya Suzuki and
Masaaki Takekoshi – Hitachi Chemical Co., Ltd.

5. 3:55 PM - A Phase Sensitive Measurement
Technique for Boosted Response Speed ofGraphene FET Gas Sensor
Yumeng Liu, Takeshi Hayasaka, Yong Cui, Jiachen Yu,
Yoshihiro Kubota, Huiliang Liu, Xiaoqian Li, Kaiming
Hu, and Liwei Lin – UC Berkeley, BSAC; Vaishno
Dasika and Luu Nguyen – Texas Instruments, Inc.

5. 3:55 PM - Thermal and Electrical
Performance of Direct Bond Interconnect
Technology for 2.5D and 3D Integrated
Circuits
Akash Agrawal, Shaowu Huang, Guilian Gao, Liang
Wang, and Laura Mirkarimi – Invensas Corporation

6. 4:20 PM - Warpage Suppression during
FO-WLP Fabrication Process
Masaaki Takekoshi, Keisuke Nishido, Yuhei Okada,
Naoya Suzuki, and Toshihisa Nonaka – Hitachi
Chemical Co., Ltd.

6. 4:20 PM - Comparison of Packaging
Concepts for High-Temperature Pressure
Sensors at 500 °C
Nilavazhagan Subbiah, Surajit Ghosh, Juergen Wilde,
and Roderich Zeiser – University of Freiburg, IMTEK

6. 4:20 PM - Electrical Performance of HighDensity 10 µm Diameter 20 µm Pitch CuPillar with Chip to Wafer Assembly
Lucile Arnaud, Arnaud Garnier, Rémi Franiatte, Alain
Toffoli, Stéphane Moreau, Franck Bana, and Séverine
Chéramy – CEA-Leti

7. 4:45 PM - Impact of Process Control on
UBM/RDL Contact Resistance for NextGeneration Fan-Out Devices
Patrik Carazzetti, Frantisek Balon, Mike Hoffmann,
Juergen Weichart, Andreas Erhart, and Ewald Strolz –Evatec AG; Kay Viehweger – Fraunhofer IZM-ASSID

7. 4:45 PM - High Vacuum and High
Robustness Al-Ge Bonding for Wafer Level
Chip Scale Packaging of MEMS Sensors
Jinghui Xu, Zhipeng Ding, Vivek Chidambaram,
Hongmiao Ji, and Yuandong Gu – Institute ofMicroelectronics, A*STAR

7. 4:45 PM - Critical Factors Affecting
Structural Transformations in 3D IC Micro
JointsHong-Wei Yang, H.Y. Yu, and C. Robert Kao –National Taiwan University

Program Sessions: Thursday, June 1, 1:30 p.m. - 5:10 p.m.
Session 22: Solder Joint & Interconnect
Reliability, Characterization and Modeling

Session 23: Additive Manufacturing
and Panel-Level Packaging

Session 24: Novel Methods to Assess
Reliability

Committee: Thermal/Mechanical
Simulation & Characterization

Committee:
Emerging Technologies

Committee:
Applied Reliability

Room: Americas Seminar

Room: Southern Hemisphere V

Room: Southern Hemisphere III

Session Co-Chairs:
Yong Liu – ON Semiconductor
Erkan Oterkus – University of Strathclyde

Session Co-Chairs:
Florian Herrault – HRL Laboratories, LLC
W. Hong Yeo – Virginia Commonwealth
University

Session Co-Chairs:
Sridhar Canumalla – Microsoft Corporation
Keith Newman – AMD

1. 1:30 PM - Peridynamic Solution of
Wetness Equation with Time Dependent
Saturated Concentration in ANSYS
Framework
Cagan Diyaroglu and Erdogan Madenci – Universityof Arizona; Selda Oterkus and Erkan Oterkus –University of Strathclyde

1. 1:30 PM - Will Low-Cost 3D Additive
Manufactured Packaging Replace the FanOut Wafer Level Packages?
Tobias Tiedje, Sebastian Lüngen, Martin Schubert,
Marco Luniak, Krzysztof Nieweglowski, and Karlheinz
Bock – Technical University Dresden

1. 1:30 PM - Condition Monitoring Algorithm
for Piezoresistive Silicon-Based Stress Sensor
Data Obtained from Electronic Control Units
Alexandru Prisacaru, Alicja Palczynska, and Przemyslaw
Jakub Gromala – Robert Bosch GmbH; Bongtae Han– University of Maryland; G.Q. (Kouchi) Zhang – Delft
University of Technology

2. 1:55 PM - A Modified Acceleration Factor
Empirical Equation for BGA Type Package
Min-Hsuan Hsu and Kuo-Ning Chiang – National Tsing
Hua University; Chang-Chun Lee – National Chung
Hsing University

2. 1:55 PM - 3D Printing as a New Packaging
Approach for MEMS and Electronic Devices
Gabrielle Aspar, Baptiste Goubault, Olivier Lebaigue,
Gilles Simon, Léa Di Cioccio, Yves Bréchet, and JeanCharles Souriau – CEA-Leti

2. 1:55 PM - Mechanical Characterization of
SAC Solder Joints at High Temperature Using
Nanoindentation
Sudan Ahmed, Md Hasnine, Jeffrey C. Suhling, andPradeep Lall – Auburn University

3. 2:20 PM - Effect of Mean Temperatureon the Evolution of Strain-Amplitude in SAC
Ball-Grid Arrays During Operation underThermal Aging and Temperature Excursions
Pradeep Lall, Kazi Mirza, and Jeff Suhling – Auburn
University; David Locker – US ARMY AMRDEC

3. 2:20 PM - 3D Printed High Frequency
Coaxial Transmission Line Based Circuits
Michael Craton, Jennifer A. Byford, Vincens Gjokaj,
Premjeet Chahal, and John Papapolymerou – Michigan
State University

3. 2:20 PM - New Method to Separate
Failure Modes by Transient Thermal Analysisof High Power LEDs
Alexander Hanss, E. Liu, Gordon Elger, Maximilian
Schmid, and Dominik Müller – Technische Hochschule Ingolstadt; Udo Karbowski and Robert Derix– Lumileds

Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C
4. 3:30 PM - Characterization of Dual Side
Molding SiP Module
Jin-Yuan Lai, Tang-Yuan Chen, Ming-Han Wang, MengKai Shih, David Tarng, and Chih-Pin Hung – Advanced
Semiconductor Engineering, Inc

4. 3:30 PM - Design and Demonstration ofHighly Miniaturized, Low Cost Panel Level
Glass Package for MEMS Sensors
Chintan Buch, Daniel Struk, Klaus-Jürgen Wolter, Peter
J. Hesketh, Venkatesh Sundaram, and Rao Tummala– Georgia Institute of Technology; Catherine Shearer
and James Haley – EMD-Ormet Circuits; Mel Findlay –KWJ Engineering; Marc Papageorge – SPEC Sensors

4. 3:30 PM - Improving Terahertz Signal
Travel Distance for Fault Isolation
Hemachandar Tanukonda Devarajulu, Mayue Xie,
Chengqing Hu, and Deepak Goyal – Intel Corporation;
Eiji Kato and Masaichi Hashimoto – Advantest
Corporation

5. 3:55 PM - Flip Chip Solder Joint Pad
Optimizations for Connectivity SiP
Applications
Quan Qi and Carlton Hanna – Intel Corporation

5. 3:55 PM - Miniature Heterogeneous FanOut Packages for High-Performance, LargeFormat Systems
Carl Prevatte, Matthew A. Meitl, Erich Radauscher, David
Gomez, Kanchan Ghosal, Salvatore Bonafede, Brook
Raymond, Tanya Moore, António Jose Trindade, andChristopher A. Bower – X-Celeprint; Paul Hines – Micross
Advanced Interconnect Technology

5. 3:55 PM - Effective Evaluation Method:
A New Delamination Test Method for MUF(Molded Underfill) Package
Junghwa Kim, Seung Han, Woochul Na, SoYoon Kim,
Ki Hyeok Kwon, Deokhoon Park, Donghwan Lee, andSang Kyun Kim – Samsung SDI

6. 4:20 PM - Anisotropic and Multiscale
Constitutive Framework for the Reliability ofMicroscale Interconnects Based on Damage
Mechanics
Zhengfang Qian – Shenzhen University; Hongtao Chen
– Harbin Institute of Technology

6. 4:20 PM - Extremely High Temperatureand High Pressure (x-HTHP) Endurable
SOI Device & Sensor Packaging for Harsh
Environment Applications
Keng Yuen Au and Eva Wai Leong Ching – Institute ofMicroelectronics, A*STAR

6. 4:20 PM - Measuring Sodium Migration in
Mold Compounds Using a Sodium Amalgam
Electrode as an Infinite Source
Stefan Schwab and Michael Nelhiebel – Kompetenzzentrum
Automobil- u. Industrieelektronik; Julia Appenroth, Peter
Weinberger, Herbert Hutter, Maximilian Bonta, and Andreas
Limbeck – Technische Universität Wien; Sabine Holzer, Michael
Bauer, and Stefan Miethaner – Infineon Technologies

7. 4:45 PM - SACQ Solder Board Level
Reliability Evaluation and Life Prediction
Model for Wafer Level Packages
Wei Lin, Quan Pham, Bora Baloglu, and Michael
Johnson – Amkor Technology, Inc.

7. 4:45 PM - A Study on the Novel Nylon
Anchoring Polymer Layer (APL) Anisotropic
Conductive Films (ACFs) for Ultra Fine Pitch
Chip-On-Glass (COG) Applications
Dal-jin Yoon, Sang-Hoon Lee, and Kyung-Wook Paik –Korea Advanced Institute of Science & Technology

7. 4:45 PM - A New Method for Predictionof Corrosion Processes in Metallization
Systems for Substrates and ElectricalContacts
Sandy Klengel, Tino Stephan, and Uwe Spohn –Fraunhofer IMWS

17

Program Sessions: Friday, June 2, 8:00 a.m. - 11:40 a.m.
Session 25: Characterization andReliability of Fan-Out & WLP

Session 26: 3D Integration Processing
and Reliability

Session 27: Advances in Thermal
Compression and Wirebonding

Committee:
Applied Reliability

Committee:
Advanced Packaging

Committee:
Interconnections

Room: Southern Hemisphere V

Room: Southern Hemisphere I

Room: Southern Hemisphere II

Session Co-Chairs:
Lakshmi N. Ramanathan – Microsoft
Corporation
Toni Mattila – Aalto University

Session Co-Chairs:
Rozalia Beica – Dow Electronic Materials
Dean Malta – Micross Advanced Interconnect
Technology

Session Co-Chairs:
Matthew Yao – GE Energy Management
William Chen – Advanced Semiconductor
Engineering, Inc.

1. 8:00 AM - The Paradoxical Role of
Sulphur in Molding Compounds: Influence
on High Temperature Reliability of Cu-Al
Wirebond Interconnects
Amar Mavinkurve, Leon Goumans, Bongkoj
Bumrungkittikul, Mark-Luke Farrugia, Erik van Olst,
Michiel van Soestbergen, and Rene Rongen – NXP
Semiconductors

1. 8:00 AM - Sub-Micron ElectricalInterconnection Enabled Ultra-High I/O
Density Wafer Level SiP Integration
Chung Jung Wu, Tung Liang Shao, Hsiao Yun Chen,
Sheng Tsung Hsiao, Yi Li Hsiao, Chih Hang Tung, Chen
Hua Yu, and Wei Heng Lin – Taiwan Semiconductor
Manufacturing Company, Ltd.

1. 8:00 AM - Heterogeneous Integration
at Fine Pitch (2-10 µm) Using Thermal
Compression Bonding
Adeel Ahmad Bajwa, SivaChandra Jangam, Saptadeep
Pal, Niteesh Marathe, Tingyu Bai, Takafumi Fukushima,
Mark Goorsky, and Subramanian Iyer – University ofCalifornia, Los Angeles

2. 8:25 AM - Mechanistic Investigation andPrevention of Al Bond Pad Corrosion in Cu
Wire-Bonded Device Assembly
Oliver Chyan, Nick Ross, Alex Lambert, Seare Berhe,and Muthappan Asokan – University of North Texas;
Mahmud Chowdhury, Shawn O’Connor, and Luu
Nguyen – Texas Instruments, Inc.

2. 8:25 AM - Temporary Bonding and
De-Bonding for Multichip-to-Wafer 3DIntegration Process Using Spin-On Glass andHydrogenated Amorphous Si
Murugesan Mariappan, Takafumi Fukushima, andMitsumasa Koyanagi – Tohoku University

2. 8:25 AM - Reliable Cu-Cu
Thermocompression Bonding by Low
Temperature Sintered Cu Nanowires
Li Du, Tielin Shi, Zirong Tang, and Guanglan Liao –Huazhong University of Science and Technology

3. 8:50 AM - Use Condition Risk Assessment
for Moisture Related Failures
Min Pei, Sibasish Mukherjee, Nitin Uppal, and Milena
Vujosevic – Intel Corporation

3. 8:50 AM - Cu/Adhesive Hybrid Bondingat 180 °C in H-Containing HCOOH Vapor
Ambient for 2.5D/3D Integration
Ran He, Masahisa Fujino, Masatake Akaike, andTadatomo Suga – University of Tokyo; Taiji Sakai and
Seiki Sakuyama – Fujitsu Semiconductor

3. 8:50 AM - Effect of Metallic Materials
Films on the Properties of Copper/Tin
Micro-Bump Thermo-Compression Bonding
Yong Guan, Qinghua Zeng, Jing Chen, Yufeng Jin, andWei Meng – Peking University; Shenglin Ma – Xiamen
University

Refreshment Break: 9:15 a.m. - 10:00 a.m. Southern Hemisphere Foyer

18

4. 10:00 AM - Drop Impact Reliability Testand Failure Analysis for Large Size High Density FOWLP Package on Package
Zhaohui Chen, Faxing Che, Mian Zhi Ding, David Soon
Wee Ho, Tai Chong Chai, and Vempati Srinivasa –Institute of Microelectronics, A*STAR

4. 10:00 AM - 3D Packaging Challenges forHigh-End Applications
Rahul Agarwal, Sukeshwar Kannan, and Luke England– GLOBALFOUNDRIES; Rick Reed, Yong Song,
SangHyoun Lee, WangGu Lee, and JinKun Yoo –Amkor Technology, Inc.

4. 10:00 AM - Thermal Bond Reliability ofHigh Reliability New Palladium-Coated Copper Wire
Motoki Eto, Ryo Oishi, and Takashi Yamada – Nippon
Micrometal Corporation; Tomohiro Uno and Tetsuya
Oyamada – Nippon Steel & Sumitomo Metal; Teruo
Haibara – Nippon Micrometal Corporation

5. 10:25 AM - The Comparative Study To
Enhance Board Level Reliability Performanceof Wafer Level Package at 0.25 mm Pitch
Using Micro-Ball Drop and Electroplated
Solder Technology
Kuei Hsiao Kuo, Yi Sin Ting, Chui Feng Weng, Feng
Lung Chien, Katch Wan, Chun Sheng Ho, and Rick Lee– Siliconware Precision Industries Co., Ltd.

5. 10:25 AM - A Novel Method for Air-Gap
Formation around Via-Middle (VM) TSVs
for Effective Reduction in Keep-Out Zones(KOZ)
King-Jien Chui, Woon Leng Loh, Xiangyu Wang,
Zhaohui Chen, and Mingbin Yu – Institute ofMicroelectronics, A*STAR

5. 10:25 AM - Correlation Study of
Pd Metallurgical Distributions and RF
Characteristics of Pd Coated/Doped Ag-alloy
Wire Bonds
Yi-Jung Sung and Lih-Tyng Hwang – National Sun YatSen University; Chang-Yi Feng – NXP Semiconductors;
Eson Chuang – Precision Packaging Materials Corp.

6. 10:50 AM - Quality and Reliability
Assessment of Cu Pillar Bumps for Fine Pitch
Applications
Othmane Jerhaoui, Stephane Moreau, David Bouchu,
Gilles Romero, Denis Marseilhan, Thierry Mourier, andArnaud Garnier – CEA-Leti

6. 10:50 AM - Warpage Study of Large 2.5D
IC Chip Module
Chieh-Lung Lai, Hung-Yuan Li, Sam Peng, Terren Lu,
and Stephen Chen – Siliconware Precision Industries
Co., Ltd.

6. 10:50 AM - Advances in Wire Bonding
Technology for 3D Die Stacking and Fan-Out
Wafer Level Package
Ivy Qin, Oranna Yauw, Gary Schulze, Aashish Shah,Bob Chylak, and Nelson Wong – Kulicke and Soffa,
Inc.

7. 11:15 AM - Effect of Prolonged Storage
up to 1-Year on the High Strain Rate
Properties of SAC Leadfree Alloys at
Operating Temperatures up to 200°C
Pradeep Lall, Di Zhang, Vikas Yadav, and Jeff Suhling– Auburn University; David Locker – US Army
AMRDEC

7. 11:15 AM - Board Level Reliability
Optimization for 3D IC Packages with Extra
Large Interposer
Laurene Yip, Ganesh Hariharan, Raghu Chaware,
Inderjit Singh, and Tom Lee – Xilinx, Inc.

7. 11:15 AM - Development of Packaging
Technology for High Temperature Resistant
SiC Module of Automobile Application
Kohei Tatsumi, Tomonori Iizuka, Kazuhito Kamei, and Masakazu Inagaki –Waseda University; Akihiro Imakire and Masayuki Hikita – Kyushu Instituteof Technology; Rikiya Kamimura – FAIS; Nobuaki Sato, Hiroaki Narimatsu,
Kazutoshi Ueda and Koji Shimizu – Mitsui High-tec Inc.; Kazuhiko Sugiura
and Kazuhiro Tsuruta – DENSO Corporation; Keiji Toda – Toyota

Program Sessions: Friday, June 2, 8:00 a.m. - 11:40 a.m.
Session 28: Advanced Materials for
Reliability Improvement

Session 29: Warpage Control andSubstrates

Session 30: RF Components andModule Integration

Committee:
Materials & Processing

Committee:
Assembly & Manufacturing Technology

Committee:
High-Speed, Wireless & Components

Room: Southern Hemisphere IV

Room: Southern Hemisphere III

Room: Americas Seminar

Session Co-Chairs:
Kwang-Lung Lin – National Cheng Kung
University
Bing Dang – IBM Corporation

Session Co-Chairs:
Paul Tiner – Texas Instruments
Paul Houston – Engent

Session Co-Chairs:
Craig Gaw – NXP Semiconductor
Wendem Beyene – Rambus Inc.

1. 8:00 AM - High Performance Insulating
Adhesive Film for High-Frequency
Applications
Junya Sato, Shin Teraki, Masaki Yoshida, and Hisao
Kondo – NAMICS Corporation

1. 8:00 AM - Innovative Advances in
Copper Electroplating for IC Substrate
Manufacturing
Kousik Ganesan, Yang Sun, Chandrashekhar Pendyala,Thomas Heaton, Radek Chalupa, Marcel Wall,
Suddhasattwa Nad, and Rahul Manepalli – Intel
Corporation; Amaneh Tasooji – Arizona State
University

1. 8:00 AM - Next Generation High-Q
Compact Size IPD Diplexer for RF Front End
SiP
Sheng-Chi Hsieh, Pao-Nan Lee, Chen-Chao Wang,
Teck Chong Lee, and Hsu-Chiang Shih – Advanced
Semiconductor Engineering, Inc.

2. 8:25 AM - Epoxy/Cyanate Ester
Copolymer Material for Molding Compounds
in High-Temperature Operations
Chia-Chi Tuan, Fan Wu, Kyoung-Sik Moon, and ChingPing Wong – Georgia Institute of Technology

2. 8:25 AM - Reflow Warpage Induced
Interconnect Gaps between Package/PCB
and PoP Top/Bottom Packages
Kaiqiang Peng, Wei Xu, Zhenkai Qin, Lei Feng, Linlin
Lai, and Wei Hu Koh – Huawei Technologies

2. 8:25 AM - Self-Actuating 3D Printed
Packaging for Deployable Antennas
Ryan Bahr, Manos Tentzeris, Abdullah Nauroze, andWenjing Su – Georgia Institute of Technology

3. 8:50 AM - High Thermal Conductivity
Mold Compounds for Advanced Packaging
Applications
Makoto Shibuya and Luu Nguyen – Texas Instruments,
Inc.

3. 8:50 AM - Warpage Tuning Study for
Multi-Chip Last Fan-Out Wafer Level
PackageHung-Yuan Li, Allen Chen, Sam Peng, George Pan,and Stephen Chen – Siliconware Precision Industries
Co., Ltd.

3. 8:50 AM - A Simple and Efficient RF
Technique for the TSV Characterization
Xiao Sun, Stefaan Van Huylenbroeck, Geert Van derPlas, and Eric Beyne – IMEC; Cesar Roda Neve – M3
Systems

Refreshment Break: 9:15 a.m. - 10:00 a.m. Southern Hemisphere Foyer
4. 10:00 AM - Enhanced Thermal Conductivity of the Underfill Materials using Insulated
Core/Shell Filler Particles for High Performance Flip Chip Applications
Tae-Ryong Kim, Kisu Joo, and Se Young Jeong– Ntrium, Inc.; Boo Taek Lim and Boung Ju Lee –National Nanofab Center; Sung-Soon Choi – Korea
Electronics Technology Institute; Myung Jin Yim – Intel
Corporation; Euijoon Yoon – Seoul National University

4. 10:00 AM - Warpage Characterization of
Glass Interposer Package Development
Meng-Kai Shih, Charles Hsu, Yungshun Chang, Karenyu
Chen, Ian Hu, David Tarng, CP Hung, and Teck Lee –Advanced Semiconductor Engineering, Inc.

4. 10:00 AM - The Smallest Form Factor GPS
for Mobile Devices
Eb Andideh, Chuck Carpenter, Jason Steighner, Mike
Yore, James Tung, Lynda Koerber, David Schnaufer, Jeff
Moran, Suwanna Jittinorasett, Bharati Ingle, Anousa
Sengsavanh, and Otto Berger – Qorvo, Inc.

5. 10:25 AM - High Thermal Performance
Package with Anisotropic Thermal
Conductive Material
Ian Hu, Jia-Rung Ho, Jin-Feng Yang, Meng-Kai Shih,,David Tarng, and Chih-Pin Hung – Advanced
Semiconductor Engineering, Inc.

5. 10:25 AM - The Influence of Resin
Coverage on Reliability for Solder Joints
Formed by One-Pass Reflow Using Resin
Reinforced Low Temperature Solder Paste
Atsushi Yamaguchi, Yasuo Fukuhara, Andy Behr,
Naomichi Ohashi, Yasuhiro Suzuki, and Hirohisa Hino
– Panasonic Corporation

5. 10:25 AM - Transparent Antennas for
Wireless Systems Based on Patterned Indium
Tin Oxide and Thin Flexible GlassMark Poliks, Yi-Lin Sung, Jack Lombardi, Robert
Malay, Charles R. Westgate, and Jeremiah Dederick– Binghamton University; Ming-Huang Huang, Sean
Garner, Scott Pollard, and Colin Daley – Corning, Inc.

6. 10:50 AM - The Reduction of Outgas
from Pre-Applied Underfill Materials by
Optimizing the Combination of Base Resinand Flux Compound
Kohei Higashiguchi, Takenori Takiguchi, Masashi
Okaniwa, Katsutoshi Ihara, Tsuyoshi Kida, Shu Yoshida,
and Toyoji Oshima – Mitsubishi Gas Chemical

6. 10:50 AM - Analysis of System-Level
Reliability of Single-Chip Glass BGA
Packages with Advanced Solders andPolymer Collars
Vidya Jayaram, Scott McCann, Bhupender Singh,
Pulugurtha Markondeya Raj, Vanessa Smet, and Rao
Tummala – Georgia Institute of Technology; Hiro
Matsuura and Yutaka Takagi – NTK/NGK

6. 10:50 AM - Transfer Function
Reconfigurable Cavity Bandpass Filter
Embedded with Metallic Grid
Shang-Yu Hung, Guann-Pyng Li, Mark Bachman,
Hsiang-Yu Chan, and Yu Guo – University ofCalifornia, Irvine

7. 11:15 AM - Study of Capillary Underfill
Filler Separation in Advanced Flip Chip
PackagesMarie-Claude Paquet – IBM Corporation; David
Danovitch, Papa Souare, and Julien Sylvestre –Université de Sherbrooke

7. 11:15 AM - A Comprehensive Study on
Stress and Warpage by Design, Simulation
and Fabrication of RDL-First Panel Level
Fan-Out Technology for Advanced Package
Puru Lin, Cheng-Ta Ko, Yu-Hua Chen, Wei-Tse Ho,
Chi-Hai Kuo, Kuan-Wen Chen, and Tzyy-Jang Tseng –Unimicron Technology Corp.

7. 11:15 AM - Capillary Condensation Based
Wireless Volatile Molecular Sensor
Saranraj Karuppuswami, Amanpreet Kaur, andPremjeet Chahal – Michigan State University;
Nophadon Wiwatcharagoses – Mongkut’s Universityof Technology

19

Program Sessions: Friday, June 2, 1:30 p.m. - 5:10 p.m.
Session 31: Auto Electronics Packaging
and Power Modules

Session 32: Reliability Challenges in
2.5D/3D Interconnect

Session 33: Advanced Bonding and
Soldering Technology

Committee:
Advanced Packaging

Committee: Interconnections Joint with
Applied Reliability

Committee:
Materials & Processing

Room: Southern Hemisphere I

Room: Southern Hemisphere II

Room: Southern Hemisphere IV

Session Co-Chairs:
Jianwei Dong – Dow Electronic Materials
Christophe Zinck – ASE

Session Co-Chairs:
Nathan Lower – Rockwell Collins, Inc.
Dongji Xie – NVIDIA Corporation

Session Co-Chairs:
Kimberly Yess – Brewer Science
Qianwen Chen – IBM Corporation

1. 1:30 PM - Novel Polymer Substrate-Based1.2 kV/ 40A Double-Sided Intelligent Power
ModuleXin Zhao, Yifan Jiang, Bo Gao, and Douglas Hopkins– North Carolina State University; Kenji Nishiguchi Risho Kogyo Co., Ltd.; Yoshi Fukawa - TOYOTech LLC

1. 1:30 PM - Reliability Challenges in 2.5D
and 3D IC Integration
Li Li, Paul Ton, Mohan Nagar, and Pierre Chia – Cisco
Systems, Inc.

1. 1:30 PM - Novel Large-Area Attachmentfor High-Temperature Power Electronics
Module Application
Chunlei Liu, Fabian Mohn, Juergen Schuderer, andDaniele Torresin – ABB Switzerland Ltd.

2. 1:55 PM - Advanced Packaging Need forAutomotive In-Cabin Application
Nokibul Islam, Ming-Che Hsieh, and Kang KeonTaek –STATS ChipPAC, Inc.

2. 1:55 PM - High Frequency Electrical
Performance and Thermo-MechanicalReliability of Fine-Pitch, Copper-Metallized
Through-Package-Vias (TPVs) in Ultra-Thin
Glass Substrates

2. 1:55 PM - Bismuth-Based Transient Liquid
Phase (TLP) Bonding as High-Temperature
Lead-Free Solder Alternatives
Junghyun Cho, Roozbeh Sheikhi, and Sandeep
Mallampati – Binghamton University; Liang Yin andDavid Shaddock – General Electric Co.

Sukhadha Viswanathan, Timothy B. Huang, Kaya Demir, P. Markondeya
Raj, Fuhan Liu, Venky Sundaram, and Tummala Rao – Georgia Institute ofTechnology; Tomonori Ogawa – Asahi Glass Co., Ltd.

3. 2:20 PM - Reliability of eWLB (embedded
wafer level BGA) for Automotive Radar
Applications
Daniel Yap, Kim Sing Wong, and Luc Petit –STMicroelectronics; Yaojian Lin, Roberto Antonicelli,and Seung Wook Yoon – STATS ChipPAC, Inc.

3. 2:20 PM - Reliability Evaluations on 3D ID
Package Beyond JEDEC
Raghunandan Chaware, Laurene Yip, Inderjit Singh,
Kenny Ng, Michael Shen, and Antai Xu – Xilinx, Inc.

3. 2:20 PM - Silver Sinter Paste for SiC
Bonding with Improved Mechanical
Properties
Wolfgang Schmitt and Ly May Chew – Heraeus
Deutschland GmbH & Co. KG

Refreshment Break: 2:45 p.m. - 3:30 p.m. Southern Hemisphere Foyer

20

4. 3:30 PM - Packaging Innovations for High
Voltage (HV) GaN Technology
Dibyajat Mishra, Vivek Arora, Luu Nguyen, Shoichi
Iriguchi, Hiroyuki Sada, Laura Clemente, Sueann Lim,
Hung-Yun Lin, Siva Gurrum, Alok Lohia, J. Sauser andS. Spencer – Texas Instruments, Inc.

4. 3:30 PM - Remarkable Suppression of
Local Stress in 3D IC by Manganese NitrideBased Filler with Large Negative CTE
Hisashi Kino, Takafumi Fukushima, and Tetsu Tanaka –Tohoku University

4. 3:30 PM - Diffusion Barrier Effect of NiW-P and Ni-Fe UBMs during High Temperature Storage
Li-Yin Gao and Zhi-Quan Liu – Chinese Academyof Sciences; Li Liu, Jing Wang, Zhao-Xia Zhou, andChang-Qing Liu – Loughborough University

5. 3:55 PM - Thin-Film Magnetic Inductors
for Integrated Power Management
Annamalai Arasu Muthukumaraswamy, King-Jien Chui,
Wei Yi Lim, Serine Soh, Jun Yu, Yew Wing Leong,
Huamao Lin, and Sunil Wickramanayaka – Institute ofMicroelectronics, A*STAR

5. 3:55 PM - Electrical Characterization of
CMP-Less Via-Last TSV under Reliability
Stress Conditions
Mingbin Yu – Institute of Microelectronics, A*STAR

5. 3:55 PM - Study of C2W Bonding Using Cu
Pillar with Side-Wall Plated Solder
Ling Xie, Sunil Wickramanayaka, Vasarla Nagendra
Sekhar, and Daniel Ismael Cereno – Institute ofMicroelectronics, A*STAR

6. 4:20 PM - Feasibility Investigations on
Selective Laser Melting for the Developmentof Microchannel Cooling in PowerElectronics
Aarief Syed-Khaja, Antonio Perinan Freire, Christopher
Kaestle, and Joerg Franke – Friedrich Alexander
University

6. 4:20 PM - A Novel Failure Analysis
Technique for Semiconductor Packaging by
Xenon Difluoride Gas
Hongqing Zhang Zhang, Frank Pompeo, and Tom
Wassick – IBM Corporation

6. 4:20 PM - Fabrication andCharacterization of Nanoporous Metallic
Interconnects Using Electrospun Nanofiber
Template and Electrochemical Deposition
Sheng-Po Fang, Seahee Hwangbo, Hyowon An, andYong-Kyu Yoon – University of Florida

7. 4:45 PM - POL-kw Modules for HighPower Applications
Liang Yin, Kaustubh Nagarkar, Arun Gowda,
Christopher Kapusta, Paul Gillespie, Tammy Johnson,
Risto Tuominen, and Donna Sherman – General
Electric Co.; Shingo Hayashibe, Hitoshi Ito, and Tadashi
Arai – Shinko Electric Industries Co., Ltd.

7. 4:45 PM - Alternative 3D Small Form
Factor Methodology of System in Package
for IoT and Wearable Devices Application
Mike Tsai, Albert Lan, Chi Liang Shih, Terence Huang,
Ryan Chiu, S. L. Chung, J. Y. Chen, Frank Chu, Cheng
Kai Chang, Sheng Ming Yang, Daniel Chen, andNicholas Kao – Siliconware Precision Industries Co.,Ltd.

7. 4:45 PM - Ga Liquid Metal Embrittlementfor Fine Pitch Interconnect Rework
Elodie Nguena, David Danovitch, and Malak Kanso– University of Sherbrooke; Richard Langlois – IBM
Corporation

Program Sessions: Friday, June 2, 1:30 p.m. - 5:10 p.m.
Session 34: Waveguide Devices andChip-to-Fiber Packaging

Session 35: Thermomechanical and
Thermal Characterization

Session 36: Advances in Signal andPower Integrity

Committee:
Optoelectronics

Committee: Thermal/Mechanical
Simulation & Characterization

Committee:
High-Speed, Wireless & Components

Room: Southern Hemisphere III

Room: Southern Hemisphere V

Room: Americas Seminar

Session Co-Chairs:
Ping Zhou – LDX Optronics, Inc.
Hiren Thacker

Session Co-Chairs:
Pradeep Lall – Auburn University
Przemyslaw Gromala – Robert Bosch GmbH

Session Co-Chairs:
Zhaoqing Chen – IBM Corporation
Amit P. Agrawal – Keyssa Inc.

1. 1:30 PM - Design, Fabrication andConnectorization of High-Performance
Multimode Glass Waveguides for BoardLevel Optical Interconnects
Lars Brusberg, Davide Fortusini, Wei Jiang, Aramais
Zakharian, Sergey Kuchinsky, Christian Fiebig, Shenping
Li, Andrey Kobyakov, and Alan Evans – Corning, Inc.;
Henning Schröder – Fraunhofer IZM

1. 1:30 PM - The Combined Effect of
Mechanical Package Stress and Humidity on
Chip Corrosion Probability
Georg Lorenz and Michél Simon-Najasek – Fraunhofer
IMWS; Achim Lindner – TDK-Micronas GmbH

1. 1:30 PM - Active and Passive Techniques
for Noise Sensitive Circuits in Integrated
Voltage Regulator Based Microprocessor
Power Delivery
Amit Jain, Sameer Shekhar, and Yan Z. Li – Intel
Corporation

2. 1:55 PM - Axially Tapered Circular Core
Polymer Optical Waveguides Enabling Highly
Efficient Light Coupling
Takaaki Ishigure, Kenji Katori, Hoshihiko Toda, andKazuki Yasuhara – Keio University

2. 1:55 PM - Mechanical Characterization of
Anodic Bonding Using Chevron Microchannel
David C. Woodrum, Mohammed Nasr, Xuchen
Zhang, Muhannad S. Bakir, and Suresh K. Sitaraman –Georgia Institute of Technology

2. 1:55 PM - High Voltage Capacitors for
Next-Generation Power Modules in Electric
VehiclesRobert Spurney, Himani Sharma, P. M. Raj, and Rao
Tummala – Georgia Institute of Technology; Naomi
Lollis – AVX Corporation

3. 2:20 PM - First Demonstration of SingleMode Polymer Optical Waveguides with
Circular Cores for Fiber-to-Waveguide
Coupling in 3D Glass Photonic Interposers
Rui Zhang, Fuhan Liu, Venky Sundaram, and Rao
Tummala – Georgia Institute of Technology

3. 2:20 PM - Package-Level Si Micro-Fluid
Cooler with Enhanced Jet Array for High
Performance 3D Systems
Yong Han, Boon Long Lau, and Gongyue Tang –Institute of Microelectronics, A*STAR; Seow Meng
Low and Jason Goh – BeCe Pte. Ltd.

3. 2:20 PM - Package and Printed Circuit
Board Design of a 19.2 Gb/s Data Link for
High-Performance Computing
Sungjun Chun, Jose Hejase, Junyan Tang, Jean Audet,
Dale Becker, Daniel Dreps, Glen Wiedemeier, Megan
Nguyen, Lloyd Walls, Francesco Preda, and Daniel
Douriet – IBM Corporation

Refreshment Break: 2:45 p.m. - 3:30 p.m. Southern Hemisphere Foyer
4. 3:30 PM - 3D Optical Coupling Techniques
on Polymer Waveguides for Wafer and Board
Level Integration
Sebastian Lüngen, Sujay Charania, Tobias Tiedje,
Krzystof Nieweglowski, Sebastian Killge, Lukas Lorenz,
Johann W. Bartha, and Karlheinz Bock – Technical
University Dresden

4. 3:30 PM - A Unified and Versatile Model
Study for Moisture Diffusion
Liangbiao Chen, Jenny Zhou, Hsing-wei Chu, andXuejun Fan – Lamar University

4. 3:30 PM - Signal and Power Integrity
Analysis of High-Speed Links with Silicon
Interposer
Wendemagegnehu Beyene, Nitin Juneja, Yeon-Chang
Hahm, Ravi Kollipara, and Joohee Kim – Rambus, Inc.

5. 3:55 PM - Position Dependence of
Coupling Efficiency of Grating Coupler in
Waveguide Cavity
Shogo Ura, Kazuki Mori, Ryo Tsujimoto, and Junichi
Inoue – Kyoto Institute of Technology; Kenji Kintaka– National Institute of Advanced Industrial Science &Technology

5. 3:55 PM - Microstructure Simulation andThermo-Mechanical Behavior Analysis of
Copper Filled through Silicon Vias Using
Coupled Phase Field and Finite Element
Methods
Shui-Bao Liang, Chang-Bo Ke, Han Jiang, Min-Bo
Zhou, and Xin-Ping Zhang – South China University ofTechnology

5. 3:55 PM - Novel Parallel Resonance Peak
Measurement and Lossy Transmission Line
Modeling of 2-T and 3-T MLCC Capacitors
for PDN Application
Larry Smith, Javid Mohamed, Jaemin Shin, and Tim
Michalka – Qualcomm Technologies, Inc.

6. 4:20 PM - Efficient, Easy-to-Use, Planar
Fiber-to-Chip Coupling Process with AnglePolished Fibers
Djorn Karnick, Nils Bauditsch, Lars Eisenblätter,
Thomas Kühner, Marc Schneider, and Marc Weber –Karlsruhe Institute of Technology (KIT)

6. 4:20 PM - On the Process/History
Dependence of Package Mechanical
Performance
Mingji Wang, Lou Nicholls, MiNa Mo, MinJae Lee,
Quan Pham, and Yong Song – Amkor Technology, Inc.

6. 4:20 PM - Eye-Diagram Estimation
Methods for Voltage- and ProbabilityDependent PAM-4 Signal on Stacked
Through-Silicon Vias
Junyong Park, Jonghoon J. Kim, Sumin Choi, Youngwoo
Kim, and Joungho Kim – Korea Advanced Institute of
Science & Technology; Heegon Kim – MST

7. 4:45 PM - Novel, High-Throughput, Fiberto-Chip Assembly Employing Only Off-theShelf Components
Nicolas Boyer, Alexander Janta-Polczynski, StephanMartel, Swetha Kamlapurkar, Sebastian Engelmann,
Paul Fortier, and Tymon Barwicz – IBM Corporation;
Jean-Francois Morissette – Université de Sherbrooke;
Ted Lichoulas – AFL Telecommunications

7. 4:45 PM - Systematic Approach to Design
High Power FPGA Package for CurrentCarrying Capability
Hong Shi, Siow Chek Tan, Jae-Gyung Ahn, Gamal
Refai-Ahmed, and Suresh Ramalingam – Xilinx, Inc.

7. 4:45 PM - Signal Integrity Modelling in
Inhomogeneous Waveguide/PCB of Arbitrary
Shape Using Broadband Green’s Function
Kung-Hau Ding – Air Force Research Laboratory; TienHao Liao and Leung Tsang – University of Michigan

21Interactive Presentations: Wednesday, May 31, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m., and Thursday, June 1, 9:00 a.m. - 11:00 a.m.
Wednesday, May 31, 2017
Session 37: Interactive Presentations 1
9:00 AM - 11:00 AM
Committee: Interactive Presentations
Room: Northern Hemisphere Foyer
Session Co-Chairs:
Rao Bonda – Amkor Technology
John Hunt – Advanced Semiconductor
Engineering, Inc.
Deborah S. Patterson – Principal, Patterson
Group
Andy Tseng – JSR Micro
1) Package-Level EMI Shielding Technology with
Silver Paste for Various Applications
Kisu Joo, Tae-Ryong Kim, Jung Woo Hwang, Jin-Ho Yoon, andSe Young Jeong – Ntrium Incorporation; Myung Jin Yim – Intel
Corporation
2) Effects of Current Stress for Low Temperature
Cu/Sn/Cu Solid-State-Diffusion Bonding
Jian Cai, Qian Wang, and Zijian Wu – Tsinghua University;
Junqiang Wang and Dejun Wang – Dalian University ofTechnology
3) High Throughput Low Stress Air Jetting Carrier
Release for RDL First Fan-Out Wafer Level Packaging
Hao Tang, Gary Shi, and Raphael He – Micro Materials Inc.;
Ming Yin, Wei Zhang, and My Nguyen – Zhejiang Microtech;
Mike Chang and Sheng-Shu Yang – ITRI
4) 48×10 Gbps Cost-Effective FPC Based On-Board
Optical Transmitter with PGA Connector
Teng Li, Gonzalo Guelbenzu de Villota, Chenhui Li, R. Patty
Stabile, and Oded Raz – Eindhoven University of Technology;
Sander Dorrestein – TE Connectivity5) A Novel Wafer Level Integration of Liquid-Metal
Injection based TSV and Integrated Passive Devices
Tao Zheng, Gaowei Xu, and Le Luo – Shanghai Institute ofMicrosystem and Information Technology
6) Next Generation Plating Technologies for FOPanel Level Packaging
Ralph Zoberbier, James Welsh, Christian Ohde, and Henning
Huebner – Atotech Deutschland GmbH
7) A Density Staggered Cantilever for Micron
Length Gravity Probing
Qidong Wang and Liqiang Cao – Institute of Microelectronics/
Stanford University; Alexander D. Rider, David C. Moore,Charles P. Blakemore, and Giorgio Gratta – Stanford University8) Scalability and Yield in Elastomer Stamp MicroTransfer-Printing
David Gomez, Kanchan Ghosal, Matthew A. Meitl, Salvatore
Bonafede, Carl Prevatte, Tanya Moore, Erich Radauscher,
Antonio Jose Trindade, and Christopher A. Bower –X-Celeprint
9) Dynamic Strain of Ultrasonic Cu and Au Ball
Bonding Measured In-situ by Using Silicon Piezoresistive Sensor
Keiichiro Iwanabe, Kenichi Nakadozono, Mamoru Sakamoto,and Tanemasa Asano – Kyushu University10) High Transmittance Broadband THz Polarizer
Using 3D-IC Technologies
Nai-Chen Chi, Ting-Yang Yu, Hsin-Cheng Tsai, Chih-Wei Luo,Kuan-Neng Chen, and Yu-Tao Yang – National Chiao Tung
University; Shiang-Yu Wang – Academia Sinica
11) High Accuracy Thermal Compression Bonding
Technology for Large-Sized Substrate
Noboru Asahi, Toshiyuki Jinda, Yoshihito Mizutani, Koichi Imai,
Hikaru Tomita, Mikio Kawakami, Masafumi Senda, Katsumi
Terada, and Yasunori Hashimoto – Toray Engineering Co., Ltd.
12) Real-Time Color-Tunable White LEDs ThroughCombination of Phosphor Patterns and Adaptive
Liquid Lens
Huai Zheng and Sheng Liu – Wuhan University; Zefeng Zhang
and Peng Yang – Huazhong University of Science & Technology
13) Yield Comparison of Die-First Face-Down and
Die-Last Fan-Out Wafer Level Packaging
Amy Lujan – SavanSys Solutions LLC
14) Multi Beam Full Cut Dicing of Thin Si IC Wafers
Jeroen van Borkulo, Paul Verburg, and Richard van der Stam –ASM Pacific Technologies

2215) A New Method for 3D Microstructure Fabrication via Ionic Wind
Shangru Zhou, Guoliang Li, Huai Zheng, and Sheng Liu –Wuhan University16) A Unique Temporary Bond Solution Based on
a Polymeric Material Tacky at Room Temperatureand Highly Thermally Resistant Application Extension from 3D-SIC to FOWLP
Alain Phommahaxay, Goedele Potoms, Julien Bertheau,
Pieter Bex, Fabrice Duval, Arnita Podpod, Teng Wang, Greet
Verbinnen, Gerald Beyer, Erik Sleeckx, Eric Beyne – IMEC;
Atsushi Nakamura – Fujifilm Electronic Materials Europe N.V.;
Yoshitaka Kamochi – Fujifilm Corporation17) 3D Printed Out-of-Plane Antennas for Use on
High Density Boards
Mohd Ifwat Mohd Ghazali, Saranraj Karuppuswami,
Amanpreet Kuar, Jennifer Byford, James Lennon, and Premjeet
Chahal – Michigan State University
Wednesday, May 31, 2017
Session 38: Interactive Presentations 2
2:00 PM - 4:00 PM
Committee: Interactive Presentations
Room: Northern Hemisphere Foyer
Session Co-Chairs:
Nam Pham – IBM Corporation
Patrick Thompson – Texas Instruments, Inc.
Eric Beyne – IMEC
Richard Rao – MicroSemi
1) Exploring DDR4 Address Bus Design for High
Speed Memory Interface
Nanju Na, Juan Wang, Sean Long, Changyi Su, Thomas To, andYong Wang – Xilinx, Inc.
2) Demonstration of High Electrical Reliability of
Sub-2 Micron Cu Traces Covered with Inorganic
Dielectrics for Advanced Packaging Technologies
Hiroshi Kudo, Ryohei Kasai, Jyunichi Suyama, Mitsuhiro Takeda,
Yumi Okazaki, Haruo Iida, Daisuke Kitayama, Toshio Sasao,
Kouji Sakamoto, Hiroaki Sato, Shouhei Yamada - Dai Nippon
Printing Co., Ltd.
3) The Comparison of Package Design and Electrical Analysis in Mobile Application
Tsun-Lung Hsieh, Po-Chih Pan, Chih-Yi Huang, Ming-Fong
Jhong, and Chen-Chao Wang – Advanced Semiconductor
Engineering, Inc.; Yuan-Hsi Chou – University of Texas, Austin
4) Multi-band Harmonic RF Tags for Barcode Applications in a Cluttered Environment
Saranraj Karuppuswami, Mohd Ifwat Mohd Ghazali,
Amanpreet Kaur, and Premjeet Chahal – Michigan State
University
5) High-Band AlN Based RF-MEMS Resonator for
TSV Integration
Nan Wang, Yao Zhu, Chengliang Sun, Mingbin Yu, Geng Li
Chua, Srinivas Merugu, Navab Singh, and Yuandong Gu –Institute of Microelectronics, A*STAR6) Equalization Enhancement Approaches for
PAM4 Signaling for Next Generation Speeds
Jiayi He, Nana Dikhaminjia, Mikheil Tsiklauri, and James
Drewniak – Missouri University of S&T; Bhyrav Mutnury andArun Chada – Dell, Inc.
7) Data Transfer Performance Analysis and Enhancement of Critical 3D Interconnects in a 3D
SIP based on Communication Channel Modeling
Methodology
Min Miao, Zhensong Li, Xiaoyang Duan, and Tianfang Chen –Beijing Information Science and Technology University; Xiaole
Cui, Yufeng Jin, Huan Liu, and Xin Sun – Peking University8) A Characterization Method for Interfacial
Delamination of Copper/Epoxy Mold Compound
Specimens Under Mixed Mode I/III Loading
V N N Trilochan Rambhatla, David Samet, Scott R. McCann,and Suresh K. Sitaraman – Georgia Institute of Technology
9) Low Temperature Ultrasonic Bonding of Cu/
Sn Microbumps with Au Layer for High Density
Interconnection Applications
Qinghua Zeng, Yong Guan, Jing Chen, and Yufeng Jin – Peking
University10) Chip-Scale SERF Atomic Magnetometer without
Magnetic Shield
Ling Lu, Jintang Shang, Zhihua Pan, and Yu Ji – Southeast
University11) Numerical Simulations of Joint-to-Joint Temperature Variation during Thermo-Compression
Bonding
Depayne Athia and Michael Mayer – University of Waterloo;
Alireza Rezvani, Horst Clauberg, and Ivy Qin – Kulicke andSoffa, Inc.
12) The Complete Packaging Reliability Studies
through One Digital Image Correlation System
Yuling Niu and Jing Wang – State University of New York at
Binghamton; Seungbae Park – State University of New York,
Binghamton
13) Resistometric Characterization of the Interface
between Au Wire Bonds to AlCuW Bond Pads
Steve Kilgore and Craig Gaw – NXP Semiconductors
14) Comparison and Consistency of On-PCB
Microstrip Line Modeling by 3D Fullwave and 2D
Quasi-Static Approaches for High Speed Packaging
System Signal Integrity Simulations
Zhaoqing Chen – IBM Corporation
15) Real-Time Diagnosis of Wire Degradation
Based on Digital Signal Analysis
Jinwoo Lee and Daeil Kwon – Ulsan National Institute of
Science & Technology
Thursday, June 1, 2017
Session 39: Interactive Presentations 3
9:00 AM - 11:00 AM
Committee: Interactive Presentations
Room: Northern Hemisphere Foyer
Session Co-Chairs:
Mark Eblen – Kyocera America, Inc.
Swapan Bhattacharya – Engent Inc.
Tz-Cheng Chiu – National Cheng Kung
University
Frank Wei – Disco Japan
1) Electrical Transmission Properties of HBM Interface on 2.1-D System in Package Using Organic
Interposer
Yutaka Uematsu and Nobuyuki Ushifusa – Hitachi, Ltd.;
Hitoshi Onozeki – Hitachi Chemical Co., Ltd.
2) The Use of Single Layer MIS in Modern Assembly
Kohan Lin, Albert Lan, Mark Liao, and Boxiang Fang –Siliconware Precision Industries Co., Ltd.
3) Physical and Electrical Characterization of 3D
Embedded Capacitor: A High-Density MIM Capacitor Embedded in TSV
Ye Lin and Chuan Seng Tan – Nanyang Technological
University4) Electrical and Thermal Simulation of SWIFT™
High Density Fan-out PoP Technology
Curtis Zwenger, Bora Baloglu, George Scott, and Mike
Kelly – Amkor Technology, Inc.; WonChul Do, JiHun Yi, and
WonGeol Lee – Amkor Technology, Korea
5) High Reliability Challenges with Cu Wire Bonding
for Automotive Devices in the AEC-Q006
JunHo Jeon, SungHo Jeon, SeokHo Na, Mina Mo, Kwangmo
Lim, DaeByoung Kang, and JinYoung Kim – Amkor Technology,Inc.
6) Development of Die Attachment Technology
for Power IC Module by Introducing Indium into
Sintered Nano-Silver Joint
Chun An Yang and C. Robert Kao – National Taiwan
University; Hiroshi Nishikawa – Osaka University7) Effect of Nickel-Coating Modified CNTs on the
Dopant Dispersion and Performance of BGA Solder
JointsHuayu Sun and Yan-Cheong Chan – City University of HongKong; Xiao Hu – HiSilicon Technologies; Fengshun Wu –Huazhong University of Science and Technology
8) Assessing the Reliability of High Temperature
Solder Alternatives
Maan Z. Kokash, Rajesh S. Sivasubramony, Jorge L. Then
Cuevas, Angelo F. Zamudio, and Peter Borgesen – Binghamton
University; Alfred A. Zinn, Randall M. Stoltenberg, Jerome
Chang, Y.-L. Tseng, and Dan Blass – Lockheed Martin
9) High Performance Silver Alloy Bonding Wire forMemory Devices
Tetsuya Oyamada, Tomohiro Uno, and Takashi Yamada –Nippon Steel & Sumitomo Metal Corporation; Daizo Oda –Nippon Micrometal Corporation

Wednesday & Thursday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 10-17 for location.

Interactive Presentations: Thursday, June 1, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m., and Friday, June 2, 8:30 a.m. - 10:30 a.m.

10) Low Pressure Solid-State Bonding Using Silver
Preforms for High Power Device Packaging
Jiaqi Wu and Chin C. Lee – University of California, Irvine11) Fabrication, Characterization and Comparisonof FR4-Compatible Composite Magnetic Materials
for High Efficiency Integrated Voltage Regulatorswith Embedded Magnetic Core Micro-Inductors
Mohamed Bellaredj, Sebastian Mueller, Anto Davis, Paul Kohl,
and Madhavan Swaminathan – Georgia Institute of Technology;
Yasuhiko Mano – Ibiden12) The Novel Failure Mechanism of the Polymer
Ball Interconnected CBGA under Board Level Thermal Mechanical Stress
Jeffrey ChangBing Lee, Cheng-Chih Chen, Dem Lee, Cherie
Chen, and Alice Lin – iST-Integrated Service Technology, Inc.
13) Development of Double Side Protection Processwith Bump Support Film (BSF) and Backside Coating Tape for WLP
Masanori Yamagishi, Tomotaka Morishita, Motoki Nozue,
Akinori Sato, Keisuke Shinomiya, and Shinya Takyu – Lintec
Corporation
14) Design of Miura Folding-Based Micro-Supercapacitors as Foldable and Miniaturized Energy
Storage Units
Bo Song, Yun Chen, Kyoung-sik Moon, and C. P. Wong –Georgia Institute of Technology15) Assembly and Reliability Challenges for Next
Generation High Thermal TIM Materials
Chi-An Pan, Chi-Tung Yeh, Wei-Chun Qiu, Rong-Zheng Lin,
Liang-Yih Hung, Kong-Toon Ng, C. F. Lin, C. Key Chung, DonSon Jiang, and C. S. Hsiao – Siliconware Precision Industries
Co., Ltd.
16) Low Temperature Curable Polyimide Film
Properties and WLP Reliability Performance with
Various Curing Conditions
Yu Chuan (Steven) Chen, Katch Wan, Chen An Chang, andRick Lee – Siliconware Precision Industries Co., Ltd.
17) The Effect of Polymer Rebound on SnBi58
Solder ACFs Joints Cracks during a Thermo-Compression Bonding
Shuye Zhang and Kyung-Wook Paik – Korea Advanced
Institute of Science & Technology
Thursday, June 1, 2017
Session 40: Interactive Presentations 4
2:00 PM - 4:00 PM
Committee: Interactive Presentations
Room: Northern Hemisphere Foyer
Session Co-Chairs:
Ibrahim Guven – Virginia Commonwealth
University
Mark Poliks – Binghamton University
Nancy Iwamoto – Honeywell
Jai Agrawal – Purdue University
1) Equivalent Thermal Conductivity Model Based
Full Scale Numerical Simulation for Thermal Management in Fan-Out Packages
Ningyu Wang, Yudan Pi, Wei Wang, and Yufeng Jin – Instituteof Microelectronics, Peking University
2) Local Stress Analysis by XRD Single Crystal
Method and Kossel Diffraction Applied to a Flip
Chip Structure
Anne-Laure Lebaudy, Manuel Fendler, and Wiyao Kpobie –CEA-Leti; Raphaël Pesci – Ecole Nationale Supérieure des Artset Métiers3) Study of Annular Copper Filled TSVs of Sensor
and Interposer Chips for 3D Integration
Cao Li and Peng Fei – Huazhong University of Science &Technology; Sheng Liu and Huai Zheng – Wuhan University
4) Investigations on the Pumping Behaviors of Copper Filler in Through-Silicon-vias (TSV)Fei Su, Ruixia Yao, Tenghui Li, and Xiaoxu Pan – Beijing
University of Aeronautics and Astronautics
5) Warpage Prediction Methodology of ExtremelyThin Packages
Zhongli Ji, Yangming Liu, Anna Wu, Ning Ye, Hem Takiar, andPeng Chen – SanDisk
6) A Design Study of 5G Antennas Optimized Using
Genetic Algorithms
VIncens Gjokaj, John Doroshewitz, Jeffrey Nanzer, andPremjeet Chahal – Michigan State University7) Cu-In-Microbumps for Low-Temperature Bonding of Fine-Pitch-Interconnects
Steffen Bickel, Iuliana Panchenko, Joerg Meyer, and Volker
Neumann – Technical University Dresden; Wieland
Wahrmund and M. Juergen Wolf – Fraunhofer IZM8) Via-in-Trench: A Revolutionary Panel-Based
Package RDL Configuration Capable of 200-450
IO/mm/layer, an Innovation for More-than-Moore
System Integration
Fuhan Liu, Chandrasekharan Nair, Hao Lu, Rui Zhang, Hang
Chen, Venky Sundaram, and Rao Tummala – Georgia Instituteof Technology; Atsushi Kubo and Tomoyuki Ando – Tokyo
Ohka Kogyo; Kwon Sang Lee – Disco Corporation
9) Simulation Analysis of a Conformal Patch Sensor
for Skin Tension and Swelling Detection
Ruiqi Lim, Ming-Yuan Cheng, Ramona Damalerio, and Weiguo
Chen – Institute of Microelectronics, A*STAR10) Effect of Material Properties of Double Layer
Non Conductive Films (D-NCFs) on the Reflow Reliability of Ultra Fine-Pitch Cu-Pillar/Sn-Ag Micro
Bump Interconnection
SeYong Lee, JiWon Shin, and Kyung-Wook Paik – Korea
Advanced Institute of Science & Technology; Woojeong Kim
and Taejin Choi – Doosan11) Wafer-Level Micro Alkali Vapor Cells with
Anti-Relaxation Coating Compatible with MEMS
Packaging for Chip-Scale Atomic Magnetometers
Yu Ji, Jintang Shang, Qi Gan, and Lei Wu – Southeast University
12) Low-Temperature High-Throughput AssemblyTechnology for Transducer Array in Medical Imaging Applications
Hoang-Vu Nguyen, Nu Bich Duyen Do, and Knut
Aasmundtveit – University College of Southeast Norway
13) Highly Efficient and Stable Quantum Dot Light
Emitting Diodes Optimized by Micro-Packaged
Luminescent Microspheres
Kai Wang and Xiaowei Sun – Southern University of Scienceand Technology; Xiaobing Luo – Huazhong University of
Science and Technology; Sheng Liu – Wuhan University
Friday, June 2, 2017
Session 41: Student Interactive Presentations
8:30 AM - 10:30 AM
Committee: Interactive Presentations
Room: Northern Hemisphere Foyer
Session Co-Chairs:
Yang Liu – IBM Corporation
Li Ming – ASM
Vaidyanathan Chelakara – Ciena Corporation
Suresh K. Sitaraman – Georgia Institute ofTechnology
1) Stress Analysis of Flexible Packaging for the Integration of Electronic Components within Woven
TextilesMenglong Li, John Tudor, Russel Torah, and Steve Beeby –University of Southampton
2) Signal Integrity Analysis of Silicon/Glass/Organic
Interposers for 2.5D/3D Interconnects
Sumin Choi, Joungho Kim, Junyong Park, and Daniel H. Jung –Korea Advanced Institute of Science & Technology; Heegon
Kim – Missouri S&T; Kiyeong Kim – Samsung Electronics
Company, Ltd.
3) A Study on the Fabrication of Electrical Circuits
on Fabrics using Cu pattern Laminated B-stage
adhesive Films for Electronic Textile Applications
Seung-Yoon Jung and Kyung-Wook Paik – Korea Advanced
Institute of Science & Technology4) Electrically Testing Non-Underfilled Flip Chip
Assemblies- Impacts on Interconnect Integrity
Antoine Cloutier and David Danovitch – Université deSherbrooke; Benoit Foisy – IBM Corporation
5) Effects of Anisotropic Conductive Films (ACFs)
Gap Heights on the Bending Reliability of Chipin-Flex (CIF) Packages for Wearable Electronics
Applications
Ji-Hye Kim, Tae-Ik Lee, Dal-Jin Yoon, Taek-Soo Kim, andKyung-Wook Paik – Korea Advanced Institute of Science &Technology6) A Study on the Fine Pitch Flex-on-Flex (FOF)
Assembly Using Flux Added Nanofiber Solder
Anisotropic Conductive Films (ACFs) and ThermoCompression Bonding Method
Ji-Soo Lee, Ji-Hye Kim, and Kyung-Wook Paik – Korea Advanced Institute of Science & Technology
7) Infrared (IR) Soldering of Metallic Nanowires
Jirui Wang, Fan Gao, and Zhiyong Gu – University of Massachusetts, Lowell8) Stretchable and Electrically Conductive Composites Fabricated from Polyurethane and Silver Nano/
Microstructures
Bo Song, Kyoung-sik Moon, and C. P. Wong – Georgia Instituteof Technology9) Numerical and Experimental Study of Fan-Out
Wafer Level Package Strength
Cheng Xu and Zhaowei Zhong – Nanyang Technological
University; Won Kyoung Choi – STATS ChipPAC, Inc.
10) Effects of Passivation Layer and Electroplating
Parameters of Copper Film on Wafer Warpage during Thermal Process
Gong Cheng, Heng Li, Weibo Zhang, Gaowei Xu, and Le Luo –Shanghai Institute of Microsystem and Information Technology
11) Development of Mechanical Locking MicroAnchor Structures for a QFN Package Application
Yu-Lung Huang, Wei-Chih Lin, Mano Ajayan, and Bao-Hui
Chang Chien – National Sun Yat-Sen University12) Reliability of Cu/NiFe and Cu/Ni Metaconductor Devices for RF Applications
Timothy Clingenpeel and Yong-Kyu Yoon – University of
Florida13) A New Fan-Out Package Structure Utilizing the
Self-Alignment Effect of Molten Solder to Improve
the Die Shift and Enhance the Thermal Properties
Hwan-Pil Park, Jae-Yong Park, Gwancheol Seo, and Young-Ho
Kim – College of Engineering / Hanyang University
14) Toughening Underfills by Stress-Absorbing CoreShell Fillers
Chia-Chi Tuan, Kyoung-Sik Moon, and Ching-Ping Wong –Georgia Institute of Technology
15) Thermal Characteristic of Sn-MWCNT Nanocomposite Solder in LED Package
Choong-Jae Lee, Jae-Jung Moon, Kwang-Ho Jung, and SeungBoo Jung – Sungkyunkwan University16) An Evaluation of Effects of Molding Compound
Properties on the Reliability of Ag Wire Bonded
Components
Keisuke Yazawa – Purdue University; Carol Handwerker, John
Blendell, Alexander Campbell, Wenhao Chen, Azzedin Jackson,
and Matthew Parsons – Purdue Univesity; Peng Su – Juniper
Networks17) A Nonlinear Transmission Line Based Harmonic
RF TagMohd Ifwat Mohd Ghazali, Saranraj Karuppuswami, Amanpreet
Kaur, and Premjeet Chahal – Michigan State University18) Numerical Analysis and Optimization of Thermal Performance of LED Filament Light Bulb
Jie Liu, Huai Zheng, and Sheng Liu – Wuhan University; Chunlin
Xu – Huazhong University Of Science And Technology19) Effective and Efficient Modeling of Differential
Vias Using Semi-Empirical Approach
Fanghui Ren – Oregon State University; Kevin Cai, Chunchun
Sui, Jayaprakash Balachandran, and Bidyut Sen – Cisco Systems,
Inc.
20) Design of Low-Profile Integrated Transformer
and Inductor for Substrate-Embedding in 1-5kW
Isolated GaN DC-DC Converters
Haksun Lee, Vanessa Smet, Pulugurtha Markondeya Raj, and
Rao Tummala – Georgia Institute of Technology21) Stretchable Capacitive Strain Sensors Based on a
Novel Polymer Composite Blend
Todd Houghton, Jignesh Vanjaria, Thomas Murphy, and Hongbin Yu – Arizona State University22) Thermal and Mechanical Analysis of 3D Glass
Packaging for Automotive Cameras
Daniel Struk, Peter Hesketh, Chintan Buch, Klaus Wolter, and
Rao Tummala – Georgia Institute of Technology23) Miniaturization of Planar Packaged Inductor
Using NiZn and Low Cost Screen Printing TechniqueColin Pardue, Mohamed F. Bellaredj, Anto K. Davis, and Madhavan Swaminathan – Georgia Institute of Technology

Thursday & Friday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 14-21 for locations.

23

2017 TECHNOLOGY CORNER EXHIBITS AND INTERACTIVE PRESENTATIONSTechnology Corner Exhibits
Wednesday, May 31
9:00 a.m. - 12:00 Noon / 1:30 p.m. - 6:30 p.m.
Thursday, June 1
9:00 a.m. - 12:00 Noon / 1:30 p.m. - 4:00 p.m.
Northern Hemisphere A – CInteractive Presentation Sessions

Wednesday, May 31
Session 37: 9:00 a.m. - 11:00 a.m. / Session 38: 2:00 p.m. - 4:00 p.m.
Thursday, June 1
Session 39: 9:00 a.m. - 11:00 a.m. / Session 40: 2:00 p.m. - 4:00 p.m.
Friday, June 2
Session 41: 8:30 a.m. - 10:30 a.m.
Northern Hemisphere Foyer, 5th Floor

24

TECHNOLOGY CORNER EXHIBITORS
3D Systems Packaging ResearchCenter (PRC)
Georgia Institute of Technology
813 Ferst Drive, NW
Atlanta, GA 30332-0560
Phone: +1 404-894-9097
Fax: +1 404-894-3842
www.prc.gatech.edu
Contact: Dr. Venky Sundaram
Prof. Rao R. Tummala
Email: vs24@gatech.edu
rao.tummala@ece.gatech.edu
Booth 320
The 3D Systems Packaging Research Center(PRC) at the Georgia Institute of Technology
is an Industry-Centric Global Academic Centerdedicated to leading-edge research, education ofhighly-interdisciplinary students and global industry
collaborations in the System-on-a-Package(SOP) vision to enable highly miniaturized, megafunctional systems in a single package. Led by Prof.
Rao Tummala, the PRC’s research encompasses
advanced 3D systems packaging technologies
including: electrical, mechanical and thermal
design; ultra-thin and ultra-high density glass
interposers and packages; ultrafine pitch chip-leveland board-level interconnections; passive andactive components and integration into power,
RF, photonic and analog modules. The PRC
model for industry collaboration is enabled by aworld-class team of cross-disciplinary academic
and research faculty, students, visiting industry
engineers, and supply-chain manufacturers. The
current industry consortium at PRC consists ofthe most comprehensive industry ecosystem
of material and tool suppliers, substrate andassembly manufacturers, and end users in awide variety of consumer and high performance
applications including high performance cloudcomputing and networking. New applications
being integrated into the consortium are new eraof automotive electronics that include connectivity
and infotainment, autonomous driving andall-electric cars requiring high power and hightemperature electronics. Companies can join
the PRC consortium for a single membership fee
to access all the programs. Benefits to industry
include intellectual property rights, technology
transfer, access to students for recruiting, oneon-one company-to-faculty relationships, stateof-the-art R&D facilities, advanced technology
prototypes, and more.
Advance Reproductions Corp
100 Flagship Dr.
North Andover MA, 01845
Phone: +1 978-685-2911
www.advancerepro.com
Contact: Don Robinson
Email: d.robinson@advancerepro.com
Booth 411
Advance Reproductions Corporation is a leading
supplier of superior, large-area and optical
Photomasks and Phototools. Innovative by
nature we strive tirelessly to collaborate withour customers on their complex requirements.
Our seasoned staff of experts and our creative
approach to each and every request is what sets
us apart. Working with unique requirements andcomplex patterning requests as well as offering
prototypes and high volume patterning wewelcome the challenge.www.advancerepro.com

AGC
4375 NW 235th Avenue
Hillsboro, OR 97124
Phone: +1 714-745-3193
Fax: +1 503-844-9308
www.agcem.com
Contact: Vern Stygar
Email: vstygar@agcem.com
Booth 309
AGC is a leader of glass, fluorinated polymers andquartz for the world’s automotive and electronics
device industries. AGC provides specialized
formulations of alkali-free alumino-borosilicate
glass with a wide range of CTE’s suitable forLED, MEMS, and glass interposer for the next
generation high frequency electronic substrates.
Our high volume capability for glass EN-A1 andvalue-added services such as vias drilling, ARcoatings, and via fill technologies makes AGC avaluable partner for your next generation mobile,
IoT or Life Science product. AGC’s premier
synthetic quartz with unparalleled formulation
control results in the lowest insertion loss andnearly zero autofluorences of any materials
now available on the market. Because of AGC’s
synthetic quartz has unparalleled low loss,
outstanding the electrical performance for highfrequency circuits can be achieved. In addition
AGC’s synthetic quartz low auto fluorescencemakes this AGC’s AQ an excellent substrate forphotonic applications in Lab on a Chip reactors.
AGC’s fluorinated polymer is ideally suited for
dielectric coatings, or creating micro or nanosized vias for Lab on a Chip applications in the Life
Science technologies sector. AGC’s fluorinatedpolymer is highly transparent to 250 nanometers.
AI Technology Inc.
70 Washington Rd.
Princeton Junction, NJ 08550
Phone: +1 609-799-9388
Fax: +1 609-799-9308
www.aitechnology.com
Contact: Maurice LeBlon
Email: mleblon@aitechnology.com
Booth 202
For over 30 years, AI Technology, Inc. (AIT) has
provided adhesive films, available as electricallyconductive or non-electrically conductive, with
low to zero interface stress for ultimate reliability
and, representative of our Thermal Interface
Materials (TIM) product line, unparalleledthermal management. AIT manufactures TIM innumerous form factors, such as greases, gels andvariously sized dry or tacky pads. AIT’s adhesive
films are critical to commercial and industrial
semiconductor, electronic and microelectronic
applications. Our diverse product line includes
molecularly flexible epoxy adhesives for die andsubstrate attach and bonding, adhesives andunderfills for multi size die bonding, DAF and
DDAF for stack-chip packaging and flip-chipbonding and underfilling and high temperaturesingle and multi chip module die bonding past
230ºC. AIT’s non-adhesive products include
conformal coatings for ultimate moisture and/or humidity protection as well as UV resistant
but PVDF transparent coatings with or without
corrosion retardants. AI Technology, Inc. (AIT)
stands behind our time-tested products, however
we are continually innovating new materials
solutions. Released in 2015, AIT’s Wafer

Processing Adhesive (WPA) is a temporary film
format high temperature bonding adhesive forthin wafer processing of bonding device wafer tocarrier wafer. Additionally, our newest research
has yielded higher performing and lower cost
solderable flexible circuit substrate materials to
replace polyimide-based organic copper-cladlaminates in high frequency microwave circuits.
Akrometrix, LLC
2700 NE Expressway
Building B, Suite 500
Atlanta, GA 30345
Phone: +1 404 486-0880 Ext. 21
Fax: +1 404-486-0890
www.akrometrix.com
Contact: Eric Moen +1-770-807-4707
Email: sales@akrometrix.com
Booth 220
Akrometrix manufactures, sells, and services
worldwide: Thermal warpage metrology systems-50°C to 300°C; Thermal strain metrology
systems 25°C to 300°C; Low cost room
temperature warpage metrology systems; Unique
software solutions and reports to enable effective
use of warpage/strain data; Test services forthermal warpage and strain metrology
Alpha Novatech, Inc.
473 Sapena Ct. #12
Santa Clara, CA 95054
Phone: +1 408-567-8082
Fax: +1 408-567-8053
www.alphanovatech.com
Contact: Glenn Summerfield
Email: sales@alphanovatech.com
Booth 402
Alpha Novatech, Inc. is your partner for Thermal
Solutions. We offer a wide variety of standard
heat sinks and accessories. Our product line
includes natural convection, forced convection,
and active heat sinks. We also offer various
attachment methods and hardware for almost
any application. In addition, we can offer free heatsink thermal simulations, standard or custom heatsinks in prototype to production quantities, quick
and easy customization without NRE fees, whilefeaturing short lead times. Standard parts arecarried in stock. Lead times for custom parts of
1–2 weeks are possible for initial quantities.
AMICRA Microtechnologies GmbH
Wernerwerkstr. 493049 Regensburg, Germany
Phone: +49-941-208209 0
Fax: +49-941-208209 9
www.amicra.com
Contact: Dr. Johann Weinhaendler
Email: sales@amicra.com
Booth 504
AMICRA Microtechnologies is a worldwide
leading supplier of high precision Die Attach
Equipment specializing in submicron placement
accuracy (±0.3µm@3s). Equipment offering
supports both Die Attach and Flip Chip bonding
processes including the following capability: in-situ
eutectic bonding, dynamic alignment, heated
tool, pulse heating, laser heating, volumetric andjet dispensing, active bond force control, highspeed solutions, in-situ UV curing, 550x600mm
bonding area, quantitative tilt calibration system,25

etc. Market focus: Opto, Silicon Photonics, AOC,
VCSEL, Laser Diode, WLP, 2.5D/3D IC, TSV,
TCB, Fan-out/EWLP. Other products: High
Speed Wafer Inking and inspection, Gel Fill Lineand Custom Solutions.
Amkor Technology, Inc.
2045 E. Innovation Circle
Tempe, AZ 85284
Phone: +1 480-821-5000
www.amkor.com
Contact: Debi Polo
Email: debi.polo@amkor.com
Booth 400
Amkor Technology is one of the world’s
largest and most accomplished providers ofsemiconductor packaging and test services.
Founded in 1968, Amkor pioneered theoutsourcing of IC assembly and test and is a
strategic manufacturing partner for the world’s
leading semiconductor companies, foundries
and electronics OEMs. Our solutions enable ourcustomers to focus on semiconductor design andwafer fabrication while utilizing Amkor as theirturnkey provider and their packaging technology
innovator.Amkor’s current operations include
more than 10M ft2 of floor space with production
facilities, product development centers andsales & support offices located in key electronics
manufacturing regions in Asia, Europe and theUnited States. Our broad package portfolio
includes leadframe, ball grid array, chip scale
and wafer level packaging. Also supported are
specialty packaging with unique development
and high volume production requirements(e.g., MEMS, sensors and SiP). Amkor is anindustry leader in advanced packaging with
development and production of large scale andcomplex 2.5/3D system solutions. Amkor’s
comprehensive manufacturing capability, scale andvision continue to strengthen our position as the“provider of choice” for semiconductor assembly
and test. For more information, visitwww.amkor.
com.
ASE Group
1255 E. Arques Ave.
Sunnyvale, CA 94085
Phone: +1 408-636-9500
Fax: +1 408-636-9485
www.aseglobal.com
Contact: Patricia MacLeod
Email: patricia.macleod@aseus.com
Booths 523, 525
With a proven track record spanning overthree decades, ASE, the OSAT market
leader, continues its tradition of manufacturingexpertise through orchestrated collaboration
with customers, suppliers and partners, alike.
Alongside a broad portfolio of establishedtechnologies, ASE is also delivering innovativeadvanced packaging, System-in-Package andMEMS solutions to meet growth momentum
across a broad range of end markets. For more
about our advances in Wire Bond, Systemin-Package, Wafer Level Packaging, Fan Out,
Flip Chip, MEMS & Sensors, and, 2.5D & 3D
technologies, all ultimately geared towards
applications to improve lifestyle and efficiency,
please visit :www.aseglobal.com.

AT&S Americas
1735 N. First St., Suite 245
San Jose, CA 95112
Phone: +1 408-573-1211
Fax: +1 408-573-1911
www.ats.net
Contact: Adriana Pace
Email: a.pace@ats.net
Booth 208
AT&S is a leading HDI and IC substrate producer
offering Embedded Component Packaging(ECP®) technology for embedding passives andbare ICs inside the laminate for IC packages
and printed circuit boards. Embedding provides
increased component density and smaller bodysize; improved signal integrity with embedded
capacitors located just microns directly below
the IC; thermal management with filled copper
vias directly on the die backside; improved shock& drop robustness; and hidden components
for security and reverse engineering resistance.
Additional components can be mounted on the
top and bottom surfaces and connected to theembedded components by copper-plated laser
micro-vias. AT&S has six manufacturing sites inAustria (2), China (2), India, and South Korea.
Embedding is available in the Leoben (Austria)
factory and in 2017 will also be available in the
Shanghai (China) factory. FC-BGA substrates
are produced in the Chongqing (China)
factory. AT&S announced participation in the
Horizon 2020 EU Research and Innovation
program to develop GaN-based modules
targeting the production of demonstrator GaN
power switches and CMOS drivers, as well as
new magnetic core materials that will enable

Be Part of The
Next Generation

I N T R O D U C T I O N : 	
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  Advantages include:
Wear
it.

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it.

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it.

Innovative IC, System-in-Package, andMEMS packaging portfolio for today’s
miniaturization, mobility, and IoT needs.

i) Bondingi) Bondingii)ii)Curing
Curingiii) Backside
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iii)
processing
processingiv)Debonding
Debondingiv)v)v)Cleaning
Cleaning

Wire
Bond

Flip
Chip

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2.5D
& 3D

FanoutSiP

BSI.T15140 series• Low-temperaturebonding
Include:	  	
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debonding	  • Reduced baking &cleaning times• Compatible with mechanicalor laser debondingAll	
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  Brewer	
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  [DATE]	
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 @asegroup_global

 aseglobal.com

w w w. b r e w e r s c i e n c e . c o m© 2017 Brewer Science, Inc.

26

switching frequencies up to 200 MHz.
AT&S is also participating in the Panel-Level
Packaging Consortium to implement fan-out
panel-level packaging (FOPLP).
Binghamton University   
Small Scale Systems Integration andPackaging (S3IP) Center
P.O. Box 6000
Binghamton, NY 13902-6000
Phone: +1 607-777-7270
Contact: Steve Czarnecki
Email: czar@binghamton.edu
Booth 317
The S3IP is a research and development
organization that addresses research challenges
in electronics packaging system design, processdevelopment, prototyping, and manufacturing
for academia and the microelectronics industry.
Located at Binghamton University, the Center
brings together partners from government,
industry and academia, providing opportunities forcollaborations that will advance microelectronics
research and development, with particular focus
on electronics packaging design and manufacturing
technology; thermal analysis and management forelectronics; characterization of materials, surfaces,and physical interfaces for electronics devices
and assemblies; and failure analysis and reliability
improvement for electronics. Subject areas
addressed include packaging of microelectronics,
2.5D/3D chip assemblies, power electronics, andintegrated photonics.
Cadence Design Systems, Inc.
2655 Seely Ave.
San Jose, CA 95134
Phone: +1 408-943-1234
Fax: +1 408-758-6610
www.cadence.com
Booth 100
Cadence enables global electronic design
innovation and plays an essential role in thecreation of today’s integrated circuits, packages,
and PCBs. Cadence® IC packaging and crossdomain co-design automation provide efficientsolutions in system-level co-design and advanced
mixed-signal packaging, delivering the automation
and accuracy to expedite the design process.
Cadence also offers an integrated system design
solution for TSMC’s advanced wafer-level
Integrated Fan-Out (InFO) packaging technology.
The solution includes implementation, signoff,and electro-thermal analysis tools that enableconcurrent multi-chip optimization for designs
incorporating InFO technology. With complex
advanced packages, designers are faced withpower integrity (PI) and signal integrity (SI)issues driven by increasing IC speeds and datatransmission rates combined with decreases
in power-supply voltages and denser, smaller
geometries. Stacked die and packages, higher
pin counts, and greater electrical performance
constraints are making the physical design ofsemiconductor packages more complex. To
address these issues, Cadence provides advanced
PI and power-aware SI Sigrity™ tools that can beused throughout the design process.

Camtek, USA, Inc.
48389 Fremont Blvd., Ste. 112
Fremont, CA 94538
Phone: +1 510-624-9905
Fax: +1 408-987-9484
www.camtek.com
Contact: Tommy Weiss
Email: tweiss@camtek.com
Booth 119
Camtek USA Inc. provides total inspection andmetrology for 3DIC and the advanced packaging
market. We provide automated solutions
dedicated for enhancing production processes
and yield in the semiconductor fabrication andpackaging industry. Camtek’s solutions range
from micro to nano by applying its technologies
to the industry-specific requirements. Camtek’sinnovations have made it a technological leader.
Camtek has sold more than 3,000 AOI systems in
34 countries around the world, winning significant
market share in all its served markets. Camtek ispart of a group of companies engaged in various
aspects of electronic packaging including advanced
substrates based on thin film technology, sample
preparation and digital material deposition.
Camtek’s uncompromising commitment
to excellence is based on Performance,
Responsiveness and Support.
Canon USA
3300 North 1st St.
San Jose, CA 95134
Phone: +1 408-468-2000
www.usa.canon.com/industrial
Contact: Doug Shelton
Email: sshelton@cusa.canon.com
Booth 418
Canon USA Industrial Products Division provides
advanced wafer & panel process equipment for
applications including semiconductor, powerdevice, advanced packaging & display. Canon
provides cost-effective processing solutions
including i-line & KrF optical lithography,
nanoimprint lithography & Canon Anelva
deposition equipment including the new FPA3030EX6 and FPA-3030i5+ steppers that aredesigned to extend advanced process capability
for ≤ 200 mm wafer processes. Canon also has
a variety of panel based lithography & deposition
solutions that can be extended to a variety of
applications. Contact semi-info@cusa.canon.com
for more info.
CEA LETI
17 Rue des Martyrs
38054 Grenoble cedex 9, France
Phone: +1 626 537 7270
www.leti.fr/en
Contact: Hughes Metras
Email: hughes.metras@cea.fr
Booth 307
CEA-LETI is an institute providing R&D andPrototyping services in the field of Micro andNanotechnologies. Capabilities include 8” and12” wafer process flows for advanced CMOS,
3D stacking, MEMS and Silicon Photonics. Basedin Grenoble, France, CEA-LETI has offices in
the US and Japan. Over the past ten years CEALETI has developed a wide range of expertise in
the fields of silicon interposers and high density
interconnects to address the needs of thesemiconductor industry in market segments suchas mobile telephones and low power computing.
Leti is working on hybrid bonding, wafer-towafer or chip-to wafer integration. Pitch of few
microns is envisioned, without underfill, room

temperature and ambient pressure bonding. Selfalignment using capillary force is also developed
for high precision, high throughput chip-to-wafer
bonding. With the support of its internal IC design
teams LETI provides industrial partners with aunique environment for validating new concepts
through models, new design tools, test vehicles
and implementing fully functional demonstratorssuch as wide I/O memory standard, 60 GHz
RF SOCs for video data transfer or photonic
interposers. Recently CEA-LETI has developed
CoolCube, an original technique for stacking
transistors sequentially in the same process flowfor 3D-VLSI. The technology is designed to allow
a connection of the stacked active layers on ananometric scale, with a very high density, due
to their alignment by a standard lithographic
process. CEA-LETI is embedded in a dynamic andinternational ecosystem that include European
and Global leaders.
Circuits Multi-Projets (CMP)
46 Avenue Felix Vialet
38000 Grenoble
FrancePhone: +33 476 57 46 17
Fax: +33 476 47 38 14
cmp.imag.fr
Contact: Dr. Olivier Guiller
Email: olivier.guiller@imag.fr
Booth 517
In the past few years CMP has been developing its
advanced packaging offers for prototyping. Bothactive and passive Silicon interposer solutions are
now available to designer as well as wafer-levelpost-processing for process modules integration(such as TSV and µ-pillars), enabling Silicon to
Silicon assemblies for 3D-IC applications. Since
1981, CMP is a Multi-Project Wafer service
organization in ICs, Photonic ICs and MEMS for
prototyping and low volume production. CMP
enables prototypes fabrication on industrial
processes at very attractive costs and offers it
great technical expertise in providing MPW andrelated services for Universities, Research Labsand Industrial companies prototyping. CMP canhandle low volume production, approximatelyfrom some dozens to some thousands pieces.
Advanced industrial technologies are madeavailable in CMOS, SiGe BiCMOS, HV-CMOS,
SOI, MEMS, 3D-IC, etc. CMP distributes thedesign rules for each technology and the standard
cell libraries for each specific software tool (designkits) free of charge and supports several CAD
software tools for both Industrial Companies
and Universities. More than 1000 Institutions
from more than 70 countries have been served,
more than 7000 projects have been prototyped
through a thousand runs, and 71 different
technologies have been interfaced.
CPS Technologies Corporation
111 S. Worcester St.
Norton, MA 02766
Phone: +1 407-341-3359
Fax: +1 508-222-0220
www.alsic.com
Contact: Tim Davis
Email: tim@jdm-associates.com
Booth 419
CPS Technologies Corporation is the worldwide
leader in the design and high-volume productionof AlSiC (aluminum silicon carbide) for highthermal conductivity (up to 1000 W/mK withembedded Pyrolytic Graphite) and devicecompatible thermal expansion. AlSiC thermal

13
27

management components manufactured by CPS
include hermetic electronic packages, heat sinks,
microprocessor & flip chip heat spreader lids,
Thermal substrates, IGBT base plates, cooler
baseplates, Pin Fin baseplates for hybrid electricvehicles, microwave & optoelectronic housings.
CST of America, Inc.
492 Old Connecticut Path, Suite 500
Framingham, MA 01701
Phone: +1 508-665-4400
Fax: +1 508-665-4401
www.cst.com
Contact: Megan Schmidt
Email: megan.schmidt@cst.com
Booth 308
CST of America, Inc. is the leading supplier of
3D electromagnetic simulation tools in North
America. CST’s products aid in the microwave/
RF and high speed design of many consumer,
industrial, aerospace and research levelcomponents and systems including interconnects,
packages, materials, wireless devices, and vehicles.
The software has an excellent 3D interface withrobust imports from all the major CAD and
EDA vendors. Huge cost savings are possible byreducing or eliminating the hardware prototype
stage of a design. Key results can be analyzed andoptimized based on user goals.
CVInc
990 N. Bowser, Suite 860
Richardson, TX 75081
Phone: +1 972-664-1568
Cell: +1 214-557-1568
Fax: +1 972-664-1569
www.covinc.com
Contact: Terence Q. Collier
Email: tqcollier@covinc.com
Booth 417
CVI offers advanced packaging turn-key solutions
for assembly and bumping. Quick turn solutions
included single die bumping, partial wafers,
complete wafers and reball on CSP and BGA’s.
Bumping materials include solder alloys, gold
stud bumps and copper pillars. Plating capabilities
include ENIG/ENIPIG/eCu and electrolytic
plating (Cu, Sn, Ni, Pb, Au and Pd) . Custom
QFN designs and modules (including open cavity).
Dummy die, substrates and interposers in silicon,
quartz, and alumina. Custom preforms for board
repair and modification.
DECA Technologies
7855 S. River Parkway, Suite 111
Tempe, AZ 85284
Phone: +1 480-345-9895
www.decatechnologies.com
Contact: Garry Pycroft
Email: garry.pycroft@decatechnologies.com
Booth 200
Deca Technologies is an electronic interconnect
solutions provider that offers fan-in and fan-out
wafer level chip scale packaging (WLCSP) services
to the semiconductor industry. Integrating solar
and semiconductor technology, we leverage
unique equipment, processes and operational
methods inspired by SunPower to addresssome of the significant barriers to the continued
adoption and growth of next generationinterconnects. Our portfolio of proprietary, gamechanging electronic interconnect solutions delivers
leadership capabilities in performance, cost andtechnology allied to a flexible manufacturing

28

process that enables 200mm and 300mm wafers
to be managed simultaneously. Deca’s process
significantly reduces cycle time and permits
multiple design iterations with minimal investment,
thereby enabling the adoption of wafer levelinterconnect technologies for a wide array ofsemiconductor device types.
DISCO Hi-Tec America, Inc.
3270 Scott Blvd.
Santa Clara, CA 95054-3011
Phone: +1 408-987-3776
Fax: +1 408-987-3785
www.discousa.com
Contact: Aris Bernales
Email: aris_b@discousa.com
Booth 410
For over 40 years, DISCO Hi-Tec America,
Inc. has been a leader in the semiconductor
industry in cutting (Kiru), grinding (Kezuru),
and polishing (Migaku) technologies. DISCO’s
focus has expanded beyond mechanical dicing
to include laser and plasma singulation. DISCO
continues to be the leader in wafer thinningand polishing/stress relief with technologies
such as SDBG enabling thinning of die to 20um
or less. To support the increasing complexity
in today’s packages, DISCO has also released
equipment capable of laser via drilling in nonsilicon transparent materials, silicon carbide ingot
slicing (KABRA), and laser lift off. In order tosupport research and development efforts, joint
development initiatives, and next generation
product prototyping, DISCO Hi-Tec America’s
KKM Services lab in Santa Clara offers capability
to process materials with our latest advanced
cutting, grinding, and polishing technologies.”
DOWA International Corp.
4320 Stevens Creek Blvd. Suite 125
San Jose, CA 95129
Phone: +1 408-236-7560
www.dowa-electronics.co.jp/en/index.
html
Contact: Hiromichi Asahara
Email: asaharah@dicny.com
Booth 103
DOWA is a Japanese material company ofnonferrous metal and the largest supplier of Ag
powder in the world. We offer Nano Ag sintering
paste for bonding applications. The advantagesof our Nano Ag paste are 1) High Thermal
Conductivity (>200W/mK), 2) Low Sintering
Temperature (175C-250C), 3) Sinter without
Pressure, and 4) High Shear Strength. We offer
variety of paste lineup and we can customize
our paste for your applications. For more detail
information, please visit booth#103.
Dow Electronic Materials
455 Forest Street
Marlborough, MA 01752
Phone: +1 508-481-5970
www.dowelectronicmaterials.com
Contact: Mark Markowski
Phone: +1 774-641-4969
markowski@dow.com
Booth 420
Dow Electronic Materials, a global supplier ofmaterials and technologies to the electronics
industry, brings innovative leadership to thesemiconductor, interconnect, finishing, display,
photovoltaic, LED and optics markets. Fromadvanced technology centers worldwide,
teams of talented Dow research scientists andapplication experts work closely with customers,

providing solutions, products and technicalservice necessary for next-generation electronics.
Dow’s portfolio includes metallization, dielectric,
lithography and assembly materials designed tomeet the most demanding needs for advanced
semiconductor packaging applications, such as
bumping, copper pillars and redistribution layer(RDL), passivation and underbump metallization(UBM) used for the latest fan-out wafer levelpackaging (FOWLP), flip chip, system in package(SiP), and 2.5D/3D chip packages.
Dynaloy – a Subsidiary of Eastman
Chemical Company
6445 Olivia Ln.
Indianapolis, IN 46226
Phone: +1 317-788-5694
Fax: +1 317-788-5690
www.dynaloy.com
Contact: Diane Scheele
Email: dscheele@eastman.com
Booth 513
Dynaloy develops, manufactures, and markets
world class advanced cleaning solutions for thesemiconductor industry. Thoroughly removing
photoresist and other residues is a critical partof enhancing device performance. In short,cleaning matters in this fast-paced and competitive
industry. That’s why Dynaloy offers custom
and stock formulations to tackle the full range
of jobs, from the least complicated to the mostchallenging. Whether you’re removing photoresist
or residue, Dynaloy’s portfolio includes products
for unique cleaning applications in the wafer levelpackaging market. Dynaloy offers the solutions
for silicon post-etch residue removal , Cu µ-pillar
bumping and fan-out wafer-level packaging(FO-WLP) photoresist removal. Our professional
staff is committed to helping engineers achieve
optimum performance through creative productdevelopment, chemical expertise, unmatchedtechnical support and steadfast customer service.
As a subsidiary of Eastman Chemical Company,
Dynaloy and Eastman combine responsiveness,material science expertise and vast resources tobe a world leader in cleaning technologies.
EV Group, Inc.
7700 S. River Parkway
Tempe, AZ 85284
Phone: +1 480-305-2400
Fax: +1 480-305-2401
www.evgroup.com
Contact: Carl Mann
Email: salesNorthAmerica@evgroup.
com
Booth 405
EV Group (EVG) is a leading supplierof equipment and process solutions forthe manufacture of semiconductors,
microelectromechanical systems (MEMS),
compound semiconductors, power devices,and nanotechnology devices. Key products
include wafer bonding, thin-wafer processing,lithography/nanoimprint lithography (NIL) andmetrology equipment, as well as photoresist
coaters, cleaners and inspection systems.
Founded in 1980, EV Group services andsupports an elaborate network of global
customers and partners all over the world. Moreinformation about EVG is available atwww.
evgroup.com.

29

ficonTEC
25 Calle Canela
San Clemente, CA 92673
Phone: +1 949-388-5800+1 949-300-7715
Fax: +1 949-388-1489
www.ficontec.com
Contact: Soon Jang
Email: soon.jang@ficontec.com
Booth 109
ficonTEC provides a wide range of micron- andsubmicron-precision test-and-measurement,
vision inspection, and assembly automation
systems for opto-electronic devices, fiber-optic
components, micro-optic devices, among
others. Such automation systems for applications
include, but are not limited to, submicronprecision LDB and die bonding, LDB stackingunstacking, submicron-precision micro-lensassembly (e.g., FAC, SAC, mirror, etc.), OE
component attachment, and integrated photonic
device assembly. ficonTEC is the recognizedindustry leader in SiPh device test, inspection, andassembly automation systems for various productdevelopment and production requirements.
Systems are designed with numerous assembly
processes in view for high-throughput, high-yield
precision automation production environment.
ficonTEC’s system products and platforms
are pre-engineered for specific applications,where each application can be optimized forthe unique needs of each customer, maximizing
their investment, and resulting in a competitive
advantage. ficonTEC also prides in assisting its
customers with developing their devices that are
conducive to automation through collaborative
product and/or process development activities,
leveraging its extensive experiences in opticaldevice/component processing technology. Pleasecome and discuss ficonTEC’s capabilities for yourapplication(s) at our booth.
Finetech
560 E. Germann Rd., Suite 103
Gilbert, AZ 85297
Phone: +1 480-893-1630
www.finetechusa.com
Contact: Jim Bishop or Robert Avila
Email: sales@finetechusa.com
Booth 503
Finetech supplies sub-micron accuracy bonders
for die attach, advanced packaging and microassembly applications. Manual, motorized andautomated models provide high process flexibility
within one platform -utilizing a modular, flexible
design. Bonding technologies include thermocompression, ultrasonic, eutectic, epoxy, sintering,
ACF/ACP, Indium and precision vacuum
die bonding. Applications areas cover opticalpackages, sensors, Si photonics, microLEDs,
C2W, Cu pillar, focal plane arrays, chip-on-glass,chip-on-flex and more. Finetech also provides
precision dispensers and advanced reworksystems for today’s challenging applications.
The deep process knowledge we have gained
through decades of experience adds value toour equipment. Our engineers work withcustomers to create effective solutions for specificapplications - they understand that “one size”
does not necessarily fit all.

FlipChip International
A Division of Huatian Technology
3701 E. University Dr.
Phoenix, AZ 85034
Phone: 602-431-4780
Fax: 602-431-6020
www.flipchip.com
Contact: Tony Curtis
Email: anthony.curtis@flipchip.com
Booth 415
FlipChip International - Huatian (FCI-HT): FCI-HT
supplies turnkey semiconductor assembly and test
services to the consumer, automotive, industrial
and medical industries. FCI-HT supports a wide
range of customers, frequently partnering withthem to engineer customized solutions including
expedite bumping and backend services on MultiProject Wafers. FCI-HT is a leader in wafer levelpackaging with patented technologies spanningfrom Cu Pillar Bumping, Spheron™ Wafer Level
Chipscale Packaging, and ChipsetT™ Embedded
Die Packaging.   FCI-HT is a division of HuatianTechnologies (HT). HT is among the top 6
OSATs in the world with over one billion dollars
in annual revenue. It is listed on the Shenzhen
Stock Exchange Market. Huatian has six ISO/TS16949 factories located in the US and China
offering a complete range of semiconductor
packaging and turnkey services.
Fraunhofer Center for Applied
Microstructure Diagnostics CAM
Heideallee 1906120 Halle (Saale), Germany
Phone: +49 345-55 89 130
Fax: +49 345-55 89 101
www.cam.fraunhofer.deContact: Prof. Dr. Matthias Petzold
Email: matthias.petzold@iwmh.
fraunhofer.de
Booth 218
We are a leading service provider of failure
diagnostics and material assessment forindustry including semiconductor technologies,
microelectronic components, microsystems
and nanostructured materials. We consider
the entire work flow from non-destructive
defect localization over high precision target
preparation to cutting edge nanoanalytics
supplemented by micro-mechanical testing, finite
element modeling and numerical simulation. We
support cooperation partners in introducing
innovative materials and technologies, improving
manufacturing process steps, securing reliable
field use of components, analyzing field returns,
and consequently optimizing manufacturing yield,
product quality, reliability, and cost efficiency.
Due to our close collaboration with leading
microelectronics manufacturers, we are able tosupport test and diagnostics equipment suppliersin exploring and evaluating upcoming markets andfuture application fields. We provide innovative
solutions for microstructure and failure diagnostics
instrumentation, problem-adapted analysis workflows and industry-compatible applications.

Fraunhofer Institute for Reliability
and Microintegration IZM
Gustav-Meyer-Allee 25
13355 Berlin, Germany
Phone: +49 30-46403-100
Fax: +49 30-46403-111
www.izm.fraunhofer.deContact: Georg Weigelt
Email: georg.weigelt@izm.fraunhofer.de
Booth 117
Invisible – but indispensable – nowadays nothingworks without highly integrated microelectronics
and microsystem technology. Reliable andcost-effective assembly and interconnection
technologies are the foundation of integratingthese in products. Fraunhofer IZM, a worldwide
leader in the development and reliability analysis
of electronic packaging technologies, provides its
customers with tailor-made system integration
technologies on wafer, chip and board level. Our
research also ensures that electronic systems are
more reliable, so that we can accurately predict
lifecycle.
FUJIFILM ELECTRONIC MATERIALS
80 Circuit Dr.
North Kingstown, RI 02852
Phone: +1 800-553-6546+1 480-987-7028
www.fujifilmusa.com
Contact: Sanjay Malik
Email: sanjay_malik@fujifilm-ffem.com
Booth 510
FUJIFILM Electronic Materials is a leading
supplier of advanced materials to the electronics
industry. We offer full complement of advanced
photoimageable and non-photoimageable
polyimide and PBO materials designed to meetcurrent and future packaging requirements, aswell as temporary bonding materials tailored for
demanding wafer thinning applications. Fujifilm
is demonstrating its innovative iACF anisotropic
conductor technology drawn from ourproprietary printing and metal substrate expertise.
Georgia Tech – Institute forElectronics and Nanotechnology
345 Ferst Dr. NW
Atlanta, GA 30318
Phone: +1 404-894-5100
Fax: +1 404-894-5028
www.ien.gatech.edu
Contact: Dean Sutter
Email: dean.sutter@ien.gatech.edu
Booth 518
Research, education, training, and shareduser facilities in the complementary fields ofelectronics and nanotechnology provides thefoundation for a broad range of advances inhealthcare, telecommunications, computing,consumer, industrial, transportation, agricultural,environmental, and national security applications.
IEN is well known for its deep expertise inelectronic design, modeling and simulation as
well as in technologies for devices, components,
sensors, energy harvesting, packaging, andtest, as well as being a provider of shared-user
facilities that are open to academia and industry
that support the needed fabrication, packaging,measurement and characterization of thesetechnologies.

29

GLOBALFOUNDRIES
2600 Great America Way
Santa Clara, CA 95054
Phone: +1 408 462 3900
www.globalfoundries.com
Contact: Ajit Dubey
Email: marketing@globalfoundries.
com
Booth 515
GLOBALFOUNDRIES is the world’s firstfull-service semiconductor foundry with atruly global footprint. Launched in 2009, thecompany has quickly achieved scale as thesecond largest foundry in the world, providing
a unique combination of advanced technology
and manufacturing to more than 250 customers.
With operations in Singapore, Germany and theUnited States, GLOBALFOUNDRIES is the only
foundry that offers the flexibility and security of
manufacturing centers spanning three continents.
The company’s five 300mm fabs and five 200mm
fabs provide the full range of process technologies
from mainstream to the leading-edge.
GLOBALFOUNDRIES is owned by Mubadala
Development Company..
HD MicroSystems, LLC
250 Cheesequake Road
Parlin, NJ 08859
Phone: +1 800-346-5656
www.hdmicrosystems.com
Email: Ronda.I.Johnson@dupont.com
Booth 319
HD MicroSystems is a joint venture of Hitachi
Chemical and DuPont Electronics specializingin liquid polyimide (PI) and polybenzoxazole(PBO) dielectric coatings. HDM will highlight
new low stress and low temperature curepolymeric materials for front-end wafer andback-end advanced packaging technologies for
Flip Chip, WLP, as well as interlayer dielectrics(ILD), stress buffer coatings (SB), redistribution
dielectrics layers (RDL) and wafer bonding
adhesives (temporary and permanent) for 3D/
TSV applications.
Henkel Electronic Materials
14000 Jamboree Rd.
Irvine, CA 91626
Phone: +1 714-368-8000
Fax: +1 714-368-2265
www.henkel.com/electronics
Contact: Janna Watzske
Email: electronics@henkel.com
Booth 302
Henkel Adhesive Electronics is a division of
global materials innovator, Henkel Corporation.
Headquartered in Irvine, California with sales,
service, manufacturing and advanced R&D centersaround the globe, Henkel AE is focused on
developing next-generation materials for a variety
of applications in semiconductor packaging,industrial, consumer, displays and emerging
electronics market sectors. A leader in die attach,underfill, solder, molding, printable ink andthermal management materials, Henkel AE hasdeveloped some of the industry’s most innovativeand enabling electronic material solutions.

30

Heraeus Electronics
301 N. Roosevelt Ave.
Chandler, AZ 85226
Phone: +1 480-589-0971
www.heraeus-electronics.com
Contact: James Wertin
Email: james.wertin@heraeus.com
Booths 312 & 314
Heraeus Electronics provides an innovative
product portfolio and trusted expertise inmatching for High Performance electronics. With
our knowledge in electronic packaging materials;
higher density, longer product life and superiorreliability in harsh conditions can be realized. Our
Materials Solutions will shorten your development
cycles, lower development costs, and bring next
generation products to market faster. Please
visit us to see our latest developments in Solder
Pastes, Sinter Pastes, Adhesives, Bonding Wires,
Hybrid Thick Film Pastes, Metal and Metal
Ceramic Substrates.
Hitachi Chemical Co., Ltd.
1-9-2, Marunouchi, Chiyoda-ku,
Tokyo 100-6606 JAPAN
Phone: +81-3-5533-6646
Fax: +81-3-5533-6983
www.hitachi-chem.co.jp
Contact: Shotaro Kato
Email: s-kato@hitachi-chem.co.jp
Booth 107
Hitachi Chemical is a leading company inproviding various materials used in advanced
semiconductor assembly packages such as
wafer level and panel level fan-out packages, 3D
packages, etc. In addition to those materials,
Hitachi Chemical provides “Open Laboratory”
located in Japan where any customers can utilize
advanced manufacturing and analytical equipment
to achieve an accelerated development forcomplex, advanced structures. The Open
Laboratory will relocate to more convenient
location, closer to Tokyo, in 2018. Our sales
offices are located around the world, withtechnical engineers stationed to support
customers in case of need. Please contact us if
you are interested in “Open Laboratory” andmaterials such as die bonding films, encapsulants(including compression molding and liquid
type encapsulants), temporary adhesives,
re-distribution layer materials, substrate materials
and much more.
Huntsman Advanced Materials
10003 Woodloch Forest Dr.
The Woodlands, TX 77380
Phone: +1 888-564-9318
Fax: +1 281-719-4032
www.huntsman.com/advanced_
materials
Contact: Petharnan Subramanian
Email: petharnan_subramanian@huntsman.com
Booth 204
Huntsman Advanced Materials provides
engineered solutions for our customers usinga wide range of high-performance thermoset
chemistries and formulations. Everyday ourscientists work with designers and engineers tobring lightweight, high-strength, durable products
to market and help solve increasingly complex
design issues. In the electronics market we
provide advanced organic protective solutions
to build, structure and assemble printed circuitboards and to encapsulate, insulate and bondelectrical and electronic components. Our

brands, such as Araldite® adhesives, Kerimid®
laminating systems, Arathane® polyurethane
adhesives and potting systems and Euremelt®
hot melt adhesives, are pioneers in the industry,
serving customers for more than 50 years. Our
customers benefit from sound technical expertiseand products that are tailor-made to meet theirrequirements.
i3 Electronics, Inc
1701 North Street
Endicott, NY 13760
Phone: +1 866-820-4820
Fax: +1 607-755-7000
www.i3electronics.com
Contact: Victor Hemingway
Email: victor.hemingway@
i3electronics.com
Booth 304
i3 Electronics, Inc., headquartered in Endicott,NY, is a vertically integrated provider of highperformance electronic solutions consisting ofdesign and fabrication of printed circuit boards &advanced semiconductor packaging; high speed
laminate expertise; advanced assembly services;
reliability & signal integrity reliability lab services;high speed back plane & press fit assembly;
and flex, rigid-flex & 2.5 & 3D die assembly. i3
product lines meet the needs of markets including
aerospace & defense, medical, high performancecomputing, industrial, telecom, semiconductor& test and alternative energy, with highly reliable
products built in robust manufacturing operations.
IBM Canada Ltd.
23 Airport Blvd
Bromont, Quebec
Canada J2L 1A3
Phone: +1 450-534-6496
Cell: +1 450-531-2474
www.ibm.com/assemblyContact: Luc Comtois
Email: assembly@ca.ibm.com
Booth 406
IBM Bromont is a world leader in semiconductor
packaging technology, products and services.
Now available to customers worldwide, we
invite you to take advantage of our experience,system level mindset, and skilled engineers to
execute your most advanced packaging andtest solutions. Tap into our deep competencies
as the industry continues to shift to custom
SoCs and SiPs. IBM is known for its multi-chippackaging and heterogeneous integration. We
offer full turnkey solutions from modelling andcharacterization through Burn-in and test. Our
test capability spans digital, analog, mixed signal,
RF as well as multi-site programming, test patternconversion, and load board design. We provide
high quality mechanical, thermal and electricaldesign (including high speed/SERDES, signal
integrity and power integrity), ensuring effective
execution of new and updated platforms. Services
include materials and process characterization,
optimized substrate design, and failure analysis
while package platforms range from large organic
substrates using high density interconnect tosilicon and glass interposers, and the corelesstechnologies. We invite you to discuss your next
generation requirements – our developments inareas such as silicon photonics are unrivaled. IBM
will help you deliver differentiated solutions whileproviding personalized, expert support to meeteven the toughest application goals.

Interconnect Systems, Inc.
741 Flynn Rd.
Camarillo, CA 93012
Phone: +1 805-482-2870
Fax: +1 805-482-8470
www.isipkg.com
Contact: Ken Roberson
Email: info@isipkg.com
Booth 520Interconnect Systems, Inc. (ISI), specializes inhigh-density module packaging and advanced
system-level interconnect solutions. ISI offers
design, qualification, and testing, coupled with fully
integrated in-house manufacturing. Capabilities
include: high-density PCB design, fine pitch SMT,
flip chip, wirebond assembly, IC packaging,custom molding, over molding, and automatedoptical inspection.
Invensas3025 Orchard Parkway
San Jose, CA 95134
Phone: +1 408 321 6000
Fax: +1 408 321 8257
www.xperi.com
Contact: Andrew Kim
Email: Andrew.kim@xperi.com
Booth 306
Invensas, a wholly owned subsidiary of Xperi
Corporation (Nasdaq: XPER), is the world’s
leading provider of advanced semiconductor
packaging and 3D interconnect technologies
that enable the next generation of electronics
products to be smaller, faster, lower power andcontain more functionality. Invensas solutions
can be found in DRAM memories, image
sensors, RF devices, MEMS sensors, processors
and mixed signal devices currently in highvolume production at leading OEMs, ODMs,
and IDMs and integrated into in billions ofelectronic products around the world, including
smartphones, tablets, laptops, PCs and data
center servers. Invensas technologies include
ZiBond®, a low temperature wafer-to-wafer or
die-to-wafer bonding, Direct Bond Interconnect(DBI®) wafer-to wafer or die-to-wafer bonding
with electrical interconnect, Bond Via Array™
(BVA®) advanced Package-on-Package andSystem-in-Package solutions, and xFD® multi-die
face-down packaging technology.
JSR Micro, Inc.
1280 N. Mathilda Ave.
Sunnyvale, CA 94089
Phone: +1 408-543-8800
Fax: +1 408-543-8964
www.jsrmicro.com
Email: atseng@jsrmicro.com
Booth 403
JSR’s unique THB series of negative tone thickfilm photoresists for RDL, micron bump, and Cu
pillar applications, along with our WPR seriesof dielectric coatings are ideal for WL-CSP, Flip
Chip, TSV, and other packaging technologies.
JSR materials provide excellent throughput, large
process margins, high aspect ratio solutions forfilm thicknesses from <10 to >100 micrometers
while being processed in standard TMAH
developer. Additionally, JSR offers exceptional
materials in the temporary bonding space –contact us to learn more.

Kulicke & Soffa
1005 Virginia Ave.
Fort Washington, PA 19034
Phone: +1 215-784-6786
Contact: Paul Keehn
Email: pkeehn@kns.com
Booth 102
Kulicke & Soffa Industries is a leading providerof semiconductor packaging and electronic
assembly equipment and solutions supporting the
global automotive, consumer, communications,computing and industrial segments. As a pioneerin the semiconductor space, K&S has provided
customers with market leading packaging
solutions for decades. In recent years, K&S has
expanded its product offerings through strategicacquisitions and organic development, adding
advanced packaging to handle the most advanced
TCB and FOWLP applications, electronics
assembly, wedge bonding and a broader range ofexpendable tools to its core Ball Bonder offerings.
Combined with its extensive expertise in process
technology and focus on development, K&S
is well positioned to help customers meet thechallenges of packaging and assembling the nextgeneration of electronic devices.
Kyocera America
1401 Route 52, Suite 203
Fishkill, NY 12524
Phone: +1 845-896-0480
Contact: Tony Soldano
Email: tony.soldano@kyocera.com
Booth 414
Kyocera International, Inc., Semiconductor
Components Group offers an extensive array oforganic FC-CSP / FC-BGA / SHDBU packages,
complex ceramic modules, embedded PWB,
and high-density PCBs for numerous applications
including RF/MW, ASICs, MPUs, graphics
processors, data centers, power semiconductors,
phased array radar, telecom, avionics and space.
Lasertec USA Inc.
2025 Gateway Place, Suite 430
San Jose, CA 95110
Phone: +1 408-437-1441
Fax: +1 408-437-1430
www.lasertec.co.jp/en/index.html
Contact: Yuji Asakawa
Email: Yasakawa@lasertecus.com
Booth 519
Lasertec Corporation, founded in 1960,
has grown into a world leading innovator of
inspection and metrology equipment serving
the global semiconductor and related industries.
Guided by its corporate philosophy, “Create
unique solutions; Create new value,” Lasertec
has created several new tools to help companies
developing and manufacturing the next generationof semiconductors – 3DICs with TSV technology.
Tools being highlighted at ECTC 2017 are
the BGM300, BIM300, and the EZ300. The
BGM300 is an IR based metrology tool capableof measuring all the critical depths/thicknesses
needed for wafer specific grind, polish and etch
process optimizing to enable the highest yielding
TSV wafers. The BIM300 is based on Lasertec’s
proprietary confocal optics and is an ideal
solution for measuring and inspecting revealedvias, bumps and other critical elements foundthroughout the TSV wafer finishing. The EZ300,
an edge inspection and analysis system, is thelatest addition to Lasertec’s product portfolio andprovides unmatched analysis capability on wafer
edge issues.

LINTEC of AMERICA INC.
15930 S. 48th Street Suite 110
Phoenix, AZ 85048
Phone: +1 480-966-0784
www.lintec-usa.com
Contact: Stuart Campbell
Email: stuart.campbell@lintec-usa.com
Booth 112
LINTEC is a worldwide leader in adhesive
technologies. For 30+ years LINTEC, throughthe Adwill brand of products, has createdequipment and materials to solve difficult
semiconductor process issues.   With a catalog
of hundreds of tapes, a myriad of equipment,
and decades of application experience LINTEC
is positioned to help. Whether you are looking
for a tape, need equipment to mount, peel,
or UV cure, or would like assistance from ourapplications labs in Phoenix and Dallas to tackle
a difficult issue; our staff stands ready to assist
you to provide the Adwill Advantage. Need toreduce costs or address reliability issues in wafer
level chip scale packages (WLCSP)? Please visit
our Interactive Presentation “Development of
Double Side Protection Process with Bump Support
Film (BSF) and Backside Coating Tape for WLP” atThursday 9-11 A.M. in the Northern Hemisphere
Foyer.
LPKF Laser & Electronics
12555 SW Leveton Dr.
Tualatin, OR USA
Phone: +1 503-454-4200
www.lpkfusa.com
Contact: Stephan Schmidt
Email: sales@lpkfusa.com
Booth 214
LPKF Laser & Electronics is a manufacturer oflaser systems for the electronics manufacturing.
LPKF’s newest system, the Vitrion 5000 is
designed solely for creation of high quality
through glass vias (TGV) at very high production
rates. The laser class 1 system is compatible withglass wafers up to 18” as well as glass panels witha maximum dimension of 20” by 20”. The system
is able to produce via holes as with an 1:10
aspect ratio and can handle substrate thicknesses
between 50 and 300 micrometers. In addition,
LPKF offers its laser direct structuring technology(LDS) for the laser-based additive creation
circuitry on 3D injection molded plastics parts forthe use in sensor housings and micro-packaging.
Malico Inc.
5, MingLung Road
Yang-Mei, Taiwan 32663
Phone: +886-3-4728155
Fax: +886-3-4725979
www.malico.com
Email: inquiry@malico.com
Booth 511
Malico is the leading manufacturer for Thermal
Solutions. We offer both standard andcustomized heat sinks. Our product line includes
passive, active, heat pipe embedded, copper
embedded and liquid cooling solutions. We offer
design and simulation assistance. Our vertical
integrated production line ensures our customer
receive the highest quality service at the shortest
lead time and in most cost effective way.

31

Mentor, A Siemens Business8005 SW Boeckman Rd.
Wilsonville, OR 97070
Phone: +1 503-547-3000
www.mentor.com/pcb
Contact: Jen Chausse
Email: sales_info@mentor.com
Booth 521
Mentor® is the worldwide market leader in PCB
systems design, High Density Advanced Packaging
solutions and analysis technologies. Mentor will
be showcasing Xpedition Package Integrator with
HyperLynx, a holistic solution for IC/Package/
Board cross-domain prototyping, planning,
optimization, layout and electrical analysis .
Visit booth 521 to learn more about Mentor’s
technologies and best practices for IC/Package/
Board co-design or by attending Mentor technicalpresentations.
Micross Advanced Interconnect
Technologies
3021 E. Cornwallis Rd.
P.O. Box 110283
Research Triangle Park, NC 27709
Fax: +1 919-354-3580
www.micross.com/advancedinterconnect-technology.aspx
Contact: Alan Huffman
Email: alan.huffman@micross.com
Booth 316
Micross is the leading one-source, one-solution
provider of bare die & wafers, wafer bumping& advanced interconnect technologies, custom
packaging & assembly, component modification
services, electrical & environmental testing,and Hi-Rel products to manufacturers andusers of semiconductor devices. In business formore than 35 years, our comprehensive arrayof high-reliability capabilities serve the global
defense, space, medical, industrial, and fablesssemiconductor markets. Micross possesses thesourcing, packaging, assembly, test, and logistics
expertise needed to support an application
throughout its entire program cycle.
Mini-Systems, Inc. (MSI)
20 David Rd.
North Attleboro, MA 02760
Phone: +1 508-695-0203
Fax: +1 508-695-6076
www.mini-systemsinc.com
Contact: Craig Tourgee
Email: ctourgee@minisystemsinc.com
Booth 203
Mini-Systems, Inc. (MSI) is a world class leader
in the manufacture of high-reliability passive
components and hermetic packages. For over
49 years MSI has been delivering superior
quality products for Military, Aerospace,
Communications, Medical and Industrial
applications. MSI manufactured products consistof precision: Thin/Thick film Chip Resistors/
Networks, QPL Resistors to MIL-PRF-55342,
MOS Chip Capacitors, Chip Attenuators, FullLine of RoHS Compliant Products, QPL Jumpers
to MIL-PRF-32159/Mounting Pads, Glassto-metal seal packages, and Custom Design
Packages. Resistors values from 0.1 Ohm to100GOhm and operating frequencies up to 40
GHz. Absolute tolerances starting at 0.005% andTCRs as low as ±2ppm/°C. Sizes start at 0101.
The hermetic packages meet or exceed package
evaluation requirements per MI-PRF-38534, Table

C-VI. Hermeticity of the packages is less than
10-10 atm cc/sec per MIL-STD-883, method
1014, condition A4. MSI is ISO-9001 certified.
Compliance includes RoHS, REACH, and DFAR.
Standard deliveries start in just 2 WEEKS!
Mitsui Chemicals America
61 Metro Drive
San Jose, CA 95110
Phone: +1 408-487-2888
www.mc-tohcello.co.jp/english/
Contact: Jeff Wishes
Email: j.wishes@mitsuichem.com
Booth 113
ICROS™ Tape has been the world’s top
protective tape used in semiconductor wafer
backgrinding (BG) for many decades. In
order to meet the strict requirements of thesemiconductor market, we optimize the whole
production process from material design to final
inspection. Everything takes place within state-ofthe-art clean room production environments withstrict quality controls in place every step of theway. The result is ICROS™ Tape, an ultraclean
tape with superior TTV (total thickness variation).
Today, ICROS™ Tape is not only used for BG
process but also for many other processes insemiconductor manufacturing flow, such as dicing,packaging process, tape for metal lift off process,protective tape for etching, tape for CMOS
image sensor handling, and protection tape forback metalizing. ICROS™ Tape is now being
developed for latest generation semiconductor
process, such as TSV wafer BG and dicing, fanout WLP, Panel Level Package and many otherprocesses.

The KEY to Perfect POLYMER Processing:

YES-VertaCure

Automated.
Comprehensive.
Flexible.
Transforming atomic-scaleengineering withmarket-leading deposition,etch, and clean technologies forfront-end wafer processing andadvanced packaging applications

Shorter process time
No trapped solvent/Oxygen
No outgassing at metallization

Learn how our innovative solutions
can help you achieve success on the wafer

www.yieldengineering.com
1.888.YES.3637
Connect with us

32

www.lamresearch.com

MRSI Systems
101 Billerica Ave.
N. Billerica, MA 01862
Phone: +1 978-667-9449
www.mrsisystems.com
Contact: Dan Crowley
Email: sales@mrsisystems.com
Booth 318
Die bond and dispense solutions from MRSI
Systems, with accuracies to one micron
for eutectic, epoxy, flip chip, and thermocompression die bonding. MRSI Systems is aleading supplier of high precision dispense andassembly equipment for the semiconductor andmicroelectronics industry, offering systems forthe manufacture of Microwave, Optical, MCMs
and MEMS devices. Entering our third decadeof advanced packaging application experience,
MRSI Systems products support all standard
interconnect technologies. The ultra-precision
MRSI Systems MRSI-M3 with 1 micron accuracy
capability for photonic and 3D packaging
applications and the MRSI-705 Die Bonders
specialize in thin die handling and accuracies
to 5 microns. The MRSI Systems MRSI-175Ag
Epoxy Dispenser is the leader for high precision
conductive epoxy dispensing including 125 micron
dots using a variety of dispense technologies.
Your Standard in Precision Automation.
Nagase America Corporation
2880 Lakeside Drive, Suite 320
Santa Clara, CA 95054
Phone: +1 408-567-9728
Fax: +1 408-567-9729
www.nagasechemtex.co.jp/en/
Contact: Ippei Yamai
Email: ippei.yamai@nagase-nam.com
Booth 303
Nagase ChemteX is a leading company forsemiconductor encapsulant of epoxy resin,
especially Liquid Molding Compound (LMC) for
FOWLP, Non-Conductive Paste (NCP) for Fine
pitch FC-PKG, Underfill for Pb-free. Engineered
Materials Systems, Inc. technology focus onelectronic materials and negative photoresist for
semiconductor, circuit assembly, photovoltaic,
printer head, camera module, disk drive, printed
electronics and photonics assembly product lines.
These Nagase Group companies create continual
improvements guiding its customers into the
future.
NAMICS Technologies, Inc.
2055 Gateway Place, Suite 480
San Jose, CA 95110
Phone: +1 408-516-4611
Fax: +1 408-516-4617
www.namics.co.jp/eContact: Tony Ruscigno
Email: sales@namics-usa.com
Booth 401
NAMICS CORPORATION is a leading source
for underfills, encapsulants, adhesives, andinsulating and conductive materials used byproducers of semiconductor devices, passive
components and solar cells. eadquartered in
Niigata, Japan with subsidiaries in the USA,
Europe, Taiwan, Singapore, Korea and China,
NAMICS serves its worldwide customers withenabling products for leading edge applications.

Nanium S. A.
Avenida 1º de Maio 801
4485-629 Vila do Conde, Portugal
Phone: +351 252 24 6301
Fax: +351 252 24 6001
www.nanium.com
Contact: Antonio Barny
Email: antonio.barny@nanium.com
Booth 501
NANIUM (www.nanium.com) is an outsourced
semiconductor packaging, assembly and test
provider, and a world-leader in 300mm WaferLevel Packaging. The company provides WaferLevel Chip Scale Packaging (WLCSP) and wasamong the first in the world to offer Wafer-Level
Fan-Out (WLFO) in high volume manufacturing.
Today, NANIUM stands as a leader in WLFO,
a technology that combines minimal form-factor
with superior performance, high integration
density, and high reliability. Since inception,NANIUM has shipped over 1 billion WLFO
packages. NANIUM delivers world-class services
and always customizes Solutions according to
the customers’ needs. Its WLFO technology
is flexible and can accommodate embedded
integration solutions ranging from single- to multidie, system-in-package and package-on-packagewith passives integration, and serve markets suchas mobile communication, medical, security,
wearables and automotive radars, to name afew. Based in Portugal, NANIUM’s facilities
include over 20,000 sqm of cleanroom area. The
company offers in-house capabilities for the entire
development chain, from package design to theflexibility to tailor and test solutions. NANIUM
has sales offices in Dresden, Germany, andBoston, MA, USA
Neu Dynamics Corp.
110 Steamwhistle Dr.
Ivyland, PA 18974
Phone: +1 215-355-2460
Fax: +1 215-355-7365
www.neudynamics.com
Contact: Don Johnson
Email: sales@neudynamics.com
Booth 216
Neu Dynamics offers encapsulation molding
systems for micro BGG and PBGA array devices,
Top and Bottom Transfer as well as multi-plungermold tooling for the latest in small outline devices(TQFP, TSSOP, MSOP, QFN, LGA, etc.) andmolded Optoelectronic packages, Automaticand semi-automatic trim and form dies andsystems supplied with trim presses (both Servoand Hydraulic driven). Neu Dynamics further
offers contract transfer molding services. Our fully
equipped molding lab allows for mold tryouts,
pilot runs and low to medium volume production.
Neu Dynamics is also capable of building highprecision injection molds specializing in insert andovermolding applications. Our sister company,
NDC International, is a distributor of a wide
range of back-end semiconductor assembly
packaging equipment and materials, and custom
automation solutions.

Nikon Metrology, Inc.
12701 Grand River Ave.
Brighton, MI 48116
Phone: +1 810-220-4360
Fax: +1 810-220-4300
www.nikonmetrology.com
Contact: Andrew Smith
Email: sales.nm.us@nikon.com
Booth 311
Nikon Metrology, Inc. offers the most complete
and innovative metrology product portfolio, withstate-of -the-art vision measuring instruments
x-ray machines with CT options, and a completeline of 3D metrology options. These reliable andinnovative solutions respond to the advanced
inspection requirements of manufacturers active
in aerospace, electronics, automotive and otherindustries. To learn more about our innovative
products and to view all our product lines please
visit our website.
Nitto Inc.
Bayside Business Park
48500 Fremont Blvd.
Fremont, CA 94538
Phone: +1 510-445-5400
Fax: +1 510-445-5480
www.nitto.com
Contact: Yasuko Ferris
Email: yasuko.ferris@nitto.com
Booth 211
Nitto Denko is a global supplier of materials andequipment for semiconductor manufacturing,
represented by the following products: ELEP
holder tapes for back-grinding and dicing; hightemperature resistant masking tape; NEL machines(Taper/Detaper/ Wafer Mounter with or without
peeling function/ UV machine) for thin wafer
application; ELEPMOUNT (2-in-1: DAF+Dicing
Tape conductive/non-conductive) for thin stacked
chip package; REVALPHA thermal-release tapefor various applications, such as dicing, grinding
and MLCC production process; clear molding
compound and sheet encapsulating resin.
Nordson DAGE
2747 Loker Avenue West
Carlsbad, CA 92010
Phone: +1 925-246-1662
www.nordsondage.com
Contact: Aram Kardjian
Email: aram.kardjian@nordsondage.com
Booth 305
Nordson DAGE is the market leading providerof award winning wire pull, ball and die shear test
systems along with X-Ray and AOI inspection
systems. They are recognized as the industry
standard. The recently released 4800 bond tester
brings the latest developments in automatedwafer testing technology to users testing wafers
from 100mm to 450mm in diameter. When
combined with an integrated wafer handlingdevice the 4800-INTEGRA™ can test multiple
wafers consecutively. Additionally, the multifunction cartridge (MFC) can be used forautomated application changing within a test
pattern or simply very quick cartridge changes
in manual operation. Automation on non-wafer
samples can also be conducted on the 4000Plus
which performs shear tests up to 200kg, pulltests up to 100kg and push tests up to 50kg. The
all-purpose 4000 and 4000 Optima systems arecapable of manual pull testing up to 50kg andshear tests to 200kg with accuracies up to 0.05%
as standard. Paragon software offers ease of use
and intelligent automated testing with a focus on33

user experience. The 4000HS high speed bondtester is used for pull and shear testing of solder
spheres to identify brittle fractures at speeds up
to 4m/sec in shear and 1.3m/sec pull.
NTK Technologies, Inc.
3979 Freedom Circle Dr., Suite 320
Santa Clara, CA 95054
Phone: +1 408-727-5180
Fax: +1 408-727-5076
www.ntktech.com
Contact: Mariel Stoops
Email: scdinfo@ntktech.com
Booth 212
NTK Technologies is a leader in IC Ceramic
Packaging. For nearly half a century, NTK has
developed specialized technologies to provide
advanced ceramic IC packaging solutions formature and start-up semiconductor companies.
NTK’s technical centers support design
optimization and simulation services through all
development and production stages -- prototype,small volume, and volume manufacturing. With
global service centers, NTK offers a wide rangeof packaging materials and design services for
CMOS/CCD Image Sensors, Opto, FPGA,
CPU, MPU, MCM, RF, LED Substrates, Hi-Rel,
Satellite, Automotive and Medical applications.
Wafer Probe Substrates utilizing multilayer
co-fired ceramic and multilayer thin film available.
Optimum package designs for 10G to 400G.
As one of the industries’ largest packaging
manufacturers, NTK’s products and services have
evolved to match the roadmaps of mainstream
and advanced IC packaging applications.
Ntrium Inc.
Lvl 2, 54-42 Dongtanhana 1-gil,Hwaseong-si, Gyeonggi-do, 18423
Republic of Korea
Phone: +82-31-8889068
Fax: +82-31-8889555
www.ntrium.com
Contact: James Lee
Email: sjlee@ntrium.com
Booth 213
Ntrium is presented with the opportunity
to converge Nano-material technology andthe Microelectronics packaging technologyof Automotive/Semiconductor/Mobile/
IT products, to ignite bright minds that solve
technical problems customers face, to provide
collaborate and innovative solutions. EMI Shielded
Package is a solution to reduce local noiseinterference caused by high frequency chips inside
the high-end devices. Spray Coating is one of
the best solutions for on-package EMI Shielding,because of its excellent SE (Shield Effectiveness)
Performance. It has (1) Good Adhesion to
Package (2) Conformal Shielding Coverage on
both Top and Side walls (3) Coating Thickness
Controllability for Thinner Device and Higher SE
Performance (4) Lower Cost and Simpler Process
than PVD (5) Free from Backside (Ball Grid andLand Grid) Contamination.

34

Ormet Circuits
6555 Nancy Ridge Dr. #200
San Diego, CA 92121
Phone: +1 858-831-0010
Fax: +1 858-455-7108
www.ormetcircuits.com
Contact: Michael Matthews
Email: support@ormetcircuits.net
Booth 121
Ormet Circuits Inc. is proud to join EMD
Performance Materials, an affiliate of Merck
KGaA, Darmstadt, Germany. The combined
Performance Materials (PMI) portfolio includes
high-tech performance chemicals for applications
in fields such as: Displays, Integrated Circuits,
Lighting Applications, Solar & Energy, Coatings,
Semiconductor Packaging. Customer sectors in
consumer electronics, lighting, printing technology,
plastics applications and integrated circuits
make use of materials and solutions from EMD
Performance Materials. Thanks to comprehensive
investments in research & development, we areconstantly extending our leading position as aninnovator and reliable partner. Our future growth
integrates key materials consisting of high purity
chemicals used in wafer fabrication to sustainable
materials for advanced back end solutions.
PAC TECH USA
328 Martin Ave.
Santa Clara, CA 95050
Phone: +1 408-588-1925 x 246
Fax: +1 408-588-1927
www.pactech.com
Contact: Richard McKee
Email: richard.mckee@pactech.com
Booth 301
Packaging Technologies GmbH (group memberof NAGASE & CO. Ltd.) is headquartered in
Nauen, Gremany with wholly owned subsidiaries:
PacTech USA Packaging Technologies Inc. in
Silicon Valley, USA, and PacTech ASIA Sdn. Bhd.
in Penang, Malaysia. PacTech is comprised of two
unique advanced packaging units: EQUIPMENTMANUFACTURING: PacLine 300 A50Automatic ENIG & ENEPIG plating tools. SB2-Jet:
Laser solder jetting equipment; Ultra-SB: Waferlevel solder ball transfer systems; LAPLACE:
Laser assisted flip-chip bonders SUBCONTRACTSERVICES: Flip Chip and Wafer Level Package
Bumping Services including ENIG or ENEPIG
for UBM (solder bumping) or OPM (wirebond).
Other services include AOI, X-Ray, Repassivation,
RDL, Wafer Thinning, Backmetal, Laser Marking,Dicing, and Tape and Reel.
Palomar Technologies Inc.
2728 Loker Avenue West
Carlsbad, CA 92010
Phone: +1 760-931-3600
Fax: +1 760-931-5191
www.palomartechnologies.com
Contact: Katie Schirmer
Email: kschirmer@bonders.com
Booth 500
Palomar Technologies, a former subsidiary of
Hughes Aircraft, is the global leader of automatedhigh-accuracy, large work area die attach andball and wedge wire bonding equipment andprecision contract assembly services. Customers
utilize the products, services and solutions
from Palomar Technologies to meet theirneeds for optoelectronic packaging, complex
hybrid assembly and micron-level component
attachment.

Panasonic Factory Solutions Co. of
America1701 Golf Road, Ste 3-1200
Rolling Meadows, IL 60008
Phone: +1 847-637-9600
Fax: +1 847-637-9601
www.panasonicfa.com
Contact: Tae Yi
Email: tae.yi@us.panasonic.com
Booth 505
Panasonic Factory Solutions Company of America(PFSA) develops and supports innovative
manufacturing processes around the core of
circuit manufacturing technologies and computerintegrated manufacturing software—thereby,
contributing to the growth and prosperity of ourcustomers’ businesses regardless of their mix orvolume.
Panasonic Industrial Devices Sales Co.
Division of Panasonic Corp. NA
10900 N. Tantau Ave., Suite 200
Cupertino, CA 95014
Phone: +1 408-861-3946
Fax: +1 408-861-3990
www3.panasonic.biz/em/e/guidance
Booth 507
Since the founding of our company in 1918, we
at Panasonic have been providing better living forour customers, always making ‘people’ central
to our activities, and thus focusing on ‘people’s
lives’. Going forward from this, and based on
our innovative electronics technology, we willcontinue to provide a wide variety of products,
systems and services.
Plasma-Therm, LLC
10050 16th St. N.
St. Petersburg, FL 33716
Phone: +1 727-577-4999
Fax: +1 727-577-7035
www.plasmatherm.com
Email: information@plasmatherm.com
Booth 408
Plasma-Therm® is a leading provider of advanced
plasma processing equipment. Plasma-Therm
systems perform critical process steps in
the fabrication of integrated circuits, micromechanical devices, solar power cells, lighting,and components of products from computersand home electronics to military systems andsatellites. Specifically, Plasma-Therm systems
employ innovative technology to etch and deposit
thin films. The company’s Mask Etcher® series forphotomask production has exceeded technology
roadmap milestones for more than 15 years.
Plasma-Therm’s Singulator® systems bring the
precision and speed of plasma dicing to chippackaging applications. Manufacturers, academic
and governmental institutions depend on PlasmaTherm equipment, designed with “lab-to-fab”
flexibility to meet the requirements of both
R&D and volume production. Plasma-Therm’s
products have been adopted globally and haveearned their reputation for value, reliability, andworld-class support. Plasma-Therm’s status as apreferred supplier of plasma process equipment
has been recognized with VLSIresearch Customer
Satisfaction awards for 17 consecutive years,
including “RANKED 1st” awards from 2012 to2016.

Promex Industries Inc.
3075 Oakmead Village Drive
Santa Clara, CA 95051
Phone: +1 408-496-0222
www.promex-ind.com
Contact: Rosie Medina
Email: rmedina@promex-ind.com
Booth 215
Promex provides heterogeneous assembly
processing integrating conventional surface
mount technology (SMT) with semiconductor
microelectronic packaging and assembly methods
for flip chip or chip/wire devices. The company
operates a 30,000 sq. ft. assembly facility withClass 100 and 1000 clean rooms in Silicon Valleythat is ISO 13485:2003, ISO 9001:2008 certified,
ITAR registered and compliant to regulatory
requirements for medical products. With ahighly skilled engineering team, Promex combines
broad technical capabilities, advanced packaging,and microelectronics assembly expertise withscalable manufacturing capacity to produce new
medical and bioscience products from concept to
production.
PURE TECHNOLOGIES
177 US Hwy # 1, No. 306
Tequesta, FL 33469 USA
Phone: +1 404-964-3791
Fax: +1 877-738-8263
Int’l Fax: +1 973-273-2132
www.puretechnologies.com
Contact: Jerry Cohn
Email: jerry@puretechnologies.com
Booth 205
Pure Technologies manufactures low (0.02, 0.01
cph/cm2), ultra-low (0.005, 0.002 cph/2) andsuper ultra-low (<0.001 cph/cm2) alpha emitting
Tin (Sn), Lead-Free (including all SAC) alloys,
Pb, Pb/Sn , Bi and virtually all alloys for over 23
years. These ALPHALO® products are available
in various shapes and sizes – ingots, anodes, slugs,pellets, foil, rods, bricks, PbO and SnO powder,etc. for wafer-level packaging, interconnects,
electroplating and sphere and powder/paste
manufacturing. ALPHA-LO® reduces/eliminatessoft errors from alpha particle emissions fromsolders, enhances performance reliability
and reduces corporate liability. All materials
are guaranteed and certified to be at secularequilibrium and are tested and retested over time
before shipping to insure that the alpha emission
rate is stable and will not increase over time.
QualiTau
830 Maude Ave.
Mountain View CA, 94043
Phone: +1 650-282-6226
Fax: +1 650-230-9192
www.qualitau.com
Email: sales@qualitau.com
Booth 416
QualiTau offers a variety of reliability test
equipment for characterization and developmentof new materials used in the manufacturing ofIntegrated Circuits, as well as process monitoringand process qualification. The MIRA, Infinity, ACE,
and Multi-Probe reliability test systems perform
tests for Hot Carrier Injection (HC), Dielectric
Breakdown (TDDB), and electromigration(EM)of interconnects, TSV, Solder Bump (8 amperesmax) at test temperatures of up to 450°C.
QualiTau’s Test Lab service is ideal for bothfabless companies and foundries seeking: Reliable,
independent evaluation and analysis. “Virtual”

capacity during times of under-capacity. Costeffective means of performing tests on an irregular
or infrequent basis. A productive and beneficial
way to “test drive” the equipment before
committing to a purchase.
Quik-Pak, a Division of Promex
10987 Via Frontera
San Diego, CA 92127
Phone: +1 858-674-4676
Fax: +1 858-674-4681
www.icproto.com
Contact: Casey Krawiec
Email: casey@icproto.com
Booth 215
Quik-Pak, a division of Promex, provides IC
packaging, assembly, and wafer preparation
services in its ISO 9001:2008 and ITAR registeredfacility in San Diego, California. Quik-Pak
manufactures over molded QFN/DFN packages
and pre-molded air cavity QFN packages thatprovide a fast, convenient solution for prototype
to full production needs. Same-day assembly
services are provided to shorten time tomarket. Due to customer demand, Quik-Pak
now provides high volume IC assembly services
utilizing its automated assembly and molding
equipment for production runs in the 10,000sof units. In addition to wire bond assembly, thecompany assembles flip chips, BGAs, stacked die,sensors, MEMS, and chip-on-board and chip-onflex assemblies.
Royce Instruments LLC
831 Latour Court, Suite C
Napa, CA 94558
Phone: +1 707-255-9078
Fax: +1 707-255-9079
www.royceinstruments.com
Contact: Bill Coney
Email: bconey©royceinstruments.com
Booth 502
Consider Royce Instruments your preeminent
supplier for Bond Testing and Die Sorting
equipment. Our equipment provides outstanding
accuracy to meet a full range of bond test anddie sorting requirements. Because bond testingand die sorting are our sole focus, we areable to dedicate ourselves to developing andsupplying leading, high-precision solutions forour customers. The Royce 600 Series Bond
Test Instruments brings unparalleled networking
capability and scalability to the bond test market.
With a choice of 3 bond testers, Royce offers an
instrument solution to meet the evolving needsof manufacturers and institutions worldwide.
Royce Die Sorters (AutoPlacer MP300, DE35ST and our new AP+) offer fully-automatic andsemi-automatic die sorting solutions for today’s
challenging applications, including die as small
as 200 um square or 50 um thick. Our new
automated die sorter, the AP+ has the capability
to handle the output mediums your process
requires (carrier tape, waffle pack, Gel-Pak,
JEDEC tray, film frame, grip ring, and custom
trays) and place to output while maintaining input
to output traceability at the die level.

Rudolph Technologies
16 Jonspin Road
Wilmington, MA 01887
Phone: +1 978-253-6200
Fax: +1 978-658-6349
www.rudolphtech.com
Email: info@rudolphtech.com
Booth 413
Rudolph Technologies is a leader in the design,development, manufacture and support of defectinspection, advanced packaging lithography,
process control metrology, and data analysis
systems and software used by semiconductor
device manufacturers worldwide. Rudolph’s
product suite offers hardware and software
solutions for the demanding requirements of theadvanced packaging market, including 2D/3Dbump inspection, RDL and overlay metrology,
and a lithography stepper specifically designed forthe back-end. Turn data into useful information
with Rudolph’s proprietary software solutions
including run-to-run control, fault detection andclassification and yield management systems.
Samtec, Inc.
2223 Owen St
New Albany, IN 47150
Phone: +1 812-944-6733
Fax: +1 812-948-5047
www.samtec.com
Contact: Glenn Dixon
Email: glenn.dixon@samtec.com
Booths 313 & 315
Known as the worldwide service leader forelectronic connectors and cables, Samtec has
focused on leading edge high speed products
and services for the last two decades. The
tremendous success in these areas has driven
Samtec to further move into faster and smaller
arenas. They now provide full turnkey solutions
for your entire signal chain from IC, through the
package, and through substrates, connectors
and cables. Samtec can help you design, model,
layout, and assemble your IC package. Advanced
Semiconductor, MEMS, and Sensor substrate
design, Flip chip, die attach, wire bonding,dam, encapsulation, transfer molding, and lid
attach, Modeling and prototyping,  Electricaltesting and debug,  In-house mid-board optical/
photonic engine design, manufacturing, andpackaging, and  New capabilities in glass
interposers and substrates with low loss electricalcharacteristics, biomedical microstructuring, and
2.5D package integration.
Sanyu Rec Company Ltd.
3-5-1 Doucho, Takatsuki
Osaka 569-8558, Japan
Phone: +81-8-0578-13684
www.sanyu-rec.jp
Contact: Hiroshi Yamada
Email: yamada@sanyu-rec.jp
Booth 115
Sanyu Rec Company Ltd. is a Japanese electronics
material supplier to the semiconductor market
place including LED market. With creative
development and numerous proprietary
technologies, SANYU REC contributes to thesegrowth fields which are driven by environmental
considerations and mobile applications. SANYUREC has provided a variety of products centeringon encapsulation materials like liquid MUF(mold underfill) material to the market. Capillary
underfill, die attach materials, and mold sheets
are also in our main product lines. Not only
these materials but also VPES (vacuum printing

35

equipment) and pressure oven are in our productlines to offer comprehensive solutions to thecustomers, which distinguishes us from ourcompetitors. SANYU REC is continuing our effort
in development of unique and new technologies.
Among such, LED is one of the areas SANYUREC is promoting the shift to.
SavansSys
10409 Peonia Court
Austin, TX 78733
Phone: +1 512-402-9943
www.savansys.com
Contact: Amy Palesko
Email: amyl@savansys.com
Booth 210
SavanSys is the industry standard choice forelectronics manufacturing cost modeling. The
company began in the mid-nineties with a focus
on multi-chip module and PCB fabrication andassembly before expanding into electronics
packaging. SavanSys provides both cost modelingservices and software products and maintains an
extensive library of manufacturing activity costs.
Projects range from multi-year ventures focusedon detailed supply chain modeling to one-time
projects comparing a new technology to thecurrent industry standard. All SavanSys projects
and products use activity based cost modeling,which is a bottom-up approach to cost that
aggregates individual cost contributors (labor,material, throughput, equipment cost, etc.) for
every step in a process flow.
SCHOTT North America, Inc.  
400 York Avenue
Duryea, PA 18642, USA
Contact: Dave Vanderpool
Phone +1 407-288-7695
Fax +1 407-321-8847
www.us.schott.com
Email: dave.vanderpool@us.schott.com
Booth 508
SCHOTT Advanced Optics is a valuable partner
for its customers in developing products andcustomized solutions for applications in optics,
lithography, astronomy, opto-electronics, life
sciences, and research. With a product portfolioof more than 120 optical glasses, special materials
and components, we master the value chain: from
customized glass development to high-precision
optical product finishing and metrology. SCHOTT
is one of the world’s leading suppliers of thin
and ultra-thin glass wafers and substrates madeof different materials in sizes of between 4” and12”, in thicknesses down to 25 µm, with various
surface qualities and customized features. The
use of proprietary production processes, a wide
selection of different materials, and continuous
expansion of state-of-the-art processing
capabilities make SCHOTT’s wafer offerings
unique in the industry. Process Capabilities include
polishing, structuring, edge treatment, ultrasonicwashing, and clean room packaging. SCHOTT’s
portfolio of Thin and Ultra-Thin glasses includes:
AF 32® eco, an alkali-free flat glass with a CTE
matched to silicon; D 263® eco, a high CTE
and high transmission glass; SCHOTT AS 87
eco, world’s first ultra-thin and toughenable glass;
B 270® i, a crown glass with extremely high CTE;
and MEMpax®, an anodic bondable glass witha CTE corresponding to silicon. The portfolio is
supplemented by FOTURAN® II, SCHOTT’s
unique photo-sensitive glass.

36

Semiconductor Equipment Corp.
5154 Goldman Avenue
Moorpark, CA 93021
Phone: +1 805-529-2293
Fax: +1 805-529-2193
www.semicorp.com
Contact: Don Moore
Email: dmooresec@aol.com
Booth 206
Semiconductor Equipment Corporation, isa manufacturer and distributor of manual,semiautomatic, and automatic equipment for
the Photonics, Semiconductor, MEMS, SMT andHybrid Industries. Back end products include
flip-chip bonders, ultrasonic die bonders, laser
diode bonders, eutectic die bonders, manual
pick & place, epoxy die bonders, die rework,
dicing tape, manual and automatic dicing tapeapplicators, UV tape curing system, backgrindingtape, backgrinding tape applicators, backgrinding
tape peelers, and die ejectors. Front end products
include semiautomatic and fully automaticcassette, SMIF, RSP, FOSB, FOUP, and EUV pod
cleaning systems and cleaning wafers for vacuum
and e-chucks.
Senju Comtek
2989 San Ysidro Way
Santa Clara, CA 95051
Phone: +1 408-963-5300
Fax: +1 408-963-5399
www.senju-m.co.jp/en
Contact: Ayano Kawa
Email: akawa@senju.com
Booth 412
Senju Comtek Corp. is an American subsidiaryof Senju Metal Industry Co. (SMIC) of Tokyo,
Japan. Senju is a global leader in solder materials
and related processing equipment with over twodozen manufacturing, technical, and sales support
facilities located around the world. Senju Comtek
has two solder paste manufacturing locations in
USA (San Jose, CA and Chicago, IL) supportinga wide range of products for the semiconductor
and PCBA industries.
SET North America
343 Meadow Fox Ln.
Chester, NH 03036
Phone: +1 603-548-7870
Fax: +1 603-887-2000
www.set-na.com
Contact: Matt Phillips
Email: mphillips@set-na.com
Booth 120To enable high-density interconnect, SETNorth America offers surface preparation andhigh-accuracy bonding tools with unparalleled
performance. For removing native oxides, residualorganics or other bond inhibitors, the ONTOS7
Atmospheric Plasma Surface Preparation toolcleans and passivates bonding surfaces to provide
high-quality bonds with superior electrical andmechanical integrity. This tool is also effective in
activating surfaces to enhance wetting and wicking
for aqueous processes or underfill materials.
The device bonders manufactured by SET are
globally renowned to deliver unsurpassed bonding
accuracy (±0.5 μm) at high temperatures andforces for chips and substrates ranging from tiny,
fragile components up to 300 mm wafers. Witha product portfolio ranging from manually loaded
versions to fully-automated operation, SET offers
bonding and nanoimprint solutions with highflexibility and field-proven reliability.

SHENMAO AMERICA, Inc.
2156 Ringwood Ave.
San Jose, CA 95131
Phone: +1 408-943-1755
Fax: +1 408-684-5477
www.shenmao.com
Contact: Hans Schiesser
Email: hschiesser@shenmao.us
Booth 514
SHENMAO America, Inc. is the American
subsidiary of SHENMAO Technology, Inc. of
TaoYuan City 328, Taiwan. Shenmao is a global
leader in manufacturing solder materials for over
44 years with 10 manufacturing, technical, andsales support facilities located around the world.
SHENMAO America, Inc. manufactures solder
paste in San Jose, CA, USA, also supporting awide range of products for the Semiconductor
Packaging and PCB Assembly industries.
SHENMAO produces SMT Solder Paste, Laser
Soldering Paste, Wave Solder Bar, Solder Wire
with/without Flux, Liquid and Paste Flux, Solder
Preforms, Semiconductor Packaging Solder
Spheres, Wafer Bumping Solder Paste, Dipping
Flux, LED Die Bonding Solder Paste, Plating
Anode and Solar PV Ribbon. 11 of the 12 largest
EMS Companies are valued customers that arecontinuously using SHENMAO Technology, Inc.
Solder Materials with great success. OSAT’s,
EMS and OEM’s qualify/re-qualify our products
for many years. For more information pleasecontactwww.shenmao.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Phone: +1 480-893-8898
Fax: +1 480-893-8637
www.microsi.com
Email: info@microsi.com
Booth 310
Shin-Etsu MicroSi, Inc. is a wholly owned
subsidiary of Shin-Etsu Chemical Ltd. Shin-Etsu
MicroSi is a world class supplier of packaging
materials for the semiconductor industry. Witha global support network- Sales Engineers, R&D,
Manufacturing, Quality Assurance, and Logisticswe are able to quickly develop and provide newtechnologies to benefit our customers. This
allows our clients to meet their ever changing
technical, commercial and environmental needs
by implementing Shin-Etsu MicroSi’s technology.
Shin-Etsu MicroSi is known for supplying highperformance Thermal Interface Materials,
Underfills, Molding Compounds, High Purity
Silicone Encapsulants, and Die Attach Materials.
Shinkawa USA, Inc.
1177 S. Porter Court
Gilbert, AZ 85296
Phone: +1 480-831-7988
www.shinkawa.com/en/
Contact Doug Day
Email: d_day@shinkawausa.com
Booth 512
Shinkawa is a leading supplier of flip chip, wirebonding and die bonding equipment. The wide
range of equipment supports various applications
including IoT and infrastructure (server/memory),
as well as mobile and communication devices.
Shinkawa provides key innovative solutions for
future packaging technology with high-accuracy
TCB flip chip bonders and ultra-high throughput
flip chip bonders for the mass reflow process(C4/C2). In the field of die and wire bonding,
Shinkawa provides ultra-thin die pick up

technology and unique wire shape technology
for RF, PoP and many other devices. Founded in
1959 in Tokyo and now with a strong presence inthe semiconductor market, Shinkawa services andsupports a diverse network of global customers
and partners all over the world.
Shinko Electric America
1280 East Arques Avenue MS 275
Sunnyvale, CA 94085
Phone: +1 408-232-0493
Fax: +1 408-955-0368
www.shinko.com
Contact: Michael Hudgens
Email: Michael.hudgens@shinko.com
Booth 421
SHINKO Electric Industries Co., LTD., is aleading manufacturer of products used in theassembly of IC’s such as Organic Substrates,
Etched and Stamped Leadframes, TO Packages
and Integrated Heatspreaders. We manufacturea full line of Organic Substrate structures including
coreless options offering enhanced electricalperformance and package miniaturization.
SHINKO also provides subcontract IC assembly
services with an emphasis on packaging solutions
such as PoP, SiP as well as advanced technologies
such as Molded Core Embedded Package(MCeP®) and Camera Module assembly andtest. Our headquarters and primary production
plants are located in the greater Nagano, Japan
area. In addition to our production facilities wealso provide the ultimate in service and solutions
for customers, with Sales and Engineering support
Worldwide. Come visit us at booth 421 to learn
more about our latest product offerings for fine
pitch interconnection, miniaturization and highdensity mounting for 3D assembly.
Sonoscan, Inc.
2149 East Pratt Blvd.
Elk Grove Village, IL 60007
Phone: +1 847-437-6400
Fax: +1 847-437-1550
www.sonoscan.com
Contact: Jack Richtsmemer
Email: jrichtsmemer@sonoscan.com
Booth 209
Founded in 1973 and headquartered in Chicago,
IL, Sonoscan®, Inc. is a worldwide leader andinnovator in Acoustic Micro Imaging (AMI)
technology. Sonoscan manufactures and markets
acoustic microscope instruments and accessories
to nondestructively inspect and analyze products.
Our C-SAM® scanning acoustic microscope
provides unmatched accuracy and robustness
setting the standard in AMI for the inspection of
products for hidden internal defects such as poor
bonding, delaminations between layers, cracks
and voids. In addition, Sonoscan offers analyticalservices through regional testing laboratories
in Asia, Europe and the U.S. and educational
workshops for beginners to advanced on AMI
technology.
SPTS Technologies
Ringland Way
Newport NP18 2TA UK
Phone: +44 1633 414000
www.spts.com
Contact: Wendy Davis
Email: enquiries@spts.com
Booth 201
SPTS Technologies, an Orbotech company,
designs, manufactures, sells, and supports

advanced etch, PVD, and CVD wafer processing
equipment and solutions for the global
semiconductor and micro-device industries,
with focus on the Advanced Packaging, MEMS,
high speed RF device, power managementand LED markets. With the addition of SPTS,
Orbotech is able to offer a broader range ofprocess solutions for Advanced Packaging, which
includes Orbotech’s Inkjet solutions for die level
printing of package marking, underfill dams andisolation layers. SPTS has manufacturing facilities
in Newport, Wales and Allentown, Pennsylvania,
and operates across 19 countries in Europe,
North America and Asia-Pacific.
STATS ChipPAC
46429 Landing Parkway
Fremont, CA 94538
Phone: +1 510-979-8000
Fax: +1 510-979-8001
www.statschippac.com
Contact: Lisa Lavin
Email: Lisa.Lavin@statschippac.com
Booth 101STATS ChipPAC is a leading OSAT providerof semiconductor design, wafer bump, probe,
packaging and test solutions for well-establishedmarket segments such as communications,consumer and computing as well as emerging
markets in automotive electronics, Internet ofThings (IoT) and wearable devices. With a global
manufacturing presence spanning Singapore,
South Korea, and China and a broad technology
portfolio ranging from leadframe and laminate
packages to advanced fan-out and fan-in wafer
level technology, flip chip interconnect, MEMS andsensors, System-in-Package (SiP) and 2.5D/3D
packaging, STATS ChipPAC provides customers
with innovative and cost-effective semiconductor
solutions. STATS ChipPAC differentiates itself
through innovative packaging solutions thatmeet increasing market demands for higher
performance, functionality and processing
speeds with a significant reduction in space in anelectronics device.
TAIYO INK MFG. CO., LTD
2675 Antler Drive
Carson City, NV 89701
Phone: +1 408-821-2705
www.taiyo-hd.co.jp/en/
Contact: Dan Okamoto
Email: dano@taiyo-america.com
Booth 111TAIYO INK MFG. CO., LTD has more than
90% market share of solder resist products on
IC-Packaging industry. Recently, TAIYO INK
MFG. CO., LTD introduced two important
products to the market. The first product,
AZ1, provides very robust TST crack resistancewith higher Tg best for large body FCBGA
and automotive BGA products. The othernew product, SR3, offers very low CTE (1520ppm) with high modulus (>10GPa) ideallyfor coreless/thin core applications. Also, basedon our expertise in photo-imageable dielectric
technology, we started to offer a photoimageable dielectric dry film material as a build-up
material for BGA substrates or interposers, or as
an insulation material for embedded applications.
Furthermore, this material can replace PI/PBO
for WLP / PLP products with greater advantage.
For more details, please visit our booth 111. Our
engineer will meet you there to answer all of yourquestions including those about our material foryour applications.

TATSUTA USA Inc.
5201 Great America Parkway,
Suite 320
Santa Clara, CA 95053
Phone: +1 408-850-7166
Fax: +1 408-562-5745
www.tatsuta.com
Contact: Mike Sakaguchi
Email: m-sakaguchi@tatsuta.com
Booth 106TATSUTA is leading provider of EMI shielding
conductive material for semiconductor industry.
TATSUTA provides innovative solutions forconformal and compartment shielding withmicron size copper and silver conductive paste.
TATSUTA is also provide unique high reliability
metallizing paste for TMV filling, low temperature
cure type conductive paste for circuitry printing
and 3D SMT For more details, please visit ourbooth 106. We will provide solutions for yourapplications.
TechSearch International Inc.
4801 Spicewood Springs Rd., Suite 150
Austin, TX 78759
Phone: +1 512-372-8887
Fax: +1 512-372-8889
www.techsearchinc.com
E-mail: tsi@techsearchinc.com
Contacts: Becky Travelstead
Booth 300
TechSearch International, Inc. has a 28-year
history of market and technology trend analysis
focused on semiconductor packaging, materials,
and assembly. Research topics include WLP,FO-WLP, Flip chip, CSPs including stacked die,
BGAs, 3D ICs with TSVs, 2.5D interposers, andSystem-in-Package (SiP), embedded components,
ADAS and automotive electronics, and panelbased processing. In conjunction with SavanSys
Solutions, wire bond, flip chip, WLP, and 3D IC
cost models are offered. TechSearch International
professionals have an extensive network ofmore than 16,000 contacts in North America,
Asia, and Europe and travel extensively, visiting
major electronics manufacturing operations andresearch facilities worldwide.
TECNISCO, LTD.
2-2-15, Minami-Shinagawa,Shinagawa-ku Tokyo, 1400004, Japan
Phone: +81-3-3472-6963
Fax: +81-3-3472-1316
www.tecnisco.co.jp/en/
Contact: Haruka Aizawa
Email: h-aizawa@tecnisco.co.jp
Booth 110TECNISCO is process service provider ofprecision component. Since established, we
have expanded the technical process field andgenerated “Cross-edge” micro processing
which means cross over the 5 (Kiru, Kezuru,
Migaku, Metalize, and assembling) cuttingedge technologies for supporting in the field of
Opto-telecommunication, Industrial lasers andMEMS devices for medical industries. We aredoing processing services and able to supply
customized parts that are manufactured withmetal, ceramic, glass and silicon by its advanced
high-precision processes and composite
technologies. TECNISCO’s expertise includes:
Dicing, Sandblasting, Milling (CNC machining),
Assembling (AuSn, AuGe, AgCuIn, AgCu),
Polishing, Bonding, Metallization (Plating,Sputtering, Vapor deposition) for producing suchas CuW, CuMoCu, CuAlNCu, Cu heatsinks (for37High power laser diode ) and Structured glass
wafer (for MEMS and Medical divice).
Teikoku Taping Systems
5090 N 40th St. Suite 140
Phoenix, AZ 85018
Phone: +1 602-367-9916
www.teikoku-taping.com
Contact: Joe Umpleby
Email: joe.umpleby@teikoku-taping.com
Booth 104
Teikoku Taping System has been a major
equipment supplier in the semiconductor industry
for more than 25 years. TTS specializes indesigning, developing and manufacturing of backend semiconductor equipment used for MEMS
dry film resist lamination, dicing, tape-and-die
attach film mounting, back grind tape lamination,and UV irradiation. Customers will be assured
because we are there to assist you throughout
your purchase, and support with processing set up
and service after installation of TTS tools. Teikoku
Taping System has three main focus areas: taping(“Haru”), de-taping (“Hagasu”) and handling(“Hakobu”).
ThreeBond International, Inc.
6184 Schumacher Park Dr.
West Chester, OH 45069
Phone: +1 408-638-7091
Fax: +1 513-779-7375
www.threebond.com
Contact: Kensuke Kitamura
Email: kkitamura@threebond.com
Booth 217
Since founded in 1955 in Japan, Threebond has
been offering the adhesive/sealant products
globally with its cutting-edge technologies.
Threebond has developed networks across six
regions: Japan, North/central Americas, south
America, Europe, Asia, and China.. Threebond
develops products mainly in the four sectors:
Transportation Equipment, Electrical andElectronics, Industrial Materials & Public Works,
and Automotive Aftermarket. Threebond
offers unique products such as UV-curing blackadhesive, 60°C x 1 minute curing elastic adhesive,
moisture blocking adhesive, UV-activated dual
curing epoxy, ultra low viscosity (2cP) UV-curingCA, high thermally conductive epoxy, etc. About
1,600 products will provide solutions to the
problems you are facing. Ask Threebond if you
need any specific adhesive or sealant.
Tohoku-MicroTec Co., Ltd.
T-Biz 203, 6-6-40 Aza-Aoba,
Aramaki, Aoba-ku,
Sendai, Miyagi 980-8579 Japan
Phone: +81-22-398-6264
Fax: +81-22-398-6265
www.t-microtec.com
Contact: Mike Hasegawa
E-mail: info@t-microtec.com
Booth 506
Tohoku-MicroTec (T-Micro) is the leading
3D/2.5D foundry service professional. Our
facility, “GINTI”, in Japan equips a new andcomplete 3D/2.5D process line of 200/300 mm
wafer. T-Micro provides worldwide customers
a wide variety of 3D-IC stacking service: full
200/300 mm wafer-to-wafer processing, chip‐
to‐wafer processing with VIA-last TSV by useof current commercial/customized 2D chips,
chip-to-chip special processing, large and thickSi-interposer processing, TSV/Micro-bump TEG

38

processing, and creation of a 2.5/3D IC process
workflow and methodology, etc. T-Micro’s
proprietary micro Au bump technology is finesize/pitch of 2.5um/5um and being utilized foradvanced sensors with millions of bumps. Our
cost‐competitive process infrastructure, using
a complete line of state‐of‐the‐art equipment,
provides worldwide customers with a cost‐effective and short‐term TAT prototyping
service for fundamental 3D‐IC R&D, technology
evaluation, “proof of concept” projects,
prototype making for mass-production, and abase‐line process development for 3D-IC/Si
interposer devices.
Tokyo Ohka Kogyo Co., Ltd.
TOK America, Inc.
190 Topaz St.
Milpitas, CA 95035
Phone: +1 408-934-8904
Fax: +1 408-956-9995
www.tok.co.jp/en/index.php
Contact: Yoshi Arai
Email: yoshi.arai@tokamerica.com
Booth 207
For over 60 years, TOK has supplied high purity
chemicals and electronic materials across theglobe. In 1971, TOK expanded its specialization
to also include process equipment production.
TOK has leveraged its microprocessing
technology across various business fields:
Semiconductor, packaging, LCDs, 3D integration,
MEMS and image sensor solutions, andcommercial products in new and emerging
technologies. Current material and equipment
offerings enable fabrication of 3DIC and include
photosensitive materials for insulation, passivation,
RDL, bump, TSV, plating, encapsulation, andother packaging related applications.
Toray International America
411 Borel Ave., Suite 520
San Mateo, CA 94402
Phone: +1 650-341-7152
Fax: +1 650-341-0845
www.toray.US/products/prod_003.
html
Contact: Hiroyuki Niwa
Email: h.niwa@toray-intl.com
Booths 407, 409
Toray Industries is a leading provider for NonConductive Film (NCF) for flip chip packages,
and photo-definable adhesive film for build-up
substrates and packages with cavity structure.
Toray’s unique polyimide and film processing
technologies provide excellent reliability andperformance which are already proven in themarket. “Photoneece” is Toray’s photo-definable
polyimide coatings for front-end buffer layer andback-end re-distribution layer for WLP and TSV.
We also offer a newly developed “Photoneece”
LT-series, which enables low temperature
cure with low residual stress for minium wafer
warpage. Toray Engineering Co., Ltd. provides
state-of-the-art Flip Chip Bonding Equipment
for semiconductor packaging (FC3000), Chip
on Wafer Bonding Equipment (FC3000W),
Vacuum Encapsulation Equipment (VE500) andvarious flexible substrates (TCP, interposer)
manufacturing equipment such as resist coater,
proximity exposure tool, etching and developing
lines.

Towa USA Corporation
1430 Tulley Rd. Ste. 416
San Jose, CA 95122
Phone: +1 408-779-4440
Fax: +1 408-779-4413
www.towajapan.co.jp
Contact: Naoki Hamada
Email: n_hamada@towajapan.co.jp
Booth 509
Towa Corporation is the market leader inproviding leading edge molding solutions to thesemiconductor industry. Towa proudly offers thelatest compression mold solutions for advanced
applications such as wafer level molding, large
panel molding, stacked die, TSV, Molded Underfill
and LED’s. Towa’s compression mold systems
have proven to be the most cost effective,
technologically advanced solutions for today’s
demanding applications. Towa also continues tobe the leader in transfer mold systems for
MCM, BGA, automotive, and medical packaging
applications. Towa has over 30 years oftransformative technological leadership to support
all your packaging needs.
Tresky GmbH
Oranienburger Chaussee 31-33
16548 Glienicke/Nordbahn
Germany
Phone: +49-33056-275 410
Fax: +49-33056-430 235
www.tresky.de
Contact: Daniel Schultze
Email: info@tresky.de
Booth 516
Tresky GmbH is a manufacturer of advanced
Automated and Manual Die Attach and Flip
Chip Systems. Tresky’s modular bonding platform
allows modular setup for new processes byadapting various options. Eutectic die bonding
with fast ramp rate heating plates, epoxy
dispensing and stamping, accommodation for
up to 12” wafers and automatic tool change arejust a few available options. For over 35 years,
Tresky has been perfecting the art of creating highprecision assembly and die bonding systems forthe semiconductor and microelectronics industry.
The fully automated bonding platforms T-6000-L
and T-8000 offering a high accurate placement in
combination with a large working area. Tresky’s
T-3000 series can generate forces up to 50kg,
using the True Vertical TechnologyTM and Beam
Splitter Optics, can achieve 1.5μm alignment
resolution.
Unisem
2241 Calle de Luna
Santa Clara, CA 95054
Phone: +1 408-734-3222
Fax: +1 408-562-9971
www.unisemgroup.com
Contact: Gil Chiu
Email: gchiu@unisemgroup.com
Booth 105
Unisem is a global provider of semiconductor
assembly and test services for many of theworld’s most successful electronics companies.
Unisem offers an integrated suite of packaging
and test services such as wafer bumping, wafer
probing, wafer grinding, a wide range of leadframeand substrate IC packaging, wafer level CSP andRF, analog, digital and mixed-signal test services.
Our turnkey services include design, assembly,
test, failure analysis, and electrical and thermal
characterization. With approximately 7,000

employees worldwide, Unisem has factory
locations in Ipoh, Malaysia; Chengdu, People’s
Republic of China and Batam, Indonesia. The
company is headquartered in Kuala Lumpur,
Malaysia.
UnitySC
611, rue Aristide Berges
ZA du Pre Millet
38330 Montbonnot Saint Martin,
FrancePhone: +33-456-52-6800
Contact: Yann Guillou
Email: contact@unity-sc.com
Booth 219
UnitySC is recognized worldwide as a key player
in inspection and metrology, combining advanced
technologies in automated optical inspection and
3D imaging with microscopy, temporal-mode
interferometry, and spectrometry, which enables
customers to deliver higher yields and fastertime to market. UnitySC provides standard andcustomized solutions adapted to specific industrial
needs and constraints, enabling a new era inprocess control. Headquartered in Grenoble,
France, the company maintains offices in Taiwan
and is supported by a network of representatives
and distributors. Customers include the largest
foundries, integrated device manufacturers,
outsourced semiconductor assembly and test
service providers, and R&D centers.
XYZTEC
36 Balch Ave.
Groveland, MA 01834
Phone: +1 978-880-2598
www.xyztec.com
Contact: Tom Haley
Email: tom.haley@xyztec.com
Booth 221XYZTEC, Inc. is the technology leader in bondtesting throughout the world. We are constantly
innovating a technology that has been basicallyunchanged for many years. Our award winning
Condor Sigma includes a Rotating Measurement
unit that allows up to 6 sensors to be available
with a mouse click. Our automation software
now includes a wire detection function that allows
complete hands off wire pull testing and our auto
grading capability makes shear-testing extremely
fast and reliable.
Yield Engineering Systems
203A Lawrence Drive
Livermore, CA 94551
Phone: +1 925-373-8353
www.yieldengineering.com
Contact:Nicole Williams-Pruitt
Email: nwilliams-pruitt@yieldengineering.com
Booth 116
Yield Engineering Systems (YES) provides awide variety of processing equipment including
ovens for the cure of dielectric materials. YES
manufactures quality equipment for the Fan-Out
Wafer Level Packaging, Semiconductor, MEMS,
Photovoltaic, FPD, Medical industries and more.
Applications for our vacuum cure ovens include
Polyimide/PBO cure, BCB bake for adhesive
wafer bonding, low temp polymer cure fortemperature sensitive devices, copper anneal to

improve electrical properties of the copper layer,
and low-K dielectric cure to remove all moisturefrom porous low-K material. Our manual andautomated vacuum cure ovens accommodate up
to 300mm wafers and offer critical improvements
in any cure process including complete removalof residual solvents, uniform temperature
distribution, pressure control, ability to maintaindry inert atmosphere, and control of heating
and cooling rates. In addition, YES ovens achieve
particle reduction in most applications. YES
equipment is engineered, manufactured andtested in Livermore, California USA. The answer
is YES to quality, flexibility, superior products andservice.
YOLE DEVELOPPEMENTLe Quartz – 75 cours Emile Zola
69100 Lyon-Villeurbanne, France
Phone: +33-472-83-01-80
Fax: +33-472-83-01-83
www.yole.fr
Contact: Camille Veyrier
Email: veyrier@yole.fr
Booth 404
Founded in 1998, Yole Développement has
grown to become a group of companies
providing marketing, technology and strategy
consulting, media and corporate finance services.
With a strong focus on emerging applications
using silicon and/or micro manufacturing,
the Yole has expanded to include more than
50 collaborators worldwide covering MEMS,
Compound Semiconductors, LED, Image
Sensors, Optoelectronics, Microfluidics &Medical, Advanced Packaging, Manufacturing,
Nanomaterials, Power Electronics and Batteries& Energy Management. The “More thanMoore” company Yole and its partners System
Plus Consulting, Blumorpho and KnowMade
support industrial companies, investors and R&D
organizations worldwide to help them understandmarkets and follow technology trends to develop
their business. CONSULTING: Market data &research, marketing analysis; Technology analysis;
Reverse engineering & costing services; Strategy
consulting; Patent analysis. REPORTS: Collectionof technology & market reports; Manufacturing
cost simulation tools; Component reverse
engineering & costing analysis; Patent investigation
MEDIA: i-Micronews.com; @Micronews, weekly
e-newsletter; Communication & webcasts
services; Events: Yole Seminars, Market Briefing.

Zuken, Inc.
1900 McCarthy Blvd.
Suite 400
Milpitas, CA 95035
Phone: +1 408-890-2831
www.zuken.com
Email: humair.mandavia@zukenusa.com
Booth 118
Zuken is a global provider of leading-edge
software and consulting services for systemlevel electrical and electronic design andmanufacturing. Founded in 1976, Zuken has
the longest track record of technologicalinnovation and financial stability in the electronic
design automation (EDA) software industry foradvanced packaging, printed circuit board design,and multi-domain co-design. The company’s
extensive experience, technological expertise andagility, combine to create world-class software
solutions. Zuken’s transparent working practices
and integrity in all aspects of business produce
long-lasting and successful customer partnershipsthat make Zuken a reliable long-term business
partner. Zuken is focused on being a long-term
innovation and growth partner. The securityof choosing Zuken is further reinforced by thecompany’s people— the foundation of Zuken’s
success. Coming from a wide range of industry
sectors, specializing in many different disciplines
and advanced technologies, Zuken’s people
relate to and understand each company’s uniquerequirements.
Zymet, Inc.
7 Great Meadow Lane
E. Hanover, NJ 07936
Phone: +1 973-428-5245
Fax: +1 973-428-5244
www.zymet.com
Contacts: Kelly Nostrame and Karl Loh
Email: info@zymet.com
Booth 321
Adhesives and encapsulants for electronics andoptoelectronics assembly. Products include
reworkable and non-reworkable underfill
encapsulants, edgefill adhesives, and edgebond
adhesives for high reliability board level assembly.  
Products also include electrically conductive andthermally conductive adhesives, ultralow stressadhesives, ACP’s and NCP’s, and UV curable
encapsulants.

ECTC SPONSORSWith 67 years of history and experiencebehind us, ECTC is recognized as the premier
semiconductor packaging conference andoffers an unparalleled opportunity to build
relationships with more than 1,000 individuals
and organizations committed to driving
innovation in semiconductor packaging.
We have a limited number of sponsorship
opportunities in a variety of packages to help getyour message out to attendees. These include
Gala, Program, and several other sponsorship

options that can be customized to yourcompany’s interest. If you would like to enhanceyour presence at ECTC and increase yourimpact with a sponsorship, please take a lookat our sponsorship brochure on the websitewww.ectc.net under “Sponsors.”
To sign-up for sponsorship or to get moredetails, please contact Wolfgang Sauter atwolfgang.sauter@globalfoundries.com
or +1-802-922-3083.

39

2017 Executive Committee
General Chair
Henning BraunischIntel Corporation
braunisch@ieee.org+1-480-552-0844

Vice-General Chair
Sam Karikalan
Broadcom Limited
sam.karikalan@broadcom.com+1-949-926-7296
Program ChairMark Poliks
Binghamton University
mpoliks@binghamton.edu+1-607-727-7104
Assistant Program Chair
Christopher Bower
X-Celeprint Inc.
cbower@x-celeprint.com+1-919-522-3230
Jr. Past General Chair ECTC
Alan Huffman
Micross Advanced Interconnect Technology
alan.huffman@micross.com+1-919-248-9216
Sr. Past General Chair ECTC
Beth Keser
Intel Corporation
beth.keser@intel.com
Sponsorship Chair
Wolfgang Sauter
GLOBALFOUNDRIES
wolfgang.sauter@globalfoundries,.com+1-802-922-3083
Finance Chair
Patrick Thompson
Texas Instruments, Inc.
patrick.thompson@ti.com+1-214-567-0660
Publications Chair
Steve Bezuk
Qualcomm Technologies, Inc.
sbezuk@qti.qualcomm.com+1-858-218-5143
Publicity Chair
Eric Perfecto
GLOBALFOUNDRIES
eric.perfecto@globalfoundries.com+1-845-894-4400
Treasurer
Tom Reynolds
T3 Group LLC
t.reynolds@ieee.org+1-850-897-7323
Exhibits Chair
Joe Gisler
Vector Associates
gislerhj.ECTC@mediacombb.net+1-480-288-6660
Web Administrator
Nancy Stoffel
GE Global Research
nstoffel1194@gmail.com+1-518-387-4529

40

Professional Development Course Chair
Kitty Pearsall
Boss Precision, Inc.
kitty.pearsall@gmail.com+1-512-845-3287
Arrangements Chair
Lisa Renzi Ragar
Renzi & Company, Inc.
lrenzi@renziandco.com+1-703-863-2223
CPMT Representative
C. P. Wong
Georgia Institute of Technology
cp.wong@mse.gatech.edu+1-404-894-8391

2017 Program Committee
Advanced Packaging
Chair
Young-Gon Kim
Integrated Device Technology, Inc.
young.kim@idt.com+1-408-360-1545
Assistant Chair
Luu Nguyen
Texas Instruments Inc.
luu.nguyen@ti.com+1-669-721-4786
Daniel Baldwin
H.B. Fuller Company
Bora Baloglu
Amkor Technology
Rozalia Beica
Dow Electronic Materials
Jianwei Dong
Dow Electronic Materials
Luke England
GLOBALFOUNDRIESAllyson Hartzell
Veryst Engineering
Beth Keser
Intel Corporation
John Knickerbocker
IBM Corporation
Steffen Kroehnert
Nanium S.A.
John H. Lau
ASM Pacific Technology
Markus Leitgeb
AT&S
Mike Ma
Amkor Technology Taiwan (ATT)
Dean Malta
Micross Advanced Interconnect Technology
Deborah S. Patterson
Principal, Patterson Group
Raj Pendse
Qualcomm Technologies, Inc.
Subhash L. Shinde
Notre Dame University
Joseph W. Soucy
Draper
Kuo-Chung Yee
TSMC
Christophe Zinck
ASE

Applied Reliability
Chair
Vikas Gupta
Texas Instruments, Inc.
gvikas@ti.com+1-214-567-3160
Assistant Chair
Deepak Goyal
Intel Corporation
deepak.goyal@intel.com+1-480-554-5203
Babak Arfaei
Ford Motor Company
Sridhar Canumalla
Microsoft Corporation
Tim Chaudhry
Amkor Technology, Inc.
Tz-Cheng Chiu
National Cheng Kung University
Darvin R. Edwards
Edwards Enterprises
Dongming He
Qualcomm Technologies, Inc.
Toni Mattila
Aalto University
Keith Newman
AMD
Donna M. Noctor
Alcatel-Lucent
S. B. Park
Binghamton University
Lakshmi N. Ramanathan
Microsoft Corporation
Richard Rao
MicroSemi
René Rongen
NXP Semiconductors
Scott Savage
Medtronic Microelectronics Center
Jeffrey Suhling
Auburn University
Dongji Xie
NVIDIA Corporation
Assembly & Manufacturing Technology
Chair
Wei KohPacrim Technology
kohmail@gmail.com+1-714-417-9979
Assistant ChairPaul Tiner
Texas Instruments
p-tiner@ti.com+1-469-471-3565
Sai Ankireddi
Maxim Integrated Products, Inc.
Garry Cunningham
NGCMark Gerber
Advanced Semiconductor Engineering Inc. USA
Paul Houston
EngentSa Huang
Medtronic Corporation
Li Jiang
Texas Instruments

Vijay Khanna
IBM Corporation
Chunho Kim
Medtronic Corporation
Yang Liu
IBM Corporation
Cheng-Hsiang (Sean) Liu
Siliconware Precision Industries Co. Ltd
Debendra Mallik
Intel Corporation
Li MingASM
Jae-Woong Nah
IBM Corporation
Valerie Oberson
IBM Corporation
Tom Poulin
Aerie Engineering
Shichun Qu
Lumileds
Shawn Shi
Medtronic Corporation
Tom Swirbel
Motorola, Inc.
Sean Too
Microsoft
Andy TsengJSR Micro
Jan Vardaman
Techsearch International
Shaw Fong WongIntel Corporation
Jin YangIntel Corporation
Tonglong Zhang
Nantong Fujitsu Microelectronics Ltd.
High-Speed, Wireless & Components
Chair
P. Markondeya Raj
Georgia Institute of Technology
raj@ece.gatech.edu+1-404 558 2615
Assistant Chair
Kemal Aygun
Intel Corporationkemal.aygun@intel.com+1-480-552-1740
Amit P. Agrawal
Keyssa Inc.
Wendem Beyene
Rambus Inc.
Eric Beyne
IMEC
Prem Chahal
Michigan State University
Zhaoqing Chen
IBM Corporation
Craig GawNXP Semiconductor
Apostolos Georgiadis
Centre Tecnologic de Telecomunicacions deCatalunya (CTTC)
Abhilash Goyal
OracleXiaoxiong (Kevin) Gu
IBM Corporation
Rockwell Hsu
Cisco Systems, Inc.
Lih-Tyng Hwang
National Sun Yat-Sen University
Mahadevan K. Iyer
Texas Instruments, Inc.
Bruce Kim
City University of New York
Timothy G. Lenihan
TechSearch International
Sebastian LiauITRI
Lianjun Liu
Freescale Semiconductor, Inc.
Nanju Na
XilinxDan OhAltera Corporation
Andrea Paganini
GLOBALFOUNDRIES, Inc.
Luca Roselli
University of Perugia
Hideki Sasaki
Renesas Electronics Corporation
Li-Cheng Shen
Quanta Research InstituteManos M. Tentzeris
Georgia Institute of Technology
Emerging Technologies
Chair
John Cunningham
Consultant
jeclaser@gmail.com+1-858-526-9121
Assistant Chair
Vaidyanathan Chelakara
Acacia Communications, Inc.
CVaidyanathan@acacia-inc.com+1-978-938-4896 x 883
Isaac Robin Abothu
Siemens Medical Solutions USA Inc.
Jai Agrawal
Purdue University
Ankur Agrawal
Intel Corporation
Meriem Akin
Leibniz Universitaet Hannover
Vasudeva P. Atluri
Renavitas Technologies
Mark Bachman
University of California, Irvine
Karlheinz Bock
Technische Universitat Dresden
Benson Chan
Binghamton University
Rabindra N. Das
MIT Lincoln Labs
Steve Greathouse
Plexus Corporation
Florian Herrault
HRL Laboratories, LLC
W. Hong YEO
Georgia Institute of Technololgy

Ramakrishna Kotlanka
Analog Devices
Kevin J. Lee
Qorvo Corporation
Menglu Li
Qualcomm Technologies, Inc.
Minhua Lu
IBM Corporation
Bharat Penmecha
Intel Corporation
C. S. Premachandran
GLOBALFOUNDRIES
Jintang ShangSoutheast University
Nancy Stoffel
GE Global Research
Maaike M. Visser Taklo
SINTEF ICT
Jimin Yao
Intel Corporation
Yue ZhangOracleInterconnections
Chair
Katsuyuki Sakuma
IBM Corporation
ksakuma@us.ibm.com+1-914-945-2080
Assistant Chair
Nathan Lower
Rockwell Collins, Inc.
nathan.lower@rockwellcollins.com+1-319-295-6687
Thibault Buisson
Yole Développement
William Chen
Advanced Semiconductor Engineering, Inc.
Kathy Cook
TesseraDavid Danovitch
University of Sherbrooke
Rajen Dias
Amkor Technology, Inc.
Bernd Ebersberger
Intel Corporation
Takafumi Fukushima
Tohoku University
Thomas Gregorich
SanDisk
Li Li
Cisco Systems, Inc.
Changqing Liu
Loughborough University
Wei-Chung Lo
ITRIJames Lu
Rensselaer Polytechnic InstituteVoya Markovich
Microelectronic Advanced Hardware Consulting,
LLC
Lou Nicholls
Amkor Technology, Inc.

41

Gilles Poupon
CEA-Leti
Lei Shan
IBM Corporation
Ho-Young Son
SK Hynix
Chuan Seng Tan
Nanyang Technological University
Matthew Yao
GE Energy Management
Dingyou Zhang
Qualcomm Technologies, Inc.

42

Materials & Processing
Chair
Bing Dang
IBM Corporation
dangbing@gmail.com+1-914-945-1568
Assistant Chair
Mikel Miller
Draper Laboratory
mrmiller@draper.com+1-617-258-2844
Tanja Braun
Fraunhofer IZMYu-Hua Chen
Unimicron
Qianwen Chen
IBM Corporation
Yung-Yu Hsu
Apple Inc.
C. Robert Kao
National Taiwan University
Dong Wook Kim
Xilinx, Inc.
Chin C. Lee
University of California, Irvine
Alvin Lee
Brewer Science
Yi LiIntel Corporation
Kwang-Lung Lin
National Cheng Kung University
Yan Liu
Medtronic Inc. USA
Daniel D. Lu
Henkel Corporation
Diptarka Majumdar
Superior Graphite
Joon-Seok Oh
Samsung Electro-Mechanics
Praveen Pandojirao-S
Johnson & Johnson
Mark Poliks
Binghamton University
Dwayne Shirley
Ivan Shubin
Lejun Wang
Qualcomm Technologies, Inc.
Frank Wei
Disco Japan
Kimberly Yess
Brewer Science
Myung Jin YimIntel Corporation

Hongbin Yu
Arizona State University
Tieyu Zheng
Microsoft Corporation
Modeling & Simulation
Chair
Kuo-Ning Chiang
National Tsinghua University
knchiang@pme.nthu.edu.tw+886-3-574-2925
Assistant Chair
Jiantao Zheng
Qualcomm Technologies, Inc.
jiantaoz@qti.qualcomm.com+1-858-658-5738
Xuejun Fan
Lamar University
Przemyslaw Gromala
Robert Bosch GmbH
Nancy Iwamote
Honeywell
Pradeep Lall
Auburn University
Sheng Liu
Wuhan University
Yong Liu
ON Semiconductor
Erdogan Madenci
University of Arizona
Tony Mak
Wentworth Institute of Technology
Erkan Oterkus
University of Strathclyde
Gamal Refai-Ahmed
Xilinx
Sandeep SaneIntel Corporation
Suresh K. Sitaraman
Georgia Institute of Technology
Wei Wang
Qualcomm Technologies, Inc.
G. Q. (Kouchi) Zhang
Delft University of Technology (TUD)
Opto-Electronics
Chair
Takaaki Ishigure
Keio University
ishigure@appi.keio.ac.jp+81-45-566-1593
Assistant Chair
Gordon Elger
Technische Hochschule Ingolstadt
gordon.elger@thi.de+49-841- 934-8284
Stephane Bernabe
CEA Leti
Fuad Doany
IBM Corporation
Soon JangficonTEC USA
Harry G. Kellzi
Teledyne Microelectronic Technologies
Masanobu Okayasu
Oclaro Japan, Inc.

Alex Rosiewicz
A2E Partners
Henning Schroeder
Fraunhofer IZM
Andrew Shapiro
JPL
Masato Shishikura
Oclaro Japan
Hiren Thacker
Masao Tokunari
IBM Corporation
Jean Trewhella
GLOBALFOUNDRIES
Shogo Ura
Kyoto Institute of Technology
Stefan Weiss
II-VI Laser Enterprise GmbH
Feng Yu
Huawei Technologies Japan
Thomas Zahner
OSRAM Opto Semiconductors GmbH
Ping Zhou
LDX Optronics, Inc.
Interactive Presentations
Chair
Michael Mayer
University of Waterloo
mmayer@uwaterloo.ca+1-519-888-4024
Assistant ChairJohn Hunt
Advanced Semiconductor Engineering, Inc.
john.hunt@aseus.com+1 480-718-8011
Swapan Bhattacharya
Engent Inc.
Rao Bonda
Amkor Technology
Mark Eblen
Kyocera America, Inc.
Ibrahim Guven
Virginia Commonwealth University
Nam Pham
IBM Corporation
Mark Poliks
Binghamton University
Patrick Thompson
Texas Instruments, Inc.
Professional Development Courses
Chair
Kitty Pearsall
Boss Precision, Inc.
kitty.pearsall@gmail.com+1-512-845-3287
Assistant Chair
Jeffrey Suhling
Auburn University
jsuhling@auburn.edu+1-334-844-3332
Vijay Khanna
IBM Corporation
Lakshmi N. Ramanathan
Microsoft Corporation

First Call for Papers
IEEE 68th Electronic Components and Technology Conference
www.ectc.net
To be held May 29 - June 1, 2018at the Sheraton San Diego Hotel & Marina, San Diego, California, USA
The Electronic Components and Technology Conference (ECTC) is the premier international electronics symposium that brings together the best in packaging, components
and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the Components,
Packaging and Manufacturing Technology (CPMT) Society of the IEEE. You are invited to submit abstracts that provide non commercial information on new developments,
technology and knowledge in the areas including, but not limited to as given below under each technical program subcommittee name. Authors are encouraged to review
the sessions of the previous ECTC programs to determine the committee selection for their abstracts.
Advanced Packaging:
Fan-Out, 2.5 & 3D, TSV and Interposer, Heterogeneous Integration and SiP,
Embedded and Advanced Substrates, MEMS & Sensors, Automotive, Power
Module, Wearable & IoT, Bio and Medical, RF, Microwave, Millimeter-Wave &EMI, High Performance Computing and Data Center, Wafer Level & Panel Level
Process, Advanced Flip-Chip, Advanced CSP and POP.
Applied Reliability:
Advanced Package Reliability (Including TSV/2.5D/3D Packaging, WCSP,
Fan-Out, Embedded Technologies), Challenges in SiP Reliability, Interconnect
Reliability (Including Flip-Chip, Wire-Bond), LED, RFID, High Voltage Packaging
and IoT Reliability, System Level Reliability Testing/Modeling, Reliability Test
Methods and Life Models, Physics of Failure, Failure Analysis Techniquesand Materials Characterization, Drop and Dynamic Mechanical Reliability,
Probabilistic Design for Reliability (PDfR), Automotive Reliability Requirements.
Assembly and Manufacturing Technology:
Embedded/Hybrid Package Manufacturing Process, Wearable/IoT Package
Assembly, Healthcare/Fitness Component Assembly, Warpage Control/
Management in Board Level Assembly, Thin Die/Thin Mold/Thin Package
Handling and Assembly, Large/Ultra Large Package (SiP, SIM, MCP) Integration
and Processing, Panel Level Manufacturing for WLP, Dicing and Singulation.
Emerging Technologies:
Wearable and Medical Electronics, Flexible, Bendable, Stretchable, Disposable, orDissolvable Packaging, Bio-Sensor Packaging, Implantable Device Packaging, New
Materials and Methods for Packaging Microfluidics, MEMS and NEMS, NanoBattery. 3D Printing, Self-Alignment and Assembly, New Additive Packaging
Process Technologies and Materials. Novel Substrates, Materials and Approaches
to Interconnects and Packaging, Packaging for Wireless, Photovoltaic,
Redundancy, Repair, Security, Anti-Counterfeiting, Components for Internetof Things (IoT) and Smart Electronics, Heterogeneous Integration. Compact &Autonomous Sensor Packaging, Wafer Level Integrated Silicon Photonics.
High-Speed, Wireless & Components:
Modules & Sub-Systems; High-Speed, RF to THz Devices & Passive
Components, Mixed-Signal; Electrical Modeling and Design; Advanced
Components: Materials, Structures, Fabrication and Characterization; Power and
Signal Integrity; High-Speed Data Transfer/Communications; Power Modules,
Power Management; Integrated Voltage Regulators (IVR); LTE, WLAN, 5G,
mm Wave and THz T/R Modules; Radars; Imagers; Wearable and Sensor
Technologies for Internet of Things (IoT); Flexible Electronics; 3D Printed RF
Components and Modules; Automotive Sensors; RF-MEMS, RF-Opto, RFID
and Tagging; M2M Platforms; Proximity Sensors; Ambient Intelligence; WirelessPower; Wireless Sensor and Computing Nodes; Wearable and Biomedical
Electronics.
You are invited to submit an abstract of no more than 750 words that describes thescope, content, and key points of your proposed paper via the website at www.
ectc.net.
If you have any questions, contact:
Dr. Christopher Bower, 68th ECTC Program Chair
X-Celeprint Inc.
3021 Cornwallis Road, Research Triangle Park, NC 27709, USA
Phone: +1-919-522-3230
E-mail: cbower@x-celeprint.com
Abstracts must be received by October 9, 2017. All abstracts must be submitted
electronically at www.ectc.net. You must include the mailing address, businesstelephone number, and email address of presenting author(s) and affiliations of all
authors with your submission.

Interconnections:Interconnections: Fan-Out and Fan-In, Wafer- and Panel-Level Interconnects,
2.5D/3D, TSV Interconnect Structures for Heterogeneous Integration and SiP,
Co-Designs and Process/Performance Trade-Off, Thermal/Mechanical/Electrical
Tests & Reliability, Embedded Systems; Si/Glass/Organic Interposers, PoP,WLCSP, Flip-Chip, Solder Bumping and Cu Pillar, TC Bonding, IMC Interconnect,
Wirebonds, RDL, Conductive Adhesives, Flexible Substrates, Power Modules,
Wearables, Interconnects for Bio-Medical, Automotive, Bio-Sensor, Energy
Harvesting, and Harsh Environments.
Materials & Processing:Wafer Level Packaging, Panel Processing & Materials, Next Generation Packaging
Substrates, Flexible and Wearable Electronics, Carbon Electronics, Battery Materials,
3D Materials and Processing, Emerging Electronic Materials, Novel Conductive andNon-Conductive Adhesives, Solder Alloys, Photoresist, Dielectrics and Under-Fill,
Molding Compounds, Thermal Interface Materials, Optoelectronic Materials.
Thermal/Mechanical Simulation & Characterization:
Thermal, Mechanical Simulation and Characterization Including: Component,
Board and System Level Modeling for Microelectronics, e.g., 3D Interconnects(TSV, Stacked Die, etc.), 2.5D Packaging (Si, Glass, Flexible Interposer, etc.),
Wafer-Level-Package (WLP), Ball-Grid-Array (BGA), Embedded Packages with
Active and Passive Components, System-in-Package (SiP), Power Electronic
Modules, LED Packaging, and MEMS; Fab/Thin Wafer Handling, Wire Bonding andAssembly Manufacture Process; Reliability Modeling Related Fracture Mechanics,
Fatigue, Electromigration, Warpage, Delamination/ Moisture, Drop Test, Material
Constitutive Relations and Characterization; Novel Modeling Including MultiScale and Multi-Physics Techniques and Solutions; Measurement Methodologies,
Characterization and Correlations.
Optoelectronics:
Integrated Photonics Modules, Fiber Optical Interconnects, Advanced Optical
Connectors, Optical Waveguide Circuits, Optical Printed Circuit Board, Mid-Board/
On-Board Optical Modules, Silicon and III-V Photonics Packaging, Optical Chip-Scaleand Heterogeneous Integration, Micro-Optical System Integration and Photonic
System-in-Package, 3D Photonics Integration, Optoelectronic Assembly andReliability, Materials and Manufacturing Technology, High-Efficiency LEDs and HighPower Lasers, Integrated Optical Sensors.
Interactive Presentations:
Abstracts may be submitted related to any of the nine major program committee
topics listed above. Interactive presentations of technical papers are highly
encouraged at ECTC. They allow for significant interaction between the presenterand attendees, which is especially suited for material that benefits from more
explanation than is practical in oral presentations. Interactive presentation session
papers are published and archived in equal merit with the other ECTC conference
papers.
Professional Development Courses
In addition to abstracts for papers, proposals are solicited from individuals interested
in teaching educational professional development courses (4 hours) on topics
described in the Call for Papers. Using the format “Course Objectives/Course
Outline/Who Should Attend,” 200-word proposals must be submitted via thewebsite at www.ectc.net by October 9, 2017.
If you have any questions, contact:
Kitty Pearsall
68th ECTC Professional Development Courses Chair
Boss Precision, Inc.
1806 W. Howard Lane, Austin, TX 78728, USA
Phone: +1-512-845-3287
E-mail: kitty.pearsall@gmail.com

43

CONFERENCE SPONSORSGold Gala Sponsors
www.amkor.com

www.cadence.com

www.dowelectronicmaterials.com

www.lintec-usa.com/

www.pactech.com

www.spts.com

www.decatechnologies.com

www.nanium.com

www.unity-sc.com/en/

Silver Gala Sponsors

www.appliedmaterials.com

www.spil.com.tw

www.ibm.com/assembly

www.suss.com

www.micron.com

www.veeco.com/technologiesandproducts/
precisionsurfaceprocessingsystems

www.zeiss.com/microscopy/int/solutions/manufacturing-assembly.html

Special & Program Sponsors

www.aseglobal.com

44

www.brewerscience.com

www.lamresearch.com

www.yieldengineering.com

CONFERENCE SPONSORS
Wednesday Luncheon Sponsor

Friday Luncheon Sponsor

Badge Lanyard Sponsor

www.aseglobal.com

www.statschippac.com

www.hdmicrosystems.com

Tote Bags Sponsor

Student Reception

Intel Student Paper Sponsor

www.emd-performance-materials.com

www.ti.com

www.intel.com

Internet Sponsor

Thumb Drive Sponsor

www.camtek.com

www.spil.com.tw

Refreshment Break Sponsors

www.agcem.com

www.atotech.com

www.fujifilmusa.com

www.inemi.org

www.jsrmicro.com

www.microsoft.com

www.namics.co.jp/e/www.qualcomm.com

www.rudolphtech.com

www.tok.co.jp/eng

Media Sponsors
Official Media Sponsor

www.chipscalereview.com

Additional Media Sponsors

www.i-micronews.com

www.3dincites.infoneedle.com

www.circuitassembly.com

www.electronics-cooling.com

www.electronics
protectionmagazine.com

www.magneticsmagazine.com

www.memsjournal.com

www.meptec.com

www.semiconductor
packagingnews.com

www.electroiq.com

45

WALT DISNEY WORLD DOLPHIN RESORT, LAKE BUENA VISTA, FLORIDA, USA

68TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE
Sheraton San Diego Hotel & Marina
San Diego, California, USA
May 29 - June 1, 2018
ECTC will be 68 years old next year and we will becelebrating in San Diego, CA! The Sheraton San Diego
Hotel & Marina is a tried and true venue for ECTC as ECTC
has been using this property for quite some time! It touts
panoramic views of the bay and the city skyline, yet is just 10
minutes from renowned attractions including the Gaslamp
Quarter, Old Town, and Balboa Park.
Dubbed by many as “the only area in the US with perfectweather,” San Diego is the oldest port on the West Coastand the sixth-largest city in the nation. Long known as a naval
base, the military, along with tourism, still dominates the
economy. In addition to rolling mountains, beautiful deserts,
and seventy miles of coastline featuring some of the world’s
best beaches, San Diego offers a wealth of attractions. Art
lovers can choose from many fine museums or catch a
Shakespearean play at the Old Globe Theater. With more
championship golf courses, over 85, than any other US city,
you won’t have a problem teeing off. The city also hosts the
Major League Baseball’s Padres. And one last thing, don’t
forget to take time to visit the world-renowned San Diego
Zoo!

46

Conference At A Glance
MONDAYMay 29, 2017
3:00 p.m. – 5:00 p.m.
Registration
Australia Foyer
TUESDAY
May 30, 2017
6:45 a.m. – 5:00 p.m.
Registration
Australia Foyer
6:45 a.m. – 8:15 a.m.
Morning PDC Registration Only
7:00 a.m. – 7:45 a.m.
PDC Instructors and Proctors
Briefing & Breakfast
Asia 1

3:00 p.m. – 3:20 p.m.
Afternoon PDC BreakSouthern Hemisphere Foyer andNorthern Hemisphere E Foyer

2:00 p.m. – 4:00 p.m.
Session 38: Interactive
Presentations 2
Northern Hemisphere Foyer

5:00 p.m. – 6:00 p.m.
ECTC Student Reception
Cabana Deck
Backup: Asia 1

2:45 p.m. – 3:30 p.m.
Refreshment BreakNorthern Hemisphere A-C

6:00 p.m. – 7:00 p.m.
General Chair’s Speakers
Reception
Crescent Terrace on Swan
Property
Backup: Northern Hemisphere D-E
By invitation only

5:30 p.m. – 6:30 p.m.
Technology Corner Reception
Northern Hemisphere A-C
6:30 p.m. – 7:30 p.m.
CPMT Women’s Panel &Reception
Southern Hemisphere IV

2:00 p.m. – 4:00 p.m.
Session 40: Interactive
Presentations 4
Northern Hemisphere Foyer
2:45 p.m. – 3:30 p.m.
Refreshment BreakNorthern Hemisphere A-C
6:30 p.m. – 7:30 p.m.
67th ECTC Gala Reception
Lake Terrace on Swan Property
Backup: Northern Hemisphere D-E
8:00 p.m. – 9:30 p.m.
CPMT Seminar
Southern Hemisphere II & III

7:30 p.m. – 9:00 p.m.
ECTC Panel Session
Southern Hemisphere II & III

7:30 p.m. – 9:00 p.m.
ECTC Plenary Session
Southern Hemisphere II & III

WEDNESDAY
May 31, 2017
6:45 a.m. – 4:00 p.m.
Conference Registration
Australia Foyer

THURSDAY
June 1, 2017
7:00 a.m. – 5:00 p.m.
Speaker Preparation
Europe 2

7:00 a.m. – 7:45 a.m.
Today’s Speakers Breakfast
Northern Hemisphere E 3-4

7:00 a.m. – 7:45 a.m.
Today’s Speakers Breakfast
Northern Hemisphere E 3 & 4

7:00 a.m. – 7:45 a.m.
Today’s Speakers Breakfast
Northern Hemisphere E 3-4

7:00 a.m. – 5:00 p.m.
Speaker Preparation
Europe 2

7:30 a.m. – 4:00 p.m.
Conference Registration
Australia Foyer

7:30 a.m. – Noon
Conference Registration
Australia Foyer

8:00 a.m. – 11:40 a.m.
Sessions 1, 2, 3, 4, 5, 6
See pages 10–11 for Locations

8:00 a.m. – 11:40 a.m.
Sessions 13, 14, 15, 16, 17, 18
See pages 14–15 for Locations

9:00 a.m. – 11:00 a.m.
Session 37: Interactive
Presentations 1
Northern Hemisphere Foyer

9:00 a.m. – 11:00 a.m.
Session 39: Interactive
Presentations 3
Northern Hemisphere Foyer

9:00 a.m. – Noon
Technology Corner Exhibits
Northern Hemisphere A-C

9:00 a.m. – Noon
Technology Corner Exhibits
Northern Hemisphere A-C

9:15 a.m. – 10:00 a.m.
Refreshment BreakNorthern Hemisphere A-C

9:15 a.m. – 10:00 a.m.
Refreshment BreakNorthern Hemisphere A-C

1:00 p.m. – 5:00 p.m.
Technology Corner Setup
Northern Hemisphere A-C

Noon
ECTC Luncheon
Northern Hemisphere D-E

Noon
CPMT Luncheon
Northern Hemisphere D-E

1:15 p.m. – 5:15 p.m.
Afternoon PDCs
See page 8 for locations

1:30 p.m. – 6:30 p.m.
Technology Corner Exhibits
Northern Hemisphere A-C

1:30 p.m. – 4:00 p.m.
Technology Corner Exhibits
Northern Hemisphere A-C

2:00 p.m. – 3:30 p.m.
ECTC Special Session
Southern Hemisphere I

1:30 p.m. – 5:10 p.m.
Sessions 7, 8, 9, 10, 11, 12
See pages 12–13 for Locations

1:30 p.m. – 5:10 p.m.
Sessions 19, 20, 21, 22, 23, 24
See pages 16–17 for Locations

7:00 a.m. – 5:00 p.m.
Speaker Preparation
Europe 2
9:30 a.m. – 5:30 p.m.
iNEMI Meeting
Oceanic 1
By invitation only
8:00 a.m. – Noon
Morning PDCs
See page 8 for locations
8:00 a.m. – 5:00 p.m.
CPMT Heterogeneous Integration
Technology Roadmap Workshop
Europe 4
10:00 a.m. – 11:30 a.m.
ECTC Special Session
Southern Hemisphere I
10:00 a.m. – 10:20 a.m.
Morning PDC BreakSouthern Hemisphere Foyer andNorthern Hemisphere E Foyer
Noon
PDC Luncheon
Northern Hemisphere D-E

FRIDAY
June 2, 2017
7:00 a.m. – 5:00 p.m.
Speaker Preparation
Europe 2

8:00 a.m. – 11:40 a.m.
Sessions 25, 26, 27, 28, 29, 30
See pages 18–19 for Locations
8:30 a.m. – 10:30 a.m.
Student Interactive Presentation
SessionNorthern Hemisphere Foyer
9:15 a.m. – 10:00 a.m.
Refreshment BreakSouthern Hemisphere Foyer
Noon
ECTC Program Chair Luncheon
Northern Hemisphere D-E
1:30 p.m. – 5:10 p.m.
Sessions 31, 32, 33, 34, 35, 36
See pages 20–21 for Locations
2:45 p.m. – 3:30 p.m.
Refreshment BreakSouthern Hemisphere Foyer

47

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