PTN3363
Low power HDMI/DVI level shifter with active DDC buffer,supporting 3.4 Gbit/s operationRev. 1 — 12 August 2014

Product data sheet

1. General description
PTN3363 is a low power, high-speed level shifter device which converts four lanes of
low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant
open-drain current-steering differential output signals, up to 3.4 Gbit/s per lane to support
36-bit deep color mode, 4K  2K video format or 3D video data transport. Each of theselanes provides a level-shifting differential active buffer, with built-in Equalization, totranslate from low-swing AC-coupled differential signaling on the source side, toTMDS-type DC-coupled differential current-mode signaling terminated into 50  to 3.3 V
on the sink side. Additionally, the PTN3363 provides a single-ended active buffer forvoltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source sideand provides a channel with active buffering and level shifting of the DDC channel(consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The
DDC channel is implemented using active I2C-bus buffer technology providing redriving
and level shifting as well as disablement (isolation between source and sink) of the clock
and data lines.
The low-swing AC-coupled differential input signals to the PTN3363 typically come from adisplay source with multi-mode I/O, which supports multiple display standards, forexample, DisplayPort, HDMI and DVI. While the input differential signals are configured tocarry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.4b specification. By using PTN3363, chip set vendors are able toimplement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See Figure 1.
The PTN3363 main high-speed differential lanes feature low-swing self-biasing differential
inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2aand/or PCI Express Standard v1.1, and open-drain current-steering differential outputs
compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The I2C-bus channel
actively buffers as well as level-translates the DDC signals. The PTN3363 supports
standby mode in order to minimize current consumption when Hot Plug Detect signal
HPD_SINK is LOW.
PTN3363 is powered from a single 3.3 V power supply consuming a small amount of
power (72 mW typical) and is offered in a 32-terminal HVQFN32 package.

PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

MULTI-MODE DISPLAY SOURCEOE_NPTN3363

reconfigurable I/Os
DP PHY ELECTRICAL
TMDS
coded
data

DP
output buffer
TX
FF

OUT_D4+
OUT_D4−AC-coupled
differential pair
TMDS data
IN_D4+DATA LANE

IN_D4−

TX
TMDS
coded
data

DP
output buffer
TX
FF

AC-coupled
differential pair
TMDS data

OUT_D3+
OUT_D3−
IN_D3+DATA LANE

IN_D3−TX
DP
output buffer
TX
FF

AC-coupled
differential pair
TMDS data
DATA LANE

OUT_D2+
OUT_D2−
IN_D2+

DVI/HDMI CONNECTOR

TMDS
coded
data

IN_D2−

TX
TMDS
clock
patternDP
output buffer
TX
FF

OUT_D1+
OUT_D1−AC-coupled
differential pairclock
CLOCK LANE

IN_D1+
IN_D1−TX

0 V to 3.3 V

HPD_SOURCE

binary inputs

EQ0/EQ1

3.3 V

DDC_EN

3.3 V

DDET

3.3 V

SCL_SOURCEHPD_SINK

0 V to 5 V

5V

SCL_SINK

3.3 V

5V

DDC I/O(I2C-bus)
CONFIGURATIONSDA_SOURCESDA_SINKHIZ_EN002aah235

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to IN_D[4:1].

Fig 1.

Typical HDMI/DVI level shifter application system diagram

PTN3363

Product data sheet

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

MULTI-MODE DISPLAY SOURCEOE_NHDMI SOURCE

AVCC(3.3 V)50 Ω

50 Ω

PTN3363

AC-coupled
differential pair
TMDS data
IN_D4+DATA LANE

IN_D4−

OUT_D4+
OUT_D4−

IN_D3+

OUT_D3+
OUT_D3−

TMDS data
enableAVCC(3.3 V)50 Ω

50 Ω

AC-coupled
differential pair
TMDS data
DATA LANE

IN_D3−TMDS data
AVCC(3.3 V)50 Ω

50 Ω

AC-coupled
differential pair
TMDS data
DATA LANE

OUT_D2+
OUT_D2−
IN_D2+

DVI/HDMI CONNECTOR

enable

IN_D2−TMDS data
enableAVCC(3.3 V)50 Ω

50 Ω

OUT_D1+
OUT_D1−AC-coupled
differential pairclock
CLOCK LANE

IN_D1+
IN_D1−TMDS data
0 V to 3.3 V

enableHPD_SOURCE

binary inputs

EQ0/EQ1

3.3 V

DDC_EN

3.3 V

DDET

3.3 V

SCL_SOURCEHPD_SINK

0 V to 5 V

5V

SCL_SINK

3.3 V

5V

DDC I/O(I2C-bus)
CONFIGURATIONSDA_SOURCESDA_SINKHIZ_EN002aah251

Fig 2.

Typical HDMI redriver application system diagram

PTN3363

Product data sheet

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

2. Features and benefits
2.1 High-speed TMDS level shifting Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals
 TMDS level shifting operation up to 3.4 Gbit/s per lane (340 MHz TMDS clock)supporting 4K  2K 3 Gbit/s and 3D video formats
 Programmable receive equalization
 Integrated 50  termination resistors for self-biasing differential inputs
 Programmable high-impedance termination resistors for HDMI redriver usage withexternal 50  termination resistors
 Back-current safe outputs to disallow current when device power is off and monitor ison Disable feature to turn off TMDS inputs and outputs and to enter low power condition Selectable differential output termination on TMDS channels

2.2 DDC level shifting Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side andvice versa)
 Rise time accelerator on connector side DDC ports
 Up to 400 kHz I2C-bus clock frequency
 Back-power safe sink-side terminals to disallow backdrive current when power is off orwhen DDC is not enabled

2.3 HPD level shifting HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, orfrom 5 V on the sink side to 3.3 V on the source side Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ whenno display is plugged in Back-power safe design on HPD_SINK to disallow backdrive current when power is off

2.4 HDMI dongle detection support
 Incorporates I2C-bus slave ROM
 Responds to DDC read to address 81h
 Feature enabled by pins DDET and DDC_EN (must be enabled for correct operation inaccordance with DisplayPort interoperability guideline)

2.5 General






PTN3363

Product data sheet

Power supply 2.8 V to 3.6 V
ESD resilience to 8 kV HBM, 1 kV CDM
Power-saving modes
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no retiming or software configuration required
32-terminal HVQFN32 package
All information provided in this document is subject to legal disclaimers.

Rev. 1 — 12 August 2014

© NXP B.V. 2014. All rights reserved.

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

3. ApplicationsPC motherboard/graphics card
Docking station
DisplayPort to HDMI adapters supporting 4K  2K and 3D video formats
DisplayPort to DVI adapters required to drive long cables

4. Ordering information
Table 1.

Ordering information

Type number
PTN3363BS

Topside markP3363

Package
Name

Description

Version

HVQFN32

plastic thermal enhanced very thin quad flat package;no leads; 32 terminals; body 5  5  0.85 mm

SOT617-3

4.1 Ordering options
Table 2.

Ordering options

Type number

Orderable
part number

Package

Packing method

Minimum
order
quantity

Temperature

PTN3363BS

PTN3363BSMP

HVQFN32

Reel 13” Q2/T3*standard mark SMD dry pack

6000

Tamb = 40 C to +105 C

PTN3363

Product data sheet

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

5. Functional diagram

OE_N

input bias

PTN3363
enableRterm

OUT_D4+
OUT_D4−

Rterm

IN_D4+
IN_D4−

EQ
enableinput bias
enableRterm

OUT_D3+
OUT_D3−

Rterm

IN_D3+
IN_D3−

EQ
enableinput bias
enableRterm

OUT_D2+
OUT_D2−

Rterm

IN_D2+
IN_D2−

EQ
enableinput bias
enableRterm

IN_D1+
IN_D1−

EQ
enable

EQ0/EQ1
HPD_SOURCE(0 V to 3.3 V)

OUT_D1+
OUT_D1−Rterm

HPD level shifter
HPD_SINK(0 V to 5 V)

200 kΩ

HIZ_ENSYSTEM CONTROL

DDC_EN (0 V to 3.3 V)
SCL_SOURCESDA_SOURCE

I2C-BUSSLAVEROM

SCL_SINK

DDC BUFFERANDLEVEL SHIFTERSDA_SINK

002aah236

DDET

Rterm = 50  (typical) when HIZ_EN = LOW; >100 k when HIZ_EN = HIGH.

Fig 3.

PTN3363

Product data sheet

Functional diagram of PTN3363

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

6. Pinning information

25 IN_D1−

26 IN_D1+

27 IN_D2−

28 IN_D2+

29 IN_D3−

30 IN_D3+

terminal 1
index area

31 IN_D4−

32 IN_D4+

6.1 Pinning

VDD

1

24 HIZ_EN

EQ1

2

23 n.c.

DDET

3

22 DDC_EN

REXT

4HPD_SOURCE

5

SDA_SOURCE

6

SCL_SOURCE

7

EQ0

8

21 HPD_SINKPTN3363BS

20 SDA_SINK
19 SCL_SINK
18 VDD
OUT_D1− 16

OUT_D1+ 15

OUT_D2− 14

OUT_D2+ 13

OUT_D3− 12

17 OE_N
OUT_D3+ 11

9
OUT_D4+

OUT_D4− 10GND002aah237

Transparent top view

HVQFN32 package supply ground is connected to the exposed center pad. The exposed centerpad must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board level performance, the exposed pad must be soldered to the board using acorresponding thermal pad on the board and for proper heat conduction through the board, thermal
vias must be incorporated in the PCB in the thermal pad region.

Fig 4.

Pin configuration for HVQFN32

6.2 Pin description
Table 3.

Pin description

SymbolPin

Type

Description

OE_N, IN_Dx and OUT_Dx signals
OE_N

17

3.3 V low-voltage
CMOS single-ended
input

Output Enable and power-saving function for high-speed differential
level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-Z
OUT_Dx outputs = high-Z; zero output current
When OE_N = LOW:
IN_Dx termination = 50 
OUT_Dx outputs = active

IN_D4+

32

Self-biasing
differential input

Low-swing differential input from display source. IN_D4+ makes adifferential pair with IN_D4. The input to this pin must be AC coupledexternally.

IN_D4

31

Self-biasing
differential input

Low-swing differential input from display source. IN_D4 makes adifferential pair with IN_D4+. The input to this pin must be AC coupledexternally.

PTN3363

Product data sheet

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

Table 3.

Pin description …continued

SymbolPin

Type

Description

IN_D3+

30

Self-biasing
differential input

Low-swing differential input from display source. IN_D3+ makes adifferential pair with IN_D3. The input to this pin must be AC coupledexternally.

IN_D3

29

Self-biasing
differential input

Low-swing differential input from display source. IN_D3 makes adifferential pair with IN_D3+. The input to this pin must be AC coupledexternally.

IN_D2+

28

Self-biasing
differential input

Low-swing differential input from display source. IN_D2+ makes adifferential pair with IN_D2. The input to this pin must be AC coupledexternally.

IN_D2

27

Self-biasing
differential input

Low-swing differential input from display source. IN_D2 makes adifferential pair with IN_D2+. The input to this pin must be AC coupledexternally.

IN_D1+

26

Self-biasing
differential input

Low-swing differential input from display source. IN_D1+ makes adifferential pair with IN_D1. The input to this pin must be AC coupledexternally.

IN_D1

25

Self-biasing
differential input

Low-swing differential input from display source. IN_D1 makes adifferential pair with IN_D1+. The input to this pin must be AC coupledexternally.

OUT_D4+

9

TMDS differential
outputHDMI-compliant TMDS output. OUT_D4+ makes a differential pair with
OUT_D4. OUT_D4+ is in phase with IN_D4+.

OUT_D4

10

TMDS differential
outputHDMI-compliant TMDS output. OUT_D4 makes a differential pair with
OUT_D4+. OUT_D4 is in phase with IN_D4.

OUT_D3+

11

TMDS differential
outputHDMI-compliant TMDS output. OUT_D3+ makes a differential pair with
OUT_D3. OUT_D3+ is in phase with IN_D3+.

OUT_D3

12

TMDS differential
outputHDMI-compliant TMDS output. OUT_D3 makes a differential pair with
OUT_D3+. OUT_D3 is in phase with IN_D3.

OUT_D2+

13

TMDS differential
outputHDMI-compliant TMDS output. OUT_D2+ makes a differential pair with
OUT_D2. OUT_D2+ is in phase with IN_D2+.

OUT_D2

14

TMDS differential
outputHDMI-compliant TMDS output. OUT_D2 makes a differential pair with
OUT_D2+. OUT_D2 is in phase with IN_D2.

OUT_D1+

15

TMDS differential
outputHDMI-compliant TMDS output. OUT_D1+ makes a differential pair with
OUT_D1. OUT_D1+ is in phase with IN_D1+.

OUT_D1

16

TMDS differential
outputHDMI-compliant TMDS output. OUT_D1 makes a differential pair with
OUT_D1+. OUT_D1 is in phase with IN_D1.

21

5 V CMOS
single-ended input

0 V to 5 V (nominal) input signal. This signal comes from the DVI or
HDMI sink. A HIGH value indicates that the sink is connected; a LOW
value indicates that the sink is disconnected. HPD_SINK is pulled downby an integrated 200 k pull-down resistor.

HPD_SOURCE 5

3.3 V CMOS
single-ended output

0 V to 3.3 V (nominal) output signal. This is level-shifted version of the
HPD_SINK signal.

SCL_SOURCE 7

single-ended 3.3 V
open-drain DDC I/O

3.3 V source-side DDC clock I/O. Pulled up by external termination to
3.3 V. 5 V tolerant I/O.

SDA_SOURCE 6

single-ended 3.3 V
open-drain DDC I/O

3.3 V source-side DDC data I/O. Pulled up by external termination to
3.3 V. 5 V tolerant I/O.

SCL_SINK

single-ended 5 V
open-drain DDC I/O

5 V sink-side DDC clock I/O. Pulled up by external termination to 5 V.
Provides rise time acceleration for LOW-to-HIGH transitions.

HPD and DDC signals
HPD_SINK

19

PTN3363

Product data sheet

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

Table 3.

Pin description …continued

SymbolPin

Type

Description

SDA_SINK

20

single-ended 5 V
open-drain DDC I/O

5 V sink-side DDC data I/O. Pulled up by external termination to 5 V.
Provides rise time acceleration for LOW-to-HIGH transitions.

DDC_EN22

3.3 V CMOS input

Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is disabled.
When DDC_EN = HIGH, buffer and level shifter are enabled.

Supply and ground
VDD

1, 18

2.8 V to 3.3 V DC
supplySupply voltage; 3.3 V  10 %.

GND[1]

centerpadgroundSupply ground. The exposed center pad must be connected to system
ground for proper operation.

Feature control signals
REXT

4

analog I/O

Current sense port used to provide an accurate current reference for thedifferential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 12.4 k resistor (1 % tolerance) from this terminal to GND is
recommended. May also be tied to GND directly (0 ). See Section 7.2
for details.

DDET

3

3.3 V input

Dongle detect enable input. When HIGH, the dongle detect function via
I2C is active. When LOW, the dongle detect function does not respondto an I2C-bus command. Must be tied to GND or VDD either directly or
via a resistor. Note that this pin may not be left open-circuited. Whenused in an HDMI dongle, this pin must be tied HIGH for correct
operation in accordance with DisplayPort interoperability guideline.
When used in a DVI dongle, this pin must be tied LOW.

EQ1

2

EQ0

8

3.3 V low-voltage
CMOS inputs

Equalizer setting input pins. These pins can be board-strapped to one
of two decode values: short to GND, short to VDD. See Table 5 for truth
table.

HIZ_EN24

high input impedancecontrol input

If HIZ_EN pin is HIGH, the input interface IN_Dx has high-Z
terminations. If the pin is LOW, the input interface has 50  (typical)
termination.

n.c.

23

-

Not connected; leave this pin open.

[1]

HVQFN32 package supply ground is connected to the exposed center pad. The exposed center pad must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad must be soldered
to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias must be
incorporated in the PCB in the thermal pad region.

PTN3363

Product data sheet

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Rev. 1 — 12 August 2014

© NXP B.V. 2014. All rights reserved.

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PTN3363

NXP Semiconductors

Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

7. Functional description
Refer to Figure 3 “Functional diagram of PTN3363”.
The PTN3363 level shifts four lanes of low-swing AC-coupled differential input signals to
DVI and HDMI-compliant open-drain current-steering differential output signals, up to
3.4 Gbit/s per lane to support 36-bit deep color, 3 Gbit/s and 3D modes. It has integrated
50  termination resistors for AC-coupled differential input signals. An enable signal
OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power
consumption to ultra low level. The TMDS outputs are back-power safe to disallow current
flow from a powered sink while the PTN3363 is unpowered.
The PTN3363’s DDC channel provides active level shifting and buffering, allowing 3.3 V
source-side termination and 5 V sink-side termination. The sink-side DDC ports areequipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet/exceed
HDMI DDC specification. Furthermore, the DDC channel is augmented with an I2C-bus
slave ROM device that provides optional HDMI dongle detect response, which can be
enabled by dongle detect pin DDET. The PTN3363 offers back-power safe sink-side I/Os
to disallow backdrive current from the DDC clock and data lines when power is off or when
DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block.
Remark: When used in an HDMI dongle, the DDET function must be enabled for correct
operation in accordance with DisplayPort interoperability guideline. When used in a DVI
dongle, the DDET function must be disabled.
The PTN3363 also provides voltage translation for the Hot Plug Detect (HPD) signal from
0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.
The PTN3363 does not retime any data. It contains no state machines. No inputs or
outputs of the device are latched or clocked. Because the PTN3363 acts as a transparent
level shifter, no reset is required.
Additional use case of PTN3363: PTN3363 can also be used in pure/native HDMI
redriver applications wherein the input signal is already HDMI-compliant. In thisapplication, the PTN3363 shall be connected as illustrated in Figure 2. The AC coupling
capacitors used are similar to that of DP++ use case.

7.1 Enable and disable features
PTN3363 offers different ways to enable or disable functionality, using the Output Enable(OE_N), and DDC Enable (DDC_EN) inputs. Whenever the PTN3363 is disabled(OE_N = HIGH and DDC_EN = LOW), the device is in Ultra low power mode and power
consumption is ultra low; otherwise the PTN3363 is in active mode and power
consumption depends on level of HPD_SINK signal. These two inputs each affect theoperation of PTN3363 differently: OE_N controls the TMDS channels, DDC_EN controls
only the DDC channel, and HPD_SINK is not affected by either of the control inputs. The
following sections and truth table describe their detailed operation.

7.1.1 Hot plug detect
The HPD channel of PTN3363 functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device(via output HPD_SOURCE). The HPD_SINK level is used to control the power state of the
PTN3363

Product data sheet

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PTN3363

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Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

PTN3363. If HPD_SINK is LOW, then PTN3363 is in standby mode. Once HPD_SINK
goes HIGH, the PTN3363 can operate and its behavior is controlled further by othercontrol pins — OE_N, DDC_EN, HIZ_EN.
The HPD channel operates independent of all these control signals.
HPD_SOURCE output follows the HPD_SINK input regardless of the power mode.

7.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turnedon.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in ahigh-impedance state. The IN_Dx input buffers are disabled and IN_Dx termination isdisabled. Power consumption is minimized.
Remark: Note that OE_N signal level has no influence on the HPD_SINK input,
HPD_SOURCE output, or the SCL and SDA level shifters.

7.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When
DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should neverchange state during an I2C-bus operation. Note that disabling DDC_EN during a bus
operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt theI2C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. The DDC
channel enable (DDC_EN) and TMDS output enable (OE_N) can be controlled
independent of each other.

7.1.4 TMDS high input impedance termination (HIZ_EN)
The HIZ_EN pin is an active HIGH input and it is used to provide high input impedance on
the high-speed inputs (IN_Dx).
When HIZ_EN is LOW, 50  termination resistors are enabled on IN_Dx and thisconfiguration option is used for HDMI level shifter use case.
If HIZ_EN is HIGH, high input impedance is presented on IN_Dx and this configuration
option is used when PTN3363 is used for native HDMI redriver use cases. In the native
redriver use case, external 50  termination resistors on the application are pulled up to
VDD.

PTN3363

Product data sheet

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Rev. 1 — 12 August 2014

© NXP B.V. 2014. All rights reserved.

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PTN3363

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Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

7.1.5 Enable/disable truth table
Table 4.

HPD_SINK, OE_N, HIZ_EN and DDC_EN enabling truth table

InputsChannels

Mode
OUT_Dx[2]HPD_SINK OE_N DDC_EN IN_Dx

DDC[3][1]

HPD_SOURCE
[4]

LOW

LOW

LOW

high-Z

high-Z

high-Z

LOWStandby

LOW

LOW

HIGH

high-Z

high-Z

high-Z

LOWStandby

LOW

HIGH

LOW

high-Z

high-Z

high-Z

LOW

Ultra low
power

LOW

HIGH

HIGH

high-Z

high-Z

high-Z

LOWStandby

HIGH

LOW

LOW

50  termination to
VRX(bias) if
HIZ_EN = LOW.

outputs areenabledhigh-Z

HIGH

Active;DDC
disabled

outputs areenabled

SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE

HIGH

Active;DDC
enabled>100 k termination
to VRX(bias) if
HIZ_EN = HIGH.
HIGH

LOW

HIGH

50  termination to
VRX(bias) if
HIZ_EN = LOW.
>100 k termination
to VRX(bias) if
HIZ_EN = HIGH.

HIGH

HIGH

LOW

high-Z

high-Z

high-Z

HIGH

Ultra low
power

HIGH

HIGH

HIGH

50  termination to
VRX(bias) if
HIZ_EN = LOW.

high-ZSDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE

HIGH

Standby;DDC
enabled>100 k termination
to VRX(bias) if
HIZ_EN = HIGH.
[1]

A LOW level on input DDC_EN disables only the DDC channel.

[2]

OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.

[3]

DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.

[4]

The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.

7.2 Analog current reference
The REXT pin (pin 6) is an analog current sense port used to provide an accurate current
reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 12.4 k resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 12.4 k  1 % resistor is not used, this pin can be connected to GND or VDD
directly (0 ). In any of these cases, the output functions normally but at reduced
accuracy over voltage and temperature of the following parameters: output levels (VOL),
differential output voltage swing, and rise and fall time accuracy.

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Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

7.3 Equalizer
The PTN3363 supports four level equalization settings based on binary input pins EQ0
and EQ1.
Table 5.

Equalizer settings

InputsEqualization for 3 Gbit/s

EQ1

EQ0

short to GND

short to GND

0 dB

short to GND

short to VDD

2 dB

short to VDD

short to GND

4 dB

short to VDD

short to VDD

6 dB

7.4 Backdrive current protection
The PTN3363 is designed for backdrive protection on all sink-side TMDS outputs,
sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where thedisplay is connected and powered, but the PTN3363 is unpowered. In these cases, thePTN3363 sinks no more than a negligible amount of leakage current, and blocks thedisplay (sink) termination network from driving the power supply of the PTN3363 or that of
the inactive DVI or HDMI source or back into the VDD power supply rail.

7.5 Squelch function
PTN3363 operates only when the input signal level is above certain minimum threshold(as per VRX_DIFFp-p). If the input falls below that minimum threshold, the outputs are
squelched.

7.6 Active DDC buffer with rise time accelerator
The PTN3363 DDC channel, besides providing 3.3 V to 5 V level shifting, includes active
buffering and rise time acceleration for reliable DDC applications. While retaining all theoperating modes and features of the I2C-bus system during the level shifts, it permits
extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) andthe clock (SCL) line as well as the rise time accelerator on the sink-side port (SCL_SINK
and SDA_SINK) enabling the bus to drive a load up to 1400 pF and 400 pF on thesource-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3363 for DVI or
HDMI level shifting enables the system designer to isolate bus capacitance tomeet/exceed HDMI DDC specification. The SDA and SCL pins are overvoltage tolerant inhigh-impedance when the PTN3363 is unpowered or when DDC_EN is LOW.
PTN3363 has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)
only. During positive bus transitions on the sink-side port, a current source is switched on
to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus VIL
threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus VIH
threshold voltage of approximately 3.5 V is approached.

7.7 I2C-bus based HDMI dongle detection
The PTN3363 includes an on-board I2C-bus slave ROM which provides a means to detect
the presence of an HDMI dongle by the system through the DDC channel, accessible via
ports SDA_SOURCE and SCL_SOURCE. This allows system vendors to detect HDMI
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dongle presence through the already available DDC/I2C-bus port using a predeterminedbus sequence. See Section 8 for more information.
For the I2C-bus HDMI Dongle Detect function to be active, input pin DDET (dongle detect)should be tied HIGH. When DDET is LOW, the PTN3363 does not respond to an I2C-bus
command. When used in an HDMI dongle, the DDET function must be enabled forcorrect operation in accordance with DisplayPort interoperability guideline. When used ina DVI dongle, the DDET function must be disabled.
The HDMI dongle detection is accomplished by accessing the PTN3363 on-board I2C-bus
slave ROM using a simple sequential I2C-bus Read operation as described below.

7.7.1 Slave address
bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

1

0

0

0

0

0

0

R/W

slave address

002aad340

R = 1; W = 0

Fig 5.

PTN3363 slave address

7.7.2 Read operation
The slave device address of PTN3363 is 80h1. PTN3363 responds to a Read command toslave address 81h (PTN3363 responds with an ACK to a Write command to address 80h).
Following the Read command, the PTN3363 responds with the contents of its internalROM, as a sequence of 16 bytes, for as long as the master continues to issue clock edges
with an acknowledge after each byte. The 16-byte sequence represents the ‘DP-HDMI
ADAPTOR<EOT>’ symbol converted to ASCII and is documented in Table 6.
The PTN3363 auto-increments its internal ROM address pointer (0x0 through 0x0F) as
long as it continues to receive clock edges from the master with an acknowledge after
each byte. If the master continues to issue clock edges past the 16th byte, the PTN3363
does not necessarily respond with 0xFF. If the master does not acknowledge a received
byte, the PTN3363 internal address pointer is reset to 0 and a new Read sequence should
be started by the master. Access to the 16-byte is by sequential read only as describedabove; there is no random-access possible to any specific byte in the ROM.

1.

A ‘dummy write’ to subaddress 0x00 is required before the I2C-bus master can read the content of the internal ROM.

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Low power HDMI/DVI level shifter supporting 3.4 Gbit/s operation

Table 6.

DisplayPort - HDMI Adaptor Detection ROM content

Internal pointer offset(hexadecimal)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Data (hexadecimal)

44

50

2D

48

44

4D

49

20

41

44

41

50

54

4F

52

04

Table 7.
Phase

HDMI dongle detect transaction sequence outline
I2C transaction

Transmitting

1

START

master2

Write command

master3

Acknowledge

slave

4

Word address offset

masterBit

Status

7

6

5

4

3

2

1

R/W

MasterSlavemandatory

-

1

0

0

0

0

0

0

0

mandatory--

mandatory

mandatory-

word address offset data byte

5

Acknowledge

slave

-

mandatory

6

STOP

masteroptional

-

7

START

mastermandatory-

8

Read command

mastermandatory-

9

Acknowledge

slave

10

Read data

slave

11

Acknowledge

master12

Read data

slave

13

:

:

:

40

Read data

slave

41

Not Acknowledge

42

STOP

1

0

0

0

0

0

0

1

-

mandatory-

mandatory

mandatory--

mandatory

:

-

-

:

-

-

-

mandatory

mastermandatory-

mastermandatory-

data byte at offset 0
data byte at offset 1

data byte at offset 15

Remark: If the slave does not acknowledge the above transaction sequence, the entire
sequence should be retried by the source.

7.8 Power management
PTN3363 implements innovative power management scheme whereby it achieves very
low power consumption in both active and standby modes. Based on OE_N, DDC_EN,
HPD_SNK, the PTN3363 intelligently optimizes the power consumption and disables
outputs (OUT_Dx). Refer to Table 8.

PTN3363

Product data sheet

Table 8.

Power management schemes

OE_N

DDC_ENHPD_SINK

Source output

PTN3363 power mode

LOW

HIGH

HIGH

source active

Active mode; DDC active

LOW

HIGH

LOW

high-Z

Standby mode

HIGH

LOW

don’t carehigh-Z

Ultra low power mode

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8. Application design-in information
8.1 Dongle or cable adaptor detect discovery mechanism
The PTN3363 supports the source-side dongle detect discovery mechanism described in
VESA DisplayPort Interoperability Guideline Version 1.1a.
When a source-side cable adaptor is plugged into a multi-mode source device that
supports multiple standards such as DisplayPort, DVI and HDMI, a discovery mechanism
is needed for the multi-mode source to configure itself for outputting DisplayPort, DVI or
HDMI-compliant signals through the dongle or cable adaptor. The discovery mechanism
ensures that a multi-mode source device only sends either DVI or HDMI signals when avalid DVI or HDMI cable adaptor is present.
The VESA Interoperability Guideline recommends that a multi-mode source to power up
with both DDC and AUX CH disabled. After initialization, the source device can use
various mechanisms to decide whether a dongle or cable adaptor is present by detecting
pin 13 on the DisplayPort connector. Depending on the voltage level detected at pin 13,
the source configures itself either:• as a DVI or HDMI source (see below paragraph for detection between DVI and
HDMI), and enables DDC, while keeping AUX CH disabled, or• as a DisplayPort source and enables AUX CH, while keeping DDC disabled.
The monitoring of the voltage level on pin 13 by a multi-mode source device is optional. A
multi-mode source may also, for example, attempt an AUX CH read transaction and, if thetransaction fails, a DDC transaction to discover the presence/absence of a cable adaptor.
Furthermore, a source that supports both DVI and HDMI can discover whether a DVI or
HDMI dongle or cable adaptor is present by using various discovery procedures. One
possible method is to check the voltage level of pin 14 of the DisplayPort connector.
Pin 14 also carries CEC signal used for HDMI. Note that other HDMI devices on the CEC
line may be momentarily pulling down pin 14 as a part of CEC protocol.
The VESA Interoperability Guideline recommends that a multi-mode source should
distinguish a source-side HDMI cable adaptor from a DVI cable adaptor by checking the
DDC buffer ID as described in Section 7.7 “I2C-bus based HDMI dongle detection”. While
it is optional for a multi-mode source to use the I2C-bus based HDMI dongle detection
mechanism, it is mandatory for HDMI dongle or cable adaptor to respond to the I2C-bus
read command. The PTN3363 provides an integrated I2C-bus slave ROM to support thismandatory HDMI dongle detect mechanism for HDMI dongles.
For a DisplayPort-to-HDMI source-side dongle or cable adaptor, DDET must be tied HIGH
to enable the I2C-based HDMI dongle detection response function of PTN3363. For a
DisplayPort-to-DVI sink-side dongle or cable adaptor, DDET must be tied LOW to disable
the function.

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9. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
SymbolParameter

Conditions

VDD

supply voltage

VI

input voltage

VESD

electrostatic discharge
voltage

Max

Unit

0.3

+4.6

V

3.3 V CMOS inputs

0.3

VDD + 0.5V

5.0 V CMOS inputs

0.3

6.0

V

65

+150

C

HBM

[1]

-

8000

V

CDM

[2]

-

1000

V

storage temperature

Tstg

Min

[1]

Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011),
ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model - Component level;
Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association,
Arlington, VA, USA.

[2]

Charged Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008),
standard for ESD sensitivity testing, Charged Device Model - Component level; JEDEC Solid State
Technology Association, Arlington, VA, USA.

10. Recommended operating conditions
Table 10.

Recommended operating conditions

SymbolParameter

VDD

supply voltage

VI

input voltage

Conditions

Min

Typ

Max

Unit

2.8

3.3

3.6

V

3.3 V CMOS inputs

0

-

3.6

V

5.0 V CMOS inputs

0

-

5.5

V

VI(AV)

average input
voltage

IN_Dn+, IN_Dn inputs

[1]

-

0

-

V

Rref(ext)

external reference
resistanceconnected between pin
REXT (pin 4) and GND[2]-

12.4  1 % -

k

Tamb

ambient temperature operating in free air

40

-

C

+105

[1]

Input signals to these pins must be AC-coupled.

[2]

Operation without external reference resistor is possible but results in reduced output voltage swing
accuracy. For details, see Section 7.2.

10.1 Current consumption

PTN3363

Product data sheet

Table 11.

Current consumption

SymbolParameter

Conditions

Min

Typ

Max

Unit

IDD

supply current

OE_N = LOW; Active mode

-

22

-

mA

OE_N = LOW; HPD_SINK = LOW;
Standby mode

-

25

-

A

OE_N = HIGH,
HPD_SINK = don’t care and
DDC_EN = LOW;
Ultra low power mode

-

-

10

A

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11. Characteristics
11.1 Differential inputs
Table 12.

Differential input characteristics for IN_Dx signals

SymbolParameter

UI

unit interval[1]Conditions

Min

Typ

Max

Unit

nominal value at 3.4 Gbit/s

[2]

-

290

-

ps

nominal value at 250 Mbit/s

[2]

-

4000

-

ps

[3]

0.15

-

1.2

V

0.8

-

-

UI

-

-

100

mV

HIZ_EN = LOW

40

50

60



HIZ_EN = HIGH

100

-

-

k

1.0

1.8

1.95

V

100

-

-

k

f = 100 MHz

-

20

-

dB

f = 1.5 GHz

-

16

-

dB

f = 3.4 GHz

-

11

-

dB

VRX_DIFFp-p

differential input peak-to-peak voltage

tRX_EYE

receiver eye timeminimum eye width at IN_Dx
input pairVi(cm)M(AC)peak common-mode input voltage(AC)includes all frequencies
above 30 kHz

Zi

input impedance

DC input impedanceVRX(bias)[4]

bias receiver voltage

ZI(se)

single-ended input impedance

inputs in high-Z state

RLin

input return loss

differential input; active mode;
HIZ_EN = LOW

[5]

[1]

UI (unit interval) = tbit (bit time).

[2]

UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 3.4 Gbit/s per lane.

[3]

VRX_DIFFp-p = 2  VRX_D+  VRX_D. Applies to IN_Dx signals.

[4]

Vi(cm)M(AC) = VRX_D+ + VRX_D / 2  VRX(cm).
VRX(cm) = DC (avg) of VRX_D+ + VRX_D / 2.

[5]

Differential inputs switch to a high-impedance state when OE_N is HIGH.

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11.2 Differential outputs
The level shifter’s differential outputs are designed to meet HDMI version 1.4b and
DVI version 1.0 specifications.
Table 13.

Differential output characteristics for OUT_Dx signals

SymbolParameter

Conditions

Min

Typ

VTT  0.01 VTT

Max

Unit

VOH(se)single-ended HIGH-level
output voltage[1]

VOL(se)single-ended LOW-level
output voltage[2]

VTT  0.60 VTT  0.50 VTT  0.40 V

VO(se)single-ended output
voltage variation

logic 1 and logic 0 state applied
respectively to differential inputs
IN_Dx; Rref(ext) connected;
see Table 10

[3]

400

500

600

mV

IOZ

OFF-state output current

single-ended

-

-

10

A

tr

rise time

20 % to 80 %

75

-

150

ps

tf

fall time

80 % to 20 %skew timetsktjit(add)

added jitter time

VTT + 0.01 V

75

-

150

ps

intra-pair

[4]

-

15

-

ps

inter-pair

[5]

-

-

250

ps

jitter contribution for TMDS
signaling at 3.4 Gbit/s;
PRBS7 pattern;
EQ0 = LOW; EQ1 = LOW;
refer to Figure 6

[6]

-

13

-

ps

[1]

VTT is the DC termination voltage in the HDMI or DVI sink. VTT is nominally 3.3 V.

[2]The open-drain output pulls down from VTT.

[3]

Swing down from TMDS termination voltage (3.3 V  10 %).

[4]This differential skew budget is in addition to the skew presented between IN_D+ and IN_D paired input pins.

[5]This lane-to-lane skew budget is in addition to skew between differential input pairs.

[6]

Jitter budget for differential signals as they pass through the level shifter.

PCB
50 Ω
5.842 cm (2.3 inch)
FR4

SMA

PRBS7 generator(400 mV peak-to-peak)

5.842 cm (2.3 inch)
FR4

SMA

PTN3633
EQ

driver

3.3 V

5.842 cm (2.3 inch)
FR4
SMA
5.842 cm (2.3 inch)
FR4

SMA

test point 1

Fig 6.

50 Ω

test point 2

jittermeasurementat BER 10−9002aah775

Setup for added jitter measurement

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11.3 HPD_SINK input, HPD_SOURCE output
Table 14.

HPD characteristics

SymbolParameter

Conditions
[1]

Min

Typ

Max

Unit

2.0

5.0

5.3

V

-

0.8

V

VIH

HIGH-level input voltage

HPD_SINK

VIL

LOW-level input voltage

HPD_SINK

0

ILI

input leakage current

HPD_SINK

-

-

40

A

VOH

HIGH-level output voltage

HPD_SOURCE

2.5

-

VDD

V

VOL

LOW-level output voltage

HPD_SOURCE

0

-

0.2

V

-

-

200

ns

tPD

propagation delay

from HPD_SINK to HPD_SOURCE;
50 % to 50 %

[2]

tt

transition time

HPD_SOURCE rise/fall; 10 % to 90 %

[3]

1

-

20

ns

HPD_SINK input pull-down resistor

[4]

150

210

270

k

Max

Unit

pull-down resistance

Rpd
[1]

Low-speed input changes state on cable plug/unplug.

[2]

Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.

[3]

Time required to transition from VOH to VOL or from VOL to VOH.

[4]

Guarantees HPD_SINK is LOW when no display is plugged in.

11.4 OE_N, DDC_EN, HIZ_EN, EQ0, EQ1
Table 15.

OE_N, DDC_EN input characteristics

SymbolParameter

VIH

HIGH-level input voltage

VIL

LOW-level input voltage
input leakage current

ILI
[1]

Conditions

OE_N pin

[1]

Min

Typ

2.0

-

-

V

-

0.8

V

-

10

A

Measured with input at VIH maximum and VIL minimum.

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11.5 DDC characteristics
Table 16.

DDC characteristics

SymbolParameter

Conditions

Input and output SCL_SOURCE and SDA_SOURCE, VCC1
VIH

HIGH-level input voltage

Min

Typ

Max

Unit

0.7  VCC1

-

3.6

V

= 2.8 V to 3.6 V[1]VIL

LOW-level input voltage

0.5

-

+0.4

V

ILI

input leakage current

VI = 3.6 V

-

-

10

A

IIL

LOW-level input current

VI = 0.2 V

-

-

10

A

VOL

LOW-level output voltage

IOL = 100 A or 6 mA

0.47

0.52

0.6

V

VOLVIL

difference between LOW-level output
and LOW-level input voltage

guaranteed by design
to prevent contention

-

70

-

mV

Cio

input/output capacitance

VI = 3 V or 0 V; VDD = 3.3 V

-

6

7

pF

VI = 3 V or 0 V; VDD = 0 V

-

6

7

pF

Input and output SDA_SINK and SCL_SINK, VCC2

= 4.5 V to 5.5 V[2]VIH

HIGH-level input voltage

0.7  VCC2

-

5.5

V

VIL

LOW-level input voltage

0.5

-

+1

V

ILI

input leakage current

-

-

10

A

IIL

LOW-level input current

VI = 0.2 V

-

-

10

A

VOL

LOW-level output voltage

IOL = 6 mA

-

0.1

0.2

V

Cio

input/output capacitance

VI = 3 V or 0 V; VDD = 3.3 V

-

-

7

pF

VI = 3 V or 0 V; VDD = 0 V

-

6

7

pF

VCC2 = 4.5 V;
slew rate = 1.25 V/s

-

4

-

mA

Itrt(pu)

VI = 5.5 V

transient boosted pull-up current[1]

VCC1 is the pull-up voltage for DDC source.

[2]

VCC2 is the pull-up voltage for DDC sink.

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12. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm

D

B

SOT617-3

A

terminal 1
index area

A
A1

E

detail X

C
e1
e
9

y1 C

C A B
C

v
w

1/2 e b

y

16

L
17

8

e

e2

Eh
1/2 e

24

1
terminal 1
index area

32

25
X

Dh
0

2.5

Dimensions
Unit(1)
mm

5 mm

scale
A(1)

A1

b

max
0.05 0.30
nom 0.85
min
0.00 0.18

c

D(1)

Dh

E(1)

Eh

5.1

3.75

5.1

3.75

0.2
4.9

3.45

4.9

e

e1

e2

0.5

3.5

3.5

L

v

w

y

0.1

0.05 0.05

y1

0.5
0.1

0.3

3.45

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outlineversion
SOT617-3

Fig 7.

References
IEC

JEDEC

JEITA

sot617-3_po

Europeanprojection

Issue date
11-06-14
11-06-21

MO-220

Package outline SOT617-3 (HVQFN32)

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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth accountof soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.

13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached toPrinted Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides boththe mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole andSurface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.

13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming froma standing wave of liquid solder. The wave soldering process is suitable for the following:• Through-hole components• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation• The moisture sensitivity level of the packages• Package placement• Inspection and repair• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave

• Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads tohigher minimum peak temperatures (see Figure 8) than a SnPb process, thus
reducing the process window• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board• Reflow temperature profile; this profile includes preheat, reflow (in which the board isheated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints (a solder pastecharacteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 17 and 18
Table 17.

SnPb eutectic process (from J-STD-020D)

Package thickness (mm)Package reflow temperature (C)
Volume (mm3)
< 350

 350

< 2.5

235

220

 2.5

220

220

Table 18.

Lead-free process (from J-STD-020D)

Package thickness (mm)Package reflow temperature (C)
Volume (mm3)< 350

350 to 2000

> 2000

< 1.6

260

260

260

1.6 to 2.5

260

250

245

> 2.5

250

245

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 8.

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temperature

maximum peak temperature= MSL limit, damage level

minimum peak temperature= minimum soldering temperaturepeak
temperaturetime
001aac844

MSL: Moisture Sensitivity Level

Fig 8.

Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365“Surface mount reflow soldering description”.

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14. Soldering: PCB footprints)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH

627

+[*[VHHGHWDLO;

3

Q63[

%\

+\ *\ 6/\

$\

Q63\

&

'
6/[
%[
$[



VROGHUODQG

VROGHUSDVWH

GHWDLO;RFFXSLHGDUHD'LPHQVLRQVLQPP
3

$[

$\

%[

%\

&

'

*[

*\

+[

+\

6/[

6/\

Q63[

Q63\































,VVXHGDWH

Fig 9.




VRWBIU

PCB footprint for SOT617-3 (HVQFN32); reflow soldering

PTN3363

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15. Abbreviations
Table 19.

Abbreviations

AcronymDescription

CDM

Charged-Device Model

CEC

Consumer Electronics Control

DDC

Data Display ChannelDP

Dry Pack

DVI

Digital Visual Interface

EMI

ElectroMagnetic Interference

ESD

ElectroStatic Discharge

HBM

Human Body Model

HDMI

High-Definition Multimedia Interface

HPD

Hot Plug Detect

I2C-busInter-IC bus

I/O

Input/Output

NMOS

Negative-channel Metal-Oxide Semiconductor

SMD

Surface Mount Device

TMDS

Transition Minimized Differential Signaling

VESA

Video Electronic Standards Association

16. Revision history
Table 20.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PTN3363 v.1

20140812

Product data sheet--

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17. Legal information
17.1 Data sheet status
Document status[1][2]Product status[3]Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]

Please consult the most recently issued document before initiating or completing a design.

[2]

The term ‘short data sheet’ is explained in section “Definitions”.

[3]

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors product isdeemed to offer functions and qualities beyond those described in the
Product data sheet.

17.3 Disclaimers
Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordancewith the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

PTN3363

Product data sheet

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with theirapplications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in thecustomer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications andthe products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted orconstrued as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents orother industrial or intellectual property rights.

All information provided in this document is subject to legal disclaimers.

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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards, customer(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

17.4 Licenses
Purchase of NXP ICs with HDMI technology
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:admin@hdmi.org.

17.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.

18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

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19. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.3
7.4
7.5
7.6
7.7
7.7.1
7.7.2
7.8
8
8.1
9
10
10.1
11
11.1
11.2
11.3
11.4
11.5
12
13

General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 4
High-speed TMDS level shifting . . . . . . . . . . . . 4
DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 4
HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 4
HDMI dongle detection support . . . . . . . . . . . . 4
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering information . . . . . . . . . . . . . . . . . . . . . 5
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional description . . . . . . . . . . . . . . . . . . 10
Enable and disable features . . . . . . . . . . . . . . 10
Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable function (OE_N) . . . . . . . . . . . 11
DDC channel enable function (DDC_EN). . . . 11
TMDS high input impedance termination(HIZ_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Enable/disable truth table . . . . . . . . . . . . . . . . 12
Analog current reference . . . . . . . . . . . . . . . . 12
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Backdrive current protection . . . . . . . . . . . . . . 13
Squelch function . . . . . . . . . . . . . . . . . . . . . . . 13
Active DDC buffer with rise time accelerator . 13
I2C-bus based HDMI dongle detection . . . . . . 14
Slave address . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read operation . . . . . . . . . . . . . . . . . . . . . . . . 14
Power management . . . . . . . . . . . . . . . . . . . . 15
Application design-in information . . . . . . . . . 16
Dongle or cable adaptor detect discovery
mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Recommended operating conditions. . . . . . . 17
Current consumption . . . . . . . . . . . . . . . . . . . 17
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18
Differential inputs . . . . . . . . . . . . . . . . . . . . . . 18
Differential outputs . . . . . . . . . . . . . . . . . . . . . 19
HPD_SINK input, HPD_SOURCE output . . . . 20
OE_N, DDC_EN, HIZ_EN, EQ0, EQ1 . . . . . . 20
DDC characteristics . . . . . . . . . . . . . . . . . . . . 21
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
Soldering of SMD packages . . . . . . . . . . . . . . 23

13.1
13.2
13.3
13.4
14
15
16
17
17.1
17.2
17.3
17.4
17.5
18
19

Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering: PCB footprints . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23
23
23
24
26
27
27
28
28
28
28
29
29
29
30

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP B.V. 2014.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 August 2014
Document identifier: PTN3363