DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
General Description
The DS2484 is an I2C-to-1-WireM bridge device thatinterfaces directly to standard (100kHz max) or fast
(400kHz max) I2C masters to perform protocol conversion between the I2C master and any downstream
1-Wire slave devices. Relative to any attached 1-Wireslave device, the DS2484 is a 1-Wire master. Internal,user-adjustable timers relieve the system host processor
from generating time-critical 1-Wire waveforms, supporting both standard and overdrive 1-Wire communication
speeds. In addition, the 1-Wire bus can be powered
down under software control. The dual-voltage operation
allows different operating voltages on the I2C and 1-Wireside. Strong pullup features support 1-Wire power delivery to 1-Wire devices such as EEPROMs and sensors.
When not in use, the DS2484 can be put in sleep mode
where power consumption is minimal.

Applications
Printers

Benefits and Features
S I2C Host Interface Supports 100kHz and 400kHzI2C Communication Speeds
S Standard and Overdrive 1-Wire Communication
SpeedsS Adjustable 1-Wire Timing for tRSTL, tMSP, tW0L,
and tREC0
S 1-Wire Port Can Be Powered Down Under
Software Control
S Supports Power-Saving Sleep Mode (SLPZ Pin),
Where the 1-Wire Port is in High Impedance
S I2C Operating Voltages: 1.8V ±5%, 3.3V ±10%, and
5.0V +5/-10%
S Built-In Level Translator: 1-Wire Operating Voltage
from 1.8V -5% to 5.0V +5%, Independent of I2C
Voltage
S Built-In ESD Protection Level of ±8kV Human
Body Model (HBM) Contact Discharge on IO Pin
S -40NC to +85NC Operating Temperature Range

Medical Instruments

S 8-Pin TDFN and 6-Pin SOT23 Packages

Industrial Sensors
Cell Phones

Ordering Information appears at end of data sheet.

Typical Application Circuit
3V
5V

RP*
(I2C PORT)

SDA
SCL

VCC

DS2484

µC
SLPZ

IO

1-Wire BUS

1-WireDEVICE #1

1-WireDEVICE #2

1-WireDEVICE #n*RP = I2C PULLUP RESISTOR (SEE THE Pullup Resistor RP Sizing SECTION FOR RP SIZING)

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

19-6701; Rev 1; 7/15

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground........-0.5V to +6V
Maximum Current into Any Pin............................................20mA
Continuous Power Dissipation (TA = +70NC)
SOT23 (derate 8.7mW/NC above +70NC)..................695.7mW
TDFN (derate 16.7mW/NC above +70NC)................1333.3mW

Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -55NC to +125NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
I2C Voltage (Note 2)

SYMBOL

CONDITIONS

VCC
VCI2C

MIN

TYP

MAX

UNITS

5.25

V

1.71
1.8V

1.71

1.8

1.89

3.3V

2.97

3.3

3.63

5V

4.5

5.0

5.25

No communication, VCC = full range
Supply Current
Power-On-Reset Trip Point

ICC

V

300

Sleep mode, VCC = 5.25V

4Sleep mode, VCC = 3.6V

3.0

VPOR

VCC = full range

1.0

1.5

1-Wire Input High Voltage

VIH1

VCC = full range

1-Wire Input Low Voltage

VIL1

VCC = full range

1-Wire Weak Pullup Resistor

RWPU

1-Wire Output Low Voltage

VOL1

IOL = 8mA sink current

Active Pullup On-Threshold

VIAPO

VCC = full range

0.6

1-Wire time slot

See APU bit description

1-Wire reset standard speed

2.375

2.5

2.625

1-Wire reset overdrive speed

0.475

0.5

0.525

FA
V

IO PIN: GENERAL DATA

Active Pullup On-Time (Note 3)

Active Pullup Impedance

1-Wire Output Fall Time (Note 4)

tAPU

RAPU

tF1

0.6 O
VCC

V
0.2 O
VCC

Low range

375

500

815

High range

700

1000

1375

0.95

V
I

0.2

V

1.2

V

VCC = 1.71V, 4mA load

100

VCC = 3.0V, 4mA load

60

VCC = 4.5V, 4mA load

40

Standard, 10pF < CLOAD < 400pF

0.25

1

Overdrive, 10pF < CLOAD < 400pF

0.05

0.2

Fs

I

Fs

IO PIN: 1-Wire TIMING (Note 5)
Reset Low TimetRSTL

Reset High TimetRSTH

Maxim Integrated

Standard
Overdrive
Standard and overdrive

-5%

See
Table 7+5%Equal to tRSTL

Fs
Fs
  2

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETERSYMBOL

Presence-Detect Sample TimetMSP

Sampling for Short and Interrupt

tSI

Write-One/Read Low Time

tW1L

Read Sample TimetMSR

Write-Zero Low Time

tW0L

Write-Zero Recovery Time

tREC0

1-Wire Time Slot

CONDITIONSStandard
Overdrive

MIN

TYP

MAX

UNITS

-5%

See
Table 7

+5%

Fs

Standard

7.6

8

8.4

Overdrive

0.71

0.75

0.79

Fs

Standard

7.6

8

8.4

Overdrive (Note 6)

0.71

0.75

0.79

Standard

11.4

12

12.6

Overdrive

1.66

1.75

1.84

-5%

See
Table 7

+5%

Fs

Standard and overdrive

-5%

See
Table 7

+5%

Fs

tSLOT

Standard and overdrive

Equal to tW0L + tREC0

Fs

Low-Level Input Voltage

VIL

VCC = full range

-0.5

+0.5

V

High-Level Input Voltage

VIH(Note 7)

1.3

VCCACT

V

Standard
Overdrive

Fs
Fs

SLPZ PIN

Input Leakage Current (Note 2)II

Wake-Up Time from Sleep ModetSWUP

VCI2C < 1.89V

6

VCI2C < 3.63V

15

VCI2C < 5.25V

32(Notes 4, 8)

2

ms

-0.5

0.3 O
VCI2C

V

0.7 O
VCI2C

VCI2C +
0.5V

V

FA

I2C SCL AND SDA PINS (Note 9)
Low-Level Input Voltage

VIL

High-Level Input Voltage

VIH

Hysteresis of Schmitt Trigger
Inputs (Note 4)

VHYS

Low-Level Output Voltage at
3mA Sink Current

VOL

Output Fall Time from VIH(MIN) to
VIL(MAX) with a Bus Capacitancefrom 10pF to 400pF

tOF

Pulse Width of Spikes
Suppressed by Input FiltertSP

Maxim Integrated

VCI2C = full range

VCI2C > 2.0V

0.05 O
VCI2C

VCI2C < 2.0V

0.1 O
VCI2C

V

VCI2C > 2.0V

0.4

VCI2C < 2.0V

0.2 O
VCI2C

V

250

ns

50

ns

(Note 4)60  3

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETERSYMBOL

Input Current with Input Voltage
Between 0.1 O VCC(MAX) and 0.9
O VCC(MAX)II(Note 10)

Input Capacitance

CI(Note 4)SCL Clock Frequency

fSCL

0

Hold Time (Repeated) START
Condition (After this period, thefirst clock pulse is generated.)tHD:STA

0.6

Fs

Low Period of the SCL Clock

tLOW

1.3

Fs

High Period of the SCL Clock

tHIGH

0.6

Fs

Setup Time for a Repeated
START ConditiontSU:STA

0.6

Fs

Data Hold TimetHD:DAT(Notes 11, 12)

Data Setup TimetSU:DAT(Note 13)250

ns

Setup Time for STOP ConditiontSU:STO

0.6

Fs

Bus Free Time Between a STOP
and START Condition

tBUF

1.3

Fs

Capacitive Load for Each Bus
Line

CB

(Notes 4, 14)

400

pF

tOSCWUP(Notes 4, 8)

2

ms

Oscillator Warmup Time

CONDITIONS

MIN
-10

TYP

MAX

UNITS

+10

FA

10

pF

400

kHz

0.9

Fs

Note 1: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are at +25°C.
Note 2: The VCI2C voltage is applied at the SLPZ pin. VCI2C must always be < VCC. The DS2484 measures VCI2C after tSWUP(wakeup from sleep mode) or after tOSCWUP (power-on reset). The Device Reset command does not cause the DS2484 tomeasure VCI2C.
Note 3: The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire Reset command or during therecovery after a short on the 1-Wire line.
Note 4: Guaranteed design and not production tested.
Note 5: Except for tF1, all 1-Wire timing specifications are derived from the same timing circuit.
Note 6: Although 1-Wire slave data sheets specify a tW1L and tRL minimum of 1µs, 1-Wire slaves will accept the shorter 0.71µs
tW1L and tRL of the DS2484.
Note 7: VCCACT refers to the VCC level being applied in the application.
Note 8: I2C communication should not take place for the max tOSCWUP or tSWUP time following a power-on reset or a wake-up
from sleep mode.
Note 9: All I2C timing values are referenced to VIH(MIN) and VIL(MAX) levels.
Note 10: The DS2484 does not obstruct the SDA and SCL lines if SLPZ is at 0V or if VCC is switched off.
Note 11: The DS2484 provides a hold time of at least 300ns for the SDA signal (referenced to the VIH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT must only be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 13: A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU:DAT R 250ns
must then be met. This requirement is met since the DS2484 does not stretch the low period of the SCL signal. Also theacknowledge timing must meet this setup time (I2C bus specification Rev. 03, 19 June 2007).
Note 14: CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depending on the actual operating voltage and frequency of the application (I2C bus specification Rev. 03, 19 June 2007).
Maxim Integrated  4

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Pin Configurations
TOP VIEW

SDA

2

SLPZ
N.C.

DS2484

3

EP

4

8

GND

7

IO

6

VCC

5

N.C.

+

1

+

SCL

TOP MARK

TDFN(2mm x 3mm)

2484
YMrr

TOP VIEWTOP MARK

VCC

IO

GND

6

5

4

SOT23

3Hrr

+

+

DS2484

1

2

3

SLPZ

SDA

SCL

“rr” = REVISION CODE

Pin Description
PIN

NAME

FUNCTION

TDFN-EP

SOT23

1

3

SCL

I2C Serial-Clock Input. Must be connected to the I2C bus supply voltage through a pullup
resistor.

2

2

SDA

I2C Serial-Data Input/Output. Must be connected to the I2C bus supply voltage through apullup resistor.

3

1

SLPZ

Power Supply for I2C Port and Active-Low Control Input to Activate the Low-Power Sleep
Mode. This pin can be driven directly by a push-pull port or by an open-drain port with a
2.2kI pullup resistor to the I2C voltage (VCI2C) over the entire operating voltage range.

4, 5

—

N.C.

No Connection. Not internally connected.

6

6

VCC

Power-Supply Input

7

5

IO

Input/Output Driver for 1-Wire Line

8

4

GND

Ground Reference

—

—

EP

Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper operation.
Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.

Maxim Integrated  5

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep ModeVCC

CONFIGURATION AND
TIMING REGISTERINPUT/OUTPUT
CONTROLLER

I2C
INTERFACE
CONTROLLER

SDA
SCL

T-TIME OSC

SLPZSTATUSREGISTER

GND

READ DATAREGISTER

LINE
XCVR

IO

DS2484

Figure 1. Block Diagram

Table 1. Device Configuration Register Bit Assignment
BIT 7
1WS

BIT 6
SPU

BIT 5
PDN

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

APU

1WS

SPU

PDN

APU

Detailed Description
The DS2484 is a self-timed 1-Wire master that supports
advanced 1-Wire waveform features including standard
and overdrive speeds, active pullup, and strong pullup
for power delivery. The active pullup affects rising edges
on the 1-Wire side. The strong pullup function uses thesame pullup transistor as the active pullup, but with adifferent control algorithm. Once supplied with commandand data, the input/output controller of the DS2484 performs time-critical 1-Wire communication functions suchas reset/presence-detect cycle, read-byte, write-byte,
single bit R/W, and triplet for ROM Search, without requiring interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, search direction taken) through the
Status register and data through the Read Data register. The DS2484 communicates with a host processor
through its I2C bus interface in standard mode or in fastmode. See Figure 1 for a block diagram.

Device Registers
The DS2484 has four registers that the I2C host canread: Device Configuration, Status, Read Data, and Port
Configuration. These registers are addressed by a read
Maxim Integrated

pointer. The position of the read pointer, i.e., the register that the host reads in a subsequent read access,is defined by the instruction the DS2484 executed last.
To enable certain 1-Wire features, the host has readand write-access to the Device Configuration and Port
Configuration registers.

Device Configuration Register

The DS2484 supports four 1-Wire features that are
enabled or selected through the Device Configuration
register (Table 1). These features are as follows:• Active Pullup (APU)• 1-Wire Power-Down (PDN)• Strong Pullup (SPU)• 1-Wire Speed (1WS)
APU, SPU, and 1WS can be selected in any combination.
While APU and 1WS maintain their states, SPU returns to
its inactive state as soon as the strong pullup has ended.
After a device reset (power-up cycle or initiated by theDevice Reset command), the Device Configuration register reads 00h. When writing to the Device Configuration
register, the new data is accepted only if the upper nibble(bits 7 to 4) is the one’s complement of the lower nibble(bits 3 to 0). When read, the upper nibble is always 0h.
  6DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Active Pullup (APU)
The APU bit controls whether an active pullup (lowimpedance transistor) or a passive pullup (RWPU resistor) is used to drive a 1-Wire line from low to high. WhenAPU = 0, active pullup is disabled (resistor mode).
Enabling active pullup is generally recommended forbest 1-Wire bus performance. The active pullup does
not apply to the rising edge of a recovery after a shorton the 1-Wire line. If enabled, a fixed-duration active
pullup (typically 2.5Fs standard speed, 0.5Fs overdrive
speed) also applies in a reset/presence detect cycle on
the rising edges after tRSTL and after tPDL.
The circuit that controls rising edges operates as follows(Figure 2): At t1, the pulldown (from DS2484 or 1-Wireslave) ends. From this point on the 1-Wire bus is pulledhigh through RWPU internal to the DS2484. VCC and thecapacitive load of the 1-Wire line determine the slope. Incase that active pullup is disabled (APU = 0), the resistive pullup continues, as represented by the solid line.
With active pullup enabled (APU = 1), and when at t2 thevoltage has reached the VIAPO threshold, the DS2484

activates a low-impedance pullup transistor, as represented by the dashed line. The active pullup remains
active until the end of the time slot (t3), after which theresistive pullup continues. The shortest duration of theactive pullup is tREC0 - (t2 - t1) in a write-zero time slot
and the longest duration is tW0L + tREC0 - tW1L - (t2 - t1)
in a write-one time slot. In a read-data time slot, the active
pullup duration is slave dependent. See the Strong Pullup(SPU) section for a way to keep the pullup transistor conducting beyond t3.
1-Wire Power Down (PDN)
The PDN bit is used to remove power from the 1-Wireport, e.g., to force a 1-Wire slave to perform a power-on
reset. PDN can as well be used in conjunction with thesleep mode (see Table 2 for details). While PDN is 1,
no 1-Wire communication is possible. To end the 1-Wire
power-down state, the PDN bit must be changed to 0.
Writing both the PDN bit and the SPU bit to 1 forces the
SPU bit to 0. With the DS2483, both bits can be written
to 1, which can be used to logically distinguish between
both parts.

Table 2. Effects of PDN and SLPZPDN =SLPZ IS LOGIC 0

SLPZ IS LOGIC 10• RWPU is connected.
• IO is at VCC, keeping the slaves powered.
• The DS2484 is powered down (sleep mode).

• RWPU is connected.
• IO is at VCC, keeping the slaves powered.
• The DS2484 is powered up (normal operation).

1• RWPU is disconnected.
• IO is at 0V, causing the slaves to lose power.
• The DS2484 is powered down (sleep mode).

• RWPU is disconnected.
• IO is at 0V, causing the slaves to lose power.
• The DS2484 is powered up.

VCC
APU = 1

NEXT TIME SLOTAPU = 0

VIAPO
VIL1MAX
0V
1-Wire BUS ISDISCHARGED

tREC0
t1

t2

t3

Figure 2. Rising Edge Pullup as Seen at the End of a Write-Zero Time Slot

Maxim Integrated  7

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Modecase), the SPU bit in the Device Configuration register
is written to 0, or the DS2484 receives the Device Resetcommand. When the strong pullup ends, the SPU bit isautomatically reset to 0. Using the strong pullup featuredoes not change the state of the APU bit in the Device
Configuration register.

Strong Pullup (SPU)The SPU bit is used to activate the strong pullup function prior to a 1-Wire Write Byte or 1-Wire Single Bit
command. Strong pullup is commonly used with 1-Wire
EEPROM devices when copying scratchpad data to themain memory or when performing a SHA computation
and with parasitically powered temperature sensors or
A/D converters. The respective Maxim 1-Wire IC data
sheets specify the location in the communications protocol after which the strong pullup should be applied. The
SPU bit must be set immediately prior to issuing the command that puts the 1-Wire device into the state where it
needs the extra power. The strong pullup uses the sameinternal pullup transistor as the active pullup feature.
See the RAPU parameter in the Electrical Characteristics
to determine whether the voltage drop is low enough tomaintain the required 1-Wire voltage at a given load current and 1-Wire supply voltage.

1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire communication generated by the DS2484. All 1-Wire slave
devices support standard speed (1WS = 0). Many
1-Wire devices can also communicate at a higher data
rate, called overdrive speed. To change from standard
to overdrive speed, a 1-Wire device needs to receive
an Overdrive-Skip ROM or Overdrive-Match ROM command, as explained in the Maxim 1-Wire IC data sheets.
The change in speed occurs immediately after the 1-Wiredevice has received the speed-changing commandcode. The DS2484 must take part in this speed change
to stay synchronized. This is accomplished by writing to
the Device Configuration register with the 1WS bit as 1
immediately after the 1-Wire Byte command that changes
the speed of a 1-Wire device. Writing to the Device
Configuration register with the 1WS bit as 0, followed by
a 1-Wire Reset command, changes the DS2484 and any
1-Wire devices on the active 1-Wire line back to standard
speed.

If SPU is 1 and APU is 0, the DS2484 treats the risingedge of the time slot as if the active pullup was activated, but uses VIH1 as the threshold to enable the strong
pullup. If SPU is 1 and APU is 1, the threshold voltage
to enable the strong pullup is VIAPO. Once enabled, in
contrast to the active pullup, the internal pullup transistor remains conducting, as shown in Figure 3, until oneof three events occurs: the DS2484 receives a command that generates 1-Wire communication (the typical

LAST BIT OF 1-Wire WRITE BYTE OR 1-Wire SINGLE BIT FUNCTIONVCCWRITE-ONE CASE
SEE TEXTWRITE-ZERO CASE

NEXT
TIME SLOTOR 1-Wire
RESET

0V
tSLOT

DS2484 RESISTIVE PULLUP

DS2484 PULLDOWN

DS2484 STRONG PULLUP

Figure 3. Low-Impedance Pullup Timing

Maxim Integrated  8

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Table 3. Status Register Bit Assignment
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DIR

TSB

SBR

RST

LL

SD

PPD

1WB

Status Register

The read-only Status register is the general means forthe DS2484 to report bit-type data from the 1-Wire side,
1-Wire busy status, and its own reset status to the hostprocessor (Table 3). All 1-Wire communication commands and the Device Reset command position the readpointer at the Status register for the host processor toread with minimal protocol overhead. Status information
is updated during the execution of certain commands
only. Bit details are given in the following descriptions.
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the
1-Wire line is busy. During 1-Wire communication 1WB
is 1; once the command is completed, 1WB returns to
its default 0. Details on when 1WB changes state andfor how long it remains at 1 are found in the Function
Commands section.
Presence-Pulse Detect (PPD)The PPD bit is updated with every 1-Wire Reset command. If the DS2484 detects a logic 0 on the 1-Wire line
at tMSP during the presence-detect cycle, the PPD bit is
set to 1. This bit returns to its default 0 if there is no presence pulse during a subsequent 1-Wire Reset command.
Short Detected (SD)The SD bit is updated with every 1-Wire Reset command. If the DS2484 detects a logic 0 on the 1-Wire line
at tSI during the presence-detect cycle, the SD bit is set
to 1. This bit returns to its default 0 with a subsequent
1-Wire Reset command, provided that the short has been
removed. If the 1-Wire line is shorted at tMSP, the PPD
bit is also set. The DS2484 cannot distinguish between ashort and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a DS2404 or DS1994 is used in
the application, the interrupt function must be disabled.
The interrupt signaling is explained in the respective
Maxim 1-Wire IC data sheets.

Maxim Integrated

Logic Level (LL)
The LL bit reports the logic state of the active 1-Wire line
without initiating any 1-Wire communication. The 1-Wireline is sampled for this purpose every time the Status
register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed theDS2484 in read mode (during the acknowledge cycle),
provided that the read pointer is positioned at the Status
register.
Device Reset (RST)
If the RST bit is 1, the DS2484 has performed an internal
reset cycle, either caused by a power-on reset or fromexecuting the Device Reset command. The RST bit iscleared automatically when the DS2484 executes a Write
Device Configuration command to restore the selectionof the desired 1-Wire features.
Single Bit Result (SBR)
The SBR bit reports the logic state of the active 1-Wireline sampled at tMSR of a 1-Wire Single Bit command or
the first bit of a 1-Wire Triplet command. The power-on
default of SBR is 0. If the 1-Wire Single Bit commandsends a 0 bit, SBR should be 0. With a 1-Wire Triplet
command, SBR could be 0 as well as 1, depending on
the response of the 1-Wire devices connected. The same
result applies to a 1-Wire Single Bit command that sends
a 1 bit.
Triplet Second Bit (TSB)The TSB bit reports the logic state of the active 1-Wireline sampled at tMSR of the second bit of a 1-Wire Triplet
command. The power-on default of TSB is 0. This bit is
updated only with a 1-Wire Triplet command and has nofunction with other commands.
Branch Direction Taken (DIR)
Whenever a 1-Wire Triplet command is executed, this bit
reports to the host processor the search direction thatwas chosen by the third bit of the triplet. The power-on
default of DIR is 0. This bit is updated only with a 1-Wire
Triplet command and has no function with other commands. For additional information, see the description of
the 1-Wire Triplet command and Application Note 187:
1-Wire Search Algorithm.

  9

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Table 4. Port Configuration Register Bit Assignment
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

0

0

0

VAL3

VAL2

VAL1

VAL0

BITS 3:0

VAL[3:0]: Parameter Value Code
See Table 7 for the conversion between binary code and parameter value.

Port Configuration Register

Function Commands

Parameter 000 (tRSTL) standard speed, overdrive speed

The DS2484 understands nine function commands thatfall into four categories: device control, I2C communication, 1-Wire setup, and 1-Wire communication. The
feedback path to the host is controlled by a read pointer,
which is set automatically by each function commandfor the host to efficiently access relevant information.
The host processor sends these commands and applicable parameters as strings of 1 or 2 bytes using the
I2C interface. The I2C protocol requires that each byte
be acknowledged by the receiving party to confirm
acceptance or not be acknowledged to indicate an error
condition (invalid code or parameter) or to end the communication. See the I2C Interface section for details of
the I2C protocol including acknowledge.

The Port Configuration register allows verifying the settings for the 1-Wire port (Table 4). The Adjust 1-Wire
Port command positions the read pointer to the Port
Configuration register for the host processor to readwith minimal protocol overhead. When reading the Port
Configuration register, the parameter values are reported
in this sequence:
Parameter 001 (tMSP) standard speed, overdrive speed
Parameter 010 (tW0L) standard speed, overdrive speed
Parameter 011 (tREC0)
Parameter 100 (RWPU)
If one continues reading, the parameter number rolls
over to 000 and one receives the same data again.
Note that the upper 4 bits read from the port configuration register are always 0. See Table 7 for the conversion
between parameter value code and actual parametervalue.

The function commands are as follows:
1) Device Reset
2) Set Read Pointer3) Write Device Configuration4) Adjust 1-Wire Port5) 1-Wire Reset
6) 1-Wire Single Bit7) 1-Wire Write Byte
8) 1-Wire Read Byte
9) 1-Wire Triplet

Maxim Integrated  10

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Device ResetCommand CodeF0h

Command Parameter

None

Description

Performs a global reset of device state machine logic. Terminates any ongoing 1-Wirecommunication.

Typical Use

Device initialization after power-up; reinitialization (reset) as desired.

Restriction

None (can be executed at any time)Error Response

None

Command Duration

Maximum 525ns. Counted from falling SCL edge of the command code acknowledge bit.

1-Wire Activity

Ends maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.

Read Pointer Position

Status register (for busy polling).

Status Bits Affected

RST set to 1; 1WB, PPD, SD, SBR, TSB, DIR set to 0.

Device Configurations Affected

1WS, APU, PDN, SPU set to 0.

Port Configurations AffectedtRSTL, tMSP, tW0L, tREC0, and RWPU default values apply.

Set Read PointerCommand CodeE1hCommand Parameter

Pointer Code (see Table 5)

Description

Sets the read pointer to the specified register. Overwrites the read pointer position of any
1-Wire communication command in progress.

Typical Use

To prepare reading the result from a 1-Wire Read Byte command; random read access ofregisters.

Restriction

None (can be executed at any time).

Error Response

If the pointer code is not valid, the pointer code is not acknowledged and the command isignored.

Command Duration

None. The read pointer is updated on the rising SCL edge of the pointer code acknowledge bit.

1-Wire Activity

Not affected.

Read Pointer Position

As specified by the pointer code.

Status Bits Affected

None

Device Configurations Affected

None

Port Configurations Affected

None

Table 5. Valid Read Pointer Codes

Maxim Integrated

REGISTER

CODE

Device Configuration RegisterC3h

Status Register

F0h

Read Data Register

E1h

Port Configuration Register

B4h

  11

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Write Device Configuration
Command CodeD2hCommand Parameter

Configuration Byte

Description

Writes a new device configuration byte. The new settings take effect immediately. Note:
When writing to the Device Configuration register, the new data is accepted only if the upper
nibble (bits 7 to 4) is the one’s complement of the lower nibble (bits 3 to 0). When read, theupper nibble is always 0h.

Typical Use

Defining the features for subsequent 1-Wire communication.

Restriction

1-Wire activity must have ended before the DS2484 can process this command.

Error Response

Command code and parameter are not acknowledged if 1WB = 1 at the time the commandcode is received and the command is ignored.

Command Duration

None. The Device Configuration register is updated on the rising SCL edge of theconfiguration-byte acknowledge bit.

1-Wire Activity

None

Read Pointer Position

Device Configuration register (to verify write).

Status Bits Affected

RST set to 0.

Device Configurations Affected

1WS, SPU, PDN, APU updated.

Port Configurations Affected

None

Adjust 1-Wire Port
Command CodeC3hCommand Parameter

Control Byte

Description

Updates the selected 1-Wire port parameter, which affects the 1-Wire timing or pullup
resistor selection. See Table 6 for the control byte format. Note: Upon a power-on reset or
after a Device Reset command, the parameter default values apply.

Typical Use

To adapt the 1-Wire port to the needs of the application. This can be necessary toaccommodate the slave timing requirements, which are different at lower pullup voltage.

Restriction

1-Wire activity must have ended before this command can be processed.

Error Response

Command code and data byte are not acknowledged if 1WB = 1 at the time the commandcode is received and the command is ignored.

Command Duration

None. The selected port parameter is updated on the rising SCL edge of the control-byte
acknowledge bit.

1-Wire Activity

None

Read Pointer Position

Port Configuration register (for verification).

Status Bits Affected

None

Device Configurations Affected

None

Port Configurations Affected

As specified by the control byte.

Maxim Integrated  12

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Table 6. Bit Allocation in the Control Byte
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

P2

P1

P0

OD

VAL3

VAL2

VAL1

VAL0

BITS 7:5

P[2:0]: Parameter Selection
000: selects tRSTL
001: selects tMSP
010: selects tW0L
011: selects tREC0; the OD flag does not apply (don’t care)
100: selects RWPU; the OD flag does not apply (don’t care)

BIT 4

OD: Overdrive Control
0: the value provided applies to the standard speed setting
1: the value provided applies to the overdrive speed setting

BITS 3:0

VAL[3:0]: Parameter Value Code
See Table 7 for the conversion between binary code and parameter value.

Table 7. Conversion Between Parameter Code and Typical Parameter Value
PARAMETER
VALUE
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

PARAMETER 000tRSTL (µs)

PARAMETER 001
tMSP (µs)

PARAMETER 010
tW0L (µs)

OD = 0
440
460
480
500
520
540
560
580
600
620
640
660
680
700
720
740

OD = 0
58
58
60
62
64
66
68
70
72
74
76
76
76
76
76
76

OD = 0
52
54
56
58
60
62
64
66
68
70
70
70
70
70
70
70

OD = 1
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

OD = 1
5.5
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.0
11.0
11.0

OD = 1
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10
10
10
10
10
10

PARAMETER 011
tREC0 (µs)

PARAMETER 100
RWPU (W)OD = N/A
2.75
2.75
2.75
2.75
2.75
2.75
5.25
7.75
10.25
12.75
15.25
17.75
20.25
22.75
25.25
25.25

OD = N/A
500
500
500
500
500
500
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000

Note: The power-on default values are bold.

Maxim Integrated  13

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
1-Wire ResetCommand Code

B4h

Command Parameter

None

Description

Generates a 1-Wire reset/presence-detect cycle at the 1-Wire line (Figure 4). The state of
the 1-Wire line is sampled at tSI and tMSP and the result is reported to the host processor
through the Status register bits PPD and SD.

Typical Use

To initiate or end any 1-Wire communication sequence.

Restriction

1-Wire activity must have ended before the DS2484 can process this command.

Error Response

Command code is not acknowledged if 1WB = 1 at the time the command code is received
and the command is ignored.

Command Duration

2 O tRSTL + maximum 262.5ns, counted from the falling SCL edge of the command code
acknowledge bit.

1-Wire Activity

Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.

Read Pointer Position

Status register (for busy polling).

Status Bits Affected

1WB (set to 1 for 2 O tRSTL), PPD is updated at tRSTL + tMSP, SD is updated at tRSTL + tSI.

Device Configurations Affected

1WS, APU apply.

Port Configurations AffectedtRSTL, tMSP, tW0L, tREC0, and RWPU current values apply.

RESET PULSEPRESENCE/SHORT DETECT
tMSP

tSI
VCC

APU CONTROLLED
EDGE

VIH1
VIL1
0V
tF1

PRESENCE PULSEtRSTL

PULLUP (SEE FIGURE 2)

tRSTH

DS2484 PULLDOWN

1-Wire SLAVE PULLDOWN

Figure 4. 1-Wire Reset/Presence-Detect Cycle

Maxim Integrated  14

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
1-Wire Single Bit
Command Code

87hCommand Parameter

Bit Byte

Description

Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the
1-Wire line (Table 8). A V value of 0b generates a write-zero time slot (Figure 5); a V value of
1b generates a write-one time slot, which also functions as a read-data time slot (Figure 6). In
either case, the logic level at the 1-Wire line is tested at tMSR and SBR is updated.

Typical Use

To perform single-bit writes or reads at the 1-Wire line when single bit communication isnecessary (the exception).

Restriction

1-Wire activity must have ended before the DS2484 can process this command.

Error Response

Command code and bit byte are not acknowledged if 1WB = 1 at the time the commandcode is received and the command is ignored.

Command DurationtSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the bitbyte.

1-Wire Activity

Begins maximum 262.5ns after the falling SCL edge of the MSB of the bit byte.

Read Pointer Position

Status register (for busy polling and data reading).

Status Bits Affected

1WB (set to 1 for tSLOT), SBR is updated at tMSR, DIR (may change its state).

Device Configurations Affected

1WS, APU, SPU apply.

Port Configurations AffectedtRSTL, tMSP, tW0L, tREC0, and RWPU current values apply.

Table 8. Bit Allocation in the Bit Byte
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

V

X

X

X

X

X

X

X

X = Don’t care

Maxim Integrated  15

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
tWOL
tMSR

VCC
VIH1
VIL1
0V
tF1

tREC0
tSLOT

PULLUP (SEE FIGURE 2)

DS2484 PULLDOWN

Figure 5. Write-Zero Time Slot

tMSR
tW1L

VCC
VIH1
VIL1
0V
tF1

tSLOT

PULLUP (SEE FIGURE 2)

DS2484 PULLDOWN

1-Wire SLAVE PULLDOWNNOTE: DEPENDING ON ITS INTERNAL STATE, A 1-Wire SLAVE DEVICE TRANSMITS DATA TO ITS MASTER (e.g., THE DS2484). WHEN RESPONDING WITH A 0,
A 1-Wire SLAVE STARTS PULLING THE LINE LOW DURING tW1L. ITS INTERNAL TIMING GENERATOR DETERMINES WHEN THIS PULLDOWN ENDS AND THE VOLTAGE
STARTS RISING AGAIN. WHEN RESPONDING WITH A 1, A 1-Wire SLAVE DOES NOT HOLD THE LINE LOW AT ALL, AND THE VOLTAGE STARTS RISING AS SOON AS tW1L
IS OVER. 1-Wire DEVICE DATA SHEETS USE THE TERM tRL INSTEAD OF tW1L TO DESCRIBE A READ-DATA TIME SLOT. TECHNICALLY, tRL AND tW1L HAVE IDENTICAL
SPECIFICATIONS AND CANNOT BE DISTINGUISHED FROM EACH OTHER.

Figure 6. Write-One and Read-Data Time Slot

Maxim Integrated  16

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
1-Wire Write Byte
Command CodeA5h

Command Parameter

Data Byte

Description

Writes a single data byte to the 1-Wire line.

Typical Use

To write commands or data to the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit
commands, but faster due to less I2C traffic.

Restriction

1-Wire activity must have ended before the DS2484 can process this command.

Error Response

Command code and data byte are not acknowledged if 1WB = 1 at the time the commandcode is received and the command is ignored.

Command Duration

8 x tSLOT + maximum 262.5ns, counted from falling edge of the last bit (LSB) of the databyte.

1-Wire Activity

Begins maximum 262.5ns after falling SCL edge of the LSB of the data byte (i.e., before thedata-byte acknowledge). Note: The bit order on the I2C bus and the 1-Wire line is different(1-Wire: LSB first; I2C: MSB first). Therefore, 1-Wire activity cannot begin before the DS2484
has received the full data byte.

Read Pointer Position

Status register (for busy polling).

Status Bits Affected

1WB (set to 1 for 8 x tSLOT).

Device Configurations Affected

1WS, SPU, APU apply.

Port Configurations AffectedtRSTL, tMSP, tW0L, tREC0, and RWPU current values apply.

1-Wire Read Byte
Command Code

96hCommand Parameter

None

Description

Generates eight read-data time slots on the 1-Wire line and stores result in the Read Dataregister.

Typical Use

To read data from the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit commands
with V = 1 (write-one time slot), but faster due to less I2C traffic.

Restriction

1-Wire activity must have ended before the DS2484 can process this command.

Error Response

Command code is not acknowledged if 1WB = 1 at the time the command code is received
and the command is ignored.

Command Duration

8 x tSLOT + maximum 262.5ns, counted from the falling SCL edge of the command code
acknowledge bit.

1-Wire Activity

Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.

Read Pointer Position

Status register (for busy polling). Note: To read the data byte received from the 1-Wire line,
issue the Set Read Pointer command and select the Read Data register. Then access theDS2484 in read mode.

Status Bits Affected

1WB (set to 1 for 8 x tSLOT).

Device Configurations Affected

1WS, APU apply.

Port Configurations AffectedtRSTL, tMSP, tW0L, tREC0, and RWPU current values apply.

Maxim Integrated  17

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
1-Wire Triplet
Command Code

78hCommand Parameter

Direction Byte

Description

Generates three time slots: two read time slots and one write time slot at the 1-Wire line.
The type of write time slot depends on the result of the read time slots and the direction
byte. The direction byte determines the type of write time slot if both read time slots are 0 (atypical case). In this case, the DS2484 generates a write-one time slot if V = 1 and a writezero time slot if V = 0. See Table 9.
If the read time slots are 0 and 1, they are followed by a write-zero time slot.
If the read time slots are 1 and 0, they are followed by a write-one time slot.
If the read time slots are both 1 (error case), the subsequent write time slot is a write-one.

Typical Use

To perform a 1-Wire Search ROM sequence; a full sequence requires this command to be
executed 64 times to identify and address one device.

Restriction

1-Wire activity must have ended before the DS2484 can process this command.

Error Response

Command code and direction byte is not acknowledged if 1WB = 1 at the time thecommand code is received and the command is ignored.

Command Duration

3 x tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of thedirection byte.

1-Wire Activity

Begins maximum 262.5ns after the falling SCL edge of the MSB of the direction byte.

Read Pointer Position

Status Register (for busy polling).

Status Bits Affected

1WB (set to 1 for 3 x tSLOT), SBR is updated at the first tMSR, TSB and DIR are updated at
the second tMSR (i.e., at tSLOT + tMSR).

Device Configurations Affected

1WS, APU apply.

Port Configurations AffectedtRSTL, tMSP, tW0L, tREC0, and RWPU current values apply.

Table 9. Bit Allocation in the Direction Byte
BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

V

X

X

X

X

X

X

X

X = Don’t care

Maxim Integrated  18

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep ModeMSB FIRST

MSB

LSB

MSB

LSB

SDA

SCL
IDLE

SLAVE
ADDRESS

R/W

ACK

1–7

8

9

START
CONDITION

DATA

1–7

ACK

8

REPEATED IF MORE BYTESARE TRANSFERRED

9

DATA

1–7

ACK/
NACK

8

9

STOP CONDITIONREPEATED START

Figure 7. I2C Protocol Overview

7-BIT SLAVE ADDRESS
A6

A5

A4

A3

A2

A1

A0

0

0

1

1

0

0

0

R/W

DETERMINESREAD OR WRITE

MSB

Figure 8. DS2484 Slave Address

I2C Interface
General Characteristics

The I2C bus uses a data line (SDA) and a clock signal(SCL) for communication. Both SDA and SCL are bidirectional lines connected to a positive supply voltage
through a pullup resistor. When there is no communication, both lines are high. The output stages of devices
connected to the bus must have an open drain or open
collector to perform the wired-AND function. Data on the
I2C bus can be transferred at rates of up to 100kbps instandard mode and up to 400kbps in fast mode. The
DS2484 works in both modes.

Maxim Integrated

A device that sends data on the bus is defined as atransmitter, and a device receiving data is defined as areceiver. The device that controls the communication iscalled a master. The devices that are controlled by themaster are slaves. To be individually accessed, eachdevice must have a slave address that does not conflictwith other devices on the bus.
Data transfers can be initiated only when the bus is notbusy. The master generates the serial clock (SCL), controls the bus access, generates the START and STOP
conditions, and determines the number of data bytes
transferred between START and STOP (Figure 7). Datais transferred in bytes with the most significant bit beingtransmitted first. After each byte follows an acknowledge
bit to allow synchronization between master and slave.

Slave Address

Figure 8 shows the slave address to which the DS2484
responds. The slave address is part of the slave address/
control byte. The last bit of the slave address/control
byte (R/W) defines the data direction. When set to 0,
subsequent data flows from master to slave (write accessmode); when set to 1, data flows from slave to master(read access mode).

  19

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep ModeI2C Definitions

The following terminology is commonly used to describe
I2C data transfers. See Figure 9 for a timing diagram.

Bus Idle or Not Busy: Both SDA and SCL are inactive and in their logic-high states.
START Condition: To initiate communication with aslave, the master must generate a START condition.
A START condition is defined as a change in state of
SDA from high to low while SCL remains high.
STOP Condition: To end communication with aslave, the master must generate a STOP condition. A
STOP condition is defined as a change in state of SDA
from low to high while SCL remains high.
Repeated START Condition: Repeated STARTs arecommonly used for read accesses to select a specificdata source or address from which to read. The master can use a repeated START condition at the endof a data transfer to immediately initiate a new datatransfer following the current one. A repeated START
condition is generated the same way as a normal
START condition, but without leaving the bus idle after
a STOP condition.
Data Valid: With the exception of the START and
STOP condition, transitions of SDA can occur only
during the low state of SCL. The data on SDA mustremain valid and unchanged during the entire highpulse of SCL plus the required setup and hold time
(tHD:DAT after the falling edge of SCL and tSU:DAT
before the rising edge of SCL; see Figure 9). There is
one clock pulse per bit of data. Data is shifted into thereceiving device during the rising edge of SCL pulse.
When finished with writing, the master must release
the SDA line for a sufficient amount of setup time(minimum tSU:DAT + tR in Figure 9) before the next rising edge of SCL to start reading. The slave shifts out
each data bit on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the risingedge of the current SCL pulse. The master generates
all SCL clock pulses, including those needed to readfrom a slave.
Acknowledge: Typically a receiving device, whenaddressed, is obliged to generate an acknowledge
after the receipt of each byte. The master must
generate a clock pulse that is associated with thisacknowledge bit. A device that acknowledges mustpull SDA low during the acknowledge clock pulse
in such a way that SDA is stable low during the highperiod of the acknowledge-related clock pulse plus
the required setup and hold time (tHD:DAT after thefalling edge of SCL and tSU:DAT before the risingedge of SCL).

SDA
tBUF
tF

tSP

tHD:STAtLOW
SCLtHD:STAtHIGH

tR
tHD:DAT

STOP

START

tSU:STASPIKE
SUPPRESSIONtSU:STOtSU:DATREPEATEDSTARTNOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

Figure 9. I2C Timing Diagram

Maxim Integrated  20

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Not Acknowledged by Slave: A slave device could
be unable to receive or transmit data, e.g., because
it is busy performing a real-time function or is in
sleep mode. In this case, the slave device does not
acknowledge its slave address and leaves the SDA
line high. A slave device that is ready to communicate
acknowledges at least its slave address. However,some time later the slave can refuse to accept data,e.g., because of an invalid command or parameter.
In this case, the slave device does not acknowledge
any of the bytes that it refuses and leaves SDA high.
In either case, after a slave has failed to acknowledge,
the master first should generate a repeated START
condition or a STOP condition followed by a START
condition to begin a new data transfer.
Not Acknowledged by Master: At some time when
receiving data, the master must signal an end of data
to the slave device. To achieve this, the master does
not acknowledge the last byte that it has received
from the slave. In response, the slave releases SDA,
allowing the master to generate the STOP condition.

Writing to the DS2484

To write to the DS2484, the master must access thedevice in write mode, i.e., the slave address must be sentwith the direction bit set to 0. The next byte to be sent is
a command code, which, depending on the command,
may be followed by a command parameter. The DS2484
acknowledges valid command codes and expected/
valid command parameters. Additional bytes or invalid
command parameters are never acknowledged.

I2C Communication Examples
See Table 10 and Table 11 for the I2C communication
legend and data direction codes.

Table 10. I2C Communication—Legend
SYMBOLS

DESCRIPTIONSTART ConditionAD, 0

Select DS2484 for Write AccessAD, 1Select DS2484 for Read Access

Sr

Repeated START Condition

P

STOP Condition

A

Acknowledged

A\

Not Acknowledged(Idle)Bus Not Busy

<byte>

Transfer of One Byte

DRST

Command “Device Reset” (F0h)

SRP

Command “Set Read Pointer” (E1h)

WCFG

Command “Write Device Configuration” (D2h)

ADJPCommand “Adjust 1-Wire Port” C3h)

1WRS

Command “1-Wire Reset” (B4h)

1WSB

Command “1-Wire Single Bit” (87h)1WWBCommand “1-Wire Write Byte” (A5h)

1WRB

Command “1-Wire Read Byte” (96h)

1WTCommand “1-Wire Triplet” (78h)Table 11. Data Direction Codes

Reading from the DS2484

To read from the DS2484, the master must access thedevice in read mode, i.e., the slave address must be sentwith the direction bit set to 1. The read pointer determines
the register that the master reads from. The master cancontinue reading the same register over and over again,
without having to readdress the device, e.g., to watch
the 1WB changing from 1 to 0. To read from a different
register, the master must issue the Set Read Pointer command and then access the DS2484 again in read mode.

Maxim Integrated

Master-to-Slave Slave-to-Master  21

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
I2C Communication Examples (continued)
Device Reset (After Power-Up)
S

AD,0

A

DRST

A

Sr

AD,1

A

<byte>A\

P

Activities that are underlined denote an optional read access to verify the success of the command.
Set Read Pointer (To Read from Another Register)Case A: Valid Read Pointer Code
S

AD,0

A

SRP

A

C3h

A

P

C3h is the read pointer code for the Device Configuration register.
Case B: Invalid Read Pointer Code
S

AD,0

A

SRP

A

E5h

A\

P

E5h is an invalid read pointer code.
Write Device Configuration (Before Starting 1-Wire Activity)
Case A: 1-Wire Idle (1WB = 0)
S

AD,0

A

WCFG

A

<byte>

A

Sr

AD,1

A

<byte>A\

P

Activities that are underlined denote an optional read access to verify the success of the command.
Case B: 1-Wire Busy (1WB = 1)
S

AD,0

A

WCFG

A\

P

The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Adjust 1-Wire Port (after power-up, e.g., to select a 1-Wire timing other than the default)
Case A: 1-Wire Idle (1WB = 0)
S

AD,0

A

ADJP

A

<byte>

A<byte>AP

Repeat to set additional port parameters

The control byte is always acknowledged, regardless of its value. See the Adjust 1-Wire Port command description
for the format of the control byte.
Case B: 1-Wire Busy (1WB = 1)
S

AD,0

A

ADJP

A\

P

The master should stop and restart as soon as the DS2484 does not acknowledge the command code.

Maxim Integrated  22

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
I2C Communication Examples (continued)
Verifying the 1-Wire port configuration
The Adjust 1-Wire Port command sets the read pointer to the Port Configuration register. If other commands were
issued to the DS2484 since then, use the Set Read Pointer command first to position the read pointer to the Port
Configuration register.
Condition: 1-Wire Idle (1WB = 0), Read Pointer at Port Configuration Register
S

AD,1

A

<byte>

A<byte>

A<byte>A\P

Repeat to read additional port parameters

1-Wire Reset (To Begin or End 1-Wire Communication)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling to Read the Result
S

AD,0

A

1WRS

A

P

(Idle)S

AD,1

A<byte>A\P

In the first cycle, the master sends the command. Then the master waits (Idle) for the 1-Wire reset to complete. In
the second cycle, the DS2484 is accessed to read the result of the 1-Wire reset from the Status register.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed, then Read the Result
S

AD,0

A

1WRS

A

Sr

AD,1

A

<byte>

A<byte>A\P

Repeat until the 1WB bit has changed to 0.

Case C: 1-Wire Busy (1WB = 1)
S

AD,0

A

1WRS

A\

P

The master should stop and restart as soon as the DS2484 does not acknowledge the command code.

Maxim Integrated  23

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
I2C Communication Examples (continued)
1-Wire Single Bit (To Generate a Single Time Slot on the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S

AD,0

A

1WSB

A

<byte>A

P(Idle)S

AD,1

A<byte>A\P

The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire Single Bit command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S

AD,0

A

1WSB

A

<byte>A

Sr

Repeat until the 1WB bit
has changed to 0.
AD,1A<byte>

A<byte>A\P

When 1WB has changed from 1 to 0, the Status register holds the valid result of the 1-Wire Single Bit command.
Case C: 1-Wire Busy (1WB = 1)
S

AD,0

A

1WSB

A\

P

The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
1-Wire Write Byte (To Send a Command Code or Data Byte to the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S

AD,0

A

1WWB

A

33h

A

P

(Idle)

33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function tocomplete. There is no data read back from the 1-Wire line with this command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed.
S

AD,0

A

1WWB

A

33h

A

Sr

Repeat until the 1WB bit
has changed to 0.
AD,1A<byte>

A<byte>A\P

When 1WB has changed from 1 to 0, the 1-Wire Write Byte command is completed.
Case C: 1-Wire Busy (1WB = 1)
S

AD,0

A

1WWB

A\

P

The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated  24

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
I2C Communication Examples (continued)
1-Wire Read Byte (To Read a Byte from the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer After Idle Time
S

AD,0

A

1WRB

A

P

(Idle)

S

AD,0

A

SRP

A

E1h

A

Sr

AD,1

A

<byte>A\P

The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the Read Data register(code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
Case B: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer Before Idle Time
S

AD,0

A

1WRB

A

Sr

AD,0

A

SRP

A

E1h

A

(Idle)S

AD,1

A<byte>A\P

P

The read pointer is set to the Read Data register (code E1h) while the 1-Wire Read Byte command is still in progress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was obtained
from the 1-Wire line.
Case C: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S

AD,0

A

Sr

1WRB

AD,0

A

A

Repeat until the 1WB bit
has changed to 0.
Sr

AD,1

A

<byte>

A<byte>

A\

SRP

A

E1h

A

Sr

AD,1

A

<byte>A\

P

Poll the Status segister until the 1WB bit has changed from 1 to 0. Then set the read pointer to the Read Data register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
Case D: 1-Wire Busy (1WB = 1)
S

AD,0

A

1WRB

A\

P

The master should stop and restart as soon as the DS2484 does not acknowledge the command code.

Maxim Integrated  25

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
I2C Communication Examples (continued)
1-Wire Triplet (To Perform a Search ROM Function on 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S

AD,0

A

1WT

A

<byte>A

P(Idle)S

AD,1

A<byte>A\P

The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire Triplet command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S

AD,0

A

1WT

A

<byte>A

Sr

Repeat until the 1WB bit
has changed to 0.
AD,1A<byte>

A<byte>A\P

When 1WB has changed from 1 to 0, the Status register holds the valid result of the 1-Wire Triplet command.
Case C: 1-Wire Busy (1WB = 1)
S

AD,0

A

1WT

A\

P

The master should stop and restart as soon as the DS2484 does not acknowledge the command code.

Maxim Integrated  26

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Applications Information
SDA and SCL Pullup Resistors

must not exceed 300ns. Assuming maximum rise time,the maximum resistor value at any given capacitance CB
is calculated as: RP(MAX) = 300ns/(CB x ln(7/3)). For abus capacitance of 400pF, the maximum pullup resistor
would be 885I.

Pullup Resistor RP Sizing

Because an 885I pullup resistor, as would be required
to meet the rise time specification at 400pF bus capacitance, is lower than RP(MIN) at 5.5V, a different approachis necessary. The “Maximum Load at Minimum RP FastMode” line in Figure 10 is generated by first calculating
the minimum pullup resistor at any given operating voltage (“Minimum RP” line) and then calculating the respective bus capacitance that yields a 300ns rise time.

According to the I2C specification, a slave device must
be able to sink at least 3mA at a VOL of 0.4V. This DC
condition determines the minimum value of the pullup
resistor: RP(MIN) = (VCI2C - 0.4V)/3mA. With an I2C pullup voltage VCI2C of 5.5V, the minimum value for the pullup resistor is 1.7kI. The “Minimum RP” line in Figure 10
shows how the minimum pullup resistor changes with theoperating (pullup) voltage.

MINIMUM RP (Ω)

For I2C systems, the rise time and fall time are measured
from 30% to 70% of the pullup voltage. The maximum
bus capacitance, CB, is 400pF. The maximum rise time

Only for pullup voltages of 3V and lower can the maxi­
mum permissible 400pF bus capacitance be maintained.
A reduced 300pF bus capacitance is acceptable for 4V
and lower pullup voltages. For fast mode operation at
any pullup voltage, the bus capacitance must not exceed
200pF. The corresponding pullup resistor value at thevoltage is indicated by the “Minimum RP” line.

2000

500

1600

400

1200

300

MINIMUM RP

200

800

LOAD (pF)

SDA is an open-drain output on the DS2484 that requiresa pullup resistor to realize high-logic levels. Because theDS2484 uses SCL only as input (no clock stretching), themaster can drive SCL either through an open-drain/collector output with a pullup resistor or a push-pull output.

MAXIMUM LOAD AT MINIMUM RP FAST MODE
400

100

0

0
1

2

3

4

5

PULLUP VOLTAGE (V)Figure 10. I2C Fast Mode Pullup Resistor Selection Chart

Maxim Integrated  27

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Package Information

Ordering InformationPART

TEMP RANGE

PIN-PACKAGE

DS2484R+T-40NC to +85NC

6 SOT23 (3k pieces)

DS2484Q+T-40NC to +85NC

8 TDFN-EP* (2.5k pieces)+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.

Maxim Integrated

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but thedrawing pertains to the package regardless of RoHS status.
PACKAGETYPE

PACKAGECODEOUTLINENO.

LAND
PATTERN NO.

6 SOT23

U6SN+121-0058

90-0175

8 TDFN-EP

T823+121-0174

90-0091  28

DS2484
Single-Channel 1-Wire Masterwith Adjustable Timing and Sleep Mode
Revision History
REVISIONNUMBERREVISION
DATE

0

5/13

Initial release

—

1

7/15

Updated the Presence-Pulse Detect (PPD) and Short Detected (SD) sections

9

DESCRIPTIONPAGESCHANGED

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min andmax limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2015 Maxim Integrated Products, Inc.

29

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.