KSZ8775CLX
Integrated 5–Port 10/100 Managed Ethernet
Switch with Port 4 RMII and Port 5 RGMII/MII/RMII Interfaces
Features• Management Capabilities- The KSZ8775CLX includes all the functionsof a 10/100BASE-T/TX switch system, which
combines a switch engine, frame buffer
management, address look-up table, queue
management, MIB counters, media access
controllers (MAC), and PHY transceivers- Non-blocking store-and-forward switch fabricassures fast packet delivery by utilizing a1024-entry forwarding table- Port mirroring/monitoring/sniffing: ingress
and/or egress traffic to any port
- MIB counters for fully compliant statistics
gathering - 36 counters per port
- Hardware support for port-based flush andfreeze command in MIB counter.
- Multiple loopback of remote, PHY, and MAC
modes support for the diagnostics- Rapid spanning tree support (RSTP) for
topology management and ring/linear
recovery• Robust PHY Ports- Four integrated IEEE 802.3/802.3u-compliant
Ethernet transceivers supporting 10Base-T
and 100BASE-TX- 802.1az EEE supported- On-chip termination resistors and internalbiasing for differential pairs to reduce power- HP Auto MDI/MDI-X™ crossover support
eliminates the need to differentiate between
straight or crossover cables in applications• MAC and GMAC Ports- Four internal media access control (MAC1 to
MAC4) units and one internal Gigabit media
access control (GMAC5) unit
- RGMII, MII, or RMII interfaces support for thePort 5 GMAC5 with uplink and RMII interface
for Port 4 MAC4
- 2 kb jumbo packet support- Tail tagging mode (one byte added before
FCS) support on Port 5 to inform theprocessor which ingress port receives thepacket and its priority

DS00002129C-page 1- Supports reduced media independent interface (RMII) with 50 MHz reference clock output- Supports media independent interface (MII)in either PHY mode or MAC mode on Port 5- LinkMD® cable diagnostic capabilities fordetermining cable opens, shorts, and length• Advanced Switch Capabilities- Non-blocking store-and-forward switch fabricassures fast packet delivery by utilizing a1024-entry forwarding table- 64kb frame buffer RAM- IEEE 802.1q VLAN support for up to 128
active VLAN groups (full-range 4096 of VLAN
IDs)
- IEEE 802.1p/q tag insertion or removal on aper port basis (egress)- VLAN ID tag/untag options on per port basis- Fully compliant with IEEE 802.3/802.3u standards- IEEE 802.3x full-duplex with force mode
option and half-duplex back-pressure collision flow control- IEEE 802.1w rapid spanning tree protocol
support- IGMP v1/v2/v3 snooping for multicast packet
filtering- QoS/CoS packets prioritization support:
802.1p, DiffServ-based and re-mapping of
802.1p priority field per port basis on fourpriority levels- IPv4/IPv6 QoS support- IPv6 multicast listener discovery (MLD)
snooping- Programmable rate limiting at the ingress andegress ports on a per port basis- Jitter-free per-packet-based rate limiting
support- Tail tagging mode (one byte added before
FCS) support on Port 5 to inform the processor which ingress port receives the packet
and its priority- Broadcast storm protection with percentage
control (global and per port basis) 2015 Microchip Technology Inc.

KSZ8775CLX- 1 kb entry forwarding table with 64 kb frame
buffer- Four priority queues with dynamic packet
mapping for IEEE 802.1p, IPv4 ToS (DIFFSERV), IPv6 traffic class, etc.
- Supports Wake-on-LAN (WoL) using AMD’s
Magic Packet™
- VLAN and address filtering- Supports 802.1x port-based security, authentication, and MAC-based authentication via
access control lists (ACL)- Provides port-based and rule-based ACLs to
support Layer 2 MAC SA/DA address, Layer
3 IP address and IP mask, Layer 4 TCP/UDP
port number, IP protocol, TCP flag, and compensation for the port security filtering- Ingress and egress rate limit based on bit per
second (bps) and packet-based rate limiting(pps)• Configuration Registers Access- High speed (4-wire, up to 50 MHz) interface(SPI) to access all internal registers- MII management interface (MIIM, MDC/MDIO 2-wire) to access all PHY registers per
clause 22.2.4.5 of the IEEE 802.3 specification- I/O pin strapping facility to set certain register
bits from I/O pins during reset time
- Control registers configurable on-the-fly• Power and Power Management- Full-chip software power down (all registers
value are not saved and strap-in value will restrap after release of the power down)- Per-port software power down
- Energy detect power down (EDPD), which
disables the PHY transceiver when cables
are removed- Supports IEEE P802.3az Energy Efficient
Ethernet to reduce power consumption intransceivers in LPI state even though cables
are not removed- Dynamic clock tree control to reduce clocking
in areas not in use- Low power consumption without extra power
consumption on transformers- Voltages: Using external LDO power supplies.
- Analog VDDAT 3.3V
- VDDIO support- s 3.3V, 2.5V, and 1.8V
- Low 1.2V voltage for analog and digital corepower
- Wake-on-LAN support with configurable
packet control• Additional Features

 2015 Microchip Technology Inc.

- Single 25 MHz +50 ppm reference clock
requirement• Comprehensive programmable two LED indicator
support for link, activity, full/half-duplex, and 10/
100 speed• Packaging and Environmental- Commercial temperature range: 0°C to+70°C• Industrial temperature range: –40°C to +85°C- Package available in an 80-pin lead free
(RoHS) LQFP form factor- Supports HBM ESD rating of 5 kV
- 0.065 µm CMOS technology for lower power
consumption• Applications- Set-Top Boxes- Networked Printers and Servers- Test Instrumentation- LAN on Motherboard- Embedded Telecom Applications- Video Record/Playback Systems- Cable Modems/Routers- DSL Modems/Routers- Digital Video Recorders- IP and Video Phones- Wireless Access Points- Digital Televisions- Digital Media Adapters/Servers- Gaming Consoles

DS00002129C-page 2

KSZ8775CLXTO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify therevision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you areusing.

Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2015 Microchip Technology Inc.

DS00002129C-page 3

KSZ8775CLX
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 5
2.0 Pin Description and Configuration ................................................................................................................................................... 6
3.0 Functional Description ................................................................................................................................................................... 16
4.0 Register Descriptions .................................................................................................................................................................... 49
5.0 Operational Characteristics ......................................................................................................................................................... 114
6.0 Electrical Characteristics ............................................................................................................................................................. 115
7.0 Package Outline .......................................................................................................................................................................... 117
Appendix A: Data Sheet Revision History ......................................................................................................................................... 126
The Microchip Web Site .................................................................................................................................................................... 128
Customer Change Notification Service ............................................................................................................................................. 129
Customer Support ............................................................................................................................................................................. 129
Product Identification System ............................................................................................................................................................ 130

DS00002129C-page 4

 2015 Microchip Technology Inc.

KSZ8775CLX
1.0

INTRODUCTION

1.1

General Description

The KSZ8775CLX is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce
system cost. It is intended for cost-sensitive applications requiring three 10/100 Mbps copper ports, one RMII on Port4, and one 10/100/1000Mbps Gigabit uplink port on Port 5. The KSZ8775CLX incorporates a small package outline, thelowest power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced
power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security
and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB
counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support.
The KSZ8775CLX provides support for multiple CPU data interfaces to effectively address both current and emerging
fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the RGMII, MII, and
RMII modes.
The KSZ8775CLX product is built upon industry-leading analog and digital technology, with features designed to offload
host processing and streamline the overall design.
• Three integrated 10/100BASE-T/TX MAC/PHYs• One integrated 10/100BASE-T/TX MAC with RMII interface• One integrated 10/100/1000Base-T/TX GMAC with selectable RGMII, MII, and RMII interfaces• Small 80-pin LQFP package
A robust assortment of power management features including Energy Efficient Ethernet (EEE), power management
event (PME), and Wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments.
All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed
through the MDC/MDIO interface.

FIGURE 1-1:

BLOCK DIAGRAM

 2015 Microchip Technology Inc.

DS00002129C-page 5

KSZ8775CLX
2.0

PIN DESCRIPTION AND CONFIGURATION

80-QFN PIN ASSIGNMENT (TOP VIEW)

XO
XI
GNDA
ISET
VDDAT33
ATST
VDD12D
RST_N
GNDD
VDDIO
SPIS_N
SDA_MDIO
SCL_MDC
SPIQ
LED1_0
LED1_1
LED2_0
LED2_1TXEN4GNDD

FIGURE 2-1:

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

KSZ8775(TOP VIEW)

PME
REFCLKO
COL5
CRS5
RXER5
RXDV5/CRSDV5/RXD5_CTL
RXD5_3
RXD5_2
VDDIO
GNDD
RXD5_1
RXD5_0RXC5/GRXC5
TXC5/REFCLKI5/GTXC5VDD12DNC
RXDV4/CRSDV4RXD4_0
RXD4_1GNDD

GNDA
INTR_NNC
TXD4_1
LED3_1
TXD4_0
LED3_0
VDD12D
GNDD
TXC4/REFCLKI4
RXC4
TXEN5/TXD5_CTL
TXD5_0
TXD5_1
GNDD
VDDIO
TXD5_2
TXD5_3
TXER5
NC

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

NC
NC
VDD12A
VDDAT33
GNDA
RXP1
RXM1
TXP1
TXM1
RXP2
RXM2
TXP2
TXM2
VDDAT33
RXP3
RXM3
TXP3
TXM3
NC
NC

TABLE 2-1:

SIGNALS

Num Pins

Pin Name

Type

1

NC

NC

No connect

2

NC

NC

No connect

3

VDD12A

P

1.2V core power

4

VDDAT

P

3.3V or 2.5V analog power

5

GNDA

GND

DS00002129C-page 6

Port

Pin Description

Analog ground 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 2-1:

SIGNALS (CONTINUED)

Num Pins

Pin Name

Type

Port

Pin Description

6

RXP1

I

1

Port 1 physical receive signal + (differential).

7

RXM1

I

1

Port 1 physical receive signal - (differential).

8

TXP1

O

1

Port 1 physical transmit signal + (differential).

9

TXM1

O

1

Port 1 physical transmit signal - (differential).

10

RXP2

I

2

Port 2 physical receive signal + (differential).

11

RXM2

I

2

Port 2 physical receive signal - (differential).

12

TXP2

O

2

Port 2 physical transmit signal + (differential)

13

TXM2

O

2

Port 2 physical transmit signal - (differential).

14

VDDAT

P

15

RXP3

I

3

Port 3 physical receive signal + (differential).

16

RXM3

I

3

Port 3 physical receive signal - (differential).

17

TXP3

O

3

Port 3 physical transmit signal + (differential).

18

TXM3

O

3

Port 3 physical transmit signal – (differential).

19

NC

NC

No connect

20

NC

NC

No connect

21

GNDA

GND

Analog ground

3.3V or 2.5V analog power

22

INTR_NOPUInterrupt. Active low.
This pin is an open-drain output pin.
Note: an external pull-up resistor is needed on
this pin when it is in use.

23

NC

NC

No connect

24

TXD4_1IPD

4

RMII: Port 4 RMII transmit bit [1].

25

LED3_1IPU/O

3Port 3 LED Indicator 1.
See global Register 11 bits [5:4] for details.
Strap option: Switch Port 5 GMAC5 interface
mode select by
LED3[1:0]
00 = MII for SW5-MII
01 = RMII for SW5-RMII
10 = Reserved
11 = RGMII for SW5-RGMII (default)

26

TXD4_0

IPD

4

RMII: Port 4 RMII transmit bit [0]27LED3_0IPU/O

3Port 3 LED Indicator 0.
See global Register 11 bits [5:4] for details.
Strap option: see LED3_1

28

VDD12DP

1.2V core power.

29

GNDD

GND

Digital ground.

 2015 Microchip Technology Inc.

DS00002129C-page 7

KSZ8775CLXTABLE 2-1:

SIGNALS (CONTINUED)

Num Pins

Pin Name30

TXC4/REFCLKI4

Type

I/O

Port

Pin Description

4

Port 4 Switch MAC4 SW4-RMII Reference
Clock Input
RMII: Input for receiving 50 MHz clock in normal
mode.

31

RXC4

I/O

4

Port 4 Switch MAC4 SW4-RMII reference clockout:
RMII: Output 50 MHz reference clock for thereceiving/transmit in the clock mode.

32

TXEN5/
TXD5_CTL

IPD

5MII/RMII: Port 5 switch transmit enable.
RGMII: Transmit data control.

33

TXD5_0IPD

5RGMII/MII/RMII: Port 5 switch transmit bit [0].

34

TXD5_1IPD

5RGMII/MII/RMII:Port 5 switch transmit bit [1].

35

GNDD

GND

36

VDDIO

P

3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.

IPD

5

RGMII/MII:Port 5 switch transmit bit [2].
RMII:
No connection.

5

RGMII/MII:Port 5 switch transmit bit [3].
RMII:
No connection.

5

MII:
Port 5 switch transmit error.
RGMII/RMII:
No connection.

37

38

TXD5_2

TXD5_3IPD

Digital ground.

39

TXER5

IPD

40

NC

NC

No connect

41

GNDD

GND

Digital ground42

RXD4_1

IPD/O

DS00002129C-page 8

4

RMII:
Port 4 SW4-RMII receive bit [1] 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 2-1:
Num Pins

SIGNALS (CONTINUED)
Pin Name

Type

Port

Pin Description
RMII:
Port 4 SW4-RMII receive bit [0].
Strap Option: Clock or Normal Mode Select inPort 4 RMII

43

RXD4_0

Ipd/O

4

PU = Clock mode in RMII, using 25MHz OSC
clock and provide 50 MHz RMII clock from pin
RXC4 (Default)
PD = Normal mode in RMII, the TXC4/REFCLKI4
pin on the Port 4 RMII will receive an external
50 MHz clock
Note: Port 4 also can use either an internal orexternal clock in RMII mode based on this strap
pin or the setting of the Register 70 (0x46) bit [7].
An external pull-up/down resistor is requested forthe strap-in.

44

RXDV4/CRSDV4

IPD/O

45

NC

NC

46

VDD12DP47

TXC5/REFCLKI5/
GTXC5

I/O

4

RMII:
CRSDV4 is for Port 4 RMII carrier sense/receive
data valid output.
No connect

51.2V core power

5

Port 5 Switch GMAC5 Clock Pin:
MII: 2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII: Input for receiving 50 MHz in normal mode.
RGMII: Input 125 MHz clock with falling and risingedge to latch data for the data transfer.

48

RXC5/
GRXC5

I/O

5

Port 5 Switch GMAC5 Clock Pin:
MII: 2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII: Output 50 MHz reference clock for thereceiving/transmit in the clock mode.
RGMII: Output 125 MHz clock with falling and rising edge to latch data for the receiving.

49

RXD5_0IPD/O

5RGMII/MII/RMII:Port 5 switch receive bit [0]50RXD5_1IPD/O

5RGMII/MII/RMII:Port 5 switch receive bit [1]

51

GNDD

GND

52

VDDIO

P

53

RXD5_2

 2015 Microchip Technology Inc.

IPD/O

Digital ground
3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.

5

RGMII/MII:Port 5 switch receive bit [2]RMII:
No connection.

DS00002129C-page 9

KSZ8775CLXTABLE 2-1:
Num Pins

54

55

56

57

58

59

SIGNALS (CONTINUED)
Pin Name

RXD5_3

RXDV5/CRSDV5/RXD5_CTL

RXER5

CRS5

COL5

REFCLKO

Type

IPD/O

IPD/O

IPD/O

IPD/O

IPD/O

Port

Pin Description

5

RGMII/MII:Port 5 switch receive bit [3]RMII:
No connection.

5

MII:
RXDV5 is for Port 5 switch MII receiving data
valid.
RMII:CRSDV5 is for Port 5 RMII carrier sense/receive
data valid output.
RGMII:
RXD5_CTL is for Port 5 RGMII receiving data
control.

5

MII:Port 5 switch receive error.
RGMII/RMII:
No connection.

5

MII:
Port 5 switch MII modes carrier sense.
RGMII/RMII:
No connection.

5

MII:
Port 5 Switch MII collision detect.
RGMII/RMII:
No connection.

IPU/O

25 MHz clock output (Option)
Controlled by the strap pin LED2_0.
Default is enabled; it is better to disable it if notusing it.

60

PME_N

I/O

Power Management Event
This output signal indicates that a wake-on-LAN
event has been detected as a result of a wake-up
frame detection. The KSZ8775CLX is requesting
the system to wake up from low power mode. Its
assertion polarity is programmable with thedefault polarity set to active low.

61

GNDD

GND

Digital ground

62

TXEN4

IPD

DS00002129C-page 10

4

RMII:
Port 4 switch SW4-RMII transmit enable.

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 2-1:
Num Pins

63

64

65

66

67

68

SIGNALS (CONTINUED)
Pin Name

LED2_1

LED2_0

LED1_1

LED1_0SPIQ

SCL_MDC

 2015 Microchip Technology Inc.

Type

IPU/O

IPU/O

IPU/O

IPU/O

IPD/O

IPU

Port

Pin Description

2

Port 2 LED Indicator 1.
See global Register 11 bits [5:4] for details.
Strap option: Port 5 MII and RMII modes selectWhen Port 5 is MII mode:
PU = MAC mode.
PD = PHY mode.
When Port 5 is RMII mode:
PU = Clock mode in RMII, using 25 MHz OSC
clock and provide 50 MHz RMII clock from pin
RXC5.
PD = Normal mode in RMII, the TXC5/REFCLKI5
pin on the Port 5 RMII will receive an external
50 MHz clock
Note: Port 5 also can use either an internal orexternal clock in RMII mode based on this strap
pin or the setting of the Register 86 (0x56) bit[7].

2Port 2 LED Indicator 0.
See global Register 11 bits [5:4] for details.
Strap option: REFCLKO enable
PU = REFCLK_O (25 MHz) is enabled. (default)
PD = REFCLK_O is disabled
Note: It is better to disable this 25 MHz clock if
not providing an extra 25 MHz clock for system.

1

Port 1 LED Indicator 1.
See global Register 11 bits [5:4] for details.
Strap option: PLL clock source selectPU = Still use 25 MHz clock from XI/XO pins eventhough it is in Port 5 RMII normal mode.
PD = Use external clock from TXC5 in Port 5 RMII
normal mode.
Note: If received clock in Port 5 RMII normal
mode has too much clock jitter, you can still selectthe 25 MHz crystal/oscillator as the switch’s clock
source.

1

Port 1 LED Indicator 0.
See global Register 11 bits [5:4] for details.
Strap option: Speed select in Port 5 RGMII
PU = 1 Gbps in RGMII. (default)
PD = 10/100 Mbps in RGMII.
Note: Programmable through internal registers
also.

All

SPI Serial Data Output in SPI Slave Mode.
Strap option: Serial bus configuration
PD = SPI slave mode.
PU = MDC/MDIO mode.
Note: An external pull-up or pull-down resistor isrequired.

All

Clock Input for SPI or MDC/MDIO Interface.
Input clock up to 50 MHz in SPI slave mode.
Input clock up to 25 MHz in MDC/MDIO for MIIM
access.

DS00002129C-page 11

KSZ8775CLXTABLE 2-1:

SIGNALS (CONTINUED)

Num Pins

Pin Name

Type

Port

Pin Description

69

SDA_MDIO

IPU/O

All

Data for SPI or MDC/MDIO Interface.
Serial data input in SPI slave mode.
MDC/MDIO interface data input/output.

70

SPIS_NIPUAllSPI Interface Chip Select.
When SPIS_N is high, the KSZ8775CLX is deselected and SPIQ is held in the high impedancestate. A high-to-low transition initiates the SPI
data transfer. This pin is active low.

71

VDDIO

P

—

3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.

72

GNDD

GND

—

Digital ground.

73

RST_N

IPU

—

Reset
This active low signal resets the hardware in thedevice. See the timing requirements in the
Section 7.0, Timing Diagrams section.

74

VDD12DP—

1.2V core power

75

ATST

NC

—

No connect. Factory test pin.

76

VDDAT

P

—

3.3V or 2.5V analog power.

—

Transmit Output Current Set
This pin configures the physical transmit output
current.
It should be connected to GND through a 12.4 kΩ
1% resistor.

—

Analog ground.

77

ISET

78

GNDA

GND

79

XI

I

—

Crystal Clock Input/Oscillator Input
When using a 25 MHz crystal, this input is connected to one end of the crystal circuit. Whenusing a 3.3V oscillator, this is the input from theoscillator.
The crystal or oscillator should have a toleranceof ±50 ppm.

80

XO

O

—

Crystal Clock Output
When using a 25 MHz crystal, this output is connected to one end of the crystal circuit.

DS00002129C-page 12

 2015 Microchip Technology Inc.

KSZ8775CLX
The KSZ8775CLX can function as a managed switch and utilizes strap-in pins to configure the device for different
modes. The strap-in option pins are configured by using external pull-up/down resistors to create a high or low state on
the pins which are sampled during the power down reset or warm reset. The functions are described in the table below.

TABLE 2-2:
Pin
Number

43

64

63

25,27

66

65

STRAP-IN OPTIONSPin Name

RXD4_0

LED2_0

LED2_1

LED3[1,0]

LED1_0

LED1_1

PU/PD

Description

IPD/O

Clock or Normal Mode Select in Port 4 RMII
Strap Option:
PU = Clock mode in RMII, using 25 MHz OSC clock and provide 50 MHz
RMII clock from pin RXC4.
PD = Normal mode in RMII, the TXC4/REFCLKI4 pin on the Port 5 RMII will
receive an external 50 MHz clock
Note: Port 4 also can use either an internal or external clock in RMII mode
based on this strap pin or the setting of the Register 70 (0x46) bit[7]. An
external pull-up/down resistor is requested.

IPU/O

REFCLKO Enable
Strap Option:
PU = REFCLK_O (25 MHz) is enabled.
PD = REFCLK_O is disabled

IPU/OPort 5 MII and RMII Modes SelectStrap Option:
When Port 5 is MII mode:
PU = MAC mode.
PD = PHY mode.
When Port 5 is RMII mode:
PU = Clock mode in RMII, using 25 MHz OSC clock and provide 50 MHz
RMII clock from pin RXC5.
PD = Normal mode in RMII, the TXC5/REFCLKI5 pin on the Port 5 RMII will
receive an external 50 MHz clock
Note: Port 5 also can use either an internal or external clock in RMII mode
based on this strap pin or the setting of the Register 86 (0x56) bit[7].

IPU/O

Switch Port 5 GMAC5 Interface Mode SelectStrap Option:
00 = MII for SW5-MII
01 = RMII for SW5-RMII
10 = Reserved
11 = RGMII for SW5-RGMII (default)

IPU/O

Port 5 Gigabit SelectStrap Option:
PU = 1 Gbps in RGMII (default).
PD = 10/100 Mbps in RGMII.
Note: Also programmable through internal register.

IPU/O

PLL Clock Source SelectStrap Option:
PU = Still uses 25 MHz clock from XI/XO pin even though it is in Port 5 RMII
normal mode (default).
PD = Uses external clock from TXC5 pin in Port 5 RMII normal mode.
Note: If received clock in Port 5 RMII normal mode has too much clock jitter,
you still can select the 25 MHz crystal/oscillator as the switch’s clock source.

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DS00002129C-page 13

KSZ8775CLXTABLE 2-2:
Pin
Number67

STRAP-IN OPTIONSPin Name

SPIQ

DS00002129C-page 14

PU/PD

Description

IPD/O

Serial Bus Configuration
Strap Option:
PD = SPI slave mode.
PU = MDC/MDIO mode.
Note: An external pull-up or pull-down resistor is required.If the uplink port isused for RGMII interface, recommend using SPI mode to have opportunity
setting the register 86 (0x56) bits [4:3] for RGMII V 2.0. MDC/MDIO mode
can’t set this feature.

 2015 Microchip Technology Inc.

KSZ8775CLX
3.0

FUNCTIONAL DESCRIPTION

The KSZ8775CLX contains three 10/100 physical layer transceivers, four media access control (MAC) units, and one
Gigabit media access control (GMAC) unit with an integrated Layer 2-managed switch. The device runs in two modes.
The first mode is as a three-port standalone switch. The second is as a five-port switch where the fifth port is provided
through a Gigabit media independent interface that supports RGMII, MII, and RMII. This is useful for implementing an
integrated broadband router.
The KSZ8775CLX has the flexibility to reside in a managed mode. In a managed mode, a host processor has complete
control of the KSZ8775CLX via the SPI bus or the MDC/MDIO interface.
On the media side, the KSZ8775CLX supports IEEE 802.3 10BASE-T/100BASE-TX on all copper ports with Auto-MDI/
MDI-X. The KSZ8775CLX can be used as a fully managed five-port switch or hooked up to a microprocessor via its
SW-RGMII/MII/RMII interfaces to allow for integrating into a variety of environments.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry and DSP technology that makes the design more efficient, allows for reduced power consumption, and smaller die size.
Major enhancements from the KSZ8995 and KS8895 to the KSZ8775CLX include high speed host interface options
such as the RGMII interface, power saving features such as IEEE 802.1az Energy Efficient Ethernet (EEE), MLD snooping, Wake-on-LAN (WoL), port-based ACL filtering for port security, enhanced QoS priority, rapid spanning tree, IGMP
snooping, port mirroring support, and flexible rate limiting.

3.1
3.1.1

Functional Overview: Physical Layer (PHY)
100BASE-TX TRANSMITThe 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII
data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B coding
followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in
MLT3 current output. The output current is set by an external 1% 12.4 kΩ resistor for the 1:1 transformer ratio. It has atypical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, andtiming jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.

3.1.2

100BASE-TX RECEIVE

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data andclock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable.
Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based oncomparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and can self-adjust against environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is thenused to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the
4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The
remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is/I/, a transmit error code-group is /H/, etc.

3.1.2.1

PLL Clock Synthesizer

The KSZ8775CLX generates 125 MHz, 83 MHz, 41 MHz, 25 MHz, and 10 MHz clocks for system timing. Internal clocks
are generated from an external 25 MHz crystal or oscillator.

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KSZ8775CLX
3.1.2.2

Scrambler/Descrambler (100BASE-TX Only)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence atthe transmitter.

3.1.3

10BASE-T TRANSMITThe 10BASE-T output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents
are at least 27 dB below the fundamental when driven by an all-ones Manchester-encoded signal.

3.1.4

10BASE-T RECEIVE

On the receive side, input buffers and level-detecting squelch circuits are employed. A differential input receiver circuit
and a PLL perform the decoding function. The Manchester-encoded data stream is separated into a clock signal and
NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse-widths in order to prevent
noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8775CLX decodes a data frame. The receiver clock is maintained active
during idle periods in between data reception.

3.1.5

MDI/MDI-X AUTO CROSSOVER

To eliminate the need for crossover cables between similar devices, the KSZ8775CLX supports HP Auto-MDI/MDI-X
and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto-MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for
the KSZ8775CLX device. This feature is extremely useful when end users are unaware of cable types, and also, saves
on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control
registers or MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are in the table below.

TABLE 3-1:

MDI/MDI-X PIN DEFINITIONS
MDI

3.1.5.1

MDI-X

RJ-45 Pins

Signals

RJ-45 Pins

Signals

1
2

TD+

1

RD+

TD–

2

RD–

3
6

RD+

3

TD+

RD–

6

TD–

Straight Cable

A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. The following
diagram depicts a typical straight cable connection between a NIC (MDI) and a switch or hub (MDI-X).

FIGURE 3-1:

TYPICAL STRAIGHT CABLE CONNECTION
10/100 ETHERNETMEDIA DEPENDENT INTERFACE

TRANSMIT PAIR

10/100 ETHERNETMEDIA DEPENDENT INTERFACE

1

1
RECEIVE PAIR2
3

2
STRAIGHT
CABLE

3

4

4

5

5

6

6

7

7

8

8

RECEIVE PAIR

TRANSMIT PAIR

MODULAR CONNECTOR(RJ-45)NIC

DS00002129C-page 16

MODULAR CONNECTOR(RJ-45)HUB(REPEATER OR SWITCH)

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KSZ8775CLX
3.1.5.2

Crossover Cable

A crossover cable connects an MDI device to another MDI device or an MDI-X device to another MDI-X device. The
following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

FIGURE 3-2:

TYPICAL CROSSOVER CABLE CONNECTION
10/100 ETHERNETMEDIA DEPENDENT INTERFACE

1
RECEIVE PAIR

10/100 ETHERNETMEDIA DEPENDENT INTERFACECROSSOVER
CABLE

1
RECEIVE PAIR

2

2

3

3

4

4

5

5

6

6

7

7

8

8

TRANSMIT PAIR

TRANSMIT PAIR

MODULAR CONNECTOR(RJ-45)HUB(REPEATER OR SWITCH)

3.1.6

MODULAR CONNECTOR(RJ-45)HUB(REPEATER OR SWITCH)

AUTO-NEGOTIATIONThe KSZ8775CLX conforms to the auto-negotiation protocol as described by the IEEE 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners
advertise their capabilities to each other and then compare their own capabilities with those they received from their link
partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. Auto-negotiation is supported only for the copper ports.
The following list shows the speed and duplex operation mode from highest to lowest.
• Highest: 100BASE-TX, full-duplex• High: 100BASE-TX, half-duplex• Low: 10Base-T, full-duplex• Lowest: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8775CLX link partner is forced to bypass auto-negotiation, the KSZ8775CLX sets its operating mode by observing the signal at its receiver. This is known as parallel detection and allows the
KSZ8775CLX to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement
protocol. The auto-negotiation link up process is shown in Figure 3-3.

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DS00002129C-page 17

KSZ8775CLX
FIGURE 3-3:

AUTO-NEGOTIATION AND PARALLEL OPERATIONSTART AUTO NEGOTIATIONNOPARALLELOPERATIONFORCE LINK SETTINGYES

BYPASS AUTO NEGOTIATION
AND SET LINK MODE

ATTEMPT AUTO
NEGOTIATION

LISTEN FOR
100BASE-TX
IDLES

LISTEN FOR
10BASE-T
LINK PULSES

JOIN
FLOW

NO
LINK MODE SET?

YES

LINK MODE SET

3.1.7

CABLE DIAGNOSTICS

The LinkMD® feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cablingproblems such as open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault withmaximum distance of 200m and accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable
digital format.
Please note that cable diagnostics are only valid for copper connections.

3.1.8

ACCESS

LinkMD is initiated by accessing the PHY’s special control/status Registers {26, 42, 58} and the LinkMD result Registers{27, 43, 59} for Ports 1, 2, and 3 respectively and in conjunction with the Port control 10 Register for Ports 1, 2, and 3
respectively to disable Auto-MDI/MDI-X.
Alternatively, the MIIM PHY Registers 0 and 1d can also be used for LinkMD access.

3.1.9

USAGE

The following is a sample procedure for using LinkMD with Registers {26, 27, 29} on Port 1.
1.
2.
3.
4.

Disable Auto-MDI/MDI-X by writing a ‘1’ to Register 29, bit [2] to enable manual control over the differential pairused to transmit the LinkMD pulse.
Start cable diagnostic test by writing a ‘1’ to Register 26, bit [4]. This enable bit is self-clearing.
Wait (poll) for Register 26, bit [4] to return a ‘0’, and indicating cable diagnostic test is completed.
Read cable diagnostic test results in Register 26, bits [6:5]. The results are as follows:•00 = normal condition (valid test)•01 = open condition detected in cable (valid test)

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KSZ8775CLX•10 = short condition detected in cable (valid test)•11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the KSZ8775CLX is unable to shut down the link partner. In this instance, thetest is not run because it would be impossible for the KSZ8775CLX to determine if the detected signal is a reflection of
the signal generated or a signal from another source.
5.

Get distance to fault by concatenating Register 26, bit [0] and Register 27, bits [7:0] and multiplying the result by
a constant of 0.4. The distance to the cable fault can be determined by the following formula:

D (distance to cable fault meter) = 0.4 x (Register 26, bit [0], Register 27, bits [7:0])
D (distance to cable fault) is expressed in meters.
Concatenated value of Registers 26 bit [0] and 27 bits [7:0] should be converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation thatvaries significantly from the norm.
For Port 2, Port 3, and using the MIIM PHY registers, LinkMD® usage is similar.

3.1.10A LINKMD® EXAMPLE

The following is a sample procedure for using LinkMD® on Port 1, Port 2, and Port 3.
//Disable Auto-MDI/MDI-X and force to MDI-X mode//’w’ is WRITE the register. ‘r’ is READ register below
w 1d 04
w 2d 04
w 3d 04//Set internal registers temporary by indirect registers, adjust for LinkMD
w 6e a0
w 6f 4dw a0 80//Enable LinkMD testing with fault cable for Port 1, Port 2, and Port 3
w 1a 10w 2a 10w 3a 10//Wait until Port Register Control 8 bit [4] returns a ‘0’ (self-clear)//Diagnosis results
r 1a
r 1b
r 2a
r 2b
r 3a
r 3b
//For example on Port 1, the result analysis based on the values of the register 0x1a and 0x1b//The register 0x1a bits [6-5] are for the open or the short detection.
//The register 0x1a bit [0] + the register 0x1b bits [7-0] = CDT_Fault_Count [8-0]//The distance to fault is about 0.4 x (CDT_Fault_Count [8-0])

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KSZ8775CLX
3.2

On-Chip Termination and Internal Biasing

The KSZ8775CLX reduces the board cost and simplifies the board layout by using on-chip termination resistors for all
ports and RX/TX differential pairs without external termination resistors. The combination of the on-chip termination andthe internal biasing will save more PCB space and power consumption in system, compared with using external biasing
and termination resistors for multiple ports’ switches because the transformers do not consume power anymore. The
center taps of the transformer should not need to be tied to the analog power.

3.3
3.3.1

Functional Overview: Media Access Controller (MAC)
MEDIA ACCESS CONTROLLER OPERATIONThe KSZ8775CLX strictly abides by IEEE 802.3 standards to maximize compatibility.

3.3.2

INTER-PACKET GAP (IPG)

If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If thecurrent packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.

3.3.3

BACK-OFF ALGORITHM

The KSZ8775CLX implements the IEEE 802.3 standard binary exponential backoff algorithm and optional “aggressivemode” back-off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in
Register 3.

3.3.4

LATE COLLISION

If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.

3.3.5

ILLEGAL FRAMESThe KSZ8775CLX discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes inRegister 4. For special applications, the KSZ8775CLX can also be programmed to accept frames up to 2k bytes inRegister 3 bit [6]. Because the KSZ8775CLX supports VLAN tags, the maximum sizing is adjusted when these tags arepresent.

3.3.6

FLOW CONTROLThe KSZ8775CLX supports standard IEEE 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8775CLX receives a pause control frame, the KSZ8775CLX will not transmit the next
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before thecurrent timer expires, the timer will be updated with the new value in the second pause frame. During this period (being
flow-controlled), only flow control packets from the KSZ8775CLX will be transmitted.
On the transmit side, the KSZ8775CLX has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based on availability of the system resources, including available buffers, available transmit queues, andavailable receive queues.
The KSZ8775CLX flow controls a port that has just received a packet if the destination port resource is busy. The
KSZ8775CLX issues a flow control frame (XOFF) containing the maximum pause time defined in the IEEE 802.3x standard. Once the resource is freed up, the KSZ8775CLX sends out the other flow control frame (XON) with zero pause
time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent overactivation and deactivation of the flow control mechanism. The KSZ8775CLX flow controls all ports if the receive queue
becomes full.

3.3.7

HALF-DUPLEX BACK PRESSURE

The KSZ8775CLX also provides a half-duplex back pressure option (this is not in IEEE 802.3 standards). The activationand deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, then the
KSZ8775CLX sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber andexcessive deference as defined in IEEE 802.3 standards, after a certain period of time, the KSZ8775CLX discontinues
carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time (no carrier
sense) prevents other stations from sending out packets and keeps other stations in a carrier-sense-deferred state. If
the port has packets to send during a back pressure situation, then the carrier-sense-type back pressure is interrupted
and those packets are transmitted instead. If there are no more packets to send, carrier-sense-type back pressure

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KSZ8775CLX
becomes active again until switch resources are free. If a collision occurs, the binary exponential back-off algorithm isskipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier
sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, theuser must enable the following:• Aggressive back-off (Register 3, bit [0])• No excessive collision drop (Register 4, bit [3])• Back pressure (Register 4, bit [5])These bits are not set as the default because this is not the IEEE standard.

3.3.8

BROADCAST STORM PROTECTION

The KSZ8775CLX has an intelligent option to protect the switch system from receiving too many broadcast packets.
Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources(bandwidth and available space in transmit queues). The KSZ8775CLX has the option to include multicast packets forstorm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per
port basis. The rate is based on a 50 ms (0.05s) interval for 100BT and a 500 ms (0.5s) interval for 10BT. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes
during the interval. The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A
(74 decimal). This is equal to a rate of 1%, as calculated in Equation 3-1.

EQUATION 3-1:
 148800 frames    se    50ms    0.05s   interval  1% =  74 frames   interval (approx) = 0x4A

3.4

Functional Overview: Switch Core

The internal look-up table stores MAC addresses and their associated information. It contains a 1k unicast address tableplus switching information. The KSZ8775CLX is guaranteed to learn 1k addresses and distinguishes itself from a hashbased look-up table, which, depending on the operating environment and probabilities, may not guarantee the absolute
number of addresses it can learn.

3.4.1

LEARNING

The internal look-up engine updates its table with a new entry if the following conditions are met:
• The received packet’s source address (SA) does not exist in the look-up table.
• The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,the last entry of the table is deleted first to make room for the new entry.

3.4.2

MIGRATION

The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly.
Migration happens when the following conditions are met:
• The received packet’s SA is in the table, but the associated source port information is different.
• The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine will update the existing record in the table with the new source port information.

3.4.3

AGING

The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The
time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove
the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging
records. The aging period is 300 ±75 seconds. This feature can be enabled or disabled through Register 3 bit [2].

3.4.4

FORWARDING

The KSZ8775CLX will forward packets using an algorithm that is depicted in the following flowcharts. The next figure
shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic
table for the destination address, and then comes up with port to forward 1 (PTF1). PTF1 is then further modified by thespanning tree, IGMP snooping, port mirroring, and port VLAN processes and authentication to come up with port to forward 2 (PTF2), as shown in the Equation 3-4. The authentication and ACL have highest priority in the forwarding process, ACL result will overwrite the result of the forwarding process. This is where the packets will be sent.
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DS00002129C-page 21

KSZ8775CLX
The KSZ8775CLX will not forward the following packets:• Error packets: These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal
size packet errors.
• IEEE 802.3x PAUSE frames: KSZ8775CLX intercepts these packets and performs full-duplex flow control accordingly.
• Local packets: Based on destination address (DA) lookup, if the destination port from the look-up table matches
the port from which the packet originated, the packet is defined as local.

FIGURE 3-4:

DESTINATION ADDRESS LOOK-UP AND RESOLUTION FLOW CHART
START

PTF 1

- SEARCH VLAN TABLE- INGRESS VLAN FILTERING- DISCARD NPVID CHECKNOVLAN ID
VALID?

PTF 1 = NULLYESGET PTF 1
FROM STATIC
ARRAY

FOUND

SEARCHSTATICARRAY- SEARCH BASED ON
DA OR DA + FID

NOT FOUNDGET PTF 1
FROM ADDRESS
TABLE

FOUND

SEARCHADDRESS
LOOK-UPTABLE- SEARCH BASED ON
DA + FIDSPANNINGTREEPROCESS

IGMP
PROCESSPORTMIRROR
PROCESS- CHECK RECEIVING PORT’S RECEIVE ENABLE BIT- CHECK DESTINATION PORT’S TRANSMIT ENABLE BIT- CHECK WHETHER PACKETS ARE SPECIAL (BPDU)- APPLIED TO MAC (#1 TO #4)- MAC #5 IS RESERVED FOR μC- IGMP WILL BE FORWARDED TO PORT 5- RX MIRROR- TX MIRROR- RX OR TX MIRROR- RX AND TX MIRRORPORT VLAN
MEMBERSHIPCHECKNOT FOUND

3.4.5

GET PTF 1 FROMVLAN TABLE

PORT
AUTHENTICATION
AND ACL

PTF 2

PTF 2

SWITCHING ENGINEThe KSZ8775CLX features a high-performance switching engine to move data to and from the MAC’s packet buffers.
It operates in store and forward modes, while the efficient switching mechanism reduces overall latency. The KSZ8775CLX has a 64kb internal frame buffer. This resource is shared between all five ports. There are a total of 512 buffers
available. Each buffer is sized at 128 bytes.

3.5
3.5.1

Functional Overview
POWER

The KSZ8775CLX device requires 3.3V analog power. An external 1.2V LDO provides the necessary 1.2V to power the
analog and digital logic cores. The various I/Os can be operated at 1.8V, 2.5V, and 3.3V. The table below illustrates thevarious voltage options and requirements of the device.

TABLE 3-2:

VOLTAGE OPTIONS AND REQUIREMENTS

Power Signal
Name

Device Pin

Requirement

VDDAT

4, 14, 76

3.3V input power to the analog blocks of transceiver in the device.

VDDIO

36, 52, 71

Choice of 1.8V or 2.5V or 3.3V for the I/O circuits. These input power pins
power the I/O circuitry of the device.

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KSZ8775CLXTABLE 3-2:

VOLTAGE OPTIONS AND REQUIREMENTS

Power Signal
Name

Device Pin

Requirement

VDD12A3

VDD12D28, 46, 74

1.2V core power. Filtered 1.2V input voltage. These pins feed 1.2V topower the internal analog and digital cores.

GNDA

5, 21, 78

Analog ground.

GNDD

29, 35, 41, 51, 61,
72

Digital ground.

3.5.2

POWER MANAGEMENTThe KSZ8775CLX supports enhanced power management in a low power state, with energy detection to ensure low
power dissipation during device idle periods. There are three operation modes under the power management function
which are controlled by the Register 14 bits [4:3] and the Port Control 10 Register bit [3] as shown below:• Register 14 bits [4:3] = 00 normal operation mode
• Register 14 bits [4:3] = 01 energy detect mode
• Register 14 bits [4:3] = 10 soft power-down mode
• Register 14 bits [4:3] = 11 reserved
The Port Control 10 Register 29, 45, 61 bit [3] = 1 are for the port-based power-down mode.
Table 3-3 indicates all internal function block statuses under four different power management operation modes.

TABLE 3-3:

INTERNAL FUNCTION BLOCK STATUS
Power Management

KSZ8775CLX
Function Blocks

Normal Mode

Energy Detect Mode

Soft Power-Down Mode

Internal PLL Clock

EnabledDisabled

Disabled

TX/RX PHY

EnabledEnergy detect at RX

Disabled

MAC

EnabledDisabled

Disabled

Host Interface

EnabledDisabled

Disabled

3.5.2.1

Normal Operation Mode

This is the default setting bits [4:3] = 00 in Register 14 after chip power-up or hardware reset. When KSZ8775CLX is innormal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is ready for CPU reador write.
During normal operation mode, the host CPU can set the bits [4:3] in Register 14 to change the current normal operation
mode to any one of the other three power management operation modes.

3.5.2.2

Energy Detect Mode

Energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8775CLX port is not connected to an active link partner. In this mode, the device will save more power when the cables areunplugged. If the cable is not plugged in, the device can automatically enter a low power state—the energy detect mode.
In this mode, the device will keep transmitting 120 ns-wide pulses at a rate of 1 pulse per second. Once activity resumes
due to plugging in a cable or an attempt by the far end to establish a link, the device can automatically power up tonormal power state in energy detect mode.
Energy detect mode consists of the normal power state and low power state. While in low power state, the device
reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detectmode is entered by setting bits [4:3] = 01 in Register 14. When the KSZ8775CLX is in this mode, it will monitor the cableenergy. If there is no energy on the cable for a time longer than the pre-configured value at bits [7:0] go-sleep time inRegister 15, then the KSZ8775CLX will go into low power state. When the KSZ8775CLX is in low power state, it willkeep monitoring the cable energy. Once the energy is detected from the cable, the device will enter normal power state.
When the device is at normal power state, it is able to transmit or receive packet from the cable.

 2015 Microchip Technology Inc.

DS00002129C-page 23

KSZ8775CLX
3.5.2.3

Soft Power-Down Mode

The soft power-down mode is entered by setting bits [4:3] = 10 in Register 14. When the KSZ8775CLX is in this mode,
all PLL clocks are disabled, also all of the PHYs and MACs are off. Any dummy host access will wake-up this device
from current soft power-down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values.

3.5.2.4

Port-Based Power-Down Mode

In addition, the KSZ8775CLX features a per-port power-down mode. To save power, a PHY port that is not in use canbe powered down via the Port Control 10 Register bit [3] or MIIM PHY Register 0 bit [11].

3.5.2.5

Energy Efficient Ethernet (EEE)

Along with supporting different power saving modes, the KSZ8775CLX extends its green functionality by supporting
EEE features defined in IEEE P802.3az/D2.3, March 2010. Both 10Base-T and 100BASE-TX EEE functions are supported in KSZ8775CLX. In 100BASE-TX, the EEE operation is asymmetric on the same link, which means one direction
could be in low power idle (LPI) state while another direction could handle packet transfer activity. Different from othertypes of power saving modes, EEE is able to maintain the link while conserving power. Based on IEEE specification,
the energy saving from EEE is done at the PHY level. KSZ8775CLX reduces the power consumption not only at PHY
level but also at MAC and switch level by shutting down the unused clocks as much as possible when the device is in
low power idle phase.

FIGURE 3-5:

EEE TRANSMIT AND RECEIVE SIGNALING PATHS
TRANSMIT PATH
MAP LPI REQUEST TO
LPI MII PATTERNISSUE ORTERMINATE LPIREQUEST
MAC

SWITCHPCS(PHY LAYER)

IDLE/DATAWAKEUPQUIET/SLEEPSLEEP/REFRESH

QUIET

SLEEP
IDLE
DATA

Quite QUIETIdle

RECEIVE PATHCONTROL/STATUS
SIGNALS
CLOCK CONTROLSTATUS REGISTERTEST CONTROL

MAC

MAP LPI/P/ AND QUIETSTATE TO LPI MIIPATTERN
PCS(PHY LAYER)

IDLE/DATAWAKEUPQUIET/SLEEPSLEEP/REFRESH

QUIET

SLEEP
IDLE
DATA

Quite QUIETIdle

LPI STATUS
SIGNALS

The KSZ8775CLX supports the IEEE 802.3az Energy Efficient Ethernet standard for both 10 Mbps and 100 Mbps interfaces. The EEE capability combines switch, MAC, and PHY to support operation in low power idle (LPI) mode. Whenthe LPI mode is enabled, systems on both sides of the link can save power during periods of low link utilization.
EEE implementation provides a protocol to coordinate transitions to or from lower power consumption without changing
the link status and without dropping or corrupting frames. The transition time into and out of the lower power consumption is kept small enough to be transparent to upper layer protocols and applications. EEE specifies the means to
exchange capabilities between link partners to determine whether EEE is supported and to select the best set of parameters common to both sides.
Besides supporting the 100BASE-TX PHY EEE, the KSZ8775CLX also supports 10BASE-T with reduced transmit
amplitude requirements for 10 Mbps mode to allow a reduction in power consumption.

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KSZ8775CLX
3.5.2.5.1

LPI Signaling

Low power idle signaling allows the switch to indicate to the PHY, and to the link partner, that a break in the data stream
is expected. The switch can use this information to enter power-saving modes that require additional time to resume
normal operation. LPI signaling also informs the switch when the link partner has sent such an indication. The definitionof LPI signaling uses the MAC for simplified full-duplex operation with carrier sense deferral. This provides full-duplex
operation but uses the carrier sense signal to defer transmission when the PHY is in the LPI mode.
The decision on when to signal LPI (LPI request) to the link partner is made by the switch and communicated to the PHY
through the MAC MII interface. The switch is also informed when the link partner is signaling LPI and indicating LPI activation (LPI indication) on the MAC interface. The conditions under which the switch decides to send LPI and what
actions are taken by the switch when it receives LPI from the link partner, are specified in the implementation section.
3.5.2.5.2

LPI Assertion

Without LPI assertion, the normal traffic transition continues on the MII interface. As soon as an LPI request is asserted,the LPI assert function starts to transmit the “Assert LPI” encoding on the MII and stops the MAC from transmitting normal traffic. Once the LPI request is de-asserted, the LPI assert function starts to transmit the normal inter-frame encoding on the MII again. After a delay, the MAC is allowed to start transmitting again. This delay is provided to allow the link
partner to prepare for normal operation. Figure 8 illustrates the EEE LPI between two active data idles.
3.5.2.5.3

LPI Detection

In the absence of “Assert LPI” encoding on the receive MII, the LPI detect function maps the receive MII signals as normal conditions. At the start of LPI, indicated by the transition from normal inter-frame encoding to the “Assert LPI” encoding on the receive MII, the LPI detect function continues to indicate idle on interface and asserts LP_IDLE indication. At
the end of LPI, indicated by the transition from the “Assert LPI” encoding to any other encoding on the receive MII, LP_IDLE indication is de-asserted and the normal decoding operation resumes.
3.5.2.5.4

PHY LPI Transmit Operation

When the PHY detects the start of “Assert LPI” encoding on the MII, the PHY signals sleep to its link partner to indicatethat the local transmitter is entering LPI mode. The EEE capability requires the PHY transmitter to go quiet after sleep
is signaled. LPI requests are passed from one end of the link to the other and system energy savings can be achieved
even if the PHY link does not go into a low power mode.
The transmit function of the local PHY is enabled periodically to transmit refresh signals that are used by the link partner
to update adaptive filters and timing circuits in order to maintain link integrity. This quiet-refresh cycle continues until the
reception of the normal inter-frame encoding on the MII. The transmit function in the PHY communicates this to the link
partner by sending a wake signal for a predefined period of time. The PHY then enters the normal operating state. No
data frames are lost or corrupted during the transition to or from the LPI mode.
In 100BT/full-duplex EEE operation, refresh transmissions are used to maintain the link and the quiet periods are used
for power saving. Approximately every 20-22 ms a refresh of 200-220 µs is sent to the link partner. The refresh transmission and quiet periods are shown in Figure 3-6.

FIGURE 3-6:

TRAFFIC ACTIVITY AND EEE LPI OPERATIONSLOW-POWER

ACTIVE

DATA/
IDLE

IDLE

TR

QUIET

WAKE

TQ

TS

QUIET

REFRESH

REFRESH

SLEEP

DATA/
IDLE

QUIET

ACTIVE

TW_PHY
TW_SYSTEM

Ts = THE PERIOD OF TIME THAT THE PHY TRANSMITS THE SLEEP SIGNAL BEFORE TURNING ALL TRANSMITTERS OFF, 200 ≤ Ts ≤ 220 USED IN 100BASE-TX.
Tq = THE PERIOD OF TIME THAT THE PHY REMAINS QUIET BEFORE SENDING THE REFRESH SIGNAL, 20_000 ≤ Tq ≤ 22_000 USED IN 100BASE-TX.
Tr = DURATION OF THE REFRESH SIGNAL, 200 ≤ Tr ≤ 220 USED IN 100BASE-TX.

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KSZ8775CLX
3.5.2.5.5

PHY LPI Receive Operation

On receive, entering the LPI mode is triggered by the reception of a sleep signal from the link partner, which indicatesthat the link partner is about to enter the LPI mode. After sending the sleep signal, the link partner ceases transmission.
When the receiver detects the sleep signal, then the local PHY indicates “Assert LPI” on the MII and the local receivercan disable some functionality to reduce power consumption. The link partner periodically transmits refresh signals thatare used by the local PHY. This quiet-refresh cycle continues until the link partner initiates transition back to normal
mode by transmitting the wake signal for a predetermined period of time controlled by the LPI assert function. This
allows the local receiver to prepare for normal operation and transition from the “Assert LPI” encoding to the normalinter-frame encoding on the MII. After a system-specified recovery time, the link supports the nominal operational data
rate.
3.5.2.5.6

Negotiation with EEE Capability

The EEE capability is advertised during the auto-negotiation stage. Auto-negotiation provides a linked device with thecapability to detect the abilities supported by the device at the other end of the link, determine common abilities, andconfigure for joint operation. Auto-negotiation is performed at power-up or reset, on command from management, due
to link failure, or due to user intervention.
During auto-negotiation, both link partners indicate their EEE capabilities. EEE is supported only if both the local device
and link partner advertise the EEE capability for the resolved PHY type during auto-negotiation. If EEE is not supported,
all EEE functionality is disabled and the LPI client does not assert LPI. If EEE is supported by both link partners for thenegotiated PHY type, then the EEE function can be used independently in either direction.

3.5.2.6

Wake-on-LAN (WoL)

Wake-on-LAN allows a computer to be turned on or woken up by a network message. The message is usually sent by
a program executed on another computer on the same local area network. Wake-up frame events are used to wake thesystem whenever meaningful data is presented to the system over the network. Examples of meaningful data include
the reception of a Magic Packet™, a management request from a remote administrator, or simply network traffic directly
targeted to the local system. The KSZ8775CLX can be programmed to notify the host of the wake-up frame detection
with the assertion of the interrupt signal (INTR_N) or assertion of the power management event (PME) signal. The PME
control is by PME indirect registers.
KSZ8775CLX MAC supports the detection of the following wake-up events:• Detection of an energy signal over a pre-configured value: Port PME Control Status Register bit [0] in PME indirect
registers.
• Detection of a link-up in the network link state: Port PME Control Status Register bit [1] in the PME indirect
registers.
• Receipt of a Magic Packet: Port PME Control Status Register bit [2] in the PME indirect registers.
There are also other types of Wake-up events that are not listed here as manufacturers may choose to implement thesein their own ways.
3.5.2.6.1

Direction of Energy

Link status wake events are useful to indicate a link-up in the network’s connectivity status.
3.5.2.6.2

Magic Packet™

The Magic Packet™ is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (FF FF FF FF FF FF)
followed by 16 repetitions of the target computer's 48-bit DA MAC address. Because the Magic Packet is only scanned
for the above string, and not actually parsed by a full protocol stack, it may be sent as any network- and transport-layer
protocol.
Magic Packet technology is used to remotely wake up a sleeping or powered-off PC on a LAN. This is accomplished bysending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capableof receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller. When the LAN
controller receives a Magic Packet frame, it will alert the system to wake up. Once the KSZ8775CLX has been enabledfor Magic Packet detection in Port PME Control Mask Register bit [2] in the PME indirect register, it scans all incoming
frames addressed to the node for a specific data sequence that indicates to the controller this is a Magic Packet frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as source address(SA), destination address (DA), which may be the receiving station’s IEEE MAC address, or a multicast or broadcast
address and CRC. The specific sequence consists of 16 duplications of the MAC address of this node with no breaks

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KSZ8775CLX
or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization
stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, aslong as the 16 duplications of the IEEE address match the address of the machine to be awakened.
3.5.2.6.3

Example of Magic Packet

If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scanning for the data sequence (assuming an Ethernet frame):
DA - SA - TYPE - FF FF FF FF FF FF - 11 22 33 44 55 66 -11 22 33 44 55 66-11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66- 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 3344 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66-MISC-CRC.
There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet oran IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a nodeat the frame’s destination. If the scans do not find the specific sequence shown above, it discards the frame and takes
no further action. If the KSZ8775CLX detects the data sequence, however, it then alerts the PC’s power management
circuitry (asserts the PME pin) to wake up the system.
3.5.2.6.4

Interrupt (INT_N/PME_N)

INT_N is an interrupt signal that is used to inform the external controller that there has been a status update in the
KSZ8775CLX interrupt status register. Bits [3:0] of Register 125 are the interrupt mask control bits to enable and disable
the conditions for asserting the INT_N signal. Bits [3:0] of Register 124 are the interrupt status bits to indicate whichinterrupt conditions have occurred. The interrupt status bits are cleared after reading those bits in the Register 124.
PME_N is an optional PME interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ8775CLX interrupt status register. Bits [4] of Register 125 are the PME mask control bits to enable
and disable the conditions for asserting the PME_N signal. Bits [4] of Register 124 are the PME interrupt status bits toindicate which PME interrupt conditions have occurred. The PME interrupt status bit [4] is cleared after reading this bitof the Register 124.
Additionally, the interrupt pins of INT_N and PME_N eliminate the need for the processor to poll the switch for statuschange.

3.5.3

FUNCTIONAL OVERVIEW: INTERFACESThe KSZ8775CLX device incorporates a number of interfaces that enable it to be designed into a standard network environment as well as a vendor-unique environment. The available interfaces are summarized in the table below. The
details for each usage in Table 3-4 is provided in the sections that follow.

TABLE 3-4:

AVAILABLE INTERFACES
Type

Usage

Registers
Accessed

SPI

Configuration andRegister Access[As Slave Serial Bus] - External CPU or controller can R/W all internal registers through this interface.

All

MIIM

Configuration andRegister Access

MDC/MDIO-capable CPU or controllers can R/W 4 PHYs registers.

PHYs Only

GMII

Data Flow

Interface to the Port 5 GMAC using the standard GMII timing.

N/AInterface

MII

Data Flow

Interface to the Port 5 GMAC using the standard MII timing.

N/A

RGMII

Data Flow

Interface to the Port 5 GMAC using the faster reduced GMII timing.

N/A

RMII

Data Flow

Interface to the Port 5 GMAC using the faster reduced MII timing.

N/A 2015 Microchip Technology Inc.

DS00002129C-page 27

KSZ8775CLX
3.5.3.1
3.5.3.1.1

Configuration Interface
SPI Slave Serial Bus Configuration

The KSZ8775CLX can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including“VLAN,” “IGMP snooping,” “MIB counters,” etc. The external SPI master device can access any registers randomly inthe datasheet shown. The SPI mode can configure all the desired settings including indirect registers and tables.
KSZ8775 default is in the ‘start switch’ mode with the register 1 bit [0] =’1’, to disable the switch, write a "0" to Register
1 bit [0].
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KSZ8775CLX also supports multiple reads or writes. After a byte is written to or read from the
KSZ8775CLX, the internal address counter automatically increments if the SPI slave select signal (SPIS_N) continues
to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on
SPIQ. If SPIS_N is kept low after the first byte is written, then bits on the master out slave input (SPID) line will be written
to the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal
must be asserted high and then low again before issuing another command and address. The address counter wraps
back to zero once it reaches the highest address. Therefore, the entire register set can be written to or read from by
issuing a single command and address.
The KSZ8775CLX is able to support a SPI bus up to 50MHz. A high performance SPI master is recommended to prevent internal counter overflow.
To use the KSZ8775CLX SPI:
1.

At the board level, connect the KSZ8775CLX pins as shown in Table 3-5.

TABLE 3-5:

2.
3.
4.

SPI CONNECTIONSKSZ8775CLX Signal Name

Microprocessor Signal Description

SPIS_N (S_CS)

SPI slave selectSCL (S_CLK)SPI clock

SDA (S_DI)

Master out. Slave input.

SPIQ (S_DO)

Master input. Slave output.

Configure the serial communication to SPI slave mode by pulling down pin SPIQ with a pull-down resistor.
Write configuration data to registers using a typical SPI write data cycle as shown in Figure 3-7 or SPI multiple
write as shown in Figure 3-8. Note that data input on SDA is registered on the rising edge of SCL clock.
Registers can be read and the configuration can be verified with a typical SPI read data cycle as shown in
Figure 3-7 or a multiple read as shown in Figure 3-8. Note that read data is registered out of SPIQ on the fallingedge of SCL clock.

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KSZ8775CLX
FIGURE 3-7:

SPI ACCESS TIMING

S_CS
S_CS
S_CLK
S_CLK

S_DI
S_DI

0

1

0

A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

TR

D7

D6

D5

D4

D3

D2

D1

D0

D2

D1

D0

S_DO
S_DO
Write
WRITE
Command
COMMAND

WRITE
Write
Data
DATA

WRITE
Write
Address
ADDRESSA) SPI Write CycleA) SPI WRITE CYCLE

S_CS
S_CS
S_CLK
S_CLK
S_DI
S_DI

S_DO
S_DO

0

1

1

A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

TR

D7
Read
READ
Command
COMMAND

ReadREAD
Address
ADDRESS

D6

D5

D4

D3

READ
Read
Data
DATA

B)B)
SPI
Read
Cycle
SPI
READ
CYCLE

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DS00002129C-page 29

KSZ8775CLX
FIGURE 3-8:

SPI MULTIPLE ACCESS TIMING

S_CS
S_CLK
S_DI

0

1

0

A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

TR

D7

D6

D5

D4

D3

D2

D1

D0

D2

D1

D0

D2

D1

D0

D2

D1

D0

S_DO
WRITE
COMMANDWRITEBYTE 1WRITE
ADDRESS

S_CS
S_CLK
S_DI

D7

D6

D5 D4

D3

D2

D1

D0

D7

D6

D5

WRITE
BYTE 2

D4

D3

WRITE
BYTE NA) SPI WRITE CYCLE

S_CS
S_CLK
S_DI

0

1

1

A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

TR

D7

S_DO
READ
COMMAND

D6

D5

D4

D3

READ
BYTE 1READ
ADDRESS

S_CS
S_CLK
S_DI

D7

D6

D5 D4

D3

D2

D1

D0

D7

READ
BYTE 2

D6

D5

D4

D3

READ
BYTE N
B)B)
SPI
Read
Cycle
SPI
READ
CYCLE

3.5.3.1.2

MII Management Interface (MIIM)

The KSZ8775CLX supports the standard IEEE 802.3 MII management interface, also known as the management data
input/output (MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8775CLX. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY
settings. Further details on the MIIM interface are found in clause 22.2.4.5 of the IEEE 802.3u specification.
The MIIM interface consists of the following:• A physical connection that incorporates the data line MDIO and the clock line MDC.
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8775CLX device.
• Access to a set of eight 16-bit registers, consisting of eight standard MIIM Registers [0:5h], 1d and 1f MIIM
registers per port.
The MIIM interface can operate up to a maximum clock speed of 25 MHz MDC clock.
The following table depicts the MII management interface frame format.

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KSZ8775CLXTABLE 3-6:

Read

MII MANAGEMENT INTERFACE FRAME FORMAT (Note 1)

Preamble

Start of
Frame

Read/
Write
OP CodePHY
Address
Bits[4:0]

REG
Address
Bits[4:0]

TA

Data Bits[15:0]

Idle

32 1s

01

10

AAAAA

RRRRR

Z0

DDDDDDDD_DDDDDDDD

Z

Write
32 1s
01
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Note 1: 4.Preamble: Consists of 32 1s
Start of Frame: The start of frame is indicated by a 01 pattern. This pattern assures transitions from thedefault logic one line state to zero and back to one.
OP Code: The operation code for a read transaction is 10, while the operation code for a write transaction
is 01.
PHY Address: The PHY address is five bits, allowing 32 unique PHY addresses. The first PHY address bit
transmitted and received is the MSB of the address.
REG Address: The register address is five bits, allowing 32 individual registers to be addressed within each
PHY. The first register address bit transmitted and received is the MSB of the address.
TA: The turnaround (TA) time is 2-bit time spacing between the register address field and the data field of aframe to avoid contention during a read transaction. For a read transaction, both the master and the PHYs
shall remain in a high-impedance state for the first bit time of the turnaround. The PHY shall drive a 0 bit
during the second bit time of the turnaround of a read transaction. During a write transaction, the mastershall drive a 1 bit for the first bit time of the turnaround and a 0 bit for the second bit time of the turnaround.
DATA: The data field is 16 bits. The first data bit transmitted and received shall be bit 15 of the register being
addressed.
The MIIM interface does not have access to all the configuration registers in the KSZ8775CLX. It can only access thestandard MIIM registers. See “Section 4.13, "MIIM Registers"”. The SPI interface, on the other hand, can be used toaccess all registers with the entire KSZ8775CLX feature set.

3.5.4

SWITCH PORT 4 MAC INTERFACE

3.5.4.1

Port 4 MAC4 SW4-RMII Interface

The reduced media independent interface (RMII) specifies a low pin-count media independent interface (MII). The
KSZ8775CLX supports RMII interface at Port 4’s switch side, provides a common interface at the MAC4 layer in thedevice, and has the following key characteristics:• Supports 10 Mbps and 100 Mbps data rates.
• Uses a single 50 MHz clock reference (provided internally or externally). In internal mode, the chip provides areference clock from the RXC4 pin to the opposite clock input pin for RMII interface. In external mode, the chipreceives a 50 MHz reference clock on the REFCLKI4 pin from an external oscillator or opposite RMII interface.
• Provides independent 2-bit-wide (bi-bit) transmit and receive data paths.
In internal mode, and when using an internal 50 MHz clock as SW4-RMII reference clock, the KSZ8775CLX Port 4
should be set to clock mode by the Strap Pin RXD4_0 or the Port Register 70 bit[7]. The clock mode of the KSZ8775CLX
device will provide the 50 MHz reference clock to the Port 4 RMII interface.
In external mode, when using an external 50 MHz clock source as SW4-RMII reference clock, the KSZ8775CLX Port 4
should be set to normal mode by the Strap Pin RXD4_0 or Port Register 70 bit[7]. The normal mode of the KSZ8775CLX
device will start to work when it gets the 50 MHz reference clock from pin TXC4/REFCLKI4 from an external 50 MHz
clock source.

 2015 Microchip Technology Inc.

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KSZ8775CLXTABLE 3-7:

PORT 4 SW4-RMII CONNECTION

SW4-RMII MAC-to-MAC Connection(PHY Mode)–

SW4-RMII MAC-to-PHY Connection(MAC Mode)

External
MAC

KSZ8775CLX
SW4-RMII

SignalType

Description

External
PHY

KSZ8775CLX
SW4-RMII

SignalType

REF_CLKI

RXC4

Output 50 MHz
in clock mode

Reference
Clock

50 MHzREFCLKI4

Input 50MHz innormal mode

CRS_DV

RXDV4/CRSDV4

OutputCarrier Sense/
Receive Data
Valid

CRS_DV

TXEN4

Input

RXD[1:0]

RXD4[1:0]

OutputReceive Data
Bit [1:0]

RXD[1:0]

TXD4[1:0]

Input

TX_EN

TXEN4

Input

Transmit Data
EnableTX_EN

RXDV4/CRSDV4

OutputTXD[1:0]

TXD4[1:0]

Input

Transmit Data
Bit 1

TXD[1:0]

RXD4[1:0]

Output50 MHzREFCLKI4

Input 50 MHz
innormal mode

Reference
Clock

REF_CLKI

RXC4

Output 50 MHz
in clock mode

MAC/PHY mode in RMII is different from MAC/PHY mode in MII. There is no strap pin and register configuration request
in RMII.

3.5.4.2

Switch Port 5 GMAC Interface

The KSZ8775CLX GMAC5 interface supports four MII/RGMII/RMII interface protocols and shares one set of input/
output signals. The purpose of this interface is to provide a simple, inexpensive, and easy-to-implement interconnection
between the GMAC/MAC sub-layer and a GPHY/PHY. Data on these interfaces are framed using the IEEE Ethernet
standard. As such, it consists of a preamble, start of frame delimiter, Ethernet headers, protocol-specific data, and acyclic redundancy check (CRC) checksum.
Transmit and receive signals for MII/RGMII/RMII interfaces are shown in the table below.

TABLE 3-8:

SIGNALS OF RGMII/MII/RMII

Direction Type

RGMII

MII

RMII

Input (Output)
Input

GTXC

TXC

REFCLKI

—

TXER

—

Input

TXD_CTL

TXEN

TXEN

Input (Output)

—

COL

—

Input

TXD[3:0]

TXD[3:0]

TXD[1:0]

Input (Output)

GRXC

RXC

RXC

Output

—

RXER

RXER

Output

RXD_CTLRXDVCRS_DV

Input (Output)

—

CRS

—

OutputRXD[3:0]

RXD[3:0]

RXD[1:0]

3.5.4.2.1

Standard Media Independent Interface (MII)For MII, the interface is capable of supporting 10/100 Mbps operation. Data and delimiters are synchronous to clockreferences. It provides four independent transmit and receive data paths and uses signal levels; two media status signals are also provided. The CRS indicates the presence of carrier, and the COL indicates the occurrence of a collision.
Both half- and full-duplex operations are provided by the MII interface.
MII transfers data using 4-bit words (nibble) in each direction, clocked at 2.5/25 MHz to achieve 10/100 Mbps speed.

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KSZ8775CLX
3.5.4.2.2

Reduced Media Independent Interface (RMII)RMII specifies a low pin count media independent interface. The KSZ8775CLX supports the RMII interface on the Port
5 GMAC5 and provides the following key characteristics:• Supports 10 Mbps and 100 Mbps data rates.
• Uses a single 50 MHz clock reference (provided internally or externally). In internal mode, the chip provides a reference clock from the RXC pin to the opposite clock input pin for RMII interface. In external mode, the chipreceives 50 MHz reference clock from an external oscillator or opposite RMII interface.
• Provides independent 2-bit wide (bi-bit) transmit and receive data paths.
3.5.4.2.3

Reduced Gigabit Media Independent Interface (RGMII)

RGMII is intended to be an alternative to the IEEE 802.3u MII and the IEEE 802.3z RGMII. The principle objective is to
reduce the number of pins required to interconnect the GMAC and the GPHY in a cost-effective and technology-independent manner. In order to accomplish this, the data paths and all associated control signals are reduced, control signals are multiplexed together, and both edges of the clock are used. For Gigabit operation, the clocks operate at
125 MHz with the rising edge and falling edge used to latch the data.
3.5.4.2.4

Port 5 GMAC5 SW5-RGMII Interface

Table 3-9 shows the RGMII reduced connections when connecting to an external GMAC or GPHY.

TABLE 3-9:

PORT 5 SW5-RGMII CONNECTION
KSZ8775CLX SW5-RGMII Connection—

External GMAC/GPHY

SW5-RGMII Signals

Type

Description

MRX_CTL

TXD5_CTL

Input

Transmit Control

MRXD[3:0]

TXD5[3:0]

Input

Transmit Data Bit[3:0]

MRX_CLK

GTX5_CLK

Input

Transmit Clock

MTX_CTL

RXD5_CTL

OutputReceive Control

MTXD[3:0]

RXD5[3:0]

OutputReceive Data Bit[3:0]

MGTX_CLK

GRXC5

OutputReceive Clock

The RGMII interface operates at up to a 1 Gbps speed rate. Additional transmit and receive signals control the different
directions of data transfer. This RGMII interface supports RGMII Rev. 2.0 with adjustable ingress clock and egress clock
delay by Register 86 (0x56).
For proper RGMII configuration with the connection partner, the Register 86 (0x56) bits [4:3] need to setup correctly. A
configuration table in Table 3-10.

TABLE 3-10:

PORT 5 SW5-RGMII CLOCK DELAY CONFIGURATION WITH CONNECTIONPARTNER

KSZ8775 Register
86 Bits [4:3]
Configuration
Bit [4:3] = 11 Mode
Bit [4:3] = 10 Mode
Bit [4:3] = 01 Mode
Bit [4:3] = 00 Mode

RGMII Clock Mode
(Receive andTransmit)

KSZ8775
Register 86 (0x56)

KSZ8775 RGMII
Clock Delay/Slew
Configuration

Connection Partner
RGMII Clock
Configuration(Note 1)Ingress Clock Input

Bit [4] = 1

Delay

No DelayEgress Clock Output

Bit [3] = 1

Delay

No DelayIngress Clock Input

Bit [4] = 1

Delay

No DelayEgress Clock Output

Bit [3] = 0

No Delay

Delay

Ingress Clock Input

Bit [4] = 0 (default)

No Delay

Delay

Egress Clock Output

Bit [3] = 1 (default)

Delay

No DelayIngress Clock Input

Bit [4] = 0

No Delay

Delay

Egress Clock Output
Bit [3] = 0
No DelayNote 1: A processor with RGMII, an external GPHY, or KSZ8775 back-to-back connection

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Delay

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KSZ8775CLX
For example, two KSZ8775 devices are the back-to-back connection. If one device set bit [4:3] = ’11’, another one
should set bit [4:3] = ‘00’. If one device set bit [4:3] =’01’, another one should set bit [4:3] = ‘01’ too.
The RGMII mode is configured by the strap-in Pin LED3 [1:0] = ’11’ (default) or Register 86 (0x56) bits [1:0] = ‘11’
(default). The speed choice is set by the strap-in pin LED1_0 or Register 86 (0x56) bit [6], the default speed is 1 Gbps
with bit [6] = ‘1’, set bit [6] = ‘0’ is for 10/100 Mbps speed in RGMII mode. KSZ8775CLX provides Register 86 bits [4:3]with the adjustable clock delay and Register 164 bits [6:4] with the adjustable drive strength for best RGMII timing on
board level in 1 Gbps mode.
3.5.4.2.5

Port 5 GMAC5 SW5-MII Interface

The table below shows two connection methods. The first is an external MAC connecting in SW5-MII PHY mode. The
second is an external PHY connecting in SW5-MII MAC mode. The MAC mode or PHY mode setting is determined by
the strap pin LED2_1.

TABLE 3-11:

PORT 5 SW5-MII CONNECTION

MAC-to-MAC Connection
KSZ8775CLX MAC5 SW5-MII PHY Mode—

MAC-to-PHY Connection
KSZ8775CLX MAC5 SW5-MII PHY Mode

External MAC

SW5-MIII
Signals

Type

Description

External PHY

SW5-MII
Signals

Type

MTXEN

TXEN5

Input

Transmit
Enable

MTXEN

RXDV5

Output

MTXER

TXER5

Input

Transmit Error

MTXER

RXER5

Output

MTXD[3:0]

RXD5[3:0]

Output

MTXD[3:0]

TXD5[3:0]

Input

Transmit Data
Bit[3:0]

MTXC

TXC5

OutputTransmit Clock

MTXC

RXC5

Input

MCOL

COL5

Input

MCOL

COL5

OutputCollision
Detection

MCRS

CRS5

OutputCarrier Sense

MCRS

CRS5

Input

MRXDV

RXDV5

OutputReceive Data
Valid

MRXDV

TXEN5

Input

MRXER

RXER5

OutputReceive Error

MRXER

TXER5

Input

OutputReceive Data
Bit[3:0]

MRXD[3:0]

TXD5[3:0]

Input

MRXD[3:0]

RXD5[3:0]

MRXC
RXC5
OutputReceive Clock
MRXC
TXC5
Input
The MII interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces, so they
run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid
or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid
and without physical layer errors. For half-duplex operation, there is a COL signal that indicates a collision has occurred
during transmission.
Note that normally, MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate
a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation
with an external MAC, if the device interfacing with the KSZ8775CLX has an MRXER pin, it can be tied low. For MAC
mode operation with an external PHY, if the device interfacing with the KSZ8775CLX has an MTXER pin, it can be tiedlow.
3.5.4.2.6

Port 5 GMAC5 SW5-RMII Interface

The reduced media independent interface (RMII) specifies a low pin count media independent interface. The KSZ8775CLX supports RMII interface on Port 5 and provides the following key characteristics:• Supports 10 Mbps and 100 Mbps data rates.
• Uses a single 50 MHz clock reference (provided internally or externally): In internal mode, the chip provides a reference clock from the RXC5 pin to the opposite clock input pin for RMII interface when Port 5 RMII is set to clockmode.
• In external mode, the chip receives 50 MHz reference clock on the TXC5/REFCLKI5 pin from an external oscillator or opposite RMII interface when the device is set to normal mode.
• Provides independent 2-bit wide (bi-bit) transmit and receive data paths.

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KSZ8775CLX
For the details of SW5-RMII (Port 5 GMAC5 RMII) signal connection, see Table 3-12:
When the device is strapped to normal mode, the reference clock comes from the TXC5/REFCLKI5 pin and will be usedas the device’s clock source. The strap pin LED1_1 can select the device’s clock source either from the TXC5/REFCLKI5 pin or from an external 25 MHz crystal/oscillator clock on the XI/XO pin.
In internal mode, when using an internal 50MHz clock as SW5-RMII reference clock, the KSZ8775CLX Port 5 should
be set to clock mode by the strap pin LED2_1 or the port Register 86 bit[7]. The clock mode of the KSZ8775CLX device
will provide the 50 MHz reference clock to the Port 5 RMII interface.
In external mode, when using an external 50 MHz clock source as SW5-RMII reference clock, the KSZ8775CLX Port 5
should be set to normal mode by the strap pin LED2_1 or the port Register 86 bit[7]. The normal mode of the KSZ8775CLX device will start to work when it receives the 50 MHz reference clock on the TXC5/REFCLKI5 pin from an external
50 MHz clock source.

TABLE 3-12:

PORT 5 SW5-RMII CONNECTION (Note 1)

MAC-to-MAC Connection
KSZ8775CLX SW5-RMII PHY Mode
External
MAC
REF_CLKI

SW5-RMII
Signals
RXC5

CRS_DV

MAC-to-PHY Connection
KSZ8775CLX SW5-RMII MAC Mode
External
PHY
50 MHzSW5-RMII
Signals
REFCLKI5

Carrier Sense/
Receive Data
Valid

CRS_DV

TXEN5

Input

–

Receive Error

RXER

TXER5

Input

RXD5[1:0]

OutputReceive Data
Bit[1:0]

RXD[1:0]

TXD5[1:0]

Input

TX_EN

TXEN5

Input

Transmit Data
EnableTX_EN

RXDV5/CRSDV5

OutputTXD[1:0]

TXD5[1:0]

Input

Transmit Data
Bit 1

TXD[1:0]

RXD5[1:0]

Output50 MHzREFCLKI5

Input 50 MHz
in Normal
Mode

Reference
Clock

REF_CLKI

RXC5

Output 50 MHz
in Clock ModeType

Description

Output 50 MHz
in Clock Mode

Reference
Clock

RXDV5/CRSDV5

Output––RXD[1:0]

Type
Input 50 MHz
in Normal
Mode

Note 1: MAC/PHY mode in RMII is different from MAC/PHY mode in MII. There is no strap pin and register configuration request in RMII; just follow the signal connections in the table above.

3.5.5
3.5.5.1

FUNCTIONAL OVERVIEW: ADVANCED FUNCTIONALITYQoS Priority Support

The KSZ8775CLX provides quality of service (QoS) for applications such as VoIP and video conferencing. The
KSZ8775CLX offers one, two, or four priority queues per port by setting the Port Control 13 Registers bit [1] and the Port
Control 0 Registers bit [0]. The 1/2/4 queues split as follows.
• [Port Control 9 Registers bit [1], Control 0 bit [0]] = 00 Single output queue as default.
• [Port Control 9 Registers bit [1], Control 0 bit [0]] = 01 Egress port can be split into two priority transmit queues.
• [Port Control 9 Registers bit [1], Control 0 bit [0]] = 10 Egress port can be split into four priority transmit queues.
The four priority transmit queue is a new feature in the KSZ8775CLX. Queue 3 is the highest priority queue and Queue
0 is the lowest priority queue. The Port Control 9 Registers bit [1] and the Port Control 0 Registers bit [0] are used toenable split transmit queues for Ports 1, 2, 3, 4, and 5, respectively. If a port's transmit queue is not split, high priority
and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or to use programmable weighted fairqueuing for the four priority queue scale by the Port Control 14, 15, 16, and 17 Registers (default values are 8, 4, 2, 1
by their bits [6:0].

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KSZ8775CLX
Register 130 bit [7:6] Prio_2Q[1:0] is used when the two-queue configuration is selected. These bits are used to map
the 2-bit result of IEEE 802.1p from Registers 128 and 129 or ToS/DiffServ mapping from Registers 144-159 (for four
queues) into two-queue mode with priority high or low.
Please see the descriptions of Register 130 bits [7:6] for more detail.
3.5.5.1.1

Port-Based Priority

With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received
at the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. The Port Control 0 Registers bits [4:3] is used to enable port-based priority for Ports 1,
2, 3, 4, and 5, respectively.
3.5.5.1.2

802.1p-Based Priority

For 802.1p-based priority, the KSZ8775CLX examines the ingress (incoming) packets to determine whether they are
tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value,as specified by Registers 128 and 129. Both Register 128 and 129 can map 3-bit priority fields of 0-7 value to 2-bit
results of 0-3 priority levels. The priority mapping value is programmable.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.

FIGURE 3-9:
8

6

6

2

2

PREAMBLE

DA

SA

VPID

TCI LENGTH LLC

BITS

16
TAGGED PACKET TYPE

3

802.1Q VLAN TAG (8100 FOR ETHERNET) 802.1P

2

46-1500

1

12

CFI

BYTES

802.1P PRIORITY FIELD FORMATVLAN ID

DATA

4
FCS

802.1p-based priority is enabled by bit [5] of the Port Control 0 Registers for Ports 1, 2, 3, 4, and 5, respectively.
The KSZ8775CLX provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the two-byte VLAN protocol ID (VPID) and the two-byte tag control information (TCI)
field, is also referred to as the IEEE 802.1Q VLAN tag.
Tag insertion is enabled by bit[2] of the Port Control 0 Registers and the Port Control 8 Registers to select which source
port (ingress port) PVID can be inserted on the egress port for Ports 1, 2, 3, 4, and 5, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the Port Control 3
and Control 4 Registers for Ports 1, 2, 3, 4, and 5, respectively. The KSZ8775CLX will not add tags to already tagged
packets.
Tag removal is enabled by bit [1] of the Port Control 0 Registers for Ports 1, 2, 3, 4, and 5, respectively. At the egress
port, tagged packets will have their IEEE 802.1Q VLAN tags removed. The KSZ8775CLX will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
IEEE 802.1p priority field re-mapping is a QoS feature that allows the KSZ8775CLX to set the user priority ceiling at any
ingress port by the Port Control 2 Register bit [7]. If the ingress packet’s priority field has a higher priority value than thedefault tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.

3.5.5.2

DiffServ-Based Priority

DiffServ-based priority uses the ToS registers (Registers 144 to 159) in the advanced control registers section. The ToS
priority control registers implement a fully decoded, 128-bit differentiated services code point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field are fully
decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP register todetermine priority.DiffServ-Based Priority

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KSZ8775CLX
3.5.6

SPANNING TREE SUPPORTPort 5 is the designated port for spanning tree support.
The other ports (Port 1 through Port 4) can be configured in one of the five spanning tree states via transmit enable,
receive enable, and learning disable register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4, respectively.
The KSZ8775CLX supports common spanning tree (CST). To support spanning tree, the host port (Port 5) is the designated port for the processor. The other ports can be configured in one of the five spanning tree states via transmit
enable, receive enable, and learning disable register settings in Port Control 2 Registers. The following table shows theport setting and software actions taken for each of the five spanning tree states.

TABLE 3-13:

PORT SETTINGS AND SOFTWARE ACTIONS FOR SPANNING TREE STATESDisable StatePort Setting

Software Action

The port should not
forward or receive any
packets. Learning is
disabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 1

The processor should not send any packets to the port. The
switch may still send specific packets to the processor (packets
that match some entries in the static table with overriding bitset) and the processor should discard those packets. Note: theprocessor is connected to Port 5 via MII interface. Address
learning is disabled on the port in this state.

Blocking StatePort Setting

Software Action

Only packets to theprocessor are
forwarded. Learning is
disabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 1

The processor should not send any packets to the port(s) in thisstate. The processor should program the static MAC table withthe entries that it needs to receive (e.g., BPDU packets). The
overriding bit should also be set so that the switch will forward
those specific packets to the processor. Address learning is disabled on the port in this state.

Listening StatePort Setting

Software Action

Only packets to andfrom the processor are
forwarded. Learning is
disabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 1

The processor should program the static MAC table with theentries that it needs to receive (e.g. BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets
to the port(s) in this state, see Tail Tagging Mode section for
details. Address learning is disabled on the port in this state.

Learning StatePort Setting

Software Action

Only packets to andfrom the processor are
forwarded. Learning isenabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 0

The processor should program the static MAC table with theentries that it needs to receive (e.g., BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets
to the port(s) in this state, see Tail Tagging Mode section for
details. Address learning is enabled on the port in this state.

Forwarding StatePort Setting

Software Action

Packets are forwarded
and received normally.
Learning is enabled.

Transmit enable = 1,
Receive enable = 1,
Learning disable = 0

The processor should program the static MAC table with theentries that it needs to receive (e.g., BPDU packets). The overriding bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets
to the port(s) in this state, see Tail Tagging Mode section for
details. Address learning is enabled on the port in this state.

3.5.7

RAPID SPANNING TREE SUPPORTThere are three operational states—discarding, learning, and forwarding—assigned to each port for RSTP. Discarding
ports do not participate in the active topology and do not learn MAC addresses. Ports in the learning states learn MAC
addresses, but do not forward user traffic. Ports in the forwarding states fully participate in both data forwarding and
MAC learning. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP configuration BPDUs
with the exception of a type field set to “version 2” for RSTP, “version 0” for STP, and a flag field carrying additional information.

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KSZ8775CLXTABLE 3-14:

PORT SETTINGS AND SOFTWARE ACTIONS FOR RAPID SPANNING TREESTATESDisable StatePort Setting

Software Action

The port should not forward or
receive any packets. Learning is
disabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 1

The processor should not send any packets to theport. The switch may still send specific packets to theprocessor (packets that match some entries in thestatic table with overriding bit set) and the processor
should discard those packets. Note: the processor isconnected to Port 5 via MII interface. Address learning is disabled on the port in this state.

Blocking StatePort Setting

Software Action

Only packets to the processor are
forwarded. Learning is disabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 1

The processor should not send any packets to theport(s) in this state. The processor should program
the static MAC table with the entries that it needs toreceive (e.g., BPDU packets). The overriding bit
should also be set so that the switch will forward
those specific packets to the processor. Address
learning is disabled on the port in this state.

Listening StatePort Setting

Software Action

Only packets to and from the processor are forwarded. Learning is
disabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 1

The processor should program the static MAC tablewith the entries that it needs to receive (e.g. BPDU
packets). The overriding bit should be set so that theswitch will forward those specific packets to the processor. The processor may send packets to theport(s) in this state, see Tail Tagging Mode section
for details. Address learning is disabled on the port inthis state.

Learning StatePort Setting

Software Action

Only packets to and from the processor are forwarded. Learning isenabled.

Transmit enable = 0,
Receive enable = 0,
Learning disable = 0

The processor should program the static MAC tablewith the entries that it needs to receive (e.g., BPDU
packets). The overriding bit should be set so that theswitch will forward those specific packets to the processor. The processor may send packets to theport(s) in this state, see Tail Tagging Mode section
for details. Address learning is enabled on the port inthis state.

Forwarding StatePort Setting

Software Action

Transmit enable = 1,
Receive enable = 1,
Learning disable = 0

The processor should program the static MAC tablewith the entries that it needs to receive (e.g., BPDU
packets). The overriding bit should be set so that theswitch will forward those specific packets to the processor. The processor may send packets to theport(s) in this state, see Tail Tagging Mode section
for details. Address learning is enabled on the port inthis state.

Packets are forwarded andreceived normally. Learning isenabled.

3.5.8

TAIL TAGGING MODE

The tail tag is only seen and used by the Port 5 interface, which should be connected to a processor by the SW5-RGMII,
MII, or RMII interfaces. One byte tail tagging is used to indicate the source/destination port on Port 5. Only bits [3:0] areused for the destination in the tail tagging byte. Other bits are not used. The tail tag feature is enabled by setting Register
12 bit [1].

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KSZ8775CLX
FIGURE 3-10:

TAIL TAG FRAME FORMAT

8

BYTES

6

PREAMBLE

TABLE 3-15:

DA

6
SA

2
VPID

2
TCI

2
LENGTH

LLC

46-1500

1

4

DATA

TAIL
TAG

FCS

TAIL TAG RULES

Ingress to Port 5 (Host to KSZ8775CLX)
Bits [3:0]

Destination

0,0,0,0Reserved

0,0,0,1

Port 1 (direct forward to Port 1)

0,0,1,0Port 2 (direct forward to Port 2)

0,1,0,0Port 3 (direct forward to Port 3)

1,0,0,0Port 4 (direct forward to Port 4)

1,1,1,1

Port 1, 2, 3, and 4 (direct forward to Port 1, 2, 3,4)

Bits [7:4]–0,0,0,0Queue 0 is used at destination port

0,0,0,1

Queue 1 is used at destination port

0,0,1,0Queue 2 is used at destination port

0,0,1,1

Queue 3 is used at destination port

0, 1,x,x

Anyhow send packets to specified port in bits [3:0]1, x,x,x

Bits [6:0] will be ignored as normal (address look-up)

Egress from Port 5 (KSZ8775CLX to Host)
Bits [1:0]

Source0,0Port 1 (packets from Port 1)

0,1

Port 2 (packets from Port 2)

1,0

Port 3 (packets from Port 3)

1,1

Port 4 (packets from Port 4)

3.5.9

IGMP SUPPORTThere are two components involved with the support of the Internet Group Management Protocol (IGMP) in Layer 2.
The first part is IGMP snooping, the second part is this IGMP packet which is sent back to the subscribed port. Thosecomponents are described below.
• IGMP Snooping: The KSZ8775CLX traps IGMP packets and forwards them only to the processor (Port 5 SW5RGMII/MII/RMII). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAPIP packets) with IP version = 0x4 and protocol version number = 0x2. Set Register 5 bit [6] to ‘1’ to enable IGMP
snooping.
• IGMP Send Back to the Subscribed Port: Once the host responds to the received IGMP packet, the host knows
the original IGMP ingress port and sends the IGMP packet back to this port only. It does this in order to avoid this
IGMP packet being broadcast to all ports, which will downgrade the performance. With tail tag mode enabled, thehost will know the port from which that IGMP packet has been received via tail tag bits [1:0] and can send back the
response IGMP packet to this subscribed port by setting bits [3:0] in the tail tag. Enable tail tag mode by setting
Register 12 bit [1].

3.5.10

IPV6 MLD SNOOPING

The KSZ8775CLX traps IPv6 multicast listener discovery (MLD) packets and forwards them only to the processor (Port5). MLD snooping is controlled by Register 164 bit [2] (MLD snooping enable) and Register 164 bit [3] (MLD option).
With MLD snooping enabled, the KSZ8775CLX traps packets that meet all of the following conditions:• IPv6 multicast packets

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DS00002129C-page 39

KSZ8775CLX• Hop count limit = 1• IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58). If the MLD option bit is set to “1”, theKSZ8775CLX traps packets with the following additional condition:- IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or 60)
For MLD snooping, tail tag mode also needs to be enabled, so that the processor knows on which port the MLD packet
was received. This is achieved by setting Register 12 bit [1].

3.5.11PORT MIRRORING SUPPORTThe KSZ8775CLX supports port mirroring as described below:• “Receive Only” mirror on a port: All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be “RX sniff” and Port 5 is programmed to be the “sniffer port.” A packet, received on
Port 1, is destined to Port 4 after the internal look-up. The KSZ8775CLX will forward the packet to both Port 4 andPort 5. KSZ8775CLX can optionally forward “bad” received packets to Port 5.
• “Transmit Only” mirror on a port: All the packets transmitted on the port will be mirrored on the sniffer port. For
example, Port 1 is programmed to be “TX sniff,” and Port 5 is programmed to be the “sniffer port.” A packet,
received on any of the ports, is destined to Port 1 after the internal look-up. The KSZ8775CLX will forward thepacket to both Ports 1 and 5.
• “Receive and Transmit” mirror on two ports: All the packets received on Port A and transmitted on Port B will bemirrored on the sniffer port. To turn on the “AND” feature, set Register 5 bit [0] to ‘1’. For example, Port 1 is programmed to be “RX sniff,” Port 2 is programmed to be “TX sniff,” and Port 5 is programmed to be the “sniffer port.”
A packet, received on Port 1, is destined to Port 4 after the internal look-up. The KSZ8775CLX will forward thepacket to Port 4 only, because it does not meet the “AND” condition. A packet, received on Port 1, is destined to
Port 2 after the internal look-up. The KSZ8775CLX will forward the packet to both Port 2 and Port 5.
Multiple ports can be selected to be “RX sniff” or “TX sniff.” Any port can be selected to be the “sniffer port.” All theseper port features can be selected through the Port Control 1 Register.

3.5.12VLAN SUPPORTThe KSZ8775CLX supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8775CLX provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address lookup, with a maximum of 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port
VID is used for look-up when IEEE 802.1q is enabled by the global Register 5 Control 3 bit [7]. In the VLAN mode, thelook-up process starts from the VLAN table look-up to determine whether the VID is valid. If the VID is not valid, thepacket will then be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look-up by
the static MAC table or dynamic MAC table. FID+DA is used to determine the destination port. The following table
describes the different actions in different situations of DA and FID+DA in the static MAC table and dynamic MAC table
after the VLAN table finishes a look-up action. FID+SA is used for learning purposes. The following table also describes
learning in the dynamic MAC table when the VLAN table has completed a look-up in the static MAC table without a valid
entry.

TABLE 3-16:

FID+DA LOOK-UP IN THE VLAN MODE

DA Found in
Static MAC
Table?

Use FID Flag?

FID Match?

DA+FID Foundin Dynamic MAC
Table?

No

Don’t Care

Don’t CareNo

Broadcast to the membership ports
defined in the VLAN table bits [11:7].

No

Don’t Care

Don’t Care

Yes

Send to the destination port defined in
the dynamic MAC table bits [58:56].

Yes

0Don’t Care

Don’t Care

Send to the destination port(s)defined in the static MAC table bits
[52:48].

Yes

1

No

No

Broadcast to the membership ports
defined in the VLAN table bits [11:7].

Yes

1

No

Yes

Send to the destination port defined in
the dynamic MAC table bits [58:56].

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KSZ8775CLXTABLE 3-16:

FID+DA LOOK-UP IN THE VLAN MODE (CONTINUED)

DA Found in
Static MAC
Table?

Use FID Flag?

FID Match?

DA+FID Foundin Dynamic MAC
Table?

Yes

1

Yes

Don’t Care

TABLE 3-17:

ActionSend to the destination port(s)defined in the static MAC table bits
[52:48].

FID+SA LOOK-UP IN THE VLAN MODE

SA+FID Found in Dynamic MAC Table?

ActionNo

The SA+FID will be learned into the dynamic table.

Yes
Time stamp will be updated.
Advanced VLAN features are also supported in KSZ8775CLX, such as VLAN ingress filtering and discard non-PVID
defined in bits [6:5] of the Port Control 2 Register. These features can be controlled on a per port basis.

3.5.13RATE LIMITING SUPPORTThe KSZ8775CLX provides a fine resolution hardware rate limiting based on both bps (bits per second) and pps (packets per second).
For bps, the rate step is 64 kbps when the rate limit is less than 1 Mbps for 100 BT or 10 BT and 640 kbps for 1000. The
rate step is 1 Mbps when the rate limit is more than 1 Mbps for 100 BT or 10 BT and 10 Mbps for 1000.
For pps, the rate step is 128 pps (besides the 1st one which is 64 pps) when the rate limit is less than 1 Mbps for 100
BT or 10 BT and 1280 pps (except the 1st one of 640 pps) for 1000. The rate step is 1 Mbps when the rate limit is morethan 1.92 kpps for 100 BT or 10 BT 19.2 kpps for 1000.
The data rate selection table is below. Note that the pps limiting is bounded by bps rate for each pps setting; the mappingis shown in the second column of the table.

TABLE 3-18:

RATE SELECTION FOR RATE LIMIT

Item

bps Bound ofpps(Egress Only)

Code

Code

10 Mbps
pps

100 Mbps
bps

1000 Mbps

pps

bps

pps

bps

7’d0

7’d0

19.2 kpps

10 Mbps

192 kpps

100 Mbps

1.92 Mpps

1000 Mbps

7d’1 to
7d’10

7d’3,6, (8x)101.92 kpps *code

1 Mbps *code

1.92 kpps *code

1 Mbps *code

19.2 kpps *code

10 Mbps *code

7d’11 to7d’1007d’11 –
7d’100—

10 Mbps

1.92 kpps *code

1 Mbps *code

19.2 kpps *code

10 Mbps *code

7d’1017d’10264 pps64 kbps

64 pps64 kbps

640 pps

640 kbps

7d’1027d’104128 pps

128 kbps

128 pps

128 kbps

1280 pps

1280 kbps

7d’1037d’108256 pps

192 kbps

256 pps

192 kbps

2560 pps

1920 kbps

7d’1047d’112384 pps

256 kbps

384 pps

256 kbps

3840 pps

2560 kbps

7d’1057d’001512 pps

320 kbps

512 pps

320 kbps

5120 pps

3200 kbps

7d’1067d’001640 pps

384 kbps

640 pps

384 kbps

6400 pps

3840 kbps

7d’1077d’001768 pps

448 kbps

768 pps

448 kbps

7680 pps

4480 kbps

7d’1087d’002896 pps

512 kbps

896 pps

512 kbps

8960 pps

5120 kbps

7d’1097d’0021024 pps

576 kbps

1024 pps

576 kbps

10240 pps

5760 kbps

7d’1107d’0021152 pps

640 kbps

1152 pps

640 kbps

11520 pps

6400 kbps

7d’1117d’0021280 pps

704 kbps

1280 pps

704 kbps

12800 pps

7040 kbps

7d’1127d’0021408 pps

768 kbps

1408 pps

768 kbps

14080 pps

7680 kbps

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KSZ8775CLXTABLE 3-18:

RATE SELECTION FOR RATE LIMIT (CONTINUED)

Item

bps Bound ofpps(Egress Only)

Code

Code

pps

bps

pps

bps

pps

bps

7d’1137d’0031536 pps

832 kbps

1536 pps

832 kbps

15360 pps

8320 kbps

10 Mbps

100 Mbps

1000 Mbps

7d’1147d’003

1664 pps

896 kbps

1664 pps

896 kbps

16640 pps

8960 kbps

7d’1157d’0031792 pps

969 kbps

1792 pps

969 kbps

17920 pps

9690 kbps

The rate limit operates independently on the “receive side” and on the “transmit side” on a per port basis. For
10BASE-T, a rate setting above 10 Mbps means the rate is not limited.
On the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control
registers. On the transmit side, the data transmit rate for each queue at each port can be limited by setting up egress
rate control registers. For bps mode, the size of each frame has options to include minimum inter-frame gap (IFG) or
preamble byte, in addition to the data field (from packet DA to FCS).

3.5.13.1

Ingress Rate Limit

For ingress rate limiting, the KSZ8775CLX provides options to selectively choose frames from all types: multicast,broadcast, and flooded unicast frames via bits [3:2] of the Port Rate Limit Control Register. The KSZ8775CLX counts
the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds
the specified rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control isenabled by the Port Rate Limit Control Register bit [4]. The ingress rate limiting supports the port-based, IEEE 802.1p
and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by bits [4:3] of the Port Control 0 Register. The IEEE 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128 and 129.
In the ingress rate limit, set Register 135 Global Control 19 bit [3] to enable queue-based rate limiting if using two-queueor four-queue mode. All related ingress ports and egress ports should be split to two-queue or four-queue mode by thePort Control 9 and Control 0 Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bits [6:0] of the Port
Register Ingress Limit Control 1-4. The two-queue mode will use Q0-Q1 for priority 0-1 by bits [6:0] of the port ingress
limit control 1-2 Registers. The priority levels in the packets of the IEEE 802.1p and DiffServ can be programmed topriority 0-3 via the Register 128 and 129 for re-mapping.

3.5.13.2

Egress Rate Limit

For egress rate limiting, the leaky bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter-frame gap is stretched on a per frame basis to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified by the data rate selection table followed by the egress rate
limit control registers.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress, and may be slightly less than the specified egress rate. The egress rate limiting supports the port-based, IEEE
802.1p- and DiffServ-based priorities. The port-based priority is fixed priority 0-3 selection by bits [4:3] of the Port Control
0 Register. The IEEE 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128
and 129. In the egress rate limit, set Register 135 Global Control 19 bit [3] to enable queue-based rate limiting if using
two-queue or four-queue mode. All related ingress ports and egress ports should be split to two-queue or four-queue
mode by the Port Control 9 and Control 0 Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bits [6:0]of the Port Egress Limit Control 1-4 Register. The two-queue mode will use Q0-Q1 for priority 0-1 by bits [6:0] of the Port
Egress Rate Limit Control 1-2 Register. The priority levels in the packets of the IEEE 802.1p and DiffServ can be programmed to priority 0-3 by Register 128 and 129 for re-mapping.
When the egress rate is limited, just use one queue per port for the egress port rate limit. The priority packets will bebased upon the data rate selection table (see Table 3-18). If the egress rate limit uses more than one queue per port for
the egress port rate limit, then the highest priority packets will be based upon the data rate selection table for the rate
limit’s exact number. Other lower priority packet rates will be limited based upon an 8:4:2:1 (default) priority ratio, which
is based on the highest priority rate. The transmit queue priority ratio is programmable.
To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth.

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KSZ8775CLX
3.5.13.3

Transmit Queue Ratio Programming

In transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by
the Port Control 10, 11, 12, and 13 Registers. When the transmit rate exceeds the ratio limit in the transmit queue, thetransmit rate will be limited by the transmit queue 0-3 ratio of the Port Control 10, 11, 12, and 13 Registers. The highest
priority queue will not be limited. Other lower priority queues will be limited based on the transmit queue ratio.

3.5.14

VLAN AND ADDRESS FILTERINGTo prevent certain kinds of packets that could degrade the quality of the switch in applications such as voice over Internet
protocol (VoIP), the switch provides the mechanism to filter and map the packets with the following MAC addresses and
VLAN IDs.
• Self-address packets• Unknown unicast packets• Unknown multicast packets• Unknown VID packets• Unknown IP multicast packets
The packets sourced from switch itself can be filtered out by enabling self-address filtering via the Global Control 18
Register bit [6]. The self-address filtering will filter packets on the egress port, self MAC address is assigned in the Register 104-109 MAC Address Registers 0-5.
The unknown unicast packet filtering can be enabled by the Global Control Register 15 bit [5] and bits [4:0] specify the
port map for forwarding.
The unknown multicast packet filtering can be enabled by the Global Control Register 16 bit [5] and the forwarding port
map is specified in bits [4:0].
The unknown VID packet filtering can be enabled by Global Control Register 17 bit [5] with the forwarding port map
specified in bits [4:0].
The unknown IP multicast packet filtering can be enabled by Global Control Register 18 bit [5] with the forwarding port
map specified in bits [4:0].
The filters above are globally based.

3.5.15IEEE 802.1X PORT-BASED SECURITY

IEEE 802.1x is a port-based authentication protocol. EAPOL is the protocol normally used by the authentication process
as an uncontrolled port. By receiving and extracting special EAPOL frames, the microprocessor (CPU) can control
whether the ingress and egress ports should forward packets or not. If a user port wants service from another port
(authenticator), it must get approval from the authenticator. The KSZ8775CLX detects EAPOL frames by checking thedestination address of the frame. The destination addresses should be either a multicast address as defined in IEEE
802.1x (01-80-C2-00-00-03) or an address used in the programmable reserved multicast address domain with offset 00-03. Once EAPOL frames are detected, the frames are forwarded to the CPU so it can send the frames to the authenticator server. Eventually, the CPU determines whether the requester is qualified or not based on its MAC_Source
addresses and frames are either accepted or dropped.
When the KSZ8775CLX is configured as an authenticator, the ports of the switch must then be configured for authorization. In an authenticator-initiated port authorization, a client is powered-up or plugs into the port and the authenticator
port sends an extensible authentication protocol (EAP) PDU to the supplicant requesting the identification of the supplicant. At this point in the process, the port on the switch is connected from a physical standpoint; however, the IEEE
802.1x process has not authorized the port and no frames are passed from the port on the supplicant into the switching
fabric. If the PC attached to the switch did not understand the EAP PDU that it received from the switch, it is not be able
to send an ID and the port remains unauthorized. In this state, the port would never pass any user traffic and would be
as good as disabled. If the client PC is running the IEEE 802.1x EAP, it would respond to the request with its configured
ID. This could be a user name/password combination or a certificate.
After the switch, the authenticator receives the ID from the PC (the supplicant). The KSZ8775CLX then passes the ID
information to an authentication server (RADIUS server) that can verify the identification information. The RADIUS
server responds to the switch with either a success or failure message. If the response is successful, the port will beauthorized and user traffic will be allowed to pass through the port like any switch port connected to an access device.
If the response is a failure, the port will remain unauthorized and, therefore, unused. If there is no response from theserver, the port will also remain unauthorized and will not pass any traffic.

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KSZ8775CLX
3.5.15.1

Authentication Register and Programming Model

The port authentication control registers define the control of port-based authentication. The per-port authentication canbe programmed in these registers. The KSZ8775CLX provides three modes for implementing the IEEE 802.1x feature.
Each mode can be selected by setting the appropriate bits in the port authentication registers.
In pass mode (AUTHENTICATION_MODE = 00), forced-authorization is enabled and a port is always authorized that
does not require any messages from either the supplicant or the authentication server. This is typically the case whenconnecting to another switch, a router, or a server, and also when connecting to clients that do not support IEEE 802.1x.
When ACL is enabled, all the packets are passed if they miss ACL rules; otherwise, ACL actions apply.
The block mode (AUTHENTICATION_MODE = 01) is the standard port-based authentication mode. A port in this mode
sends EAP packets to the supplicant and will not become authorized unless it receives a positive response from theauthentication server. Before authentication, traffic is blocked to all of the incoming packets. Upon authentication, software will switch to pass mode to allow all the incoming packets. In this mode, the source address of incoming packets
is not checked, including the EAP address. The forwarding map of all the reserved multicast addresses needs to be
configured to allow forwarding before and after authentication in the look-up table. When ACL is enabled, packets except
ACL hits are blocked.
The third mode is trap mode (AUTHENTICATION_MODE = 11'b). In this mode, all the packets are sent to CPU port. If
ACL is enabled, the missed packets are forwarded to the CPU rather than dropped. All these per-port features can beselected through the Port Control 5 Register; bit [2] is used to enable ACL, bits [1:0] are for the modes selected.

3.5.16ACCESS CONTROL LIST (ACL) FILTERING

An ACL can be created to perform the protocol-independent Layer 2 MAC, Layer 3 IP, or Layer 4 TCP/UDP ACL filteringthat manages incoming Ethernet packets based on the ACL rule table. The feature allows the switch to filter customer
traffic based on the source MAC address in the Ethernet header, the IP address in the IP header, and the port number
and protocol in the TCP header. This function can be performed through the MAC table and ACL rule table. Besides
multicast filtering using entries in the static table, ACLs can be configured for all routed network protocols to filter the
packets of those protocols as the packets pass through the switch. Access lists can prevent certain traffic from entering
or exiting a network.

3.5.16.1

Access Control Lists

The KSZ8775CLX offers a rule-based access control list. The ACL rule table is an ordered list of access control entries.
Each entry specifies certain rules (a set of matching conditions and action rules) to permit or deny the packet access tothe switch fabric. The meaning of ‘permit’ or ‘deny’ depends on the context in which the ACL is used. When a packet isreceived on an interface, the switch compares the fields in the packet against any applied ACLs to verify that the packet
has the permissions required to be forwarded, based on the conditions specified in the lists.
The filter tests the packets against the ACL entries one-by-one. Usually, the first match determines whether the router
accepts or rejects packets. However, it is allowed to cascade the rules to form more robust and/or stringent requirements
for incoming packets. ACLs allow switch filter ingress traffic based on the source, destination MAC address and Ethernet
type in the Layer 2 header, the source and destination IP address in the Layer 3 header, and port number protocol in
the Layer 4 header of a packet.
Each list consists of three parts: the matching field, the action field, and the processing field. The matching field specifies
the rules that each packet matches against and the action field specifies the action taken if the test succeeds against
the rules. Figure 3-11 shows the format of ACL and a description of the individual fields.

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KSZ8775CLX
FIGURE 3-11:

3.5.16.2

ACL FORMAT

Matching Fields

MD [1:0]: MODE - there are three modes of operation defined in ACL.
MD = 00 disables the current rule list. No action will be taken.
MD = 01 is qualification rules for Layer 2 MAC header filtering.
MD = 10 is used for Layer 3 IP address filtering.
MD = 11 performs Layer 4 TCP port number/protocol filtering.
ENB [1:0]: ENABLE – Enables different rules in the current list.
When MD = 01,
If ENB = 00, the 11 bits of the aggregated bit field from PM, P, RPE, RP, MM in the action field specify a count value forpackets matching the MAC address and type in the matching fields.
The count unit is defined in MSB of the forward bit field; while = 0, µsec will be used and while = 1, msec will be used.
The second MSB of the forwarded bit determines the algorithm used to generate an interrupt when the counter terminates. When = 0, an 11-bit counter is loaded with the count value from the ACL and starts counting down every unit oftime. An interrupt is generated when it expires (i.e., the next qualified packet has not been received within the period
specified by the value). When = 1, the counter is incremented on every matched packet received and an interrupt isgenerated when the terminal count reaches the count value in the ACL. The count resets thereafter.
If ENB = 01, the MAC address bit field is used for testing;
If ENB = 10, the MAC type bit field is used for testing;
If ENB = 11, both the MAC address and type are tested against these bit fields in the list.
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KSZ8775CLX
If ENB = 01, the IP address and mask or IP protocol is enabled to be tested accordingly.
If ENB = 10, the source and destination addresses are compared. The drop/forward decision is based on the EQ bit
setting.
When MD = 11,
If ENB = 00, protocol comparison is enabled.
If ENB = 01, TCP address comparison is selected.
If ENB = 10, UDP address comparison is selected.
If ENB = 11, the sequence number of the TCP is compared.
S/D: Source or destination selection
S/D = 0, the destination address/port is compared;
S/D = 1, the source is chosen.
E/Q: comparison algorithm:
E/Q = 0, match if they are not equal;
E/Q = 1, match if they are equal.
MAC Address [47:0]: MAC source or destination address
TYPE [15:0]: MAC Ether TypeIP Address [31:0]: IP source or destination address
IP Mask [31:0]: IP address mask for group address filtering
MAX Port [15:0], MIN Port [15:0] (Sequence Number [31:0]): The range of TCP port number or sequence number
matching.
PC [1:0]: Port comparison
PC = 00, the comparison is disabled.
PC = 01, matches either one of MAX or MIN.
PC = 10, match if the port number is in the range of MAX to MIN.
PC = 11, match if the port number is out of the range.
PRO [7:0]: IP protocol to be matched
FME: Flag match enable
FME = 0, disable TCP FLAG matching.
FME = 1, enable TCP FLAG matching.
FLAG [5:0]: TCP flag to be matched.

3.5.16.3

Action Field

PM [1:0]: Priority mode
PM = 00, no priority is selected, the priority is determined by the QoS/classification is used.
PM = 01, the priority in P bit field is used if it is greater than QoS result.
PM = 10, the priority in P bit field is used if it is smaller than QoS result.
PM = 11, the P bit field will replace the priority determined by QoS.
P [2:0]: Priority.
RPE: Remark priority enable
RPE = 0, no remarking is necessary.
RPE = 1, the VLAN priority bits in the tagged packets are replaced by RP bit field in the list.
RP [2:0]: Remarked priority.
MM [1:0]: Map mode
MM = 00, no forwarding remapping is necessary.
MM = 01, the forwarding map in FORWARD is OR’ed with the forwarding map from the look-up table.

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KSZ8775CLX
MM = 10, the forwarding map in FORWARD is AND’ed with the forwarding map from the look-up table.
MM = 11, the forwarding map in FORWARD replaces the Forwarding map from the look-up table.
FORWARD Bits [4:0]: Forwarding port(s) - Each bit indicates the forwarding decision of one port.

3.5.16.4

Processing Field

FRN Bits [3:0]: First rule number – Assigns which entry with its Action Field in 16 entries is used in the rule set.
For the rule set, see description below.
RULESET Bits [15:0]: Rule set - Group of rules to be qualified, there are 16 entries rule can be assigned to a rule set
per port by the two rule set registers. The rule table allows the rules to be cascaded. There are 16 entries in the RTB.
Each entry can be a rule on its own, or can be cascaded with other entries to form a rule set. The test result of incoming
packets against rule set will be the AND’ed result of all the test result of incoming packets against the rules included inthis rule set. The action of the rule set will be the action of the first rule specified in FRN field. The rule with higher priority
will have lower index number. Or rule 0 is the highest priority rule and rule 15 is the lowest priority. ACL rule table entry
is disabled when mode bits are set to 2’b00.
A rule set is used to select the match results of different rules against incoming packets. These selected match results
will be AND’ed to determine whether the frame matches or not. The conditions of different rule sets having the sameaction will be OR’ed for comparison with frame fields, and the CPU will program the same action to those rule sets thatare to be OR’ed together. For matched rule sets, different rule sets having different actions will be arbitrated or chosen
based upon the first rule number (FRN) of each rule set. The rule table will be set up with the high priority rule at the topof the table or with the smaller index. Regardless whether the matched rule sets have the same or different action, thehardware will always compare the first rule number of different rule sets to determine the final rule set and action.

3.5.16.5

Denial of Service (DoS) Attack Prevention via ACL

The ACL can provide certain detection/protection of the following DoS attack types based on rule setting, which can be
programmed to drop or not to drop each type of DoS packet respectively.
Example 1: When MD = ‘10’, ENABLE = ‘10’, setting the EQ bit to ‘1’ can determine the drop or forward packets withidentical source and destination IP addresses in IPv4/IPv6.
Example 2: When MD = ‘11’, ENABLE = ‘01’/’10’, setting the EQ bit to ‘1’ can determine the drop or forward packets withidentical source and destination TCP/UDP ports in IPv4/IPv6.
Example 3: When MD = ‘11’, ENABLE = ‘11’, Sequence Number = ‘0’, FME = ‘1’, FMSK = ‘00101001’, FLAG =‘xx1x1xx1’, Setting the EQ bit to ‘1’ will drop/forward the all packets with a TCP sequence number equal to ‘0’, and flag
bit URG = ‘1’, PSH = ‘1’, and FIN = ‘1’.
Example 4: When MD = ‘11’, ENABLE = ‘01’, MAX Port = ‘1024’, MIN Port = ‘0’, FME = ‘1’, FMSK = ‘00010010’, FLAG= ‘xxx0xx1x’, Setting the EQ bit to ‘1’ will drop/forward the all packets with a TCP port number ≤1024, and flag bit URB= ‘0’, SYN = ‘1’.
ACL-related registers list as the Register 110 (0x6E), the Register 111 (0x6F), and the ACL rule tables.

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KSZ8775CLX
4.0

DEVICE REGISTERS

The KSZ8775CLX device has a rich set of registers available to manage the functionality of the device. Access to theseregisters is via the MIIM or SPI interfaces. The figure below provides a global picture of accessibility via the various interfaces and addressing ranges from the perspective of each interface.

FIGURE 4-1:

INTERFACE AND REGISTER MAPPING• The registers within the linear 0x00-0xFF address space are all accessible via the SPI interface by a CPU
attached to that bus. The mapping of the various functions within that linear address space is summarized inTable 4-1.

TABLE 4-1:
Register
Locations
0x00 – 0xFF

0x6E – 0x6F

0x70 – 0x78

0xA0

MAPPING OF FUNCTIONAL AREAS WITHIN THE ADDRESS SPACE
Device Area

Description

Switch Control
Registers that control the overall functionality of the switch, MAC, and PHYs.
and Configuration

Indirect Control
Registers

Registers used to indirectly address and access distinct areas within the device.
Management information base (MIB) counters
Static MAC address table
Dynamic MAC address table
VLAN table
PME indirect register
ACL indirect register
EEE indirect Register

Indirect Access
Registers

Registers used to indirectly address and access four distinct areas within thedevice.
Management Information Base (MIB) counters
Static MAC address table
Dynamic MAC address table
VLAN table

This indirect byte register is used to access:Indirect Byte
PME indirect registers
Access Registers ACL indirect registers
EEE indirect registers

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KSZ8775CLXTABLE 4-1:

MAPPING OF FUNCTIONAL AREAS WITHIN THE ADDRESS SPACE (CONTINUED)

0x17 – 0x4F

TABLE 4-2:

PHY1 to PHY4
MIIM Registers
Mapping to Those The same PHY registers as specified in IEEE 802.3.
Port Registers’
Address Ranges

DIRECT REGISTER DESCRIPTION
Address

Contents

0x00-0x01

Family ID, Chip ID, Revision ID, and start switch Registers

0x02-0x0D

Global Control Registers 0 – 11

0x0E-0x0F

Global Power Down Management Control Registers

0x10-0x14

Port 1 Control Registers 0 – 4

0x15

Port 1 Authentication Control Register0x16-0x18

Port 1 Reserved (Factory Test Registers)

0x19-0x1F

Port 1 Control/Status Registers

0x20-0x24

Port 2 Control Registers 0 – 4

0x25

Port 2 Authentication Control Register0x26-0x28

Port 2 Reserved (Factory Test Registers)

0x29-0x2F

Port 2 Control/Status Registers

0x30-0x34

Port 3 Control Registers 0 – 4

0x35

Port 3 Authentication Control Register0x36-0x38

Port 3 Reserved (Factory Test Registers)

0x39-0x3F

Port 3 Control/Status Registers

0x40-0x44

Port 4 Control Registers 0 – 4

0x45

Port 4 Authentication Control Register0x46-0x48

Port 4 Reserved (Factory Test Registers)

0x49-0x4F

Port 4 Control/Status Registers

0x50-0x54

Port 5 Control Registers 0 – 4

0x56-0x58

Port 5 Reserved (Factory Test Registers)

0x59-0x5F

Port 5 Control/Status Registers

0x60-0x67

Reserved (Factory Testing Registers)

0x68-0x6D

MAC Address Registers

0x6E-0x6F

Indirect Access Control Registers

0x70-0x78

Indirect Data Registers

0x79-0x7B

Reserved (Factory Testing Registers)

0x7C-0x7D

Global Interrupt and Mask Registers

0x7E-0x7F

ACL Interrupt Status and Control Registers

0x80-0x87

Global Control Registers 12 – 19

0x88

Switch Self Test Control Register0x89-0x8F

QM Global Control Registers

0x90-0x9F

Global ToS Priority Control Registers 0 - 15

0xA0

Global Indirect Byte Register

0xA0-0xAF

Reserved (Factory Testing Registers)

0xB0-0xBE

Port 1 Control Registers

0xBF

Reserved (Factory Testing Register): Transmit Queue Remap Base Register

0xC0-0xCE

Port 2 Control Registers

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DS00002129C-page 49

KSZ8775CLXTABLE 4-2:

DIRECT REGISTER DESCRIPTION (CONTINUED)
Address

Contents

0xCF

Reserved (Factory Testing Register)

0xD0-0xDE

Port 3 Control Registers

0xDF

Reserved (Factory Testing Register)

0xE0-0xEE

Port 4 Control Registers

0xEF

Reserved (Factory Testing Register)

0xF0-0xFE

Port 5 Control Registers

0xFF

Reserved (Factory Testing Register)DS00002129C-page 50

 2015 Microchip Technology Inc.

KSZ8775CLX
4.1

Global Registers

TABLE 4-3:

GLOBAL REGISTERS

AddressName

Description

Mode

Default

Chip family.

RO

0x87

0x7 for KSZ8775

RO

0x7

Register 0 (0x00): Chip ID0
7-0

Family ID

Register 1 (0x01): Chip ID1/Start Switch
7-4

Chip ID

3-1

Revision ID

RO

0x0

1 = Start the switch function of the chip
0 = Stop the switch function of the chipR/W

1

New back-off enable

New back-off algorithm designed for UNH
1 = Enable
0 = Disable

R/W

0

Global soft reset enable

Global Software Reset
1 = Enable reset of all FSM and data path(not configuration)
0 = Disable reset
Note: This reset will stop receiving packets if they are in traffic. All registers keep
their configuration values.

R/W

0

Flush dynamic MAC
table

Flush the entire dynamic MAC table for
RSTP. This bit is self-clearing (SC).
1 = Trigger the flush dynamic MAC table
operation.
0 = Normal operation
Note: All the entries associated with a portthat has its learning capability turned off(learning disable) will be flushed. If you
want to flush the entire table, the learning
capability of all ports must be turned off.

R/W
(SC)

0

4

Flush static MAC table

Flush the matched entries in static MAC
table for RSTP
1 = Trigger the flush static MAC table
operation.
0 = Normal operation
Note: The matched entry is defined as theentry in the Forwarding Ports field that
contains a single port and MAC address
with unicast. This port, in turn, has its
learning capability turned off (learning disable). Per port, multiple entries can bequalified as matched entries.

R/W
(SC)

0

3

Reserved

N/A Don’t change.

RO

1

2

Reserved

N/A Don’t change.

RO

1

UNH Mode

1 = The switch will drop packets with
0x8808 in the T/L filed or DA = 01-80-C200-00-01.
0 = The switch will drop packets qualified
as flow control packets.

R/W

0

0

Start Switch

Register 2 (0x02): Global Control 0
7

6

5

1

 2015 Microchip Technology Inc.

DS00002129C-page 51

KSZ8775CLXTABLE 4-3:

GLOBAL REGISTERS (CONTINUED)

Address0

Name

Link Change Age

Description

Mode

Default

1 = Changing from link to no link will cause
the address table to age faster (<800 µs).
After an age cycle is complete, the age
logic will return to normal (300 ±75 seconds).
Note: If any port is unplugged, alladdresses will be automatically aged out.

R/W

0

N/A Don’t change.

RO

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

1

Register 3 (0x03): Global Control 1
7

Reserved

6

2kb packet support

5

IEEE 802.3x Transmit
Flow Control Disable

1 = Enable 2 kb packet support.
0 = Disable 2 kb packet support.
0 = Enables transmit flow control basedon AN result.
1 = Will not enable transmit flow control
regardless of the AN result.
0 = Enables receive flow control basedon AN result.

4IEEE 802.3x Receive
Flow Control Disable

1 = Will not enable receive flow control
regardless of the AN result.
Note: Bit [5] and bit [4] default values arecontrolled by the same pin, but they canbe programmed independently.
1 = Check frame length field in the IEEE
packets. If the actual length does notmatch, the packet will be dropped (for L/
T <1500).

3

Frame Length Field
Check

2

Aging Enable1

Fast Aging Enable

1 = Turn on Fast Aging (800 µs).

R/W

0

0

Aggressive Back-Off
Enable1 = Enable more aggressive back-off
algorithm in half-duplex mode toenhance performance. This is not in theIEEE standard.

R/W

0

Unicast Port VLAN Mismatch Discard

This feature is used for port VLAN
(described in Port Control 1 Register).
1 = All packets can cross VLAN boundary.
0 = Unicast packets (excluding unknown/
multicast/broadcast) can cross VLAN
boundary.
Note: When mirroring is enabled, thesingle-destination packets will be dropped
if it’s mirrored to another port.

R/W

1

Multicast Storm
Protection Disable

1 = Broadcast storm protection does notinclude multicast packets. Only DA =FFFFFFFFFFFF packets will be
regulated.
0 = Broadcast storm protection includes
DA = FFFFFFFFFFFF and DA[40] = 1
packet.

R/W

1

1 = Enable aging function in the chip.
0 = Disable aging function.

Register 4 (0x04): Global Control 276DS00002129C-page 52

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-3:
Address

GLOBAL REGISTERS (CONTINUED)
Description

Mode

Default

Back Pressure Mode

1 = Carrier sense-based back pressure isselected.
0 = Collision-based back pressure isselected.

R/W

1

4

Flow Control and Back
Pressure Fair Mode

1 = Fair mode is selected. In this mode, if
a flow control port and a non-flow control
port talk to the same destination port, thenpackets from the non-flow control port
may be dropped. This is to prevent theflow control port from being controlled foran extended period of time.
0 = In this mode, if a flow control port anda non-flow control port talk to the same
destination port, the flow control port will
be flow controlled. This may not be fair tothe flow control port.

R/W

1

3

No Excessive CollisionDrop

1 = The switch will not drop packets when
16 or more collisions occur.
0 = The switch will drop packets when 16
or more collisions occur.

R/W

0

2

Reserved

N/A Don’t change.

RO

0

1

Legal Maximum Packet
Size Check Disable

1 = Enables acceptance of packet sizes
up to 1536 bytes (inclusive).
0 = 1522 bytes for tagged packets (notincluding packets with STPID from CPU to
Ports 1-4), 1518 bytes for untagged packets. Any packets larger than the specified
value will be dropped.

R/W

0

0

Reserved

N/A

RO

0

7

802.1q VLAN Enable

1 = 802.1q VLAN mode is turned on.
VLAN table needs to be set up before theoperation.
0 = 802.1q VLAN is disabled.

R/W

0

6

1 = IGMP snoop enabled. All the IGMP
IGMP Snoop Enable on packets will be forwarded to the processor
Switch Port 5 SW5via Switch Port 5 RGMII/MII/RMII interRGMII/MII/RMII Interface face.
0 = IGMP snoop disabled.

R/W

0

5-1

Reserved

N/A Don’t change.

RO

00000

Sniff Mode Select

1 = Enables RX and TX sniff (both source
port and destination port need to match).
0 = Enables RX or TX sniff (either source
port or destination port need to match).
Note: Default is used to implement RXonly sniff.

R/W

0

1 = Enable half-duplex back pressure on
the switch MII/RMII interface.
0 = Disable back pressure on the switch
MII interface.

R/W

0

5

Name

Register 5 (0x05): Global Control 30Register 6 (0x06): Global Control 4
7

Switch SW5-MII/RMII
Back Pressure Enable 2015 Microchip Technology Inc.

DS00002129C-page 53

KSZ8775CLXTABLE 4-3:

GLOBAL REGISTERS (CONTINUED)

Address

Description

Mode

Default

6

Switch SW5-MII/RMII
Half-Duplex Mode

1 = Enable MII/RMII interface half-duplex
mode.
0 = Enable MII/RMII interface full-duplex
mode.

R/W

0

5

Switch SW5-MII/RMII
Flow Control Enable

1 = Enable full-duplex flow control on theswitch MII/RMII interface.
0 = Disable full-duplex flow control on theswitch MII/RMII interface.

R/W

0

4

Switch SW5-MII/RMII
Speed

1 = The switch SW5-MII/RMII is in 10
Mbps mode.
0 = The switch SW5-MII/RMII is in 100
Mbps mode.

R/W

0

3

Null VID Replacement

1 = Replace null VID with port VID (12bits).
0 = No replacement for null VID.

R/W

0Broadcast Storm
Protection Rate Bit[10:8]

This register, along with the next register,
determines how many 64-byte blocks ofpacket data are allowed on an input port ina preset period. The period is 50 ms for
100BT or 500 ms for 10BT. The default is
1%.

R/W

000

This register, along with the previous register, determines how many 64-byte
blocks of packet data are allowed on an
input port in a preset period. The period is
50ms for 100BT or 500 ms for 10BT. The
default is 1%.
Note: 148,800 frames/sec × 50ms/interval
× 1% = 74 frames/interval (approx.) =
0x4A

R/W

0x4A

R/W (SC)

0

2-0

Name

Register 7 (0x07): Global Control 5

7-0

Broadcast Storm Protection Rate Bits[7:0]Register 8 (0x08): Global Control 6 MIB Control
7

Flush Counter

1 = All the MIB counters of enabled port(s)will be reset to 0. This bit is self-cleared
after the operation finishes.
0 = No reset of the MIB counter.

6

Freeze Counter

1 = Enabled port(s) will stop counting.
0 = Enabled port(s) will not stop counting.

R/W

0

5

Reserved

N/A Don’t change.

RO

0Control Enable

1 = Enable flush and freeze for each port.
Bit [4] is for Port 5 Flush + Freeze.
Bit [3] is for Port 4 Flush + Freeze.
Bit [2] is for Port 3 Flush + Freeze.
Bit [1] is for Port 2 Flush + Freeze.
Bit [0] is for Port 1 Flush + Freeze.
0 = Disable flush and freeze.

R/W

0

N/A Don’t change.

RO

0x40

N/A Don’t change.

RO

0x00

N/A Don’t change.

RO

0

4-0

Register 9 (0x09): Global Control 7
7-0

Factory Testing

Register 10 (0x0A): Global Control 8
7-0

Factory Testing

Register 11 (0x0B): Global Control 9
7

Reserved

DS00002129C-page 54

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-3:
Address

6

GLOBAL REGISTERS (CONTINUED)
Name

Description

Mode

Default

Port 5 SW5-RMII Reference Clock Edge SelectSelect the data sampling edge of theSW5-RMII reference clock:
1 = Data sampling on the negative edge of
REFCLK.
0 = Data sampling on the positive edge of
REFCLK (default).

R/W

0

R/W

00

Programmable LED output to indicate theport’s activity/status using two bits of thecontrol register. LED is ON (active) when
the output is LOW; the LED is OFF (inactive) when the output is HIGH.
Control

00

01

10

11

LEDx_1

Speed

ACT

DuplexDuplexLEDx_0Link/ACT

Link

Link/ACT

Link

Bits [5:4]

5-4

LED Mode

LINK = LED ON;
ACT = LED Blink;
LINK/ACT = LED ON/Blink.
Speed = LED ON (100BT);
LED OFF (10BT);
LED Blink (1000BT reserved).
Duplex = LED ON (full-duplex);
LED OFF (half-duplex).
3

Reserved

N/A Don’t change.

RO

0

2

Reserved

N/A Don’t change.

RO

0

REFCLKO Enable

1 = Enable REFCLKO pin clock output
0 = Disable REFCLKO pin clock output.
Strap-in option: LED2_0
PU = REFCLK_O (25 MHz) is enabled.
(default)
PD = REFCLK_O is disabled
Note: This is an additional clock and cansave an oscillator if the system needs thisclock source. If the system doesn’t needthis clock source, it should be disabled.

R/W

0

SPI Read Sampling
Clock Edge SelectSelect the SPI clock edge for sampling
SPI read data.
1 = Trigger on the rising edge of SPI clock(for higher speed SPI).
0 = Trigger on the falling edge of SPI
clock.

R/W

0

Reserved

N/A Don’t change

RO

00

PLL Power-Down

PLL Power-Down Enable:
1 = Enable
0 = Disable
Note: It occurs in the energy detect(EDPD) mode.

R/W

0

1

0

Register 12 (0x0C): Global Control 10
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DS00002129C-page 55

KSZ8775CLXTABLE 4-3:

GLOBAL REGISTERS (CONTINUED)

Address

Name

Power Management
Mode Select

4–3

Reserved
2-0
Register 13 (0x0D): Global Control 11
7-0

Factory Testing

Description

Mode

Default

Power Management Mode:
00 = Normal mode (D0)
01 = Energy Detection mode (D2)
10 = Soft Power-Down mode (D3)
11 = Reserved
Note: RC means Read Clear.

R/W
(RC)

00

N/A Don’t change.

RO

000

N/A Don’t change

RO

00000000

Register 14 (0x0E): Power-Down Management Control 1
7-6

Reserved

N/A Don’t change

RO

00

PLL Power-Down

PLL Power-Down Enable:
1 = Enable
0 = Disable
Note: It occurs in the energy detect(EDPD) mode.

R/W

0

4–3

Power Management
Mode SelectPower Management Mode:
00 = Normal mode (D0)
01 = Energy Detection mode (D2)
10 = Soft Power-Down mode (D3)
11 = Reserved
Note: RC means Read Clear.

R/W
(RC)

00

2-0

Reserved

N/A Don’t change.

RO

000

R/W

01010000

5Register 15 (0x0F): Power-Down Management Control 2

7-0

4.2

Go_Sleep_Time [7:0]

When the energy detect mode is enabled,
this value is used to control the minimum
period that the no energy event has to be
detected consecutively before the device
enters the low power state. The unit is 20
ms. The default of go_sleep time is 1.6
seconds (80 Dec × 20 ms).

Port Registers

The following registers are used to enable features that are assigned on a per port basis. The register bit assignments
are the same for all ports, but the address for each port is different, as indicated.

TABLE 4-4:

PORT REGISTERS

AddressName

Description

Mode

Default

Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0
Register 64 (0x40): Port 4 Control 0
Register 80 (0x50): Port 5 Control 0
7

Broadcast Storm Protection Enable

1 = Enable broadcast storm protection
for ingress packets on the Port.
0 = Disable broadcast storm protection.

R/W

0

6

1 = Enable DiffServ priority classification
DiffServ Priority Classifor ingress packets on port.
fication Enable
0 = Disable DiffServ function.

R/W

0DS00002129C-page 56

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-4:
Address

5

4–3

2

1

0

PORT REGISTERS (CONTINUED)
Name

Mode

Default

1 = Enable 802.1p priority classification
802.1p Priority Classifi- for ingress packets on port.
cation Enable
0 = Disable 802.1p priority classification
for ingress packets on port.

R/W

0

Port-Based Priority
Classification Enable

00 = Ingress packets on port will be classified as priority 0 queue if Diffserv or
802.1p classification is not enabled or
fails to classify.
01 = Ingress packets on port will beclassified as priority 1 queue if Diffserv
or 802.1p classification is not enabled or
fails to classify.
10 = Ingress packets on port will beclassified as priority 2 queue if Diffserv
or 802.1p classification is not enabled or
fails to classify.
11 = Ingress packets on port will be classified as priority 3 queue if Diffserv or
802.1p classification is not enabled or
fails to classify.
Note: DiffServ, 802.1p, and port priority
can be enabled at the same time. The
OR’ed result of 802.1p and DSCP overwrites the port priority.

R/W

00

Tag Insertion

1 = When packets are output on theport, the switch will add 802.1q tags topackets without 802.1q tags when
received. The switch will not add tags topackets already tagged. The tag
inserted is the ingress port’s “Port VID.”
0 = Disable tag insertion.

R/W

0

Tag Removal

1 = When packets are output on theport, the switch will remove 802.1q tags
from packets with 802.1q tags when
received. The switch will not modify
packets received without tags.
0 = Disable tag removal.

R/W

0

Two Queues Split
EnableThis bit [0] in Registers16/32/48/64/80
should be in combination with Registers177/193/209/225/241 bit [1] for Ports
1-5. This will select the split of 1, 2, and
4 queues:
For Port 1, Register 177 bit [1], Register
16 bit [0]:11 = Reserved
10 = The port output queue is split into
four priority queues or if map 802.1p topriority 0-3 mode.
01 = The port output queue is split into
two priority queues or if map 802.1p topriority 0-3 mode.
00 = Single output queue on the port.
There is no priority differentiation eventhough packets are classified into highor low priority.

R/W

0 2015 Microchip Technology Inc.

Description

DS00002129C-page 57

KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

Sniffer Port

1 = Port is designated as sniffer port andwill transmit packets that are monitored.
0 = Port is a normal port.

R/W

0

Receive Sniff

1 = All the packets received on the port
will be marked as monitored packets
and forwarded to the designated sniffer
port.
0 = No packets received are monitored.

R/W

0

Transmit Sniff

1 = All the packets transmitted on theport will be marked as monitored packets and forwarded to the designatedsniffer port.
0 = No transmitted packets are monitored.

R/W

0Port VLAN
Membership

Defines the port’s “Port VLAN” membership.
Bit [4] stands for Port 5
Bit [3] stands for Port 4
Bit [2] stands for Port 3
Bit [1] stands for Port 2
Bit [0] stands for Port 1
The port can only communicate within
the membership. A ‘1’ includes a port in
the membership, a ‘0’ excludes a port in
the membership.

R/W

0x1f

1 = If packet‘s user priority field isgreater than the user priority field in the
port’s default tag register, this replaces
the packet’s user priority field with theuser priority field in the default tag ofPort Control 3 Register.
0 = Does not replace packet’s priority
field with the port default tag priority fieldof the Port Control 3 Register bits [7:5].

R/W

0

R/W

0

R/W

0

Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
Register 65 (0x41): Port 4 Control 1
Register 81 (0x51): Port 5 Control 1
7

6

5

4-0

Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Register 66 (0x42): Port 4 Control 2
Register 82 (0x52): Port 5 Control 2

7

User Priority Ceiling6

1 = The switch will discard packets
whose VID port membership in VLAN
Ingress VLAN Filtering. table bits[11:7] does not include theingress port.
0 = No ingress VLAN filtering.

5

Discard Non-PVID
Packets

DS00002129C-page 58

1 = The switch will discard packets
whose VID does not match ingress port
default VID.
0 = No packets will be discarded.

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-4:
Address

4

3

2

1

0

PORT REGISTERS (CONTINUED)
Name

Description

Mode

Default

Force Flow Control

1 = Enables RX and TX flow control on
the port, regardless of the AN result.
0 = Flow control is enabled based on the
AN result (default)
Note: This bit is for Port 1, Port 2, Port3, and Port 4 SW4-RMII.

R/W

0Back Pressure Enable

1 = Enable port half-duplex back pressure.
0 = Disable port half-duplex back pressure.
Note: This bit is for Port 1, Port 2, Port3, and Port 4 SW4-RMII.

R/W

0

Transmit Enable

1 = Enable packet transmission on theport.
0 = Disable packet transmission on the
port.
Note: Bits [2:0] are used for spanning
tree support. See Spanning Tree Support section for more information.

R/W

1

Receive Enable

1 = Enable packet reception on the port.
0 = Disable packet reception on the port.
Note: Bits [2:0] are used for spanning
tree support. See Spanning Tree Support section for more information.

R/W

1

Learning Enable

1 = Disable switch address learning
capability.
0 = Enable switch address learning.
Note: Bits [2:0] are used for spanning
tree support. See Spanning Tree Support section for more information.

R/W

0Port’s default tag, containing:
7-5: User priority bits
4: CFI bit
3-0: VID[11:8]

R/W

0

Default Port 1’s tag, containing:
7-0: VID[7:0]Note: Registers 19 and 20 (and thosecorresponding to other ports) serve two
purposes: (1) Associated with theingress untagged packets, and used foregress tagging; (2) Default VID for the
ingress untagged or null-VID-tagged
packets and used for address look up.

R/W

1

Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Register 67 (0x43): Port 4 Control 3
Register 83 (0x53): Port 5 Control 3
7-0

Default Tag [15:8]

Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Register 68 (0x44): Port 4 Control 4
Register 84 (0x54): Port 5 Control 4

7-0

Default Tag [7:0] 2015 Microchip Technology Inc.

DS00002129C-page 59

KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
Register 69 (0x45): Port 4 Control 5
Register 85 (0x55): Port 5 Control 5
7-3

Reserved

N/A Don’t change

RO

00000

2

ACL Enable

1 = Enable ACL
0 = Disable ACL

R/W

0

AUTHENTICATION_MODE

These bits control port-based authentication:
00, 10 = Authentication disable, all trafficis allowed (forced-authorized), if ACL isenabled, pass all traffic if ACL missed
01 = Authentication enabled, all traffic isblocked, if ACL is enabled, traffic isblocked if ACL missed
11 = Authentication enabled, all traffic istrapped to CPU port, if ACL is enabled,
traffic is trapped to Port 5 CPU port only
if ACL missed.

R/W

00

R/W

0 - Port 4
1 - Port 5

1-0

Register 22 (0x16): Reserved
Register 38 (0x26): Reserved
Register 54 (0x36): Reserved
Register 70 (0x46): Port 4 Interface Control 6
Register 86 (0x56): Port 5 Interface Control 6

7

RMII_CLK_SEL

DS00002129C-page 60

Port 4 and Port 5 RMII Mode Select
1 = RMII uses internal clock (clockmode)
0 = RMII uses external clock (normal
mode)
Strap-in option for Port 5: LED2_1
PU = Clock mode in SW5-RMII to provide 50MHz reference clock from RXC5
(default).
PD = Normal mode in SW5-RMII toreceive 50 MHz reference clock from
TXC5/REFCLKI5.
Note: This pin has an internal pull-up.
Strap-in option for Port 4: RXD4_0
PU = Clock mode in SW4-RMII, using
25 MHz OSC clock and provide 50MHzRMII clock from pin RXC4.
PD = Normal mode in SW4-RMII, theTXC4/REFCLKI4 pin on the port 4 SW4RMII will receive an external 50 MHz
clock (default).
Note: This pin has an internal pulldown.

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-4:
Address

PORT REGISTERS (CONTINUED)
Name

Description

Mode

Default

R/W

1

6

Is_1Gbps

1 = 1 Gbps is chosen for Port 5 in RGMII
mode.
0 = 10/100Mbps is chosen for Port 5 in
RGMII mode.
Strap-in option: LED1_0
PU = 1 Gbps in SW5-RGMII mode
(default)
PD = 10/100 Mbps in SW5-RGMII mode
Note: This pin has an internal pull-up.
Use bit [4] of the Register 6, Global Control 4 to set for 10 or 100 speed in 10/
100Mbps mode. This bit is reserved forPort 4.

5

Reserved

N/A Don’t change

RO

1

RGMII Internal Delay(ID) Ingress Enable

Enable Ingress RGMII ID mode
1 = Ingress RGMII-ID enabled. Aninternal delay is added to ingress
clock input.
0 = No delay is added, only clock to data
skew applied.
Note: If RGMII connection partner transmit data to clock skew is in standard
spec ±0.5 ns without delay inserted on
PCB, then set bit [4] =’1’ will enable aningress delay to meet the input skew
min 1ns to max 2.6 ns requirement (theclock trace should be equal length withdata traces in PCB layout).

R/W

0

RGMII Internal Delay(ID) Egress Enable

Enable Egress RGMII ID mode
1 = Egress RGMII-ID enabled. Aninternal delay is added to egress
clock output.
0 = No delay is added, only clock to data
skew applied.
Note: If setting bit [3] = ‘1’, RGMII transmit clock adds an internal egress delay
to add min 1ns data to clock skew toreceive side, then the receiving side
may or may not add any internal delay
to meet its own receiving timing requirement. (The clock trace should be equal
length with data traces in PCB layout if
no additional external skew on clock isneeded).

R/W

1

MII Mode SelectPort 5 SW5-MII Mode Select
1 = MII is in MAC mode (default).
0 = MII is in PHY mode.
Strap-in option: LED2_1
PU = MII is in MAC mode. (default)
PD = MII is in PHY mode.
Note: When setting SW5-MII to PHY
mode, the CRS, COL, RXC, and TXC
pins will change from the input to output.
This bit is reserved for Port 4.

R/W

1

4

3

2

 2015 Microchip Technology Inc.

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KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

Interface Mode Select

These bits select the interface type andmode for switch Port 5 (SW5).
Port 5 Mode Select:
00 = MII
01 = RMII
10 = Reserved
11 = RGMII.
Strap-in option: LED3[1:0]00 = MII
01 = RMII
10 = Reserved
11 = RGMII (default)
Note: These pins have internal pull-ups.
These bits are reserved for Port 4.

R/W

11

Reserved

N/A Don’t Change

RO

0000

5-4

Advertised Flow Control Capability

These bits indicate that the KSZ8775CLX has implemented both the optional
MAC control sublayer and the PAUSE
function as specified in IEEE Clause 31
and Annex 31B for full duplex operation
independent of rate and medium.
00 = No pause
01 = Symmetric PAUSE
10 = Asymmetric PAUSE toward link
partner toward link partner
11 = Both Symmetric PAUSE and Asymmetric PAUSE toward local devices
Bit [5] indicates that asymmetric PAUSE
is supported. The value of bit [4], whenbit [5] is set, indicates the direction of
the PAUSE frames that are supported
for flow across the link. Asymmetric
PAUSE configuration results in independent enabling of the PAUSE receive and
PAUSE transmit functions as defined byIEEE Annex 31B.

R/W

11

3

1 = Advertise 100BT full-duplex
capability.
Advertised 100BT Full0 = Suppress 100BT full-duplex
Duplex Capability
capability from transmission to link
partner.

R/W

1

2

1 = Advertise 100BT half-duplex
capability.
Advertised 100BT Half0 = Suppress 100BT half-duplex
Duplex Capability
capability from transmission to link
partner.

R/W

1

1

Advertised 10BT FullDuplex Capability

R/W

1

1-0

Register 23 (0x17): Port 3 Control 7
Register 39 (0x27): Port 3 Control 7
Register 55 (0x37): Port 3 Control 7
Register 71 (0x47): Reserved
Register 87 (0x57): Reserved
7-6DS00002129C-page 62

1 = Advertise 10BT full-duplex
capability.
0 = Suppress 10BT full-duplex capability
from transmission to link partner.

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

Address

Mode

Default

1 = Advertise 10BT half-duplex
capability.
0 = Suppress 10BT half-duplex
capability from transmission to link
partner.

R/W

1

Reserved

N/A Don’t change

RO

0000

5-4

Partner Flow Control
CapableThese bits indicate the partner capability
for both the optional MAC control sublayer and the PAUSE function as
specified in IEEE Clause 31 and Annex
31B for full duplex operation
independent to rate and medium.
00 = No pause
01 = Symmetric PAUSE
10 = Asymmetric PAUSE toward link
partner toward link partner
11 = Both Symmetric PAUSE andAsymmetric PAUSE toward local
devices

RO

00

3

Partner 100BT
Full-Duplex Capability

1 = Link partner 100BT full-duplex
capable.
0 = Link partner not 100BT full-duplex
capable.

RO

0

2

Partner 100BT HalfDuplex Capability

1 = Link partner 100BT half-duplex
capable.
0 = Link partner not 100BT half-duplex
capable.

RO

0

1

Partner 10BT FullDuplex Capability

1 = Link partner 10BT full-duplex
capable.
0 = Link partner not 10BT full-duplex
capable.

RO

0

0

Partner 10BT HalfDuplex Capability

1 = Link partner 10BT half-duplex
capable.
0 = Link partner not 10BT half-duplex
capable.

RO

0

0

Name

Advertised 10BT HalfDuplex Capability

Description

Register 24 (0x18): Port 1 Status 0
Register 40 (0x28): Port 2 Status 0
Register 56 (0x38): Port 3 Status 0
Register 72 (0x48): Reserved
Register 88 (0x58): Reserved
7-6

Register 25 (0x19): Port 1 Status 1
Register 41 (0x29): Port 2 Status 1
Register 57 (0x39): Port 3 Status 1
Register 73 (0x49): Reserved
Register 89 (0x59): Reserved
7

Hp_Mdix

1 = HP Auto MDI/MDI-X Mode
0 = Microchip Auto MDI/MDI-X Mode

R/W

1

6

Factory Testing

N/A Don’t change

RO

0

5

Polrvs

1 = Polarity is reversed
0 = Polarity is not reversedRO0 2015 Microchip Technology Inc.

DS00002129C-page 63

KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

AddressName

4Transmit Flow Control
Enable3

Description

Mode

Default

1 = Transmit flow control feature is
active0 = Transmit flow control feature isinactive

RO

0

Receive Flow Control
Enable1 = Receive flow control feature is active
0 = Receive flow control feature is inactive

RO

0

2

Operation Speed

1 = Link speed is 100 Mbps
0 = Link speed is 10 Mbps

RO

0

1

Operation Duplex

1 = Link duplex is full
0 = Link duplex is half

RO

0

0

Reserved

N/A Don’t changeRO

0

Cable Diagnostic Test
(CDT) 10M Short

1 = Less than 10 meter short

RO

0

CDT_Result

00 = Normal condition
01 = Open condition detected in cable
10 = Short condition detected in cable
11 = Cable diagnostic test has failed

RO

00

4

CDT_Enable

1 = Enable cable diagnostic test. After
CDT test has completed, this bit will be
self-cleared.
0 = Indicates that the cable diagnostic
test (if enabled) has indicated cablediagnostic test.

R/W
(SC)

0

3

Force_Link

1 = Force link pass
0 = Normal operation

R/W

0

2

Pwrsave

1 = Enable power saving
0 = Disable power saving

R/W

0

Remote Loopback

1 = Perform Remote loopback, loopback
on Port 1 as follows:
Port 1 (Register 26, bit [1] = ‘1’)
Start: RXP1/RXM1 (Port 1)
Loopback: PMD/PMA of Port 1’s PHY
End: TXP1/TXM1 (Port 1)
Setting Register 42, 58, 74 bit [1] = ‘1’will perform remote loopback on Port 2,
3, 4.
0 = Normal Operation.

R/W

0

CDT_Fault_Count[8]Bit[8] of CDT fault countDistance to the fault.
It is approximately 0.4 × CDT_Fault_Count[8:0].

RO0Register 26 (0x1A): Port 1 PHY Control 8
Register 42 (0x2A): Port 2 PHY Control 8
Register 58 (0x3A): Port 3 PHY Control 8
Register 74 (0x4A): Reserved
Register 90 (0x5A): Reserved
7

6-5

1

0

Register 27 (0x1B): Port 1 LinkMD result
Register 43 (0x2B): Port 2 LinkMD result
Register 59 (0x3B): Port 3 LinkMD result
Register 75 (0x4B): Reserved
Register 91 (0x5B): Reserved

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KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

Address

Mode

Default

RO

0

Disable Auto-Negotiation

1 = Disable auto-negotiation. Speed andduplex are decided by bits [6:5] of thesame register.
0 = Auto-negotiation is on.
Note: This bit shouldn’t be used for Port4 SW4-RMII.

R/W

0Forced Speed

1 = Forced 100BT if auto-negotiation isdisabled (bit [7]).
0 = Forced 10BT if auto-negotiation isdisabled (bit [7]).
Note: This bit is for Port 1, Port 2, Port3, and Port 4 SW4-RMII.

R/W

1

5

Forced Duplex

1 = Forced full-duplex if (1) AN is disabled or (2) AN is enabled but failed.
0 = Forced half-duplex if (1) AN is disabled or (2) AN is enabled but failed(default).
Note: This bit is for Port 1, Port 2, Port3, and Port 4 SW4-RMII.

R/W

0

4-0

Reserved

N/A Don’t change

RO

0x1f

R/W

0

7-0

Name

Description

Bits[7:0] of CDT fault countDistance to the fault.
CDT_Fault_Count[7:0]
It is approximately 0.4m × CDT_Fault_Count[8:0]Register 28 (0x1C): Port 1 Control 9
Register 44 (0x2C): Port 2 Control 9
Register 60 (0x3C): Port 3 Control 9
Register 76 (0x4C): Port 4 Control 9
Register 92 (0x5C): Reserved

7

6

Register 29 (0x1D): Port 1 Control 10
Register 45 (0x2D): Port 2 Control 10
Register 61 (0x3D): Port 3 Control 10
Register 77 (0x4D): Port 4 Control 10
Register 93 (0x5D): Reserved

7

LED Off

1 = Turn off all Ports’ LEDs (LEDx_2,
LEDx_1, LEDx_0 pins, where “x” is theport number). These pins will be driven
high if this bit is set to ‘1’.
0 = Normal operation.

6

Txids

1 = Disable port’s transmitter.
0 = Normal operation.

R/W

0

5

Restart AN

1 = Restart auto-negotiation.
0 = Normal operation.

R/W
(SC)

0

4

Reserved

N/A Don’t change

RO

0

3

Power Down

1 = Power down.
0 = Normal operation.

R/W

0

2

Disable Auto MDI/MDI- 1 = Disable Auto-MDI/MDIX function.
X
0 = Enable Auto-MDI/MDIX function.

R/W

0

1

Forced MDI

R/W

0 2015 Microchip Technology Inc.

1 = If Auto-MDI/MDIX is disabled, force
PHY into MDI mode.
0 = MDI-X mode.

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KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

Address0

Name

MAC Loopback

Description

Mode

Default

1 = Perform MAC loopback. Loopback
path is as follows: (e.g., set Port 1 MAC
Loopback (Reg. 29, bit [0] = ‘1’), use
Port 2 as monitor port. The packets willtransfer.
Start: Port 2 receiving (also can start toreceive packets from Port 3, 4, 5).
Loopback: Port 1’s MAC.
End: Port 2 transmitting (also can end at
Port 3, 4, 5 respectively).
Setting Register 45, 61, 77, 93, bit [0] =‘1’ will perform MAC loopback on Port 2,
3, 4, 5 respectively.
0 = Normal Operation.
Note: Bit[0] MAC loopback supports
Port 1 through Port 5. Other bits support
Port 1 through Port 3.

R/W

0

Register 30 (0x1E): Port 1 Status 2
Register 46 (0x2E): Port 2 Status 2
Register 62 (0x3E): Port 3 Status 2
Register 78 (0x4E): Reserved
Register 94 (0x5E): Reserved
7

MDIX Status

1 = MDI.
0 = MDI-X.

RO

0

6

Auto-Negotiation Done

1 = Auto-Negotiation done.
0 = Auto-Negotiation not done.

RO

0

5

Link Good

1 = Link good.
0 = Link not good.

RO

0

4-0

Reserved

N/A Don’t change

RO

00000

R/W

0

Register 31 (0x1F): Port 1 Control 11 and Status 3
Register 47 (0x2F): Port 2 Control 11 and Status 3
Register 63 (0x3F): Port 3 Control 11 and Status 3
Register 79 (0x4F): Reserved
Register 95 (0x5F): Reserved

7

PHY Loopback

1 = Perform PHY loopback. Loopback
path is as follows. Example: Set Port 1
PHY Loopback (Reg. 31, bit [7] = ‘1’)
Use Port 2 as monitor port. The packets
will transfer.
Start: Port 2 receiving (also can startfrom Port 3, 4, 5).
Loopback: PMD/PMA of Port 1’s PHY
End: Port 2 transmitting (also can end at
Port 3, 4, 5 respectively).
Setting Register 47, 63, 79, 95, bit [7] =‘1’ will perform PHY loopback on Port 2,
3, 4, 5 respectively.
0 = Normal operation.

6

Reserved

N/A Don’t change

RO

0

PHY Isolate

1 = Electrical isolation of PHY from theinternal MII and TX+/TX-.
0 = Normal operation.

R/W

0

5

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KSZ8775CLXTABLE 4-4:

PORT REGISTERS (CONTINUED)

Address

Description

Mode

Default

4

Soft-Reset

1 = PHY soft-reset. This bit is self-clearing.
0 = Normal operation.

R/W
(SC)

0

3

Force Link

1 = Force link in the PHY.
0 = Normal operation

R/W

0Port Operation Mode
Indication

Indicate the current state of port operation mode:
000 = Reserved
001 = Still in Auto-Negotiation
010 = 10BASE-T half-duplex
011 = 100BASE-TX half-duplex
100 = Reserved
101 = 10BASE-T full-duplex
110 = 100BASE-TX full-duplex
111 = Reserved

RO

001

2-0

Port Control 7-11 and Port Status 1-3 contents can be accessed by MDC/MDIO interface via the standard
MIIM registers.

Note:

4.3

Name

Advanced Control Registers

TABLE 4-5:

ADVANCED CONTROL REGISTERS

AddressName

Description

Mode

Default

Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address
in MAC pause control frames.
Register 104 (0x68): MAC Address Register 0
7-0

MACA[47:40]

—

R/W

0x00

—

R/W

0x10

—

R/W

0xA1

—

R/W

0xff

—

R/W

0xff

—

R/W

0xff

Register 105 (0x69): MAC Address Register 1
7-0

MACA[39:32]

Register 106 (0x6A): MAC Address Register 2
7-0

MACA[31:24]

Register 107 (0x6B): MAC Address Register 3
7-0

MACA[23:16]

Register 108 (0x6C): MAC Address Register 4
7-0

MACA[15:8]

Register 109 (0X6D): MAC Address Register 5
7-0

MACA[7:0]

Use Registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table,
PME registers, ACL tables, EEE registers, and the MIB counters.
Register 110 (0x6E): Indirect Access Control 0 2015 Microchip Technology Inc.

DS00002129C-page 67

KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

7-5

EEE/ACL/PME
Indirect Register
Function Select000 = Indirect mode is used for table select in bits [3:2].
While these bits are not equal 000, bits [3:2] are usedfor 2 additional MSB address bits.
001 = Global and port-based EEE registers are
selected, port count is specified in 4 MSB indirect
address bits and 8 bits register pointer is specified in 8
LSB indirect address bits.
010 = Port-based ACL registers are selected, port
count is specified in 4 MSB indirect address bits andregister pointer is specified in 8 LSB indirect address
bits.
011 = Reserved
100 = PME control registers are selected.
101 = LinkMD cable diagnosis used. (See example in
LinkMD section).

R/W

000

4

Read High Write
Low

1 = Read cycle.
0 = Write cycle.

R/W

0

3-2

Table Select orIndirect Address[11:10]If bits [6:5] = 00, then00 = Static MAC Address Table selected.
01 = VLAN table selected.
10 = Dynamic Address Table selected.
11 = MIB Counter selected.
If bits [6:5] not equal 00, then these are indirect
address [11:10] that is MSB of indirect address, bits
[11:8] of the indirect address may be served as portaddress, and bits [7:0] as register address.
Note: The Register 110 bits[3:0] are used for the indirect address bits [11:8] 4 MSB bits, the 4 bits are used
for the port indirect registers as well.
0000 = Global indirect registers
0001 = Port 1 indirect registers
0010 = Port 2 indirect registers
0011 = Port 3 indirect registers
0100 = Port 4 indirect registers
0101 = Port 5 indirect registers
The Register 111 bits[7:0] are used for the indirect
address bits of 8 LSB for indirect register address
spacing.

R/W

0

1-0

Indirect Address[9:8]

Bits [9:8] of indirect address.

R/W

00

R/W

00000000

Register 111 (0x6F): Indirect Access Control 1
7-0
Note:

Indirect Address Bits [7:0] of indirect address.
[7:0]

Write to Register 111 will actually trigger a command. Read or write access is decided by bit [4] of Register
110.

DS00002129C-page 68

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KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

The following Indirect Data Registers 112-120 are used for table of static, VLAN, dynamic table, PME, EEE, ACL, andMIB counters.
Register 112 (0x70): Indirect Data Register 8
7-0

Indirect Data
[68:64]

Bits [68:64] of indirect data.

R/W

00000000

R/W

00000000

R/W

00000000

R/W

00000000

R/W

00000000

R/W

00000000

R/W

00000000

R/W

00000000

R/W

00000000

Register 113 (0x71): Indirect Data Register 7
7-0

Indirect Data
[63:56]

Bits [63:56] of indirect data.

Register 114 (0x72): Indirect Data Register 6
7-0

Indirect Data
[55:48]Bits [55:48] of indirect data.

Register 115 (0x73): Indirect Data Register 5
47-40

Indirect Data
[47:40]

Bits [47:40] of indirect data.

Register 116 (0x74): Indirect Data Register 4
7-0

Indirect Data
[39:32]

Bits [39:32] of indirect data.

Register 117 (0x75): Indirect Data Register 3
7-0

Indirect Data
[31:24]

Bits [31:24] of indirect data

Register 118 (0x76): Indirect Data Register 2
7-0

Indirect Data
[23:16]

Bits [23:16] of indirect data.

Register 119 (0x77): Indirect Data Register 1
7-0

Indirect Data
[15:8]

Bits [15:8] of indirect data.

Register 120 (0x78): Indirect Data Register 0
7-0

Indirect Data [7:0] Bits [7:0] of indirect data.

The named indirect byte registers are direct registers that are used for PME/ACL/EEE indirect register access only.
The Indirect Byte Register 160 (0XA0) is used for read/write to all PME, EEE, and ACL indirect registers.
Register 160 (0XA0): Indirect Byte Register (For PME, EEE, and ACL Registers)
7-0

Indirect Byte [7:0]

Byte data of indirect access.

R/W

00000000

Register 124 (0x7C): Interrupt Status Register
7–5

Reserved

N/A Don’t change

RO

000

4

PME Interrupt
Status

1 = PME interrupt request
0 = Normal
Note: This bit reflects PME control registers, write to
PME control register to clear
Note: This bit is set when PME is asserted. Write a “1”to clear this bit (WC)

RO

0

3

Port 4 Interrupt
Status

1 = Port 4 interrupt request
0 = Normal
Note: This bit is set by Port 4 link change. Write a “1”to clear this bit (WC)

R/WC

0

2

Port 3 Interrupt
Status

1 = Port 3 interrupt request
0 = Normal
Note: This bit is set by a link change on Port 3. Write a“1” to clear this bit (WC)

R/WC

0

 2015 Microchip Technology Inc.

DS00002129C-page 69

KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

1

Port 2 Interrupt
Status

1 = Port 2 interrupt request
0 = Normal
Note: This bit is set by a link change on Port 2. Write a“1” to clear this bit (WC)

R/WC

0

0

Port 1 Interrupt
Status

1 = Port 1 interrupt request
0 = Normal
Note: This bit is set by link change on Port 1. Write a“1” to clear this bit (WC)

R/WC

0

Register 125 (0x7D): Interrupt Mask Register
7–5

Reserved

N/A Don’t change

RO

000

4

PME Interrupt
Mask

1 = Enable PME interrupt.
0 = Normal

R/W

0

3

Port 4 Interrupt
Mask

1 = Enable Port 4 interrupt.
0 = Normal

R/W

0

2

Port 3 Interrupt
Mask

1 = Enable Port 3 interrupt.
0 = Normal

R/W

0

1

Port 2 Interrupt
Mask

1 = Enable Port 2 interrupt.
0 = Normal

R/W

0

0

Port 1 Interrupt
Mask

1 = Enable Port 1 interrupt.
0 = Normal

R/W

0Register 126 (0x7E): ACL Interrupt Status Register
7–5
4-0

Reserved

N/A Don’t change

RO

000

ACL_INT_STATUSACL Interrupt Status, one bit per port
1 = ACL interrupt detected.
0 = No ACL interrupt detected.

RO

00000

Register 127 (0x7F): ACL Interrupt Control Register
7–5

Reserved

N/A Don’t change

RO

000

4-0

ACL_INT_ENABLEACL Interrupt Enable, one bit per port
1 = ACL interrupt enabled.
0 = ACL interrupt disabled.

R/W

0

The Registers 128 and 129 can be used to map from 802.1p priority field 0-7 to the switch’s four priority queues 0-3.
0x3 is the highest priority queue, as priority 3, and 0x0 is the lowest priority queues, as priority 0.
Register 128 (0x80): Global Control 12
7–6

Tag_0x3

IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x3.

R/W

0x1

5–4

Tag_0x2IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x2.

R/W

0x1

3–2

Tag_0x1

IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x1.

R/W

0x0

1–0

Tag_0x0

IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x0.

R/W

0x0

R/W

0x3

Register 129 (0x81): Global Control 13
7–6

Tag_0x7

DS00002129C-page 70

IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x7.

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

5–4

Tag_0x6

IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x6.

R/W

0x3

3–2

Tag_0x5

IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x5.

R/W

0x2

1–0

Tag_0x4IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has avalue of 0x4.

R/W

0x2

R/W

10

RO

001000RO

10Register 130 (0x82): Global Control 14
When the 2 Queues configuration is selected, these
Pri_2Q[1:0] bits are used to map the 2-bit result ofIEEE 802.1p from Register 128/129 or TOS/DiffServfrom Register 144-159 mapping (for 4 Queues) into
two queues low/high priorities.

7–6

Pri_2Q[1:0]2-bit result of IEEE 802.1p or ToS/DiffServ
00 (0) = Map to low priority queue01 (1) = Prio_2Q[0] map to low/high priority queue
10 (2) = Prio_2Q[1] map to low/high priority queue
11 (3) = Map to high priority queue
Pri_2Q[1:0] :00 = Result 0,1, 2 are low priority. 3 is high priority.
01 = Not supported and should be avoided
10 = Result 0,1 are low priority. 2, 3 are high priority(default).
11 = Result 0 is low priority. 1, 2, 3 are high priority.

5-0

Reserved

N/A Don’t change

Register 131 (0x83): Global Control 15
7-6

Reserved

N/A Don’t change

5

Unknown Unicast 1 = Enable supporting unknown unicast packet forward
Packet Forward
0 = Disable

R/W

0

4–0

00000 = Filter unknown unicast packet
00001 = Forward unknown unicast packet to Port 1
00011 = Forward unknown unicast packet to Port 1,
Unknown Unicast Port 2
Packet Forward
00111 = Forward unknown unicast packet to Port 1,
Port Map
Port 2, and Port 3
01111 = Forward unknown unicast packet to Port 1,
Port 2, Port 3, and Port 411111 = Broadcast unknown unicast packet to all ports

R/W

00000

RO

01

R/W

0

Register 132 (0x84): Global Control 16
7-6

Reserved

5

Unknown Multicast Packet For- 1 = Enable supporting unknown multicast packet forward (notward
including IP multi- 0 = Disable
cast packet)

 2015 Microchip Technology Inc.

N/A Don’t change

DS00002129C-page 71

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ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

Unknown Multicast Packet Forward Port Map

00000 = Filter unknown multiicast packet
00001 = Forward unknown multicast packet to Port 1
00011 = Forward unknown multicast packet to Port 1,
Port 200111 = Forward unknown multicast packet to Port 1,
Port 2, and Port 3
01111 = Forward unknown multicast packet to Port 1,
Port 2, Port 3 and, Port 411111 = Broadcast unknown multicast packet to all
ports

R/W

00000

4–0

Register 133(0x85): Global Control 17
7–6

Reserved

N/A Don’t change

RO

00

5

Unknown VID
Packet Forward

1 = Enable supporting unknown VID packet forward
0 = Disable

R/W

0

Unknown VID
Packet Forward
Port Map

00000 = Filter unknown VID packet
00001 = Forward unknown VID packet to Port 1
00011 = Forward unknown VID packet to Port 1, Port 200111 = Forward unknown VID packet to Port 1, Port 2,
and Port 3
01111 = Forward unknown VID packet to Port 1, Port 2,
Port 3, and Port 411111 = Broadcast unknown VID packet to all ports

R/W

00000

4–0

Register 134 (0x86): Global Control 18
Reserved

N/A Don’t changeRO0

Self-Address Filter Enable

1 = Enable filtering of self-address unicast and multicast packet
0 = Do not filter self-address packet
Note: The self-address filtering will filter packets on theegress port, self MAC address is assigned in the Register 104-109.

R/W

0

5

Unknown IP Multi- 1 = Enable supporting unknown IP multicast packet
cast Packet For- forwardward
0 = Disable supporting unknown IP multicast packet
forward

R/W

0

4–0

Unknown IP Multi- 00000 = Filter unknown IP multicast packet
cast Packet For- 00001 = Forward unknown IP multicast packet to Port
ward Port Map
100011 = Forward unknown IP multicast packet to Port
1, Port 200111 = Forward unknown IP multicast packet to Port
1, Port 2, and Port 3
01111 = Forward unknown IP multicast packet to Port
1, Port 2, Port 3, and Port 411111 = Broadcast unknown IP multicast packet to all
ports

R/W

00000

RO

00

R/W

01

7

6

Register 135 (0x87): Global Control 19
7-6

Reserved

5–4

The unit period for calculating ingress rate limit
Ingress Rate Limit 00 = 16 ms
Period01 = 64 ms
1x = 256 ms

DS00002129C-page 72

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KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

R/W

03

Queue-based
Enable queue-based egress rate limit
Egress Rate Limit 0 = Port-based egress rate limit (default)
Enabled
1 = Queue-based egress rate limit

2

Insertion Source
Port PVID Tag
Selection Enable

1 = Enable source port PVID tag insertion or non-insertion option on the egress port for each source port
PVID based on the Port Control 8 Registers.
0 = Disable, all packets from any ingress port will beinserted PVID based on Port Control 0 Register bit [2].

R/W

0

1–0

Reserved

N/A Don’t changeRO

00

Register 144 (0x90): ToS Priority Control Register 0
The IPv4/IPv6 ToS priority control registers implement a fully decoded 64-bit differentiated services code point(DSCP) register used to determine priority from the 6-bit ToS field in the IP header. The most significant six bits of the
ToS field are fully decoded into 64 possibilities and the singular code that results is mapped to the value in the corresponding bit in the DSCP register.
7–6

5–4

3–2

1–0

DSCP[7:6]

IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP OS/DiffServ/Traffic
Class value is 0x03.

R/W

00

DSCP[5:4]

IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP OS/DiffServ/Traffic
Class value is 0x02.

R/W

00

DSCP[3:2]

IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP OS/DiffServ/Traffic
Class value is 0x01.

R/W

00

DSCP[1:0]

IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP OS/DiffServ/Traffic
Class value is 0x00.

R/W

00

Register 145 (0x91): ToS Priority Control Register 1
7–6

DSCP[15:14]

IPv4 and IPv6 mapping for value 0x07

R/W

00

5–4

DSCP[13:12]

IPv4 and IPv6 mapping for value 0x06

R/W

00

3–2

DSCP[11:10]

IPv4 and IPv6 mapping for value 0x05

R/W

00

1–0

DSCP[9:8]

IPv4 and IPv6 mapping for value 0x04

R/W

00

Register 146 (0x92): ToS Priority Control Register 2
7–6

DSCP[23:22]

IPv4 and IPv6 mapping for value 0x0B

R/W

00

5–4

DSCP[21:20]

IPv4 and IPv6 mapping for value 0x0A

R/W

00

3–2

DSCP[19:18]

IPv4 and IPv6 mapping for value 0x09

R/W

00

1–0

DSCP[17:16]

IPv4 and IPv6 mapping for value 0x08

R/W

00

Register 147 (0x93): ToS Priority Control Register 3
7–6

DSCP[31:30]

IPv4 and IPv6 mapping for value 0x0F

R/W

00

5–4

DSCP[29:28]

IPv4 and IPv6 mapping for value 0x0E

R/W

00

3–2

DSCP[27:26]

IPv4 and IPv6 mapping for value 0x0D

R/W

00

1–0

DSCP[25:24]

IPv4 and IPv6 mapping for value 0x0C

R/W

00

Register 148 (0x94): ToS Priority Control Register 4
7–6

DSCP[31:30]

IPv4 and IPv6 mapping for value 0x0F

R/W

00

5–4

DSCP[29:28]

IPv4 and IPv6 mapping for value 0x0E

R/W

00

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ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

3–2

DSCP[27:26]

IPv4 and IPv6 mapping for value 0x0D

R/W

00

1–0

DSCP[25:24]

IPv4 and IPv6 mapping for value 0x0C

R/W

00

Register 149 (0x95): ToS Priority Control Register 5
7–6

DSCP[47:46]

IPv4 and IPv6 mapping for value 0x17

R/W

00

5–4

DSCP[45:44]

IPv4 and IPv6 mapping for value 0x16

R/W

00

3–2

DSCP[43:42]

IPv4 and IPv6 mapping for value 0x15

R/W

00

1–0

DSCP[41:40]

IPv4 and IPv6 mapping for value 0x14

R/W

00

R/W

00

Register 150 (0x96): ToS Priority Control Register 6
7–6

DSCP[55:54]

IPv4 and IPv6 mapping for value 0x1B

5–4

DSCP[53:52]

IPv4 and IPv6 mapping for value 0x1A

R/W

00

3–2

DSCP[51:50]

IPv4 and IPv6 mapping for value 0x19

R/W

00

1–0

DSCP[49:48]

IPv4 and IPv6 mapping for value 0x18

R/W

00

Register 151 (0x97): ToS Priority Control Register 7
7–6

DSCP[63:62]

IPv4 and IPv6 mapping for value 0x1F

R/W

00

5–4

DSCP[61:60]

IPv4 and IPv6 mapping for value 0x1E

R/W

00

3–2

DSCP[59:58]

IPv4 and IPv6 mapping for value 0x1D

R/W

00

1–0

DSCP[57:56]

IPv4 and IPv6 mapping for value 0x1C

R/W

00

Register 152 (0x98): ToS Priority Control Register 8
7–6

DSCP[71:70]

IPv4 and IPv6 mapping for value 0x23

R/W

00

5–4

DSCP[69:68]

IPv4 and IPv6 mapping for value 0x22

R/W

00

3–2

DSCP[67:66]

IPv4 and IPv6 mapping for value 0x21

R/W

00

1–0

DSCP[65:64]

IPv4 and IPv6 mapping for value 0x20

R/W

00

Register 153 (0x99): ToS Priority Control Register 9
7–6

DSCP[79:78]

IPv4 and IPv6 mapping for value 0x27

R/W

00

5–4

DSCP[77:76]

IPv4 and IPv6 mapping for value 0x26

R/W

00

3–2

DSCP[75:74]

IPv4 and IPv6 mapping for value 0x25

R/W

00

1–0

DSCP[73:72]

IPv4 and IPv6 mapping for value 0x24

R/W

00

R/W

00

Register 154 (0x9A): ToS Priority Control Register 10
7–6

DSCP[87:86]

IPv4 and IPv6 mapping for value 0x2B

5–4

DSCP[85:84]

IPv4 and IPv6 mapping for value 0x2A

R/W

00

3–2

DSCP[83:82]

IPv4 and IPv6 mapping for value 0x29

R/W

00

1–0

DSCP[81:80]

IPv4 and IPv6 mapping for value 0x28

R/W

00

R/W

00

Register 155 (0x9B): ToS Priority Control Register 11
7–6

DSCP[95:94]

IPv4 and IPv6 mapping for value 0x2F

5–4

DSCP[93:92]

IPv4 and IPv6 mapping for value 0x2E

R/W

00

3–2

DSCP[91:90]

IPv4 and IPv6 mapping for value 0x2D

R/W

00

1–0

DSCP[89:88]

IPv4 and IPv6 mapping for value 0x2C

R/W

00

IPv4 and IPv6 mapping for value 0x33

R/W

00

Register 156 (0x9C): ToS Priority Control Register 12
7–6

DSCP[103:102]

5–4

DSCP[101:100]

IPv4 and IPv6 mapping for value 0x32

R/W

00

3–2

DSCP[99:98]

IPv4 and IPv6 mapping for value 0x31

R/W

00

1–0

DSCP[97:96]

IPv4 and IPv6 mapping for value 0x30

R/W

00

R/W

00

Register 157 (0x9D): ToS Priority Control Register 13
7–6

DSCP[111:110]

DS00002129C-page 74

IPv4 and IPv6 mapping for value 0x37

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ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

5–4

DSCP[109:108]

3–2
1–0

Description

Mode

Default

IPv4 and IPv6 mapping for value 0x36

R/W

00

DSCP[107:106]

IPv4 and IPv6 mapping for value 0x35

R/W

00

DSCP[105:104]

IPv4 and IPv6 mapping for value 0x34

R/W

00

Register 158 (0x9E): ToS Priority Control Register 14
7–6

DSCP[119:118]

IPv4 and IPv6 mapping for value 0x3B

R/W

00

5–4

DSCP[117:116]

IPv4 and IPv6 mapping for value 0x3A

R/W

00

3–2

DSCP[115:114]

IPv4 and IPv6 mapping for value 0x39

R/W

00

1–0
DSCP[113:112]
IPv4 and IPv6 mapping for value 0x38
Register 159 (0x9F): ToS Priority Control Register 15

R/W

00

7–6

DSCP[127:126]

IPv4 and IPv6 mapping for value 0x3F

R/W

00

5–4

DSCP[125:124]

IPv4 and IPv6 mapping for value 0x3E

R/W

00

IPv4 and IPv6 mapping for value 0x3D

R/W

00

DSCP[121:120]
IPv4 and IPv6 mapping for value 0x3C
Register 163 (0XA3): Global Control 20

R/W

00

RO

0

3–2

DSCP[123:122]

1–0
7

Reserved

N/A Don’t change

6–4

High speed interfaces drive strength for RGMI
000 = 2 mA
001 = 4 mA
RGMII
010 = 8 mA
High Speed Drive 011 = 12 mA
Strength
100 = 16 mA
101 = 20 mA
110 = 24 mA (default)
111 = 28 mA

R/W

110

3

Reserved

RO

0

2–0

Low speed interfaces drive strength for MII & RMII
000 = 2 mA
001 = 4 mA
MII/RMII
010 = 8 mA (default)
Low Speed Drive 011 = 12 mA
Strength
100 = 16 mA
101 = 20 mA
110 = 24 mA
111 = 28 mA

R/W

010

RO

0x2

N/A Don’t change

Register 164 (0XA4): Global Control 21
7–4

Reserved

N/A Don’t change

3

IPv6 MLD snooping option
IPv6 MLD Snoop1 = Enable
ing Option
0 = Disable

R/W

0

2

IPv6 MLD snooping enable
IPv6 MLD Snoop1 = Enable
ing Enable
0 = Disable

R/W

0

1–0

ReservedRO

10

N/A Don’t change

Register 176 (0xB0): Port 1 Control 12
Register 192 (0xC0): Port 2 Control 12
Register 208 (0xD0): Port 3 Control 12
Register 224 (0xE0): Port 4 Control 12
Register 240 (0xF0): Reserved

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ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

7

Description

Mode

Default

Reserved

N/A Don’t change

RO

1

6

Pass All Frames

Port-based enable to pass all frames
1 = Enable
0 = Disable
Note: This is used in the port mirroring with RX sniff
only.

R/W

0

5–4

Reserved

N/A Don’t change

RO

0000

3

Register 176: Insert source Port 1 PVID for untagged
frame at egress Port 5
Register 192: Insert source Port 2 PVID for untagged
Insert Source Portframe at egress Port 5
PVID for
Register 208: Insert source Port 3 PVID for untagged
Untagged Packet
frame at egress Port 5
Destination toRegister 224: Insert source Port 4 PVID for untagged
Highest Egress
frame at egress Port 5
Port
Register 240: Insert source Port 5 PVID for untagged
frame at egress Port 4
Note: Enabled by the Register 135 bit [2].

R/W

0

2

Register 176: Insert source Port 1 PVID for untagged
frame at egress Port 4
Register 192: Insert source Port 2 PVID for untagged
Insert Source Portframe at egress Port 4
PVID for
Register 208: Insert source Port 3 PVID for untagged
Untagged Packet
frame at egress Port 4
Destination toRegister 224: Insert source Port 4 PVID for untagged
Second Highest
frame at egress Port 3
Egress Port
Register 240: Insert source Port 5 PVID for untagged
frame at egress Port 3
Note: Enabled by the Register 135 bit [2].

RW

0

RW

0

RW

0

Register 176: Insert source Port 1 PVID for untagged
frame at egress Port 3

1

Register 192: Insert source Port 2 PVID for untagged
Insert Source Port frame at egress Port 3
PVID for
Untagged Packet Register 208: Insert source Port 3 PVID for untagged
frame at egress Port 2
Destination toRegister 224: Insert source Port 4 PVID for untagged
Second Lowest
frame at egress Port 2
Egress Port
Register 240: Insert source Port 5 PVID for untagged
frame at egress Port 2
Note: Enabled by the Register 135 bit [2].

0Register 176: Insert source Port 1 PVID for untagged
frame at egress Port 2
Register 192: Insert source Port 2 PVID for untagged
Insert Source Portframe at egress Port 1
PVID for
Register 208: Insert source Port 3 PVID for untagged
Untagged Packet
frame at egress Port 1
Destination toRegister 224: Insert source Port 4 PVID for untagged
Lowest Egress
frame at egress Port 1
Port
Register 240: Insert source Port 5 PVID for untagged
frame at egress Port 1
Note: Enabled by the Register 135 bit [2].

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KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

Register 177 (0xB1): Port 1 Control 13
Register 193 (0xC1): Port 2 Control 13
Register 209 (0xD1): Port 3 Control 13
Register 225 (0xE1): Port 4 Control 13
Register 241 (0xF1): Port 5 Control 13
7-2

Reserved

N/A Don’t change

RO

0000000

1

4 Queue Split
EnableThis bit, in combination with Register16/32/48/64/80 bit[0], selects the split of 1, 2, and 4 queues:{Register 177 bit [1], Register 16 bit [0] = }:11 = Reserved.
10 = The port output queue is split into four priority
queues or if mapping 802.1p to priority 0-3 mode.
01 = The port output queue is split into two priority
queues or if mapping 802.1p to priority 0-3 mode.
00 = Single output queue on the port. There is no priority differentiation even though packets are classified
into high and low priority.

R/W

0

0

Enable Dropping
Tag

0 = Disable tagged packets drop
1 = Enable tagged packets drop

R/W

0

7

0 = Strict priority transmits all the packets from this PriEnable Port
ority Queue 3 before transmitting lower-priority queues.
Transmit Queue 3 1 = Bits [6:0] reflect the packet number allowing it toRatiotransmit from this Priority Queue 3 within a certain
time.

R/W

1

6-0

Port Transmit
Queue 3
Ratio[6:0]

R/W

0001000

7

0 = Strict priority transmits all the packets from this PriEnable Port
ority Queue 2 before transmitting lower-priority queues.
Transmit Queue 2 1 = Bits [6:0] reflect the packet number allowing it toRatiotransmit from this Priority Queue 2 within a certain
time.

R/W

1

6-0

Port Transmit
Queue 2
Ratio[6:0]

R/W

0001000

Register 178 (0xB2): Port 1 Control 14
Register 194 (0xC2): Port 2 Control 14
Register 210 (0xD2): Port 3 Control 14
Register 226 (0xE2): Port 4 Control 14
Register 242 (0xF2): Port 5 Control 14

Packet number for Transmit Queue 3 for highest priority packets in four-queues mode.

Register 179 (0xB3): Port 1 Control 15
Register 195 (0xC3): Port 2 Control 15
Register 211 (0xD3): Port 3 Control 15
Register 227 (0xE3): Port 4 Control 15
Register 243 (0xF3): Port 5 Control 15

Packet number for Transmit Queue 2 for high/low priority packets in high/low priority packets in four-queues
mode.

Register 180 (0xB4): Port 1 Control 16
Register 196 (0xC4): Port 2 Control 16
Register 212 (0xD4): Port 3 Control 16
Register 228 (0xE4): Port 4 Control 16
Register 244 (0xF4): Port 5 Control 16

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KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

7

0 = Strict priority transmits all the packets from this PriEnable Port
ority Queue 1 before transmitting lower-priority queues.
Transmit Queue 1 1 = Bits [6:0] reflect the packet number allowing it toRatiotransmit from this Priority Queue 1 within a certain
time.

R/W

1

6-0

Port Transmit
Queue 1
Ratio[6:0]

R/W

0000010

R/W

1

R/W

0000001

Packet number for Transmit Queue 1 for low/high priority packets in four-queues mode and high priority packets in two-queues mode.

Register 181 (0xB5): Port 1 Control 17
Register 197 (0xC5): Port 2 Control 17
Register 213 (0xD5): Port 3 Control 17
Register 229 (0xE5): Port 4 Control 17
Register 245 (0xF5): Port 5 Control 17

7Enable Port
Transmit Queue
0 Ratio

0 = Strict priority transmits all the packets from thisPriority Queue 0 before transmitting lower-priority
queues.
1 = Bits [6:0] reflect the packet number allowing it totransmit from this Priority Queue 0 within a certain
time.

Packet number for Transmit Queue 0 for lowest
Port Transmit
Queue 0priority packets in four-queues mode and low priority
Ratio[6:0]
packets in two-queue mode.
Register 182 (0xB6): Port 1 Rate Limit Control
Register 198 (0xC6): Port 2 Rate Limit Control
Register 214 (0xD6): Port 3 Rate Limit Control
Register 230 (0xE6): Port 4 Rate Limit Control
Register 246 (0xF6): Port 5 Rate Limit Control
6-0

7Reserved

RO

0

6

Ingress Limit Port/
1 = Ingress rate limit is port-based
Priority-Based
0 = Ingress rate limit is priority-based
SelectR/W

05

Ingress Limit Bit/
Packets Mode
Select

1 = Rate limit is counted based on the number of packets.
0 = Rate limit is counted based on the number of bits.

R/W

0

4

1 = Flow control is asserted if the port’s receive rate is
Ingress Rate Limit
exceeded.
Flow Control
0 = Flow control is not asserted if the port’s receive rate
Enableis exceeded.

R/W

0

3-2

Ingress Limit
Mode

These bits determine what type of frames are limited
and counted against ingress rate limiting.
00 = Limit and count all frames.
01 = Limit and count broadcast, multicast, and flooded
unicast frames.
10 = Limit and count broadcast and multicast frames
only.
11 = Limit and count broadcast frames only.

R/W

00

Count IFG Bytes

1 = Each frame’s minimum inter-frame gap.IFG bytes(12 per frame) are included in ingress and egress rate
limiting calculations.
0 = IFG bytes are not counted.

R/W

0

1

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KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

0Count Preamble
Bytes

Description
1 = Each frame’s preamble bytes (8 per frame) are
included in ingress and egress rate limiting calculations.
0 = Preamble bytes are not counted.

Mode

Default

R/W

0Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1
Note: In the port priority 0-3 ingress rate limit mode, all related egress ports should be set to two-queues or fourqueues mode.
7

Reserved—

6-0

Ingress data rate limit for priority 0 frames. Ingress trafPort-Based Prior- fic from this port is shaped according to Table 3-18,
ity 0 Ingress Limit "Rate Selection for Rate Limit" in the Section 3.5.13,"Rate Limiting Support" section.

RO

0

R/W

0000000

Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2
Note: In the port priority 0-3 ingress rate limit mode, all related egress ports should be set to two-queues or fourqueues mode.
7

Reserved—

6-0

Ingress data rate limit for priority 1 frames. Ingress trafPort-Based Prior- fic from this port is shaped according to Table 3-18,
ity 1 Ingress Limit "Rate Selection for Rate Limit" in the Section 3.5.13,"Rate Limiting Support" section.

RO

0

R/W

0000000

Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3
Note: In the port priority 0-3 ingress rate limit mode, all related egress ports should be set to two-queues or fourqueues mode.
7

Reserved—

6-0

Ingress data rate limit for priority 2 frames. Ingress trafPort-Based Prior- fic from this port is shaped according to Table 3-18,
ity 2 Ingress Limit "Rate Selection for Rate Limit" in the Section 3.5.13,"Rate Limiting Support" section.

RO

0

R/W

0000000

Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4
Note: In the port priority 0-3 ingress rate limit mode, all related egress ports should be set to two-queues or fourqueues mode.

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ADVANCED CONTROL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

7

Any write to this register triggers port ingress rate limit
engine to take effect for all the priority queues according to priority ingress limit control.
Port-Based
Note: For the port priority 0-3 ingress rate limit control
Ingress Rate Limit
to take effect, bit [7] in Register 186, 202, 218, 234,
Enableand 250 for Ports 1, 2, 3, 4, and 5, respectively willneed to be set after configured bits [6:0] of Port Ingress
Limit Control 1-4 registers.

R/W

0

6-0

Ingress data rate limit for priority 3 frames. Ingress trafPort-Based Prior- fic from this port is shaped according to Table 3-18,
ity 3 Ingress Limit "Rate Selection for Rate Limit" in the Section 3.5.13,"Rate Limiting Support" section.

R/W

0000000

Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1
Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1
Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1
Note: In the port queue 0-3 egress rate limit mode, the highest priority gets the exact rate limit based on the rate
select table. Other packets’ priority rates are based upon the ratio of the Port Control 14/15/16/17 Registers whenusing more than one egress queue per port.
7

6-0

Reserved—

RO

0

Port Queue 0
Egress Limit

Egress data rate limit for priority 0 frames. Egress traffic from this priority queue is shaped according toTable 3-18, "Rate Selection for Rate Limit" in the Section 3.5.13, "Rate Limiting Support" section.
In four-queues mode, it is lowest priority.
In two-queues mode, it is low priority.

R/W

0000000

Register 188 (0xBC): Port 1 Queue 1 Egress Limit Control 2
Register 204 (0xCC): Port 2 Queue 1 Egress Limit Control 2
Register 220 (0xDC): Port 3 Queue 1 Egress Limit Control 2
Register 236 (0xEC): Port 4 Queue 1 Egress Limit Control 2
Register 252 (0xFC): Port 5 Queue 1 Egress Limit Control 2
Note: In the port queue 0-3 egress rate limit mode, the highest priority gets the exact rate limit based on the rate
select table. Other packets’ priority rates are based upon the ratio of the Port Control 14/15/16/17 Registers whenusing more than one egress queue per port.
7

6-0

Reserved—

RO

0

Port Queue 1
Egress Limit

Egress data rate limit for priority 1 frames. Egress traffic from this priority queue is shaped according toTable 3-18, "Rate Selection for Rate Limit" in the Section 3.5.13, "Rate Limiting Support" section.
In four-queues mode, it is low/high priority.
In two-queues mode, it is high priority.

R/W

0000000

Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3
Note: In the port queue 0-3 egress rate limit mode, the highest priority gets the exact rate limit based on the rate
select table. Other packets’ priority rates are based upon the ratio of the Port Control 14/15/16/17 Registers whenusing more than one egress queue per port.
7

Reserved

DS00002129C-page 80

—

RO

0

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-5:

ADVANCED CONTROL REGISTERS (CONTINUED)

Address

Name

6-0

Port Queue 2
Egress Limit

Description

Egress data rate limit for priority 2 frames. Egresstraffic from this priority queue is shaped according to Table 3-18, "Rate Selection for Rate Limit" in the
Section 3.5.13, "Rate Limiting Support" section.

Mode

Default

R/W

0000000

In four-queues mode, it is high/low priority.
Register 190 (0xBE): Port 1 Queue 3 Egress Limit Control 4
Register 206 (0xCE): Port 2 Queue 3 Egress Limit Control 4
Register 222 (0xDE): Port 3 Queue 3 Egress Limit Control 4
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4
Note: In the port queue 0-3 egress rate limit mode, the highest priority gets the exact rate limit based on the rate
select table. Other packets’ priority rates are based upon the ratio of the Port Control 14/15/16/17 Registers whenusing more than one egress queue per port.
7

6-0

Reserved

Port Queue 3
Egress Limit—

Egress data rate limit for priority 3 frames. Egresstraffic from this priority queue is shaped according to Table 3-18, "Rate Selection for Rate Limit" in the
Section 3.5.13, "Rate Limiting Support" section.

RO

0

R/W

0000000

RO

0

R/W

0000000

RO

0x80

RO

0x15

RO

0x0C

RO

0x32

RO

0x00

section.
In four-queues mode, it is high/low priority.

Register 190 (0xBE): Port 1 Queue 3 Egress Limit Control 4
Register 206 (0xCE): Port 2 Queue 3 Egress Limit Control 4
Register 222 (0xDE): Port 3 Queue 3 Egress Limit Control 4
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4
7

6-0

Reserved
Port Queue 3
Egress Limit

Egress data rate limit for priority 3 frames. Egress traffic from this priority queue is shaped according toTable 3-18, "Rate Selection for Rate Limit" in the Section 3.5.13, "Rate Limiting Support" section.
In four-queues mode, it is highest priority.

Register 191 (0xBF): Testing Register
7-0

Reserved

N/A Don’t change

Register 207 (0xCF): Reserved Control Register
7-0

Reserved

N/A Don’t change

Register 223 (0xDF): Test Register 2
7-0

Reserved

N/A Don’t change

Register 239 (0xEF): Test Register 3
7-0

Reserved

N/A Don’t change

Register 255 (0xFF): Testing Register 4
7-0

Reserved

 2015 Microchip Technology Inc.

N/A Don’t change

DS00002129C-page 81

KSZ8775CLX
4.4

Indirect Register Description

TABLE 4-6:

INDIRECT REGISTER DESCRIPTION
Control

Indirect Address

Contents

Direct Address 0x6E
Function Select bits [7-5] = 000
Table_select bits [3-2] = 00

0x000 – 0x01F

Static MAC address table entry 0 – 31

Direct Address 0x6E
Function Select bits [7-5] = 000
Table_select bits [3-2] = 01

0x000 – 0x1FF

VLAN table bucket 0 – 1023
(4 entries per bucket)

Direct Address 0x6E
Function Select bits [7-5] = 000
Table_select bits [3-2] = 100x000 – 0x1FF

Dynamic MAC address table entry
0 – 1023
0x000 – 0x01F Port 1 MIB counters
0x020 – 0x03F Port 2 MIB counters

Direct Address 0x6E
Function Select bits [7-5] = 000
Table_select bits [3-2] = 110x000 – 0x08F,
0x100 – 0x109

0x040 – 0x05F Port 3 MIB counters
0x060 – 0x07F Port 4 MIB counters
0x080 – 0x09F Port 5 MIB counters0x100 – 0x113 Total bytes anddropped MIB counters

Direct Address 0x6E
Function Select bits [7-5] = 001,
bits [3-0] = Indirect Address,
bits [11-8] = MSB Indirect Address= port indirect register address
0xn{0xn, 6h00} – {0xn, 6h05}

n = port number
Use Indirect Byte Register (0xA0)

Direct Address 0x6E
Function Select bits [7-5] = 010,
bits [3-0] = Indirect Address,
bits [11-8] = MSB Indirect Address= port indirect register address
0xn{0xn, 6h00} – {0xn, 6h1F}

Direct Address 0x6E
Function Select bits [7-5] = 011,
bits [3-0] = Indirect Address,
bits [11-8] = MSB Indirect Address= port indirect register address
0xn{0xn, 8h00} – {0xn, 8h4FF}

ACL entry 0 – 15,
6h00 and 6h01 for entry 0, etc.
n = port number
Use Indirect Byte Register(0xA0)

Direct Address 0x6E
Function Select bits [7-5] = 100,
bits [3-0] = Indirect Address,
bits [11-8] = MSB Indirect Address= port indirect register address
0xn{0xn, 8h00} – {0xn, 8h4FF}

Direct Address 0x6E
Function Select bits [7-5] = 101,
bits [3-0] = Indirect Address,
bits [11-8] = MSB Indirect Address= port indirect register address
0xn{0xn, 8h00} – {0xn, 8h4FF}

DS00002129C-page 82

Port-based 16-bit EEE Control
Registers
0–5

Reserved for the factory

Configuration Registers, PME, etc.
n = 0 - Global
n = 1 – 4 Port number
Use Indirect Byte Register(0xA0)Reserved for the factory 2015 Microchip Technology Inc.

KSZ8775CLX
4.5

Static MAC Address Table

The KSZ8775CLX incorporates a static and a dynamic address table. When a DA look-up is requested, both tables aresearched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched
for aging, migration, and learning purposes. The static DA look-up result has preference over the dynamic DA look-up
result. If there are DA matches in both tables, the result from the static table is used. The static table can only beaccessed and controlled by an external SPI master (usually a processor). The entries in the static table are not agedout by KSZ8775CLX. An external device does all addition, modification, and deletion.
Register bit assignments are different for static MAC table reads and static MAC table writes, as shown in Table 4-7 and
7-4.

TABLE 4-7:

FORMAT OF STATIC MAC ADDRESSES FOR READS (32 ENTRIES)

Address

Description

Mode

Default

FID

Filter VLAN ID, representing one of the 128 active
VLANs.

RO

0000000

56

Use FID

1 = Use (FID+MAC) to look-up in static table.
0 = Use MAC only to look-up in static table.

RO

0

55

Reserved

Reserved.

RO

N/A

54

Override

1 = Override spanning tree “transmit enable = 0” or“receive enable = 0” setting. This bit is used forspanning tree implementation.
0 = No override.

RO

0

53

Valid

1 = This entry is valid, the look-up result will beused.
0 = This entry is not valid.

RO

0

52-48

These 5 bits control the forward ports.
For example:
00001 = Forward to Port 100010 = Forward to Port 2
Forwarding Ports 00100 = Forward to Port 3
01000 = Forward to Port 4
10000 = Forward to Port 500110 = Forward to Port 2 and Port 3
11111 = Broadcasting (excluding the ingress port)

RO

00000

47-0

MAC Address
(DA)

RO

0x0

63-57

TABLE 4-8:

Name

48-bit MAC address.

FORMAT OF STATIC MAC ADDRESSES FOR WRITES (32 ENTRIES)

Address

Description

Mode

Default

FID

Filter VLAN ID, representing one of the 128 active
VLANs.

W

0000000

Use FID

1 = Use (FID+MAC) to look-up in static table.
0 = Use MAC only to look-up in static table.

W

0

54

Override

1 = Override spanning tree “transmit enable = 0” or“receive enable = 0” setting. This bit is used forspanning tree implementation.
0 = No override.

W

0

53

Valid

1 = This entry is valid, the look-up result will beused.
0 = This entry is not valid.

W

0

62-56
55

Name

 2015 Microchip Technology Inc.

DS00002129C-page 83

KSZ8775CLXTABLE 4-8:

FORMAT OF STATIC MAC ADDRESSES FOR WRITES (32 ENTRIES) (CONTINUED)

AddressName

Description

Mode

Default

W

00000

W

0x0

52-48

Forwarding
Ports

These 5 bits control the forward ports.
For example:
00001 = Forward to Port 100010 = Forward to Port 200100 = Forward to Port 3
01000 = Forward to Port 4
10000 = Forward to Port 500110 = Forward to Port 2 and Port 3
11111 = Broadcasting (excluding the ingress port)

47-0

MAC Address(DA)

48-bit MAC address.

Examples:• Static Address Table Read (read the 2nd entry)
Write to Register 110 with 0x10 (read static table selected)
Write to Register 111 with 0x1 (trigger the read operation)
Then
Read Register 113 (63:56)
Read Register 114 (55:48)
Read Register 115 (47:40)
Read Register 116 (39:32)
Read Register 117 (31:24)
Read Register 118 (23:16)
Read Register 119 (15:8)
Read Register 120 (7:0)• Static Address Table Write (write the 8th entry)
Write Register 113 (62:56)
Write Register 114 (55:48)
Write Register 115 (47:40)
Write Register 116 (39:32)
Write Register 117 (31:24)
Write Register 118 (23:16)
Write Register 119 (15:8)
Write Register 120 (7:0)
Write to Register 110 with 0x00 (write static table selected)
Write to Register 111 with 0x7 (trigger the write operation)

DS00002129C-page 84

 2015 Microchip Technology Inc.

KSZ8775CLX
4.6

VLAN Table

The VLAN table is used for look-up. If 802.1q VLAN mode is enabled (Register 5 bit [7] = 1), this table is used to retrieve
VLAN information that is associated with the ingress packet. There are three fields for filter ID (FID), Valid, and VLAN
membership in the VLAN table. The three fields must be initialized before the table is used. There is no VID field
because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space. Each entry has
four VLANs. Each VLAN has 13 bits. Four VLANs need 52 bits. There are a total of 1024 entries to support a total of4096 VLAN IDs by using dedicated memory address and data bits. Refer to the table below for details. FID has 7 bits
to support 128 active VLANs.

TABLE 4-9:
Address

VLAN TABLE
Name

Description

Mode

Initial Value
Suggestion

R/W

0

R/W

11111

Format of Static VLAN Table (Support Max 4096 VLAN ID entries and 128 Active VLANs)
12

11-7

Valid

1 = The entry is valid.
0 = Entry is invalid.

Specifies which ports are members of the VLAN.
If a DA look-up fails (no match in both static and dynamic tables),Membership the packet associated with this VLAN will be forwarded to the ports
specified in this field.
For example, 11001 means Ports 5, 4, and 1 are in this VLAN.

Filter ID. The KSZ8775CLX supports 128 active VLANs represented by these seven-bit fields. FID is the mapped ID. If 802.1q
6-0
FID
R/W
0
VLAN is enabled, the look-up will be based on FID+DA andFID+SA.
If 802.1q VLAN mode is enabled, the KSZ8775CLX assigns a VID to every ingress packet when the packet is untagged
or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with
non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based on a VID number
with its dedicated memory address and data bits. If the entry is not valid in the VLAN table, the packet is dropped andno address learning occurs. If the entry is valid, the FID is retrieved. The FID+DA and FID+SA lookups in MAC tables
are performed. The FID+DA look-up determines the forwarding ports. If FID+DA fails for look-up in the MAC table, thepacket is broadcast to all the members or specified members (excluding the ingress port) based on the VLAN table. If
FID+SA fails, the FID+SA is learned. To communicate between different active VLANs, set the same FID; otherwise,
set a different FID.
The VLAN table configuration is organized as 1024 VLAN sets. Each VLAN set consists of four VLAN entries to support
up to 4096 VLAN entries. Each VLAN set has 60 bits total and 3 reversed bits are inserted between entries. 52 bits areused for the VLAN set, which should be read or written at the same time specified by the indirect address.
The VLAN entries in the VLAN set are mapped to indirect data registers as follows:• Entry0[12:0] maps to the VLAN set bits [12:0] {Register 119[4:0], Register 120[7:0]}• Entry1[12:0] maps to the VLAN set bits[28:16] {Register 117[4:0], Register 118[7:0]}• Entry2[12:0] maps to the VLAN set bits[44:32] {Register 115[4:0], Register 116[7:0]}• Entry3[12:0] maps to the VLAN set bits[60:48] {Register 113[4:0], Register 114[7:0]}
In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information is extracted. To
update any VLAN entry, the VLAN set is read first, then only the desired VLAN entry is updated and the whole VLAN
set is written back. The FID in the VLAN table is 7 bits, so the VLAN table supports unique 128 flow VLAN groups. Each
VLAN set address is 10 bits long (maximum is 1024) in the Indirect Address Register 110 and 111, the bits [9:8] of VLAN
set address is at bits [1:0] of Register 110, and the bits [7:0] of VLAN set address is at bits [7:0] of Register 111. Eachwrite and read can access up to four consecutive VLAN entries.
Examples:• VLAN Table Read (read the VID = 2 entry)
Write the indirect control and address registers first
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID = 0, 1, 2, 3 entries) 2015 Microchip Technology Inc.

DS00002129C-page 85

KSZ8775CLX
Then read the Indirect Data Registers bits [38:26] for VID = 2 entry
Read Register 115 (0x73), (Register 115 [4:0] are bits [12:8] of VLAN VID = 2 entry)
Read Register 116 (0x74), (Register 116 [7:0] are bits [7:0] of VLAN VID = 2 entry)• VLAN Table Write (write the VID = 10 entry)
Read the VLAN set that contains VID = 8, 9, 10, 11.
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID = 8, 9, 10, 11 indirect address)
Read the VLAN set first by the Indirect Data Registers 113, 114, 115, 116, 117, 118, 119, 120.
Modify the Indirect Data Registers bits [44:32] by the Register 115 bit[4:0] and Register 116 bits [7:0] as follows
Write to Register 115 (0x73), (Register115 [4:0] are bits [12:8] of VLAN VID = 10 entry)
Write to Register 116 (0x74), (Register116 [7:0] are bits [7:0] of VLAN VID = 10 entry)
Then write the indirect control and address Registers
Write to Register 110 (0x6E) with 0x04 (write VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID = 8, 9, 10, 11 indirect address)
Table 4-10 shows the relationship between the indirect address/data registers and the VLAN ID.

TABLE 4-10:

INDIRECT REGISTERS AND VLAN ID

Indirect Address
High/Low bit[9-0] for
VLAN Sets

Indirect Data
Registers bits for
Each VLAN Entry

VID
Numbers

VID bit[12-2] in
VLAN Tag

VID bit[1-0] in
VLAN Tag

0

Bits [12:0]

0

0

0

0

Bits [28:16]

1

0

1

0

Bits [44:32]

2

0

2

0

Bits [60:48]

3

0

3

1

Bits [12:0]

4

1

0

1

Bits [28:16]

5

1

1

1

Bits [44:32]

6

1

2

1

Bits [60:48]

7

1

3

2

Bits [12:0]

8

2

0

2

Bits [28:16]

9

2

1

2

Bits [44:32]

10

2

2

2

Bits [60:48]

11

2

3

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

1023

Bits [12:0]

4092

1023

0

1023

Bits [28:16]

4093

1023

1

1023

Bits [44:32]

4094

1023

2

1023

Bits [60:48]

4095

1023

3

DS00002129C-page 86

 2015 Microchip Technology Inc.

KSZ8775CLX
4.7

Dynamic MAC Address Table

Table 4-11 is read-only.

TABLE 4-11:

DYNAMIC MAC ADDRESS TABLE

AddressName

71

Mac Empty

70-61

60-59

Mode

Default

1 = There are no valid entries in the table.
0 = There are valid entries in the table.

RO

1

Number of
Valid Entries

Indicates how many valid entries in the table.
0x3ff means 1K entries
0x1 and bit [71] = 0: means 2 entries
0x0 and bit [71]= 0: means 1 entry
0x0 and bit [71] = 1: means 0 entry

RO

0Time Stamp

2-bit counters for internal aging

RO

—

58-56

Source PortThe source port where FID+MAC is learned.
000 = Port 1
001 = Port 2010 = Port 3
011 = Port 4
100 = Port 5

RO

0x0

55

Data Ready

1 = The entry is not ready, retry until this bit is set to 0.
0 = The entry is ready.

RO

—

FID

Filter ID.

RO

0x0

RO

0x0

54-48
47-0
Examples:Description

MAC Address 48-bit MAC address.

• Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size
Write to Register 110 with 0x18 (read dynamic table selected)
Write to Register 111 with 0x0 (trigger the read operation) and thenRead Register 112 (71:64)
Read Register 113 (63:56); // the above two registers show # of entries
Read Register 114 (55:48) // if bit [55] is 1, restart (reread) from this register
Read Register 115 (47:40)
Read Register 116 (39:32)
Read Register 117 (31:24)
Read Register 118 (23:16)
Read Register 119 (15:8)
Read Register 120 (7:0)• Dynamic MAC Address Table Read (read the 257th entry), without retrieving # of entries information
Write to Register 110 with 0x19 (read dynamic table selected)
Write to Register 111 with 0x1 (trigger the read operation) and thenRead Register 112 (71:64)
Read Register 113 (63:56)
Read Register 114 (55:48) // if bit [55] is 1, restart (reread) from this register
Read Register 115 (47:40)
Read Register 116 (39:32)
Read Register 117 (31:24)
Read Register 118 (23:16)
Read Register 119 (15:8)
Read Register 120 (7:0)

 2015 Microchip Technology Inc.

DS00002129C-page 87

KSZ8775CLX
4.8

PME Indirect Registers

The EEE registers are provided on global and per port basis. These registers are read/write using indirect memory
access as shown below.

TABLE 4-12:

PME INDIRECT REGISTERS

AddressName

Description

Mode

Default

Global PME Control Register
Register 110 (0x6E) bits [7:5] = 100 for PME, Register 110 bits [3:0] = 0x0 for the indirect global register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x00 (bits [31:24]), 0x01 (bits [23:16]), 0x02 (bit [15:8]), 0x03 (bits [7:0]).
Location: (100 PME) → {0x0, offset} → 0xA0 holds the data.
31-2

Reserved—

RO

All ‘0’1

PME Output Enable

1= PME output pin is enabled.
0= PME output pin is disabled.

R/W

0

0

PME Output Polarity

1= PME output pin is active high.
0= PME output pin is active low.

R/W

0Port PME Control Status Register
Register 110 (0x6E) bits [7:5] = 100 for PME, Register 110 bits [3:0] = 0xn for the Indirect Port Register (n = 1,2,3,4).
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x00 (bits [31:24]), 0x01 (bits [23:16]), 0x02 (bits [5:8]), 0x03 (bits [7:0]).
Location: (100 PME) → {0xn, offset} → 0xA0 holds the data.
31-3

Reserved—

RO

All ‘0’2

Magic Packet Detect

1 = Magic packet is detected at any port
(write 1 to clear).
0 = No magic packet is detected.

R/W
W1C

0

1

Link Up Detect

1 = Link up is detected at any port (write
1 to clear).
0 = No link-up is detected.

R/W
W1C

0

0

Energy Detect

1 = Energy is detected at any port (write
1 to clear).
0 = No energy is detected.

R/W
W1C

0

Port PME Control Mask Register
Register 110 (0x6E) bits [7:5] = 100 for PME, Register 110 bits [3:0] = 0xn for port (n = 1,2,3,4).
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x04 (bits [31:24]), 0x05 (bits [23:16]), 0x06 (bits [15:8]), 0x07 (bits [7:0]).
Location: (100 PME) → {0xn, offset} → 0xA0 holds the data.
31-3

Reserved—

RO

All ‘0’2

Magic Packet Detect
Enable1 = The PME pin will be asserted whena magic packet is detected at hostQMU.
0 = The PME pin will not be asserted by
the magic packet detection.

R/W

0

1

Link Up Detect
Enable1 = The PME pin will be asserted whena link-up is detected at any port.
0 = The PME pin will not be asserted by
the link-up detection.

R/W

0

0

1 = The PME pin will be asserted whenenergy on line is detected at any port.
Energy Detect Enable
0 = The PME pin will not be asserted by
the energy detection.

R/W

0DS00002129C-page 88

 2015 Microchip Technology Inc.

KSZ8775CLX
4.9

Programming Examples

Read Operation
1.

2.
3.

Use the Indirect Access Control Register to select register to be read, to read Global PME Control Register. Write
0x90 to the Register 110 (0x6E) // PME selected and read operation, and 4 MSBs of Port number (Register 110
bits [3:0]) = 0 for the Global PME Register.
Write 0x03 to the Register 111 (0x6F) // trigger the read operation for bits [7:0] of the Global PME Control Register.
Read the Indirect Byte Register 160 (0xA0) // Get the value of the Global PME Control Register.

Write Operation
1.
2.
3.

Write 0x80 to the Register 110 (0x6E) //PME selected and write operation, and 4 MSBs of Port number = 0 for
the Global PME Register.
Write 0x03 to the Register 111 (0x6F) // select write the bits [7:0] of the Global PME Control Address Register.
Write new value to the Indirect Byte Register 160 bits [7:0] (0xA0) //Write value to the Global PME Control Register of the Indirect PME Data Register by the assigned the indirect data register address.

4.10

ACL Rule Table and ACL Indirect Registers

4.10.1

ACL REGISTER AND PROGRAMMING MODEL

The ACL registers are accessible by the microcontroller through a serial interface. The per-port register set is accessed
through the indirect addressing mechanism. The ACL entries are stored in the format shown in the following figure. EachACL rule list table can input up to 16 entries per port. The total of five ACL rule list tables can be set for five ports.

FIGURE 4-2:

ACL TABLE ACCESS

To update any port-based ACL registers, it is suggested to execute a read modify write sequence for each 128-bit entry(112 are used) addressed by the indirect address register to ensure the integrity of control content. A minimum of two
indirect control writes and two indirect control reads are needed for each ACL entry read access (indirect data read shallfollow), and a minimum of one indirect control read and three indirect control writes are required for each ACL entry write
access. Each 112-bit port-based ACL word entry (ACL Word) is accomplished through a sequence of the Indirect

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DS00002129C-page 89

KSZ8775CLX
Access Control 0 Registers 110 (0x6E) access by specifying the bits[3:0] 4-bit port number (indirect address [11:8]) and
8-bit indirect register address (indirect address[7:0]) in the Indirect Access Control 1 Register 111 (0x6F). The address
numbers 0x00-0x0d are used to specify the byte location of each entry (see Figure 15). Address 0x00 indicates the byte
15 (MSB) of each 128-bit entry, address 0x01 indicates the byte 14, etc. Bytes at address 0x0E and 0x0F are reserved
for the future. Address 0x10 and 0x11 hold bit-wise byte enable for each entry. Address 0x12 is used as control andstatus register. The format of these registers is defined in the following section.

4.10.2ACL INDIRECT REGISTERS

The information in this table is used to implement ACL mode selection and per-port filtering.

TABLE 4-13:

TEMPORARY STORAGE FOR 14-BYTES ACL RULES

AddressName

Description

Mode

Default

Port_ACL_0
ACL Port Register 0 (0x00)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x00 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Processing Field
7-4

3-0

Reserved

—

RO

0x0

FRN[3:0]This is for the first rule number of the rule set. There
are a total of 16 entries per port in the ACL rule table.
Each single rule can be set with another rule for a rule
set by the ACL Port Register 12 (0x0c) and Register
13 (0x0d).
Whether using a single rule or rule set, users have toassign an entry for using which Action Field via
FRN[3:0].

R/W

0000

Port_ACL_1
ACL Port Register 1 (0x01)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x01 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields
7-6

5-4

Reserved

—

RO

00

MD[1:0]MODE
00 = Disable the current rule list, no action taken
01 = Qualify rules for Layer 2 MAC header filtering
10 = Used for Layer 3 IP address filtering
11 = Performs Layer 4 TCP port number/protocol filtering

R/W

00

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KSZ8775CLXTABLE 4-13:
Address

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)
Name

Description

Mode

Default

3-2

ENB[1:0]

ENABLE
When MD=01:
00 = The 11 bits from PM, P, REP, MM in action field
specify a count value for packets matching MAC
Address and TYPE in Matching Field.
The count unit is defined in FORWARD field bit [4];Bit [4] = 0, µs is used.
Bit [4] = 1, ms is used.
The FORWARDED field bit [3] determines the algorithm used to generate interrupt when counter terminated. Bit [3] = 0, an 11-bit counter will be loaded withthe count value from the list and start counting down
every unit time. An interrupt will be generated when
expires (i.e., next qualified packet has not been
received within the period specified by the value).
Bit [3] = 1, the counter is incremented every matchedpacket received and the interrupt is generated while
terminal count reached, the count resets thereafter.
01 = MAC address bit field is participating in test.
10 = MAC TYPE bit field is used for test.
11 = Both MAC address and TYPE are tested against
these bit fields in the list.
When MD=10:00 = Reserved.
01 = IP address and mask or IP protocol is enabled to
be tested accordingly.
10 = SA and DA are compared; the drop/forward decision is based on the E/Q bit setting.
11 = Reserved
When MD=11:00 = Protocol comparison is enabled.
01 = TCP/UDP address comparison is selected.
10 = It is same with ‘01’
11 = The sequence number of TCP is compared.

R/W

00

1

S_D

Source/Destination Address
0 = DA is used to compare.
1 = SA is used to compare

R/W

0

0

EQ

Compare Equal
0 = Match if they are not equal.
1 = Match if they are equal.

R/W

0

Port_ACL_2
ACL Port Register 2 (0x02)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits[3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x02 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

MAC_ADDR[47:40] MAC Address

R/W

00000000

Port_ACL_3
ACL Port Register 3 (0x03)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

MAC_ADDR[39:32] MAC Address 2015 Microchip Technology Inc.

R/W

00000000

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KSZ8775CLXTABLE 4-13:

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)

AddressName

Description

Mode

Default

Port_ACL_3
ACL Port Register 3 (0x03)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

MAC_ADDR[39:32] MAC Address

R/W

00000000

Port_ACL_4
ACL Port Register 4 (0x04)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x04 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

MAC_ADDR[31:24] MAC Address

R/W

00000000

Port_ACL_5
ACL Port Register 5 (0x05)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x05 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

MAC_ADDR[23:16] MAC Address

R/W

00000000

Port_ACL_6
ACL Port Register 6 (0x06)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x06 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

MAC_ADDR[15:8]

MAC Address

R/W

00000000

Port_ACL_7
ACL Port Register 7 (0x07)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x07 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

MAC_ADDR[7:0]

MAC Address

R/W

00000000

Port_ACL_8
ACL Port Register 8 (0x08)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x08 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

TYPE[15:8]

Ether Type

R/W

00000000

Port_ACL_9
ACL Port Register 9 (0x09)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 2 (Note 1)
7-0

TYPE[7:0]

Ether Type

R/W

00000000

Note 1: Layer 2, Layer 3, and Layer 4 in matching field should be in different entries. Same layer should be in sameentry. See ACL Format figure for details.

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KSZ8775CLXTABLE 4-13:
Address

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)
Name

Description

Mode

Default

Port_ACL_2
ACL Port Register 2 (0x02)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits[3:0 ] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x02 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 (Note 1)
7-0

IP_ADDR[31:24]

IP Address

R/W

00000000

Port_ACL_3
ACL Port Register 3 (0x03)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 (Note 1)
7-0

IP_ADDR[23:16]

IP Address

R/W

00000000

Port_ACL_4
ACL Port Register 4 (0x04)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x04 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 IP (Note 1)
7-0

IP_ADDR[15:8]

IP Address

R/W

00000000

Port_ACL_5
ACL Port Register 5 (0x05)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x05 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 (Note 1)
7-0

IP_ADDR[7:0]

IP Address

R/W

00000000

Port_ACL_6
ACL Port Register 6 (0x06)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x06 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 (Note 1)
7-0

IP_Mask[31:24]

IP Mask

R/W

00000000

Port_ACL_7
ACL Port Register 7 (0x07)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x07 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 (Note 1)
7-0

IP_Mask[23:16]

IP Mask

R/W

00000000

Port_ACL_8
ACL Port Register 8 (0x08)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x08 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 (Note 1)
7-0

IP_Mask[15:8]

 2015 Microchip Technology Inc.

IP Mask

R/W

00000000

DS00002129C-page 93

KSZ8775CLXTABLE 4-13:

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)

AddressName

Description

Mode

Default

Port_ACL_9
ACL Port Register 9 (0x09)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 3 (Note 1)
7-0

IP_Mask[7:0]

IP Mask

R/W

7-0

Port_ACL_2
ACL Port Register 2 (0x02)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits[3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x02 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 4 (Note 1)
7-0

MAX Port[15:8]

For range of TCP port number or sequence number
matching

R/W

00000000

Port_ACL_3
ACL Port Register 3 (0x03)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 4 (Note 1)
7-0

MIN Port[7:0]

For range of TCP port number or sequence number
matching

R/W

00000000

Port_ACL_4
ACL Port Register 4 (0x04)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x04 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 4 (Note 1)
7-3

Reserved

Reserved

RO

00000

2-1

PC [1:0]00 = The port comparison is disabled.
01 = Matching either one of MAX or MIN.
10 = Match if the port number is in the range of MAX
and MIN.
11 = Match if the port number is out of the range

R/W

00

0

PRO[7]For the IP protocol to be matched—

0

Port_ACL_5
ACL Port Register 5 (0x05)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x05 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 4 (Note 1)
7-1

PRO[6:0]

For the IP protocol to be matched

R/W

0000000

FME

Flag Match Enable
0 = Disable TCP FLAG matching
1 = Enable TCP FLAG matching

R/W

0

0

Port_ACL_6
ACL Port Register 6 (0x06)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x06 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} →0xA0 holds the data.
Matching Fields for Layer 4 (Note 1)

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KSZ8775CLXTABLE 4-13:

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)

Address
7-0

Name
FMSK[7:0]

Description
TCP FLAG Mask

Mode

Default

R/W

00000000

Port_ACL_7
ACL Port Register 7 (0x07)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x07 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Matching Fields for Layer 4 (Note 1)
7-0

FLAG[7:0]

TCP FLAG

R/W

00000000

Port_ACL_8
ACL Port Register 8 (0x08)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x08 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
7-0

Reserved

Reserved

RO

00000000

ACL Port Register 9 (0x09)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
7-0
Reserved
Reserved
RO

00000000

Port_ACL_9

Port_ACL_A
ACL Port Register 10 (0x0A)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x0A to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Action Field

7-6

PM[1:0]Priority Mode
00 = No priority is selected; the priority determined by
QoS. Classification is used in the tagged packets.
01 = Priority in P [2:0] bits field is used if it is greaterthan QoS result in the 3-bit priority field of the tagged
packets received.
10 = Priority in P [2:0] bits field is used if it is smaller
than QoS result in the 3-bit priority field of the tagged
packets received.
11 = P [2:0] bits field will replace the 3-bit priority fieldof the tagged packets received.

5-3

P[2:0]

Priority
Note: The 3-bit priority value to be used depends on
PM [1:0] setting in bits [7:6].

R/W

000

RPE

Remark Priority Enable
0 = No remarking is necessary.
1 = VLAN priority bits in the packets are replaced by
RP [2:1] bits field below in the list.

R/W

0

RP[2:1]

Remark Priority
00 = Priority 0
01 = Priority 1
10 = Priority 2
11 = Priority 3

R/W

00

2

1-0

 2015 Microchip Technology Inc.

R/W

00

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KSZ8775CLXTABLE 4-13:

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)

AddressName

Description

Mode

Default

Port_ACL_B
ACL Port Register 11 (0x0B)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x0B to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Action Field
7

6-5

4-0

RP[0]

Remark Priority

R/W

0

MM[1:0]

Map Mode
00 = No forwarding remapping is necessary. Don’t
use the forwarding map in FORWARD field, use theforwarding map from the look-up table only.
01 = The forwarding map in FORWARD field is OR’ed
with the forwarding map from the look-up table.
10 = The forwarding map in FORWARD field isAND’ed with the forwarding map from the look-up
table.
11 = The forwarding map in FORWARD field replaces
the forwarding map from the look-up table.

R/W

00

FORWARD[4:0]Port Map
Each bit indicates forwarding decision of one port.
Bit [0] = Port 1
Bit [1] = Port 2
Bit [2] = Port 3
Bit [3] = Port 4
Bit [4] = Port 5
When MD=01 and ENB=00,
Bit [4] is used as count unit:
0 = µs
1 = msBit [3] is used to select count modes:
0 = Count down in the 11-bit counter from an assigned
value in the action field PM, P, RPE, RP and MM, aninterrupt will be generated when expired.
1= Count up in the 11-bit counter for every matchedpacket received up to reach an assigned value in theaction field PM, P, RPE, RP and MM, and then aninterrupt will be generated.
Note: See ENB field description for detail.

R/W

Port_ACL_C
ACL Port Register 12 (0x0C)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x0C to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Processing Field
7-0

RULESET[15:8]

DS00002129C-page 96

Each bit indicates this entry in bits 0 to 16, total 16
entries of the rule list can be assigned for the rule set
to be used in the rules cascade per port.

R/W

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KSZ8775CLXTABLE 4-13:

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)

AddressName

Description

Mode

Default

Port_ACL_D
ACL Port Register 13 (0x0D)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x0D to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
Processing Field
7-0

RULESET[7:0]

Each bit indicates this entry in bits [0-15] 16 entries of
the rule list to be assigned for the rule set to be usedin the rules cascade per port.

R/W

00000000

Port_ACL_BYTE_ENB_MSB
ACL Port Register 14 (0x10)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, and 4.
Register 111 (0x6F) bits [7:0] = Offset 0x10 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
7-6

Reserved

—

RO

00

R/W

0

Byte Enable in ACL table; 14 bytes per entry
1 = Byte is selected for read/write
0 = Byte is not selected
5-0

BYTE_ENB[13:8]

Bit [0] of BYTE_ENB[13:0] is for byte address 0x0D
in ACL table entry
Bit [1] of BYTE_ENB[13:0] is for byte address 0x0C
in ACL table entry
Bit [13] of BYTE_ENB[13:0] is for byte address 0x00
in ACL table entry

Port_ACL_ BYTE_ENB_LSB
ACL Port Register 15 (0x11)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x11 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.

7-0

BYTE_ENB[7:0]

Byte Enable in ACL table; 14 bytes per entry
1 = Byte is selected for read/write
0 = Byte is not selected
Bit [0] of BYTE_ENB[13:0] is for byte address 0x0D in
ACL table entry
Bit [1] of BYTE_ENB[13:0] is for byte address 0x0C in
ACL table entry
Bit [13] of BYTE_ENB[13:0] is for byte address 0x00
in ACL table entry.

R/W

7-0

Port_ACL_ACCESS_CONTROL1
ACL Port Register 16 (0x12)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x12 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
7

Reserved

N/A Don’t change

RO

0

6

WRITE_STATUS

Write Operation Status
1 = Write completed
0 = Write is in progress

RO

1

5

READ_STATUS

Read Operation Status
1 = Read completed
0 = Read is in progressRO1

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KSZ8775CLXTABLE 4-13:

TEMPORARY STORAGE FOR 14-BYTES ACL RULES (CONTINUED)

AddressName

Description

Mode

Default

4

WRITE_READ

Request Type
1 = Write
0 = Read

R/W

0

3-0

ACL_ENTRY_ADDRESSACL Entry Address
0000= entry 0.
0001= entry 11111= entry 15.

R/W

0000

Port_ACL_ ACCESS_CONTROL2
ACL Port Register 17 (0x13)
Register 110 (0x6E) bits [7:5] = 010 for ACL, Register 110 bits [3:0] = 0xn for Port 1, 2, 3, 4, and 5.
Register 111 (0x6F) bits [7:0] = Offset 0x13 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) → {0xn, offset} → 0xA0 holds the data.
7-1

Reserved

N/A Don’t change0

1 = DLR filtering uses single ACL entry. DLR packet
Force Device Level matching the ACL entry will be considered as MISS
Redundancy (DLR) 0 = DLR filtering uses multiple ACL entries. DLRMiss
packet matching the rule set for DLR packet will beconsidered as HIT.

RO

0000000

R/W

0

The ACL registers can be programmed using the read/write examples below.
Examples:Read Operation• Use the Indirect Access Control Register to select register to be read. To read Entry0 that is 1st entry of Port 1:
Write 0x41 to Register 110 (0x6E) // select ACL and write to Port 1 (Port 2, 3, 4 and 5 are 0x42, 0x43, 0x44 and 0x45)
Write 0x10 to Register 111 (0x6F) // trigger the write operation for Port 1 in the ACL Port Register 14 (Byte Enable MSB
register) address.
Write 0x3F into the Indirect Byte Register 160 (0xA0) for MSB of Byte Enable word.
Write 0x41 to Register 110 (0x6E) // select write to Port 1.
Write 0x11 to Register 111 (0x6F) // trigger the write operation for Port 1 in the ACL Port Register 15 (Byte Enable LSB
Register) address. (The above 2 may be part of burst).
Write 0xFF into the Indirect Byte Register 160 (0xA0) for LSB of Byte Enable word.
(The above steps set Byte Enable Register to select all bytes in ACL word from 0x00-0x0d in ACL table entry)
Write 0x41 to Register 110 (0x6E) //select ACL and write operations to Port 1.
Write 0x12 to Register 111 (0x6F) //Write ACL read/write control register address 0x12 to the indirect address in Register
111 to trigger the read operation for Port 1 in the ACL Port Register 16 (ACL Access Control Register) to read entry 0.
Write 0x00 into the Indirect Byte Register 160 (0xA0)//ACL Port Register 16 (0x12) bit[4]=0 to read ACL and bits [3:0] =0x0 for entry 0.
(The above steps set ACL control register to read ACL entry word 0).
Write 0x51 to Register 110 (0x6E) //select ACL and read to Port 1 (Port 2, 3, 4 and 5 are 0x52, 0x53, 0x54 and 0x55).
Write 0x12 to Register 111 (0x6F) //trigger the read operation for Port 1 in the ACL Port Register16 (ACL Access Control
1).
Read the Indirect Byte Register 160 (0xA0) to get data (If bit [5] is set, the read completes in the ACL port Register 16(0x12) and go to next step. Otherwise, repeat the above polling step).
Write 0x51 to Register 110 (0x6E) // select read to Port 1.
Write 0x00 to Register 111 (0x6F) // trigger the read/burst read operation(s) based on the Byte Enable Register settingby the Port 1 ACL access Register 0 (0x00).
Read/Burst read the Indirect Byte Register 160 (0xA0) // to get data of ACL entry word 0, write 0x00 to 0x0D indirect
address and read Register 160 (0xA0) after each byte address write to Register 111 (0x6F).

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KSZ8775CLX
Write Operation• Use the Indirect Access Control Register to select register to be written. To write even byte number of 15th entry ofPort 5:
Write 0x55 to Register 110 (0x6E) // select ACL and read to Port 5.
Write 0x12 to Register 111 (0x6F) // trigger the read operation for Port 5 ACL Access Control Register read.
Read the Indirect Byte Register 160 (0xA0) to get data (If bit [6] is set, the previous write completes and go to next step.
Otherwise, repeat the above polling step).
Write 0x45 to Register 110 (0x6E) // select ACL and write to Port 5.
Write 0x00 to Register 111 (0x6F) //set offset address for Port 5 ACL Port Register 0.
Write/Burst write the Indirect Byte Register 160 (0xA0) for ACL Port Register 0, 1, 2, …,13 from 0x00 to 0x0D) (Write or
Burst write even bytes of Port 5 ACL access Registers 0, 1, …, 13 to holding buffer).
Write 0x45 to Register 110 (0x6E) // select ACL and write to Port 5.
Write 0x10 to Register 111 (0x6F) // trigger the write operation for Port 5 in the ACL Port Register 14 (Byte Enable MSB
register).
Write 0x15 into the Indirect Byte Register 160 (0xA0) for MSB of Byte Enable word to enable odd bytes address 0x01,
0x03 and 0x05.
Write 0x45 to Register 110 (0x6E) // select write to Port 5.
Write 0x11 to Register 111 (0x6F) // trigger the write operation for Port 5 in the ACL Port Register 15 (Byte Enable LSB
register).
Write 0x55 into the Indirect Byte Register 160 (0xA0) for LSB of Byte Enable word to enable odd bytes address 0x07,
0x09, 0x0B and 0x0D.
(The above steps set Byte Enable register to select odd address bytes in ACL word)
Write 0x45 to Register 110 (0x6E) // select write to Port 5.
Write 0x12 to Register 111 (0x6F) // write the port ACL access control register address (0x12) to the Indirect Address
Register 111 for setting the write operation to Port 5 in the ACL Port Register 16 to write entry 15 bytes 1, 3, 5…,13.
Write 0x1F into the Indirect Byte Register 160 (0xA0) // for the write operation to 15th entry in the ACL Port Register 16(0x12) bit4=1 to write ACL, bits [3:0] = 0xF to write entry 15.
(The above steps set ACL Control Register to write ACL entry word 15 from holding buffer)
The bit arrangement of above example assumes Layer 2 rule of MODE = 01 in ACL Port Register 1 (0x01), refer to ACL
format for MODE = 10 and 11.

4.11

EEE Indirect Registers

The EEE function is for all copper ports only. The EEE registers are provided on global and per port basis. These registers are read/write using indirect memory access as shown in Table 4-14.

TABLE 4-14:
Address

EEE GLOBAL REGISTERS
Name

Description

Mode

Default

EEE Global Register 0
Global EEE QM Buffer Control Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0x0 for the indirect global register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x30 (bits [15:8]), 0x31 (bits [7:0])
Location: (001 EEE) → {0x0, offset} → 0xA0 holds the data.
15-8

Reserved

N/A Don’t change

RO

0x40

7

Low Power Idle (LPI)
Terminated By Input
Traffic Enable

1 = LPI request will be stopped if input traffic is
detected.
0 = LPI request won’t be stopped by input traffic.

R/W

0

6-0

Reserved

N/A Don’t change

RO

0x10

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KSZ8775CLXTABLE 4-14:

EEE GLOBAL REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

EEE Global Register 1
Global Empty TXQ to LPI Wait Time Control Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0x0 for the indirect global register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x32 (bits [15:8]), 0x33 (bits [7:0])
Location: (001 EEE) → {0x0, offset} → 0xA0 holds the data.

15-0

Empty TXQ to LPI Wait
Time

This register specifies the time that the LPI
request will be generated after a TXQ has been
empty exceeds this configured time. This is only
valid when EEE 100BT is enabled. This setting
will apply to all the ports. The unit is 1.3 ms. The
default value is 1.3 sec. (range from 1.3 ms to
86 second)

R/W

0x10

EEE Global Register 2
Global EEE PCS DIAGNOSTIC Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0x0 for the indirect global register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x34(bits [15:8]), 0x35 (bits [7:0])
Location: (001 EEE) → {0x0, offset} → 0xA0 holds the data.
15-12

Reserved

N/A Don’t change

RO

0x6

11-8

Reserved

N/A Don’t change

RO

0x8

7-4

Reserved

N/A Don’t change

RO

0x0

3

1 = Enable next page exchange during autonegotiation.
Port 4 Next Page Enable
0 = Skip next page exchange during auto-negotiation.

R/W

1

2

1 = Enable next page exchange during autonegotiation.
Port 3 Next Page Enable
0 = Skip next page exchange during auto-negotiation.

R/W

1

1

1 = Enable next page exchange during autonegotiation.
Port 2 Next Page Enable
0 = Skip next page exchange during auto-negotiation.

R/W

1

0

1 = Enable next page exchange during autonegotiation.
Port 1 Next Page Enable
0 = Skip next page exchange during auto-negotiation.

R/W

1

EEE Global Register 3
Global EEE Minimum LPI cycles before back to Idle Control Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0x0 for the indirect global register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x36 (bits [15:8], 0x37 (bits [7;0]Location: (001 EEE) → {0x0, offset} → 0xA0 holds the data.
15-0

Reserved

N/A Don’t changeRO

0x0000EEE Global Register 4
Global EEE Wakeup Error Threshold Control Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0x0 for the indirect global register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x38 (bits [15:8]), 0x39 (bits [7;0])
Location: (001 EEE) → {0x0, offset} → 0xA0 holds the data.

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KSZ8775CLXTABLE 4-14:
Address

15-0

EEE GLOBAL REGISTERS (CONTINUED)
Name

Description

Mode

Default

EEE Wakeup Threshold

This value specifies the maximum time allowed
for PHY to wake up.
If wakeup time is longer than this, EEE wakeup
error count will be incremented.
Note: This is an EEE standard, don’t change.

RO

0x0201EEE Global Register 5
Global EEE PCS Diagnostic Control Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0x0 for the indirect global register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x3A (bits [15:8]), 0x3B (bits [7:0])
Location: (001 EEE) → {0x0, offset} → 0xA0 holds the data.
15-0

TABLE 4-15:
Address

Reserved

N/A Don’t changeRO

0x0001

Mode

Default

EEE PORT REGISTERS
Name

Description

EEE Port Register 0
Port Auto-Negotiation Expansion Status Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0xn, n = 3-4 for the Indirect Port Register ,Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x0C (bits [15:8]), 0x0D (bits [7:0])
Location: (001 EEE) → {0xn, offset} → 0xA0 holds the data.
15-7

Reserved

N/A Don’t change

RO

9h000

6

Receive Next Page
Location Able

1 = Received Next Page storage location is
specified by bits [6:5]
0 = Received Next Page storage location is not
specified by bits [6:5]

RO

1

5

Received Next Page
Storage Location

1 = Link Partner Next Pages are stored in MIIM
Register 8h (Additional next page)
0 = Link Partner Next Pages are stored in MIIM
Register 5h

RO

1

4

Parallel Detection Fault

1 = A fault has been detected via the Parallel
Detection function.
0 = A fault has not been detected via the Parallel
Detection function.
This bit is cleared after reading.

R/LH

0

3

Link Partner Next Page
Able

1 = Link Partner is Next Page abled
0 = Link Partner is not Next Page abled

RO

0

2

Next Page Able

1 = Local Device is Next Page abled
0 = Local Device is not Next Page abled

RO

1

1

Page Received

1 = A New Page has been received
0 = A New Page has not been received

R/LH

0

0

Link Partner Auto-Nego- 1 = Link Partner is Auto-Negotiation abled
tiation Able
0 = Link Partner is not Auto-Negotiation abled

RO

0

EEE Port Register 1
Port Auto-Negotiation Next Page Transmit Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0xn, n = 3-4 for the Indirect Port Register ,Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x0E (bits [15:8]), 0x0F (bits [7:0])
Location: (001 EEE) → {0xn, offset} → 0xA0 holds the data.
This register doesn’t need to be set if EEE Port Register 5 bit[7] = 1 default for automatically perform EEE capability 2015 Microchip Technology Inc.

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KSZ8775CLXTABLE 4-15:

EEE PORT REGISTERS (CONTINUED)

AddressName

Description

Mode

Default

R/W

0

15

Next Page

Next Page (NP) is used by the Next Page function to indicate whether or not this is the last
Next Page to be transmitted. NP shall be set as
follows:
1 = Additional Next Page(s) will follow.
0 = Last page.

14

Reserved

Reserved

RO

0

Message Page

Message Page (MP) is used by the Next Page
function to differentiate a Message Page from an
Unformatted Page. MP shall be set as follows:
1 = Message Page
0 = Unformatted Page

R/W

1

Acknowledge 2

Acknowledge 2 (Ack2) is used by the Next Page
function to indicate that a device has the ability
to comply with the message. Ack2 shall be set
as follows:
1 = Will comply with message.
0 = Cannot comply with message.

R/W

0

11

ToggleToggle (T) is used by the Arbitration function toensure synchronization with the Link Partner
during Next Page exchange. This bit shallalways take the opposite value of the Toggle bitin the previously exchanged Link Codeword.
The initial value of the Toggle bit in the first Next
Page transmitted is the inverse of bit [11] in thebase Link Codeword and, therefore, may
assume a value of logic one or zero. The Toggle
bit shall be set as follows:
1 = Previous value of the transmitted Link Codeword equal to logic zero.
0 = Previous value of the transmitted Link Codeword equal to logic one.

RO

0

10-0

Message/Unformatted
Code Field

Message/Unformatted Code field bits [10:0]

R/W

10-0

13

12

EEE Port Register 2
Port Auto-Negotiation Link Partner Next Page Receive Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0xn, n = 3-4 for the indirect port register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x10 (bits [15:8]), 0x11 (bits [7:0])
Location: (001 EEE) → {0xn, offset} → 0xA0 holds the data.

15

Next Page

DS00002129C-page 102

Next Page (NP) is used by the Next Page function to indicate whether or not this is the last
Next Page to be transmitted. NP shall be set as
follows:
1 = Additional Next Page(s) will follow.
0 = Last page.

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KSZ8775CLXTABLE 4-15:

EEE PORT REGISTERS (CONTINUED)

Address

Description

Mode

Default

Acknowledge

Acknowledge (Ack) is used by the Auto-Negotiation function to indicate that a device has successfully received its Link Partner’s Link
Codeword. The Acknowledge Bit is encoded in
bit D14 regardless of the value of the Selector
Field or Link Codeword encoding. If no Next
Page information is to be sent, this bit shall be
set to logic one in the Link Codeword after the
reception of at least three consecutive and consistent FLP Bursts (ignoring the Acknowledge bit
value).

RO

0

Message Page

Message Page (MP) is used by the Next Page
function to differentiate a Message Page from an
Unformatted Page. MP shall be set as follows:
1 = Message Page
0 = Unformatted Page

RO

0

Acknowledge 2

Acknowledge 2 (Ack2) is used by the Next Page
function to indicate that a device has the ability
to comply with the message. Ack2 shall be set
as follows:
1 = Will comply with message.
0 = Cannot comply with message.

RO

0

11

ToggleToggle (T) is used by the Arbitration function toensure synchronization with the Link Partner
during Next Page exchange. This bit shallalways take the opposite value of the Toggle bitin the previously exchanged Link Codeword.
The initial value of the Toggle bit in the first Next
Page transmitted is the inverse of bit [11] in thebase Link Codeword and, therefore, may
assume a value of logic one or zero. The Toggle
bit shall be set as follows:
1 = Previous value of the transmitted Link Codeword equal to logic zero.
0 = Previous value of the transmitted Link Codeword equal to logic one.

RO

0

10-0

Message/Unformatted
Code Field

Message/Unformatted Code field bits [10:0]

RO

0

14

13

12

Name

EEE Port Register 3
Link Partner EEE Capability Status and Local Device EEE Capability Advisement Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0xn, n = 3-4 for the Indirect Port Register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x28 (bits [15:8]), 0x29 (bits [7:0])
Location: (001 EEE) → {0xn, offset} → 0xA0 holds the data.
15

Reserved

N/A Don’t change

RO

0

14

Link Partner (LP)
10GBASE-KR EEE

1 = EEE is supported for 10GBASE-KR
0 = EEE is not supported for 10GBASE-KR

RO

0

13

LP 10GBASE-KX4 EEE

1 = EEE is supported for 10GBASE-KX4
0 = EEE is not supported for 10GBASE-KX4

RO

0

12

LP 1000BASE-KX EEE

1 = EEE is supported for 1000BASE-KX
0 = EEE is not supported for 1000BASE-KX

RO

0

11

LP 10GBASE-T EEE

1 = EEE is supported for 10GBASE-T
0 = EEE is not supported for 10GBASE-T

RO

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KSZ8775CLXTABLE 4-15:

EEE PORT REGISTERS (CONTINUED)

AddressName

10

LP 1000BASE-T EEE

9Description

Mode

Default

1 = EEE is supported for 1000BASE-T
0 = EEE is not supported for 1000BASE-T

RO

0

LP 100BASE-TX EEE

1 = EEE is supported for 100BASE-TX
0 = EEE is not supported for 100BASE-TX

RO

0

8-2

Reserved

Reserved

RO

7h’0

1

1 = EEE is supported for 100BASE-TX
0 = EEE is not supported for 100BASE-TX
Local 100BASE-TX EEE
Note: This is for local port to support EEE capability

R/W

1

0

ReservedRO

0

N/A Don’t change

EEE Port Register 4
Port EEE Wake Up Error Count Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0xn, n = 3-4 for the Indirect Port Register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x2A (bits [15:8]), 0x2B (bits [7:0])
Location: (001 EEE) → {0xn, offset} → 0xA0 holds the data.

15-0

EEE Wakeup Error
CounterThis count is incremented by one whenever a
wakeup from LPI to Idle state is longer than the
Wake-Up error threshold time specified in EEE
Global Register 4. The default of Wake-Up error
threshold time is 20.5 µs. This register is readclearedRO

0x0000EEE Port Register 5
Port EEE Control Register
Register 110 (0x6E) bits [7:5]=001 for EEE, Register 110 bits [3:0] = 0xn, n = 3-4 for the Indirect Port Register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x2C (bits [15:8]), 0x2D (bits [7:0])
Location: (001 EEE) → {0xn, offset} → 0xA0 holds the data.
15

10BT EEE Disable

1 = 10BT EEE mode is disabled
0 = 10BT EEE mode is enabled
Note: 10BT EEE mode saves power by reducing signal amplitude only.

14-8

Reserved

N/A Don’t change

R/W

1

RO

7h’0

7

1 = H/W will automatically perform EEE capability exchange with Link Partner through next
page exchange. EEE 100BT enable (bit [0] of
H/W-Based EEE NP
this register). Will be set by H/W if EEE capabilAuto-Negotiation Enable
ity is matched.
0 = H/W based EEE capability exchange is off.
EEE capability exchange is done by software.

R/W

1

6

1 = 100BT EEE is enabled by H/W-based NP
H/W 100BT EEE Enable
exchange
Status0 = 100BT EEE is disabled

R

0

R/RC

0

5

TX LPI Received

DS00002129C-page 104

1 = Indicates that the transmit PCS has
received low power idle signaling one or moretimes since the register was last read.
0 = Indicates that the PCS has not received low
power idle signaling.
This bit is cleared after reading.

 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-15:

EEE PORT REGISTERS (CONTINUED)

Address

4

3

2

1

0

Name

Description

Mode

Default

TX LPI Indication

1 = Indicates that the transmit PCS is currently
receiving low power idle signals.
0 = Indicates that the PCS is not currently
receiving low power idle signals.

R

0

RX LPI Received

1 = Indicates that the receive PCS has received
low power idle signaling one or more times since
the register was last read.
0 = Indicates that the PCS has not received low
power idle signaling.
This bit is cleared after reading.

R/RC

0

RX LPI Indication

1 = Indicates that the receive PCS is currently
receiving low power idle signals.
0 = Indicates that the PCS is not currently
receiving low power idle signals.

R

0

EEE SW Mode Enable

1 = EEE is enabled through S/W setting bit [0] of
this register.
0 = EEE is enabled through H/W auto-negotiation

R/W

0

EEE SW 100BT Enable

1 = EEE 100BT is enabled
0 = EEE 100BT is disabled
Note: This bit could be set by S/W or H/W if H/
W-based EEE Next Page auto-negotiation
enable is on.

R/W

0

EEE Port Register 6
Port EEE LPI Recovery Time Register
Register 110 (0x6E) bits [7:5] = 001 for EEE, Register 110 bits [3:0] = 0xn, n = 3-4 for the Indirect Port Register,
Register 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x2E (bits [15:8]), 0x2F (bits [7:0])
Location: (001 EEE) → {0xn, offset} → 0xA0 holds the data.
15-8

7-0

Reserved

Reserved

RO

15-8

LPI Recovery Counter

This register specifies the time that the MAC
device has to wait before it can start sending out
packets. This value should be the maximum of
the LPI recovery time between local device andremote device.
The unit is 640 ns.
The default is about 25 µs = 39 (0x27) × 640 ns
Note: This value can be adjusted if the PHY
recovery time is less than the standard 20.5 µs
for the packets to be sent out quickly from EEE
LPI mode.

R/W

7-0

Programming Examples
Read Operation• Use the Indirect Access Control Register to select register to be read, to read the EEE Global Register 0 (Global
EEE QM Buffer Control Register).
Write 0x30 to the Register 110 (0x6E) // EEE selected and read operation, and 4 MSBs of Port number = 0 for the
global register.
Write 0x30 to the indirect Register 111 (0x6F) // trigger the read operation and ready to read the EEE Global Register 0 bits [15:8].
Read the Indirect Byte Register 160 (0xA0) //Get the bits [15:8] value of the EEE Global Register 0.

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KSZ8775CLX
Write Operation• Write 0x20 to Register 110 (0x6E) // EEE selected and write operation, 4 MSBs of Port number = 0 is for global
register.
Write 0x31 to Register 111 (0x6F) // select the offset address, ready to write the EEE Global Register 0 bits [7:0].
Write new value to the Indirect Byte Register 160 (0xA0) bits [7:0].

4.12

Management Information Base (MIB) Counters

The MIB counters are provided on a per port basis. These counters are read using indirect memory access as indicatedin Table 4-16.

TABLE 4-16:

PORT 1 MIB COUNTER INDIRECT MEMORY OFFERS

OFFSET

Counter Name

Description

0x0

RxHiPriorityByte

RX hi-priority octet count including bad packets.

0x1

RxUndersizePkt

RX undersize packets w/good CRC.

0x2

RxFragments

RX fragment packets w/bad CRC, symbol errors or alignment errors.

0x3

RxOversize

RX oversize packets w/good CRC (max: 1536 or 1522 bytes).

0x4

RxJabbers

RX packets longer than 1522 bytes w/either CRC errors, alignment
errors, or symbol errors (depends on max packet size setting) or RX
packets longer than 1916 bytes only.

0x5

RxSymbolError

RX packets w/ invalid data symbol and legal preamble, packet size.

0x6

RxCRCerror

RX packets within (64,1522) bytes w/an integral number of bytes anda bad CRC (upper limit depends on max packet size setting).

0x7

RxAlignmentError

RX packets within (64,1522) bytes w/a non-integral number of bytes
and a bad CRC (upper limit depends on max packet size setting).

0x8

RxControl8808Pkts

The number of MAC control frames received by a port with 88-08h in
EtherType field.

0x9

RxPausePkts

The number of PAUSE frames received by a port. PAUSE frame isqualified with EtherType (88-08h), DA, control opcode (00-01), data
length (64 byte min), and a valid CRC.

0xA

RxBroadcast

RX good broadcast packets (not including errored broadcast packets
or valid multicast packets).

0xB

RxMulticast

RX good multicast packets (not including MAC control frames,
errored multicast packets or valid broadcast packets).

0xC

RxUnicast

RX good unicast packets.

0xD

Rx64Octets

Total RX packets (bad packets included) that were 64 octets inlength.

0xE

Rx65to127Octets

Total RX packets (bad packets included) that are between 65 and127 octets in length.

0xF

Rx128to255Octets

Total RX packets (bad packets included) that are between 128 and255 octets in length.

0x10

Rx256to511Octets

Total RX packets (bad packets included) that are between 256 and511 octets in length.

0x11

Rx512to1023Octets

Total RX packets (bad packets included) that are between 512 and1023 octets in length.

0x12

Rx1024to1522Octets

Total RX packets (bad packets included) that are between 1024 and1522 octets in length.

0x13

Rx1523to2000Octets

Total RX packets (bad packets included) that are between 1523 and2000 octets in length.

0x14

Rx2001toMax-1Octets

Total RX packets (bad packets included) that are between 2001 andMax-1 octets in length (upper limit depends on max packet size -1).

0x15

TxHiPriorityByte

TX hi-priority good octet count, including PAUSE packets.

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KSZ8775CLXTABLE 4-16:
OFFSET

PORT 1 MIB COUNTER INDIRECT MEMORY OFFERS (CONTINUED)Counter Name

Description
The number of times a collision is detected later than 512 bit-times
into the TX of a packet.

0x16

TxLateCollision

0x17

TxPausePkts

The number of PAUSE frames transmitted by a port.

0x18

TxBroadcastPkts

TX good broadcast packets (not including errored broadcast or valid
multicast packets).

0x19

TxMulticastPkts

TX good multicast packets (not including errored multicast packets orvalid broadcast packets).

0x1A

TxUnicastPkts

TX good unicast packets.

0x1B

TxDeferred

TX packets by a port for which the first TX attempt is delayed due tothe busy medium.

0x1C

TxTotalCollision

TX total collision, half-duplex only.

0x1D

TxExcessiveCollision

A count of frames for which TX fails due to excessive collisions.

0x1E

TxSingleCollision

Successfully transmits frames on a port for which TX is inhibited byexactly one collision.

0x1F

TxMultipleCollision

Successfully transmits frames on a port for which TX is inhibited bymore than one collision.

For Port 2, the base is 0x20, same offset definition (0x20-0x3f)
For Port 3, the base is 0x40, same offset definition (0x40-0x5f)
For Port 4, the base is 0x60, same offset definition (0x60-0x7f)
For Port 5, the base is 0x80, same offset definition (0x80-0x9f)

TABLE 4-17:

FORMAT OF PER-PORT MIB COUNTERS

AddressName

Description

Mode

Default

38

Overflow

1 = Counter overflow.
0 = No Counter overflow.

RO

0

37

Count Valid

1 = Counter value is valid.
0 = Counter value is not valid.

RO

0

36-30

Reserved

N/A No changeROAll ‘0’29-0Counter Values

Counter value.

RO

0

TABLE 4-18:

ALL PORT-DROPPED PACKET MIB COUNTERS

OffsetCounter Name

0x100

Port1 RX Total Bytes

Port 1 RX total octet count, including bad packets.

0x101

Port1 TX Total Bytes

Port 1 TX total good octet count, including PAUSE packets.

0x102

Port1 RX Drop Packets

Port 1 RX packets dropped due to lack of resources.

0x103

Port1 TX Drop Packets

Port 1 TX packets dropped due to lack of resources.

0x104

Port2 RX Total Bytes

Port 2 RX total octet count, including bad packets.

0x105

Port2 TX Total Bytes

Port 2 TX total good octet count, including PAUSE packets.

0x106

Port2 RX Drop Packets

Port 2 RX packets dropped due to lack of resources.

0x107

Port2 TX Drop Packets

Port 2 TX packets dropped due to lack of resources.

0x108

Port3 RX Total Bytes

Port 3 RX total octet count, including bad packets.

0x109

Port3 TX Total Bytes

Port 3 TX total good octet count, including PAUSE packets.

0x10A

Port3 RX Drop Packets

Port 3 RX packets dropped due to lack of resources.

0x10B

Port3 TX Drop Packets

Port 3 TX packets dropped due to lack of resources.

 2015 Microchip Technology Inc.

Description

DS00002129C-page 107

KSZ8775CLXTABLE 4-18:

ALL PORT-DROPPED PACKET MIB COUNTERS (CONTINUED)

OffsetCounter Name

0x10C

Port4 RX Total Bytes

Port 4 RX total octet count, including bad packets.

0x10D

Port4 TX Total Bytes

Port 4 TX total good octet count, including PAUSE packets.

0x10E

Port4 RX Drop Packets

Port 4 RX packets dropped due to lack of resources.

0x10F

Port4 TX Drop Packets

Port 4 TX packets dropped due to lack of resources.

0x110

Port5 RX Total Bytes

Port 5 RX total octet count, including bad packets.

0x111

Port5 TX Total Bytes

Port 5 TX total good octet count, including PAUSE packets.

0x112

Port5 RX Drop Packets

Port 5 RX packets dropped due to lack of resources.

0x113

Port5 TX Drop Packets

Port 5 TX packets dropped due to lack of resources.

TABLE 4-19:

Description

FORMAT OF PER-PORT TOTAL RX/TX BYTES MIB COUNTERS

AddressName

Description

Mode

Default

38

Overflow

1 = Counter overflow.
0 = No Counter overflow.

RO

0

37

Count Valid

1 = Counter value is valid.
0 = Counter value is not valid.

RO

0

36

Reserved

N/A No change

RO

0

35-0

Counter Values

Counter value.

RO

0

TABLE 4-20:

FORMAT OF ALL PORT DROPPED PACKET MIB COUNTERS

AddressName

Description

Mode

Default

Format of All Port Dropped Packet MIB Counters
38

Overflow

1 = Counter overflow.
0 = No Counter overflow.

RO

0

37

Count Valid

1 = Counter value is valid.
0 = Counter value is not valid.

RO

0

36-16

Reserved

N/A No changeROAll ‘0’15-0Counter Values
Counter value.
Note:
All per-port MIB counters are read-clear.

RO

0

The KSZ8775CLX provides a total of 36 MIB counters per port. These counters are used to monitor the port activity for
network management and maintenance. These MIB counters are read using indirect memory access, as shown in thefollowing examples.
Programming Examples:• MIB counter read (read Port 1 Rx64Octets counter)Write to Register 110 with 0x1c (read MIB counters selected)
Write to Register 111 with 0xd (trigger the read operation)
Then
Read Register 116 (counter value [39:32])// If bit [38] = 1, there was a counter overflow
Read Register 117 (counter value [31:24])
Read Register 118 (counter value [23:16])
Read Register 119 (counter value [15:8])
Read Register 120 (counter value [7:0])• MIB counter read (read Port 2 Rx64Octets counter)

DS00002129C-page 108

 2015 Microchip Technology Inc.

KSZ8775CLX
Write to Register 110 with 0x1c (read MIB counter selected)
Write to Register 111 with 0x2d (trigger the read operation)
Then
Read Register 116 (counter value [39:32])// If bit [38] = 1, there was a counter overflow
Read Register 117 (counter value [31:24])
Read Register 118 (counter value [23:16])
Read Register 119 (counter value [15:8])
Read Register 120 (counter value [7:0])• MIB counter read (read Port 1 TX drop packets)
Write to Register 110 with 0x1d
Write to Register 111 with 0x03
Then
Read Register 116 (counter value [39:32])// If bit [38] = 1, there was a counter overflow
Read Register 119 (counter value [15:8])
Read Register 120 (counter value [7:0])
To read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 20 = 26 µs, where there are 160
registers, 3 overhead, 8 clocks per access, at 50 MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. The all-port MIB counters aredesigned as read-clear.

4.13

MIIM Registers

All the registers defined in this section can be also accessed via the SPI interface. Note that different mapping mechanisms are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for Port 1, “0x2” for Port 2, “0x3”for Port 3, and “0x4” for Port 4. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh).

TABLE 4-21:
Address

MIIM REGISTERS
Name

Description

Mode

Default

Register 0h: Basic Control
Soft Reset

1 = PHY soft reset.
0 = Normal operation.

R/W
(SC)

0

14

Loopback

1 = Perform MAC loopback. Loopback path is asfollows:
Assume the loopback is at Port 1 MAC, Port 2 isthe monitor Port.
Port 1 MAC loopback (Port 1 Reg. 0, bit [14]=’1’)Start: RXP2/RXM2 (Port 2). Can also start fromPort 3, 4, 5
Loopback: MAC/PHY interface of Port 1’s MAC
End: TXP2/TXM2 (Port 2). Can also end at Ports
3, 4, 5 respectively
Setting address 0x3, 4, 5 Reg. 0, bit [14] = ‘1’ will
perform MAC loopback on Ports 3, 4, 5. respectively.
0 = Normal Operation.

R/W

0

13

Force 100

1 = 100 Mbps.
0 = 10 Mbps.

R/W

1

15

 2015 Microchip Technology Inc.

DS00002129C-page 109

KSZ8775CLXTABLE 4-21:
Address

MIIM REGISTERS (CONTINUED)
Name

Description

Mode

Default

12

AN Enable

1 = Auto-Negotiation enabled.
0 = Auto-Negotiation disabled.

R/W

1

11

Power Down

1 = Power down.
0 = Normal operation.

R/W

0

10

PHY Isolate

1 = Electrical PHY isolation of PHY from TX+/
TX-.
0 = Normal operation.

R/W

0

9

Restart AN

1 = Restart Auto-Negotiation.
0 = Normal operation.

R/W

0

8

Force Full
Duplex

1 = Full-duplex.
0 = Half-duplex.

R/W

1

7

Reserved

ReservedRO

0

6

Reserved

Reserved

RO05

Hp_mdix

1 = HP Auto-MDI/MDIX mode
0 = Auto-MDI/MDIX mode

R/W

1

4

Force MDI

1 = MDI mode when disable Auto-MDI/MDIX.
0 = MDIX mode when disable Auto-MDI/MDIX.

R/W

0

3

Disable Auto
MDI/MDI-X

1 = Disable Auto-MDI/MDIX.
0 = Enable Auto-MDI/MDIX.

R/W

0

2

Disable far End
fault

1 = Disable far end fault detection.
0 = Normal operation.

R/W

0

1

Disable Transmit

1 = Disable transmit.
0 = Normal operation.

R/W

0

0

Disable LED

1 = Disable LED.
0 = Normal operation.

R/W

0Register 1h: Basic Status
15

T4 Capable

0 = Not 100 BASET4 capable.

RO

0

14

100 Full Capable

1 = 100BASE-TX full-duplex capable.
0 = Not capable of 100BASE-TX full-duplex.

RO

1

13

100 Half Capable

1 = 100BASE-TX half-duplex capable.
0 = Not 100BASE-TX half-duplex capable.

RO

1

12

10 Full Capable

1 = 10BASE-T full-duplex capable.
0 = Not 10BASE-T full-duplex capable.

RO

1

11

10 Half Capable

1 = 10BASE-T half-duplex capable.
0 = 10BASE-T half-duplex capable.

RO

1

10-7

Reserved

ReservedRO

0

6

Reserved

ReservedRO

0

5

AN Complete

1 = Auto-Negotiation complete.
0 = Auto-Negotiation not completed.

RO

0

4

Far End fault

1 = Far end fault detected.
0 = No far end fault detected.

RO

0

3

AN Capable

1 = Auto-Negotiation capable.
0 = Not Auto-Negotiation capable.

RO

1

2

Link Status

1 = Link is up.
0 = Link is down.

RO

0

1

Reserved

ReservedRO00

Extended Capa0 = Not extended register capable.
ble

RO

0

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 2015 Microchip Technology Inc.

KSZ8775CLXTABLE 4-21:
Address

MIIM REGISTERS (CONTINUED)
Name

Description

Mode

Default

High order PHYID bits.

RO

15-0

Low order PHYID bits.

RO

0x1550Register 2h: PHYID HIGH
15-0

Phyid HighRegister 3h: PHYID LOW
15-0

Phyid Low

Register 4h: Advertisement Ability
15

Reserved

Reserved

RO

0

14

Reserved

Reserved

RO

0

13

Reserved

Reserved

RO

0

12-11

Reserved

Reserved

RO

01

10

Pause

1 = Advertise pause ability.
0 = Do not advertise pause ability.

R/W

1

9

Reserved

Reserved

R/W

0

8

Adv 100 Full

1 = Advertise 100 full-duplex ability.
0 = Do not advertise 100 full-duplex ability.

R/W

1

7

Adv 100 Half

1 = Advertise 100 half-duplex ability.
0 = Do not advertise 100 half-duplex ability.

R/W

1

6

Adv 10 Full

1 = Advertise 10 full-duplex ability.
0 = Do not advertise 10 full-duplex ability.

R/W

1

5

Adv 10 Half

1 = Advertise 10 half-duplex ability.
0 = Do not advertise 10 half-duplex ability.

R/W

1

4-0

Selector Field[00001] = IEEE 802.3

RO

00001

Register 5h: Link Partner Ability
15

Reserved

Reserved

RO

0

14

Reserved

Reserved

RO

0

13

Reserved

Reserved

RO

0

12-11

Reserved

Reserved

RO

0

10

Pause

1 = Link partner flow control capable.
0 = Link partner not flow control capable.

RO

0

9

Reserved

ReservedRO0

8

Adv 100 Full

1 = Link partner 100BT full-duplex capable.
0 = Link partner not 100BT full-duplex capable.

RO

0

7

Adv 100 Half

1 = Link partner 100BT half-duplex capable.
0 = Link partner not 100BT half-duplex capable.

RO

0

6

Adv 10 Full

1 = Link partner 10BT full-duplex capable.
0 = Link partner not 10BT full-duplex capable.

RO

0

5

Adv 10 Half

1 = Link partner 10BT half-duplex capable.
0 = Link partner not 10BT half-duplex capable.

RO

0

4-0

Reserved

Reserved

RO

00001

R/W
(SC)

0

Register 1dh: LinkMD Control/Status

15

Cable Diagnostic Test
CDT_Enable 2015 Microchip Technology Inc.

1 = Enable cable diagnostic. After CDT test hascompleted, this bit will be self-cleared.
0 = Indicates cable diagnostic test (if enabled)
has completed and the status information is valid
for reading.

DS00002129C-page 111

KSZ8775CLXTABLE 4-21:
Address

14-13
12MIIM REGISTERS (CONTINUED)
Name

Description

Mode

Default

CDT_Result

00 = Normal condition
01 = Open condition detected in cable
10 = Short condition detected in cable
11 = Cable diagnostic test has failedRO00

CDT 10M Short

1 = Less than 10 meter short

RO

0

11-9

Reserved

Reserved

RO

0

8-0

CDT_Fault_Count

Distance to the fault. Approximately 0.4m ×
CDT_Fault_Count[8:0]RO

000000000

Register 1fh: PHY Special Control/Status
15-11

Reserved—

RO

0000000000

Port Operation
Mode Indication

Indicate the current state of port operation mode:
000 = Reserved
001 = Still in auto-negotiation
010 = 10BASE-T half-duplex
011 = 100BASE-TX half-duplex
100 = Reserved
101 = 10BASE-T full-duplex
110 = 100BASE-TX full-duplex
111 = PHY/MII isolate

RO

001

Reserved

N/A Don’t changeRO

00

Polrvs

1 = Polarity is reversed
0 = Polarity is not reversed

RO

0

MDI-X status

1 = MDI
0 = MDI-X

RO

0

Force_lnk

1 = Force link pass
0 = Normal operation

R/W

3

Pwrsave

1 = Enable power save
0 = Disable power save

R/W

2

Remote Loopback

1 = Perform Remote loopback. Loopback path isas follows:
Port 1 (PHY ID address 0x1 Reg. 1fh, bit [1] =‘1’)Start: RXP1/RXM1 (Port 1)
Loopback: PMD/PMA of Port 1’s PHY
End: TXP1/TXM1 (Port 1)
Setting PHY ID address 0x2, 3, 4, 5 Reg. 1fh bit[1] = ‘1’, will perform remote loopback on Port2, 3, 4, 5.
0 = Normal operation.

R/W

1

Reserved

RO

0

10-8

7-6
5
4
3
2

1

0

Reserved

DS00002129C-page 112

 2015 Microchip Technology Inc.

KSZ8775CLX
5.0

OPERATIONAL CHARACTERISTICS

5.1

Absolute Maximum Ratings*

Supply Voltage (VDD12A, VDD12D) ............................................................................................................. –0.5V to +1.8V(VDDAT, VDDIO) ................................................................................................................... –0.5V to +4.0V
Input Voltage ............................................................................................................................................. –0.5V to +4.0V
Output Voltage .......................................................................................................................................... –0.5V to +4.0V
Lead Temperature (soldering, 10s) ......................................................................................................................... 260°C
Storage Temperature (TS) ...................................................................................................................... –55°C to +150°C
Maximum Junction Temperature (TJ) ...................................................................................................................... 125°C
HBM ESD Performance Rating (Note 5-1)................................................................................................................ .5 kV
Note 5-1

Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ inseries with 100 pF.

*Exceeding the absolute maximum ratings may damage the device.

5.2

Operating Conditions**

Supply Voltage (VDD12A,VDD12D) ...................................................................................................... +1.140V to +1.260V(VDDAT @ 3.3V)...................................................................................................................... +3.135V to +3.465V(VDDAT @ 2.5V)...................................................................................................................... +2.375V to +2.625V(VDDIO @ 3.3V) ...................................................................................................................... +3.135V to +3.465V(VDDIO @ 2.5V) ...................................................................................................................... +2.375V to +2.625V(VDDIO @ 1.8V) ...................................................................................................................... +1.710V to +1.890V
Ambient Temperature (TA)Commercial......................................................................................................................................... 0°C to 70°C
Industrial ......................................................................................................................................... –40°C to 85°C
Junction Thermal Resistance
Thermal Resistance (JA).....................................................................................................................55.05°C/W
Industrial Resistance (JC) ....................................................................................................................25.06°CW**The device is not guaranteed to function outside its operating ratings. Unused inputs must always be tied to an appropriate logic voltage level (GND or VDD).

 2015 Microchip Technology Inc.

DS00002129C-page 113

KSZ8775CLX
6.0

ELECTRICAL CHARACTERISTICS

VIN = 1.2V/3.3V; TA = 25°C.
SymbolParameters

Conditions

Min.

Typ.

Max.

Units

100BASE-TX Operation – All Ports 100% Utilization
IDX

100BASE-TX (Transmitter) 3.3V
Analog

VDDAT

—

106

—

mA

ID12

100BASE-TX 1.2V

VDD12A + VDD12D

—

38

—

mA

IDDIO

100BASE-TX (Digital IO) 3.3V DigiVDDIO
tal

—

22

—

mA

—

108

—

mA

VDD12A + VDD12D

—

32

—

mA

VDDIO

—

18

—

mA
mA

10BASE-T Operation – All Ports 100% Utilization
IDX

10BASE-T (Transmitter) 3.3V AnaVDDAT
log

ID12

10BASE-T 1.2V

IDDIO

10BASE-T (Digital IO) 3.3V Digital

Auto-Negotiation Mode
IDX

3.3V Analog

VDDAT

—

50

—

ID12

1.2V Analog/Digital

VDD12A + VDD12D

—

35

—

mA

IDDIO

3.3V Digital

VDDIO

—

17

—

mA

Power Management ModeISPDM1

Soft Power Down Mode 3.3V

VDDAT + VDDIO

—

0.8

—

mA

ISPDM2

Soft Power Down Mode 1.2V

VDD12A + VDD12D

—

1.5

—

mA

IEDM1

Energy Detect Mode (EDPD) 3.3V

VDDAT + VDDIO

—

25

—

mA

IEDM2

Energy Detect Mode (EDPD) 1.2V

VDD12A + VDD12D

—

29

—

mA

IEEE1

100BT EEE Mode at Idle 3.3V

VDDAT + VDDIO

—

26

—

mA

IEEE2

100BT EEE Mode at Idle 1.2V

VDD12A + VDD12D

—

29

—

mA

VDDIO = 3.3V

2.0

—

—

V

VDDIO = 2.5V

1.8

—

—

V

VDDIO = 1.8V

—

—

V

VDDIO = 3.3V

1.3
—

—

0.8

V

VDDIO = 2.5V

—

—

0.7

V

VDDIO = 1.8V

—

—

0.5

V

VIN = GND ~ VDDIO

—

—

10

µA

VDDIO = 3.3V

2.4

—

—

V

VDDIO = 2.5V

2.0

—

—

V

VDDIO = 1.8V

—

—

V

VDDIO = 3.3V

1.5
—

—

0.4

V

VDDIO = 2.5V

—

—

0.4

V

VDDIO = 1.8V

—

—

0.3

V

VIN = GND ~ VDDIO

—

—

10

µA

CMOS Inputs
VIH

Input High Voltage

VIL

Input Low Voltage

IIN

Input Current(Excluding Pull-Up/Pull-Down)

CMOS Outputs
VOH

VOL
IOZ

Output High Voltage

Output Low Voltage
Output Tri-State Leakage

100BASE-TX Transmit (Measured Differentially After 1:1 Transformer)
VO

Peak Differential Output Voltage100Ω termination on the differential
output

0.95

—

1.05

V

VIMB

Output Voltage Imbalance100Ω termination on the differential
output——2%DS00002129C-page 114

 2015 Microchip Technology Inc.

KSZ8775CLX
Symboltr/tf

Parameters
Rise/Fall Time

Conditions

Min.

Typ.

Max.

Units

—

3

—

5

ns

—

0.5

ns

—

±0.5

ns

Rise/Fall Time Imbalance——

Duty Cycle Distortion

—

0
—

—

Overshoot

—

—

—

5

%

—

Output Jitters

Peak-to-peak

0

0.75

1.4

ns

5 MHz square wave

300

400

585

mV

2.2

2.5

2.8

V

10BASE-T Receive
VSQ

Squelch Threshold

10BASE-T Transmit (Measured Differentially After 1:1 Transformer) VDDAT = 3.3V
VP

Peak Differential Output Voltage

tr/tf

Rise/Fall Times

Output Jitters100Ω termination on the differential
outputPeak-to-peak
—

—

1.4

3.5

ns

—

28

30

ns

I/O Pin Internal Pull-Up and Pull-Down Resistance
R1.8PUI/O Pin Effective Pull-Up Resistance

VDDIO = 1.8V

75

95

135

kΩ

R1.8PDI/O Pin Effective Pull-Down Resistance

VDDIO = 1.8V

53

68

120

kΩ

R2.5PUI/O Pin Effective Pull-Up Resistance

VDDIO = 2.5V

46

60

93

kΩ

R2.5PDI/O Pin Effective Pull-Down Resistance

VDDIO = 2.5V

46

59

103

kΩ

R3.3PUI/O Pin Effective Pull-Up Resistance

VDDIO = 3.3V

35

45

65

kΩ

R3.3PDI/O Pin Effective Pull-Down Resistance

VDDIO = 3.3V

37

46

74

kΩ

 2015 Microchip Technology Inc.

DS00002129C-page 115

KSZ8775CLX
7.0

TIMING DIAGRAMS

7.1

RGMII Timing

The RGMII timing conforms to the timing requirements in the RGMII Version 2.0 specification.

FIGURE 7-1:

TABLE 7-1:

RGMII V2.0 SPECIFICATIONRGMII TIMING PARAMETERS

SymbolParameter

Min

Typ

Max

Units

TskewT

Data to clock output skew (at transmitter) Note 7-1

–500

0

500

ps

TskewR

Data to clock input skew (at receiver)Note 7-1

1

—

2.6

ns

TsetupT

Data to clock output setup (at transmitter – integrated delay)

1.0

2.0

—

ns

TholdT

Clock to data output hold (at transmitter – integrated delay)

1.0

2.0

—

ns

TsetupR

Data to clock input setup (at receiver – integrated delay)

0.8

2.0

—

ns

TholdR

Clock to data input hold (at receiver – integrated delay)

0.8

20.

—

ns

Tcyc

Clock Cycle DurationNote 7-2

7.2

8

8.8

ns

Duty_G

Duty Cycle for Gigabit

45

50

55

%

Duty_T

Duty Cycle for 10/100T

40

50

60

%

tr/tf
Rise/Fall Time (20-80%)
—
—
0.75
ns
Note 7-1
RGMII v2.0 add Internal Delay (RGMII-ID) option to match the data to clock output/input skew for
RGMII transmit and receiving, see the register 86 bits[4:3] for detail..
Note 7-2

For 10 Mbps and 100 Mbps, Tcyc scales to 400 ns ±40 ns and 40 ns ±4 ns.

DS00002129C-page 116

 2015 Microchip Technology Inc.

KSZ8775CLX
7.2

MII Timing

FIGURE 7-2:

MAC MODE MII TIMING – DATA RECEIVED FROM MII
ts3

RECEIVE TIMING

tcyc3

th3

MRXCLK
MTXEN
MTXER
MTXD[3:0]

FIGURE 7-3:

MAC MODE MII TIMING – DATA TRANSMITTED FROM MII
tcyc3

TRANSMIT TIMINGMRXCLKMRXDVMRXD[3:0]

TABLE 7-2:

MAC MODE MII TIMING PARAMETERS
10BASE-T/100BASE-TX

SymbolParameter
Min.

tCYC3

Clock Cycle—tS3

Set-Up Time

2

Typ.

Max.

Units

400/40

—

ns

—

—

ns
ns
ns

tH3

Hold Time

2

—

—

tOV3

Output Valid

3

8

10

 2015 Microchip Technology Inc.

DS00002129C-page 117

KSZ8775CLX
FIGURE 7-4:

PHY MODE MII TIMING – DATA RECEIVED FROM MIIRECEIVE TIMING
ts4

tcyc4

th4

MTXCLK

MTXEN

MTXER
MTXD[3:0]

FIGURE 7-5:

PHY MODE MII TIMING – DATA TRANSMITTED FROM MII
tcyc4

TRANSMIT TIMING

tov4

TABLE 7-3:

PHY MODE MII TIMING PARAMETERS
10BASE-T/100BASE-TX

7.3

SymbolParameter

Min.

Typ.

Max.

Units

tCYC4

Clock Cycle—

400/40—ns

tS4

Set-Up Time

10

—

—

ns

tH4

Hold Time

0

—

—

ns

tOV4

Output Valid

16

20

25

ns

RMII Timing

FIGURE 7-6:
TRANSMITTIMINGRMII TIMING – DATA RECEIVED FROM RMII
tcyc

REFCLK
t1
t2
TX_EN
TXD[1:0]

DS00002129C-page 118

 2015 Microchip Technology Inc.

KSZ8775CLX
FIGURE 7-7:

RMII TIMING – DATA TRANSMITTED TO RMII
tcyc

RECEIVE
TIMINGREFCLK

CRSDV
RXD[1:0]
tod

TABLE 7-4:

7.4

RMII TIMING PARAMETERS

SymbolParameter

Min.

Typ.

Max

Units

tCYC

Clock Cycle

—

20

—

ns

t1

Set-Up Time

4

—

—

ns

t2

Hold Time

2

—

—

ns

tOD

Output Delay

3

—

10

ns

SPI Timing

FIGURE 7-8:

SPI INPUT TIMING

 2015 Microchip Technology Inc.

DS00002129C-page 119

KSZ8775CLXTABLE 7-5:

SPI INPUT TIMING PARAMETERS

SymbolParameter

Min.

Typ.

Max.

Units

fC

Clock Frequency

—

—

50

MHz

tCHSL

SPIS_N Inactive Hold Time

2

—

—

ns

tSLCH

SPIS_N Active Set-Up Time

4

—

—

ns

tCHSH

SPIS_N Active Hold Time

2

—

—

ns

tSHCH

SPIS_N Inactive Set-Up Time

4

—

—

ns

tSHSL

SPIS_N Deselect Time

10

—

—

ns

tDVCH

Data Input Set-Up Time

4

—

—

ns

tCHDX

Data Input Hold Time

2

—

—

ns

tCLCH

Clock Rise Time

—

—

1

µs

tCHCL

Clock fall Time

—

—

1

µs

tDLDH

Data Input Rise Time

—

—

1

µs

tDHDL

Data Input Fall Time

—

—

1

µs

Min.

Typ.

Max.

Units

FIGURE 7-9:

TABLE 7-6:

SPI OUTPUT TIMINGSPI OUTPUT TIMING PARAMETERS

SymbolParameter

fC

Clock Frequency

—

—

50

MHz

tCLQX

SPIQ Hold Time

0

—

0

ns

tCLQV

Clock Low to SPIQ Valid

—

60

ns

tCH

Clock High Time

9

—

—

ns

tCL

Clock Low Time

9

—

—

ns

tQLQH

SPIQ Rise Time

—

—

50

ns

tQHQL

SPIQ Fall Time

—

—

50

ns

tSHQZ

SPIQ Disable Time

—

—

15

ns

DS00002129C-page 120

 2015 Microchip Technology Inc.

KSZ8775CLX
7.5

Auto-Negotiation Timing

FIGURE 7-10:

AUTO-NEGOTIATION TIMING

AUTO -NEGOTIATIONFAST LINK PULSE (FLP) TIMING

FLP
BURST

FLP
BURST

TX+/TXtFLPW

tBTB

CLOCK
PULSE

DATA
PULSE

tPW

tPW

CLOCK
PULSE

DATA
PULSE

TX+/TX-

tCTD
tCTC

TABLE 7-7:

AUTO-NEGOTIATION TIMING PARAMETERS

SymbolParameter

Min.

Typ.

Max.

Units

8

16

24

ms

tBTB

FLP burst to FLP burst

tFLPW

FLP burst width

—

2

—

ms

tPW

Clock/Data pulse width

—

100

—

ns

tCTD

Clock pulse to Data pulse

55.5

64

69.5

µs

tCTC

Clock pulse to Clock pulse

111

128

139

µs

—

Number of Clock/Data pulses per burst

17

—

33

—

 2015 Microchip Technology Inc.

DS00002129C-page 121

KSZ8775CLX
7.6

MDC/MDIO Timing

FIGURE 7-11:

MDC/MDIO TIMING DIAGRAMTABLE 7-8:

MDC/MDIO TIMING PARAMETERS

Symbol7.7

Parameter

Min.

Typ.

Max.

Units

tP

MDC Period

—

400

—

ns

tMD1

MDIO (PHY Input) Setup to Rising Edge of MDC

10

—

—

ns

tMD2

MDIO (PHY Input) Hold from Rising Edge of MDC

4

—

—

ns

tMD3

MDIO (PHY Output) Delay from Rising Edge of MDC

5

—

—

ns

Power-Down/Power-Up and Reset Timing

TABLE 7-9:

RESET TIMING PARAMETERS

SymbolParameter

Min.

Typ.

Max

Units

tSR

Stable Supply Voltages to Reset High

10

—

—

ms

tCS

Configuration Set-Up Time

5

—

—

ns

tCH

Configuration Hold Time

5

—

—

ns

tRC

Reset to Strap-In Pin Output

6

—

—

ns

tVR

3.3V Rise Time

200

—

—

µs

DS00002129C-page 122

 2015 Microchip Technology Inc.

KSZ8775CLX
7.8

Reset Circuit Diagram

The following discrete reset circuit is recommended as shown in Figure 7-12 when powering up the KS8775 device. For
applications where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc.), the recommended reset
circuit is shown as in Figure 7-13.

FIGURE 7-12:

RECOMMENDED RESET CIRCUIT
VDDIO
D1: 1N4148
R
10kΩ

D1

KS8775RST

C
10μF

FIGURE 7-13:

RECOMMENDED CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
VDDIO

R
10kΩ

D1

KS8775

CPU/FPGA
RST_OUT_n

RST
C
10μF

D2

D1: 1N4148
Figure 7-13 shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2
is required if using different VDDIO voltage between switch and CPU/FPGA. Diode D2 should be selected to provide
maximum 0.3V VF (Forward Voltage), for example, VISHAY BAT54, MSS1P2L. Alternatively, a level shifter device canalso be used. D2 is not required if switch and CPU/FPGA use same VDDIO voltage.

7.9

Selection of Isolation Transformer (Note 1)

One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/
TX at chip side. Table 7-10 gives recommended transformer characteristics.

TABLE 7-10:

TRANSFORMER SELECTION CRITERIACharacteristic

Value

Test Condition

Turn Ratio

1CT:1CT—

Open-Circuit Inductance (min.)

350 µH

100 mV, 100 kHz, 8 mA

Insertion Loss (max.)

1.1 dB

0.1 MHz to 100 MHz

HIPOT (min.)1500 VRMS—

 2015 Microchip Technology Inc.

DS00002129C-page 123

KSZ8775CLX
Note 1: The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5 dB. For the transmit linetransformer, insertion loss of up to 1.3 dB can be compensated by increasing the line drive current by meansof reducing the ISET resistor value.
Table 7-11 shows the transformer vendors that provide compatible magnetic parts for the device.

TABLE 7-11:

QUALIFIED MAGNETIC VENDORS

Vendors and Parts

Auto MDIX

Number of
Ports

Auto
MDIX

Vendors and Parts

Numberof Ports

Pulse

H1164NL

Yes

4

Pulse

H1102

Yes

1

YCL

PH406082

Yes

4

Bel Fuse

S558-5999-U7

Yes

1

TDK

TLA-6T718A

Yes

1

YCL

PT163020

Yes

1

LanKomLF-H41S

Yes

1Transpower

HB726

Yes

1

Datatronic

NT79075

Yes

1

Delta

LF8505

Yes

1

7.10

Selection of Reference Crystal

TABLE 7-12:

TYPICAL REFERENCE CRYSTAL CHARACTERISTICS
Characteristic

Value

Units

Frequency

25.0

MHz

Frequency Tolerance (max.)

±50

ppm

Load Capacitance (max.) (Note 1)

27

pF

Series Resistance (max. ESR)
Note 1: Typical value varies per specific crystal specs.

40

DS00002129C-page 124

 2015 Microchip Technology Inc.

KSZ8775CLX
8.0
Note:

PACKAGE OUTLINE
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging/.

FIGURE 8-1:

80-LEAD LQFP 10 MM X 10 MM PACKAGE OUTLINE AND RECOMMENDED
LAND PATTERN

 2015 Microchip Technology Inc.

DS00002129C-page 125

KSZ8775CLX
Notes:

DS00002129C-page 126

 2015 Microchip Technology Inc.

KSZ8775CLX
APPENDIX A:TABLE A-1:

DATA SHEET REVISION HISTORYREVISION HISTORY

Revision

Section/Figure/Entry

Correction

DS00002129A (03-29-16)

ALL

Initial conversion

DS00002129B (04-22-16)

Section 5.2/Operating Conditions/Supply Voltage

Changed Conditional value (VDDIAT @ 3.3V) to(VDDAT @2.5V).

DS00002129C (07-18-16)

Figure 2-1

Corrected incorrect figure caption.

 2015 Microchip Technology Inc.

DS00002129C-page 127

KSZ8775CLX
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to makefiles and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family ordevelopment tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.

CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://microchip.com/support

DS00002129C-page 128

 2015 Microchip Technology Inc.

KSZ8775
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.

X

X

Device Interface

X

Package

X

SpecialTemperature
Range
Attributes

X
Bond
Wire

Device:

KSZ8775 - Integrated 5-Port 10/100 Managed Ethernet
Switch with Port 4 RMII and Port 5 RGMII/MII/RMII Interfaces

Interface:C= Configurable

Package:L= 80-pin LQFPSpecial Attribute:

X=

Temperature
Range:CC
IC=
0C to= -40C to

Examples:a)

KSZ8775CLXCC
Configurable Interface
80-pin LQFP
Commercial Temperatureb)

KSZ8775CLXIC
Configurable Interface
80-pin LQFP
Industrial TemperatureNone 2015 Microchip Technology Inc.

+70C
+85C

(Commercial)(Industrial)

DS00002129C-page 129

KSZ8775

DS00002129C-page 130

 2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

•

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.

Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE areregistered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks ofMicrochip Technology Incorporated in the U.S.A. and othercountries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and proceduresare for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEMCERTIFIED BY DNV== ISO/TS 16949 == 2016 Microchip Technology Inc.

Silicon Storage Technology is a registered trademark ofMicrochip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of theirrespective companies.
© 2016, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0436-1

DS00002129C-page 131

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