USB5532B
2-Port SS/HS USB Hub Controller
General Description
The USB5532B hub is a 2-port SuperSpeed/Hi-Speed,
low-power, configurable hub controller family fully compliant with the USB 3.0 Specification. The USB5532B
supports 5 Gbps SuperSpeed (SS), 480 Mbps HiSpeed (HS), 12 Mbps Full-Speed (FS) and 1.5 Mbps
Low-Speed (LS) USB signaling for complete coverageof all defined USB operating speeds.
The USB5532B supports USB 2.0 speeds through its
USB 2.0 hub controller. The new SuperSpeed hub controller operates in parallel with the USB 2.0 controller,
so the 5 Gbps SuperSpeed data transfers are notaffected by the slower USB 2.0 traffic.
The USB5532B supports battery charging on a per port
basis. On battery charging enabled ports, the devices
provide automatic USB data line handshaking. The
handshaking supports USB 1.2 Charging Downstream
Port (CDP), Dedicated Charging Port (DCP) and nonUSB 1.2 devices.
The USB5532B is configured for operation throughinternal default settings, where custom configurations
are supported through an on-chip OTP ROM, an external SPI ROM, or SMBus.

Product Features• USB 3.0 compliant 5 Gbps, 480 Mbps, 12 Mbps
and 1.5 Mbps operation, USB pins are 5 V tolerant- Integrated termination and pull-up/pull-downresistors• Two downstream USB 3.0 ports• Supports battery charging of most popular battery
powered devices- USB-IF Battery Charging rev. 1.2 support(DCP & CDP)
- Apple Portable product charger emulation- Blackberry charger emulation- Chinese YD/T 1591-2006 charger emulation- Chinese YD/T 1591-2009 charger emulation- Supports additional portable devices

 2012 - 2015 Microchip Technology Inc.

• Emulates portable/handheld native wall chargers- Charging profiles emulate a handheld
device’s wall charger to enable fast charging(minutes vs. hours)• Enables charging from a mobile platform that isoff• Support tablets’ high current requirements• Optimized for low-power operation and low thermal dissipation• Vendor Specific Messaging (VSM) support for
firmware upload over USB• Configuration via OTP ROM, SPI ROM, or SMBus• On-chip 8051 µC manages VBUS, and other hub
signals• 8 KB RAM, 32 KB ROM• One Time programmable (OTP) ROM: 8 kbit
- Includes on-chip charge pump
• Single 25 MHz XTAL or clock input for all on-chip
PLL and clocking requirements• Supports JTAG boundary scan
• PHYBoost (USB 2.0)
- Selectable drive strength for improved signal
integrity• VariSense (USB 2.0)
- controls the receiver sensitivity enabling four
programmable levels of USB signal receive
sensitivity• IETF RFC 4122 compliant 128-bit UUID

Software Features• Compatible with Microsoft Windows 7, Vista, XP,
Mac OSX10.4+, and Linux Hub Drivers

DS00001679C-page 1

USB5532B
TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify therevision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you areusing.

Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS00001679C-page 2

 2012 - 2015 Microchip Technology Inc.

USB5532B
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Block Diagram ................................................................................................................................................................................. 6
3.0 Pin Information ................................................................................................................................................................................ 7
4.0 Standard Interface Connections ................................................................................................................................................... 13
5.0 Functional Operation ..................................................................................................................................................................... 24
6.0 DC Parameters ............................................................................................................................................................................. 63
7.0 AC Specifications .......................................................................................................................................................................... 67
8.0 Package Drawing .......................................................................................................................................................................... 70
Appendix A: Data Sheet Revision History ........................................................................................................................................... 72
Appendix B: Acronyms ........................................................................................................................................................................ 74
Appendix C: References ..................................................................................................................................................................... 75
The Microchip Web Site ...................................................................................................................................................................... 76
Customer Change Notification Service ............................................................................................................................................... 76
Customer Support ............................................................................................................................................................................... 76
Product Identification System ............................................................................................................................................................. 77

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 3

USB5532B
1.0

INTRODUCTION

1.1

Conventions

Within this manual, the following abbreviations and symbols are used to improve readability.
ExampleBIT
FIELD.BIT

x…y
BITS[m:n]Name of a single bit within a field
Name of a single bit (BIT) in FIELD
Range from x to y, inclusive
Groups of bits from m to n, inclusive

PIN

Pin Namezzzzb

Binary number (value zzzz)

0xzzz

Hexadecimal number (value zzz)

zzhHexadecimal number (value zz)

rsvd

Reserved memory location. Must write 0, read value indeterminate

code

Instruction code, or API function or parameter

Multi Word Name

Used for multiple words that are considered a single unit, such as:
Resource Allocate message, or Connection Label, or Decrement Stack Pointer instruction.

Section Name

Section or Document name.

x

1.2

Description

Don’t care

<Parameter><> indicate a Parameter is optional or is only used under some conditions{,Parameter}

Braces indicate Parameter(s) that repeat one or more times.

[Parameter]

Brackets indicate a nested Parameter. This Parameter is not real and actually decodes into
one or more real parameters.

Overview

The USB5532B hub is a 2-port, low-power, configurable Hub Controller fully compliant with the USB 3.0 Specification
2. The USB5532B supports 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS) and
1.5 Mbps Low-Speed (LS) USB signaling for complete coverage of all defined USB operating speeds.
All required resistors on the USB ports are integrated into the hub. This includes all series termination resistors and all
required pull-down and pull-up resistors on D+ and D- pins. The over-current sense inputs for the downstream facing
ports have internal pull-up resistors.
The USB5532B hub includes programmable features such as:• MultiTRAKTM Technology (USB 2.0): implements a dedicated Transaction Translator (TT) for each port. Dedicated TTs help maintain consistent full-speed data throughput regardless of the number of active downstream
connections.
• PortSwap (USB 2.0): allows direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length
or crossing of the USB differential signals on the PCB.
• PHYBoost (USB 2.0): enables 4 programmable levels of USB signal drive strength in downstream port transceivers. PHYBoost will also attempt to restore USB signal integrity.
As shown on the Product Identification System page, two USB5532B firmware versions are available: “-5000” and “6080”. These options differ in the following ways:• The Dynamic Charging Port feature and related DYNCPDIS_N pin function are only available on the -6080
device. Refer to Section 5.1.3, "Dynamic Charging Port (6080 Only)" for additional details.
• The TRST/DYNCPDIS_N/UCS_SMBALERT_N pin buffer type is “IPU” in the -6080 device and “I” in the -5000
device. Refer to Pin Information on page 7 for additional details.
• The Global Suspend power consumption has been significantly lowered in the -6080 device. Refer to Section 6.3,
"Power Consumption" for additional details.

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 4

USB5532B
1.3

Configurable Features

The USB5532B hub controller provides a default configuration that is sufficient for most applications. When initialized
in the default configuration, the following features may be configured:• Downstream non-removable ports, where the hub will automatically report as a compound device• Downstream disabled ports• Downstream port power control and over-current detection on a ganged or individual basis• USB signal drive strength• USB differential pair pin location
The USB5532B hub controllers can alternatively be configured by OTP or as an SMBus slave device. When configuredby an OTP or over SMBus, the following configurable features are provided:• Support for compound devices on a port-by-port basis• Selectable over-current sensing and port power control on an individual or ganged basis to match the circuit board
component selection• Customizable vendor ID, product ID, and device ID• Configurable delay time for filtering the over-current sense inputs• Indication of the maximum current that the hub consumes from the USB upstream port
• Indication of the maximum current required for the hub controller• Custom string descriptors (up to 30 characters): Product, manufacturer, and serial number

DS00001679C-page 5

 2012 - 2015 Microchip Technology Inc.

Common
Block
& PLL
SS
PHY
BufferSS
PHY
BufferRegisters& Hub I/O

USB2.0PHY

 2012 - 2015 Microchip Technology Inc.

RX
SS
PHY

TX
SS
PHY

USB2.0PHY

Downstream USB Port 1

BufferBufferRegisters& Hub I/O

APB Bus

2k OTP

Reset & 8051
Boot Seq.

XData to
APB Bridge

SS
PHY

RX

BufferUSB2.0PHY

Downstream USB Port 2

SS
PHY

TX

Buffer

Downstream RX SS bus

Downstream TX SS bus

HS/FS/LS Routing Logic

VBUS
Control

XData

USB 2.0 Hub Controller

8k RAM

32k ROM

Embedded
8051 µC

Timer

SPI
MasterSPI

FIGURE 2-1:

USB 3.0 Hub Controller

RX

2.0

TX

Upstream USB Port

USB5532B

BLOCK DIAGRAM
USB5532B BLOCK DIAGRAM

DS00001679C-page 6

USB5532B
3.0

PIN INFORMATIONThis chapter outlines the pinning configurations for each chip. The detailed pin descriptions are listed by function in Section 3.2, "Pin Descriptions (Grouped by Function)," on page 8.

Pin Configurations

TMS/OCS2

TCK/OCS1

TRST/DYNCPDIS_N/
UCS_SMBALERT_N

TDI

TDO

SPI_DISPI_DOSPI_CLKSPI_CE_N

SM_CLK

SM_DAT

PRT_PWR1/PRT_CTL1

PRT_PWR2/PRT_CTL2

VDD33

NC

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

USB5532B 64-PIN QFN

VBUS

FIGURE 3-1:

48

3.1

TEST

49

32

NC

RESET_N

50

31

VDD12

VDD12

51

30

NC

VDD33

52

29

NC

USB2DP_UP

53

28

VDD12

USB2DM_UP

54

27

NC

USB3DP_TXUP

55

26

NC

USB3DM_TXUP

56

NC

VDD12

57

USB5532B

25
24

USB3DP_RXUP

58(Top View QFN-64)

NC

23

NC

USB3DM_RXUP

59

22

NC

ATEST

60

21

VDD12

XTALOUT

61

20

NC

XTALIN/CLK_IN

62

19

NC

VDD33

63

18

NC

RBIAS

64

17

NC

Ground Pad

5

6

7

8

9

10

11

12

13

14

15

16

VDD12

USB3DP_RXDN1

USB3DM_RXDN1VDD12USB2DP_DN2

USB2DM_DN2

USB3DP_TXDN2

USB3DM_TXDN2VDD12USB3DP_RXDN2

USB3DM_RXDN2

VDD33

3

USB3DP_TXDN1

4

2

USB2DM_DN1

USB3DM_TXDN1

1

USB2DP_DN1(must be connected to VSS with a via field)

Indicates pins on the bottom of the device.

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 7

USB5532B
3.2

Pin Descriptions (Grouped by Function)

An N at the end of a signal name indicates that the active (asserted) state occurs when the signal is at a low voltage
level. When the N is not present, the signal is asserted when it is at a high voltage level. The terms assertion and negation are used exclusively in order to avoid confusion when working with a mixture of active low and active high signals.
The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a highor low voltage. The term negate, or negation, indicates that a signal is inactive.

TABLE 3-1:

USB5532B PIN DESCRIPTIONS

SymbolBuffer Type

Description
USB 3.0 INTERFACE

USB3DP_TXUP

IO-U

USB 3 Upstream
Upstream SuperSpeed transmit data plus

USB3DM_TXUP

IO-U

USB 3 Upstream
Upstream SuperSpeed transmit data minus

USB3DP_RXUP

IO-U

USB 3 Upstream
Upstream SuperSpeed receive data plus

USB3DM_RXUP

IO-U

USB 3 Upstream
Upstream SuperSpeed receive data minus

USB3DP_TXDN[2:1]

IO-U

USB 3 Downstream
Downstream SuperSpeed transmit data plus for ports 1 through 2.

USB3DM_TXDN[2:1]

IO-U

USB 3 Downstream
Downstream SuperSpeed transmit data minus for ports 1 through 2.

USB3DP_RXDN[2:1]

IO-U

USB 3 Downstream
Downstream SuperSpeed receive data plus for ports 1 through 2.

USB3DM_RXDN[2:1]

IO-U

USB 3 Downstream
Downstream SuperSpeed receive data minus for ports 1 through 2.
USB 2.0 INTERFACE

USB2DP_UP

IO-U

USB Bus Data
These pins connect to the upstream USB bus data signals.

USB2DM_UP

IO-U

USB Bus Data
These pins connect to the upstream USB bus data signals.

USB2DP_DN[2:1]
USB2DM_DN[2:1]

DS00001679C-page 8

IO-U
IO-U

USB Downstream
Downstream Hi-Speed data plus for ports 1 through 2.
USB Downstream
Downstream Hi-Speed data minus for ports 1 through 2.

 2012 - 2015 Microchip Technology Inc.

USB5532B
TABLE 3-1:

USB5532B PIN DESCRIPTIONS (CONTINUED)

SymbolBuffer Type

Description
USB PORT CONTROLPRT_PWR[2:1]/
PRT_CTL[2:1]

O12

USB Power Enable
Enables power to USB peripheral devices downstream.
Note:

VBUS

I

This pin also provides configuration strap functions.
See Note 3-1.

Upstream VBUS Power Detect
This pin can be used to detect the state of the upstream bus power. The
device monitors this pin to determine when to assert the internal D+ pullup resistor (signaling a connect event).
When designing a detachable hub, this pin should be connected to
VBUS on the upstream port via a 2:1 voltage divider. Two 100 k
resistors are suggested.
For self-powered applications with a permanently attached host, this pin
must be connected to a dedicated host control output, or connected tothe 3.3 V domain that powers the host (typically VDD33).
SPI INTERFACE (4 PINS)SPI_CE_N

O12

SPI_CLKO12SPI Enable
SPI Clock
SPI Serial Data Out

SPI_DOO12

The output for the SPI port.
Note:

SPI_DIIThis pin also provides configuration strap functions.
See .

SPI Serial Data In
The SPI data in to the controller from the ROM. This pin has a weakinternal pull-down applied at all times to prevent floating.
JTAG/OCS INTERFACEJTAG Asynchronous ResetTRST

DYNCPDIS_N

IPU(Note 3-4)

Note:

If using the SMBus interface, a pull-up on this signal will enable
Legacy Mode, while leaving it unconnected or pulled-down will
enable Advanced Mode.

Note:

Only available in test mode.

Dynamic Charging Port Disable
This active-low signal is used to globally disable Battery Charging
support on all USB downstream ports configured as Charging Ports.
Note:

UCS_SMBALERT_N

This signal available in -6080 versions only

UCS1002 SMBus Alert
When charging port is enabled and SMBus devices are used, this signal
acts as an active-low SMBus alert.

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 9

USB5532B
TABLE 3-1:

USB5532B PIN DESCRIPTIONS (CONTINUED)

SymbolBuffer Type

Description
JTAG Clock

TCKThis input is used for JTAG boundary scan and has a weak pull-down.
It can be left floating or grounded when not used. If the JTAG isconnected, then this signal will be detected high, and the software
disables the pull up after reset.
I

Note:

Only available in test mode.

Over-Current Sense 1

OCS1

Input from external current monitor indicating an over-current condition.
Note:

This pin also provides configuration strap functions.
See Note 3-3.

JTAG TMS

TMS

Used for JTAG boundary scan.
Note:
OCS2

I

Only available in test mode.

Over-Current Sense 2
Input from external current monitor indicating an over-current condition.
Note:

This pin also provides configuration strap functions.
See Note 3-3.

JTAG TDI

TDI
I

Used for JTAG boundary scan.
Note:

Only available in test mode.

JTAG TDO

TDO
O12

Used for JTAG boundary scan.
Note:

Only available in test mode.
MISC

RESET_NIS

Reset Input
The system uses this active low signal to reset the chip. The active lowpulse should be at least 1 s wide.
Crystal Input: 25 MHz crystal.

XTALIN

CLK_INICLKxThis pin connects to either one terminal of the crystal or to an external
25 MHz clock when a crystal is not used.
External Clock Input
This pin connects to either one terminal of the crystal or to an external
25 MHz clock when a crystal is not used.

XTALOUTOCLKx

Crystal Output
The clock output, providing a crystal 25 MHz. When an external clock
source is used to drive XTALIN/CLK_IN, this pin becomes a noconnect.

TEST

IPD

Test Pin
Treat as a no connect pin or connect to ground. No trace or signal
should be routed or attached to this pin.

RBIAS

I-R

USB Transceiver Bias
A12.0 k (+/- 1%) resistor is attached from ground to this pin to set thetransceiver’s internal bias settings.

ATEST

A

Analog Test Pin
This signal is used for testing the chip and must always be connected
to ground.

DS00001679C-page 10

 2012 - 2015 Microchip Technology Inc.

USB5532B
TABLE 3-1:

USB5532B PIN DESCRIPTIONS (CONTINUED)

SymbolBuffer Type

Description

SM_CLK

I/O12

SMBus Clock

SM_DAT

I/O12

SMBus Data Pin(14) NC-

No connect pins
DIGITAL AND POWER(4) VDD33

3.3 V Power(8) VDD12

1.25 V PowerVSS

Ground Pad
This exposed pad is the device’s only connection to VSS and theprimary thermal conduction path. Connect to an appropriate via field.

Note 3-1

The PRT_PWR[2:1] pins can optionally provide additional configuration strap functions toenable/disable the associated port and configure its battery charging capabilities. Configuration strap
values are latched on device reset. Table 3-2 details the functions associated with the various strap
settings.
Strapping features are enabled by default and can be optionally disabled via the Pro-Touch software
programming tool. For additional information on the Pro-Touch programming tool, contact your local
sales representative.
Strapping functions are not supported for designs that support OCS but not power switching.

TABLE 3-2:

PRT_PWR[2:1] CONFIGURATION STRAP STATESPRT_PWR[2:1]
Strap Setting

Port State

Battery Charging

No Pull-Up or Pull-Down

EnabledDisabledPull-Down:<10 k to VSS

Disabled

N/A

Pull-Up:<10 k and >1 k to VDD33

EnabledEnabledNote 3-2

The SPI_DO pin provides an additional SPI_SPD_SEL configuration strap function. SPI_SPD_SEL
selects between the 30MHz SPI Mode when pulled-down to ground (default) and the 60MHz SPI
Mode when pulled-up to VDD33. The SPI_SPD_SEL strap value is latched on Power-On Reset(POR) or RESET_N deassertion.

Note 3-3

The OCS[2:1] pins can optionally provide additional configuration strap functions. To set theassociated port into the non-removable state, the OCS pin must be configured with a pull-down(<10 k to VSS). Otherwise, the port will be configured in the removable state. Configuration strap
values are latched on device reset.
Strapping features are enabled by default and can be optionally disabled via the Pro-Touch software
programming tool. For additional information on the Pro-Touch programming tool, contact your local
sales representative.
Strapping functions are not supported for designs that support OCS but not power switching.

Note 3-4

This pin has an internal pull-up only in the -6080 version. The internal pull-up is only active after the
SMBus mode (Legacy/Advanced) configuration strap has been sampled at POR or reset. The -5000
version is an “I” type buffer.

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 11

USB5532B
3.3

Buffer Type Descriptions

TABLE 3-3:

BUFFER TYPE DESCRIPTIONS

Buffer Type

Description

I

Input

I/O

Input/output

IPD

Input with internal weak pull-down resistor

IPU

Input with internal weak pull-up resistor

IS

Input with Schmitt trigger

O12

Output 12 mA

I/O12Input/output buffer with 12 mA sink and 12 mA source

I/OSD12Open drain with Schmitt trigger and 12 mA sink.

ICLKx

XTAL clock input

OCLKx

XTAL clock output

I-R

RBIAS

I/O-U

Analog input/output defined in USB specification

DS00001679C-page 12

 2012 - 2015 Microchip Technology Inc.

USB5532B
4.0

STANDARD INTERFACE CONNECTIONS

4.1

SPI Interface

The hub will interface to external memory depending on configuration of the USB5532B pins associated with each interface type. The USB5532B will first check to see whether an external SPI Flash is present. If not, the USB5532B will
operate from internal ROM. If SPI Flash is present, the chip will operate from the external ROM.
The USB5532B is capable of code execution from an external SPI ROM. On power up, the firmware looks for an external
SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If avalid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in theexternal SPI device. If a valid signature is not found, then execution continues from internal ROM. The following sections
describe the interface options to the external SPI ROM.

4.1.1

OPERATION OF THE HI-SPEED READ SEQUENCEThe SPI controller will automatically handle code reads going out to the SPI ROM Address. When the controller detects
a read, the controller drops the SPI_CE, and puts out a 0x0B, followed by the 24-bit address. The SPI controller thenputs out a DUMMY byte. The next eight clocks clock in the first byte. When the first byte is clocked in a ready signal issent back to the processor, and the processor gets one byte.
After the processor gets the first byte, its address will change. If the address is one more than the last address, the SPI
controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI
controller will terminate the transaction by taking SPI_CE high. As long as the addresses are sequential, the SPI Controller will keep clocking in data.

FIGURE 4-1:

SPI HI-SPEED READ OPERATION

USB Hub

CE#
SPI
CONTROLLER

ADDRESSCONTROL

CLK

SI

CACHE

SPI
ROM

SPI_DI
Serial to
Parllel 2012 - 2015 Microchip Technology Inc.

SO

DS00001679C-page 13

USB5532B
FIGURE 4-2:

SPI HI-SPEED READ SEQUENCESPI_CEN

15 16

0 1 2 3 4 5 6 7 8

23 24

31 32

80

71 72

63 64

55 56

47 48

39 40

SPI_CLK

ADD.

0B

SPI_DO
MSB

ADD.

ADD.

X

MSB

HIGH IMPEDANCESPI_DI

N

N+1

N+2

N+3

N+4

DOUT

DOUT

DOUT

DOUT

DOUT

MSB

4.1.2

OPERATION OF THE DUAL HI-SPEED READ SEQUENCEThe SPI controller also supports dual data mode (at 30 MHz SPI speed only). When configured in dual mode, the SPI
controller will automatically handle reads going out to the SPI ROM. When the controller detects a read, the controller
drops the SPI_CE_N, and puts out a 0x3B, followed by the 24-bit address. The SPI controller then puts out a DUMMY
byte. The next four clocks clock in the first byte. The data appears two bits at a time on data out and data in. When thefirst byte is clocked in a ready signal is sent back to the processor, and the processor gets one byte.
After the processor gets the first byte, the address will change. If the address is one more than the last address, the SPI
controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI
controller will terminate the transaction by taking SPI_CE_N high. As long as the addresses are sequential, the SPI Controller will keep clocking in data.

FIGURE 4-3:

SPI DUAL HI-SPEED READ OPERATION

USB Hub

ADDRESSCONTROLCE#
SPI
CONTROLLER
CLK

CACHE

SI

SPI
ROM

SPI_DI
2-Serial to8-Parallel

DS00001679C-page 14

SO

 2012 - 2015 Microchip Technology Inc.

USB5532B
FIGURE 4-4:

SPI DUAL HI-SPEED READ SEQUENCESPI_CEN

0 1 2 3 4 5 6 7 8

15 16

23 24

31 32

59

55 56

51 52

47 48

43 44

39 40

SPI_CLK

ADD.

0B

SPI_DO

ADD.

ADD.

X

N

N+1

N+2

N+3

D1

D2

D3

D4

D5

Bits-6,4,2,0

Bits-6,4,2,0

Bits-6,4,2,0
MSB

MSB

MSB

HIGH IMPEDANCESPI_DI

Bits-6,4,2,0 Bits-6,4,2,0

N+4

N

N+1

N+2

N+3

N+4

D1

D2

D3

D4

D5

Bits-7,5,3,1

Bits-7,5,3,1

Bits-7,5,3,1

Bits-7,5,3,1 Bits-7,5,3,1

MSB

4.1.3

32-BYTE CACHE

There is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. Once
the SPI controller detects a jump, the base address pointer is initialized to that address. As each new sequential databyte is fetched, the data is written into the cache, and the length is incremented. If the sequential run exceeds 32 bytes,
the base address pointer is incremented to indicate the last 32 bytes fetched. If the USB5532B does a jump, and thejump is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external access.

4.1.4

INTERFACE OPERATION TO SPI PORT WHEN NOT DOING FAST READS

There is an 8-byte command buffer: SPI_CMD_BUF[7:0]; an 8-byte response buffer: SPI_RESP_BUF[7:0]; and a length
register that counts out the number of bytes: SPI_CMD_LEN. Additionally, there is a self-clearing GO bit in the SPI_CTL
Register. Once the GO bit is set, the device drops SPI_CE_N, and starts clocking. It will put out SPI_CMD_LEN X 8 number of clocks. After the first byte, the COMMAND, has been sent out, and the SPI_DI is stored in the SPI_RESP buffer.
If the SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the SPI_DO line. This mode is used
for program execution out of internal RAM or ROM.

FIGURE 4-5:

SPI INTERNALLY-CONTROLLED OPERATION

USB HubCE#
SPI_CMD_LEN

SPICONTROLLER
CLK

 2012 - 2015 Microchip Technology Inc.

SPI_CMD_BUF[3:0]SI

SPI_RSP_BUF[7:0]

SO

SPI
ROM

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USB5532B
4.1.4.1

ERASE EXAMPLE

To perform a SCTR_ERASE, 32BLK_ERASE, or 64BLK_ERASE, the device writes 0x20, 0x52, or 0xD8, respectively
to the first byte of the command buffer, followed by a 3-byte address. The length of the transfer is set to 4 bytes. To dothis, the device first drops SPI_CE_N, then counts out 8 clocks. It then puts out the 8 bits of command, followed by 24
bits of address of the location to be erased on the SPI_DO pin. When the transfer is complete, the SPI_CE_N goes high,while the SPI_DI line is ignored in this example.

FIGURE 4-6:

SPI ERASE SEQUENCESPI_CEN

0 1 2 3 4 5 6 7 8

15 16

23 24

31

SPI_CLK

Command

ADD.

ADD.

ADD.

SPI_DOMSB

MSBHIGH IMPEDANCESPI_DI

4.1.4.2

BYTE PROGRAM EXAMPLE

To perform a Byte Program, the device writes 0x02 to the first byte of the command buffer, followed by a 3-byte addressof the location that will be written to, and one data byte. The length of the transfer is set to 5 bytes. The device first drops
SPI_CE_N, 8 bits of command are clocked out, followed by 24 bits of address, and one byte of data on the SPI_DO pin.
The SPI_DI line is not used in this example.

FIGURE 4-7:

SPI BYTE PROGRAM

SPI_CEN

0 1 2 3 4 5 6 7 8

15 16

23 24

31 32

39

SPI_CLK

0xDB

SPI_DOMSB

SPI_DI

DS00001679C-page 16

0x00
MSB

0xBF

0xFE
/0xFF

Data
MSB

LSB

HIGH IMPEDANCE

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USB5532B
4.1.4.3

COMMAND ONLY PROGRAM EXAMPLE

To perform a single byte command such as the following:- - WRDI- - WREN- - EWSR- - CHIP_ERASE- - EBSY- - DBSY
The device writes the opcode into the first byte of the SPI_CMD_BUF and the SPI_CMD_LEN is set to one. The device
first drops SPI_CE, then 8 bits of the command are clocked out on the SPI_DO pin. The SPI_DI is not used in this example.

FIGURE 4-8:

SPI COMMAND ONLY SEQUENCESPI_CEN

0 1 2 3 4 5 6

7

SPI_CLK

Command

SPI_DOMSB

SPI_DI

4.1.4.4

HIGH IMPEDANCEJEDEC-ID READ EXAMPLE

To perform a JEDEC-ID command, the device writes 0x9F into the first byte of the SPI_CMD_BUF and the length of thetransfer is 4 bytes. The device first drops SPI_CE_N, then 8 bits of the command are clocked out, followed by the 24
bits of dummy bytes (due to the length being set to 4) on the SPI_DO pin. When the transfer is complete, the SPI_CE_N
goes high. After the first byte, the data on SPI_DI is clocked into the SPI_RSP_BUF. At the end of the command, there
are three valid bytes in the SPI_RSP_BUF. In this example, 0xBF, 0x25, 0x8E.

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DS00001679C-page 17

USB5532B
FIGURE 4-9:

SPI JEDEC-ID SEQUENCESPI_CEN

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

SPI_CLK

9F

SPI_DOMSB

SPI_DIHIGH IMPEDANCE
BF
MSB

4.2

25

8E

MSB

SMBus Slave Interface

Next, the USB5532B will look to receive configuration and commands from an optional SMBus master (if present). When
SMBus is enabled, the SMBus can operate in either legacy (USB 2.0 only) or advanced mode (access to both USB 2.0
and 3.0 registers). Next, the USB5532B will look for (optional) configuration present in the internal OTP memory. Anyregister settings that are modified via the SMBus interface will overwrite the internal OTP settings.
The SMBus slave interface is enabled when pull-up resistors are detected on both SM_DAT and SM_CLK for the firstmillisecond after reset. For operation in SMBus Legacy Mode, an additional pull-up resistor is required on TRST. If the
SMBus interface is enabled, then the USB5532B will wait indefinitely for the SMBus host to configure the device. Once
SMBus configuration is complete, device initialization will proceed. To disable the SMBus, a pull-down resistor of 10 K
must be applied to either SM_DAT, SM_CLK, or both SM_DAT and SM_CLK if desired. If SMBus is disabled, the device
proceeds directly to device initialization using the internal OTP ROM.

4.2.1

PULL-UP RESISTOR FOR SMBUS

External pull-up resistors (10 k recommended) are required on the SM_DAT and SM_CLK pins when implementing
either SMBus mode.

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USB5532B
FIGURE 4-10:

SMBUS SLAVE CONNECTION

VDD
10 k

USB Hub
10 k

SCL
SM_CLKSDA

SM_DAT

Master

4.2.1.1

Invalid Protocol Response Behavior

Note that any attempt to update registers with an invalid protocol will not be updated. The only valid protocols are write
block and read block (described Section 5.5, "SMBus Slave Interface," on page 29), where the hub only responds to the
7-bit hardware selected slave addresses (0101100b or 0101101b). Additionally, the only valid registers for the hub are
outlined in the USB5532B Configuration Release Notes documentation.

4.2.2

SLAVE DEVICE TIMEOUT

Devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds
25 ms (TTIMEOUT, MIN). The master must detect this condition and generate a stop condition within or after the transferof the interrupted data byte. Slave devices must reset their communication and be able to receive a new START condition no later than 35 ms (TTIMEOUT, MAX).
Note:

4.2.3

Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its
communications port after a start or stop condition. The slave device timeout must be implemented.

STRETCHING THE SCLK SIGNAL

The hub supports stretching of the SCLK by other devices on the SMBus. The hub will stretch the clock as needed.

4.2.4

BUS RESET SEQUENCEThe SMBus slave interface resets and returns to the idle state upon a START condition followed immediately by a STOP
condition.

4.2.5

SMBUS ALERT RESPONSE ADDRESSThe SMBALERT# signal is not supported by the USB5532B.

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USB5532B
4.3

Reset

There are two different resets that the device experiences. One is a hardware reset (either from the internal POR reset
circuit or via the RESET_N pin) and the second is a USB Bus Reset.

4.3.1

INTERNAL POR

All reset timing parameters are guaranteed by design.

4.3.2

EXTERNAL HARDWARE RESET

A valid hardware reset is defined as assertion of RESET_N for a minimum of 1 s after all power supplies are within
operating range.
Assertion of RESET_N (external pin) causes the following:
1.
2.
3.
4.
5.

The PHY is disabled, and the differential pairs will be in a high-impedance state.
All transactions immediately terminate; no states are saved.
All internal registers return to the default state.
The external crystal oscillator is halted.
The PLL is halted.

4.4Standard Port Power Configuration

The device natively operates with standard port power controllers or poly-fuse devices for the downstream port powers
when battery charging is not enabled on a port. It is not recommended to have the downstream ports of a single device
mix poly-fuse and standard power controller support, as the configuration of the hub cannot correctly report which ports
are poly-fuse and which are port power controllers to the host.
Any port without battery charging can also be used in individual port power controls or ganged power controls. The port
power control output only supports either Ganged or Individual modes on a global basis for all downstream ports.
The overcurrent setting also supports individual or global settings, but also adds the ability to configure specific ports to
be part of an overcurrent gang with others setup for individual connections. This hybrid configuration should only be
used when utilizing poly-fuse power devices.

4.4.1

PORT POWER CONTROLLER

The most common method for downstream port power controls is to utilize current-limited power switches for USB applications. The devices allow the downstream port powers to be enabled through a control signal and report over-current
conditions through a flag output.
Two connection methods are possible for these controllers, Combined mode and Independent mode.
In Combined mode, the FLG and EN signals are tied together with an external 10K ohm pull-up and driven to a single
PRT_CTL signal on the device, as shown in Figure 4-11.

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USB5532B
FIGURE 4-11:

COMBINED MODE IMPLEMENTATION

5V

PRT_CTLOCS

USB Power
SwitchUSB553xEN

USB
DeviceIn Individual mode, the PRT_CTL signal is driven directly to the EN input of the power switch and the OCS input is connected to the FLG output of the power switch with a 10K pull-up connected, as shown in Figure 4-12.

FIGURE 4-12:

INDIVIDUAL MODE IMPLEMENTATION

5V

PRT_CTL

EN
5V

USB553x
OCS

10k

USB Power
SwitchFLG

USB
Device 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 21

USB5532B
4.4.2

POLY-FUSE

An alternate method of downstream power control is to utilize poly-fuse devices. In this configuration, the poly-fusedevices are used to report overcurrent conditions to the USB5532B through the OCS input, as shown in Figure 4-13.

FIGURE 4-13:

POLY-FUSE IMPLEMENTATION

5V

3.3V

USB553x

OCS

Poly Fuse

10k

USB
Device4.5

Charging Port Configurations

The device can also be configured to operate as a charging port for one or more downstream ports. Ganged port power
control and/or overcurrent is not supported if any of the downstream ports are configured as charging ports. If a port isconfigured to support a charging port mode, either a standard port power controller or a UCS1002 may be implemented.
For more information on charging port support, refer to Section 5.1, "Charging Port Configuration," on page 24.

4.5.1

PORT POWER CONTROLLER

The only special limitation of using the device as a charging port is that the port power controller must be capable of thehigher current to support the charging port modes. Refer to Section 4.4.1, "Port Power Controller," on page 20 for more
information on this implementation.

4.5.2

UCS1002

Using a UCS1002 device as a downstream port power controller is only supported on ports that are enabled as charging
ports.
If the UCS1002 is implemented, the USB5532B communicates with all of the implemented UCS1002 ports over SMBus
using one of the PRT_CTLx/OCSx signals as the SMCLK/SMDAT. Additionally, DYNCPDIS_N becomes the UCS_SMBALERT_N signal. Multiple UCS1002 devices may be connected to the SMBus in parallel.
After reset, for any enabled charging ports, the USB5532B performs SMBus commands on the configured
PRT_CTLx/OCSx signals and checks UCS1002 devices at specific addresses (see Table 4-1) to confirm which ports
are utilizing UCS1002 devices as the downstream power controllers.

TABLE 4-1:

UCS1002 ADDRESS MAPPINGPort

Address

1

0x30

2

0x31

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USB5532B
In this configuration, the UCS1002 is utilized as an SMBus enabled port power switch and all charging port handshaking
on the D+/D- signals are controlled directly from the USB5532B. An example implementation can be seen in Figure 414.

FIGURE 4-14:

UCS1002 CHARGING IMPLEMENTATION

USB2DM_DN1

D-

USB2DP_DN1

D+Port 1 USB 3
A-TypeReceptacle

USB3DM_RXDN1

SSRX-

USB3DP_RXDN1

SSRX+

330

USB3DM_TXDN1

0.1uF

SSTX-

USB3DP_TXDN1

0.1uF

SSTX+

ShL1

GND1

ShL2

GND2

ShR1

Vbus

ShR2

100uF

0.1uF

Shield

3.3V

PRT_CTL1
TCK/OCS1
TRST/DYNCPDIS_N/
UCS_SMBALERT_N

10K

10K

USB553x

UCS1002

VBUS1
VBUS2
SMCLK/S0

SMDATA/LATCH
5V

ALERT
M1

 2012 - 2015 Microchip Technology Inc.

DPIN

M2

DMIN

EM_EN

10K

DPOUT

COMM_SEL

33K

DMOUT

SEL

47K

DS00001679C-page 23

USB5532B
5.0

FUNCTIONAL OPERATIONThis chapter details the functional operation of various device features.

5.1

Charging Port Configuration

The USB5532B supports downstream charging ports on any available port. The hub contains internal hardware andalgorithms to natively support various voltage levels on the D+/D- signals along with the BC 1.2 Handshaking protocol,
allowing charging devices to detect the downstream port as a charging port.
A port can be configured for either RapidCharge support or Samsung Legacy Charging mode support. This section
details the various charging port modes. The following terminology will be helpful in the understanding of these features:• SDP - Standard Downstream Port - A port that is not operating as a charging port and has active USB communications.
• CDP - Charging Downstream Port - A port that is operating as a charging port and has active USB communications.
• DCP - Dedicated Charging Port - A port that is operating as a charging port but has no USB communications.
• S0 - Normal system power state in full run.
• S3 - Typically a Sleep state, where the system can be woken from USB HID devices• S4 - Typically a Hibernate sleep state, where the system state is stored to a hard drive and does not support wakefrom USB HID devices.
• S5 - Typically an OFF state for a system.

5.1.1

RAPID CHARGEThis mode enables concurrent operation of Apple, BC 1.2 and DP/DM Shorted Emulation charging. The only applicable
options are to choose Apple 1A or Apple 2A charging mode on a per port basis. Refer to Section 5.2.1.1, "Apple
Charging Mode," on page 26.
Note:

5.1.2

Apple and DP/DM Shorted Emulation charging modes are only operational in DCP mode.

SAMSUNG LEGACY CHARGINGThis mode drives a specified voltage on the DP/DM lines to allow legacy Samsung devices to detect the port as
Charging capable. This is only operational in DCP modes.

5.1.3

DYNAMIC CHARGING PORT (6080 ONLY)

Dynamic Charging Port support utilizes the device’s DYNCPDIS_N pin to disable Battery Charging support globallywhen low and, when high, allow any ports configured as Charging Ports (either through a configuration file or straps) toresume their Battery Charging operation in the configured Charging mode.
This feature is currently supported only when using standard USB port power controllers. Please contact your Microchip
FAE if required to use this feature with other port power controller configurations.
Figure 5-1, Figure 5-2, and Figure 5-3 detail the operation of Dynamic Charging Port in the S0, S3, and S4/S5 power
modes, respectively. For any of the flow diagram transitions, there is a Y/Z nomenclature.
Y = Dynamic BC enable signal
Z = Device attached and sensed by device
Note:

The Dynamic Charging Port feature and related DYNCPDIS_N pin function is available in the “-6080” version of the device only.

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DS00001679C-page 24

USB5532B
FIGURE 5-1:

S0 STATE TRANSITIONS

S0
0/X

SDP

0/0

1/1
1/0

CDP

DCP

0/1

FIGURE 5-2:

1/X

S3 STATE TRANSITIONS

S3
0/X

X/X

Power Cycle

SDP

0/X

1/X
Power Cycle

X/X

CDP

DCP

X/0
X/1

FIGURE 5-3:

1/X

S4/S5 STATE TRANSITIONS

S4/S5
0/X
X/X
SDP

Power Off
0/X

1/X

CDP

Power On

DCP

Power Cycle
X/X

X/X

1/X

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USB5532B
5.2

Configuration Options

By default, the USB5532B configuration allows the device to operate as a standard USB hub when connected to a USB
host controller. The device also contains a number of configurable options which can be set through its user interfaces:• One-Time Programmable (OTP) Memory (one time burn configuration)• External SPI (only when using external SPI firmware)• SMBus Slave Interface (controlled by SMBus host controller. Must be updated every time.)
Refer to Standard Interface Connections on page 13 for details on the SPI and SMBus interfaces.
SPI and OTP configuration can be created and applied through the Protouch tool. The following subsections detail tovarious device parameters that can be configured via the Protouch tool.

5.2.1

CHARGING PORT ENABLE

This option enables, on a per-port basis, DFPs to become charging ports. If this is enabled on a port, it must be configured as a per-port PWR/OCS control. Ganged OCS or PWR controls are not supported concurrently. The normal configuration is to support the RapidCharge protocol. Refer to Section 5.2.17, "Port Power/OCS Control," on page 27 formore information.

5.2.1.1

Apple Charging Mode

This option enables either Apple 1 Amp or Apple 2 Amp for the RapidCharge protocol charging mode when a port isconfigured as a charging port and not enabled for Samsung Mode. This mode enables the selected Apple charging
mode to operate concurrently with BC1.2.

5.2.1.2

Samsung Charging Mode

This option enables the Samsung Charging mode on a port. If this is selected, the Apple Charging mode setting is
ignored and only the Samsung charging mode is supported on that port.

5.2.1.3

UCS1002 SMBus Interface Selection

USC1002 port power controllers are only supported if battery charging is enabled on that port. When BC is enabled,
there is an option to select the external signals (PRTCTLx/OCSx) that are used for the SMBus SDA/SCL signals. Only
Ports 1-4 signals can be used. This feature is supported on the “-6080” and newer devices.

5.2.2

USB VID

This field is the 16-bit USB Vendor ID reported by both USB 2.0 and USB 3.0 hubs.

5.2.3

USB2 PID

This field is the 16-bit USB Product ID reported by the USB 2.0 hub only.

5.2.4

USB3 PID

This field is the 16-bit USB Product ID reported by the USB 3.0 Hub only.

5.2.5

USB DID

This field is the 16-bit USB Device ID reported by both the USB 2.0 and USB 3.0 hubs.

5.2.6

USB NON-REMOVABLE SETTING

This is the per-port Non-Removable setting for both USB 2.0 and USB 3.0 hubs. If any ports are set as Non-Removable,both the USB 2.0 and USB 3.0 hubs will be automatically set to report as Compound devices.

5.2.7

USB PORT DISABLES

This is the per-port setting used to disable ports for both USB 2.0 and USB 3.0 hubs.

5.2.8

USB SELF/BUS-POWEREDThis setting is used to configure the USB2 and USB3 hubs to report as Self-Powered or Bus-Powered.

5.2.9

USB SYSTEM MAX POWER

This field is the maximum total system power on VBUS including non-Removable devices if permanently attached.

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USB5532B
5.2.10USB HUB MAX CURRENT

This field is the maximum current of the hub and system components to support the hub on VBUS.

5.2.11

USB LANGUAGE ID

This field selects the USB language ID.

5.2.12

USB MANUFACTURER STRING

This field contains the manufacturer string reported by both USB 2.0 and USB 3.0 hubs (maximum of 30 characters).

5.2.13

USB 2.0 PRODUCT STRING

This field contains the product string reported by the USB 2.0 hub (maximum of 30 characters).

5.2.14

USB 3.0 PRODUCT STRING

This field contains the product string reported by the USB 3.0 hub (maximum of 30 characters).

5.2.15

USB SERIAL STRING

This field contains the serial string reported by the USB 2.0 and USB 3.0 hubs (maximum of 30 characters).

5.2.16PIN STRAP DISABLES

This setting disables the external pin configuration straps on power-up that select the following on ports 1-4:
• Port Disable• Port Non-Removable• Battery Charging Enable
If the user needs to select the above settings in a configuration file for ports 1-4, they must also disable the pin straps
to ensure the settings are not overridden by the strap controls.

5.2.175.2.17.1

PORT POWER/OCS CONTROLPer-Port PWR/OCS Combined Mode

This per-port setting controls whether the Power Enable and OCS signals are on the same pin. This setting is only valid
for ports 1-4.
Refer to Section 4.4, "Standard Port Power Configuration," on page 20 for additional port power setting details and connection diagrams.

5.2.17.2

OCS Gang Control

This setting can gang multiple ports into an OCS ganging to report overcurrent on any port in this gang.

ALL GANGEDThis single setting configures all ports into an OCS gang.

SPLIT GANGEDThis setting allows the user to gang select ports together while not ganging others.
Requires the setting of the following:• USB 2.0 hub OCS gang set• USB 3.0 hub OCS gang set• Ports contained within the OCS gang (any other ports will operate as a per-port power control/ocs)• GPIO used as OCS Gang input

5.2.17.3

USB Port Power Gang Control

This setting can gang all ports into single Port Power control.

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USB5532B
5.2.17.4

No Port Power Controls

This parameter requires setting the hubs power-on time to 0 for both USB 2.0 and USB 3.0 hubs. It also requires thesetting of the USB3 PWR_SW_CTL signal.

USB POWER-ON TIME (ADVANCED)This parameter sets the USB power-on to power Good time in 2ms intervals for both the USB 2.0 and USB 3.0 hubs.

USB 3.0 NO POWER SWITCH SELECT
When enabled, the USB 3.0 hub operates in accordance with the USB 3.0 specification for No Power Switches.

5.2.17.5

USB 2.0 Over-Current Timer

This setting controls the signal filter on the OCS pin for the USB 2.0 hub. These settings should be controlled with care,as the default configuration has been tested thoroughly.
The valid settings are:• 50ns• 1000ns• 200ns• 400ns

5.2.17.6

USB 3.0 Over-Current Timer

This setting controls the signal filter on the OCS pin for the USB 3.0 hub. These settings should be controlled with care,as the default configuration has been tested thoroughly.
The valid settings are:• 750ns• 10000ns• 1250ns• 1500ns

5.2.18USB2 PORT DP/DM PIN SWAP

This per-port setting internally swaps the DP and DM signals for the USB 2.0 port.
Port 0 = UFP
Port 1-7 = DFP ports 1-7

5.2.19USB 2.0 PORT HS OUTPUT CURRENT

This per-port setting boosts the USB High-Speed driver output.
Port 0 = UFP
Port 1-7 = DFP ports 1-7
Settings are defined within the Protouch tool.

5.2.20USB 2.0 PORT SQUELCH

This per-port setting modifies the USB input squelch setting.
Port 0 = UFP
Port 1-7 = DFP ports 1-7
Settings are defined within the Protouch tool.

5.2.21

USB 2.0 HUB ADVANCED CONTROLSThe settings in the following sub-sections are advanced controls, which most applications will not require to be set, since
the default configurations allow seamless operation. Only advanced users/applications should override the default configurations detailed here.

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USB5532B
5.2.21.1

USB 2.0 HS Disable

This setting disables USB High-Speed operation on the entire USB 2.0 hub.

5.2.21.2

USB 2.0 MTT Disable

This setting disables the Multi-TT operation on the entire USB 2.0 hub.

5.2.21.3

USB 2.0 FS EOP Disable

This setting disables the End Of Packet (EOP) generation of End Of Frame 1 (EOF1) when in Full-Speed mode.

5.2.22UUID OVERRIDE

These controls allow the user to override the 128-bit UUID value within the device (set at the Microchip Factory as aunique value for each device). By USB Specification, if multiple devices are connected within one system as a single
Compound Device, all UUID (within the BOS descriptor) should be set the same.

5.3

One-Time Programmable (OTP) Memory

The device contains an internal One-Time Programmable memory, which allows various configuration settings to be
configured for the end application. This memory requires a configuration to be created through the Microchip ProTouch
tool or by a Microchip FAE. The ProTouch tool then allows programming of this block over a USB 2.0 connection to a
Microsoft Windows Host.
There is also an option to support OTP programming via the SMBus interface. However, this method of OTP programming is not preferred. Please contact your local Microchip FAE for more information on OTP programming via SMBus.

5.3.1

CONFIGURATION FILE CREATION

For information on configuration file creation, refer to the ProTouch tool.

5.4

External SPI

The device supports operation utilizing an external SPI Flash or ROM. In normal operation, the internal microcontroller
runs from the internal ROM. If an external SPI memory is implemented, the full Firmware image must be loaded into the
SPI.
When using an external SPI memory, there are two options available. The configuration can be loaded from the internal
OTP, or the internal OTP can be ignored and the configuration file loaded into the SPI memory.
Please contact your Microchip FAE for more information on how to obtain access to an external SPI memory image andhow to support the different configuration options.
For information on SPI interface connections, refer to Section 4.1, "SPI Interface," on page 13.

5.4.1

CONFIGURATION FILE CREATION

For information on configuration file creation, refer to the ProTouch tool.

5.5

SMBus Slave Interface

Typical block write and block read protocols are shown in Figure 5-6 and Figure 5-5. SMBus RAM buffer offset accesses
are performed using 7-bit slave addressing, a 16-bit SMBus RAM buffer offset field (for legacy and advanced modes,
respectively), and an 8-bit data field. The shading shown in the figures during a read or write indicates the hub is driving
data on the SM_DAT line; otherwise, host data is on the SM_DAT line.
The SMBus slave address assigned to the hub (0101100b or 0101101b) allows it to be identified on the SMBus. The
SMBus RAM buffer offset field is the internal offset in SMBus RAM to be accessed. The data field is the data that thehost is attempting to read/write from/to the SMBus RAM buffer.
Note:

Data bytes are transferred MSB first.

For information on connecting the SMBus slave interface to a host, refer to Section 4.2, "SMBus Slave Interface," onpage 18.

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USB5532B
5.5.1

BLOCK WRITE

The block write begins with a slave address and a write condition. After the command code, the host issues a byte countwhich describes how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would
be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be zero. A block write or read allows
a transfer maximum of 32 data bytes.
For the following SMBus tables:

FIGURE 5-4:

BLOCK WRITE
Denotes Master-to-Slave

Denotes Slave-to-Master

1

7

1

1

16

1

S

Slave Address

Wr

A

SMBus RAM Buffer Offset

A

...

8

1

8

1

8

1

8

1

1

Byte Count = N

A

Data byte 1A

Data byte 2A

Data byte N

A

P

5.5.2

BLOCK READ

A block read differs from a block write in that the repeated start condition exists to satisfy the I2C specification’s requirement for a change in the transfer direction.

FIGURE 5-5:
1S

BLOCK READ
7

1

Slave Address

Wr

1

16

1

1

7

1

1

A

SMBus RAM
Buffer Offset

A

S

Slave Address

Rd

A

...

8

1

8

1

8

1

8

1

1

Byte Count = N

A

Data byte 1A

Data byte 2A

Data byte N

A

P

5.5.3

STANDARD SMBUS COMMANDS

There are special commands that can be sent in the place of the 16-bit address bytes. These commands are used toenumerate the hub, access the configuration registers, or simply reset the device. The commands consist of the 16-bit
command followed by a 00h byte to terminate the command.

FIGURE 5-6:

SMBUS COMMANDS

1

7

1

1

16

1

S

Slave Address

Wr

A

OPCODEA

 2012 - 2015 Microchip Technology Inc.

...

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TABLE 5-1:

SPECIAL SMBUS COMMANDS

Operation

OPCODE

Reboot9936hReboot internal MCU.

Configuration Register
Access9937hRead and Write Configuration Registers

Extended Command

993Eh

Execute Extended Status Commands

USB Attach

AA55hEnter Configuration StageUSB Attach with SMBus
Access

AA56hEnter Configuration Stage with SMBus Access Enabled

5.5.4

Description

SPECIAL HUB COMMANDS

Below is a list of the extended commands and the code used to execute them.

TABLE 5-2:

EXTENDED COMMANDS

Command

Code

Set Address

00h

Get Default Address

01h

Get Hub Info

02h

Get UCS Port Mask

03h

Port Connect Status

80h

Port Power Status

81h

Port Force Disable

82h

Port DP/DM Status

83h

UCS Byte Read84h

UCS Byte Write

85h

UCS Block Read86h

UCS Block Write

87h

The extended commands provide access to the status of the device. From these registers a SMBus controller can see
the connection status of the hub, communicate with the UCS1000, and change the SMBus address if desired. Whenthe extended command is sent the hub will interpret the memory starting at offset 00h as follows:

TABLE 5-3:

MEMORY FORMAT FOR EXTENDED HUB COMMAND

RAM Address

Description

Notes

0000h

Command

Code of the extended command to execute.

0001h

Status

Always write 0 to this register, it will be updated after the command is executed with the status.

0002h

Data1

The first byte of data to write to or read from when executing the command.

...

...

...

0004h+N

DataN

The Nth byte of data to write to or read from when executing the command.

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5.5.4.1

Special Command Example

The following example shows how to read the Charger Detection register to find out what type of charger the hub has
connected to:
1.

First write data to the memory of the hub.

TABLE 5-4:

EXAMPLE SMBUS WRITE COMMAND

Byte
0

Value

Comment

5Ah

Address plus write bit.

100h

Memory address 0000h.

200h

Memory address 0000h.

303h

Number of bytes to write to memory.

480h

Get Port Device Status.

500h

Reading one data bytes.

6

1Fh

Read all ports.

2.

After the data is written, execute the Configuration Register Access command.

TABLE 5-5:

CONFIGURATION REGISTER ACCESS COMMAND

Byte

Value

Comment

05Ah

Address plus write bit.

1

99hCommand 993Eh.

2

3Eh

Command 993Eh.

300h

Command Completion.

3.

Finally, read back data starting at memory offset 04h, which is where the Data byte starts.

TABLE 5-6:

EXAMPLE SMBUS READ COMMAND

Byte
0

Value

Comments

5Ah

Address plus Write bit.

100h

Memory Address 0004h.

203h

Memory Address 0004h.

059h

Address plus Read bit.

1

80h

Device sends 128 bytes of data.

2

03hUpstream Connection Status. (SS and HS)

302hPort 1 Connection Status. (HS/FS/LS Only)

401h

Port 2 Connection Status. (SS Only)

Although the device can send out 128 bytes of memory data, it isn’t necessary to read the entire set, the SMBus Mastercan send a stop at any time.

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5.5.4.2

Set Address (00h)The set address command will change the SMBus address to the value in Data1 or memory address 0002h. The next
SMBus read will have to account for this change in address.

TABLE 5-7:

SET ADDRESS BYTESET ADDR(0X00)

Bit

SMBus Address

Name

R/W

Description

7

DEFAULT

W

Resets to the default SMBus address.

7:0

ADDRESSW

New SMBus Address

5.5.4.3

Get Default Address (01h)This command will always return the default address of the USB5x3xB (2dh).

5.5.4.4

Get Hub Info (02h)The command will return the status of the hub in Data1. The status byte follows the following format:

TABLE 5-8:

HUB INFORMATION

USB2_HUB_INFO(0X02)Bit

Name

USB2 Hub Information
R/W

Description

7

CONFIGURED

R

1 = Hub is in the configured state.
2 = Hub is in the unconfigured state.

6:0

USB2_ADDRESSR

The address of the USB2 hub.

5.5.4.5

Get UCS Port Mask(03h)This will return a mask of which port is assigned a UCS port controller based on the UCS device detection.

5.5.4.6

Port Connect Status (80h)Data1 of the memory is written by the SMBus master and after the command is executed Data 2-6 will be populatedwith the status of each port.
Data1 is a port mask where each bit represents the port status to return. Bit 0 is the upstream port, bit 1 is the downstream port 1, etc.
The port connect status byte can be interpreted as follows:

TABLE 5-9:

HUB INFORMATION

PORT_CONNECT(0X80)Bit

Name

Port Connect Status
R/W

Description

7:6

Reserved

R

Reserved

5

USB2_SUSPEND

R

0 = Port is not suspended.
1 = Port is in the L2 Suspend State.

4

USB3_SUSPEND

R

0 = Port is not suspended.
1 = Port is in the U3 Suspend State.

3:2

Reserved

R

Reserved

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TABLE 5-9:

HUB INFORMATION (CONTINUED)

PORT_CONNECT(0X80)Bit

Name

Port Connect Status
R/W

Description

1

USB2_CONNECTR

0 = No USB2 connection detected. (HS/FS/LS)
1 = USB2 connection detected.

0

USB3_CONNECTR

0 = No USB3 connection detected.
1 = USB3 connection detected.

5.5.4.7

Port Power Status (81h)Data1 of the memory is written by the SMBus master and after the command is executed Data 2-6 will be populatedwith the status of each port. A ‘1’ means the port power is enabled, a ‘0’ means the port power is disabled.
Data1 is a port mask where each bit represents the port status to return. Bit 0 is the upstream port, bit 1 is the downstream port 1, etc.

5.5.4.8

Port Force Disable (82h)Data1 of the memory is the port mask and Data 2-6 is the port disable state requested.
Data1 is a port mask where each bit represents the port status to return. Bit 0 is the upstream port, bit 1 is the downstream port 1, etc.
The port disable byte will be interpreted as follows:

TABLE 5-10:

HUB INFORMATION

PORT_DISABLE(0X82)Bit

Name

Port Disable
R/W

Description

7

OVERWRITEW

If this bit is 1 then the data in bits 2:0 will be overwritten.

6:3

Reserved

W

Reserved

2

FORCE_OFFW

0 = Port Power controlled by hub.
1 = Port Power forced off.

1

USB3_TERM_DIS

W

0 = USB3 Terminations controlled by hub.
1 = USB3 Terminations disabled.

0

USB2_TERM_DIS

W

0 = USB2 Terminations controlled by hub.
1 = USB2 Terminations disabled.

5.5.4.9

Port DP/DM Status (83h)Data1 of the memory is written by the SMBus master and after the command is executed Data 2-6 will be populatedwith the status of each port.
Data1 is a port mask where each bit represents the port status to return. Bit 0 is the upstream port, bit 1 is the downstream port 1, etc.
The port DP/DM status byte can be interpreted as follows:

TABLE 5-11:

PORT DP/DM STATUS

PORT_DPDM(0X83)Bit

Name

Port DP/DM Status
R/W

Description

7:2

Reserved

W

Reserved

1

FS_DM

W

0 = DM line is below the FS threshold.
1 = DM line is above the FS threshold (LS idle state)

0

FS_DP

W

0 = DP line is below the FS threshold.
1 = DP line is above the FS threshold. (FS idle state) 2012 - 2015 Microchip Technology Inc.

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5.5.4.10

UCS Byte Read (84h)

The first data byte (Data1) contains the address of the UCS register to read. The second data byte (Data2) will containthe data after the command is executed.

5.5.4.11

UCS Byte Write (85h)

The first data byte (Data1) contains the address of the UCS register to write to. The second data byte (Data2) contains
the data to be written.

5.5.4.12

UCS Block Read (86h)

The first data byte (Data1) contains the address of the UCS register to read. The second data byte (Data2) contains thenumber of bytes to read. The subsequent data bytes will be populated with the contents of the Data2 registers startingat Data1.

5.5.4.13

UCS Block Write (87h)

The first data byte (Data1) contains the address of the UCS register to write to. The second data byte (Data2) contains
the number of bytes to write. The subsequent data bytes contain the data to write.

5.6

Runtime Register Definitions

Below is the list of configuration registers and their address. The INIT column contains the values that will be loaded
when the USB Attach commands are sent. Register definitions are provided in the subsequent sub-sections. For information on accessing these registers, refer to Section 5.6.1, "Accessing Runtime Registers," on page 36.

TABLE 5-12:

CONFIGURATION REGISTER MEMORY MAP

ADDR

R/W

Name

0806h

R/W

LED0_PIO0_CTL1

LED0/PIO0 Register 1

00h

0807h

R/W

LED0_PIO0_CTL2

LED0/PIO0 Register 2

00h

0808h

R/W

LED1_PIO1_CTL1

LED1/PIO1 Register 1

00h

0809h

R/W

LED1_PIO1_CTL2

LED1/PIO1 Register 2

00h

082Dh

R/W

VBUS_OCS_PD

VBUS and OCS Pull-Down Register

00h

082Fh

R/W

LED0_PD

LED0 Pull-down Register

00h

0831h

R/W

VBUS_OCS_DIR

VBUS and OCS Direction Register

00h

0833h

R/W

LED0_DIR

LED0 Direction Register

00h

0835h

R/W

VBUS_OCS_OUT

VBUS and OCS Output Register

00h

0837h

R/W

LED0_OUT

LED0 Output Register

00h

0839h

R/W

VBUS_OCS_IN

VBUS and OCS Input Register

Note 5-1

083Bh

R/W

LED0_IN

LED0 Input Register

Note 5-1

083Dh

R/W

VBUS_OCS_PU

VBUS and OCS Pull-up Resistor Register

FEh

083Fh

R/W

LED0_PU

LED0 Pull-up Resistor Register

00h

092Eh

R/W

PRT_PWR_PD

Port Power Pull-down Resistor Register

00h

0932h

R/W

PRT_PWR_DIR

Port Power Direction Register

00h

0936h

R/W

PRT_PWR_OUT

Port Power Output Register

00h

093Ah

R/W

PRT_PWR_IN

Port Power Input Register

Note 5-1

DS00001679C-page 35

FunctionINIT

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USB5532B
TABLE 5-12:

CONFIGURATION REGISTER MEMORY MAP (CONTINUED)

ADDR

R/W

093Eh

R/W

PRT_PWR_PU

Port Power Pull-up Resistor Register

00h

3C00h

R/W

PRT_PWR_SEL1

Port 1 Power Select Register

03h

3C04h

R/W

PRT_PWR_SEL2

Port 2 Power Select Register

03h

3C20h

R/W

OCS_CFG_SEL1

Port 1 OCS Select Register

01h

3C24h

R/W

OCS_CFG_SEL2

Port 2 OCS Select Register

01h

5246h

R/W

CDP_DETECT

Charging Downstream Detected Register

Note 5-1

525Ah

R/W

OSC_GANGOCS Gang Control Register

00h

525Bh

R/W

OCS_GANG_GPIOOCS Gang Signal Select Register

00h

60CAh

R/W

HS_UP_BOOST

USB Upstream Boost Register

00h

60CCh

R/W

HS_UP_SENSE

USB Upstream VariSense Register

00h

61C0h

R/W

SS_UP_STATE

USB3 Upstream Link State Register

Note 5-1

64CAh

R/W

HS_P1_BOOST

USB Port 1 Boost Register

00h

64CCh

R/W

HS_P1_SENSE

USB Port 1 VariSense Register

00h

65C0h

R/W

SS_P1_STATE

USB3 Port 1 Link State

Note 5-1

68CAh

R/W

HS_P2_BOOST

USB Port 2 Boost Register

00h

68CCh

R/W

HS_P2_SENSE

USB Port 2 VariSense Register

00h

69C0h

R/W

SS_P2_STATE

USB3 Port 2 Link State

Note 5-1

Note 5-1

5.6.1

Name

Function

INIT

Status registers do not have a default value because the status can change depending on system
conditions.

ACCESSING RUNTIME REGISTERS

The Configuration Register Access operation allows the SMBus Master to read or write to the internal registers of thehub. When the Configuration Register Access command is sent the hub will interpret the memory starting at offset 00h
as follows:

TABLE 5-13:

MEMORY FORMAT FOR CONFIGURATION REGISTER ACCESSRAM Address

Description

Notes

0000h

Direction

0 = Register Write, 1 = Register Read.

0001h

Data Length

Number of bytes to Read/Write when executing the command.

0002h

Configuration
Address MSB

The upper byte of the 16-bit configuration register address.

0003h

Configuration
Address LSB

The lower byte of the 16-bit configuration register address.

0004h

Data1

The first byte of data to write to or read from the Configuration Address.

...

...

...

0004h+N

DataN

The Nth byte of data to write to or read from the Configuration Address, N
is equal to the Data Length.

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5.6.1.1

Configuration Register Write Example

The following example shows how the SMBus messages will be formatted to set the VID of the hub to a custom value,
AA55h.
1.

Write data to the memory of the hub:

TABLE 5-14:

EXAMPLE SMBUS WRITE COMMAND

Byte

Value

Comment

05Ah

Address plus write bit.

100h

Memory address 0000h.

200h

Memory address 0000h.

306h

Number of bytes to write to memory.

400h

Write Configuration Register.

5

02h

Writing two data bytes.

630h

VID is in register 3000h.

700h

VID is in register 3000h.

855h

LSB of Vendor ID AA55h.

9AAh

MSB of Vendor ID AA55h.

2.

Execute the Configuration Register Access command:

TABLE 5-15:

CONFIGURATION REGISTER ACCESS COMMAND

Byte

Value

Comment

05Ah

Address plus write bit.

1

99hCommand 9937h.

237h

Command 9937h.

300h

Command Completion.

5.6.1.2

Configuration Register Read Example

The following example shows how to read the Charger Detection register to find out what type of charger the hub has
connected to:1.

Write data to the memory of the hub.

TABLE 5-16:

EXAMPLE SMBUS WRITE COMMAND

Byte

Value

Comment

05Ah

Address plus write bit.

100h

Memory address 0000h.

200h

Memory address 0000h.

304h

Number of bytes to write to memory.

4

01h

Read Configuration Register.

5

01h

Reading one data bytes.

630h

BC Detect is in register 30E2h.

7E2h

BC Detect is in register 30E2h.

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USB5532B
2.

Execute the Configuration Register Access command.

TABLE 5-17:

CONFIGURATION REGISTER ACCESS COMMAND

Byte

Value

Comment

0

5Ah

1

99h

Command 9937h.

237h

Command 9937h.

300h

Command Completion.

3.

Address plus write bit.

Read back data starting at memory offset 04h, which is where the Data byte starts.

TABLE 5-18:

EXAMPLE SMBUS READ COMMAND

Byte

Value

Comments

05Ah

Address plus Write bit.

100h

Memory Address 0004h.

204h

Memory Address 0004h.

359h

Address plus Read bit.

480h

Device sends 128 bytes of data.

556hCharging Downstream Port Detected.
Although the device can send out 128 bytes of memory data, it isn’t necessary to read the entire set, the SMBus Mastercan send a stop at any time.

5.6.2

LED0/PIO0 REGISTER 1

TABLE 5-19:

LED0/PIO0 REGISTER 1

LED0_CTL1(0X0806)
Bit

Name

LED0_PIO0 Control Register
R/W

Description

7

XNOR

R/W

This bit toggles the polarity of the LED output. It can be used to invert thepolarity.

6

MODE

R/W

0 - Blink the LED.
1 - Breath the LED.

5:0

RATE

R/W

In Blink mode: This is the Blink Rate of LED in 50 ms increments. Duty
cycle of 50%. Rate range is 50 ms to 3.15 seconds.
In Breath mode: This is the time for an active breadth in 500 ms
increments.

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5.6.3

LED0/PIO0 REGISTER 2TABLE 5-20:

LED0/PIO0 REGISTER 2

LED0_CTL2(0X0807)

LED0_PIO0 Control Register 2

Bit

Name

R/W

Description

7:2

TRAILOFF_TIME

R/W

In Blink mode: Time the LED must continue blinking after LED_ON isturned off. TRAIL_TIME is in 50ms increments. Range is 50 ms to 3.15
seconds.
In Breath mode: This is the time for an sleeping in between breadths in
500 ms increments

1

LED_ONR/W

If LED_ON is set, then start blinking or breathing this LED.
Blink timer starts when this bit is enabled. No short blinks permitted.
When this bit is disabled, blinking stops when TRAIL_TIME expires.
In Breath Mode: Breath timer starts when this bit is enabled. No short
blinks permitted. When this bit is disabled, blinking stops immediately.

0

LED_PIO

5.6.4

LED1/PIO1 REGISTER 1

TABLE 5-21:

R/W‘0’ = PIO0
‘1’ = LED0

LED1/PIO1 REGISTER 1

LED1_CTL1(0X0808)
Bit

Name

LED1_PIO1 Control Register
R/W

Description

7

XNOR

R/W

This bit toggles the polarity of the LED output. It can be used to invert thepolarity.

6

MODE

R/W

0 - Blink the LED.
1 - Breath the LED.

5:0

RATE

R/W

In Blink mode: This is the Blink Rate of LED in 50 ms increments. Duty
cycle of 50%. Rate range is 50 ms to 3.15 seconds.
In Breath mode: This is the time for an active breadth in 500 ms
increments.

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5.6.5

LED1/PIO1 REGISTER 2TABLE 5-22:

LED1/PIO1 REGISTER 2

LED1_CTL2(0X0809)Bit
7:2

LED1_PIO1 Control Register

Name

R/W

Description

TRAILOFF_TIME

R/W

In Blink mode: Time the LED must continue blinking after LED_ON isturned off. TRAIL_TIME is in 50ms increments. Range is 50 ms to 3.15
seconds.
In Breath mode: This is the time for an sleeping in between breadths in
500 ms increments.

1

LED_ONR/W

If LED_ON is set, then start blinking or breathing this LED.
Blink timer starts when this bit is enabled. No short blinks permitted. When
this bit is disabled, blinking stops when TRAIL_TIME expires.
In Breath Mode: Breath timer starts when this bit is enabled. No short
blinks permitted. When this bit is disabled, blinking stops immediately.

0

LED_GPIO

5.6.6

VBUS AND OCS PULL-DOWN REGISTERTABLE 5-23:

R/W‘0’ = PIO1
‘1’ = LED1

VBUS AND OCS PULL-DOWN REGISTER

VBUS_OCS_PD(0X082D)
Bit

Name

VBUS and OCS Pull-Down Register
R/W

Description

7:5

Reserved

R/W

Reserved

4

OCS4

R/W

“0” = Disables the pull-down resistor on the OCS4 pin.
“1” = Enables the pull-down resistor on the OCS4 pin.

3

OCS3

R/W

“0” = Disables the pull-down resistor on the OCS3 pin.
“1” = Enables the pull-down resistor on the OCS3 pin.

2

OCS2

R/W

“0” = Disables the pull-down resistor on the OCS2 pin.
“1” = Enables the pull-down resistor on the OCS2 pin.

1

OCS1

R/W

“0” = Disables the pull-down resistor on the OCS1 pin.
“1” = Enables the pull-down resistor on the OCS1 pin.

0

VBUS

R/W

“0” = Disables the pull-down resistor on the VBUS pin.
“1” = Enables the pull-down resistor on the VBUS pin.

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USB5532B
5.6.7

LED0 PULL-DOWN REGISTERTABLE 5-24:

LED0 PULL-DOWN REGISTER
LED0_PD(0X082F)

Bit

Name

LED0 Pull-Down Register
R/W

Description

7:1

Reserved

R/W

Reserved.

0

LED0

R/W

“0” = Disables the pull-down resistor on the LED0 pin.
“1” = Enables the pull-down resistor on the LED0 pin.

5.6.8

VBUS AND OCS DIRECTION REGISTERTABLE 5-25:

VBUS AND OCS DIRECTION REGISTER

VBUS_OCS_DIR(0X0831)Bit

Name

VBUS and OCS Direction Register
R/W

Description

7:5

Reserved

R/W

Reserved

4

OCS4

R/W

Direction: 0 = In, 1 = Out.

3

OCS3

R/W

Direction: 0 = In, 1 = Out.

2

OCS2

R/W

Direction: 0 = In, 1 = Out.

1

OCS1

R/W

Direction: 0 = In, 1 = Out.

0

VBUS

R/W

Direction: 0 = In, 1 = Out.

5.6.9

LED0 DIRECTION REGISTERTABLE 5-26:

LED0 DIRECTION REGISTER
LED0_DIR(0X0833)

Bit

Name

LED0 Direction Register 1
R/W

Description

7:1

Reserved

R/W

Reserved

0

LED0

R/W

Direction: 0 = In, 1 = Out.

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USB5532B
5.6.10

VBUS AND OCS OUTPUT REGISTERTABLE 5-27:

VBUS AND OCS OUTPUT REGISTER

VBUS_OCS_OUT(0X0835)Bit

Name

VBUS and OCS Register
R/W

Description

7:5

Reserved

R/W

Reserved

4

OCS4

R/W

Output Buffer Data.

3

OCS3

R/W

Output Buffer Data.

2

OCS2

R/W

Output Buffer Data.

1

OCS1

R/W

Output Buffer Data.

0

VBUS

R/W

Output Buffer Data.

5.6.11

LED0 OUTPUT REGISTERTABLE 5-28:

LED0 OUTPUT REGISTER
LED0_OUT(0X0837)

Bit

Name

LED0 Output Register
R/W

Description

7:1

Reserved

R/W

Reserved

0

LED0

R/W

PIO0 Output Buffer Data. This bit has no meaning if PIO0 is in LED
mode.

5.6.12

VBUS AND OCS INPUT REGISTERTABLE 5-29:

VBUS AND OCS INPUT REGISTER

VBUS_OCS_IN(0X0839)Bit

Name

VBUS and OCS Input Register
R/W

Description

7:5

Reserved

R

Reserved

4

OCS4

R

Input Buffer Data.

3

OCS3

R

Input Buffer Data.

2

OCS2

R

Input Buffer Data.

1

OCS1

R

Input Buffer Data.

0

VBUS

R

Input Buffer Data.

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USB5532B
5.6.13

LED0 INPUT REGISTERTABLE 5-30:

LED0 INPUT REGISTER
LED0_IN(0X083B)

Bit

Name

LED0 Input Register
R/W

Description

7:1

Reserved

R

Reserved

0

LED0

R

PIO0 Input Buffer Data. This bit is not valid if PIO0 is in LED mode.

5.6.14

VBUS AND OCS PULL-UP RESISTOR REGISTERTABLE 5-31:

VBUS AND OCS PULL-UP RESISTOR REGISTER

VBUS_OCS_PU(0X083D)
Bit

Name

VBUS and OCS Pull-Up Register
R/W

Description

7:5

Reserved

R/W

Reserved

4

OCS4

R/W

“0” = Disables the pull-up resistor on the OCS4 pin.
“1” = Enables the pull-up resistor on the OCS4 pin.

3

OCS3

R/W

“0” = Disables the pull-up resistor on the OCS3 pin.
“1” = Enables the pull-up resistor on the OCS3 pin.

2

OCS2

R/W

“0” = Disables the pull-up resistor on the OCS2 pin.
“1” = Enables the pull-up resistor on the OCS2 pin.

1

OCS1

R/W

“0” = Disables the pull-up resistor on the OCS1 pin.
“1” = Enables the pull-up resistor on the OCS1 pin.

0

VBUS

R/W

“0” = Disables the pull-up resistor on the VBUS pin.
“1” = Enables the pull-up resistor on the VBUS pin.

5.6.15

LED0 PULL-UP RESISTOR REGISTERTABLE 5-32:

LED0 PULL-UP RESISTOR REGISTER
LED0_PU(0X083F)

Bit

Name

LED0 Pull-Up Register
R/W

Description

7:1

Reserved

R/W

Reserved

0

LED0

R/W

“0” = Disables the pull-up resistor on the LED0 pin.
“1” = Enables the pull-up resistor on the LED0 pin.

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USB5532B
5.6.16

PORT POWER PULL-DOWN RESISTOR REGISTERTABLE 5-33:

PORT POWER PULL-DOWN RESISTOR REGISTER

PRT_PWR_PD(0X092E)

Port Power Pull-Down Register

Bit

Name

R/W

Description

7:1

PRT_PWR_PD[7:1]

R/W“0” = Disables the pull-down resistor on the PRT_PWR[N] pad. Where N
is the bit being controlled. Bit 1 controls PRT_PWR 1 and so on.
“1” = Enables the pull-down resistor on the PRT_PWR[N] pad.

0

Reserved

R/W

Reserved

5.6.17

PORT POWER DIRECTION REGISTERTABLE 5-34:

PORT POWER DIRECTION REGISTER

PRT_PWR_DIR(0X0932)

Port Power Direction Register

Bit

Name

R/W

Description

7:1

PRT_PWR_D[7:1]

R/W

PRT_PWR[7:1] Direction: 0 = In, 1 = Out.

0

Reserved

R/W

Reserved

5.6.18PORT POWER OUTPUT REGISTERTABLE 5-35:

PORT POWER OUTPUT REGISTER

PRT_PWR_OUT(0X0936)

Port Power Output Register

Bit

Name

R/W

7:1

PRT_PWR_O[7:1]

R/W

PRT_PWR[7:1] Output Buffer Data.

0

Reserved

R/W

Reserved

5.6.19PORT POWER INPUT REGISTERTABLE 5-36:

Description

PORT POWER INPUT REGISTER

PRT_PWR_IN(0X093A)
Bit

Name

Port Power Input Register
R/W

Description

7:1

PRT_PWR[7:1]

R

PRT[7:1] Input Buffer Data.

0

Reserved

R

Reserved

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USB5532B
5.6.20PORT POWER PULL-UP RESISTOR REGISTERTABLE 5-37:

PORT POWER PULL-UP RESISTOR REGISTER

PRT_PWR_PU(0X093E)

Port Power PULL UP REGISTER

BIT

NAME

R/W

DESCRIPTION

7:1

PRT_PWR_PU[7:1]

R/W“0” = Disables the pull-up resistor on the PRT_PWR[N] pad. Where N isthe bit being controlled. Bit 1 controls PRT_PWR 1 and so on.
“1” = Enables the pull-up resistor on the PIO pad.

0

Reserved

R

Reserved

5.6.21PORT 1 POWER SELECT REGISTER

The bits in this register are configured via a configuration file. Users must not change the values of these settings
dynamically.

TABLE 5-38:

PORT 1 POWER SELECT REGISTER

PRT_PWR_SEL1(0X3C00)
Bit

Port 1 Power Select

Name

R/W

7

COMBINED_MODE

R/W

0 - The Port Power and over-current sense use separate pins.
1 - The Port Power and over-current sense use the same pins.

6

Reserved

R

Reserved

5

DISABLED

R/W

When set this disables the port. Used to inform the hub a port ispermanently disabled.

4

NR_DEVICE

R/W

When set indicates this port has a permanently attached device.

3:0

PRT_SEL

R/W

This selects the source for the port power for port10000b - Port Power is disabled for this Port.
0001b - Port is on if USB2 port power is on
0010b - Port is on if USB3 port power is on
0011b - Port is on if USB2 or USB3 port power is on
0100b - Port is on if designated GPIO is on
All other values are reserved.

Note:

The port disable, port non-removable and combined mode bits must be set through a configuration file toensure functionality when the part enumerates.

DS00001679C-page 45

Description

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USB5532B
5.6.22

PORT 2 POWER SELECT REGISTER

The bits in this register are configured via a configuration file. Users must not change the values of these settings
dynamically.

TABLE 5-39:

PORT 2 POWER SELECT REGISTER

PRT_PWR_SEL2(0X3C04)
Bit

Port 2 Power Select

Name

R/W

7

COMBINED_MODE

R/W

0 - The Port Power and over-current sense use separate pins.
1 - The Port Power and over-current sense use the same pins.

6

Reserved

R

Reserved

5

DISABLED

R/W

When set this disables the port. Used to inform the hub a port ispermanently disabled.

4

NR_DEVICE

R/W

When set indicates this port has a permanently attached device.

3:0

PRT_SEL

R/W

This selects the source for the port power for port10000b - Port Power is disabled for this Port.
0001b - Port is on if USB2 port power is on
0010b - Port is on if USB3 port power is on
0011b - Port is on if USB2 or USB3 port power is on
0100b - Port is on if designated GPIO is on
All other values are reserved.

Note:

The port disable, port non-removable and combined mode bits must be set through a configuration file toensure functionality when the part enumerates.

5.6.23

Description

PORT 1 OCS SELECT REGISTER

The bits in this register are configured via a configuration file. Users must not change the values of these settings
dynamically.

TABLE 5-40:

PORT 1 OCS SELECT REGISTEROCS_CFG_SEL1(0X3C20)
Bit

Name

Port 1 OCS SelectR/W

Description

7:4

Reserved

R/W

Reserved.

3:0

OCS_SEL

R/W

This selects the source for the port power for port10000b - The port is disabled
0001b - OCS comes from OCS pin
0010b - OCS comes from GPIO
1111b - OCS is force on (for testing)
All other values are reserved.

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USB5532B
5.6.24

PORT 2 OCS SELECT REGISTER

The bits in this register are configured via a configuration file. Users must not change the values of these settings
dynamically.

TABLE 5-41:

PORT 2 OCS SELECT REGISTEROCS_CFG_SEL2(0X3C24)
Bit

Name

Port 2 OCS SelectR/W

Description

7:4

Reserved

R/W

Reserved.

3:0

OCS_SEL

R/W

This selects the source for the port power for port10000b - The port is disabled
0001b - OCS comes from OCS pin
0010b - OCS comes from GPIO
1111b - OCS is force on (for testing)
All other values are reserved.

5.6.25CHARGING DOWNSTREAM DETECTED REGISTERTABLE 5-42:

CHARGING DOWNSTREAM DETECTED REGISTERCDP_DETECT(0X5246)
Bit

Name

Charging Downstream Detected
R/W

Description

7:2

Reserved

R/W

Reserved

1

P2_CDP

R/W

0 = No CDP handshake detected.
1 = Charging Downstream Port handshake detected prior to
enumeration.

0

P1_CDP

R/W

0 = No CDP handshake detected.
1 = Charging Downstream Port handshake detected prior to
enumeration.

5.6.26OCS GANG CONTROL REGISTERTABLE 5-43:

OCS GANG CONTROL REGISTEROCS_GANG(0X525A)Bit

Name

OCS Gang Control
R/W

Description

7:3

Reserved

R/W

Reserved

2

P2_OCS_GANG

R/W

Setting this bit to 1 will cause this ports OCS status to be ganged to theselected pin.

1

P1_OCS_GANG

R/W

Setting this bit to 1 will cause this ports OCS status to be ganged to theselected pin.

0

Reserved

R/W

Reserved

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USB5532B
5.6.27OCS GANG SIGNAL SELECT REGISTERTABLE 5-44:

OCS GANG SIGNAL SELECT REGISTEROCS_GANG_GPIO(0X525B)OCS Gang Control

Bit

Name

R/W

7:6

RESERVED

R/W

Reserved

5:0

GANGED_OCS_
SIGNAL

R/W

Only the following configurations are valid settings:
0 = TRST
1 = OCS1
3 = OCS2
4 = SPI_CLK
5 = SPI_DO
6 = OCS3
7 = OCS4
8 = PRTCTL1
9 = PRTCTL2
15 = SM_CLK

5.6.28USB UPSTREAM BOOST REGISTERTABLE 5-45:

Description

USB UPSTREAM BOOST REGISTER

HS_UP_BOOST(0X60CA)Bit

Name

USB Upstream Boost Register
R/W

Description

7:3

Reserved

R/W

Reserved

2:0

HS_BOOSTR/W

HS Output Current.
3’b000: Nominal
3’b001: Decrease by 5%
3’b010: Increase by 10%
3’b011: Increase by 5%
3’b100: Increase by 20%
3’b101: Increase by 15%
3’b110: Increase by 30%
3’b111: Increase by 25%

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USB5532B
5.6.29USB UPSTREAM VARISENSE REGISTERTABLE 5-46:

USB UPSTREAM VARISENSE REGISTERPHY_UP_SENSE(0X60CC)
Bit

Name

USB Upstream Varisense Register
R/W

Description

7:3

Reserved

R

Reserved

2:0

HS_SQ_TUNE[2:0]

R/W

Squelch Tune
3’b000: Nominal 100mV Trip Point
3’b001: Decrease by 12.5mV
3’b010: Decrease by 25mV
3’b011: Decrease by 37.5mV
3’b100: Decrease by 50mV
3’b101: Decrease by 62.5mV
3’b110: Increase by 25mV
3’b111: Increase by 12.5mV

5.6.30USB3 UPSTREAM LINK STATE REGISTERTABLE 5-47:

USB3 UPSTREAM LINK STATE REGISTER

SS_UP_STATE(0X61C0)

USB3 Upstream Link State

Bit

Name

7:4

LINK_STATE

R

Refer to Table 5-54, "USB 3.0 Link States" for more details.

3

Reserved

R

Reserved

2:0

LINK_SUB_STATE

R

Refer to Table 5-54, "USB 3.0 Link States" for more details.

5.6.31

USB PORT 1 BOOST REGISTERTABLE 5-48:

R/W

Description

USB PORT 1 BOOST REGISTER

HS_P1_BOOST(0X64CA)Bit

Name

USB Port 1 Boost Register
R/W

Description

7:3

Reserved

R/W

Reserved

2:0

HS_BOOSTR/W

HS Output Current.
3’b000: Nominal
3’b001: Decrease by 5%
3’b010: Increase by 10%
3’b011: Increase by 5%
3’b100: Increase by 20%
3’b101: Increase by 15%
3’b110: Increase by 30%
3’b111: Increase by 25%

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USB5532B
5.6.32

USB PORT 1 VARISENSE REGISTERTABLE 5-49:

USB PORT 1 VARISENSE REGISTER

PHY_P1_SENSE(0X64CC)Bit

Name

USB Port 1 Varisense Register
R/W

Description

7:3

Reserved

R

Reserved

2:0

HS_SQ_TUNE[2:0]

R/W

Squelch Tune
3’b000: Nominal 100mV Trip Point
3’b001: Decrease by 12.5mV
3’b010: Decrease by 25mV
3’b011: Decrease by 37.5mV
3’b100: Decrease by 50mV
3’b101: Decrease by 62.5mV
3’b110: Increase by 25mV
3’b111: Increase by 12.5mV

5.6.33

USB3 PORT 1 LINK STATETABLE 5-50:

USB3 PORT 1 LINK STATE

SS_P1_STATE(0X65C0)

USB3 Port1 Link State

Bit

Name

7:4

LINK_STATE

R

Refer to Table 5-54, "USB 3.0 Link States" for more details.

3

Reserved

R

Reserved

2:0

LINK_SUB_STATE

R

Refer to Table 5-54, "USB 3.0 Link States" for more details.

5.6.34

USB PORT 2 BOOST REGISTERTABLE 5-51:

R/W

Description

USB PORT 2 BOOST REGISTER

HS_P2_BOOST(0X68CA)Bit

Name

USB Port 2 Boost Register
R/W

Description

7:3

Reserved

R/W

Reserved

2:0

HS_BOOSTR/W

HS Output Current.
3’b000: Nominal
3’b001: Decrease by 5%
3’b010: Increase by 10%
3’b011: Increase by 5%
3’b100: Increase by 20%
3’b101: Increase by 15%
3’b110: Increase by 30%
3’b111: Increase by 25%

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DS00001679C-page 50

USB5532B
5.6.35

USB PORT 2 VARISENSE REGISTERTABLE 5-52:

USB PORT 2 VARISENSE REGISTER

PHY_P2_SENSE(0X68CC)Bit

Name

USB Port 2 Varisense Register
R/W

Description

7:3

Reserved

R

Reserved

2:0

HS_SQ_TUNE[2:0]

R/W

Squelch Tune
3’b000: Nominal 100mV Trip Point
3’b001: Decrease by 12.5mV
3’b010: Decrease by 25mV
3’b011: Decrease by 37.5mV
3’b100: Decrease by 50mV
3’b101: Decrease by 62.5mV
3’b110: Increase by 25mV
3’b111: Increase by 12.5mV

5.6.36

USB3 PORT 2 LINK STATETABLE 5-53:

USB3 PORT 2 LINK STATE

SS_P2_STATE(0X69C0)

USB3 Port 2 Link State

Bit

Name

7:4

LINK_STATE

R

Refer to Table 5-54, "USB 3.0 Link States" for more details.

3

Reserved

R

Reserved

2:0

LINK_SUB_STATE

R

Refer to Table 5-54, "USB 3.0 Link States" for more details.

TABLE 5-54:

R/W

Description

USB 3.0 LINK STATESNUM

Link State

00h

U0

01h

U1

02h

U2

03h

U3

04h

SIS.Disabled

05h

RX.Detect

06h

SS.Inactive

07h

Polling

08h

Recovery09h

Hot Reset

0Ah

Compliance

0Bh

Loopback

DS00001679C-page 51

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USB5532B
6.0

DC PARAMETERS

6.1

Maximum Ratings
Parameter

Storage Temperature

Symbol
TA

MIN
-55

MAX

Units

150

Comments°C

Lead Temperature°C

1.25 V supply voltage

VDD12

-0.5

1.6

V

3.3 V supply voltage

VDD33

-0.5

4.0

V

Voltage on USB+ andUSB- pins-0.5(3.3 V supply
voltage + 2) 6

V

Voltage on any signal
powered by VDD33
rail

-0.5

VDD33 + 0.3

VVoltage on any signal
pin powered by the
VDD12

-0.5

VDD12 + 0.3

V

HBM ESD
Performance2

kV

Power Consumption

1.4W

Refer to JEDEC Specification J-STD020D.

Note 1: Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only. Therefore, functional operation of the device at any condition above those indicated in the operation
sections of this specification are not implied.
2: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line
may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.

6.2

Operating Conditions
Parameter

Symbol

MIN

USB5532B Operating
Temperature

TA

Die Temperature

TJ

1.25 V supply voltage

VDD12

1.22

3.3 V supply voltage

VDD33

0

MAX

Units

70

°C

115

°C

1.31

V

Comments

3.0

3.6

V

1.25 V supply rise time tRT
3.3 V supply rise time tRT

0

400

s

0

400

s

(Table 6-1)

Voltage on
USB+ and USB- pins

-0.3

5.5

V

If any 3.3 V supply voltage drops
below 3.0 V, then the MAX
becomes:

Voltage on any signal
powered by VDD33 rail

-0.3

VDD33

V

(Table 6-1)

(3.3 V supply voltage) + 0.5  5.5

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DS00001679C-page 63

USB5532B
TABLE 6-1:

SUPPLY RISE TIME MODEL

Voltage

tRTxx

VDD33

3.3 V

100%

90%
1.25 V
VDD12

100%

90%
VSS

10%

t90%

t10%

6.3

Time

Power Consumption

This section details the power consumption of the device as measured during various modes of operation. All typicalmeasurements were taken with power supplies at nominal values (VDD12 = 1.25 V, VDD33 = 3.3 V).
TypicalSupply Current (mA)
VDD33

Typical Power (mW)

VDD12

Reset

0.2

5.0

6.9

No VBUS

5.6

25.0

49.7

Global Suspend (Note 6-1)

1.1

8.3

14.0

2 FS Ports

23

70

162

2 HS Ports

43

75

236

2 SS Ports

17

813

1072

2 SS/HS Ports

50

873

1256

Note 6-1

The Global Suspend typical supply current and power are stated for device version -6080. Version 5000 has a typical supply current of 9 mA for VDD33, 29 mA for VDD12, and 66 mW of total power
consumption.

DS00001679C-page 64

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USB5532B
6.4

DC Electrical Characteristics

TABLE 6-2:

DC ELECTRICAL CHARACTERISTICS
Parameter

Symbol

MIN

TYP

MAX

Units

0.8

V

Comments

IS Type Input Buffer
Low Input Level

VILIHigh Input Level

VIHI

Hysteresis (IS only)

VHYSI

2.0

TTL Levels

V
420

mV

I, IPU, IPD Type Input Buffer
Low Input Level

VILI

0.8
2.0

V

TTL Levels

High Input Level

VIHI

Pull Down

PD

72

A

V
VIN = 0

Pull Up

PU

58

A

VIN = VDD33ICLK Input Buffer
Low Input Level

VILCKHigh Input Level

VIHCK

0.8

0.3

V

Input Leakage

IIL

-10

+10

A

VIN = 0 to VDD33

Low Input Leakage

IIL

-10

+10

A

VIN = 0High Input Leakage

IIH

-10

+10

A

VIN = VDD33

0.4

V

IOL = 12 mA @VDD33 = 3.3 V

V

IOH = -12 mA @VDD33 = 3.3 V

+10

A

VIN = 0 to VDD33(Note 6-2)

0.4

V

IOL = 12 mA @VDD33 = 3.3 V

V

IOH = -12 mA @VDD33 = 3.3 V

A

VIN = 0 to VDD33(Note 6-2)

V

Input Leakage(All I and IS buffers)

O12 Type Buffer
Low Output Level

VOL

High Output Level

VOH

VDD33
-0.4

Output Leakage

IOL

-10

I/O12, I/O12PU & I/O12PD
Type Buffer
Low Output Level

VOL

High Output Level

VOH

VDD33
-0.4

Output Leakage

IOL

-10

+10

Pull Down

PD

72

A

Pull Up

PU

58

A

IO-U
(Note 6-3)
Note 6-2

Output leakage is measured with the current pins in high impedance.

Note 6-3

See USB 2.0 Specification 1. for USB DC electrical characteristics.

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DS00001679C-page 65

USB5532B
6.5

Capacitance

TABLE 6-3:

PIN CAPACITANCE
LimitsParameter

SymbolClock Input Capacitance

MAX

Unit

CXTAL

2

pF

Input Capacitance

CIN

5

pF

Output Capacitance

COUT

10

pF

Note 6-4

6.5.1

MIN

TYP

Test Condition
All pins except USB pins and the pins
under the test tied to AC ground

Capacitance TA = 25°C; fc = 1 MHz; VDD33 = 3.3 V

PACKAGE THERMAL SPECIFICATIONS

Thermal parameters are measured or estimated for devices with the exposed pad soldered to thermal vias in a multilayer 2S2P PCB per JESD51. Thermal resistance is measured from the die to the ambient air. The values provided are
based on the package body, die size, maximum power consumption, 70°C ambient temperature, and 125°C junction
temperature of the die.
Symbol

JA
JT
JC

USB5532B(°C/W)VELOCITY(Meter/s)

23.0

0

0.1

0

1.4

0

Use the following formulas to calculate the junction temperature:

TJ = P x JA + TA
TJ = P x JT + TT
TJ = P x JC + TC

SymbolDescription

TJ

Junction temperatureP

Power dissipatedJA

Junction-to-ambient-temperature

JC

Junction-to-top-of-package

JTJunction-to-bottom-of-caseTA

Ambient temperatureTC

Temperature of the bottom of the caseTT

Temperature of the top of the case

DS00001679C-page 66

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USB5532B
7.0

AC SPECIFICATIONS

7.1

Oscillator/Crystal

Crystal: Parallel resonant, fundamental mode, 25 MHz 30 ppm
External Clock: 50% duty cycle  10%, 25 MHz  30 ppm, jitter < 100 ps rms

FIGURE 7-1:

TYPICAL CRYSTAL CIRCUIT

XTAL1(CS1 = CB1 + CXTAL1 )C1Crystal
C0

CL

C2
XTAL2
(CS2 = CB2 + CXTAL2 )TABLE 7-1:

CRYSTAL CIRCUIT LEGEND

SymbolDescription

In Accordance With

C0

Crystal shunt capacitanceCL

Crystal load capacitanceCB

Total board or trace capacitanceOEM board design

CS

Stray capacitanceMicrochip IC and OEM board designCXTALXTAL pin input capacitanceMicrochip IC

C1

Load capacitors installed on OEM
board

Calculated values based on Figure 7-2 (Note 7-2)

C2

FIGURE 7-2:

Crystal manufacturer’s specification (Note 7-1)

FORMULA TO FIND THE VALUE OF C1 AND C2

C1 = 2 x (CL – C0) – CS1
C2 = 2 x (CL – C0) – CS2
Note 7-1

C0 is usually included (subtracted by the crystal manufacturer) in the specification for CL and should
be set to 0 for use in the calculation of the capacitance formulas in Figure 7-2. However, the PCB
itself may present a parasitic capacitance between XTALIN and XTALOUT. For an accurate
calculation of C1 and C2, take the parasitic capacitance between traces XTALIN and XTALOUT into
account.

Note 7-2

Consult crystal manufacturer documentation for recommended capacitance values.

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DS00001679C-page 67

USB5532B
7.2

External Clock

50% duty cycle  10%, 25 MHz  30 ppm, jitter < 100 ps rms.
Note:

The external clock is based upon 1.2 V CMOS Logic. XTALOUT should be treated as a no connect whenan external clock is supplied.

7.2.1

SMBUS CLOCK

The maximum frequency allowed on the SMBus clock line is 100 kHz.

7.2.2

USB 2.0

bit The Microchip hub conforms to all voltage, power, and timing characteristics and specifications as set forth in theUSB 2.0 Specification 1.

7.3

SPI Timing

FIGURE 7-3:

SPI TIMINGTCEH

SPI_CENTFC

SPI_CLK
TDH

TCLQ
Input Data
Valid

SPI_DI
TOS

TOH

TOV

Output Data
Valid

SPI_DOTABLE 7-2:

SPI TIMING OPERATION

Name

Parameter

TOH
Output Data
Valid

MIN

MAX

Unit

TFC

Clock Frequency

TCEH

Chip Enable High Time

TCLQ

Clock to Input Data

TDH

Input Data Hold Time

0

ns

TOS

Output Set up Time

5

ns

TOH

Output Hold Time

5

ns

TOV

Clock to Output Valid4

ns

DS00001679C-page 68

60

MHz

9

ns

50

ns

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USB5532B
7.4

SMBus Timing

The SMBus slave interface complies with the SMBus Specification Revision 1.0. See Section 2.1, AC Specifications on
page 3 for more information.

FIGURE 7-4:

SMBUS SLAVE TIMING DIAGRAM

SM_DATA

tBUF

tLOW

tR

tHD;STAtHD;DATtF

tHD;STA

SM_CLKTABLE 7-3:

tHIGH

tSU;DATtSU;STAtSU;STOSMBUS SLAVE TIMING MODES

SymbolParameter

MIN

MAX

Unit

fSCL

SM_CLK clock frequency

0

100

KHz

tHD;STA

Hold time START condition

4

-

s

tLOW

LOW period of the SM_CLK clock

4.7

-

s

tHIGH

HIGH period of the SM_CLK clock

4

-

s

tSU;STA

Set-up time for a repeated START condition

4.7

-

s

tHD;DATDATA hold time\

0

-

ns

tSU;DATDATA set-up time

250

-

ns

tR

Rise time of both SM_DATA and SM_CLK signals

-

1000

ns

tF

Fall time of both SM_CLK and SM_DATA lines

-

300

ns

tSU;STO

Set-up time for a STOP condition

4

-

s

tBUF

Bus free time between a STOP and START
condition

4.7

-

s

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 69

USB5532B
8.0

PACKAGE DRAWING
USB5532B 64-PIN QFN PACKAGE OUTLINE

Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging

FIGURE 8-1:

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 70

USB5532B

DS00001679C-page 71

http://www.microchip.com/packaging

USB5532B 64-PIN QFN PACKAGE OUTLINE (CONTINUED)

Note: For the most current package drawings,
see the Microchip Packaging Specification at

FIGURE 8-1:

 2012 - 2015 Microchip Technology Inc.

USB5532B
APPENDIX A:TABLE A-1:

DATA SHEET REVISION HISTORYDATA SHEET REVISION HISTORY

Revision Level & Date

Section/Figure/Entry

Correction

DS00001679C (10-12-15)"Product Identification
System"Ordering information corrected.

DS00001679B (09-26-14)

Document is converted to Microchip template
Overview on page 4“USB 2.0” added following mention of MultiTRAKTechnology, PortSwap and PHYBoost.

Cover

References to “8K RAM” changed to “8 KB RAM”
and references to “32 K ROM” changed to “32 KB
ROM”.
Second paragraph in General Description modified.

Section 3.2, "Pin Descriptions Corrected PRT_PWRx/PRT_CTLx pin description to(Grouped by Function)," on
include cross-reference note.
page 8FIGURE 3-1: USB5532B 64Pin QFN on page 7

Updated PRT_PWRx/PRT_CTLx pin names toinclude both primary and secondary functions.

Section 3.2, "Pin Descriptions Provided additional VBUS pin description(Grouped by Function)," on
information for clarity.
page 8
Section 4.2, "SMBus Slave
Interface," on page 18

REV A (02-27-14)

In second paragraph, updated sentence “To disable
the SMBus, a pull-down resistor of 10 10 K must
be applied to SM_DAT.” to:“To disable the SMBus, a pull-down resistor of
10 K must be applied to either SM_DAT,
SM_CLK, or both SM_DAT and SM_CLK if
desired.”Replaces previous SMSC version 1.3; document has been Microchip branded
General Description on cover: “legacy” is replaced with “non-USB 1.2”

Rev. 1.3(01-23-14)

All

Added -6080 firmware ordering code and info
throughout document.

Introduction on page 4

Added information on the -5000 vs. -6080 firmware
differences.

Section 6.5.1, "Package
Thermal Specifications," onpage 66

Added package thermal specifications.

Functional Operation on page Renamed chapter. Updated entire chapter with24
additional information on battery charging,
configuration options, OTP, and external SPI
operation, runtime register definitions, etc.
Standard Interface
Connections on page 13

Renamed chapter. Added Non-BC Power
Configuration and Battery Charging sections.

Pin Information on page 7

Added alternate functions to TRST pin.

Section 6.3, "Power
Consumption," on page 64

Updated power consumption values.

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 72

USB5532B
TABLE A-1:

DATA SHEET REVISION HISTORY (CONTINUED)

Revision Level & Date
Rev. 1.2(05-31-13)

Section/Figure/Entry

Correction

All

Removed industrial temp. SKU information fromdocument.

Section 6.1, "Maximum
Ratings," on page 63

Added maximum power consumption row/data totable.

Section 6.2, "Operating
Conditions," on page 63

Added maximum die temperature row/data to table.

Section 6.3, "Power
Consumption," on page 64

Added power consumption numbers

Note 3-1 on page 11 andNote 3-3 on page 11

Updated note to reflect configuration straps areenabled by default.

Pin Information on page 7

Updated TRST pin description with the following
note: “If using the SMBus interface, a pull-up on thissignal will enable Legacy Mode, while leaving it
unconnected or pulled-down will enable Advanced
Mode.”

Package Drawing on page 70 Updated recommended land pattern drawings andinformation.
Rev. 1.1(03-05-13)

Ordering Codes

Updated ordering codes to for A2 material

Ordering Codes

Corrected tape and reel quantity from 3000 to 2500.

Section 3.2, "Pin Descriptions Added Note 3-1 and Note 3-3 explaining the(Grouped by Function)," onconfiguration strap functions on the PRT_PWRxpage 8and OCSx pins.

Rev. 1.0(09-06-12)DS00001679C-page 73

Section 4.1.2, "Operation of
the Dual Hi-Speed Read
Sequence," on page 14

Updated first sentence to state that dual data modeis supported only at an SPI speed of 30 MHz

Standard Interface
Connections on page 13

Clarified interface ordering explanation.

Section 4.2, "SMBus Slave
Interface," on page 18

Removed “either an external I2C (if present) and”
from last sentence of section.

Section 4.2, "SMBus Slave
Interface," on page 18

Added additional sentence: “For operation in
SMBus Legacy Mode, an additional pull-up resistor
is required on TRST.”

Section 5.5, "SMBus Slave
Interface," on page 29,
FIGURE 5-6: SMBus
Commands on page 30,
FIGURE 5-5: Block Read on
page 30

Updated “register address” references to “SMBus
RAM buffer offset”.

SPI_DO pin description &Added note to describe the SPI_SPD_SEL
configuration strap function on the SPI_DO.

All

Removed references to GPIOs and LEDs

All

Initial revision.

 2012 - 2015 Microchip Technology Inc.

USB5532B
APPENDIX B:

ACRONYMS

I2C:Inter-Integrated Circuit1

OCS:

Over-Current Sense

PCB:

Printed Circuit Board

PHY:

Physical Layer

PLL:

Phase-Locked Loop

QFN:

Quad Flat No Leads

RoHS:

Restriction of Hazardous Substances Directive

SCL:

Serial Clock

SIE:

Serial Interface Engine

SMBus:

System Management Bus

TT:

Transaction Translator

1.

I2C is a registered trademark of Philips Corporation.

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 74

USB5532B
APPENDIX C:
1.
2.
3.
4.
5.
6.
7.

REFERENCES

Universal Serial Bus Specification, Version 2.0, April 27, 2000 (12/7/2000 and 5/28/2002 Errata)
USB Implementers Forum, Inc. http://www.usb.org
Universal Serial Bus Specification, Version 3.0, November 13, 2008
USB Implementers Forum, Inc. http://www.usb.org
System Management Bus Specification, version 1.0
SMBus. http://smbus.org/specs/
MicroChip 24AA02/24LC02B (Revision C)
Microchip Technology Inc. http://www.microchip.com/

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 75

USB5532B
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to makefiles and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family ordevelopment tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.

CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 76

USB5532B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

[X]

DeviceTemperature
Range

XXX

-

-

Package[X](1)Tape and Reel
OptionDevice:USB5532B

Temperature
Range:

Blank

Package:

5000JZX = 64-pin QFN 9 x 9mm 6.0mm exposed pad
USB 3.0 2-Port Hub with VSM & Apple/BC 1.2 Charging=

0C to+70C

Examples:a)

USB5532B-5000JZXb)

USB5532B-6080JZX

Commercial

6080JZX = 64-pin QFN 9 x 9mm 6.0mm exposed pad
USB 3.0 2-Port Hub with VSM & Apple/BC 1.2 Charging
Note 1:
Tape and Reel
Option:Blank
TR= Standard packaging (tray)= Tape and Reel(1) 2012 - 2015 Microchip Technology Inc.

Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Reel size is 4,000.

DS00001679C-page 77

USB5532B
Note the following details of the code protection feature on Microchip devices:•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

•

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may besuperseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and holdharmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly orotherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck,
MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and
UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL
ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., inother countries.
All other trademarks mentioned herein are property of their respective companies.
© 2012 - 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781632778659

QUALITY MANAGEMENT SYSTEMCERTIFIED BY DNV== ISO/TS 16949 == 2012 - 2015 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and proceduresare for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS00001679C-page 78

Worldwide Sales and Service
AMERICAS

ASIA/PACIFIC

ASIA/PACIFICEUROPE

Corporate Office2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
supportWeb Address:www.microchip.com

Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
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China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130

Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393

China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049

Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829

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Tel: 91-80-3090-4444
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Fax: 86-29-8833-7256

Canada - Toronto
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Fax: 905-673-6509

Germany - KarlsruheTel: 49-721-625370
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Tel: 49-89-627-144-0
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Italy - Milan
Tel: 39-0331-742611
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07/14/15

 2012 - 2015 Microchip Technology Inc.

DS00001679C-page 79