Engineer-to-Engineer NoteaEE-276

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Video Framework Considerations for Image Processing on Blackfin®
Processors
Contributed by Kunal Singh and Ramesh Babu

Introduction
In any system, memory partitioning and data
flow management are crucial elements for a
successful multimedia framework design.
Blackfin® processors have a hierarchal memoryand non-intrusive DMA with the Parallel
Peripheral Port interface. When used in yourapplication, they can provide very high systemefficiency.
This EE-Note discusses the following topics thatshould be considered for obtaining maximum
performance on ADSP-BF533 and ADSP-BF561
Blackfin family processors in video processing
applications:

Memory considerationsInternal memory space

SDRAM memory spaceManaging external data accesses

Rev 1 – September 8, 2005

buffers associated with video applications. The
Blackfin processor's memory has a unified
address range, which includes the internal L1memory, (in case of the ADSP-BF561 processor
also L2 memory) SDRAM memory, andasynchronous memory spaces.
Internal Memory Space

The L1 memory operates at core clock frequency
and hence, has lowest latency compared to theother memory spaces. Blackfin processors haveseparate Data and Instruction L1 memory.
Buffer 0---------------CoreFetch

Buffer 1
Buffer 2DMAAccess---------------Coefficients

DMA modes for PPI capture and display


Working with ITU-R-656 input modes

Outputting ITU-R-656 video frames

DMA prioritization and traffic control
registerFigure 1. Un-Optimized L1 Memory Allocation

Memory Considerations
The Blackfin processor architecture supports ahierarchical memory that allows the programmer
to access faster, smaller memories for code thatruns the most often and larger memory for data

The L1 data SRAM is constructed from singleported subsections, each subsection consisting of
4 Kbytes of memory. This organization results in
multi-ported behavior when there are
simultaneous access to different sub-banks or

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aaccessing one even and one odd 32-bit word
within the same 4K sub-bank.

minimized. The SDC can keep track of one row
per bank (with up to four internal SDRAMbanks) at a time, hence it can switch between
four internal SDRAM banks without any stalls.

Buffer 0
CodeCoreFetch

Video Frame 0
Buffer 1
DMAAccessVideo Frame 1

Instruction
DMA

Buffer 2

External

Ref Frame

BusDMA

UnusedCoefficients
CoreFetch

UnusedFigure 2. Optimized L1 Memory Allocation

Figure 1 shows the un-optimized allocation ofmemory for different buffers. Each block in thefigure represents a 4 Kbyte sub-bank in internal
data memory. Here the internal data buses are notused effectively, since the processor cannot fetch
the two data words simultaneously.
Figure 2 shows the optimized memory allocation
across internal 4 Kbyte data memory banks. Thismemory allocation allows simultaneous dual
DAG and a DMA access, and hence, maximum
throughput over data buses.
In video encoding and decoding applications,
optimized memory allocation reduces the latency
involved in accessing L1 data memory due tosimultaneous access from core and DMA
controller
SDRAM Memory SpaceThe SDRAM Controller (SDC) enables theprocessor to transfer data to and fromSynchronous DRAM (SDRAM). The SDRAM
controller supports a connection to four internalbanks within the SDRAM. In end applications,by mapping the data buffers appropriately indifferent internal sub-banks, the latency involvedin accessing data by core/DMA can be

Figure 3. Un-Optimized SDRAM Memory Allocation

In image processing applications, the video
frame is bought into the memory using a PPIDMA. Because of the image size (i.e., VGA, D-1
NTSC, D-1 PAL, 4CIF, 16CIF, etc.), each frameof the image must be captured in SDRAM
memory using a PPI DMA channel. The
algorithm can read the pixels block by blockfrom SDRAM and process each block as it isbrought in. The PPI captures the next frame intoanother buffer while core is processing theprevious buffer. Since both core and DMAs areaccessing the SDRAM memory simultaneously,
it is necessary to map the code, video frame, andother buffers appropriately to minimize thelatency involved in accessing SDRAM memory.
Figure 3 shows the un-optimized memory
allocation in SDRAM internal sub-banks. In
Figure 3, both the code and video frame buffer
are mapped to SDRAM internal Bank 0. This
allocation method causes more latency because
SDRAM row activation cycles occur at almost
every cycle. This is due to alternating coreaccesses (fetching the instructions) and DMA
accesses to different pages within the same

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aSDRAM internal bank. The latency may cause a
PPI FIFO overflow error (in the case of image
capture) or underflow (in the case of image
display). In order to increase throughput ofexternal memory accesses, it is necessary toallocate video/reference buffers such that only
one DMA accesses an SDRAM bank at anygiven time.

CodeInstruction
DMA

Video Frame 0ExternalBusDMA

Video Frame 1

Ref Frame

Figure 4. Optimized SDRAM Memory Allocation

Figure 4 shows the optimized memory allocation
within SDRAM internal banks. In this memory
allocation example, at any time, either the core or
the DMA controller is accessing the particularinternal bank of SDRAM memory. Hence, thelatency is minimized, since row activation cycles
are spread across hundreds of SDRAM accesses.

DMA Modes for PPI Capture andDisplay
The Blackfin DMA controller can transfer data
between its memory space and peripherals
efficiently. The designer can choose appropriate
DMA modes (for example: stop mode, autobuffer, or descriptor-based DMA) to transfer thedata. Also, the programmer can choose the DMA
priority for a particular peripheral by using
appropriate DMA channel.
The Blackfin processor's PPI port supports theindustry-standard ITU-R-656 mode and generalpurpose I/O mode with various internal andexternal frame sync options. Images can beseamlessly captured or displayed using the PPI
along with the appropriate DMA mode. The
programmer has to choose the appropriate DMA
mode such that images can be processed in realtime without loosing a frame.
In image encoding applications, the PPI can be
programmed in descriptor chaining mode tocapture images in two or more buffers. The corecan process one buffer while DMA is filling theother buffer. You must ensure that the core andthe DMA controller do not access the same
SDRAM bank, as discussed in SDRAM Memory
Space section.
CoreAccess

DMAAccessVideo Frame 0
Video Frame 1
Ref Frame

Managing External Data Accesses

Accessing the external memory is performed
more efficiently when the transfer is made in thesame direction. While accessing the SDRAM
memory, performing group transfers in a singledirection (avoiding frequent direction turnarounds) can reduce the latency involved in thedata transfer. Frequent turnarounds on the DMA
controller can increase the latency due to a write
followed by a read access.

CodeCoreAccess

CodeDMAAccessVideo Frame 0
Video Frame 1
Ref Frame

Figure 5. PPI DMA and Core Accesses Without Any
Conflict in Accessing SDRAM Internal Sub-banks

In image encoding and decoding applications, thenumber of million cycles per cycles (MIPS)

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aconsumed by the processor is not constant. TheMIPS consumed varies from the compression
ratio, captured image, and so on. In image
decoding applications, if the decoded frame to be
displayed is not yet ready, the PPI can transmit
the recently decoded frame again. In order toachieve this functionality, the PPI can be
programmed in stop mode DMA. This mode has
more control over the data that needs to display
as output.
In stop mode DMA, an interrupt is generated
after each work unit and the DMA channel is in apaused state.

In order to minimize processor overhead to deinterlace the frame, the PPI can capture the video
frame by skipping one line after each active line
(as depicted in Figure 7). Then memory DMA
can de-interlace the Field 2 into the Field 1 byfilling the blank lines.

Field 1

PPI capturesby skipping
one line

Hence, if the next frame to be displayed is not
yet ready, the same frame can be re-transmitted.
This can be achieved inside the PPI DMAinterrupt subroutine.

Field 2

Active Video LineWorking with ITU-R-656 Input Modes

The PPI supports three input modes for ITU-R656-framed data.
Entire field modeActive field onlyVertical blanking only

Skipped Line

Figure 7. 2-D DMA Capture Alternating Lines

Field 1

In video encoding applications, the video frame
can be captured in active field only mode, so that
only Field 1 and Field 2 are captured. Since theITU-R-656 has interlaced video format, video
algorithms may require the video data to be inde-interlaced format. Using Memory DMA, theprogrammer can de-interlace the video frame.

Field 2

Active Video Line
Skipped Line

Figure 8. De-Interlacing Using Memory DMA

Figure 6. Typical ITU-R-656 Video Frame Partitioning

Figure 8 illustrates de-interlacing using memory
DMA. The data in Field 2 must be de-interlacedwith data in Field 1. Hence, the skipped line is
replaced with the data in Field 2. Here, theMDMA source address should contain theaddress of the first line of Field 2, and theMDMA destination address should contain theVideo Framework Considerations for Image Processing on Blackfin® Processors (EE-276)

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afirst skipped line. Both the source and destination
MDMAx_Y_MODIFY should be configured for countto skip one line.
Outputting ITU-R-656 Video Frames

The PPI does not explicitly provide functionality
for framing an ITU-R-656 output stream withproper preambles and blanking intervals.
However, this is achieved by first creating acomplete frame in the memory and thentransmitting the same via the PPI in zero frame
sync mode. The video data, blanking data, andcontrol code can be set up in memory prior tosending out the video stream. The horizontal andvertical blanking information can be set up inmemory (one time) and then only the active
fields can be updated on a frame-by-frame basis.

highest priority. Programmers can assign aparticular DMA channel to a peripheral andhence can change the priority of peripheral
DMA.
By default, the PPI uses higher priority channels,
compared to other peripherals. If an application
has more than one DMA running in parallel, theperipherals with high data rates or low latency
requirements can be assigned to lower numbered(higherpriority)
channelsviatheDMA_PERIPHERAL_MAP registers.
Using DMA Traffic Control registers, theprogrammer can influence the direction of data
movement in internal DMA buses (DAB, DCB,and DEB). Traffic control provides a way toinfluence how often the transfer direction on thedata buses may change, by automaticallygrouping same-direction transfers together.
The DAB, DCB, and DEB buses provide ameans for DMA-capable peripherals to gain
access to on-chip and off-chip memory with little
or no degradation in core bandwidth to memory.
The DMA controller uses the DAB bus to accessthe DMA-capable peripherals. The DCB bus isused to access internal memory. Similarly, theDEB bus used to access external memory
through the EBIU.

One-time initialization of horizontal,vertical, and control codes inmemory
Active field data updated for eachframe
Figure 9. Blanking and Active Video in Memory

DMA Prioritization and Traffic
Control Registers
In Blackfin processors, all peripherals are DMA
capable. By default, each peripheral is linked to aparticular DMA channel. Each DMA channel has
its own priority to access the memory. DMAchannels with the lowest number have theFigure 10. DMA Traffic Control Register

By using the traffic control register, theprogrammer can influence the direction of eachVideo Framework Considerations for Image Processing on Blackfin® Processors (EE-276)

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aDMA bus independently, by grouping same
direction transfers together.
Figure 10 shows the fields in the DMA_TC_PER
register. For example, consider an application inwhich both the Memory DMA and PPI DMA are
active and a traffic control register is used. If
both the PPI DMA and Memory DMA request
the DEB bus (with memory DMA going “withthe traffic” and the PPI DMA going “against thetraffic”), the memory DMA is granted the DEBbus even though PPI DMA has higher priority.
Since the PPI DMA is “against the traffic” of theDEB bus, the effective priority of the PPI DMA
is increased by 16, and hence, the memory DMA
is granted access to the DEB bus. The PPI DMA
gets access to the DEB bus when the traffic
control counter times out (or until traffic stops orchanges direction on its own).
For more information DMA Traffic Control
registers, refer the ADSP-BF533 and ADSPBF561 Hardware Reference manuals.
Bus Arbitration

The DMA bus has higher priority over the corebus while accessing internal L1 memory. Bydefault, when accessing external memory, thecore has higher priority over the DMA bus. By
setting the CDPRIO bit in the EBIU_AMGCTL

register, all DEB transactions to the external bus
have priority over core accesses to externalmemory. Programmers can use this bit,depending on their application requirement.
DMA and Cache Coherency

In an application, if both core and DMA accessthe shared buffer and cache is enabled, thesoftware should provide cache coherency support
by invalidating the data in the shared buffer. InBlackfin processors, the cache can be invalidated
using memory-mapped registers. Also, theVisualDSP++® 4.0 development tools provide
C-callable library functions to invalidate theindividual cache banks. Software can invalidate
the cache each time before accessing the shared“volatile” buffer.

Conclusion
By considering the various factors discussed inthis EE-Note, you can obtain maximum
performance from Blackfin processors in image
processing applications.

References[1] ADSP-BF533 Blackfin Processor Hardware Reference. Revision 3.1 May 2005. Analog Devices, Inc.
[2] ADSP-BF561 Blackfin Processor Hardware Reference. Revision 1.0, July 2005. Analog Devices, Inc.

Document History
Revision

Description

Rev 1 – September 08, 2005
by Kunal Singh

Initial Release

Video Framework Considerations for Image Processing on Blackfin® Processors (EE-276)

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