MLX80104/5
LIN Slave Controller for Switches

IO4

IO6

SW6

SW7

VS

SW8

27

26

25

24

23

22

GNDA

1

21

AWD

IREF

2

20

SW9

SW5

3

19

IO7

SW4

4

18

IO0

SW3

5

17

GNDD

TO

6

16

GNDL

TI1

7

15

LIN

11

12

13

14

SW1

SW0

IO1

LIN Transceiver according to LIN 2.x and SAE J2602

SW2

TI0

8

o Baud rate up to 19.2 kBaud
o Frame processingo Low interrupt load to the application

9

LIN Protocol Controller according to LIN 2.x and SAE J2602

MLX80104/5
QFN 5x5 28

10Byte EEPROM with ECC

IO2o Internal 12 MHz RC-Oscillatoro 16-bit MULAN MCU with 16kB ROM or OTP, 512 Byte RAM, 192

IO5

Application Controller

IO3

Features28

Datasheeto Slew rate control for best EME behaviouro High EMI immunity

IO Configuration
o
o
o
o
o
o
o
o
o
o

18 fully configurable high current/high voltage inputs/outputs (7mA/26.5V)
Ground shift tolerant I/Os
All IOs configurable pull up or pull down characteristics
Eight PWM outputs (8-bit, 80Hz to 30kHz)
Ten 10-bit ADC channels
Eight Interrupt capable Inputs
Configurable Wake up sources (LIN, IOs, ADC)
Constant current output (2mA) for external low voltage loads via bipolar transistor
IOs fully diagnosable
Integrated window watchdog and additional independent analogue watchdog

Voltage Regulatoro Low standby current consumption of typ 25µA in sleep modeo Over-temperature shutdown, 45V load dump protected

Other Featureso Automotive Temperature Range of –40°C to 125°C
o Small MLF 5x5 28pin packageo Ready-to-use firmware available (UniROM)

Order Code

Temp. Range Package

DeliveryRemark

MLX80104 KLQ-DAG-000-RE
MLX80104 KLW-DAG-000-RE
MLX80105 KLQ-EAA-000-RE
MLX80105 KLW-EAA-000-RE-40 - 125 °C-40 - 125 °C-40 - 125 °C-40 - 125 °C

Reel
Reel
Reel
Reel

ROM, See 22 Marking
ROM, See 22 Marking
OTP, See 22 Marking
OTP, See 22 Marking

QFN 5x5
QFN 5x5 WF
QFN 5x5
QFN 5x5 WF

Short Description
This IC is a fully integrated LIN Slave for matrix switch or single switch Applications in automotive environment. It is
suitable for bus systems according to LIN 2.x as well as SAE J2602.
The combination of physical layer LIN transceiver and LIN protocol controller along with easy to configure switch
inputs and PWM outputs make it possible to develop in a short timeframe simple, but powerful and cheap switch
slave nodes for LIN Bus systems.
MLX80104/5 – Datasheet
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LIN Slave Controller for Switches
DatasheetContents
1.

General Overview .............................................................................................................................................. 7
1.1

2.

3.

4.

Electrical Characteristics .................................................................................................................................... 8
2.1

Absolute Maximum Ratings ............................................................................................................................. 8

2.2

Operating Conditions ....................................................................................................................................... 9

2.3

Static Characteristics ....................................................................................................................................... 9

2.4

Dynamic Characteristics ................................................................................................................................ 12

MULAN – MULtiple CPU with Analog and Network support .............................................................................13
3.1

General .......................................................................................................................................................... 13

3.2

MULAN Block Diagram .................................................................................................................................. 13

3.3

CPU Timing .................................................................................................................................................... 14

3.4

MLX16-8 ......................................................................................................................................................... 14

Address Space ..................................................................................................................................................15
4.1

Memory Mapping .......................................................................................................................................... 15

4.2

RAM Sharing .................................................................................................................................................. 16

4.3

ROM/OTP Sharing .......................................................................................................................................... 16

4.4

EEPROM ......................................................................................................................................................... 17

4.4.1.
4.4.2.
4.4.3.
4.4.4.
4.4.5.

4.5
5.

6.

Block Diagram.................................................................................................................................................. 7

Static/dynamic Characteristics ...............................................................................................................................17
Write Timing ..........................................................................................................................................................17
Read timing ............................................................................................................................................................17
Read .......................................................................................................................................................................18
Write/Erase ............................................................................................................................................................19

OTP (MLX80105 only) .................................................................................................................................... 21

IO Registers ......................................................................................................................................................22
5.1

General .......................................................................................................................................................... 22

5.2

System Protected ports .................................................................................................................................. 22

5.3Standard ports ............................................................................................................................................... 24

IO Ports ............................................................................................................................................................25
6.1
6.1.1.
6.1.2.
6.1.3.
6.1.4.
6.1.5.
6.1.6.
6.1.7.
6.1.8.

Common Features of Pin SWx and IOx .......................................................................................................... 25
Pin structure ..........................................................................................................................................................26
Configuration Register Central Current Source ......................................................................................................27
Configuration Register SWx ...................................................................................................................................28
Configuration Register IOx .....................................................................................................................................29
Switch current generation .....................................................................................................................................30
The switch detection thresholds ............................................................................................................................31
Switch diagnosis .....................................................................................................................................................33
Switch Configuration in sleep mode ......................................................................................................................36

6.2

Additional Operation Modes SWx Ports ........................................................................................................ 37

6.3

Additional Operation Modes IOx Ports .......................................................................................................... 40

6.4

The IREF pin ................................................................................................................................................... 42

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LIN Slave Controller for Switches
Datasheet
7.

Clock System ....................................................................................................................................................43
7.1

RC-Oscillator .................................................................................................................................................. 43

7.2

Crystal Oscillator ............................................................................................................................................ 43

8.

Watchdog System .............................................................................................................................................44
8.1

Analogue Watchdog ...................................................................................................................................... 44

8.1.1.
8.1.2.

Using the analogue WDOG ....................................................................................................................................45
Timing definition ....................................................................................................................................................45

8.2

Digital Window Watchdog............................................................................................................................. 46

8.3

Watchdog Register ........................................................................................................................................ 47

9.

Analogue to digital converter ...........................................................................................................................48
9.1

General Description ....................................................................................................................................... 48

9.2

Input divider ................................................................................................................................................... 49

9.3

Accuracy of the reference .............................................................................................................................. 49

9.4

ADC Register .................................................................................................................................................. 50

10.

Interrupts .........................................................................................................................................................51

10.1

Interrupt vectors ............................................................................................................................................ 52

10.2

Priority port .................................................................................................................................................... 52

10.3

Interrupt mask and pending ports ................................................................................................................. 52

10.4

High level system interrupts .......................................................................................................................... 53

10.4.1.
10.4.2.
10.4.3.
10.4.4.
10.4.5.
10.4.6.

Reset interrupt and watchdogs ..............................................................................................................................53
Stack error..............................................................................................................................................................53
Exception error ......................................................................................................................................................54
Protection error .....................................................................................................................................................54
Invalid address .......................................................................................................................................................54
Program error ........................................................................................................................................................54

10.5

Debugger interrupt ........................................................................................................................................ 55

10.6

Pin change Interrupt ...................................................................................................................................... 55

10.7

External Watchdog interrupt ......................................................................................................................... 55

10.8

Software interrupt ......................................................................................................................................... 55

11.

PWM Unit.........................................................................................................................................................56

11.1

General .......................................................................................................................................................... 56

11.2

Block Diagram................................................................................................................................................ 56

11.3

PWM frequency calculation ........................................................................................................................... 57

11.4

PWM Control Register ................................................................................................................................... 57

11.5

Available PWM Frequencies .......................................................................................................................... 59

12.

Timer ................................................................................................................................................................60

12.1
13.

Timer Calculation ........................................................................................................................................... 60

LIN Interface .....................................................................................................................................................61

13.1

The Concept ................................................................................................................................................... 61

13.2

LIN Physical Layer .......................................................................................................................................... 62

14.

Sleep Mode and Wake up System ....................................................................................................................65

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LIN Slave Controller for Switches
Datasheet
14.1

Entering Sleep Mode by API ........................................................................................................................... 65

14.2

Wake Up System ............................................................................................................................................ 65

14.2.1.
14.2.2.
14.2.3.

LIN Bus ...................................................................................................................................................................65
Local Wake-up .......................................................................................................................................................65
Internal Wake-up ...................................................................................................................................................65

15.

Thermal Shutdown ...........................................................................................................................................66

16.

System behaviour .............................................................................................................................................67

16.1

Reset behaviour ............................................................................................................................................. 67

16.2

Initialising the System .................................................................................................................................... 67

17.

ROM Patches ....................................................................................................................................................69

17.1

Principle of operation .................................................................................................................................... 69

17.2

Patch start address ........................................................................................................................................ 70

17.3

Patch jump instruction ................................................................................................................................... 70

18.

Application Hints ..............................................................................................................................................72

18.1

Application Examples ..................................................................................................................................... 72

18.1.1.

19.

Software Development ....................................................................................................................................75

19.1
20.

Switch Matrix Hints ................................................................................................................................................73

UniROM (80104 only) .................................................................................................................................... 75

Programming Interface.....................................................................................................................................77

20.1

Characteristics for the interface pins ............................................................................................................. 78

20.2

Melexis Mini E-Mlx emulator ......................................................................................................................... 79

20.3

Melexis Mini E-Mlx emulator and Melexis interface adapter ........................................................................ 81

20.4

Melexis Programmer PTC-04 ......................................................................................................................... 83

20.4.1.

20.5
21.

PTC04 DB 15 Female Connector ............................................................................................................................84

Third party programmer ................................................................................................................................ 86

Operating under Disturbance ...........................................................................................................................87

21.1

Loss of battery ............................................................................................................................................... 87

21.2

Loss of Ground ............................................................................................................................................... 87

21.3

Short circuit to battery ................................................................................................................................... 87

21.4

Short circuit to ground ................................................................................................................................... 87

21.5

Thermal overload ........................................................................................................................................... 87

21.6

Undervoltage Vs ............................................................................................................................................ 87

22.

Marking/Order Code ........................................................................................................................................88

22.1

Marking MLX80104 ....................................................................................................................................... 88

22.2

Order Code MLX80104 ................................................................................................................................... 88

22.3

Marking MLX80105 ....................................................................................................................................... 89

22.4

Order Code MLX80105 ................................................................................................................................... 89

23.

Pin Description .................................................................................................................................................90

24.

Mechanical Specification ..................................................................................................................................92

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LIN Slave Controller for Switches
Datasheet25.

Land Pattern Recommendations ......................................................................................................................93

26.

ESD/EMC Remarks ............................................................................................................................................94

26.1

ESD/EMC Recommendations for the MLX80104/5 ........................................................................................ 94

26.2

Automotive Qualification Test Pulses ............................................................................................................ 94

26.3

EMC Test pulse definition .............................................................................................................................. 95

27.

References .......................................................................................................................................................96

28.

List of Abbreviations .........................................................................................................................................96

29.

Revision History ...............................................................................................................................................9730.

Standard information regarding manufacturability of Melexis products with different soldering processes ....99

31.

Disclaimer ......................................................................................................................................................100

List of Figures
FIGURE 1 - BLOCK DIAGRAM ............................................................................................................................................... 7
FIGURE 2 - BLOCK DIAGRAM OF MULAN CPU ................................................................................................................ 13
FIGURE 3 - CPU INTERLEAVING ........................................................................................................................................ 14
FIGURE 4 - EEPROM READ ............................................................................................................................................... 18
FIGURE 5 - COMMON PIN STRUCTURE SWX AND IOX........................................................................................................ 26
FIGURE 6 - VOLTAGE DEPENDENCY OF THE SWITCH CURRENT........................................................................................... 30
FIGURE 7 - VOLTAGE DROPS EXTERNAL LS SWITCH .......................................................................................................... 31
FIGURE 8 - VOLTAGE DROPS SWITCH MATRIX.................................................................................................................... 31
FIGURE 9 - VOLTAGE DROPS EXTERNAL HS SWITCH ......................................................................................................... 32
FIGURE 10 - WAKE UP DETECTION FOR SWITCH INPUTS ..................................................................................................... 37
FIGURE 11 - STRUCTURE OF SWX PINS .............................................................................................................................. 38
FIGURE 12 - STRUCTURE OF IOX PINS ................................................................................................................................ 40
FIGURE 13 - SAMPLE CIRCUITRY FOR IREF PIN ................................................................................................................. 42
FIGURE 14 - ANALOGUE WATCHDOG BEHAVIOUR ............................................................................................................. 44
FIGURE 15 - ADC COMPONENTS ........................................................................................................................................ 48
FIGURE 16 - PWM UNIT..................................................................................................................................................... 56
FIGURE 17 - BLOCK DIAGRAM OF TIMER........................................................................................................................... 60
FIGURE 18 - LIN OSI-REFERENCE MODEL......................................................................................................................... 61
FIGURE 19 - RECEIVER DEBOUNCING & PROPAGATION DELAY .......................................................................................... 62
FIGURE 20 - RESET BEHAVIOUR ......................................................................................................................................... 67
FIGURE 21 - PATCH HARDWARE ........................................................................................................................................ 69
FIGURE 22 - PATCH CODE IN EEPROM ............................................................................................................................. 70
FIGURE 23 - PATCH CODE IN RAM .................................................................................................................................... 70
FIGURE 24 - APPLICATION SCHEMATIC SAMPLE ................................................................................................................. 73
FIGURE 25 - READING THE SWITCH MATRIX ...................................................................................................................... 74
FIGURE 26 - PIN OUT MLX80104/05 – TOP VIEW .............................................................................................................. 77
FIGURE 27 - MLX80104/05 PROGRAMMING INTERFACE WITH THE MELEXIS MINI E-MLX EMULATOR ............................. 80
FIGURE 28 - MELEXIS MLX80104/05 PROGRAMMING INTERFACE ADAPTER ..................................................................... 81
FIGURE 29 - MLX80104/05 PROGRAMMING INTERFACE WITH THE MELEXIS MINI E-MLX EMULATOR AND MELEXISINTERFACE ADAPTER ................................................................................................................................................. 82
FIGURE 30 - CONNECTION DIAGRAM BETWEEN PTC-04 AND MLX80104/5 ...................................................................... 83
FIGURE 31 - MLX80104/05 PROGRAMMING INTERFACE WITH THE MELEXIS PTC-04 ....................................................... 85
FIGURE 32 - PIN OUT MLX80104/5 – TOP VIEW ................................................................................................................ 90
FIGURE 33 - QFN28 DRAWING .......................................................................................................................................... 92

MLX80104/5 – Datasheet
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LIN Slave Controller for Switches
Datasheet

List of Tables
TABLE 1 - ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 8
TABLE 2 - OPERATING CONDITIONS .................................................................................................................................... 9
TABLE 3 - STATIC CHARACTERISTICS ................................................................................................................................ 11
TABLE 4 - DYNAMIC CHARACTERISTICS ............................................................................................................................ 12
TABLE 5 - UNIFIED MEMORY MAPPING .............................................................................................................................. 15
TABLE 6 - MLX16 PRE-DEFINED PAGES ............................................................................................................................ 16
TABLE 7 - SYSTEM PROTECTED PORTS OVERVIEW ............................................................................................................ 23
TABLE 8 - STANDARD PORTS OVERVIEW .......................................................................................................................... 24
TABLE 9 - LOGIC TABLE FOR DETECTION OF LS INPUT SWITCHES ...................................................................................... 33
TABLE 10 - LOGIC TABLE FOR DIAGNOSIS OF LS INPUT SWITCHES SHORT VS. BATTERY .................................................... 33
TABLE 11 - LOGIC TABLE FOR DIAGNOSIS OF ALL INPUT SWITCHES SHORT VS. OTHER SWITCHES BY I1............................. 33
TABLE 12 - LOGIC TABLE FOR DIAGNOSIS OF ALL INPUT SWITCHES SHORT VS. OTHER SWITCHES BY I2............................. 34
TABLE 13 - LOGIC TABLE FOR BREAK DETECTION OF LS INPUT SWITCHES ........................................................................ 34
TABLE 14 - LOGIC TABLE FOR DETECTION OF HS INPUT SWITCHES ................................................................................... 34
TABLE 15 - LOGIC TABLE FOR DIAGNOSIS OF HS INPUT SWITCHES SHORT VS. GND .......................................................... 34
TABLE 16 - LOGIC TABLE FOR BREAK DETECTION OF HS INPUT SWITCHES ........................................................................ 35
TABLE 17 - SLEEP MODE CONFIGURATION OVERVIEW (SWITCH DETECTION) ..................................................................... 37
TABLE 18 - ACTIVE MODE CONFIGURATION OVERVIEW SWX PINS .................................................................................... 39
TABLE 19 - ACTIVE MODE CONFIGURATION OVERVIEW IOX PINS ...................................................................................... 41
TABLE 20 - ADC INPUT DIVIDER ....................................................................................................................................... 49
TABLE 21 - INTERRUPT INPUTS .......................................................................................................................................... 51
TABLE 22 - INTERRUPT VECTORS ....................................................................................................................................... 52
TABLE 23 - PRIO PORT ENCODING .................................................................................................................................... 52
TABLE 24 - CONFIGURABLE PWM FREQUENCIES.............................................................................................................. 59
TABLE 25 - DUTY CYCLE MEASUREMENT AND CALCULATION IN ACCORDANCE TO LIN PHYSICAL LAYER SPECIFICATION
2.X FOR BAUD RATES UP TO 20KBPS .......................................................................................................................... 63
TABLE 26 - DUTY CYCLE MEASUREMENT AND CALCULATION IN ACCORDANCE TO LIN PHYSICAL LAYER SPECIFICATION
2.X FOR BAUD RATES OF 10.4KBPS OR BELOW ........................................................................................................... 64
TABLE 27 - PIN DESCRIPTION 9 PIN MINI CIRCULAR CONNECTOR ....................................................................................... 79
TABLE 28 - PIN DESCRIPTION 10 PIN HEADER CONNECTOR ................................................................................................ 81
TABLE 29 - CONNECTIONS FOR THIRD PARTY PROGRAMMER ............................................................................................. 86

MLX80104/5 – Datasheet
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LIN Slave Controller for Switches
Datasheet

1. General Overview
1.1

Block Diagram

Figure 1 shows the principle block diagram of MLX80104/5.

Power Supply

VS

VDDD
VDDA

ADC_VS

VS

VAUX

8mA
In high

...
SW1
SW2
...

...

Auxiliary Supply +WakeUp Logic

ADC_MUXADC_IO1 In
IO_IN
IO1 InIO Mux

SW1

...

SW4
SW5

IO Mux IO6

10-bitADC

Window
WD

Timer

IREF

ADC_IREF

RC-

GNDA

Oscillator
12 MHzGNDD
GNDL

Dual Task
MULAN LIN MCU

16kbyte ROM/OTP

512byte RAM

TI0
TO

VS
2mA

IO4

TI1
Test/Debug
Interface

MUX
SW9 In

IO3

IO6
IO7

ADC_IOx
ADC_VS
ADC_IREF

...

SW9

IO2

IO5

IO6 Out
PWMx OutIO Mux SW9

IO1

IO6 InIO Mux SW5

SW5 InIO0

ADC_IO6 In

PWM

SW6
SW7
SW8

IO1 Out
PWMx Out

PWM0
...
PWM7

SW0 InSW3

WD

WakeUp SWx

8mA

SW2

POR/WD

WakeUp LIN

IO0
IO1
...
In low

SW0

UVLO

LIN
Transceiver

LIN

192byte EEPROM

Figure 1 - Block Diagram

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LIN Slave Controller for Switches
Datasheet

2. Electrical Characteristics
All voltages are referenced to ground (GND). Positive currents flow into the IC.

2.1

Absolute Maximum Ratings

In accordance with the Maximum Rating System (IEC 60134). The absolute maximum ratings given in the table below
are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so.
Long term exposure to limiting values may affect the reliability of the device.
Parameter

SymbolBattery Supply Voltage
Short term supply voltage
Transients at supply voltage
Transients at supply voltage
Transients at high voltage signal pins
Transients at high voltage signal pins
Transient at high voltage signal and power supply pins

VS
VS_ld
VS_tr1
VS_tr2
VLINx_tr1
VLINx_tr2
VHV_tr3

DC voltage on LIN, SWx, IOx pins

VLIN_DCDC voltage on IREF, AWD pin

Vlogic_DC
VESDIEC

ESD capability

Maximum latch – up free current at any pin

VESDHBMVESDCDMILATCH

Maximum power dissipation

Ptot

Thermal impedance

JA
Tstg
Tvj

Storage temperature
Junction temperature

Condition

Min

Max

Unit

-0.3
-0.3
-100

40
40

+50
+100

V
V
V
V
V
V
V

40

V

7

V

-6

6

kV

-8
-2
-750
-500

kV
kV
V
mA

Tamb = +125 °C
Tamb = + 85 °C

8
2
750
500
0.78
2

JEDEC 1s2p board, none air flow

32

K/W

+150
+150

°C
°C

ISO 7637/2 pulse 5; t < 400 ms
ISO 7637/2 pulse 1[1]ISO 7637/2 pulses 2 [1]ISO 7637/3 pulse 1 [2]ISO 7637/3 pulses 2 [2]ISO 7637/2 pulses 3A, 3B [3]T<500ms, VS = 18V
VS = 0V
IEC 61000-4-2
Pin LIN, VS to GND
HBM (AEC-Q100-002) [4]
Pin LIN, VS to GND
Other pins
CDM (AEC-Q100-011)

+50
-100
-150
-22
-40
-0.3

-55
-40

W

Table 1 - Absolute Maximum Ratings

[1]
[2]
[3]
[4]

ISO 7637/2 test pulses are applied to VS via a reverse polarity diode and >2uF blocking capacitor.
ISO 7637/3 test pulses are applied to LIN via a coupling capacitance of 100nF.
ISO 7637/3 test pulses are applied to LIN via a coupling capacitance of 1nF.
ISO 7637/2 test pulses are applied to VS via a reverse polarity diode and >2uF blocking capacitor.
Equivalent to discharging a 100pF capacitor through a 1.5Kohm resistor conforms to AEC-Q100-002

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LIN Slave Controller for Switches
Datasheet

2.2

Operating Conditions

Parameter
Battery supply voltage [1]Short time battery supply voltage [2]Operating ambient temperature

Symbol

Min

Max

Unit

VS
VS_S
Tamb

5
18
-40

18
27
+125

V
V
°C

Table 2 - Operating Conditions[1][2]

Vs is the IC supply voltage including voltage drop of reverse battery protection diode, V DROP = 0.4…1V, VBAT_ECU = 6…27V.
Short time: t < 1 min

2.3

Static Characteristics(VS = 5 to 27V, TA = -40 to +125°C, unless otherwise specified)Parameter

SymbolCondition

Min

Typ

Max

Unit

6

20

mA

5

V

50

µA

90

µA

Pin VS
3.00

Supply current, active withoutswitch current

IS

3.01

Undervoltage lockout

VS_UV

3.02

Supply current, sleep mode

ISsl_typ

VS = 12V

3.03

Supply current, sleep mode

ISsl

VS = 18V

25

PIN LIN
3.10

Short circuit bus current

IBUS_LIM

VLIN= VS = 18V, TxD = 0

40

120

200

mA

3.11

Pull up resistor LIN

RSLAVE

VLIN=0, TxD open

20

30

60

k

3.12

Pull up current LIN, Sleep mode

IBUS_PU_Sleep VLIN=0, VS=12V, sleep mode

-100

-75

3.13

LIN reverse current, recessive

IBUS_PAS_rec

Receiver input leakage current

IBUS_PAS_dom VS = 12V, VLIN=0

3.14

LIN reverse current loss of battery

IBUS_NO_BAT VS=0V, 0V < VLIN < 18V

3.15

LIN current during loss of Ground [3]IBUS_NO_GND VS=VGND=12V, 0V<VLIN<18V

3.16

Transmitter dominant voltage

Vol_LIN

load=500, TxD=0

3.17

Recessive output voltage

Voh_LINTxD open

3.18

Lin input capacitance [1]CLIN

Pulse response via 1k,VPulse=12V, VS=14V

3.19

Voltage drop serial diode [1]CSerDiode

3.30

Receiver dominant voltage

VBUSdom

3.31

Receiver recessive voltage

VBUSrec

3.32

Centre point of receiver threshold

VBUS_cnt

VBUS_cnt =( Vth_dom + Vth_rec )/2

3.33

Receiver hysteresis

VHYS

VHYS =( Vth_dom -Vth_rec )MLX80104/5 – Datasheet
390108010400

VLIN>VS , 5V <VLIN <18V,
5V <VS <18V , TxD open

µA
20

µA

-1

mA
23

µA

20

µA

0.2

Vs

1

Vs

25

35

pF

0.7

1.0

V

0.4*VS

V

-100
0.8

0.4
0.6*VS

Page 9 of 100

0.475*VsV
0.5*Vs

0.525*VsV

0.175*Vs

V

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LIN Slave Controller for Switches
Datasheet
Parameter

SymbolCondition

Min

Typ

Max

Unit

PIN SWx, IOx in normal mode
3.40

Central current source on
resistance pull up configuration

Rih_SWx

Pull up mode, voltage shift
max 0.1*Vs

1

K

3.41

Central current source on
resistance pull down configuration

Ril_SWx

Pull down mode, voltage shift
max 0.1*Vs

1

K

3.42

High level input voltage

Vih_SWx

Input mode

3.43

Low level input voltage

Vil_SWx

Input mode

3.44

On resistance SWx

RON_IO

Low side mode, VSWx=0.5V

3.45

Source current central current
sourceIih_SWx

Vs=5V
Vs=13V (TA = 25°C)
Vs=18V

1.5
7

3.46

Sink current central current source

Iil_SWx

Vs=5V
Vs=13V (TA = 25°C)
Vs=18V

1.5
7

1.4

V
50

0.9

V

100



12

mA

mA
12

3.47

Leakage current low level input

Ileakl_SWx

Vil_SWx = 0, VS = 18V

-10

10

µA

3.48

Leakage current high level input

Ileakh_SWx

Vih_SWx = 18V, VS = 18V

-10

10

µA

Vs

V

3.1

mA

PIN IREF
3.60

Input voltage range

VIREF

0

3.61

Output current

IIREF

1.3

3.62

Leakage current low level input

Ileakl_IREF

VlREF = 0, VS = 18V

-10

10

µA

3.63

Leakage current high level input

Ileakh_IREF

VIREF = 3.4V, VS = 18V

-10

10

µA

0

3.4

V

2

PIN AWD
3.70

Input voltage range

VAWD

3.71

Pull down current

IPD_AWD

2

µA

3.72

Pull up current

IPU_AWD

20

µA

3.73

RESET threshold

VAWD_IRQ

0.5

V

3.74

Interrupt threshold

VAWD_Int

1.5

V

3.75

Down threshold

VAWD_d2.5

V

Wakeup capability SWx,IOx
3.80

Wake up pull up resistance SWx,
IOx [4]

Rih_WU_SWx

Pull up mode, voltage shift
max 0.1Vs

500

1000



3.81

Wake up pull down resistanceSWx, IOx [4]Ril_WU_SWx

Pull down mode, voltage shift
max 0.1Vs

500

1000



3.82

High level input voltage

Vih_WU_SWx

Input mode

1.4

3.83

Low level input voltage

Vil_WU_SWx

Input mode

3.84

On resistance in sleep mode
SWx/IOx

RON_WU_IO

Low side mode (S3x),
VSWx/IOx=0.5V

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V

50

0.9

V

100

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LIN Slave Controller for Switches
Datasheet
Parameter

SymbolCondition

Min

Typ

Max

Unit

Thermal Protection
3.90

Thermal shutdown [1]

Tsd

155

180

°C

3.91

Thermal recovery [1]

Trec

126

150

°C

One time measurement

5

LSB

Three time measurement

2

LSB

1000



ADC Resolution (INL)
3.67
3.68

ADC accuracy

Vmess_diff

Switches
On - resistance [2] [5]

RSW _oncarbon on gold0

Off - resistance [2]RSW _off

Open switch

500

150

K

Table 3 - Static Characteristics
[1]
[2]
[3]
[4]
[5]

Parameter not tested in production, guaranteed by qualification.
Switch parameter not determined by the IC, values are calculation basis for all currents and thresholds
The current is determined by the master pull-up. To prevent discharging of the battery, the master pull up will be disconnectedunder Loss of Ground conditions
Resistance is valid for the sum of switch resistance and the ESD protection resistance
A 500Ohm series resistor is required in case of the remote switch outside of the module and the switch is in this case directly
supplied from the battery

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2.4

Dynamic Characteristics(VS = 7 to 27V, TA = -40 to +125°C, unless otherwise specified)Parameter

SymbolCondition

Min

Typ

Max

Unit

6

µs

PIN LIN
trx_pdf

CRxD = 25pF, rising and Falling
edge

[2]

trx_sym

ttx_pdf - trx_pdr

-2

2

µs

4.03

Receiver debounce time [2]trx_deb

LIN rising and falling edge

0.5

4

µs

4.04

LIN duty cycle 1 [3,4]D1

20kbps operation, normal modetBit = 50µs, D1=tLIN_rec(min)/(2*tBit)

0.396

4.05

LIN duty cycle 2 [3,4]D2

20kbps operation, normal modetBit = 50µs, D2=tLIN_rec(max)/(2*tBit)

4.06

LIN duty cycle 3 [3,4]D3

10.4kbps operation, low speed,tBit = 96µs, D3=tLIN_rec(min)/(2*tBit)

4.07

LIN duty cycle 4 [3,4]D4

10.4kbps operation, low speed,tBit = 96µs, D3=tLIN_rec(max)/(2*tBit)

0.590

4.08

trec(max) – tdom(min)t3

10.4kbps operation, low speed
mode

15.9

µs

4.09

trec(min) – tdom(max)t4

10.4kbps operation, low speed
mode

17.28

µs

4.12

Wake up filter timetWU

Sleep mode, LIN rising andfalling edge

150

µs

50

µs

4.01
4.02

Propagation delay receiver [1]Propagation delay receiver symmetry

0.581
0.417

15

PIN SWx/IOx
4.21

Local wake-up filter time

twu_local

Sleep mode rising and falling
edge

10

25

ADCx
4.22

Conversion time ADC

tconv

12

µs

PIN IOx
4.24

Slew Rate IOx[5]tSlew_IOx

Low side mode, VS=6V, Rpullup=2.5k, Cload = 20pF

2.5

µs

10

ms

General
Device start up time [6] [7]tSUP

After POR,UVR, Wakeup

3

5

Table 4 - Dynamic Characteristics
[1]
[2]
[3]
[4]
[5]
[6]
[7]

This parameter is tested by applying a square wave signal to the LIN. The minimum slew rate for the LIN rising and fallingedges is 50V/us
See figure – Receiver debounce and propagation delay
See figure – Duty cycle measurement and calculation
Standard loads for duty cycle measurements are 1K/1nF, 660/6.8nF, 500/10nF, internal termination disabled
Only information
Only characterization, guaranteed by design
This time contains the activation time of hardware components and the software initialisation time. To get first valid switch status
information, the programmed switch debouncing time must be added.

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3. MULAN – MULtiple CPU with Analog and Network support
3.1

GeneralThe MULAN CPU is a dual task implementation of the Melexis LIN Controller (MLX4) and the MLX16-8 CPU core. It is
possible to run two tasks simultaneously with this architecture, one task for communication and the other task is free
for the customer application. The communication between both tasks is done via API commands. The complete
firmware including API for the LIN controller is supported by Melexis. The Customer only needs to program theapplication software on the MLX16-8 CPU. For a detailed description of this CPU please see the MLX16-8 data book.

MULAN Block Diagram

RB

12MHz

3.2

Mulan
Test
controller
Mlx16
perpheryInterrupt
controller

EEPROM

Mlx4
perpheryMlx16-8

CPUs
interfac
e

Mlx4

ROM
arbiterRAM
arbiter

ROM

RAM

Mlx4 - Mlx16 shared resources

Figure 2 - Block Diagram of MULAN CPU

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Datasheet

3.3

CPU Timing

MULAN use two CPUs:
A 4 bit CPU to handle a low speed protocol such as LIN.
A 16 bit CPU for an application firmware.
This construction has the following advantages:
The user does not need to take care of the real time problems of a protocol.
The protocol is handled by a Melexis firmware that can be updated when the protocol evolves.
The application CPU throughput is not affected by the protocol handling.
There is a native inter-task protection, e.g. an application crash does not affect the protocol handling.
Both CPUs share a common 12 MHz clock, a common ROM for program memory and a common RAM for data. Twomemory arbiters are used for resolving conflicts with a common strategy: The Mlx4 always has priority.
Most of the time there is no conflict as the CPUs are interleaved as shown on Figure 3.

RAM
accessRAM
accessRAM
access
Delay

Fetch

Execute

Fetch

Execute (ROM
read)

Fetch

Execute

Fetch

ROM
accessROM
accessROM
accessRAM
accessDelay

ExecuteconflictROM
accessRAM
access

Fetch

Fetch

ExecuteExecute

Fetch

ROM
accessROM
accessconflictROM
accessROM
accessFigure 3 - CPU interleaving

3.4

MLX16-8

The 16 bit CPU is an Mlx16-8. This core is an evolution of the Mlx16 to increase GCC code generation efficiency. Thechange is limited to a few added instructions. A detailed description can be found in the Mlx16-8 datasheet. For
readers familiar with the Mlx16, the list of instructions added is:- CALLF: Call Far (anywhere within 64K)
- FSB
: Find first bit set (in a word)- MOVSB [X++], [Y++]: Copy array of bytes- MOVSW [X++], [Y++]: Copy array of words- Push #Word: Push a constant word into the stack- SFB: Set first bit (in a word)
Moreover a new address mode has been added to allow direct access to any location. It is similar to dp: Addressing
mode but allows any address within 64K at expense of an extra word of op-code.

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4. Address Space
Mlx4 and Mlx16 share a common ROM and RAM. From the 2 CPUs a unified 16 bit bus is created (Von Neumannarchitecture). This bus is hooked to the ROM, the RAM, the EEPROM and the Mlx16-8 peripherals. Two arbiters are in
charge of creating a unique memory address and corresponding access signals for ROM and RAM.

4.1

Memory Mapping

The unified 16 bit bus accesses devices as shown on Table 5.
Mlx16-8

E030
E000
C020
C000
B000
A200
A000
80C0
8014
8000
4000
2000

-

FFFF
E02F
DFFF
C01F
BFFF
AFFF
A1FF
9FFF
80BF
8013
7FFF
3FFF

Not used
Mlx16 System Ports
Not used
Mlx16 User ports
Not usedNot used
RAM (2)
Not used
EEPROM (1)EEPROM Melexis Area (1)Not used
ROM

1000 -

1FFF

ROM

0000 -0FFF

ROM

SystemMemory space

Write

Fetch

Allowed

48 Bytes
32 Bytes

RAM: 512 Bytes(2)

EEPROM: 172 Bytes
EEPROM: 20 Bytes
ROM: 8kBytes, Mlx16 code
ROM: 4kBytes, Mlx4 or Mlx16
code
ROM: 4kBytes, Minimum Mlx4
code(1): Fetch enabled in this area for patch codes(2): See RAM sharing for Mlx4-Mlx16 distribution and protection
Table 5 - Unified memory mapping
There are some restrictions for accessing certain areas depending on the type of access:Mlx4 can fetch anywhere from 0x0000 to 0x1FFF (12 bits word address)
Mlx16 can fetch from:o ROM:
Normal caseo EEPROM:
For patched codeo RAM:For test purposes
Mlx4 and Mlx16 can read any RAM location (limited to 256 bytes for Mlx4)

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The predefined pages of the Mlx16-8 are encoded as shown on Table 5. Some have fixed values (in grey) while others
have value that depends of the ROM size. Table 6 gives examples for most common ROM sizes.

Name
Fp0:
Fp1:
Fp2:
Fp3:
Fp4:
Fp5:
Fp6:
Fp7:
Dp:
Io:
Ep:

ROM
16K Note
3F00 Last ROM page (used by interrupt controller)
3E00 Could be used for C runtime
3D00 Could be used for C runtime
3C00 Could be used for C runtime
3B00 Could be used for C runtime
A100 In (large) RAM for fast patches (copied from EEPROM)
A000 In RAM Dp: for test routines
8000 In EEPROM to allow single instruction patch start
A000 Mlx16 private RAM
C000 Standard Ports
8000 EEPROM (First page)
Legend:Fixed address for any ROM size
Address depending on the ROM size
Table 6 - MLX16 pre-defined pages

4.2

RAM Sharing

A RAM size of 512 bytes is available for the MLX80104/5. This area is used by both CPUs.
While Mlx4 sees its private and shared RAM areas as 2 consecutive spaces, Mlx16 sees the private area of Mlx4 at the
top of its RAM address space and the shared area at its bottom. This arrangement has the following advantages:
 Shared area is in Mlx16 Dp: address space, so Mlx16 has a fast access to it.
 The Mlx16-8 private area is in a single piece which makes GCC more efficient.

4.3

ROM/OTP Sharing

The MLX80104/5 has integrated 16Kbyte ROM or OTP. This area is used from both CPUs. The LIN Task + LIN API use
5kbytes while the rest (11kbytes) is available for the application running on the MLX16
Each CPU has is own separate program code in the ROM/OTP area but there is no specific mechanism to isolate them.
The linker program merges the two programs and verifies that there is no overlapping, but if at execution time anerror causes one CPU to jump into the code of the other one, it will of course execute unpredictable instructions andthis situation will be detected either by watchdog overflow or protection error.

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4.4

EEPROM

With the EEPROM it is possible to store non-volatile information. The EEPROM block is a 96 x 16bit Electrically
Erasable Programmable Read Only Memory (EEPROM) with single power supply, single-error correction (SEC) anddouble-error detection (DED). An internal charge pump generates high voltage needed for the Erase/Write operations.
The EEPROM is Mlx16 private. The required EEPROM data for the Mlx4 execution is placed in RAM by the Mlx16
before it releases Mlx4 reset.
The EEPROM is organized in words (16 bits). Reading byte-wise is possible, but writing is only possible word-wise.

4.4.1. Static/dynamic Characteristics
Parameter

Remarkmin

Tamb = 25°C

100 000

Tamb = 125°C

10 000

Data retention time

Tamb = 85°C

10Erase/Write time

Tamb = -40…125°C

4

Number of erase/write cycles

Typ

Max

Unit

Years
8

ms

4.4.2. Reserved EEPROM Segments
Segment name
Melexis area
Patch0 start address
Patch1 start address
User area
Patch0 area
Patch1 area

Segment range(word addresses)
0x8000 – 0x8013
0x80140x80160x8018 – 0x809E
0x80A0 – 0x80AE
0x80B0 – 0x80BE

Description
Melexis calibration data
start address and enable bit for firmware patch 0
start address and enable bit for firmware patch 1
User data
Patch0Patch1The using of firmware patches is optional but recommended. In case no firmware patch is used, these areas can beused for user data.

4.4.3. Write Timing
The EEPROM requires a 5ms delay for write and erase operations. This is generated from a 250 KHz internal clock. A
write or erase access to the EEPROM starts a 5ms delay period that can be monitored by either polling port bit
EE_BUSY or waiting for the interrupt EE_IT.
Note:
While the EEPROM is being written, both CPUs are still running. An attempt to read or write to EEPROM by Mlx16
while it is busy generates an exception interrupt.

4.4.4. Read timing
The read access time of the EEPROM is 4 clock periods. This delay is created using the master clock.

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4.4.5. Read
A read is done “on the fly” by adding wait states in the instruction.
Instruction

Instruction

Read EEPROM instruction

Instruction

250ns Delay

Figure 4 - EEPROM read

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Datasheet

4.4.6. Write/Erase
The MLx16 supports 2 operations: Read and Write, while EEPROM requires 3 operations: Read, Write, and Erase.
EEPROM Write and Erase are both accomplished by an Mlx16 write instruction.
As write and erase delays are long, the Mlx16 does not delay its instruction till completion. A specific hardware buffers
address and data and the CPU continues its execution while the write/erase is ongoing.
The CPU has 2 options to know when the write/erase delay is terminated. It can either poll bit EE_BUSY (0 when notbusy, 1 when busy) for a 0 value, or it can enable interrupt EE_IT that will be triggered when EE_BUSY goes from 1 to0.
In order to minimize the risk of erroneous write/erase of the EEPROM, those accesses are only possible in systemmode, e.g. application should call a secure system function to erase or write.
Since some applications require the EEPROM should never be written there is an extra protection for the EEPROM.
The system port CONTROL has a bit EN_EEPROM_WE (0 at reset) that must be set to enable write and erase, or elsethe operation is cancelled and a protection interrupt is generated.
EEPROM Control register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

0xE001

EEPROM

EE_BUSY

Reserved

Reserved

Reserved

Reserved

EE_BUSY
EE_CTL[1:0]

Bit2

Bit1

Bit0

Reserved EE_CTL[1] EE_CTL[0]Will be always high in case there is a write process running
Controls the EEPROM read and write mode
00
Write
01
Erase
10
Block write, write access to any EEPROM address will overwrite the complete EEPROM
11
Block erase, write access to any EEPROM address will reset the complete EEPROM to 1

System Control register
Address

Name

Bit7

0xE000CONTROL

Reserved

EEPROM_WE
OUTC_WEOUTB_WEOUTA_WE
HALT
M4_PORB

Bit6

Bit5

Bit4

Bit3

Bit2

EEPROM_
OUTC_WE OUTB_WE OUTA_WE Reserved
WE

Bit1

Bit0

HALT

M4_PORB

Write enable bit EERPOM
1 = EEPROM content can be changed
0 = EEPROM content can not be changed
Write enable bit
1 = ANA_OUTC can be changed
0 = ANA_OUTC can not be changed
Write enable bit
1 = ANA_OUTB can be changed
0 = ANA_OUTB can not be changed
Write enable bit
1 = ANA_OUTA can be changed
0 = ANA_OUTA can not be changed
Writing to the bit will halt the MLX16
Mlx4 Reset: Writing to the bit resets the MLX4

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System Various register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE000VARIOUSEE_DED

EE_SEC

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

EE_DED
EE_SECEEPROM double-error detection
1 = EEPROM double-error detected
0 = EEPROM double-error not detected
EEPROM single-error correction
1 = EEPROM single-error detected and corrected
0 = EEPROM single-error not detected

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4.5

OTP (MLX80105 only)

The MLX80105 has integrated 16Kbyte OTP. This area is used by both CPUs. The LIN Task + LIN API use
5kbytes while the rest (11kbytes) is available for the application running on the MLX16
Each CPU has is own separate program code in the OTP area but there is no specific mechanism to isolatethem. The linker program merges the two programs and verifies that there is no overlapping, but if at
execution time an error causes one CPU to jump into the code of the other one, it will of course execute
unpredictable instructions and this situation will be detected either by watchdog overflow or protection error.
From the functional point of view the MLX80104 (ROM) behaves the same as the MLX80105 (OTP).

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5. IO Registers
5.1

GeneralThere are 2 port spaces for the Mlx16:
 System protected ports (starting at address 0xE000), Mlx16 bit USER must be cleared.
 User ports (starting at address 0xC000), not protected, Mlx16 bit USER must be set.
The Mulan port map has an open window of 16 bytes of custom user ports and of 12 bytes of custom system ports(not included in Mulan). Reading to non existing custom ports will have no effect and reading from non existentcustom ports will always return 0.

5.2

System Protected ports

Table 7 shows the available system ports. All of these ports are system protected, meaning they are only accessible
with bit USER=0. All of these registers are located outside of the IO-Segment.
Name

Address

AccessMode

MLX
SEL_XTALMLXSTATUS
SW_IN_H
SW_IN_L
IO_IN
IO_AWD
IO_IRQ
IO_EN
IO_INT_ENF
IO_INT_ENR
MLX
MLX
ANA_OUTC_H
ANA_OUTC_L
ANA_OUTB_H
ANA_OUTB_L
ANA_OUTA_H
ANA_OUTA_L
PATCH3_A_H
PATCH3_A_L
PATCH2_A_H
PATCH2_A_L
PATCH1_A_H
PATCH1_A_L
PATCH0_A_H
PATCH0_A_L

0xE02F
0xE02E
0xE02D
0xE02C
0xE02B
0xE02A
0xE0290xE0280xE0270xE0260xE0250xE0240xE0230xE0220xE0210xE0200xE01F0xE01E0xE01D
0xE01C
0xE01B
0xE01A
0xE0190xE0180xE0170xE0160xE0150xE014Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte

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Description
MLX Reserved
Selection of internal/external Oscillator
MLX Reserved
Wakeup Source and central pull up/down input comparator
SW8..9 Input comparator
SW0..7 Input comparator
IO0..8 Input comparator
Watchdog Acknowledge
Interrupt source of IO generated interrupts
Enable IO pins
Enable IO interrupt on falling edges
Enable IO interrupt on rising edges
MLX Reserved
MLX Reserved
ADC reference calibration
RC Oscillator trimming, enable external system clock source
Current references and bandgap trimming, slew rate LIN transceiver
Switch current source trimming, VDDD and VDDA trimming
Setting EEPROM write delay, timer controlled wake up enable
Power down enable LIN transceiver
4th Patch start address high byte, patch enable
4th Patch start address low byte
3rd Patch start address high byte, patch enable
3rd Patch start address low byte
2nd Patch start address high byte, patch enable
2nd Patch start address low byte
1st Patch start address high byte, patch enable
1st Patch start address low byte

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Page

43
27
28
28
29
44
29
29
29
29

68
68
68
68
68
68
70
70
70
70
70
70
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LIN Slave Controller for Switches
Datasheet
Name

Address

PATCH3_I_H
PATCH3_I_L
PATCH2_I_H
PATCH2_I_L
PATCH1_I_H
PATCH1_I_L
PATCH0_I_H
PATCH0_I_L
MLX
MLX
PEND_H
PEND_L
MASK_H
MASK_L
PRIO_H
PRIO_LSHRAMHSHRAMLEEPROMCONTROL

0xE0130xE0120xE0110xE0100xE00F0xE00E0xE00D
0xE00C
0xE00B
0xE00A
0xE0090xE0080xE0070xE0060xE0050xE0040xE0030xE0020xE0010xE000AccessMode
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Word/Byte
Byte
Byte

Description
4th Patch jump instruction high byte
4th Patch jump instruction low byte
3rd Patch jump instruction high byte
3rd Patch jump instruction low byte
2nd Patch jump instruction high byte
2nd Patch jump instruction low byte
1st Patch jump instruction high byte
1st Patch jump instruction low byte
MLX reserved
MLX reserved
Pending Interrupts high byte
Pending Interrupts low byte
Interrupt mask high byte
Interrupt mask low byte
Interrupt priority high byte
Interrupt Priority low byte
Upper limit for the RAM not accessible by MLX16
Lower limit for the RAM not accessible by MLX16
EEPROM control register
System control register

Page
70
70
70
70
70
70
70
70

53
53
53
53
53
53

19
19

Table 7 - System Protected Ports Overview

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5.3

Standard ports

Table 8 shows the available system ports. All of these ports are system protected, meaning they are only accessible
with bit USER=1. All of these registers are located outside of the IO-Segment.
Name

Address

Access
Mode

MLX
MLX

0xC01F
0xC01E

Byte
Word/Byte

SW_CONFIG

0xC01D

S3H
S2H
S1H
S3L_H
S3L_L
S2L_H
S2L_L
S1L_H
S1L_L
PWM_DATA_READ
PWM_DATA_WRITE
PWM_ADPWM_CTL
MLX
MLX
MLX
MLX
ADC_IN_H
ADC_IN_L
ADC_CTL_H
ADC_CTL_L
TIMER_H
TIMER_L
XIN
WTG
WDCTRLWDT
VER
VARIOUS

0xC01C
0xC01B
0xC01A
0xC0190xC0180xC0170xC0160xC0150xC0140xC0130xC0120xC0110xC0100xC00F
0xC00E
0xC00D
0xC00C
0xC00B
0xC00A
0xC0090xC0080xC0070xC0060xC0050xC0040xC0030xC0020xC001
0xC000Description

MLX reserved
MLX reserved
Current configuration central current source, IREF
Byte
enableWord/Byte IO pin open drain enable (S3)Byte
IO pin central current source pull down enable (S2)
Word/Byte IO pin central current source pull up enable (S1)Byte
SW8..9 pin open drain enable (S3)Word/Byte SW0..7 pin open drain enable (S3)Byte
SW8..9 pin central current source pull down enable (S2)
Word/Byte SW0..7 pin central current source pull down enable (S2)Byte
SW8..9 pin central current source pull up enable (S1)
Word/Byte SW0..7 pin central current source pull up enable (S1)Byte
PWM duty cycle value (read only)
Word/Byte PWM duty cycle write register
Byte
PWM channel selection
Word/Byte PWM configuration register
Byte
MLX reserved
Word/Byte MLX reserved
Byte
MLX reserved
Word/Byte MLX reserved
Byte
ADC result high byte
Word/Byte ADC result low byte
Byte
ADC reference voltage and channel selection
Word/Byte ADC configuration and status
Byte
Timer register high byte, Timer enable
Word/Byte Timer register low byte
Byte
Thermal error
Word/Byte Digital Watchdog tag register
Byte
Digital watchdog control register
Word/Byte Digital Watchdog timeout register
Byte
Hardware revision
Word/Byte/Bit System status

Page

27
29
27
27
28
28
27
27
27
27

57
58

50
50
50
50
60
60
66
47

Table 8 - Standard Ports Overview

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6. IO Ports
The MLX80104/5 contains two types of ports. All of them are proof to battery voltage.
In case of ECU loss of battery (LOB) and a short of the wiring harness to an external supply line the MLX80104/5 will
be reverse powered. Please refer to chapter “Operating under Disturbance”.

6.1

Common Features of Pin SWx and IOx

The ports SW0..9 as well as the ports IO0..7 allow a very flexible control of up to 18 single switches or a switch matrix
or any combination of both, supplied by an internal current source of typically >7mA. The switch control is sequential
and periodical, so that only one port will be supplied at the same time.
If switches are placed outside and connected via a wiring harness to the ECU the MLX80104/5 allows full diagnosis ofshort circuits or broken line.
All ports provide a programmable wake up function and a 10mA open drain low side switch (matrix row connection to
GND).
If ports are not used for switch detection, they can be configured passive (tristate behaviour) or as general purpose
10mA open drain output with port monitor. The input thresholds are compatible to 3.3V/5V supply systems. The
accuracy of the input threshold allows a monitoring of external voltages without ADC. It allows connection of external
supplied encoders, halls or similar.
Furthermore this architecture supports driving of logic output signals for other ECU components via an external pullup resistor as well as the driving of high side or low side loads by providing base current for an external pnp transistor.

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6.1.1. Pin structure
Vs

I1

Central switch pin
configuration block

Vref_h
COMP

Vs

Pin
SW1

S1x

2µs

Swin_PU

18x multiplex
High side

Rswitch
+

ESD

Rprot

Pad
SWx/IO_x

SW_in
COMP

LS-switch

Vref_CMOS

EN_GND
S3x
Vbat

HS-switch
Rswitch

Vs

+

Pin
SW2

Rprot

Pad
SWx/IO_x

ESD

18x multiplex
Low side

SW_in
COMP

EN_GND

S2x

Vref_CMOS

Swin_PD

S3x

COMP

2µs

I2
Vref_l

MLX80104

Figure 5 - Common pin Structure SWx and IOx
Figure 5 illustrates the basic structure and control of the ports for switch detection.
The default configuration of all ports after power on or wake up is tristate. After the initialisation procedure the ports
will be configured by the MCU. The pull up or pull down current is provided by two central current sources I1 and I2.
The currents for switch control have to be applied sequentially by the multiplex switches S1x or S2x. If a low
impedance path to Ground is required (open drain buffer or matrix mode row connection), the local switch S3x has tobe used.
Because of the multiplex principle only two comparators are required to detect the port input voltage levels. For RF
interference as well as suppression of automotive disturbances the comparator path contains a debounce filter oftypically 2µs.
The multiplex switches S1, S2 as well as the local open drain buffer S3 are controlled by the registers S3H and S3L.

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6.1.2. Configuration Register Central Current Source
Status Register pull up/down input comparator – System protected port
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE02CSTATUS--

WAKEUP_
ERROR

INTERNAL_
WAKEUPLOCAL_
WAKEUP

BUS_
WAKEUP

SWIN_PU

SWIN_PD

WAKEUP_ERRORINTERNAL_WAKEUPLOCAL_WAKEUP
BUS_WAKEUPSWIN_PD
SWIN_PU

Will be set if during change to sleep mode a switch state change is detected
Wakeup event generated from the internal timer
Wakeup event generated from a wakeup configured SWx or IOx pin
Wakeup event generated from the LIN bus
Input comparator of central current source pull down
Input comparator of central current source pull up

Central current source configuration
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC01D

SW_CONFIG

-

-

-

-

IREF_EN

DIAG_S2

DIAG_S1-

IREF_EN
DIAG_S2
DIAG_S1

Switch IREF PIN on/off (0=off)
Configure central pull down current source to 10..20% of nominal value for switch diagnosis
Configure central pull up current source to 10..20% of nominal value for switch diagnosis

Central current source enable register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC01B

S2H

IO7_S2

IO6_S2

IO5_S2

IO4_S2IO3_S2IO2_S2

IO1_S2

IO0_S20xC01A

S1H

IO7_S1

IO6_S1

IO5_S1

IO4_S1

IO3_S1IO2_S1IO1_S1

IO0_S10xC017

S2L_H

-

-

-

-

-

-

SW9_S2

SW8_S20xC016

S2L_L

SW7_S2

SW6_S2

SW5_S2

SW4_S2

SW3_S2SW2_S2

SW1_S2

SW0_S20xC015

S1L_H

-

-

-

-

-

-

SW9_S1

SW8_S10xC014

S1L_L

SW7_S1

SW6_S1

SW5_S1

SW4_S1

SW3_S1

SW2_S1

SW1_S1

SW0_S1

IOx_S2
IOx_S1
SWx_S2
SWx_S1

Enable central pull down current source for IOx (S2) – See Figure 5
Enable central pull up current source for IOx (S2) – See Figure 5
Enable central pull down current source for SWx (S2) – See Figure 5
Enable central pull up current source for SWx (S2) – See Figure 5

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Datasheet

6.1.3. Configuration Register SWx
Open drain output configuration register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC019

S3L_H

-

-

-

-

-

-

SW9_S3

SW8_S30xC018

S3L_L

SW7_S3

SW6_S3

SW5_S3

SW4_S3SW3_S3SW2_S3

SW1_S3

SW0_S3

SWx_S3

Enables open drain transistor at SWx pin (S3) – See Figure 5

Input comparator register – System protected ports
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE02B

SW_IN_H

-

-

-

-

-

-

SW_IN9SW_IN80xE02A

SW_IN_L

SW_IN7

SW_IN6

SW_IN5

SW_IN4

SW_IN3

SW_IN2

SW_IN1

SW_IN0

SW_INxInput comparator of pin SWx

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Datasheet

6.1.4. Configuration Register IOx
Open drain output configuration register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC01C

S3H

IO7_S3IO6_S3IO5_S3IO4_S3IO3_S3IO2_S3

IO1_S3

IO0_S3

IOx_S3

Enables open drain transistor at IOx pin (S3) – See Figure 5

Input comparator register – System protected ports
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE029IO_IN

IO7_IN

IO6_IN

IO5_IN

IO4_IN

IO3_IN

IO2_IN

IO1_IN

IO0_IN

0xE026

IO_EN

IO7_EN

IO6_EN

IO5_EN

IO4_EN

IO3_ENIO2_EN

IO1_EN

IO0_ENIOx_INIOx_EN

Input comparator of pin IOx
Enables IOx input comparator

Interrupt register – System protected ports
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE027

IO_IRQ

IO7_IRQ

IO6_IRQ

IO5_IRQ

IO4_IRQ

IO3_IRQ

IO2_IRQ

IO1_IRQ

IO0_IRQ

0xE025IO_INT_ENF

IO7_INTF

IO6_INTF

IO5_INTF

IO4_INTF

IO3_INTF

IO2_INTF

IO1_INTF

IO0_INTF

0xE024

IO_INT_ENR

IO7_INTR

IO6_INTR

IO5_INTR IO4_INTR

IO3_INTR IO2_INTR

IO1_INTR

IO0_INTR

IOx_IRQ
IOx_INTF
IOx_INTRInterrupt source of external interrupt
Enables falling edge interrupt on IOx
Enables rising edge interrupt on IOx

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6.1.5. Switch current generation
The switch level detection is limited by the following criteria:
 Battery voltage range of 5…27V
 GND or VBAT shift < 0.1*Vs max.
 Applied current >7mA
 For switch matrix mode the voltage drop via the internal GND switch (S3) has to be lower than or equal to the
maximum GND shift voltage for a low side input switch
 Contact resistance of the switch up to 1KΩ
 Internal voltage drops ( On - resistance of multiplex switches, impedance of the current source, supply wiring
resistance) Failure diagnosis for switches placed outside
In order to meet these requirements, the switch current has to be a function of the battery voltage and must be
limited for battery voltages higher than 14V:

Figure 6 - Voltage dependency of the switch current
For normal battery operation voltages of 13..14V, a minimum current of >7mA can be guaranteed.
In case of higher battery voltages the current will be limited to <10mA.

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6.1.6. The switch detection thresholds
VS

LS – switch
MLX80104

Vbat 14V

Vbat 7V

Injection current (calibrated)

8mA

3.5mA

GND shift(0.1*Vbat)

1.4V

0.7V

Drop switch (1kΏ)

8V

3.5V

Drop S1(300Ώ)

2.4V

1.05V

Drop current source I1

1V

0.5V

Supply voltage Vs

13V

6V

Metal wire
resistance

Vdrop_I1
Vref_h

I1

Vin_h

COMP

Swin_PUON resistanceS1x

Vdrop_S1
S1x

Rswitch+Vin_hVdrop_sw

Rprot
Rleak

Switch closed: (maximum input low voltage)>500KO(1) Vin_h = Vgnd_shift + Vdrop_sw + Vdrop_S1(2) Vin_h < VS – Vdrop_I1 < Vref_h

Vgnd_shift
Chassis_GND

Switch open: (minimum input high voltage)

ECU_GND(3) Vs > Vin_h = I1 * Rleak > Vref_hFigure 7 - Voltage drops external LS switch

These conditions will be met by Vref_h = 0.9*VS

VS

MLX80104

Switch matrix
Vbat 14V

Vbat 7V

Metal wire
resistance

Vdrop_I1
Vref_hI1

Injection current (calibrated)

8mA

3.5mA

Drop S3(175Ώ)

1.4V

0.6V

Drop switch (1kΏ)

8V

3.5V

Drop S1(300Ώ)

2.4V

1.05V

Drop current source I1

1V

0.5V

Supply voltage Vs

13V

6V

Vin_h

COMP

Swin_PUON resistanceS1x

Vdrop_S1
S1x

Rswitch+Vin_hVdrop_sw

Rprot
Rleak
>500KO

Switch closed: (maximum input low voltage)(1) Vin_h = Vdrop_S3 + Vdrop_sw + Vdrop_S1(2) Vin_h < VS – Vdrop_I1 < Vref_hMatrix row
S3x
Vdrop_S3
ON –resistanceS3x

Switch open: (minimum input high voltage)
ECU_GND(3) Vs > Vin_h = I1 * Rleak > Vref_h
These conditions will be met by Vref_h = 0.9*VS
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Figure 8 - Voltage drops switch matrix
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Datasheet

Vbat_ECU

HS – switch
Vbat 14V

Vbat 7V

Injection current (calibrated)

8mA

3.5mA

Vbat shift(0.1*Vbat)

1.4V

0.7V

Vbat_
chassisVbat_shift

Rleak>500KO

Drop switch (1kΏ)

8V

3.5V

Drop S2(300Ώ)

2.4V

1.05V

RswitchDrop current source I2

1V

0.5V

Rprot

Supply voltage Vs

13V

6V

Vin_l

Vdrop_sw+

VS
S2x

MLX80104

Vdrop_S2

ON resistanceS1x

Switch closed: (minimum input high voltage)

Vin_l(1) Vbat-Vin_l = Vdrop_S2 + Vdrop_sw + Vbat_shift(2) Vbat-Vin_l < Vdrop_I2 > Vref_l

COMP

I2

Swin_PD

Vdrop_I2

Switch open: (maximum input low voltage)

Vref_lMetal wire
resistance(3) 0< Vbat-Vin_l = Vbat –(I2 * Rleak) < Vref_l
ECU_GND

These conditions will be met by Vref_l = 0.1*VS
Figure 9 - Voltage drops external HS switch

Parameters of input switches

Closed switch threshold resistance (including optional protection resistor)

Rin_max< 1175Ώ

Closed switch threshold resistance (including optional protection resistor
and maximum battery or GND shift)

Rin_max_ext< 1000Ώ

Protection resistor for external switches

Rprot>100 Ώ

Protection capacitor for external switches

Cprot

0…10nF

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6.1.7.

Switch diagnosis

If switches are connected via a wiring harness outside the ECU some failure states has to be considered:

Short circuit to battery
Short circuit to GND
Short circuit to other switches
Break of wires in the harness

For diagnosis the current sources I1 as well as I2 can be configured to 10..20% of the normal current value. Assuming
the same worst case conditions as used for the switch detection level calculation, the diagnosis current allows thedetection of up to 7.5kΩ resistance in the switch path.
Low side switch
Table 9 - Logic table for detection of LS input switches
Error
Condition

ClosedSwitchOpen
SwitchBrokenWire

Short tobattery

Short toGND

Short
to 2ndswitch

SWx_S1
IOx_S1

SWx_S2
IOx_S2

SWIN_PU

1

0

0

0

1

1/0

1

0

0

0

SWIN_PD

0

0

0

0

0

0

1

0

0

0

DIAG_S1 DIAG_S2

As shown in the Table 9, a closed switch cannot be differentiated from a short vs. GND by the logic level of SWIN_PU,
but if the value is stable after a certain number of cycles, a faulty closed or shorted switch can be identified.
A short to battery can be detected by using the complementary diagnosis current 10..20% * I2:Table 10 - Logic table for diagnosis of LS input switches short vs. battery
Error
Condition

ClosedSwitchOpen
SwitchBrokenWire

Short tobattery

Short toGND

Short
to 2ndswitch

SWx_S1
IOx_S1

SWx_S2
IOx_S2

SWIN_PU

0

0

0

0

0

0

0

1

0

1

SWIN_PD

0

0

0

1

0

1/0

0

1

0

1

DIAG_S1 DIAG_S2

If a switch Sx is shorted to another switch Sy, a diagnosis is possible by applying the injection current I1 to the firstswitch and a sequential scan of the other switches Sy with the diagnosis current 10..20% * I2:Table 11 - Logic table for diagnosis of all input switches short vs. other switches by I1
Error
Condition

No short

Short to2nd
Switch+ Shortto GND

Switch x Switch x Switch y Switch y+ Short to
SWx_S1/ SWx_S2/ SWy_S1/ SWy_S2/ DIAG_S1 DIAG_S2
Vbat
IOx_S1
IOx_S2 IOy_S1 IOy_S2

SWIN_PU

0

0

1

0

0

1

1

0

0

1

SWIN_PD

0

1

0

1

0

1

1

0

0

1

This diagnosis additionally allows the detection of double fault conditions (short to other switch pin & short to battery
or GND). For separation of double fault condition with short vs. battery the diagnosis scan has to be repeated by the
opposite current configuration applying the injection current I2 to the first switch and a sequential scan of the otherswitches Sy with the diagnosis current 10..20% * I1:
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Datasheet

Table 12 - Logic table for diagnosis of all input switches short vs. other switches by I2
Error
Condition

No short

Short to2nd
Switch+ Shortto GND+ Shortto VbatSwitch x
SWx_S1/
IOx_S1

Switch x
SWx_S2/
IOx_S2

Switch y
SWy_S1/
IOy_S1

SWIN_PU
SWIN_PD

0
0

1
0

1
0

0
1

0
0

1
1

1
1

Switch y
SWy_S2/ DIAG_S1 DIAG_S2
IOy_S2
0
0

1
1

0
0

The last possible fault condition of the wiring harness is a break(s) of wire(s).This fault cannot be detected by using thescan methods as described in the above tables.
By adding a resistor of 7.5kΩ±1% in parallel to the switch, an open switch can be differentiated from a switch break.
nd
For diagnosis the scan result has to be compared to a 2 scan with the diagnosis injection current 10..20% * I1:Table 13 - Logic table for break detection of LS input switches
Short to
SWx_S1/
2nd
IOx_S1switchError
Condition

Closed

Open

Break

Short to
Vbat

Short toGND

SWx_S2/
DIAG_S1 DIAG_S2
IOx_S2

SWIN_PU

1

1

0

0

1

1/0

1

0

1

0

SWIN_PD

0

0

0

0

0

0

1

0

1

0

High side switch
For the diagnosis of the HS – input switches the complementary configuration has to be applied:
Table 14 - Logic table for detection of HS input switches
Short to
SWx_S1/ SWx_S2/
2nd
DIAG_S1 DIAG_S2
IOx_S1
IOx_S2switchError
Condition

Closed

Open

Break

Short to
Vbat

Short to
GND

SWIN_PD

1

0

0

1

0

1/0

0

0

0

0

SWIN_PU

0

0

0

0

0

0

0

0

0

0

As shown in the Table 14, a closed switch cannot be differentiated from a short to battery by the logic level of
SWIN_PD, but if the value is stable after a certain number of cycles, a faulty closed or shorted switch can be identified.
A short to GND can be distinguished from an open switch by using the complementary diagnosis current 10..20% * I1:Table 15 - Logic table for diagnosis of HS input switches short vs. GND
Short to
SWx_S1/ SWx_S2/
2nd
DIAG_S1 DIAG_S2
IOx_S1
IOx_S2switchError
Condition

Closed

Open

Break

Short to
Vbat

Short to
GND

SWIN_PD

0

0

0

0

0

0

1

0

1

0

SWIN_PU

0

0

0

0

1

1/0

1

0

1

0

By adding a resistor of 7.5kΩ±1% in parallel to the switch, an open switch can be distinguished from a broken wire. Fornddiagnosis the scan result has to be compared to a 2 scan with the diagnosis injection current 10..20% * I2:

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Datasheet
Table 16 - Logic table for break detection of HS input switches
Error
Condition

Short to
SWx_S1/ SWx_S2/
2nd
DIAG_S1 DIAG_S2
IOx_S1 IOx_S2
switchClosed

Open

Break

Short to
Vbat

Short to
GND

SWIN_PD

1

1

0

0

1

1/0

0

1

0

1

SWIN_PU

0

0

0

0

0

0

0

1

0

1

The short circuits vs. other switch input pins are covered by the method described in Table 14 and Table 15.

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6.1.8. Switch Configuration in sleep mode
In case of a valid go to sleep condition, the following procedure must be initiated:All ports requesting a wake up capability will be connected in parallel by the closed switches S1x or S2x to theshared sleep comparators and the shared pull up/down resistors.



Any permanently closed pushbutton or switch as well as ports with short circuits to battery or GND have to
be excluded from the wake up capability, because a permanent current would be applied in sleep mode andno wake up edge detection would be possible (OR interconnection). This makes switch diagnosis mandatory
before GO TO SLEEP

Switches with parallel resistor for break diagnosis have to be excluded from the wake up capability becauseof a permanent current flow in sleep mode and an undefined shift of the wake up threshold.

After the GO TO SLEEP command any local wake up condition will be suppressed by a sleep counter in order
to insure stable conditions at any port and prevent an invalid wake up.
The status of S1x, S2x as well as S3x (matrix rows) will be stored with the rising edge of the GO TO SLEEP
command.



In case of a changed switch status after the GO TO SLEEP timeout period the system will wake up
immediately and a ‘wake up error flag’ will be set.



A local wake up will be detected after a change of a switch position(s) for longer than the specified wake up
filter time, the local wake up flag will be set.

This described procedure allows a change into power saving modes even in case of failures

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Datasheet

Vs

MLX80104
Vs

Pin
SW1

nSBY

SBY

I1

10K

Rswitch
+

ESD

Rprot

LS-switch

Vrefh
Sleep
COMP

SW_in

COM
P

Fallingedge
detect25µs
Wu_error

Vref_CMOS

S1x

EN_GND S3x

config’18x switch

Vbat

GoToSleepcounterPad
SW3

HS-switch
Rswitch

Vs

+

SBY
WU

18x switch
config’

Pin
SW2

Rprot

FF

Risingedge
detect

S2x
ESD
COM
P

SW_in

Vref_CMOS

Sleep
COMP

I2

10K

25µs

Vrefl

EN_GND S3x
nSBY

SBY

Figure 10 - Wake up detection for switch inputs
As shown in Table 17, the following sleep mode configurations are possible:
Table 17 - Sleep mode configuration overview (switch detection)
Mode

6.2

S1x

S2x

S3x

Comment

No wake up required

0

0

0

Port tristate

Wake up for LS switch

1

0

0

Internal wake up
current source to Vs

Wake up fur HS switch

0

1

0

Internal wake up
current source to
GND

Wake up matrix columns

1

0

0

Internal wake up
current source to Vs

Wake up matrix rows

0

0

1

Path to GND

Additional Operation Modes SWx Ports

Open drain output mode
The SWx pins can also be used as normal open drain outputs. This mode can be switched on via the configuration
register bits. In this mode the central current source (S1x and S3x) should not be applied to the open drain configuredpin.
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Because of the high voltage capability of the pin the current capability can be easy extended via an external pnptransistor.

S1x/S2x
Vs

Pin
SW_x

HV_clamp

ESD
1.25V
+/-2%
EN_GND

LS/
latch

COMP

SW_IN

S3x

SBY

MLX80104

Figure 11 - Structure of SWx pins

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Table 18 - Active mode configuration overview SWx pins
Register SW_Sxy

ModeReg. SW_CONFIG

Central current
source value

Input result

RemarkSWx_S1

SWx_S2

SWx_S3

DIAG_S1

DIAG_S2

I1

I2

Tristate

0

0

0

x

x

x

x

-

Central pullup current

1

0

0

0

X

100%

X

SWIN_PULow side switch
or matrix
columns

Central pulldown
current

0

1

0

x

0

x

100%

SWIN_PDHigh side switch

Matrix row
connection

0

0

1

x

x

x

x

SWIN_PU

Diagnosis 1

1/0

1/0

0

1

0

10..20%100%

SWIN_PU/
SWIN_PD

SwitchDiagnosis

Diagnosis 2

1/0

1/0

0

0

1

100%

10..20%

SWIN_PU/
SWIN_PD

SwitchDiagnosis

Digital Input

0

0

0

x

x

x

x

SW_InxOpen drain
output

0

0

1/0

x

x

x

x

SW_Inx

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6.3

Additional Operation Modes IOx Ports

Open drain output mode
The IOx pin can also be used as normal open drain outputs. This mode can be switched on via the configuration
register bits. In this mode the central current source (S1x and S3x) should not be applied to the open drain configured
pin.
Because of the high voltage capability of the pin the current capability can be easy extended via an external pnptransistor.
ADC input mode
Every IOx pin can also be used as analogue input signal for the integrated 10-bit ADC. Via the ADC_CTL register the IOx
pins can be selected to be used as ADC channel. See chapter 9 Analogue to digital converter for detailed description.
Interrupt capable input
In case external events should generate an interrupt the IOx pins can also be configured as an interrupt source. Theinterrupt sensitivity can be configured either for the falling or for the rising or for both edges. See chapter 10
Interrupts for a detailed description.
PWM Output
The eight available PWM channels can be applied to the corresponding IOx pin via the register PWM_AD. For outputof the PWM channels the pin must be configured in open drain configuration. See chapter 11 PWM Unit for a detailed
description.

IO_IN

S1x/S2x

VDDD

Vs

IO_WU

Pin
IO_x

HV_clamp

Level
shift

WU
filterboth edge
detect

ESD
25µs

COMP
1.25V

EN_GND

LS/
latch

S3x

LS/
latch

IO_WAKE_EN
SBY

SBY

ADC_EN
ADC_IN

HV_clamp

MLX80104
Figure 12 - Structure of IOx pins

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IOx_S1 1

IOx_S2 1

IOx_S3 2

IOx_EN 3

IOx_IRQ 4

ADCMUXx 5

PWMx_y 6

DIAG_S1 7

DIAG_S2 7

Table 19 - Active mode configuration overview IOx pins

Input
result

Tristate

0

0

0

0

x

0

0

x

x

-

Central pullup current

1

0

0

0

x

0

0

x

x

SWIN_PULow side switch
or matrix
columns

Central pull
down current

0

1

0

0

x

0

0

x

x

SWIN_PDHigh side switch

Matrix row
connection

0

0

1

0

x

0

0

x

x

SWIN_PU

Diagnosis 1

1/0

1/0

0

0

x

0

0

1

0

SWIN_PU/
SWIN_PD

Switchdiagnosis

Diagnosis 2

1/0

1/0

0

0

x

0

0

0

1

SWIN_PU/
SWIN_PD

Switchdiagnosis

Digital Input

0

0

0

1

0

0

0

x

x

IO_INxInterrupt
Input

0

0

0

1

1

0

0

x

x

IO_IRQx
IO_INxADC Input

0

0

0

0

x

1

0

x

x

ADC result

Open drain
output

0

0

1

1/0

x

0

0

x

x

IO_INxOpen drain
PWM Output

0

0

1

0

x

0

1

x

x

-

Remark1

Central current source enable register
Open drain output configuration register IOx
3
Input comparator register IOx
4
Interrupt register IOx
5
ADC channel selection register
6
PWM channel selection register
7
Central current source configuration register2

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6.4

The IREF pin

This pin provides a calibrated pull up current from the VS supply. This output current can be used for generation of an
external reference or supply voltage by using an external bipolar transistor.
An Application Note “External supply regulator using the IREF pin” is available at Softdist.

Vs
IREF_EN
VBat

LS/
latch

SBY

Vs

2mA +/- 5%

ESD

VB
VBE BZV55/
C5V6

PAD
IREF_OUT

MLX80104

V_ext +/- 1%

Figure 13 - Sample circuitry for IREF pin
For increasing the accuracy of the V_ext voltage at higher loads a zener diode can be placed at the base of thetransistor. V_ext = VB - VBE
Via the central current source diagnose register the IREF current can be switched on/off.
The voltage at this pin can be monitored via the internal ADC channel IREF

Central current source configuration register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC01E

SW_CONFIG

-

-

-

-

IREF_EN

DIAG_S2

DIAG_S1-

IREF_EN
DIAG_S2
DIAG_S1

Switch IREF PIN on/ff (0=off)
Configure central pull down current source to 10..20% of nominal value for switch diagnosis
Configure central pull up current source to 10..20% of nominal value for switch diagnosis

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7. Clock System
7.1

RC-Oscillator

The main oscillator is a 12MHz RC oscillator, which will be trimmed under software control according to the storedcalibration value in the EEPROM. The frequency can be trimmed from 8MHz up to 14MHz.
After Reset the RC oscillator is calibrated with the default reset value 0x00. The RC oscillator will be calibrated during
production process to 12MHz 5. The calibration value will be stored in the EEPROM and the software initialisation
routine must set this value in the system configuration register (See 16.2 Initialising the System) after start up.

7.2

Crystal Oscillator

In case an external 12MHz resonator or crystal is connected, it is possible to select this oscillator as system clock by
setting the XTAL_ON bit in the external clock source register. The loading capacitors are not a part of the IC and must
be added externally.
The start-up of the IC will always be done with the internal RC Oscillator. The XTAL oscillator can be switched on andoff via the SEL_XTAL register. The settling time has to be taken into account, before under software control the XTAL
oscillator will be selected as system clock for the IC.
External clock source register – system protected register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE02ESEL_XTAL

-

-

-

-

-

-

-

XTAL_ONXTAL_ON

Selection of external clock source
0 = Use internal RC oscillator (reset value)
1 = Use external clock source

The clock switching will be done fully synchronous and therefore the switching doesn’t generate spikes or
disturbances to the CPU.
The external XTAL oscillator must be connected to IO2 and IO5. In this case, the IO2 and IO5 must be configured astristate and can’t be used for any other function.

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8. Watchdog System
The MLX80104/5 is equipped with two different watchdog systems. One digital programmable window watchdog andone completely independent operating analogue Watchdog are available.

8.1

Analogue Watchdog

The analogue Watchdog is intended to fulfil application requirements where a completely independent clock sourcefrom the CPU is demanded for the watchdog system. Therefore an analogue system is used for this function.
This system is based on charging/discharging an external capacity. For definition of the watchdog time an external
capacitor must be connected to the pin AWD. Together with a fixed loading current source inside of the IC, theWatchdog time can be adjusted to any application needs.
The Watchdog will be started automatically after reset. Once this has been done after the power on, the Watchdog
cannot be stopped anymore. The Watchdog is stopped during sleep mode and is enabled again after every returnfrom wakeup or power on reset.
Watchdog acknowledge register – system protected register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE028IO_AWD

-

-

-

-

-

-

AWD_ACK-AWD_ACK

Writing “1” Acknowledge the analogue watchdog

Writing a “1” to the AWD_ACK bit loads the external capacitor to the upper threshold and restarts the unloading time.
This bit will be cleared automatically after charging of the watchdog capacity is done. Software cannot read back thevalue.

PORt WDt_R

AWD_IRQAWD_ACK
CWD_H
CWD_M
CWD_L

t WD_RAWD_RST
Figure 14 - Analogue watchdog behaviour

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8.1.1. Using the analogue WDOG
If the Watchdog has been started by power on reset, the capacitor voltage on AWD pin ramps up until the upper
voltage level is reached. After that, the current source of WDOG reverts to unload the capacitor. On half of theWatchdog time it generates precondition status information via an external watchdog interrupt request to the CPU.
This request can be used to store sensitive data into non-volatile memory and to continue without restarting WDOG.
It is not allowed to use this interrupt to trigger the watchdog!
The Watchdog must be acknowledged before the CWD_L voltage is reached, otherwise a system shutdown will be
performed. This system shutdown ends with a POR.

8.1.2. Timing definition
The watchdog time is defined by the external capacitor connected to the AWD pin. The value of this capacitor can becalculated as follows:
tWDt_R [ms] = WD[nF]
andtWD_R [ms] = 0.1*WD [nF]
Example:WD = 10nF -> tWDt_R =10ms und tWD_R = 1ms
The complete watchdog period will be for this example: 10ms+1ms=11ms

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8.2

Digital Window Watchdog

The Mulan digital watchdog has 3 possible behaviors and is running on a 12MHz clock. It is described in the next
chapters.
Important:
After reset the intelligent watchdog is disabled. Bootstrap code should enable it as needed.
Timer watchdog description
In this mode, the watchdog is a free-running up counter that can be reset by software. When it reaches a predefined
timeout value, a watchdog reset is generated (RST_WD_IT). Software must therefore periodically clear this counter toavoid a CPU reset. As interrupt RST_WD_IT is also generated at power on reset, reading bit WD_BOOT of register
CONTROL can be used to find out which source has generated it (WD_BOOT = 1 in case it is the watchdog).
Window watchdog description
In the window mode clearing the counter is only authorized within a time window starting at half the predefined
timeout value. In case a clear is done outside the window (e.g. before half the timeout delay), a RST_WD_IT interrupt
is generated (WD_BOOT = 1). At the end of the window an interrupt is generated (not a reset). That interrupt also
starts a new waiting sequence which is stopped when the software clears the free-running up counter. If the software
has not cleared the counter after a given time, a RST_WD_IT interrupt is generated.
Intelligent watchdog description
This watchdog operates in a completely different way. It supposes the software allocates for a given task a given
provision of time and a tag. This amount of time is programmable and can be changed. The tag can represent a stateof the software. Once this time is elapsed, it generates an interrupt (not a reset). The software must check if the newstate of the program is coherent with the tag saved, and then reload a new couple of time and tag. The interrupt
generated also starts a new waiting sequence that is cleared when the software updates the couple time and tag (i.e.
when the interrupt is serviced). If the software has not updated the couple time and tag after a given time, a
RST_WD_IT interrupt is generated.

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8.3

Watchdog Register

Watchdog Tag Register
Address

Name

0xC004

WD_TAG

WD_TAG[7:0]

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

WD_TAG[7:0]Tag value to be used for intelligent Watchdog mode

Watchdog Control Register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC003

WDCTRL

ERR

WND

MODE1

MODE0

-

-

DIV1

DIV0

Bit3

Bit2

Bit1

Bit0

ERR
WND
MODE[1:0]

DIV[1:0]

Watchdog access error (read only, clear on read)Window Watchdog Value (read only)
Definition of Watchdog behaviour
00
Disabled
01
Timer Watchdog
10
Window Watchdoog
11Intelligent Watchdog
Watchdoog clock divider, definition of watchdog clock (OSC=187kHz)
00
OSC/8
01
OSC/3210
OSC/12811
OSC/512Watchdog Timer Register
Address

Name

0xC002

WDT

WDT[7:0]

Bit7

Bit6

Bit5

Bit4

WDT[7:0]

Watchdog timeout value, function depends on selected mode

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9. Analogue to digital converter
9.1

General Description

The ADC10 is a 10-bit analogue-to-digital converter, which utilizes successive approximation technique with aninternal sample and hold circuit.
The pins IO0 … IO7 can be used as ADC input. In addition the voltage on pin IREF and VS can be monitored via ADC.
Please have a look to section 9.2 for information about the input divider.

MLX80104

ADC control register

ADC_CTL_L
ADC_CTL_H

VSReference voltage
VREFH 0.75V 1.5V 2.5V

0 .. 5V
IO0
ADC interrupt

ADC_INTADC result

ADC_IN_L
ADC_IN_H

10-Bit
ADC

MUX
IO7
IREF
VS

Figure 15 - ADC components
The reference voltage VREFH is based on the internal bandgap reference and is applied to the DAC after power on. In
accordance to the linear input voltage range of the analogue input pins the default value of VREFH is 2.5V. To improvethe maximum resolution of the measurement, the reference voltage can be adapted to VREFH=1.5V as well as 750mV.
The maximum theoretical resolution (1LSB) can be calculated by
VREFHmin / 1024 = 0.75V /1024 = 732V.

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9.2

Input divider

The following table illustrates the input divider on the pins, the possible maximal input voltage and resolution for thedifferent ADC reference voltages.
Ref 0.75V

Ref 1.5V

Ref 2.5V

Pin

DividerMax
input
voltage

Resolution

Max
input
voltage

Resolution

Max
input
voltage

Resolution

IO0..IO7

2

1.5V

732µV

3V

1.46mV

5V

2.44mV

IREF

4

3V

2.93mV

6V

5.86mV

10V

9.77mV

VS

14

10.5V

10.25mV

21V

20.51mV

35V

34.18mV

Table 20 - ADC Input divider

9.3

Accuracy of the reference

The maximum reference voltage VREFH is generated by an amplified bandgap voltage. This voltage is divided by aresistor divider with a dividing error better than 1% to generate 1.5V or 750mV as reference voltage. The value of thereference voltage can be selected by the ADC_CTL register.
The best accuracy can be calculated by:
VREFHmin +/- (MinStepsize / divider factor) = 750mV +/- 1mVThis value contains the gain and offset failure of the amplifier chain and the deviation of the resistor network.
The overall deviation of the output voltage is defined by the accuracy at room temperature, the temperature
gradients of the bandgap reference and the offset voltage of the amplifier (approximately +/- 1.5% from –40…150C.) This results in a total deviation of
VREFHmin +/- (minStepsize + (1.5%*VREFHmax)) / divider factor = 750mV +/- 16mV
The absolute error of the measured input voltage additionally depends on the distance of the maximum input
voltage to VREFHmax.
Example:VREFH = 750mV
Vin_max = 100mV (e.g. shunt measurement)
Maximum absolute error: Vin_err_max = ((VREFH / Vin_max) x VREFHTol_max ) +/- 1LSB = +/- 2.5mV

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9.4

ADC Register

ADC result register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

0xC00B

ADC_IN_H

-

-

-

-

-

-

ADC_R [9..8]0xC00A

ADC_IN_L

Bit2

Bit1

ADC_R

Bit0

ADC_R [7..0]

Result of ADC conversion

ADC selection register
Address

Name

0xC009ADC_CTL_H

VREF
ADCMUX

Bit7

Bit6

Bit5

VREF

Bit4

Bit3

-

ADC reference voltage selection
000b
off
010b
1.5V
001b
2.5V
100b
750V
ADC channel selection
0000b off
0001b IO0, divided by 2, 3µs sampling time
0010b IO1, divided by 2, 3µs sampling time0011b IO2, divided by 2, 3µs sampling time
0100b IO3, divided by 2, 3µs sampling time

0101b
0110b
0111b
1000b
1001b
1010b

Bit0

ADCMUX

IO4, divided by 2, 3µs sampling time
IO5, divided by 2, 3µs sampling time
IO6, divided by 2, 3µs sampling time
IO7, divided by 2, 3µs sampling timeVs, divided by 14, 10µs sampling time,
500mV error, Switched off during standby
IREF, voltage at IREF pin, divided by 4,
3µs sampling time

ADC configuration register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC008ADC_CTL_L

BUSY

-

-

-

-

-

FAST

START

START
FAST
BUSY

If set it starts the ADC conversion
Selection of conversion clock0
slow clock - conversion time 10µs
1fast clock – conversion time 5µs
ADC conversion in progress

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10. Interrupts
Table 21 - shows all available interrupts in the MLX80104/5.
Column “Pos” represents the interrupt input position in the interrupt controller.
Column “Abs” represents the absolute priority of the input.
Column “Rel” represents the relative priority for inputs having an identical absolute priority.
Column “type” defines which instruction will be issued by the interrupt controller in case of interrupt.
Priority
Description
Pos Abs Rel
Reset + Watchdogs Reset000
Stack error
101
Protection error202Invalid address303Program error
4
04
Exchange request
5
1
0
Task reset
6
1
1
Watchdog attention
7
1
2
Mutex
8
2
0
Signal, Handshake, Event, [Mutex]
9
5
0
Timer
10 3-6 0
ADC end of conversion
11 3-6 1
End of EEPROM Write/Erase
12 3-6 2
Pin change interrupt IOx
13 3-6 3External Watchdog interrupt
14 3-6 4
Software interrupt
15 70
Notes:
1: Abort current instruction
2: Abort current instruction ►Return is NOT possible
3: No disable possible
4: Priority 0 can only be reached in system mode
5: For conformance test

Type
Jump
Jump
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call

Notes
1,3,4
1,3,4
2,3,4
2,3,4
2,3,4
3,5
3

PRIO

PRIO[1:0]
PRIO[3:2]
PRIO[5:4]
PRIO[7:6]
PRIO[9:8]

Ports
MASK

PEND

MASK[0]MASK[1]
MASK[2]
MASK[3]
MASK[4]
MASK[5]
MASK[6]
MASK[7]
MASK[8]
MASK[9]MASK[10]

PEND[0]PEND[1]
PEND[2]
PEND[3]
PEND[4]
PEND[5]
PEND[6]
PEND[7]
PEND[8]
PEND[9]PEND[10]

Table 21 - Interrupt inputs

Reminder:The highest priority is 0 and the lowest is 7.
The absolute priority is compared to Mlx16 priority to trigger an interrupt
The relative priority is used by interrupt controller to decide between identical absolute priority interrupts fired at
the same time: Lowest is issued first.
Note:
The level 0 of priority is not reachable in user mode. When Mlx16-8 sets priority to 0 in user mode, it is interpreted
as priority 1 by the interrupt controller.

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10.1 Interrupt vectors
Table 22 - Interrupt vectors shows the interrupt vectors table as well as the type of interrupt generated (callor jump). They all use Far Page 0 (e.g. top of the ROM). See example of Fp0 in Table 6.
Priority
Pos Abs Rel
0
0
0
1
0
1
2
0
2
3
0
3
4
0
4
5
1
0
6
1
1
7
1
2
8
2
0
9
5
0
10 3-6 0
11 3-6 1
12 3-6 2
13 3-6 3
14 3-6 415
70

Description
Reset + Watchdogs Reset
Stack error
Protection error
Invalid address
Program error
Exchange request
Task reset
Watchdog attention
Mutex
Signal, Handshake, Event, [Mutex]
Timer
ADC end of conversion
End of EEPROM Write/Erase
Pin change interrupt
External watchdog interrupt
Software interrupt

Type
Jump
Jump
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call
Call

Interrupt vector
Addr Name
Fp0:80 RST_WD_IT
Fp0:88 STACK_IT
Fp0:90 PROT_ERR_IT
Fp0:98 INV_AD_IT
Fp0:A0 PROG_ERR_IT
Fp0:A8 EXCHANGE_IT
Fp0:B0 TASK_RST_IT
Fp0:B8 WD_ATT_IT
Fp0:C0 M4_MUTEX_IT
Fp0:C8 M4_SHE_IT
Fp0:D0 TIMER_IT
Fp0:D8 ADC_IT
Fp0:E0 EE_IT
Fp0:E8 EXT0_IT
Fp0:F0 EXT1_IT
Fp0:F8 SOFT_IT

Table 22 - Interrupt vectors

10.2 Priority port
The port PRIO defines the priority level of 4 interrupt inputs. It is divided in 4 be fields of 2 bits. The
correspondence between each field value is shown on Table 23.
Priority Absolute
field
Priority
00
3
01
4
10
5
11
6
Table 23 - PRIO port encoding

10.3 Interrupt mask and pending ports
A mask bit at 0 (value at reset) masks an interrupt input, while a mask bit at 1 makes it visible to the Mlx16.
Note that with a mask at 0 it is still possible to check if the interrupt input is set by reading the corresponding
pending bit.
The interrupt pending bit is set when the interrupt occurs, the Mlx16 cannot write into this port to simulate aninterrupt. Writing in this port is used for clearing the pending bit, which discards the corresponding interrupt.
As writing a 1 in any pending bit clears it while writing a 0 does nothing, you can clear one or more interrupt
bits in one shot, by example writing 0x0001 in PEND port clear the interrupt 5, while writing 0x7FF clear all
interrupts from 5 to 15.

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Pending interrupt register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE009PEND_H

-

-

-

-

-

SOFT_IT

EXT1_IT

EXT0_IT

0xE008

PEND_L

EE_IT

ADC_IT

TIMER_IT

M4_SHE_IT

M4_MUTEX_IT

WD_ATT_IT

TASK_RST_ EXCHANGE_IT
IT

For abbreviation please see Table 22.
Interrupt mask register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE007

MASK_H

-

-

-

-

-

SOFT_IT

EXT1_IT

EXT0_IT

0xE006

MASK_L

EE_IT

ADC_IT

TIMER_IT

M4_SHE_IT

M4_MUTEX_IT

WD_ATT_IT

TASK_RST_ EXCHANGE_IT
IT

For abbreviation please see Table 22.
Interrupt priority register
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xE005

PRIO_H

-

-

-

-

-

-

EXT1[1]

EXT1[0]0xE004

PRIO_L

EXT0[1]

EXT0[0]

EE[1]

EE[0]

ADC[1]

ADC[0]

TMR[1]

TMR[0]

Further information can be found in Table 21.
EXT1[1:0]
Priority of external watchdog interrupt
EXT0[7:0]
Priority of pin change interrupt
EE[1:0]Priority of end of EEPROM Write/Erase interrupt
ADC[1:0]
Priority of ADC end of conversion interrupt
TMR[1:0]
Priority of Timer interrupt

10.4 High level system interrupts
10.4.1. Reset interrupt and watchdogs
This interrupt is generated at power on reset or if the intelligent watchdog asks for a reset. Take care that thepriority is not reset in the Mlx16, so this interrupt routine must start with instruction “MOV UPR, #0”.

10.4.2. Stack error
A stack error occurs when the Mlx16 uses the stack pointer to access an invalid or an unauthorized area. No
protection error or invalid address interrupt is generated. Obviously this interrupt uses a jump and does notpush the program counter into the stack.

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10.4.3. Exception error
There are 3 interrupts due to software errors on the Mlx16: a protection error, an invalid address or aprogram error. These interrupts are at level 0, therefore you cannot return to the interrupted program. The
program counter value pushed on the stack can only be used for debugging purpose. The device reaction
after this failure condition must be done in the ISR and depends on the application requirements. It is
possible to release a RESET, switch to sleep mode or program and endless loop to keep stable behaviour ofthe device.

10.4.4. Protection error
A protection error interrupt happens when the Mlx16 attempts an unauthorized access or to clear the user bit(Mlx16 M register). Here is an exhaustive list of possible causes: Write in user mode in the EEPROM.
 Access to EEPROM while it is busy (EE_BUSY=1).
 Write in port EEPROM while it is busy (EE_BUSY=1).
 Write in system mode in EEPROM while EN_EEPROM_WE is 0
 ADC conversion request while ADC is busy (ADC_BUSY=1)
 Write in ANA_OUTx ports while corresponding OUTx_WE bit of port CONTROL is 0.
 Write in the Mlx4 RAM private area.
 Write in user mode into a system port.
 Access error in the Intelligent Watchdog
 Clear the user bit (try to enter system mode) not after a jump or call far page.

10.4.5. Invalid address
An invalid address interrupt occurs when the Mlx16 does an invalid memory access. Here is an exhaustive
list of possible causes:
 Read, write or fetch a word at an odd address Read, write or fetch into an unused area
 Write a byte or a bit in EEPROM
 Write a bit in a digital port supporting only word or byte.
 Fetch into port area

10.4.6. Program error
A program error occurs when the Mlx16 tries to execute an invalid Mlx16 instruction. Typically, it means thatMlx16 has an invalid value in its program counter (PC).

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10.5 Debugger interrupt
This interrupt is intended to be used together with the Emulator.

10.6 Pin change Interrupt
This interrupt will be used to react on change pin IOx status. The edge sensitivity can be programmed in theinterrupt register (See 6.1.4 Configuration Register IOx). For the interrupt generation, the IOx will be
debounced with 3us. After the debouncing the interrupt will be generated and the interrupt request is stored
for every channel in the IRQ register.

10.7 External Watchdog interrupt
This interrupt is requested if the analogue watchdog has reached half of the Watchdog time period. See chapter 8
Watchdog System for details.

10.8 Software interrupt
It is possible to trigger a low priority interrupt by software setting bit SWI of port SWI to 1 the port bit isautomatically reset after one clock period, so it will always be re-read as a 0.

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11. PWM Unit
11.1 General
There are 8 PWM channels available. They share a common 8 bits free running counter with an input clock being
either a 750kHz clock or a 12MHz divided by a programmable divider from 1 to 64. The duty cycle for each PWM
channel can be set separately via PWM data register. The available PWM channels can be output to an IOx pin in low
side configuration. The selection must be done via the PWM_AD register.
To calculate the correct initialisation value for the PWM control register Equation 1 to Equation 4 are valid.
Additionally, in Table 24 you will find all possible PWM frequencies and the corresponding parameters for the PWM
control register.
Every IOx pin has its own PWM duty cycle register. To address this register 1st the channel must be selected via PWM
channel register (0xC011). After this selection the duty cycle can be written to the PWM duty cycle register (0xC012).
After this procedure, the programmed cycle will be output on IOx pin if the pin is configured as open drain output and
the PWM block is enabled (Bit PWM_EN in the PWM control register 0xC010).
Because the PWM is running with the CPU frequency, the accuracy is better than ±5% of the nominal PWM frequency.

11.2 Block Diagram
750 k Hz
Programmableprescalerby 1 to 64

1 2 MHzPWM _ FSB

PWM _ EN1

8 bitscounter

PWM _ DIV

1

6

Zero

Port PWM _ CFG

8
Load

8

8

>
IO0

Duty cycle
IO0

3
Port
PWM_ADPort
PWM_DATA

64 bits
Buffer

...

8

>

8
Duty cycle
IO7

8

>
IO7

PWM _ EN

Figure 16 - PWM unit

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11.3 PWM frequency calculation
Depending on the needed PWM frequency you have to choose the right equation. In case the frequency is in therange of 45Hz to 2.9kHz, Equation 3 is valid. And in case the frequency is in the range of 0.72kHz to 46kHz, Equation 4
is the right one.

FPWM kHz 

FPWM MHz 

750kHzPWM _ DIV  1 256

Equation 1 - PWM frequency for PWM_FSB=0

PWM _ DIV 

12MHz
PWM _ DIV  1 256

Equation 2 - PWM frequency for PWM_FSB=1750kHz1
FPWM kHz 256PWM _ DIV 

Equation 3 - Parameter PWM_DIV for frequencies in therange of 45.1 .. 2929.7Hz (PWM_FSB=0)

12MHz
1
FPWM MHz 256Equation 4 - Parameter PWM_DIV for frequencies in therange of 721.2 .. 46875Hz (PWM_FSB=1)

11.4 PWM Control Register
PWM channel selection
Address

Name

Bit7

Bit6

Bit5

Bit4

0xC011

PWM_AD

-

-

-

-

Bit5

Bit4

PWMSEL

000b
001b
010b
011b
100b
101b
110b
111b

Bit3

Bit2

Bit1

Bit0

PWMSEL

Address duty cycle register for IO0
Address duty cycle register for IO1Address duty cycle register for IO2
Address duty cycle register for IO3
Address duty cycle register for IO4Address duty cycle register for IO5
Address duty cycle register for IO6
Address duty cycle register for IO7

Duty cycle register
Address

Name

0xC012

PWM_DATA_WRITEPWM_DATA_WRITE

0xC013

PWM_DATA_READ

PWM_DATA_READ

PWM_DATA_WRITE
PWM_DATA_READ

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Bit7

Bit6

Bit3

Bit2

Bit1

Bit0

8-bit duty cycle value for selected PWM channel (for writing new duty cycle value)
For reading the current duty cycle

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PWM control register
Address

Name

0xC010PWM_CTL

PWM_ENPWM_FSBPWM_DIV

Bit7

Bit6

Bit5

PWM_EN PWM_FSB

Bit4

Bit3

Bit2

Bit1

Bit0

PWM_DIV

Enable/Disable PWM generation
1 = Enable
0 = Disable
Selection between input clock of 750kHz or 12MHz
0 = 750kHz
1 = 12MHz
Programmable pre-divider 1 to 64

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11.5 Available PWM Frequencies
Following PWM frequencies are configurable via the PWM Control Register PWM_CTL on page 58.
PWM
Frequency
in Hz

PWM_CTL
[5:0]

FSB

DIV

PWM
Frequency
in Hz

PWM_CTL
[5:0]

FSB

DIV

PWM
Frequency
in Hz

PWM_CTL
[5:0]

FSB

DIV

45.8

0x3F

0

63

139.5

0x14

0

20

1171.9

0x28

1

39

46.5

0x3E

0

62

146.5

0x13

0

19

1201.9

0x27

1

38

47.3

0x3D

0

61

154.2

0x12

0

18

1233.6

0x26

1

37

48.0

0x3C

0

60

162.8

0x11

0

17

1266.9

0x25

1

36

48.8

0x3B

0

59

172.3

0x10

0

16

1302.1

0x24

1

35

49.7

0x3A

0

58

183.1

0x0F

0

15

1339.3

0x23

1

34

50.5

0x39

0

57

195.3

0x0E

0

14

1378.7

0x22

1

33

51.4

0x38

0

56

209.3

0x0D

0

13

1420.5

0x21

1

32

52.3

0x37

0

55

225.4

0x0C

0

12

1464.8

0x01

0

1

53.3

0x36

0

54

244.1

0x0B

0

11

1464.8

0x20

1

31

54.3

0x35

0

53

266.3

0x0A

0

10

1512.1

0x1F

1

30

55.3

0x34

0

52

293.0

0x09

0

9

1562.5

0x1E

1

29

56.3

0x33

0

51

325.5

0x08

0

8

1616.4

0x1D

1

28

57.4

0x32

0

50

366.2

0x07

0

7

1674.1

0x1C

1

27

58.6

0x31

0

49

418.5

0x06

0

6

1736.1

0x1B

1

26

59.8

0x30

0

48

488.3

0x05

0

5

1802.9

0x1A

1

25

61.0

0x2F

0

47

585.9

0x04

0

4

1875.0

0x19

1

24

62.3

0x2E

0

46

732.4

0x03

0

3

1953.1

0x18

1

23

63.7

0x2D

0

45

732.4

0x40

1

63

2038.0

0x17

1

22

65.1

0x2C

0

44

744.0

0x3F

1

62

2130.7

0x16

1

21

66.6

0x2B

0

43

756.0

0x3E

1

61

2232.1

0x15

1

20

68.1

0x2A

0

42

768.4

0x3D

1

60

2343.8

0x14

1

19

69.8

0x29

0

41

781.3

0x3C

1

59

2467.1

0x13

1

18

71.5

0x28

0

40

794.5

0x3B

1

58

2604.2

0x12

1

17

73.2

0x27

0

39

808.2

0x3A

1

57

2757.4

0x11

1

16

75.1

0x26

0

38

822.4

0x39

1

56

2929.7

0x00

0

0

77.1

0x25

0

37

837.1

0x38

1

55

2929.7

0x10

1

15

79.2

0x24

0

36

852.3

0x37

1

54

3125.0

0x0F

1

14

81.4

0x23

0

35

868.1

0x36

1

53

3348.2

0x0E

1

13

83.7

0x22

0

34

884.4

0x35

1

52

3605.8

0x0D

1

12

86.2

0x21

0

33

901.4

0x34

1

51

3906.3

0x0C

1

11

88.8

0x20

0

32

919.1

0x33

1

50

4261.4

0x0B

1

10

91.6

0x1F

0

31

937.5

0x32

1

49

4687.5

0x0A

1

9

94.5

0x1E

0

30

956.6

0x31

1

48

5208.3

0x09

1

8

97.7

0x1D

0

29

976.6

0x02

0

2

5859.4

0x08

1

7

101.0

0x1C

0

28

976.6

0x30

1

47

6696.4

0x07

1

6

104.6

0x1B

0

27

997.3

0x2F

1

46

7812.5

0x06

1

5

108.5

0x1A

0

26

1019.0

0x2E

1

45

9375.0

0x05

1

4

112.7

0x19

0

25

1041.7

0x2D

1

44

11718.8

0x04

1

3

117.2

0x18

0

24

1065.3

0x2C

1

43

15625.0

0x03

1

2

122.1

0x17

0

23

1090.1

0x2B

1

42

23437.5

0x02

1

1

127.4
133.2

0x16
0x15

0
0

22
21

1116.11143.3

0x2A
0x29

1
1

41
40

46875.0

0x01

1

0

Table 24 - Configurable PWM Frequencies
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12. Timer
The timing generation principle is shown on Figure 17.

12MHz

Div by 16

Programmable
Divider
1 to 32767

750kHzTIMER_ITInterrupt

1
15

TMR Register

Figure 17 - Block Diagram of Timer

A 15 bits free running counter clocked by 750kHz is available to generate TIMER_IT interrupt at a rate varying from
1.33µs (TIMER [14:0] = 0) to 43.689ms (TIMER [14:0] = 32767). The timer is made of a down counting loadable binary
counter. It is enabled by TMR_EN (bit 15) of TMR register. Once enabled each time it reaches 0x0000; it is reloaded by
the value of TMR register TMR [14:0] and generates a TIMER_IT interrupt. Reading register TMR reads the current
value of the counter when TMR_EN = 1 or an unknown value when TMR_EN = 0.
Because the timer is running with the CPU frequency, the accuracy is better than ±5% of the nominal value.
Timer Register
Address

Name

Bit7

0xC007

TIMER_H

TMR_EN

0xC006

TIMER_L

TMR_EN
TMR

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

TMR [14:8]
TMR[7:0]

Enable/Disable Timer
1 = Enable
0 = Disable
15-bit Timer value

12.1 Timer Calculation
The TMR value for the TIMER register can be calculated with Equation 5, where Timer_Period is the time between thetimer interrupts in µs.

TMR14 : 0 

Timer_Period μs 12MHz
16
Equation 5 - Calculation of the TMR parameter

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13. LIN Interface
13.1 The Concept
The LIN protocol is implemented on a MULAN core on the MLX4 part. The complete MLX16 part is free for theapplication. With this dual core architecture the bus communication is decoupled from the application. The complete
LIN driver running on the MLX4 is part of the software development system and will be supported by Melexis. The
communication between both CPUs is done via an API. This API uses the common RAM area for data exchange. The
application task (running on MLX16) transmits all necessary LIN configuration data via the API to the LIN task (runningon MLX4) during the initialization process. Further information can be found in the document “MelexCM LIN Firmware
API - Programmer’s Reference Manual”.

Supervisor

Task 1

Task 0LIN SBIF

Application
softwareFault
confinement

Bus failuremanagement

Data Link Layer

Api

Mlx4- Dual

Inter-task port of the Mlx4

Systemsynchronization

Linsoftware

Timer(Compare/Capture)Bit levelbus
interface(digital)

Logical Link Layer
Acceptance filtering
Recovery Management
Message validation
Time- base synchronozation
Medium Acces Control
Data Encapsulation/Decapsul.
Error detection/Signaling
Serialization/De serialization

OSI Model

Physical Layer
Bit timing
Bit synchronization
Line driver/receiver

Bus interface

Figure 18 - LIN OSI-Reference model

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13.2 LIN Physical Layer
The MLX80104/5 contains an integrated physical layer for applications of low speed vehicle serial data network
communication using the Local Interconnect Network (LIN) protocol. The device is designed in accordance to thephysical layer definition of the LIN Protocol Specification Package 2.x and the SAE J2602 standard. The corresponding
baudrate and slew rate can be set via API commands.
The sleep mode capability allows a shutdown of the whole application. The included wake-up function detects
incoming dominant bus messages and wakes up the IC.
Because of the good symmetry parameter of the transceiver the communication with RC based synchronization
accuracy is possible under all worst case conditions in Vbat - or Ground shift, even in case of recessive bus voltages
down to 5V.
RxD debounce
The RxD debouncing circuit and the integrated low pass filter in the receiver path prevent RxD spikes in case of RFinterferences and schaffner pulses to guarantee a correct sampling of the master request.
TxD timeout
A special feature is the TxD timeout. In case of a faulty blocked TxD (MLX or LIN controller crash) the Bus output isswitched off automatically after the specified TxD timeout reaction time to prevent a dominant bus. The transmission
is continued by next TxD L to H transition without delay.

Undervoltage lockout
An undervoltage lockout comparator detects an unspecified decrease of the regulated supply voltage VAUX. Thismeasurement covers both, unspecified overload on VAUX and unspecified decrease of VS. It’s an additional factor ofsafety against undefined bus behaviour. To prevent a transmission interrupt due to Schaffner or RF modulation adebounce filter is used for spike suppression.

t < trec_deb

t < trec_deb

VLINx

t
tREC_PDF
tREC_PDR
VRxDx
50%

t

Figure 19 - Receiver debouncing & propagation delay
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Duty cycle calculation LIN 2.x
With the timing parameters shown in the picture below two duty cycles , based on trec(min) and trec(max) can becalculated as follows : tBit =50µs D1 = trec(min) / (2 x tBit)
D2 = trec(max) / (2 x tBit)

Table 25 - Duty cycle measurement and calculation in accordance to LIN physical layer specification 2.x for baud rates
up to 20Kbps

Duty cycle calculation J2602:
With the timing parameters shown in the table below two duty cycles , based on trec(min) and trec(max) can be calculated
as follows : tBit =96µs
D3 = trec(min) / (2 x tBit)
D4 = trec(max) / (2 x tBit)

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Table 26 - Duty cycle measurement and calculation in accordance to LIN physical layer specification 2.x for baud ratesof 10.4Kbps or below

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14. Sleep Mode and Wake up System
14.1 Entering Sleep Mode by API
A valid MLX80104/5 sleep command is used to switch into the most power saving mode under software control. In
this mode all unnecessary function blocks are switched off to save the maximum possible current, keeping only someminimum parts alive, which will watch events or conditions for possible wakeup requests.
To enter Sleep Mode the following sequence has to be performed: Application software first takes care of saving any
needed data into non-volatile memory, because Sleep Mode will force the system to switch off power supplies. Anyregister content of the CPU, the content of volatile memories, etc. will be lost.
Finally a HALTED command (set “EN_HALTED” bit) has to be performed, which gives a signal to enter the sleep mode.
Make sure that MLX4 is already halted otherwise the system cannot finish the power down procedure. This request
starts the system shutdown process. This has to be the last action from the CPU. After sending this request the CPU
has to stay in an infinite loop, waiting for system shutdown. This shutdown will be performed, even if incoming
wakeup conditions should occur – which will be ignored as long as the system is not in sleep mode. This ensures thatthe system first shuts down and clears all CPU registers completely, to secure a defined restart into Power On state.
By receiving a HALTED Signal from the CPU the following sequence is performed from the MLX80104/5 itself:
 Analogue Watchdog is disabled All registers not required in sleep mode are cleared and contain their reset values.
 All registers containing configuration needed in sleep mode (i.e. enable bits for Wake Up sources etc.) keep
their values
 The internal auxiliary supply is switched on to supply the wake-up comparators as well as the wake-up enableregister
Any trimming value gets lost and must be restored within the software initialisation routine after wake-up.
The digital supply as well as the analogue supply is switched off.
In Sleep Mode all IOs will be switched to tri-state (high-impedance).

14.2 Wake Up System
There are three possible ways to wake-up the MLX80104/5:

14.2.1. LIN Bus
The LIN standby receiver detects any changing edge on the bus exceeding the wake up debouncing time of minimum
50us. The integrated filter prevents a wake up via EMC interferences.

14.2.2. Local Wake-up
The second way to wake up the slave node is a local wake up condition. The input comparators detect any changing
edge exceeding the wake up thresholds and the local wake up debouncing time of minimum 20us.
Every wake up detection set a wake up flag, the bandgap reference and the voltage regulators are switched on andthe power on procedure starts. The information about a local wake up is stored in the status register.

14.2.3. Internal Wake-up
The third way to wake-up is the configurable internal wake timer. After a configured time the MLX80104/5 is switchedon. This mode is foreseen for observing applications with a very slow current consumption in user mode.
If local wake up capabilities are used, the leakage currents of the connected switches will increase the current
consumption of the whole slave node.
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15. Thermal Shutdown
A thermal overload of the MLX80104/5 may occur due to an increased power dissipation and high ambient
temperature. Causes for the unspecific power dissipation may be:-

Short LIN to Vbat/Vs
Shorted load at IO Pins
IO loads too highIn case the chip temperature exceeds the specified limit, the THERMAL bit in the XIN register (see below) will be set to
1. This bit can be used for triggering the software to find the reason of the thermal problem. This can be done bydisable SWx/IOx pins to check if the external circuitry causes the problem.
Thermal Error Bit
Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0xC005

XIN

-

-

-

-

-

-

-

THERMAL

THERMAL

Thermal error bit
0 = no thermal error
1 = Thermal error

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16. System behaviour
16.1 Reset behaviour
After connecting power to the VS pin the system will start operation. The on-chip supplies start after the definedminimum voltage level is reached on the VS pin. The system is in the RESET state as long as the supply voltage is below
its minimum voltage level.

VS
VAUX
VDDA
VDDD

VAUX_PORN
VDDD_PORNVDDA_PORNRESETN

Figure 20 - Reset behaviour

The reset signal keeps the complete IC in reset state if the supply voltage is below the specified value. After reaching
the minimum voltage level of the supply, the reset signal becomes inactive and the initialisation sequence is started.
The RC-Oscillator is switched on with the lowest frequency and the CPU starts the initialisation.

16.2 Initialising the System
For correct system start-up some registers in the IO part must be restored after every RESET or WAKEUP by writing
the values from reserved EEPROM addresses. These trim values have been stored during chip test. Overwriting these
EEPROM memory addresses is prohibited otherwise the data for application needs is lost and the correct IC behaviour
cannot be guaranteed in the specified range.
Start-up steps:
1.
Trim the bandgap to the expected value (3bit),2.
Trim the RC to the expected frequency (7bit),3.
Trim the internal biasing to the expected current,
4.
Trim the ADC reference to the expected voltage for every input range (7bit),5.
Trim the switch current (4bit),
6.
Set the EEPROM delay time (4bit).

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System configuration register
Address

Name

Bit7

0xE021

ANA_OUTC_H

reserved

ADC-REF *0xE020ANA_OUTC_L EN_XTAL

RC_CALI *0xE01F

ANA_OUTB_H

CU_TRIM *0xE01EANA_OUTB_L

reserved

SW_TRIM *0xE01D

ANA_OUTA_H

EE_DELAY *reserved

0xE01CANA_OUTA_L

EE_DELAY
INT_WAKE

BG_TRIM
CU_TRIM
SW_TRIM
ADC_REF
RC-CALI
EN_XTAL

Bit6

Bit5

Bit4

Bit3

reserved

reserved

Bit2

Bit1

Bit0

BG_TRIM *INT_WAKE

Set the EEPROM programming time
Control of internal timer controlled wake up
00
off
01
wake up after 0.5s
02
wake up after 1s
03
wake up after 2s
Adjust bandgap
Adjust current references
Adjust switch current source
Adjust reference voltage of ADC VREFH
RC-Oscillator calibration
Enable use of external Quartz or Resonator as clock source for the MCU
0internal RC-Clock is used1
Switch from RC to external

Attention: All values marked with “*” are trimming values for analogue IC parameter. Those values must be kept after initialisation of
the IC! Otherwise the IC will not operate correctly.

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17. ROM Patches
In order to rapidly correct minor bugs in ROM a specific hardware has been added to replace up to four ROM spaces
by EEPROM code. The principle is shown on Figure 21.
Address
16={ 0, AD_CMP0}E

PATCH0_A={ 0, AD_CMP1}
E

PATCH1_A==

AD_CMP2

DecoderCPUs{ 0, AD_CMP3}
E

PATCH3_A

AD_CMP1{ 0, AD_CMP1}
E

PATCH2_A

AD_CMP0

AD_CMP3

Patch ports
ROM

DATA ROM
EEPROM / RAM

PATCH0_I

INSTR0 (*)

PATCH1_I

INSTR1 (*)

PATCH2_I

INSTR2 (*)

PATCH3_I

INSTR3 (*)

MUX

Data

(*): JUMP FPx instructions

Figure 21 - Patch hardware

17.1 Principle of operation
There are 4 possible patch start addresses PATCHx_A (x=0..3) available. In case the program counter (PC) of the CPU
points to an address, which is equal to one of the PATCHx_A ports (and the patch is enabled) the PC will be redirectedto the address defined by the PATCHx_I port.
The patch instruction can be located in the EEPROM or the RAM.
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17.2 Patch start address
Initially the patches are disabled (Bit E=0). The Mlx16 ROM startup code must be written in a way that an EEPROM
byte decides if patches must be applied. If yes, patch ports must be loaded. This operation must be done prior to any
other to allow patch of any code.
PATCHi_A
At reset

15
E
0

14

13

12

11

10

x

x

x

x

x

9
x

8
7
6
5
AD_CMP0[14:0]
x
x
x
x

4

3
x

2
x

1
x

0
x

x

Port PATCHx_A (x = 0 to 3) must be loaded with the address where the patch should start.
Note: This address is only 15 bits, but ROM is less than 32Kbytes.

17.3 Patch jump instruction
PATCHx_I must be loaded with a special instruction (a jump into far page) and the address into the far page. Figure 22
shows a how to execute the patch in EEPROM while Figure 23 shows a how to execute the patch from RAM (itsupposes RAM has been loaded before).
PATCHx_I
At reset

15
0
x

14
1
x

13
0
x

12
0
x

11
0
x

10
0
x

9
0
x

8
0
x

7
1
x

6
1
x

5
1
x

4
x

3

2
1
FPAD[4:0]
x
x
x

0

3

1
0

0
0

2
1
FPAD[4:0]
x
x
x

0

3

0
0

x

Fp7
15
1

14
0

13
0

12
0

11
0

10
0

Resulting patch start address
9
8
7
6
5
4
0
0
FPAD[4:0]

20

Fp7 value (Defined on Table 6)
Figure 22 - Patch code in EEPROM
PATCHx_I
At reset

15
0
x

14
1
x

13
0
x

12
0
x

11
0
x

10
0
x

9
0
x

8
0
x

7
1
x

6
0
x

5
1
x

4
x

3

x

Fp5
15
1

14
0

13
1

12
0

11
0

Resulting patch start address
10
9
8
7
6
5
4
0
0
1
FPAD[4:0]

2
0

1
0

Fp5 value (Defined on Table 6)
Figure 23 - Patch code in RAM

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Notes:- A patch can only start on an 8 bytes boundary.
- The last instruction of the patch must be a far jump back to the first correct ROM instruction.
Important:
The access time to EEPROM is longer than for ROM; therefore the execution time of the patched code will be a bit
slower than the same code in executed from ROM.
Abnormal cases where two patches are at the same address but have different instruction is solved by giving priority
to the lowest patch id. See examples below.
Examples:If PATCH0_A = PATCH1_A, PATCH0_I is used
If PATCH0_A = PATCH3_A, PATCH0_I is used
If PATCH1_A = PATCH2_A = PATCH3_A, PATCH1_I is used

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18. Application Hints
Further information regarding the use of the IO and SW pins can be found in the Application note “Standard
input/output pin configurations”.

18.1 Application Examples
The SWx are used for connection to a switch matrix as well as for single switches to GND or VS
The IOx pins can be used for different purposes:
1. Single switch input connected to GND or VS incl. switch diagnostics
2. Rotating encoder input
3. General purpose digital input
4. Open drain high voltage capable output
5. ADC Input
The pin IREF, via an external bipolar transistor, is used to generate a 5V voltage to supply external pull up resistors.

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VBat

22µF

AWD

VS

100nF

VS

optional

IREF
IO4
VDD_pu

SW0
SW1
SW2
SW3
SW4
VS

SW5
IO5

SW6

MLX80104

VS

SW7
VS

Diagnostic 7.5k

SW8

IO6

SW9
Diagnostic 7.5k
VDD_puVDD_pu

IO7
IO0

Encoder 1

IO1
IO2

Encoder 2

IO3
TI0
TI1
LIN

TO

180p

GND

Figure 24 - Application schematic sample

18.1.1. Switch Matrix Hints
If more than two switches are closed at the same time, it can happen that reading the switches gives a wrong result. A“ghost” switch is detected, that means it will read out a certain switch is pressed, but this switch is not really pressed(See Figure 25). To avoid this effect, diodes can be used for decoupling the switches. The diodes prevent the fault
current by a closed switch in another row.
Note: This wiring with diodes is only necessary if it is possible to press more than three switches at the same time.
Example: In a matrix without diodes (left example) the open switch 2b (“ghost” switch from left example) is
recognized as closed. The closed switches 1b, 1c and 2c setup a wrong current path. This wrong path is prevented in
the protected wiring (right example) by the diode 1c.

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a

b

c

a

1

1

2

2

3

3

b

c

correct realization

wrong realization
Figure 25 - Reading the switch matrix

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19. Software Development
For software development a software development environment consisting ofCompiler

Linker

DebuggerUser library

LIN2.x / J2602 API

and a hardware development kit consisting of

Evaluation board

Emulator

Application board

are available at Melexis. The kit description can be found in [4].

19.1 UniROM (80104 only)
Beside the software development at customer side a ready-to-use firmware, so called uniROM, is available. The
uniROM firmware offers a ready to use application software which removes the need for new software developmentfor new LIN applications. This Software can be configured to the need of different applications. Further information
can be found in [1].
The main features are:

LIN protocol specification according to LIN 2.x and J2602



19.2kBaud and 10.4kBaud transmission speedUp to 5 LIN configurable LIN frames:oConfigurable data byte lengthoConfigurable LIN identifieroConfigurable communication direction (slave to master, master to slave)oConfigurable data byte content on byte levelEvent triggered frame

Go to sleep commandNode configuration servicesoAssign NADoAssign frame ID rangeoAssign frame ID (according LIN2.0)

oRead by identifieroJ2602 target resetoJ2602 broadcast reset

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Error detection (Communication error (according LIN2.x), EEPROM error, Thermal overload error, undervoltage error, over voltage error etc.)



EEPROM user area for production dataHardware CRC to protect EEPROM dataInternal 12MHz RC-oscillator. For higher accuracy an external resonator can be applied. But this is only
necessary for slave to slave communication)



Window watchdog and additional independent analog watchdog



18 configurable high voltage I/O pins which are ground shift tolerant and can be used as following:o

Up to 18 switch inputs (low side or low side can be configured for each pin separately) ) incl. broken
line detectionoSwitch matrix inputs (5x5, 5x4, 4x4, 4x3, 3x3, 3x2) incl. broken line detectionoUp to 18 configurable open drain outputsoUp to eight 10bit ADC inputsoUp to 8 PWM outputs with common frequency between 45Hz … 46,9kHz and different duty cycles
for each outputoSupport of SMART Fets with current senseoUp to two rotary encoders supported



Configurable debouncing times for switchesInternal supply voltage measurementConfigurable Wake up sources (LIN, switches, ADC)

Software SPI and I C-interface supported for controlling IO extensionConstant current source output IREF (2mA) for building an external help supply

2

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20. Programming Interface
The MLX80104/05 programming interface consists of the pins:Pin 6 - TO => output
Pin 8 - TI0 => input 0
Pin 7 - TI1 => input 1

TO is an open drain output. In case a third party programmer is used, an external pull-up resistor of 500Ohm against
3.3V to this pin is necessary. In case the Melexis Mini E-Mlx emulator with Melexis interface adapter or the PTC-04 isused, no extra pull-up resistor is needed.

IO3

IO4

IO6

SW6

SW7

VS

SW8

28

27

26

25

24

23

22

Additionally it is necessary to connect the MLX80104/05 with the supply voltage Vs and to stop the analog watchdog
by connecting AWD (Pin 21) with GND.

GNDA

1

21

AWD

IREF

2

20

SW9

SW5

3

19

IO7

SW4

4

18

IO0

SW3

5

17

GNDD

TO

6

16

GNDL

TI1

7

15

LIN

8

9

10

11

12

13

14

TI0

IO5

IO2

SW2

SW1

SW0

IO1

MLX80104/05
QFN 5x5 28

Figure 26 - Pin out MLX80104/05 – Top view

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20.1 Characteristics for the interface pins
Parameter

SymbolCondition

Min

Typ

Max

Unit

7

18

V

7.8

8.2

V

10

mA

2

4.5

V

0

3.4

V

Pin VS
Supply voltage

VS

Supply voltage during OTP
programming

VS

Supply current, active withoutswitch current

IS

Undervoltage lockout

VS_UV

6

PIN AWD
Input voltage range

VAWD

Pull down current

IPD_AWD

2µA

PIN TO
Input voltage range
Pull up resistor (only necessary incase third party programmer isused)
Input frequency

VTO

0

RTO_PULLUP
FTI

3.4
500

max output load 20pF

V
Ω

20

MHz

3.4

V

PIN TI0,TI1
Input voltage range

VTI

0

Input threshold rising edge

VTI_RISE

1.7

V

Input threshold falling edge

VTI_FALL

1.5

V

Input frequency

FTI

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20.2 Melexis Mini E-Mlx emulator
To use the MLX80104/05 programming interface directly with the Melexis Mini E-Mlx connector it is necessary to put
external components (see Figure 27) and a 9 pin mini circular connector with shield on the PCB. The connector could
be a MD-90SM from CUI INC. This part can be ordered for instance from Digi-Key (CP-2290-ND).
The Melexis emulator does not provide the supply voltage for the MLX80104/05. Because of this the module has to be
powered by an external power supply.
To disable the analog watchdog during programming and debugging it is necessary to connect pin 21 AWD to GND via
a Jumper JP1.

Pin NoName

Function

1

TI0

Test input 0

2

GND

Ground3VSVS output

4

TI1

Test input 1

5

LIN/MUSTOpen (not used)

6

V0Open (not used)

7

V2

3.3V input

8

TO

Test output

9

V1

Open (not used)

ShieldGND

GroundTable 27 - Pin description 9 pin mini circular connector
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Figure 27 - MLX80104/05 programming interface with the Melexis Mini E-Mlx emulator

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20.3 Melexis Mini E-Mlx emulator and Melexis interface adapter
In case there is not enough space to put all necessary components on the PCB as described in chapter 20.1 it ispossible to use the Melexis interface adapter. This connector includes the 9 pin mini circular connector as well as allnecessary components.

Figure 28 - Melexis MLX80104/05 programming interface adapter
The interface adapter provides an 10 pin header on top side as well as an 10 pin female header on the bottom side toconnect the adapter to the MLX80104/05 module.
The Melexis emulator does not provide the supply voltage for the MLX80104/05. Because of this the module has to be
powered by an external power supply.

Pin NoName

Function

1

GND

Ground2

TO

Test output

3

TI1

Test input 1

4

TI0

Test input 0

5VSVS input6n.c.

not used

7

AWD

Analog watchdog

8

LIN/MUST

not used9

V1

not used10

TM_ENABLE

not used

Table 28 - Pin description 10 pin header connector

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Figure 29 - MLX80104/05 programming interface with the Melexis Mini E-Mlx emulator and Melexis interface adapter

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20.4 Melexis Programmer PTC-04
The PTC-04 can be used for programming OTP & EEPROM via Melexis Test Interface. 3 test pins must be accessible by
the PTC-04 programmer. These pins are TO (Test Interface output), TI0 and TI1 (both Test Interface inputs are used fordata and clock).
Additionally, the analog Watchdog pin AWD must be connected to GND to disable it. Otherwise, the IC will be reset via
the analog Watchdog which makes it impossible to execute any operation via the Melexis Test Interface.
A more detailed schematic can be found in Figure 31.

Customer EOL
Programming
System with Melexis
MLX80104/05 PSF
Library DLL(using Microsoft
Windows XP or 7)

Melexis PTC-04

USB

Melexis PTC-04
Power Supply

Shielded wire
(length max 50cm formax. programming speed)

GND
VS

USB
DB15
FemaleConnector

AWD

TO
TI0
TI1

Customer Module

MLX80104
MLX80105

EOL (OTP, EEPROM)
via Melexis
Test Interface

PowersupplyFigure 30 - Connection diagram between PTC-04 and MLX80104/5
There is no additional power supply for the MLX80104/5 necessary. It will be powered via the PTC-04.
Melexis suggests to keep the cable length between the PTC-04 and the MLX80105 as short as possible to allow a
maximum programming speed (in the range of 0.5m maximum). Shielded wires must be used.
The most critical connections regarding the used cable and the cable length are TO, TI0 and TI1.
In case the cable length is longer than 0.5m the customer has to be secure that the shape of the signals for TO (at the
PTC-04), TI0 and TI1 (at the MLX80104/05) are still correct. Otherwise the test interface speed has to be reduced byusing the Melexis PSF DLL function SetSetting().

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20.4.1. PTC04 DB 15 Female Connector
All unused pins of the connector have to be left open.
PTC05 DB15 Female Connector
7

8
15

Pins
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

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6
14

5
13

Name
VBAT
N.C.
DGND
MUST
TXD0
VOUT_PPS2
MUST0 / TI0
MICE / TO
LIN_OUT+5V_DIG_CON
DGND
RXD0
XCK0
N.C.
MUST1 / TI1

12

2

3

4
11

10

1
9

Description
Power Supply (output)
Not connected
Digital Ground
Analog test pin
USART Transmit Data
VOUT_PPS2
Digital test pin TI0
Digital test pin TO
LIN BUS+5V DC Supply
Digital Ground
USART Receive Data
USART ClockNot connected
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Figure 31 - MLX80104/05 programming interface with the Melexis PTC-04
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20.5 Third party programmer
In case a third party programmer tool is used, the MLX80104/05 based module has to provide at least following
connections.

MLX80104/05
Pin NoName

Function

1,17,16

GND

Ground6

TO

Test output

7

TI1

Test input 1

8

TI0

Test input 0

21

AWD

Analog watchdog

Table 29 - Connections for third party programmer

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21. Operating under Disturbance
21.1 Loss of battery
If the MLX80104/5 is disconnected from the battery, the bus pin is in high Impedance State. There is no impact to thebus traffic and to the ECU itself.
The IC will be reverse powered if switches are placed outside and via wiring harness a short circuit to battery or afaulty blocked switch is connected to the MLX80104/5.To prevent undefined failure currents the ports for connections
to external switches or loads have to be protected by a serial resistor of at least 100Ώ.

21.2 Loss of GroundIn case of an interrupted ECU ground connection there is no influence to the bus line.

21.3 Short circuit to battery
The LIN transmitter output current is limited to the specified value in case of short circuit to battery in order to protect
the MLX80104/5 itself.

21.4 Short circuit to groundIf the bus line is shorted to negative shifted ground levels, there is no current flow from the ECU ground to the bus
and no distortion of the bus traffic.
If the controller detects a short circuit of the bus to ground (RxD timeout) the transceiver can be set into sleep mode.
The internal slave termination resistor is switched off and only a high impedance termination is applied to the bus.
The failure current of the whole system can be reduced by at least ten times to prevent a fast discharge of the carbattery. If the failure disappears, the bus level will become recessive again and will wake up the system even if nolocal wake up is present or possible.

21.5 Thermal overload
The MLX80104/5 is protected against thermal overloads. If the chip temperature exceeds the specified value, thetransmitter is switched off until thermal recovery. The receiver is still working during thermal shutdown.

21.6 Undervoltage Vs
If the ECU battery supply voltage is missing or decreases under the specified value, the LIN pin functions as passive.

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22. Marking/Order Code22.1 Marking MLX80104

80104D

Silicon RevisionM27237

Lot Number
Assembly Date Code – week number

11110AG

Firmware Revision
Assembly Date Code – Year22.2 Order Code MLX80104

MLX80104 KLQ DAG 000 RE
Delivery Form (RE = Reel)
Option Code (000 = Standard)
Firmware Version AG
Silicon Version D
Package Code (LQ=QFN,
LW=QFN with wettable flanks)
Temperature Code (K=-40 to 125°C)
Product Name

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22.3 Marking MLX80105

80105E

Silicon Revision

M25574Lot Number

1

1110

Assembly Date Code – week number
Assembly Date Code – Year22.4 Order Code MLX80105

MLX80105 KLQ EAA 000 RE
Delivery Form (RE = Reel)
Option Code (000 = Standard)
Firmware Version (AA=no Firmware)
Silicon Version E
Package Code (LQ=QFN,
LW=QFN with wettable flanks)
Temperature Code (K=-40 to 125°C)
Product Name

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IO3

IO4

IO6

SW6

SW7

VS

SW8

28

27

26

25

24

23

22

23. Pin Description

GNDA

1

21

AWD

IREF

2

20

SW9

SW5

3

19

IO7

SW4

4

18

IO0

SW3

5

17

GNDD

TO

6

16

GNDL

TI1

7

15

LIN

9

10

11

12

13

14

IO5

IO2

SW2

SW1

SW0

IO1

TI0

8

MLX80104/5
QFN 5x5 28

Figure 32 - Pin out MLX80104/5 – Top view

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Table 1 – Pin Description MLX80104 QFN 5x5 28
Pin NoName

Function

1

GNDA

Analogue ground and ADC ground

GND

2

IREF

IREF output

O

3

SW5

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

4

SW4

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

5

SW3

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

6

TO

Test output, unconnected in application mode

O

7

TI1

Test input - connect to GND in application mode

I

8

TI0

Test input - connect to GND in application mode

I

9

IO5

SWx functionality and ADC input, wake up capable, PWM output

I/O

10

IO2

SWx functionality and ADC input, wake up capable, PWM output

I/O

11

SW2

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

12

SW1

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

13

SW0

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

14

IO1

SWx functionality and ADC input, wake up capable, PWM output

I/O

15

LIN

Connection to LIN bus

IO

16

GNDL

LIN driver ground

GND

17

GNDD

Digital ground

GND

18

IO0

SWx functionality and ADC input, wake up capable, PWM output

I/O

19

IO7

SWx functionality and ADC input, wake up capable, PWM output

I/O

20

SW9

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

21

AWD

Watch dog load capacitor

I/O

22

SW8

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

23

VS

High voltage supply, battery voltage

P

24

SW7

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

25

SW6

Switch matrix I/O, single switch input, open drain output, wake up capable

I/O

26

IO6

SWx functionality and ADC input, wake up capable, PWM output

I/O

27

IO4

SWx functionality and ADC input, wake up capable, PWM output

I/O

28

IO3

SWx functionality and ADC input, wake up capable, PWM output

I/O

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24. Mechanical Specification
1

2

N

E2
L

K

E

BottomExposed Pad

D

A

A3

D2

e

A1

b

Figure 33 - QFN28 Drawing

Table 2 – QFN28 Package Dimensions
Symbolmin
QFN28 nom
max

[1]
[2]
[3]
[4]
[5]
[6]

A

A1

0.80

0

0.90

0.02

1.00

0.05

A3

b

D

0.18
0.20

0.25
0.30

D2

E

3.00
5.00

3.10
3.25

E2

e

K

3.00
5.00

3.10
3.25

L

N [6][3]ND [5]

NE [5]

0.45
0.50

0.20

0.55

[1]

28

7

7

[2]

0.65

Dimensions and tolerances conform to ASME Y14.5M-1994
All dimensions are in Millimeters. All angels are in degrees
N is the total number of terminals
Dimension b applies to metalized terminal and is measured between 0.25 and 0.30mm from terminal tip
ND and NE refer to the number of terminals on each D and E side respectively
Depopulation is possible in a symmetrical fashion

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25. Land Pattern Recommendations
This recommendation is provided as a guideline for board layout.

Table 3 – QFN28 Land Pattern Dimensions
Symbol

Land
X1

Land
Y1

Tab LandX2

Tab LandY2

Land Space
C1

Land SpaceC2(in mm)

0.30

1.00

3.25

3.25

4.70

4.70

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26. ESD/EMC Remarks
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.

26.1 ESD/EMC Recommendations for the MLX80104/5
In order to minimize EMC influences, the PCB has to be designed according to EMC guidelines. The MLX80104/5 is an
ESD sensitive device and has to be handled according to the rules in IEC61340-5-2. MLX80104/5 will apply therequirements in the application according to the specification and to ISO7637-2

26.2 Automotive Qualification Test Pulses
The following chapter is valid for a complete assembled module. That means that automotive test pulses are applied
to the complete module and not to the single IC. Therefore attention must be taken, that only protected pins
(protection done the IC itself or by external components) are wired to a module connector. In the recommended
application diagrams, the reverse polarity diode together with the capacitors on supply pins, the protection resistors
in several lines and the load dump protected IC itself will protect the module against the below listed automotive test
pulses. The exact values of the capacitors for the application have to be chosen in dependence of the automotive
requirements of the module.
For the LIN pin the specification “LIN Physical Layer Spec 2.x” is valid.
Supply Pin VS is protected via the reverse polarity diode and the supply capacitors. No damage will occur for definedtest pulses. A deviation of characteristics is allowed during pulse 1 and 2; but the module will recover to the normal
function after the pulse without any additional action. During test pulse 3a, 3b, 5 the module will work withincharacteristic limits.
Test pulses on supply lines
Parameter

SymbolUs

Dim

Test Condition

Transient test pulses in accordance to ISO7637-2 (supply lines)
Test pulses are defined with the 12V DC voltage shift on the supply lines. Application schematics are according
application notes.
Test pulse #1

vpulse1-100

V5000 pulses, t1 = 5s, td = 2ms,
Ri = 10Ω

Test pulse #2a

vpulse275

V5000 pulses, t1 = 0.5s, td = 0.05ms,
Ri = 2Ω

Test pulse #3a

vpulse3a-200

V1h, t1 = 0.1ms, t4 = 10ms,
t5 = 90ms, Ri = 50Ω

Test pulse #3b

vpulse3b200

V1h, t1 = 0.1ms, t4 = 10ms,
t5 = 90ms, Ri = 50Ω

Test pulse #5b

vpulse545V

10 pulses, td = 400ms, Ri = 0.5Ω

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Test pulses on LIN line
Parameter

SymbolUs

Dim

Test Condition

Transient test pulses in accordance to ISO7637-3 (signal lines)
Test pulses are defined with the 12V DC voltage shift on the signal lines. Application schematics are according
application notes.
vpulse1-100

V5000 pulses, t1 = 5s, td = 2ms,
Ri = 10Ω

vpulse275

V5000 pulses, t1 = 0.5s, td = 0.05ms,
Ri = 2Ω

Test pulse #3a

vpulse3a-200

V1000 bursts, t1 = 0.1ms, t4 = 10ms,
t5 = 90ms, Ri = 50Ω

Test pulse #3b

vpulse3b200

V1000 bursts, t1 = 0.1ms, t4 = 10ms,
t5 = 90ms, Ri = 50Ω

Test pulse #1

8

Test pulse #2a926.3 EMC Test pulse definition
EMC Test Pulse shapes
Test Pulse 1

Test pulse 2
200 msV

0.5...5s< 100 µs

50 µs
V

12 V
0V
10%

t

1 µs

90%

vpulse1

vpulse2

90%

10%
12V

1 µs
2 ms

0V
t

200 ms0.5...5s

Test Pulse 3a

Test Pulse 3b
100 ns

V

5 ns

12V

10%

90%

V

vpulse3b0Vtvpulse3b

vpulse3a
vpulse3a

10%

12V
0V

100 µs
10 ms

90 ms

100 µs

90%

10 ms

t
90 ms

5 ns
100 nsTest Pulse 5 (Load Dump)
V
Pulse 590%

Pulse 5 atdevicevpulse5
40V

10%
12V
t
tr = 0.1...10ms
td = 40...400ms

8
9

Test pulse 1 is not part of ISO 7637-3 for signal lines, this test is made additional.
Test pulse 2 is not part of ISO 7637-3 for signal lines, this test is made additional.

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27. References[1][2]

Software Functional Specification for MLX80104 UniROM
LIN Specification Package 2.1[3]

GM LIN/J2602 Implementation Specification[4]

MLX80104/08 – Software Development Kit

November 24,
2006
Issue
1.4
December 19,
2006

28. List of Abbreviations
Dp
Ep
Fp
GCC

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EEPROM
Far page
GNU Compiler Collection

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29. Revision History
VersionChanges

0.1

RemarkDateFirst preliminary
releaseMarch 2008

0.11

Updated application schematic

March 2008

001

Update of block diagram of MLX80104
Increase RAM size to 512byte
Update absolute maximum ratings
Update static characteristics
Definition of pull up/down resistance on SWx and IOx in sleep mode
Chapter ADC
Add additional channel IREF
Chapter PWM unit
Increase number of PWM channels on IOx to eight
Change the access to duty cycle register
Chapter mechanical specification
Update package dimensions
Update chapter automotive test pulses

December
2008

002

Correct test pin description in chapter Pin description
Chapter Timer added
Application example modified
ADC chapter updated
Chapter Patches added

February
2010003

Update absolute maximum ratings

July 2010

004

Chapter PWM Unit
Equation for PWM_DIV register added
Frequency table added
Chapter Timer
Equation for Timer register added
Chapter ADC
Description for input divider added

September
2010

005

Chapter Programming Interface added

September
2010

006

Small layout changes done

January
2011

007

Chapter Application Examples
Application Schematic modified, capacitor value at VS pin increased tofulfil the performance status A
Chapter PWM unit
Block Diagram PWM unit modified
Chapter Automotive Qualification Test Pulses
Voltage levels updated

008

Order Information updated
Marking MLX80104/5 updated
Disclaimer updated
Chapter Software Development added009

Package drawing corrected

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010

Chapter “Memory Mapping” updated
Chapter “Programming Interface”
New sub-chapter “Melexis programmer PTC-04” added
New chapter “Land Pattern Recommendations” added
Chapter “Operating Conditions” updated
Chapter “Melexis Programmer PTC-04” updated

June 2012

011

Chapter “List of Abbreviations” added
Chapter “EEPROM” updated

April 2013

012

Chapter “Programming Interface” updated

July 2013

013

Chapter “Order Code” updated

January
2014014

Chapter “Order Code” updated
Chapter “Melexis Mini E-Mlx emulator and Melexis interface adapter” updated
Chapter “Entering Sleep Mode by API” updated

March 2014

015

Chapter “Order Code” updated
Chapter “Static Characteristics” updated

May 2014

016

Chapter “Operating Conditions” updated
Chapter “Switch diagnosis” updated
Chapter “Order Code” updated (wettable flanks)
Chapter “Reserved EEPROM Segments” added
Chapter “The IREF pin” updated
Parameter “LIN current during loss of Ground” updated in chapter “Static
Characteristics”

April 2015

017

Chapter “Characteristics for the interface pins” Parameter “Supply voltage during
OTP programming” updated

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30. Standard information regarding manufacturability ofMelexis products with different soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity levelaccording to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)

IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing(reflow profiles according to table 2)

Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices

Iron Soldering THD’s (Through Hole Devices)

EN60749-15
Resistance to soldering temperature for through-hole mounted devices

Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)

EIA/JEDEC JESD22-B102 and EN60749-21
Solderability

For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature,temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed uponwith Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesivestrength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information
on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the use of certain
Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality.aspx

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31. Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term ofSale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth
herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right tochange specifications and prices at any time and without notice. Therefore, prior to designing this product into asystem, it is necessary to check with Melexis for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements,
or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically notrecommended without additional processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable torecipient or any third party for any damages, including but not limited to personal injury, property damage, loss of
profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, inconnection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or
liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services.
© 2012 Melexis NV. All rights reserved.

For the latest version of this document, go to our website atwww.melexis.com
Or for additional information contact Melexis Direct:
Europe, Africa, Asia:

America:Phone: +32 1367 0495
Phone: +1 248 306 5400
E-mail: sales_europe@melexis.com E-mail: sales_usa@melexis.com

ISO/TS 16949 and ISO14001 Certified

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