IR3553

40A Integrated PowIRstage®
FEATURESDESCRIPTION

 Peak efficiency up to 93.2% at 1.2V
 Integrated driver, control MOSFET, synchronous
MOSFET and Schottky diode Input voltage (VIN) operating range up to 15V
 Output voltage range from 0.25V to Vcc-2.5V, or to
5.5V if internal current sense amplifier is not used
 Output current capability of 40A DC
 Operation up to 1.0MHz

The IR3553 integrated PowIRstage® is a synchronous buckgate driver co-packed with a control MOSFET and asynchronous MOSFET with integrated Schottky diode. It is
optimized internally for PCB layout, heat transfer anddriver/MOSFET timing. Custom designed gate driver and
MOSFET combination enables higher efficiency at lower
output voltages required by cutting edge CPU, GPU and
DDR memory designs.
Up to 1.0MHz switching frequency enables highperformance transient response, allowing miniaturizationof output inductors, as well as input and output capacitors
while maintaining industry leading efficiency. The IR3553’s
superior efficiency enables smallest size and lower solution
cost. The IR3553 PCB footprint is compatible with the
IR3550 (60A) and the IR3551 (50A).

 Integrated current sense amplifier VCC under voltage lockout Thermal flag Body-Braking® load transient support
 Diode-emulation high efficiency mode Compatible with 3.3V PWM logic and VCC tolerant Compliant with Intel DrMOS V4.0
 PCB footprint compatible with IR3550 and IR3551
 Efficient dual sided cooling Small 4mm x 6mm x 0.9mm PQFN package Lead free RoHS compliant package

APPLICATIONS

Integrated current sense amplifier achieves superior
current sense accuracy and signal to noise ratio vs. best-inclass controller based Inductor DCR sense methods.
The IR3553 incorporates the Body- Braking® feature whichenables reduction of output capacitors. Synchronous diodeemulation mode in the IR3553 removes the zero-current
detection burden from the PWM controller and increases
system light-load efficiency.

 Voltage Regulators for CPUs, GPUs, and DDR
memory arrays High current, low profile DC-DC converters

BASIC APPLICATION
IR3553VIN

4.5V to 7V

VIN
4.5V to 15V

BOOST
PHSFLT#

PHSFLT#

PWM

PWM

BBRK#

BBRK#

REFIN

REFIN

CSIN+

IOUT

IOUT

CSIN-

LGND

PGND

SW

VOUT

Efficiency (%)

VCC

VCC

94

20

92

18

90

16

88

14

86

12

84

10

82

8

80

6

78

4

76

2

74

Power Loss (W)The IR3553 is optimized specifically for CPU core power
delivery in server applications. The ability to meet thestringent requirements of the server market also makes
the IR3553 ideally suited to powering GPU and DDR
memory designs and other high current applications.

0
0

5

10

15

20

25

30

35

40

Output Current (A)Figure 1: IR3553 Basic Application Circuit

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July 16, 2014 | DATASHEET V3.3

Figure 2: Typical IR3553 Efficiency & Power Loss (See Note 2 on Page 8)

IR3553

40A Integrated PowIRstage®
PINOUT DIAGRAM

ORDERING INFORMATION
Package

Tape & Reel Qty

Part Number

PQFN, 25 Lead
4mm x 6mm

3000

IR3553MTRPBF

Package

Qty

Part Number

PQFN, 25 Lead
4mm x 6mm

100

IR3553MPBF

Figure 3: IR3553 Pin Diagram, Top View

TYPICAL APPLICATION DIAGRAM
VCC
4.5V to 7V
R1
10k

PHSFLT#
PWM
BBRK#
Optional for
diode emulation
setup

REFIN
C8
1nF

VIN

C3
1uF

IR3553
18

PHSFLT#

19

PWM

20

BBRK#

C9
22nF

21

LGND

22

REFIN

23

IOUT

3

14-16

VCC

VIN

BOOST
Gate
DriversandCurrent
Sense
Amplifier17

C5
0.22uF24
1
No Connect

R2
2.49k

CSIN+
2

Figure 4: Application Circuit with Current Sense Amplifier

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July 16, 2014 | DATASHEET V3.3

C6
22uF

C7
470uF

VOUT

6-11

PGND 12, 13
PGND 4
CSIN-

L1
150nH

SW

IOUT
TGND

C2
4.5V to 15V
10uF x 2

C1
0.22uFC4
0.22uFIR3553

40A Integrated PowIRstage®
TYPICAL APPLICATION DIAGRAM (CONTINUED)
VCC
4.5V to 7V

VIN

C3
0.22uFR1
10k

IR3553

PHSFLT#
PWM
BBRK#

18

PHSFLT#

19

PWM

20

BBRK#

21

LGND

22

REFIN

23

IOUT

TGND

3

14-16

VCC

VIN

BOOST
Gate
DriversandCurrent
Sense
AmplifierC2
4.5V to 15V
10uF x 2

C1
0.22uF17

C5
0.22uF

L1
150nH

R2
2.49k

C4
0.22uF

CS+

CS-

CSIN+

1
24
No Connect2

Figure 5: Application Circuit without Current Sense Amplifier

FUNCTIONAL BLOCK DIAGRAM

VCC

BBRK#

VIN

VIN

VIN

17

14

15

16

VCC

20

S

Q

R
PO R
3.3V

PW M

BO O ST

3
3.3V

19

PH SFLT#18

LG N D

21

IO U T

23

REFIN

22

M O SFET& Therm al
D etection

Pow er-on
Reset(PO R),
3.3V
Reference,andD ead-tim eControl

D river

D riverCurrent Sense
Am plifier
+

-

1

2

24

5

25

4

12

13

CSIN - CSIN + TG N D G ATEL G ATEL PG N D PG N D PG N D

Figure 6: IR3553 Functional Block Diagram
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July 16, 2014 | DATASHEET V3.3

C7
470uF

VOUT

6-11

PGND 12, 13
PGND 4
CSIN-

C6
22uF

SW

6

SW

7

SW

8

SW

9

SW

10

SW

11

SW

40A Integrated PowIRstage®

IR3553

PIN DESCRIPTIONSPIN #PIN NAME

PIN DESCRIPTION

1

CSIN-

Inverting input to the current sense amplifier. Connect to LGND if the current sense
amplifier is not used.

2

CSIN+

Non-Inverting input to the current sense amplifier. Connect to LGND if the current sense
amplifier is not used.

3

VCC

Bias voltage for control logic. Connect a minimum 1uF cap between VCC and PGND (pin4) if current sense amplifier is used. Connect a minimum 0.22uF capacitor between VCC
and PGND (pin 4) if current sense amplifier is not used.

4, 12, 13

PGND

Power ground of MOSFET driver and the synchronous MOSFET. MOSFET driver signal isreferenced to this pin.

5, 25

GATEL

Low-side MOSFET driver pins that can be connected to a test point in order to observe
the waveform.

6 – 11SW

Switch node of synchronous buck converter.

VIN

High current input voltage connection. Recommended operating range is 4.5V to 15V.
Connect at least two 10uF 1206 ceramic capacitors and a 0.22uF 0402 ceramic
capacitor. Place the capacitors as close as possible to VIN pins and PGND pins (12-13).
The 0.22uF 0402 capacitor should be on the same side of the PCB as the IR3553.

17

BOOST

Bootstrap capacitor connection. The bootstrap capacitor provides the charge to turn on
the control MOSFET. Connect a minimum 0.22µF capacitor from BOOST to SW pin. Placethe capacitor as close to BOOST pin as possible and minimize parasitic inductance of
PCB routing from the capacitor to SW pin.

18

PHSFLT#

Open drain output of the phase fault circuits. Connect to an external pull-up resistor.
Output is low when a MOSFET fault or over temperature condition is detected.

PWM

3.3V logic level tri-state PWM input and 7V tolerant. “High” turns the control MOSFET
on, and “Low” turns the synchronous MOSFET on. “Tri-state” turns both MOSFETs off in
Body-Braking® mode. In diode emulation mode, “Tri-state” activates internal diodeemulation control. See “PWM Tri-state Input” Section for further details about the PWM
Tri-State functions.

20

BBRK#

3.3V logic level input and 7V tolerant with internal weak pull-up to 3.3V. Logic low
disables both MOSFETs. Pull up to VCC directly or by a 4.7kΩ resistor if Body-Braking® is
not used. The second function of the BBRK# pin is to select diode emulatiom mode.
Pulling BBRK# low at least 20ns after VCC passes its UVLO threshold selects internal®
diode emulation control. See “Body-Braking Mode” Section for further details.

21

LGND

Signal ground. Driver control logic, analog circuits and IC substrate are referenced tothis pin.

22

REFIN

Reference voltage input from the PWM controller. IOUT signal is referenced to thevoltage on this pin. Connect to LGND if the current sense amplifier is not used.

23

IOUT

Current output signal. Voltage on this pin is equal to V(REFIN) + 32.5 * [V(CSIN+) –V(CSIN-)]. Float this pin if the current sense amplifier is not used.

TGND

This pin is connected to internal power and signal ground of the driver. For best
performance of the current sense amplifier, TGND must be electrically isolated fromPower Ground (PGND) and Signal Ground (LGND) in the PCB layout. Connect to PGND if
the current sense amplifier is not used.

14 – 16

19

24

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40A Integrated PowIRstage®

IR3553

ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These arestress ratings only and functional operation of the device at these or any other conditions beyond those indicated in theoperational sections of the specifications are not implied.
PIN Number

PIN NAME

VMAX

VMIN

ISOURCE

ISINK

1

CSIN-

VCC + 0.3V

-0.3V

1mA

1mA

2

CSIN+

VCC + 0.3V

-0.3V

1mA

1mA
5A for 100ns,
200mA DC

3

VCC

8V

-0.3V

NA

4

PGND

0.3V

5, 25

GATEL

VCC + 0.3V

6-11

SW

2

25V

-0.3V
-3V for 20ns,-0.3V DC
-5V for 20ns,-0.3V DC12, 13

PGND

NA

NA

15mA
1A for 100ns,
200mA DC
45A RMS,
60A Peak
20A RMS,
25A Peak

14-16

VIN

2

25V

-0.3V

5A RMS

17

BOOST

33V

-0.3V

1A for 100ns,
100mA DC

15mA
1A for 100ns,
200mA DC
20A RMS,
25A Peak
45A RMS,
60A Peak
15A RMS,
20A Peak
5A for 100ns,
100mA DC

18

PHSFLT#

VCC + 0.3V

-0.3V

1mA

20mA

19

PWM

VCC + 0.3V

-0.3V

1mA

1mA

20

BBRK#

VCC + 0.3V

-0.3V

1mA

1mA

21

LGND

0.3V

-0.3V

15mA

15mA

22

REFIN

3.5V

-0.3V

1mA

1mA

23

IOUT

VCC + 0.3V

-0.3V

5mA

5mA

24

TGND

0.3V

-0.3V

NA

NA

1

Note:
1. Maximum BOOST – SW = 8V.
2. Maximum VIN – SW = 25V.
3. All the maximum voltage ratings are referenced to PGND (Pins 12 and 13).
THERMAL INFORMATION
Thermal Resistance, Junction to Top (θJC_TOP)

23.2 °C/W

Thermal Resistance, Junction to PCB (pin 13) (θJB)

2.5 °C/W

1

22.2 °C/W

Thermal Resistance (θJA)

Maximum Operating Junction Temperature-40 to 150°C

Maximum Storage Temperature Range-65°C to 150°C

ESD rating

HBM Class 1B JEDEC Standard

MSL Rating

3

Reflow Temperature

260°C

Note:
1. Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air.
Refer to International Rectifier Application Note AN-994 for details.
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IR3553

40A Integrated PowIRstage®
ELECTRICAL SPECIFICATIONSThe electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C.

RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
PARAMETERSYMBOL

MIN

MAX

UNIT

Recommended VIN Range

VIN

4.5

15

V

Recommended VCC Range

VCC

4.5

7

V

Recommended REFIN Range

REFIN

0.25

VCC – 2.5

V

Recommended Switching Frequency

ƒSW

200

1000

kHz

Recommended Operating Junction Temperature

TJ

-40

125

°C

ELECTRICAL CHARACTERISTICSPARAMETERSYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Efficiency and Maximum Current
Note 2. See Figure 2.

92.7

%

Note 3. See Figure 7.

92.2

%

IDC_MAX

Note 2.

40

A

IPK_MAX

Note 4. 5ms load pulse
width, 10% load duty cycle.

60

A

PWM Input High Threshold

VPWM_HIGH

PWM Tri-state to HighPWM Input Low Threshold

VPWM_LOWPWM Tri-state to Low

PWM Tri-state Float Voltage

VPWM_TRIPWM Floating

1.2

Hysteresis

VPWM_HYS

Active to Tri-state or Tristate to Active, Note 1

65

IR3553 Peak Efficiency

Note 1

IR3553 Maximum DC Current

ηNote 1

IR3553 Maximum Peak Current

Note 1PWM Comparator

Tri-state Propagation DelaytPWM_DELAY

2.5

V
0.8

V

1.65

2.1

V

76

100

mV

PWM Tri-state to Low
transition to GATEL >1V38

ns

PWM Tri-state to Hightransition to GATEH >1V

18

ns

PWM Sink Impedance

RPWM_SINK

3.67

5.1

8.70

kΩ

PWM Source Impedance

RPWM_SOURCE

3.67

5.1

8.70

kΩ

Internal Pull up Voltage

VPWM_PULLUPVCC > UVLO

3.3

Minimum Pulse WidthtPWM_MIN

Note 1

41

58

ns

V

Current Sense Amplifier
CSIN+/- Bias Current

ICSIN_BIAS

-100

0

100

nA

CSIN+/- Bias Current Mismatch

ICSIN_BIASMM

-50

0

50

nA

Calibrated Input Offset Voltage

VCSIN_OFFSET

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July 16, 2014 | DATASHEET V3.3

Self-calibrated offset,
0.5V ≤ V(REFIN) ≤ 2.25V

±450

µV

IR3553

40A Integrated PowIRstage®
PARAMETERGain

SYMBOLGCS

CONDITIONS

MIN

TYP

MAX

UNIT

0.5V ≤ V(REFIN) ≤ 2.25V,-5mV ≤ *V(CSIN+) –V(CSIN-)]≤ 25mV, 0°C ≤ TJ ≤ 125°C

30.0

32.5

35.0

V/V

0.5V ≤ V(REFIN) ≤ 2.25V,-5mV ≤ *V(CSIN+) – V(CSIN-)]≤ 25mV

30.0

33.0

36.0

V/V

0.8V ≤ V(REFIN) ≤ 2.25V,-10mV ≤*V(CSIN+)–V(CSIN-)]≤ 25mV

28.0

31.5

35.0

V/V

C(IOUT) = 10pF. Measure at
IOUT. Note 1

4.8

6.8

8.8

MHz

Unity Gain Bandwidth

fBW

Slew RateSR

Differential Input Range

VD_IN

Common Mode Input Range

VC_IN

Output Impedance (IOUT)RCS_OUTIOUT Sink Current

ICS_SINK

Driving external 3 kΩInput Offset Voltage

VIN_OFFSET

Leading Edge Blanking Time
Negative Current Time-Out

6
0.8V ≤ V(REFIN) ≤ 2.25V,

V/µs

-10

25

mV

0

VCC2.5

V

62

200

Ω

0.5

0.8

1.1

mA

Note 1

-12

-3

3

mV

tBLANK

V(GATEL)>1V Starts Timer

50

150

200

ns

tNC_TOUTPWM = Tri-State,
V(SW) ≤ -10mV

12

28

46

µs

Diode Emulation Mode Comparator

Digital Input – BBRK#
Input voltage highVBBRK#_IH

2.0

Input voltage low

VBBRK#_IL

Internal Pull Up Resistance

RBBRK#_PULLUPVCC > UVLOInternal Pull Up Voltage

VBBRK#_PULLUPVCC > UVLO

69

V

200

0.8

V

338

kΩ

3.3

V

Digital Output – PHSFLT#
Output voltage high

VPHASFLT#_OH

VCC

V

Output voltage low

VPHASFLT#_OL

4mA

150

300

mV

Input current

IPHASFLT#_IN

V(PHSFLT#) = 5.5V

0

1

µA

Control MOSFET Short Threshold

VCM_SHORT

Measure from SW to PGND

3.3

Synchronous MOSFET Short Threshold

VSM_SHORT

Measure from SW to PGND

150

200

250

mV

Synchronous MOSFET Open Threshold

VSM_OPEN

Measure from SW to PGND

-250

-200

-150

mV

Propagation DelaytPROP

PWM High to Low Cycles

15

Cycle

Rising Threshold

TRISE

PHSFLT# Drives Low,
Note 1

160°C

Falling Threshold

TFALL

Note 1

135°C

Phase Fault Detection
V

Thermal Flag

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IR3553

40A Integrated PowIRstage®
PARAMETERSYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

I(BOOST) = 30mA, VCC=6.8V

360

520

920

mV

Bootstrap Diode
Forward Voltage

VFWD

VCC Under Voltage Lockout
Start Threshold

VVCC_START

3.3

3.7

4.1

V

Stop Threshold

VVCC_STOP

3.0

3.4

3.8

V

Hysteresis

VVCC_HYS

0.2

0.3

0.4

V

4

8

12

mA

1

µA

GeneralVCC Supply Current

IVCC

VCC = 4.5V to 7V

VIN Supply Leakage Current

IVIN

VIN = 20V, 125C, V(PWM) =Tri-State

BOOST Supply Current

IBOOST

4.75V < V(BOOST)-V(SW) <8V

REFIN Bias Current

IREFINSW Floating Voltage

VSW_FLOATSW Pull Down Resistance

RSW_PULLDOWN

0.5

1.5

3.0

mA

-1.5

0

1

µA

V(PWM) = Tri-State

0.2

0.4

V

BBRK# is Low or VCC = 0V

18

kΩ

Notes
1. Guaranteed by design but not tested in production
2. VIN=12V, VOUT=1.2V, ƒSW = 300kHz, L=210nH (0.2mΩ), VCC=6.8V, CIN=47uF x 4, COUT =470uF x3, 400LFM airflow, no heat sink, 25°C
ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.
3. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, CIN=47uF x 4, COUT =470uF x3, no airflow, no heat sink, 25°C ambient
temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.
4. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=210nH (0.2mΩ, 13mm x 13mm x 8mm), VCC=6.8V, CIN=47uF x 4, COUT =470uF x3, no heat sink,
25°C ambient temperature, 8-layer PCB of 3.7” (L) x 2.6” (W), 5ms load pulse width, 10% load duty cycle, and IR3553 junction
temperature below 125°C.

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IR3553

40A Integrated PowIRstage®
TYPICAL OPERATING CHARACTERISTICS

93

1.30

9.0

92

1.25

7.5

1.20

6.0

1.15

4.5

1.10

3.0

1.05

1.5

1.00

0.0

0.95

-1.5

0.90

-3.0

81

0.85

-4.5

80

0.80

91
90
Normalized Power Loss

89
87
86
85
84
83
82

5

10

15

20

25

30

35

40

-6.0
5

6

7

8

9

Output Current (A)

10

11

12

13

14

15

Input Voltage (V)Figure 10: Normalized Power Loss vs. Input Voltage

Figure 7: Typical IR3553 Efficiency

10
9

1.5

15

1.4

12

1.3

9

1.2

6

1.1

3

1.0

0

0.9

-3

8
Normalized Power Loss

6
5
4
3
2
1
0

0.8

0

5

10

15

20

25

30

35

40

-6
0.8

0.9

1

1.1

Output Current (A)Figure 8: Typical IR3553 Power Loss

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

Output Voltage (V)Figure 11: Normalized Power Loss vs. Output Voltage

Normalized Power Loss

Power Loss (W)7

Case Temperature Adjustment (°C)

0

1.30

9.0

1.25

7.5

1.20

6.0

1.15

4.5

1.10

3.0

1.05

1.5

1.00

0.0

0.95

-1.5

0.90

-3.0

0.85

-4.5

0.80
200

Case Temperature Adjustment (°C)

Efficiency (%)

88

Case Temperature Adjustment (°C)

Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow,
8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.

-6.0

300

400

500

600

700

800

900

1000

Switching Frequency (kHz)

Figure 9: Thermal Derating Curve, TCASE <= 125°C

9July 16, 2014 | DATASHEET V3.3

Figure 12: Normalized Power Loss vs. Switching Frequency

40A Integrated PowIRstage®

IR3553TYPICAL OPERATING CHARACTERISTICS (CONTINUED)

1.30

9.0

1.25

7.5

1.20

6.0

1.15

4.5

1.10

3.0

1.05

1.5

1.00

0.0

0.95

-1.5

0.90

-3.0

0.85

-4.5

0.80
5.00

5.25

5.50

5.75

6.00

6.25

6.50

6.75

PWM
5V/div
Case Temperature Adjustment (°C)

Normalized Power Loss

Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow,
8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.

GATEL
10V/div-6.0
7.00

VCC Voltage (V)400ns/div

1.30

9.0

1.25

7.5

1.20

6.0

1.15

4.5

1.10

3.0

1.05

1.5

1.00

0.0

0.95

-1.5

0.90

-3.0

0.85

-4.5

130

140

150

160

170

180

190

Figure 16: Switching Waveform, IOUT = 0A

PWM
5V/div
Case Temperature Adjustment (°C)

Normalized Power Loss

Figure 13: Normalized Power Loss vs. VCC Voltage

0.80
120

SW
5V/divSW
5V/div

GATEL
10V/div

-6.0
210

200

Output Inductor (nH)

400ns/div

Figure 14: Power Loss vs. Output Inductor

Figure 17: Switching Waveform, IOUT = 40A

60

PWM
2V/div

50

VCC Current (mA)

Vcc=6.8V40

Vcc=5V

30

20

SW
5V/div

10

0
200

300

400

500

600

700

800

900

1000

fsw (kHz)40ns/div

Figure 15: VCC Current vs. Switching Frequency

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July 16, 2014 | DATASHEET V3.3

Figure 18: PWM to SW Delays, IOUT = 10A

40A Integrated PowIRstage®

IR3553TYPICAL OPERATING CHARACTERISTICS (CONTINUED)
Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow,
8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.

PWM
2V/div

BBRK#
5V/div

PWM
5V/divSW
5V/div

GATEL
5V/div
GATEL
10V/div
40ns/div

400ns/div

Figure 19: Body-Braking® Delays

Figure 22: Diode Emulation Mode, IOUT = 3A

PWM
2V/div
PWM
2V/divSW
5V/divSW
5V/div
GAETL
10V/div
100ns/div

400ns/div

Figure 20: PWM Tri-state Delays, IOUT = 10A

Figure 23: Body-Braking® Mode, IOUT = 3A

VCC
2V/div

PWM
2V/div

BBRK#
1V/divSW
5V/divSW
10V/div

100ns/div

Figure 21: PWM Tri-state Delays, IOUT = 10A

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July 16, 2014 | DATASHEET V3.3

2ms/div

Figure 24: Diode Emulation Setup through BBRK# Capacitor

40A Integrated PowIRstage®

IR3553TYPICAL OPERATING CHARACTERISTICS (CONTINUED)
Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow,
8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.

V(IOUT)V(REFIN)
0.2V/div

VCC
2V/divIL
10A/div

BBRK#
2V/divSW
20V/div
2us/div

4ms/div

Figure 25: Diode Emulation Setup through BBRK# Input

Figure 28: Current Sense Amplifier Output, IOUT = 0A

V(IOUT)V(REFIN)
0.2V/div

VCC
2V/divIL
10A/div

BBRK#
2V/divSW
20V/div
2us/div

4ms/div

Figure 26: Diode Emulation Setup through BBRK# Input

Figure 29: Current Sense Amplifier Output, IOUT = 20A

0.50
0.45

V(IOUT)V(REFIN)
0.2V/div

0.40

IOUT-REFIN (V)

0.35
0.30

IL
10A/div

0.25
0.20
0.15
0.10
0.05
0.00
0

5

10

15

20

25

30

35

SW
20V/div

40

Output Current (A)2us/div

Figure 27: Current Sense Amplifier Output vs. Current

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July 16, 2014 | DATASHEET V3.3

Figure 30: Current Sense Amplifier Output, IOUT = 20A, 300kHz

40A Integrated PowIRstage®
THEORY OF OPERATIONDESCRIPTION
The IR3553 PowIRstage® is a synchronous buck driver withco-packed MOSFETs with integrated Schottky diode, which
provides system designers with ease of use and flexibility
required in cutting edge CPU, GPU and DDR memory
power delivery designs and other high-current low-profile
applications.
The IR3553 is designed to work with a PWM controller.
It incorporates a continuously self-calibrated current sense
amplifier, optimized for use with inductor DCR sensing.
The current sense amplifier provides signal gain and noise
immunity, supplying multiphase systems with a superior
design toolbox for programmed impedance designs.
The IR3553 provides a phase fault signal capableof detecting open or shorted MOSFETs, or an overtemperature condition in the vicinity of the power stage.

IR3553a synchronous diode emulation feature allowing designers
to maximize system efficiency at light loads withoutcompromising transient performance. Once the diodeemulation mode is set, it cannot be reset until the VCC
power is recycled.

PWM TRI-STATE INPUTThe IR3553 PWM accepts 3-level input signals. When PWM
input is high, the synchronous MOSFET is turned off andthe control MOSFET is turned on. When PWM input is low,
control MOSFET is turned off and synchronous MOSFET isturned on. Figures 16-18 show the PWM input and thecorresponding SW and GATEL output. If PWM pin is floated, the built-in resistors pull the PWM pin into a tri-stateregion centered around 1.65V.
When PWM input voltage is in tri-state region, the IR3553
will go into either Body-Braking® mode or diode emulation
mode depending on BBRK# selection during VCC power up.

BODY-BRAKING® MODE
The IR3553 accepts an active low Body-Braking® input
which disables both MOSFETs to enhance transient
performance or provide a high impedance output.
The IR3553 provides diode emulation feature which avoids
negative current in the synchronous MOSFET and improves
light load efficiency.
The IR3553 PWM input is compatible with 3.3V logic signal
and 7V tolerant. It accepts 3-level PWM input signals with
tri-state.

BBRK# PIN FUNCTIONSThe BBRK# pin has two functions. During normal
operation, it accepts direct control signal from the PWM
controller to enable Body-Braking®, which turns off bothcontrol and synchronous MOSFETs to improve the loadtransient response.
The second function of BBRK# pin is to select BodyBraking® (tristate) or diode emulation mode when PWM
pin receives a tri-state signal. The seletion is recongnizedright after VCC passes its UVLO threshold during the VCC
power up. If the BBRK# input is always high, the default
operation mode is Body- Braking®, in which both MOSFETs
will be turned off when the PWM input is in tri-state. If the
BBRK# input has been pulled low for at least 20ns after the
VCC passes its UVLO threshold during power up, the diodeemulation mode is set. PWM input in tri-state will activate

13

July 16, 2014 | DATASHEET V3.3

International Rectifier’s Body-Braking® is an operation
mode in which two MOSFETs are turned off. When thesynchronous MOSFET is off, the higher voltage across the
Shottky diode in parallel helps discharging the inductor
current faster, which reduces the output voltage
overshoot. The Body-Braking® can be used either toenhance transient response of the converter after load
release or to provide a high impedance output.
There are two ways to place the IR3553 in Body-Braking®
mode, either controlling the BBRK# pin directly or througha PWM tri-state signal. Both control signals are usuallyfrom the PWM controller.
Pulling BBRK# low forces the IR3553 into Body-Braking®
mode rapidly, which is usually used to enhance convertertransient response after load release, as shown in Figure
19. Releasing BBRK# forces the IR3553 out of BodyBraking® mode quickly.
The BBRK# low turns off both MOSFETs and therefore canalso be used to disable a converter. Please note that soft
start may not be available when BBRK# is pulled high toenable the converter.
If the BBRK# input is always high, the Body-Braking® isactivated when the PWM input enters the tri-state region,
as shown in Figures 20 and 21. Comparing to pulling down
the BBRK# pin directly, the Body-Braking® response to
PWM tri-state signal is slower due to the hold-off time

40A Integrated PowIRstage®
created by the PWM pin parasitic capacitor with the pullup and pull-down resistors of PWM pin. For better
performance, no more than 100pF parasitic capacitive load
should be present on the PWM line of IR3553.

SYNCHRONOUS DIODE EMULATION MODE
An additional feature of the IR3553 is the synchronous
diode emulation mode. This function enables increased
efficiency by preventing negative inductor current fromflowing in the synchronous MOSFET.
As shown in Figure 22, when the PWM input enters the tristate region the control MOSFET is turned off first, and thesynchronous MOSFET is initially turned on and then isturned off when the output current reaches zero. If thesensed output current does not reach zero within a set
amount of time the gate driver will assume that the output
is de-biased and turn off the synchronous MOSFET,
allowing the switch node to float.
This is in contrast to the Body-Braking® mode shown in
Figure 23, where GATEL follows PWM input. The Schottky
diode in parallel with the synchronous MOSFET conducts
for a longer period of time and therefore lowers the lightload efficiency.
The zero current detection circuit in the IT3553 isindependent of the current sense amplifier and therefore
still functions even if the current sense amplifier is not
used. As shown in Figure 6, an offset is added to the diodeemulation comparator so that a slightly positive output
current in the inductor and synchronous MOSFET is treatedas zero current to accommodate propagation delays,
preventing any negative current flowing in thesynchronous MOSFET. This causes the Schottky diode inparallel with the synchronous MOSFET to conduct before
the inductor current actually reaches zero, and the
conduction time increases with inductance of the output
inductor.
To set the IR3553 in diode emulation mode, the BBRK# pinmust be toggled low at least once after the VCC passes its
UVLO threshold during power up. One simple way is to use
the internal BBRK# pull-up resistor (200kΩ typical) with an
external capacitor from BBRK# pin to LGND, as shown in
Figure 4. To ensure the diode emulation mode is properly
set, the BBRK# voltage should be lower than 0.8V when the
VCC voltage passes its UVLO threshold (3.3V minimum and3.7V typical), as shown in Figure 24. A digital signal fromthe PWM controller can also be used to set the diodeemulation mode. The BBRK# signal can either be pulled
low for at least 20ns after the VCC passes its UVLO
14July 16, 2014 | DATASHEET V3.3

IR3553threshold, as shown in Figure 25, or be pulled low before
VCC power up and then released after the VCC passes its
UVLO threshold, as shown in Figure 26.
Once the diode emulation mode is set, it cannot be reset
until the VCC power is recycled.

PHASE FAULT AND THERMAL FLAG OUTPUT
The phase fault circuit looks at the switch node withrespect to ground to determine whether there is a
defective MOSFET in the phase. The output of the phasefault signal is high during normal operation and is pulled
low when there is a fault. Each driver monitors the
MOSFET it drives. If the switch node is less than a certain
voltage above ground when the PWM signal goes low or
if the switch node is a certain voltage above ground when
the PWM signal rises, this gives a fault signal. If there are anumber of consecutive faults the phase fault signal isasserted.
Thermal flag circuit monitors the temperature of theIR3553. If the temperature goes above a threshold (160°C
typical) the PHSFLT# pin is pulled low after a maximum
delay of 100us.
The PHSFLT# pin can be pulled low by either the phasefault circuit or the thermal flag circuit, but the IR3553 relieson the system to take protective actions. The phase fault
signal could be used by the system to turn off the AC/DC
converter or blow a fuse to disconnect the DC/DC
converter input from the supply.
If PHSFLT# is not used it can be floated or connected to
LGND.

LOSSLESS AVERAGE INDUCTOR CURRENTSENSING
Inductor current can be sensed by connecting a series
resistor and a capacitor network in parallel with theinductor and measuring the voltage across the capacitor,
as shown in Figure 31.
The equation of the current sensing network is as follows.

L
1
RL
vCS ( s )  vL ( s ) iL ( s ) RL
1  sRCS CCS
1  sRCS CCS
1 s iL ( s) RL when L RL  RCSCCS

40A Integrated PowIRstage®
IR3553

VIN

VIN
CIN

+

vL

-

L
SW

RL

iL
RCS

Current
Sense
Amplifier

CCS

VOUT
COUT

+ vCS +CSIN+

- CSIN-

Figure 31: Inductor current sensing

Usually the resistor RCS and capacitor CCS are chosen so thatthe time constant of RCS and CCS equals the inductor time
constant, which is the inductance L over the inductor DCR(RL). If the two time constants match, the voltage across CCS
is proportional to the current through L, and the sense
circuit can be treated as if only a sense resistor with thevalue of RL was used. The mismatch of the time constants
does not affect the measurement of inductor DC current,
but affects the AC component of the inductor current.
The advantage of sensing the inductor current versus highside or low side sensing is that actual output current being
delivered to the load is obtained rather than peak or
sampled information about the switch currents. The
output voltage can be positioned to meet a load line basedon real time information. This is the only sense methodthat can support a single cycle transient response. Other
methods provide no information during either loadincrease (low side sensing) or load decrease (high side
sensing).

CURRENT SENSE AMPLIFIER
A high speed differential current sense amplifier is locatedin the IR3553, as shown in Figure 6. Its gain is nominally32.5, and the inductor DCR increase with temperature isnot compensated inside the IR3553. The current sense
amplifier output IOUT is referenced to REFIN, which isusually connected to a reference voltage from the PWM
controller. Figure 27 shows the differential voltage ofV(IOUT) – V(REFIN) versus the inductor current and reflects
the inductor DCR increase with temperature at higher
current.
The current sense amplifier can accept positive differential
input up to 25mV and negative input up to -10mV before
clipping. The output of the current sense amplifier is
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July 16, 2014 | DATASHEET V3.3

IR3553summed with the reference voltage REFIN and sent to the
IOUT pin. The REFIN voltage is to ensure at light loads
there is enough output range to accommodate thenegative current ripple shown in Figure 28. In a multiphaseconverter, the IOUT pins of all the phases can be tied
together through resistors, and the IOUT voltage
represents the average current through all the inductors
and is used by the controller for adaptive voltage
positioning.
The input offset voltage is the primary source of error forthe current signal. In order to obtain very accurate current
signal, the current sense amplifier continuously calibrates
itself, and the input offset of this amplifier is within +/450uV. This calibration algorithm can create a small ripple
on IOUT with a frequency of fsw/128.
If the IR3553 current sense amplifier is required, connect
its output IOUT and the reference voltage REFIN to the
PWM controller and connect the inductor sense circuit asshown in Figure 4. If the current sense amplifier is notneeded, tie CSIN+, CSIN- and REFIN pins to LGND and float
IOUT pin, as shown in Figure 5.

MAXIMUM OUTPUT VOLTAGE
When the IR3553 current sense amplifier is used, themaximum output voltage is limited by the VCC voltage
used and should be lower than VCC – 2.5V to ensure
enough headroom for the current sense amplifier. The
maximum voltage is 4.3V when 6.8V VCC is used, but isonly 2.5V when 5V VCC is used. The maximum voltage is
4.3V when 6.8V is used for the VCC.
When the IR3553 current sense amplifier is not used, themaximum voltage is not limited by the VCC voltage. The
IR3553 can support output voltage up to 5.5V but theoutput current must be derated since the MOSFET ratio
was optimized for duty cycles of 10% to 20%.

DESIGN PROCEDURES
POWER LOSS CALCULATIONThe single-phase IR3553 efficiency and power loss
measurement circuit is shown in Figure 32.
The IR3553 power loss is determined by,
PLOSS  VIN  I IN  VCC  IVCC  VSW  I OUT

Where both MOSFET loss and the driver loss are included,
but the PWM controller and the inductor losses are not.

40A Integrated PowIRstage®
C3
1uF

VCC IVCC

IIN
VIN

VCC

PHSFLT#

BOOST

PWM
BBRK#

REFIN

Determine the output voltage normalizing factor with
VOUT=1V, which is 0.90 based on the dashed lines in
Figure 11.

C5
0.22uF

4)

Determine the switching frequency normalizing factor
with ƒSW = 300kHz, which is 0.99 based on the dashedlines in Figure 12.

5)Determine the VCC MOSFET drive voltage normalizing
factor with VCC=5V, which is 1.18 based on the dashedlines in Figure 13.

6)

Determine the inductance normalizing factor with
L=210nH, which is 0.94 based on the dashed lines in
Figure 14.

7)

Multiply the power loss under the default conditions
by the five normalizing factors to obtain the power
loss under the new conditions, which is 4.7W x 1.02 x
0.90 x 0.99 x 1.18 x 0.94 = 4.74W.

C2
47uF x4

L1
150nH

IOUT VOUT
SW

LGND
C7
1nF

3)
VIN

C1
0.22uF

IR3553

R1
10k

CSIN+

R2
2.49k

C6
470uF x3
C4
0.22uF

CSINIOUT

IR3553PGND
VSWFigure 32: IR3553 Power Loss Measurement

Figure 7 shows the measured single-phase IR3553
efficiency under the default test conditions, VIN=12V,
VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V,
TAMBIENT = 25°C, no heat sink, and no air flow.
The efficiency of an interleaved multiphase IR3553
converter is always higher than that of a single-phase
under the same conditions due to the reduced input RMS
current and more input/output capacitors.
The measured single-phase IR3553 power loss under thesame conditions is provided in Figure 8.
If any of the application condition, i.e. input voltage,
output voltage, switching frequency, VCC MOSFET drivervoltage or inductance, is different from those of Figure 8, a
set of normalized power loss curves should be used.
Obtain the normalizing factors from Figure 10 to Figure 14
for the new application conditions; multiply these factors
by the power loss obtained from Figure 8 for the requiredload current.
As an example, the power loss calculation procedures
under different conditions, VIN=10V, VOUT=1V, ƒSW = 300kHz,
VCC=5V, L=210nH, VCC=5V, IOUT=30A, TAMBIENT = 25°C, noheat sink, and no air flow, are as follows.
1)

2)

Determine the power loss at 30A under the default
test conditions of VIN=12V, VOUT=1.2V, ƒSW = 400kHz,
L=150nH, VCC=7V, TAMBIENT = 25°C, no heat sink, and no
air flow. It is 4.7W from Figure 8.
Determine the input voltage normalizing factor with
VIN=10V, which is 1.02 based on the dashed lines in
Figure 10.

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July 16, 2014 | DATASHEET V3.3

THERMAL DERATING
Figure 9 shows the IR3553 thermal derating curve with thecase temperature controlled at or below 125°C. The test
conditions are VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH(0.29mΩ), VCC=7V, TAMBIENT = 0°C to 90°C, with and without
heat sink, and Airflow = 0LFM /100LFM /200LFM /400LFM.
If any of the application condition, i.e. input voltage,
output voltage, switching frequency, VCC MOSFET drivervoltage, or inductance is different from those of Figure 9, a
set of IR3553 case temperature adjustment curves should
be used. Obtain the temperature deltas from Figure 10 to
Figure 14 for the new application conditions; sum thesedeltas and then subtract from the IR3553 casetemperature obtained from Figure 9 for the required load
current.
8)

From Figure 9, determine the maximum current at therequired ambient temperature under the default
conditions, which is 34.5A at 45°C with 0LFM airflow
and the IR3550 case temperature of 125°C.

9)

Determine the case temperature with VIN=10V, which
is +0.6° based on the dashed lines in Figure 10.

10) Determine the case temperature with VOUT=1V, which
is -3.0° based on the dashed lines in Figure 11.
11) Determine the case temperature with ƒSW = 300kHz,
which is -0.4° based on the dashed lines in Figure 12.

40A Integrated PowIRstage®
12) Determine the case temperature with VCC = 5V, whichis +5.4° based on the dashed lines in Figure 13.
13) Determine the case temperature with L=210nH, which
is -1.8° based on the dashed lines in Figure 14.
14) Sum the case temperature adjustment from 9) to 13),+0.6° -3.0° -0.4° +5.4° -1.8° = +0.8°. Add the delta to
the required ambient temperature in step 8), 45°C +(+0.8°C) = 45.8°C, at which the maximum current isreduced to 34A when the allowed junction
temperature is 125°C, as shown in Figure 9. If only
105°C junction temperature is allowed, the required
ambient temperature is equivalent to 45.8°C + (125°C 105°C) = 65.8°C, which indicates 29.5A maximum
current at the 45°C required ambient temperature.

INDUCTOR CURRENT SENSING CAPACITOR CCS
AND RESISTOR RCS
If the IR3553 is used with inductor DCR sensing, care must
be taken in the printed circuit board layout to make a
Kelvin connection across the inductor DCR. The DC
resistance of the inductor is utilized to sense the inductor
current. Usually the resistor RCS and capacitor CCS in parallelwith the inductor are chosen to match the time constant of
the inductor, and therefore the voltage across thecapacitor CCS represents the inductor current.
Measure the inductance L and the inductor DC resistanceRL. Pre-select the capacitor CCS and calculate RCS as follows.
L RL
RCS 
C CS

INPUT CAPACITORS CVINAt least two 10uF 1206 ceramic capacitors and one 0.22uF
0402 ceramic capacitor are recommended for decoupling
the VIN to PGND connection. The 0.22uF 0402 capacitor
should be on the same side of the PCB as the IR3553 andnext to the VIN and PGND pins. Adding additional
capacitance and use of capacitors with lower ESR and
mounted with low inductance routing will improve
efficiency and reduce overall system noise, especially insingle-phase designs or during high current operation.

BOOTSTRAP CAPACITOR CBOOST
A minimum of 0.22uF 0402 capacitor is required for thebootstrap circuit. A high temperature 0.22uF or greater
value 0402 capacitor is recommended. It should be
mounted on the same side of the PCB as the IR3553 and as
close as possible to the BOOST pin. A low-inductance PCB
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July 16, 2014 | DATASHEET V3.3

IR3553routing of the SW pin connection to the other terminal of
the bootstrap capacitor is required to minimize the ringing
between the BOOST and SW pins.

VCC DECOUPLING CAPACITOR CVCC
A 0.22uF to 1uF ceramic decoupling capacitor is required at
the VCC pin. It should be mounted on the same side of the
PCB as the IR3553 and as close as possible to the VCC andPGND (pin 4). Low inductance routing between the VCC
capacitor and the IR3553 pins is required to minimize theringing between the BOOST and SW pins.

BODY-BRAKING® PIN FUNCTION
The BBRK# pin should be pulled up to VCC if the feature is
not used by the PWM controller. Use of a 4.7kΩ resistor ora direct connection to VCC is recommended.

MOUNTING OF HEAT SINKS
Care should be taken in the mounting of heat sinks so as
not to short-circuit nearby components. The VCC andBootstrap capacitors are typically mounted on the sameside of the PCB as the IR3553. The mounting height ofthese capacitors must be considered when selecting theirpackage sizes.

HIGH OUTPUT VOLTAGE DESIGNCONSIDERATIONSThe IR3553 is capable of creating output voltages above
the 3.3V recommended maximum output voltage as there
are no restrictions inside the IR3553 on the duty cycle
applied to the PWM pin. However if the current sensefeature is required, the common mode range of thecurrent sense amplifier inputs must be considered. A
violation of the current sense input common mode range
may cause unexpected IR3553 behavior. Also the output
current rating of the device will be reduced as the duty
cycle increases. In very high duty cycle applications
sufficient time must be provided for replenishment of the
Bootstrap capacitor for the control MOSFET drive.

LAYOUT EXAMPLE
Contact International Rectifier for a layout example
suitable for your specific application.

IR3553

40A Integrated PowIRstage®
METAL AND COMPONENT PLACEMENT Lead land width should be equal to nominal part
lead width. The minimum lead to lead spacing
should be ≥ 0.2mm to prevent shorting.

 Center pad land length and width should beequal to maximum part pad length and width.
 Only 0.30mm diameter via shall be placed in thearea of the power pad lands and connected to
power planes to minimize the noise effect on the
IC and to improve thermal performance.

 Lead land length should be equal to maximum
part lead length +0.15 - 0.3 mm outboard
extension and 0 to + 0.05mm inboard extension.
The outboard extension ensures a large andvisible toe fillet, and the inboard extension willaccommodate any part misalignment andensure a fillet.

23

22

21

20

19

18

17

16
1
15

2

3

4
14
5

24

13
25

12

6

7

8

9

10

11

Figure 33: Metal and component placement* Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format.

18

July 16, 2014 | DATASHEET V3.3

40A Integrated PowIRstage®
SOLDER RESIST The solder resist should be pulled away fromthe metal lead lands by a minimum of 0.06mm.
The solder resist miss-alignment is a maximumof 0.05mm and it is recommended that the low
power signal lead lands are all Non Solder Mask
Defined (NSMD). Therefore pulling the S/R
0.06mm will always ensure NSMD pads.
 The minimum solder resist width is 0.13mm
typical.

 The dimensions of power land pads, VIN, PGND,
TGND and SW, are Non Solder Mask Defined(NSMD). The equivalent PCB layout becomes
Solder Mask Defined (SMD) after power shaperouting.
 Ensure that the solder resist in-between the leadlands and the pad land is ≥ 0.15mm due to thehigh aspect ratio of the solder resist strip
separating the lead lands from the pad land.

 At the inside corner of the solder resist where
the lead land groups meet, it is recommended
to provide a fillet so a solder resist width of ≥0.17mm remains.

Figure 34: Solder resist* Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format.

19

July 16, 2014 | DATASHEET V3.3

IR3553

40A Integrated PowIRstage®

IR3553

STENCIL DESIGN The stencil apertures for the lead lands should beapproximately 65% to 75% of the area of the leadlands depending on stencil thickness. Reducing
the amount of solder deposited will minimize theoccurrence of lead shorts. Since for 0.5mm pitch
devices the leads are only 0.25mm wide, thestencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult
to maintain repeatable solder release.
 The low power signal stencil lead land apertures
should therefore be shortened in length to keeparea ratio of 65% to 75% while centered on leadland.

 The power pads VIN, PGND, TGND and SW, land
pad apertures should be approximately 65% to
75% area of solder on the center pad. If too muchsolder is deposited on the center pad the part will
float and the lead lands will be open. Solder
paste on large pads is broken down into small
sections with a minimum gap of 0.2mm between
allowing for out-gassing during solder reflow.
 The maximum length and width of the land pad
stencil aperture should be equal to the solder
resist opening minus an annular 0.2mm pull backto decrease the incidence of shorting the center
land to the lead lands when the part is pushed
into the solder paste.

Figure 35: Stencil design* Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format.
20

July 16, 2014 | DATASHEET V3.3

40A Integrated PowIRstage®
MARKING INFORMATION

Site/Date/Marking Code
Lot Code

3553M
?YWW?
xxxx

Figure 36: PQFN 4mm x 6mm

PACKAGE INFORMATION

Figure 37: PQFN 4mm x 6mm
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July 16, 2014 | DATASHEET V3.3

IR3553

40A Integrated PowIRstage®

IR3553

Data and specifications subject to change without notice.
This product will be designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com

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