NXP Semiconductors
Technical Data

Document Number: MC33912
Rev. 10.0, 8/2016

LIN system basis chip with dc motor
pre-driver and current sense

33912

The 33912G5/BAC is a Serial Peripheral Interface (SPI) controlled System Basis
Chip (SBC), combining many frequently used functions in an MCU based
system, plus a Local Interconnect Network (LIN) transceiver. The 33912 has a
5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting
features. The device provides full SPI readable diagnostics and a selectabletiming watchdog for detecting errant operation. The LIN Protocol Specification
2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry which can bedisabled for higher data rates.
Two 50 mA/60 mA high-side switches and two 150 mA/160 mA low-side
switches with output protection are available. All outputs can be pulse-widthmodulated (PWM). Four high voltage inputs are available for use in contact
monitoring, or as external wake-up inputs. These inputs can be used as highvoltage Analog Inputs. The voltage on these pins is divided by a selectable ratio
and available via an analog multiplexer.
The 33912 has three main operating modes: Normal (all functions available),
Sleep (VDD off, wake-up via LIN, wake-up inputs (L1-L4), cyclic sense and forced
wake-up), and Stop (VDD on with limited current capability, wake-up via CS, LIN
bus, wake-up inputs, cyclic sense, forced wake-up and external reset).
The 33912 is compatible with LIN Protocol Specification 2.0, 2.1, and SAEJ26022. This device is powered using SMARTMOS technology.
Features• Full-duplex SPI interface at frequencies up to 4.0 MHz• LIN transceiver capable of up to 100 kbps with wave shaping• Current sense module• Four high voltage analog/logic Inputs• Configurable window watchdog• Switched/protected 5.0 V output (used for Hall sensors)• Two 50 mA high-side and two 150 mA/160 mA low-side protected switches• 5.0 V low drop regulator with fault detection and low voltage reset (LVR)
circuitry

SYSTEM BASIS CHIP WITH LIN
2ND GENERATIONAC SUFFIX (Pb-FREE)
98ASH70029A
32-PIN LQFP

Applications• Door module: window• Lift, mirror, door lock, seat control switch• Seat position motors, occupancy sensor• Rain and light sensor, light control, sun roof
• Wiper, turning light, cruise control• Climate: small motors, control panel• Engine control: sensors, small motors

33912

VBAT

VSENSE
HS1

VS1
VS2

LIN INTERFACE

L1
L2
L3
L4

LIN
VDD

LGND
PGND
AGND

MCU

PWMIN
ADOUT0ADOUT1
MOSI
MISO
SCLK
CS
RXD
TXD
IRQ
RST

LS1
M

LS2
ISENSEHISENSELHVDD
HS2
WDCONF

Figure 1. 33912 simplified application diagram© 2016 NXP B.V.

MC33912G5AC / MC34912G5AC

1Orderable parts

The 33912G5 data sheet is within MC33912G5 product specifications, Pages 3 to 52
The 33912BAC data sheet is within MC33912BAC product specifications, Pages 53 to 103
Table 1. Orderable part variations
Part number (1)MC33912G5AC

MC34912G5AC

Temperature (TA)

Package

Generation-40 to 125 °C-40 to 85 °C

Changes
1. Increase ESD Gun IEC61000-4-2 (gun test contact with 150 pF,
330 ohm test conditions) performance to achieve ±6.0 kV min on the
LIN pin.

2.5
32-LQFP

2. Immunity against ISO7637 pulse 3b
3. Reduce EMC emission level on LIN
4. Improve EMC immunity against RF - target new specification including
3x68pF
5. Comply with J2602 conformance test

MC33912BAC-40 to 125 °C

MC34912BAC-40 to 85 °C

2.0

Initial release

Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.

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NXP Semiconductors

MC33912G5AC / MC34912G5AC

2MC33912G5 product specifications, Pages 3 to 52

33912

NXP Semiconductors

3

MC33912G5AC / MC34912G5AC

3Internal block diagram
VS2

INTERRUPT CONTROLMODULE
LVI, HVI,ALL OT (VDD,HS,LS,LIN,SD)RESET CONTROLMODULE
LVR, WD, EXT ΜCVS1INTERNAL BUS

RST IRQ

VDD

AGND
VOLTAGE REGULATOR

5.0 V OUTPUT
MODULE

HVDD
LS1

LOW-SIDE
CONTROL
MODULEWINDOW
WATCHDOG
MODULE

LS2

PWMIN

PGND
VS2

MISO

SCLK

SPI
&
CONTROL

VS2

HS1

HS2
ANALOG MULTIPLEXERMOSI

HIGH-SIDECONTROL
MODULECS
ADOUT0

WAKE-UP MODULE

VBATSENSE MODULEVSENSECHIP TEMPERATURESENSE MODULEANALOG INPUTMODULE

L1
L2
L3

RXD
TXD

DIGITAL INPUT MODULE

LIN PHYSICAL
LAYER

L4

LIN

ISENSEH
CURRENT SENSE MODULEISENSELLGND

WDCONFADOUT1Figure 2. 33912 simplified internal block diagram

33912

4

NXP Semiconductors

HVDD

VSENSE

NC

VS1

VS2

HS1

30

29

28

27

26

25

Pinout diagram

VDD

4.1

31

Pin connections

AGND

4

32

MC33912G5AC / MC34912G5AC

L1

MISO

3

22

L2

MOSI

4

21

L3

SCLK

5

20

L4

CS

6

19

LS1

ADOUT0

7

18

PGND

PWMIN

8

17

LS2

11

12

13

14

15

16

RST

10

9

ISENSEH

23

ISENSEL

2

LGND

TXD

LIN

HS2

WDCONF

24

ADOUT1

1

IRQ

RXD

Figure 3. 33912 pin connections
A functional description of each pin can be found in the Functional pin description section beginning on page 23.
Table 2. 33912 pin definitions
Pin

Pin name

Formal nameDefinition

1

RXD

Receiver Output

This pin is the receiver output of the LIN interface which reports the state of the bus
voltage to the MCU interface.

2

TXD

Transmitter Input

This pin is the transmitter input of the LIN interface which controls the state of the bus
output.

3MISO

SPI Output

SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the highimpedance state.

4

MOSI

SPI Input

SPI (Serial Peripheral Interface) data input.

5

SCLK

SPI Clock

SPI (Serial Peripheral Interface) clock Input.

6

CS

SPI Chip Select

7

ADOUT0

Analog Output Pin 0

8

PWMIN

PWM Input

9

RSTInternal Reset I/O

SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
Analog Multiplexer Output.
High-side and Low-side Pulse Width Modulation Input.
Bidirectional Reset I/O pin - driven low when any internal reset source is asserted. RST
is active low.

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NXP Semiconductors

5MC33912G5AC / MC34912G5AC

Table 2. 33912 pin definitions (continued)
Pin

Pin name

Formal nameDefinition

10

IRQ

Internal Interrupt
OutputInterrupt output pin, indicating wake-up events from Stop mode or events from Normal
and Normal request modes. IRQ is active low.

11

ADOUT1

Analog Output Pin 1

Current sense analog output.

12

WDCONF

Watchdog
Configuration Pin

This input pin is for configuration of the watchdog period and allows the disabling of thewatchdog.

13

LIN

LIN Bus14

LGND

LIN Ground Pin

This pin represents the single-wire bus transmitter and receiver.

15
16

ISENSELISENSEH

Current Sense Pins

Current Sense differential inputs.

17
19

LS2
LS1

Low-side Outputs

Relay drivers low-side outputs.

18

PGND

Power Ground Pin

This pin is the device low-side ground connection. It is internally connected to the LGND
pin.

20
21
22
23

L4
L3
L2
L1

Wake-up Inputs

These pins are the wake-up capable digital inputs(2). In addition, all Lx inputs can besensed analog via the analog multiplexer.

24
25

HS2
HS1

High-side Outputs

High-side switch outputs.

26
27

VS2
VS1

Power Supply Pin

These pins are device battery level power supply pins. VS2 is supplying the HSx drivers
while VS1 supplies the remaining blocks.(3)28NC

Not Connected

This pin can be left open or connected to any potential ground or power supply.

29

VSENSE

Voltage Sense Pin

Battery voltage sense input.(4)

30

HVDD

Hall Sensor Supply
Output+5.0 V switchable supply output pin.(5)

31

VDD

Voltage Regulator
Output+5.0 V main voltage regulator output pin.(6)

32

AGND

Analog Ground Pin

This pin is the device analog ground connection.

This pin is the device LIN ground connection. It is internally connected to the PGND pin.

Notes
2. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.
3. Reverse battery protection series diodes must be used externally to protect the internal circuitry.
4. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It
is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.
5. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.
6. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required.

33912

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NXP Semiconductors

MC33912G5AC / MC34912G5AC

5Electrical characteristics

5.1

Maximum ratings

Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
SymbolRatings

Value

Unit

Supply Voltage at VS1 and VS2• Normal Operation (DC)• Transient Conditions (load dump)-0.3 to 27-0.3 to 40

V

VDD

Supply Voltage at VDD-0.3 to 5.5

V

VIN

Input / Output Pins Voltage• CS, RST, SCLK, PWMIN, ADOUT0, ADOUT1, MOSI, MISO, TXD, RXD,
HVDD
• Interrupt Pin (IRQ)-0.3 to VDD +0.3
-0.3 to 11

V

VHS

HS1 and HS2 Pin Voltage (DC)- 0.3 to VSUP +0.3

V

VLS

LS1 and LS2 Pin Voltage (DC)-0.3 to 45

V

VLxDC
VLxTR

L1, L2, L3 and L4 Pin Voltage• Normal Operation with a series 33 k resistor (DC)• Transient input voltage with external component (according to ISO7637-2)(See Figure 5, page 19)-18 to 40±100

V

VISENSEISENSEH and ISENSEL Pin Voltage (DC)-0.3 to 40

V

VVSENSEVSENSE Pin Voltage (DC)-27 to 40

V

VBUSDCVBUSTR

LIN Pin Voltage• Normal Operation (DC)• Transient input voltage with external component (according to ISO7637-2)(See Figure 4, page 19)-18 to 40-150 to 100

V

IVDD

VDD output current

Internally Limited

A

Notes

Electrical ratings
VSUP(SS)
VSUP(PK)

VIN(IRQ)

(7)
(8)

Notes
7. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.
8. Extended voltage range for programming purpose only.

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NXP Semiconductors

7MC33912G5AC / MC34912G5AC

Table 3. Maximum ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
SymbolRatings

Value

Unit

Notes

ESD Capability• AECQ100• Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω)
VESD1-1
VESD1-2
VESD1-3• LIN Pin
• L1, L2, L3, and L4• all other Pins
• Charge Device Model - JESD22/C101 (CZAP = 4.0 pF)± 8.0k
± 6.0k±2000

VESD2-1
VESD2-2• Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)• All other Pins (Pins 2-7, 10-15, 18-23, 26-31)• According to LIN Conformance Test Specification / LIN EMC Test
Specification, August 2004 (CZAP = 150 pF, RZAP = 330 Ω)

± 750
± 500
V

VESD3-1
VESD3-2
VESD3-3
VESD3-4• Contact Discharge, Unpowered• LIN pin with 220 pF• LIN pin without capacitor• VS1/VS2 (100 nF to ground)• Lx inputs (33 kΩ serial resistor)• According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω)

± 20k
± 11k
>± 12k±6000

VESD4-1
VESD4-2
VESD4-3• Unpowered• LIN pin with 220 pF and without capacitor• VS1/VS2 (100 nF to ground)• Lx inputs (33 kΩ serial resistor)± 8000± 8000± 8000

Thermal ratings
TA

Operating Ambient Temperature
33912
34912

-40 to 125-40 to 85

°C

(9)

TJ

Operating Junction Temperature-40 to 150

°C

TSTG

Storage Temperature-55 to 150

°C

RθJA

Thermal Resistance, Junction to Ambient
Natural Convection, Single Layer board (1s)Natural Convection, Four Layer board (2s2p)

85
56

°C/W

(9), (10)RθJC

Thermal Resistance, Junction to Case

23

°C/W

(12)

TPPRT

Peak Package Reflow Temperature During Reflow

Note 14°C(13), (14)(9), (11)

Notes
9.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

10.
11.
12.
13.

Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature andMoisture Sensitivity Levels (MSL), go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view allorderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

14.

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NXP Semiconductors

MC33912G5AC / MC34912G5AC

5.2

Static electrical characteristics

Table 4. Static electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

Supply voltage range (VS1, VS2)
VSUP

Nominal Operating Voltage

5.5

–

18

V

VSUPOP

Functional Operating Voltage

–

–

27

V

VSUPLD

Load Dump

–

–

40

V

–

4.5

10

mA

(16)

–
–
–

47
62
180

80
90
400

µA

(16), (17),(18), (19)

–
–
–

27
33
160

35
48
300

µA

(16), (18)

–

10

–

µA

(20)

1.5
–

3.0
0.9

3.9
–

V

(21), (20)

VSUP Undervoltage Detection (VSUV Flag) (Normal and Normal
Request Modes, Interrupt Generated)• Threshold (measured on VS1)
• Hysteresis (measured on VS1)

5.55
–

6.0
0.2

6.6
–

VSUP Overvoltage Detection (VSOV Flag) (Normal and Normal
Request Modes, Interrupt Generated)• Threshold (measured on VS1)
• Hysteresis (measured on VS1)

18
–

19.25
1.0

20.5
–

(15)

Supply current range (VSUP = 13.5 V)
IRUN

ISTOP

Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State
Stop Mode, VDD ON with IOUT = 100 µA, LIN Recessive State• 5.5 V < VSUP < 12 V
• VSUP = 13.5 V• 13.5 V < VSUP < 18 V

ISLEEPICYCLIC

Sleep Mode, VDD OFF, LIN Recessive State• 5.5 V < VSUP < 12 V
• VSUP = 13.5 V• 13.5 V ≤ VSUP < 18 V
Cyclic Sense Supply Current Adder

Supply under/overvoltage detections
Power-On Reset (BATFAIL)
VBATFAIL• Threshold (measured on VS1)VBATFAIL_HYS

VSUV

VSUV_HYSVSOVVSOV_HYS• Hysteresis (measured on VS1)

V

V

Notes
15. Device is fully functional. All features are operating.
16. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.
17.

Total IDD current (including loads) below 100 µA.

18.

Stop and Sleep Modes current increases if VSUP exceeds13.5 V.

19.
20.
21.

This parameter is guaranteed after 90 ms.
This parameter is guaranteed by process monitoring but not production tested.
The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.

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NXP Semiconductors

9MC33912G5AC / MC34912G5AC

Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

Voltage regulator (22) (VDD)
VDDRUN

Normal Mode Output Voltage• 1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V

4.75

5.00

5.25

V

IVDDRUN

Normal Mode Output Current Limitation

60

110

200

mA

VDDDROP

Dropout Voltage• IVDD = 50 mA

–

0.1

0.25

V

VDDSTOP

Stop Mode Output Voltage• IVDD < 5.0 mA

4.75

5.0

5.25

V

IVDDSTOP

Stop Mode Output Current Limitation

6.0

13

36

mA

–
–

–
–

25
25

mV

–
–

–
–

80
50

mV

LRRUN
LRSTOPLDRUNLDSTOPLine Regulation• Normal Mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA• Stop Mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA
Load Regulation• Normal Mode, 1.0 mA < IVDD < 50 mA• Stop Mode, 0.1 mA < IVDD < 5.0 mA

(23)

TPRE

Overtemperature Prewarning (Junction)• Interrupt generated, VDDOT Bit Set

90

115

140

°C

(24)

TPRE_HYS

Overtemperature Prewarning Hysteresis

–

13

–

°C

(24)

Overtemperature Shutdown Temperature (Junction)

150

170

190

°C

(24)

Overtemperature Shutdown Hysteresis

–

13

–

°C

(24)

VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100%
• IHVDD = 15 mA

-2.0

–

2.0

%

Current Limitation

20

35

50

mA

HVDDDROP

Dropout Voltage• IHVDD = 15 mA; IVDD = 5.0 mA

–

160

300

mV

LRHVDDLine Regulation• IHVDD = 5.0 mA; IVDD = 5.0 mA

–

–

40

mV

LDHVDD

Load Regulation• 1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA

–

–

20

mV

TSD
TSD_HYSHall sensor supply output (25) (HVDD)HVDDACC
IHVDD

Notes
22. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.
23. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).
24. This parameter is guaranteed by process monitoring but not production tested.
25. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

33912

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NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

VDD Low Voltage Reset Threshold

4.3

4.5

4.7

V

VOL

Low-state Output Voltage• IOUT = 1.5 mA; 3.5 V ≤ VSUP ≤ 27 V

0.0

–

0.9

V

IOH

High-state Output Current (0 V < VOUT < 3.5 V)

-150

-250

-350

µA

IPD_MAX

Pull-down Current Limitation (internally limited)
VOUT = VDD

1.5

–

8.0

mA

VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

V

Notes

RST input/output pin (RST)VRSTTHMISO SPI output pin (MISO)
VOL

Low-state Output Voltage• IOUT = 1.5 mA

0.0

–

1.0

V

VOH

High-state Output Voltage• IOUT = -250 µA

VDD -0.9

–

VDD

V

ITRIMISO

Tri-state Leakage Current• 0 V ≤ VMISO ≤ VDD

-10

–

10

µA

SPI input pins (MOSI, SCLK, CS)
VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

V

IIN

MOSI, SCLK Input Current• 0 V ≤ VIN ≤ VDD

-10

–

10

µA

CS Pull-up Current• 0 V < VIN < 3.5 V

10

20

30

µA

IPUCS

Interrupt output pin (IRQ)
VOL

Low-state Output Voltage• IOUT = 1.5 mA

0.0

–

0.8

V

VOH

High-state Output Voltage• IOUT = -250 µA

VDD -0.8

–

VDD

V

IOUT

Leakage Current• VDD ≤ VOUT ≤ 10 V

–

–

2.0

mA

Pulse width modulation input pin (PWMIN)
VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

V

IPUPWMIN

Pull-up current• 0 V < VIN < 3.5 V

10

20

30

µA

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MC33912G5AC / MC34912G5AC

Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

–
–
–

–
–
–

7.0
10
14

Unit

Notes

Ω

(26)

High-side outputs HS1 and HS2 Pins (HS1, HS2)RDS(on)Output Drain-to-Source On Resistance• TJ = 25 °C, ILOAD = 50 mA; VSUP > 9.0 V• TJ = 150 °C, ILOAD = 50 mA; VSUP > 9.0 V• TJ = 150 °C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V

ILIMHSX

Output Current Limitation• 0 V < VOUT < VSUP - 2.0 V

60

90

250

mA

(27)

IOLHSX

Open Load Current Detection

–

5.0

7.5

mA

(28)

ILEAK

Leakage Current• -0.2 V < VHSX < VS2 + 0.2 V

–

–

10

µA

VTHSC

Short-circuit Detection Threshold• 5.5 V < VSUP < 27 V

VSUP -2.0

–

–

V

(29)

THSSD

Overtemperature Shutdown

140

160

180

°C

(30), (34)Overtemperature Shutdown Hysteresis

–

10

–

°C

(34)

–
–
–

–
–
–

2.5
4.5
10

THSSD_HYS

Low-side outputs LS1 and LS2 Pins (LS1, LS2)RDS(on)Output Drain-to-Source On Resistance• TJ = 25 °C, ILOAD = 150 mA, VSUP > 9.0 V• TJ = 125 °C, ILOAD = 150 mA, VSUP > 9.0 V• TJ = 125 °C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V

ΩILIMLSX

Output Current Limitation• 2.0 V < VOUT < VSUP

160

275

350

mA

(31)

IOLLSX

Open Load Current Detection

–

7.5

12

mA

(32)

ILEAK

Leakage Current• -0.2 V < VOUT < VS1

–

–

10

µA

VCLAMP

Active Output Energy Clamp• IOUT = 150 mA

VSUP +2.0–

VSUP +5.0

V

VTHSC

Short-circuit Detection Threshold• 5.5 V < VSUP < 27 V

2.0

–

–

V

(29)

TLSSD

Overtemperature Shutdown

140

160

180

°C

(33), (34)Overtemperature Shutdown Hysteresis

–

10

–

°C

TLSSD_HYS

Notes
26. This parameter is production tested up to TA = 125 °C, and guaranteed by process monitoring up to TJ = 150 °C.
27.
28.
29.
30.
31.
32.
33.
34.

When overcurrent occurs, the corresponding high-side stays ON with limited current capability and the HSxCL flag is set in the HSSR.
When open load occurs, the flag (HSxOP) is set in the HSSR.
HS and LS automatically shutdown if HSOT or LSOT occurs or if the HVSE flag is enabled and an overvoltage occurs.
When overtemperature shutdown occurs, both high-sides are turned off. All flags in HSSR are set.
When overcurrent occurs, the corresponding low-side stays ON with limited current capability and the LSxCL flag is set in the LSSR.
When open load occurs, the flag (LSxOP) is set in the LSSR.
When overtemperature shutdown occurs, both low-sides are turned off. All flags in LSSR are set.
Guaranteed by characterization but not production tested

33912

12

NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

L1, L2, L3 and L4 input pins (L1, L2, L3, L4)
VTHL

Low Detection Threshold• 5.5 V < VSUP < 27 V

2.0

2.5

3.0

V

(35)

VTHH

High Detection Threshold• 5.5 V < VSUP < 27 V

3.0

3.5

4.0

V

(35)

VHYS

Hysteresis• 5.5 V < VSUP < 27 V

0.4

0.8

1.4

V

(35)

IIN

Input Current• -0.2 V < VIN < VS1

-10

–

10

µA

(36)

RLXIN

Analog Input Impedance

800

1300

2000

kΩ

(37)

Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0)• LXDS (Lx Divider Select) = 0• LXDS (Lx Divider Select) = 1

0.95
3.42

1.0
3.6

1.05
3.78

VRATIOLx-OFFSET

Analog Output offset Ratio• LXDS (Lx Divider Select) = 0• LXDS (Lx Divider Select) = 1

-80
-22

6.0
2.0

80
22

mV

LXMATCHING

Analog Inputs Matching• LXDS (Lx Divider Select) = 0• LXDS (Lx Divider Select) = 1

96
96

100
100

104
104

%

RATIOLX

Window watchdog configuration pin (WDCONF)(38)
REXT

External Resistor Range

20

–

200

kΩ

WDACC

Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)

-15

–

15

%

2.0
2.8
3.6

3.0
-

2.8
3.6
4.6

Temperature Sense Analog Output Voltage per characterization• TA = 25 °C

3.1

3.15

3.2

V

STTOV

Internal Chip Temperature Sense Gain

9.0

10.5

12

mV/K

STTOV_3T

Internal Chip Temperature Sense Gain per characterization at 3
temperatures. See Figure 16, Temperature sense gain

9.9

10.2

10.5

mV/K

RATIOVSENSEVSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0)• 5.5 V < VSUP < 27 V

5.0

5.25

5.5

RATIOVSENSECZVSENSE Input Divider Ratio (RATIOVSENSE=VSENSE/VADOUT0) per
characterization• 5.5 <VSUP< 27 V

5.15

5.25

5.35

(39)

Analog multiplexer

VADOUT0_TEMPVADOUT0_25

Temperature Sense Analog Output Voltage• TA = -40 °C• TA = 25 °C• TA = 125 °C

V

(40)

(40)

(40)

Notes
35. The unused Lx pins must be connected to ground.
36. Analog multiplexer input disconnected from Lx input pin.
37. Analog multiplexer input connected to Lx input pin.
38. For VSUP 4.7 V to 18 V
39.

Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)40.

These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed byproduction test.

33912

NXP Semiconductors

13

MC33912G5AC / MC34912G5AC

Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

VSENSE Output Related Offset

-30

-10

30

mV

VSENSE Output Related Offset per characterization

-30

-12.6

0

mV

Notes

Analog multiplexer (continued)
OFFSETVSENSE
OFFSETVSENSE_C
Z(41)

Analog outputs (ADOUT0 and ADOUT1)
VOUT_MAX

Maximum Output Voltage• -5.0 mA < IO < 5.0 mA

VDD -0.35

–

VDD

V

VOUT_MIN

Minimum Output Voltage• -5.0 mA < IO < 5.0 mA

0.0

–

0.35

V

Current sense amplifier (ISENSEH, ISENSEL)GGain• CSGS (Current Sense Gain Select) = 0• CSGS (Current Sense Gain Select) = 1

29
14

30
14.5

31
15

DIFF

Differential Input Impedance• CSGS (Current Sense Gain Select) = 0• CSGS (Current Sense Gain Select) = 1

2.0
5.0

10
20

30
50

kΩ

CM

Common Mode Input Impedance• CSGS (Current Sense Gain Select) = 0• CSGS (Current Sense Gain Select) = 1

100
100

–
–

200
200

kΩ

VIN

ISENSEH, ISENSEL Input Voltage Range

-0.2

–

3.0

V

VIN_OFFSET

Input Offset Voltage• CSAZ (Current Sense Auto Zero) = 0• CSAZ (Current Sense Auto Zero) = 1

-15
-2.0

–
–

15
2.0

mV

RxD output pin (LIN physical layer) (RxD)
VOL

Low-state Output Voltage• IOUT = 1.5 mA

0.0

–

0.8

V

VOH

High-state Output Voltage• IOUT = -250 µA

VDD -0.8

–

VDD

V

TXD input pin (LIN physical layer) (TXD)
VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

VIPUIN

Pin Pull-up Current, 0 V < VIN < 3.5 V

10

20

30

µA

5.0

-

6.0

V

-

400

-

mV

LIN physical layer with J2602 feature enabled (bit DIS_J2602 = 0)
VTH_UNDER_VOLTA LIN Undervoltage threshold• Positive and Negative threshold (VTHP, VTHN)GEVJ2602_DEG

Hysteresis (VTHP - VTHN)

Notes
41. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed byproduction test.

33912

14

NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

LIN physical layer, transceiver (LIN)(42)
VBAT

Operating Voltage Range

8.0

-

18

V

VSUP

Supply Voltage Range

7.0

-

18

V

Voltage Range within which the device is not destroyed

-0.3

-

40

V

Current Limitation for Driver Dominant State• Driver ON, VBUS = 18 V

40

90

200

mA

IBUS_PAS_DOM

Input Leakage Current at the receiver• Driver off; VBUS = 0 V; VBAT = 12 V

-1.0

–

–

mA

IBUS_PAS_REC

Leakage Output Current to GND• Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥
VBAT

–

–

20

µA

IBUS_NO_GND

Control unit disconnected from ground• GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V

-1.0

–

1.0

mA

(43)

IBUSNO_BAT

VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V

–

–

100

µA

(44)

VBUSDOM

Receiver Dominant State

–

–

0.4

VSUP

VBUSREC

Receiver Recessive State

0.6

–

–

VSUP

VBUS_CNT

Receiver Threshold Center• (VTH_DOM + VTH_REC)/2

0.475

0.5

0.525

VSUP

VHYS

Receiver Threshold Hysteresis• (VTH_REC - VTH_DOM)

–

–

0.175

VSUP

VSERDIODE

Voltage Drop at the serial Diode in pull-up path

0.4

1.0

V

VSHIFT_BAT

VBAT_SHIFT

0

11.5%

VBAT

VSHIFT_GND

GND_SHIFT

0

11.5%

VBAT

5.3

5.8

V

VSUP_NON_OP
IBUS_LIM

VBUSWU

LIN Wake-up threshold from Stop or Sleep mode

RSLAVE

LIN Pull-up Resistor to VSUP

20

30

60

kΩ

TLINSD

Overtemperature Shutdown

140

160

180

°C

Overtemperature Shutdown Hysteresis

–

10

–

°C

TLINSD_HYS

(45)

(46)

Notes
42. Parameters guaranteed for 7.0 V ≤ VSUP ≤ 18 V.
43.
44.
45.
46.

Loss of local ground must not affect communication in the residual network.
Node has to sustain the current which can flow under this condition. Bus must remain operational under this condition.
This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, NXP does notguarantee this parameter during the product's life time.
When overtemperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.

33912

NXP Semiconductors

15

MC33912G5AC / MC34912G5AC

5.3

Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

SPI interface timing (see Figure 13, page 22)
f SPIOPSPI Operating Frequency

–

–

4.0

MHz

tPSCLKSCLK Clock Period

250

–

N/A

ns

tWSCLKH

SCLK Clock High Time

110

–

N/A

ns

(47)

tWSCLKLSCLK Clock Low Time

110

–

N/A

ns

(47)

tLEAD

Falling Edge of CS to Rising Edge of SCLK

100

–

N/A

ns

(47)

tLAG

Falling Edge of SCLK to CS Rising Edge

100

–

N/A

ns

(47)

tSISU

MOSI to Falling Edge of SCLK

40

–

N/A

ns

(47)

tSIH

Falling Edge of SCLK to MOSI

40

–

N/A

ns

(47)

tRSO

MISO Rise Time• CL = 220 pF

–

40

–

ns

(47)

tFSO

MISO Fall Time• CL = 220 pF

–

40

–

ns

(47)

Time from Falling or Rising Edges of CS to:- MISO Low-impedance- MISO High-impedance

0.0
0.0

–
–

50
50

ns

(47)

Time from Rising Edge of SCLK to MISO Data Valid• 0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100 pF

0.0

–

75

ns

(47)

t RST

Reset Low-level Duration After VDD High (see Figure 12, page 22)

0.65

1.0

1.35

ms

t RSTDF

Reset Deglitch Filter Time

350

480

900

ns

8.5
79
110

10
94
150

11.5
108
205

tSOEN
tSODIStVALIDRST output pin

Window watchdog configuration pin (WDCONF)

t PWD

Watchdog Time Period• External Resistor REXT = 20 kΩ (1%)• External Resistor REXT = 200 kΩ (1%)• Without External Resistor REXT (WDCONF Pin Open)

ms

(48)

Current sense amplifier(47)CMR

Common Mode Rejection Ratio

70

–

–

dB

SVR

Supply Voltage Rejection Ratio

60

–

–

dB

GBP

Gain Bandwidth Product

0.75

3.0

–

MHz

SR

Output Slew-Rate

0.5

–

–

V/µs

(49)

Notes
47. This parameter is guaranteed by process monitoring but not production tested.
48. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)49.

Analog Outputs are supplied by VDD and from 100 Hz to 4.0 kHz

33912

16

NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 5. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

8.0

20

38

μs

(50)

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop
Command) and Stop Mode Activation

–

–

5.0

μs

(50)

Normal Request Mode Timeout (see Figure 12, page 22)

110

150

205

ms

Cyclic Sense ON Time from Stop and Sleep mode

130

200

270

µs

(51)

Cyclic Sense Accuracy

-35

+35

%

(50)

t S-ON

Delay Between the SPI Command and HS /LS Turn On• 9.0 V < VSUP < 27 V

–

–

10

μs

(52)

t S-OFF

Delay Between the SPI Command and HS /LS Turn Off• 9.0 V < VSUP < 27 V

–

–

10

μs

(52)

t SNR2N

Delay Between Normal Request and Normal mode After a Watchdog
Trigger Command (Normal Request Mode)

–

–

10

μs

(50)

t WUCSt WUSPI

Delay Between CS Wake-up (CS LOW to HIGH) in Stop mode and:• Normal Request mode, VDD ON and RST HIGH
• First Accepted SPI Command

9.0
90

15
—

80
N/A

μs

t 2CS

Minimum Time Between Rising and Falling Edge on the CS

4.0

—

—

μs

VSUP Deglitcher• (DIS_J2602 = 0)

35

50

70

μs

L1, L2, L3 and L4 inputs
t WUF

Lx Filter Time Deglitcher

State machine timingt STOPt NR TOUT
TON

J2602 deglitcher

tJ2602_DEG(53)

LIN physical layer: driver characteristics for normal slew rate - 20.0 kbit/sec according to lin physical layer specification(54), (55)D1

Duty Cycle 1:• THREC(MAX) = 0.744 * VSUP
• THDOM(MAX) = 0.581 * VSUP
• D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V

D2

0.396

—

—

—

—

0.581

Duty Cycle 2:• THREC(MIN) = 0.422 * VSUP
• THDOM(MIN) = 0.284 * VSUP
• D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V

Notes
50. This parameter is guaranteed by process monitoring but not production tested.
51. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, NXP does notguarantee this parameter during the product's life time.
52. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to external load.
53. This parameter has not been monitoring during operating life test.
54. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal thresholddefined at each parameter.
55. See Figure 7, page 20.

33912

NXP Semiconductors

17

MC33912G5AC / MC34912G5AC

Table 5. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

LIN physical layer: driver characteristics for slow slew rate - 10.4 kbit/sec according to lin physical layer specification(56), (57)

D3

Duty Cycle 3:• THREC(MAX) = 0.778 * VSUP
• THDOM(MAX) = 0.616 * VSUP
• D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V

D4

0.417

—

—

—

—

0.590

—

20

—

Duty Cycle 4:• THREC(MIN) = 0.389 * VSUP
• THDOM(MIN) = 0.251 * VSUP
• D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V

LIN physical layer: driver characteristics for fast slew rate
SRFAST

LIN Fast Slew Rate (Programming mode)V / μs

LIN physical layer: characteristics and wake-up timings(58)
—

4.2

6.0

t REC_SYM

Propagation Delay and Symmetry• Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR,
tREC_PDF)• Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR

- 2.0

—

2.0

t PROPWLBus Wake-up Deglitcher (Sleep and Stop modes)

42

70

Bus Wake-Up Event Reported• From Sleep Mode
• From Stop Mode—
9.0

TXD Permanent Dominant State Delayt REC_PDt WAKE_SLEEPt WAKE_STOPt TXDDOM

μs

(59)

95

μs

(60), (64)
(61)

—
27

1500
35

μs

(62)

0.65

1.0

1.35

s

-

10

-

kHz

(63)

Pulse width modulation input pin (PWMIN)fPWMINPWMIN pin
• Max. frequency to drive HS and LS output pins

(64)

Notes
56. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal thresholddefined at each parameter. See Figure 6, page 20.
57. See Figure 8, page 20.
58. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to
LIN signal threshold defined at each parameter. See Figure 6, page 20.
59. See Figure 9, page 21
60. See Figure 10, page 21 for Sleep and Figure 11, page 21 for Stop mode.
61. This parameter is tested on automatic tester but has not been monitoring during operating life test.
62. The measurement is done with 1.0 µF capacitor and 0mA current load on VDD. The value takes into account the delay to charge the capacitor. The
delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V. See Figure 10, page 21.
The delay depends of the load and capacitor on VDD.
63.

In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11, page 21.

64.

This parameter is guaranteed by process monitoring but not production tested.

33912

18

NXP Semiconductors

MC33912G5AC / MC34912G5AC

5.4

Timing diagrams
33912
1.0 nF

LIN

TRANSIENT PULSE
GENERATOR(NOTE)GND

PGND LGND

AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

Figure 4. Test circuit for transient test pulses (LIN)
33912
Transient Pulse
Generator(Note)

1.0 nF
L1, L2, L3, L4
10 kΩ

GND

PGND LGND AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.

Figure 5. Test circuit for transient test pulses (Lx)
VSUP

TXD

LIN

R0

RXD
C0

R0 AND C0 COMBINATIONS:• 1.0 KΩ and 1.0 nF• 660 Ω and 6.8 nF• 500 Ω and 10 nF

Figure 6. Test circuit for LIN timing measurements

33912

NXP Semiconductors

19

MC33912G5AC / MC34912G5AC

TXD

VLIN_REC
THREC(MAX)

74.4% VSUPTHDOM(MAX)

58.1% VSUP

tBIT

tBIT

tBUS_DOM(MAX)tBUS_REC(MIN)
Thresholds ofreceiving node 1

LIN
THREC(MIN)
THDOM(MIN)

Thresholds ofreceiving node 2

42.2% VSUP
28.4% VSUPtBUS_DOM(MIN)tBUS_REC(MAX)RXD
Output of receiving Node 1
tREC_PDF(1)tREC_PDR(1)RXD
Output of receiving Node 2
tREC_PDF(2)tREC_PDR(2)Figure 7. LIN timing measurements for normal slew rate

TXD

VLIN_REC
THREC(MAX)

77.8% VSUPTHDOM(MAX)

61.6% VSUP

tBIT

tBIT

tBUS_DOM(MAX)tBUS_REC(MIN)
Thresholds ofreceiving node 1

LIN
THREC(MIN)
THDOM(MIN)

Thresholds ofreceiving node 2

38.9% VSUP
25.1% VSUPtBUS_DOM(MIN)tBUS_REC(MAX)RXD
Output of receiving Node 1
tREC_PDF(1)tREC_PDR(1)RXD
Output of receiving Node 2
tREC_PDR(2)tREC_PDF(2)Figure 8. LIN timing measurements for slow slew rate

33912

20

NXP Semiconductors

MC33912G5AC / MC34912G5AC

VLIN_REC
VBUSREC

0.6% VSUP

VBUSDOM

0.4% VSUP

VSUP

LIN BUS SIGNAL

RXD
tREC_PDF

tREC_PDR

Figure 9. LIN receiver timing
VLIN_REC

LIN

5.0 V

VBUSWUDOMINANT LEVEL

3.0 V
VDD
tPROPWL

tWAKE_SLEEP

Figure 10. LIN wake-up sleep mode timing

VLIN_REC

LIN

5.0 V

VBUSWUDOMINANT LEVELIRQ

tPROPWL

tWAKE_STOP

Figure 11. LIN wake-up stop mode timing

33912

NXP Semiconductors

21

MC33912G5AC / MC34912G5AC

VSUP

VDD

RST

tNRTOUTtRST

Figure 12. Power on reset and normal request timeout timingtPSCLKCS
tWSCLKH

tLEAD

tLAG

SCLK
tWSCLKL
tSISU

MOSI

UNDEFINED

D0

tSIH

DON’T CARE

D7

DON’T CAREtVALIDtSODIS

tSOEN
MISO

D0

DON’T CARE

D7

Figure 13. SPI timing characteristics

33912

22

NXP Semiconductors

MC33912G5AC / MC34912G5AC

6Functional description

6.1

Introduction

The 33912 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For
automotive body electronics, the 33912 is well suited to perform relay control in applications such as a window lift, sunroof, etc. via the
LIN bus. Power switches are provided on the device configured as high-side and low-side outputs. Other ports are also provided, which
include a current and voltage sense port, a Hall Sensor port supply, and four wake-up capable pins. An internal voltage regulator provides
power to a MCU device.
Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible
with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground.

6.2

Functional pin description

See Figure 1, 33912 simplified application diagram, page 1, for a graphic representation of the various pins referred to in the following
paragraphs. Also, see the pin diagram on page 5 for a description of the pin locations in the package.

6.2.1

Receiver output pin (RXD)

The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD Low when LIN
bus is dominant, RXD High when LIN bus is recessive.

6.2.2

Transmitter input pin (TXD)

The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD
is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating.

6.2.3

Lin bus pin (LIN)

The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN
bus specification 2.0, 2.1, and SAE J2602-2. The LIN interface is only active during Normal Mode. See Table 6,
Operating modes overview.

6.2.4

Serial data clock pin (SCLK)The SCLK pin is the SPI clock input. MISO data changes on the positive transition of the SCLK. MOSI is sampled on the negative edgeof the SCLK.

6.2.5

Master out slave in pin (MOSI)The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the negative edge of SCLK.

6.2.6

Master in slave out pin (MISO)

The MISO pin sends data to a SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this
output pin changes on the positive edge of the SCLK. When CS is High, this pin remains in the high-impedance state.

6.2.7

Chip select pin (CS)

CS is an active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in thesame SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched.
A valid transmission must consist of 8 bits only. While in STOP mode, a low-to-high level transition on this pin generates a wake-up
condition for the 33912.

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6.2.8

Analog multiplexer pin (ADOUT0)The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer,
including the VSENSE, L1, L2, L3, L4 input voltages, and the internal junction temperature.

6.2.9

Current sense amplifier pin (ADOUT1)The ADOUT1 pin is an analog interface to the MCU A/D converter. It allows the MCU to read the output of the current sense amplifier.

6.2.10 PWM input control pin (PWMIN)
This digital input can control the high-sides and low-sides drivers in Normal Request and Normal mode. To enable PWM control, the MCU
must perform a write operation to the High-side Control register (HSCR) or the Low-side Control register (LSCR). This pin has an internal
20 μA current pull-up.

6.2.11 Reset pin (RST)This bidirectional pin is used to reset the MCU in case the 33912 detects a reset condition, or to inform the 33912 the MCU has just been
reset. After release of the RST pin, Normal Request mode is entered.
The RST pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure which allows this pin
to be shorted either to VDD or to GND during software development, without the risk of destroying the driver.

6.2.12 Interrupt pin (IRQ)
The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request mode or to signal a wakeup from Stop mode. This active low output transitions to high only after the interrupt is acknowledged by a SPI read of the respective status
bits.

6.2.13 Watchdog configuration pin (WDCONF)
The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window
watchdog period. When connected directly to ground, the watchdog is disabled. When this pin is left open, the watchdog period is fixed
to its lower precision internal default value (150 ms typical).

6.2.14 Ground connection pins (AGND, PGND, LGND)
The AGND, PGND, and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator
and the current sense module. The PGND and LGND pins are used for high current load return as in the relay-drivers and LIN interface pin.
Note: PGND, AGND, And LGND pins must be connected together.

6.2.15 Current sense amplifier input pins (ISENSEH and ISENSEL)
The ISENSEH and ISENSEL pins are the input pins of a ground compatible differential amplifier designed to be used to sense the voltage
drop over a shunt resistor. The main purpose of this amplifier is to implement accurate current sensors. The gain of the differential amplifier
can be set by the SPI.

6.2.16 Low-side pins (LS1 and LS2)LS1 and LS2 are the low-side driver outputs. Those outputs are short-circuit protected and include active clamp circuitry to drive inductive
loads. Due to the energy clamp voltage on this pin, it can raise above the battery level when switched off. The switches are controlled
through the SPI and can be configured to respond to a signal applied to the PWMIN input pin. Both low-side switches are protected against
overheating. In case of VS1 disconnection and the low-sides are still supplied by VBAT through a load, both low-sides has a VDS voltage
equal to the clamping value, as stated in the specification.

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6.2.17 Digital/analog pins (L1, L2, L3, and L4)
The Lx pins are multi purpose inputs. They can be used as digital inputs, which can be sampled by reading the SPI and used for wakeup when 33912 is in Low-power mode or used as analog inputs for the analog multiplexer. When used to sense voltage outside themodule, a 33 kΩ series resistor must be used on each input.
When used as wake-up inputs L1-L4 can be configured to operate in cyclic-sense mode. In this mode one or both of the high-side switches
are configured to be periodically turned on and sample the wake-up inputs. If a state change is detected between two cycles a wake-up
is initiated. The 33912 can also wake-up from Stop or Sleep by a simple state change on L1-L4.
When used as analog inputs, the voltage present on the Lx pins is scaled down by an selectable internal voltage divider and can be routed
to the ADOUT0 output through the analog multiplexer. When an Lx input is not selected in the analog multiplexer, the voltage divider isdisconnected from this input.
Note: If an Lx input is selected in the analog multiplexer, it is disabled as a digital input and remains disabled in Low-power mode. No
wake-up feature is available in this condition.

6.2.18 High-side output pins (HS1 and HS2)
These two high-side switches are able to drive loads such as relays or lamps. Their structures are connected to the VS2 supply pin. The
pins are short-circuit protected and both outputs are also protected against overheating. HS1 and HS2 are controlled by the SPI and can
respond to a signal applied to the PWMIN input pin. HS1 and HS2 outputs can also be used during low-power mode for the cyclic-senseof the wake inputs.

6.2.19 Power supply pins (VS1 and VS2)Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection
and negative transient voltages with external components. These pins sustain standard automotive voltage conditions such as a load
dump at 40 V. The high-side switches (HS1 and HS2) are supplied by the VS2 pin. All other internal blocks are supplied by the VS1 pin.

6.2.20 Voltage sense pin (VSENSE)
This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input
is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery
voltage. The ESD structure on this pin allows for excursion up to +40 V and down to -27 V, allowing this pin to be connected directly tothe battery line. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

6.2.21 Hall sensor switchable supply pin (HVDD)This pin provides a switchable supply for external hall sensors. While in Normal mode, this current limited output can be controlled throughthe SPI. The HVDD pin needs to be connected to an external capacitor to stabilize the regulated output voltage.

6.2.22 +5.0 V main regulator output pin (VDD)
An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply amicrocontroller. The pin is current limited against shorts to GND and overtemperature protected. During Stop mode, the voltage regulator
does not operate with its full drive capabilities and the output current is limited. During Sleep mode, the regulator output is completely
shutdown.

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7Functional device operations

7.1

Operational modes

7.1.1

Introduction

The 33912 offers three main operating modes: Normal (Run), Stop, and Sleep (Low-power). In Normal mode, the device is active and isoperating under normal application conditions. The Stop and Sleep modes are low power modes with wake-up capabilities.
In Stop mode, the voltage regulator still supplies the MCU with VDD (limited current capability), while in Sleep mode the voltage regulator
is turned off (VDD = 0 V). Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset andthe voltage regulator is turned back on.
The selection of the different modes is controlled by the MOD1:2 bits in the Mode Control register (MCR). Figure 14 describes howtransitions are done between the different operating modes. Table 6, 28, gives an overview of the operating modes.

7.1.2

Reset mode

The 33912 enters the Reset mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, it enters
the Normal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (VDD low, watchdog
trigger fail, after wake-up from Sleep mode, Normal Request mode timeout occurs).

7.1.3

Normal request modeThis is a temporary mode automatically accessed by the device after the Reset mode, or after a wake-up from Stop mode. In Normal
Request mode, the VDD regulator is ON, the RESET pin is High, and the LIN is operating in RX Only mode.
As soon as the device enters in the Normal Request mode an internal timer is started for 150 ms (typical value). During these 150 ms, theMCU must configure the Timing Control register (TIMCR) and the Mode Control register (MCR) with MOD2 and MOD1 bits set = 0, to
enter the Normal mode. If within the 150 ms timeout, the MCU does not command the 33912 to Normal mode, it enters in Reset mode. If
the WDCONF pin is grounded in order to disable the watchdog function, it goes directly in Normal mode after the Reset mode.

7.1.4

Normal mode

In Normal mode, all 33912 functions are active and can be controlled by the SPI interface and the PWMIN pin. The VDD regulator is ON
and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog
function is enabled. The wake-up inputs (L1-L4) can be read as digital inputs or have its voltage routed through the analog-multiplexer.
The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0, 2.1 and SAEJ2602. The LIN bus can transmit
and receive information. The high-side and low-side switches are active and have PWM capability according to the SPI configuration. Theinterrupts are generated to report failures for VSUP over/undervoltage, thermal shutdown, or thermal shutdown prewarning on the main
regulator.

7.1.5

Sleep mode

The Sleep mode is a low power mode. From Normal mode, the device enters into Sleep mode by sending one SPI command through theMode Control register (MCR), or (VDD low > 150 ms) with VSUV = 0. When in Reset mode, a VDD undervoltage condition with no VSUP
undervoltage (VSUV = 0) sends the device to Sleep mode. All blocks are in their lowest power consumption condition. Only some wakeup sources (wake-up inputs with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. Theinternal low-power oscillator may be active if the IC is configured for cyclic-sense. In this condition, one of the high-side switches is turnedon periodically and the wake-up inputs are sampled. Wake-up from Sleep mode is similar to a power-up. The device goes in Reset mode
except the SPI reports the wake-up source and the BATFAIL flag is not set.

7.1.6

Stop mode

The Stop mode is the second Low-power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The
application MCU is always supplied while the 33912 is operating in Stop mode. The device can enter into Stop mode only by sending the
SPI command. When the application is in this mode, it can wake-up from the 33912 side (for example: cyclic sense, force wake-up, LIN
bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode transitions the 33912 to Normal Request mode andgenerates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin.

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Normal Request
Timeout
Expired(t NRTOUT)
Normal Request
timeout
expired (NR
TOUT)
VVDD
Low
DD Low
VDD High andNormalRequestVVDDLow
Low
DD

VVDD
LOW (>t NRTOUT) expired) Expired
DD Low (>NRTOUT
andand
VSUV
=0
VSUV
=0

Wake-up
Wake-Up (Reset)(Reset)Sleep
CommandSLEEP
Command

Sleep

Stop
STOPCommand
CommandNormalWD
FailedWD
failedWake-up(Interrupt)
Wake-Up Interrupt

Reset

Reset
Delay
(t Delay
VDD
High and
Reset
RST) expired
RST) (tExpired

WD
Disabled
WD disabledPower Up

WDtrigger
Trigger
WD

Power
Down

Stop

VDD
VDD Low
Low
Legend
WD: Watchdog
Notes:WD Disabled:
Watchdog disabled (WDCONF pin connected to GND)
WD
- meansisWatchdog
WD Trigger:
Watchdog
triggered by a SPI command
WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)
WD Failed: No watchdog trigger or trigger occurs in closed window
WD trigger – means Watchdog is triggered by SPI command
Stop Command: Stop command sent via the SPI
WD failed – means no Watchdog trigger or trigger occurs in closed window
Sleep Command: Sleep command sent via the SPISTOP Command - means STOP command sent via SPI
Wake-up from Stop Mode: L1, L2, L3 or L4 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.
SLEEP
Commandmeanscommand
via wake-up,
SPI
Wake-up from
Sleep
Mode: L1,- L2,
L3 orSLEEP
L4 statechange, send
LIN bus
Periodic wake-up.
Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Figure 14. Operating modes and transitions

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Table 6. Operating modes overview
Function

Reset mode

Normal request mode

Normal mode

Stop mode

Sleep mode

VDD

Full

Full

Full

Stop

-

SPI

-

-

SPI/PWM

-

HVDD
LSx

-

SPI

(65)
(66)

-

SPI/PWM(66)

SPI/PWM

Note

(67)

Note(68)

HSx-

SPI/PWM

Analog Mux

-

SPI

SPI

-

-

Lx

-

Inputs

InputsWake-up

Wake-up

Current Sense

On

On

On

-

-

LIN

-

Rx-Only

Full/Rx-Only

Rx-Only/Wake-up

Wake-up

Watchdog-

150 ms (typ.) timeout

On(69)/Off--Voltage
Monitoring

VSUP/VDD

VSUP/VDD

VSUP/VDD

VDD

-

Notes
65. Operation can be enabled/controlled by the SPI.
66. Operation can be controlled by the PWMIN input.
67. HSx switches can be configured for cyclic sense operation in Stop mode.
68. HSx switches can be configured for cyclic sense operation in Sleep mode.
69. Windowing operation when enabled by an external resistor.

7.1.7

Interrupts

Interrupts are used to signal a microcontroller peripheral needs to be serviced. The interrupts which can be generated, change according
to the operating mode. While in Normal and Normal Request modes, the 33912 signals through interrupts special conditions which may
require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the Interrupt Source register(ISR).
While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts. Wake-up is performed bypowering-up the MCU. In Normal and Normal Request mode the wake-up source can be read by the SPI. The interrupts are signaled to
the MCU by a low logic level of the IRQ pin, which remains low until the interrupt is acknowledged by a SPI read command of the ISR
register. The IRQ pin is then be driven high.
Interrupts are only asserted while in Normal, Normal Request and Stop mode. Interrupts are not generated while the RST pin is low. The
following is a list of the interrupt sources in Normal and Normal Request modes. Some of these can be masked by writing to the SPI Interrupt Mask register (IMR).

7.1.7.1

Low-voltage interrupt

Signals when the supply line (VS1) voltage drops below the VSUV threshold (VSUV).

7.1.7.2

High-voltage interrupt

Signals when the supply line (VS1) voltage increases above the VSOV threshold (VSOV).

7.1.7.3

Overtemperature prewarning

Signals when the 33912 temperature has reached the pre-shutdown warning threshold. It is used to warn the MCU an overtemperature
shutdown in the main 5.0 V regulator is imminent.

7.1.7.4

LIN overtemperature shutdown / TXD stuck at dominant / RXD short-circuit

These signal fault conditions within the LIN interface causes the LIN driver to be disabled. In order to restart the operation, the fault must
be removed and TXD must go recessive.

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7.1.7.5

High-side overtemperature shutdown

Signals a shutdown in the high-side outputs.

7.1.7.6

Low-side overtemperature shutdown

Signals a shutdown in the low-side outputs.

7.1.8

Reset

To reset a MCU the 33912 drives the RST pin low for the time the reset condition lasts. After the reset source is removed, the statemachine drives the RST output low for at least 1.0 ms (typical value) before driving it high. In the 33912, four main reset sources exist:

7.1.8.1

5.0 V regulator low-voltage reset (VRSTTH)

The 5.0 V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects the voltage at the VDD pin has
dropped below the reset threshold VRSTTH, the 33912 issues a reset. In case of overtemperature, the voltage regulator is disabled andthe voltage monitoring issues a VDDOT Flag independently of the VDD voltage.

7.1.8.2

Window watchdog overflow

If the watchdog counter is not properly serviced while its window is open, the 33912 detects an MCU software run-away and resets the
microcontroller.

7.1.8.3

Wake-up from sleep mode

During Sleep mode, the 5.0 V regulator is not active, hence all wake-up requests from Sleep mode require a power-up/reset sequence.

7.1.8.4

External reset

The 33912 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low.
The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality
is also active in Stop mode. After the RST pin is released, there is no extra t RST to be considered.

7.1.9

Wake-up capabilities

Once entered into one of the Low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation.
In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode the wake-up is performed by activating the 5.0 V
regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers and reading theInterrupt Source register. There is no specific SPI register bits to signal a CS wake-up or external reset. If necessary this condition isdetected by excluding all other possible wake-up sources.

7.1.9.1

Wake-up from wake-up inputs (L1-L4) with cyclic sense disabled

The wake-up lines are dedicated to sense state changes of external switches and wake-up the MCU (in Sleep or Stop mode). In order toselect and activate direct wake-up from Lx inputs, the Wake-up Control register (WUCR) must be configured with appropriate LxWE inputs
enabled or disabled. The wake-up input’s state is read through the Wake-up Status register (WUSR). Lx inputs are also used to perform
cyclic-sense wake-up.
Note: Selecting an Lx input in the analog multiplexer before entering Low-power mode disables the wake-up capability of the Lx input

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7.1.9.2

Wake-up from wake-up inputs (L1-L4) with cyclic sense timer enabled

The SBCLIN can wake-up at the end of a cyclic sense period if on one of the four wake-up input lines (L1-L4) a state change occurs. Oneor both HSx switch can be activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wake-up are exclusive. If cyclicsense is enabled, the force wake-up can not be enabled. In order to select and activate the cyclic sense wake-up from Lx inputs, before
entering in low power modes (Stop or Sleep modes), the following SPI set-up has to be performed:
In WUCR: select the Lx input to WU-enable.
In HSCR: enable the desired HSx.
• In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits.
• Perform Goto Sleep/Stop command.

7.1.9.3

Forced wake-up

The 33912 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and Forced wake-up are
exclusive. If Forced wake-up is enabled, the Cyclic Sense can not be enabled.
To determine the wake-up period, the following SPI set-up has to be sent before entering in low power modes:• In TIMCR: select the CS/WD bit and determine the low power mode period with CYSTx bits.
• In HSCR: all HSx bits must be disabled.

7.1.9.4

CS wake-up

While in Stop mode, a rising edge on the CS causes a wake-up. The CS wake-up does not generate an interrupt, and is not reported in
the SPI.

7.1.9.5

LIN wake-up

While in the low-power mode, the 33912 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by a dominant
to recessive transition causes a LIN wake-up. This behavior protects the system from a short to ground bus condition. The bit RXONLY = 1
from LINCR register disables the LIN wake-up from Stop mode.

7.1.9.6

RST wake-up

While in Stop mode, the 33912 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. The 33912 changes
to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an interrupt andis not reported via the SPI.
From Stop mode, the following wake-up events can be configured:• Wake-up from Lx inputs without cyclic sense• Cyclic sense wake-up inputs• Force wake-up• CS wake-up• LIN wake-up• RST wake-up
From Sleep mode, the following wake-up events can be configured:• Wake-up from Lx inputs without cyclic sense• Cyclic sense wake-up inputs• Force wake-up• Lin wake-up

7.1.10 Window watchdog
The 33912 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external
resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears
are performed by writing through the SPI in the MOD bits of the Mode Control register (MCR).
During the first half of the SPI timeout, watchdog clears are not allowed, but after the first half of the SPI timeout window, the clear
operation opens. If a clear operation is performed outside the window, the 33912 resets the MCU, in the same way as when the watchdog
overflows.

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WINDOW CLOSEDNO WATCHDOG CLEAR
ALLOWEDWD TIMING X 50%

WINDOW OPEN
FOR WATCHDOG
CLEAR

WD TIMING X 50%

WD PERIOD (tPWD)
WD TIMING SELECTED BY RESISTORON WDCONF PIN

Figure 15. Window watchdog operation
To disable the watchdog function in Normal mode the user must connect the WDCONF pin to ground. This measure effectively disables
Normal Request mode. The WDOFF bit in the Watchdog Status register (WDSR) is set. This condition is only detected during Reset mode.
If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms(typ.) and signals the faulty condition through the Watchdog Status register (WDSR).
The watchdog timebase can be further divided by a prescaler which can be configured by the Timing Control register (TIMCR). During
Normal Request mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. Incase of a timeout, the 33912 enters into Reset mode, resetting the microcontroller before entering again into Normal Request mode.

7.1.11 Faults detection management
The 33912 has the capability to detect faults like an over or undervoltage on VS1, TxD in permanent Dominant State, overtemperatureon HS, LIN. It is able to take corrective actions accordingly. Most of faults are monitoring through SPI and the Interrupt pin. The
microcontroller can also take actions. Table 7 summarizes all fault sources the device is able to detect with associated conditions. The
status for a device recovery and the SPI or pins monitoring are also described.
Table 7. Fault detection management conditions
Block

Fault

Mode

Condition

Fallout

RecoveryBattery FailAll modes

VSUP<3.0 V (typ)then power-up-

VSUP > 19.25 V (typ)In Normal mode, HS
and LS shutdown if
bit HVSE=1 (regMCR)

VSUP < 6.0 V (typ)-VDD < 4.5 V (typ)Reset (70)

VSUP Overvoltage

Power Supply

Normal, Normal
RequestVSUP Undervoltage
VDD Undervoltage
VDD Overtemp
Prewarning
VDD
Overtemperature

All except Sleep

All except Low
Power modes

Rxd Pin Short-Circuit
LIN

Txd Pin Permanent
Dominant
Lin Driver
Overtemperature

Normal, Normal
RequestMonitoring(71)REG (Flag, Bit)

Interrupt

Condition gone

VSR (BATFAIL, 0)-

Condition gone, tore-enable HS or LS
write to HSCR or
LSCR registers

VSR (VSOV,3)

IRQ low + ISR(0101)(72)

VSR (VSUV,2)

IRQ low + ISR(0101)--

Condition gone

Temperature >115 °C (typ)-VSR (VDDOT,1)

IRQ low + ISR(0101)

Temperature >170 °C (typ)VDD shutdown,
Reset then Sleep--

RXD pin shorted to
GND or 5.0 V

LIN trans shutdown

LINSR,(RXSHORT,3)

TXD pin low for morethan 1.0 s (typ)Temperature >160 °C (typ)

LIN transmitter
shutdown

LIN transmitter reenabled once thecondition is gone
and TXD is high

LINSR (TXDOM,2)

IRQ low + ISR(0100)(72)

LINSR (LINOT,1)33912

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Table 7. Fault detection management conditions
Block

Fault

Mode

Condition

Fallout

RecoveryTemperature >160 °C (typ)Both HS thermal
shutdown

Condition gone, tore-enable HS write
to HSCR reg

Current through HSx< 5.0 mA (typ)-High-side Drivers
Overtemperature
Hs1 Open Load
Detection
High-side

Hs2 Open Load
Detection

All flags in HSSR
are set

IRQ low + ISR(0010) (72)

HSSR (HS2OP,3)
Current through HSx
tends to rise above
the current limit
60 mA (min)HSx on with limited
current capability
60 mA (min)Temperature >160 °C (typ)Both LS thermal
shutdown

Current through LSx< 7.5 mA (typ)-Low-side Drivers
Overtemperature
Ls1 Open Load
Normal, Normal
RequestLs1 Overcurrent
Ls2 Overcurrent

Normal Request
Timeout Expired

Interrupt

Condition gone

Hs2 Overcurrent

Ls2 Open Load

REG (Flag, Bit)

HSSR (HS1OP,1)
Normal, Normal
RequestHs1 Overcurrent

Low-side

Monitoring(71)Normal Request

Watchdog

HSSR (HS1CL,0)HSSR (HS2CL,2)

Condition gone, toAll flags in LSSR are
re-enable LS write toset
LSCR reg

IRQ low + ISR(0011) (72)

LSSR (LS1OP,1)
LSSR (LS2OP,3)-

Current through LSx
tends to rise above
the current limit
160 mA (min)LSx on with limited
current capability
160 mA (min)The MCU did notcommand the device
to Normal mode
within the 150 ms
timeout after reset

Reset

LSSR (LS1CL,0)-LSSR (LS2CL,2)-

Watchdog Timeout

Normal

WD timeout or WD
clear within thewindow closed

Reset

-

Watchdog Error

NormalWDCONF pin is
floating

WD internal lower
precision timebase
150 ms (typ)

WDSR (WDTO, 3)
Connect WDCONF
to a resistor or to WDSR (WDERR, 2)
GND

Notes
70. When in Reset mode a VDD undervoltage condition combined with no VSUP undervoltage (VSUV=0) sends the device to Sleep mode.
71.
72.

Registers to be read when back in Normal Request or Normal mode depending on the fault. Interrupts only generated in Normal, Normal Request
and Stop modes
Unless masked, If masked IRQ remains high and the ISR flags are not set.

7.1.12 Temperature sense gain
The analog multiplexer can be configured via the SPI to allow the ADOUT0 pin to deliver the internal junction temperature of the device.
Figure 16 illustrates the internal chip temp sense obtained per characterization at three temperatures with three different lots and 30
samples.

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Temperature Sense Analog Output Voltage
5
4.5

Vadout0 (V)

4
3.5
3
2.5
2
-50

0

50

100

150

Temperature (°C)
Figure 16. Temperature sense gain

7.1.13 High-side output pins HS1 and HS2
These outputs are two high-side drivers intended to drive small resistive loads or LEDs incorporating the following features:• PWM capability (software maskable)• Open load detection• Current limitation• Overtemperature shutdown (with maskable interrupt)• High-voltage shutdown (software maskable)• Cyclic sense
The high-side switches are controlled by the bits HS1:2 in the High-side Control register (HSCR).

7.1.13.1

PWM capability (direct access)Each high-side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in
the High-side Control register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low.
This applies to HS2 configuring HS2 and PWMHS2 bits.

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Interrupt
Control
ModuleMOD1:2
HSx
HSxOP

VDD
VDD
PWMIN

High-Side Interrupt

High Voltage Shutdown

HVSE

PWMHSxVS2

on/offControlStatusHSxCL

HIgh-side Drivercharge pumpopen load detection
current limitation
overtemperture shutdown (interrupt maskable)
High-voltage shutdown (maskable)

Cyclic Sense

HSx

Wake-up
ModuleFigure 17. High-side drivers HS1 and HS2

7.1.13.2

Open load detection

Each high-side driver signals an open load condition if the current through the high-side is below the open load current threshold. The
open load condition is indicated with the bits HS1OP and HS2OP in the High-side Status register (HSSR).

7.1.13.3

Current limitation

Each high-side driver has an output current limitation. In combination with the overtemperature shutdown the high-side drivers areprotected against overcurrent and short-circuit failures. When the driver operates in the current limitation area, it is indicated with the bits
HS1CL and HS2CL in the HSSR.
Note: If the driver is operating in current limitation mode, excessive power might be dissipated.

7.1.13.4

Overtemperature protection (HS interrupt)

Both high-side drivers are protected against overtemperature. In case of an overtemperature condition both high-side drivers are
shutdown and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source
register (ISR).
A thermal shutdown of the high-side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. If the bit HSM is set in theInterrupt Mask register (IMR), then an interrupt (IRQ) is generated. A write to the high-side Control register (HSCR), when theovertemperature condition is gone, re-enables the high-side drivers.

7.1.13.5

High-voltage shutdown

In case of a high voltage condition and if the high voltage shutdown is enabled (bit HVSE in the Mode Control register (MCR) is set, both
high-side drivers are shutdown. A write to the high-side Control register (HSCR), when the high voltage condition is gone, re-enables thehigh-side drivers.

7.1.13.6

Sleep and stop mode

The high-side drivers can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 6, Operating modes overview.

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7.1.14 Low-side output pins LS1 and LS2
These outputs are two low-side drivers intended to drive relays incorporating the following features:• PWM capability (software maskable)• Open load detection• Current limitation• Overtemperature shutdown (with maskable interrupt)• Active clamp (for driving relays)• High-voltage shutdown (software maskable)
The low-side switches are controlled by the bit LS1:2 in the Low-side Control register (LSCR). To protect the device against overvoltage
when an inductive load (relay) is turned off. An active clamp re-enables the low-side FET if the voltage on the LS1 or LS2 pin exceeds acertain level.

7.1.14.1

PWM capability (direct access)Each low-side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits LS1 and PWMLS1 are set in
the Low-side Control register (LSCR), the LS1 driver is turned on if the PWMIN pin is high and turned off if the PWMIN pin is low. The
same applies to the LS2 and PWMLS2 bits for the LS2 driver.
VDD

Interrupt
Control
ModuleHVSE

VDD

PWMLSx

Low-side Interrupt

High-voltage Shutdown

PWMIN

MOD1:2

activeclamp
LSxon/offLSx

Control

LSxOP

Status

LSxCL

Low-side Driver(active clamp)
Open load Detection
Current Limitation
Overtemperture Shutdown (interrupt maskable)
High-voltage shutdown (maskable)
PGND

Figure 18. Low-side drivers LS1 and LS2

7.1.14.2

Open load detection

Each low-side driver signals an open load condition if the current through the low-side is below the open load current threshold. The open
load condition is indicated with the bit LS1OP and LS2OP in the Low-side Status register (LSSR).

7.1.14.3

Current limitation

Each low-side driver has a current limitation. In combination with the overtemperature shutdown the low-side drivers are protected against
overcurrent and short-circuit failures. When the drivers operate in current limitation, this is indicated with the bits LS1CL and LS2CL in the
LSSR.
Note: If the drivers are operating in current limitation mode excessive power might be dissipated.

7.1.14.4

Overtemperature protection (LS interrupt)

Both low-side drivers are protected against overtemperature. In case of an overtemperature condition both low-side drivers are shutdown
and the event is latched in the Interrupt Control Module. The shutdown is indicated as an LS Interrupt in the Interrupt Source register (ISR).
If the bit LSM is set in the Interrupt Mask register (IMR) then an Interrupt (IRQ) is generated. A write to the Low-side Control register(LSCR), when the overtemperature condition is gone, re-enables the low-side drivers.

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7.1.14.5

High-voltage shutdown

In case of a high-voltage condition and if the high-voltage shutdown is enabed (bit HVSE in the Mode Control register (MCR) is set) both
low-sides drivers are shutdown. A write to the low-side Control register (LSCR), when the high-voltage condition is gone, re-enables thelow-side drivers.

7.1.14.6

Sleep and stop mode

The low-side drivers are disabled in Sleep and Stop mode. Also see Table 6, Operating modes overview.

7.1.15 LIN physical layer
The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed tomeet the LIN physical layer specification and has the following features:• LIN physical layer 2.0, 2.1 and SAEJ2602 compliant• Slew rate selection• Overtemperature shutdown• Advanced diagnostics
The LIN driver is a low-side MOSFET with thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no
external pull-up components are required for the application in a slave node. The fall time from dominant to recessive and the rise timefrom recessive to dominant is controlled. The symmetry between both slopes is guaranteed.

7.1.15.1

LIN pin

The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance.

WAKE-UP
MODULELIN
Wake-up

MOD1:2
LSR0:1VS1
J2602

LIN DRIVER

RXONLY

Slope and Slew Rate Control

RXSHORT

Overtemperature Shutdown (interrupt maskable)

TXDOM
LINOT

30 K
LIN
TXD
SLOPE
CONTROL
WAKE-UPFILTER

LGND

RXD
RECEIVER

Figure 19. LIN interface
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7.1.15.2

Slew rate selection

The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew
rate can be adapted with the bits LSR1:0 in the LIN Control register (LINCR). The initial slew rate is optimized for 20 kBit/s.

7.1.15.3

J2602 conformance

To be compliant with the SAE J2602-2 specification, the J2602 feature has to be enabled in the LINCR register (bit DIS_J2602 sets to 0).
The LIN transmitter is disabled in case of a VSUP undervoltage condition occurs and TXD is in Recessive state: the LIN bus goes in
Recessive state and RXD goes high. The LIN transmitter is not disabled if TXD is in Dominant state. A deglitcher on VSUP (tJ2602_DEG) is
implemented to avoid false switching.
If the (DIS_J2602) bit is set to 1, the J2602 feature is disabled and the communication TXD-LIN-RXD works for VSUP down to 4.6 V (typicalvalue) and then the communication is interrupted. The (DIS_J2602) bit is set per default to 0.

7.1.15.4

Overtemperature shutdown (LIN interrupt)

The output low-side FET is protected against overtemperature conditions. In case of an overtemperature condition, the transmitter is
shutdown and the LINOT bit in the LIN Status register (LINSR) is set.
If the LINM bit is set in the Interrupt Mask register (IMR), an Interrupt IRQ is generated. The transmitter is automatically re-enabled oncethe condition is gone and TXD is high.

7.1.15.5

RXD short-circuit detection (LIN interrupt)

The LIN transceiver has a short-circuit detection for the RXD output pin. If the device transmits and in case of a short-circuit condition,either 5.0 V or Ground, the RXSHORT bit in the LIN Status register (LINSR) is set and the transmitter is shutdown.
If the LINM bit is set in the Interrupt Mask register (IMR), an Interrupt IRQ is generated. The transmitter is automatically re-enabled oncethe condition is gone (transition on RXD) and TXD is high. A read of the LIN Status register (LINSR) without the RXD pin short-circuit
condition clears the bit RXSHORT.

7.1.15.6

TXD dominant detection (LIN interrupt)

The LIN transceiver monitors the TXD input pin to detect a stuck in dominant (0 V) condition. In case of a stuck condition (TXD pin 0 V for
more than 1 second (typ.)), the transmitter is shutdown and the TXDOM bit in the LIN Status register (LINSR) is set.
If the LINM bit is set in the IMR, an Interrupt IRQ is generated. The transmitter is automatically re-enabled once TXD is high. A read of the
LIN Status register (LINSR) with the TXD pin at 5.0 V clears the bit TXDOM.

7.1.15.7

LIN receiver operation only

While in Normal mode, the activation of the RXONLY bit disables the LIN TXD driver. In case of a LIN error condition, this bit isautomatically set. If Stop mode is selected with this bit set, the LIN wake-up functionality is disabled and the RXD pin reflects the state of
the LIN bus.

7.1.15.8

Stop mode and wake-up feature

During Stop mode operation, the transmitter of the physical layer is disabled. The receiver is still active and able to detect wake-up eventson the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge generates a wake-up interrupt, and is reported in theInterrupt Source register (ISR). Also see Figure 11, page 21.

7.1.15.9

Sleep mode and wake-up feature

During Sleep mode operation, the transmitter of the physical layer is disabled. The receiver must be active to detect wake-up events on
the LIN bus line. A dominant level longer than TPROPWL followed by a rising edge generates a system wake-up (Reset), and is reported
in the Interrupt Source register (ISR). Also see Figure 10, page 21.

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7.2

Logic commands and registers

7.2.1

33912 SPI interface and configuration

The serial peripheral interface creates the communication link between a microcontroller (master) and the 33912. The interface consistsof four pins (see Figure 20):
• CS — Chip Select• MOSI — Master-out Slave-in• MISO — Master-in Slave-out• SCLK— Serial Clock
A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0)
and the slave replies with 4 system status bits (VMS,LINS,HSS,LSS) + 4 bits of status information (S3:S0).
CS

Register Write Data
MOSI

A3

A2

A1

A0

C3

C2

C1

C0

S1

S0

Register Read DataMISO

VMS LINS HSS

LSS

S3

S2

SCLK
Read Data Latch

Rising: 33912 changes MISO/MCU changes MOSI

Write Data Latch

Falling: 33912 samples MOSI/MCU samples MISO

Figure 20. SPI protocol
During the inactive phase of the CS (HIGH), the new data transfer is prepared. The falling edge of the CS indicates the start of a new datatransfer and puts the MISO in the low-impedance state and latches the analog status data (register read data).
With the rising edge of the SPI clock (SCLK), the data is moved to MISO/MOSI pins. With the falling edge of the SPI clock (SCLK), thedata is sampled by the receiver. The data transfer is only valid if exactly 8 sample clock edges are present during the active (low) phaseof CS. The rising edge of the Chip Select CS indicates the end of the transfer and latches the write data (MOSI) into the register. The CS
high forces MISO to the high-impedance state.
Register reset values are described along with the reset condition. Reset condition is the condition causing the bit to be set to its reset
value. The main reset conditions are:- Power-On Reset (POR): the level at which the logic is reset and BATFAIL flag sets.
- Reset mode
- Reset done by the RST pin (ext_reset)

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7.3

SPI register overview

Table 8. System status register
Address(A3:A0)$0 - $F

BIT

Register Name / Read / Write Information
SYSSR - System Status Register

R

7

6

5

4

VMS

LINS

HSS

LSS

Table 9 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.
Table 9. SPI register overview
Address(A3:A0)

BIT

Register name / read / write information

3

2

1

0

MCR - Mode Control Register

W

HVSE

0

MOD2

MOD1

VSR - Voltage Status Register

R

VSOV

VSUV

VDDOT

BATFAIL

VSR - Voltage Status Register

R

VSOV

VSUV

VDDOT

BATFAILWUCR - Wake-up Control Register

W

L4WE

L3WE

L2WE

L1WE

WUSR - Wake-up Status Register

R

L4

L3

L2

L1

WUSR - Wake-up Status Register

R

L4

L3

L2

L1

LINCR - LIN Control RegisterW

DIS_J2602

RXONLYLSR1

LSR0

LINSR - LIN Status RegisterR

RXSHORT

TXDOM

LINOT

0

LINSR - LIN Status RegisterR

RXSHORT

TXDOM

LINOT

0

HSCR - High-side Control RegisterW

PWMHS2PWMHS1HS2HS1HSSR - High-side Status Register

R

HS2OP

HS2CL

HS1OP

HS1CL

HSSR - High-side Status Register

R

HS2OP

HS2CL

HS1OP

HS1CL

LSCR - Low-side Control RegisterW

PWMLS2PWMLS1LS2LS1LSSR - Low-side Status Register

R

LS2OP

LS2CL

LS1OP

LS1CL

LSSR - Low-side Status Register

R

LS2OP

LS2CL

LS1OP

LS1CL

TIMCR - Timing Control Register

W

CS/WD

WD2

WD1

WD0

CYST2

CYST1

CYST0

WDSR - Watchdog Status Register

R

WDTO

WDERR

WDOFF

WDWO

$B

WDSR - Watchdog Status Register

R

WDTO

WDERR

WDOFF

WDWO

$C

AMUXCR - Analog Multiplexer Control Register

W

LXDS

MX2

MX1

MX0

$D

CFR - Configuration Register

W

HVDD

CYSX8

CSAZ

CSGS

IMR - Interrupt Mask Register

W

HSM

LSM

LINM

VMM

ISR - Interrupt Source Register

R

ISR3

ISR2

ISR1

ISR0

ISR - Interrupt Source Register

R

ISR3

ISR2

ISR1

ISR0

$0
$1
$2
$3
$4
$5
$6
$7
$8
$9

$A

$E
$F

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7.3.1
7.3.1.1

Register definitions
System status register - SYSSRThe System Status register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It
summarizes the status of the Voltage Monitor Status (VMS), LIN Status (LINS), High-side Status (HSS), and the Low-side Status (LSS).
Table 10. System status register

Read

7.3.1.1.1

S7

S6

S5

S4

VMS

LINS

HSS

LSS

VMS - voltage monitor status

This read-only bit indicates one or more bits in the VSR are set.
1 = Voltage Monitor bit set
0 = NoneBATFAIL
VDDOT
VSUV

VMS

VSOV
Figure 21. Voltage monitor status

7.3.1.1.2

LINS - LIN status

This read-only bit indicates one or more bits in the LINSR are set.
1 = LIN Status bit set
0 = None

LINOT
TXDOM

LINS

RXSHORT
Figure 22. LIN status

7.3.1.1.3

HSS - high-side switch status

This read-only bit indicates one or more bits in the HSSR are set.
1 = High-side Status bit set
0 = None
HS1CL
HS1OP
HS2CL

HSS

HS2OP

Figure 23. High-side status

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7.3.1.1.4

LSS - low-side switch status

This read-only bit indicates one or more bits in the LSSR are set.
1 = Low-side Status bit set
0 = None
LS1CL
LS1OP
LS2CL

LSS

LS2OP

Figure 24. Low-side status

7.3.1.2

Mode control register - MCR

The Mode Control register (MCR) allows switching between the operation modes and to configure the 33912. Writing the MCR returns
the VSR.
Table 11. Mode control register - $0
C3

C2

C1

C0

Write

HVSE

0

MOD2

MOD1

Reset Value

1

0

-

-

Reset Condition

POR

POR

-

-

7.3.1.2.1

HVSE - high-voltage shutdown enable

This write-only bit enables/disables automatic shutdown of the high-side and the low-side drivers during a high-voltage VSOV condition.
1 = automatic shutdown enabled
0 = automatic shutdown disabled

7.3.1.2.2

MOD2, MOD1 - mode control bits

These write-only bits select the operating mode and allow clearing the watchdog in accordance with Table 9 Mode Control Bits.
Table 12. Mode control bits
MOD2

MOD1

Description00Normal Mode01

Stop Mode

10

Sleep Mode11Normal Mode + Watchdog Clear

7.3.1.3

Voltage status register - VSR

Returns the status of the several voltage monitors. This register is also returned when writing to the Mode Control register (MCR).
Table 13. Voltage status register - $0/$1

Read

S3

S2

S1

S0

VSOV

VSUV

VDDOT

BATFAIL

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7.3.1.3.1

VSOV - VSUP overvoltage

This read-only bit indicates an overvoltage condition on the VS1 pin.
1 = Overvoltage condition.
0 = Normal condition.

7.3.1.3.2

VSUV - VSUP undervoltage

This read-only bit indicates an undervoltage condition on the VS1 pin.
1 = Undervoltage condition
0 = Normal condition

7.3.1.3.3

VDDOT - main voltage regulator overtemperature warningThis read-only bit indicates the main voltage regulator temperature reached the Overtemperature Prewarning threshold.
1 = Overtemperature Prewarning
0 = Normal

7.3.1.3.4

BATFAIL - battery fail flag

This read-only bit is set during power-up and indicates the 33912 had a Power-On-Reset (POR). Any access to the MCR or VSR clears
the BATFAIL flag.
1 = POR Reset has occurred
0 = POR Reset has not occurred

7.3.1.4

Wake-up control register - WUCR

This register is used to control the digital wake-up inputs. Writing the WUCR returns the Wake-up Status register (WUSR).
Table 14. Wake-up control register - $2
C3

C2

C1

C0

Write

L4WE

L3WE

L2WE

L1WE

Reset Value

1

1

1

1

Reset Condition

7.3.1.4.1

POR, Reset mode or ext_reset

LxWE - wake-up input x enable

This write-only bit enables/disables which Lx inputs are enabled. In Stop and Sleep mode the LxWE bit determines which wake inputs areactive for wake-up. If one of the Lx inputs is selected on the analog multiplexer, the corresponding LxWE is masked to 0.
1 = Wake-up Input x enabled
0 = Wake-up Input x disabled

7.3.1.5

Wake-up status register - WUSR

This register is used to monitor the digital wake-up inputs and is also returned when writing to the WUCR.
Table 15. Wake-up status register - $2/$3

Read

S3

S2

S1

S0

L4

L3

L2

L1

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7.3.1.5.1

Lx - wake-up input x

This read-only bit indicates the status of the corresponding Lx input. If the Lx input is not enabled, then the according Wake-up status
returns 0. After a wake-up from Stop or Sleep mode these bits also allow to determine which input has caused the wake-up, by first reading
the Interrupt Status register (ISR) and then reading the WUSR. The source of the wake-up is only reported on the first WUCR or WUSR
access.
1 = Lx pin high, or Lx is the source of the wake-up
0 = Lx pin low, disabled or selected as an analog input

7.3.1.6

LIN control register - LINCRThis register controls the LIN physical interface block. Writing the LIN Control register (LINCR) returns the LIN Status register (LINSR).
Table 16. LIN control register - $4
C3

C2

C1

C0

Write

DIS_J2602

RXONLYLSR1

LSR0

Reset Value

0

0

0

0

Reset Condition

POR

POR, Reset mode,
ext_reset or LIN failure
gone*

POR

* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag resets automatically when the failure is gone.

7.3.1.6.1

J2602 - LIN dominant voltage selectThis write-only bit controls the J2602 circuitry. If the circuitry is enabled (bit sets to 0), the TXD-LIN-RXD communication works down tothe battery undervoltage condition is detected. Below, the bus is in recessive state. If the circuitry is disabled (bit sets to 1), thecommunication TXD-LIN-RXD works down to 4.6 V (typical value).
0 = Enabled J2602 feature
1 = Disabled J2602 feature

7.3.1.6.2

RXONLY - LIN receiver operation onlyThis write-only bit controls the behavior of the LIN transmitter. In Normal mode, the activation of the RXONLY bit disables the LINtransmitter. In case of a LIN error condition, this bit is automatically set. In Stop mode this bit disables the LIN wake-up functionality, andthe RXD pin reflects the state of the LIN bus.
1 = only LIN receiver active (Normal mode) or LIN wake-up disabled (Stop mode)
0 = LIN fully enabled

7.3.1.6.3

LSRx - LIN slew rate

This write-only bit controls the LIN driver slew-rate in accordance with Table 17.
Table 17. LIN slew rate control
LSR1

LSR0

Description00Normal Slew Rate (up to 20 kb/s)

0

1

Slow Slew Rate (up to 10 kb/s)

1

0

Fast Slew Rate (up to 100 kb/s)

1

1

Reserved

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7.3.1.7

LIN status register - LINSRThis register returns the status of the LIN physical interface block and is also returned when writing to the LINCR.
Table 18. LIN status register - $4/$5

Read

S3

S2

S1

S0

RXSHORT

TXDOM

LINOT

0

7.3.1.7.1

RXSHORT - RXD pin short-circuit

This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The short-circuit delay must bea worst case of 8µs to be detected and to shutdown the driver. To clear this bit, it must be read after the condition is gone (transition
detected on RXD pin). The LIN driver is automatically re-enabled once the condition is gone and TXD is high.
1 = RXD short-circuit condition
0 = None

7.3.1.7.2

TXDOM - TXD permanent dominantThis read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LINtransmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second (typical value).
To clear this bit, it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes High.
1 = TXD stuck at dominant fault detected
0 = None

7.3.1.7.3

LINOT - LIN driver overtemperatureThis read-only bit signals the LIN transceiver was shutdown due to overtemperature. The transmitter is automatically re-enabled after theovertemperature condition is gone and TXD is high. The LINOT bit is cleared after a SPI read once the condition is gone.
1 = LIN overtemperature shutdown
0 = None

7.3.1.8

High-side control register - HSCR

This register controls the operation of the high-side drivers. Writing to this register returns the high-side Status register (HSSR).
Table 19. High-side control register - $6
C3
Write
Reset Value
Reset Condition

7.3.1.8.1

C2

PWMHS2 PWMHS1
0

0
POR

C1

C0

HS2

HS1

0

0

POR, Reset mode, ext_reset, HSx
overtemp or (VSOV & HVSE)PWMHSx - PWM input control enable

This write-only bit enables/disables the PWMIN input pin to control the respective high-side switch. The corresponding high-side switch
must be enabled (HSx bit).
1 = PWMIN input controls HSx output
0 = HSx is controlled only by the SPI

7.3.1.8.2

HSx - HSx switch control.

This write-only bit enables/disables the corresponding high-side switch.
1 = HSx switch on
0 = HSx switch off

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7.3.1.9

High-side status register - HSSRThis register returns the status of the high-side switches and is also returned when writing to the HSCR.
Table 20. High-side status register - $6/$7

Read

S3

S2

S1

S0

HS2OP

HS2CL

HS1OP

HS1CL

7.3.1.9.1

High-side thermal shutdown

A thermal shutdown of the high-side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously.

7.3.1.9.2

HSxOP - high-side switch open load detection

This read-only bit signals the high-side switches are conducting current below a certain threshold indicating possible load disconnection.
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal

7.3.1.9.3

HSxCL - high-side current limitation

This read-only bit indicates the respective high-side switch is operating in current limitation mode.
1 = HSx in current limitation (or thermal shutdown)
0 = Normal

7.3.1.10

Low-side control register - LSCR

This register controls the operation of the low-side drivers. Writing the low-side Control register (LSCR) also returns the low-side Status
register (LSSR).
Table 21. Low-side control register - $8
C3
Write
Reset ValuePWMLS2 PWMLS1
0

Reset Condition

7.3.1.10.1

C2

0
POR

C1

C0

LS2

LS1

0

0

POR, Reset mode, ext_reset, LSx
overtemp or (VSOV & HVSE)

PWMLx - PWM input control enable

This write-only bit enables/disables the PWMIN input pin to control the respective low-side switch. The corresponding low-side switch must
be enabled (LSx bit).
1 = PWMIN input controls LSx
0 = LSx is controlled only by the SPI

7.3.1.10.2

LSx - LSx switch control

This write-only bit enables/disables the corresponding low-side switch.
1 = LSx switch on
0 = LSx switch off

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7.3.1.11

Low-side status register - LSSR

This register returns the status of the low-side switches and is also returned when writing to the LSCR.
Table 22. Low-side status register - $8/$9

Read

C3

C2

C1

C0

LS2OP

LS2CL

LS1OP

LS1CL

7.3.1.11.1

Low-side thermal shutdown

A thermal shutdown of the low-side drivers is indicated by setting all LSxOP and LSxCL bits simultaneously.

7.3.1.11.2

LSxOP - low-side switch open load detection

This read-only bit signals the low-side switches are conducting current below a certain threshold indicating possible load disconnection.
1 = LSx Open Load detected (or thermal shutdown)
0 = Normal

7.3.1.11.3

LSxCL - low-side current limitation

This read-only bit indicates the respective low-side switch is operating in current limitation mode.
1 = LSx in current limitation (or thermal shutdown)
0 = Normal

7.3.1.12

Timing control register - TIMCR

This register allows to configure the watchdog, the cyclic sense and Forced Wake-up periods. Writing to the Timing Control register(TIMCR) also returns the Watchdog Status register (WDSR).
Table 23. Timing control register - $A
C3
Write

CS/WD

Reset Value-

Reset Condition-

7.3.1.12.1

C2

C1

C0

WD2

WD1

WD0

CYST2

CYST1

CYST0

0

0

0

POR

CS/WD - cyclic sense or watchdog prescaler selectThis write-only bit selects which prescaler is being written to, the Cyclic Sense/Forced Wake-up prescaler or the Watchdog prescaler.
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select

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7.3.1.12.2

WDx - watchdog prescalerThis write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 24.
This configuration is valid only if windowing watchdog is active.
Table 24. Watchdog prescaler
WD2

WD1

WD0

Prescaler divider

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

6

1

0

0

8

1

0

1

10

1

1

0

12

1

1

1

14

7.3.1.12.3

CYSTx - cyclic sense period prescaler selectThis write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the Configuration register (CFR) (seepage 49). This option is only active if one of the high-side switches is enabled when entering in Stop or Sleep mode. Otherwise, a timed
wake-up is performed after the period shown in Table 25.
Table 25. Cyclic sense and force wake up interval
CYSX8(73)

CYST2

CYST1

CYST0

Interval

X

0

0

0

No cyclic sense(74)

0

0

0

1

20 ms

0

0

1

0

40 ms

0

0

1

1

60 ms

0

1

0

0

80 ms

0

1

0

1

100 ms01

1

0

120 ms01

1

1

140 ms1001

160 ms10

1

0

320 ms10

1

1

480 ms1

1

0

0640 ms1

1

0

1

800 ms1

1

1

0

960 ms111

11120 ms

Notes
73. bit CYSX8 is located in Configuration register (CFR)
74. No Cyclic Sense and no Force Wake-up available.

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7.3.1.13

Watchdog status register - WDSR

This register returns the Watchdog status information and is also returned when writing to the TIMCR.
Table 26. Watchdog status register - $A/$B

Read

S3

S2

S1

S0

WDTO

WDERR

WDOFF

WDWO

7.3.1.13.1

WDTO - watchdog timeout

This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the Watchdog within the windowclosed. Any access to this register or the Timing Control register (TIMCR) clears the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None

7.3.1.13.2

WDERR - watchdog error

This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision
timebase. The Windowing function is disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating

7.3.1.13.3

WDOFF - watchdog off

This read-only bit signals the watchdog pin connected to Ground and therefore disabled. In this case watchdog timeouts are disabled andthe device automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming the Flashmemory.
1 = Watchdog is disabled
0 = Watchdog is enabled

7.3.1.13.4

WDWO - watchdog window open

This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case
WDERR is High.
1 = Watchdog window open
0 = Watchdog window closed

7.3.1.14

Analog multiplexer control register - MUXCRThis register controls the analog multiplexer and selects the divider ration for the Lx input divider.
Table 27. Analog multiplexer control register -$C
C3

C2

C1

C0

Write

LXDS

MX2

MX1

MX0

Reset Value

1

0

0

0

Reset Condition

POR

7.3.1.14.1

POR, Reset mode or ext_reset

LXDS - Lx analog input divider selectThis write-only bit selects the resistor divider for the Lx analog inputs. Voltage is internally clamped to VDD.
0 = Lx Analog divider: 1
1 = Lx Analog divider: 3.6 (typ.)

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7.3.1.15

MXx - analog multiplexer input select

These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 28.
When disabled or when in Stop or Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower
current consumption.
Table 28. Analog multiplexer channel select
MX2

MX1

MX0

Meaning000Disabled001

Reserved010

Die Temperature Sensor(75)

0

1

1

VSENSE input

1

0

0

L1 input

10

1

L2 input1

1

0

L3 input

1

1

1

L4 input

Notes
75. Accessing the Die Temperature Sensor directly from the Disabled state is notrecommended. If this transition must be performed and to avoid theintermediate state, wait at least 1.0 ms, then start the die temp measurement.

Possible access is Disabled → Vsense input → Die Temperature Sensor.

7.3.1.16

Configuration register - CFRThis register controls the Hall Sensor Supply enable/disable, the cyclic sense timing multiplier, enables/disables the Current Sense Autozero function and selects the gain for the current sense amplifier.
Table 29. Configuration register - $D
C3

C2

C1

C0

Write

HVDD

CYSX8

CSAZ

CSGS

Reset Value

0

0

0

0

Reset Condition

POR, Reset mode or ext_reset

POR

POR

POR

7.3.1.16.1

HVDD - hall sensor supply enable

This write-only bit enables/disables the state of the hall sensor supply.
1 = HVDD on
0 = HVDD off

7.3.1.16.2

CYSX8 - cyclic sense timing x 8

This write-only bit influences the cyclic sense and Forced Wake-up period as shown in Table .
1 = Multiplier enabled
0 = None

7.3.1.16.3

CSAZ - current sense auto-zero function enable

This write-only bit enables/disables the circuitry to lower the offset voltage of the current sense amplifier.
1 = Auto-zero function enabled
0 = Auto-zero function disabled33912

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7.3.1.16.4

CSGS - current sense amplifier gain selectThis write-only bit selects the gain of the current sense amplifier.
1 = 14.5 (typ.)0 = 30 (typ.)7.3.1.17

Interrupt mask register - IMRThis register allows masking of some of the interrupt sources. No interrupt is generated to the MCU and no flag is set in the ISR register.
The 5.0 V Regulator overtemperature prewarning interrupt and undervoltage (VSUV) interrupts can not be masked and always causes aninterrupt. Writing to the IMR returns the ISR.
Table 30. Interrupt mask register - $E
C3

C2

C1

C0

Write

HSM

LSM

LINM

VMM

Reset Value

1

1

1

1

Reset Condition

POR

7.3.1.17.1

HSM - high-side interrupt mask

This write-only bit enables/disables interrupts generated in the high-side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled

7.3.1.17.2

LSM - low-side interrupt mask

This write-only bit enables/disables interrupts generated in the low-side block.
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled

7.3.1.17.3

LINM - LIN interrupts mask

This write-only bit enables/disables interrupts generated in the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled

7.3.1.17.4

VMM - voltage monitor interrupt mask

This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor
block is the VSUP overvoltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled

7.3.1.18

Interrupt source register - ISR

This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges
the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ is driven highfor 10 µs and then be driven low again. This register is also returned when writing to the Interrupt Mask register (IMR).
Table 31. Interrupt source register - $E/$F

Read

S3

S2

S1

S0

ISR3

ISR2

ISR1

ISR0

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7.3.1.18.1

ISRx - interrupt source register

These read-only bits indicate the interrupt source following Table 32. If no interrupt is pending then all bits are 0. If more than one interrupt
is pending, the interrupt sources are handled sequentially multiplex.
Table 32. Interrupt sources
Interrupt source
ISR3 ISR2 ISR1 ISR0

Prioritynone maskablemaskable

0

0

0

0

no interrupt

no interrupt

none

0

0

0

1

Lx Wake-up from Stop and Sleep mode-

highest

0

0

1

0

-

HS Interrupt (Overtemperature)

0

0

1

1

-

LS Interrupt (Overtemperature)

0

1

0

0

LIN Wake-up

LIN Interrupt (RXSHORT, TXDOM, LIN OT)
Voltage Monitor Interrupt (High Voltage)
-

0

1

0

1

Voltage Monitor Interrupt (Low Voltage and VDD
overtemperature)

0

1

1

0

Forced Wake-up

lowest33912

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8

Typical application

The 33912 can be configured in several applications. The figure below shows the 33912 in the typical Slave Node Application.
V

BAT

VS2

VS1

D1

C2

C1

C4

Interrupt
Control Module
LVI, HVI, HTI, OCI

IRQ

C3

InternalBus

VDD

Voltage Regulator

C5

AGND

HVDD

5V Output Module

VDD
IRQ

Reset
Control Module
LVR, HVR, HTR, WD,

RST

LS1
Low Side Control
Module

RST
TIMER

LS2

HS1
HS2

MISO
MOSI

Chip Temp Sense Module

SCLK

Analog Multiplexer

SPI&
CONTROLSPICSVSENSEVBAT Sense Module

R2

L1
Analog Input Module

A/D

R1

Motor Output
High Side Control
ModuleMCU

HB Type Relay

PGNDWindow
Watchdog Module

PWMIN

Hall Sensor Supply

ADOUT0

R3

L2
Wake Up Module

L3
Digital Input Module

L4

R4
Analog Input
R5
Analog Input

RXD
LIN Physical Layer

SCI

LIN

LIN

TXD
C6

ISENSEH
Current Sense Module

ADOUT1WDCONF

LGND

AGND

ISENSEL

PGND

A/D

R6

R7

Typical Component Values:

C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 4.7 µF; C6 = 22 0pF or 68 pF
R1 = 10 kΩ; R2 = R3 = 10 kΩ; R4 = R5 = 33 kΩ; R6 = 20 Ω; R7 = 20 kΩ200 kΩ
Recommended Configuration of the not Connected Pins (NC):Pin 28 = this pin is not internally connected and may be used for PCB routing
optimization.

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9MC33912BAC product specifications, Pages 53 to 103

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10Internal block diagram
VS2

INTERRUPTCONTROL
MODULE
LVI, HVI, HTI, OCIRESET CONTROLMODULE
LVR, HVR, HTR, WD

VS1

INTERNAL BUS

RST IRQ

VDD

AGND
VOLTAGE REGULATOR

5V OUTPUT
MODULE

HVDD
LS1

LOW-SIDE
CONTROL
MODULEWINDOW
WATCHDOG
MODULE

LS2

PWMIN

PGND
VS2

MISO

SCLK

SPI
&
CONTROL

VS2

HS1

HS2
ANALOG MULTIPLEXERMOSI

HIGH-SIDECONTROL
MODULECS
ADOUT0

WAKE-UP MODULE

VBATSENSE MODULEVSENSECHIP TEMPERATURESENSE MODULEANALOG INPUTMODULE

L1
L2
L3

RXD
TXD

DIGITAL INPUT MODULE

LIN PHYSICAL
LAYER

L4

LIN

ISENSEH
CURRENT SENSE MODULEISENSELLGND

WDCONFADOUT1Figure 25. 33912 simplified internal block diagram

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AGND

VDD

HVDD

VSENSE

NC

VS1

VS2

HS1

32

31

30

29

28

27

26

25

Pin connections

L1

MISO

3

22

L2

MOSI

4

21

L3

SCLK

5

20

L4

CS

6

19

LS1

ADOUT0

7

18

PGND

PWMIN

8

17

LS2

9

10

11

12

13

14

15

16
ISENSEH

23

ISENSEL

2

LGND

TXD

LIN

HS2

WDCONF

24

ADOUT1

1

IRQ

RXD

RST

11

Figure 26. 33912 pin connections
A functional description of each pin can be found in the Functional pin description on page 73.
Table 33. 33912 pin definitions
Pin

Pin name

Formal nameDefinition

1

RXD

Receiver Output

This pin is the receiver output of the LIN interface which reports the state of the bus
voltage to the MCU interface.

2

TXD

Transmitter Input

This pin is the transmitter input of the LIN interface which controls the state of the bus
output.

3MISO

SPI Output

SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the highimpedance state.

4

MOSI

SPI Input

SPI (Serial Peripheral Interface) data input.

5

SCLK

SPI Clock

SPI (Serial Peripheral Interface) clock Input.

6

CS

SPI Chip Select

7

ADOUT0

Analog Output Pin 0

8

PWMIN

PWM Input

9

RSTInternal Reset I/OBidirectional Reset I/O pin - driven low when any internal reset source is asserted. RST
is active low.

10

IRQ

Internal Interrupt
OutputInterrupt output pin, indicating wake-up events from Stop mode or events from Normal
and Normal request modes. IRQ is active low.

11

ADOUT1

Analog Output Pin 1

SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
Analog Multiplexer Output.
High-side and Low-side Pulse Width Modulation Input.

Current sense analog output.

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Table 33. 33912 pin definitions (continued)
Pin

Pin name

Formal nameDefinition

12

WDCONF

Watchdog
Configuration Pin

This input pin is for configuration of the watchdog period and allows the disabling of thewatchdog.

13

LIN

LIN Bus14

LGND

LIN Ground Pin

15
16

ISENSELISENSEH

Current Sense Pins

Current Sense differential inputs.

17
19

LS2
LS1

Low-side Outputs

Relay drivers low-side outputs.

18

PGND

Power Ground Pin

This pin is the device low-side ground connection. It is internally connected to the LGND
pin.

20
21
22
23

L4
L3
L2
L1

Wake-up Inputs

These pins are the wake-up capable digital inputs(76). In addition, all Lx inputs can besensed analog via the analog multiplexer.

24
25

HS2
HS1

High-side Outputs

High-side switch outputs.

26
27

VS2
VS1

Power Supply Pin

These pins are device battery level power supply pins.VS2 is supplying the HSx drivers
while VS1 supplies the remaining blocks.(77)29

VSENSE

Voltage Sense Pin

Battery voltage sense input.(78)

30

HVDD

Hall Sensor Supply
Output+5.0 V switchable supply output pin.(79)

31

VDD

Voltage Regulator
Output+5.0 V main voltage regulator output pin.(80)

32

AGND

Analog Ground Pin

This pin is the device analog ground connection.

This pin represents the single-wire bus transmitter and receiver.
This pin is the device LIN ground connection. It is internally connected to the PGND pin.

Notes
76. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.
77. Reverse battery protection series diodes must be used externally to protect the internal circuitry.
78. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It
is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.
79. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.
80. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10.0 Ω) required.

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12Electrical characteristics

12.1

Maximum ratings

Table 34. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
SymbolRatings

Value

Unit

Supply Voltage at VS1 and VS2• Normal Operation (DC)• Transient Conditions (load dump)-0.3 to 27-0.3 to 40

V

Supply Voltage at VDD-0.3 to 5.5

V

Notes

Electrical ratings
VSUP(SS)
VSUP(PK)
VDD
VIN
VIN(IRQ)

Input / Output Pins Voltage• CS, RST, SCLK, PWMIN, ADOUT0, ADOUT1, MOSI, MISO, TXD, RXD,
HVDD
• Interrupt Pin (IRQ)(81)-0.3 to VDD +0.3

V(82)

-0.3 to 11

VHS

HS1 and HS2 Pin Voltage (DC)- 0.3 to VSUP +0.3

V

VLS

LS1 and LS2 Pin Voltage (DC)-0.3 to 45

V

VLxDC
VLxTR

L1, L2, L3 and L4 Pin Voltage• Normal Operation with a series 33 kΩ resistor (DC)• Transient input voltage with external component (according to ISO7637-2)(See Figure 28)-18 to 40±100

V

VISENSEISENSEH and ISENSEL Pin Voltage (DC)-0.3 to 40

V

VVSENSEVSENSE Pin Voltage (DC)-27 to 40

V

VBUSDCVBUSTR

LIN Pin Voltage• Normal Operation (DC)• Transient input voltage with external component (according to ISO7637-2)(See Figure 27)-18 to 40-150 to 100

V

IVDD

VDD output current

Internally LimitedA± 8000
±2000
± 150

V

VESD1-1
VESD1-2
VESD2
VESD3-1
VESD3-2

ESD Voltage• Human Body Model - LIN Pin• Human Body Model - all other Pins
• Machine Model• Charge Device Model• Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25, and 32)• All other Pins (Pins 2-7, 10-15, 18-23, 26-31)

(83)

± 750
± 500

Notes
81. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.
82. Extended voltage range for programming purpose only.
83. Testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Machine Model (CZAP = 200 pF, RZAP = 0 Ω)
and the Charge Device Model, Robotic (CZAP = 4.0 pF).

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Table 34. Maximum ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
SymbolRatings

Value

Unit

Notes

(84)

Thermal ratings
TA

Operating Ambient Temperature
33912
34912

-40 to 125-40 to 85°C

TJ

Operating Junction Temperature-40 to 150

°C

TSTG

Storage Temperature-55 to 150

°C

RθJA

Thermal Resistance, Junction to Ambient
Natural Convection, Single Layer board (1s)Natural Convection, Four Layer board (2s2p)

85
56

°C/W

RθJC

Thermal Resistance, Junction to Case

23

°C/W

(88)

°C

(89), (90)TPPRTPeak Package Reflow Temperature During Reflow

Note 90(85), (86)(85), (87)Notes
84. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.
85.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

86.
87.
88.
89.

Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature andMoisture Sensitivity Levels (MSL), Go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view allorderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

90.

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12.2

Static electrical characteristics

Table 35. Static electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

Supply voltage range (VS1, VS2)
VSUP

Nominal Operating Voltage

5.5

–

18

V

VSUPOP

Functional Operating Voltage

–

–

27

V

VSUPLD

Load Dump

–

–

40

V

(91)

Supply current range (VSUP = 13.5 V)
IRUN

Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State

–

4.5

10

mA

(92)

ISTOP

Stop mode, VDD ON with IOUT = 100 µA, LIN Recessive State• 5.5 V < VSUP < 12 V
• VSUP = 13.5 V

–
–

48
58

80
90

µA

(92), (93),(94)

ISLEEP

Sleep mode, VDD OFF, LIN Recessive State• 5.5 V < VSUP < 12 V
• 12 V ≤ VSUP < 13.5 V

–
–

27
37

35
48

µA

(92), (94)ICYCLIC

Cyclic Sense Supply Current Adder(95)

–

10

–

µA

Supply under/overvoltage detections
VBATFAILVBATFAIL_HYS

VSUV

VSUV_HYSVSOVVSOV_HYS(96)

Power-On Reset (BATFAIL)• Threshold (measured on VS1)
• Hysteresis (measured on VS1)

1.5
–

3.0
0.9

3.9
–

VSUP Undervoltage Detection (VSUV Flag) (Normal and Normal
Request modes, Interrupt Generated)• Threshold (measured on VS1)
• Hysteresis (measured on VS1)

5.55
–

6.0
1.0

6.6
–

VSUP Overvoltage Detection (VSOV Flag) (Normal and Normal
Request modes, Interrupt Generated)• Threshold (measured on VS1)
• Hysteresis (measured on VS1)

18
–

19.25
1.0

20.5
–

V

(95)
(95)

V

V

Notes
91. Device is fully functional. All features are operating.
92. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.
93.

Total IDD current (including loads) below 100 µA.

94.

Stop and Sleep modes current increases if VSUP exceeds 13.5 V.

95.
96.

This parameter is guaranteed by process monitoring but not production tested.
The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.

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Table 35. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

Voltage regulator(97) (VDD)
VDDRUN

Normal Mode Output Voltage• 1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V

4.75

5.00

5.25

V

IVDDRUN

Normal Mode Output Current Limitation

60

110

200

mA

VDDDROP

Dropout Voltage• IVDD = 50 mA

–

0.1

0.25

V

VDDSTOP

Stop Mode Output Voltage• IVDD < 5.0 mA

4.75

5.0

5.25

V

IVDDSTOP

Stop Mode Output Current Limitation

6.0

12

36

mA

–
–

20
5.0

25
25

mV

–
–

15
10

80
50

mV

LRRUN
LRSTOPLDRUNLDSTOPLine Regulation• Normal mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA• Stop mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA
Load Regulation• Normal mode, 1.0 mA < IVDD < 50 mA• Stop mode, 0.1 mA < IVDD < 5.0 mA

(98)

TPRE

Overtemperature Prewarning (Junction)• Interrupt generated, VDDOT Bit Set

110

125

140

°C

(99)

TPRE_HYS

Overtemperature Prewarning Hysteresis

–

10

–

°C

(99)

Overtemperature Shutdown Temperature (Junction)

155

170

185

°C

(99)

Overtemperature Shutdown Hysteresis

–

10

–

°C

(99)

VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100%
• IHVDD = 15 mA

-2.0

–

2.0

%

Current Limitation

20

30

50

mA

HVDDDROP

Dropout Voltage• IHVDD = 15 mA; IVDD = 5.0 mA

–

160

300

mV

LRHVDDLine Regulation• IHVDD = 5.0 mA; IVDD = 5.0 mA

–

25

40

mV

LDHVDD

Load Regulation• 1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA

–

10

20

mV

TSD
TSD_HYSHall sensor supply output (100) (HVDD)HVDDACC
IHVDD

Notes
97. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.
98. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).
99. This parameter is guaranteed by process monitoring but not production tested.
100. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

33912

60

NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 35. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

VDD Low Voltage Reset Threshold

4.3

4.5

4.7

V

VOL

Low-state Output Voltage• IOUT = 1.5 mA; 3.5 V ≤ VSUP ≤ 27 V

0.0

–

0.9

V

IOH

High-state Output Current (0 < VOUT < 3.5 V)

-150

-250

-350

µA

IPD_MAX

Pull-down Current Limitation (internally limited)
VOUT = VDD

1.5

–

8.0

mA

VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

V

Notes

RST input/output pin (RST)VRSTTHMISO SPI output pin (MISO)
VOL

Low-state Output Voltage• IOUT = 1.5 mA

0.0

–

1.0

V

VOH

High-state Output Voltage• IOUT = -250 µA

VDD -0.9

–

VDD

V

ITRIMISO

Tri-state Leakage Current• 0 V ≤ VMISO ≤ VDD

-10

–

10

µA

SPI input pins (MOSI, SCLK, CS)
VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

V

IIN

MOSI, SCLK Input Current• 0 V ≤ VIN ≤ VDD

-10

–

10

µA

CS Pull-up Current• 0 V < VIN < 3.5 V

10

20

30

µA

IPUCS

Interrupt output pin (IRQ)
VOL

Low-state Output Voltage• IOUT = 1.5 mA

0.0

–

0.8

V

VOH

High-state Output Voltage• IOUT = -250 µA

VDD -0.8

–

VDD

V

VOH

Leakage Current• VDD ≤ VOUT ≤ 10 V

–

–

2.0

mA

Pulse width modulation input pin (PWMIN)
VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

V

IPUPWMIN

Pull-up current• 0 V < VIN < 3.5 V

10

20

30

µA

33912

NXP Semiconductors

61

MC33912G5AC / MC34912G5AC

Table 35. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

–
–
–

–
–
–

7.0
10
14

Unit

Notes

Ω

(101)

High-side output HS1 and HS2 pins (HS1, HS2)RDS(on)Output Drain-to-Source On Resistance• TJ = 25 °C, ILOAD = 50 mA; VSUP > 9.0 V• TJ = 150 °C, ILOAD = 50 mA; VSUP > 9.0 V• TJ = 150 °C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V

ILIMHSX

Output Current Limitation• 0 V < VOUT < VSUP - 2.0 V

60

120

250

mA

(102)

IOLHSX

Open Load Current Detection

–

5.0

7.5

mA

(103)

ILEAK

Leakage Current• -0.2 V < VHSX < VS2 + 0.2 V

–

–

10

µA

VTHSC

Short-circuit Detection Threshold• 5.5 V < VSUP < 27 V

VSUP -2.0

–

–

V

(104)

THSSD

Overtemperature Shutdown

150

165

180

°C

(105),(106)

Overtemperature Shutdown Hysteresis

–

10

–

°C

(106)

–
–
–

–
–
–

2.5
4.5
10

THSSD_HYS

Low-side output LS1 and LS2 pins (LS1, LS2)RDS(on)Output Drain-to-Source On Resistance• TJ = 25 °C, ILOAD = 150 mA, VSUP > 9.0 V• TJ = 125 °C, ILOAD = 150 mA, VSUP > 9.0 V• TJ = 125 °C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V

ΩILIMLSX

Output Current Limitation• 2.0 V < VOUT < VSUP

160

275

350

mA

(107)

IOLLSX

Open Load Current Detection

–

8.0

12

mA

(108)

ILEAK

Leakage Current• -0.2 V < VOUT < VS1

–

–

10

µA

VCLAMP

Active Output Energy Clamp• IOUT = 150 mA

VSUP +2.0–

VSUP +5.0

V

VTHSC

Short-circuit Detection Threshold• 5.5 V < VSUP < 27 V

2.0

–

–

V

(109)

TLSSD

Overtemperature Shutdown

150

165

180

°C

(110),(106)

Overtemperature Shutdown Hysteresis

–

10

–

°C

(106)

TLSSD_HYS

Notes
101. This parameter is production tested up to TA = 125 °C and guaranteed by process monitoring up to TJ = 150 °C.
102.
103.
104.
105.
106.
107.
108.
109.
110.

When overcurrent occurs, the corresponding high-side stays ON with limited current capability and the HSxCL flag is set in the HSSR.
When open load occurs, the flag (HSxOP) is set in the HSSR.
When short-circuit occurs and if HVSE flag is enabled, both HS automatic shutdown.
When overtemperature shutdown occurs, both high-sides are turned off. All flags in HSSR are set.
Guaranteed by characterization but not production tested
When overcurrent occurs, the corresponding low-side stays ON with limited current capability and the LSxCL flag is set in the LSSR.
When open load occurs, the flag (LSxOP) is set in the LSSR.
When short-circuit occurs and if HVSE Flag is enabled, both LS automatic shutdown
When overtemperature shutdown occurs, both low-sides are turned off. All flags in LSSR are set.

33912

62

NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 35. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

L1, L2, L3, and L4 input pins (L1, L2, L3, L4)
VTHL

Low Detection Threshold• 5.5 V < VSUP < 27 V

2.0

2.5

3.0

V

VTHH

High Detection Threshold• 5.5 V < VSUP < 27 V

3.0

3.5

4.0

V

VHYS

Hysteresis• 5.5 V < VSUP < 27 V

0.5

1.0

1.5

V

IIN

Input Current• -0.2 V < VIN < VS1

-10

–

10

µA

(111)

RLXIN

Analog Input Impedance

800

1550

–

kΩ

(112)

Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0)• LXDS (Lx Divider Select) = 0• LXDS (Lx Divider Select) = 1

0.95
3.42

1.0
3.6

1.05
3.78

VRATIOLx-OFFSET

Analog Output offset Ratio• LXDS (Lx Divider Select) = 0• LXDS (Lx Divider Select) = 1

-80
-22

0.0
0.0

80
22

mV

LXMATCHING

Analog Inputs Matching• LXDS (Lx Divider Select) = 0• LXDS (Lx Divider Select) = 1

96
96

100
100

104
104

%

RATIOLX

Window watchdog configuration pin (WDCONF)
REXT

External Resistor Range

20

–

200

kΩ

WDACC

Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)

-15

–

15

%

Internal Chip Temperature Sense Gain

–

10.5

–

mV/K

RATIOVSENSEVSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0)• 5.5 V < VSUP < 27 V

5.0

5.25

5.5

OFFSETVSENSEVSENSE Output Related Offset• -40 °C < TA < -20 °C

-30
-45

–
–

30
45

mV

(113)

Analog multiplexer
STTOV

Analog outputs (ADOUT0 and ADOUT1)
VOUT_MAX

Maximum Output Voltage• -5.0 mA < IO < 5.0 mA

VDD -0.35

–

VDD

V

VOUT_MIN

Minimum Output Voltage• -5.0 mA < IO < 5.0 mA

0.0

–

0.35

V

Notes
111. Analog multiplexer input disconnected from Lx input pin.
112. Analog multiplexer input connected to Lx input pin.
113. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)33912

NXP Semiconductors

63

MC33912G5AC / MC34912G5AC

Table 35. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

Current sense amplifier (ISENSEH, ISENSEL)GGain• CSGS (Current Sense Gain Select) = 0• CSGS (Current Sense Gain Select) = 1

29
14

30
14.5

31
15

DIFF

Differential Input Impedance• CSGS (Current Sense Gain Select) = 0• CSGS (Current Sense Gain Select) = 1

2.0
5.0

10
20

30
50

kΩ

CM

Common Mode Input Impedance• CSGS (Current Sense Gain Select) = 0• CSGS (Current Sense Gain Select) = 1

75
75

–
–

300
300

kΩ

VIN

ISENSEH, ISENSEL Input Voltage Range

-0.2

–

3.0

V

VIN_OFFSET

Input Offset Voltage• CSAZ (Current Sense Auto Zero) = 0• CSAZ (Current Sense Auto Zero) = 1

-15
-2.0

–
–

15
2.0

mV

RxD output pin (LIN physical layer) (RxD)
VOL

Low-state Output Voltage• IOUT = 1.5 mA

0.0

–

0.8

VOH

High-state Output Voltage• IOUT = -250 µA

VDD -0.8

–

VDD

V
V

TXD input pin (LIN physical layer) (TXD)
VIL

Low-state Input Voltage

-0.3

–

0.3 x VDD

V

VIH

High-state Input Voltage

0.7 x VDD–

VDD +0.3

VIPUIN

Pin Pull-up Current, 0 V < VIN < 3.5 V

10

20

30

µA

33912

64

NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 35. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

40

120

200

mA

-1.0
–

–
–

–
20

mA
µA

-1.0

–

1.0

mA

–

–

100

µA

–
0.6
0.475
–

–
–
0.5
–

0.4
–
0.525
0.175

VSUP -1.0
–

–
1.1

–
1.4

–

1.7

2.0

Notes

LIN physical layer, transceiver (LIN)(114)
IBUSLIM

IBUS_PAS_DOM
IBUS_PAS_REC

Output Current Limitation• Dominant State, VBUS = 18 V
Leakage Output Current to GND• Dominant State; VBUS = 0 V; VBAT = 12 V
• Recessive State; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS
≥ VBAT

IBUS_NO_GND• GND Disconnected; GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS
< 18 V• VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V

IBUS
VBUSDOMVBUSREC
VBUS_CNT
VHYS
VLIN_REC
VLIN_DOM_0

Receiver Input Voltages• Receiver Dominant State• Receiver Recessive State• Receiver Threshold Center (VTH_DOM + VTH_REC)/2• Receiver Threshold Hysteresis (VTH_REC - VTH_DOM)
LIN Transceiver Output Voltage• Recessive State, TXD HIGH, IOUT = 1.0 µA• Dominant State, TXD LOW, 500 Ω External Pull-up Resistor,LDVS = 0• Dominant State, TXD LOW, 500 Ω External Pull-up Resistor,LDVS = 1

VLIN_DOM_1

VSUP

V

RSLAVE

LIN Pull-up Resistor to VSUP

20

30

60

kΩ

TLINSD

Overtemperature Shutdown

150

165

180

°C

Overtemperature Shutdown Hysteresis

–

10

–

°C

TLINSD_HYS

(115)

Notes
114. Parameters guaranteed for 7.0 V ≤ VSUP ≤ 18 V.
115.

When overtemperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.

33912

NXP Semiconductors

65

MC33912G5AC / MC34912G5AC

12.3

Dynamic electrical characteristics

Table 36. Dynamic electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

SPI interface timing (see Figure 36)
f SPIOPSPI Operating Frequency

–

–

4.0

MHz

tPSCLKSCLK Clock Period

250

–

N/A

ns

tWSCLKH

SCLK Clock High Time

110

–

N/A

ns

(116)

tWSCLKLSCLK Clock Low Time

110

–

N/A

ns

(116)

tLEAD

Falling Edge of CS to Rising Edge of SCLK

100

–

N/A

ns

(116)

tLAG

Falling Edge of SCLK to CS Rising Edge

100

–

N/A

ns

(116)

tSISU

MOSI to Falling Edge of SCLK

40

–

N/A

ns

(116)

tSIH

Falling Edge of SCLK to MOSI

40

–

N/A

ns

(116)

tRSO

MISO Rise Time• CL = 220 pF

–

40

–

ns

(116)

tFSO

MISO Fall Time• CL = 220 pF

–

40

–

ns

(116)

0.0
0.0

–
–

50
50

ns

(116)

Time from Rising Edge of SCLK to MISO Data Valid(116)• 0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100 pF

0.0

–

75

ns

(116)

t RST

Reset Low-level Duration After VDD High (see Figure 35)

0.65

1.0

1.35

ms

t RSTDF

Reset Deglitch Filter Time

350

600

900

ns

8.5
79
110

10
94
150

11.5
108
205

tSOEN
tSODIStVALIDTime from Falling or Rising Edges of CS to:• MISO Low-impedance• MISO High-impedance

RST output pin

Window watchdog configuration pin (WDCONF)

t PWD

Watchdog Time Period• External Resistor REXT = 20 kΩ (1%)• External Resistor REXT = 200 kΩ (1%)• Without External Resistor REXT (WDCONF Pin Open)

ms

(117)

Current sense amplifier (116)
CMR

Common Mode Rejection Ratio

70

–

–

dB

SVR

Supply Voltage Rejection Ratio

60

–

–

dB

GBP

Gain Bandwidth Product

0.75

3.0

–

MHz

SR

Output Slew-rate

0.5

–

–

V/µs

(118)

Notes
116. This parameter is guaranteed by process monitoring but not production tested.
117. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)118.

Analog Outputs are supplied by VDD

33912

66

NXP Semiconductors

MC33912G5AC / MC34912G5AC

Table 36. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

8.0

20

38

μs

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop
Command) and Stop mode Activation

–

–

5.0

μs

Normal Request Mode Timeout (see Figure 35)

110

150

205

ms

t S-ON

Delay Between SPI Command and HS /LS Turn On• 9.0 V < VSUP < 27 V

–

–

10

μs

(120)

t S-OFF

Delay Between SPI Command and HS /LS Turn Off• 9.0 V < VSUP < 27 V

–

–

10

μs

(120)

t SNR2N

Delay Between Normal Request and Normal Mode After a Watchdog
Trigger Command (Normal Request Mode)

–

–

10

μs

(119)

t WUCSt WUSPI

Delay Between CS Wake-up (CS LOW to HIGH) in Stop mode and:• Normal Request mode, VDD ON and RST HIGH
• First Accepted SPI Command

9.0
90

15
—

80
N/A

μs

t 2CS

Minimum Time Between Rising and Falling Edge on the CS

4.0

—

—

μs

L1, L2, L3, and L4 inputs
t WUF

Wake-up Filter Time

State machine timingt STOPt NR TOUT(119)

LIN physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec (121), (122)D1Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs• 7.0 V ≤ VSUP ≤ 18 V

0.396

—

—

D2

Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs• 7.6 V ≤ VSUP ≤ 18 V

—

—

0.581

LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec (121), (123)D3Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs• 7.0 V ≤ VSUP ≤ 18 V

0.417

—

—

μs

D4

Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96µs
• 7.6 V ≤ VSUP ≤ 18 V

—

—

0.590

μs

Notes
119. This parameter is guaranteed by process monitoring but not production tested.
120. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to external load.
121. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal thresholddefined at each parameter. See Figure 29.
122. See Figure 30.
123. See Figure 31.

33912

NXP Semiconductors

67

MC33912G5AC / MC34912G5AC

Table 36. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 125 °C for the 33912 and -40 °C ≤ TA ≤ 85 °C for the 34912,
unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unlessotherwise noted.
SymbolCharacteristic

Min.

Typ.

Max.

Unit

Notes

—

20

—

V / μs

—
- 2.0

3.0
—

6.0
2.0

μs

(125)

LIN physical layer: driver characteristics for fast slew rate
SRFAST

LIN Fast Slew Rate (Programming mode)

LIN physical layer: characteristics and wake-up timingst REC_PDt REC_SYM(124)

Propagation Delay and Symmetry• Propagation Delay Receiver, tREC_PD = MAX (tREC_PDR,
tREC_PDF)• Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR

t PROPWLBus Wake-up Deglitcher (Sleep and Stop modes)

42

70

95

μs

(126)

t WAKEt WAKEBus Wake-up Event Reported• From Sleep mode
• From Stop mode

—
9.0

—
13

1500
17

μs

(127)

t TXDDOM

TXD Permanent Dominant State Delay

0.65

1.0

1.35

s

-

10

-

kHz

(128)

Pulse width modulation input pin (PWMIN)fPWMINPWMIN pin
• Max. frequency to drive HS and LS output pins

(129)

Notes
124. VSUP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to
LIN signal threshold defined at each parameter. See Figure 29.
125. See Figure 32.
126. See Figure 33 for Sleep and Figure 34 for Stop mode.
127. The measurement is done with 1µF capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the capacitor. The
delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V. See Figure 33. The
delay depends of the load and capacitor on VDD.
128.

In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 34.

129.

This parameter is guaranteed by process monitoring but not production tested.

33912

68

NXP Semiconductors

MC33912G5AC / MC34912G5AC

12.4

Timing diagrams
33912
1.0 nF

LIN

TRANSIENT PULSE
GENERATOR(NOTE)GND

PGND LGND

AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

Figure 27. Test circuit for transient test pulses (LIN)
33912
Transient Pulse
Generator(Note)

1.0 nF
L1, L2, L3, L4
10 kΩ

GND

PGND LGND AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.

Figure 28. Test circuit for transient test pulses (Lx)
VSUP

TXD

LIN

R0

RXD
C0

R0 AND C0 COMBINATIONS:• 1.0 KΩ and 1.0 nF• 660 Ω and 6.8 nF• 500 Ω and 10 nF

Figure 29. Test circuit for LIN timing measurements

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TXD

VLIN_REC

tBIT

tBIT

tBUS_DOM (MAX)tBUS_REC (MIN)

tREC - MAX
74.4% VSUP

tDOM - MIN
58.1% VSUP
40.0% VSUP

LIN

tDOM - MIN

60.0% VSUP

58.1% VSUP
40.0% VSUP
28.4% VSUP

28.4% VSUP
42.2% VSUP
tREC - MIN

tDOM - MAX

tBUS_DOM (MIN)tBUS_REC (MAX)

RXD

tRDOM

tRREC

Figure 30. LIN timing measurements for normal slew rate
TXD

VLIN_REC

tBIT

tBIT

tBUS_DOM (MAX)tBUS_REC (MIN)

tREC - MAX
tDOM - MIN
LIN

tDOM - MIN
77.8% VSUP

61.6% VSUP
40.0% VSUP

60.0% VSUP

61.6% VSUP
40.0% VSUP
25.1% VSUP

25.1% VSUP
38.9% VSUP
tREC - MIN

tDOM - MAX

tBUS_DOM (MIN)tBUS_REC (MAX)

RXD

tRDOM

tRREC

Figure 31. LIN timing measurements for slow slew rate

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VLIN_REC
VBUSREC
VBUSDOM

VSUP

LIN BUS SIGNALRXD
tRX_PDFtRX_PDR

Figure 32. LIN receiver timing
VLIN_REC

LIN
0.4 VSUPDOMINANT LEVEL

VDD
tPROPWLtWAKE

Figure 33. LIN wake-up sleep mode timing
Vrec
VLIN_REC

LIN
0.4VSUP
0.4 VSUP

Dominant
Level
Dominant level

IRQ

t PROPWL
TpropWLt WAKE
Twake

Figure 34. LIN wake-up stop mode timing

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VSUP

VDD

RST

tNRTOUTtRST

Figure 35. Power on reset and normal request timeout timingtPSCLKCS
tWSCLKH

tLEAD

tLAG

SCLK
tWSCLKL
tSISU

MOSI

UNDEFINED

D0

tSIH

DON’T CARE

D7

DON’T CAREtVALIDtSODIS

tSOEN
MISO

D0

DON’T CARE

D7

Figure 36. SPI timing characteristics

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13Functional description

13.1

Introduction

The 33912 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. The
33912 is well suited to perform relay control in applications like window lift, sunroof, etc. via LIN bus, for automotive body electronics.
Power switches are provided on the device configured as high-side and low-side outputs. Other ports are also provided, which include acurrent and voltage sense port, a Hall Sensor port supply, and four wake-up capable pins. An internal voltage regulator provides power
to a MCU device.
Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible
with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground.

13.2

Functional pin description

See Figure 1, 33912 simplified application diagram, for a graphic representation of the various pins referred to in the following paragraphs.
Also, see the pin diagram on page 55 for a description of the pin locations in the package.

13.2.1 Receiver output pin (RxD)
The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD Low when LIN
bus is dominant, RXD High when LIN bus is recessive.

13.2.2 Transmitter input pin (TXD)
The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD
is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating.

13.2.3 LIN bus pin (LIN)
The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN
bus specification 2.0. The LIN interface is only active during Normal and Normal Request modes.

13.2.4 Serial data clock pin (SCLK)The SCLK pin is the SPI clock input pin. MISO data changes on the negative transition of the SCLK. MOSI is sampled on the positiveedge of the SCLK.

13.2.5 Master out slave in pin (MOSI)The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the positive edge of SCLK.

13.2.6 Master in slave out pin (MISO)
The MISO pin sends data to a SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this
output pin changes on the negative edge of the SCLK. When CS is High, this pin remains in high-impedance state.

13.2.7 Chip select pin (CS)
CS is an active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in thesame SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched.
A valid transmission must consist of 8 bits only. While in STOP mode, a low-to-high level transition on this pin generates a wake-up
condition for the 33912.

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13.2.8 Analog multiplexer pin (ADOUT0)The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer,
including the VSENSE, L1, L2, L3, L4 input voltages, and the internal junction temperature.

13.2.9 Current sense amplifier pin (ADOUT1)The ADOUT1 pin is an analog interface to the MCU A/D converter. It allows the MCU to read the output of the current sense amplifier.

13.2.10PWM input control pin (PWMIN)
This digital input can control the high-sides and low-sides drivers in Normal Request- and Normal mode. To enable PWM control, the MCU
must perform a write operation to the High-side Control register (HSCR) or the Low-side Control register (LSCR). This pin has an internal
20 μA current pull-up.

13.2.11Reset pin (RST)This bidirectional pin is used to reset the MCU in case the 33912 detects a reset condition, or to inform the 33912 the MCU has just been
reset. After release of the RST pin, Normal Request mode is entered. The RST pin is an active low filtered input and output formed by aweak pull-up and a switchable pull-down structure which allows this pin to be shorted either to VDD or to GND during softwaredevelopment, without the risk of destroying the driver.

13.2.12Interrupt pin (IRQ)
The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request mode or to signal a wakeup from Stop mode. This active low output transitions to high only after the interrupt is acknowledged by a SPI read of the respective status
bits.

13.2.13Watchdog configuration pin (WDConf)
The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window
watchdog period. When connected directly to ground, the watchdog is disabled. When this pin is left open, the watchdog period is fixed
to its lower precision internal default value (150 ms typical).

13.2.14Ground connection pins (AGND, PGND, LGND)
The AGND, PGND and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator
and the current sense module. The PGND and LGND pins are used for high current load return as in the relay-drivers and LIN interface pin.
Note: PGND, AGND and LGND pins must be connected together.

13.2.15Current sense amplifier input pins (ISENSEH and ISENSEL)
The ISENSEH and ISENSEL pins are the input pins of a ground compatible differential amplifier designed to be used to sense the voltage
drop over a shunt resistor. The main purpose of this amplifier is to implement accurate current sensors. The gain of the differential amplifier
can be set by the SPI.

13.2.16Low-side pins (LS1 and LS2)LS1 and LS2 are the low-side driver outputs. Those outputs are short-circuit protected and include active clamp circuitry to drive inductive
loads. Due to the energy clamp voltage on this pin, it can raise above the battery level when switched off. The switches are controlled
through the SPI and can be configured to respond to a signal applied to the PWMIN input pin. Both low-side switches are protected against
overheating.

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13.2.17Digital/analog pins (L1, L2, L3, and L4)
The Lx pins are multi purpose inputs. They can be used as digital inputs, which can be sampled by reading the SPI and used for wakeup when 33912 is in Low-power mode or used as analog inputs for the analog multiplexer. When used to sense voltage outside themodule, a 33 kΩ series resistor must be used on each input.
When used as wake-up inputs L1-L4 can be configured to operate in cyclic-sense mode. In this mode one of the high-side switches isconfigured to be periodically turned on and sample the wake-up inputs. If a state change is detected between two cycles a wake-up is
initiated. The 33912 can also wake-up from Stop or Sleep by a simple state change on L1-L4.
When used as analog inputs, the voltage present on the Lx pins is scaled down by an selectable internal voltage divider and can be routed
to the ADOUT0 output through the analog multiplexer.
Note: If an Lx input is selected in the analog multiplexer, it is disabled as a digital input and remains disabled in low power mode. No wakeup feature is available in this condition.
When an Lx input is not selected in the analog multiplexer, the voltage divider is disconnected from this input.

13.2.18High-side output pins (HS1 and HS2)
These two high-side switches are able to drive loads such as relays or lamps. Their structures are connected to the VS2 supply pin. The
pins are short-circuit protected and both outputs are also protected against overheating. HS1 and HS2 are controlled by the SPI and can
respond to a signal applied to the PWMIN input pin. HS1 and HS2 outputs can also be used during Low-power mode for the cyclic-senseof the wake inputs.

13.2.19Power supply pins (VS1 and VS2)Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection
and negative transient voltages with external components. These pins sustain standard automotive voltage conditions such as a load
dump at 40 V. The high-side switches (HS1 and HS2) are supplied by the VS2 pin. All other internal blocks are supplied by VS1 pin.

13.2.20Voltage sense pin (VSENSE)
This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input
is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery
voltage. The ESD structure on this pin allows for excursion up to +40 V and down to -27 V, allowing this pin to be connected directly tothe battery line. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

13.2.21Hall sensor switchable supply pin (HVDD)This pin provides a switchable supply for external hall sensors. While in Normal mode, this current limited output can be controlled throughthe SPI. The HVDD pin needs to be connected to an external capacitor to stabilize the regulated output voltage.

13.2.22+5.0 V main regulator output pin (VDD)
An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply amicrocontroller. The pin is current limited against shorts to GND and overtemperature protected. During Stop mode, the voltage regulator
does not operate with its full drive capabilities and the output current is limited. During Sleep mode, the regulator output is completely
shutdown.

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13.3

Functional internal block description

MC33912 - Functional Block Diagram
Integrated Supply
Hall Sensor Supply
Voltage Regulator
HVDD
VDD
Analog Circuitry
Wake-Up
Window Watchdog

Digital / Analog Input
Voltage, Current & Temperature Sense
MCU Interface and Output Control
SPI Interface

Reset & IRQ Logic

LIN Interface / Control

LS/HS - PWM Control

High Side Drivers
HS1 - HS2
Low Side Drivers
LS1 - LS2
LIN Physical Layer
Interface

Analog Output 0/1
Integrated Supply
Analog Circuitry

MCU Interface and Output Control
Drivers

Figure 37. Functional internal block diagram

13.3.1 Analog circuitry
The 33912 is designed to operate under automotive operating conditions. A fully configurable window watchdog circuit resets theconnected MCU in case of an overflow. Two low power modes are available with several different wake-up sources to reactivate thedevice. Four analog / digital inputs can be sensed or used as the wake-up source. The device is capable of sensing the supply voltage(VSENSE), the internal chip temperature (CTEMP) as well as the motor current using an external sense resistor.

13.3.2 High-side drivers
Two current and temperature protected high-side drivers with PWM capability are provided to drive small loads such as Status LEDs or
small lamps. Both Drivers can be configured for periodic sense during Low-power modes.

13.3.3 Low-side drivers
Two current and temperature protected low-side drivers with PWM capability are provided to drive H-Bridge type relays for power motor
applications

13.3.4 MCU interface
The 33912 provides its control and status information through a standard 8-Bit SPI interface. Critical system events such as Low- or Highvoltage/Temperature conditions as well as overcurrent conditions in any of the driver stages can be reported to the connected MCU via
IRQ or RST. Both low-side and both high-side driver outputs can be controlled via the SPI register as well as the PWMIN input. The
integrated LIN physical layer interface can be configured via the SPI register and its communication is driven through the RXD and TXD
device pins. All internal analog sources are multiplexed to the ADOUT 0 pin. The current sense analog signal is directly routed through
ADOUT1.

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13.3.5 Voltage regulator outputs
Two independent voltage regulators are implemented on the 33912. The VDD main regulator output is designed to supply a MCU with a
precise 5.0 V. The switchable HVDD output is dedicated to supply small peripherals as hall sensors.

13.3.6 LIN physical layer interface
The 33912 provides a LIN 2.0 compatible LIN physical layer interface with selectable slew rate and various diagnostic features.

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14Functional device operations

14.1

Operational modes

14.1.1 Introduction
The 33912 offers three main operating modes: Normal (Run), Stop, and Sleep (Low Power). In Normal mode, the device is active and isoperating under normal application conditions. The Stop and Sleep modes are Low-power modes with wake-up capabilities.
In Stop mode, the voltage regulator still supplies the MCU with VDD (limited current capability), while in Sleep mode the voltage regulator
is turned off (VDD = 0 V). Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset andthe voltage regulator is turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the Mode Control register(MCR). Figure 38 describes how transitions are done between the different operating modes. Table 37 gives an overview of the operating
modes.

14.1.2 Reset mode
The 33912 enters the Reset mode after a power up. In this mode, the RST pin is low for 1ms (typical value). After this delay, it enters theNormal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (VDD low, watchdog trigger
fail, after wake-up from Sleep mode, Normal Request mode timeout occurs).

14.1.3 Normal request modeThis is a temporary mode automatically accessed by the device after the Reset mode, or after a wake-up from Stop mode. In Normal
Request mode, the VDD regulator is ON, the RESET pin is High, and the LIN is operating in RX Only mode.
As soon as the device enters in the Normal Request mode an internal timer is started for 150 ms (typical value). During these 150 ms, theMCU must configure the Timing Control register (TIMCR) and the Mode Control register (MCR) with MOD2 and MOD1 bits set = 0, to
enter the Normal mode. If within the 150 ms timeout, the MCU does not command the 33912 to Normal mode, it enters in Reset mode. If
the WDCONF pin is grounded, to disable the watchdog function, it goes directly in Normal mode after the Reset mode. If the WDCONF
pin is open, the 33912 stays typically for 150 ms in Normal Request before entering in Normal mode.

14.1.4 Normal mode
In Normal mode, all 33912 functions are active and can be controlled by the SPI interface and the PWMIN pin. The VDD regulator is ON
and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog
function is enabled.The wake-up inputs (L1-L4) can be read as digital inputs or have its voltage routed through the analog-multiplexer.
The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0. The LIN bus can transmit and receive
information. The high-side and low-side switches are active and have PWM capability according to the SPI configuration. The interrupts
are generated to report failures for VSUP over/undervoltage, thermal shutdown, or thermal shutdown prewarning on the main regulator.

14.1.5 Sleep mode
The Sleep mode is a Low-power mode. From Normal mode, the device enters into Sleep mode by sending one SPI command throughthe Mode Control register (MCR). All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up inputs
with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. The internal low-power oscillator
may be active if the IC is configured for cyclic-sense. In this condition, one of the high-side switches is turned on periodically and the wakeup inputs are sampled. Wake-up from Sleep mode is similar to a power-up. The device goes in Reset mode except the SPI reports thewake-up source and the BATFAIL flag is not set.

14.1.6 Stop mode
The Stop mode is the second Low-power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The
application MCU is always supplied while the 33912 is operating in Stop mode. The device can enter into Stop mode only by sending the
SPI command. When the application is in this mode, it can wake-up from the 33912 side (for example: cyclic sense, force wake-up, LIN
bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode transitions the 33912 to Normal Request mode andgenerates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin.

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Normal Request
Timeout
Expired(t NRTOUT)
Normal Request
timeout
expired (NR
TOUT)
VVDD
Low
DD Low
VDD High andNormalRequestVVDDLow
Low
DD

VVDD
LOW (>t NRTOUT) expired) Expired
DD Low (>NRTOUT
andand
VSUV
=0
VSUV
=0

Wake-up
Wake-Up (Reset)(Reset)Sleep
CommandSLEEP
Command

Sleep

Stop
STOPCommand
CommandNormalWD
FailedWD
failedWake-Up(Interrupt)
Wake-Up Interrupt

Reset

Reset
Delay
(t Delay
VDD
High and
Reset
RST) expired
RST) (tExpired

WD
Disabled
WD disabledPower Up

WDtrigger
Trigger
WD

Power
Down

Stop

VDD
VDD Low
Low
Legend
WD: Watchdog
Notes:WD Disabled:
Watchdog disabled (WDCONF pin connected to GND)
WD
- meansisWatchdog
WD Trigger:
Watchdog
triggered by a SPI commandWDmeans orWatchdog
disabled(WDCONF
terminal connected to GND)
WD Failed: No disabled
watchdog- trigger
trigger occurs
in closed
window
WD trigger – means Watchdog is triggered by SPI command
Stop Command: Stop command sent via the SPI
WD failed – means no Watchdog trigger or trigger occurs in closed window
Sleep Command: Sleep command sent via the SPISTOP Command - means STOP command sent via SPI
Wake-Up from Stop Mode: L1, L2, L3 or L4 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.
SLEEP
Commandmeans
SLEEP
command
via wake-up,
SPI
Wake-Up from
Sleep
Mode: L1,- L2,
L3 or
L4 statechange,send
LIN bus
Periodic wake-up.
Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Figure 38. Operating modes and transitions

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Table 37. Operating modes overview
Function

Reset mode Normal request mode

Normal mode

Stop mode

Sleep mode

VDD

Full

Full

Full

Stop

-

HVDD

-

SPI(130)

SPI

-

-

LSx

-

SPI/PWM(131)SPI/PWM

-

-

HSx

-

(131)

SPI/PWM(132)

Analog Mux

-

SPI

SPI

-

-

Lx

-

Inputs

InputsWake-up

Wake-up

Current Sense

On

On

On

-

-

LIN

-

Rx-Only

Full/Rx-Only

Rx-Only/Wake-up

Wake-up

(134)

-

-

On

VDD

-

SPI/PWM

Watchdog-

150 ms (typ.) timeout

VSENSE

On

On

On

Note

/Off

Note(133)

Notes
130. Operation can be enabled/controlled by the SPI.
131. Operation can be controlled by the PWMIN input.
132. HSx switches can be configured for cyclic sense operation in Stop mode.
133. HSx switches can be configured for cyclic sense operation in Sleep mode.
134. Windowing operation when enabled by an external resistor.

14.1.7 Interrupts
Interrupts are used to signal a microcontroller peripheral needs to be serviced. The interrupts which can be generated, change according
to the operating mode. While in Normal and Normal Request modes, the 33912 signals through interrupts special conditions which may
require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the Interrupt Source register(ISR).
While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts. Wake-up is performed bypowering-up the MCU. In Normal and Normal Request mode the wake-up source can be read by the SPI. The interrupts are signaled to
the MCU by a low logic level of the IRQ pin, which remains low until the interrupt is acknowledged by a SPI read. The IRQ pin then isdriven high.
Interrupts are only asserted while in Normal, Normal Request and Stop mode. Interrupts are not generated while the RST pin is low. The
following is a list of the interrupt sources in Normal and Normal Request modes. Some of these can be masked by writing to the SPI Interrupt Mask register (IMR).

14.1.7.1

Low-voltage interrupt

Signals when the supply line (VS1) voltage drops below the VSUV threshold (VSUV).

14.1.7.2

High-voltage interrupt

Signals when the supply line (VS1) voltage increases above the VSOV threshold (VSOV).

14.1.7.3

Overtemperature prewarning

Signals when the 33912 temperature has reached the pre-shutdown warning threshold. It is used to warn the MCU an overtemperature
shutdown in the main 5.0 V regulator is imminent.

14.1.7.4

LIN overcurrent shutdown/overtemperature shutdown/TXD stuck at dominant/
RXD short-circuit

These signal fault conditions within the LIN interface causes the LIN driver to be disabled, except for the LIN overcurrent condition. The
fault must be removed and must be acknowledged by reading the SPI to restart the operation. The LINOC bit functionality in the LIN Status
register (LINSR) is to indicate an LIN overcurrent has occurred and the driver remains enabled.

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14.1.7.5

High-side overtemperature shutdown

Signals a shutdown in the high-side outputs.

14.1.7.6

Low-side overtemperature shutdown

Signals a shutdown in the low-side outputs.

14.1.8 ResetTo reset a MCU the 33912 drives the RST pin low for the time the reset condition lasts. After the reset source is removed, the statemachine drives the RST output low for at least 1.0 ms (typical value) before driving it high. In the 33912, four main reset sources exist:

14.1.8.1

5.0 V regulator low-voltage-reset (VRSTTH)

The 5.0 V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects the voltage at the VDD pin has
dropped below the reset threshold VRSTTH, the 33912 issues a reset. In case of an overtemperature, the voltage regulator is disabled andthe voltage monitoring issues a VDDOT Flag independently of the VDD voltage.

14.1.8.2

Window watchdog overflow

If the watchdog counter is not properly serviced while its window is open, the 33912 detects an MCU software run-away and resets the
microcontroller.

14.1.8.3

Wake-up from sleep mode

During Sleep mode, the 5.0 V regulator is not active, hence all wake-up requests from Sleep mode require a power-up/reset sequence.

14.1.8.4

External reset

The 33912 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low.
The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality
is also active in Stop mode. After the RST pin is released, there is no extra t RST to be considered.

14.1.9 Wake-up capabilities
Once entered into one of the Low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation.
In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode the wake-up is performed by activating the 5.0 V
regulator and resetting the MCU. In both cases, the MCU can detect the wake-up source by accessing the SPI registers. There is no
specific SPI register bit to signal a CS wake-up or external reset. If necessary, this condition is detected by excluding all other possible
wake-up sources.

14.1.9.1

Wake-up from wake-up inputs (L1-L4) with cyclic sense disabled

The wake-up lines are dedicated to sense state changes of external switches and wake-up the MCU (in Sleep or Stop mode). To selectand activate direct wake-up from Lx inputs, the Wake-up Control register (WUCR) must be configured with appropriate LxWE inputs
enabled or disabled. The wake-up input’s state is read through the Wake-up Status register (WUSR). Lx inputs are also used to perform
cyclic-sense wake-up.
Note: Selecting an Lx input in the analog multiplexer before entering low power mode disables the wake-up capability of the Lx input

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14.1.9.2

Wake-up from wake-up inputs (L1-L4) with cyclic sense timer enabled

The SBCLIN can wake-up at the end of a cyclic sense period if on one of the four wake-up input lines (L1-L4) a state change occurs. The
HSx switch is activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wake-up are exclusive. If cyclic sense isenabled, the force wake-up can not be enabled. In order to select and activate the cyclic sense wake-up from Lx inputs, before enteringin low power modes (Stop or Sleep modes), the following SPI set-up has to be performed:
In WUCR: select the Lx input to WU-enable.
In HSCR: enable the desired HSx.
• In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits.
• Perform Goto Sleep/Stop command.

14.1.9.3

Forced wake-up

The 33912 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and Forced wake-up are
exclusive. If Forced wake-up is enabled, the Cyclic Sense can not be enabled.
To determine the wake-up period, the following SPI set-up has to be sent before entering in Low-power modes:• In TIMCR: select the CS/WD bit and determine the Low-power mode period with CYSTx bits.
• In HSCR: all HSx bits must be disabled.

14.1.9.4

CS wake-up

While in Stop mode, a rising edge on the CS causes a wake-up. The CS wake-up does not generate an interrupt, and is not reported on
the SPI.

14.1.9.5

LIN wake-up

While in the Low-power mode, the 33912 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by adominant to recessive transition causes a LIN wake-up. This behavior protects the system from a short to ground bus condition.

14.1.9.6

RST wake-up

While in Stop mode, the 33912 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. The 33912 thenchanges to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate aninterrupt and is not reported via the SPI.
From Stop mode, the following wake-up events can be configured:• Wake-up from Lx inputs without cyclic sense• Cyclic sense wake-up inputs• Force wake-up• CS wake-up• LIN wake-up• RST wake-up
From Sleep mode, the following wake-up events can be configured:• Wake-up from Lx inputs without cyclic sense• Cyclic sense wake-up inputs• Force wake-up• LIN wake-up

14.1.10Window watchdog
The 33912 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external
resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears
are performed by writing through the SPI in the MOD bits of the Mode Control register (MCR).
During the first half of the SPI timeout, watchdog clears are not allowed, but after the first half of the SPI timeout window, the clear
operation opens. If a clear operation is performed outside the window, the 33912 resets the MCU, in the same way as when the watchdog
overflows.

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WINDOW CLOSEDNO WATCHDOG CLEAR
ALLOWEDWD TIMING X 50%

WINDOW OPEN
FOR WATCHDOG
CLEAR

WD TIMING X 50%

WD PERIOD (tPWD)
WD TIMING SELECTED BY REGISTERON WDCONF PIN

Figure 39. Window watchdog operation
To disable the watchdog function in Normal mode the user must connect the WDCONF pin to ground. This measure effectively disables
Normal Request mode. The WDOFF bit in the Watchdog Status register (WDSR) is set. This condition is only detected during Reset mode.
If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms(typ.) and signals the faulty condition through the Watchdog Status register (WDSR).
The watchdog timebase can be further divided by a prescaler which can be configured by the Timing Control register (TIMCR). During
Normal Request mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. Incase of a timeout, the 33912 enters into Reset mode, resetting the microcontroller before entering again into Normal Request mode.

14.1.11High-side output pins HS1 and HS2
These outputs are two high-side drivers intended to drive small resistive loads or LEDs incorporating the following features:• PWM capability (software maskable)• Open load detection• Current limitation• Overtemperature shutdown (with maskable interrupt)• High-voltage shutdown (software maskable)• Cyclic sense
The high-side switches are controlled by the bits HS1:2 in the high-side Control register (HSCR).

14.1.11.1 PWM capability (direct access)Each high-side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in
the High-side Control register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low.
This applies to HS2 configuring HS2 and PWMHS2 bits.

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Interrupt
Control
ModuleMOD1:2
HSx
HSxOP

VDD
VDD
PWMIN

High-side Interrupt

High-voltage Shutdown

HVSE

PWMHSxVS2

on/offControlStatusHSxCL

HIgh-side - Drivercharge pumpopen load detection
current limitation
Overtemperture shutdown (interrupt maskable)
High-voltage shutdown (maskable)

Cyclic Sense

HSx

Wake-up
ModuleFigure 40. High-side drivers HS1 and HS2

14.1.11.2 Open load detection
Each high-side driver signals an open load condition if the current through the high-side is below the open load current threshold. The
open load condition is indicated with the bits HS1OP and HS2OP in the High-side Status register (HSSR).

14.1.11.3 Current limitation
Each high-side driver has an output current limitation. In combination with the overtemperature shutdown the high-side drivers areprotected against overcurrent and short-circuit failures. When the driver operates in the current limitation area, it is indicated with the bits
HS1CL and HS2CL in the HSSR.
Note: If the driver is operating in current limitation mode, excessive power might be dissipated.

14.1.11.4 Overtemperature protection (HS interrupt)
Both high-side drivers are protected against overtemperature. In case of an overtemperature condition both high-side drivers are
shutdown and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source
register (ISR). A thermal shutdown of the high-side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. If the bit HSM
is set in the Interrupt Mask register (IMR), then an interrupt (IRQ) is generated. A write to the High-side Control register (HSCR), when
the overtemperature condition is gone, re-enables the high-side drivers.

14.1.11.5 High-voltage shutdown
In case of a high-voltage condition and if the high-voltage shutdown is enabled (bit HVSE in the Mode Control register (MCR) is set), both
high-side drivers are shutdown. A write to the High-side Control register (HSCR), when the high-voltage condition is gone, re-enables thehigh-side drivers.

14.1.11.6 Sleep and stop mode
The high-side drivers can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 37.

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14.1.12Low-side output pins (LS1 and LS2)
These outputs are two low-side drivers intended to drive relays incorporating the following features:• PWM capability (software maskable)• Open load detection• Current limitation• Overtemperature shutdown (with maskable interrupt)• Active clamp (for driving relays)• High-voltage shutdown (software maskable)
The low-side switches are controlled by the bit LS1:2 in the Low-side Control register (LSCR). To protect the device against overvoltage
when an inductive load (relay) is turned off. An active clamp re-enables the low-side FET if the voltage on the LS1 or LS2 pin exceeds acertain level.

14.1.12.1 PWM capability (direct access)Each low-side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits LS1 and PWMLS1 are set in
the Low-side Control register (LSCR), then the LS1 driver is turned on if the PWMIN pin is high and turned off if the PWMIN pin is low.
The same applies to the LS2 and PWMLS2 bits for the LS2 driver.

HVSE

VDD

Interrupt
Control
Module

VDD

MOD1:2LSx
LSxOP

PWMLSx

Low-side Interrupt

High-voltage Shutdown

PWMIN

activeclamp
LSxon/offControlStatus

LSxCL

Low-side Driver(active clamp)
Open load Detection
Current Limitation
Overtemperture Shutdown (interrupt maskable)
High-voltage shutdown (maskable)
PGND

Figure 41. Low-side drivers LS1 and LS2

14.1.12.2 Open load detection
Each low-side driver signals an open load condition if the current through the low-side is below the open load current threshold. The open
load condition is indicated with the bit LS1OP and LS2OP in the Low-side Status register (LSSR).

14.1.12.3 Current limitation
Each low-side driver has a current limitation. In combination with the overtemperature shutdown the low-side drivers are protected against
overcurrent and short-circuit failures. When the drivers operate in current limitation, this is indicated with the bits LS1CL and LS2CL in the
LSSR.
Note: If the drivers are operating in current limitation mode excessive power might be dissipated.

14.1.12.4 Overtemperature protection (LS interrupt)
Both low-side drivers are protected against overtemperature. In case of an overtemperature condition both low-side drivers are shutdown
and the event is latched in the Interrupt Control Module. The shutdown is indicated as an LS Interrupt in the Interrupt Source register (ISR).
If the bit LSM is set in the Interrupt Mask register (IMR) than an Interrupt (IRQ) is generated. A write to the Low-side Control register(LSCR), when the overtemperature condition is gone, re-enables the low-side drivers.

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14.1.12.5 High-voltage shutdown
In case of a high-voltage condition and if the high-voltage shutdown is enabed (bit HVSE in the Mode Control register (MCR) is set) both
low-sides drivers are shutdown. A write to the Low-side Control register (LSCR), when the high-voltage condition is gone, re-enables thelow-side drivers.

14.1.12.6 Sleep and stop mode
The low-side drivers are disabled in Sleep and Stop mode. Also see Table 37.

14.1.13LIN physical layer
The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed tomeet the LIN physical layer specification and has the following features:• LIN physical layer 2.0 compliant• Slew rate selection• Overcurrent shutdown• Overtemperature shutdown• LIN pull-up disable in Stop and Sleep modes• Advanced diagnostics• LIN dominant voltage level selection
The LIN driver is a low-side MOSFET with overcurrent and thermal shutdown. An internal pull-up resistor with a serial diode structure is
integrated, so no external pull-up components are required for the application in a slave node. The fall time from dominant to recessive
and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed.

14.1.13.1 LIN pin
The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance.

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INTERRUPTCONTROL
MODULE

High-voltage
Shutdown

High-side
Interrupt

WAKE-UP
MODULELIN
Wake-up

MOD1:2
LSR0:1VS1

LINPE

LIN – DRIVERLDVSRXONLYRXSHORT

Slope and Slew Rate Control
Overcurrent Shutdown (interrupt maskable)
Overtemperature Shutdown (interrupt maskable)

TXDOM
LINOT
LINOC
30K
LIN
TXD
SLOPE
CONTROL
WAKE-UPFILTER

LGND

RXD
RECEIVER

Figure 42. LIN interface

14.1.13.2 Slew rate selection
The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew
rate can be adapted with the bits LSR 1:0 in the LIN Control register (LINCR). The initial slew rate is optimized for 20 kBit/s.

14.1.13.3 LIN pull-up disable in stop and sleep modes
In cases of a LIN bus short to GND or LIN bus leakage during Low-power mode, the internal pull-up resistor on the LIN pin can be
disconnected by clearing the LINPE bit in the Mode Control register (MCR). The LINPE bit also changes the Bus wake-up threshold(VBUSWU). This feature reduces the current consumption in STOP and SLEEP modes. It also improves performance and safe operation.

14.1.13.4 Current limit (LIN interrupt)
The output low-side FET is protected against overcurrent conditions. In case of an overcurrent condition (e.g. LIN bus short to VBAT), thetransmitter is not shutdown. The bit LINOC in the LIN Status register (LINSR) is set. If the LINM bit is set in the Interrupt Mask register(IMR), an Interrupt IRQ is generated.

14.1.13.5 Overtemperature shutdown (LIN interrupt)
The output low-side FET is protected against overtemperature conditions. In case of an overtemperature condition, the transmitter is
shutdown and the LINOT bit in the LIN Status register (LINSR) is set. If the LINM bit is set in the Interrupt Mask register (IMR), an Interrupt
IRQ is generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. A read of the LIN Status register(LINSR) with the TXD pin high, re-enables the transmitter.

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14.1.13.6 RXD short-circuit detection (LIN interrupt)
The LIN transceiver has a short-circuit detection for the RXD output pin. In cases of a short-circuit condition, either 5.0 V or Ground, the
RXSHORT bit in the LIN Status register (LINSR) is set and the transmitter is shutdown. If the LINM bit is set in the Interrupt Mask register(IMR), an Interrupt IRQ is generated. The transmitter automatically re-enables once the condition is gone (transition on RXD) and TXD ishigh. A read of the LIN Status register (LINSR) without the RXD pin short-circuit condition clears the bit RXSHORT.

14.1.13.7 TXD dominant detection (LIN interrupt)
The LIN transceiver monitors the TXD input pin to detect a stuck in dominant (0V) condition. In case of a stuck condition (TXD pin 0 V for
more than 1 second (typ.)), the transmitter is shutdown and the TXDOM bit in the LIN Status register (LINSR) is set. If the LINM bit is set
in the IMR, an Interrupt IRQ is generated. The transmitter automatically re-enables once TXD is high. A read of the LIN Status register(LINSR) with the TXD pin at 5.0 V clears the bit TXDOM.

14.1.13.8 LIN dominant voltage level selection
The LIN dominant voltage level can be selected by the bit LDVS in the LIN Control register (LINCR).

14.1.13.9 LIN receiver operation only
While in Normal mode, the activation of the RXONLY bit disables the LIN TXD driver. If case of a LIN error condition, this bit isautomatically set. If a Low-power mode is selected with this bit set, the LIN wake-up functionality is disabled, then in STOP mode, theRXD pin reflects the state of the LIN bus.

14.1.13.10Stop mode and wake-up feature
During Stop mode operation, the transmitter of the physical layer is disabled. If the LIN-PU bit was set in the Stop mode sequence, theinternal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in the recessive state. The receiver isstill active and able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge
generates a wake-up interrupt, and is reported in the Interrupt Source register (ISR). Also see Figure 34.

14.1.13.11Sleep mode and wake-up feature
During Sleep mode operation, the transmitter of the physical layer is disabled. If the LIN-PU bit was set in the Sleep mode sequence, theinternal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in recessive state. The receiver must be
active to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge generates a system
wake-up (Reset), and is reported in the Interrupt Source register (ISR). Also see Figure 33.

14.2

Logic commands and registers

14.2.1 33912 SPI interface and configuration
The serial peripheral interface creates the communication link between a microcontroller (master) and the 33912. The interface consistsof four pins (see Figure 43):
• CS — Chip Select• MOSI — Master-Out Slave-In• MISO — Master-In Slave-Out• SCLK— Serial Clock
A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0)
and the slave replies with 4 system status bits (VMS,LINS,HSS,LSS) + 4 bits of status information (S3:S0).

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CS

Register Write Data
MOSI

A3

A2

A1

A0

C3

C2

C1

C0

S1

S0

Register Read DataMISO

VMS LINS HSS

LSS

S3

S2

SCLK
Read Data Latch

Rising Edge of SCLK
Change MISO/MISO Output

Write Data Latch

Falling Edge of SCLK
Sample MISO/MISO Input

Figure 43. SPI protocol
During the inactive phase of the CS (HIGH), the new data transfer is prepared. The falling edge of the CS indicates the start of a new datatransfer and puts the MISO in the low-impedance state and latches the analog status data (register read data). With the rising edge of the
SPI clock (SCLK), the data is moved to MISO/MOSI pins. With the falling edge of the SPI clock (SCLK), the data is sampled by thereceiver.
The data transfer is only valid if exactly 8 sample clock edges are present during the active (low) phase of CS. The rising edge of the Chip
Select CS indicates the end of the transfer and latches the write data (MOSI) into the register. The CS high forces MISO to the highimpedance state. Register reset values are described along with the reset condition. Reset condition is the condition causing the bit to be
set to its reset value. The main reset conditions are:- Power-On Reset (POR): the level at which the logic is reset and BATFAIL flag sets.
- Reset mode
- Reset done by the RST pin (ext_reset)

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14.3

SPI register overview

Table 38. System status register
Address(A3:A0)$0 - $F

BIT

Register name / read / write information
SYSSR - System Status Register

R

7

6

5

4

VMS

LINS

HSS

LSS

Table 39 summarizes the SPI register content for Control Information (C3:C0)=W and status information (S3:S0) = R.
Table 39. SPI register overview
Address(A3:A0)

$0
$1
$2
$3
$4
$5
$6
$7
$8
$9

$A

BIT

Register name / read / write information

3

2

1

0

MCR - Mode Control Register

W

HVSE

LINPE

MOD2

MOD1

VSR - Voltage Status Register

R

VSOV

VSUV

VDDOT

BATFAIL

VSR - Voltage Status Register

R

VSOV

VSUV

VDDOT

BATFAILWUCR - Wake-up Control Register

W

L4WE

L3WE

L2WE

L1WE

WUSR - Wake-up Status Register

R

L4

L3

L2

L1

WUSR - Wake-up Status Register

R

L4

L3

L2

L1

LINCR - LIN Control Register

W

LDVS

RXONLYLSR1

LSR0

LINSR - LIN Status RegisterR

RXSHORT

TXDOM

LINOT

LINOC

LINSR - LIN Status RegisterR

RXSHORT

TXDOM

LINOT

LINOC

HSCR - High-side Control RegisterW

PWMHS2PWMHS1HS2HS1HSSR - High-side Status Register

R

HS2OP

HS2CL

HS1OP

HS1CL

HSSR - High-side Status Register

R

HS2OP

HS2CL

HS1OP

HS1CL

LSCR - Low-side Control RegisterW

PWMLS2PWMLS1LS2LS1LSSR - Low-side Status Register

R

LS2OP

LS2CL

LS1OP

LS1CL

LSSR - Low-side Status Register

R

LS2OP

LS2CL

LS1OP

LS1CL

TIMCR - Timing Control Register

W

CS/WD

WD2

WD1

WD0

CYST2

CYST1

CYST0

WDSR - Watchdog Status Register

R

WDTO

WDERR

WDOFF

WDWO

$B

WDSR - Watchdog Status Register

R

WDTO

WDERR

WDOFF

WDWO

$C

AMUXCR - Analog Multiplexer Control Register

W

LXDS

MX2

MX1

MX0

$D

CFR - Configuration Register

W

HVDD

CYSX8

CSAZ

CSGS

$E
$F

IMR - Interrupt Mask Register

W

HSM

LSM

LINM

VMM

ISR - Interrupt Source Register

R

ISR3

ISR2

ISR1

ISR0

ISR - Interrupt Source Register

R

ISR3

ISR2

ISR1

ISR0

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14.3.1 Register definitions
14.3.1.1

System status register - SYSSRThe System Status register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It
summarizes the status of the Voltage Status register (VSR), LIN Status register (LINSR), High-side Status register (HSSR), and the Lowside Status register (LSSR).
Table 40. System status register

Read

14.3.1.1.1

S7

S6

S5

S4

VMS

LINS

HSS

LSS

VMS - voltage monitor status

This read-only bit indicates one or more bits in the VSR are set.
1 = Voltage Monitor bit set
0 = NoneBATFAIL
VDDOT
VSUV

VMS

VSOV
Figure 44. Voltage monitor status

14.3.1.1.2

LINS - LIN status

This read-only bit indicates one or more bits in the LINSR are set.
1 = LIN Status bit set
0 = None

LINOC
LINOT
TXDOM

LINS

RXSHORT
Figure 45. LIN status

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14.3.1.1.3

HSS - high-side switch status

This read-only bit indicates one or more bits in the HSSR are set.
1 = High-side Status bit set
0 = None

HS1CL
HS1OP
HS2CL

HSS

HS2OP

Figure 46. High-side status

14.3.1.1.4

LSS - low-side switch status

This read-only bit indicates one or more bits in the LSSR are set.
1 = Low-side Status bit set
0 = None

LS1CL
LS1OP
LS2CL

LSS

LS2OP

Figure 47. Low-side status

14.3.1.2

Mode control register - MCR

The Mode Control register (MCR) allows switching between the operation modes and to configure the 33912. Writing the MCR returns
the VSR.
Table 41. Mode control register - $0
C3

C2

C1

C0

Write

HVSE

LINPE

MOD2

MOD1

Reset Value

1

1

-

-

Reset Condition

POR

POR

-

-

14.3.1.2.1

HVSE - high-voltage shutdown enable

This write-only bit enables/disables automatic shutdown of the high-side and the low-side drivers during a high-voltage VSOV condition.
1 = automatic shutdown enabled
0 = automatic shutdown disabled

14.3.1.2.2

LINPE - LIN pull-up enable.

This write-only bit enables/disables the 30 kΩ LIN pull-up resistor in STOP and SLEEP modes. This bit also controls the LIN bus wake-up
threshold.
1 = LIN pull-up resistor enabled
0 = LIN pull-up resistor disabled

14.3.1.2.3

MOD2, MOD1 - mode control bits

These write-only bits select the operating mode and allow clearing the watchdog in accordance with Table 85 Mode Control Bits.
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Table 42. Mode control bits
MOD2

MOD1

Description00Normal Mode01

Stop Mode

10

Sleep Mode11Normal Mode + Watchdog Clear

14.3.1.3

Voltage status register - VSR

Returns the status of the several voltage monitors. This register is also returned when writing to the Mode Control register (MCR).
Table 43. Voltage status register - $0/$1

Read

S3

S2

S1

S0

VSOV

VSUV

VDDOT

BATFAIL

14.3.1.3.1

VSOV - VSUP overvoltage

This read-only bit indicates an overvoltage condition on the VS1 pin.
1 = Overvoltage condition.
0 = Normal condition.

14.3.1.3.2

VSUV - VSUP undervoltage

This read-only bit indicates an undervoltage condition on the VS1 pin.
1 = Undervoltage condition.
0 = Normal condition.

14.3.1.3.3

VDDOT - main voltage regulator overtemperature warningThis read-only bit indicates the main voltage regulator temperature reached the Overtemperature Prewarning threshold.
1 = Overtemperature Prewarning
0 = Normal

14.3.1.3.4

BATFAIL - battery fail flag

This read-only bit is set during power-up and indicates the 33912 had a Power-On-Reset (POR).
Any access to the MCR or VSR clears the BATFAIL flag.
1 = POR Reset has occurred
0 = POR Reset has not occurred

14.3.1.4

Wake-up control register - WUCR

This register is used to control the digital wake-up inputs. Writing the WUCR returns the Wake-up Status register (WUSR).
Table 44. Wake-up control register - $2
C3

C2

C1

C0

Write

L4WE

L3WE

L2WE

L1WE

Reset Value

1

1

1

1

Reset Condition

POR, Reset mode or ext_reset

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14.3.1.4.1

LxWE - wake-up input x enable

This write-only bit enables/disables which Lx inputs are enabled. In Stop and Sleep mode the LxWE bit determines which wake inputs areactive for wake-up. If one of the Lx inputs is selected on the analog multiplexer, the corresponding LxWE is masked to 0.
1 = Wake-up Input x enabled.
0 = Wake-up Input x disabled.

14.3.1.5

Wake-up status register - WUSR

This register is used to monitor the digital wake-up inputs and is also returned when writing to the WUCR.
Table 45. Wake-up status register - $2/$3

Read

S3

S2

S1

S0

L4

L3

L2

L1

14.3.1.5.1

Lx - wake-up input x

This read-only bit indicates the status of the corresponding Lx input. If the Lx input is not enabled, then the according Wake-up status
returns 0. After a wake-up from Stop or Sleep mode these bits also allow to determine which input has caused the wake-up, by first reading
the Interrupt Status register (ISR) and then reading the WUSR.
1 = Lx Wake-up.
0 = Lx Wake-up disabled or selected as analog input.

14.3.1.6

LIN control register - LINCRThis register controls the LIN physical interface block. Writing the LIN Control register (LINCR) returns the LIN Status register (LINSR).
Table 46. LIN control register - $4
C3

C2

C1

C0

Write

LDVS

RXONLYLSR1

LSR0

Reset Value

0

0

0

0

POR, Reset modeor ext_reset

POR, Reset mode,
ext_reset or LIN failure
gone*

Reset Condition

POR* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag resets automatically when the failure is gone.

14.3.1.6.1

LDVS - LIN dominant voltage selectThis write-only bit controls the LIN Dominant voltage:
1 = LIN Dominant Voltage = VLIN_DOM_1 (1.7V typ)
0 = LIN Dominant Voltage = VLIN_DOM_0 (1.1V typ)14.3.1.6.2

RXONLY - LIN receiver operation onlyThis write-only bit controls the behavior of the LIN transmitter. In Normal mode, the activation of the RXONLY bit disables the LINtransmitter. In case of a LIN error condition, this bit automatically sets. In Stop mode this bit disables the LIN wake-up functionality, andthe RXD pin reflects the state of the LIN bus.
1 = only LIN receiver active (Normal mode) or LIN wake-up disabled (Stop mode).
0 = LIN fully enabled.

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14.3.1.6.3

LSRx - LIN slew rate

This write-only bit controls the LIN driver slew-rate in accordance with Table 47.
Table 47. LIN slew rate control
LSR1

LSR0

Description00Normal Slew Rate (up to 20 kb/s)

0

1

Slow Slew Rate (up to 10 kb/s)

1

0

Fast Slew Rate (up to 100 kb/s)

1

1

Reserved

14.3.1.7

LIN status register - LINSRThis register returns the status of the LIN physical interface block and is also returned when writing to the LINCR.
Table 48. LIN status register - $4/$5

Read

S3

S2

S1

S0

RXSHORT

TXDOM

LINOT

LINOC

14.3.1.7.1

RXSHORT - RXD pin short-circuit

This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The short-circuit delay must bea worst case of 8.0 µs to be detected and to shutdown the driver. To clear this bit, it must be read after the condition is gone (transition
detected on RXD pin). The LIN driver automatically re-enables once the condition is gone.
1 = RXD short-circuit condition.
0 = None.

14.3.1.7.2

TXDOM - TXD permanent dominantThis read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LINtransmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second (typical value). To clear this bit,it must be read after TXD has gone high. The LIN driver automatically re-enables once TXD goes High.
1 = TXD stuck at dominant fault detected.
0 = None.

14.3.1.7.3

LINOT - LIN driver overtemperature shutdown

This read-only bit signals the LIN transceiver was shutdown due to overtemperature. The transmitter automatically re-enables after theovertemperature condition is gone and TXD is high. The LINOT bit clears after a SPI read once the condition is gone.
1 = LIN overtemperature shutdown
0 = None

14.3.1.7.4

LINOC - LIN driver overcurrent shutdown

This read-only bit signals an overcurrent condition occurred on the LIN pin. The LIN driver is not shutdown but an IRQ is generated. To
clear this bit, it must be read after the condition is gone.
1 = LIN overcurrent shutdown
0 = None

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14.3.1.8

High-side control register - HSCR

This register controls the operation of the high-side drivers. Writing to this register returns the High-side Status register (HSSR).
Table 49. High-side control register - $6
C3
Write

C2

PWMHS2 PWMHS1

Reset Value0

Reset Condition

14.3.1.8.1

C1

C0

HS2

HS1

0

0

0
POR

POR, Reset mode, ext_reset,
HSx overtemp or (VSOV &HVSE)PWMHSx - PWM input control enable

This write-only bit enables/disables the PWMIN input pin to control the respective high-side switch. The corresponding high-side switch
must be enabled (HSx bit).
1 = PWMIN input controls HSx output.
0 = HSx is controlled only by the SPI.

14.3.1.8.2

HSx - HSx switch control

This write-only bit enables/disables the corresponding high-side switch.
1 = HSx switch on.
0 = HSx switch off.

14.3.1.9

High-side status register - HSSRThis register returns the status of the high-side switches and is also returned when writing to the HSCR.
Table 50. High-side status register - $6/$7

Read

S3

S2

S1

S0

HS2OP

HS2CL

HS1OP

HS1CL

14.3.1.9.1

High-side thermal shutdown

A thermal shutdown of the high-side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously.

14.3.1.9.2

HSxOP - high-side switch open load detection

This read-only bit signals the high-side switches are conducting current below a certain threshold indicating possible load disconnection.
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal

14.3.1.9.3

HSxCL - high-side current limitation

This read-only bit indicates the respective high-side switch is operating in current limitation mode.
1 = HSx in current limitation (or thermal shutdown)
0 = Normal

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14.3.1.10 Low-side control register - LSCR
This register controls the operation of the low-side drivers. Writing the Low-side Control register (LSCR) also returns the Low-side Status
register (LSSR).
Table 51. Low-side control register - $8
C3
Write

C2

PWMLS2 PWMLS1

Reset Value0

Reset Condition

0
POR

C1

C0

LS2

LS1

0

0

POR, Reset mode, ext_reset,
LSx overtemp or (VSOV &HVSE)

14.3.1.10.1 PWMLx - PWM input control enable
This write-only bit enables/disables the PWMIN input pin to control the respective low-side switch. The corresponding low-side switch must
be enabled (LSx bit).
1 = PWMIN input controls LSx.
0 = LSx is controlled only by the SPI.

14.3.1.10.2 LSx - LSx switch control
This write-only bit enables/disables the corresponding low-side switch.
1 = LSx switch on.
0 = LSx switch off.

14.3.1.11 Low-side status register - LSSR
This register returns the status of the low-side switches and is also returned when writing to the LSCR.
Table 52. Low-side status register - $8/$9

Read

C3

C2

C1

C0

LS2OP

LS2CL

LS1OP

LS1CL

14.3.1.11.1 Low-side thermal shutdown
A thermal shutdown of the low-side drivers is indicated by setting all LSxOP and LSxCL bits simultaneously.

14.3.1.11.2 LSxOP - low-side switch open load detection
This read-only bit signals the low-side switches are conducting current below a certain threshold indicating possible load disconnection.
1 = LSx Open Load detected (or thermal shutdown)
0 = Normal

14.3.1.11.3 LSxCL - low-side current limitation
This read-only bit indicates the respective low-side switch is operating in current limitation mode.
1 = LSx in current limitation (or thermal shutdown)
0 = Normal

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14.3.1.12 Timing control register - TIMCR
This register is a double purpose register which allows to configure the watchdog and the cyclic sense periods. Writing to the Timing
Control register (TIMCR) also returns the Watchdog Status register (WDSR).
Table 53. Timing control register - $A
C3
Write

CS/WD

Reset Value-

Reset Condition

-

C2

C1

C0

WD2

WD1

WD0

CYST2

CYST1

CYST0

0

0

0

POR

14.3.1.12.1 CS/WD - cyclic sense or watchdog prescaler selectThis write-only bit selects which prescaler is being written to, the Cyclic Sense prescaler or the Watchdog prescaler.
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select14.3.1.12.2 WDx - watchdog prescalerThis write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 54.
This configuration is valid only if windowing watchdog is active.
Table 54. Watchdog prescaler
WD2

WD1

WD0

Prescaler divider

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

6

1

0

0

8

1

0

1

10

1

1

0

12

1

1

1

14

14.3.1.12.3 CYSTx - cyclic sense period prescaler selectThis write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the Configuration register (CFR) (seeConfiguration register - CFR). This option is only active if one of the high-side switches is enabled when entering in Stop or Sleep mode.
Otherwise a timed wake-up is performed after the period shown in Table 55.
Table 55. Cyclic sense interval
CYSX8(135)

CYST2

CYST1

CYST0

Interval

X

0

0

0

No cyclic sense

0

0

0

1

20 ms

0

0

1

0

40 ms

0

0

1

1

60 ms

0

1

0

0

80 ms

0

1

0

1

100 ms01

1

0

120 ms01

1

1

140 ms1001

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Table 55. Cyclic sense interval (continued)
CYSX8(135)

CYST2

CYST1

CYST0

Interval

1

0

1

0

320 ms10

1

1

480 ms1

1

0

0640 ms1

1

0

1

800 ms1

1

1

0

960 ms111

11120 ms

Notes
135. bit CYSX8 is located in Configuration register (CFR)

14.3.1.13 Watchdog status register - WDSR
This register returns the Watchdog status information and is also returned when writing to the TIMCR.
Table 56. Watchdog status register - $A/$B

Read

S3

S2

S1

S0

WDTO

WDERR

WDOFF

WDWO

14.3.1.13.1 WDTO - watchdog timeout
This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the Watchdog within the windowclosed. Any access to this register or the Timing Control register (TIMCR) clears the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None

14.3.1.13.2 WDERR - watchdog error
This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision
timebase. The Windowing function is disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating

14.3.1.13.3 WDOFF - watchdog off
This read-only bit signals the watchdog pin connected to Ground and therefore disabled. In this case watchdog timeouts are disabled andthe device automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming theFlash memory.
1 = Watchdog is disabled
0 = Watchdog is enabled

14.3.1.13.4 WDWO - watchdog window open
This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored if WDERR
is High.
1 = Watchdog window open
0 = Watchdog window closed

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14.3.1.14 Analog multiplexer control register - MUXCRThis register controls the analog multiplexer and selects the divider ration for the Lx input divider.
Table 57. Analog multiplexer control register -$C
C3

C2

C1

C0

Write

LXDS

MX2

MX1

MX0

Reset Value

1

0

0

0

Reset Condition

POR

POR, Reset mode or
ext_reset

14.3.1.14.1 LXDS - Lx analog input divider selectThis write-only bit selects the resistor divider for the Lx analog inputs. Voltage is internally clamped to VDD.
0 = Lx Analog divider: 1
1 = Lx Analog divider: 3.6 (typ.)14.3.1.15 MXx - analog multiplexer input select
These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 58. When disabled or when in Stopor Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption.
Table 58. Analog multiplexer channel select
MX2

MX1

MX0

Meaning000Disabled001

Reserved010

Die Temperature Sensor

0

1

1

VSENSE input

1

0

0

L1 input

10

1

L2 input1

1

0

L3 input

1

1

1

L4 input

14.3.1.16 Configuration register - CFRThis register controls the Hall Sensor Supply enable/disable, the cyclic sense timing multiplier, enables/disables the Current Sense Autozero function and selects the gain for the current sense amplifier.
Table 59. Configuration register - $D
C3

C2

C1

C0

Write

HVDD

CYSX8

CSAZ

CSGS

Reset Value

0

0

0

0

POR

POR

POR

POR, Reset mode
Reset Condition
or ext_reset

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14.3.1.16.1 HVDD - Hall sensor supply enable
This write-only bit enables/disables the state of the hall sensor supply.
1 = HVDD on
0 = HVDD off

14.3.1.16.2 CYSX8 - cyclic sense timing x 8
This write-only bit influences the cyclic sense period as shown in Table 55.
1 = Multiplier enabled
0 = None

14.3.1.16.3 CSAZ - current sense auto-zero function enable
This write-only bit enables/disables the circuitry to lower the offset voltage of the current sense amplifier.
1 = Auto-zero function enabled
0 = Auto-zero function disabled

14.3.1.16.4 CSGS - current sense amplifier gain selectThis write-only bit selects the gain of the current sense amplifier.
1 = 14.5 (typ.)0 = 30 (typ.)14.3.1.17 Interrupt mask register - IMRThis register allows masking of some of the interrupt sources. The respective flags within the Interrupt Source register (ISR) continues towork but does not generate interrupts to the MCU. The 5.0 V Regulator overtemperature prewarning interrupt and undervoltage (VSUV)
interrupts can not be masked and always causes an interrupt. Writing to the IMR returns the ISR.
Table 60. Interrupt mask register - $E
C3

C2

C1

C0

Write

HSM

LSM

LINM

VMM

Reset Value

1

1

1

1

Reset Condition

POR

14.3.1.17.1 HSM - high-side interrupt mask
This write-only bit enables/disables interrupts generated in the high-side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled

14.3.1.17.2 LSM - low-side interrupt mask
This write-only bit enables/disables interrupts generated in the low-side block.
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled

14.3.1.17.3 LINM - LIN interrupts mask
This write-only bit enables/disables interrupts generated in the LIN block.
1 = LIN Interrupts Enabled
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14.3.1.17.4 VMM - voltage monitor interrupt mask
This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor
Block is the VSUP overvoltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled

14.3.1.18 Interrupt source register - ISR
This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges
the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ is driven highfor 10 µs and then be driven low again. This register is also returned when writing to the Interrupt Mask register (IMR).
Table 61. Interrupt source register - $E/$F

Read

S3

S2

S1

S0

ISR3

ISR2

ISR1

ISR0

14.3.1.18.1 ISRx - interrupt source register
These read-only bits indicate the interrupt source following Table 62. If no interrupt is pending then all bits are 0. If more than one interrupt
is pending, the interrupt sources are handled sequentially multiplex.
Table 62. Interrupt sources
ISR3

ISR2

ISR1

ISR0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

Interrupt source

Prioritynone maskablemaskableno interrupt

no interrupt

none

Lx Wake-up from Stop mode

highest0-

HS Interrupt (Overtemperature)

1

1

-

LS Interrupt (Overtemperature)

1

0

0

0

1

0

1

Voltage Monitor Interrupt(Low-voltage and VDD overtemperature)

Voltage Monitor Interrupt(High-voltage)

0

1

1

0

-

Forced Wake-up

LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN OC)
or LIN Wake-up

lowest33912

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15

Typical application

The 33912 can be configured in several applications. The figure below shows the 33912 in the typical Slave Node Application.
V

BAT

VS2

VS1

D1

C2

C1

C4

Interrupt
Control Module
LVI, HVI, HTI, OCI

IRQ

C3

InternalBus

VDD

Voltage Regulator

C5

AGND

HVDD

5V Output Module

VDD
IRQ

Reset
Control Module
LVR, HVR, HTR, WD,

RST

LS1
Low Side Control
Module

RST
TIMER

LS2

HB Type Relay

PGNDWindow
Watchdog Module

PWMIN

HS1
HS2

MISO
MOSI

Chip Temp Sense Module

SCLK

Analog Multiplexer

SPI&
CONTROLSPICSVSENSEVBAT Sense Module

R2

L1
Analog Input Module

A/D

R1

Motor Output
High Side Control
ModuleMCUHall Sensor Supply

ADOUT0

R3

L2
Wake Up Module

L3
Digital Input Module

L4

R4
Analog Input
R5
Analog Input

RXD
LIN Physical Layer

SCI

LIN

LIN

TXD
C6

ISENSEH
Current Sense Module

ADOUT1WDCONF

LGND

AGND

ISENSEL

PGND

A/D

R6

R7

Typical Component Values:

C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 4.7 µF; C6 = 220 pF
R1 = 10 kΩ; R2 = R3 = 10 kΩ; R4 = R5 = 33 kΩ; R6 = 20 Ω; R7 = 20 kΩ-200 kΩ
Recommended Configuration of the not Connected Pins (NC):Pin 28 = this pin is not internally connected and may be used for PCB routing
optimization.

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16

Packaging

16.1

Package dimensions

Important For the most current revision of the package, visit www.nxp.com and select Documentation, then under Available
Documentation column select Packaging Information.

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17

Revision history

Table 63. Revision history
Revision

Date

1.0

5/2007•

Initial Release

2.0

9/2007•••••

Several textual corrections
Page 11: “Analog Output offset Ratio” (LXDS=1) changed to “Analog Output offset” +/-22mV
Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5Page 12: Common mode input impedance corrected to 75kΩPage 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release

3.0

9/2007•

Revision number incremented at engineering request.

4.0

2/2008••Changed Functional Block Diagram on page 24.
This Data Sheet and previous versions cover Part Numbers MC33912BAC and MC34912BAC. Future revisions do notcover these Part Numbers.

•
•
•

•
•

Datasheet updated according to the Pass1.2 silicon version electrical parameters
Add Maximum Rating on IBUS_NO_GND parameter
Added L1, L2, L3, and L4, Temperature Sense Analog Output Voltage per characterization, Internal Chip Temperature
Sense Gain per characterization at 3 temperatures. See Figure 16, Temperature sense gain, VSENSE Input Divider
Ratio (RATIOVSENSE=VSENSE/VADOUT0) per characterization, and VSENSE Output Related Offset per
characterization parameters
Added Temperature sense gain section
Minor corrections to ESD Capability, (19), Cyclic Sense ON Time from Stop and Sleep mode, Lin bus pin (LIN), Serial
data clock pin (SCLK), Master out slave in pin (MOSI), Master in slave out pin (MISO), Low-side pins (LS1 and LS2),
Digital/analog pins (L1, L2, L3, and L4), Normal request mode, Sleep mode, LIN overtemperature shutdown / TXD stuckat dominant / RXD short-circuit, Fault detection management conditions, LIN physical layer, LIN interface,
Overtemperature shutdown (LIN interrupt), LIN receiver operation only, SPI protocol, Lx - wake-up input x, LIN control
register - LINCR, and RXSHORT - RXD pin short-circuit
This data sheet does not contain electrical parameters for MC33912BAC and MC34912BAC (see revision 4.0).
Updated Freescale form and style

5.0

10/2008

Description of changes

•
•

6.0

2/2009••Added explanation for pins Not Connected (NC).
This data sheet does not contain electrical parameters for MC33912BAC and MC34912BAC (see revision 4.0).

7.0

3/2009••Changed VBAT_SHIFT and GND_SHIFT maximum from 10% to 11.5% for both parameters on page 14.
This data sheet does not contain electrical parameters for MC33912BAC and MC34912BAC (see revision 4.0).

8.0

3/2010••Combined Complete Data sheet for Part Numbers MC33912BAC and MC34912BAC to the back of this data sheet.
Changed ESD Voltage for Machine Model from ± 200 to ± 150

9.02/2014•No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to lastparagraph.

9/2015••

Added (75) to Table 28
Updated template form and style.

8/2016•

Updated to NXP document form and style

10.0

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107How to Reach Us:

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parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,and actual performance may vary over time. All operating parameters, including "typicals," must be validated for eachcustomer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
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Document Number: MC33912
Rev. 10.0
8/2016