S-24C16C (WLP PRODUCT)
www.ablic.com
www.ablicinc.com

2-WIRE SERIAL E2PROM© ABLIC Inc., 2016

Rev.1.0_01_H

The S-24C16C is a 2-wire, low current consumption and wide range operation serial E2PROM. The S-24C16C has thecapacity of 16 K-bit, and the organization is 2048 words  8-bit. Page write and sequential read are available.
Caution This product is intended to use in general electronic devices such as consumer electronics, officeequipment, and communications devices. Before using the product in medical equipment or automobile
equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is
indispensable.

 Features
 Operating voltage range

Read:
1.6 V to 5.5 V
Write:
1.7 V to 5.5 V
16 bytes / page

 Page write: Sequential read
 Operation frequency:
400 kHz (1.6 V to 5.5 V) Write time:
5.0 ms max.
 Noise suppression:
Schmitt trigger and noise filter on input pins (SCL, SDA)
 Write protect function during the low power supply voltage
 Endurance:
106cycles / word*1 (Ta = 25°C)
 Data retention:
100 years (Ta = 25°C)
 Memory capacity:
16 K-bit Write protect:100%
 Initial delivery data:FFh Lead-free, halogen-free*1. For each address (Word: 8-bit)

 Package WLP-6J

1

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

 Pin Configuration
1. WLP-6J
Table 1

WLP-6J
Bottom view
C1
A2

C2
VCC

B1
GND

B2
WP

A1
SDA

A2
SCL

Figure 1

Pin NoA1
A2
B1

Symbol
*2
SDA
*2
SCL
GND

B2

WP

C1
C2

*1

A2
VCC
*1. Connect to GND.
*2. Do not use it in high impedance.

S-24C16CI-H6T3S3

Remark Refer to the “Package drawings” for the details.

2

Description
Serial data I/O
Serial clock input
GroundWrite protect input
Connected to VCC:
Protection valid
Open or connected to GND: Protection invalid
TEST pinPower supply

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
 Block Diagram

VCC

WP
SCL

GND

Start / Stop
Detector

SDA

Voltage Detector
Serial ClockController

High-Voltage Generator

LOAD
Device AddressComparator

COMP

Data Register

LOAD INC

R/W

Address
Counter

Y Decoder

X Decoder

Memory Cell Array

Selector

Data Output
ACK Output
Controller

DIN
DOUT

Figure 23

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

 Absolute Maximum Ratings
Table 2Item
Power supply voltage
Input voltage
Output voltage
Operation ambient temperature
Storage temperature

Symbol
VCC
VIN
VOUT
Topr
Tstg

Absolute Maximum Ratings
0.3 to 6.5
0.3 to 6.5
0.3 to 6.5
40 to 85
65 to 150

Unit
V
V
V
°C
°C

Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.

 Recommended Operating Conditions
Table 3
Item

SymbolPower supply voltage

VCC

High level input voltage
Low level input voltage

VIH
VIL

Condition
Read
Write
VCC = 1.6 V to 5.5 V
VCC = 1.6 V to 5.5 V

Ta = 40°C to 85°C
Min.
Max.
1.6
1.7

5.5
5.5

0.7  VCC
0.3

5.5
0.3  VCC

Unit
V
V
V
V

 Pin Capacitance
Table 4Item
Input capacitanceI/O capacitance

SymbolCondition
CIN
VIN = 0 V (SCL, A2, WP)
VI/O = 0 V (SDA)
CI/O(Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit

10
pF

10
pF

 Endurance
Table 5
Item
SymbolOperation Ambient Temperature
Endurance
NW
Ta = 25°C*1. For each address (Word: 8 bits)

Min.
106

Max.


Unit
cycles / word*1

Min.
100

Max.


Unit
year

 Data Retention
Table 6
Item
Data retention

4

Symbol

Operation Ambient Temperature
Ta = 25°C

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
 DC Electrical Characteristics
Table 7

Ta = 40°C to 85°C
Item

VCC = 1.6 V to 5.5 V
fSCL = 400 kHz
Min.
Max.

0.8

Symbol Condition

Current consumption (READ)



ICC1

Unit

mA

Table 8Ta = 40°C to 85°C
Item

VCC = 1.7 V to 5.5 V
fSCL = 400 kHz
Min.
Max.

2.5

Symbol Condition

Current consumption (WRITE)



ICC2

Unit

mA

Table 9Item

SymbolStandby current
consumption

ISB

Input leakage current 1

ILI1

Output leakage current

ILO

Input current 1

IIL

Input current 2

IIH

Input Impedance 1

ZIL

Input Impedance 2

ZIH

Low level output voltage VOL

Condition

VIN = VCC or GND
SCL, SDA, A2
VIN = GND to VCC
SDA
VOUT = GND to VCC
WP
VIN < 0.3  VCC
WP
VIN > 0.7  VCC
WP
VIN = 0.3  VCC
WP
VIN = 0.7  VCC
IOL = 3.2 mA
IOL = 1.5 mA
IOL = 0.7 mA

Ta = 40°C to 85°C
VCC = 2.5 V to 5.5 V VCC = 1.8 V to 5.5 V VCC = 1.6 V to 1.8 V Unit
Min.

Max.

Min.

Max.

Min.

Max.



3.5



3.5



2.0

A



1.0



1.0



1.0

A



1.0



1.0



1.0

A



50.0



50.0



50.0

A



2.0



2.0



2.0

A

30



30



30



k

500



500



500



k





0.4
0.3
0.2






0.3
0.2






0.3
0.2

V
V
V

5

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

 AC Electrical Characteristics
Table 10 Measurement Conditions
Input pulse voltage
Input pulse rising / falling time
Output reference voltage
Output load

Input pulse voltage

0.2  VCC to 0.8  VCC
20 ns or less0.3  VCC to 0.7  VCC
100 pF

Output reference voltage

0.8  VCC
0.7  VCC
0.3  VCC
0.2  VCC
Figure 3 I/O Waveform during AC Measurement
Table 11
Ta = 40°C to 85°C

Item

SymbolSCL clock frequency
SCL clock time “L”
SCL clock time “H”
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL, SDA rising time
SCL, SDA falling time
WP setup time
WP hold time
WP release setup time
WP release hold time
Bus release time
Noise suppression time

fSCL
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STAtSU.DATtHD.DATtSU.STO
tR
tF
tWS1
tWH1
tWS2
tWH2
tBUF
tI

tHIGH

tF

Unit

VCC = 1.6 V to 5.5 V
Min.
Max.
0
400
1.3

0.6

0.1
0.9
50

0.6

0.6

100

0

0.6


0.3

0.3
0

0

0

0

1.3


50

tLOW

kHz
s
s
s
ns
s
s
ns
ns
s
s
s
s
s
s
s
s
ns

tR

SCL
tHD.STA
tHD.DATtSU.STAtSU.DATtSU.STO

SDA(input)
tAA

tDH

SDA
(output)
Figure 4 Bus Timing

6

tBUF

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

Table 12
Ta = 40°C to 85°C
Item
Write time

Start Condition

SymboltWR

VCC = 1.7 V to 5.5 V
Min.
Max.

5.0

Acknowledgment
SignalWrite data

Stop Condition

Unit
ms

tWR

Start Condition

SCL

D0

SDA
tWS1

tWH1

tWS2

tWH2

WP
(valid)WP(invalid)

Figure 5 Write Cycle Timing

7

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

 Pin Functions
1. A2 (Test) pin
The slave address can not be assigned in the S-24C16C since addressing function is removed.
The A2 pin should be connected to the GND.

2. SDA (Serial data input / output) pin
The SDA pin is used for the bi-directional transmission of serial data. This pin is a signal input pin, and an Nch open
drain output pin.
In use, generally, connect the SDA line to any other device which has the open-drain or open-collector output with
Wired-OR connection by pulling up to VCC by a resistor (Figure 6 shows the relation with an output load).

3. SCL (Serial clock input) pin
The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL
clock, pay attention to the rising and falling time and comply with the specification.

4. WP (Write protect input) pin
The write protect is enabled by connecting the WP pin to VCC. When not using the write protect, connect this pin to
GND or set in open.
20
18
16
14
Maximum value of pull-up resistor

12

[k]

10

fSCL = 400 kHz

8
6
4
2
0
100

10
Value of load capacity[pF]

Figure 6 Output Load

 Initial Delivery Data
Initial delivery data of all addresses is “FFh”.

8

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
 Operation
1. Start condition

Start is identified by a high to low transition of the SDA line while the SCL line is stable at high.
Every operation begins from a start condition.

2. Stop condition
Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high.
When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device
enters standby mode.
When a device receives a stop condition during a write sequence, the reception of the write data is halted, and the
S-24C16C initiates a write cycle.

tSU.STA

tHD.STAtSU.STOSCL

SDAStart Condition

Stop Condition
Figure 7 Start / Stop Conditions

9

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

3. Data transmission
Changing the SDA line while the SCL line is low, data is transmitted.
Changing the SDA line while the SCL line is high, a start or stop condition is recognized.

tSU.DATtHD.DATSCL

SDA

Figure 8 Data Transmission Timing

4. Acknowledge
The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA
line to acknowledge the receipt of the 8-bit data.
When an internal write cycle is in progress, the device does not generate an acknowledge.

SCL(E2PROM Input)

1

8

9

SDA
(Master Output)

Acknowledge
OutputSDA(E PROM Output)
2

Start ConditiontAA
Figure 9 Acknowledge Output Timing

10

tDH

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
5. Device addressing

To start communication, the master device on the system generates a start condition to the bus line. Next, themaster device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus.
The upper 4 bits of the device address are the “Device Code”, and are fixed to “1010”.
In the S-24C16C, successive 3 bits (P2, P1, P0) are “Page Address”. Choose the 8 memory blocks of 256-byte(Adress 000h to 0FFh, 100h to 1FFh, 200h to 2FFh, 300h to 3FFh, 400h to 4FFh, 500h to 5FFh, 600h to 6FFh, and700h to 7FFh).

Device Code10

1

Page Address
0

P2

P1

MSB

P0

R/W
LSB

Figure 10 Device Address

11

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

6. Write
6. 1 Byte write
When the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start
condition, the S-24C16C acknowledges it. And the S-24C16C receives 8-bit word address and responds with an
acknowledge. After the S-24C16C receives 8-bit write data and responds with an acknowledge, it receives a stop
condition and that initiates the write cycle at the addressed memory.
During the write cycle all operations are forbidden and no acknowledge is generated.

S
T
A
R
T
SDA LINE

DEVICEADDRESS
1
M
S
B

W
R
I
T
E

0 1 0 P2 P1 P0 0

WORD ADDRESSDATA

W7 W6 W5 W4 W3 W2 W1 W0

D7 D6 D5 D4 D3 D2 D1 D0

L R A
S / C
B W K

Figure 11 Byte Write

12

A
A
C
C
K
K

S
T
O
P

A
C
K

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

6. 2 Page write
The page write mode allows up to 16 bytes to be written in a single write operation in the S-24C16C.
Its basic process to transmit data is as same as byte write, but it operates page write by sequentially receiving
8-bit write data as much data as the page size has.
When the S-24C16C receives a 7-bit device address and a 1-bit read / write instruction code set to “0”, following astart condition, it generates an acknowledge. And the S-24C16C receives 8-bit word address and responds withan acknowledge. After the S-24C16C receives 8-bit write data and responds with an acknowledge, it receives
8-bit write data corresponding to the next word address, and generates an acknowledge. The S-24C16C repeats
reception of 8-bit write data and generation of acknowledge in succession. The S-24C16C can receive as many
write data as the maximum page size.
Receiving a stop condition initiates a write cycle of the area starting from the designated memory address andhaving the page size equal to the received write data.

S
T
A
R
T
SDA
LINE

W
R
I
T
E

WORD ADDRESS (n)DATA (n)1 0 1 0 P2 P1 P0 0

W7W6 W5W4 W3 W2 W1W0

D7 D6 D5 D4 D3 D2 D1 D0

DEVICEADDRESS

M
S
B

L R A
S / C
BWK

A
C
K

DATA (n+1)
D7
A
C
K

S
T
O
P

DATA (n+x)
D0

D7
A
C
K

D0
A
C
K

Figure 12 Page Write

In the S-24C16C, the lower 4 bits of the word address are automatically incremented every time when the
S-24C16C receives 8-bit write data. If the size of the write data exceeds 16 bytes, the upper 4 bits of the word
address and page address (P2, P1, P0) remain unchanged, and the lower 4 bits are rolled over and the last
16-byte data that the S-24C16C received will be overwritten.

13

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

6. 3 Write protect
Write protect is available in the S-24C16C. When the WP pin is connected to the VCC, write operation to memoryarea is inhibited.
When the WP pin is connected to GND or set in open, the write protect is invalid, and write operation in all
memory area is available.
Fix the level of the WP pin from start condition in the write operation (byte write, page write) until stop condition. If
the WP pin changes during this time, the address data being written at this time is not guaranteed. Regarding thetiming of write protect, refer to Figure 5.
In not using the write protect, connect the WP pin to GND or set it open. The write protect is valid in the range of
operation power supply voltage.
As seen in Figure 13 when the write protect is valid, the S-24C16C does not generate an acknowledgment signal
after data input.

S
T
A
R
T
SDA LINE

DEVICEADDRESS
1
M
S
B

W
R
I
T
E

0 1 0 P2 P1 P0 0

WORD ADDRESSDATA

W7 W6 W5 W4 W3 W2 W1 W0

D7 D6 D5 D4 D3 D2 D1 D0

L R A
S / C
B W K

WP

Figure 13 Write Protect

14

A
A
C
C
K
K

S
T
O
P

N
A
C
K

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

6. 4 Acknowledge polling
Acknowledge polling is used to know the completion of the write cycle in the S-24C16C.
After the S-24C16C receives a stop condition and once starts the write cycle, all operations are inhibited and no
response is made to the signal transmitted by the master device.
Accordingly the master device can recognize the completion of the write cycle in the S-24C16C by detecting a
response from the slave device after transmitting the start condition, the device address and the read / write
instruction code to the S-24C16C (slave device).
That is, if the S-24C16C does not generate an acknowledgment signal, the write cycle is in progress and if the
S-24C16C generates an acknowledgment signal, the write cycle has been completed.
It is recommended to use the read instruction “1” as the read / write instruction code transmitted by the masterdevice.

Acknowledge polling during write

DATA
SDA
LINE

D2 D1 D0

S
T
O
P

W
R
I
T
E

S
T
A
R
T

S
T
A
R
T

DEVICEADDRESS 0

W
R
I
T
E
DEVICEADDRESS 0

R N
/ A
W C
K

WORD
ADDRESS
A
C
K

R A
/ C
WK

tWR
Acknowledge polling during read
S
S
R
T
T
E
A
O
A
R
P
D
DATA
T
SDA
DEVICE
D2 D1 D0
ADDRESS 1
LINE
R N
/ A
W C
K

S
T
A
R
T

NO ACK from
R Master Device
E
A
D
DEVICEADDRESS 1

DATA

R A
/ C
WK

S
T
O
P

S
T
A
R
T
DEVICEADDRESS
R A
/ C
WK

tWR
RemarkUsers are able to input word address and data after ACK output in acknowledge polling during write.
Users are able to read data after ACK output in acknowledge polling during read. However, after that users
input the write instruction, a start condition may not be input during data output. Input a stop condition and thenext instruction after data output and ACK output.

Figure 14 Usage Example of Acknowledge Polling15

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

7. Read7. 1 Current address read
Either in writing or in reading the S-24C16C holds the last accessed memory address. The memory address ismaintained as long as the power voltage does not decrease less than the operating voltage.
The master device can read the data at the memory address of the current address pointer without assigning theword address as a result, when it recognizes the position of the address pointer in the S-24C16C. This is called“Current Address Read”.
In the following the address counter in the S-24C16C is assumed to be “n”.
When the S-24C16C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following astart condition, it responds with an acknowledge.
Next, an 8-bit data at the address “n” is sent from the S-24C16C synchronous to the SCL clock. The address
counter is incremented and the content of the address counter becomes n1.
The master device outputs stop condition not an acknowledge, the reading of S-24C16C is ended.
S
T
A
R
T
SDA LINE

DEVICEADDRESSR
E
A
D

1 0 1 0 X X X 1
M
S
B

L R A
S / C
B W K

NO ACK fromMaster Device

S
T
O
P

D7 D6 D5 D4 D3 D2 D1 D0
DATA

Figure 15 Current Address Read
Attention should be paid to the following point on the recognition of the address pointer in the S-24C16C.
In Read, the memory address counter in the S-24C16C is automatically incremented after output of the 8th bit ofthe data. In Write, on the other hand, the upper bits of the memory address (the upper bits of the word address
and the page address*1) are left unchanged and are not incremented.
*1. S-24C16C is the upper 4bits of the word address and the page address P2, P1 and P0.

16

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

7. 2 Random read
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When the S-24C16C receives a 7-bit device address and a 1-bit read / write instruction code set to “0” following astart condition, it responds with an acknowledge.
And the S-24C16C receives 8-bit word address and responds with an acknowledge. The memory address isloaded to the address counter in the S-24C16C by these operations. Reception of write data does not follow in adummy write whereas reception of write data follows in byte write and in page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device canread the data starting from the arbitrary memory address by transmitting a new start condition and performing thesame operation in the current address read.
That is, when the S-24C16C receives a 7-bit device address and a 1-bit read / write instruction code set to “1”,following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from the
S-24C16C in synchronous to the SCL clock. The master device outputs stop condition not an acknowledge, thereading of S-24C16C is ended.

W
R
I
T
E

WORD ADDRESS (n)1 0 1 0 P2 P1 P0 0

W7 W6 W5 W4 W3 W2 W1 W0

S
T
A
R
T
SDA
LINE

DEVICEADDRESS

M
S
B

L R A
S / C
B W K

S
T
A
R
T

DEVICEADDRESSR
E
A
D

1 0 1 0 X X X 1
A
C
K

M
S
B

NO ACK fromMaster Device
DATA

S
T
O
P

D7 D6 D5 D4 D3 D2 D1 D0

L R A
S / C
B W K

DUMMY WRITE

Figure 16 Random Read

17

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

7. 3 Sequential read
When the S-24C16C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following astart condition both in current address read and random read, it responds with an acknowledge.
When an 8-bit data is output from the S-24C16C synchronous to the SCL clock, the address counter is
automatically incremented.
When the master device responds with an acknowledge, the data at the next memory address is transmitted.
Response with an acknowledge by the master device has the memory address counter in the S-24C16C
incremented and makes it possible to read data in succession. This is called “Sequential Read”.
The master device outputs stop condition not an acknowledge, the reading of S-24C16C is ended.
Data can be read in succession in the sequential read mode. When the memory address counter reaches the lastword address, it rolls over to the first word address.

DEVICEADDRESSSDA
LINENO ACK fromMaster Device

R
E
A
D
1
R A
/ C
W K

A
C
K
D7

D0
DATA (n)

A
C
K
D7

D0

D7

DATA (n+1)

Figure 17 Sequential Read

18

S
T
O
P

A
C
K
D0
DATA (n+2)

D7D0DATA (n+x)

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

 Write Protect Function during the Low Power Supply Voltage
The S-24C16C has a built-in detection circuit which operates with the low power supply voltage, cancels Write when the
power supply voltage drops and power-on. Its detection and release voltages are 1.20 V typ. (Refer to Figure 18).
The S-24C16C cancels Write by detecting a low power supply voltage when it receives a stop condition.
In the data trasmission and the Write operation, data in the address written during the low power supply voltage is notassurable.
Power Supply Voltage
Detection Voltage (VDET)
1.20 V typ.

Release Voltage (VDET)
1.20 V typ.

Write Instruction cancel
Figure 18 Operation during Low Power Supply Voltage

19

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

 Using S-24C16C
1. Adding a pull-up resistor to SDA I/O pin and SCL input pin
In consideration of I2C-bus protocol function, the SDA I/O pins should be connected with a pull-up resistor.
The S-24C16C cannot transmit normally without using a pull-up resistor.
In case that the SCL input pin of the S-24C16C is connected to the Nch open drain output pin of the master device,connect the SCL pin with a pull-up resistor. As well, in case the SCL input pin of the S-24C16C is connected to the tristate output pin of the master device, connect the SCL pin with a pull-up resistor in order not to set it in highimpedance. This prevents the S-24C16C from error caused by an uncertain output (high impedance) from the tri-state
pin when resetting the master device during the voltage drop.

20

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
2. Equivalent circuit of input and I/O pin

The SCL pin and the SDA pin do not have a built-in pull-down or pull-up resistor.
The WP pin has a built-in pull-down resistor.The SDA pin has an open-drain output.
The followings are equivalent circuits of the pins.

SCL

Figure 19 SCL Pin

SDA

Figure 20 SDA Pin

WP

Figure 21 WP Pin

21

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

3. Phase adjustment during S-24C16C access
The S-24C16C does not have a pin to reset (the internal circuit). The users cannot forcibly reset it externally. If thecommunication to the S-24C16C interrupted, the users need to handle it as you do for software.
In the S-24C16C, users are able to reset the internal circuit by inputting a start condition and a stop condition.
Although the reset signal is input to the master device, the S-24C16C’s internal circuit does not go in reset, but it doesby inputting a stop condition to the S-24C16C. The S-24C16C keeps the same status thus cannot do the next
operation. Especially, this case corresponds to that only the master device is reset when the power supply voltage
drops.
If the power supply voltage restored in this status, input the instruction after resetting (adjusting the phase with themaster device) the S-24C16C. How to reset is shown below.
[How to reset S-24C16C]
The S-24C16C is able to be reset by a start and stop instructions. When the S-24C16C is reading data “0” or is
outputting the acknowledgment signal, outputs “0” to the SDA line. In this status, the master device cannot output
an instruction to the SDA line. In this case, terminate the acknowledgment output operation or the Read operation,and then input a start instruction. Figure 22 shows this procedure.
First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets
the SDA line to “H”. By this operation, the S-24C16C interrupts the acknowledgment output operation or data
output, so input a start condition*1. When a start condition is input, the S-24C16C is reset. To make doubly sure,
input the stop condition to the S-24C16C. The normal operation is then possible.

Start
Condition

Start
Condition

Dummy Clock
1

2

8

Stop
Condition

9

SCL

SDA

Figure 22 Resetting S-24C16C*1. After 9 clocks (dummy clock), if the SCL clock continues to being output without inputting a start condition,
S-24C16C may go in the write operation when it receives a stop condition. To prevent this, input a start
condition after 9 clocks (dummy clock).
Remark22

Regarding this reset procedure with dummy clock, it is recommended to perform at the system
initialization after applying the power supply voltage.

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
4. Acknowledge check

The I2C-bus protocol includes an acknowledge check function as a handshake function to prevent a communication
error. This function allows detection of a communication failure during data communication between the masterdevice and S-24C16C. This function is effective to prevent malfunction, so it is recommended to perform an
acknowledge check with the master device.

5. Built-in power-on-clear circuit
The S-24C16C has a built-in power-on-clear circuit that initializes itself at the same time during power-on.
Unsuccessful initialization may cause a malfunction. To operate the power-on-clear circuit normally, the following
conditions must be satisfied to raise the power supply voltage.
5. 1 Raising power supply voltage
Shown in Figure 23, raise the power supply voltage from 0.2 V max., within the time defined as tRISE which is thetime required to reach the power supply voltage to be set.
For example, if the power supply voltage is 5.0 V, tRISE = 200 ms seen in Figure 24. The power supply voltage
must be raised within 200 ms.
tRISE max.

Power Supply Voltage (VCC)

VINIT max.

0.2 V

0V

*1

*2

tINIT max.

*1. 0 V means there is no difference in potential between the VCC pin and the GND pin of the S-24C16C.
*2. tINIT is the time required to initialize the S-24C16C. No instructions are accepted during this time.
Figure 23 Raising Power Supply Voltage

23

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

5.0
4.0
Power Supply Voltage (VCC)
[V]

3.0
2.0

50

100

150

200

Rise Time (tRISE) max.
[ms]

For example: If the supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms.
Figure 24 Rise Time of Power Supply Voltage

When initialization is successfully completed by the power-on-clear circuit, the S-24C16C enters the standby
status.
If the power-on-clear circuit does not operate;
The S-24C16C has not completed initialization, an instruction previously input is still valid or an instruction may beinappropriately recognized. In this case, S-24C16C may perform the Write operation.
The voltage drops due to power off while the S-24C16C is being accessed. Even if the master device is reset due
to the low power voltage, the S-24C16C may malfunction unless the power-on-clear operation conditions of
S-24C16C are satisfied.
When not using this rise time seen in Figure 24, adjust the phase (reset) to reset the internal circuit in the
S-24C16C normally.

24

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

5. 2 Initialization time
The S-24C16C initializes at the same time when the power supply voltage is raised. Input instructions to the
S-24C16C after initialization. S-24C16C does not accept any instruction during initialization.
Figure 25 shows the initialization time of the S-24C16C.

100 m
10 m
Initialization Time(tINIT) max.
[s]

1.0 m
100 
10 
1.0 
1.0 

10  100  1.0 m 10 m 100 m
Rise Time (tRISE)[s]

Figure 25 Initialization Time of S-24C16C

25

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

6. Data hold time (tHD.DAT = 0 ns)
If SCL and SDA of the S-24C16C are changed at the same time, it is necessary to prevent a start / stop condition
from being mistakenly recognized due to the effect of noise.
The S-24C16C may error if it does not recognize a start / stop condition correctly during transmission.
It is recommended to set the delay time of 0.3 s minimum from a falling edge of SCL for the SDA.
This is to prevent S-24C16C from going in a start / stop condition due to the time lag caused by the load of the bus
line.
tHD.DAT = 0.3 s min.

SCL

SDA

Figure 26 S-24C16C Data Hold Time

7. SDA pin and SCL pin noise suppression time
The S-24C16C includes a built-in low-pass filter at the SDA and SCL pins to suppress noise. This means that if thepower supply voltage is 5.0 V, noise with a pulse width of 130 ns or less can be suppressed.
For details of the assurable value, refer to noise suppression time (tl) in Table 11.

300

Noise Suppression Time (tI) max.
[ns]

200
100

2

3

4

5

Power Supply Voltage (VCC)[V]

Figure 27 Noise Suppression Time for SDA and SCL Pins

26

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
8. Operation when input stop condition during input write data

The S-24C16C does the write operation only when it receives data of 1 byte or more and receives a stop condition
immediately after ACK output.
Refer to Figure 28 regarding details.

S
T
A
R
T
SDA
LINE

Write Enable

Write Enable

Write Enable

by the STOP conditionby the STOP conditionby the STOP condition

Write Inhibition

Write Inhibition

Write Inhibitionby the STOP conditionby the STOP conditionby the STOP condition

W
R
I
T
E

WORD ADDRESS (n)DATA (n)1 0 1 0 P2 P1 P0 0

W7W6 W5W4 W3 W2 W1W0

D7 D6 D5 D4 D3 D2 D1 D0

DEVICEADDRESS

M
S
B

L R A
S / C
BWK

A
C
K

DATA (n+1)
D7
A
C
K

S
T
O
P

DATA (n+x)
D0

D7
A
C
K

D0
A
C
K

Figure 28 Write Operation by Inputting Stop Condition during Write

9. Command cancel by start condition
By a start condition, users are able to cancel command which is being input. However, adjust the phase while the
S-24C16C is outputting “L” because users are not able to input a start condition. When users cancel the command,
there may be a case that the address will not be identified. Use random read for the read operation, not current
address read.

10. Precaution for use
Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on thedata sheet). Exceeding the supply voltage rating can cause latch-up.
Operations with moisture on the S-24C16C pins may occur malfunction by short-circuit between pins. Especially, inoccasions like picking the S-24C16C up from low temperature tank during the evaluation. Be sure that not remain
frost on the S-24C16C’s pins to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.

27

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H

 Precautions● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
● ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.

 Precautions for WLP package● The side of device silicon substrate is exposed to the marking side of device package. Since this portion has lower
strength against the mechanical stress than the standard plastic package, chip, crack, etc should be careful of thehanding of a package enough. Moreover, the exposed side of silicon has electrical potential of device substrate, andneeds to be kept out of contact with the external potential.
● In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it mind that it
may affect the characteristic of a device when exposed a device in the bottom of a high light source.

28

2-WIRE SERIAL E2PROM
S-24C16C (WLP PRODUCT)

Rev.1.0_01_H
 Product Name Structure
1. Product name
S-24C16C

I

-

H6T3

S

3
Environmental codeS:
Lead-free, halogen-free
Package name (abbreviated) and IC packing specification
H6T3: WLP-6J, Tape
Fixed
Product name
S-24C16C: 16 K-bit

2. Package
Package Name
WLP-6J

Package
HJ006-C-P-SD

Drawing CodeTape
HJ006-C-C-SD

Reel
HJ006-C-R-SD

29

B

0.96±0.03
2

1

6-(ø0.25)

A
A
B

C

0.4

0.39 max.

Sø0.25±0.02

0.04 S

Pin No.
A1

Symbol
SDA

B1
C1
A2
B2
C2

GND
A2
SCL
WP
VCC

No. HJ006-C-P-SD-2.0

TITLE
No.

WLP-6J-C-PKG Dimensions(S-24C16C)
HJ006-C-P-SD-2.0

ANGLE
UNIT

mm

ABLIC Inc.

+0.1

ø1.5 -0ø0.5±0.05

C1

A1

C2

A2

0.55±0.05

4.0±0.1

2.01

1.71±0.05

0.18±0.05

4.0±0.1

2.0±0.05

0.5

0.3

Feed direction

No. HJ006-C-C-SD-1.0

TITLE
No.

WLP-6J-C-C a r r i e r T a p e(S-24C16C)
HJ006-C-C-SD-1.0

ANGLE
UNIT

ABLIC Inc.

12.5max.

9.0±0.3
Enlarged drawing in the central part
ø13±0.2

No. HJ006-C-R-SD-1.0

WLP-6J-C-Reel(S-24C16C)
HJ006-C-R-SD-1.0

TITLE
No.
ANGLE
UNIT

QTY.
mm

ABLIC Inc.

3,000

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

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