Uniform Sector
Dual and Quad Serial Flash

GD25B256E
DATASHEET

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1

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GD25B256E

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

Contents
1

FEATURES .........................................................................................................................................................42

GENERAL DESCRIPTIONS .............................................................................................................................5

3

MEMORY ORGANIZATION ...............................................................................................................................84

DEVICE OPERATIONS......................................................................................................................................9
4.1

SPI MODE .............................................................................................................................................................. 9

4.2

RESET FUNCTION .................................................................................................................................................... 9

5

DATA PROTECTION ........................................................................................................................................ 10

6

REGISTERS...................................................................................................................................................... 117

6.1

STATUS REGISTER ................................................................................................................................................... 11

6.2

EXTENDED ADDRESS REGISTER .................................................................................................................................. 15

COMMAND DESCRIPTIONS .......................................................................................................................... 16
7.1

WRITE ENABLE (WREN) (06H) ................................................................................................................................ 21

7.2

WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 21

7.3

READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .............................................................................................. 21

7.4

WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H) ........................................................................................... 22

7.5

READ EXTENDED ADDRESS REGISTER (C8H) ................................................................................................................ 22

7.6

WRITE EXTENDED ADDRESS REGISTER (C5H)............................................................................................................... 23

7.7

WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 23

7.8

READ DATA BYTES (03H/13H) ................................................................................................................................ 24

7.9

READ DATA BYTES AT HIGHER SPEED (0BH/0CH) ........................................................................................................ 24

7.10

DUAL OUTPUT FAST READ (3BH/3CH) ...................................................................................................................... 25

7.11

QUAD OUTPUT FAST READ (6BH/6CH) ..................................................................................................................... 25

7.12

DUAL I/O FAST READ (BBH/BCH) ............................................................................................................................ 26

7.13

QUAD I/O FAST READ (EBH/ECH) ........................................................................................................................... 27

7.14

SET BURST WITH WRAP (77H) ................................................................................................................................. 29

7.15

PAGE PROGRAM (PP 02H OR 4PP 12H) .................................................................................................................... 29

7.16

QUAD PAGE PROGRAM (32H/34H) .......................................................................................................................... 30

7.17

SECTOR ERASE (SE 20H OR 4SE 21H) ....................................................................................................................... 31

7.18

32KB BLOCK ERASE (BE32 52H OR 4BE32 5CH) ....................................................................................................... 31

7.19

64KB BLOCK ERASE (BE64 D8H OR 4BE64 DCH) ...................................................................................................... 32

7.20

CHIP ERASE (CE) (60/C7H) ..................................................................................................................................... 32

7.21

ENTER 4-BYTE ADDRESS MODE (EN4B) (B7H) ........................................................................................................... 33

7.22

EXIT 4-BYTE ADDRESS MODE (EX4B) (E9H) ............................................................................................................... 33

7.23

READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 34

7.24

READ IDENTIFICATION (RDID) (9FH) ......................................................................................................................... 34

7.25

READ UNIQUE ID (4BH) .......................................................................................................................................... 35

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7.26

ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 35

7.27

PROGRAM SECURITY REGISTERS (42H) ....................................................................................................................... 36

7.28

READ SECURITY REGISTERS (48H) ............................................................................................................................. 37

7.29

ENABLE RESET (66H) AND RESET (99H) ..................................................................................................................... 38

7.30

PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 38

7.31

PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 39

7.32

DEEP POWER-DOWN (DP) (B9H) ............................................................................................................................. 39

7.33

RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ......................................................................... 40

7.34

READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)................................................................................................. 40

8ELECTRICAL CHARACTERISTICS .............................................................................................................. 42
8.1

POWER-ON TIMING ................................................................................................................................................ 42

8.2

INITIAL DELIVERY STATE ........................................................................................................................................... 42

8.3

ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 42

8.4

CAPACITANCE MEASUREMENT CONDITIONS................................................................................................................. 43

8.5

DC CHARACTERISTICS .............................................................................................................................................. 44

8.6

AC CHARACTERISTICS .............................................................................................................................................. 47

9

ORDERING INFORMATION............................................................................................................................ 53
9.1

10

11

GD25B256E

VALID PART NUMBERS ............................................................................................................................................ 54
PACKAGE INFORMATION ......................................................................................................................... 55

10.1

PACKAGE SOP16 300MIL ...................................................................................................................................... 55

10.2

PACKAGE WSON8 (6X5MM) ................................................................................................................................... 56

10.3

PACKAGE WSON8 (8X6MM) ................................................................................................................................... 57

10.4

PACKAGE TFBGA-24BALL (5X5 BALL ARRAY) ............................................................................................................. 58
REVISION HISTORY .................................................................................................................................... 59

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GD25B256E

1 FEATURES◆ 256M-bit Serial Flash◆ Fast Program/Erase Speed- 32M-Byte- Page Program time: 0.25ms typical- 256 Bytes per programmable page

- Sector Erase time: 30ms typical- Block Erase time: 0.12s/0.15s typical◆ Standard, Dual, Quad SPI- Chip Erase time: 70s typical- Standard SPI: SCLK, CS#, SI, SO, RESET#- Dual SPI: SCLK, CS#, IO0, IO1, RESET#◆ Flexible Architecture- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3, RESET#- Uniform Sector of 4K-Byte- 3 or 4-Byte Address Mode

- Uniform Block of 32/64K-Byte◆ High Speed Clock Frequency◆ Low Power Consumption- 133MHz for fast read with 30PF load

- 16μA typical standby current- Dual I/O Data transfer up to 266Mbits/s- 1μA typical deep power down current- Quad I/O Data transfer up to 532Mbits/s◆ Advanced Security Features◆ Software Write Protection- 128-bit Unique ID for each device- Write protect all/portion of memory via software- Serial Flash Discoverable parameters (SFDP) register- Top/Bottom Block protection- 3x2048-Byte Security Registers With OTP Locks◆ Endurance and Data Retention◆ Single Power Supply Voltage- Minimum 100,000 Program/Erase Cycles- Full voltage range: 2.7-3.6V- 20-year data retention typical◆ Package Information◆ Allows XiP (eXecute In Place) Operation- SOP16 300mil- High speed Read reduce overall XiP instruction fetch time

- WSON8 (6x5mm)- Continuous Read with Wrap further reduce data latency to- WSON8 (8x6mm)

fill up SoC cache

http://www.elm-tech.com- TFBGA-24ball (5x5 Ball Array)

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GD25B256E

GENERAL DESCRIPTIONSThe GD25B256E (256M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and the Dual/Quad SPI:
Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2, I/O3. The Dual I/O data is transferred with speed of
266Mbit/s, and the Quad I/O data is transferred with speed of 532Mbit/s.

CONNECTION DIAGRAM
CS#

1

8

VCC

SO
(IO1)

2

7

IO3

IO2

3

6

SCLK

VSS

Top View

4

5

SI
(IO0)

8 - LEAD WSON

Top View

1

16

SCLK

VCC

2

15

SI
(IO0)

RESET#

3

14

NC

NC

4

13

DNU

NC

5

12

NC

NC

6

11

NC

CS#

7

10

VSS

SO
(IO1)

8

9

IO2

Top View

16-LEAD SOP

A2

A3

A4

A5

NC

NC

RESET#

DNU

B1

B2

B3

B4

B5

NC

SCLK

VSS

VCC

NC

C1

C2

C3

C4

C5

NC

CS#

DNU

IO2

NC

D1

D2

D3

D4

D5

NC

SO
(IO1)

SI(IO0)

IO3

NC

E1

E2

E3

E4

E5

NC

NC

NC

NC

NC

24-BALL TFBGA (5x5 ball array)

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IO3

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GD25B256E

PIN DESCRIPTION
Table 1. Pin Description for SOP16 Package
Pin No.

Pin Name

I/O

Description

1

IO3

I/O

2

VCC

3

RESET#

I

Reset Input

7

CS#

I

Chip Select Input

8

SO (IO1)

I/O

Data Output (Data Input Output 1)

9

IO2

I/O

Data Input Output 2

10

VSS

Ground13

DNU

Do Not Use (It may connect to internal signal inside)

15

SI (IO0)

I/O

Data Input (Data Input Output 0)

16

SCLK

I

Serial Clock Input

Data Input Output 3
Power Supply

Table 2. Pin Description for WSON8 Package
Pin No.

Pin Name

I/O

Description

1

CS#

I

Chip Select Input

2

SO (IO1)

I/O

Data Output (Data Input Output 1)

3

IO2

I/O

Data Input Output 2

4

VSS

5

SI (IO0)

I/O

Data Input (Data Input Output 0)

6

SCLK

I

Serial Clock Input

7

IO3

I/O

Data Input Output 3

8

VCC

GroundPower Supply

Table 3. Pin Description for TFBGA24 Package
Pin No.

Pin Name

I/O

Description

A4

RESET#

I

A5/C3

DNU

B2

SCLK

B3

VSS

GroundB4VCC

Power Supply

C2

CS#

I

Chip Select Input

C4

IO2

I/O

Data Input Output 2

D2

SO (IO1)

I/O

Data Output (Data Input Output 1)

D3

SI (IO0)

I/O

Data Input (Data Input Output 0)

D4

IO3

I/O

Data Input Output 3

Reset Input
Do Not Use (It may connect to internal signal inside)

I

Serial Clock Input

Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.

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GD25B256E

StatusRegister

IO2

IO3
SCLK
CS#

SPI
Command &Control Logic

SI(IO0)High Voltage
Generators
Page Address
Latch/Counter

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Flash
MemoryColumn Decode And
256-Byte Page Buffer

SO(IO1)RESET#

Write Protect Logic
and Row Decode

BLOCK DIAGRAM

Byte Address
Latch/Counter

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GD25B256E

MEMORY ORGANIZATION

GD25B256E
Each device has

Each block has

Each sector has

Each page has

32M

64/32K

4K

256

Bytes

128K

256/128

16

-

pages

8K

16/8

-

-

sectors

512/1K---

blocksUNIFORM BLOCK SECTOR ARCHITECTURE
GD25B256E 64K Bytes Block Sector Architecture
Block
511

510

……

……

2

1

0

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SectorAddress range

8191

1FFF000H

1FFFFFFH

……

……

……

8176

1FF0000H

1FF0FFFH

8175

1FEF000H

1FEFFFFH

……

……

……

8160

1FE0000H

1FE0FFFH

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

47

02F000H

02FFFFH

……

……

……

32

020000H

020FFFH

31

01F000H

01FFFFH

……

……

……

16

010000H

010FFFH

1500F000H

00FFFFH

……

……

……

0

000000H

000FFFH

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GD25B256E

4 DEVICE OPERATIONS
4.1

SPI ModeStandard SPI
The GD25B256E features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the risingedge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPIThe GD25B256E supports Dual SPI operation when using the “Dual Output Fast Read”, “Dual Output Fast Read with 4Byte address”, “Dual I/O Fast Read” and “Dual I/O Fast Read with 4-Byte address” commands (3BH, 3CH, BBH and BCH).
These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using theDual SPI command, the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPIThe GD25B256E supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad Output Fast Read with 4Byte address”, “Quad I/O Fast Read”, “Quad I/O Fast Read with 4-Byte address” (6BH, 6CH, EBH, ECH) commands. These
commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the
Quad SPI commands, the SI and SO pins become bidirectional I/O pins: IO0 and IO1, in addition to IO2 and IO3 pins. For
GD25B256E, the QE bit is set to 1 as default and cannot be changed.

4.2

RESET Function

The RESET# pin goes low for a minimum period of tRLRH (1μs) will reset the flash. After reset cycle, the flash is at thefollowing states:-Standby mode
-All the volatile bits will return to the default status as power on.
Figure 1 RESET ConditionCS#

RESET#RESET

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GD25B256E

DATA PROTECTION

The GD25B256E provide the following data protection methods:◆

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:-Power-Up / Software Reset (66H+99H)-Write Disable (WRDI)-Write Status Register (WRSR)-Page Program (PP)-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)◆Software Protection Mode: The Block Protect bits (BP4-BP0) define the section of the memory array that can beread but not changed.

◆

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down Mode command and Software Reset (66H+99H).

◆

Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.
Table 4. GD25B256E Protected area size
Status Register Content

Memory Content

BP4

BP3

BP2

BP1

BP0

BlocksAddresses

Density

Portion

X

0

0

0

0

NONE

NONE

NONE

NONE

0

0

0

0

1

511

01FF0000h-01FFFFFFh

64KB

Upper 1/512

0

0

0

1

0

510 to 511

01FE0000h-01FFFFFFh

128KB

Upper 1/256

0

0

0

1

1

508 to 511

01FC0000h-01FFFFFFh

256KB

Upper 1/128

0

0

1

0

0

504 to 511

01F80000h-01FFFFFFh

512KB

Upper 1/64

0

0

1

0

1

496 to 511

01F00000h-01FFFFFFh

1MB

Upper 1/32

0

0

1

1

0

480 to 511

01E00000h-01FFFFFFh

2MB

Upper 1/16

0

0

1

1

1

448 to 511

01C00000h-01FFFFFFh

4MB

Upper 1/8

0

1

0

0

0

384 to 511

01800000h-01FFFFFFh

8MB

Upper 1/4

0

1

0

0

1

256 to 511

01000000h-01FFFFFFh

16MB

Upper 1/2

1

0

0

0

1

0

00000000h-0000FFFFh

64KB

Lower 1/512

1

0

0

1

0

0 to 100000000h-0001FFFFh

128KB

Lower 1/256

1

0

0

1

1

0 to 300000000h-0003FFFFh

256KB

Lower 1/128

1

0

1

0

0

0 to 700000000h-0007FFFFh

512KB

Lower 1/64

1

0

1

0

1

0 to 1500000000h-000FFFFFh

1MB

Lower 1/32

1

0

1

1

0

0 to 3100000000h-001FFFFFh

2MB

Lower 1/16

1

0

1

1

1

0 to 6300000000h-003FFFFFh

4MB

Lower 1/8

1

1

0

0

0

0 to 127

00000000h-007FFFFFh

8MB

Lower 1/4

1

1

0

0

1

0 to 255

00000000h-00FFFFFFh

16MB

Lower 1/2

X

1

1

0

X

ALL

00000000h-01FFFFFFh

32MB

ALL

X

1

X

1

X

ALL

00000000h-01FFFFFFh

32MB

ALL

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GD25B256E

6 REGISTERS
6.1

Status Register
Table 5. Status Register-SR No.1

No.

Name

Description

Note

S7

SRP0

Status Register Protection Bit

Non-volatile writable

S6

BP4

Block Protect Bit

Non-volatile writable

S5

BP3

Block Protect Bit

Non-volatile writable

S4

BP2

Block Protect Bit

Non-volatile writable

S3

BP1

Block Protect Bit

Non-volatile writable

S2

BP0

Block Protect Bit

Non-volatile writable

S1

WEL

Write Enable Latch

Volatile, read only

S0

WIP

Erase/Write In Progress

Volatile, read only

Table 6. Status Register-SR No.2
No.

Name

Description

Note

S15

SUS1

Erase Suspend Bit

Volatile, read only

S14

SRP1

Status Register Protection Bit

Non-volatile writable

S13

LB3

Security Register Lock Bit

Non-volatile writable (OTP)

S12

LB2

Security Register Lock Bit

Non-volatile writable (OTP)

S11

LB1

Security Register Lock Bit

Non-volatile writable (OTP)

S10

SUS2

Program Suspend Bit

Volatile, read only

S9

QE

Quad Enable Bit

QE = 1 permanently

S8

ADS

Current Address Mode Bit

Volatile, read only

No.

Name

Description

Note

S23

Reserved

Reserved

Reserved

S22

DRV1

Output Driver Strength Bit

Non-volatile writable

S21

DRV0

Output Driver Strength Bit

Non-volatile writable

S20

ADP

Power Up Address Mode Bit

Non-volatile writable

S19

EE

Erase Error Bit

Volatile, read only

S18

PE

Program Error Bit

Volatile, read only

S17

DC1

Dummy Configuration Bit

Non-volatile writable

S16

DC0

Dummy Configuration Bit

Non-volatile writable

Table 7. Status Register-SR No.3

The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When

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WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means
the device is not in program/erase/write status register progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erasecommand is accepted.
BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 2&3)
becomes protected against Page Program (PP), Sector Erase (SE), Block Erase (BE), and Chip Erase (CE) commands.
SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits
control the method of write protection: software protection, power supply lock-down or one time programmable protection.
SRP1

SRP0

Status Register00

Software Protected

10Power Supply Lock-Down(1)(2)

1

1

One Time Program(2)Description
The Status Register can be written to after a Write Enablecommand, WEL=1.(Default)
Status Register is protected and cannot be written to again until
the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be written
to.

NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
ADS bit
The Address Status (ADS) bit is a read only bit that indicates the current address mode the device is operating in. The
device is in 3-Byte address mode when ADS=0 (default), and in 4-Byte address mode when ADS=1.
QE bitThe Quad Enable (QE) bit is a non-volatile bit in the Status Register that allows Quad operation. The default value of QE
bit is 1 and it cannot be changed, so that the IO2 and IO3 pins are enabled all the time.
LB3, LB2, LB1 bits
The LB3, LB2 and LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13, S12 and S11) thatprovide the write protect control and status to the Security Registers. The default state of LB3, LB2 and LB1 bits are 0, thesecurity registers are unlocked. The LB3, LB2 and LB1 bits can be set to 1 individually using the Write Register instruction.
The LB3, LB2 and LB1 bits are One Time Programmable, once they are set to 1, the Security Registers will become readonly permanently.

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GD25B256E

SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an Erase/
Program Suspend (75H) command (The Erase Suspend will set the SUS1 bit to 1, and the Program Suspend will set the
SUS2 bit to 1). The SUS1 and SUS2 bits are cleared to 0 by Erase/Program Resume (7AH) command, software reset(66H+99H) command, as well as a power-down, power-up cycle.
DC1, DC0 bits
The Dummy Configuration (DC) bits are non-volatile, which select the number of dummy cycles between the end of address
and the start of read data output. Dummy cycles provide additional latency that is needed to complete the initial read accessof the flash array before data can be returned to the host system. Some read commands require additional dummy cycles
as the SCLK frequency increases.
The following dummy cycle tables provide different dummy cycle settings that are configured.
Command

BBH, BCH

EBH, ECH

DC1, DC0

Dummy Cycles

Freq.(MHz)

00

4

104

01

8

133

10

4

104

11

8

133

00

6

104

01

10

133

10

6

104

11

10

133

PE bit
The Program Error (PE) bit is a read-only bit that indicates a program failure. It will also be set when the user attempts toprogram a protected array sector or access the locked OTP space. PE is cleared to "0" after program operation resumes.
EE bit
The Erase Error (EE) bit is a read-only bit that indicates an erase failure. It will also be set when the user attempts to erase
a protected array sector or access the locked OTP space. EE is cleared to "0" after erase operation resumes
ADP bit
The Address Power-up (ADP) bit is a non-volatile writable bit that determines the initial address mode when the device ispowered on or reset. This bit is only used during the power on or device reset initialization period. When ADP=0 (factory
default), the device will power up into 3-Byte address mode, the Extended Address Register must be used to access memory
regions beyond 128Mb. When ADP=1, the device will power up into 4-Byte address mode directly.

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Power Up
Device Initialization& Status Register Refresh(Non-Volatile Cells)

3-Byte Address

Standard SPI
Dual SPI
Quad SPI

ADP bit value

Enable 4-Byte (B7H)
Disable 4-Byte (E9H)

ADP = 1

4-Byte Address

Standard SPI
Dual SPI
Quad SPI

DRV1, DRV0 bits
The DRV1 and DRV0 bits are used to determine the output driver strength for the Read operations.
Table 8. Driver Strength for Read Operations
DRV1, DRV0

Driver Strength

00

100%

01

75% (default)

10

50%

11

25%

Reserved bit
It is recommended to set the value of the reserved bit as “0”.

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Software Reset(66H + 99H)

HardwareReset

ADP = 0

Uniform Sector
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6.2

GD25B256E

Extended Address Register
Table 9. Extended Address Register

No.

Name

Description

Note

EA7

Reserved

Reserved

Reserved

EA6

Reserved

Reserved

Reserved

EA5

Reserved

Reserved

Reserved

EA4

Reserved

Reserved

Reserved

EA3

Reserved

Reserved

Reserved

EA2

Reserved

Reserved

Reserved

EA1

Reserved

Reserved

Reserved

EA0

A24

Address bit

Volatile writable

The bits of the Extended Address Register are as follows:
A24 bit
The Extended Address Bits are used only when the device is operating in the 3-Byte Address Mode, which are volatile
writable by C5H command.
A24

Address

00000 0000h-00FF FFFFh

1

0100 0000h-01FF FFFFh

If the device powers up with ADP bit set to 1, or an “Enter 4-Byte Address Mode (B7H)” instruction is issued, the device will
require 4-Byte address input for all address related instructions, and the Extended Address Bit setting will be ignored.
Reserved bit
It is recommended to set the value of the reserved bit as “0”.

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GD25B256E

COMMAND DESCRIPTIONSAll commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the firstrising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with mostsignificant bit first on SI, and each bit is latched on the rising edges of SCLK.
Every command sequence starts with a one-byte command code. Depending on the command, this might be followed byaddress bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence
has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down,
and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can becompleted after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return todeselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write
Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command isrejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low
is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL
will not be reset.
Table 10. Commands (3- or 4-Byte Addr. Mode)
Command Name

Byte 1

Byte 2Byte 3

Write Enable

06H

Write Disable

04H

Read Status Register-1

05H(S7-S0)(cont.)

Read Status Register-2

35H(S15-S8)(cont.)

Read Status Register-3

15H(S23-S16)(cont.)

Write Status Register-1

01H

S7-S0

Write Status Register-2

31H

S15-S8

Write Status Register-3

11H

S23-S16

C8H(EA7-EA0)

C5H

EA7-EA0

Read Extended Addr.
RegisterWrite Extended Addr.
Register
Volatile SR write
EnableSet Burst with Wrap
Chip Erase
Enter 4-Byte Address
Mode
Exit 4-Byte Address
Mode

Byte 4

Byte 550H
77H

dummy(1)dummy(1)dummy(1) W7-W0(1)C7/60H
B7H
E9H

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Byte 6

Byte 7

Byte 8Byte 9Uniform Sector
Dual and Quad Serial Flash
Read Manufacturer/
Device ID

90H

Read Identification

9FH

Enable Reset

66H

Reset

99H

Program/Erase
Suspend
Program/Erase
ResumeDeep Power-Down
Release From DeepPower-Down

00H(MID7MID0)

00H

00H

GD25B256E(MID7MID0)(ID15-ID8) (ID7-ID0)(cont.)(ID7-ID0)(cont.)

75H
7AH
B9H
ABH

Release From DeepPower-Down and Read

ABH

dummy

dummy

dummy

(ID7-ID0)(cont.)5AH

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(cont.)13H

A31-A24

A23-A16

A15-A8

A7-A0(D7-D0)(cont.)0CH

A31-A24

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(cont.)3CH

A31-A24

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(2)(cont.)

6CH

A31-A24

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(3)(cont.)BCH

A31-A24(4) A23-A16(4) A15-A8(4)A7-A0(4)M7-M0(5) (D7-D0)(2)(cont.)ECH

A31-A24(6) A23-A16(6) A15-A8(6)A7-A0(6)M7-M0(7)

dummy

dummy

12H

A31-A24

A23-A16

A15-A8

A7-A0

D7-D0

Next Byte

34H

A31-A24

A23-A16

A15-A8

A7-A0

D7-D0(8) Next Byte

21H

A31-A24

A23-A16

A15-A8

A7-A0

5CH

A31-A24

A23-A16

A15-A8

A7-A0

DCH

A31-A24

A23-A16

A15-A8

A7-A0

Device ID
Read Serial Flash
Discoverable
Parameter
Read Data with 4-Byte
Address
Fast Read with 4-Byte
Address
Fast Read Dual Output
with 4-Byte Address
Fast Read Quad
Output with 4-Byte
Address
Fast Read Dual I/Owith 4-Byte Address
Fast Read Quad I/Owith 4-Byte Address
Page Program with 4Byte Address
Quad Page Programwith 4-Byte Address
Sector Erase with 4Byte Address
Block Erase (32K) with
4-Byte Address
Block Erase (64K) with
4-Byte Address

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Table 11. Commands (3-Byte Addr. Mode)
Command Name

Byte 1

Byte 2Byte 3

Byte 4

Byte 5

Byte 6

Read Data

03H

A23-A16

A15-A8

A7-A0(D7-D0)(cont.)

Fast Read

0BH

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(cont.)

Dual Output Fast Read

3BH

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(2)(cont.)6BH

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(3)(cont.)

Dual I/O Fast Read

BBH

A23-A16(9) A15-A8(9)A7-A0(9)M7-M0(5) (D7-D0)(2)(cont.)

Quad I/O Fast Read

EBH

A15-A8(10) A7-A0(10)M7-M0(7)dummy

dummy (D7-D0)(3) (cont.)

Page Program

02H

A15-A8

A7-A0

D7-D0

Next Byte

D7-D0(8)Next Byte

Quad Output Fast
Read

A23A16(10)A23-A16

Quad Page Program

32H

A23-A16

A15-A8

A7-A0

Sector Erase

20H

A23-A16

A15-A8

A7-A0

Block Erase (32K)

52H

A23-A16

A15-A8

A7-A0

Block Erase (64K)

D8H

A23-A16

A15-A8A7-A0

Read Unique ID

4BH

00H

00H

00H

44H

A23-A16

A15-A8

A7-A0

42H

A23-A16

A15-A8

A7-A0

D7-D0

Next Byte

48H

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)Erase Security
Registers(11)Program Security
Registers(11)Read Security
Registers(11)dummy(UID7UID0)

Byte 7

Byte 8Byte 9(cont.)(cont.)

Table 12. Commands (4-Byte Addr. Mode)
Command Name

Byte 1

Byte 2Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

Read Data

03H

A31-A24

A23-A16

A15-A8

A7-A0(D7-D0)(cont.)

Fast Read

0BH

A31-A24

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(cont.)

Dual Output Fast Read

3BH

A31-A24

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(2)(cont.)6BH

A31-A24

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)(3)(cont.)

Dual I/O Fast Read

BBH

A31-A24(4) A23-A16(4) A15-A8(4)A7-A0(4)M7-M0(5) (D7-D0)(2)(cont.)

Quad I/O Fast Read

EBH

A31-A24(6) A23-A16(6) A15-A8(6)A7-A0(6)M7-M0(6)

dummy

dummy

Page Program

02H

A31-A24

A15-A8

A7-A0

D7-D0

Next Byte

Quad Page Program

32H

A31-A24(6) A23-A16(6) A15-A8(6)A7-A0(6)D7-D0(8) Next Byte

Sector Erase

20H

A31-A24

A23-A16

A15-A8

A7-A0

Block Erase (32K)

52H

A31-A24

A23-A16

A15-A8

A7-A0

Block Erase (64K)

D8H

A31-A24

A23-A16

A15-A8A7-A0

Quad Output Fast
Read

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Byte 8Byte 9(D7D0)(3)

Uniform Sector
Dual and Quad Serial Flash
Read Unique ID
Erase Security
Registers(11)Program Security
Registers(11)Read Security
Registers(11)GD25B256E
dummy(UID7-

4BH

00H

00H

00H

00H

44H

A31-A24

A23-A16

A15-A8

A7-A0

42H

A31-A24

A23-A16

A15-A8

A7-A0

D7-D0

Next Byte

48H

A31-A24

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)Note:
1. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, x, x)
2. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
3. Quad Output Data
IO0 = (D4, D0, …)
IO1 = (D5, D1, …)
IO2 = (D6, D2, …)
IO3 = (D7, D3, …)
4. Dual Input 4-Byte Address
IO0 = A30, A28, A26, A24, A22, A20, A18, A16, A14, A12, A10, A8

A6, A4, A2, A0

IO1 = A31, A29, A27, A25, A23, A21, A19, A17, A15, A13, A11, A9

A7, A5, A3, A1

5. Dual Input Mode bit
IO0 = M6, M4, M2, M0
IO1 = M7, M5, M3, M1
6. Quad Input 4-Byte Address
IO0 = A28, A24, A20, A16, A12, A8, A4, A0
IO1 = A29, A25, A21, A17, A13, A9, A5, A1
IO2 = A30, A26, A22, A18, A14, A10, A6, A2
IO3 = A31, A27, A23, A19, A15, A11, A7, A3
7. Quad Input Mode bit
IO0 = M4, M0
IO1 = M5, M1
IO2 = M6, M2
IO3 = M7, M3
8. Quad Output Data
IO0 = D4, D0, …
IO1 = D5, D1, …
IO2 = D6, D2, …
IO3 = D7, D3, …

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UID0)(cont.)(cont.)

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GD25B256E

9. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8

A6, A4, A2, A0

IO1 = A23, A21, A19, A17, A15, A13, A11, A9

A7, A5, A3, A1

10. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0
IO1 = A21, A17, A13, A9, A5, A1
IO2 = A22, A18, A14, A10, A6, A2
IO3 = A23, A19, A15, A11, A7, A3
11. Security Registers Address
Security Register1: A23-A16=00H, A15-A12=1H, A11 = 0b, A10-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A12=2H, A11 = 0b, A10-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A12=3H, A11 = 0b, A10-A0= Byte Address;

TABLE OF ID DEFINITIONS
GD25B256E
Operation Code

MID7-MID0

ID15-ID8

ID7-ID0

9FH

C8

40

19

90H

C8

18

ABH

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7.1

GD25B256E

Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must
be set prior to every Page Program (PP), Quad Page Program (QPP), Sector Erase (SE), Block Erase (BE), Chip Erase(CE), Write Status Register (WRSR) and Erase/Program Security Registers command.
The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes high.
Figure 2. Write Enable Sequence Diagram
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

06H
High-ZSO

7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit may be
set to 0 by issuing the Write Disable (WRDI) command to disable Page Program (PP), Quad Page Program (QPP), Sector
Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), that require WEL be set to 1 for execution.
The WRDI command can be used by the user to protect memory areas against inadvertent writes that can possibly corrupt
the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1.
The WEL bit is reset by following condition: Write Disable command (WRDI), Power-up, and upon completion of the Write
Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands.
The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high.
Figure 3. Write Disable Sequence Diagram
CS#
0

1

2

3

4

5

6

7

SCLK
Command

SI

SO

04H
High-Z

7.3 Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any
time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it
is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code of “05H” / “35H” / “15H”, the SO will output Status Register
bits S7~S0 / S15~S8 / S23~S16.

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Figure 4. Read Status Register Sequence Diagram

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

7

Status Register 1/2/3
6 5 4 3 2 1 0

SCLK
Command
05H or 35H or 15H

SI

High-Z

SO

MSB

7

Status Register 1/2/3
6 5 4 3 2 1 0

7MSB

7.4 Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S19, S18, S15, S10, S9, S8, S1 and S0 of the Status Register.
For command code of “01H” / “31H” / “11H”, the Status Register bits S7~S0 / S15~S8 / S23~S16 would be written. CS#
must be driven high after the eighth bit of the data byte has been latched in. Otherwise, the Write Status Register (WRSR)
command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW)
is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value ofthe Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, andis 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2,
BP1, and BP0) bits, to define the size of the area that is to be treated as read-only.
Figure 5. Write Status Register Sequence Diagram
CS#

0

1

8

9 10 11 12 13 14 15

01H/31H/11H

7

6

High-Z

MSB

2

3

4

5

6

7

SCLK
Command

SI
SO

7.5

Status Register in
5

4

3

2

1

0

Read Extended Address Register (C8H)

The Read Extended Address Register instruction is entered by driving CS# low and shifting the instruction code “C8H” into
the SI pin on the rising edge of SCLK. The Extended Register bits are then shifted out on the SO pin at the falling edge of
SCLK with most significant bit (MSB) first.

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Figure 6 Read Extended Address Register Sequence Diagram

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLKCommandSI

C8H
High-ZSO

7

6

EAR out
5 4 3 2

MSB

7.6

1

0

7

6

EAR out
5 4 3 2

1

0

7

MSB

Write Extended Address Register (C5H)

The Write Extended Address Register instruction allows new Address bit values to be written to the Extended Address
Register. A Write Enable (WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit before it
can be accepted.
The Write Extended Address Register instruction is entered by driving CS# low, sending the instruction code “C5H”, andthen writing the Extended Register data Byte.
Upon power up or the execution of a Software/Hardware Reset, the Extended Address Register bit values will be cleared
to 0.
Figure 7 Write Extended Address Register Sequence Diagram
CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

C5H

7

Extended Addr.
Register In
6 5 4 3 2 1

High-ZMSB

SCLKCommand

SI
SO

7.7

0

Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system
configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting
the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be
issued prior to a Write Status Register command and any other commands can’t be inserted between them. Otherwise,
Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set
the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit
values.

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Figure 8. Write Enable for Volatile Status Register Sequence Diagram

CS#

0

1

2

3

4

5

6

7

SCLK

CommandSI

50H
High-ZSO

7.8 Read Data Bytes (03H/13H)
The Read Data Bytes (READ) command is followed by a 3/4-Byte address, and each bit being latched-in on the rising edgeof SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency
fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read with a single
Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle isin progress, is rejected without having any effects on the cycle that is in progress.
Figure 9. Read Data Bytes Sequence Diagram

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31 32 33 34 35 36 37 38 39

SCLKCommand03H

SI

High-ZSO

24-bit address

3

23 22 21

2

1

0

MSB
MSB

7

6

Data Out1
5 4 3 2 1

Data Out20

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.9

Read Data Bytes at Higher Speed (0BH/0CH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3/4-Byte
address and a dummy Byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, and each bit being shifted out, at a Max frequency f C, on the falling edge of SCLK. The first
Byte addressed can be at any location. The address is automatically incremented to the next higher address after each
Byte of data is shifted out.

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Figure 10. Read Data Bytes at Higher Speed Sequence Diagram

CS#
0

1

2

3

4

5

6

8

7

9 10

28 29 30 31

SCLK
24-bit address

Command23 22 21

0BH

SI

1

2

3

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

Dummy Byte
SI

7

6

5

4

3

0

1

2

7 6
MSB

SO

Data Out1
5 4 3 20

1Data Out2
7 6 5
MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.10 Dual Output Fast Read (3BH/3CH)
The Dual Output Fast Read command is followed by 3/4-Byte address and a dummy Byte, and each bit being latched in on
the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after
each Byte of data is shifted out.
Figure 11. Dual Output Fast Read Sequence Diagram

CS#
0

1

2

3

4

5

6

8

7

9 10

28 29 30 31

SCLK

24-bit address

CommandSI
SO

23 22 21

3BH

1

2

3

0

High-ZCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Dummy Clocks
SI
SO

0

6

Data Out2
Data Out1
7 5 3 1 7 5 3 1
MSB
MSB

7

6

4

2

0

6

4

2

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.11 Quad Output Fast Read (6BH/6CH)
The Quad Output Fast Read command is followed by 3/4-Byte address and a dummy Byte, and each bit being latched in

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GD25B256E

on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The
first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each
Byte of data is shifted out.
Figure 12 Quad Output Fast Read Sequence Diagram
CS#
0

1

2

3

4

5

6

8

7

9 10

28 29 30 31

SCLK
24-bit address

Command

IO0

1

2

3

0

High-Z

IO1

High-Z

IO2

High-Z

IO3
CS#

23 22 21

6BH

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Dummy Clocks

IO0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

IO3

7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.12 Dual I/O Fast Read (BBH/BCH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3/4Byte address and a “Continuous Read Mode” Byte 2-bit per clock by SI and SO, and each bit being latched in on the risingedge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first Byte addressed canbe at any location. The address is automatically incremented to the next higher address after each Byte of data is shiftedout.

Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits
(M7-4) after the input 3- or 4-Byte address (A23-A0 or A31-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then
the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. If
the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the command code, thus returning
to normal operation. A Reset command can be also used to reset (M7-0) before issuing normal command.

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Figure 13 Dual I/O Fast Read Sequence Diagram ((M5-4) ≠ (1, 0))

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

6

4

2

0

6

5

3

1

7

SCLK

Command
BBH

IO0
IO1

7

A23-16
CS#

4

2

0

6

5

3

1

7

A15-8

4

2

0

6

5

3

1

7

A7-0

4

2

0

5

3

1

M7-0

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCLK
IO0

6

4

2

0

6

4

2

0

6

4

2

0

6

4

2

0

6

IO1

7

5

3

1

7

5

3

1

7

5

3

1

7

5

3

1

7

Byte2

Byte1

Byte3

Byte4

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.
Figure 14 Dual I/O Fast Read Sequence Diagram ((M5-4) = (1, 0))

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

IO0

6

4

2

0

6

4

2

0

6

4

2

0

6

IO1

7

5

3

1

7

5

3

1

7

5

3

1

7

SCLK

A23-16

CS#

A15-8

A7-0

4

2

0

5

3

1

M7-0

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SCLK
IO0

6

4

2

0

6

4

2

0

6

4

2

0

6

4

2

0

6

IO1

7

5

3

1

7

5

3

1

7

5

3

1

7

5

3

1

7

Byte1

Byte2

Byte3

Byte4

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.13 Quad I/O Fast Read (EBH/ECH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3/4Byte address and a “Continuous Read Mode” Byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, and each bit
being latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1,
IO2, IO3. The first Byte addressed can be at any location. The address is automatically incremented to the next higher

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address after each Byte of data is shifted out.

Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3- or 4-Byte address (A23-A0 or A31-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0),then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH commandcode. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the command code,
thus returning to normal operation. A Reset command can be also used to reset (M7-0) before issuing normal command.
Figure 15 Quad I/O Fast Read Sequence Diagram ((M5-4) ≠ (1, 0))
CS#
8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

0

1

2

3

4

5

6

7

SCLK
Command

IO0

EBH

A23-16 A15-8 A7-0 M7-0

Dummy

Byte1 Byte2

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.
Figure 16 Quad I/O Fast Read Sequence Diagram ((M5-4) = (1, 0))

CS#

5

0

6

7

8

13

14

15

SCLK

dummy

Address
IO[3:0]Addr.

M7-4 M3-0

Byte 1

Byte 2

Data out

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap”(77H) commands prior to EBH or ECH. The “Set Burst with Wrap” (77H) command can either enable or disable the “WrapAround” feature for the following EBH or ECH commands. When “Wrap Around” is enabled, the data being accessed canbe limited to either an 8/16/32/64-Byte section of a 256-Byte page. The output data starts at the initial address specified in
the command, once it reaches the ending boundary of the 8/16/32/64-Byte section, the output will wrap around the beginningboundary automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cacheafterwards within a fixed length (8/16/32/64-Byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.

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7.14 Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” command to access a fixed length of
8/16/32/64-byte section within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low  Send Set Burst with Wrap command  Send 24 dummy
bits  Send 8 bits “Wrap bits”  CS# goes high.
W6,W5

W4=0

W4=1 (default)

Wrap Around

Wrap Length

Wrap Around

Wrap Length

0, 0

Yes

8-byte

No

N/A

0, 1

Yes

16-byte

No

N/A

1, 0

Yes

32-byte

No

N/A

1, 1

Yes

64-byteNo

N/A

If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” command will use
the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return tonormal read operation, another Set Burst with Wrap command should be issued to set W4=1.
Figure 17. Set Burst with Wrap Sequence DiagramCS#

8

9 10 11 12 13 14 15

x

x

x

x

x

x

4

x

IO1

x

x

x

x

x

x

5

x

IO2

x

x

x

x

x

x

6

x

IO3

x

x

x

x

x

x

x

x

0

1

2

3

4

5

6

7

SCLK
Command

IO0

77H

W6-W4

7.15 Page Program (PP 02H or 4PP 12H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address Bytes
and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goesbeyond the end of the current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Programcommand sequence: CS# goes low  sending Page Program command  3 or 4-Byte address on SI  at least 1 Byte
data on SI  CS# goes high. If more than 256 Bytes are sent to the device, previously latched data are discarded and thelast 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent
to device, they are correctly programmed at the requested addresses without having any effects on the other Bytes of thesame page. CS# must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Page
Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page

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Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
Figure 18 Page Program Sequence Diagram (ADS=0)
CS#
0

1

2

3

4

5

6

8

7

28 29 30 31 32 33 34 35 36 37 38 39

9 10

SCLK
24-bit address

5

4

3

2

1

2077

2078

2079

1

0

0 7

1

MSB

0

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2073

MSB
2072

CS#

6

2076

2

3

2075

23 22 2102H

SI

Data Byte 1

2074

Command

7

6

SCLK

Data Byte 3

Data Byte 2
SI

7

6

5

4

MSB

3

2

1

0 7

6

5

4

3

2

MSB

Data Byte 256
1

0

5

4

3

2

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.16 Quad Page Program (32H/34H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. A Write Enable(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page
Program command. The quad Page Program command is entered by driving CS# Low, followed by the command code
(32H), three address Bytes and at least one data Byte on IO pins.
The command sequence is shown below. If more than 256 Bytes are sent to the device, previously latched data arediscarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256
data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on theother Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has been latched in;otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At someunspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.

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Figure 19 Quad Page Program Sequence Diagram

1

2

3

4

5

6

7

8

28 29 30 31 32 33 34 35

9 10

542

0

543

CS#

SCLK

0 4

0

4

0

Byte
256
4 0

IO1

5

1

5

1

5 1

IO2

6

2

6

2

6 2

IO3

7

3

7

3

7 3

24-bit address

Command
IO0

23 22 21

32H

2

3

Byte1 Byte2

1

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.17 Sector Erase (SE 20H or 4SE 21H)
The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered bydriving CS# low, followed by the command code, and 3- or 4-address Byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-Byte or 4-Byte address on
SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise
the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose
duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the valueof the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A
Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
bit is not executed.
Figure 20. Sector Erase Sequence Diagram

CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK
24 Bits Address

Command

SI

20H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.18 32KB Block Erase (BE32 52H or 4BE32 5CH)
The 32KB Block Erase command is for erasing the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase command is entered bydriving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid
address for the 32KB Block Erase command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-Byte or 4-Byte

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address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address byte has been latched in;otherwise the 32KB Block Erase command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle(whose duration is tBE1) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to checkthe value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit isreset. A 32KB Block Erase command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, andBP0) bits is not executed.
Figure 21. 32KB Block Erase Sequence Diagram (ADS=0)

CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK
24 Bits Address

Command

SI

23 22
MSB

52H

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.19 64KB Block Erase (BE64 D8H or 4BE64 DCH)
The 64KB Block Erase command is for erasing the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is enteredby driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid
address for the 64KB Block Erase command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-Byte or 4-Byte
address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address byte has been latched in;otherwise the 64KB Block Erase command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle(whose duration is tBE2) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to checkthe value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit isreset. A 64KB Block Erase command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, andBP0) bits is not executed.
Figure 22. 64KB Block Erase Sequence Diagram (ADS=0)

CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK
24 Bits Address

Command

SI

D8H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.20 Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS#
Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of thesequence.

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The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. CS# must be
driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed.
As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase
cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write inProgress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed, if theno block is protected by the Block Protect bits. The Chip Erase (CE) command is ignored if one or more sectors are protected.
Figure22. Chip Erase Sequence Diagram
CS#

0

1

2

3

4

5

6

7

SCLK

CommandSI

60H or C7H

7.21 Enter 4-Byte Address Mode (EN4B) (B7H)
The Enter 4-Byte Address Mode command enables accessing the address length of 32-bit for the memory area of higher
density (larger than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit
11 (ADS bit) of status register will be automatically set to “1” to indicate the 4-Byte address mode has been enabled. Oncethe 4-Byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit.
All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit.
The sequence of issuing EN4B instruction is: CS# goes low  sending Enter 4-Byte mode command CS# goes high.
Figure 23 Enter 4-Byte Address Mode Sequence Diagram

CS#
SCLK
SI
SO

0

1

2

3

4

5

6

7

Command
B7H
High-Z

7.22 Exit 4-Byte Address Mode (EX4B) (E9H)
The Exit 4-Byte Address Mode command is executed to exit the 4-Byte address mode and return to the default 3-Byte
address mode. After sending out the EX4B instruction, the bit 11 (ADS bit) of status register will be cleared to “0” to indicate
the exit of the 4-Byte address mode. Once exiting the 4-Byte address mode, the address length will return to 24-bit.
The sequence of issuing EX4B instruction is: CS# goes low  sending Exit 4-Byte Address Mode command CS# goeshigh.

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Figure 24 Exit 4-Byte Address Mode Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

7

CommandSI

E9H
High-ZSO

7.23 Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command thatprovides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK withmost significant bit (MSB) first.
Figure 25. Read Manufacture ID/ Device ID Sequence Diagram

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

SCLKCommandSI

90H

3

23 22 212

1

0

High-ZSO
CS#

24-bit address

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI
SO

7

Device ID

Manufacturer ID
6 5 4 3 2 1

0

MSB

7

6

5

4

3

2

1

0

MSB

7.24 Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes ofdevice identification. The device identification indicates the memory type in the first byte, and the memory capacity of thedevice in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is notdecoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followedby the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The Read
Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high,the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode

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and execute commands.
Figure 26. Read Identification ID Sequence Diagram

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6

SCLK

9FH

SI
SO

MSB

CS#

Manufacturer ID
5 4 3 2 10

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SCLK
SIMemory Type ID15-ID8
7 6 5 4 3 2 1 0

SO

Capacity ID7-ID0
6 5 4 3 2 1

7

0

MSB

MSB

7.25 Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique
ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3- or 4-Byte Address(000000H or 00000000H) Dummy Byte128bit Unique ID Out CS# goes high.
Figure 27. Read Unique ID Sequence Diagram
CS#
0

SCLK

1

2

3

4

5

6

7

9 10

28 29 30 31

24-bit address(000000H)
23 22 21
3 2

Command

SI

8

4BH

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI

Dummy Byte
7

6

5

4

3

2

0

1

SO

7
MSB

Data Out1
6 5 4 3 2

1

Data Out2
0 7 6 5MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.26 Erase Security Registers (44H)
The GD25B256E provides 3x2048-Byte Security Registers which can be erased and programmed individually. These

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registers may be used by the system manufacturers to store security and other important information separately from themain memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  3- or
4-Byte address on SI  CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth
bit of the last address Byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon
as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers
Lock Bit (LB1, LB2, LB3) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored.
Address

A23-16

A15-12

A11

A10-0

Security Register #1

00H

0001b

0b

Don't care

Security Register #2

00H

0010b

0b

Don't care

Security Register #3

00H

0011b

0b

Don't care

Figure 28. Erase Security Registers command Sequence Diagram

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK
CommandSI

44H

24 Bits Address

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.27 Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains eightpages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)
bit before sending the Program Security Registers command. The Program Security Registers command is entered bydriving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon asCS# is driven high, the self-timed Program Security Registers cycle (whose duration is t PP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB1, LB2, LB3) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
Address

A23-16

A15-12

A11

A10-0

Security Register #1

00H

0001b

0b

Byte Address

Security Register #2

00H

0010b

0b

Byte Address

Security Register #3

00H

0011b

0b

Byte Address

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Figure 29. Program Security Registers command Sequence Diagram
CS#
1

0

2

3

4

5

6

8

7

28 29 30 31 32 33 34 35 36 37 38 39

9 10

SCLK
24-bit address

5

4

3

2

1

2077

2078

2079

1

0

0 7

1

MSB

0

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2073

MSB
2072

CS#

6

2076

2

3

2075

23 22 2142HSI

Data Byte 1

2074

Command

SCLK

Data Byte 3

Data Byte 2
SI

7

6

4

5

3

0 7

1

2

MSB

1

2

3

4

5

6

Data Byte 256
7

0

MSB

2

3

4

5

6

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.

7.28 Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3- or 4-Byte
address (A23-A0 or A31-A0) and a dummy Byte, and each bit is latched-in on the rising edge of SCLK. Then the memory
content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency f C, on the falling edge of SCLK.
The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after
each byte of data is shifted out. Once the A10-0 address reaches the last byte of the register (Byte 7FFH), it will reset to
000H, the command is completed by driving CS# high.
Address

A23-16

A15-12

A11

A10-0

Security Register #1

00H

0001b

0b

Byte Address

Security Register #2

00H

0010b

0b

Byte Address

Security Register #3

00H

0011b

0b

Byte Address

Figure 30. Read Security Registers command Sequence Diagram

CS#
0

SCLK

1

2

3

4

5

6

8

7

28 29 30 31

24-bit address

CommandSI

9 10

23 22 21

48H

2

3

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO

7

6

5

4

3

2

1

0
7 6
MSB

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode or 4-Byte command, the address length is 32-bit.
37

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7.29 Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default
power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status(WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous Read Modebit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and “Reset (99H)” command sequence as follow: CS# goes low  Sending Enable Resetcommand  CS# goes high  CS# goes low  Sending Reset command  CS# goes high. Once the Reset command isaccepted by the device, the device will take approximately t RST / tRST_E to reset. During this period, no command will be
accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by the device. It is recommended to check the WIP bit and the SUS1/SUS2 bit in
Status Register before issuing the Reset command sequence.
Figure 31. Enable Reset and Reset command Sequence Diagram

CS#

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCLK

SI

CommandCommand

66H

99H

High-ZSO

7.30 Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H, 31H, 11H) and
Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 21H, 52H, 5CH, D8H, DCH, C7H,
60H) and Page Program command (02H, 12H, 32H, 34H) are not allowed during Program suspend. The Write Status
Register command (01H, 31H, 11H) and Erase Security Registers command (44H) and Erase commands (20H, 21H, 52H,
5CH, D8H, DCH, C7H, 60H) are not allowed during Erase suspend. Program/Erase Suspend is valid only during the page
program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend theprogram/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS1/SUS2 bit in the Status Register
equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS1/SUS2
bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1
to 0 within “tsus” and the SUS1/SUS2 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off
during the suspend period will reset the device and release the suspend state.
Figure 32. Program/Erase Suspend Sequence Diagram
CS#

0

1

2

3

4

5

6

7

tSUS

SCLK

Command
SI
SO

75H
High-Z
Accept read command

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7.31 Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a
Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS1/SUS2 bit equal to 1 and the WIP bit equal to 0. After issued the SUS1/SUS2 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active.
Figure 33. Program/Erase Resume Sequence Diagram
CS#

0

1

2

3

4

5

6

7

SCLK
CommandSI

7AH
Resume Erase/Program

7.32 Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (theDeep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in activeuse, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device,
and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the DeepPower-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command.
Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down and Read Device ID (RDI) command or software reset command. The Release from Deep Power-Down andRead Device ID (RDI) command releases the device from Deep Power-Down mode, also allows the Device ID of the device
to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always in the Standby Mode after PowerUp.
The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high.
CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down(DP) command is not executed. As soon as CS# is driven high, it requires a delay of t DP before the supply current is reduced
to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 34. Deep Power-Down Sequence Diagram

CS#
0

1

2

3

4

5

6

7

tDP

SCLK
CommandSI

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Deep Power-down mode

B9H

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7.33 Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release thedevice from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high. Release from Power-Down will take the time duration of tRES1 (See AC
Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin mustremain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS#
pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The ID7~ID0 are then shifted out on the fallingedge of SCLK with most significant bit (MSB) first. The Device ID value is listed in Manufacturer and Device Identificationtable. The Device ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the ID7~ID0, the command is the same aspreviously described, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC
Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If
the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (whenWIP equals 1) the command is ignored and will not have any effects on the current cycle.
Figure 35. Release Power-Down Sequence Diagram

CS#

0

1

2

3

4

5

6

t RES17

SCLK

CommandSI

ABH
Deep Power-down modeStand-by mode

Figure 36. Release Power-Down/Read Device ID Sequence Diagram

CS#
0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38

SCLKCommand

SI

SO

ABH

High-Zt RES23 Dummy Bytes

23 22

2

1

0

MSB

MSB

7

6

Device ID
5 4 3 2

10

Deep Power-down Mode Stand-byMode

7.34 Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional andfeature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can beinterrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216B.

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Figure 37. Read Serial Flash Discoverable Parameter command Sequence Diagram

CS#

0

SCLK

1

2

3

4

5

6

7

8

CommandSI

9 10

28 29 30 31

24-bit address

5AH

3

23 22 212

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO

Dummy Byte

7

6

5

4

3

2

1

0

7 6
MSB

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

Table 13. Signature and Parameter Identification Data Values (Please contact GigaDevice for Details)

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GD25B256E

ELECTRICAL CHARACTERISTICS

8.1 Power-On Timing
Figure 38. Power-On Timing Sequence Diagram
Vcc(max)

Chip Selection is not allowed
Vcc(min)tVSL

Device is fully
accessible

VWI

Time

Table 14. Power-Up Timing and Write Inhibit Threshold
SymbolParameter

Min.

tVSL

VCC (min.) to device operation

2.5

VWI

Write Inhibit Voltage

1.5

Max.

Unit
ms

2.5

V

8.2 Initial Delivery StateThe device is delivered with the memory array erased: all bits are set to 1 (each Byte contains FFH). The Status Registercontains 00H, except that DRV0 bit (S21) and QE bit (S9) are set to 1.

8.3

Absolute Maximum Ratings
Parameter

Value

Unit

Ambient Operating Temperature (TA)

-40 to 85℃-40 to 105-40 to 125
Storage Temperature-65 to 150℃

Transient Input/Output Voltage (note: overshoot)-2.0 to VCC+2.0

V

Applied Input/Output Voltage-0.6 to VCC+0.4

V-0.6 to 4.2

V

VCC

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GD25B256E

Figure 39. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns

Maximum Positive Overshoot Waveform

20ns

20ns

Vss
Vcc + 2.0V

Vss-2.0V
Vcc

20ns

20ns

20ns

8.4 Capacitance Measurement Conditions
SymbolParameter

Min.

Typ.

Max.

Unit

Conditions

CIN

Input Capacitance6

pF

VIN=0V

COUT

Output Capacitance8pF

VOUT=0V

CL

Load Capacitance

30

pF

Input Rise And Fall time

5ns

Input Pulse Voltage

0.1VCC to 0.8VCC

V

Input Timing Reference Voltage

0.2VCC to 0.7VCC

V

Output Timing Reference Voltage

0.5VCCV

Figure 40. Absolute Maximum Ratings Diagram

0.8VCC

Input timing reference level

0.1VCC

0.7VCC
0.2VCC

Output timing reference level
AC Measurement Level

Note: Input pulse rise and fall time are<5ns

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8.5 DC Characteristics(TA = -40℃~85℃, VCC=2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

μA

ILO

Output Leakage Current

±2

μA

ICC1

Standby Current

16

50

μA

ICC2

Deep Power-Down Current

1

15

μA

14

27

mA

12

15

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 133MHz,

ICC3Operating Current (Read)

Q=Open(x4 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(x4 I/O)

ICC4Operating Current (PP)

CS#=VCC

12

20

mA

ICC5

Operating Current (WRSR)

CS#=VCC

12

20

mA

ICC6

Operating Current (SE)

CS#=VCC

12

20

mA

ICC7

Operating Current (BE)

CS#=VCC

12

20

mA

ICC8

Operating Current (CE)

CS#=VCC

12

20

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 3.3V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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GD25B256E(TA = -40℃~105℃, VCC=2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

μA

ILO

Output Leakage Current

±2

μA

ICC1

Standby Current

16

100

μA

ICC2

Deep Power-Down Current

1

35

μA

14

32

mA

12

20

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 133MHz,

ICC3Operating Current (Read)

Q=Open(x4 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(x4 I/O)

ICC4Operating Current (PP)

CS#=VCC

12

25

mA

ICC5

Operating Current (WRSR)

CS#=VCC

12

25

mA

ICC6

Operating Current (SE)

CS#=VCC

12

25

mA

ICC7

Operating Current (BE)

CS#=VCC

12

25

mA

ICC8

Operating Current (CE)

CS#=VCC

12

25

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 3.3V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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VUniform Sector
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GD25B256E(TA = -40℃~125℃, VCC=2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

μA

ILO

Output Leakage Current

±2

μA

ICC1

Standby Current

16

200

μA

ICC2

Deep Power-Down Current

1

60

μA

14

32

mA

12

20

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 133MHz,

ICC3Operating Current (Read)

Q=Open(x4 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(x4 I/O)

ICC4Operating Current (PP)

CS#=VCC

12

25

mA

ICC5

Operating Current (WRSR)

CS#=VCC

12

25

mA

ICC6

Operating Current (SE)

CS#=VCC

12

25

mA

ICC7

Operating Current (BE)

CS#=VCC

12

25

mA

ICC8

Operating Current (CE)

CS#=VCC

12

25

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 3.3V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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8.6

GD25B256E

AC Characteristics(TA = -40℃~85℃, VCC=2.7~3.6V, CL=30pf)
SymbolfC

Parameter

Min.

Typ.

Serial Clock Frequency For: all commands except
03H, 13H

Max.

Unit.

133

MHz

80

MHz

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time

tCLCH

Serial Clock Rise Time (Slew Rate)

0.2

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.2

V/ns

tSLCH

CS# Active Setup Time

5

ns

tCHSH

CS# Active Hold Time

5

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5

ns

tSHSL

CS# High Time (Read/Write)

20

ns

tSHQZ

Output Disable Time

tCLQX

Output Hold Time

1.2

ns

tDVCH

Data In Setup Time

2

ns

tCHDX

Data In Hold Time

2

ns

tCLQV

Clock Low To Output Valid (30pF)

7

ns

tDP

CS# High To Deep Power-Down Mode

3

μs

30

μs

30

μs

20

μs

tRES1
tRES2

45%
45%

6

CS# High To Standby Mode Without Electronic
Signature Read
CS# High To Standby Mode With Electronic Signature
Read
CS# High To Next Command After SuspendtRS

Latency Between Resume And Next Suspend

tRST_Ens(1/Fc)

tSUS

tRST

ns

(1/Fc)

100

ns

μs

CS# High To Next Command After Reset (Except
From Erase)CS# High To Next Command After Reset (FromErase)

30

μs

12

ms

tW

Write Status Register Cycle Time

5

20

ms

tBP1

Byte Program Time (First Byte)

40

90

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

7

μs

tPP

Page Programming Time

0.25

2

ms

tSE

Sector Erase Time

30

400

ms

tBE1

Block Erase Time (32K Bytes)

0.12

1.2

s

tBE2

Block Erase Time (64K Bytes)

0.15

1.6

s

tCE

Chip Erase Time (GD25B256E)

70

200

s

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1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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Uniform Sector
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GD25B256E(TA = -40℃~105℃, VCC=2.7~3.6V, CL=30pf)
SymbolfC

Parameter

Min.

Typ.

Serial Clock Frequency For: all commands except
03H, 13H

Max.

Unit.

133

MHz

80

MHz

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time

tCLCH

Serial Clock Rise Time (Slew Rate)

0.2

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.2

V/ns

tSLCH

CS# Active Setup Time

5

ns

tCHSH

CS# Active Hold Time

5

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5

ns

tSHSL

CS# High Time (Read/Write)

20

ns

tSHQZ

Output Disable Time

tCLQX

Output Hold Time

1.2

ns

tDVCH

Data In Setup Time

2

ns

tCHDX

Data In Hold Time

2

ns

tCLQV

Clock Low To Output Valid (30pF)

7

ns

tDP

CS# High To Deep Power-Down Mode

3

μs

30

μs

30

μs

20

μs

tRES1
tRES2

45%
45%

6

CS# High To Standby Mode Without Electronic
Signature Read
CS# High To Standby Mode With Electronic Signature
Read
CS# High To Next Command After SuspendtRS

Latency Between Resume And Next Suspend

tRST_Ens(1/Fc)

tSUS

tRST

ns

(1/Fc)

100

ns

μs

CS# High To Next Command After Reset (Except
From Erase)CS# High To Next Command After Reset (FromErase)

30

μs

12

ms

tW

Write Status Register Cycle Time

5

20

ms

tBP1

Byte Program Time (First Byte)

40

100

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

10

μs

tPP

Page Programming Time

0.25

2.4

ms

tSE

Sector Erase Time

30

500

ms

tBE1

Block Erase Time (32K Bytes)

0.12

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.15

3

s

tCE

Chip Erase Time (GD25B256E)

70

400

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

49

Rev.1.0

Uniform Sector
Dual and Quad Serial Flash

GD25B256E(TA = -40℃~125℃, VCC=2.7~3.6V, CL=30pf)
SymbolfC

Parameter

Min.

Typ.

Serial Clock Frequency For: all commands except
03H, 13H

Max.

Unit.

133

MHz

80

MHz

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time

tCLCH

Serial Clock Rise Time (Slew Rate)

0.2

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.2

V/ns

tSLCH

CS# Active Setup Time

5

ns

tCHSH

CS# Active Hold Time

5

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5

ns

tSHSL

CS# High Time (Read/Write)

20

ns

tSHQZ

Output Disable Time

tCLQX

Output Hold Time

1.2

ns

tDVCH

Data In Setup Time

2

ns

tCHDX

Data In Hold Time

2

ns

tCLQV

Clock Low To Output Valid (30pF)

7

ns

tDP

CS# High To Deep Power-Down Mode

3

μs

30

μs

30

μs

20

μs

tRES1
tRES2

45%
45%

6

CS# High To Standby Mode Without Electronic
Signature Read
CS# High To Standby Mode With Electronic Signature
Read
CS# High To Next Command After SuspendtRS

Latency Between Resume And Next Suspend

tRST_Ens(1/Fc)

tSUS

tRST

ns

(1/Fc)

100

ns

μs

CS# High To Next Command After Reset (Except
From Erase)CS# High To Next Command After Reset (FromErase)

30

μs

12

ms

tW

Write Status Register Cycle Time

5

20

ms

tBP1

Byte Program Time (First Byte)

40

100

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

10

μs

tPP

Page Programming Time

0.25

2.4

ms

tSE

Sector Erase Time

30

800

ms

tBE1

Block Erase Time (32K Bytes)

0.12

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.15

3

s

tCE

Chip Erase Time (GD25B256E)

70

400

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

50

Rev.1.0

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

Figure 41. Input Timing

tSHSL

CS#

tCHSL
SCLK

tSLCH

tDVCH

tCHSH

MSB

SO

High-Z

tCHCL

tCLCH

tCHDX

SI

tSHCH

LSB

Figure 42. Output Timing

CS#

tCLH

SCLK
tCLQV

tCLQV

tCLQX

tCLL

tCLQX

LSB

SO
SI
Least significant address bit (LIB) in

Figure 43. Resume to Suspend Timing Diagram

ResumeCommandCS#

tRS

SuspendCommandFigure 44 RESET Timing

CS#

tRB

RESET#
tRLRH

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51

Rev.1.0

tRHSL

tSHQZ

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

Table 15 Reset Timing
SymbolParameter

Min.

Typ.

Max.

Unit.

tRLRH

Reset Pulse Width

1

μs

tRHSL

Reset High Time Before Read

50

ns

tRB

Reset Recovery Time

12

Note:
1. The device need tRB (max) at most to get ready for all commands after RESET# low.

http://www.elm-tech.com

52

Rev.1.0msUniform Sector
Dual and Quad Serial Flash9

GD25B256E

ORDERING INFORMATIONGD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
S: Pb Free + Halogen Free Green Package + SRP1 Function
R: Pb Free + Halogen Free Green Package + RESET# Pin
K: Pb Free + Halogen Free Green Package + RESET# Pin +SRP1 Function
Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial (-40℃ to +105℃)
E: Industrial (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)**
Package Type
F: SOP16 300mil
W: WSON8 (6x5mm)
Y: WSON8 (8x6mm)
B: TFBGA-24ball (5x5 Ball Array)
Generation
E: E Version
Density256: 256M bit
Series
B: 3V, 4KB Uniform Sector, default x4I/O
Product Family
25: SPI NOR Flash**F grade has implemented additional test flows to ensure higher product quality than I grade.

http://www.elm-tech.com

53

Rev.1.0

Uniform Sector
Dual and Quad Serial Flash
9.1

GD25B256E

Valid Part Numbers

Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40℃ to +85℃)

Product Number

Density

Package Type

Packing
Options

GD25B256EFIR
GD25B256EWIG
GD25B256EWIS
GD25B256EYIGGD25B256EYISGD25B256EBIR

256Mbit

SOP16 300mil

T/Y/R

256Mbit

WSON8 (6x5mm)

Y/R

256Mbit

WSON8 (8x6mm)

Y/R

256MbitTFBGA-24ball (5x5 Ball Array)Y

Temperature Range J: Industrial (-40℃ to +105℃)

Product Number

Density

Package Type

Packing
Options

GD25B256EFJR
GD25B256EWJG
GD25B256EYJG
GD25B256EBJR

256Mbit
256Mbit
256Mbit
256Mbit

SOP16 300mil
WSON8 (6x5mm)
WSON8 (8x6mm)
TFBGA-24ball (5x5 Ball Array)

T/Y/R
Y/R
Y/R
Y

Temperature Range E: Industrial (-40℃ to +125℃)

Product Number

Density

Package Type

Packing
Options

GD25B256EFER
GD25B256EWEG
GD25B256EYEG
GD25B256EBER

256Mbit
256Mbit
256Mbit
256Mbit

SOP16 300mil
WSON8 (6x5mm)
WSON8 (8x6mm)
TFBGA-24ball (5x5 Ball Array)

T/Y/R
Y/R
Y/R
Y

Temperature Range F: Industrial+ (-40℃ to +85℃)

Product Number

Density

Package Type

Packing
Options

GD25B256EFFR
GD25B256EWFG
GD25B256EYFG
GD25B256EBFR

256Mbit
256Mbit
256Mbit
256Mbit

SOP16 300mil
WSON8 (6x5mm)
WSON8 (8x6mm)
TFBGA-24ball (5x5 Ball Array)

T/Y/R
Y/R
Y/R
Y

http://www.elm-tech.com

54

Rev.1.0

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

10 PACKAGE INFORMATION
10.1 Package SOP16 300MIL
D
16

9

E1

E

h
1

h

8

“A”

L1

L
θ

b

A

A2
b

Base Metalc
Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.10

2.05

0.31

0.10

10.20

10.10

7.40

Nom

-

0.20

-

0.41

0.25

10.30

10.30

7.50

Max

2.65

0.30

2.55

0.51

0.33

10.40

10.50

7.60

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.

http://www.elm-tech.com

55

Rev.1.0

e

L

L1

0.40
1.27

1.27

1.40

h

θ

0.25

0

-

-

0.75

8

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

10.2 Package WSON8 (6x5mm)c

D
PIN 1#E

A1
A

Top View

Side View

D2
4

5

e

E2

b

1

8

L
Bottom View
Dimensions
Symbol

A

A1

c

b

D

D2

E

E2

Min

0.70

0.00

0.180

0.35

5.90

3.30

4.90

3.90

Nom

0.75

0.02

0.203

0.40

6.00

3.40

5.00

4.00

Max

0.80

0.05

0.250

0.50

6.10

3.50

5.10

4.10

Unit
mm

e

L
0.50

1.27

0.60
0.75

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These leadshapes are compatible with each other.

http://www.elm-tech.com

56

Rev.1.0

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

10.3 Package WSON8 (8x6mm)c

D
PIN 1#E

A1
A

Top View

Side View

D2

4

5

E2

e
b

1

8

L
Bottom View
Dimensions
Symbol

A

A1

c

b

D

D2

E

E2

Min

0.70

0.00

0.180

0.35

7.90

3.30

5.90

4.20

Nom

0.75

0.02

0.203

0.40

8.00

3.40

6.00

4.30

Max

0.80

0.05

0.250

0.45

8.10

3.50

6.10

4.40

Unit
mm

e

L
0.45

1.27

0.50
0.55

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These leadshapes are compatible with each other.

http://www.elm-tech.com

57

Rev.1.0

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

10.4 Package TFBGA-24BALL (5x5 ball array)
1

2

3

4

5

5

4

3

2

1

A

A

B

B

b

C

D

C

D1

D

D

e

E

E
e

E

E1

A2

A

A1

Dimensions
Symbol

A

A1

A2

b

E

Min

-

0.25

0.75

0.35

5.90

Nom

-

0.30

0.80

0.40

6.00

Max

1.20

0.35

0.85

0.45

6.10

Unit
mm

E1

58

Rev.1.0

D1

e

4.00

1.00

7.90
4.00

Note: Both the package length and width do not include the mold flash.

http://www.elm-tech.com

D

8.00
8.10

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

11 REVISION HISTORY
Version No
1.0

Description
Initial release

http://www.elm-tech.com

59

Rev.1.0

Page

Date

All

2020-8-31

Uniform Sector
Dual and Quad Serial Flash

GD25B256E

Important NoticeThis document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
according to the laws of the People’s Republic of China and other applicable laws. The Company reserves all rights undersuch laws and no Intellectual Property Rights are transferred (either wholly or partially) or licensed (either expressly or
impliedly). The names and brands of third party referred thereto (if any) are the property of their respective owner andreferred to for identification purposes only.
The Company does not assume any warranty or condition, express or implied, with regard to this document or any
Product, including, but not limited to, the implied warranties of merchantability, fitness for any particular purpose, noninfringement, or any warranty arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document toproperly design, program, and test the functionality and safety of any application and any product produced. Except forcustomized products which has been expressly identified in the applicable agreement, the Products are designed,
developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The
Products are not designed or intended for use in, and no warranty is made respect to, any applications designed or intended
for the operation of weaponry, nuclear equipment, atomic energy control instruments, combustion control instruments,
airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical devices orsystems (including resuscitation equipment and surgical implants etc.), pollution control or hazardous substancesmanagement, or other uses where failure to perform can reasonably be expected to result in personal injury, death, property
or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, andcustomers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold theCompany as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and otherliabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves theright to make changes, corrections, modifications or improvements to this document and the Products andservices described herein at any time, without notice. And the company shall have no responsibility whatsoever
for conflicts or incompatibilities arising from future changes to them.

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60

Rev.1.0