Ⅱ-8. Accelerator

RIKEN Accel. Prog. Rep. 56 (2023)
RIKEN
Accel. Prog. Rep. 56 (2023)

Development and test operation of the prototype of the new beaminterlock system for machine protection of RIBF
M. Komiyama,∗1 M. Fujimaki,∗1 A. Kamoshida,∗1,∗2 M. Hamanaka,∗3 M. Nishimura,∗3 R. Koyama,∗3K. Kaneko,∗3 A. Uchiyama,∗1 and N. Fukunishi∗1
Continuing from 2021, we are developing a new beaminterlock system (BIS) for machine protection based on
CompactRIO1) (hereafter, cRIO-BIS), a product by National Instruments, as a successor system to the BIS,2)
which has been in operation since 2006. We set up a prototype using one CompactRIO and one expansion chassis
with I/O modules and developed the logic for digital input signals. The prototype signals for both a beam chopper and a beam stopper (Faraday cup) immediately after
receiving an alert signal. Details are shown in Fig. 1.
Chopper set/reset signal from the console,
1. Input alarm signal
users, devices, etc.
3. Order to work a beam chopper via
2. Order to work a beam
dedicated hardwire#1 (NI-9149)#5 (cRIO-9056)
chopperFPGA (on chassis)

BIS Logic Unit (DI)BIS Logic Unit (DI)BIS Logic Unit (DI)BIS Logic Unit (DI)

Relay-DO

BIS Logic Unit (DO)BIS Chopper Unit (TTL)BIS Chopper Unit (DO)CPU
FC status from EPICS

BIS Chopper Unit (DI)

Chopper output
request information

FPGA (on chassis)

2. Order to set Faradaycup (FC)

EPICS-LAN
FC status Set interlock pattern/ Monitor signals
4. Output a signal to a beam chopper.
It immediately deflects a beam justbelow the ion source.

N-DIM FC-H31

3. Insert FC installed upstream of theproblematic component

N-DIM FC-H72

Fig. 1. Hardware conﬁguration and process ﬂow in the cRIOBIS prototype.

The CompactRIO system has three layers for implementing logic for signal control: a ﬁeld-programmablegate array (FPGA) layer, which is the most reliable andcapable of the fastest signal processing, a real-time OS(RT-OS) layer that is positioned in the upper layer ofFPGA and communicates with FPGA, and a WindowsOS layer that is positioned in the upper layer of themand communicates with them. FPGA is implemented on
both CompactRIO and its expansion chassis, and RTOS is implemented on CompactRIO. The goal of cRIOBIS is to stop the beam within 1 ms by outputting asignal to the beam chopper from an alert signal input.
Thus, interlock logic for signal input/output is implemented on the FPGA. However, signal condition setting
and monitoring do not require the same speed as interlock logic. Thus, they are implemented on the RT-OSand controlled by using experimental physics and industrial control system (EPICS)3) by setting up an EPICS
server on the RT-OS.
Based on the operational experience of the BIS, cRIOBIS implements two types of logic units; BIS Logic Unit
∗1∗2
∗3

RIKEN Nishina Center
National Instruments Japan Corporation
SHI Accelerator Service Ltd.

(BLU) and BIS Chopper Unit (BCU). The BLU judges
conditions such as mask and holding time for alert signal
input and sends a signal to the BCU to request a signal
to the beam chopper via dedicated hard wire. The BCU
compares the input signal from the BLU and the insertion status of the Faraday cup and outputs a signal to thebeam chopper. Since the BCU is designed to perform not
only the function of BIS but also the role of the existingchopper signal control panel (it will be decommissioned
in the future), it also receives signals from the console’s
manual switches and user’s devices and outputs signal tothe beam chopper.
After developing the prototype in the control room,
its two stations were installed next to RIBF-BIS station 5 in the computer room of the Nishina Building andnext to RIBF-BIS station 1 in the power supply room 2of the RIBF building. The signal wiring was performed
during the summer maintenance period. Since the prototype was planned to be tested in a part of the RIBF-BISconsisting of 5 stations, we connected the input signals
into the prototype in parallel with the RIBF-BIS andevaluated its performance. The GUI for signal settingsand prototype monitoring has been developed using theControl System Studio (CSS)4) of EPICS, and the log
system has been developed using the system in RILACoperation.5)
After installing the prototype, we measured the response time of the system with alert signals generated
experimentally from an actual component and obtained
a result of approximately 250 µs (between 229.0 µs to260.0 µs). This is consistent with the system’s responsetime measurements using test input signals in the controlroom. Furthermore, it was conﬁrmed by the test that theresponse time could be reduced to less than 200 µs by
adding a pull-up circuit to the signal input/output part.
Since the response time of RIBF-BIS measured using thesame signal was approximately 15 ms, we were able todevelop a system that is approximately 100 times fasterthan the BIS.
We have started the test operation of the prototype
during the beam service times scheduled in the latter
half of the ﬁscal year 2022. Some minor corrections werenecessary; however, no major defects were observed.
References
1) CompactRIO,
https://www.ni.com/ja-jp/shop/compactrio.html .
2) M. Komiyama et al., RIKEN Accel. Prog. Rep. 39, 239(2006).
3) EPICS, https://epics.anl.gov/ .
4) CSS, http://controlsystemstudio.org/ .
5) A. Uchiyama et al., Proc. 18th Annual Meeting of Particle
Accelerator Society of Japan (2021), p. 532.

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