Nuclear Inst. and Methods in Physics Research, A 924 (2019) 422–425

Contents lists available at ScienceDirect

Nuclear Inst. and Methods in Physics Research, A
journal homepage: www.elsevier.com/locate/nima

R&D status of SOI-based pixel detector with 3D stacking readout✩
Toru Tsuboyama a ,∗, Shun Ono a , Miho Yamada a , Yasuo Arai a , Manabu Togawa a , Ikuo Kurachi a ,Yoichi Ikegami a , Kazuhiko Hara b , Akimasa Ishikawa c , Masayuki Ikebe d , Makoto Motoyoshi ea KEK, High Energy Accelerator Research Organization, Tsukuba, Ibaraki

305-0801, Japanb University of Tsukuba, Tsukuba, Ibaraki

305-8571, Japan
cTohoku University, Aoba-ku, Sendai, Miyagi 980-8578, JapandHokkaido University, Sapporo 060-0814, Japan
eTohoku Microtec, Aoba-ku, Sendai, Miyagi 980-8579, Japan

ARTICLEINFO

Keywords:
SOI CMOS pixel sensor
3D stacking

ABSTRACTSOFIST4 is an SOI pixel sensor designed for the International Linear Collider (ILC) vertex detector. In orderto satisfy the requirements of the ILC vertex detector, the chip consists of three-stage hit-charge and hit-timememories in each 20 μm × 20 μm pixel with 3D integration technology. The SOFIST4 chip was submitted for an
MPW run in 2017, and 3D integration will be performed in 2018. In this article, the design of the SOFIST4 chip
is first described. Then the 3D integration and 3D CAD technology are explained.

1. Introduction
The luminosity of particle accelerators is being increased rapidly inorder to examine the standard model and explore new particle physics.
The pixel detectors, which will be installed close to the collision point,should be operated at high hit rates from physics events as well asbeam backgrounds. To measure the particle tracks precisely, we needto reduce the pixel size. In addition, a high time resolution is necessary
to select the hit signal from the off timing backgrounds. To implement
such complex functions in the pixel sensor, we have started R&D of a
3D integration pixel sensor, where readout IC chips are stacked on thesensor, and a high-density signal connection is made between the chips.
An effort toward a 3D integrated pixel sensor has been reportedby the VIP collaboration [1]. The group stacked two readout ICs andintegrated them onto a sensor wafer. The X-ray images were successfully
obtained using the sensor.
2. SOFIST pixel sensor
In the International Linear Collider (ILC) [2], approximately 1300
beam bunches undergo collisions with 554-nsec intervals for 1 ms,
followed by a non-collision interval of 200 ms, as shown in Fig. 1.
The SOFIST silicon-on-insulator (SOI) pixel sensor [3] is designed tosatisfy the requirements for the bunch structure. We decided to integrate

several memories for the charge and timing of hits in each pixel andsample data during the 1300 collisions. The SOFIST1 and SOFIST2
prototype sensors have hit-charge memories and hit-time memories,respectively. SOFIST1 exhibited a 1.4 μm spatial resolution with a
20 μm × 20 μm pixel size [3]. SOFIST2 showed approximately 2 μsec
timing resolution (preliminary).
2.1. SOFIST4
In 2017, we submitted the SOFIST4 prototype chip. To integrate
the full pixel functions in the small pixel area of 20 μm × 20 μm,
we introduced SOI 3D integration technology. The pixel circuits are
distributed on the lower and the upper chips as shown in Fig. 2.
The sense node, charge-sensitive amplifier (CSA), and comparator are
integrated in the lower chip, and the shift register and the three-stage
hit-charge and hit-time memories are implemented in the upper chip.
There are four bump connections per pixel, as shown in Fig. 3. Twobumps transfer the analog signal and comparator output from the lower
chip to the upper chip. The other two bumps connect the ground andthe power supply to stabilize the power supply. The SOFIST4 chipincorporates the double SOI (DSOI) radiation-hard technology [4] sothat it will work in the harsh radiation conditions in high luminosity
accelerators. The specifications of the SOFIST4 chip are summarized inTable 1.

✩ This work is supported by a JSPS Grant-in-Aid for Scientific Research on Innovative Areas (No. 25109006), Japan, the Japan/US Cooperation Program in theField of High Energy Physics, Japan, KEK Detector Technology Project, Japan, the VLSI Design and Education Center (VDEC), the University of Tokyo, Japan, andTIA collaborative research program "Kakehashi" project, Japan. The authors also acknowledge the advice and work of the personnel of LAPIS Semiconductor Co.,Ltd.
∗ Corresponding author.
E-mail address: toru.tsuboyama@kek.jp (T. Tsuboyama).

https://doi.org/10.1016/j.nima.2018.08.089
Received 4 February 2018; Received in revised form 22 August 2018; Accepted 23 August 2018
Available online 29 August 20180168-9002/© 2018 Elsevier B.V. All rights reserved.

T. Tsuboyama, S. Ono, M. Yamada et al.

Nuclear Inst. and Methods in Physics Research, A 924 (2019) 422–425

Fig. 1. The beam collision structure of the ILC.

Fig. 2. Pixel circuit of SOFIST4.

Fig. 3. Pixel layouts of the SOFIST4 lower chip and upper chip. The four pads for the bump connection are shown with bold lines.
Table 1
Specifications of the SOFIST4 chip.

2.2. SOFIST4 operation

Pixel size
Number of bumps/pixel
Array size
Bump density
Active area
Chip size
Wafer
Wafer thickness

The CSA and comparator are reset before each beam collision. Ifthe comparator detects the hit signal after a collision, it triggers theshift register. The shift register outputs REGOUT_1 to 3 are connected
to hit-charge and hit-time memories 1 to 3, respectively. A ramping
voltage, which is used to record the hit time, is supplied to RAMP_IN.
The memories hold the hit-charge and ramping voltage when REGOUT_1
to 3 are asserted. Thus, each pixel can hold information on up to threehits in the 1300 collisions. The voltage in the hit-charge and hit-time
memories are read out at 200 ms intervals and transferred to the dataacquisition system.

20 μm × 20 μm
4104 × 104
10k connection/mm22.08 mm × 2.08 mm
4.45 mm × 4.45 mm
DSOI (FZ-p)
50 μmpressure in order to realize a reliable connection. As the pressure is alimited in order to reduce the stress to the CMOS circuit, it was notpossible to achieve a high connection yield.
To improve the quality of 3D integration, a method of using conebumps made of gold nanoparticles was developed [5]. Fig. 4 shows aschematic of the bump deposition apparatus. Gold nanoparticles areproduced in the generation chamber and transferred to the deposition

3. 3D integration with the gold nanoparticle bumps
To achieve high-density bump bonding, a new bumping method isintroduced. Conventionally, such high-density connections are madeusing indium bumps. However, the indium bump method requires high423

T. Tsuboyama, S. Ono, M. Yamada et al.

Nuclear Inst. and Methods in Physics Research, A 924 (2019) 422–425

Fig. 4. Schematic of the gold nanoparticle bump development chamber.

Fig. 5. (A) Typical shapes of the gold bumps. (B) Cut out view of a gold bump after the bonding process.

Fig. 6. Procedure for SOI 3D stacking.

Fig. 7. (a) Virtual layers for the DRC and LVS produced in the 3D CAD. (b) Procedure for the DRC and LVS for 3D stacking.

chamber. The nanoparticles are sprayed through a photoresist on thethere is no oxide layer, a high connection yield can be achieved. The
connection resistance is typically 0.3 Ω per connection [6].
Fig. 6 shows the procedure for 3D integration. (A) Gold bumps aredeveloped on the upper chip. (B) The upper and lower chips are thenplaced face to face and aligned. (C) The two chips are pressed so thatthe cone bumps on the upper chip touch the pads on the lower chip.
(D) Finally the silicon part of the upper chip is ground out and the wirebonding pads are developed. Through silicon vias are not necessary inwafer. They naturally develop into cone-shaped bumps, as shown inFig. 5(a). The typical size of each bump is 2.5 μm in diameter and 2.5 μm
in height. The minimum spacing between bumps is 5 μm. As the bumps
are piles of gold nanoparticles, they can be crushed by low pressure,as shown in Fig. 5(b); consequently, the variation of the bump heights
can be absorbed, and the stress to the silicon wafer is reduced. Because424

T. Tsuboyama, S. Ono, M. Yamada et al.

Nuclear Inst. and Methods in Physics Research, A 924 (2019) 422–425

the SOI 3D integration, because the electrical connections between thetop and bottom surfaces can be made naturally.

will be finished in late 2018, after which evaluation will start. Once thetechnology is established, a more intelligent pixel sensor, for example,
several pixel sensor layers that are unified, will be tested to reconstruct
tracks inside the pixel detector. The dense connections between chipscould lead to highly parallel data processing.

4. CAD design tools
To design the 3D integration ICs, there have been efforts to extend
the existing 2D CAD tools [5]. However, design rule check (DRC) andlayout versus schematic (LVS) are indispensable for verifying the design
geometrically and logically. For the design of the SOFIST4 chip, a new
method is developed [7]. When a user places micro-bump cells like vias,
several virtual layers are automatically generated in the upper and lowerchips. The virtual layers unify the two chips geometrically, as shownin Fig. 7(a). For LVS, the virtual layer forms circuit nodes between
the upper and lower circuits, and the combined circuit verification
becomes possible. To proceed with efficient verification, the upperand lower chips should be checked independently. Then the two chips
are combined with the virtual layers, and combined verification is beapplied, as shown in Fig. 7(b). Dummy bumps, which are necessary for
equalizing the stress on the wafer, are generated automatically.
To implement 3D DRC and LVS in the existing LSI CAD tool, only therule files were modified, and we did not have to develop special tools.
In this 3D extension, however, the capabilities of the combined parasitic
extractions [8] are still to be implemented.

References[1] R. Lipton, et al., 3D integration at Radiation Imaging Detectors, PoS (Vertex2014)045, http://dx.doi.org/10.22323/1.227.0045;
R. Lipton, 3D Integration of Sensors and Electronics, Vertex2017, 10-15 Sept. 2017,
Asturias, Spain.
[2] T. Behnke, et al., The International Linear Collider Technical Design Report, arXiv:
1306.6329, June 26, 2013.
[3] S. Ono, et al., Development of a pixel sensor with fine space–time resolution basedon SOI technology for the ILC vertex detector, Nucl. Instrum. Methods Phys. Res.,
Sect. A 845 (2017) 139–142;
M. Yamada, et al., Development of monolithic pixel detector with SOI technology
for the ILC vertex detector, J. Instrum. D13 (2018) C01037.
[4] Y. Arai, SOI Monolithic Pixel Detector Technology, PoS(Vertex 2016)029, http://dx.doi.org/10.22323/1.287.0029.
[5] C.T. Lin, D.M. Kwai, Y.F. Chou, T.S. Chen, W.C. Wu, CAD reference flow for 3D
via-last integrated circuits, in: Proceedings of the Asia and South Pacific DesignAutomation Conference, IEEE Press, 2010, pp. 187–192.
[6] M. Motoyoshi, et al., 3D Integration technology for sensor application using less than
5 𝜇𝑚-pitch gold cone-bump connection, J. Instrum. 10 (2015) C03004.
[7] M. Ikebe, I. Kurachi, Y. Arai, M. Motoyoshi, D. Kasai, https://kds.kek.jp/indico/event/24312/session/5/contribution/21/material/slides/0.pdf. Last visited 2018.
[8] Y. Peng, CAD Tools and Methodologies for Reliable 3D IC Design, Analysis, and Optimization (Dissertation), Georgia Institute of Technology, 2016, https://smartech.
gatech.edu/h{and}le/1853/56330, Last visited.

5. Summary and prospects
The SOFIST4 chip was submitted for an MPW run in June 2017.
The wafer will be delivered in February 2018, and the 3D integration

425