Total Ionization Damage Compensations in Double
Silicon-on-Insulator Pixel Sensors

A University of Tsukuba
B High Energy Accelerator Research Organization (KEK)C Kyoto University
D National Institute of Advanced Industrial Science and Technology (AIST)E Lapis Semiconductor Miyagi Co., Ltd.
F Lapis Semiconductor Co., Ltd.

E-mail: honda@hep.px.tsukuba.ac.jp
We are developing monolithic pixel sensors based on a 0.2 µ m fully-depleted Silicon-on-Insulator(SOI) technology. SOI sensors have properties such as high-speed operation, low-power dissipation, and SEU/SET immunity. The major issues applying them in high-radiation environments are
the total ionization dose (TID) effects. The effects are rather substantial in the SOI devices since
the transistors are enclosed in the oxide layers where generated holes are trapped and affect theoperation of the near-by transistors. Double SOI sensors that provide an independent electrode
underneath the buried oxide (BOX) layer have been developed. A negative voltage applied to thiselectrode is expected to cancel any positive potential due to hole traps in the BOX layer. We have
irradiated transistor test elements and pixel sensors with γ -rays. By adjusting the potential ofthis electrode, the TID effects are shown to be compensated. The transistors irradiated to 2 MGy
recovered their performances by applying a bias to the electrode. The transistors showed to havemodest differences in behaviors of TID compensations according to their types. The pixel sensor
irradiated to 100 kGy recovered its functionality by applying a bias to the electrode. The radiation
tolerance of the SOI devices has been substantially improved by employing the innovative double
SOI.

Technology and Instrumentation in Particle Physics 2014,
2-6 June, 2014
Amsterdam, the Netherlands∗ Speaker.

c Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike Licence.
⃝

http://pos.sissa.it/

PoS(TIPP2014)039

Shunsuke HONDA∗A , Kazuhiko HARAA , Kohei TSUCHIDAA , Mari ASANOA , Naoshi
TOBITAA , Tatsuya MAEDAA , Yasuo ARAIB , Toshinobu MIYOSHIB , Takeshi TSURUC ,Morifumi OHNOD , Noriyuki MIURAE , Hiroki KASAIE , Masao OKIHARAF

TID Compensations in Double SOI Pixel Sensors

Shunsuke HONDA

1. SOI Pixel Device

NMOS

2

PMOS

PoS(TIPP2014)039

The potential of novel monolithic pixel devices utilizing a 0.2 µ m fully depleted silicon-oninsulator (FD-SOI) technology has been intensively explored for various applications including
high-energy, space, γ /X-ray imaging, and other applications[1][2][3][4]. As the technology characteristics of our SOI pixel devices, we adapt "bonded"-wafers provided by SOITEC Co.[5] andutilize the commercial reliable process by Lapis Semiconductor[6]. SOI bonded wafers were fabricated from two silicon wafers with optimized resistivities. Separated by a 200 nm thick buriedoxide (BOX) layer, nominally the active layer is 40 nm thick silicon of 18 Ωcm used as the circuit
part, and the handle wafer is 50∼500 µ m thickness of 700∼25k Ωcm resistivity used as the sensing
part. Table 1 summarizes the main
Charged particle
characteristics of the Lapis FD-SOI
1 poly + 5 metal processprocess, and typical silicon types
and resistivities.
Fig. 1 shows schematically the
BOX(SiO
structure of an SOI pixel device.
2)
p+ p+
p+
n+
SensorGuard
Bias
Because this design does not reBPWElectrode
Ring Ring
quire mechanical bump bonds, ahigh Volt.
nｰ Sensor
Alhigh pixel density can be realized.
50~500um
Not needing the bump bonds is
expected to reduce the fabrication
cost substantially. The thickness
Figure 1: Schematics of SOI pixel device. Two silicon wafers
and resistivity of the sensing partare bonded interleaved with 200 nm thick buried oxide (BOX)can be optimized per application.
layer. The pixel electrodes are fabricated by implantation of p
Low-power and high-speed operaor n dopants after removing the top silicon and BOX layers. The
transistors are inter-connected via aluminum metal placed on top
tions are realized by FD-SOI, pro(five metal layers available). The detector bias is applied fromviding a large operation temperathe backplane, or from the front contact (bias ring). The BPW is
ture range from less than 1 K to
to isolate the back-gate effect to the front transistor circuits.
630 K.
We have identified three issues
to solve to utilize SOI devices inTable 1: Lapis FD-SOI process
high energy experiments. One isthe back-gate effect where the bias
Process
0.2 µ m low leakage fully-depleted SOI CMOS
voltage applied for sensor deple1poly+5metal layers, MIM(1.5 µ F/µ m2 ), DMOS
tion affects the operation of the SOICore(I/O) voltage = 1.8(3.3) V
SOI Wafer Diameter : 200 mmϕ
circuit. To shield the electric-field
Top Si : CZ (p ∼18 Ωcm), 40nm thickfrom the bias voltage, buried p-well
Buried oxide : 200 nm thickHandle wafer : CZ (n ∼0.7 kΩcm), FZ(n ∼7 kΩcm / p ∼25 kΩcm)(BPW) electrode for p-type sensor
Double-SOI available
nodes (buried n-well (BNW) for nBackside Mechanical grind(down to 200 µ m), chemical etching,type sensor nodes) has been develimplant, laser annealing, Al plating.
Further thinning to 50,100 µ m available.
oped. However, the BPW electrode increases the sensor capacitance, hence modifies the signal response shape. An alternative option is preferable.

TID Compensations in Double SOI Pixel Sensors

Shunsuke HONDA

2. Double-SOI Process
In order to solve these issues, we have developed double SOI wafers with SOITEC first in
2012. The double SOI wafer has two sets of low resistive silicon and BOX pair layers made by
SmartCut technology repeated twice. The second silicon layer (SOI2) interleaved with the BOX
layers is used as an individual electrode with controllable potential. A negative voltage applied to
the SOI2 compensates the effect of trapped hole charge, therefore it is expected the transistor characteristics to be recovered. Also the same layer should be effective to suppress the back-gate effectand the cross-talk.
The
double SOI wafer we evalNegative View
uated uses p-type CZ silicon (10∼18 Ωcm) for theН62,fЌFPZLWK&R6LfNЌVT
top-side active layer (SOI1)
 ZR&R6Lf0ЌVT
and 80 nm-thick SOI2 layer.
These two layers, SOI1 and
Gate
Top-SOISOI2, are interleaved with
BOX2
a BOX layer (BOX2), SOI2
BOX1
and the handle with another
SOI2 (2nd Si)
Sub
0.3um
150 nm-thick BOX layer(BOX1). Fig. 2 shows TEM
Figure 2: TEM image of the double-SOI wafer and across processed
images from the first suctransistor and pixel node.
ceeded double SOI process.
Si 46.7nm

SiO2 158.7nm

Si 84nm

SiO2 156.0nm

3. Tested Samples and Cobalt Irradiation
We evaluate the radiation damage and the compensation of TID with SOI2 using transistortest-element-group (TrTEG) chips, TrTEG6, and integration-type pixel sensors, INTPIXh2.
TrTEG6 contains 18 transistor types each for PMOS and NMOS, as listed in Table 2. The
core transistors (with oxide thickness tox =4 nm) are provided with low (LVT) and normal (NVT)
threshold types, and IO (tox =7 nm) with normal (NVT) and high (HVT) threshold types. Transistors
3

PoS(TIPP2014)039

The second issue is the cross-talk between sensor nodes and near-by SOI circuit, which istypical in devices with a thin BOX layer.
The third is that the radiation effect is relatively complicated. The total ionization dose (TID)
effect [7] is rather substantial. Each SOI transistor is fully enclosed in oxide layers. With theradiation, generated holes are trapped in BOX, and affect the operation of the SOI circuit; the transistor threshold shifts negatively [8][9][10]. Characteristics of the SOI transistor, e.g. the threshold,should be restorable by applying a negative voltage to the positively charged region. The developed
BPW is not suitable for this purpose because the potential configuration is limited with respect tothe near-by pixel node and backside potential. The BNW with n-type pixel nodes may be effective
provided that the sheet resistance is low enough. Although, the additional BPW/BNW electrodes
increase the sensor capacitance further more and tend to increase the coupling noise among thecircuits through this common electrode.

TID Compensations in Double SOI Pixel Sensors

Shunsuke HONDA

are tested for several gate lengths and widths, with body floating (BF) or three kinds of bodyconnections (two versions of body connected to source, S-TIE and S-TIE2, and one with voltage
applicable externally, MULTIB-TIE).

Table 2: Tested transistors. M is the number of transistors connected in series, giving the effective transistor width as W×M.

COMMENT
NVT_BF
NVT_BF
NVT_BF
LVT_BF
LVT_BF
LVT_BFIOHVT_BF
IOHVT_BF
LVT_S-TIE
LVT_S-TIE
LVT_S-TIE
NVT_S-TIE2
NVT_S-TIE2
NVT_S-TIE2
NVT_MULTIB-TIE
NVT_MULTIB-TIE
NVT_MULTIB-TIE
IONVT_S-TIE

VDD
STORExLOAD(sensor)
RST

M
4
10
20
4
10
20
7
7
4
10
20
4
10
20
4
10
20
20

STORE

+V
V_RST

VSS(GND)

Storage
capacitor
COL_OUT

W[µ m]
5
5
5
5
5
5
5
5
5
5
5
10
6
5
5
5
5
5

READ

L[µ m]
0.20
0.50
1.00
0.20
0.50
1.00
0.35
0.35
0.20
0.50
1.00
0.40
0.60
1.00
0.20
0.50
1.00
1.00

RSTx

No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Figure 3: INTPIXh2 on-pixel circuit

TrTEG chips and INTPIXh2 sensors were irradiated with 60 Co γ -rays at Takasaki Advanced
Radiation Research Institute, JAEA. The total dose ranged from 3 kGy up to 2 MGy for TrTEG6
chips, and up to 100 kGy for INTPIXh2 sensors. All samples were grounded and kept at room
temperature during the irradiation. The irradiation time was typically 20 h (up to ∼200 kGy for
TrTEG6, ∼20 kGy for INTPIXh2) or 200 h (∼2 MGy for TrTEG6, ∼100 kGy for INTPIXh2).
The samples were brought to University of Tsukuba in four hours at room temperature, then kept
at -20 ◦ C in the refrigerator except during the measurements.
4

PoS(TIPP2014)039

INTPIXh2, with pixel size of 18 µ m square, has an on-pixel circuit as shown in Fig. 3. The
pixel outputs in the same column are sent out one after the other to a 12-bit ADC located outside thechip. Since the irradiation was performed on a chip by chip basis, the functionality of the on-pixel
circuits together with a common on-chip peripheral circuit including output buffers and switching
logics was evaluated all together. The tested version has SOI2 layers to which only a single voltage
can be applied, therefore fine voltage tuning between e.g. PMOS and NMOS transistors was notpossible.

TID Compensations in Double SOI Pixel Sensors

Shunsuke HONDA

4. Transistor Performancevth : tr10 : pch_L0.50_W5_m20_colvst

vth[V]

vth[V]

vth : tr10 : nch_L0.50_W5_m20_colvst
1

1

0.5

0.5

0

0

-0.5

-0.5
-1

-1

dashed line: preirrad value

dashed line: preirrad value

-1.5

NMOS

-2
1

-1.5

䖃VSOI2= 0V 䖃VSOI2=-3V 䖃VSOI2=-10V 䖃VSOI2=-25V
䖃VSOI2=-1V 䖃VSOI2=-4V 䖃VSOI2=-15V 䖃VSOI2=-30V
䖃VSOI2=-2V 䖃VSOI2=-5V 䖃VSOI2=-20V 䖃VSOI2=-35V

10

102

-2
1

103

dose[kGy]䖃VSOI2= 0V 䖃VSOI2=-3V 䖃VSOI2=-10V 䖃VSOI2=-25V
䖃VSOI2=-1V 䖃VSOI2=-4V 䖃VSOI2=-15V 䖃VSOI2=-30V
䖃VSOI2=-2V 䖃VSOI2=-5V 䖃VSOI2=-20V 䖃VSOI2=-35V

PMOS

10

102

103

dose[kGy]

Figure 4: Threshold voltage shifts of typical (left) NMOS and (right) PMOS transistors as a function of thedose. The curves are shown for various VSOI2 settings. The dashed lines are the pre-irradiation values.

Optimum VSOI2 to compensate vth shift _ pch

Optim.VSOI2[V]Optim.VSOI2[V]Optimum VSOI2 to compensate vth shift _ nchbody ﬂoa ng

0
-10
body
connec ng

-20
-30
-40

‫؟ٴ‬BF_NVT‫؟ٴ‬BF_LVT‫؟ٴ‬S-TIE_LVT‫؟ٴ‬S-TIE2_NVT‫؟ٴ‬MULTIB-TIE_NVT

0
-10
-20
-30
-40

NMOS

PMOS

-50
1

‫؟ٴ‬BF_NVT‫؟ٴ‬BF_LVT‫؟ٴ‬S-TIE_LVT‫؟ٴ‬S-TIE2_NVT‫؟ٴ‬MULTIB-TIE_NVT

-50
10

102

103

dose[kGy]

1

10

102

103

dose[kGy]

Figure 5: The optimum VSOI2 voltages for various types of (left) NMOS and (right) PMOS core transistors.

Considering the operation of a pixel sensor, where various transistors are incorporated, weshould evaluate whether all transistors can be recovered equally with a same VSOI2 . Optimum
VSOI2 is defined as the VSOI2 per dose and per transistor type to recover the threshold to the preirradiation value measured at VSOI2 =0 V. Here, we evaluate the optimum VSOI2 dependence on thecore transistor types, since the dependence on the I/O transistors is relatively smaller than on thecore transistors [11]. As shown in Fig. 5, noticeable differences are observed between NMOS and
PMOS. Furthermore, there is a systematic difference observed among body connections notably in
NMOS. The BF NMOS transistors tend to "rebound" [12] more significantly than other types.
5

PoS(TIPP2014)039

The transistor characteristics were evaluated through ID -VG curves, which were measured at
VD = 1.8 V, VS = 0 V for NMOS, VD = 0 V, VS = 1.8 V for PMOS with VBPW grounded, VBACK
floating, and VB = VS for MULTIB-TIE types. The ID -VG curves shift negatively with increasing
dose due to trapped holes. Therefore NMOS transistors become always ON after a high enoughdose. We define the threshold voltage as VG at ID =100×W/L [nA]. Fig. 4 shows threshold shifts ofa typical transistor (TrTEG6 NO.10) as a function of the total dose. Also shown are the shifts withvarious VSOI2 settings. By applying VSOI2 properly, the threshold can be set to the pre-irradiation
value up to 2MGy.

0.5

Shunsuke HONDA

dVth=Vth-Vth(preirrad,VSOI2=0V) : nch

dVth[V]dVth[V]TID Compensations in Double SOI Pixel Sensors

0.4
0.3

0.4
0.3

0.2

0.2

0.1

0.1

0

0

-0.1

-0.1

-0.2
-0.3
-0.4
-0.5
1

NMOS

dVth=Vth-Vth(preirrad,VSOI2=0V) : pch

0.5

-0.2

‫؟ٴ‬BF_NVT‫؟ٴ‬BF_LVT‫؟ٴ‬S-TIE2_NVT

-0.3

PMOS

-0.4
10

102

103

10

102

103

dose[kGy]

Figure 6: Compensation of the threshold voltages as a function of the dose, where four average VSOI2 curves(see text) are used.

Separate VSOI2 settings may be required to fully compensate heavily irradiated transistors for
the TID. In order to demonstrate this, here we assume that four voltages are usable as VSOI2 for BF
and S-TIE2 for NMOS, and BF and S-TIE2 for PMOS. (INTPIXh2 uses mostly S-TIE2 and BF
transistors, and no S-TIE nor MULTIB-TIE.) Each VSOI2 dependence on the dose is the averageof optimum VSOI2 values in the same category. Fig. 6 shows the compensation of the thresholdvoltage under this assumption for all the transistors. The threshold voltages are compensated towithin ±0.05 V for NMOS and ±0.1 V for PMOS transistors. We notice that the wider variation
for the PMOS is due to larger variation of the threshold voltage against VSOI2 at higher doses.

5. Response of INTPIXh2 Pixel Detector
The functionality of the pixel electronic,
shown in Fig. 7, was examined by measuring
the response to reset voltages RSTV (see Fig. 3).
After 100 kGy irradiation, the output exceeds the
ADC full range at VSOI2 =0 V for any RSTV.
By applying a VSOI2 , the RSTV response is
obtained. As the VSOI2 increased, the linear
response range becomes wider. The dynamic
range is not fully recovered at VSOI2 = −10 V.
This is explained that a single VSOI2 is employedin the present design. At VSOI2 = −10 V, thethreshold voltages of some transistors (mainly
PMOS) are not fully compensated at 100 kGy,
see Fig. 5. Since multiple and various transistors
are involved in the circuit, the response curve is
not completely back to the original one. Since
the functionality as a pixel device is recovered,
VSOI2 settings dependent on the transistor typeshould recover the functionality further.

Charge[ADCcount]$'&>$'8@5679&=

4500
4000
3500
3000
2500
2000
1500
1000
500
0
0

preirradVSOI2=-2.0v
VSOI2=-3.0v
VSOI2=-4.0v
VSOI2=-5.0v
VSOI2=-6.0v
VSOI2=-7.0v
VSOI2=-8.0v
VSOI2=-9.0v
VSOI2=-10.0v
VSOI2=-11.0v

200 400 600 800 1000 1200 1400
RST_V[mV]Figure 7: INTPIXh2 RSTV curves for preirradiation and after 100 kGy. For 100 kGy sample, the curves are taken with various VSOI2 values.

6

PoS(TIPP2014)039

dose[kGy]-0.5
1‫؟ٴ‬BF_NVT‫؟ٴ‬BF_LVT‫؟ٴ‬S-TIE2_NVT

TID Compensations in Double SOI Pixel Sensors

VSOI2=0.0V
500

200

188
186

CZ09(IR light) VSOI2=-10.0V
600

VSOI2=0.0V
500

184

Row Adr202

CZ09_0.0v_IR light_10
600

204

Row AdrRow Adr

CZ05_IR light_100

Shunsuke HONDA

188
186

600

VSOI2=-10.0V
500

184

198
400

196

182

400

180
194

300

192

300

178

200
174

188
100

300

178
176

200

186

400

180

176
190

182

200
174

172

100

170

172

100

170

184
166 168 170 172 174 176 178 180 182 184 186
Column Adr

pre-irrad sample

0

168
198 200 202 204 206 208 210 212 214 216 218
Column Adr

100kGy sample

0

168
198 200 202 204 206 208 210 212 214 216 218
Column Adr

0100kGy sample

Charge[ADCcount]&KDUJH>$'8@

After confirming the functionality of theelectronics part, we measured the pixel response7000
to an infrared (IR) laser pulse of 1064 nm wave6000
length and 10 ns pulse duration. The responseof the sample irradiated up to 100 kGy is satu5000
rated at VSOI2 = 0 V and the image could not4000
be obtained. By applying VSOI2 = −10 V, theimage is recovered, as shown in the Fig. 8. To
3000
evaluate the response quantitatively, we plot theVRST(pre-irrad:w/ SOI2)=0.55V
2000
VRST(pre-irrad:w/oSOI2)=0.45V
VRST(100kGy:w/ SOI2)=0.95V
average ADC output as a function of the square
VSOI2(pre-irrad)=0V
VSOI2(100kGy)=-10.0v
1000
root of the sensor bias. A linear response is obINT_T=120ns
tained from the pre-irradiation sample, as shown0
0 2 4 6 8 10 12 14 16 18 20
in Fig. 9. The sample irradiated to 100 kGy
Bias voltage [ V]showed a similar linearity at VSOI2 = −10 V.
Figure 9: INTPIXh2 response to IR laser as a
Also plotted in the figure is the linearity meafunction of the bias voltage, for double SOI pixels
sured for a non-irradiated single SOI pixel debefore and after 100 kGy irradiation, and single
vice. The difference is understood as a larger
SOI pixel at pre-irradiation.
detector capacitance in the double SOI devices,which leads to a slightly degraded sensitivity compared to the single SOI device.
8000

䖃䠖pre-irrad w/ SOI2=0V
䖃䠖100kGy irradiated w/ SOI2 , VSOI2=-10V
䖃䠖pre-irrad w/o SOI2

6. Summary
We have evaluated the TID effects in the newly developed double SOI devices, demonstratingthat the TID effects in the SOI transistors can be mostly compensated for by VSOI2 adjustmentin the dose range up to 2 MGy. The optimum VSOI2 is found to show some modest differencesamong the samples, NMOS and PMOS, source-tied and body floating. Some separate values of
SOI2 voltages can be optimized further to compensate for the TID effects.A design based on theobtained information is the next step to minimize the TID effects in larger dose range.
The pixel devices irradiated up to 100 kGy showed substantial recovery in response, although
periodical calibration and VSOI2 tuning depending on transistor type are required to maintain the
7

PoS(TIPP2014)039

Figure 8: INTPIXh2 response to IR laser. (left) pre-irradiation, (center) after 100 kGy with VSOI2 = 0 V,
and (right) after 100 kGy with VSOI2 = −10 V.

TID Compensations in Double SOI Pixel Sensors

Shunsuke HONDA

References[1] T. Miyoshi et al., Monolithic pixel detectors fabricated with single and double SOI wafers, presented
at this talk, PoS(TIPP2014)044; K. Hara et al., Development of FD-SOI Monolithic Pixel Devices forHigh-Energy Charged Particle Detection, NSS/MIC 2011 IEEE, p. 1045.
[2] S. Nakashima et al., Development and characterization of the latest X-ray SOI pixel sensor for a
future astronomical mission, Nuclear Instruments and Methods in Physics Research A 731 (2013), p.
74; A. Takeda et al.,Development and Evaluation of Event-Driven SOI Pixel Detector for X-ray
Astronomy, presented at this symposium, PoS(TIPP2014)138[3] T. Hatsui et al., Line-Spread Function and Noise Spectrum Analysis of a Direct-Detection X-Ray
CMOS Image Sensor with 500 um Thick High Resistivity Silicon, NSS/MIC 2013 IEEE, M14-4; S.
Ono et al., Noise Analysis of a Silicon-on-Insulator (SOI) Pixel Sensor with 500 um Thick HighResistivity Silicon for X-Ray Free-Electron Laser Experiments, NSS/MIC 2013 IEEE, NPO1-11.
[4] D. Nio et al., Investigation of Geiger-Mode APD Using SOI Technology, NSS/MIC 2013 IEEE,
NPO1-86; Y. Sekiguchi et al., Basic Performance of SOI Pixel Detectors for Radiation Monitor,
NSS/MIC 2013 IEEE, NPO1-184.
[5] SOITEC: http://www.soitec.com/en/technologies/smart-cut/[6] Lapis Semiconductor Co., Ltd.: http://www.lapis-semi.com/en/.
[7] J. R. Schwank, M. R Shaneyfelt, D. M. Fleetwood, J. A. Felix, P. E. Dodd, P. Paillet, and V.
Ferlet-Cavrois, Radiation Effects in MOS Oxides, IEEE Trans. Nucl. Sci., vol. 55-4, p. 1833, 2008.
[8] K. Hara et al., Radiation Resistance of SOI Pixel Devices fabricated with OKI 0.15um FD-SOI
Technology. IEEE IEEE Trans. Nucl. Sci., vol. 56-5, p. 2896, 2009.
[9] K. Hara et al., "Development of INTPIX and CNTPIX Silicon-On-Insulator Monolithic Pixel
Devices", PoS (Vertex2010) 033.
[10] M. Kochiyama et al., Radiation effects in silicon-on-insulator transistors with back-gate control
method fabricated with OKI Semiconductor 0.20 um FD-SOI technology, Nucl. Instr Meth A636
(2011) S62.
[11] S. Honda, K. Hara et al.,Total Ionization Damage Effects in Double Silicon-on-Insulator Devices,
NSS/MIC 2013 IEEE, N41-2.
[12] J. R. Schwank, P. S. Winokur, P. J. McWhorter, F. W. Sexton, P. V. Dressendorfer, and D. C. Turpin,
Physical mechanisms contributing to device Rebound, IEEE Trans. Nucl. Sci., vol. NS-31, p. 1434,
1984.

8

PoS(TIPP2014)039

original performance.
Further studies are now in progress to evaluate the compensation in the actual pixel readout
read out chain. Other SOI2 issues, back-gate effect and cross-talk suppressions, are being evaluated.
In summary, the radiation tolerance has been enhanced substantially by employing the innovative double SOI. The observed differences of compensation among diffferent transistor-types areto be taken into account to design radiation tolerant devices operational in dose range exceeding
100kGy. The present study reported in this paper encourages us to work toward the realization of
double SOI pixel detectors to be operational in future collider experiments.