Transforming an SSD into a Cost-EffectiveEdge Server
Neil Werdmuller
Director Storage Solutions
ArmFlash Memory Summit 2018
Santa Clara, CA1

Who am I?
••••••

28 years’ experience in embedded
Lead the storage solutions teamWork closely with the industry’s top storage suppliers
Previously in wireless at Texas Instruments
BSc in Computer Science from Portsmouth University (UK)I enjoy brewing beer at home!

Flash Memory Summit 2018
Santa Clara, CA2

What will we cover today?
••••

Why compute is moving to the edge
Design structure of servers and SSD storage
Why run an SSD as an edge server?
Ecosystem support available

Flash Memory Summit 2018
Santa Clara, CA

3

Arm computing is everywhere#1shipping
processor instorage
devices

21Bn

Arm-basedchips shippedin 2017
Flash Memory Summit 2018
Santa Clara, CA> 5Bn

people using
Arm-based
mobilephones

120Bn

Arm-basedchips to dateWhy computation is moving to the edge

BandwidthFlash Memory Summit 2018
Santa Clara, CA

Power

Cost

Latency

Reliability

Security5

Edge server

Basic Server:
DRAM•

Arm Cortex-A series or Intel x86

Memory:•DRAM

Storage:•SSD/HDD

Network Interface

Compute:CPU(s)

PCIeInterfaces:•

Ethernet + PCIe/SATA…

Flash Memory Summit 2018
Santa Clara, CAStorage

6

SSD storage

Basic Server:
DRAM

Compute:Arm Cortex-R series or Cortex-A series

Memory:•DRAM ~1GB for each 1TB of flash

PCIe•

CPU(s)

Storage:•Today 256GB to 64TB… flash storage

Interfaces:•PCIe/SATA/SAS…

Flash Memory Summit 2018
Santa Clara, CA

Flash

7

Classic Edge Server:

Edge SSD•

Arm-based systemon-chip (SoC)

Memory:•Shared DRAM

Storage:
•DRAM

Vs.

Ethernet…

Flash Memory Summit 2018
Santa Clara, CACPU(s)PCIeCPU(s)PCIeShared FlashInterface•Basic Server:

Network Interface

Compute:Network Interface

DRAM

CPU(s)

FlashFlashDRAM

8SSD controllers
SSD SoC Functionality:

Compute:Flash Memory Summit 2018
Santa Clara, CA

Memory Control

NAND FlashNAND Flash

Memory Control

NAND Flash

Host / Flash
Address Translation

CLE
ALE
CE
RE
WE
WP
R/B
IDin
IDout

Memory Control

Block Management
Wear Levelling, Bad
Block mapping...

BackendProcessor

CLE
ALE
CE
RE
WE
WP
R/B
IDin
IDout

CLE
ALE
CE
RE
WE
WP
R/B
IDin
IDout

NAND FlashFlash System
Management

CLE
ALE
CE
RE
WE
WP
R/B
IDin
IDout

Memory Control

Cache / Buffer
Management

Garbage collection,
ECC/LDPC ErrorCorrection/Detection,
Read Scrubbing...

Flash Translation Layer

Garbage collection,
ECC/LDPC Error
Correction/Detection,
Read Scrubbing...

DRAM typically >1GB for each 1TB of flash

PCIe/SATA/SASBackend
Processor

Flash Processor Control•

Host Control
MVMe
Command Queues

Memory:Frontend Processor(s)Host Control•

DRAM
Cache + FTL Tables

Encryption•

Frontend: Host I/F + Flash Translation Layer• Typically Cortex-R or Cortex-A series
Backend: Flash management• Typically Cortex-R or Cortex-M series
Custom accelerators: encryption, LDPC,…

Compression•9Adding HLOS for an Edge SSD server
Cortex-A series apps processor running:Flash Memory Summit 2018
Santa Clara, CAApplications
Processor

DRAM

PCIe Internal Interface• Single PCB and product housing• Apps processor(s) added in to a SSD• Ethernet network interface• Internal interface to SSD controller SoC• PCIe or could be enhanced by chip-to-chip interface

NV Memory
PCIe Internal Interface

Edge SSD server:

Apps processor + SSD:

Network Interface• High-level OS such as Linux• Networking protocols: Ethernet, TCP/IP, RDMA…
• Open source applications and workloads• Standard administration functions

DRAM

FrontendControllerProcessor

BackendProcessor

NVMemory

BackendProcessor

NVMemory

BackendProcessor

NVMemory10Single SoC for cost/latency reduction• Lower latency by removing internal (PCIe) interface• Separation of apps processor and the SSD processing• Shared DRAM and other SoC resources
Combined into frontend/apps processor• Hypervisor provides SSD frontend separation from Linux• Lowest cost and tightest integration• Lowest possible latency• Highest internal bandwidthFlash Memory Summit 2018
Santa Clara, CA

Applications
Processor

DRAM

PCIe Internal Interface

PCIe Internal Interface

Network Interface

NV Memory

DRAMFrontend
Controller
Processor

Applications
Processor
Frontend
Controller
Processor

DRAM

Combined
Applications
andFrontend
Processor

BackendProcessor

NV
MemoryBackendProcessor

NV
MemoryBackendProcessor

NV
MemoryBackendProcessor

DRAM
Network Interface

Separate Cortex-A series processor• Enables any SSD (or HDD) to run Linux• Wide performance range from Cortex-A5 to Cortex-A76

SSD Apps Processor Integration:

Network Interface

Optimizations

BackendProcessor

NV
MemoryBackendProcessor

NV
MemoryBackendProcessor

NV
MemoryNV
MemoryBackendProcessor

NV
MemoryBackendProcessor

NV
Memory11

Why a SSD for an Edge server? (1 of 3)
An SSD SoC has flexible compute

Edge SSD Server:• And an Edge server requires storage anywayRobust• Core SSD functionality unmodified• SSDs can include power loss protection

Flash Memory Summit 2018
Santa Clara, CA

Network Interface• Adding ‘additional’ compute in SoC inexpensive• More, or larger, cores or additional clusters• Custom acceleration easily integrated: ML, FPGA…
• Single DRAM reduces requirements

Combined
Applications
andFrontend
Processor

NV
MemoryBackendProcessor

NV
MemoryFrontend
Controller
Processor

BackendProcessor

NV
MemoryBackendProcessor

NVMemory

BackendProcessor

NV
MemoryBackendProcessor

NV
MemoryApplications
Processor

DRAM
Network Interface

Lowest cost

BackendProcessor

DRAM12Why a SSD for an Edge server? (2 of 3)• Shared single DRAM
• Minimal data copying and movement• Less protocol processing

High bandwidths

Edge SSD Server:• Ethernet to high bandwidth internal buses• Parallelism of wide backend processing

Lowest latencies• No internal cross interface latencies• In-storage compute or inference all in DRAM

Flash Memory Summit 2018
Santa Clara, CA

Combined
Applications
andFrontend
Processor

NV
MemoryBackendProcessor

NV
MemoryFrontend
Controller
Processor

BackendProcessor

NVMemoryBackend
Processor

NVMemory

BackendProcessor

NVMemory

BackendProcessor

NVMemory

Applications
Processor

DRAM
Network Interface• Removes bottleneck of PCIe lanes

BackendProcessor

DRAM
Network Interface

Lowest power

13

Why a SSD for an Edge server? (3 of 3)
Flexibility• One SoC that is suitable for:• Edge SSD, NVMe-oF, In-storage compute,…
• Arm NEON and Compute Library for ML…
• Potential for additional Arm or 3rd party ML

Security• TrustZone isolates Linux and SSD functionality• Processing of data is all done on the drive• Decrypted data remains on the drive
Flash Memory Summit 2018
Santa Clara, CA

BackendProcessor

DRAM
Network Interface• Single low power core to multiple clusters of highperformance cores

Edge SSD Server:

Combined
Applications
andFrontend
Processor

NV
MemoryBackendProcessor

NV
MemoryFrontend
Controller
Processor

BackendProcessor

NV
MemoryBackendProcessor

NV
MemoryBackendProcessor

NV
MemoryBackendProcessor

NV
MemoryApplications
Processor

DRAM
Network Interface

Scalability of compute and storage

14

Linux ecosystem on Arm

www.linaro.org

Flash Memory Summit 2018
Santa Clara, CA15

A few ‘Works on Arm’ partners

www.worksonarm.com

Flash Memory Summit 2018
Santa Clara, CA

16

Conclusions for Edge SSD• Edge SSD is an evolution not a revolution• Edge SSD delivers with low-cost, low-power and lowest-latency• High-performance, high-bandwidth and highly flexible• Edge SSD and In-storage compute opens up many possibilities• This presentation will be made available in FMS proceedings• Please come to my second talk on Thursday at 8:30am for more information…
• COMP-301-1: “Bringing Intelligence to Enterprise Storage Drives”

Flash Memory Summit 2018
Santa Clara, CA17

To learn more...
For more information, visit storage.arm.com.

neil.werdmuller@arm.com
linkedin.com/nwerdmuller

Flash Memory Summit 2018
Santa Clara, CA18

Thank You!
Danke!
Merci!
!
!
Gracias!
Kiitos!
감사합니다ध"यवाद
19

Confidential © 2018 Arm Limited

The Arm trademarks featured in this presentation are registered trademarks ortrademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All
rights reserved. All other marks featured may be trademarks of their respective
owners.
www.arm.com/company/policies/trademarks20© 2018 Arm Limited

Flash Memory Summit 2018
Santa Clara, CA