Diagonal 4.60 mm (Type 1/4.0) 8 Mega-Pixel CMOS Image Sensor with Square Pixel for
Color Cameras

IMX219PQH5-C
Description
The IMX219PQH5-C is a diagonal 4.60 mm (Type 1/4.0) CMOS active pixel type image sensor with a square pixel
array and 8.08M effective pixels. This chip operates with three power supplies, analogue 2.8 V, digital 1.2 V, and IF
1.8 V, and has low power consumption. High sensitivity, low dark current, and no smear are achieved through the
adoption of R, G, and B primary color pigment mosaic filters. This chip features an electronic shutter with variablecharge-storage time.
In addition, this product is designed for use in cellular phone and tablet pc. When using this for another application,
Sony does not guarantee the quality and reliability of product. Therefore, don't use this for applications other thancellular phone and tablet pc. Consult your Sony sales representative if you have any questions.

Features◆ Back-illuminated CMOS image sensor Exmor RTM◆ 2-wire serial communication circuit on chip
◆ CSI2 serial data output (selection of 4lane/2lane)◆ Timing generator, H and V driver circuits on chip
◆ CDS/PGA on chip
◆ 10-bit A/D converter on chip
◆ Automatic optical black (OB) clamp circuit on chip
◆ PLL on chip (rectangular wave)◆ High sensitivity, low dark current, no smear◆ Excellent anti-blooming characteristics◆ Variable-speed shutter function (1 H units)◆ R, G, B primary color pigment mosaic filters on chip
◆ Max. 30 frame/s in all-pixel scan mode
◆ Pixel rate: 280 [Mpixel/s] (All-pixels mode)◆ 180 frame/s @720p with 2x2 analog (special) binning, 60 frame/s @1080p with V-crop◆ Data rate: Max. 755 Mbps/lane(@4lane), 912Mbps/Lane(@2lane)* Exmor R is a trademark of Sony Corporation. The Exmor R is a Sony's CMOS image sensor with significantly enhanced imaging
characteristics including sensitivity and low noise by changing fundamental structure of ExmorTM pixel adopted column parallel A/D converter
to back-illuminated type.
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility forany problems arising out of the use of these circuits.

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IMX219PQH5-C

Device Structure◆ CMOS image sensor◆ Image size

: Diagonal 4.60 mm (Type 1/4.0)◆ Total number of pixels◆ Number of effective pixels◆ Number of active pixels◆ Chip size
◆ Unit cell size
◆ Substrate material: 3296 (H) × 2512 (V) approx. 8.28 M pixels: 3296 (H) × 2480 (V) approx. 8.17 M pixels: 3280 (H) × 2464 (V) approx. 8.08 M pixels: 5.095 mm (H) × 4.930 mm (V) (w/ Scribe): 1.12 µm (H) × 1.12 µm (V): Silicon2

IMX219PQH5-C

USE RESTRICTION NOTICEThis USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using theimage sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may,at any time, modify this Notice which will be available to you in the latest specifications book for the
Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its
own use restriction notice on the Products, such a use restriction notice will additionally apply between
you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or
distributor of Sony on such a use restriction notice when you consider using the Products.
Use Restrictions
 The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance withthe terms and conditions set forth in this specifications book and otherwise notified by Sony from time
to time.
 You should not use the Products for critical applications which may pose a life- or injury- threatening
risk or are highly likely to cause significant property damage in the event of failure of the Products. You
should consult your sales representative beforehand when you consider using the Products for such
critical applications. In addition, you should not use the Products in weapon or military equipment.
 Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and militaryequipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
 Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient careto ensure the safe design of your products such as component redundancy, anti-conflagration features,and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire orother social damage as a result of such failure.
Export Control
 If the Products are controlled items under the export control laws or regulations of various countries,
approval may be required for the export of the Products under the said laws or regulations.
You should be responsible for compliance with the said laws or regulations.
No License Implied The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise.
Sony will not assume responsibility for any problems in connection with your use of such information or
for any infringement of third-party rights due to the same. It is therefore your sole legal and financial
responsibility to resolve any such problems and infringement.
Governing Law
 This Notice shall be governed by and construed in accordance with the laws of Japan, without reference
to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating
to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as thecourt of first instance.
Other Applicable Terms and Conditions
 The terms and conditions in the Sony additional specifications, which will be made available to you when
you order the Products, shall also be applicable to your use of the Products as well as to thisspecifications book. You should review those terms and conditions when you consider purchasing
and/or using the Products.

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IMX219PQH5-C

Contents
Description...................................................................................................................................................... 1
Features ......................................................................................................................................................... 1
Device Structure ............................................................................................................................................. 2
USE RESTRICTION NOTICE ......................................................................................................................... 3
1.

Block Diagram and Pin Configuration...................................................................................................... 10
1-1 Block Diagram ................................................................................................................................... 10
1-2 Pin Description .................................................................................................................................. 10
1-3 Pin Equivalent Circuit ........................................................................................................................ 13
1-4 Chip Center, Optical Center and Pin Assignment ............................................................................... 14
1-5 Pin Coordinates................................................................................................................................. 15

2.

Pixel Signal Output Specifications........................................................................................................... 16
2-1 CSI-2 Signalling Mode....................................................................................................................... 16
2-1-1 MIPI Transmitter.......................................................................................................................... 16
2-1-2 Output Lane ................................................................................................................................ 16

3.

Control Registers .................................................................................................................................... 17
3-1 2-wire Serial Communication Operation Specifications ...................................................................... 17
3-1-1 Communication Protocol ............................................................................................................. 17
3-1-2 2-wire serial communication read/write operation supported ........................................................ 19
3-1-3 2-wire serial communication block characteristics ........................................................................ 23
3-1-4 2-wire serial communication register map .................................................................................... 24
3-1-5 Register Synchronization (Frame Bank) ...................................................................................... 25
3-2 2-wire Serial Communication Register Map(Configuration register, Parameter limit register) ..... 26

3-2-1 Configuration Registers – [0x0000-0x0FFF] ................................................................................ 26
3-2-2 Set-up Registers – [0x0100-0x0147] ........................................................................................... 28
3-2-3 Frame Bank Control and Group “A” – [0x0150-0x018D] ............................................................... 30
3-2-4 Frame Bank Control Group “B” – [0x0254-0x028D] ..................................................................... 32
3-2-5 Set-up Registers – [0x0300-0x0627] ........................................................................................... 33
3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static) ............................................... 36
3-3-1 Integration Time and Gain Parameter Limit Registers – [0x1000-0x1301] .................................... 36
3-4 Manufacturer Specific Registers – [0x3000-0x5FFF] .......................................................................... 41
3-5 Frame Bank A and Bank B specific output samples ........................................................................... 43
4.

Output Data Format ................................................................................................................................ 47
4-1 CSI-2 Output Data Format ................................................................................................................. 47
4-1-1 CSI-2 Output Data Channels ....................................................................................................... 47
4-1-2 CSI-2 Frame Structure ................................................................................................................ 47
4-1-3 Short Packet & Long Packet........................................................................................................ 48
4-1-4 Data type .................................................................................................................................... 49

4

IMX219PQH5-C

4-1-5 CSI-2 Frame Format ................................................................................................................... 49
4-1-6 CSI-2 Embedded Data Line......................................................................................................... 50
5-1 Pixel Array Physical Image ................................................................................................................ 52
5-2 Pixel Binning Mode ........................................................................................................................... 53
5-3 image size......................................................................................................................................... 54
5-4 Readout Position ............................................................................................................................... 55
5-5 Frame Rate Calculation Formula ....................................................................................................... 56
5-6 Black Level Control ........................................................................................................................... 56
5-7 Storage Time (Electronic Shutter) Settings ........................................................................................ 56
5-7-1 Storage Time (Electronic Shutter) Setting Registers .................................................................... 56
5-7-2 Storage Time Calculation Method................................................................................................ 57
5-8 Gain Settings .................................................................................................................................... 58
5-8-1 Analogue Gain Settings............................................................................................................... 58
5-8-2 Digital gain settings ..................................................................................................................... 60
6.

On Chip Image Processing ..................................................................................................................... 62
6-1 Test Pattern Generator ...................................................................................................................... 62
6-1-1 Test Pattern ................................................................................................................................ 62
6-2 Digital Gain Setting............................................................................................................................ 67
6-3 Black Level Adjust ............................................................................................................................. 67
6-4 Defect Correction .............................................................................................................................. 67
6-5 Pixel Re-alignment H Direction .......................................................................................................... 67
6-6 Pixel Re-alignment V Direction .......................................................................................................... 687.

NVM Memory Map.................................................................................................................................. 69
7-1 Block Diagram ................................................................................................................................... 69
7-2 NVM Functions ................................................................................................................................. 69
7-3 Related Registers.............................................................................................................................. 70
7-4 NVM Memory Map ............................................................................................................................ 72
7-5 Defects Address registration .............................................................................................................. 75
7-5-1 Single defect address .................................................................................................................. 75
7-5-2 Same Color Adjoining defect address .......................................................................................... 75
7-5-3 2x4 defect address ...................................................................................................................... 75
7-5-4 Example Setting .......................................................................................................................... 76

8.

How to operate IMX219PQH5-C ............................................................................................................. 77
8-1 Power on sequence ............................................................................................................................. 77
8-2 Power off sequence ............................................................................................................................. 79

9.

Other Functions ...................................................................................................................................... 81
9-1 Clock System .................................................................................................................................... 81
9-1-1 Clock Structure ........................................................................................................................... 81
9-1-2 EXCK_FREQ setting depend on INCK frequency ........................................................................ 81

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IMX219PQH5-C

9-2 Clock Setting Example ...................................................................................................................... 82
9-3 Temperature Sensor .......................................................................................................................... 83
10.

Electrical Characteristics....................................................................................................................... 84

10-1 Absolute Maximum Ratings ............................................................................................................. 84
10-2 Recommended Operating Conditions .............................................................................................. 84
10-3 Electrical Characteristics ................................................................................................................. 85
10-4 AC Characteristics........................................................................................................................... 86
10-4-1 Master Clock Waveform Diagram .............................................................................................. 86
10-5 Electrical Characteristics ................................................................................................................. 86
11.

Spectral Sensitivity Characteristic ......................................................................................................... 87

12.

Image Sensor Characteristics ............................................................................................................... 88

12-1 Image Sensor Characteristics .......................................................................................................... 88
12-2 Zone Definition used for specifying image sensor characteristics ..................................................... 88
13.

Measurement Method for Image Sensor Characteristics ....................................................................... 89

13-1 Measurement conditions ................................................................................................................. 89
13-2 Color Coding of This Image Sensor and Readout ............................................................................ 89
13-3 Definition of Standard Imaging Conditions ....................................................................................... 89
13-4 Measurement method...................................................................................................................... 90
14.

Spot Pixel Specification ........................................................................................................................ 91

15.

Notice on White Pixels Specifications ................................................................................................... 92

15-1 Measurement Method for Spot Pixels .............................................................................................. 93
15-2 Spot Pixel Pattern Specifications ..................................................................................................... 93
16.

Chief Ray Angle Characteristics............................................................................................................ 94

17.

Connection Example............................................................................................................................. 95

18.

Notes On Handling ............................................................................................................................... 96

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IMX219PQH5-C

Table of Figures
Fig. 1 Block Diagram .............................................................................................................................. 10
Fig. 2 Pin Equivalent Circuit .................................................................................................................... 13
Fig. 3 Chip Center and Optical Center..................................................................................................... 14
Fig. 4 Relationship between Output pin name and MIPI output Lane ....................................................... 16
Fig. 5 2-wire Serial Communication......................................................................................................... 17
Fig. 6 2-wire Serial Communication Protocol ........................................................................................... 17
Fig. 7 Start Condition .............................................................................................................................. 18
Fig. 8 Repeated Start Condition .............................................................................................................. 18
Fig. 9 Stop Condition .............................................................................................................................. 18
Fig. 10 Slave Address ............................................................................................................................. 18
Fig. 11 Acknowledge and Negative Acknowledge .................................................................................... 19
Fig. 12 CCI single read from random location.......................................................................................... 20
Fig. 13 CCI single read from current location........................................................................................... 20
Fig. 14 CCI sequential read starting from random location ...................................................................... 21
Fig. 15 CCI sequential read starting from current location ....................................................................... 21
Fig. 16 CCI single write to random location ............................................................................................. 22
Fig. 17 CCI sequential write starting from random location ...................................................................... 22
Fig. 18 2-wire Serial Communication Specifications ................................................................................ 23
Fig. 19 Function Example for Frame Bank .............................................................................................. 25
Fig. 20 Frame Structure for Serial signal output ...................................................................................... 47
Fig. 21 Signaling Waveform during Line Blanking Period (CSI-2)............................................................. 48
Fig. 22 Signaling Waveform during Frame Blanking Period (CSI-2) ......................................................... 48
Fig. 23 Short Packet & Long Packet........................................................................................................ 48
Fig. 24 Frame Format during Embedded Data Line Output ..................................................................... 50
Fig. 25 Embedded data lines alignment in RAW8 mode .......................................................................... 50
Fig. 26 Detailed Embedded Data Line Output in RAW10 Output Mode .................................................... 50
Fig. 27 Pixel Array Physical Image .......................................................................................................... 52
Fig. 28 Image of 2x2 averaged Binning Mode ......................................................................................... 53
Fig. 29 Image size .................................................................................................................................. 54
Fig. 30 Readout Position......................................................................................................................... 55
Fig. 31 Output Image Diagrams for Vertical Flip and Horizontal Mirror..................................................... 55
Fig. 32 Data Flow Diagram ..................................................................................................................... 62
Fig. 33 Block Diagram ............................................................................................................................ 69
Fig. 34 NVM Map structure ..................................................................................................................... 69
Fig. 35 Single defect ............................................................................................................................... 75
Fig. 36 Same Color Adjoining defect ....................................................................................................... 75
Fig. 37 2x4 defect ................................................................................................................................... 75
Fig. 38 Power-on Sequence in 2-wire Serial Communication Mode ......................................................... 77

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IMX219PQH5-C

Fig. 39 Start streaming sequence with 2-wire serial communication (external reset) ................................ 78
Fig. 40 Power-off Sequence in 2-wire Serial Communication................................................................... 79
Fig. 41 Software Standby Operation Pattern 1 ........................................................................................ 80
Fig. 42 Software Standby Operation Pattern 2 ........................................................................................ 80
Fig. 43 Clock System Block Diagram ...................................................................................................... 81
Fig. 44 Master Clock Square Waveform Diagram .................................................................................... 86
Fig. 45 Spectral sensitivity characteristics ............................................................................................... 87
Fig. 46 Zone Definition Diagram .............................................................................................................. 88
Fig. 47 Color coding alignment................................................................................................................ 89
Fig. 48 Measurement Method for Spot Pixels .......................................................................................... 93
Fig. 49 Chief Ray Angle Characteristics .................................................................................................. 94
Fig. 50 Recommended Circuit ................................................................................................................. 95

TablesTable 1 Pin Description ........................................................................................................................... 10
Table 2 Pin Coordinates .......................................................................................................................... 15
Table 3 Description of 2-wire Serial Communication Pins ........................................................................ 17
Table 4 R/W Bit ....................................................................................................................................... 18
Table 5 2-wire Serial Communication Address Space.............................................................................. 19
Table 6 Operations Supported by 2-wire Serial Communication .............................................................. 19
Table 7 2-wire Serial Communication Operation Specifications ............................................................... 23
Table 8 2-wire Serial Communication AC Timing (Fast mode plus (INCK[fSCK] = 11.4 to 27 MHz)) ......... 23
Table 9 2-wire Serial Communication AC Timing (Fast mode).................................................................. 24
Table 10 2-wire Serial Communication Register Map Address Areas ....................................................... 24
Table 11 Access command sequence...................................................................................................... 41
Table 12 Number of CSI lane Setting Registers ....................................................................................... 47
Table 13 Image pixel area and data type ................................................................................................. 49
Table 14 Sync Code Settings .................................................................................................................. 49
Table 15 Embedded Data Line Tag ......................................................................................................... 51
Table 16 Mode example .......................................................................................................................... 53
Table 17 Image Orientation Register ....................................................................................................... 55
Table 18 Gain Setting Variables .............................................................................................................. 56
Table 19 Storage Time Setting Register .................................................................................................. 56
Table 20 Storage Time Offset Register.................................................................................................... 56
Table 21 Storage Time Setting (in case of Line_Length_pck = 3448) ....................................................... 57
Table 22 Gain Setting Variables .............................................................................................................. 58
Table 23 Analogue Gain Setting .............................................................................................................. 59
Table 24 Digital Gain Settings ................................................................................................................. 60
Table 25 Example of Digital Gain Setting ................................................................................................ 61

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IMX219PQH5-C

Table 26 Description of Test Pattern Registers ........................................................................................ 63
Table 27 Description of Test Patterns ...................................................................................................... 64
Table 28 Black Level Adjust Setting Register ........................................................................................... 67
Table 29 Pixel Re-alignment H Direction Setting Registers ...................................................................... 67
Table 30 Pixel Re-alignment V Direction Setting Registers ...................................................................... 68
Table 31 Functions via NVM ................................................................................................................... 69
Table 32 Related Registers ..................................................................................................................... 70
Table 33 NVM Memory capacity.............................................................................................................. 72
Table 34 NVM Memory Map Example ..................................................................................................... 72
Table 35 Example setting of defect pixel ................................................................................................. 76
Table 36 Operation Specifications 2-wire Serial Communication Mode .................................................... 78
Table 37 Initialization sequence with XCLR ............................................................................................. 78
Table 38 Operation Specifications in 2-wire Serial Communication .......................................................... 79
Table 39 EXCK_FREQ setting table ........................................................................................................ 81
Table 40 Temperature setting registers.................................................................................................... 83
Table 41 Absolute Maximum Ratings ...................................................................................................... 84
Table 42 Recommended Operating Conditions ....................................................................................... 84
Table 43 DC Characteristics.................................................................................................................... 85
Table 44 Master Clock Square Waveform Input Characteristics ............................................................... 86
Table 45 Electrical Characteristics........................................................................................................... 86
Table 46 Image Sensor Characteristics ................................................................................................... 88
Table 47 Measurement Conditions .......................................................................................................... 89
Table 48 Spot Pixel Specifications........................................................................................................... 91

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IMX219PQH5-C

1. Block Diagram and Pin Configuration
1-1 Block Diagram

Fig. 1 Block Diagram

1-2 Pin Description
Table 1 Pin Description
PinNo.

SymbolI/O

A/D

Description

Remarks

1

VDDLSC1PowerD

1.2 V Power

2

VSSLSC1GND

D

1.2 V GND

3VDDHCM1PowerA

2.8 V Power

4

VSSHCM1

GND

A

2.8 V GND

5VSSLCN1

GND

D

1.2 V GND

6

VDDLCN1PowerD

1.2 V Power

7

VSSLDM1

8

VSSLSC2GND

D

1.2 V GND

9VDDHFIL1PowerA

2.8 V Power

10

VDDLCN2PowerD

1.2 V Power

11

VSSLCN2

GND

D

1.2 V GND

12VSSHCM2

GND

A

2.8 V GND

13

VDDHCM2PowerA

2.8 V Power

14

VSSLSC3GND

D

1.2 V GND

15

VDDLSC3PowerD

1.2 V Power

16

VCP

O

A

Analog Output

Connect to capacitor (2.2 µF)

17

VBO

O

A

Analog Output

Connect to capacitor (1.0 µF)

18

VSSHSN1GND

A

2.8 V GND

Dummy

10

NC

= VANAIMX219PQH5-C

Pin
No.

SymbolI/O

A/D

Description

Remarks

19

VDDHSN1PowerA

2.8 V Power

20

VSSLSC4GND

D

1.2 V GND

21

POREN

I

D

Digital Input

22

XCLR

I

D

Digital Input

23

TENABLEI

D

Digital Input

NC

24

GPO

I/O

D

Digital Input/Output

Connect to VSSLSC
when GPO is not enable

25

FSTROBEO

D

Digital Output

26

SDA

I/O

D

Digital Input/Output

27

SCL

I

D

Digital Input

28

TEST1

I

D

Digital Input

NC

29

SWTCK

I

D

Digital Input

NC

30

INCK

I

D

Digital Input

31

VDDMCOPower

D

1.8 V Power32

VSSLSC5GND

D

1.2 V GND

33

VDDLSC5PowerD

1.2 V Power34

VDDHFIL2PowerA

2.8 V Power

35

VDDLSC6PowerD

1.2 V Power36

VSSLSC6GND

D

1.2 V GND37

VSSLDM2

38

VDDLSC7PowerD

1.2 V Power

39

VSSLSC7GND

D

1.2 V GND

40

VDDLIO1PowerD

1.2 V Power41

VSSLIO1

GND

D

1.2 V GND

42

DMO1N

O

D

Digital Output

43

DMO1P

O

D

Digital Output

44

DMO2N

O

D

Digital Output

45

DMO2P

O

D

Digital Output

46

VSSLIO2

GND

D

1.2 V GND

47

DCKN

O

D

Digital Output

48

DCKP

O

D

Digital Output

49

VSSLIO3

GND

D

1.2 V GND

50

DMO3N

O

D

Digital Output

51

DMO3P

O

D

Digital Output

52

DMO4N

O

D

Digital Output

53

DMO4P

O

D

Digital Output

54

VSSLIO4

GND

D

1.2 V GND

55

VDDLIO2PowerD

1.2 V Power56

VSSLSC8GND

D

1.2 V GND

57

VDDLSC8PowerD

1.2 V Power

Dummy

11

Connect to VDIG

= VANANC

IMX219PQH5-C

Pin
No.

SymbolI/O

A/D

Description

Remarks

58

VSSHPL

GND

D

2.8 V GND

59

VDDHPLPower

D

2.8 V Power

60

TVCDSIN

I

A

Analog Input

NC, For test

61

TVMON

O

A

Analog Output

NC, For test

62

VSSHAN

GND

A

2.8 V GND

63

VDDHANPower

A

2.8 V Power

64

VDDHSN2PowerA

2.8 V Power

65

VSSHSN2GND

A

2.8 V GND

12

IMX219PQH5-C

1-3 Pin Equivalent Circuit
SymbolEquivalent circuit

Symbol

VSSH

VCP

Equivalent circuit

AnalogOutputAnalogOutput

VBO

VSSH

VDIG

VDIG

Digital
Input

Digital
Input
XCLR

INCK

VSSL

VSSL

VDIG

VDIG

Digital I/O

VDIG
Digital
I/O

SDA
SCL
VSSL

VDIG

GPO

VSSL
Schmitt
Buffer

VSSL

VDIG

VDIG

VDIG
VDIG

DigitalOutputFSTROBE

POREN

VDIG

Analog
Input

VSSL

VSSL

VDDH: 2.8 V power supply, VDIG: 1.8 V power supply, VDDL: 1.2 V power supply
VSSH: 2.8 V GND, VSSL: 1.2 V GND

Fig. 2 Pin Equivalent Circuit

13

IMX219PQH5-C

1-4 Chip Center, Optical Center and Pin Assignment(Unit: µm)

Fig. 3 Chip Center and Optical Center

14

IMX219PQH5-C

1-5 Pin Coordinates
Table 2 Pin Coordinates
Pin
No.

SymbolX(pad center)Y(pad center)

Pin
No.

SymbolX(pad center)Y(pad center)

1

VDDLSC1

2247.502355.00

35

VDDLSC6-2447.50-2165.00

2

VSSLSC1

1767.502355.00

36

VSSLSC6-2247.50-2365.00

3

VDDHCM1

1647.502355.00

37

VSSLDM2-2127.50-2365.00

4

VSSHCM1

1407.502355.00

38

VDDLSC7-807.50-2365.00

5

VSSLCN1

1167.502355.00

39

VSSLSC7-567.50-2365.00

6

VDDLCN1

687.502355.00

40

VDDLIO1

447.50-2365.00

7

VSSLDM1

567.502355.00

41

VSSLIO1

567.50-2365.00

8

VSSLSC2

447.502355.00

42

DMO1N

687.50-2365.00

9

VDDHFIL1

167.502356.00

43

DMO1P

807.50-2365.00

10

VDDLCN2-727.502355.00

44

DMO2N

927.50-2365.00

11

VSSLCN2-1207.50

2355.00

45

DMO2P

1047.50-2365.00

12

VSSHCM2-1407.50

2355.0046

VSSLIO2

1167.50-2365.00

13

VDDHCM2-1647.50

2355.0047

DCKN

1287.50-2365.00

14

VSSLSC3-1767.50

2355.00

48

DCKP

1407.50-2365.00

15

VDDLSC3-2247.50

2355.0049

VSSLIO31527.50-2365.00

16

VCP-2447.50

1915.00

50

DMO3N

1647.50-2365.00

17

VBO-2447.50

1795.00

51

DMO3P

1767.50-2365.00

18

VSSHSN1-2447.50

1675.00

52

DMO4N

1887.50-2365.00

19

VDDHSN1-2447.50

1555.00

53

DMO4P

2007.50-2365.00

20

VSSLSC4-2447.50

1125.0054

VSSLIO42127.50-2365.00

21

POREN

-2447.50

1005.00

55

VDDLIO2

2247.50-2365.00

22

XCLR-2447.50

885.0056

VSSLSC82447.50-2165.00

23

TENABLE-2447.50

765.0057

VDDLSC82447.50-1925.00

24

GPO-2447.50

645.0058

VSSHPL

2447.50-507.00

25

FSTROBE-2447.50

525.0059

VDDHPL

2447.50-387.00

26

SDA-2447.50

405.0060

TVCDSIN

2447.50-20.0027

SCL-2447.50

205.0061

TVMON2447.50

100.0028

TEST1-2447.50

5.00

62

VSSHAN

2447.50750.0029

SWTCK-2447.50-115.00

63

VDDHAN

2447.50870.0030

INCK-2447.50-235.00

64

VDDHSN2

2447.50

1850.00

31

VDDMCO-2447.50-355.00

65

VSSHSN2

2447.50

1970.00

32

VSSLSC5-2447.50-480.00

33

VDDLSC5-2447.50-600.00

34

VDDHFIL2-2447.50-726.00

15

IMX219PQH5-C

2. Pixel Signal Output Specifications
IMX219PQH5-C has CSI-2 interface and the options are 4 lanes or 2lanes.

2-1 CSI-2 Signalling Mode
2-1-1 MIPI Transmitter
Output pin of CSI-2 are shown below

MIPI BlockDMO1P/N

Lane 1DMO2P/N

Lane 2

DCKP/N

Clock LaneDMO3P/N

Lane 3

DMO4P/N

Lane 4

Fig. 4 Relationship between Output pin name and MIPI output Lane

Data and clock signals are transmitted using CSI-2 interface (high speed serial interface). Detailed explanation of
CSI-2 interface is in following two documents, “MIPI Alliance Standard for Camera Serial Interface2 (CSI-2)
Version 1.01” and “MIPI Alliance Specification for D-PHY Version 1.10.00”. In CSI-2 interface, one bit of data istransmitted by a pair of differential signals. In the transmitter of CSI-2 interface, differential digital signals of data orclock are converted to differential current signals. At the receiver of CSI-2 interface, inserting output resistance,
which is serial to a pair of differential outputs (data or clock), or connecting the receiver block, which includes
internal resistance for a pair of differential outputs (data or clock), is required. In the case of using output
resistance, output resistance is placed close to the receiver. Additionally, it is recommended that each space
between differential output lines such as DMO1P/DMO1N, DMO2P/DMO2N, DMO3P/DMO3N, DMO4P/DMO4N,
or DCKP/DCKN is identical, the length of all differential output lines is same, and output line length between thetransmitter and the receiver is minimum.

2-1-2 Output Lane
Two or Four data output Lanes are applied from MIPI Alliance Standard for Camera Serial Interface2 (CSI-2)
Version 1.01.

2-1-2-1 2Lane Output
Outputs of data and clock come from CSI-2 output pins (DMO1P/DMO1N, DMO2P/DMO2N, DCKP/DCKN). A
pair of DMO1P/DMO1N is called Lane1 data and a pair of DMO2P/DMO2N is called Lane2 data. Also, clock
signals come from CSI-2 output pins, DCKP/DCKN. Maximum output data rate is 912 Mbps/lane. (1lane output
is not supported).

16

IMX219PQH5-C

3. Control Registers
The IMX219PQH5-C can use the 2-wire serial communication method for sensor control. These specifications aredescribed for sensor control using the 2-wire serial communication as follows.

3-1 2-wire Serial Communication Operation Specifications
The 2-wire serial communication method conforms to the Camera Control Instance (CCI). CCI is an I2C fast-mode
plus ( INCK[fSCK] = 11.4 to 27 MHz) compatible interface, and the data transfer protocol is I2C standard.
This 2-wire serial communication circuit can be used to access the control-registers and status-registers of
IMX219PQH5-C.

SCL
IMX149
IMX219MasterSDA

Fig. 5 2-wire Serial Communication
Table 3 Description of 2-wire Serial Communication Pins
SymbolDescription

SDA

Serial data communication

SCL

Serial clock input

3-1-1 Communication Protocol
2-wire serial communication supports a 16-bit register address and 8-bit data message type.
S

Slave Address
[7:1]

R
/ A
W

Register Address[15:8]A

Register Address
[7:0]

Data
[7:0]

A

A
/ P
A

From Master to Slave

S=Start Condition

A=Acknowledge

Direction Dependent on Operation(Sr=Repeated Start Condition)

A=Negative Acknowledge

From Slave to Master

P=Stop Condition

Fig. 6 2-wire Serial Communication Protocol
Data is transferred serially, MSB first in 8-bit units. After each data byte is transferred, A (Acknowledge)/Ā
(Acknowledge) is transferred. Data (SDA) is transferred at the clock (SCL) cycle. SDA can change only
while SCL is Low, so the SDA value must be held while SCL is High.
The Start condition is defined by SDA changing from High to Low while SCL is High. When the Stopcondition is not generated in the previous communication phase and Start condition for the next
communication is generated, that Start condition is recognized as a Repeated Start condition.

17

IMX219PQH5-C

Bus free state

SDA

MSB

SDA

S

A7

LSB
A6

A5

A4

A3

A2

A1

R/W

ACK

SCL

SCL

Data sampling

The Data changeds
while the clock is Low.

Start Condition

Fig. 7 Start Condition

MSB

SDA

ACK/NACK

SDA

S

A7

A6

A5

A4

A3

SCL

SCL

Start Condition
The Stop condition is not generated.

Fig. 8 Repeated Start Condition
The Stop condition is defined by SDA changing from Low to High while SCL is High.
Bus free state

SDA

SDA

SCL

SCL

D5

D4

D3

D2

D1

D0

R/W

ACK/NACKP

Stop Condition

Fig. 9 Stop Condition

LSB

0 0 1 0 0 0 0

R/W

[7:1]

MSB

R/W

Slave Address

Fig. 10 Slave Address

The R/W bit indicates the data transfer direction.

Table 4 R/W Bit
R/W bitTransfer direction

0

Write (Master →Sensor)

1

Read (Sensor → Master)

After transfer of each data byte, the Master or the sensor transmits an Acknowledge / Negative Acknowledge andreleases (does not drive) SDA. When Negative Acknowledge is generated, the Master must immediately generate
the Stop condition and end the communication.

18

IMX219PQH5-C

SDA

SDA

SCL

SCL

SDA

SDA

SCL

SCL

D1

D0

R/W

ACK

D1

D0

R/W

NACK

Fig. 11 Acknowledge and Negative Acknowledge
The registers have a 16-bit address space, and are assigned as follows.

Table 5 2-wire Serial Communication Address Space
Address area

Description

0x0000 - 0x0FFF

Configuration register

0x1000 - 0x1FFF

Parameter limit register
Read Only and Static register

0x3000 - 0xFFFF

Manufacture specific register

3-1-2 2-wire serial communication read/write operation supported
The IMX219PQH5-C supports the following four read operations and two write operations that conform to the
SMIA standard.

Table 6 Operations Supported by 2-wire Serial Communication
1

CCI Single read from random location(Single read from an optional address)

2

CCI Single read from current location(Single read from the held address)

3

CCI sequential read starting from random location(Sequential read starting from an optional address)

4

CCI sequential read starting from current location(Sequential read starting from the held address)

5

CCI single write to random location(Single write to an optional address)

6

CCI sequential write starting from random location(Sequential write starting from an optional address)

19

IMX219PQH5-C

3-1-2-1 CCI single read from random location
The sensor has an index function that indicates which address it is focusing on. In reading the data at an
optional single address, the Master must set the index value to the address to be read. For this purpose it
performs dummy write operation up to the register address. The upper level of the figure below shows thesensor internal index value, and the lower level of the figure shows the SDA I/O data flow. The Master sets thesensor index value to M by designating the sensor slave address with a write request, then designating theaddress (M). Then, the Master generates the start condition. The Start condition is generated without
generating the Stop condition, so it becomes the Repeated Start condition. Next, when the Master sends theslave address with a read request, the sensor outputs an Acknowledge immediately followed by the index
address data on SDA . After the Master receives the data, it generates a Negative Acknowledge and the Stopcondition to end the communication.

Previous Index value

S

Slave
Address
[7:1]

0A

Index
M+1

Index M

Register
RegisterA
Address
Address[15:8][7:0]
Index, value M

Slave
Address
[7:1]

A Sｒ

From Master to Slave

S=Start Condition

From Slave to Master

Sr=Repeated Start Condition

Data
[7:0]

1A

P=Stop ConditionAP

A=Acknowledge
A=Negative Acknowledge

Fig. 12 CCI single read from random location
3-1-2-2 CCI single read from current location
After the slave address is transmitted by a write request, that address is designated by the next communicationand the index holds that value. In addition, when data read/write is performed, the index is incremented by thesubsequent Acknowledge/Negative Acknowledge timing. When the index value is known to indicate theaddress to be read, sending the slave address with a read request allows the data to be read immediately after
Acknowledge. After receiving the data, the Master generates a Negative Acknowledge and the Stop condition
to end the communication, but the index value is incremented, so the data at the next address can be read bysending the slave address with a read request.

Previous Index value,K

S

Slave
Address
[7:1]

1A

Data
[7:0]

Index
K+2

Index K+1

AP

S

Slave
Address[7:1]

1A

From Master to Slave

S=Start Condition

A=Acknowledge

From Slave to Master

P=Stop Condition

A=Negative Acknowledge

Fig. 13 CCI single read from current location

20

Data
[7:0]

AP

IMX219PQH5-C

3-1-2-3 CCI sequential read starting from random location
In reading data sequentially, which is starting from an optional address, the Master must set the index value tothe start of the addresses to be read. For this purpose, dummy write operation includes the register address
setting. The Master sets the sensor index value to M by designating the sensor slave address with a readrequest, then designating the address (M). Then, the Master generates the Repeated Start condition. Next,
when the Master sends the slave address with a read request, the sensor outputs an Acknowledge followed
immediately by the index address data on SDA. When the Master outputs an Acknowledge after it receives thedata, the index value inside the sensor is incremented and the data at the next address is output on SDA. This
allows the Master to read data sequentially. After reading the necessary data, the Master generates a Negative
Acknowledge and the Stop condition to end the communication.

Previous Index value, K

Index M

Slave
Register
RegisterSlave
S Address 0 A Address A Address ASｒ Address 1 A[7:1][15:8][7:0][7:1]
Index, value M

Index(M+L-1)

Index M+1

Data
[7:0]

From Master to Slave

S=Start Condition

From Slave to Master

Sr=Repeated Start Condition

A

Data
[7:0]

A

A

Data
[7:0]

Index
(M+L)
AP

L bytes of data

P=Stop Condition

A=Acknowledge
A=Negative Acknowledge

Fig. 14 CCI sequential read starting from random location
3-1-2-4 CCI sequential read starting from current location
When the index value is known to indicate the address to be read, sending the slave address with a readrequest allows the data to be read immediately after the Acknowledge. When the Master outputs an
Acknowledge after it receives the data, the index value inside the sensor is incremented and the data at thenext address is output on SDA. This allows the Master to read data sequentially. After reading the necessarydata, the Master generates a Negative Acknowledge and the Stop condition to end the communication.

Index K
Slave
S Address 1 A
[7:1]

Index
(K+L-1)

Index K+1

Data
[7:0]

A

Data
[7:0]

A

A

Data
[7:0]

Index
(K+L)
AP

L bytes of data

From Master to Slave

S=Start Condition

A=Acknowledge

From Slave to Master

P=Stop Condition

A=Negative Acknowledge

Fig. 15 CCI sequential read starting from current location

21

IMX219PQH5-C

3-1-2-5 CCI single write to random location
The Master sets the sensor index value to M by designating the sensor slave address with a write request, anddesignating the address (M). After that the Master can write the value in the designated register by transmitting
the data to be written. After writing the necessary data, the Master generates the Stop condition to end thecommunication.

Previous Index value

S

Slave
Address
[7:1]

0A

Index
M+1

Index M

Register
RegisterA
Address
Address[15:8][7:0]
Index, value M

A
/P
A

Data
[7:0]

A

From Master to Slave

S=Start Condition

A=Acknowledge

From Slave to Master

P=Stop Condition

A=Negative Acknowledge

Fig. 16 CCI single write to random location
3-1-2-6 CCI sequential write starting from random location
The Master can write a value to register address M by designating the sensor slave address with a write
request, designating the address (M), and then transmitting the data to be written. After the sensor receives thewrite data, it outputs an Acknowledge and at the same time increments the register address, so the Master canwrite to the next address simply by continuing to transmit data. After the Master writes the necessary number ofbytes, it generates the Stop condition to end the communication.

Previous Index value, K

Index M

Slave
Register
Register
S Address 0 A Address A Address A[7:1][15:8][7:0]
Index, value M

Data
[7:0]

Index
(M+L-1)

Index M+1

A

Data
[7:0]

A

A

Data
[7:0]

L bytes of data

From Master to Slave

S=Start Condition

A=Acknowledge

From Slave to Master

P=Stop Condition

A=Negative Acknowledge

Fig. 17 CCI sequential write starting from random location

22

Index
(M+L)
A
/P
A

IMX219PQH5-C

3-1-3 2-wire serial communication block characteristics
The block operation specifications for 2-wire serial communication are show below.

Repeated
Start
Condition

Start
Condition

Stop
Condition

tBUF
SDA
tR

tF

SCL

tSUDATtHIGH
tLOWtSUSTAtHDDATtHDSTAtSUSTO

tHDSTA

Fig. 18 2-wire Serial Communication Specifications

Table 7 2-wire Serial Communication Operation Specifications
Item

SymbolConditions

Min.

Max.

Unit

Low level input voltage

VIL

-0.5

0.3VDIG

V

High level input voltage

VIH

0.7VDIG

VDIG+0.5

V

0.25VDIGV

Low level output voltage VOL

VDIG < 2 V,Sink 2 mA

High level output voltage VOH

VDIG < 2 V,Sink 2 mA

0.75VDIG

Output fall time

tof

Load 10 pF – 400 pF,0.7VDIG – 0.3VDIG

Input current

II

0.1VDIG -0.9VDIG

SDA I/O capacitanceSCL Input capacitance

V
120

ns

10

µA

CI/O

8

pF

CI

6

pF

-10

Table 8 2-wire Serial Communication AC Timing (Fast mode plus (INCK[fSCK] = 11.4 to 27 MHz))
Item

Symbol

Min.

Max.

Unit

SCL clock frequency ( INCK[fSCK] = 11.4 to 27 MHz)

fSCL

0

1000

kHz

Rise time (SDA and SCL)

tR

―

120

ns

Fall time (SDA and SCL)

tF

―

120

ns

Hold time (start condition)

tHDSTA

0.26

―

µs

Setup time (rep.-start condition)tSUSTA

0.26

―

µs

Setup time (stop condition)tSUSTO

0.26

―

µs

Data setup timetSUDAT

50―

ns

Data hold time

tHDDAT0―µs

Bus free time between Stop and Start condition

tBUF

0.5

µs

Low period of the SCL clock

tLOW

0.5

µs

High period of the SCL clock

tHIGH

0.26

µs

23

IMX219PQH5-C

Table 9 2-wire Serial Communication AC Timing (Fast mode)
Item

Symbol

Min.

Max.

Unit

SCL clock frequency ( INCK[fSCK] = 6 to 27 MHz)

fSCL

0

400

kHz

Rise time (SDA and SCL)

tR

―

300

ns

Fall time (SDA and SCL)

tF

―

300

ns

Hold time (start condition)

tHDSTA

0.6―µs

Setup time (rep.-start condition)tSUSTA

0.6―µs

Setup time (stop condition)tSUSTO

0.6―µs

Data setup timetSUDAT

100―

ns

Data hold time

tHDDAT0

0.9µs

Bus free time between Stop and Start condition

tBUF

1.3

µs

Low period of the SCL clock

tLOW

1.3

µs

High period of the SCL clock

tHIGH

0.6

µs

3-1-4 2-wire serial communication register map
3-1-4-1 Description of 2-wire communication register map
In 2-wire serial communication, there is a 16-bit address space as follows. In IMX219PQH5-C, there arepartially unreadable registers, which is described in Register map. If reading unreadable registers, the value tobe read is 00h.

Table 10 2-wire Serial Communication Register Map Address Areas
Address Area

Description

0x0000 - 0x0fff

Configuration register

0x1000 - 0x1fff

Parameter limit register
Read Only and Static resister

0x3000 - 0xffff

Manufacture specific register24

IMX219PQH5-C

3-1-5 Register Synchronization (Frame Bank)
Sequence for control of frame bank is explained in this section:
1.
2.

All registers on frame bank are latched by vertical synchronization (V-sync) signal.
Any change for registers on frame bank are reflected to functions in next frame (or following next frame) if thecorresponding registers are updated.
Figures for sequences of frame bank are shown in following statements.
In case that user changes analog/digital gain and integration time only, we see no “no-data” term.

In case that user changes following registers, we may see a term in which we do not see any output from thesensor in addition to vertical blanking interval. From ISP's standing point, it seems that sensor has a bit longer
vertical blanking interval.
Additional “no-data term” will be equal to coarse_integration_time + 20[H] if fast tracking mode register isactivated.
List of registers is:- Binning related registers (especially for analog binning)- Sub-sampling registers (for vertical direction)- Vertical image orientation registers- Vertical ROI

Fig. 19 Function Example for Frame Bank

25

IMX219PQH5-C

3-2 2-wire Serial Communication Register Map(Configuration register, Parameter limit register)
3-2-1 Configuration Registers – [0x0000-0x0FFF]
3-2-1-1 Status Registers – [0x0000-0x001B] (Read Only Dynamic Registers)
Index

Byte

Register Name

RW

0000

[7:0]

MODEL_ID[15:8]

RO

0001

[7:0]

MODEL_ID[7:0]

RO

0004

[7:0]

Lot_ID[23:16]

RO-D

Comment
model id

ReTimeDefault
(HEX)

Embd
DL

02
19

Lot_ID of the sensor
Copied from NVM

XX

○

XX

○

XX

○

0005

[7:0]

Lot_ID[15:8]

RO-D

0006

[7:0]

Lot_ID[7:0]

RO-D

0007

[7:0]

Wafer_Num

RO-D

Wafer Number of the Sensor in the Lot.
Value 0x01-0x19 is available.

XX

○

000D

[7:0]

Chip_Number[15:8]

RO-D

Chip ID in the wafer

XX

○

000E

[7:0]

Chip_Number[7:0]

RO-D

XX

○

0018

[7:0]

FRM_CNT[7:0]

RO-D

FF

○

0019

[7:0]

PX_ORDER

RO-D

01

○

001A

[1:0]

DT_PEDESTAL[9:8]

RO-D

0

○

001B

[7:0]

DT_PEDESTAL[7:0]

RO-D

40

○

26

IMX219PQH5-C

3-2-1-2 Frame Format Description – [0x0040-0x0047]
Embd
DL

frame_format_model_type

01

○

RO

frame_format_model_subtype

12

○

5C

○

RO-D

frame_format_descriptor_0
D0

○

10

○

02

○

59

○

A0

○

Default

Embd
DL

Byte

Register Name

RW

0x0040[7:0]

FRM_FMT_TYPE[7:0]RO

0x0041[7:0]

FRM_FMT_SUBTYPE[7:0]0x0042[7:0]

FRM_FMT_DESC0[15:8]

0x0043[7:0]

FRM_FMT_DESC0[7:0]0x0044[7:0]

FRM_FMT_DESC1[15:8]

Comment

RO
0x0045[7:0]

FRM_FMT_DESC1[7:0]0x0046[7:0]

FRM_FMT_DESC2[15:8]

frame_format_descriptor_1

RO-D
0x0047[7:0]

ReTimeDefault
(HEX)

Index

frame_format_descriptor_2

FRM_FMT_DESC2[7:0]

3-2-1-3 Analogue Gain Description Registers – [0x0080-0x0093]
Index

Byte

Register Name

RW

0x0080―――0x0081[7:0]

analogue_gain_capability

RO

0x0082―

Reserved

RO

Comment

ReTime(HEX)
00

Analogue Gain Description Registers

000

Reserved

0x0083―――0x0084―――0x0085[7:0]

analogue_gain_code_min

RO-D

Analogue Gain Description Registers

00

0x0086[7:0]

analogue_gain_code_max

ROAnalogue Gain Description Registers

00

0x0087[7:0]

possible to setup up to E8 (HEX)

E00x0088[7:0]

analogue_gain_code_step

00
00

RO

00
Analogue Gain Description Registers

0x0089[7:0]

0x008A[7:0]

01
analogue_gain_typeRO00
Analogue Gain Description Registers

0x008B[7:0]

0x008C[7:0]00
analogue_gain_m0

RO00
Analogue Gain Description Registers

0x008D[7:0]

0x008E[7:0]00
analogue_gain_c0

RO01
Analogue Gain Description Registers

0x008F[7:0]

0x0090[7:0]00
analogue_gain_m1

ROFF
Analogue Gain Description Registers

0x0091[7:0]

0x0092[7:0]

FF
analogue_gain_c1

RO01
Analogue Gain Description Registers

0x0093

[7:0]

00

27

IMX219PQH5-C

3-2-1-4 Data Format Description – [0x00C0-0x00D1]
Embd
DL

data_format_model_type

01

○

RO

data_format_model_subtype

01

○

0A

○

RO

data_format_descriptor_0
08

○

0A

○

0A

○

Default
(HEX)

Embd
DL

Byte

Register Name

RW

Comment

0x00C0[7:0]

DT_FMT_TYPE[7:0]RO0x00C1[7:0]

DT_FMT_SUBTYPE[7:0]0x00C2[7:0]

DT_FMT_DESC0[15:8]

0x00C3[7:0]

DT_FMT_DESC0[7:0]0x00C4[7:0]

DT_FMT_DESC1[15:8]
RO

0x00C5[7:0]

ReTimeDefault
(HEX)

Index

data_format_descriptor_1

DT_FMT_DESC1[7:0]

3-2-2 Set-up Registers – [0x0100-0x0147]
3-2-2-1 General Set-up Registers – [0x0100-0x0106]
Index

Byte

Register Name

0x0100[4:0]

mode_select [4:0]0x0101―

Reserved

0x0102―

Reserved

0x0103[0]0x0104

RW

Comment

ReTimeRW

Mode Select:
0: SW standby, 1: Streaming00○

software_reset

RW

Software reset

00

○

[0]

corrupted frame status

RO-D

corrupted frame status00○

0x0105[0]

mask_corrupted_frames

RW

mask_corrupted_frames

01○

0x0106[0]

fast standby enable

RW

fast standby from streaming

00

○

28

IMX219PQH5-C

3-2-2-2 Output Set-up Registers – [0x0110-0x0147]
Default
(HEX)

Embd
DL

CSI-2 channel ID

0

○

RO

CSI-2 signalling mode0○

CSI_LANE_MODE

RW

CSI_lane_mode
0: Reserved, 1: 2-Lane, 2: Reserved,
3: 4-Lane

3

○

[0]

TCLK_POST[8]RW

Global Timing Parameters

00x0119[7:0]

TCLK_POST[7:0]

RW

Global Timing Parameters

6F

0x011A[0]

THS_PREPARE[8]RW

Global Timing Parameters

0

Index

Byte

Register Name

RW

0x0110[1:0]

CSI_CH_ID

RW

0x0111[1:0]

CSI_SIG_MODE

0x0114[1:0]

0x0118Comment

ReTime0x011B[7:0]

THS_PREPARE[7:0]

RW

Global Timing Parameters

2F

0x011C[0]

THS_ZERO_MIN[8]RW

Global Timing Parameters

00x011D[7:0]

THS_ZERO_MIN[7:0]

RW

Global Timing Parameters57

0x011E[0]

THS_TRAIL[8]RW

Global Timing Parameters

00x011F[7:0]

THS_TRAIL[7:0]

RW

Global Timing Parameters

2F

0x0120[0]

TCLK_TRAIL_MIN[8]RW

Global Timing Parameters

00x0121[7:0]

TCLK_TRAIL_MIN[7:0]

RW

Global Timing Parameters

2F

0x0122[0]

TCLK_PREPARE[8]RW

Global Timing Parameters

00x0123[7:0]

TCLK_PREPARE[7:0]

RW

Global Timing Parameters

2F

0x0124[0]

TCLK_ZERO[8]RW

Global Timing Parameters

00x0125[7:0]

TCLK_ZERO[7:0]

RW

Global Timing Parameters

BF

0x0126[0]

TLPX[8]RW

Global Timing Parameters

00x0127[7:0]

TLPX[7:0]

RW

Global Timing Parameters27

0x0128[0]

DPHY_CTRLRWMIPI Global timing setting
0: auto mode, 1: manual mode

1

0x012A[7:0]

EXCK_FREQ[15:8]

RW

INCK frequency [MHz]0C

0x012B[7:0]

EXCK_FREQ[7:0]

RW

INCK frequency [MHz]

00

[7]

TEMPERATURE_EN

RW

start register to measure sensor
temperature

0

○

[6:0]

TEMPERATURE_VAL

RO-D

result of measurement of sensor
temperature

XX

○

[7:0]

READOUT_V_CNT[15:8]

indicates current V-counter value forread-out

XX

○

RO-D

XX

○

0x01400x01420x0143[7:0]

READOUT_V_CNT[7:0]RW

defines polarity of V-sync signal.
0: Lo-active, 1: Hi-active

0

0x0144[0]

VSYNC_POL

0x0145―Reserved

0x0146[0]

FLASH_POL

RW

defines polarity of flash strobe signal.
0: Hi-active, 1: Lo-active

0

0x0147[0]

VSYNC_TYPE

RW

Vsync type control
0: Vsync, 1: Reserved

029

IMX219PQH5-C

3-2-3 Frame Bank Control and Group “A” – [0x0150-0x018D]
3-2-3-1 Frame Bank Control Registers - [0x0150-0x0153]
Index

Byte

Register Name

RW

Comment

ReTimeDefault
(HEX)

Embd
DL

[1]

FRAME_BANK_STATUS

RO-D

indicates frame bank applied in current frame

X

○

[0]

FRAME_BANK _ENABLE

RW

defines Frame Bank to be applied in next
frame (manual switching)

0

○

[7:0]

FRAME_BANK _FRM_CNT

RO-D

frame counter value for frame bank switching.

XX

○

RW

When host changes frame_bank_enableregisterunder ERS mode, sensor immediately stops
current V-blanking and start new exposure.

0○

Re-TimeDefault
(HEX)

Embd
DL

0x01500x01510x0152[0]0x0153―

FRAME_BANK_FAST_TRACKING――

3-2-3-2 Frame Bank Registers Group “A”- [0x0154-0x018D]
Index

Byte

Register Name

RW

0x0154[7:0]

FRAME_DURATION_A

RWdefines number of frames to apply
Frame Bank-A to actual function.

frame bank00○

0x0155[0]

COMP_ENABLE_A

RW

compression 10 to 8 mode
0: Disable, 1: Enable

frame bank0○

analogue_gain_code_global

frame bank

00

○

1

○

00

○

0x0156―0x0157[7:0]

ANA_GAIN_GLOBAL_A

0x0158[3:0]

DIG_GAIN_GLOBAL_A [11:8]

0x0159

[7:0]

DIG_GAIN_GLOBAL_A [7:0][7:0]

COARSE_INTEGRATION_
TIME_A[15:8]

0x015A

―

0x015B[7:0]

COARSE_INTEGRATION_
TIME_A[7:0]0x015C―

Reserved

0x015D[0]

SENSOR_MODE_A

0x015E―

Reserved

0x015F―

Reserved

0x0160[7:0]

FRM_LENGTH_A[15:8]

0x0161[7:0]

FRM_LENGTH_A[7:0]0x0162[7:0]

LINE_LENGTH_A[15:8]

0x0163[7:0]

LINE_LENGTH_A[7:0]0x0164[3:0]

X_ADD_STA_A[11:8]

0x0165[7:0]

X_ADD_STA_A[7:0]0x0166[3:0]

X_ADD_END_A[11:8]

0x0167[7:0]

X_ADD_END_A[7:0]0x0168[3:0]

Y_ADD_STA_A[11:8]

0x0169[7:0]

Y_ADD_STA_A[7:0]0x016A[3:0]

Y_ADD_END_A[11:8]

0x016B[7:0]

Y_ADD_END_A[7:0]0x016C[3:0]

x_output_size[11:8]

0x016D[7:0]

x_output_size[7:0]0x016E[3:0]

y_output_size[11:8]

0x016F[7:0]

y_output_size[7:0]Comment―
RW
RW

digital gain global

frame bank

RW

coarse_integration_time

frame bank

03

○
E8

RO

shutter mode register.
0: ERS, 1: reserved

RW

frame_length_lines
BINNING_MODE = 0,1,2
Unit: 1Lines
BINNING_MODE = 3
Units: 2Lines

frame bank

RW

line_length_pck
Units: Pixels

frame bank

RW

x_addr_startX-address of the top left corner of thevisible pixel data
Units: Pixels

frame bank

RW

x_addr_end
X-address of the bottom right corner ofthe visible pixel data Units: Pixels

frame bank

RW

y_addr_startY-address of the top left corner of thevisible pixel data
Units: Lines

frame bank

RW

y_addr_end
X-address of the bottom right corner ofthe visible pixel data Units: Pixels

frame bank

RW

output image size (X-direction)
Width of image data output from thesensor module Units: Pixels

frame bank

RW

output image size (Y-direction)
Height of image data output from thesensor module Units: Lines

frame bank30

frame bank

X

○

0A

○

A8

○

0D

○

78

○

0

○

00

○

C

○

CF

○

0

○

00

○

9

○

9F

○

C

○

D0

○

9

○

A0

○

IMX219PQH5-C

Index

Byte

0x0170[2:0]

Register NameRW

X_ODD_INC_A
RW

0x01710x0172[2:0]

Y_ODD_INC_A[0]

IMG_ORIENTATION_A[0]Re-TimeDefault
(HEX)

Embd
DL

x_odd_inc
Increment for odd pixels 1, 3

frame bank1○

y_odd_inc
Increment for odd pixels 1, 3

frame bank1○

image_orientation (for both direction)
bit[0]: hori. direction bit[1]: vert.
direction0○

frame bank0○Comment

RW[1]

IMG_ORIENTATION_A[1]0x0173―

Reserved

0x0174[1:0]

BINNING_MODE_H_A

RW

defines binning mode (H-direction).
0: no-binning, 1: x2-binning,
2: x4-binning, 3: x2-analog (special)binning

frame bank0○0x0175[1:0]

BINNING_MODE_V_A

RW

defines binning mode (V-direction).
0: no-binning, 1: x2-binning,
2: x4-binning, 3: x2-analog (special)binning

frame bank0○0x0176[0]

BINNING_CAL_MODE_H_A

RW

defines binning mode (H-direction).
0 :average, 1: sumframe bank0○0x0177[0]

BINNING_CAL_MODE_V_A

RW

defines binning mode (V-direction).
0: average, 1: sumframe bank0○0x0189[7:0]

ANA_GAIN_GLOBAL_SHORT_A

RW

Analog gain (short exposure)frame bank00○

0x018A[7:0]

COARSE_INTEG_TIME_SHO
RT_A [15:8]

01

○

RW

Coarse integ time (short exposure)frame bank
F4

○

0A

○

0A

○

0x018B[7:0]

COARSE_INTEG_TIME_SHO
RT_A [7:0]0x018C[7:0]

CSI_DATA_FORMAT_A [15:8]

0x018D[7:0]

CSI_DATA_FORMAT_A [7:0]

RW

RW

CSI-2 data format

31

frame bank

IMX219PQH5-C

3-2-4 Frame Bank Control Group “B” – [0x0254-0x028D]
3-2-4-1 Frame Bank Registers Group “B”- [0x0254-0x028D]
Index

Byte

Register Name

RW

0x0254[7:0]

FRAME_DURATION_B

RW

0x0255[0]

COMP_ENABLE_B

RW

0x0256―0x0257[7:0]

ANA_GAIN_GLOBAL_B

0x0258[3:0]

DIG_GAIN_GLOBAL_B[11:8]

0x0259

[7:0]

DIG_GAIN_GLOBAL_B[7:0][7:0]

COARSE_INTEGRATION_
TIME_B[15:8]

RW
RW

0x025A―

0x025B[7:0]

COARSE_INTEGRATION_
TIME_B[7:0]0x025C―

Reserved

0x025D[0]

SENSOR_MODE_B

0x025E―

Reserved

0x025F―

Reserved

0x0260[7:0]

FRM_LENGTH_B[15:8]

0x0261[7:0]

FRM_LENGTH_B[7:0]0x0262[7:0]

LINE_LENGTH_B[15:8]

0x0263[7:0]

LINE_LENGTH_B[7:0]0x0264[3:0]

X_ADD_STA_B[11:8]

0x0265[7:0]

X_ADD_STA_B[7:0]0x0266[3:0]

X_ADD_END_B[11:8]

0x0267[7:0]

X_ADD_END_B[7:0]0x0268[3:0]

Y_ADD_STA_B[11:8]

0x0269[7:0]

Y_ADD_STA_B[7:0]0x026A[3:0]

Y_ADD_END_B[11:8]

0x026B[7:0]

Y_ADD_END_B[7:0]0x026C[3:0]

x_output_size[11:8]

0x026D[7:0]

x_output_size[7:0]0x026E[3:0]

y_output_size[11:8]

0x026F[7:0]

y_output_size[7:0]

Re-TimeDefault
(HEX)

Embd
DL

defines number of frames to apply
FrameBank-A to actual function.

frame bank00○

compression 10 to 8 mode
0: Disable, 1: Enable

frame bank0○

analogue_gain_code_global

frame bank

00

○

1

○

00

○

03

○

E8

○

Comment―
RW
RW

digital gain global

frame bankcoarse_integration_time

frame bank○ROshutter mode register.
0: ERS, 1: reserved

frame bank

RW

frame_length_lines
BINNING_MODE = 0,1,2 Unit:1Lines
BINNING_MODE = 3
Units:2Lines

frame bank

RW

line_length_pck
Units: Pixels

RW

x_addr_startX-address of the top left corner of thevisible pixel data
Units: Pixels

RW

x_addr_end
X-address of the bottom right corner ofthe visible pixel data Units: Pixels

RW

y_addr_startY-address of the top left corner of thevisible pixel data
Units: Lines

frame bank

RW

y_addr_end
X-address of the bottom right corner ofthe visible pixel data Units: Pixels

frame bank

RW

output image size (Y-direction)
Height of image data output from thesensor module Units: Lines

frame bank

RW

output image size (Y-direction)
Height of image data output from thesensor module Units: Lines

frame bankframe bankframe bankframe bank

0

○

0A

○

A8

○

0D

○

78

○

0

○

00

○

C

○

CF

○

0

○

00

○

9

○

9F

○

C

○

D0

○

9

○

A0

○

frame bank

1

○

1

○

0

○

0

○

0x0270[2:0]

X_ODD_INC_B

RW

x_odd_inc
Increment for odd pixels 1, 3

0x0271[2:0]

Y_ODD_INC_B

RW

y_odd_inc
Increment for odd pixels 1, 3

frame bank[0]

IMG_ORIENTATION_B[0]

RW

[1]

IMG_ORIENTATION_B[1]RW

image_orientation
bit[0]: hori. direction, bit[1]: vert.
directionframe bank

0x0273―

Reserved

0x0274[1:0]

BINNING_MODE_H_B

RW

defines binning mode (H-direction).
0: no-binning, 1: x2-binning,
2: x4-binning, 3: x2-analog (special)binning

frame bank0○0x0275[1:0]

BINNING_MODE_V_B

RW

defines binning mode (V-direction).
0: no-binning, 1: x2-binning,
2: x4-binning, 3: x2-analog (special)binning

frame bank0○0x0276[0]

BINNING_CAL_MODE_H_B

RW

defines binning mode (H-direction).
0: average, 1: sumframe bank0○frame bank0○0x02720x0277[0]

BINNING_CAL_MODE_V_B

RW

defines binning mode (V-direction).
0: average, 1: sum

0x0289[7:0]

ANA_GAIN_GLOBAL_SHORT_B

RW

Analog gain (short exposure)frame bank

00

○

[7:0]

COARSE_INTEG_TIME_SHO
RT_B [15:8]

RW

Coarse integ time (short exposure)frame bank01○

0x028A32

IMX219PQH5-C

Index

Byte

Register Name

0x028B[7:0]

COARSE_INTEG_TIME_SHO
RT_B [7:0]0x028C[7:0]

CSI_DATA_FORMAT_B [15:8]

0x028D[7:0]

CSI_DATA_FORMAT_B [7:0]

Default
(HEX)

Embd
DL

F4

○

0A

○

0A

○

Default
(HEX)

Embd
DL

vt_pix_clk_div
Video Timing Pixel Clock Divider Value

05

○

RW

vt_sys_clk_div
Video Timing System Clock Divider Value

1

○

RW

pre_pll_clk_vt_div
Pre PLL clock Video Timing System Divider
Value
values:Integer-N mode :prepllck_vt_div = 1, 2, 3
For example
1: EXCK_FREQ 6 MHz to 12 MHz
2: EXCK_FREQ 12 MHz to 24 MHz
3: EXCK_FREQ 24 MHz to 27 MHz

V-sync2○

RW

pre_pll_clk_op_div
Pre PLL clock Output System Divider Value
values:Integer-N mode :prepllck_vt_div = 1, 2, 3
For example
1: EXCK_FREQ 6 MHz to 12 MHz
2: EXCK_FREQ 12 MHz to 24 MHz
3: EXCK_FREQ 24 MHz to 27 MHz

V-sync2○

RW

pll_vt_multiplier
PLL Video Timing System multiplier Value

V-syncRW

Comment

RW

CSI-2 data format

Re-Timeframe bank3-2-5 Set-up Registers – [0x0300-0x0627]
3-2-5-1 Clock Set-up Registers – [0x0300-0x0313]
Index

Byte

Register Name

RW

0x0300――RW

0x0301[4:0]

0x0302―0x0303[1:0]

0x0304[7:0]

VTPXCK_DIV―VTSYCK_DIVPREPLLCK_VT_DIV

RW

[7:0]

PREPLLCK_OP_DIV

0x0306[2:0]

PLL_VT_MPY[10:8]

0x0307[7:0]

PLL_VT_MPY[7:0]0x0308―――0x0309[4:0]

OPPXCK_DIV

RW

0x030A――

RW

0x030B[1:0]

OPSYCK_DIV

0x030C[2:0]

PLL_OP_MPY[10:8][7:0]

PLL_OP_MPY[7:0]

Re-TimeRW

0x03050x030D

Comment

0

○

75

○

op_pix_clk_div
Output Pixel Clock Divider Value

0A

○

RW

op_sys_clk_div
Output System Clock Divider Value1○

pll_op_multiplier
PLL Output System multiplier Value

0

○

RW

75

○

33

V-syncIMX219PQH5-C

3-2-5-2 Flash Control (ERS) Registers – [0x0320-0x0338]
Byte

Register Name

RW

0x0320[0]FLASH_START_TRIG

RW

Flash strobe start trigger for ERS mode.

00x0321[0]

FLASH_STATUS

RO-D

Flash status signal

00x0322[7:0]

FLASH_STROBE_DIV[7:0]

RWInternal divider for checking timing of
flash strobe.

01

0x0324[1:0]

FLASH_STROBE_OUTPUT_ENABLE

RW

Flash strobe output enable.
[0] ERS mode [1] reserved

00x032E[1:0]

FLASH_MODE

RW

Flash strobe mode setting for ERS mode.
0: shutter sync (single),
1: shutter sync (continuous mode),
2: vcnt sync (single)

00x032F[0]

FLASH_REF_MODE

RW

Flash strobe reference point setting for
ERS mode.
exposure (0) or read-out (1)00x0330[7:0]

FLASH_STROBE_
REF[15:8]

RW

Start point of flash strobe control.

0x0331[7:0]

FLASH_STROBE_
REF[7:0]0x0332[7:0]

FLASH_STROBE_LATENCY_RS[15:8]

0x0333[7:0]

FLASH_STROBE_LATENCY_RS[7:0]0x0334[7:0]

FLASH_STROBE_
HI_PERIOD_RS[15:8]

0x0335[7:0]

FLASH_STROBE_
HI_PERIOD_RS[7:0]0x0336[7:0]

FLASH_STROBE_
LO_PERIOD_RS[15:8]

0x0337[7:0]

FLASH_STROBE_
LO_PERIOD_RS[7:0]0x0338[7:0]

FLASH_STROBE_
COUNT_RS

Comment

Re-TimeDefault
(HEX)

Index

Embd
DL

○

00
00

RW

00

Latency control of flash strobe in ERS
mode

00
00

RW

active period of flash strobe in ERS mode
01

RW

RW

00

interval between active period of flash
strobe in ERS mode

01

Number of events in which flash strobe isasserted.

01

3-2-5-3 Even increment Registers – [0x0381-0x0383]
Index

Byte

0x0381[2:0]

0x0382―0x0383[2:0]

Register Name

X_EVN_INC―
Y_EVN_INC

Re-TimeDefault

RW

CommentROx_even_inc
Increment for even pixels

01

y_even_inc
Increment for even pixels

01

(HEX)

Embd
DL

―
RO

3-2-5-4 Integration Time Registers – [0x0388-0x0389]
Index

Byte

0x0388[7:0]

Register Name

RW

FINE_INTEG_TIME[15:8][7:0]

Re-TimeDefault
(HEX)
01

RO-D
0x0389Comment

fine_integration_time

FINE_INTEG_TIME[7:0]

F4

34

Embd
DL

IMX219PQH5-C

3-2-5-5 Test Pattern Registers – [0x0600-0x0627]
Index

Byte

0x0600[0]Register Name

RW

0x0601[7:0]

0x0602[1:0]

TD_R[9:8]

0x0603[7:0]

TD_R[7:0]

0x0604[1:0]

TD_GR[9:8]RW

0x0605[7:0]

TD_GR[7:0]0x0606[1:0]

TD_B[9:8]

test_pattern_mode

V-sync0

test_data_red
0
test_data_greenR00
0RW
0x0607[7:0]

TD_B[7:0]

0x0608[1:0]

TD_GB[9:8]0x0609[7:0]

TD_GB[7:0]0x060A[7:0]

H_CUR_WIDTH[15:8]

test_data_blue
00
0

RW

test_data_greenB00
0RW
0x060B[7:0]

H_CUR_WIDTH[7:0]0x060C[7:0]

H_CUR_POS[15:8]

0x060D[7:0]

H_CUR_POS[7:0]0x060E[7:0]

V_CUR_WIDTH[15:8]

0

[7:0]

V_CUR_WIDTH[7:0]0x0610[7:0]

V_CUR_POS[15:8]

horizontal_cursor_position
00
0RW
0x060Fhorizontal_cursor_width00

RW

vertical_cursor_width
00
0

RW

vertical_cursor_position

V_CUR_POS[7:0]0x0612――0x0620[3:0]

TP_WINDOW_X_OFFSET[11:8]

00
―
0
RW

0x 0621[7:0]

TP_WINDOW_X_OFFSET[7:0]0x 0622[3:0]

TP_WINDOW_Y_OFFSET[11:8]

0x 0623[7:0]

TP_WINDOW_Y_OFFSET[7:0]0x 0624[3:0]

TP_WINDOW_WIDTH[11:8]

0

[7:0]

TP_WINDOW_WIDTH[7:0]0x 0626[3:0]

TP_WINDOW_HEIGHT[11:8]

test_pattern_window_y_offset
00
0RW
0x 0625

test_pattern_window_x_offset
00

RW

test_pattern_window_width
00
0

RW
[7:0]

(HEX)

00
RW

0x 0627

Default

00
RW

[7:0]

Re-Time0
test_pattern_mode

0x0611

Comment

test_pattern_window_height

TP_WINDOW_HEIGHT[7:0]

00

35

Embd
DL

IMX219PQH5-C

3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static)
3-3-1 Integration Time and Gain Parameter Limit Registers – [0x1000-0x1301]
3-3-1-1 Integration Time Parameter Limit Registers – [0x1000-0x1007]
Index

Byte

0x1000―0x1001[0]0x1002―0x1003―0x1004[7:0]

Register Name

integration_time_capability

0x1005[7:0]

0x1006[7:0]

0x1007

[7:0]

RW

RO

Reserved

ROcoarse_integration_time_min

ROComment

Re-Time0 – coarse integration but NO fine
integration

Default
(HEX)

Embd
DL

0

00
Format: 16-bits unsigned integer
01
coarse_integration_time_max_
marginRO(Current frame length – current max coarse
exp)

00

Format: 16-bits unsigned integer04

3-3-1-2 Digital Gain Parameter Limit Registers – [0x1080-0x1089]
Index

Byte

Register Name

0x1080――0x1081[0]0x1082―

RW

RO

0x1083―0x1084[7:0]

digital_gain_capability[7:0]

0x1086

[7:0]
[7:0]

0x1088[7:0]
digital_gain_step_size

0x1089Default
(HEX)

1

RO
00

digital_gain_max
0x1087

1 – per channel digital gain *Re-Time00
Reserved

digital_gain_min
0x1085

Comment

[7:0]

RO

RO

RO

Minimum recommended digital gain value
Format: 16-bit unsigned 8.8 fixed point
number01

Maximum recommended digital gain value
Format: 16-bit unsigned 8.8 fixed point
number0F

Digital gain step size
Format: 16-bit unsigned 8.8 fixed point
number* Only a setup common to channel

36

00

FF
00
01

Embd
DL

IMX219PQH5-C

3-3-1-3 Pre-PLL and PLL Clock Set-up Capability Registers – [0x1100-0x111F]
Index

Byte

0x1100[7:0]

0x1101

Register Name

[7:0]

0x1102[7:0]

0x1103[7:0]

0x1104[7:0]

0x1105[7:0]

0x1106[7:0]

0x1107[7:0]

0x1108

[7:0]
[7:0]
[7:0]
[7:0]

0x110C

[7:0]

(HEX)

RO

Minimum external clock frequency
Format: IEEE 32-bit float
Units: MHz
6 MHz ( = min_ext_clk_freq_mhz)

C0
00

RO

Maximum external clock frequency
Format: IEEE 32-bit float Units: MHz
27 MHz ( = max_ext_clk_freq_mhz)

D8
00
00

max_pre_pll_clk_div
0x110B

Default41

min_pre_pll_clk_div
0x1109Re-Time00

max_ext_clk_freq_mhz

0x110A

Comment40
min_ext_clk_freq_mhz

0x110D

RW

RO

RO

Minimum Pre PLL divider value
Format: 16-bit unsigned integer

00

Maximum Pre PLL divider value
Format: 16-bit unsigned integer

00

01

0D
40

[7:0]
min_pll_ip_freq_mhz

RO

Minimum PLL input clock frequency
Format: IEEE 32-bit float Units: MHz
6 MHz

C0

0x110E[7:0]

0x110F[7:0]00

0x1110[7:0]41

0x1111[7:0]
max_pll_ip_freq_mhz

0x1112[7:0]

0x1113[7:0]

0x1114

[7:0]
[7:0]

0x1116[7:0]
max_pll_multiplier

0x1117[7:0]

0x1118[7:0]

0x1119[7:0]

0x111A[7:0]

0x111B[7:0]

0x111C

[7:0]
[7:0]

0x111E[7:0]

0x111F

[7:0]

D8
00

RO

RO

Minimum PLL multiplier
Format: 16-bit unsigned integer

00

Maximum PLL Multiplier
Format: 16-bit unsigned integer

07
FF

Minimum PLL output clock
frequency Format: IEEE 32-bit float

D8

Units: MHz
432 MHz000843
min_pll_op_freq_mhz

0x111D

Maximum PLL input clock frequency
Format: IEEE 32-bit float Units: MHz
27 MHz ( = max_ext_clk_freq_mhz)

00
min_pll_multiplier

0x1115

RO

00

RO

00
44
max_pll_op_freq_mhz

ROMaximum PLL output clock frequency
Format: IEEE 32-bit float
Units: MHz
916 MHz

65
00
00

37

Embd
DL

IMX219PQH5-C

3-3-1-4 Read Domain Clock Set-up Capability Registers – [0x1120-0x1137]
Index

Byte

0x1120[7:0]

Register Name

min_vt_sys_clk_div
0x1121[7:0]

0x1122[7:0]
max_vt_sys_clk_div

0x1123[7:0]

0x1124[7:0]

0x1125RW

RO

RO

Comment

Re-TimeDefault(HEX)

Minimum video timing system clock divider
value
Format: 16-bit unsigned integer

00

Maximum video timing system clock divider
value
Format: 16-bit unsigned integer

00

01

02
43

[7:0]
min_vt_sys_clk_freq_mhz

RO

Minimum video timing system clock frequency
Format: IEEE 32-bit float Units: MHz
200 MHz48

0x1126[7:0]

0x1127[7:0]00

0x1128[7:0]

440x1129[7:0]
max_vt_sys_clk_freq_mhz

0x112A[7:0]

RO

Maximum video timing system clock frequency
Format: IEEE 32-bit float Units: MHz
700 MHz00

2F00

0x112B[7:0]00

0x112C[7:0]42

0x112D[7:0]
min_vt_pix_clk_freq_mhz

0x112E[7:0]

0x112F[7:0]

0x1130[7:0]

0x1131[7:0]

0x1132[7:0]

0x1133[7:0]

0x1134

[7:0]
[7:0]
[7:0]
[7:0]

00

RO

Maximum video timing pixel clock frequency
Format: IEEE 32-bit float Units: MHz
140 MHz0C
00
00

max_vt_pix_clk_div
0x1137A0

43

min_vt_pix_clk_div
0x1136

Minimum video timing pixel clock frequency
Format: IEEE 32-bit float Units: MHz
80 MHz00

max_vt_pix_clk_freq_mhz

0x1135

RO

RO

RO

Minimum video timing pixel clock divider value
Format: 16-bit unsigned integer

00

Maximum video timing pixel clock divider value
Format: 16-bit unsigned integer

00

38

05

05

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DL

IMX219PQH5-C

3-3-1-5 Frame Timing Parameter Limit Registers – [0x1140-0x114B]
Index

Byte

0x1140[7:0]

0x1141[7:0]

0x1142[7:0]

0x1143[7:0]

0x1144[7:0]

0x1145[7:0]

0x1146[7:0]

Register Name

min_frame_length_
lines

RO

max_frame_length_
lines

RO

min_line_length_pck

RO

max_line_length_pck
0x1147[7:0]

0x1148[7:0]
min_line_blanking_pck

0x1149[7:0]

0x114A[7:0]
min_frame_blanking_lines

0x114B

RW

RO

RO

RO

[7:0]

Comment

Re-TimeMinimum Frame Length allowed. Value
both sensor dependent
Format: 16-bit unsigned integer Units:
Lines
Maximum possible number of lines per
Frame. Value sensor dependent
Format: 16-bit unsigned integer Units:
Lines
Minimum Line Length allowed. Value
sensor dependent. But setup is possible at asmaller value *Format: 16-bit unsigned integer Units: Pixel
Clock
Maximum possible number of pixel clocks
per line. Value sensor dependent
Format: 16-bit unsigned integer Units: Pixel
Clock

Default
(HEX)

Embd
DL

01
00
FF
FE
0D
78
7F
F0

Minimum line blanking time in pixel clocks
Format: 16-bit unsigned integer Units: Pixel
Clock
Minimum frame blanking in video timinglines
Format: 16-bit unsigned integer Units: Pixel
Clock

00
A8
00
20

* possible to setup up to D60 (HEX)
3-3-1-6 Output Clock Set-up Capability Registers – [0x1160-0x1177]
Index

Byte

0x1160[7:0]

Register Name

min_op_sys_clk_div
0x1161[7:0]

0x1162[7:0]
max_op_sys_clk_div

0x1163[7:0]0x1164[7:0]

0x1165[7:0]

Comment

Minimum output system clock divider value
Format: 16-bit unsigned integer

00

RO

Maximum output system clock divider value
Format: 16-bit unsigned integer

00

RO

Re-TimeDefault
(HEX)

RW

01

02
43

min_op_sys_clk_freq_mhz

RO

Minimum output system clock frequency
Format: IEEE 32-bit float
Units: MHz
200 MHz48

0x1166[7:0]

0x1167[7:0]00

0x1168[7:0]

440x1169[7:0]
max_op_sys_clk_freq_mhz

ROMaximum output system clock frequency
Format: IEEE 32-bit float Units: MHz
916 MHz00650x116A[7:0]

0x116B

[7:0]00

0x116C[7:0]41

0x116D[7:0]

0x116E[7:0]

0x116F[7:0]

0x1170[7:0]

min_op_pix_clk_freq_mhz

0x1171[7:0]

0x1172[7:0]

0x1173[7:0]

0x1174[7:0]

0x1175[7:0]

0x1176

[7:0]

A0
00

42
RO

Maximum output pixel clock frequency
Format: IEEE 32-bit float Units: MHz
114.5 MHz

E5
00
00

min_op_pix_clk_div

max_op_pix_clk_div[7:0]

Minimum output pixel clock frequency
Format: IEEE 32-bit float Units: MHz
20 MHz00

max_op_pix_clk_freq_mhz

0x1177

RO

20

RO

RO

Minimum output pixel clock divider value
Format: 16-bit unsigned integer

00

Maximum output pixel clock divider value
Format: 16-bit unsigned integer

00

39

08

0A

Embd
DL

IMX219PQH5-C

3-3-1-7 Image Size Parameter Limit Registers – [0x1180-0x118F]
Index

Byte

0x1180[7:0]

Register Namex_addr_min
0x1181[7:0]

0x1182[7:0]

0x1183[7:0]

0x1184[7:0]

y_addr_min

x_addr_max
0x1185[7:0]

0x1186

[7:0]
[7:0]

0x1188[7:0]

0x1189[7:0][7:0]
min_y_output_size

0x118B[7:0]

0x118C[7:0]

0x118D[7:0]

0x118E[7:0]

0x118F[7:0]

Minimum Y-address of the addressable
pixel array Format: 16-bit unsigned integer
Value: Always 000

Maximum X-address of the addressable
pixel array Format: 16-bit unsigned integer

0CRO

min_x_output_size
0x118A

Minimum X-address of the addressable
pixel array Format: 16-bit unsigned integer
Value: Always 0

00

RO

RO

y_addr_max
0x1187

CommentRO

max_x_output_size

max_y_output_size

RO

RO

RO

Re-TimeDefault

RW

(HEX)

Embd
DL

00

00

CF
09

Maximum Y-address of the addressable
pixel array Format: 16-bit unsigned integer

9F

Minimum x output size in pixels
Format: 16-bit unsigned integer

01

Minimum y output size in pixels
Format: 16-bit unsigned integer

01

Maximum x output size in pixels
Format: 16-bit unsigned integer

0C

00

00

D0

Maximum y output size in pixels

09

Format: 16-bit unsigned integer

A0RO

3-3-1-8 Sub-Sampling Parameter Limit Registers – [0x11C0-0x11C7]
Index

Byte

0x11C0[7:0]

0x11C1[7:0]

0x11C2[7:0]

Register Name

min_even_inc

max_even_inc
0x11C3[7:0]

0x11C4[7:0]
min_odd_inc

0x11C5[7:0]

0x11C6[7:0]

Minimum Increment for even pixels
Format: 16-bit unsigned integer (static)

00

RO

Maximum increment for even pixels
Format: 16-bit unsigned integer (static)

00

Minimum Increment for odd pixels
Format: 16-bit unsigned integer (static)00

Maximum Increment for odd pixels
Format: 16-bit unsigned integer (static)00

RO

max_odd_inc
0x11C7

Comment

RO

RO

[7:0]

Re-TimeDefault

RW

(HEX)

Embd
DL

01

01

01

03

3-3-1-9 Image Compression Capability Registers – [0x1300-0x1301]
Index

Byte

0x1300―0x1301[0]Register Name―compression_capability

RW

Comment

Re-TimeDefault

Embd

(HEX)

DL

―
RO

compression_capability (support comp10to8)

401

IMX219PQH5-C

3-4 Manufacturer Specific Registers – [0x3000-0x5FFF]
To access this address area, it is necessary to send command sequence as below.

Table 11 Access command sequence
Seq. No.

Address (Hex)

data

1

30EB

05

2

30EB

0C

3

300A

FF

4

300B

FF

5

30EB

05

6

30EB

09

Register [0x3200-0x3243]
Index
(HEX)

Bit

Register Name

RW

Comment

Re-Timed

Default
(HEX)

3200

[2:0]

OTPIF_CTRL

RWOTP I/F control register[0] enable [1]R/W [2]error clear

0

3201

[1:0]

OTPIF_STATUS

RO-D

OTP I/F status; [0] read ready [1] write ready

0

3202

[7:0]

OTPIF_PAGE_SELECT

RW

otpif_page_select

0

3204

[7:0]

OTPIF_DT_0

RW

otpif_data_0

00

3205

[7:0]

OTPIF_DT_1

RW

otpif_data_1

00

3206

[7:0]

OTPIF_DT_2

RW

otpif_data_2

00

3207

[7:0]

OTPIF_DT_3

RW

otpif_data_3

00

3208

[7:0]

OTPIF_DT_4

RW

otpif_data_4

00

3209

[7:0]

OTPIF_DT_5

RW

otpif_data_5

00

320A

[7:0]

OTPIF_DT_6

RW

otpif_data_6

00

320B

[7:0]

OTPIF_DT_7

RW

otpif_data_7

00

320C

[7:0]

OTPIF_DT_8

RW

otpif_data_8

00

320D

[7:0]

OTPIF_DT_9

RW

otpif_data_9

00

320E

[7:0]

OTPIF_DT_10

RW

otpif_data_10

00

320F

[7:0]

OTPIF_DT_11

RW

otpif_data_11

00

3210

[7:0]

OTPIF_DT_12

RW

otpif_data_12

00

3211

[7:0]

OTPIF_DT_13

RW

otpif_data_13

00

3212

[7:0]

OTPIF_DT_14

RW

otpif_data_14

00

3213

[7:0]

OTPIF_DT_15

RW

otpif_data_15

00

3214

[7:0]

OTPIF_DT_16

RW

otpif_data_16

00

3215

[7:0]

OTPIF_DT_17

RW

otpif_data_17

00

3216

[7:0]

OTPIF_DT_18

RW

otpif_data_18

00

3217

[7:0]

OTPIF_DT_19

RW

otpif_data_19

00

3218

[7:0]

OTPIF_DT_20

RW

otpif_data_20

00

3219

[7:0]

OTPIF_DT_21

RW

otpif_data_21

00

321A

[7:0]

OTPIF_DT_22

RW

otpif_data_22

00

321B

[7:0]

OTPIF_DT_23

RW

otpif_data_23

00

321C

[7:0]

OTPIF_DT_24

RW

otpif_data_24

00

321D

[7:0]

OTPIF_DT_25

RW

otpif_data_25

00

321E

[7:0]

OTPIF_DT_26

RW

otpif_data_26

00

321F

[7:0]

OTPIF_DT_27

RW

otpif_data_27

00

3220

[7:0]

OTPIF_DT_28

RW

otpif_data_28

0041

IMX219PQH5-C

Index
(HEX)

Bit

Register Name

RW

Comment

Re-Timed

Default
(HEX)

3221

[7:0]

OTPIF_DT_29

RW

otpif_data_29

00

3222

[7:0]

OTPIF_DT_30

RW

otpif_data_30

00

3223

[7:0]

OTPIF_DT_31

RW

otpif_data_31

00

3224

[7:0]

OTPIF_DT_32

RW

otpif_data_32

00

3225

[7:0]

OTPIF_DT_33

RW

otpif_data_33

00

3226

[7:0]

OTPIF_DT_34

RW

otpif_data_34

00

3227

[7:0]

OTPIF_DT_35

RW

otpif_data_35

00

3228

[7:0]

OTPIF_DT_36

RW

otpif_data_36

00

3229

[7:0]

OTPIF_DT_37

RW

otpif_data_37

00

322A

[7:0]

OTPIF_DT_38

RW

otpif_data_38

00

322B

[7:0]

OTPIF_DT_39

RW

otpif_data_39

00

322C

[7:0]

OTPIF_DT_40

RW

otpif_data_40

00

322D

[7:0]

OTPIF_DT_41

RW

otpif_data_41

00

322E

[7:0]

OTPIF_DT_42

RW

otpif_data_42

00

322F

[7:0]

OTPIF_DT_43

RW

otpif_data_43

00

3230

[7:0]

OTPIF_DT_44

RW

otpif_data_44

00

3231

[7:0]

OTPIF_DT_45

RW

otpif_data_45

00

3232

[7:0]

OTPIF_DT_46

RW

otpif_data_46

00

3233

[7:0]

OTPIF_DT_47

RW

otpif_data_47

00

3234

[7:0]

OTPIF_DT_48

RW

otpif_data_48

00

3235

[7:0]

OTPIF_DT_49

RW

otpif_data_49

00

3236

[7:0]

OTPIF_DT_50

RW

otpif_data_50

00

3237

[7:0]

OTPIF_DT_51

RW

otpif_data_51

00

3238

[7:0]

OTPIF_DT_52

RW

otpif_data_52

00

3239

[7:0]

OTPIF_DT_53

RW

otpif_data_53

00

323A

[7:0]

OTPIF_DT_54

RW

otpif_data_54

00

323B

[7:0]

OTPIF_DT_55

RW

otpif_data_55

00

323C

[7:0]

OTPIF_DT_56

RW

otpif_data_56

00

323D

[7:0]

OTPIF_DT_57

RW

otpif_data_57

00

323E

[7:0]

OTPIF_DT_58

RW

otpif_data_58

00

323F

[7:0]

OTPIF_DT_59

RW

otpif_data_59

00

3240

[7:0]

OTPIF_DT_60

RW

otpif_data_60

00

3241

[7:0]

OTPIF_DT_61

RW

otpif_data_61

00

3242

[7:0]

OTPIF_DT_62

RW

otpif_data_62

00

3243

[7:0]

OTPIF_DT_63

RW

otpif_data_6300

42IMX219PQH5-C

3-5 Frame Bank A and Bank B specific output samples
Specific output examples are shown on the following pages.
Frame Bank A mode
Addr
(Hex)

Frame Bank B mode

Register Namein Byte
(Hex)

Addr
(Hex)

Line1 (Embedded Data Line)

Register Namein Byte(Hex)

Line1 (Embedded Data Line)

0x0000

MODEL_ID[15:8]

X20x0000

MODEL_ID[15:8]

X20x0001

MODEL_ID[7:0]190x0001

MODEL_ID[7:0]190x0002FABRICATION_TOP

XX

0x0002FABRICATION_TOP

XX

0x0004

LOT_ID_TOP[23:16]

XX

0x0004

LOT_ID_TOP[23:16]

XX

0x0005

LOT_ID_TOP[15:8]

XX

0x0005

LOT_ID_TOP[15:8]

XX

0x0006

LOT_ID_TOP[7:0]XX

0x0006

LOT_ID_TOP[7:0]XX

0x0007

WAFER_NUM_TOP

XX

0x0007

WAFER_NUM_TOP

XX

0x000D

CHIP_NUMBER[15:8]

XX

0x000D

CHIP_NUMBER[15:8]

XX

0x000E

CHIP_NUMBER[7:0]XX

0x000E

CHIP_NUMBER[7:0]XX

0x000FPROCESS_VERSION

XX

0x000FPROCESS_VERSION

XX

0x0011

ROM_IDXX

0x0011

ROM_IDXX

0x0018

FRM_CNT[7:0]XX

0x0018

FRM_CNT[7:0]XX

0x0019PX_ORDER

XX

0x0019PX_ORDER

XX

0x001A

DT_PEDESTAL[9:8]XX0x001A

DT_PEDESTAL[9:8]XX0x001B

DT_PEDESTAL[7:0]XX

0x001B

DT_PEDESTAL[7:0]XX

0x0040

FRM_FMT_TYPE[7:0]XX

0x0040

FRM_FMT_TYPE[7:0]XX

0x0041

FRM_FMT_SUBTYPE[7:0]120x0041

FRM_FMT_SUBTYPE[7:0]120x0042

FRM_FMT_DESC0[15:8]

XX

0x0042

FRM_FMT_DESC0[15:8]

XX

0x0043

FRM_FMT_DESC0[7:0]XX

0x0043

FRM_FMT_DESC0[7:0]XX

0x0044

FRM_FMT_DESC1[15:8]

XX

0x0044

FRM_FMT_DESC1[15:8]

XX

0x0045

FRM_FMT_DESC1[7:0]XX

0x0045

FRM_FMT_DESC1[7:0]XX

0x0046

FRM_FMT_DESC2[15:8]

XX

0x0046

FRM_FMT_DESC2[15:8]

XX

0x0047

FRM_FMT_DESC2[7:0]XX

0x0047

FRM_FMT_DESC2[7:0]XX0x0100

MODE_SEL

XX

0x0100

MODE_SEL

XX

0x0103

SW_RESETXX

0x0103

SW_RESETXX

0x0104

corrupted frame status

XX

0x0104

corrupted frame status

XX

0x0105

mask_corrupted_frames

XX

0x0105

mask_corrupted_frames

XX

0x0106

fast standby enableXX

0x0106

fast standby enableXX

0x0110

CSI_CH_ID

XX

0x0110

CSI_CH_ID

XX

0x0111

CSI_SIG_MODE

00

0x0111

CSI_SIG_MODE

00

0x0114

CSI_LANE_MODE

XX

0x0114

CSI_LANE_MODE

XX

0x0140Temperature_EN, Temperature_VAL

XX

0x0140Temperature_EN, Temperature_VAL

XX

0x0142READOUT_V_CNT [15:8]

XX

0x0142READOUT_V_CNT [15:8]

XX

43

IMX219PQH5-C

Addr
(Hex)

Register Namein Byte
(Hex)

Addr
(Hex)

Register Namein Byte(Hex)

0x0143READOUT_V_CNT[7:0]XX

0x0143READOUT_V_CNT[7:0]XX

0x0150[0]: FRAME_BANK_ENABLE

XX

0x0150[0]: FRAME_BANK_ENABLE

XX

0x0151

FRAME_BANK _FRM_CNT

XX

0x0151

FRAME_BANK _FRM_CNT

XX

0x0152

FRAME_BANK _FAST_TRACKING

XX

0x0152

FRAME_BANK _FAST_TRACKING

XX

Line2 (Embedded Data Line)

Line2 (Embedded Data Line)

0x0154

FRAME_DURATION_A

XX

0x0254

FRAME_DURATION_B

XX

0x0155

COMP_ENABLE_A

XX

0x0255

COMP_ENABLE_B

XX

0x0157

ANA_GAIN_GLOBAL_A

XX

0x0257

ANA_GAIN_GLOBAL_B

XX

0x0158

DIG_GAIN_GLOBAL_A [11:8]

XX

0x0258

DIG_GAIN_GLOBAL_B[11:8]

XX

0x0159DIG_GAIN_GLOBAL_A [7:0]XX

0x0259DIG_GAIN_GLOBAL_B[7:0]XX

0x015ACOARSE_INTEGRATION_
TIME_A[15:8]

XX

0x025ACOARSE_INTEGRATION_
TIME_B[15:8]

XX

0x015BCOARSE_INTEGRATION_
TIME_A[7:0]XX

0x025BCOARSE_INTEGRATION_
TIME_B[7:0]XX

0x015DSENSOR_MODE_A

XX

0x025DSENSOR_MODE_B

XX

0x0160

FRM_LENGTH_A[15:8]

XX

0x0260

FRM_LENGTH_B[15:8]

XX

0x0161

FRM_LENGTH_A[7:0]XX

0x0261

FRM_LENGTH_B[7:0]XX

0x0162

LINE_LENGTH_A[15:8]

XX

0x0262

LINE_LENGTH_B[15:8]

XX

0x0163

LINE_LENGTH_A[7:0]XX

0x0263

LINE_LENGTH_B[7:0]XX

0x0164

X_ADD_STA_A[11:8]

XX

0x0264

X_ADD_STA_B[11:8]

XX

0x0165

X_ADD_STA_A[7:0]XX

0x0265

X_ADD_STA_B[7:0]XX

0x0166

X_ADD_END_A[11:8]

XX

0x0266

X_ADD_END_B[11:8]

XX

0x0167

X_ADD_END_A[7:0]XX

0x0267

X_ADD_END_B[7:0]XX

0x0168

Y_ADD_STA_A[11:8]

XX

0x0268

Y_ADD_STA_B[11:8]

XX

0x0169Y_ADD_STA_A[7:0]XX

0x0269Y_ADD_STA_B[7:0]XX

0x016AY_ADD_END_A[11:8]

XX

0x026AY_ADD_END_B[11:8]

XX

0x016BY_ADD_END_A[7:0]XX

0x026BY_ADD_END_B[7:0]XX

0x016Cx_output_size[11:8]

XX

0x026Cx_output_size[11:8]

XX

0x016Dx_output_size[7:0]XX

0x026Dx_output_size[7:0]XX

0x016Ey_output_size[11:8]

XX

0x026Ey_output_size[11:8]

XX

0x016Fy_output_size[7:0]XX

0x026Fy_output_size[7:0]XX

0x0170X_ODD_INC_A

XX

0x0270X_ODD_INC_B

XX

0x0171Y_ODD_INC_A

XX

0x0271Y_ODD_INC_B

XX

0x0172

IMG_ORIENTATION_A

XX

0x0272

IMG_ORIENTATION_B

XX

0x0174

BINNING_MODE_H_A

XX

0x0274

BINNING_MODE_H_B

XX

0x0175BINNING_MODE_V_A

XX

0x0275BINNING_MODE_V_B

XX

0x0176BINNING_CAL_MODE_H_A

XX

0x0276BINNING_ CAL_MODE_H_B

XX

44

IMX219PQH5-C

Addr
(Hex)

Register Namein Byte
(Hex)

Addr
(Hex)

Register Namein Byte(Hex)

0x0177BINNING_ CAL_MODE_V_A

XX

0x0277BINNING_ CAL_MODE_V_B

XX

0x0188RESERVE

XX

0x0288RESERVE

XX

0x0189ANA_GAIN_GLOBAL_SHORT_A

XX

0x0289ANA_GAIN_GLOBAL_SHORT_B

XX

0x018ACOARSE_INTEG_TIME_SHORT_A [15:8]

XX

0x028ACOARSE_INTEG_TIME_SHORT_B [15:8]

XX

0x018BCOARSE_INTEG_TIME_SHORT_A [7:0]XX

0x028BCOARSE_INTEG_TIME_SHORT_B [7:0]XX

0x018CCSI_DATA_FORMAT_A [15:8]

XX

0x028CCSI_DATA_FORMAT_B [15:8]

XX

0x018D

CSI_DATA_FORMAT_A [7:0]XX

0x028D

CSI_DATA_FORMAT_B [7:0]XX

0x0190LSC_ENABLE_A

XX

0x0290LSC_ENABLE_B

XX

0x0191

LSC_COLOR_MODE_A

XX

0x0291

LSC_COLOR_MODE_B

XX

0x0192

LSC_SELECT_TABLE_A

XX

0x0292

LSC_SELECT_TABLE_B

XX

0x0193

LSC_TUNING_ENABLE_A

XX

0x0293

LSC_TUNING_ENABLE_B

XX

0x0194

LSC_WHITE_BALANCE_RG_A[15:8]

XX

0x0294

LSC_WHITE_BALANCE_RG_B[15:8]

XX

0x0195

LSC_WHITE_BALANCE_RG_A[7:0]XX

0x0295

LSC_WHITE_BALANCE_RG_B[7:0]XX

0x0196RESERVE

XX

0x0296RESERVE

XX

0x0197RESERVE

XX

0x0297RESERVE

XX

0x0198

LSC_TUNING_COEF_R_A

XX

0x0298

LSC_TUNING_COEF_R_B

XX

0x0199

LSC_TUNING_COEF_GR_A

XX

0x0299

LSC_TUNING_COEF_GR_B

XX

0x019A

LSC_TUNING_COEF_GB_A

XX

0x029A

LSC_TUNING_COEF_GB_B

XX

0x019B

LSC_TUNING_COEF_B_A

XX

0x029B

LSC_TUNING_COEF_B_B

XX

0x019C

LSC_TUNING_R_A[12:8]

XX

0x029C

LSC_TUNING_R_B[12:8]

XX

0x019D

LSC_TUNING_R_A[7:0]XX

0x029D

LSC_TUNING_R_B[7:0]XX

0x019E

LSC_TUNING_GR_A[12:8]

XX

0x029E

LSC_TUNING_GR_B[12:8]

XX

0x019F

LSC_TUNING_GR_A[7:0]XX

0x029F

LSC_TUNING_GR_B[7:0]XX0x01A0

LSC_TUNING_GB_A[12:8]

XX

0x02A0

LSC_TUNING_GB_B[12:8]

XX

0x01A1

LSC_TUNING_GB_A[7:0]XX0x01A1

LSC_TUNING_GB_B[7:0]XX0x01A2

LSC_TUNING_B_A[12:8]

XX

0x01A2

LSC_TUNING_B_B[12:8]

XX

0x01A3

LSC_TUNING_B_A[7:0]XX0x01A3

LSC_TUNING_B_B[7:0]XX0x01A4

LSC_KNOT_POINT_FORMAT_A

XX

0x01A4

LSC_KNOT_POINT_FORMAT_B

XX

0x0301VTPXCK_DIV

XX

0x0301VTPXCK_DIV

XX

0x0303VTSYCK_DIV

XX

0x0303VTSYCK_DIV

XX

0x0304

PREPLLCK_VT_DIV

XX

0x0304

PREPLLCK_VT_DIV

XX

0x0305

PREPLLCK_OP_DIV

XX

0x0305

PREPLLCK_OP_DIV

XX

0x0306

PLL_VT_MPY[10:8]

XX0x0306

PLL_VT_MPY[10:8]

XX0x0307

PLL_VT_MPY[7:0]XX

0x0307

PLL_VT_MPY[7:0]XX

0x0309OPPXCK_DIV

XX

0x0309OPPXCK_DIVXX

45

IMX219PQH5-C

Addr
(Hex)

Register Namein Byte
(Hex)

Addr
(Hex)

Register Namein Byte(Hex)

0x030BOPSYCK_DIV

XX

0x030BOPSYCK_DIV

XX

0x030C

PLL_OP_MPY[10:8]

XX0x030C

PLL_OP_MPY[10:8]

XX0x030D

PLL_OP_MPY[7:0]XX

0x030D

PLL_OP_MPY[7:0]XX

0x030ERESERVE

XX

0x030ERESERVE

XX

0x0318RESERVE

XX

0x0318RESERVE

XX

0x0319RESERVE

XX

0x0319RESERVE

XX

0x031ARESERVE

XX

0x031ARESERVE

XX

0x031BRESERVE

XX

0x031BRESERVE

XX

0x031CRESERVE

XX

0x031CRESERVE

XX

0x031DRESERVE

XX

0x031DRESERVE

XX

0x031ERESERVE

XX

0x031ERESERVE

XX

0x031FRESERVE

XX

0x031FRESERVE

XX

0x0321

FLASH_STATUS

XX

0x0321

FLASH_STATUS

XX

46

IMX219PQH5-C

4. Output Data Format
4-1 CSI-2 Output Data Format
4-1-1 CSI-2 Output Data Channels
The IMX219PQH5-C can select the CSI-2 2 lanes or CSI-2 4 lanes serial signal output method that uses all pairsof differential signals for image data output.

Table 12 Number of CSI lane Setting Registers
Index

Byte

Register Name

RW

0x0114[1:0]

CSI_LANE_MODE

RW

Comment

Default(HEX)

03: 4Lane03

01: 2Lane

RemarkSetting before“standby cancel”

4-1-2 CSI-2 Frame Structure
The image frame structure is shown below.

FS
PH

Embedded Data Lines

PF

PacketHeaderPixels(effective pixels)

PacketFooterline blanking

FEframe blanking

FS

Next Frame

Fig. 20 Frame Structure for Serial signal output

47

IMX219PQH5-C

Line Blanking
Clock
Lane
Disconnect
Terminator

Data
Lane
LP-11

LP-01 LP-00

Fig. 21 Signaling Waveform during Line Blanking Period (CSI-2)

Frame Blanking

Clock
Lane

Disconnect
Terminator

Data
Lane
LP-11

LP-01 LP-00

Fig. 22 Signaling Waveform during Frame Blanking Period (CSI-2)

4-1-3 Short Packet & Long Packet
Short Packet

Long Packet

PH

PH

4byte

4byte

Frame Count Number

Payload Data

PF

Number of Visible Horizontal Pixels

ECC

Data ID

Word Count

1byte

1byte

2byte

Data ID

Word Count

1byte

2byte

VC

Data Type

VC

Data Type

2bit

6bit

2bit

6bit

ECC
1byte

Fixed Register Value

Fig. 23 Short Packet & Long Packet

48

CRC
2byte

IMX219PQH5-C

4-1-4 Data type
Data types of each line are shown as below.

Table 13 Image pixel area and data typeimage pixel area

Data Type

Embedded Data Lines

Embedded Data

OBside ineffective area

Null

OB area for internal use

Nulleffective OB

OPB Data

Effective area side ineffective area

Nulleffective pixel

RAW10 or RAW8 or COMP8

4-1-5 CSI-2 Frame Format
The data format of each line is based on CSI-2 General Frame Format.
The period from a line end sync code to the line start sync code for the next line is called the line blanking period.
Likewise, the period from a frame end sync code to the next frame start sync code is called the frame blanking
period. Packet header consists of the following data.

Table 14 Sync Code Settings
Header[7:0]

Description

Setting register

Remarks

Addr: 0x0110[7:6]

Virtual Channel Identifier

See Register Section
CSI_channel_identifier[5:0]

Synch Short Packet Data types

NA

6’h00

Frame Start Code

NA

6’h01

Frame End Code

NA

6’h12

Embedded DataNA

Written data in the sensor

6’h2A

RAW8

CSI_data_format

16’h0808

6’h2B

RAW10

CSI_data_format

16’h0A0A

49

IMX219PQH5-C

4-1-6 CSI-2 Embedded Data LineThe value of the 2-wire serial communication configuration register can be output at the start of the frame. The
output register is indicated in the “Embd DL” column of the 2-wire serial communication Register Map.
The Embedded data line is output in the two lines following the sync code FS.

FS
PH

Embedded Data Lines

PF

PacketHeaderPixels(effective pixels)

PacketFooterFE

Fig. 24 Frame Format during Embedded Data Line Output
The output method differs according to the data format.
In RAW10 mode, dummy bytes are inserted after outputting 4 bytes of data and tags.

RAW8 (top 8bit, 10b-8b compress) mode

Simplified 2-Byte Tagged Data Format

Data Format Code

Packet Header

0A

Tag Data Tag Data Tag Data Tag Data 07

07

07

07

07

Packet Footer

Padding CharactersFig. 25 Embedded data lines alignment in RAW8 mode

RAW10 mode Simplified 2-Byte Tagged Data Format
Data Format Code

Packet Header

55h Dummy Bytes

0A Tag Data Tag 55 Data Tag Data 07

55h Dummy Bytes

55

07

07

07

55

Packet Footer

Padding CharactersFig. 26 Detailed Embedded Data Line Output in RAW10 Output Mode50

IMX219PQH5-C

The end of the address and register value is determined according to the tags embedded in the data.

Table 15 Embedded Data Line Tag
Tag

Data Byte Description

00h

Illegal Tag. If found treat as end of Data

07h

End of Data (Data Byte Value = 07H)aah

CCI Register Index MSB [15:8]

a5h

CCI Register Index LSB [7:0]5ahAuto increment the CCI index after the data byte - valid data
Data byte contains valid CCI register data

55hAuto increment the CCI index after the data byte - null dataA CCI register does NOT exist for the current CCI index.
The data byte value is the 07H

ffh

Illegal Tag. If found treat as end of Data

51

IMX219PQH5-C

5.

Setting Required for Imaging

5-1 Pixel Array Physical Image
Pixel array physical image is shown below. It is the pixel array when upper right corner of the physical image is Pin 1.
The IMX219PQH5-C has vertical OB area, which cannot read out. Readout position is explained by Readout Position
sessionInvalid Active area （8）InValid Active Area (8)OPB Invalid Area（16）Effective OPB（16）OPB Invalid Area （8）Fig. 27 Pixel Array Physical Image

52

Invalid Active area （8）Effective Area 2480(V)Active Area 3280 (H)Active Area 2464(V)Invalid Active area （8）Effective Area 3296（H)IMX219PQH5-C

5-2 Pixel Binning Mode
Binning read-out can be used to obtain an image of lower resolution for full field of view. It has advantage on frame
rate than using digital scaling, and on signal-to-noise ratio than using sub-sampling. See Binning Capability Registers,for detail of available configurations.
The following diagram describes on 2x2 averaged binning operations. Pixels of two adjacent rows and columns areaveraged, and read out as one output pixel.
[ Image of full pixels][ Output image of2x 2 averaged binning]
Gb(0,7)

0

1

2

3

4

5

6

7

B(7,7)
7

average0
6

1

2( {B(1,1)+B(1,3)}/2+ { B(3,1)+B(3,3)}/ 2 )/2

5

3

3

average2
4
1( { Gb(0,1)+ Gb (0,3)}/2+{Gb(2,1)+Gb(2,3)}/ 2 )/2

3

average0

2

1( { R(0,0)+R(0,2)}/2+{R(2,0)+R(2,2)}/ 2 )/2

average0

Gr(7,0)averageaverageaverageaverageR(0,0)

Readout direction( {Gr(1,0)+Gr(1,2)}/2+ { Gr(3,0)+Gr(3,2)}/ 2 )/2

Readout direction

Description of pixels in the figure
Pixels with bold lines: Pixels read out as binned image

Other pixels: Pixels just used for averaging

Fig. 28 Image of 2x2 averaged Binning Mode
For explanation, represent individual pixels with it's addresses in the format “color (x, y) ” - for example, The Red
pixel in the lower left corner is expressed as R (0, 0).
By performing 2x2 binning, R (0, 0) after binning is obtained by the following equation.
R (0, 0) after binning = ( {R (0, 0) + R (0, 2)} /2 + {R (2,0) + R (2,2)} /2 ) / 2
And, the total number of output pixels is reduced to 1/4 of the original pixel array.
Settings mode example

Table 16 Mode example

Mode

Full

x2binningx4binning

Frame rate

30 frame/s

120 frame/s

120 frame/s

H binning―

AnalogDigital

H

x1

x2

X4

V

x1

x2

x4

53

IMX219PQH5-C

5-3 image size
The relation of image output size and the register is shown below.

Fig. 29 Image size54

IMX219PQH5-C

5-4 Readout Position
The IMX219PQH5-C default status is readout from the lower left corner when Pin 1 is located in the upper rightcorner. The image is inverted vertically and horizontally by the lens, so proper image output results when Pin 1 islocated in the upper right corner.

1PIN

F

F
Lens

image_orientation=0h

Fig. 30 Readout Position
Readout direction can be set by the registers.

Table 17 Image Orientation Register
image_orientation
[0]

Mode

0

no mirror (Readout from the left with Pin 1 in the upper right corner)

1

Horizontal Mirror (Readout from the right with Pin 1 in the upper right corner)

image_orientation
[1]

Mode

0

no flip (Readout from the bottom with Pin 1 in the upper right corner)

1

Vertical Flip (Readout from the top with Pin 1 in the upper right corner)

CCI register

SONY

SO
NY

SONY

SO
NY

SONY

image_orientation=1h

image_orientation=2h

image_orientation=3h

SO
NY

Fig. 31 Output Image Diagrams for Vertical Flip and Horizontal Mirror

55

IMX219PQH5-C

5-5 Frame Rate Calculation Formula
Frame rate in all-pixel scan mode is calculated by the followings.
Frame

ate frame/s

ime Per Line [sec]1
ime per Line[sec](Frame Length)Line Length pck[pix]2

Pix Clock Freq[MHz][ In the case of (frame_length_lines - 4 > coarse_integration_time) ]: Frame_Length = frame_length_lines[ In the case of (frame_length_lines - 4 < coarse_integration_time) ]: Frame_Length = coarse_integration_time + 4

5-6 Black Level Control
The IMX219PQH5-C has a stable black level clamp function. The average value of the black level is adjusted to 64d.
When selecting output format RAW8, Black level in the table below is divided by 4.

Table 18 Gain Setting Variables
CCI

Black Level (dec)
64 (Fixed) RAW10, COMP8
16 (Fixed) RAW8

5-7 Storage Time (Electronic Shutter) Settings
5-7-1 Storage Time (Electronic Shutter) Setting Registers
The storage time setting registers are shown below. The value of the register, coarse_integration_time, indicatesthe number of lines for the storage time.
The maximum storage time value in normal frame rate mode is obtained by subtracting “4” from the number oflines per frame (set by frame_length_lines) including the blanking period.

CCI
registers

Table 19 Storage Time Setting Register
Register name

Addresscoarse_integration_time

0x015A
0x015B
0x025A
0x025B

Setting value (dec)Remarks

1 to frame_length_lines-4

0x015A = coarse_integration_time_A[15:8]
0x015B = coarse_integration_time_A[7:0]0x025A = coarse_integration_time_B[15:8]
0x025B = coarse_integration_time_B[7:0]

The value of the register, fine_integration_time, indicates the number of pixels for the storage time.
The register, fine_integration_time, is a fixed value, read only register.

CCI
registers

Table 20 Storage Time Offset Register
Register name

Address

Setting value (dec)fine_integration_time

0x03880x0389500

56Remarks
RO registerIMX219PQH5-C

5-7-2 Storage Time Calculation Method
The storage time (TSH) can be obtained from the following equation.
TSH = ( Coarse_Integration_Time × ime Per Line ) + (αpix_clk_period = 1/Pix_Clock_Freq [MHz]pix clk period )Where α = offset time = readdable from fine_integration_time register and obtained from the following equation.
α = fine_integration_time / 2

Table 21 Storage Time Setting (in case of Line_Length_pck = 3448)
Number of
total lines

frame_length

coarse_integration_time[15:0]

Dec

Dec

Dec

All-pixel scan[s]1(1 x 3448/2 + α) x pix clk period(determined byN(N x 3448/2 + α) x pix clk period

frame_length_lines

:

:

2724

(2724 x 3448/2 + α) x pix clk period

2728
Normal frame rate
mode
(4:3 Full-Pel Raw10)2728[15:0])

Low frame ratemodeLong-time exposure

Storage time (T SH)

2729

2729

2725

(2725 x 3448/2 + α) x pix clk period

2730

2730

2726

(2726 x 3448/2 + α) x pix clk period

:

:

:

:

2M+3

2M+3

2M-1

((2M-1) x 3448/2 + α) x pix clk period

2M+4

2M+4

2M

(2M x 3448/2 + α) x pix clk period

:

:

:

:

65534

65534

65530

(65530 x 3448/2 + α) x pix clk period57

IMX219PQH5-C

5-8 Gain Settings
Analogue gain and digital gain can be set independently.

Analogue Gain Settings
Only global analogue gain is supported.
The analogue gain is set by the following equation.
Gain analogue(m0

X + c0)(m1

X + c1)The variables are shown in the table below.

Table 22 Gain Setting Variables
Register name
CCI registers

5-8-1

Address

Remarksm0

analogue_gain_m0

0x008C/0x008D

Fixed to 0

m1

analogue_gain_m1

0x0090/0x0091

Fixed to -1

c0

analogue_gain_c0

0x008E/0x008F

Fixed to 256

c1

analogue_gain_c1

0x0092/0x0093

Fixed to 256

X

ANA_GAIN_GLOBAL_A

0x0157,0 to 232

X

ANA_GAIN_GLOBAL_B

0x02570 to 232

Therefore, the analogue gain is as follows.
Gain analogue(256)(256 - X)

The relationship between the setting value X (analogue_gain_code_global) and the gain is shown on the following
page.

58

IMX219PQH5-C

ANA_GAIN_GLOBAL

Gain(times)Gain(dB)

ANA_GAIN_GLOBAL

Gain(times)Gain(dB)

0.00
0.03
0.07
0.10
0.14
0.17
0.21
0.24
0.28
0.31
0.35
0.38
0.42
0.45
0.49
0.52
0.56
0.60
0.63
0.67
0.71
0.74
0.78
0.82
0.86
0.89
0.93
0.97
1.01
1.04
1.08
1.12
1.16
1.20
1.24
1.28
1.32
1.36
1.40
1.44
1.48
1.52
1.56
1.60
1.64
1.68
1.72
1.76
1.80
1.85
1.89
1.93
1.97
2.01
2.06
2.10
2.14
2.19
2.23
2.28
2.32
2.36
2.41
2.45

64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

1.33
1.34
1.34
1.35
1.36
1.37
1.38
1.38
1.39
1.40
1.41
1.41
1.42
1.43
1.44
1.45
1.45
1.46
1.47
1.48
1.49
1.50
1.50
1.51
1.52
1.53
1.54
1.55
1.56
1.57
1.58
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
1.70
1.70
1.71
1.73
1.74
1.75
1.76
1.78
1.79
1.80
1.81
1.83
1.84
1.85
1.87
1.88
1.89
1.91
1.92
1.94
1.95
1.97
1.98

2.50
2.54
2.59
2.64
2.68
2.73
2.77
2.82
2.87
2.92
2.96
3.01
3.06
3.11
3.16
3.21
3.25
3.30
3.35
3.40
3.45
3.50
3.56
3.61
3.66
3.71
3.76
3.82
3.87
3.92
3.97
4.03
4.08
4.14
4.19
4.25
4.30
4.36
4.41
4.47
4.53
4.59
4.64
4.70
4.76
4.82
4.88
4.94
5.00
5.06
5.12
5.18
5.24
5.30
5.37
5.43
5.49
5.56
5.62
5.69
5.75
5.82
5.89
5.95

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191

2.00
2.02
2.03
2.05
2.06
2.08
2.10
2.11
2.13
2.15
2.17
2.19
2.20
2.22
2.24
2.26
2.29
2.30
2.32
2.35
2.37
2.39
2.41
2.44
2.46
2.48
2.51
2.53
2.56
2.58
2.61
2.64
2.66
2.69
2.72
2.75
2.78
2.81
2.84
2.88
2.91
2.94
2.98
3.01
3.05
3.08
3.12
3.16
3.20
3.24
3.28
3.32
3.37
3.41
3.46
3.50
3.55
3.61
3.66
3.71
3.76
3.82
3.88
3.94

6.02
6.09
6.16
6.23
6.30
6.37
6.44
6.51
6.58
6.65
6.73
6.80
6.88
6.95
7.03
7.10
7.18
7.26
7.34
7.42
7.50
7.58
7.66
7.74
7.82
7.91
7.99
8.08
8.16
8.25
8.34
8.43
8.52
8.61
8.70
8.80
8.89
8.98
9.08
9.18
9.28
9.37
9.47
9.58
9.68
9.78
9.89
10.00
10.10
10.21
10.32
10.43
10.55
10.66
10.78
10.90
11.02
11.14
11.26
11.39
11.51
11.64
11.77
11.91

59

Gain(dB)Gain(dB)

1.00
1.00
1.01
1.01
1.02
1.02
1.02
1.03
1.03
1.04
1.04
1.04
1.05
1.05
1.05
1.06
1.07
1.07
1.07
1.08
1.08
1.09
1.09
1.10
1.10
1.11
1.11
1.12
1.12
1.13
1.13
1.14
1.14
1.14
1.15
1.16
1.16
1.17
1.17
1.18
1.18
1.19
1.20
1.20
1.21
1.21
1.22
1.22
1.23
1.23
1.24
1.25
1.25
1.26
1.27
1.27
1.28
1.29
1.29
1.30
1.30
1.31
1.32
1.32

Gain(times)Gain(times)

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

ANA_GAIN_GLOBAL

ANA_GAIN_GLOBAL

Table 23 Analogue Gain Setting

192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232

4.00
4.06
4.13
4.20
4.27
4.34
4.41
4.49
4.57
4.65
4.74
4.83
4.92
5.02
5.12
5.22
5.33
5.45
5.56
5.69
5.82
5.95
6.09
6.24
6.40
6.56
6.73
6.92
7.11
7.31
7.53
7.75
8.00
8.26
8.53
8.82
9.14
9.48
9.84
10.24
10.66

12.04
12.18
12.32
12.46
12.60
12.75
12.90
13.05
13.20
13.36
13.52
13.68
13.84
14.01
14.19
14.36
14.54
14.72
14.91
15.10
15.30
15.50
15.70
15.91
16.12
16.34
16.57
16.80
17.04
17.28
17.54
17.79
18.06
18.34
18.62
18.92
19.22
19.54
19.87
20.21
20.56

IMX219PQH5-C

5-8-2 Digital gain settings
The IMX219PQH5-C can set the digital gain for global. The registers required to set the digital gain are as follows.

Table 24 Digital Gain Settings
Upper byte address(Setting range:1 to15)

Lower byte address(Setting range:0 to 255)

DIG_GAIN_GLOBAL_A

0x01580x0159DIG_GAIN_GLOBAL_B

0x02580x0259CCI register nameEach register is comprised of 2 bytes, with the upper byte [15:8] setting the integer portion and the lower byte [7:0]
setting the fractional portion of the gain. The gain for global is obtained by the following equation.
Gain digital Upperbyte +Lowerbyte
256

The upper byte can be set to a value between 1 and 15, and the lower byte to a value between 0 and 255.
Therefore, the digital gain setting range for global is as follows.
0

1 + 256 [times](0 dB) ≤ Gain digital ≤ 15 +

255
256

[times](24 dB)

When gain is considered in log linear scale, the adjustment steps are large at low gain and extremely small at highgain. The register values are shown on the following page in case of the gain in log linear manner in 0.1 dB steps.

60

IMX219PQH5-C

61

3.98 12.00
4.03 12.10
4.07 12.20
4.12 12.30
4.17 12.40
4.22 12.50
4.27 12.60
4.32 12.70
4.36 12.80
4.41 12.90
4.47 13.00
4.52 13.10
4.57 13.20
4.63 13.30
4.68 13.40
4.73 13.50
4.79 13.60
4.84 13.70
4.90 13.80
4.95 13.90
5.01 14.00
5.07 14.10
5.13 14.20
5.19 14.30
5.25 14.40
5.31 14.50
5.37 14.60
5.43 14.70
5.50 14.80
5.56 14.90
5.63 15.00
5.69 15.10
5.75 15.20
5.82 15.30
5.89 15.40
5.96 15.50
6.03 15.60
6.09 15.70
6.16 15.80
6.24 15.90
6.31 16.00
6.38 16.10
6.46 16.20
6.53 16.30
6.61 16.40
6.68 16.50
6.76 16.60
6.84 16.70
6.92 16.80
7.00 16.90
7.08 17.00
7.16 17.10
7.25 17.20
7.33 17.30
7.41 17.40
7.50 17.50
7.59 17.60
7.67 17.70
7.76 17.80
7.85 17.90

Lower
byte

Gain(dB)dec hex dec hex
3 3 251 FB
4 4 7 74 4 19 13
4 4 31 1F
4 4 43 2B
4 4 56 38
4 4 68 44
4 4 81 51
4 4 93 5D
4 4 106 6A
4 4 120 78
4 4 133 85
4 4 146 92
4 4 160 A0
4 4 173 AD
4 4 187 BB
4 4 201 C9
4 4 215 D7
4 4 230 E6
4 4 244 F4
5 5 3 35 5 18 12
5 5 33 21
5 5 48 30
5 5 64 40
5 5 79 4F
5 5 95 5F
5 5 111 6F
5 5 127 7F
5 5 143 8F
5 5 160 A0
5 5 176 B0
5 5 193 C1
5 5 210 D2
5 5 227 E3
5 5 245 F5
6 6 7 76 6 24 18
6 6 42 2A
6 6 61 3D
6 6 79 4F
6 6 98 62
6 6 117 75
6 6 136 88
6 6 155 9B
6 6 175 AF
6 6 195 C3
6 6 215 D7
6 6 235 EB
7 7 0 07 7 20 14
7 7 41 29
7 7 63 3F
7 7 84 54
7 7 106 6A
7 7 128 80
7 7 150 96
7 7 172 AC
7 7 195 C3
7 7 218 DA

2.00 6.00
2.02 6.11
2.04 6.21
2.07 6.30
2.09 6.40
2.11 6.50
2.14 6.59
2.16 6.71
2.19 6.80
2.21 6.91
2.24 7.00
2.27 7.10
2.29 7.19
2.32 7.30
2.34 7.40
2.37 7.50
2.40 7.60
2.43 7.70
2.45 7.79
2.48 7.90
2.51 8.00
2.54 8.09
2.57 8.20
2.60 8.30
2.63 8.40
2.66 8.50
2.69 8.60
2.72 8.70
2.75 8.80
2.79 8.90
2.82 9.01
2.85 9.10
2.88 9.20
2.92 9.30
2.95 9.41
2.98 9.50
3.02 9.60
3.05 9.70
3.09 9.80
3.13 9.90
3.16 10.00
3.20 10.10
3.23 10.20
3.27 10.30
3.31 10.40
3.35 10.50
3.39 10.60
3.43 10.70
3.47 10.80
3.51 10.90
3.55 11.00
3.59 11.10
3.63 11.20
3.67 11.30
3.71 11.40
3.76 11.50
3.80 11.60
3.85 11.70
3.89 11.80
3.93 11.90

Upper
byte

Gain(times)

dec hex dec hex
1 1 255 FF
2 2 5 52 2 11 B
2 2 17 11
2 2 23 17
2 2 29 1D
2 2 35 23
2 2 42 2A
2 2 48 30
2 2 55 37
2 2 61 3D
2 2 68 44
2 2 74 4A
2 2 81 51
2 2 88 58
2 2 95 5F
2 2 102 66
2 2 109 6D
2 2 116 74
2 2 124 7C
2 2 131 83
2 2 138 8A
2 2 146 92
2 2 154 9A
2 2 161 A1
2 2 169 A9
2 2 177 B1
2 2 185 B9
2 2 193 C1
2 2 201 C9
2 2 210 D2
2 2 218 DA
2 2 226 E2
2 2 235 EB
2 2 244 F4
2 2 252 FC
3 3 5 53 3 14 E
3 3 23 17
3 3 32 20
3 3 42 2A
3 3 51 33
3 3 60 3C
3 3 70 46
3 3 80 50
3 3 90 5A
3 3 99 63
3 3 109 6D
3 3 120 78
3 3 130 82
3 3 140 8C
3 3 151 97
3 3 161 A1
3 3 172 AC
3 3 183 B7
3 3 194 C2
3 3 205 CD
3 3 217 D9
3 3 228 E4
3 3 239 EF

Lower
byte

Gain(dB)

0.00
0.10
0.20
0.30
0.40
0.49
0.59
0.68
0.81
0.90
0.99
1.11
1.20
1.29
1.41
1.49
1.61
1.69
1.80
1.91
1.99
2.10
2.21
2.31
2.39
2.49
2.59
2.69
2.79
2.89
3.01
3.10
3.20
3.29
3.41
3.50
3.59
3.70
3.79
3.90
4.01
4.09
4.20
4.30
4.40
4.50
4.60
4.70
4.80
4.90
5.00
5.11
5.20
5.30
5.41
5.50
5.60
5.69
5.80
5.90

Upper
byte

Gain(times)

1.00
1.01
1.02
1.04
1.05
1.06
1.07
1.08
1.10
1.11
1.12
1.14
1.15
1.16
1.18
1.19
1.20
1.21
1.23
1.25
1.26
1.27
1.29
1.30
1.32
1.33
1.35
1.36
1.38
1.39
1.41
1.43
1.45
1.46
1.48
1.50
1.51
1.53
1.55
1.57
1.59
1.60
1.62
1.64
1.66
1.68
1.70
1.72
1.74
1.76
1.78
1.80
1.82
1.84
1.86
1.88
1.91
1.93
1.95
1.97

Lower
byte

Gain(dB)dec hex dec hex
1 1 0 01 1 3 3
1 1 6 6
1 1 9 91 1 12 C
1 1 15 F
1 1 18 12
1 1 21 15
1 1 25 19
1 1 28 1C
1 1 31 1F
1 1 35 23
1 1 38 26
1 1 41 29
1 1 45 2D
1 1 48 30
1 1 52 34
1 1 55 37
1 1 59 3B
1 1 63 3F
1 1 66 42
1 1 70 46
1 1 74 4A
1 1 78 4E
1 1 81 51
1 1 85 55
1 1 89 59
1 1 93 5D
1 1 97 61
1 1 101 65
1 1 106 6A
1 1 110 6E
1 1 114 72
1 1 118 76
1 1 123 7B
1 1 127 7F
1 1 131 83
1 1 136 88
1 1 140 8C
1 1 145 91
1 1 150 96
1 1 154 9A
1 1 159 9F
1 1 164 A4
1 1 169 A9
1 1 174 AE
1 1 179 B3
1 1 184 B8
1 1 189 BD
1 1 194 C2
1 1 199 C7
1 1 205 CD
1 1 210 D2
1 1 215 D7
1 1 221 DD
1 1 226 E2
1 1 232 E8
1 1 237 ED
1 1 243 F3
1 1 249 F9

Upper
byte

Gain(times)

Lower
byte

Gain(dB)

Upper
byte

Gain(times)

Table 25 Example of Digital Gain Setting

dec hex dec hex
7 7 241 F1 7.94 18.00
8 8 9 9 8.04 18.10
8 8 33 21 8.13 18.20
8 8 57 39 8.22 18.30
8 8 81 51 8.32 18.40
8 8 106 6A 8.41 18.50
8 8 131 83 8.51 18.60
8 8 156 9C 8.61 18.70
8 8 182 B6 8.71 18.80
8 8 207 CF 8.81 18.90
8 8 234 EA 8.91 19.00
9 9 4 4 9.02 19.10
9 9 31 1F 9.12 19.20
9 9 58 3A 9.23 19.30
9 9 85 55 9.33 19.40
9 9 113 71 9.44 19.50
9 9 141 8D 9.55 19.60
9 9 169 A9 9.66 19.70
9 9 198 C6 9.77 19.80
9 9 227 E3 9.89 19.90
10 A 0 0 10.00 20.00
10 A 30 1E 10.12 20.10
10 A 60 3C 10.23 20.20
10 A 90 5A 10.35 20.30
10 A 121 79 10.47 20.40
10 A 152 98 10.59 20.50
10 A 183 B7 10.71 20.60
10 A 215 D7 10.84 20.70
10 A 247 F7 10.96 20.80
11 B 23 17 11.09 20.90
11 B 56 38 11.22 21.00
11 B 90 5A 11.35 21.10
11 B 123 7B 11.48 21.20
11 B 157 9D 11.61 21.30
11 B 192 C0 11.75 21.40
11 B 227 E3 11.89 21.50
12 C 6 6 12.02 21.60
12 C 41 29 12.16 21.70
12 C 77 4D 12.30 21.80
12 C 114 72 12.45 21.90
12 C 151 97 12.59 22.00
12 C 188 BC 12.73 22.10
12 C 226 E2 12.88 22.20
13 D 8 8 13.03 22.30
13 D 47 2F 13.18 22.40
13 D 86 56 13.34 22.50
13 D 125 7D 13.49 22.60
13 D 165 A5 13.64 22.70
13 D 206 CE 13.80 22.80
13 D 247 F7 13.96 22.90
14 E 32 20 14.13 23.00
14 E 74 4A 14.29 23.10
14 E 116 74 14.45 23.20
14 E 159 9F 14.62 23.30
14 E 203 CB 14.79 23.40
14 E 246 F6 14.96 23.50
15 F 35 23 15.14 23.60
15 F 80 50 15.31 23.70
15 F 125 7D 15.49 23.80
15 F 171 AB 15.67 23.90
15 F 217 D9 15.85 24.00

IMX219PQH5-C

6. On Chip Image Processing
Data flow of our “On-Chip Image Processing” is written in following figure.
A/D-converted digital signal is input, and processed data is asserted from CSI-2.

Analogue
DomainTest
Pattern
Generator

DefectCorrection

Digital Gain
Setting

default mode

Pixel
Re-align
In H
direction

Black
Level
Adjust

FIFO

Fig. 32 Data Flow Diagram
6-1 Test Pattern Generator
The IMX219PQH5-C can output test signals using the internal pattern generator.

6-1-1 Test Pattern
The test pattern output function outputs fixed pattern image data from the IMX219PQH5-C. Built-in image patterns
can be output by setting the necessary registers.
The registers must be set by communication to output the test pattern. There are no restrictions on the sequence
for setting the registers related to test pattern output. The prescribed output is obtained by setting the necessary
registers while the sensor is operating.

62

IMX219PQH5-C

Table 26 Description of Test Pattern Registers
AddressName

Description

0x06000000h– no pattern (default)
0001h – solid color
0002h – 100 % color bars
0003h – fade to grey color bar
0004h – PN90005h – 16 split color bar
0006h – 16 split inverted color bar
0007h – column counter
0008h – inverted column counter
0009h – PN31

test_pattern_mode
0x06010x0602

TD_R[9:8]

0x0603

TD_R[7:0]

0x0604

TD_GR[9:8]0x0605

TD_GR[7:0]0x0606

TD_B[9:8]

0x0607

TD_B[7:0]

0x0608

TD_GB[9:8]0x0609

TD_GB[7:0]0x060A

H_CUR_WIDTH[15:8]

0x060B

H_CUR_WIDTH[7:0]0x060C

H_CUR_POS[15:8]

0x060D

H_CUR_POS[7:0]0x060E

V_CUR_WIDTH[15:8]

0x060F

V_CUR_WIDTH[7:0]0x0610

V_CUR_POS[15:8]

0x0611

V_CUR_POS[7:0]0x0612

FRM_RST_OFF

0x0620

TP_WINDOW_X_OFFSET[11:8]

0x0621

TP_WINDOW_X_OFFSET[7:0]0x0622

TP_WINDOW_Y_OFFSET[11:8]

0x0623

TP_WINDOW_Y_OFFSET[7:0]0x0624

TP_WINDOW_WIDTH[11:8]

0x0625

TP_WINDOW_WIDTH[7:0]0x0626

TP_WINDOW_HEIGHT[11:8]

0x0627

TP_WINDOW_HEIGHT[7:0]

test_data_red
test_data_red
test_data_greenR
test_data_greenR
test_data_blue
test_data_blue
test_data_greenB
test_data_greenB
horizontal_cursor_width
horizontal_cursor_width
horizontal_cursor_position
horizontal_cursor_position
vertical_cursor_width
vertical_cursor_width
vertical_cursor_position
vertical_cursor_position
Frame reset control w/ PN9,PN31
0: Frame reset ON (default)
1: Frame reset OFF
test_pattern_window_x_offset

test_pattern_window_y_offset

test_pattern_window_width

test_pattern_window_height63

IMX219PQH5-C

6-1-1-1 Pattern Description

Table 27 Description of Test Patterns
100 % color bar
test_pattern_mode = 0002h
Embedded data line

fade to gray color bar
test_pattern_mode = 0003h
Embedded data line

64

IMX219PQH5-C

16 split Color Bar Chart
test_pattern_mode = 0005h
Embedded data line

Inversed 16 split Color Bar Chart
test_pattern_mode = 0006h
Embedded data line65

IMX219PQH5-C

column counter
test_pattern_mode = 0007h
Embedded data line

inverted column counter
test_pattern_mode = 0008h

Embedded data line66

IMX219PQH5-C

6-2 Digital Gain Setting
See Digital gain settings section.

6-3 Black Level Adjust
The register required to set the Black Level Adjust is as follows.

Table 28 Black Level Adjust Setting Register
Index
(HEX)

Bit

Register Name

RW

D1EA

[1:0]

DT_PEDESTAL[9:8]

RW

Comment

Default(HEX)

Re-Timed0
Set Black Level

D1EB

[7:0]

DT_PEDESTAL[7:0]RW40

6-4 Defect Correction
The registers required to set the Defect Correction are as follows.
3 different functions are implemented; (Please refer to “7-5 Defects Address registration” session);
1.Static single defect pixel correction
2.Static same color adjoin pixel correction
3.Static 2x4 defect pixel correction
Defect addresses for mapped_couplet_correct (couplet defect: two adjacent defect pixels of the same color) arestored in NVM , and sensor processes them in itself.

6-5 Pixel Re-alignment H Direction
The registers required to set the Pixel Re-alignment H Direction are as follows.

Table 29 Pixel Re-alignment H Direction Setting Registers
Index

Byte

Register Name

RW

0x0164[3:0]

X_ADD_STA_A[11:8]

RW

Comment

x_addr_start
0x0165[7:0]

X_ADD_STA_A[7:0]RW0x0166[3:0]

X_ADD_END_A[11:8]

RW
x_addr_end

0x0167[7:0]

X_ADD_END_A[7:0]RW0x0264[3:0]

X_ADD_STA_B[11:8]

RW
x_addr_start

0x0265[7:0]

X_ADD_STA_B[7:0]RW0x0266[3:0]

X_ADD_END_B[11:8]

RW
x_addr_end

0x02670x0174[7:0][0]

X_ADD_END_B[7:0]

BINNING_MODE_H_A

Re-Time

RW

67

Embd
DL

0

○

00

○

C

○

CF

○

0

○

00

○

C

○

CF

○

0

○

Frame Bank

Frame Bank

Frame Bank

Frame Bank

RW
defines binning mode
(H-direction).
0: no-binning,
1: x2-binning
2: x4-binning3: x2-analog (special)binning

Default(HEX)

Frame BankIMX219PQH5-C

0x0274[0]

BINNING_MODE_H_B

RW

defines binning mode
(H-direction).
0: no-binning,
1: x2-binning
2: x4-binning3: x2 analog (special)binning

Frame Bank

0○

Re-TimeDefault
(HEX)

Embd
DL

Frame Bank

00○

Frame Bank

00○

Frame Bank

09○

Frame Bank

9F○

6-6 Pixel Re-alignment V Direction
The registers required to set the Pixel Re-alignment H Direction are as follows.

Table 30 Pixel Re-alignment V Direction Setting Registers
Index

Byte

Register Name

RW

0x168

[3:0]

Y_ADD_STA_A[11:8]

RW

0x169

[7:0]

Y_ADD_STA_A[7:0]

RW

0x16A

[3:0]

Y_ADD_END_A[11:8]

RW

0x16B

[7:0]

Y_ADD_END_A[7:0]

RW

0x268

[3:0]

Y_ADD_STA_B[11:8]

RW

0x269

[7:0]

Y_ADD_STA_B[7:0]

RW

0x26A

[3:0]

Y_ADD_END_B[11:8]

RW

0x26B

[7:0]

Y_ADD_END_B[7:0]

RW

0x175

0x275

[0]

[0]

BINNING_MODE_V_A

BINNING_MODE_V_B

Commenty_addr_starty_addr_end

Frame Bank○

Frame Bank○

Frame Bank○

Frame Bank○

RW

defines binning mode
(V-direction).
0:no-binning
1:x2-binning
2:x4-binning
3:x2 analog (special)binning

Frame Bank○

RW

defines binning mode
(V-direction).
0:no-binning
1:x2-binning
2:x4-binning
3:x2 analog (special)binning

Frame Bank○y_addr_starty_addr_end

68

IMX219PQH5-C

7. NVM Memory Map
7-1 Block Diagram

CCI

NVM
AccessControl(ECC)

Control
Block

NVM

Pipeline
Pixel Controller

Fig. 33 Block Diagram
NVM is composed of 12 pages (from 0 to 11) and 64 bytes per page. ECC is also applied for every 16 address(bytes), 4 rows in 1 page.

Fig. 34 NVM Map structure
7-2 NVM Functions
NVM block has following functions.

Table 31 Functions via NVM
No

Item

Description

1

Data Interface

User can write/read data via CCI by the unit of page2

Writing Reg. Value

Writing assigned address and values which are transferred into theassigned registers.
(Please refer to Related Registers session “Then when writing; ”)

3

Writing Defect address

Writing assigned address, whose values are used for defectcorrections (Please refer to Defects Address registration session)

4

Reading

Reading NVM data by the unit of page, not ECC region(Please refer to Related Registers session “Then when reading;”)

5

ECC Function

Can apply ECC for each 16 bytes (1-row) block.
1-bit per 16 bytes can be corrected.

69

IMX219PQH5-C

6

ECC status

Can check while reading/writing that ECC is applied by page.
1. Read data is correct. No ECC is applied.
2. Read data is correct with 1-bit correction of ECC.
3. Read data is incorrect though ECC is applied (means >2 bits per aunit of 16-byte (row) are incorrect).

7-3 Related Registers
Table 32 Related Registers
Index

Byte

0100

[0]

Register Name

Mode_sel

RW

Comment

Re-TimeDefault(HEX)

RW

Mode select0: SW- Standby
1: Streaming

0

00

3300

[7:0]

SYSOTP_IF_MODE1

RW

OTP mode setting[1:0]: control access cycle tofuse cell
00: INCK cycle
01: INCK/2 cycle
10: INCK/4 cycle
11: INCK/8 cycle[3]: ECC disable switch
0: ECC on,1:ECC off[5]:write mode;
0: test mode
1: recommended

5E54

[7:0]

OUTF

RW

Monitor Output Enable

C0

5E59

[7:0]

TESTMNT1

RW

Monitor Output

00

4053

[7:0]

TEST_FSTRB

RW

Set FStrobe pin to monitor

00

012A

[7:0]

EXCK_FREQ [15:8]

RW

07

012B

[7:0]

EXCK_FREQ [7:0]

RW

input_clk_frequency_mhz(default = 7.6[MHz])

3302

[7:0]

SYSOTP_IF_WRCNT[15:8]

RW

Embd
DL

Comments

99
00

OTP write clock setting
3303
3200

[7:0]
[2:0]

SYSOTP_IF_WRCNT[7:0]
OTPIF_CTRL

RW

00

RW

OTP I/F control register[0] enable [1]R/W [2]error
clear

0

0

3201

[1:0]

OTPIF_STATUS

RO-D

OTP I/F status; [0] read ready[1] write ready[2] 0: normal
1: Data error exists, andcannot be corrected by ECC.
Read data is incorrect.

3202

[2:0]

OTPIF_PAGE_SELECT

RW

otpif_page_select

0

3204

[7:0]

OTPIF_DT_0

RW

otpif_data_000

RW

otpif_data_63

00(DT_1 to DT_62)
3243

[7:0]

OTPIF_DT_63

Trigger tostart write
sequence

Before writing / reading following steps are required
1. Set Sensor being SW-Standby by 0x0100 = 0h
2. Wait one frame time (See t0 in 8-2 Power off sequence session) when previous status is streaming.
3. Set monitor output to check writing pulse by 0x5E54=00h and 0x5E59=FFh, 4053=0Ah. (option, debug purpose
only)
4. Set OTP write clock setting. (target = 25 µS)(When INCK = 12.0 MHz, “wrcnt” should be set to 012Ch (target = 25µs : 300d) at 0x3302, 0x3303)
Then when writing;
1. Set controller "ECC ON" or ECC OFF" by 0x3300 = "20h" (ECC ON) or "28h" (ECC OFF)
2. Set Write by 0x3200 = "3h."3. Set page from 0 to 11 by 0x3202.
4. Set 0x3204 to 0x3243 OTPIF_DT_0to 63 = xxh (Data to Write)
Please overwrite all values when you program next page.

70

IMX219PQH5-C

OTP controller does NOT clear previous values automatically.
5. Set last byte of OTP buffer 0x3243 need to write again with same value of step4
6. Wait write sequence finish ( >12.8msec:target [25µs /bit] x 8 bit x 16btye x 4row)
7. Repeat the above (3) – (6) sequence again for twice write process.
Then when reading;
1. Set controller “ECC ON” or “ECC OFF” by 0x3300 = 00h (ECC ON), 08h (ECC OFF) ;2. Set Read by 0x3200 = "1h."3. Set page from 0 to 11 by 0x3202.
4. Set 0x3204 to 0x3243 OTPIF_DT_0to 63 = xxh (Data to Write)71

IMX219PQH5-C

7-4 NVM Memory Map
Table 33 NVM Memory capacity
Capacity

data Owner

768 byte

Total

672 byte

Integrator

96 byteSony

Table 34 NVM Memory Map Example
Page
(dec)

Row
(dec)

Addr
(hex)

0

0-3

000 - 03F

Integrator

14-7

040 - 07F

Integrator

2

8-11

080 - 0BF

Integrator

3

12-15

0C0 - 0FF

Integrator

4

16-19

100 - 13F

Integrator

5

20-23

140 - 17F

Integrator

6

24-27

180 - 1BF

Integrator

7

28-31

1C0 - 1FF

Integrator

8

32-35

200 - 23F

Integrator

9

36-39

240 - 27F

Integrator

10

40-41

280 - 29F

Integrator

Category

Name

Value
(hex)

data
Owner

10

42

2A0

memcfg1

Defines availability of each data
[7:1] reserved[0]: defect address available
Value 0x00 makes sensor skip copying data from
NVM to register.

10

42

2A1

Defect Correction

defect_num[7:0]Integrator

10

42

2A2

Defect Correction{DFCT_SRC_10[1:0]CP_DFCT_DIR_10[1:0]
H_DFCT_ADDR_10[11:9]}

Integrator

10

42

2A3

Defect Correction

H_DFCT_ADDR_10[7:0]Integrator

10

42

2A4

Defect Correction

V_DFCT_ADDR_10[11:4]

Integrator

10

42

2A5

Defect Correction{V_DFCT_ADDR_10[3:0]
DFCT_SRC_11[1:0]CP_DFCT_DIR_11[1:0]}

Integrator

10

42

2A6

Defect Correction

H_DFCT_ADDR_11[11:4]

Integrator

10

42

2A7

Defect Correction{H_DFCT_ADDR_11[3:0], V_DFCT_ADDR_11[11:8]}

Integrator

10

42

2A8

Defect Correction

V_DFCT_ADDR_11[7:0]Integrator

10

42

2A9

Defect Correction{DFCT_SRC_12[1:0]CP_DFCT_DIR_12[1:0]
H_DFCT_ADDR_12[11:8]}

Integrator

10

42

2AA

Defect Correction

H_DFCT_ADDR_12[7:0]Integrator

10

42

2AB

Defect Correction

V_DFCT_ADDR_12[11:4]

Integrator
Integrator

01

Integrator

10

42

2AC

Defect Correction{V_DFCT_ADDR_12[3:0]
DFCT_SRC_13[1:0]CP_DFCT_DIR_13[1:0]}

10

42

2AD

Defect Correction

H_DFCT_ADDR_13[11:4]

Integrator

10

42

2AE

Defect Correction{H_DFCT_ADDR_13[3:0], V_DFCT_ADDR_13[11:8]}

Integrator

10

42

2AF

Defect Correction

H_DFCT_ADDR_13[7:0]Integrator

10

43

2B0

please don't write

Defect number

Sony

10

43

2B1

please don't write

Defect address (single, 2 adjacent in same color ,2x4 static),10 address

Sony

72

IMX219PQH5-C

Page
(dec)

Row
(dec)

Addr
(hex)

Category

Name

10

43

2B2

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2B3

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2B4

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2B5

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2B6

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2B7

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2B8

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2B9

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2BA

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2BB

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2BC

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2BD

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2BE

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

10

43

2BF

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C0

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C1

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C2

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C3

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C4

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C5

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C6

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C7

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C8

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2C9

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2CA

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2CB

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2CC

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2CD

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

73

Value
(hex)

data
Owner

IMX219PQH5-C

Page
(dec)

Row
(dec)

Addr
(hex)

Category

Name

11

44

2CE

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

44

2CF

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

45

2D0

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

45

2D1

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

45

2D2

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

45

2D3

please don't write

Defect address (single, 2 adjacent in same color , 2x4
static),10 address

Sony

11

45

2D4 - 2DF

please don't write

Sony Calibration Area

Sony

11

46

2E0 - 2E5

please don't write

Sony Calibration Area

Sony

11

46

2E6

Fabrication, copy
to 0x0002

Sony Calibration Area

Sony

11

46

2E7

Lot ID, copy to
0x0004

Sony Calibration Area

Sony

11

46

2E8

Lot ID, copy to
0x0005

Sony Calibration Area

Sony

11

46

2E9

Lot ID, copy to
0x0006

Sony Calibration Area

Sony

11

46

2EA

Wafer Number,copy to 0x0007

Sony Calibration Area

Sony

11

46

2EB

Chip Number,copy to 0x000D

Sony Calibration Area

Sony

11

46

2EC

Chip Number,copy to 0x000E

Sony Calibration Area

Sony

11

46

2ED

Process revision,
0x000F

Sony Calibration Area

Sony

11

46

2EE - 2EF

please don't write

Sony Calibration Area

Sony

11

47

2F0 - 2FF

please don't write

Sony Calibration Area

Sony

74

Value
(hex)

data
Owner

IMX219PQH5-C

7-5 Defects Address registration
The single defect, the same color adjoining (SCA) defect and 2 x 4 defect are stored into NVM and corrected.

7-5-1 Single defect address
1. Target Address; (x, y) = (xt, yt)*Output area is Effective Area
Output size is 3280x2464 (0,0) - (3279,2463)
x = image area address + offset; offset = 8dy = image area address + offset; offset = 48d (not include embedded lines)

Scan Direction
Image Orientation = 0d
Starting Red Pixel Datax

Fig. 35 Single defect
7-5-2 Same Color Adjoining defect address
1. Target Address; (x, y) = (xt, yt)*Output area is Effective Area
Output size is 3280x2464 (0,0) - (3279,2463)
x = image area address + offset; offset = 8dy = image area address + offset; offset = 48d (not include embedded lines)
2. Directions are also described in the following figure
0d = defect in right adjoining
1d = defect in right bottom adjoining
2d = defect in bottom adjoining
3d = defect in left bottom adjoining

3

x

0

2

1

Scan Direction
Image Orientation = 0d
Starting Red Pixel Data

Fig. 36 Same Color Adjoining defect
7-5-3 2x4 defect address
1. Target Address; (x, y) = (xt, yt)*Output area is Effective Area
Output size is 3280x2464 (0,0) - (3279,2463)
x = image area address + offset; offset = 8dy = image area address + offset; offset = 48d (not include embedded lines)
2. Only upper left pixel address needed in this case, always RED pixels

xScan Direction
Image Orientation = 0d
Starting Red Pixel Data

Fig. 37 2x4 defect75

IMX219PQH5-C

7-5-4 Example Setting
Example when defect addr are
1st: (228d, 522d), func: adjoin, dir: 1
2nd: (2846d, 1460d), func: 2x4
3rd: (26d, 20d), single→ Offset values are (physical address)
1st: (236d, 570d) , func: adjoin, SRC = 2, DIR = 1, H_ADR = ECh, V_ADR = 23Ah
2nd: (2854d, 1508d) , func:2x4 SRC = 3, DIR = 0, H_ADR = B26h, V_ADR = 5E4h
3rd: (34d, 68d), func: single SRC = 1, DIR = 0, H_ADR = 22h, V_ADR = 44h

Table 35 Example setting of defect pixel
Addr (hex)description

Value (hex)

2A0

Defines availability of each data
[7:1] reserved[0]: defect address available
Value 0x00 makes sensor skip copying data from NVM to register.

01

2A1

defect_num[7:0]3

2A2{DFCT_SRC_10[1:0]CP_DFCT_DIR_10[1:0]
H_DFCT_ADDR_10[11:9]}

90

2A3

H_DFCT_ADDR_10[7:0]

EC

2A4

V_DFCT_ADDR_10[11:4]

23

2A5

{V_DFCT_ADDR_10[3:0]
DFCT_SRC_11[1:0]CP_DFCT_DIR_11[1:0]}

AC

2A6

H_DFCT_ADDR_11[11:4]

B2

2A7

{H_DFCT_ADDR_11[3:0], V_DFCT_ADDR_11[11:8]

65

2A8

V_DFCT_ADDR_11[7:0]

E4

2A9

{DFCT_SRC_12[1:0]CP_DFCT_DIR_12[1:0]
H_DFCT_ADDR_12[11:8]}

40

2AA

H_DFCT_ADDR_12[7:0]

22

2AB

V_DFCT_ADDR_12[11:4]

04

2AC

{V_DFCT_ADDR_12[3:0]
DFCT_SRC_13[1:0]CP_DFCT_DIR_13[1:0]}

40

2AD

H_DFCT_ADDR_13[11:4]

00

2AE

{H_DFCT_ADDR_13[3:0], V_DFCT_ADDR_13[11:8]

00

2AF

H_DFCT_ADDR_13[7:0]0076IMX219PQH5-C

8. How to operate IMX219PQH5-C
8-1 Power on sequence
Power on sequence of IMX219PQH5-C is below figure.
Startup Sequence in 2-wire Serial Communication Mode
Perform power-on according to the following sequence.
The XCLR pin must be released (Low → High) after all the power supplies (VANA,VDIG,VDDL) are completed.

Power Off

SoftwareStandby

HardwareStandbyStreaming(Active)

t0
VANA
t1
VDIG

VDDL
(1.1V)

t2

INCK

XCLR

t3

XCLR
(internal)

t5

t9, t10

t4
CCI

t6

t7

t8

CLK
+/-

LP10

LP11

Data
1 &2 +/-

LP10

LP11

Data
3 & 4 +/-

LP10

LP11

Fig. 38 Power-on Sequence in 2-wire Serial Communication Mode77

IMX219PQH5-C

Table 36 Operation Specifications 2-wire Serial Communication Mode
Constraint
Sequence free of VDDs risingLabelt0, t1, t2

Min.

Max.

Units

VANA, VDIG, VDDL may
rise in any order.

ns

―

µs

200

µs

6

―

ms

t6

―

32000

clocks

D-PHY power-up

t7

1

1.1

ms

D-PHY init

t8

100

110

µs

After releasing software standby todata streaming timet9

1.2 ms +exposure time―

Quick launch up time

t10

―

1

XCLR risingt3

Internal XCLR is Low to High after
VDDs & XCLR suppliedt4

releasing software standby after
XCLR Low to Hight5

Initializing time of silicon

0.5

Comment

frame

charge up VRL
clock is INCK
Case of INCK = 6[MHz],5.3[msec]

stable time until optimal
image quality

Start streaming sequence with 2-wire serial communication
IMX219PQH5-C requires the command sequence below to output image data.

Fig. 39 Start streaming sequence with 2-wire serial communication (external reset)
Table 37 Initialization sequence with XCLR
(1) to (3)Refer power up sequence timing diagram
Set PLL parameters
Basic setting (operation-critical setting)(4)

Set Readout mode (start/end position, size, mode, integration time, and gain)
Set MIPI interface parameters(5)Start streaming with 0x0100 (mode_select = 1)stAfter “Wake Up ime” + “Init ime”, 1 frame starts and images come out

78

IMX219PQH5-C

8-2 Power off sequence
Perform the power-off in the sequence shown below.

Streaming (Active)

HardwareStandby

Software Standby

Power Off

VBAT

VANA
t3
VDIG

t4

VDDL

t5

INCK

XCLR

t1

XCLR
(internal)

t2
t0

CCI

CLK
+/-

LP11

LP00

Data
1 &2 +/-

LP11

LP00

Data
3 & 4 +/-

LP11

LP00

Fig. 40 Power-off Sequence in 2-wire Serial Communication
Table 38 Operation Specifications in 2-wire Serial Communication
Constraint

Label

Communication end – Software standby

t0

Software standby - XCLR H → L

t1

Falling time of internal XCLR after
XCLR H → L

t2

VANA falling - VDIG falling - VDDL falling

Min.

Max.

Units

One frametime (*1)

s0t3,t4,t5

VANA, VDIG and VDDL
may fall in any order.

(*1) One frame time = 1/(Frame_Rate[frame/s])
Can set fast standby mode when fast standby register (0x0106)] set to enable (0x01).
Sequence for fast standby mode;(1) 0x0106 set to 0x01 ( fast standby mode is enable)(2) 0x0100 set to 0x00 ( SW standby )(3) Can change to SW standby after read out of current line.

79

Until frame
outputns
10

Commentµs
nsIMX219PQH5-C

To in power-off sequence varies depending on the CCI communication end timing as shown below.
1.

When the CCI communication is performed with Software Standby between SOF and EOF, all communicatedframe data is output and the status is converted to Software Standby.
Enter
Stop
SDA
SCL
CSI2
DATA

S
O
F

Frame
Counter

E
O
F
N

0xFF

Frame_length_lines
Fig. 41 Software Standby Operation Pattern 1

2.

When the CCI communication is performed with Software Standby during FrameBlanking, the status isconverted to Software Standby immediately after communication.
Enter
Stop
SDA
SCL
CSI2
DATA
Frame
Counter

S
O
F

E
O
F

Frame
Blanking

N

0xFF

Frame_length_lines
Fig. 42 Software Standby Operation Pattern 280

IMX219PQH5-C

9. Other Functions
9-1 Clock System
9-1-1 Clock Structure
The IMX219PQH5-C clock system has the following structure.
2Ch
10

10

Pipe
Line

ADC

FiFo

10

10

Control Unit

DIV1

DIV2
0x0301:VTPXCK_DIV=4(1/4), 5(1/5), 8(1/8) or 10(1/10)
0x0303:VTSYCK_DIV=1(1/1)

PLL1

Pre-Div1

mipi_CLK

OUT_CLKPIX_CLK

SYSCLK

Data Out

Mipi

0x0306:PLL_VT_MPY[10:8]
0x0307:PLL_VT_MPY[7:0]0x0309:OPPXCK_DIV=8(1/8) or 10(1/10)
0x030B:OPSYCK_DIV=1(1/2)

PLL2
0x030CPLL_OP_MPY[10:8]
0x030D:PLL_OP_MPY[7:0]

Pre-Div2

0x0305=1(1/1), 2(1/2) or 3(1/3)
automatically for EXCK_FREQ

0x0304=1(1/1), 2(1/2) or 3(1/3)
automatically for EXCK_FREQ

INCK

0x012A:EXCK_FREQ[15:8]
0x012B:EXCK_FREQ[7:0]Fig. 43 Clock System Block Diagram
The IMX219PQH5-C is comprised of 2 ch Pipe-Line, and 2 PLL for both pixel read domain and Output data domain.
See following section (Clock Setting Example) for detail.
Relationships between 2 domains are the followings;
1 If, Pix Rate of PLL1 domain < Data Rate of PLL2 domain, data is always correctly output from the sensor
2 If Pix Rate of PLL1 domain > Data rate of PLL2 domain, Else If de-rating (binning and sub-sampling without
resize), FiFo can handle.

9-1-2 EXCK_FREQ setting depend on INCK frequency
The IMX219PQH5-C has the function that automatically set Pre-Div1 and Pre-Div2 by setting the registerby setting the register of EXCK_FREQ, case of changing INCK frequency.

Table 39 EXCK_FREQ setting table
INCK

EXCK_FREQ

PREPLLCK_VT_DIV PREPLLCK_OP_DIV(Input Pin)

(0x012A/0x012B)(0x0304)(0x0305)

6 to 12[MHz]6d to 12d (06h to 0Ch)

01h (auto set)

01h (auto set)

12 to 24[MHz]12d to 24d (0Ch to 18h)

02h (auto set)

02h (auto set)

24 to 27[MHz]24d to 27d (18h to 1Bh)

03h (auto set)

03h (auto set)81

RemarkIMX219PQH5-C

9-2 Clock Setting Example
Interface

CSI-2

CSI-2

CSI-2

ADC bit width

10

10

10

Data Mode

Raw10

Raw10

Raw10

FPS

30 frame/s

180 frame/s

21 frame/s (*１)

Lanes

4

4

2

Full-Pel

2 (V) X2 (H) analog(special) binning

Full-Pel

3280 x 2464

1408 x 792

3280 x 2464

pll1_vt_freq

702 MHz702 MHz456 MHz

EXCK_FREQ

12

12

12

VTSYCK_DIV

1

1

1

vt_pix_clk_div

5

5

10

Pix Rate

280.8M pix

280.8M pix

182.4M pix

Actual freq (VTCK)

140.4 MHz

140.4 MHz91.2 MHz

pll2_op_freq

726 MHz726 MHz912 MHzop_sys_clk_div

1

1

1

op_pix_clk_div

10

10

10

de-rating1

1

1

Output Lanes

4

4

2

Actual freq (OPCK)

72.6 MHz72.6 MHz91.2 MHz

Actual MIPI-freq (byte)

90.75 MHz

90.75 MHz

114 MHz

Speed/Lane (Ch)726 Mbps

726 Mbps

912 Mbps

Total Output Rate

2.904 Gbps

2.904 Gbps

1.824 Gbps

Bin
Sub
Output Size (H, V)*１

Max. frame rate is 21 frame/s

82

IMX219PQH5-C

9-3 Temperature Sensor
Registers to be related about temperature sensor are the followings.

Table 40 Temperature setting registers
Index

Re-TimeDefault

Byte

Register Name

RW

Comment[7]

TEMPERATURE_EN

RW

start register to measuresensor temperature

0

[6:0]

TEMPERATURE_VAL

RO-D

result of measurement ofsensor temperature

00

(HEX)

Embd
DL

Comments

0x0140

The temperature sensor measures the junction temperature of the sensor silicon. The target range is -10 to 95
degrees in C, with +/- 5 degree in C deviation. The sensor is operated immediately after streaming mode, and thevalue will be stored in the register.
The following table shows the relationship between temperature and stored value.

Temperature[℃]
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95

temperature_val[dec]
0
6
12
18
24
30
36
43
49
55
61
67
73
79
85
91
97
104
110
116
122
128

83

temperature_val[hex]
0
6
C
12
18
1E
24
2B
31
37
3D
43
49
4F
55
5B
61
68
6E
74
7A
80

IMX219PQH5-C

10. Electrical Characteristics
10-1 Absolute Maximum Ratings
Table 41 Absolute Maximum Ratings
Item

SymbolMin.

Supply voltage (analogue)

VANA

Supply voltage (Core)

Typ.

Max.

Unit

Remarks

-0.3

3.3

V

VDDL

-0.3

2.0

V

Supply voltage (IF)

VDIG

-0.3

3.3

V

Input voltage

VI

-0.3

3.3

V

Output voltage

VO

-0.3

3.3

V

Operating temperature (function)

Topr

-20

60

˚C

Junction temperature

Storage temperature

Tstg

-30

80

˚C

Junction temperature

Performance guarantee temperature

Tspec

-20

60

˚C

Junction temperature

10-2 Recommended Operating Conditions
Table 42 Recommended Operating Conditions
Item

Symbol

Min.

Typ.

Max.

Unit

Supply voltage (analogue)

VANA

2.6

2.8

3.0

V

Supply voltage (Core)

VDDL

1.08

1.2

1.3

V

Supply voltage (IF)

VDIG

1.62

1.8

1.98

V

84

Remarks

IMX219PQH5-C

10-3 Electrical Characteristics
Table 43 DC Characteristics
Item

Pins

Symbol

Min.

Typ.

Max.

Unit

VANA

2.6

2.8

3.0

V

VDIG

1.62

1.8

1.98

V

VDDL

1.08

1.20

1.30

V

VIL

-0.5

0.3VDIGV

SCL, SDA,

VIH

0.7VDIG

VDIG + 0.5

V

GPO

VOL

0.25VDIGV

VDDHFIL1,2
VDDHCM1,2
VDDHANVDDHPL
Supply voltage

VDDHSN1,2
VDDMCOVDDLSC1-8
VDDLCN1,2
VDDLIO1,2

Digital input/output
voltage

VOH
Digital output voltage

Digital input voltage

FSTROBE

0.75VDIG

VOL

V
0.45

V

V

VOH

VDIG - 0.45

VIL

-0.3

0.35VDIG

VIH

0.65VDIG

VDIG + 0.3

XCLR,INCK

85

Comment

IMX219PQH5-C

10-4 AC Characteristics
10-4-1 Master Clock Waveform Diagram
10-4-1-1 INCK Square Waveform Input Specifications
Input specifications are shown below when square-wave inputs directly into the external pin INCK.
fRIS

fFA

E

LL

0.65VDIG
0.5VDIG
0.35VDIG
tp

Fig. 44 Master Clock Square Waveform Diagram
Table 44 Master Clock Square Waveform Input Characteristics
Item

Symbol

Min.

Typ.

Max.

Unit

6

18

27

MHz

600

ps

Frequency

fSCK

jitter (period, peak-to-peak)

Tjitter

Rise Time

fRISE

1

10

ns

Fall Time

fFALL

1

10

ns

Duty Cycle

fDUTY

40

60

%

Input Leakage

fILEAK

-10

10

µA

Comment

10-5 Electrical Characteristics
Table 45 Electrical Characteristics(VANA = 3.0 V, VDDL = 1.3 V, VDIG = 1.98 V, Tj = 60 ˚C)
Item

SymbolIVAVA_strm

Min.

Typ.

Max.

Unit

Comment

33

38

mA

VTmax is max speed
read out from pixel array
CSI2 4 lanes, VANA current

Current consumption(Full,30 frame/s)
IVDDL_strm

100

160

mA

VTmax is max speed
read out from pixel array
CSI2 4 lanes, VDDL current
Defect Correction, L.S.C.
function off

HW-Standby current

ISTB_ana

50µA

XCLR = Lo, VANA current

ISTB_dig

10µA

XCLR = Lo, VDIG current

ISTB_Iddl

50µA

XCLR = Lo, VDDL currentNote) Measurement conditions

86

IMX219PQH5-C

11. Spectral Sensitivity Characteristic(Neither lens characteristics nor light source characteristics is included.)

Fig. 45 Spectral sensitivity characteristics

87

IMX219PQH5-C

12. Image Sensor Characteristics
12-1 Image Sensor Characteristics
Table 46 Image Sensor Characteristics(30 frame/s, VANA = 2.8 V, VDIG = 1.2 V, VIF = 1.8 V, Tj = 60 ˚C)

Item

Range

Measurement
methodLSBCenter1

Center

2

LSB

Zone1

3

70

%

Zone2D

4

Design assurance

0.5

LSB

Zone2D

5

When operation at
15 frame/s

Min.

S

205

RG

0.45

0.51

0.57

BG

0.40

0.46

0.52

Saturation signal

Vsat

1023

Video signal
shadingSH

Dark signal

Vdt

Sensitivity

Typ.

Unit

SymbolMax.

Sensitivity ratio

Remarks

1/120 s storage

LSB is the abbreviation of Least Significant Bit. 10 bits = 1023 digital is the maximum output code for the output unit.
The base gain in which the saturation signal output matches with 1023 LSB is 0[dB] when the OB level is 64 LSB(standard recommended value). The data described at this image sensor characteristics are the measurement
standard without base gain setting, and indicates the results evaluated with OB as a reference.

12-2 Zone Definition used for specifying image sensor characteristics(9, 11)Dummy

2

OB side ignored area

8

Effective OB

16

OB side ignored area

16(3288, 26)(1, 43)(9, 51)(413, 291)

(2884, 2274)

Zone1(3288, 2514)

Zone2D(3296, 2522)

Zone3

Fig. 46 Zone Definition Diagram88

IMX219PQH5-C

13. Measurement Method for Image Sensor Characteristics
13-1 Measurement conditions
The device operation conditions are at the typical values of the bias and clock voltage.

Table 47 Measurement Conditions
Supply voltage

Analog 2.8 V, digital 1.2 V, IF 1.8 V

Clock

INCK (EXTCLK) 18 MHz

In the following measurements, spot pixels are excluded and, unless otherwise specified, the optical black(OB) level is used as the reference for the signal output, which is taken as the value of the Gr, Gb, R and B
digital signal outputs of the measurement system.
As an example of 1 LSB, the typical value is 1 LSB ≈ 0.357 mV in all-pixel output 10-bit operation mode.

13-2 Color Coding of This Image Sensor and Readout
The primary color filters of this image sensor are arranged in the layout shown in the figure below. Gr and Gb
denote the G signals on the same line as the R signal and the B signal, respectively. The R signal and Gr signallines and the Gb signal and B signal lines are output successively.
All pixel signals are output successively in a 1/15 s period.
Gb

B

Gb

B

Gb

B

R

Gr

R

Gr

R

Gr

Gb

B

Gb

B

Gb

B

R

Gr

R

Gr

R

Gr

Gb

B

Gb

B

Gb

B

R

Gr

R

Gr

R

Gr

Fig. 47 Color coding alignment13-3 Definition of Standard Imaging Conditions
Standard imaging condition I
Use a pattern box (luminance: 706 cd/m2, color temperature of 3200 K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0 mm) as an IR cut
filter and image at F2.8. The luminous intensity to the sensor receiving surface at this point is defined as thestandard sensitivity testing luminous intensity.
Standard imaging condition II
A testing lens with CM500S (t = 1.0 mm) is used as an IR cut filter for light source with 3200 K color
temperature. The luminous intensity to the sensor receiving surface is adjusted to the luminous intensity
level shown in each measurement item by the light source output, lens aperture or storage time control by
the electronic shutter.
Standard imaging condition III
A recommended testing lens with CM500S (t = 1.0 mm) is used as an IR cut filter for light source with 3200 K
color temperature. The luminous intensity to the sensor receiving surface is adjusted to the luminous intensity
level shown in each measurement item by the light source output or storage time control by the electronic
shutter.

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IMX219PQH5-C

13-4 Measurement method
Sensitivity
Set the measurement condition to the standard imaging condition I. After setting the luminous intensityof 10 times that of the standard imaging condition and the electronic shutter mode with a shutter speedof 1/150 s, measure the Gr and Gb signal outputs (VGr, VGb) at the center of imaging area, andsubstitute the values into the following formula.
S = {((VGr + VGb)/2) × (1/10) × (150/120)} [LSB]

Sensitivity ratio
Set the measurement condition to the standard imaging condition II. After adjusting so that the averagevalue of the Gr and Gb signal output is 333 [LSB], measure the R signal output (VR [LSB]), the Gr andGb signal outputs (VGr, VGb [LSB]) and the B signal output (VB [LSB]) at the imaging area Center inframe readout mode, and substitute the values into the following formulas.
VG = (VGr + VGb)/2
RG = VR/VG
RB = VB/VG

Saturation signal
Set the measurement condition to the standard imaging condition II. After adjusting the luminous
Intensity to 20 times the intensity with the average value of the Gr, Gb signal outputs, 333 [LSB],
measure the average value of the Gr, Gb, R and B signal outputs.

Video signal shading
Set the measurement condition to the standard imaging condition III. With the lens diaphragm at F2.8,
adjust the luminous intensity so that the average value of the Gr and Gb signal outputs is 333 [LSB].
Then measure the maximum value (Gmax [LSB]) and minimum value (Gmin [LSB]) of the Gr and Gb
signal outputs, and substitute the values into the following formula.
SH = ((Gmax – Gmin)/Gmax) × 100 [%]Dark signal
Measure the output difference between 1/15 [s] signal output (Va) and 1/15000 or less [s] signal output(Vb) at the device ambient temperature of 60 ˚C and the device in the light-obstructed state, andcalculate the signal output at 1/15 [s] storage by them using the following approximate formula. Then,
this is Vdt [LSB].
Vdt = (Va – Vb) × (1/15)/(1/15) – (1/15000) ≈ (Va –Vb) [LSB]90

IMX219PQH5-C

14. Spot Pixel Specification
Table 48 Spot Pixel Specifications(15 frame/s, VANA = 2.8 V, VDIG = 1.2 V, VIF = 1.8 V, Tj = 60 ˚C)Maximum distorted pixels in each zone
Type ofdistortion

Level
Note 1)

Zone2D

Zone3

IneffectiveOB

EffectiveOB

Measurement
methodBlack or white
pixels at high light

30 % ≤ D40

No evaluation criteria applied

2

White pixels inthe dark

28 (LSB) ≤ D

600

No evaluation criteria applied

2

Note)

1.
2.
3.

Remarks

1/30 sstorage
Note 2)

D...Spot pixel level.
Continuous same color pixels in the horizontal or vertical direction are NG.
he above chart (hereinafter referred to as the “Spot Pixel Specifications”) is thestandard only for sorting image sensor products in this specification book (hereinafter referred to as
the “P ODUC S”) before shipment from a manufacturing factory. Sony Corporation and its
distributors (collectively hereinafter referred to as the “Seller”) disclaim and will not assume any
liability even if actual number of distorted pixels of the PRODUCTS delivered to you exceeds the
maximum number set forth in the White and Black Pixel Specifications. You are solely liable for any
claim, damage or liability arising from or in connection with such distorted pixels. If the Seller
separately has its own product warranty program for the P ODUC S (the “Program”), the conditionsin this specification book shall prevail over the Program and the Seller shall not assume any liability
under the Program to the extent there is contradiction.

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IMX219PQH5-C

15. Notice on White Pixels Specifications
After shipment inspection of CMOS image sensors, pixels of CMOS image sensors may be distorted and thendistorted pixels may cause white point effects in dark signals in picture images. (Such white point effects
shall be hereinafter referred to as "White Pixels.") Cosmic radiation is one of the causes of White Pixels.
Unfortunately, it is not possible with current scientific technology for CMOS image sensors to prevent such
distorted pixels. It is recommended that when you use CMOS image sensors, you should consider taking
measures against White Pixels, such as adoption of automatic compensation systems for White Pixels andestablishment of quality assurance standards.
White Pixels may be also caused by alpha radiation, which will be emitted in a process of decay of radioactive
isotopes which inevitably exist in the air in minute amounts and may exist in materials or parts of CMOS image
sensor devices (e.g. packaging materials, seal glass, wiring materials and IC chips). It is recommended thatyou should use materials or parts which do not include radioactive isotopes, which are sources of alpharadiation, and consider taking measures, such as adoption of vacuum packaging technologies in order toensure that the PRODUCTS are not exposed to the air. As the density of radioactive isotopes in the air of theunderground space may become thicker than that on the ground, it is highly recommended to ensure the
PRODUCTS are not exposed to the air in using or storing the PRODUCTS at the underground space.
[For Your Reference] The Annual number of White Pixels Occurrence Caused by Cosmic Radiation
The data in the below chart shows the estimated annual number of White Pixels occurrence caused by cosmic
radiation in a single-story building in Tokyo at an altitude of 0 meters. The data shows estimated number of White
Pixels based on records of past field tests calculated taking structures and electrical properties of each device into
account. However, the data in the chart is for your reference purpose only, and shall not be construed as part of any
CMOS image sensor product specifications which the Seller warrants.
Example of Annual Number of Occurrence
White Pixel Level (in case of integration time = 1/30 s)
Annual number of occurrence(Tj = 60 ˚C)
5.6 mV or higher
10.0 mV or higher
24.0 mV or higher
50.0 mV or higher
72.0 mV or higher

0.8
0.5
0.3
0.2
0.1

pcs
pcs
pcs
pcs
pcs

Note 1) The above data indicates the number of White Pixels occurrence when a CMOS image sensor is left
for a year.
Note 2) The annual number of White Pixels occurrence fluctuates depending on the CMOS image sensor storage
environment (such as altitude, geomagnetic latitude and building structure), time (solar activity effects)
and so on. Moreover, there may be statistic errors. Please take notice and understand that this is an
example of test data with experiments that have being conducted over a specific time period and ina specific environment.
Note 3) This data does not guarantee the upper limits of the annual number of White Pixels occurrence.
Note 4) As this data does not take occurrence of White Pixels caused by alpha radiation into account, White
Pixels are likely to occur at higher value than the rate set forth in such data.
For Your Reference:
The annual number of White Pixels occurrence caused by cosmic radiation at an altitude of 3,000 meters will befrom 5 to 10 times higher than that at an altitude of 0 meters because of the density of the cosmic rays. In addition,
in high latitude geographical areas such as London and New York, the density of cosmic rays increases due
to a difference in the geomagnetic density, so the annual number of White Pixels occurrence caused by cosmic
radiation in such areas approximately doubles when compared with that in Tokyo.

92

IMX219PQH5-C

15-1 Measurement Method for Spot Pixels
Measure under the standard imaging condition II.

15-2 Spot Pixel Pattern Specifications
Black or white pixels at high light
After adjusting the average value of the Gr/Gb signal output to 333 [LSB], measure the local dip point (black
pixel at high light, VXB) and peak point (white pixel at high light, VXK) in the Gr/Gb signal output Vx (x = Gr/Gb), andsubstitute the values into the following formula.

Fig. 48 Measurement Method for Spot Pixels

White pixels in the dark
Set the device to a dark setting and measure the local peak point of the signal output waveform using the
average value of the dark signal output as a reference.

93

IMX219PQH5-C

16. Chief Ray Angle Characteristics

IMX219 CRA
40

Angle ［°］

30

20

10

0
0

10

20

30

40
50
60
70
Image Height ［%］80

Fig. 49 Chief Ray Angle Characteristics

94

90

100

IMX219PQH5-C

17. Connection Example
VanaVdigVddl

2.2 µF2.2 µF
0.22 µF

VSSLSC4POREN
XCLR
TENABLEGPOFSTROBE
SDA

NC

Chip center(0,0)

VDDHCM1VSSLSC1VSSLCN1VSSHCM1VSSLSC2VSSLDM1VDDLCN1VDDHFIL1

VDDLCN2VSSLCN2

1.0 µFVSSHCM2

VCP
VBO
VSSHSN1VDDHSN1

2.2 µFVSSLSC3VDDHCM2NC
VDDLSC3VDDLSC1VSSHSN2VDDHSN2VDDHANVSSHANSCLTVMONTVCDSIN

TEST1
SWTCK
INCK
VDDMCOVSSLSC5VDDLSC5VDDHFIL2

NC
NC

NC
NC

VDDHPLVSSHPLVDDLIO1VSSLIO1
DMO1N
DMO1P
DMO2N
DMO2P
VSSLIO2DCKNDCKPVSSLIO3
DMO3N
DMO3P
DMO4N
DMO4P
VSSLIO4VDDLIO2VSSLSC7VDDLSC7VDDLSC6VSSLSC6VSSLDM2

Optical center(-0.025,-91.065 µm)

VDDLSC8VSSLSC8NC

AGNDDGND

Fig. 50 Recommended Circuit*1

Pad open size

75 µm × 75 µm *1

Pad pitch

120 µm

85 µm × 85 µm (Only VDDHFIL1 pad)Note) When fixing the voltage of chip back side, fix it to VDDHSN voltage
Note) GPO must be connected to GND, when GPO function is not enable.

95

IMX219PQH5-C

18. Notes On Handling
1. Static charge prevention
Image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
(1) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
(2) Use a wrist strap when handling directly.
(3) Install grounded conductive mats on the floor and working table to prevent the generation of static
electricity.
(4) Ionized air is recommended for discharge when handling image sensors.
(5) For the shipment of mounted boards, use boxes treated for the prevention of static charges.
2. Protection from dust and dirt
(1) Perform all work in a clean environment.
(2) Do not touch the chip surface with hand and make any object contact with it.
(3) Keep in a dedicated case to protect from dust and dirt. To prevent dew condensation, preheat or
precool when moving to a room with great temperature differences.
3. Others(1) Do not expose to strong light (sun rays) for long periods, as the color filters of color devices will
be discolored.
(2) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage
or use in such conditions.
(3) This product is precision optical parts, so care should be taken not to apply excessive mechanicalshocks or force.
(4) Reliability assurance of this product should be ignored because it is a bare chip.
(5) Note that imaging characteristics of the sensor may be affected when approaching strong
electromagnetic wave or magnetic field during operation.
(6) Note that X-ray inspection may damage characteristics of the sensor.
(7) Note that the sensor may be damaged when using ultraviolet ray and infrared laser for mounting it.
(8) Note that image may be affected by the light leaked to optical black when using an infrared cut
filter that has transparency in near infrared ray area during shooting subjects with high luminance.

96