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6 62L 5x 50v 55 and to develop additional hardware software interface 19 28. The foregoing techniques are described by thefollowing prior art patents: U.S. Pat. No. 5,274,700 to Lindley et al. entitled "MSI 80C100 chip-set peripheral controller"
describes a CPU-DMA "dispatcher" 14 that uses a queue RAM of dynamic memory 15 to provide a dispatcher queue of datathat can be addressed directly and independently of the CPU. When data to be written to dynamic memory 15 is detected, thedispatcher 14 shifts the data address registers 11 and 12, addresses dynamic memory 15 directly using register 21, and performs
an LPSDMA operation from registers 22-29. When the data read from dynamic memory 15 is detected, the dispatcher 14 shifts
the data address registers 11 and 12, addresses dynamic memory 15 directly using register 21, and performs a LPSDMA
operation from registers 22-29. The dispatcher 14 uses a read-modify-write technique that is composed of three separate
operations. The second of the three operations updates the data address registers. The first operation is a read operation fromdynamic memory 15. The third operation is a write operation from the data address registers. The LPSDMA operation is shifted
over the CPU bus by the dispatcher 14 using the bus interface 12-18. Data is transferred from the data address registers to thedata I/O registers 17-22 by the LPSDMA operation. The dispatcher 14 is used to perform LPSDMA operations in a manner
similar to the LPSDMA operations performed by the memory controller 9 of the invention. U.S. Pat. No. 5,241,385 toOkamura et al. entitled "I/O subsystem having read modify write buffer in I/O controller" describes an I/O subsystem thatenables one memory location to be read, modified, and written simultaneously. When the same memory location is read,modified, and written, the I/O controller is said to be a Read-Modify-Write (RMW) controller. The I/O controller has an I/Obase address register which holds the address that is to be read, modified, and written. An I/O access register is used to set theoperation to be performed at each cycle. The I/O access register is connected to a control register which is controlled by aprocessor through a processor bus. The I/O base address register is connected to a register bank ofDownload Mcgs Embedded Configuration Software 12 8l Audio Mp3 In 320 Kbps, 256 Kbps, 192 Kbps, 128 Kbps Highquality for free File Name: Mcgs Embedded Configuration Software 12 8l Duration: 24 Minutes 3 Seconds Updated: January 05
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