IEEE Std 1149.1(JTAG) Testability

Primer1997
Printed in U.S.A.
1096–AL

SSYA002C

Semiconductor GroupIEEE Std 1149.1(JTAG) Testability
Primer

SSYA002Ci

IMPORTANT NOTICE
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Copyright  1996, Texas Instruments Incorporated

ii

Contents

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SUPPORT
Device Boundary-Scan Description Language (BSDL) files
and other information regarding Texas Instruments IEEE Std
1149.1/JTAG/boundary-scan products are maintained on theWorld-Wide Web at URL http://www.ti.com/sc/docs/jtag/
jtaghome.htm; or, on the main Texas Instruments home pageat URL http://www.ti.com. Search for keywords JTAG
and testability.

iii

Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Overall Rationale for Design for Test . . . . . . . . . . . . . . . . . 1-2
Reduced Cost and Higher Quality . . . . . . . . . . . . . . . . . . . 1-3
Benefits Over Standard Test Methods . . . . . . . . . . . . . . . . 1-3
Standard Test Solutions Versus Proprietary Solutions . . . 1-5
An Industry Standard — IEEE Std 1149.1-1990(JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Benefits of Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Traditional Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Efficient Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Lower Cost for Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Production Time Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Easier Board-Level Isolation . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Simple Access to Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Boundary-Scan Architecture
and IEEE Std 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Boundary-Scan Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Test Interface and Boundary-Scan Architecture . . . . . . . . 3-3
Test Access Port and Operation . . . . . . . . . . . . . . . . . . . . . 3-5
IEEE Std 1149.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Instruction Register (Required) . . . . . . . . . . . . . . . . . . 3-8
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
IEEE Std 1149.1 Required Instructions . . . . . . . . . . . . . . 3-12
BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . 3-12
EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
IEEE Std 1149.1 Optional Instructions . . . . . . . . . . . . . . . 3-13
INTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
RUNBIST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
USERCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . 3-14
Obtaining IEEE Std 1149.1-1990 . . . . . . . . . . . . . . . . . . . 3-15v

Using DFT in ASICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Design-for-Test Considerations . . . . . . . . . . . . . . . . . . . . . . 4-1
The Need for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Test-Time Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Time to Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Fault Coverage and Cost of Ownership . . . . . . . . . . . . . . . 4-5
Developing Testability Strategies . . . . . . . . . . . . . . . . . . . . 4-8
Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Boundary-Scan Description Language (BSDL) . . . . . . . . 5-1
How BSDL Is Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Elements of BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Verifying BSDL Accuracy . . . . . . . . . . . . . . . . . . . . . . . 5-4
Potential BSDL Errors . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
How to Receive the BSDL Specification . . . . . . . . . . 5-5
Obtaining BSDL for TI Devices . . . . . . . . . . . . . . . . . . 5-5
Hierarchical Scan Description Language (HSDL) . . . . . . 5-6
Elements of HSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
How to Receive the HSDL Specification . . . . . . . . . . 5-8
Serial Vector Format (SVF) . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
SVF Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Default State Transitions . . . . . . . . . . . . . . . . . . . . . . 5-12
SVF Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
How to Receive the SVF Specification . . . . . . . . . . 5-16
Suggested Design-for-Test Flow . . . . . . . . . . . . . . . . . . . 6-1
Test Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Built-In Self-Test (BIST) Methodology . . . . . . . . . . . . . . . . 6-3
Internal Scan Test Methodology . . . . . . . . . . . . . . . . . . . . . 6-3
Design Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
IC Design Implementation . . . . . . . . . . . . . . . . . . . . . . 6-4
IC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Using SVF for IC Design Validation . . . . . . . . . . . . . . 6-6
Data Passed to Board Designer . . . . . . . . . . . . . . . . . 6-7
Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Partitioned Scan Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
vi

Contents

Board Validation/Manufacturing Test . . . . . . . . . . . . . . . . . 6-9
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Board-Etch and Solder-Joint Testing . . . . . . . . . . . . . . . . . 7-1
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Cluster Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Board-Edge Connector Testing . . . . . . . . . . . . . . . . . . . . . . 7-7
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
ASIC Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Memory-Testing Techniques . . . . . . . . . . . . . . . . . . . . . . . 7-12
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Backplane Multidrop Environment . . . . . . . . . . . . . . . . . . 7-17
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Embedded Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Boundary-Scan Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
vii

Product Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
IEEE Std 1149.1-Compatible Components . . . . . . . . . . . . 8-1
Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
IEEE Std 1149.1 (JTAG) Boundary-Scan Logic . . . . . . . . 8-2
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Universal Bus Transceiver (UBT) . . . . . . . . . . . . . . 8-4
Scan Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Other Support and Learning Products . . . . . . . . . . . . . 9-1
Scan Educator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Scan Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Supporting Documentation Included . . . . . . . . . . . . . 9-3
CD-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Testability Video Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Appendix A — Abbreviations/Acronyms . . . . . . . . . . . A-1
Appendix B — Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Appendix C — References . . . . . . . . . . . . . . . . . . . . . . . . C-1
Appendix D — Internet Starting Points . . . . . . . . . . . . . D-1
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1

viii

Contents

Illustrations
1-1
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
6-1
6-2
6-3
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11

Chip Through System-Level Test . . . . . . . . . . . . . . 1-1
Boundary-Scan Testing Using theIEEE Std 1149.1 Bus . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Boundary-Scan Example . . . . . . . . . . . . . . . . . . . . . 3-2
Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . 3-4
TAP Controller State Diagram . . . . . . . . . . . . . . . . . 3-5
TAP Control Output Interconnect Diagram . . . . . . 3-7
General Instruction Register Architecture . . . . . . . 3-8
Test Data Register Architecture . . . . . . . . . . . . . . . 3-10
Conceptual View of aControl-and-Observe BSC . . . . . . . . . . . . . . . . . . . 3-11
Device Identification Register Structure . . . . . . . . 3-11
Fault Grade Versus Development Time . . . . . . . . . 4-3
Economic Trade-Off for a Testable Design . . . . . . 4-4
Defect Level Versus Fault Coverage . . . . . . . . . . . 4-5
Motorola and Delco Study Results . . . . . . . . . . . . . 4-6
ASIC ppm Versus PCB ppm Rate . . . . . . . . . . . . . . 4-7
Cost of Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Testability Development Flow . . . . . . . . . . . . . . . . 4-11
Scan Path of Six ICs . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Initial DFT Concerns . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Designing Testability for ASICs and Boards . . . . . 6-4
Debug and Verification of a
Boundary-Scan Design . . . . . . . . . . . . . . . . . . . . . . . 6-7
Etch/Interconnect Testing . . . . . . . . . . . . . . . . . . . . . 7-2
Open-Etch Condition . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Open-Solder-Joint Condition . . . . . . . . . . . . . . . . . . 7-3
Short-to-Ground Condition . . . . . . . . . . . . . . . . . . . . 7-3
Bond-Wire Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Cluster Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Backplane Open-Circuit Fault . . . . . . . . . . . . . . . . . 7-8
PWB Connector Fault . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Backplane Short-to-Ground Fault . . . . . . . . . . . . . . 7-9
Block Diagram of Simplified
Boundary-Scannable RAM Interface . . . . . . . . . . 7-13
Testing Embedded RAM . . . . . . . . . . . . . . . . . . . . . 7-15
ix

7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
8-1

x

Testing Embedded ROM . . . . . . . . . . . . . . . . . . . . 7-16
Backplane Ring Configuration . . . . . . . . . . . . . . . . 7-18
Backplane Star Configuration . . . . . . . . . . . . . . . . 7-19
Backplane With ASP-Equipped Boards . . . . . . . . 7-20
General Boundary-Scan Test . . . . . . . . . . . . . . . . . 7-25
Assembly Verification Flow . . . . . . . . . . . . . . . . . . 7-26
Automated Functional Verification andFault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Interactive Verification and Fault Isolation . . . . . . 7-28
TI’s Family of IEEE Std 1149.1 (JTAG)
Boundary-Scan Logic . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Contents

Tables
1-1
1-2
5-1
5-2
7-1

High-Technology Product Scenarios . . . . . . . . . . . . . 1-3
Time to Develop Test Programs (in Man-Months) . . 1-4
SVF TAP State Names . . . . . . . . . . . . . . . . . . . . . . . 5-13
Stable-State Path Examples . . . . . . . . . . . . . . . . . . 5-14
Access Rates of IEEE Std 1149.1 Devices
With and Without BIST . . . . . . . . . . . . . . . . . . . . . . . 7-14
8-1 IEEE Std 1149.1 UBTs Replace
50+ Bus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

xiChapter 1
Introduction
Design for test (DFT), also known as design for testability, isa process that incorporates rules and techniques in thedesign of a product to make testing easier.
Structured design for test is a system methodology rather
than a collection of discrete techniques. This methodology
impacts all phases of a product’s life, from device circuitdesign through field service. Design for test is used to
manage complexity, minimize development time, and reduce
manufacturing costs.
Testing has two major aspects: control and observation. To
test any system it is necessary to put the system into aknown state, supply known input data (test data), andobserve the system to see if it performs as designed andmanufactured. If control or observation cannot be carried out,
there is no way to know empirically if the system performs as
it should.
During the normal product development flow, testing (it may
be known by different names) takes place at many points
during the process. If testing is considered at the chip designlevel, its benefits can be used at all levels of electronic
assembly, from chip through system level. See Figure 1-1.
IC
Test

Board
Test

Box
Test

SystemTest

Figure 1-1. Chip Through System-Level Test

1-1

Designers usually test various functions to validate theirdesign. Manufacturing and customer groups subject thedesign to an assortment of unique criteria to see if theconcept works in practice. Is it manufacturable? Will it standup to real-world operating conditions? Will repair be cost
efficient? In addition to direct testability considerations,production managers want features designed into the
product to help them minimize scrap and manufacturingcosts. Good system-testability methodology provides anintegrative function throughout the product development
cycle and allows materials created during an early phase ofdevelopment to be reused in later phases. Various chip
designers have used this integration feature as a tool to help
manage the development of complex products.
Testability provides companies with a firmer grasp on theeconomic and market-window constraints due to productdevelopment. One major workstation manufacturer claimed:
Test program development would have been nearly
impossible without scan techniques.
Chip-level test development time fell from 1 man-year toabout 20 hours.
Board-level test development time fell from multiple
man-years to about a week.
Three months were cut off development time.

Overall Rationale for Design for Test
Manufacturers of state-of-the-art electronic products face aunique set of problems. Although modern circuit density, highdevice speed, surface-mount packaging, and complex
board-interconnect technology have a positive influence onstate-of-the-art electronic systems, these factors canadversely affect ability to verify correct design and operation.
Increased complexity and lack of physical access to circuitry
makes for costly and time-consuming testing using traditional
test techniques.

1-2

Introduction

Reduced Cost and Higher Quality
Reacting to this complexity, with an eye on the bottom line,
manufacturers may opt to perform less rigorous testing.
Manufacturers who choose the less rigorous testing as an
expeditious alternative to the expense of full testing gamble
their technical credibility in the marketplace and expose
themselves to the high cost of product returns. In today’s
global electronics marketplace, a manufacturer who delivers
poorly tested products does not remain competitive. The costfor detecting and identifying faults using traditional test
methods increases by an order of magnitude as a circuit’s
level of complexity increases. These increased costs anddevelopment time reduce profit margins, delay productintroduction, and reduce time-to-market windows. An
increasing number of companies have simultaneously
improved their product quality and profit margins by adopting
system-level (integrative) design methods. Design for test is
one such system-level approach.

Benefits Over Standard Test Methods
Time to market is more important than ever in the hightechnology marketplace. Companies that can produce quality
products with a short product development cycle-time have acompetitive advantage. Designing testability into a system
can play an important role in introducing a new
high-technology product with an expected five-year life cycle
to market on time. Table 1-1 shows various productdevelopment time/budget scenarios and the resulting project
profitability.
Table 1-1. High-Technology Product Scenarios {Product
A

Product
B

ProductC

To Market:

on timeon time6 mos. late

Budget:on

50% over

on

100%

96%

66%

Available Profit
Over 5 Years:{Source:McKinsey & Company
1-3Adding testability to a product increases design time andcosts, while reducing costs of design validation,
manufacturing test, and system maintenance.
The system design phase of product development
represents only 15 percent of a product’s total life-cycle cost.
However, the system design phase has a 70-percent impact
on a product’s operation and support costs over the product’s
total life (source: Mitre Corporation, 1987 Government
Microcircuit Applications Conference).
The majority of faults found on boards, such as solder joints(shorts and opens), components (wrong device, missing
device, wrong orientation, wire-bond failure, and stuck pins),
etch integrity, and connector faults, make up over 95 percent
of failures found. A structured technique such as
boundary-scan testing allows for pins-out testing to easily
detect these failures (source: Teradyne).
The additional cost of designing testability into a system
during the system design phase can be more than offset
over the product’s total life.
Design cycle times have shortened significantly over theyears while test program development time has increased,
necessitating that companies adopt structured or repeatable
methodologies. Table 1-2 documents the increase in test
program development time as test requirements increase.
Table 1-2. Time to Develop Test Programs (inMan-Months) †1987–1980

3–6 months

1981–1983

6–12 months

1984–1986

9–18 months

1987–1990

12–24 months†Source: Texas Instruments

1-4

Introduction

Standard Test Solutions Versus Proprietary
SolutionsEmbedded test, emulation, and maintenance circuitry are
well defined and understood within the test community.
Previously, the lack of standards caused these structures tobe implemented in an ad hoc and proprietary manner. Since
proprietary solutions are usually more expensive and labor
intensive, the added costs further limited the use of thesetest circuits. Boundary-scan testing combined with acommon test bus interface and test protocol has thesebenefits:
Provides a standard and cost-effective solution to
traditional test problems
Opens new applications
The ability to reuse previously developed test data and touse less costly test equipment means that this approachyields products that are less expensive to manufacture.

An Industry Standard — IEEE Std 1149.1-1990(JTAG)In 1985, an ad hoc group composed of key electronic
manufacturers joined to form the Joint Test Action Group(JTAG). JTAG had over 200 members around the world,
including major electronics and semiconductor
manufacturers. This group met to establish a solution to the
problems of board test and to promote a solution as anindustry standard. The solution, which became IEEE Std
1149.1-1990, IEEE Standard Test Access Port andBoundary-Scan Architecture, is the basis for Texas
Instruments (TI) testability products. IEEE Std 1149.1
allows test instructions and data to be serially loaded into a
device and enables the subsequent test results to be seriallyread out.
Every IEEE Std 1149.1-compatible device has four additional
pins — two for control and one each for input and output
serial test data. To be compatible, a component must havecertain basic test features, but IEEE Std 1149.1 allows
designers to add test features to meet their own uniquerequirements. The specification was adopted as an IEEE
standard in February 1990.
1-5

Chapter 2
Benefits of Testability
This chapter explains how designing testability into devices
eliminates problems associated with traditional testing andimproves quality and efficiency.

Traditional Testing
Traditional board-level and device-level testing consumes agreat deal of time and requires special hardware andcomplex automatic test equipment (ATE) for each type ofboard or device. This results in increased costs anddevelopment time. In addition, extensive testing is necessary
for the evermore stringent reliability standards andperformance standards in the defense, aerospace,automotive, computer, and communications industries.
These extensive tests can delay the market introduction of
products, disrupt just-in-time (JIT) manufacturing flows, andlimit the productivity of standard ATE operations. This
creates numerous problems because time to market is more
important than ever in the high-technology marketplace.
Companies that produce quality products with a shortproduct-development cycle time have a competitive
advantage.

Efficient Testing
An innovative approach to the problems inherent withtraditional testing is to incorporate design-for-test techniquesthat allow embedded testing to be performed. For example,
data can be scanned in to stimulate internal system nodes
while the component or circuit is embedded within thesystem. During the same scan, the previous condition ofeach node is scanned out. This saves test time and reduces
the number of test vectors needed.

Lower Cost for Testing
The additional cost of designing testability into a system
during the design phase is more than offset over the
product’s total life. This is accomplished by reducing the test
program development time, minimizing fixture complexity,
and allowing for the use of lower-cost ATE solutions. Anothercost benefit is the economy of scale gained by having astandard test approach that spans design, test, manufacture,
field repairs, and maintenance.
2-1

Production Time Savings
Board-level boundary-scan testing is easily implemented
using TI’s line of IEEE Std 1149.1 testability devices, suchas:Widebus and octal bus interfaces
Scan-support devices
ASIC and DSP
These IEEE Std 1149.1-compliant devices are included inboard design with little modification to existing circuitry.
Embedded testability greatly reduces the need for other test
points on the board, and offers these advantages:
Greatly simplified test fixtures
Reduced fixture construction time
Sophisticated built-in test and debug operations
Many ICs or boards can be tested together using the serialIEEE Std 1149.1 test bus under the control of boundary-scan
test software.

Easier Board-Level Isolation
Fault isolation on a printed circuit board can be greatly
improved by electronically isolating suspect areas using
boundary-scannable devices. The IEEE Std 1149.1 test bus
controls boundary-scannable devices to place them in
EXTEST for pins-out testing. This effectively partitions or
isolates circuitry for separate testing. Partitioning a systemusing IEEE Std 1149.1-compliant devices reduces thenumber of patterns required for testing each circuit area. See
Figure 2-1 for an example of a design than can bepartitioned.

Simple Access to Circuits
Highly integrated, modern, multilayer systems or lCs with
fine-pitch pins are virtually impossible to access using
manual probes or ATE. Some boards require extensive
fixturing or redesign before they can be tested effectively.
TI’s testability devices with boundary-scan architecture
eliminate physical access problems. These parts provide thedesigner with testability for the most complex andhard-to-access circuits, and add controllability of test circuits.
In addition, a designer can easily observe and control
internal device functions.
2-2

Benefits of Testability

TDI

TDO

UBT
(buffer)

Buffer’BCT8244

UBT
Data (xcvr)

Control’LVTH18502

TDO

Address
Memory Array

Logic

Buffer’BCT8244

Microprocessor’LVTH18504’ABTH18504

UBT(latch)Data

TDI’LVTH18245

TDO

TDI
IEEE Std 1149.1
Bus

TDI

TDO

TCK

Parallel Data In/Out

TMS

Edge
Connector

Figure 2-1. Boundary-Scan Testing Using the IEEE Std
1149.1 Bus

2-3

Chapter 3
Boundary-Scan Architecture
and IEEE Std 1149.1
Boundary scan is a special type of scan path with a register
added at every I/O pin on a device. Although this requires
the addition of a special test latch on some pins, thetechnique offers several important benefits. The mostobvious benefit offered by the boundary-scan technique isallowing fault isolation at the component level. Such anisolation requirement is common in telecomunications
switching environments where prompt field repair is critical.
A major problem driving the development of IEEE Std 1149.1
boundary scan is the adverse effect of surface-mounttechnology. The inclusion of a boundary-scan path insurface-mount components, in many cases, affords the only
way to perform continuity tests between devices. By placing
a known value on an output buffer of one device andobserving the input buffer of another interconnected device, itis easy to see if the printed wiring board (PWB) net iselectrically connected. Failure of this simple test indicatesbroken circuit traces, cold solder joints, solder bridges, orelectrostatic-discharge (ESD) induced failures in an IC
buffer — all common problems on PWBs.
A less-obvious advantage of the boundary-scanmethodology is the ability to apply predeveloped functional
pattern sets to the I/O pins of the IC by way of the scan path.
IC manufacturers and ASIC developers create functional
pattern sets for DC test purposes. Subsets of these patterns
can be reused for in-circuit functional IC testing. Reusing
existing patterns in the development of system diagnostics
can save large amounts of development resources,
especially if many of the ICs in a system have embedded
boundary-scan paths.
IEEE Std 1149.1 is a common protocol and boundary-scanarchitecture developed into an industrial standard after
thousands of man hours of cooperative development byapproximately 200 major international electronics firms. Early
contributors in the development of IEEE Std 1149.1 were
AT&T, DEC, Ericsson, IBM, Nixdorf, Philips, Siemens,
and TI. These companies recognized that only anonproprietary architecture would encourage companies to
3-1

offer the compatible integrated circuits, test equipment, andCAD software needed to bring product development,
manufacturing, and test costs under control in today’scompetitive electronics marketplace. Many people believethat boundary-scan architecture will do for development,
manufacturing, and test what the RS-232C standard did forcomputer peripherals.

Boundary-Scan Overview
Boundary scan is the application of a scan path at theboundary (I/O) of ICs to provide controllability andobservability access via scan operations. Figure 3-1 showsan IC with an application-logic section and related input andoutput, and a boundary-scan path consisting of a series ofboundary-scan cells (BSCs), in this case one BSC per ICfunction pin.

NDI

BSC

Application
Logic

NDO
BSC

TDI

TDO

Figure 3-1. Boundary-Scan Example
The BSCs are interconnected to form a scan path between
the host IC’s test data input (TDI) pin and test data output(TDO) pin. During normal IC operation, input and output
signals pass freely through each BSC, from the normal data
input (NDI), to the normal data output (NDO). However, when
the boundary-test mode is entered, the IC’s boundary iscontrolled in such a way that test stimulus can be shifted inand applied from each BSC output (NDO), and test response
can be captured at each BSC input (NDI) and shifted out for
inspection. External testing of wiring interconnects andneighboring ICs on a board assembly is accomplished byapplying test stimulus from the output BSCs and capturing
test response at the input BSCs. As an option, internal
testing of the application logic can be accomplished by
3-2

Boundary-Scan Architecture and IEEE Std 1149.1

applying test stimulus from the input BSCs and capturing test
response at the output BSCs. The implementation of a scanpath at the boundary of IC designs provides an embedded
testing capability that can overcome the physical accessproblems in current and future board designs.

Test Interface and Boundary-Scan Architecture
Figure 3-2 shows the IEEE Std 1149.1 architecture. The
architecture consists of an instruction register, a bypass
register, a boundary-scan register (highlighted), optional user
data register(s), and a test interface referred to as the test
access port (TAP). In Figure 3-2, the boundary-scan register(BSR), a serially accessed data register made up of a seriesof boundary-scan cells (BSCs), is shown at the input andoutput boundary of the IC.
The instruction register and data registers are separate scanpaths arranged between the primary test data input (TDI) pin
and primary test data output (TDO) pin. This architecture
allows the TAP to select and shift data through one of the two
types of scan paths, instruction or data, without accessing
the other scan path.

3-3

BSC
BSC
Core Logic

BSC

Output
Pins

BSC

BSC

BSC

Input
Pins

BSC

BSC

OE

BSC

Boundary-Scan Register

User Data
Register
BypassResister

TDI

Instruction
Register
TMS
TCK

TAP

TDO

Note: The boundary-scan register is shifted TDI to TDO.

Figure 3-2. Boundary-Scan Architecture

3-4

Boundary-Scan Architecture and IEEE Std 1149.1

Test Access Port and Operation
The TAP is controlled by the test clock (TCK) and test mode
select (TMS) inputs. These two inputs determine whether an
instruction register scan or data register scan is performed.
The TAP consists of a small controller design, driven by the
TCK input, which responds to the TMS input as shown in thestate diagram in Figure 3-3. The IEEE Std 1149.1 test bus
uses both clock edges of TCK. TMS and TDI are sampled on
the rising edge of TCK, while TDO changes on the fallingedge of TCK.
Test-Logic-Reset
1

0
1

1

1

Run-Test/Idle

Select-DR-Scan0

Select-IR-Scan00Capture-DR

1

1

Capture-IR00

Shift-DR

Shift-IR

1

1

0

0

1

1
Exit1-DR

Exit1-IR
0

0

Pause-IR

Pause-DR
0

1

1
Exit2-DR
0

0

1

1

Update-DR1

0

Exit2-IR0

Update-IR10Note: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the rising edge of TCK.

Figure 3-3. TAP Controller State Diagram

3-5

The main state diagram consists of six steady states:
Test-Logic-Reset, Run-Test/Idle, Shift-DR, Pause-DR,
Shift-IR, and Pause-IR. A unique feature of this protocol isthat only one steady state exists for the condition when TMS
is set high: the Test-Logic-Reset state. This means that a
reset of the test logic can be achieved within five TCKs or
less by setting the TMS input high.
At power up, or during normal operation of the host IC, the
TAP is forced into the Test-Logic-Reset state by driving TMS
high and applying five or more TCKs. In this state, the TAP
issues a reset signal that places all test logic in a condition
that does not impede normal operation of the host IC. Whentest access is required, a protocol is applied via the TMS and
TCK inputs, causing the TAP to exit the Test-Logic-Resetstate and move through the appropriate states. From the
Run-Test/Idle state, an instruction register scan or a dataregister scan can be issued to transition the TAP through theappropriate states shown in Figure 3-3.
The states of the data register scan and instruction registerscan blocks are mirror images of each other, adding
symmetry to the protocol sequences. The first action that
occurs when either block is entered is a capture operation.
For the data registers, the Capture-DR state is used tocapture (or parallel load) the data into the selected serial
data path. If the BSR is the selected data register, the normal
data inputs (NDIs) are captured during this state. In the
instruction register, the Capture-IR state is used to capture
status information into the instruction register.
From the Capture state, the TAP transitions to either the Shiftor Exit1 state. Normally, the Shift state follows the Capturestate so that test data or status information can be shifted out
for inspection and new data shifted in. Following the Shiftstate, the TAP either returns to the Run-Test/Idle state via the
Exit1 and Update states or enters the Pause state via Exit1.
The reason for entering the Pause state is to temporarilysuspend the shifting of data through either the selected dataregister or instruction register while a required operation,such as refilling a tester memory buffer, is performed. From
the Pause state, shifting can resume by re-entering the Shiftstate via the Exit2 state or be terminated by entering the
Run-Test/Idle state via the Exit2 and Update states.

3-6

Boundary-Scan Architecture and IEEE Std 1149.1

Upon entering the data register scan or instruction registerscan blocks, shadow latches in the selected scan path areforced to hold their present state during the capture and shiftoperations. The data being shifted into the selected scanpath is not output through the shadow latch until the TAP
enters the Update-DR or Update-IR state. The Update state
causes the shadow latches to update (or parallel load) with
the new data that has been shifted into the selected scanpath.
Figure 3-4 shows the TAP control output signals, along with
the instruction register and data register interconnects.
MSB
TDI

LSB

Instruction Register

1
TDO
0

CLOCKIR
UPDATEIRSHIFTIRTMSRESET*TAP
TCK

SELECT
ENABLESHIFTDR
UPDATEDR
CLOCKDR

Data Register
MSB

LSB

Figure 3-4. TAP Control Output Interconnect Diagram

3-7

IEEE Std 1149.1 Registers
This section contains descriptions of the required andoptional registers specified in IEEE Std 1149.1-1990.
Instruction Register (Required)
The instruction register is responsible for providing theaddress and control signals required to access a particular
data register in the scan path. The instruction register isaccessed when the TAP receives an instruction register scan
protocol. During an instruction register scan operation the
SELECT output from the TAP (Figure 3-4) selects the outputof the instruction register to drive the TDO pin. A general
instruction register architecture is shown in Figure 3-5.
STATUS 0
STATUS 1
STATUS 6
STATUS 7
7
TDI
CLOCKIR

UPDATEIR

1

0

TDO

Instruction
Shift Register

SHIFTIRRESET*

6

7

6

1

0

Instruction
Shadow Latch

7

6

1

0

Instruction Register Outputs

Figure 3-5. General Instruction Register Architecture
The instruction register consists of an instruction shift
register and an instruction shadow latch. The instruction shift
register (Figure 3-5) consists of a series of shift register bits
arranged to form a single scan path between the TDI andTDO pins of the host IC. During instruction register scan
operations, the TAP exerts control via the instruction register
shift enable (SHIFTIR) and instruction register clock

3-8

Boundary-Scan Architecture and IEEE Std 1149.1

(CLOCKIR) signals to cause the instruction shift register topreload status information and shift data from TDI to TDO.
Both the preload and shift operations occur on the risingedge of TCK; however, the data shifted out from the host IC
from TDO occurs on the falling edge of TCK. The status
inputs are user-defined observability inputs, except for thetwo least-significant bits, which are always 01 for scan-path
testing purposes. (The instruction register has a minimum
length of two bits.)
The instruction shadow register (Figure 3-5) consists of aseries of latches, one latch for each instruction shift registerbit. During an instruction register scan operation, the latchesremain in their present state. At the end of the instruction
register scan operation, the instruction register update(UPDATEIR) input updates the latches with the new
instruction installed in the instruction shift register. When
activated, the RESET* input sets the instruction shadow
register to the value of the BYPASS instruction (or IDCODE
instruction, if it is supported). This forces the device into its
normal functional mode and selects the bypass register (ordevice identification register, if one is present).
Data Registers
IEEE Std 1149.1 requires two data registers; boundary-scanregister and bypass register, with a third, optional, device
identification register. Additional user-defined data registers
can be included. The data registers are arranged in parallelfrom the primary TDI input to the primary TDO output. The
instruction register supplies the address that allows one ofthe data registers to be accessed during a data register scan
operation. During a data register scan operation, theaddressed scan register receives TAP control via the dataregister shift enable (SHIFTDR) and data register clock(CLOCKDR) inputs to preload test response and shift datafrom TDI to TDO. During a data register scan operation, the
SELECT output from the TAP (Figure 3-4) selects the outputof the data register to drive the TDO pin. When one scanpath in the data register is being accessed, all other scanpaths remain in their present state.

3-9

Boundary-Scan Register

Device Identification Register
G

Optional
Design-Specific Test Data Register
From
TDI

Optional

MUX

To
TDO
MUX

Design-Specific Test Data Register
Optional
Design-Specific Test Data Register
Optional
Bypass Register

Clock and Control Signals From Instruction
Register, TAP Controller, etc.

Figure 3-6. Test Data Register Architecture
Boundary-Scan Register — The boundary-scan register(BSR) consists of a series of boundary-scan cells(BSCs) arranged to form a scan path around theboundary of the host IC. The BSCs provide thecontrollability and observability features required toperform boundary-scan testing as described in the
Boundary-Scan Overview section of this chapter.
Shadow latches in the BSCs, driving the NDO outputs
remain in their present state during a data register scan
operation. At the end of a data register scan operation,
the data register update (UPDATEDR) input updates
the shadow latches with the new boundary test pattern
to be applied from the NDO outputs of the BSCs.
Figure 3-7 shows a conceptual view of acontrol-and-observe BSC.

3-10

Boundary-Scan Architecture and IEEE Std 1149.1

SerialOutputShiftDRIR Decode
Mode
G

NDI

1
G
1
1

Serial Input

1
1D

1D

C1

C1

NDO

ClockDR UpdateDR

Figure 3-7. Conceptual View of a Control-and-Observe BSC
Bypass Register (Required) — The bypass register consistsof a single scan register bit. When selected, the bypass
register provides a single-bit scan path between TDI
and TDO. Thus, the bypass register allows abbreviating
the scan path through devices that are not involved in
the test. The bypass register is selected when the
instruction register is loaded with a pattern of all ones tosatisfy the IEEE Std 1149.1 BYPASS instruction
requirement.
Device Identification Register (Optional) — The device
identification register is an optional register, defined byIEEE Std 1149.1, to identify the device’s manufacturer,
part number, revision, and other device-specificinformation. Figure 3-8 shows the bit assignments
defined for the device identification register. These bits
can be scanned out of the device identification register
after its selection.
MSB

LSB
1

Version(bits 31–28)

Part Number(bits 27–12)

Fixed(bit 0)

Manufacturer Identity(bits 11–1)

Figure 3-8. Device Identification Register Structure
Although the device identification register is optional,
IEEE Std 1149.1 has dedicated an instruction to select
3-11this register. The device identification register isselected when the instruction register is loaded with the
IDCODE instruction, the bit code of which is defined by
the vendor.
Manufacturer’s identity codes (bit1 through bit11) are
assigned, maintained, and updated by the EIA/JEDEC
office. Any company can be added to the JEDECStandard Manufacturer’s Identification Code(Publication JEP106) by request to the JEDEC office at
202-457-4973.

IEEE Std 1149.1 Required Instructions
IEEE Std 1149.1 defines nine test instructions. Of the nine
instructions, three are required and six are optional. The
following subsections contain brief descriptions of eachrequired test instruction.
BYPASS Instruction
The required BYPASS instruction allows the IC to remain in afunctional mode and selects the bypass register to beconnected between TDI and TDO. The BYPASS instruction
allows serial data to be transferred through the IC from TDI
to TDO without affecting the operation of the IC. The bit codeof this instruction is defined as all ones by IEEE Std 1149.1.
SAMPLE/PRELOAD Instruction
The required SAMPLE/PRELOAD instruction allows the IC toremain in its functional mode and selects the boundary-scanregister to be connected between TDI and TDO. During this
instruction, the boundary-scan register can be accessed via
a data scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used topreload test data into the boundary-scan register before
loading an EXTEST instruction. The bit code for this
instruction is defined by the vendor.

3-12

Boundary-Scan Architecture and IEEE Std 1149.1

EXTEST Instruction
The required EXTEST instruction places the IC into an
external boundary-test mode and selects the boundary-scanregister to be connected between TDI and TDO. During this
instruction, the boundary-scan register is accessed to drive
test data off-chip via the boundary outputs and receive test
data off-chip via the boundary inputs. The bit code of this
instruction is defined as all zeroes by IEEE Std 1149.1.

IEEE Std 1149.1 Optional Instructions
The following subsections contain brief descriptions of theoptional IEEE Std 1149.1 instructions.
INTEST Instruction
The optional INTEST instruction places the IC in an internalboundary-test mode and selects the boundary-scan registerto be connected between TDI and TDO. During this
instruction, the boundary-scan register is accessed to drive
test data on-chip via the boundary inputs and receive test
data on-chip via the boundary outputs. The bit code of this
instruction is defined by the vendor.
RUNBIST Instruction
The optional RUNBIST instruction places the IC in a self-test
mode, enables a comprehensive self-test of the IC’s core
logic, and selects a user-specified data register to beconnected between TDI and TDO. During this instruction, theboundary outputs are controlled so that they cannot interferewith neighboring ICs during the RUNBIST operation. Also,
the boundary inputs are controlled so that external signals
cannot interfere with the RUNBIST operation. The bit code ofthis instruction is defined by the vendor.
CLAMP Instruction
The optional CLAMP instruction sets the outputs of an IC tologic levels determined by the contents of the boundary-scanregister and selects the bypass register to be connected
between TDI and TDO. Before loading this instruction, thecontents of the boundary-scan register can be preset with
the SAMPLE/PRELOAD instruction. During this instruction,
data can be shifted through the bypass register from TDI to
3-13

TDO without affecting the condition of the outputs. The bitcode of this instruction is defined by the vendor.
HIGHZ Instruction
The optional HIGHZ instruction sets all outputs (including
two-state as well as three-state types) of an IC to a disabled(high-impedance) state and selects the bypass register to beconnected between TDI and TDO. During this instruction,
data can be shifted through the bypass register from TDI to
TDO without affecting the condition of the IC outputs. The bitcode of this instruction is defined by the vendor.
IDCODE Instruction
The optional IDCODE instruction allows the IC to remain in
its functional mode and selects the optional device
identification register to be connected between TDI and
TDO. The device identification register (see Figure 3-8) is a
32-bit shift register containing information regarding the IC
manufacturer, device type, and version code. Accessing thedevice identification register does not interfere with theoperation of the IC. Also, access to the device identification
register should be immediately available, via a TAP
data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional TRST* pin or byotherwise moving to the Test-Logic-Reset state. The bit codeof this instruction is defined by the vendor.
USERCODE Instruction
The optional USERCODE instruction allows the IC to remain
in its functional mode and selects the device identification
register to be connected between TDI and TDO. During the
USERCODE instuction, the optional 32-bit device
identification register captures user-defined information
about the IC. Accessing the device identification register
does not interfere with the operation of the IC. The bit codeof this instruction is defined by the vendor.

3-14

Boundary-Scan Architecture and IEEE Std 1149.1

Obtaining IEEE Std 1149.1-1990
To learn more about IEEE Std 1149.1, please refer to the
publications, IEEE Standard Test Access Port andBoundary-Scan Architecture, IEEE Std 1149.1-1990(includes IEEE Std 1149.1a-1993) and Supplement to IEEE
Std 1149.1-1990, IEEE Standard Test Access Port andBoundary-Scan Architecture, IEEE Std 1149.1b-1994. These
documents are available through IEEE (1-800-678-IEEE).
IEEE Std 1149.1-1990/IEEE Std 1149.1a-1993 is alsoavailable from Texas Instruments on CD-ROM (seeChapter 9, Other Support and Learning Products).

3-15

Chapter 4
Using DFT in ASICs
The concern most often voiced by application-specificintegrated circuit (ASIC) users is that of testability. This
chapter is intended to provide an understanding of ASIC
testability that can be used for developing test strategies
when designs are being initiated.

Design-for-Test Considerations
Designing testability into any circuit affects the hardware tosome degree. Additional logic will probably have to be
added. This additional logic increases the amount of siliconrequired to implement the design. The savings fromenhanced testability do not usually show up until the cycle
time and testing cost of the circuit and its end system areanalyzed.
Fault simulation is an important part of designing fortestability. This technique enables you to evaluate your test
patterns to determine whether these patterns detect faults.
Faults may occur during either the design-tooling stage or
the circuit-fabrication stage. A fault simulator uses fault
models, such as a node shorted to power (stuck-at-one) or anode shorted to ground (stuck-at-zero), and compares the
response of a fault-free circuit with the response of a faulty
circuit. If the response of the fault-free circuit is different than
the response of the faulty circuit, then the test patterns havedetected the fault.
By faulting all the nodes in the circuit, the fault simulator
produces the test-pattern fault grade or fault coverage. The
fault coverage is the percentage of faults detected among
the total faults. The higher the fault coverage, the better thetest pattern set separates a faulty circuit from a fault-freecircuit. After determining which faults have not been detectedby the current set of test patterns, additional test patterns
can be generated to detect those faults.
Adoption of design-for-test principles early in the design
process ensures the maximum testability for the minimum
effort. These guidelines emphasize that test is a part of thedesign flow, not a process that is done at the end of thedesign cycle.
4-1

Three basic elements must come together to make a
successful ASIC circuit:Logic design, including schematic capture, library
selection, synthesis, and simulation
Logic testability, including fault-detection andtest-application criteria within predefined cost andtime-scale budgets
Vendor’s manufacturing capability, including processing
and packaging

The Need for Testability
Most engineers involved in the design of ASIC devices arefamiliar with the trade-offs between gate arrays, standard
cells, and full custom devices. They are also familiar with thevendor selection process. The aspect of test capability andtestability is often overlooked.
Testability could be ignored when typical designs were only a
few thousand gates. These designs were implemented first
and then turned over to a test engineer or to a vendor tocreate a test program for production. As design complexities
increased, this approach to testing became futile. Successful
high-density ASIC design and manufacturing demand thatcircuits be built with testability incorporated into the design
process.
Although testability imposes additional constraints in thedesign phase, design verification and test can beunmanageable, if ignored until the design is completed andtestability is handled as a postdesign insertion. In fact, thedesign constraints are overwhelmingly balanced by improved
testability, which adds value to the device throughout
manufacturing and system life.

4-2

Using DFT in ASICs

Test-Time Cost
Test cost, as it relates to time, is a simple calculation. Most
commercial testers cost between $2 million and $3 million.
Under normal circumstances, the tester depreciation, plant,
operator, and support personnel costs are between 10 and
20 cents per test second.
Brute-force test approaches often generate a large numberof test patterns. Since test patterns are run at multiple
power-supply values and possibly at multiple temperatures,
inefficient pattern sets can severely impact the test costs of acomplex ASIC device.

Time to Market
Surveys indicate that 40 percent of the development cycle
time for an ASIC device is required for test insertion andtest-pattern generation. This figure is expected to increase
as device complexity increases. The intent of adesign-for-test strategy is to achieve high fault-detection test
programs in reduced time (Figure 4-1). The obvious
cycle-time reductions result from designed-in testability(elimination of iterative redesigns resulting from poor design
practices), and from automatic test-pattern generation(ATPG).
100
With DFT Strategies
Fault Grade %8060
Without DFT Strategies
40
20
0
Hours

Days

Weeks

MonthsTime to Develop Test Patterns

Figure 4-1. Fault Grade Versus Development Time4-3

Figure 4-2 shows the economic relationship between time tomarket and system manufacturing and field maintenancecosts. Point 1 represents the case where market-entry timing
forces a constraint on the development time. Since 40
percent of this time is expended in inserting testability, thetemptation is to rush to market with devices that are notcompletely testable or tested. The result is ahigher-than-desirable manufacturing and field-maintenancecost. Point 2 represents the case where DFT and ATPG
techniques are employed to develop devices that arecompletely tested. This situation allows an economic
optimum that is more favorable to long-term manufacturingand maintenance costs.

Cost $

g
Economic
Optimum
1

Without DFT Strategy

Economic
Optimum2

g With DFT Strategy
Manufacturingand Field CostFault Coverage %Development andTime-to-Market Cost

Total Cost

Figure 4-2. Economic Trade-Off for a Testable Design
A less obvious result of a DFT strategy is the reduction of
debug time. The designer must make certain assumptions
about system requirements. Often, a new device does notwork in the system environment and requires debugging. If
the device is designed for controllability and observability
access, the debugging process is enhanced. Conversely, if
these two features are overlooked, debugging andmanufacturing can be significantly harder to accomplish, if
not impossible. Oscilloscopes and logic analyzers are notvery effective in debugging systems utilizing complex ASIC
devices in a surface-mount environment.

4-4

Using DFT in ASICs

Fault Coverage and Cost of Ownership
Figure 4-3 shows the trade-off between time to market andmanufacturing and field-maintenance costs. The horizontal
factor on this figure is fault coverage. The relationshipbetween fault coverage and device defect level is well
documented.
Figure 4-3 is a plot of the relationship modeled by T. W.
Williams for fault coverages of 90 percent, or greater.
The Williams model is:D+ [1 * Y (1 * T) ] x100

Where:
D = Defect level in percent
Y = Theoretical functional process yield
T = Fault coverage of the test program used
7
50%

Defect Level %

6
5

60%

4
70%
3
80%

2

90%

1
0

90

91

92

93

94

95

96

97

98

99 10050% Process Yield —6.70 6.04 5.39 4.74 4.07 3.41 2.73 2.08 1.38 0.89 .00

60% Process Yield —4.98 4.48 4.00 3.51 3.02 2.52 2.02 1.52 1.01 0.51 .00

70% Process Yield —3.50 3.16 2.81 2.47 2.12 1.77 1.42 1.06 0.71 0.36 .00

80% Process Yield —2.21 1.99 1.77 1.55 1.33 1.11 0.89 0.67 0.45 0.22 .00

90% Process Yield —1.05 0.94 0.84 0.73 0.63 0.53 0.42 0.32 0.21 0.11 .00

Fault Coverage %Figure 4-3. Defect Level Versus Fault Coverage
To briefly explore the Williams model, assume that the
ASIC vendor has a silicon and assembly process yield that is4-5

70 percent. If the fault grade of the test program is also 70
percent, the defect level is projected to be 10.1 percent, or
101,000 ppm (this is outside the limits of the chart and was
calculated). At a fault grade of 90 percent, the defect level isprojected to be 3.5 percent or 35,000 ppm.
A study of the model shows that the process yield becomesan insignificant term when the fault coverage of the test
program is very close to 100 percent.
Motorola and Delco performed a study in 1980 that supports
the Williams model. Their experimental results are shown in
Figure 4-4. A fault coverage of 99.9 percent was required toobtain defect levels in the range of 100 ppm.

Defect Level ppm

100 000

10 0001000

100Harrison, Holzwarth, Motz, Delco;
Daniels, Thomas, Weimann, Motorola, 9/80
10

90

99

99.9

Fault Coverage %Figure 4-4. Motorola and Delco Study Results
Figure 4-5 shows the maximum allowable ASIC defect rateto achieve a goal PCB defect rate as a function of thenumber of ASIC devices per board assembly. Note that for
multiple-device PCB designs, a goal of 500 ppm requires
ASIC defect levels in the range of 100 to 200 ppm.

4-6

Using DFT in ASICs

600

Number of ASICs Per Board

500

1

ASIC ppm Rate

400
300

2

200

3
4
5
10
20

100
0

0

100

200

300

400

500

600

Goal PCB ppm Rate

Figure 4-5. ASIC ppm Versus PCB ppm Rate
Theoretical and experimental studies conclude that ahigh-fault-grade test-pattern set is required for
low-defect-level ASIC devices. This type of pattern set isnearly impossible to obtain through brute force. The
requirements for a high-fault-grade pattern set are:
ATPG tool
Fault grader
A testable design meeting the constraints of the ATPG tool
As stated earlier, a design-for-test strategy has performanceand area costs. Now, the cost of new tools has been added.
Benefits such as lower test costs and reduced time to market
have been mentioned. These benefits are real, but often hardto quantify. Reduced cost of ownership is another major
benefit and is easy to quantify.
Figure 4-6 shows what is commonly referred to as the“cost-of-ownership, order-of-magnitude relationship”. It
shows that each company has a cost associated with finding
a defect in a packaged device before it has entered theassembly process. This cost can be calculated easily. The
cost of finding a defective device after assembly onto a PCB
is an order-of-magnitude more than before assembly. This
continues until the cost to discover a defective device in asystem at a customer’s site is three orders-of-magnitude
higher than that of discovery before assembly on to a PCB.

4-7

The lowest cost of ownership is achieved by finding defective
units before they are shipped from the vendor.

Discovery Site

Customer Site
SystemPCB
Package
Device

0

1X

10X

100X

1000X

Cost-of-Defect-Discovery Multiplier

Figure 4-6. Cost of Ownership
The previous discussions lead to the conclusion that thelowest cost of ownership can be obtained by providing the
ASIC vendor with an efficient, high-fault-detection set of test
vectors. These DFT methodologies provide lower cost ofownership with the added benefit of reduced time to market.

Developing Testability Strategies
The following strategies outline the process of design fortest.
1. Select a technology.
When selecting a technology or vendor, make sure there
is enough performance and gate-count margin to allow theinsertion of testability.
2. Commit to testability design practices.
Testability design practices work. Commit to use them,and review them with the design team before the design
begins. Add a testability commitment to the design
requirements document developed for the design project.
Make testability audits part of the design review process.
3. Establish a fault-grade requirement.
The fault-grade requirement usually can be provided by
the manufacturing or quality organization. Establish thisrequirement before the first design review. Add thefault-grade requirement to the design requirements
4-8

Using DFT in ASICs

document. This requirement drives many of the decisions
that follow in the development of the test strategy.
Many companies consider the fault-grade requirement tobe an index of device cost of ownership. Failure toachieve it impacts profits throughout the lifetime of thedevice.
4. Decide if IEEE Std 1149.1 is a system requirement.
When implemented in an ASIC device, IEEE Std 1149.1
allows test of the interconnect between devices on a PCB
through a four-pin test bus. If IEEE Std 1149.1 is selected,
the four dedicated test pins also can be used to control
core-logic test techniques such as built-in self-test (BIST),
internal scan, on-chip emulation, and boundary-scanthrough the test access port (TAP) and instruction register.
5. Select an ASIC testability approach based on gatedensity.
Designs with fewer than 10K gates
Designs with fewer than 10K gates are not generally
complex enough to require structured test approaches.
The overhead impact is usually too high to justify them.
Nonstructured, good design practices are usually
sufficient.
Designs with more than 10K gates, but fewer than 20K
gates
Structured techniques should be considered for designs
in this density. Nonstructured, good design practices areprobably sufficient for highly combinatorial circuits
without memory. Structured approaches should beconsidered as complexity is increased by the addition ofsequential circuits, feedback, and memory. Consider
boundary-scan testing for reduced cycle times and highfault grades.
Designs with more than 20K gates
The complexity of circuits this dense usually requires
structured approaches to achieve high fault grades. At
this density, it is often hard to control or observe deeply
embedded circuits. The overhead associated withstructured testability approaches is acceptable at thisdensity.

4-9

6. Choose structured tools.
Scan testing is typically the preferred structured approachfor sequential logic. The available scan choices are:Clocked scan
Multiplexed flip-flop scan
Level-sensitive scan-design (LSSD)
Parallel scan chains
Partial scan
7. Establish a diagnostic functional-pattern set to expedite
debug.
This is an important step in decreasing the time to market
for an ASIC device. The purpose of this pattern set is toisolate circuitry for analysis.
8. Generate high fault-grade test patterns.
The fault grade of a test pattern set determines the best
possible quality level attainable with that set of patterns.
9. Simulate test patterns and timing.
Two types of simulation are required during development.
Logic simulation verifies both functionality andperformance of the device. Test-pattern simulation
produces the information needed to verify the test
patterns in a tester environment.
Figure 4-7 contains a flow chart that steps through thedesign-for-test process.

4-10

Using DFT in ASICs

Pick a technology/vendor
Commit to good testability
design practices
Establish a fault-grade
requirement
Yes
Implement
IEEE Standard 1149.1

No

Yes

IEEE Standard 1149.1
required for PCB?

Density = Gates < 10K ?
No

YesConsiderscan

Recommendscan

10K < Gates < 20K ?
No
Choose structured approach
Scan/BIST
Develop diagnostic patternsets and locate critical paths
Develop high fault-grade
pattern sets
Generate test description
language
Simulate test patterns andtimingHave a system to ensure
test patterns are compatible
with logic revisions

Minimum Time to Market

Figure 4-7. Testability Development Flow

4-11

Chapter 5
Data Formats
Several data formats have emerged to make IEEE Std
1149.1 successful and well supported by tools. This chapter
discusses the most widely accepted data formats that
support IEEE Std 1149.1 — BSDL, HSDL, and SVF.

Boundary-Scan Description Language (BSDL)In 1990, IEEE Std 1149.1 was approved and implementationof the standard accelerated. As more people became awareof and used the standard, the need for a standard method fordescribing IEEE Std 1149.1-compatible devices wasrecognized. The IEEE Std 1149.1 working group establisheda subcommittee to develop a device description language toaddress this need.
The subcommittee has since developed an industry standard
language called Boundary-Scan Description Language(BSDL). BSDL is a subset and standard practice of VHDL(VHSIC Hardware Description Language) that describes how
IEEE Std 1149.1 is implemented in a device and how it
operates. BSDL captures the essential features of any IEEE
Std 1149.1 implementation. BSDL has been formally adopted
as part of IEEE Std 1149.1b-1994.
IEEE Std 1149.1 is a structured design-for-test approach well
suited for tools and automation. Tools developed to support
the standard can control the test access port (TAP). If theyknow how the boundary-scan architecture was implemented
in the device, such tools can also control the I/O of thedevice. BSDL provides a standard machine- andhuman-readable data format for describing how IEEE Std
1149.1 boundary-scan architecture is implemented in a
device.
How BSDL Is Used
Many IEEE Std 1149.1 tools already on the market support
BSDL as a data input format. These tools offer different
capabilities to customers implementing IEEE Std 1149.1 into
their designs, including board interconnect automatic
test-pattern generation (ATPG) and automatic test equipment(ATE).
5-1

When tools that support BSDL are used, such BSDL is often
received from the semiconductor vendor. This can result insignificant time and cost savings.
Teradyne estimates that to create in-circuit test patterns for aleading microprocessor normally can take as long as sevenweeks:
One week to study the device
Four weeks to develop in-circuit test patterns
Two weeks to verify the patterns on ATE
The development cost estimate for this approach is $14,000.
If the microprocessor supports IEEE Std 1149.1, and the
BSDL is supplied by the vendor, the time to develop in-circuit
test patterns is less than two hours (less than $100) using
today’s tools.
Elements of BSDLA BSDL description for a device consists of the following
elements:
Entity descriptions
Generic parameter
Logical port description
Use statement(s)Component conformance statement
Pin mapping(s)Scan port identification
Instruction register description
Optional register decription
Register access description
Boundary register description
Entity Descriptions — The entity statement names the entity,
such as the device name (e.g., SN74BCT8245A). An
entity description begins with an entity statement andterminates with an end statement.
entity XYZ is{statements to describe the entity go here}
end XYZ;

5-2

Data Formats

Generic Parameter — A generic parameter is a parameterthat can come from outside the entity, or it can bedefaulted, such as a package type (e.g., “DW”).
generic (PHYSICAL_PIN_MAP : string := “DW”);

Logical Port Description — The port description gives logicalnames to the I/O pins (system and TAP pins), anddenotes their nature, such as input, output, bidirectional,
linkage (analog or power supply/return) and so on.
port (OE:in bit;
Y:out bit_vector(1 to 3);
A:in bit_vector(1 to 3);
GND, VCC, NC:linkage bit;
TDO:out bit;
TMS, TDI, TCK:in bit);Use Statement(s) — The use statement refers to external
definitions found in packages and package bodies.
use STD_1149_1_1994.all;Component Conformance Statement — The component
conformance statement indicates the latest issue ofIEEE Std 1149.1 to which the device conforms.
attribute COMPONENT_CONFORMANCE of XYZ : entity is“STD_1149_1_1993”;

Pin Mapping(s) — The pin mapping provides a mapping oflogical signals onto the physical pins of a particulardevice package.
attribute PIN_MAP of XYZ : entity is
PHYSICAL_PIN_MAP;
constant DW:PIN_MAP_STRING:=“OE:1, Y:(2,3,4), A:(5,6,7), GND:8, VCC:9, ” &”TDO:10, TDI:11, TMS:12, TCK:13, NC:14”;

Scan Port Identification — The scan port identification
statements define the device’s TAP.
attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6,
BOTH);

Instruction Register Description — The instruction register
description identifies the device-dependent
characteristics of the instruction register.
attribute INSTRUCTION_LENGTH of XYZ : entity is 2;
attribute INSTRUCTION_OPCODE of XYZ : entity is“BYPASS (11),”&“EXTEST (00),”&“SAMPLE (10),”&“IDCODE (01)”attribute INSTRUCTION_CAPTURE of XYZ : entity is
“01”;

5-3

Optonal Register Description — The optional register
description identifies the values captured in the device
identification register for the optional IDCODE and
USERCODE instructions, if supported.
attribute IDCODE_REGISTER of XYZ : entity is“01010100000011111100000000101111”;

Register Access Description — The register accessdescription defines which register is placed between
TDI and TDO for each instruction.
attribute REGISTER_ACCESS of XYZ : entity is“BOUNDARY (EXTEST, SAMPLE),”&“BYPASS (BYPASS)”;

Boundary Register Description — The boundary register
description contains a list of boundary-scan cells, alongwith information regarding the cell type and associatedcontrol.
attribute BOUNDARY_LENGTH of XYZ : entity is 7;
attribute BOUNDARY_REGISTER of XYZ : entity is“0 (BC_1, Y(1), output3, X, 6, 0, Z),”&“1 (BC_1, Y(2), output3, X, 6, 0, Z),”&“2 (BC_1, Y(3), output3, X, 6, 0, Z),”&“3 (BC_1, A(1), input , X),”&“4 (BC_1, A(2), input , X),”&“5 (BC_1, A(3), input , X),”&“6 (BC_1, OE , input , X),”&“6 (BC_1, * , control, 0)”;

Verifying BSDL Accuracy
Creating a BSDL file that is syntactically and semanticallycorrect is only the beginning. A syntactically and semanticallycorrect BSDL file can still contain descriptive errors andresult in time-consuming debugging of board-level tests anddiagnostics. A BSDL file must be validated (compared)
against the silicon.

5-4

Data Formats

Potential BSDL Errors
As with any hand-entered data, typographical errors
potentially exist. BSDL contains many commas andsemicolons that contribute error possibilities. Fortunately,
syntax and semantics errors can easily be identified andcorrected using syntax and semantics checking tools during
the authoring process.
Other common errors are:Wrong pinout
Wrong cell types
Wrong boundary-scan register orderWrong boundary-scan register length
Wrong instruction register opcodes
Wrong control cell locations
Wrong control cell disable value
Wrong I/O pin control cell
Wrong identification code value
Wrong capture-IR value
Typographical errors or device documentation errors canresult in implementation errors.
How to Receive the BSDL Specification
Contact the IEEE (1-800-678-IEEE) and refer to Supplement
to IEEE Std 1149.1-1990, IEEE Standard Test Access Port
and Boundary-Scan Architecture, IEEE Std 1149.1b-1994 toreceive a copy of the Boundary-Scan Description Language(BSDL) specification.
Obtaining BSDL for TI Devices
Texas Instruments makes catalog-device BSDL files
available to customers through the World-Wide Web. As ofthis writing, these files can be located on the Texas
Instruments IEEE Std 1149.1/JTAG/Boundary-Scan Silicon
Products page located at URL http://www.ti.com/sc/docs/
jtag/silicon.htm; or, on the main Texas Instruments home
page at URL http://www.ti.com. Search for keyword BSDL.

5-5

Hierarchical Scan Description Language (HSDL)
Texas Instruments developed the hierarchical scan
description language (HSDL) to complement BSDL, using
the same subset of VHDL statements as BSDL. HSDL picks
up where BSDL stops to describe additional attributes ofIEEE Std 1149.1 devices and how IEEE Std 1149.1 devices
are connected at the board and system levels.
HSDL uses the BSDL entity and package in new ways.
Entities in HSDL are used to describe modules as well as
devices. A module is any level of architecture above thedevice level, including boards, multichip modules,
backplanes, subsystems, and systems. In addition, HSDL
provides two new packages used to indicate that an entity is
an HSDL device or module.
BSDL is ideal for describing how IEEE Std 1149.1 isimplemented in a device, but stops there. HSDL provides amethod for describing how IEEE Std 1149.1 devices areconnected at the board, module, and system levels. HSDL
serves two needs not addressed by BSDL:
Describes the test-bus interconnections of IEEE Std
1149.1 at the board or module level
Improves ease of use and reduces risk during interactive
design debug and verification
Allows descriptions of boards with dynamic andreconfigurable architectures
Elements of HSDL
HSDL module statements use much of the same syntax as
BSDL. New statements have been added to describe themembers and scan paths of the module and to simplify
interactive use.
Entity description
Generic parameter
Logical port description
Use statement(s)[Optional module description(s)][Optional port description(s)]Pin mapping(s)5-6Data Formats

Scan port identification[Optional members description(s)][Optional bus composition(s)]Path description[Optional member connections][Optional constraint description(s)][Optional design warning]
Entity Description — The entity statement names the entity,
such as the module name (e.g., BOARD). An entity
description begins with an entity statement andterminates with an end statement.
entity BOARD is{statements to describe the entity go here}
end BOARD;

Generic Parameter — A generic parameter may come fromoutside the entity or it may be defaulted, such as a
package type (e.g., “UNDEFINED”).
generic (PHYSICAL_PIN_MAP : string := “UNDEFINED”);

Logical Port Description — The port description gives logicalnames to the I/O pins (system and TAP pins), anddenotes their nature such as input, output, bidirectional,
linkage (analog or power supply/return) and so on.
port (TDI:in bit;
TDO:out bit;
TMS:in bit;
TCK:in bit;
GND:linkage bit);Use Statement(s) — The use statement refers to external
definitions found in packages and package bodies.
use STD_1149_1_1994.all;use HSDL_module.all;

Pin Mapping(s) — The pin mapping provides a mapping oflogical signals onto the physical pins of a particular
entity.
attribute PIN_MAP of BOARD : entity is
PHYSICAL_PIN_MAP;
constant PINOUT1 : PIN_MAP_STRING :=“TDI:1, TDO:2, TMS:3, TCK:4, GND:5”;

5-7

Scan Port Identification — The scan port identification
statements define the entity’s TAP.
attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_CLOCK of TCK : signal is (5.0e6,
LOW);

Members Description (Optional) — Members represent
devices or other modules that are on the module.
Usually members represent components, but someboards may contain scannable daughtercards, card
slots, etc. that require member modules to describe
them.
attribute MEMBERS of BOARD : entity is“U1 (XYZ1, DW),”&“U2 (XYZ2, DW)”;

Bus Composition (Optional) — Buses in an HSDL module
can be built of module buses, member module buses,
member device buses, and member device test
registers.
attribute BUS_COMPOSITION of BOARD : entity is“bus1[4] (U1.Boundary[3,0]),”&“bus2[4] (U2.Boundary[3,0])”;Path Description — Module paths are intended to describe
the netlist of TAP signals (scan paths) on the board.
constant boardpath1 : STATIC_PATH :=“U1, U2”;
end BOARD;

How to Receive the HSDL Specification
Originally developed by Texas Instruments primarily insupport of its ASSET business, HSDL is now supported by
ASSET InterTech, which acquired ASSET in 1995.

5-8

Data Formats

Serial Vector Format (SVF)
Serial Vector Format, commonly referred to as SVF, wasjointly developed by Texas Instruments and Teradyne in
1991. SVF is a standard ASCII format for expressing test
patterns that represent the stimulus, expected response, andmask data for IEEE Std 1149.1-based tests. The need for
SVF arose from the desire to have vendor-independent IEEE
Std 1149.1 test patterns that are transportable across a wide
selection of simulation software and test equipment — fromdesign verification through field diagnostics.
Boundary-scan test execution is controlled by thesequencing of TAP signals on the pins of the devices. Eachdevice’s behavior is determined solely by the states of its
TAP pins. Boundary-scan tools must maintain knowledge ofthe sequences required to exert certain behaviors within adevice and where that device is located in the serial scanpath.
SVF controls the IEEE Std 1149.1 test bus using commands
that transition the TAP from one steady state to another.
Rather than describe the explicit state of the IEEE Std
1149.1 bus on every TCK cycle, SVF describes it in terms oftransactions conducted between stable states. For instance,
the process of scanning in an instruction is described merely
in terms of the data involved and the desired stable state toenter after the scan has been completed. The Capture,
Update, Pause, etc. states are inferred rather than explicitly
represented. The data to be scanned in, expected data out,
and compare mask are all grouped in an easily
understandable manner. A command is provided to support
deterministic navigation of TAP states where required.
In addition to supporting higher level depictions of scan
operations, SVF also supports combined serial and parallel
operations. This allows SVF to accommodate ATE
environments where some stimulus/response is handled via
parallel I/O, and serial signals are accessed via an IEEE Std
1149.1-control environment.
SVF also supports the concept of scan offsets. Offsets allow
a test to be applied to a component or cluster of logic
embedded in the middle of a scan path. In Figure 5-1, adevice exists in multiple instances on a board. Seriallyapplied tests were generated by the designer that areavailable in SVF format. To reuse this test, it is necessary to
5-9

put all other devices on the scan path into the BYPASS
mode. The IEEE Std 1149.1 test controller must therefore
comprehend 24 instruction register bits (8-bit IR x 3 devices)
before and 16 instruction register bits (8-bit IR x 2 devices)
after the target device. Once in BYPASS, the devices
introduce three data register bits before and two data register
bits after the target device.
SVF allows a header and trailer to be defined once, which
maintains the instruction register and data registers of thenontargeted devices in the desired BYPASS state. No
modifications are required to the SVF for the device. In
Figure 5-1, if the same test were targeted toward anotherdevice downstream, this would be accommodated merely bychanging the headers and trailers.
Trailer
TDI

U1

U2

Header
U3

U4

U5

U6

TDO

TargetFigure 5-1. Scan Path of Six ICs
The offset approach is capable of installing any instruction
register and data register stimulus, provided these values areconstant for the entire process of applying the SVF device
sequence.
SVF Structure
The SVF file is defined as an ASCII file that consists of a setof SVF statements. Statements are terminated by asemicolon (;) and may continue for more than one line. The
maximum number of ASCII characters per line is 256. SVF is
not case sensitive, and comments can be inserted into an
SVF file after an exclamation point (!) or a pair of slashes (//).
Each statement consists of a command and parameters
associated with that specific command. Commands can begrouped into three types: state commands, offset
commands, and parallel commands.

5-10

Data Formats

State Commands
State commands are used to specify how the test sequences
will traverse the IEEE Std 1149.1 TAP state machine. The
following state commands are supported:
SDR
SIR
ENDDR
ENDIR
RUNTEST
STATE
TRST

Scan data register
Scan instruction register
Define end state of DR scan
Define end state of IR scanEnter Run-Test/Idle state
Go to specified stable state
Drive the TRST line to the designated level

SDR performs an IEEE Std 1149.1 data register scan. SIR
performs an IEEE Std 1149.1 instruction register scan.
ENDDR and ENDIR establish a default state for the bus
following any data register scan or instruction register scan,
respectively. RUNTEST goes to Run-Test/Idle state for a
specific number of TCKs. For each of the above commands,
a default path through the state machine is used. Each ofthese commands also terminates in a stable, nonscannable
state.
STATE places the bus in a designated IEEE Std 1149.1
stable state. TRST activates or deactivates the optional
test-reset signal of the IEEE Std 1149.1 bus.
Offset Commands
Offset commands allow a series of SVF commands to betargeted toward a contiguous series of points in the scanpath. Examples would be a sequence for executing self-test
on a device, or a cluster test where all devices involved in
the cluster test are grouped together. The following offset
commands are supported:
HDR
HIR
TDR
TIR

Header data for data bits
Header data for instruction bits
Trailer data for data bits
Trailer data for instruction bits

5-11

HDR specifies a particular pattern of data bits to be padded
onto the front of every data scan. HIR specifies the same forthe front of every instruction register scan. TDR and TIR
specify data to be injected on the back of each scan. These
patterns need only be specified once and are included oneach scan unless changed by a subsequent HDR, HIR,
TDR, or TIR command.
Parallel Commands
Parallel commands are used to map and apply the following
commands:
PIO — Specifies a parallel test pattern
PIOMAP — Designates the mapping of bits in the PIO
command to logical pin names
Parallel commands allow SVF to combine serial and parallel
sequences. PIOMAP commands are used by parallel I/O
controllers to map data bits in the command into parallel I/O
channels using the ASCII logical pin name as a reference.
The PIO command specifies the execution of a parallel
pattern application/sample. SVF does not specify any otherproperties of parallel I/O such as drive, levels, or skew.
Default State Transitions
SVF uses names for the TAP states that are similar to theIEEE Std 1149.1 TAP state names. Table 5-1 lists the SVF
equivalent names for the TAP states.

5-12

Data Formats

Table 5-1. SVF TAP State Names
IEEE Std 1149.1 TAP
State NameSVF TAP
State Name

Test-Logic-ResetRESET

Run-Test/Idle

IDLE

Select-DR-Scan

DRSELECT

Capture-DR

DRCAPTURE

Shift-DRDRSHIFT

Pause-DRDRPAUSE

Exit1-DR

DREXIT1

Exit2-DR

DREXIT2

Update-DR

DRUPDATE

Select-IR-Scan

IRSELECT

Capture-IR

IRCAPTURE

Shift-IR

IRSHIFT

Pause-IR

IRPAUSE

Exit1-IR

IREXIT1

Exit2-IR

IREXIT2

Update-IR

IRUPDATE

5-13

Table 5-2 identifies sample default paths taken whentransitioning from one state to a specified new state. For
example, if the current state is RESET and DRPAUSE isselected as the end state, the TAP moves from RESET
through IDLE, DRSELECT, DRCAPTURE, DREXIT1 to
DRPAUSE. One must only specify the current and end states
and not each intermediate step. See the TAP controller state
diagram on page 3-5 of Chapter 3, Boundary-Scan
Architecture and IEEE Std 1149.1 to determine statetransition paths not shown in Table 5-2.
Table 5-2. Stable-State Path Examples
Current StateEnd StateState Path

RESET

RESET

RESET

RESET

IDLE

RESET

RESET

DRPAUSE

IDLE
RESET
IDLE
DRSELECTDRCAPTURE
DREXIT1
DRPAUSERESETIRPAUSERESETIDLEDRSELECTIRSELECTIRCAPTURE
IREXIT1
IRPAUSE

5-14

Data Formats

SVF Example
The following is an example SVF file:!
!

Begin Test Program
Disable Test Reset line
TRST OFF;! Initialize UUT
STATE RESET;! End IR scans in DRPAUSEENDIR DRPAUSE;! End DR scans in DRPAUSEENDDR DRPAUSE;! 24 bit IR header
HIR 24 TDI (FFFFFF);! 3 bit DR header
HDR 3 TDI (7);! 16 bit IR trailer
TIR 16 TDI (FFFF);! 2 bit DR trailer
TDR 2 TDI (3);! 8 bit IR scan, load BIST opcode
SIR 8 TDI (41) TDO (81) MASK (FF);! 16 bit DR scan, load BIST seed
SDR 16 TDI (ABCD);! RUNBIST for 95 TCK Clocks
RUNTEST 95 TCK ENDSTATE IRPAUSE;! 16 bit DR scan, check BIST status
SDR 16 TDI (0000) TDO(1234) MASK(FFFF);! Enter Test-Logic-Reset
STATE RESET;! End Test Program

The test begins by deasserting TRST. The DRPAUSE stateis established as the default end state for instruction registerscans and data register scans. Twenty-four bits of header
and 16 bits of trailer data are specified for instruction registerscans. No status bits are checked. Three bits of header data
and two bits of trailer data are specified for data registerscans.
In the example above, a single device in the middle of thescan is targeted. Notice from the 24-bit IR header (3 x 8-bitIR) and the 3-bit DR header (3 x 1-bit DR) that the targeted
device has three devices before it in the scan path. From the
16-bit IR trailer (2 x 8-bit IR) and the 2-bit DR trailer (2 x 2-bitDR), the targeted device has two devices following it in thescan path. After the header and trailer offsets are
established, all subsequent scans are the concatenation of
the header, scan data, and trailer bits. The targeted device
supports BIST, which is initialized by scanning hex 41 into
the instruction register, followed by hex ABCD into the
5-15

selected data register. The BIST in the targeted device isthen executed by entering the Run-Test/Idle state for
95 clock cycles. Next, the BIST result is scanned out and thestatus bits compared against a deterministic value todetermine pass/fail.
How to Receive the SVF Specification
Orignally developed by Texas Instruments (with Teradyne)
primarly in support of its ASSET business, SVF is now
supported by ASSET InterTech, which acquired ASSETin 1995.

5-16

Data Formats

Chapter 6
Suggested Design-for-Test Flow
The designer of any new product must plan for testing at any
time in the life cycle of the product. This process is called
design for test (DFT). The test methodology, defined by IEEE
Std 1149.1, is used to ease problems associated with bothproduct development and all levels of testing. Onceboundary-scan architecture is built into a device, tests
developed for that device can be reused after it is in a
product. Figure 6-1 summarizes the concerns applicable toany new product design.

SystemRequirements

Engineering
Requirements

Manufacturing
Requirements

Total
Requirements

Architecture

To
Figure6-2

Field Service
Requirements
Marketing
Requirements

Figure 6-1. Initial DFT Concerns

6-1

Test Requirements
Before implementing a boundary-scan test scheme, thedesigner must define test requirements for the following
phases of the product life cycle:
Design verification
Manufacturing test
Field test (also can be used for incoming inspection)
These studies must ensure that the necessary controls aredesigned into the hardware to support the following
requirements:
During design verification, an engineer requires
controllability of the circuitry, both internal to the IC and atboard and system levels. Design engineers need
controllability and observability of every logic node in thesystem. If this proves to be unrealistic, reasonable
coverage is achievable with partial scan in aboundary-scan design.
Manufacturing test may include interconnect testing andfunctional logic validation.
Field or embedded testing typically may only include theability to report faults and to isolate a fault to a
field-repairable unit (board or subsystem).
For both manufacturing test and field test, IEEE Std 1149.1
logic and test vectors can be used to test clusters or blocks
of logic.
Internal IC testing at the board or system level requires asubset of the complete IC logic-verification patterns tovalidate basic IC logic functions. Each level of hierarchicaltesting has a different set of fault characteristics. IEEE Std
1149.1 logic can be used throughout the testing life cycle ofthe product.

6-2

Suggested Design-for-Test Flow

Built-In Self-Test (BIST) Methodology
BIST usually consists of special circuitry built as part of anIC’s internal design. BIST tests typically perform thesefunctions:Pseudorandom pattern generation (PRPG)
Parallel signature analysis (PSA)
Serial signature analysis (SSA)
State machine-based generation/comparison
IEEE Std 1149.1 commands can initiate BIST tests andreturn the test results.

Internal Scan Test Methodology
Many high-density microprocessors and ASICs now include
internal IEEE Std 1149.1-compliant scan circuitry.
High-pin-count and fine-pitch packages limit physical accessto package pins and devices with high gate count limit
observation of the internal logic states. Internal scan, either
partial or full, can do the following:
Provide access to internal registers
Partition the design
Reduce the design to combinatorial networks surroundedby scannable registers
Provide fast, efficient testing of internal logic
Internal scan also allows on-chip emulation control andcircuit observability within a device to provide design
verification. The emulation capability also can aid in softwaredevelopment to control highly complex functions designed
into a device.

6-3

Design Effort
Figure 6-2 summarizes the various steps involved in ASIC
and board design.
Catalog
DeviceSelection

From
Figure6-1Architecture

Third-Party
Simulation
ModelsBoard Design

Prototype
Assembly

ASIC Design

D Entry
D Simulation
D Layout
D Fabrication
D Entry
D Simulation
D Synthesis
D Vector Generation
D 1149.1 Insertion
D Vector Generation
D Simulation
D Fabrication

Board
NetlistTo
Figure
6-3

HSDL
Files

BSDL
Files
Simulation
Vectors

Figure 6-2. Designing Testability for ASICs and Boards
IC Design Implementation
Synthesis of ASICs has become a popular approach to ASIC
design. ASIC designers faced with DFT for the first time areconcerned about lack of knowledge and the additional design
time involved. Today, there are several vendors supporting
synthesis and/or insertion tools that can automatically
6-4

Suggested Design-for-Test Flowgenerate the following elements of an IEEE Std 1149.1
architecture:
Test access port (TAP) controller
Instruction register
Instruction decode logic
Bypass register
Boundary-scan register
Such tools also can automatically generate test vectors forIEEE Std 1149.1-compliant designs. This means that adesigner can quickly and correctly implement basic IEEE Std
1149.1 test circuitry in an ASIC.
If synthesis is not available, most ASIC vendors offer alibrary of macros that the designer can use to implement
IEEE Std 1149.1 into their designs. Using vendor macros
requires considerably more effort and knowledge toimplement IEEE Std 1149.1 into an ASIC, compared to usingsynthesis. However, in the absence of synthesis orboundary-scan insertion tools, using vendor macros issignificantly easier than implementing boundary-scanarchitecture using a library that has no such macros. Texas
Instruments offers a family of IEEE Std 1149.1-compliant
ASIC macros for gate array and standard cell designs.
The ASIC designer is required to provide a Boundary-Scan
Description Language (BSDL) file that describes the finished
ASIC. This information becomes the basis for tools that
automatically create board interconnect test vectors. These
vectors can be used by the board designer for debug andvalidation and by manufacturing test departments for quality
assurance.
Several DFT tool vendors plan to implement automatic BSDL
creation that is available once the ASIC design has been
completed. The creation of a BSDL file by the ASIC designer
is straightforward if the design tool used does not
automatically create it.

6-5

IC Simulation
During IC simulation, the designer can use IEEE Std 1149.1
logic to simplify the simulation patterns required to validate
the design. First, patterns must be developed to verify that
the IEEE Std 1149.1 interface is operating properly. Simple
IR and DR scan patterns can be developed to perform thischeck. If internal scan is implemented, then simulation
pattern sets can be written to test internal logic clusters using
the internal scan registers. This partitioned approach
simplifies design validation.
Using SVF for IC Design Validation
Many IEEE Std 1149.1-compliant tools use Serial Vector
Format (SVF) as the primary test pattern data format andinterfaces between simulators and ATE testers also support
SVF.
A collection of manually-generated SVF patterns, simulation
patterns translated into SVF and ATPG-generated SVF
patterns can be used to validate the IEEE Std 1149.1 logic.
Initial tests must first verify that serial data can be scanned
into and out of the IC. Proper use of internal scan registers topartition the internal functional logic can simplify fault
detection and isolation.
IC testing usually is broken into three parts; static functional
tests at 1 MHz, at-speed functional tests, and parametrictests. Because IEEE Std 1149.1 architecture relies onserially scanning control and test data, only static functional
testing and DC parametric testing can be performed via theIEEE Std 1149.1 architecture. However, the IEEE Std 1149.1
TAP can be used to access user-defined test instructions(such as RUNBIST), which can be operated at speed.
INTEST patterns generated by a simulator can be used tovalidate the internal logic of the IC. By comparing thesepatterns with simulation results and by observing internalscan register contents, the designer can isolate faulty
internal logic. Figure 6-3 summarizes the design validation
flow for all products, from IC through system-level products.

6-6

Suggested Design-for-Test FlowPrototype
Assembly

Board
NetlistFrom
Figure
6-2

Debug
and
Validation

Integration
and Test

Manufacturing
and Test

Ship

Boundary-Scan
Test Tool

HSDL
Files

Field
Service

Simulation
Vectors

BSDL
Files

Interconnect
Patterns
(SVF)

Fault
Dictionary

Figure 6-3. Debug and Verification of a Boundary-Scan
DesignData Passed to Board Designer
The board designer needs test data to use during the design
debug and validation phase. This data includes:
BSDL for the ASICs as developed by the ASIC designer
BSDL for catalog devices from the device vendor
The BSDL that the designer creates for the ASIC must be
validated to ensure that it is correct since it will be used bytools that develop more tests for board debug and validation.
The new tests are then applicable for manufacturing test andfield service test vector generation. BSDL created by asynthesis tool should accurately reflect a device’s
construction.
Along with the BSDL file for the device, the ASIC designer
may also be asked to provide a subset of the ASIC
simulation patterns if the ASIC supports the optional INTEST
instruction. A subset of the simulation patterns may consist
6-7

of the static (1-MHz) functional patterns. Only a subset ofpatterns may be needed because it may be impractical toreapply the entire static functional test pattern set at theboard level. Many companies have found that they canachieve an acceptable level of confidence that the ASIC isfunctioning correctly using only a portion of the entire static
functional pattern set.

Board Design
Most of the concepts described for IC design also apply toboard and system integration. BSDL is used to describe theIEEE Std 1149.1 scan architecture of an IC, and Hierarchical
System Description Language (HSDL) is used to describe
subsystems and systems. HSDL is used to describe thescan architecture, group discrete signals into logical groups(e.g., ADDR0 –15, DATA 0–7) and to define constraints.

Constraints
A constraint defines a logic condition that can apply
potentially harmful signals to a circuit. IEEE Std 1149.1 gives
direct control of all scannable signals, so it is possible tocreate logic states that functionally would not be entered. For
example, bus-arbitration logic can be overridden anddangerous hardware conditions or conflict can occur. An
example of a constraint is to inhibit any test pattern thatwould cause two scannable output nodes to drive a common
bus net at the same time.

Partitioned Scan PathAt the board level, the designer must consider how topartition the IEEE Std 1149.1 scan path. Commercial devices
are available (such as TI’s SN74ACT8997† SPL) to switch asingle primary scan path to one or more multiple secondary
scan paths. The designer should consider the benefits andpenalties associated with partitioned scan paths.

† SN54ACT8997, SN74ACT8997 Scan Path Linkers With 4-Bit Identification
Buses, Literature Number SCAS157C, Texas Instruments 1996.

6-8

Suggested Design-for-Test Flow

Penalties associated with partitioned scan paths include:
Scan overhead required to switch from one partition toanotherTiming delays in routing TMS (affecting scan frequency)
Added complexity of the IEEE Std 1149.1 test program
Benefits associated with partitioned scan paths include:
Shorter scan paths
Additional fault tolerance
Somewhat simplified test software

Board Validation/Manufacturing Test
The IEEE Std 1149.1 architecture has the ability to detect,and in many cases, isolate a scan path fault. The instruction
register definition requires that the two (2) least-significant
bits (those closest to TDO) of a device be, respectively, a
logic 1, followed by a logic 0 during an IR scan. This rule
allows the IEEE Std 1149.1-compliant bus controller toperform a simple IR scan to prove all devices on the bus candrive a logic 1 and logic 0 on the TDI–TDO path. There are
ATPG tools available that automatically generate SVF bus
validation patterns that can be applied by the bus controller.
The primary objective of IEEE Std 1149.1 is to allow control
and observation of device input and output pins for the
purpose of interconnect testing. The reduced size of IC
packages has made interconnect testing of PWBs difficultand expensive when using conventional interconnect testing.
Commercial tools are available that automatically generate
SVF patterns for interconnect testing. Such tools input aboard netlist and the BSDL of the scannable components
and output an SVF pattern set. This pattern set, along with afault dictionary lookup table, allows an IEEE Std 1149.1 bus
controller to apply the interconnect patterns to the board anddetect/isolate faulty interconnections.

6-9

After proving correct operation of the IEEE Std 1149.1 bus
and board interconnect, the designer can control andobserve all boundary-scan nodes. Commercially available
boundary-scan test tools allow interactive, macro, or
high-level-language programming control for the designer.
The board designer also can import and reapply the SVF
patterns developed by the IC designer. This reuse of patternsets provides these benefits:
Knowledge is passed from one designer to another.
Overall product development cycle is reduced.
Using common SVF patterns reduces ambiguity between
hierarchical test levels.
The SVF pattern set developed by the IC designer tests an
individual IC. The board designer has to be able to relocate
the relative scan position of the IC SVF test to match its scan
position on the board dynamically. SVF headers and trailers
can be manipulated by the boundary-scan test tool to allow
such dynamic test relocation.

Summary
As designers become better acquainted with IEEE Std
1149.1, they will no doubt find benefits well beyond those
discussed in this chapter. The standard became available
just in time to offer solutions and benefits to customers
experiencing complex problems introduced by newtechnology.
The benefits that customers can realize from IEEE Std
1149.1 architecture include:
Reuse test data throughout the product life cycle
Apply off-the-shelf components, tools, and ATE solutions
from multiple vendors
Maintain common data base formats for these benefits:
Shared common databases between IC, board, andsystem designers (BSDL, HSDL)
Reusable pattern sets (SVF)
Reusable test pattern set (TPS) code

6-10

Suggested Design-for-Test Flow

Chapter 7
Applications
This chapter presents a number of testing problems andshows how boundary-scan testing and TI products can beused to solve them.

Board-Etch and Solder-Joint Testing
The current approach to detecting board-etch andsolder-joint faults in today’s electronics industry uses two
forms of automatic test equipment (ATE): bare-board testers
and digital in-circuit testers. Bare-board test is done after
board fabrication. Tests for open-etch circuits between nodes
force a voltage onto one circuit node and sense the voltage
at another circuit node. This technique is used only on a raw,
unassembled board.
An in-circuit test is done after board assembly and checks
for:
Correct orientation of parts
Correct value and type of parts
Correct solder joints between all parts and the board
Software models of each part on a board are used togenerate the test patterns used by the in-circuit tester. The
main assumption is that both board and in-circuit testers
require physical access to nodes or points on the board to
perform the necessary testing. Both testers require the ability
to inject a voltage or current onto a nodal network and sense
the voltage or current at another point on the network.
Higher-density packaging technologies, finer-pitch board
etch, and more complex digital integrated circuits have madebare-board and in-circuit testing much more expensive.
Solution
Several testability products from Texas Instruments lendthemselves to support IC-to-IC continuity testing. The
techniques outlined allow detection and, in most cases,
isolation of board-etch and solder-joint faults, without forcing
any additional requirements on the electrical design
engineer. ASIC devices and bus-interface components with
7-1

boundary-scan cells (BSCs) allow controlled insertion ofdigital logic values onto a nodal network and provide themeans to sample the digital logic values on the nodal
network. Broken-etch and solder-joint faults can be detected
and isolated in this manner.
Detailed Description
In the simple circuit shown in Figure 7-1, one driver (IC #1)
on a network drives digital logic values while the otherreceivers (ICs #2 and 3) sense changing values on the net. If
multiple driver lCs exist on a network, each driver is allowed
to drive, in turn, while all receivers sense to detect andisolate a fault to a specific driver or portion of the net.

Core
Logic

BSC
IC #1

BSC

Core
Logic

BSC

Core
Logic

IC #2

IC #3

Figure 7-1. Etch/Interconnect Testing
If an etch is broken on a network or an IC is not soldered tothe board properly, then nodes of some ICs are notconnected to nodes on others, as shown in Figure 7-2 andFigure 7-3 . When driver IC #1 drives, only IC #2 senses thecorrect logic value; IC #3 does not.

7-2

Applications

IC #1

IC #2

IC #3

Figure 7-2. Open-Etch Condition

IC #1

IC #2

IC #3

Figure 7-3. Open-Solder-Joint Condition
If an etch is shorted to ground or power due to a solder fault,then none of the ICs are able to drive or sense the correct
logic values. See Figure 7-4.

IC #1

IC #2

IC #3

Figure 7-4. Short-to-Ground Condition
The overall coverage of etch- and solder-fault detection andisolation depends on the percentage of a board’s circuitrythat has boundary-scan architecture. Only networks driven
by BSCs or IEEE Std 1149.1-compliant ICs can be tested inthis way; nonscan-controlled networks require conventional
approaches.

7-3

Because the driver and receiver BSCs are in silicon within
the ASIC, this technique can be used to test silicon bonding
to package pins in the integrated-circuit foundry. A simple
bond-out tester can drive a logic value to an input pin of an
IC and the sensing function can occur on the BSC buffering
the input to the core logic of the ASIC. The reverse
procedure can be used on an output pin of an IC; the BSC
driving the output of the core logic forces a logic value thatthe bond-out tester senses and records. See Figure 7-5.
Bond Wire

Package

Pin

Silicon

BSC

Core
Logic

BonderTesterStimulus

BSC

BonderTesterSensorFigure 7-5. Bond-Wire Testing
Summary
The current technique used to detect and isolate board-etchand solder-joint faults remains unaltered. With TI’s suite of
testability products, board testing can be performed without
external digital in-circuit testers. Boundary-scan architecture
eliminates the need for physical probe points on
printed-circuit boards that contain advanced-packaged,
surface-mount integrated circuits. The need to develop partmodels for in-circuit test generation also is eliminated.

7-4

Applications

Cluster Testing
Complex digital designs use large-scale integrated circuits
and ASICs to accomplish many functions on compact circuitboards. Not all logic functions are integrated, so discrete
devices are still used for some functions. Discrete logic
seldom includes boundary-scan test architecture due to theexpense and complexity; these parts must be tested anotherway.
Solution
Testing discrete logic functions on a board has to be done
from the boundary of the logic cluster. Combinatorial logic isnormally driven by and into sequential elements such as aregister or a clocked ASIC. By replacing the register with aIEEE Std 1149.1-compliant device, or by using Texas
Instruments IEEE Std 1149.1-compliant macro cells at theboundary of the ASIC, the cluster logic may be easily tested.
By using members of TI’s family of testability products, ahigher percentage of circuitry may be tested while reducing
the vector count necessary to perform a functional test.
Detailed Description
Figure 7-6 shows a simple circuit incorporating combinational
logic sandwiched between sequential logic.
IEEE
Std1149.1
DeviceLogic Cluster
AND, OR, NAND, NOR,
EXOR, Inverter Gates

TDI

A
B S
S I
C C

B
S
C
TDO

Figure 7-6. Cluster Testing

7-5

During normal circuit operation, the IEEE Std
1149.1-compliant device drives the glue logic through to the
BSCs in the ASIC. Two methods may be used to perform atest of the logic cluster using the TI family of testability
products. There are benefits and drawbacks to bothmethods.
1. Method one is to scan a fixed-order set of test patterns
called deterministic test vectors into the IEEE Std
1149.1-compliant device and sample the resultant data at
the ASIC boundary.
2. Method two is to command the IEEE Std 1149.1-compliant
device to output a pseudorandom pattern of data while the
ASIC performs a parallel signature analysis of its inputs.
Deterministic Test Vectors
Deterministic test vectors scanned into the UUT can pinpointa problem more easily than signature analysis. Since theexact input stimulus is known, the failing response can bedetected. Deterministic test vectors perform a complete andmeaningful test, but consume a lot of time and enoughmemory to store all vector data for both stimulus andresponse.
Signature Analysis
Signature analysis can be performed quickly and virtuallyautomatically. After valid pattern generation and signature
analysis seed values are obtained, the resultant signature
can be checked against the correct value. This test can be
performed at the scan clock speed and requires very little
memory for data storage. However, the fault cannot belocated without using an extensive fault dictionary.
Signature analysis requires that the IEEE Std
1149.1-compliant device be able to generate stimulus
patterns and the ASIC be able to capture a signature of its
inputs. This means that appropriate macro cells must be
used as outputs of the driving device and as inputs to theboundary of the ASIC. These cells require additional space
and additional circuitry to be incorporated into each BSC.
Summary
Using the IEEE Std 1149.1-compliant family of testability
products from Texas Instruments enables designers to add
7-6

Applications

features previously unachievable in their designs. It isbeneficial to test glue-logic clusters using existingboundary-scan components that surround the logic cluster.
This provides added value to the boundary-scan overhead
built into a design’s larger devices.

Board-Edge Connector Testing
Board-to-board fault detection and isolation within a digitalsystem have historically depended primarily on built-in test(BIT) software. This approach is adequate for detecting
functional faults on boards, assuming that the processor
executing BIT software can access the boards installed in
the system. Backplane faults typically manifest themselves inthese ways:
Broken or bent pins on connectors
Broken etch on a backplane motherboard
Termination-network fault
Bus contention on a bused network
Many bus faults in today’s digital processor environments areso catastrophic in nature that the processor executing BIT
cannot access the boards installed within the system toisolate the fault.
Solution
In much the same way that boundary scan allows detection
and isolation of etch and solder-joint faults on a PWB,
surrounding the bus interface of a board with IEEE Std
1149.1-compliant devices allows detection and isolation ofbus and connector faults. By placing IEEE Std
1149.1-compliant devices in a controlled test mode, eachboard, in turn, can drive the backplane bus while the otherboards receive the driven logic values.
Detailed Description
Broken etch on a motherboard backplane presents problems
similar to that of broken etch on a PWB connecting
integrated circuits; some boards cannot communicate toothers past the etch break (see Figure 7-7). By placing thetestability devices on each board into a controlled test mode,
7-7

one board at a time can drive logic data onto the bus while
the others are receiving logic data. This method provides
enough conclusive data to detect and isolate the continuity
break.
BSC

BSC

BSC

BSC

BSC

BSC

BackplaneOpen Etch
Condition

Figure 7-7. Backplane Open-Circuit Fault
A broken connector pin fault can be detected and isolated in
the same manner as etch breaks; the board with a bad pin is
not able to drive and receive data onto a particular channelon the backplane. See Figure 7-8.
BSC

BSC

BSC

BSC

BSC

BSC

Backplane

FaultyConnector
Pin Condition

Figure 7-8. PWB Connector Fault
Termination network open or short to VCC /ground shows up
as a channel on the backplane that cannot be driven to a
7-8

Applications

certain logic state. The characteristic of this fault could be
confused with a bus contention fault. See Figure 7-9.
BSC

BSC

BSC

BSC

BSC

BSC

Backplane

Short-to-Ground
Condition

Figure 7-9. Backplane Short-to-Ground Fault
Bus contention faults occur when a three-state bus driver isstuck in a functional-enable mode. The BSCs in a controlledmode can be disabled by the test circuitry, thus bypassing
the functional-enable control. All of the tests described canbe executed offline in a test mode or by built-in test (BIT)software interfacing to an IEEE Std 1149.1-compliant serial
scan controller in the system.
Summary
Board-to-board fault detection and isolation in a controlled
offline test mode and concurrent background BIT execution
can be dramatically improved by using boundary-scan
testability devices within the bus interface circuitry of eachboard installed in a system. Boundary-scan architecture at
the backplane-interface can increase fault isolation bymasking some interface logic from the circuitry under test.

7-9

ASIC Verification
Very-high-density ASIC devices pose severe barriers to all
testing, beginning with design verification and continuing withtest and verification of the manufactured part.
Solution
IEEE Std 1149.1-based testing can be used for testing andverifying ASIC devices if the design process, beginning withdesign specifications, includes scan-based testing. This
example cites the development of a vector processor ASIC
with 165,000 gates.
Detailed Description
The test logic in the vector processor includes internal scanand built-in emulation logic, in addition to boundary scan andthe optional INTEST capability. The emulation capability
includes control of the processor, implementing RUN, STOP,SINGLE-STEP, and EXAMINE/MODIFY internal registers,
and real-time breakpoints.
Test Development
Design verification, test hardware, and test software aredeveloped concurrently with the ASIC. Verification code
consists of two types of tests:
Scan-based tests and diagnostics
Embedded test code
A boundary-scan test tool is used to execute and monitor
boundary-scan tests. The tests are used to verify test bus
operation, scan path integrity, internal-register access,core-logic operation, and IC-to-IC interconnects. An
expanding set of scan-based utilities and special-purpose
test programs are written to perform specific tests ortroubleshoot hardware problems. These utilities aredeveloped from the time hardware integration is begun.
In addition to the scan-based tests, embedded test code isdeveloped in microcode to verify instruction set execution,
register and memory decode, memory access, andinput/output operations. The embedded tests targetfunctional logic and verify at-speed operations.

7-10

Applications

Design Verification
The vector processor ASIC in the design incorporates
extensive internal scan paths and breakpoint logic controlled
via the IEEE Std 1149.1 test bus. Key registers that areaccessible via scan include the address and data register
files, ALU and multiplier pipeline registers, and the program
instruction register.
Initial checkout of the vector processor includes scan path
integrity and internal register access using internal scan andboundary scan. The first devices contain nonfunctional
microcode RAM, therefore an alternate plan is devised touse IEEE Std 1149.1 to validate all other circuitry.
The vector processor checkout uses the boundary-scanarchitecture to perform register reads and writes and simple
operations to verify microcode execution. Simple microcode
operations are tested by scanning an opcode into the
instruction register and clocking the processor using
boundary scan.
A test routine is developed in C++ that automates the
microcode execution steps. The program reads
microcode-object files, scans the instruction into the
instruction register, clocks the processor, and reads the
program counter to locate the next instruction. As each
instruction is executed, the program dumps the accumulator
and status registers to allow monitoring of each instruction.
This process is repeated for each microcode routine until all
microcode is executed and nearly all processor functions areverified using the “bad” vector processors. Many weeks are
saved while waiting for new vector processors.
Summary
Design verification, hardware test, and software integration
represent significant challenges. Anticipating this, many
design-for-test and integration capabilities need to beincorporated into the device to ensure controllability andobservability of embedded functions. IEEE Std 1149.1
provides the primary method for design verification,
hardware/software integration, and hardware test.
Test and interaction issues in this case were aggravated by
the lack of physical access caused by the small geometry of
the module. Boundary-scan testing saved a significant
7-11

portion of the design verification effort that would have beenrequired for the less-effective conventional physical accessmethods.

Memory-Testing Techniques
The steady increase in memory density has led to theincreased use of high-capacity memory boards in today’s
electronic systems. It has also encouraged the use ofembedded memory within microprocessors, digital signal
processors (DSP), and ASICs. As a result, testing of theseboards and devices has become more complex.
Large-capacity memory boards require very long test
execution times for adequate fault detection. Large bus sizes(32 bits) and high bus fanout further complicate the problem
of isolating component faults. Embedded memories, which
often make up a significant portion of the device area, create
additional difficulties due to a lack of test access.
Solution
The use of scan-path technologies can simplify the problemof testing large memory arrays within a system or embedded
memories within a device. Scan-path devices such as TI’s
bus-interface components can be used to partition large
memory device arrays into smaller, more easily testable
arrays to increase component fault isolation. In addition, theuse of TI’s IEEE Std 1149.1-compliant macro cells within
ASIC devices provides controllability and observability ofembedded memory that is normally inaccessible. Memory
test times can be reduced through the efficient partitioning
and testing of several memory arrays (on a board or within adevice) in parallel.
Detailed Description
Figure 7-10 shows a 256 × 8 memory array, associated bus
interface, and control logic configured to test various
memory-pattern-generation techniques. This configuration
allows for explicit read/write operations using IEEE Std
1149.1 EXTEST and SAMPLE instructions. In addition, thecomponents have a BIST capability (controlled by IEEE Std
1149.1 instructions) used to perform memory read/write
operations. The test results shown in Table 7-1 compare
explicit scanning in the RAM array address, data, and strobe
7-12

Applications

signal to using an IEEE Std 1149.1-instruction-controlled
BIST to generate address, data, and strobe signals
automatically at the test clock (TCK) rate of 6.25 MHz.
’BCT8245

To
Embedded
Processor

1B1
1B2
1B3
1B4
2B1
2B2
2B3
2B4
DIR
G\

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

D0
D1
D2
D3
D4
D5
D6
D7

Memory
D0
D1
D2
D3
D4
D5
D6
D7

A0
A1
A2
A3
A4
A5
A6
A7

’BCT8244
A0
A1
A2
A3
A4
A5
A6
A7

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

CS\

TDO TDITMS TCK

WE\

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
G1\
G2\

To
Embedded
Processor

TDO TDITMS TCK

Vcc’BCT8244

MemoryControl

TDO

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
G2\
G1\

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

TDO TDITMS TCK

TMS
TCK
TDI

Figure 7-10. Block Diagram of Simplified
Boundary-Scannable RAM Interface

7-13

Table 7-1. Access Rates of IEEE Std 1149.1 Devices
With and Without BIST
Mode

256
Accesses

1,000,000
Accesses

0.00041 seconds<0.01 minutes

IEEE Std 1149.1(With BIST Capabilities)
Time to Apply
Number of Scans

7

28,000

Number of Patterns

512

2,000,000

IEEE Std 1149.1(Using EXTEST and SAMPLE)
5.625 seconds

375.00 minutes

Number of Scans

Time to Apply

512

2,000,000

Number of Patterns

512

2,000,000

Table 7-1 shows that the BIST controlled by IEEE Std 1149.1
instructions overcomes the limitations of conventional
memory testing. Using boundary-scan EXTEST and
SAMPLE/PRELOAD solves the direct physical accessproblem, but it is time consuming. By using BIST circuitry
embedded within the functional logic surrounding large
memory arrays, IEEE Std 1149.1 tests can be designed toemulate closely the characteristics and timing speeds of thememory being accessed. TI’s bus-interface components offer
the IEEE Std 1149.1-controlled BIST functionality required totest memory, while providing the electrical signal conditioning
and buffering a design engineer typically designs around a
microprocessor.
In a similar fashion, TI’s family of IEEE Std
1149.1-compatible cells can be used within an ASIC device
to provide access to embedded memory normallyinaccessible through external pins. The IEEE Std
1149.1-compatible cells support the same self-test features
as the bus-interface devices (PRPG, PSA, Toggle 1/0
modes), which further simplify memory testing. Additionalfeatures such as programmable PRPG and PSA taps, built-in
comparison logic, maskable PSA/comparison inputs, andbidirectional cells provide even more flexibility in self-test
design. These features can be used with a built-in test
controller to create an autonomous BIST for the memory
array and/or other functions within the device.

7-14

Applications

The use of IEEE Std 1149.1 cells in performing read/write
tests on RAM is shown in Figure 7-11. Address sequencing
is performed using the PRPG mode. The PRPG and toggle
modes automatically generate data patterns to be written to
the memory cells under test while the memory write enable iscontrolled by direct scan. When reading from memory, data
patterns are verified using the comparison logic in the IEEE
Std 1149.1-compatible cells. This is possible since each
IEEE Std 1149.1-compatible cell can latch and remember thelast data pattern that was written when configured correctly.
During memory reads, the latched pattern is fed back forcomparison with the data being read. A pass/fail signal forthe test can be generated by combining the comparison
outputs of each IEEE Std 1149.1-compatible cell.
ASIC Functions
IN

OUT
PRPG/
PSA/
Compare

PRPG

ADDR
Scan
Register CTRL

Embedded
RAM Cell

DATA

Scan
Register

FeedBack
TDI

TDO

Figure 7-11. Testing Embedded RAM

7-15

A similar testing method can be used when testing read-only
memory (ROM) embedded within a device, as shown in
Figure 7-12. During ROM tests, address sequencing andread enables are controlled as in Figure 7-11, and the PSA
mode is used to compress the data output into a
representative signature. If desired, comparison logic can beused to compare the calculated signature with a known goodsignature to generate a memory pass/fail signal.
ASIC Functions
IN

OUT

PSA/
Compare

PRPG
ADDR
Scan
Register CTRL

Embedded
ROM

DATA

Scan
Register

Pass/
Fail

Good
Signature

TDI

TDO

Figure 7-12. Testing Embedded ROM
Summary
The use of TI’s bus-interface components andboundary-scan cells provides increased fault detection andisolation capabilities when used to partition large-capacity
memory boards and devices with embedded memory. The
increased partitioning allows the use of parallel testing andautonomous built-in self test, greatly reducing the overall test
execution times normally attributed to memory testing. IEEE
Std 1149.1 bus-interface components provide simple
replacements for buffers and transceivers that are normallyused in memory system design, while creating little impact
on system performance. TI’s boundary-cell library is acompletely configurable set of test cells that allows thedesigner to create sophisticated test structures (such as
built-in self test for memories), while requiring only a minimal
knowledge of test engineering principles.

7-16

Applications

Backplane Multidrop Environment
The backplane environment, which carries many signals inparallel to all the boards, contains certain conditions notfound in other test situations. A typical backplane with acomplement of boards (such as a computer that uses
different accessory boards) may be configured differently for
different purposes. In other cases, certain boards may becapable of interacting independently of normal backplane
activity, and some boards may include BIST. For maximum
usefulness and short test times, a test program must
accommodate a partially populated backplane, while allowing
more than one board to be active at a time.
IEEE Std 1149.1 was developed to serially access ICs on aboard, but it also can be used to access boards installed in a
backplane. By making simple hardware modifications to the
backplane circuitry, ring or star backplane configurations canbe accessed using normal IEEE Std 1149.1 commands.
In a backplane configured as a ring (see Figure 7-13), allboards directly receive the TCK and TMS control outputs
from a primary test-bus controller (TBC). The scan path isdaisy chained between the TBC’s TDO output and TDI input.
During a test, the TBC drives TMS and TCK to scan data
through all boards in the backplane, through the TDO/TDI
bus connections. A serial path works only if all the boards
are present and can scan data from their TDI input to TDO
output. A missing or faulty board breaks the path, so the TBC
cannot scan data through the backplane.

7-17

U3

U1

U2

U2

U2

U3

U1

U3

U1

TDO

TDO

TDO

Backplane

TCK
TMS

TDI

TCK
TDO
TMS

TDO

Test-Bus
Controller

Figure 7-13. Backplane Ring Configuration
In a backplane star configuration (see Figure 7-14), the TBC
drives TCK and TDI directly to all boards and each board
outputs a TDO signal to the TBC. Each board requires aunique TMS signal from the TBC and a separate circuit tracefor each signal. During testing, only one board is enabled ata time and only the TMS signal for that board is active. In a
backplane with 50 boards, the TBC needs 50 individual TMS
signals, with circuit traces for each. Another drawback is that
only one board can be scanned at a time.

7-18

Applications

U3

U1

U2

U2

U2

U1

U3

U1

U3

Backplane

TMS3
TDI

TMS2

TCK
TDO
TMS1

TDO

Test-Bus
Controller

Figure 7-14. Backplane Star Configuration
Solution
A new serial bus protocol has been developed by Texas
Instruments that is interpreted by a TI device called theAddressable Scan Port (ASP) (SN74ABT8996{). This device
provides linkage between IEEE Std 1149.1-compatible
boards and a backplane. The ASP becomes the IEEE Std
1149.1 input bus for each board in the backplane. It
intercepts the protocol on the normal incoming IEEE Std
1149.1 signal wires, allowing it to connect or disconnect its
board with the IEEE Std 1149.1 bus on the backplane. Once
connected, the board can communicate using the IEEE Std
1149.1 protocol.
The ASP protocol is invoked when the IEEE Std 1149.1 bus
is in one of the following four TAP states: Test-Logic-Reset,
Run-Test/Idle, Pause-IR, or Pause-DR.
{

SN54ABT8996, SN54ABT8996 10-Bit Addressable Scan Ports Multidrop
Addressable IEEE 1149.1 (JTAG) TAP Transceivers, Literature Number
SCBS489A, Texas Instruments 1996.

7-19

The protocol can address and select any ASP-equippedboard in the backplane. After the board is connected to theIEEE Std 1149.1 bus, the ASP simply passes data through tothe bus so normal operation can resume.
Detailed Description
Figure 7-15 shows a backplane with ASP devices on eachboard, allowing individual boards to be configured and active
simultaneously.
U2

U2

U3

U1

U1

U2

U3

ASP

ASP

U1

U3

ASP

Backplane

TDI

TCK
TDO
TMS

TCK
TDI
TMS
TDO

Test-Bus
Controller

Figure 7-15. Backplane With ASP-Equipped Boards
For example, if the interconnects between two boards are to
be tested, it is necessary to select and scan the first board to
output a test pattern, then select the other board to receive
the test pattern. The ASP makes it possible to select andscan the second board without resetting the first board.
During operation, each pattern of the interconnect test isscanned out of the receiving board before a new pattern isscanned into the driving board.

7-20

Applications

Another test may be to select and initiate self-tests in a
selected group of backplane boards. The ASP allows BIST tostart on each board and run while other board tests are
initialized. Each board is then polled to read the test results,
one board at a time.
Summary
The special problems associated with backplane testing canbe accommodated when the SN74ABT8996 Addressable
Scan Port is added to individual boards.

Embedded Applications
Field testing can be simplified if equipment is configured totake advantage of embedded IEEE Std 1149.1 functions.
Solution
TI’s SN74ACT8990† Test-Bus Controller (TBC) andSN74LVT8980‡ Embedded Test-Bus Controller (eTBC)
devices can be embedded in system circuitry to provide
autonomous IEEE Std 1149.1-based testing. A licensable,
embeddable “C” source code product called Scan Engine,which includes test vector translators, is available to simplify
embedded boundary-scan test applications.
Detailed Description
TI’s test-bus controller devices operate under the control of ahost processor to master one or more IEEE Std 1149.1 scanpaths. Appearing to the host as memory- or I/O-mapped
peripherals, they accept parallel command and test data andconvert it to appropriate IEEE Std 1149.1 protocols, as
required. Thus, they allow the host software to operate at ahigh-level (essentially, at the level of SVF) rather thanrequiring that it encode knowledge of TMS state,sequencing, etc.

† SN54ACT8990, SN74ACT8990 Test-Bus Controllers, Literature Number
SCAS190C, Texas Instruments 1996.
‡ SN54LVT8980, SN74LVT8980 Embedded Test-Bus Controllers, Literature
Number SCBS676, Texas Instruments 1996.

7-21

Host Interface
Both TBC and eTBC devices implement a generic hostinterface. Each contains a set of memory- or I/O-mappable
registers that can be read/written by the host to control its
operation and monitor its status.
The host interface of the TBC consists of a 16-bit data bus,
5-bit address bus, read strobe, and write strobe. The
24-register set includes two command registers, in addition
to scan-data FIFOs, configuration registers, status registers,
and counter registers.
The host interface of the eTBC consists of an 8-bit data bus,
3-bit address bus, read/write select and read/write strobe.
The 8-register set includes one command register in addition
to scan-data FIFOs, configuration registers, status register,and counter register.
IEEE Std 1149.1 Interface
The TBC implements six separate TMS output signals
allowing it to directly master up to six separatestar-configured scan paths. The TBC also has two separate
TDI inputs that can be used to support scan paths withdifferent requirements for buffering of their TDO signals (forexample, scan path(s) that are on the same PCB as the TBC
versus scan path(s), which are on remote PCBs).
The eTBC implements a single set of TAP-mastering
outputs, allowing it to directly master only one scan path.
However, the eTBC provides a wealth of features thatprovide exceptional flexibility in control of scan test
operations:
Programmable division of TCK output frequency allows
support for slow-scan-rate components while still operating
fast-scan-rate components at higher speed.
Discrete mode of TAP control enables arbitrary TMS/TDO
sequences to allow for support of non-compliant
components or specialized test extensions.
Gated mode of TCK output provides mechanism fordirectly supporting ’ABT8996 Addressable Scan Port
(ASP) shadow protocols in multidrop configurations.

7-22

Applications

Command Set
Both TBC and eTBC devices support high-level commandsets that allow the host to directly request IEEE Std 1149.1
state changes, scan operations, or periods of execution in
the Run-Test/Idle state.
While the TBC can be made to generate ASP shadow
protocols by proper sequencing of configuration changes andscan operations, the eTBC command set contains direct
ASP scan commands.
Isolating the TBC From the IEEE Std 1149.1 Bus
Each of the TBC and eTBC devices provides a mechanism
for allowing its IEEE Std 1149.1 interface to be disabled.
When the TOFF* of the TBC is asserted or the OE* of theeTBC is released, the respective TAP-mastering outputs areforced to a high-impedance state. By so disabling the IEEE
Std 1149.1 interface, an external controller (for example, ascan-based ATE) is allowed to take control over theembedded scan path.
Host Requirements
A host processor executing embedded test software (forexample, Scan Engine) needs three primary hardware
resources:
Memory- (or I/O-) mapped parallel access to the
TBC/eTBC
ROM/EPROM space for the object code
RAM or ROM space for the test vectors. These test
vectors are broken into two primary blocks, stimulus data
and response data.
It should be noted that the stimulus data could either be
downloaded into RAM or be permanently programmed into
ROM/EPROM.
Summary
The SN74ACT8990 Test-Bus Controller and SN74LVT8980
Embedded Test-Bus Controller devices offer the designer ofhigh-reliability equipment a way to embed automatic IEEE
Std 1149.1-compliant test circuitry into products. Scan
Engine software provides an easy way to control the TBC in
7-23

an embedded system. The solution discussed here
maintains IEEE Std 1149.1-compatibility and access to test
vectors developed during design verification. The result is
continuous quality assurance with direct traceability todevelopment data.

Boundary-Scan Test Flow
When new ASICs or boards come from the manufacturingline, the first concern is that the devices work as designed.
High-density ASICs and multi-layer PWBs with surface
mount devices cannot be adequately tested withoutboundary-scan testing.
Solution
Use boundary-scan techniques and tools on products
designed with IEEE Std 1149.1-1990-compatible
components.
Detailed Description
Figure 7-16 summarizes an efficient verification processusing BSDL supplied by manufacturers of IEEE Std
1149.1-compatible ICs and HSDL developed for the ASICs
and PWB.

7-24

Applications

CAE or SC Vendor
Data

Automated Assembly
Verification
Pass
Automated Functional
Verification

Pass

Fail
Interactive
Verification andFault Isolation
Pass
System Integrationor Manufacturing

Figure 7-16. General Boundary-Scan Test

7-25

Automated Assembly Verification
Automated assembly verification depends on getting BSDL
or HSDL descriptions for IEEE Std 1149.1-compatible
devices from the manufacturer and developing
corresponding HSDL for modules, boards, and systems.
Figure 7-17 shows the flow that verifies a correct scan pathand interconnections between boundary-scan cells.
Create Scan Path Data
Base Using BSDL/HSDL
Translator

Verify Device and System
Scan Path Using Scan Path
ATPG

Verify Interconnections
Using Interconnect ATPG

Fault
Coverage
Report

Fault
Diagnostic
ReportFigure 7-17. Assembly Verification Flow
Devices that pass assembly verification must then be tested
for functionality.
Automated Functional Verification and Fault Detection
Functional verification begins with IC testing, followed byvirtual component or cluster testing and system verification.
These flows and the tools involved are shown in Figure 7-18.

7-26

Applications

Integrated Circuit
Test (INTEST)
Apply Vectors
From CAE

No
Repair

Tests
Pass
?
Yes
SystemVerification

Cluster Test
Apply Test
Vectors

Tests
Pass
?
No

Apply Test
Program Set

Yes
No

Tests
Pass
?
Yes

Interactive
Verification andFault Isolation

System Integrationor Manufacturing

Figure 7-18. Automated Functional Verification andFault Detection
No matter which flow is used, the goal is to reuse datawhenever possible. For functional verification we want toreuse any serial or parallel vectors developed in the CAE
system; those vectors become a pass/fail test. When CAE
vectors are not available, boundary-scan test tools support
test stimulus development approaches such as vector
recording, macros, and high-level-language programs.
All functional tests highlight failures down to the vector level.
Knowing which vector failed can reduce the time spent ininteractive testing to isolate the problem to a device, register,or pin.

7-27

Interactive Verification and Fault Isolation
Figure 7-19 shows how faults in units failing previous tests
can be isolated using scan-based test tools.
Use Diagnostics From
Previous Tests

Other Non-Scan
Instruments

Interactive
Scan Tool

Scan-Based Logic
Analysis Tool

Initialize Test
SystemParameters

Apply Stimulus

Analyze Results

Results
Ok?

No

Yes
System Integration/
Manufacturing

Figure 7-19. Interactive Verification and Fault Isolation
Summary
Design verification and fault isolation processes are greatly
enhanced when a full suite of boundary-scan tools andtechniques are used.

7-28

Applications

Chapter 8
Product Summary
This chapter provides a brief description of TI’s
comprehensive offering of IEEE Std 1149.1-compatible
components and a listing of TI’s IEEE Std 1149.1 (JTAG)
boundary-scan logic product family.

IEEE Std 1149.1-Compatible Components
TI has a long history of involvement with JTAG and IEEE Std
1149.1 and of support for integrated circuits that incorporate
IEEE Std 1149.1-compatible boundary scan. Starting withrelease of the first commercially available boundary-scanlogic ICs in May 1990, only 3 months after ratification ofIEEE Std 1149.1, TI has lead the semiconductor industry in
its offerings of products that support board- and system-leveltestability.
In addition to TI’s broad line of boundary-scan logic devices(see below), which are implemented primarily for the purposeof building board- and system-level test architectures, TI
supports IEEE Std 1149.1-compatible ICs across its broad
product lines. From ASIC to DSP, networking to multimedia,
TI’s portfolio includes many boundary-scan devices.
Highlights
ASIC — To facilitate the implementation of IEEE Std
1149.1-compliant boundary scan in TI’s ASIC products,
boundary-scan-cell modules have been developed for CMOS
standard-cell and gate-array libraries.
DSP — Select functions in TI’s ’C4x, ’C5x, ’C54x, and ’C8x
(MVP) generations incorporate IEEE Std 1149.1 boundary
scan. In addition, all functions in these generations and in the’C2xx generation use the test access port (TAP), as specified
by IEEE Std 1149.1, to access on-chip emulation features.
Networking — Currently, several functions fromThunderLAN (Ethernet) and ThunderCELL(Asynchronous Transfer Mode) families offer IEEE Std
1149.1 boundary scan.

8-1

IEEE Std 1149.1 (JTAG) Boundary-Scan Logic
TI’s family of IEEE Std 1149.1 (JTAG) boundary-scan logic
includes octal bus interface, Widebus, and scan-support
functions that incorporate circuitry that allows them, and theelectronic systems or subsystems in which they are used, tobe tested without reliance on traditional probing techniques.
In all, over 30 devices, composed of a wide selection of BCT
and ABT octal bus interface, ABT(H) and LVTH Widebus,and scan-support functions, are currently available.
For data sheets and documentation, see the 1997
Boundary-Scan Logic, IEEE Std 1149.1 (JTAG) 5-V and
3.3-V Bus-Interface and Scan-Support Products Data Book,
literature number SCTD002.
Bus
Interface

Octal

BCT

Scan
SupportWidebus

ABT

ABT/H†LVTH†† “H” indicates bus hold

Figure 8–1. TI’s Family of IEEE Std 1149.1 (JTAG)
Boundary-Scan Logic

8-2

Product Summary

Bus Interface
Bus-interface functions are available in BCT, ABT, and LVT(3.3-V ABT) technologies, in octal and Widebus
(18- and 20-bit) options of standard buffers, latches, flip-flops,
transceivers, and registered transceivers. Featured is theuniversal bus transceiver (UBT) which, in a single package,
can serve all of these common bus-interface roles. In addition,
ABT and LVT technologies offer devices with bus-hold inputs
and integrated series-damping resistors. Package options forthe bus-interface devices include plastic dual in-line (PDIP),
small-outline integrated circuit (SOIC), shrink small-outline
package (SSOP), thin shrink small-outline package (TSSOP),
and plastic thin quad flat package (TQFP).
Octal Bus Interface
SN74BCT8240A
SN74BCT8244A
SN74BCT8245A
SN74BCT8373A
SN74BCT8374A
SN74ABT8245
SN74ABT8543
SN74ABT8646
SN74ABT8652
SN74ABT8952

24
24
24
24
24
24
28
28
28
28

Octal Inverting Buffer/ Driver
Octal Buffer/ Driver
Octal Bus Transceiver
Octal Transparent D-Type Latch
Octal D-Type Flip-Flop
Octal Bus Transceiver
Octal Registered Bus Transceiver
Octal Registered Bus Transceiver
Octal Registered Bus Transceiver
Octal Registered Bus Transceiver

64
64
64
64
64
64
64
64
64
64
64
64
64

18-Bit Universal Bus Transceiver
20-Bit Universal Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Universal Bus Transceiver
20-Bit Universal Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Universal Bus Transceiver
18-Bit Universal Bus Transceiver
20-Bit Universal Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Registered Bus Transceiver

Widebus— TQFP
SN74ABT18502
SN74ABT18504
SN74ABT18646
SN74ABT18652
SN74ABTH18502A
SN74ABTH18504A
SN74ABTH18646A
SN74ABTH18652A
SN74LVT18502
SN74LVTH18502A
SN74LVTH18504A
SN74LVTH18646A
SN74LVTH18652A

8-3

Widebus— TQFP, with series-damping resistors
SN74ABTH182502A
SN74ABTH182504A
SN74ABTH182646A
SN74ABTH182652A
SN74LVT182502
SN74LVTH182502A
SN74LVTH182504A
SN74LVTH182646A
SN74LVTH182652A

64
64
64
64
64
64
64
64
64

18-Bit Universal Bus Transceiver
20-Bit Universal Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Universal Bus Transceiver
18-Bit Universal Bus Transceiver
20-Bit Universal Bus Transceiver
18-Bit Registered Bus Transceiver
18-Bit Registered Bus Transceiver

56
56
56
64
64
64
56

18-Bit Bus Transceiver
18-Bit Inverting Bus Transceiver
18-Bit Bus Transceiver
18-Bit Universal Bus Transceiver
20-Bit Universal Bus Transceiver
18-Bit Universal Bus Transceiver
18-Bit Inverting Bus Transceiver

Widebus — TSSOP
SN74ABT18245A
SN74ABT18640
SN74LVTH18245
SN74LVTH18512
SN74LVTH18514
SN74LVTH18516
SN74LVTH18640

Widebus — TSSOP, with series-damping resistors
SN74LVTH182245
SN74LVTH182512
SN74LVTH182514
SN74LVTH182516
SN74LVTH182640

56
64
64
64
56

18-Bit Bus Transceiver
18-Bit Universal Bus Transceiver
20-Bit Universal Bus Transceiver
18-Bit Universal Bus Transceiver
18-Bit Inverting Bus Transceiver

Universal Bus Transceiver (UBT)The UBT is the flagship of TI’s IEEE Std 1149.1 bus-interface
offerings. With its dual-ranked latch storage and generalized
control logic, the basic UBT can perform all of the mostcommon bus-interface roles: driver, latch, flip-flop,transceiver, latched transceiver, and registered transceiver.
Enhanced UBT functions offer additional features such as
clock enable and stored/real-time data multiplexers. With theadded feature of boundary scan, TI’s IEEE Std 1149.1 UBTs
are the ideal solution for nearly all bus-interface needs.

8-4

Product Summary

Table 8-1. IEEE Std 1149.1 UBTs Replace 50+ Bus
Functions
FUNCTION

8 BIT

9 BIT

10
BIT

Transceiver’245,’623,’645’863

Buffer/Driver’241,’244,’541

LatchedTransceiver

16 BIT

18 BIT

20 BIT’861’16245,’16623’16863’16861’827’16241,’16244,’16541’16825’16827’16543’16472’16373’16843’16646,16652’16474

’543

Latch

’373,’573

Registered
Transceiver’646,’652

Flip-Flop’374,’574

’843

’841

’821

’16374Standard
UBT*’16841’16821’16500,’16501

Universal
Bus Driver’16835’18502 and ’18512 UBTs Replace Above Functions

Registered
Transceiver
w/CLK
Enable’2952

Flip-Flopw/CLK
Enable’377’16470,’16952’823’16823

Std UBT*w/CLK
Enable’16721’16600,16601’18516 UBT Replaces Above Functions’18504 and ’18514 UBTs Replace All Above Functions*Non-Boundary-Scan Device

Scan Support
Scan-support functions facilitate implementation of boardand system-level test architectures. These include devices
for mastering the IEEE Std 1149.1 test bus, adapting theIEEE Std 1149.1 test bus to multidrop configuration,
performing at-speed functional test, and partitioning the scanpath into smaller, more manageable segments.
SN74LVT8980

28

Embedded Test-Bus Controller

SN74ACT8990

44

Test-Bus Controller

SN74ABT8996

24

Addressable Scan Port

SN74ACT8994

28

Digital Bus Monitor

SN74ACT8997

28

Scan-Path Linker

SN74ACT8999

28

Scan-Path Selector
8-5Test-Bus Controllers
Embedded Test-Bus Controller (eTBC) — The
SN74LVT8980 provides a simple, off-the-shelf solution thatcan be hosted by a low-cost 8-bit microcontroller or
microprocessor to generate the signals required to masterthe IEEE Std 1149.1 test bus. Its LVT implementation meansthat this device is the industry’s first test-bus solution tooperate at 3.3 V, while it still interfaces to scan-path devices
that use 5-V power.
Test-Bus Controller (TBC) — The SN74ACT8990 provides asimple, off-the-shelf solution that can be hosted by a 16-bit
microcontroller/microprocessor to generate the signals
required to master the IEEE Std 1149.1 test bus.
Backplane/Multidrop Test-Bus Support
Addressable Scan Port (ASP) — IEEE Std 1149.1 defines
how to implement boundary scan at the IC level but does notaddress board- or system-level architectures. With TI’s
SN74ABT8996 device, backplane or other multidrop
applications now can be supported.
At-Speed Functional Test
Digital Bus Monitor (DBM) — The SN74ACT8994 is a
special-function device that provides the capability toemulate the functions of logic and signal analyzers. The
DBM can be embedded in systems as a non-intrusive
at-speed monitor. A single DBM monitors up to 16 signals,
but several can be used in concert for width or depth
expansion.
Scan-Path Support
Scan-Path Linker (SPL) — The SN74ACT8997 provides for
scan-path partitioning by allowing selection, under IEEE Std
1149.1 scan control, of any combination of up to four
secondary scan paths. Multiple SPL devices can becascaded to support any desired number of secondary scanpaths, as well as multilevel hierarchies.
Scan-Path Selector (SPS) — The SN74ACT8999 provides
for scan-path partitioning by allowing selection, under IEEE
Std 1149.1 scan control, of any one of four secondary scanpaths.
8-6

Product Summary

Note:
Not all devices mentioned are available at the time ofthis printing. Contact your TI sales representative or
authorized distributor for commercial or military grade
availability information.

8-7

Chapter 9
Other Support and Learning ProductsThis chapter provides information concerning learning tools
available for IEEE Std 1149.1-1990.

Scan Educator
The Scan Educator PC-based tutorial software introduces
the fundamentals of IEEE Std 1149.1, including architecture,
protocols, and required instruction set. Self-paced andmenu-driven, it contains both information and animatedboundary-scan simulations. Hands-on exercises guide you
through a boundary-scan test of an IEEE Std
1149.1-compliant octal at the bit-by-bit and register levels.
You also are shown how to use boundary-scan testing withsingle or multiple devices for in-circuit observability andcontrollability.

Scan Board
No matter where you are on the boundary-scan learning
curve, TI’s Scan Board can help you move to higher levels of
understanding — quickly and easily. Scan Board can be alearning tool for new users of boundary-scan and a test andevaluation platform for the experienced user. This speciallydeveloped board comes with multiple IEEE Std
1149.1-compliant devices that can help you evaluate both thetools and the concepts behind board-level testing. With Scan
Board, you can perform boundary-scan interconnect tests
and insert various faults and fault types, as well as
demonstrate board-level built-in self-test (BIST) for testing
memory, internal test (INTEST) of an ASIC, internal BIST of
an ASIC, cluster testing, single- and multiple-scan paths, andmany other capabilities. Scan Board comes with schematics,
netlists, X-Y plots, data sheets, test patterns, BSDL
descriptions, and a free executable software program. This
software allows you to apply test patterns supplied with Scan
Board, or to apply your own.

9-1

Scan Board demonstrates these advanced test techniquesand more:
Scan-path verification
Interconnect testing
Pins-in (IC core logic) testing
BIST methods at the device and board level
Boundary-scan interconnect automatic test-patterngeneration (ATPG)
Functional cluster logic tests using boundary-scan and
BIST capabilities
Fault detection and isolation
Control and monitoring of discrete event lines
Counting, toggle, and pseudorandom pattern generation(PRPG) stimulus methods
Parallel signature analysis (PSA) response capture
Scan-path switching
Flexibility
Scan Board incorporates basic boundary-scan features for
new users to learn boundary-scan testing, and also
incorporates advanced extensions such as BIST, INTEST,internal scan, and multiple scan paths for advanced users.
Scan Board’s physical layout separates independent multiple
functions both electrically and physically, while maintaining asingle continuous IEEE Std 1149.1 scan path for ease of test
manipulation. Fault-injection switches are provided so theuser can practice fault-isolation techniques. Scan Board
provides for the injection of 12 different faults. Fault types
include: stuck-at-one, stuck-at-zero, bridging, non-adjacentbridging, internal device, and scan path.

9-2

Other Support and Learning ProductsCompatibility
Scan Board is compatible with in-circuit test fixtures andtesters. Nodes are accessible via boundary-scan or from thebottom with adequate and uniform spacing for in-circuit
probes. Nets without both the boundary-scan driver andreceiver are accessible via 40-mil probe points with 100-mil
spacing.
Supporting Documentation Included
Scan Board comes with board description and operation,
schematics and diagrams, X-Y and Gerber plots, a fault
table, and boundary-scan device data sheets. Electronic files
include BSDL, HSDL, Netlists (Viewlogic, EDIF 2.0.0, andTeradyne CDB), interconnect patterns (SVF), ASIC internal
test patterns (SVF), and cluster-logic test patterns (SVF).
Scan Board demonstration software is included at no extra
charge.

CD-ROM
TI has combined the key elements of IEEE Std 1149.1 on asingle CD-ROM. Now the latest versions of the IEEE Std
1149.1-1990 (including IEEE Std 1149.1a-1993) are merged
into one searchable document.
Also included are TI’s:
Test-bus evaluation report
Application notes
Data sheets for TI boundary-scan products
The test-bus evaluation (TBE) report was written by TI’s
Defense Systems & Electronics Group to evaluate theapplications and impact of standard test buses on overallsystem testability. The TBE report is based on years oftest-bus development and applications experience at TI;
since the early 1980s, TI has played a key role in defining
test buses, first, for the VHSIC program, and then later as a
key contributor in both JTAG and IEEE Std 1149.1.
This CD-ROM brings together current information on IEEE
Std 1149.1. Microsoft and UNIX environments are supported.

9-3

Testability Video Tape
Texas Instruments offers a 74-minute, two-part video toexplain the concept of testability. The tapes are available in
U.S. (NTSC) and international (PAL) formats.
Tape 1 — The first tape explains the growing importance of
testability and the tremendous potential impact on cost,time, and quality that design for test (DFT) can have. It
also describes the work of the Joint Test Action Group(JTAG) and the provisions of IEEE Std 1149.1.
Tape 2 — The second tape examines the standard in moredetail. It explains the test-bus architecture andinstructions and shows how to use boundary-scan
testing on a board or system. The tape includes
software-support standards, example application, andinformation on how boundary-scan test tools help
automate boundary-scan testing. The tape clearly
explains the function of each component of thestandard, and shows how they work together to provide
an accurate, dependable test procedure.
Boundary-Scan Video Outline
Introduction — Testing problems and concepts
Economics — Benefits and cost-reduction potential
Design-for-Testability Concept — Controls, diagnosis,
DFT strategies, and more
Introduction — IEEE Std 1149.1 Boundary Scan
Details of IEEE Std 1149.1
Testing With IEEE Std 1149.1 Boundary Scan — During
design and development, production, field testing andmaintenance. Also in this section: testing theboundary-scan core logic at the board level, optimized
interconnect tests, isolating interconnect faults, testingboards with a mix of boundary-scan andnonboundary-scan components, testing mixed-signal
boards, and exploiting BIST during tests.
Digital Applications of IEEE Std 1149.1 Boundary Scan
— Data formats supporting boundary scan, plus
application notes

9-4

Other Support and Learning Products

Proposed Product Development and Support Cycle
Commercially Available Products for DFT
Available Training on DFT and Boundary Scan

9-5

Appendix A
Abbreviations/Acronyms
AC
ASIC
ASP
ASSET
ATE
ATG
ATPG
BIST
BIT
B/S
BSC
BSDL
BSR
BST
CAD
CAE
DBM
DC
DFT
DIP
DR
DSP
EDA
ESD
ETBC
FIFO
HDL
HSDL
IC
ICE
ICT
ID
IEEE
I/O

Alternating Current (dynamic)
Application-Specific Integrated Circuit
Addressable Scan Port
Advanced Support System for Emulation
and Test
Automatic Test Equipment
Automatic Test Generation
Automatic Test-Pattern Generation
Built-In Self-Test
Built-In Test
Boundary Scan
Boundary-Scan Cell
Boundary-Scan Description Language
Boundary-Scan Register
Boundary-Scan Test
Computer-Aided Design
Computer-Aided Engineering
Digital Bus Monitor
Direct Current (static)
Design for Test
Dual In-Line Package
Data Register
Digital Signal Processor
Electronic Design Automation
Electrostatic Discharge
Embedded Test-Bus ControllerFirst-In, First-Out (memory)
Hardware Description Language
Hierarchical Scan Description Language
Integrated Circuit
In-Circuit Emulation
In-Circuit Test
Identification
Institute of Electrical and Electronics Engineers
Input/Output
A-1

IR
ISP
JEDEC
JIT
JTAG
LSB
LSSD
MSB
PCB
PPM
PRPG
PSA
PWB
SPL
SPS
SSA
SVF
TAP
TBC
TCK
TDI
TDL
TDO
TMS
TPS
UBT
UUT
VHDL
VHSIC
XCVR

A-2

Instruction Register
In-System Programming
Joint Electronic Device Engineering Council
Just-In-Time (manufacturing)
Joint Test Action Group
Least-Significant Bit
Level-Sensitive Scan Design
Most-Significant Bit
Printed Circuit Board
Parts Per Million
Pseudorandom Pattern Generation
Parallel Signature Analysis
Printed Wiring Board
Scan-Path Linker
Scan-Path Selector
Serial Signature Analysis
Serial Vector Format
Test Access Port
Test-Bus Controller
Test Clock
Test Data Input
Test Description Language
Test Data Output
Test Mode SelectTest Program Set
Universal Bus Transceiver
Unit Under Test
VHSIC Hardware Description Language
Very High-Speed Integrated Circuit
TransceiverAbbreviations/Acronyms

Appendix B
Glossary
Automatic Test Generation
A functional test pattern generation that is done
algorithmically on a computer
Boundary-Scan Description Language (BSDL)
A hardware description language developed to describe
devices built to IEEE Std 1149.1. See also HSDL.
Built-In Self Test
Logic included within a design that can apply test signals
and compare results to determine if the design isworking correctly
Concurrent Fault Simulation
A fault simulation method that simulates only fault
models that differ from the fault-free model at the node
being simulated. The node being simulated is an
event-driven node.
Controllability
The ability to set a logical value on a signal node within
the design. Controllability can be a measure of how
difficult it is to generate test patterns. If a signal is hard
to control, it is difficult to set up values necessary to test
design features.
Design for Test
A method that incorporates rules and techniques in thedesign process to make testing easierDetectable Fault
A possible failure that has at least one test pattern orsequence of patterns that, when applied to a device,detect failure
Deterministic Test Vectors
A fixed-order set of test patterns
Fault
A design failure or flaw that causes an incorrect
response to input stimuli
Fault Grade
The percentage of modeled faults that will be detectedby a test sequence when applied to a device. The fault
grade is determined through fault simulation.

B-1

Fault Model
A simulator representation of a fault to model an
unexpected behavior of a failure
Fault Simulation
The process of simulating test patterns using fault
models and a fault-free model to determine whether
potential failures will be detected with the test sequence
Gate-Pin Fault
A fault modeled at the connection of a gate pin to thesignal-node net
Hierarchical Scan Description Language (HSDL)
A superset of BSDL developed by TI. HSDL is used todescribe IEEE Std 1149.1-compliant devices, modules,
and systems. See also BSDL.
Initialization
The process of placing a circuit or unit under test into aknown state for testing or logic simulation
Interconnect Testing
A test process that verifies correct connections between
ICs and modules on a board
Level-Sensitive Scan Design (LSSD)
The IBM DFT methodology of scan design. “Level
Sensitive” means that all registers are activated with
voltage levels rather than clock edges.
Linear Feedback Shift Register (LFSR)
A shift register counter that can be used forpseudorandom test pattern generation and forcompression of test pattern results
Load Fault
A fault model that is a load on a wired junction
Logical Redundancy
Design logic that, removed from the design, performs
and provides the same static logic responses. Logicalredundancy may be purposefully added to improve
speed or drive performance.
Modular Testing
Testing a design by applying independent test
sequences to test isolatable modules. Each module has
its own test sequence that is not affected by othermodules in the design. With modular testing, ATG and
fault grading can be performed on a single module at a
time.
B-2

Glossary

Multiple Fault
A fault model created by simultaneously representing
the fault with multiple stuck-at faults
Node Fault
A fault model that ties an interconnection net to a fixed
logic level. A node fault is equivalent to all sources on a
net being source faults with the same logical value.
Observability
The capability to observe the effect of a node value at an
output pin. If the node value changes, the output value
also changes.
Parallel Fault Simulation
A method that simulates a set of fault models at thesame time as the fault-free model
Parallel Signature Analyzer
An LFSR used to compress test data by collecting datafrom the design and exclusive ORing the resulting test
data with register-state data
Parametric Test
A test that checks the voltage, current, and timing
specifications of a design. The ac and dc propagation
tests are parametric tests.
Propagation
The response of an output of a gate (or net) to an inputof the gate (or net)
Scan-Path Design
A DFT methodology where all or a selected group of
storage elements can be serially interconnected tofacilitate testing of embedded combinational logic in an
integrated circuit
Scan-Path Linker (SPL)
TI’s SN74ACT8997 device acts as a scan-path
multiplexer, allowing dynamic path switching. The SPL
can select any combination of four secondary scanpaths.
Scan-Path Selector (SPS)
TI’s SN74ACT8999 device acts as a scan-path
multiplexer, allowing dynamic path switching. The SPS
can select one of four secondary scan paths at a time.

B-3

Scan Testing
The DFT technique that connects all internal registers ina design into a shift register used during test. The scan
shift registers, called scan paths, are used to load any
desirable state before application of a test overcombinational logic between serial (scannable) registerlatches and unload any resultant state for observation.
Serial Vector Format (SVF)
A standard ASCII-based pattern format for expressingIEEE Std 1149.1 scan operations and state transitions.
This vector format was jointly developed by TI and
Teradyne to allow pattern transportability between test
tools.
Source Fault
A fault model that is a source to a wired-junction net.
Gate outputs are examples of source faults.
Stuck Closed (Shorted Gate) Fault
A stuck-at fault model in which the transistor controlled
by the gate is always closed. This has the same effectas shorted data lines. This fault model is the same as an
SA1 fault on the gate input of an n-p-n transistor or an
SA0 fault on the gate input of a p-n-p transistor.
Stuck Fault
A failure model in which a gate pin is modeled as stuck
to VCC (for stuck-at-one, SA1 ) or to GND (forstuck-at-zero, SA0)
Stuck Open (Open Gate) Fault
A stuck-fault model in which the transistor controlled by
the gate is always open. This fault model is the same as
an SA0 fault on the gate input of an n-p-n transistor oran SA1 fault on the gate input of a p-n-p transistor.
Test Access Port (TAP)
Port described in IEEE Std 1149.1-1990. Must contain aminimum of three input connections (TDI, TMS, TCK)
and one output connection (TDO). A fourth input
connection (TRST*) is optional. The TAP provides
access to test functions built into a component.
Test Description Language (TDL)
A test pattern format that describes the stimuli and
expected results for a test application. TDL tests areapplied using I/O connector pins.

B-4

GlossaryTest Generation
The process of producing a test sequence to test adesign. Three methods of test generation are: automatic
test generation (ATG), manual test preparation, andrandom input values generation.
Test Pattern
A set of input stimuli values that are applied at the
beginning of a period of time and a set of output
observation values made at the end of a period of timethat are represented by a string of values
Test Pattern Grading
The process of fault simulating a test pattern sequence
to obtain a fault grade
Test Point Insertion
The DFT technique that includes additional connections
to internal nodes for either control or state observation
Test Vector
Another name for a test pattern
Testability
The property of a circuit, board, or system that enables
testing
Undetectable Fault
A fault that cannot be detected by any achievable test
pattern. Undetectability may be due to logic redundancy
or to logic that cannot be observed.
Unpredictable Fault
A fault that causes the value of a node to beindeterminate, thereby making it impossible to detect a
fault

B-5

Appendix C
References
1. Agrawal, Vishwani D., “Sampling Techniques for
Determining Fault Coverage in LSI Circuits,” Journal of
Digital Systems, Vol. V., Number 3, pp. 189-203.
2. Bennetts, R. G., Introduction to Digital Board Testing,
Crane, Russak & Company, Inc., NY, NY, 1982.
3. Bhavsar, D. K., and R. W. Heckelman, “Self-Testing by
Polynomial Division,” Digest of IEEE Test
Conferences,1981, pp. 208-216.
4. Bleeker, van den Eijnden, de Jong, Boundary-Scan Test
— A Practical Approach, ISBN 0-792-9296-5.
5. Frohwerk, R. A., “Signature Analysis: A New Digital Field
Service Method,” Hewlett-Packard Journal, May 1977,
pp. 2-8.
6. IEEE Std 1149.1-1990 (includes IEEE Std 1149.1a-1993),
IEEE Standard Test Access Port and Boundary-Scan
Architecture, ISBN 1-55937-350-4.
7. IEEE Std 1149.1b-1994, Supplement to IEEE Standard
Test Access Port and Boundary-Scan Architecture, ISBN
1-55937-497-7.
8. Jandhyala, S. and A.W. Ley, “Design-for-Test Analysis ofa Buffered SDRAM DIMM,” 1996 Proceedings,
International Workshop on Memory Technology, Design,
and Testing.
9. Ley, A. W., “A Look at Boundary Scan from a Designer’s
Perspective,” 1994 Proceedings, Electronic Design,
Automation & Test Asia Conference.
10. Maunder, Colin M. and Rodham E. Tulloss, The Test
Access Port and Boundary-Scan Architecture, ISBN
0-8186-9070-4.

C-1

11. Parker, Kenneth P., The Boundary-Scan Handbook, ISBN
0-7923-9270-1.
12. Peterson, W. W., and E. J. Weldon Jr., Error Correcting
Codes, MIT Press, Cambridge, MA, 1972.
13. Pynn, C., Strategies for Electronics Test, McGraw-Hill,
Inc., NY, 1986.
14. Sridhar, T., D. S. Ho, T. J. Powell, and S. M. Thatte,“Analysis and Simulation of Parallel Signature Analyzers,”
1982 International Test Conference, Philadelphia, PA,
November 15-18,1982, pp. 656-661.
15. Thatte, S. M., D. S. Ho, H. T. Yuan, T. Sridhar, and T. J.
Powell, “An Architecture for Testable VLSI Processors,”
1982 International Test Conference, Philadelphia, PA,
November 15-18, 1982, pp. 484-493.
16. Turner, M.E., D. G. Leet, Ronald J. Prilik, and D. J.
McLean, “Testing CMOS VLSI: Tools, Concepts, andExperimental Results,” 1985 International Test
Conference, Philadelphia, PA, November 19-21, 1985,
pp. 322-328.
17. Whetsel, L., “A Proposed Standard Test Bus andBoundary Scan Architecture,” 1988 IEEE International
Conference on Computer Design, Rye Brook, NY,
October 3-5, 1988, pp. 330-333.
18. Whetsel, L., “A Proposed Method of Accessing 1149.1 in
Backplane Environment,” 1992 Proceedings, International
Test Conference.
19. Whetsel, L., “Hierarchically Accessing 1149.1
Applications in a System Environment,” 1993
Proceedings, International Test Conference.
20. Williams, T. W., “VLSI Testing,” Computers, Vol. 17, No.
10, October 1984, pp. 126-136.

C-2

References

Appendix DInternet Starting Points
Institute of Electrical and Electronics Engineers (IEEE)
http://www.ieee.org/index.html
IEEE Std 1149.1
http://www.computer.org/tab/tttc/standard/s1149-1/
home.html
Test Technology Technical Committee (sponsor for IEEE
1149.x standards)
http://www.computer.org/tab/tttc/
Texas Instruments
http://www.ti.com
Texas Instruments Semiconductor Group
http://www.ti.com/sc/docs/schome.htm
Texas Instruments Advanced System Logic
http://www.ti.com/sc/docs/asl/home.htm
Texas Instruments IEEE 1149.1 (JTAG) Boundary Scan
http://www.ti.com/sc/docs/jtag/jtaghome.htm
Texas Instruments IEEE 1149.1 Silicon Product and BSDL
Availability
http://www.ti.com/sc/docs/jtag/silicon.htm
Texas Instruments Product Information Data Sheet Search
http://www.ti.com/sc/docs/psheets/pids.htm

D-1

IndexA

B

ABT octals, 8-2, 8-3

backplane configuration
multidrop (ASP), 7-19, 8-6
illustrated, 7-20
ring, 7-17
illustrated, 7-18
star, 7-18
illustrated, 7-19

ABT Widebus, 8-2, 8-3, 8-4
Addressable Scan Port
(ASP), 8-6
application illustrated, 7-20
introduction, 7-19
application notes, 9-3

backplane faults, 7-7, 7-8,
7-9

ASIC, 8-1

BCT octals, 8-2, 8-3

ASP. See Addressable ScanPort

board design
flow illustrated, 6-4
principles discussed, 6-8

at-speed functional test, 8-6

board faults, 1-4
automatic test equipment(ATE)boundary-scan, See alsoboard-etch and solder-joint
IEEE Std 1149.1
testing, 7-1
ASIC synthesis, 6-4
traditional test, 2-1
ASIC testability, 4-9
use of BSDL, 5-1
ASIC verification, 7-10
use of SVF, 5-9, 6-6
automated assembly
verification, 7-26
automatic test generation
automated functional(ATG), defined, B-1
verification, 7-25
backplane multidrop
automatic test-pattern
testing, 7-17, 8-6
generation (ATPG)
illustrated, 7-20
BSDL input, 5-1
benefits, 1-5, 2-1, 2-2, 3-1,
impact on time to market,
3-2
4-3
board testing, 1-4, 7-1
in assembly verification
board validation, 6-9
flow, 7-26
CD-ROM, 9-3
SVF output, 6-6, 6-9
Index-1

vector processor
boundary-scan (continued)
verification, 7-10
circuit partitioning
video tape, 9-4
described, 2-2
illustrated, 2-3
boundary-scan cell (BSC)
cluster testing, 7-5
described, 3-2
constraints, 6-8
illustrated, 3-11
controllability andobservability, 3-2
Boundary-Scan Description
described, 3-1
Language (BSDL)
design considerations
boundary register
illustrated, 6-1
description, 5-4
design debug andcomponent conformanceverification illustrated,statement, 5-3
6-7
defined, B-1
design flow illustrated, 6-4
elements of, 5-2edge connector testing, 7-7
entity descriptions, 5-2
embedded testing, 7-21
error types, 5-5evaluation, 9-1
for ASICs, 6-5
illustrated, 3-2
for catalog devices, 5-5
in surface-mount devices,
generic parameter, 5-3
3-1
history, 5-1
interactive verification,
instruction register7-28
description, 5-3
interconnect testing, 3-1,
logical port description, 5-3
3-2
optional register
manufacturing test, 6-9
description, 5-4
memory test times, table,
pin mapping, 5-3
7-14
register accessmemory testing, 7-12
description, 5-4
microcode simulation, 7-11
scan port identification, 5-3
signature analysis, 7-6
subset of VHDL syntax,
test development, 7-10
5-1
test flow, 7-24
use statements, 5-3
testing,uses, 5-1
design overview, 6-1
validation, 5-4, 6-7
illustrated, 2-3
tutorial (Scan Educator),
9-1

Index-2

boundary-scan register(BSR)
described, 3-10
illustrated, 3-4
in BSDL, 5-4
in use
CLAMP, 3-13
EXTEST, 3-14
INTEST, 3-13
SAMPLE/PRELOAD,
3-12

cost of testing, 1-3, 2-1

Ddata sheets, for TI IEEE Std
1149.1 testability
devices, 9-3
DBM. See Digital Bus
Monitorbuilt-in self-test (BIST)
design for test
defined, B-1
additional cost amortized,
in ASICs, 4-9
2-1
initiated by IEEE Std
ASIC
1149.1, 3-13, 6-3, 7-13
fault simulation, 4-1
test functions, 6-3
testability, 4-1
circuit isolation, 2-2
bus interface, 8-3
concerns, 6-1
cost of overlooked defects,
bypass register4-7
described, 3-11
illustrated, 4-8
in usecycle-time reduction, 4-3
BYPASS, 3-12
defined, 1-1, B-1
CLAMP, 3-13
design constraints, 4-2
default, 3-9
design costs, 1-4
HIGHZ, 3-14
design flow
described, 6-1
illustrated, 6-1, 6-4, 6-7
design impact, 1-4, 4-2
developing test strategies,
CD-ROM with IEEE Std
4-8
1149.1, 9-3
economic trade-off, 4-4effect on hardware, 4-1
concurrent fault simulation,embedded test, 2-1
defined, B-1
improved debugging, 4-4
in ASICs, 4-1
controllability, 3-2, 6-2, 7-11
in the design process, 4-1
defined, B-1
introduction to, 1-1
in embedded memory,
new tool costs, 4-7
7-12

CIndex-3

design for test (continued)
partitioning penalties, 6-9
rationale, 1-2
reduced cost and higher
quality, 1-3
reduced manufacturingcost, 2-2
standard test approach,
2-2
strategy, 4-3system-level approach, 1-3
test strategy flow
illustrated, 4-11
test strategy vs. gatedensity, 4-9
with ATPG, 4-4
yield vs. devices/board, 4-6
yield vs. fault grade, 4-5

DSP, 8-1

detectable fault, defined, B-1

fault model
defined, B-2
examples, 4-1

deterministic test vectors,
defined, B-1
device identification register
described, 3-11
illustrated, 3-11
in BSDL, 5-4
in usedefault, 3-9
IDCODE, 3-14
USERCODE, 3-14
Digital Bus Monitor (DBM),
8-6

Index-4

E
Embedded Test-Bus
Controller, (eTBC), 7-21,
8-6

F
fault, defined, B-1
fault grade
defined, B-1
simulator results, 4-1

fault simulation
defined, B-2
in ASIC design, 4-1

Ggate-pin fault, defined, B-2

IEEE Std 1149.1 (continued)
internal scan, 6-3
introduction, 1-5
macro libraries, 6-5
Hierarchical Scan
obtaining specifications,
Description Language
3-15(HSDL), See also
on CD-ROM, 9-3
Boundary-Scan
optional pins, B-4
Description Language
TRST*, 3-14
bus composition, 5-8
optional registers, 3-9
defined, B-2
device identification
described, 5-6
register, 3-11
elements of, 5-6
user-defined data
entity description, 5-7
register, 3-9
generic parameter, 5-7
optional test instructions
history, 5-6
CLAMP, 3-13
logical port description, 5-7
HIGHZ, 3-14
members description, 5-8
IDCODE, 3-14
obtaining specifications,
INTEST, 3-13
5-8
RUNBIST, 3-13
path descriptions, 5-8
USERCODE, 3-14
pin mapping, 5-7
origins of, 3-1
scan port identification, 5-8
partitioned scan path, 6-8,
use statements, 5-7
8-6
uses, 5-6, 6-8
required pins, 1-5, B-4
TCK, 3-5
TDI, 3-5
TDO, 3-5
TMS, 3-5
IC test, explained, 6-6
required registers
boundary-scan register,IEEE Std 1149.1, See also
3-10
boundary scan,
bypass register, 3-11
Boundary-Scan
instruction register, 3-8
Description Language
required test instructions
architecture
BYPASS, 3-12
described, 3-3
EXTEST, 3-13
illustrated, 3-4
SAMPLE/PRELOAD,
benefits, 6-10
3-12
built-in self-test, 6-3
reuse of test vectors, 3-1,
bus master. See Test Bus
6-10
Controller

H

I

Index-5

IEEE Std 1149.1 (continued)
supporting data formats,
5-1
test data registers
described, 3-9
illustrated, 3-10
IEEE Std 1149.1-compatible
components, 8-1
IEEE Std 1149.1 (JTAG)
Boundary-Scan Logic,
8-2
bus interface, 8-3
scan support, 8-5
Universal Bus Transceiver(UBT), 8-4
in-circuit test, described, 7-1
initialization, defined, B-2
instruction register
described, 3-8
illustrated, 3-8
in BSDL, 5-3

Joint Test Action Group(continued)
introduction, 1-5

Llevel-sensitive scan design(LSSD)
defined, B-2
in ASICs, 4-10
linear feedback shift register(LFSR), defined, B-2
load fault, defined, B-2
logical redundancy, defined,
B-2
LVT Widebus, 8-2, 8-3, 8-4

Mmemory test
interconnect testing, 6-2, 6-5,
controllability, 7-12
6-9, 7-1
embedded memory, 7-12
defined, B-2
observability, 7-12
described, 3-2
illustrated, 7-2
modular testing, defined, B-2
internal scan, described, 6-3

J
Joint Test Action Group(JTAG), See also
boundary scan, IEEE Std
1149.1
Index-6

multidrop test bus, 7-19,
7-20, 8-6
multiple fault, defined, B-3

Nscan pathdescribed, 3-2
illustrated, 3-2

networking ICs, 8-1

scan-path design, defined,
B-3

node fault, defined, B-3

O
observability, 3-2, 6-2, 7-11
defined, B-3
in embedded memory,7-12
octals, bus interface, 8-3

Pparallel fault simulation,
defined, B-3
parallel signature analyzer,
defined, B-3
parametric test, defined, B-3
product summary, 8-1
propagation, defined, B-3

S
Scan Board, 9-1
Scan Educator tutorial, 9-1

Scan-Path Linker (SPL), 8-6
defined, B-3
scan-path partitioning, 6-8,
8-6
Scan-Path Selector (SPS),
8-6
defined, B-3
scan testing, defined, B-4
Serial Vector Format (SVF)
defined, B-4
described, 5-9
headers and trailers
illustrated, 5-10
history, 5-9
obtaining specifications,
5-16
offset commands, 5-11
parallel commands, 5-12
program example, 5-15
scan offsets, 5-9
state commands, 5-11
structure, 5-10
TAP state names, table,
5-13
uses, 5-9
SN74ABT8996 (ASP), Seealso Addressable Scan
Port, 7-19, 8-6

Scan Engine, 7-21

Index-7

SN74ACT8990 (TBC), Seealso Test-Bus Controller,
7-21, 8-6
SN74ACT8994 (DBM), Seealso Digital Bus Monitor,
8-6

T
TBC. See Test-Bus
Controller

test
applications
ASIC verification, 7-10
backplane multidrop
testing, 7-17
board etch/solder joint
SN74ACT8999 (SPS), Seetesting, 7-1
also Scan-Path Selector,
boundary-scan test flow,
8-6
7-24
cluster testing, 7-5
SN74LVT8980 (eTBC), Seeedge connector testing,also Embedded Test-Bus
7-7
Controller, 7-21, 8-6
embedded testing, 7-21
source fault, defined, B-4
memory testing, 7-12
costs of traditional ATE,
SPL. See Scan-Path Linker
2-1
design validation, 6-6
SPS. See Scan-Pathfault isolation, 6-6
Selector
fault simulation andgrading, 4-1
stuck closed (shorted gate)functional, at-speed, 8-6
fault, defined, B-4
IC simulation, 6-6
product test requirements,
stuck fault, defined B-4
6-2
reduced manufacturingstuck open (open gate) fault,
cost, 2-2
defined, B-4
reusing vectors, 6-10
traditional ATE
bare board test, 7-1
in-circuit test, 7-1
SN74ACT8997 (SPL), Seealso Scan-Path Linker,
6-8, 8-6

Index-8

test access port (TAP)
controller state diagram
illustrated, 3-5
defined, B-4
described, 3-3
detailed description, 3-6
in BSDL, 5-3
operation, 3-5
output control illustrated,
3-7
Test-Bus Controller (TBC),
7-17, 7-21, 8-6
test-bus evaluation report,
9-3
test-bus master. See
Test-Bus Controller
test data registers illustrated,
3-10

defined, 1-1, B-5
testability video, 9-4
time to market
impact on profitability, 1-3
introduction, 4-3
relationship to testability,
4-4
illustrated, 4-3
training products
CD-ROM, 9-3
Scan Board, 9-1
Scan Educator, 9-1
testability video, 9-4
tutorial (Scan Educator), 9-1

Utest description language(TDL), defined, B-4

undetectable fault, defined,
B-5

test generation, defined, B-5

Universal Bus Transceiver(UBT), 8-4

test pattern, defined, B-5
test pattern grading, defined,
B-5
test point insertion, defined,
B-5
test program, development
time required, table, 1-4
test vector, defined, B-5
testability, See also designfor test

unpredictable fault, defined,
B-5

V
video tape on testability, 9-4

W
Widebus, 8-2, 8-3, 8-4

Index-9