Proceedings of LINAC 2004, Lübeck, Germany

DIGITAL FEEDBACK SYSTEM FOR J-PARC LINAC RF SOURCE
S. Michizono#, S. Anami, S. Yamaguchi, KEK, Tsukuba, JapanT. Kobayashi, JAERI, Tokai, Japan
with DSPs has been developed for these requirements.
The FPGAs are in charge of fast feedback for the cavities
and the DSPs will be operated for data/program exchange
and a slow feedback system, such as tuning the cavities.
In this report, the hardware developments andperformance of the feedback system are described.

Abstract
At the proton linac of J-PARC (Japan ProtonAccelerator Research Complex), an accelerating electricfield stability of ±1% in amplitude and ±1° in phase isrequired for the RF system. In order to accomplish theserequirements, a digital feedback system is adopted forflexibility of the feedback (FB) and feedforward (FF)algorism implementation. FPGAs are used for the realtime FB system. A DSP board is also utilized for dataprocessing and communication between FPGAs and acrate control CPU (Host). The system was examined with
the SDTL cavity, and satisfied the stability specification.

FEEDBACK EQUIPMENT
The digital feedback system is installed in a compact
PCI (cPCI crate). The backplane of the cPCI crate is
specially designed so as to separate the ground line
between digital and analog boards. The digital equipment,such as the CPU, DSP (Spectrum Signal Processing Inc.
‘Barcelona’, 4xTMS320C6701) and I/O boards, arelocated on left side of the cPCI crate, and analog boards,
such as the RF&CLK (rf and clock generator) andMixer&I/Q (mixers and I/Q modulators) boards, areinstalled on the right side. The RF&CLK board createstiming clock (fTim:12 MHz, fTrig: 48MHz, fLO: 312 MHz)and RF (fRF: 324 MHz) signals synchronized with a
distributed reference signal [2]. Since the accuracy ofaround 2 ps is required especially to the LO signal (312MHz), the reference signal is planned to change from 12

INTRODUCTION
Twenty klystrons (324 MHz, 3 MW) will be installed inthe J-PARC linac. An RFQ, 3 DTLs and 16 SDTL
modules are driven by klystrons [1]. The maximum pulse
width and repetition rate are 620 µs, including the cavity
build-up time, and 50 pps, respectively. Because the rf
source should maintain the accelerating field within anamplitude stability of ±1% and phase stability of ±1°, ahighly intelligent feedback system should be constructed.
A digital feedback system using the FPGAs combined

To ADC 4
Q input
fRF

klystronI input
I/Q
modulator

To ADC 3

circulator

AD8345

cavity 1

cavity 2

FPGA 1
FF_I table

fTim

Block RAM

FFbeam_I table

I_set table
+ +

fLO

AD6644ADC

Mixer (12MHz)AD8343ADC
fLO
cPCI (Mixer & I/Q modulator board)data acquisition
status output
DSP board(Spectrum Balcelona)
TMS320C6701 x4
J1J2J3IQ

ADC1ADC2program
parameter[Pgain]LPF

IQ++-+

IQ

IQ
calibration
a -bb a 2+

Block RAM+abcd++[Igain][Igain]+Loop offset

FB offcalibration
a -bb a 1

[Pgain]

FB on
FB on

FB offfTrig

limit++Q+ +Q_set table

PEM DN4
FF_Q table
J5

FFbeam_Q table

cPCI

I/O
cPCI

___________________________________________

#cPCI

PLC

Figure 1: Schematic diagram of the digital feedback system.

shinichiro.michizono@kek.jp

1DACAD9764

PEM FPGA board (Xilinx Vertex-E XCV600E x2)

CPUDACI

Proceedings of LINAC 2004, Lübeck, Germany
MHz to 312 MHz.
An FPGA (Vertex-E XCV600E, which will be replaced
by XC2V2000 in this year) sends I and Q components toan I/Q modulator (AD8345) through 14-bit DACs
(AD9764). The modified signal drives a klystron. An
active mixer (AD8343) receives the rf signal from thecavity and down-converts it to an IF signal (12 MHz).
The FPGA obtains I/Q components by measuring the IF
signals at a 48-MHz clock through a 14-bit ADC(AD6644). One of the FPGAs works for the rf signals
from cavities, and another serves as a monitor of the rf
signals from cavity input ports, which is used for tuner
control. Figure 1 shows a schematic diagram of the digital
FB system. Simple PI control is adopted for cavity control.
The FF signal is added as beam compensation. The digital
FB system is controlled through a PLC [3].

8000

Amplitude

6000
4000
20000050100
Time [µs]150200Figure 3: Step response measured by the digital system.
8000
7000

The system configuration is shown in Figure 2. Prior toa high-power test using a SDTL, a low-level FB wastested using a simulation cavity [4] with a delay line.
After checking the performance with the simulation cavity,

6000
Set value

FEEDBACK PERFORMANCE

cavitycPCI
324 MHz

Klystron0phaseshifterAmp.

cont onRF on
Beam on200300Figure 4: Set-values used for the feedback.
rf power. The parameters of the set-values are theamplitude, phase, overdrive and Q value for build-up(Qset). In this test, these parameters were 6,000, 0° , 5%
and 40,000, respectively. This combination of amplitude
and phase corresponds to 6,000 and 0 in the I and Qcomponents, respectively.
Figure 5 shows the I/Q components during FB (withoutFF). Proportional and integral gains of 10 and 15/1000 at
a 48-MHz clock were adopted in this experiment. The
variations of both components at flattop were less than 10.
The corresponding errors of the amplitude and phase in
the pulse were ±0.08% and ±0.04°, respectively. The
stabilities were also evaluated using an external monitor.
5phasemonitorwave
detector

Attenuator

Ext.Trig.

Figure 2: Schematic diagram of the LLRF system
configuration.
a high-power test was carried out. Figure 3 shows the step
response obtained by the digital system without FB. The
measured loaded Q value from this measurement wasabout 22,000.
Set-values of the FB are an exponential pattern, as
shown in Figure 4, for a fast build-up time with a limited

6010

Q component

6000

I/Q components

6005

I component

Time [µs]mixer

Mixer in(324MHz)
~0dBm

6000
5995
5990
200

100

simulation cavity

100m cableoscilloscope

NIMtriggerunita)

3000

0Limit
Amp.

12MHz

4000

1000

AM/PM

I/Q out(324MHz)~0dBm
Attenuator

5000

2000

klystron/cavity conditioningcPCI LLRF system
LLRF estimation by simulation cavity
SGoverdrive

4000
2000

600

-5-100400

00500-15
200

400

600

Time [ µs]Time [ µs]Time [ µs]Figure 5: Measured I/Q components during rf operation. Fullscale I/Q:center, expansion I: left, expansion Q:right. No feedforward was used. The proportional and integral gains for the feedback are 10 and 15/1000 at a 48MHz clock, respectively.

2Proceedings of LINAC 2004, Lübeck, Germany
0.2

0-0.05+1 degree

Amplitude+1%

phase error [deg.]

Phase

Amplitude error [%]

0.1

0-0.1

-0.1
-0.15
-0.2
-0.25

-0.2

0

Applied high-voltage (klystron)(3% sag)

51015

05

Time [hours]

1015Time [hours]

Figure 8: Trend-graphs of the amplitude and phasestabilities.

SUMMARY
A digital FB system used at the rf sources in the JPARC linac has been developed. The requirements for theLLRF system are stabilities of ±1% in amplitude and ±1°in phase. The system was examined by a SDTL cavity,and show good stabilities of ±0.08% in amplitude and±0.04° in phase. The stabilities remained for more than 15hours at ±0.2% in amplitude and ±0.25° in phase.

Figure 6: Waveforms of the amplitude and phaseobtained by external monitors.

Figure 6 shows the amplitude and phase signals obtainedwith a wavedetector and a mixer, which corresponds toerrors of ±0.2% in amplitude and ±0.2° in phase. The
measured data with the external monitor were about 4times larger, probably due to the ambiguity of themeasurement system. Further development of the externalmeasurement system is required for a more preciseevaluation.
The measured values were compared with thecalculated values based on the state equations. Theses
showed good agreements, including the overshooting(Figure 7). This indicates that the system is well-modeledin the simulation, and that simulations will be helpful fordeveloping new FB algorisms.
The stability of the system was also examined duringlong-time operation. The results are shown in Figure 8.
Stabilities of ±0.2% in amplitude and ±0.25° in phasewere achieved for more than 17 hours.

REFERENCES[1] S.Yamaguchi et al., “Overview of The RF System for
The JAERI/KEK High-Intensity Proton Linac”,
LINAC2002, Gyeongju, Aug. 2002, p.452.
[2] T.Kobayashi et al., “RF Reference Distribution
System for J-PARC Linac”, this conference.
[3] S. Anami et al., “Control of the Low Level RF
System for the J-Parc Linac”, this conference.
[4] S. Michizono et al., “Digital RF Control System for
400-MeV Proton Linac of JAERI/KEK Joint Project”
LINAC2002, Gyeongju,Aug. 2002, p.184.

SDTL 6000
70006050

6000
6000

4000

I component

I component

5000
measured
calculated
set

3000
2000

measured
calculated
set

5950

1000
0
50

100

150

200

5900
160

250

180

200

220240Time [ µs]Time [ µs]Figure 7: Comparison with the measured and calculated I-component. These show good agreements, including overshoot.

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