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AND90012/D
Key Steps to Design a
Multimode PFC Stage Using
the NCP1618A
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APPLICATION NOTE
critical or discontinuous conduction mode) as a function of
the inductor current cycle duration for an optimized
operation over the line/load range. In light load, frequency
foldback is engaged to further maximize the efficiency andthe circuit can be driven in soft−SKIP mode where the output
voltage swings between two levels to minimize the standby
losses. In addition, valley turn on of the MOSFET isprovided in both the critical and discontinuous conduction
modes. Note that the NCP1618A multimode algorithm
closely controls the switching frequency in all
circumstances (65 kHz in continuous conduction mode withjittering and between 25 kHz and 130 kHz in the othermodes), hence easing EMI filtering.

This paper describes the key steps and provides the mainequations useful to rapidly design a multimode PFC stage
driven by the NCP1618A. The process is illustrated by apractical 500 W, universal−mains application:• Maximum output power: 500 W• Input voltage range: from 90 Vrms to 265 Vrms
• Regulation output voltage: 390 V• CCM frequency: 65 kHz• Clamp Frequency: 130 kHz
Introduction
Forward or half−bridge converters take a significant
advantage of a narrow input voltage range. In suchapplications, the PFC stage is wished to start first and to keepon as long as the power supply is plugged in. Optimally, thedownstream converter should turn on when the output of the
PFC stage is nominal. The NCP1618A is an innovative
controller optimized for these applications. It features ahigh−voltage start−up current source to promptlypre−charge the VCC capacitor and a “pfcOK” pin to enable
the downstream converter when the PFC stage is ready for
operation. In addition, its soft−skip cycle mode minimizes
the PFC stage losses in very−light−load conditions.
Furthermore, the NCP1618A multimode engine leads the
PFC boost pre−converter to transition from one conduction
mode to another depending on the line/load conditions for an
optimized efficiency over the whole operating range.
Housed in a SO−9 package, the circuit further incorporates
the features necessary for robust and compact PFC stages,
with a minimal number of external components. NCP1618A
functions make it the ideal candidate in systems wherecost−effectiveness, reliability, low stand−by power,high−level efficiency over the load range and near−unity
power factor are key parameters:High−Voltage Capability

The circuit features a high−voltage (HV) pin that monitors
the input voltage. The sensed information is the input for theline−range, line−sag and brownout detection circuitries. In
addition, an internal high−voltage start−up circuit draws
current from the HV pin to charge up the VCC capacitor when
the PFC stage is plugged in. Note that the start−up current
source is reduced when the VCC voltage is below VCC(inhibit)(0.8 V typically) to prevent the circuit from overheating if
the VCC pin happens to accidentally be grounded.
Nevertheless a 100 mF VCC capacitor can be charged up toits start level within about 200 ms.
Fast Line / Load Transient Compensation

The NCP1618A incorporates a digital transconductanceerror amplifier and a digital compensation setting the low
bandwidth necessary for proper line current shaping.
However, the NCP1618A dramatically narrows the output
voltage range. First, the controller detects over−voltage(OVP) situations and interrupts the power delivery as longas the output voltage exceeds this OVP threshold. Also, thedynamic response enhancer (DRE) drastically speeds−up
the regulation loop when the output voltage is 4.5% below
its desired level. As a matter of fact, a PFC stage provides thedownstream converter with a very narrow voltage range.

Multimode Capability

The NCP1618A is a multimode controller. As detailed in
the next section, it selects the operating mode (continuous,© Semiconductor Components Industries, LLC, 2020

December, 2020 − Rev. 1

1

Publication Order Number:AND90012/D

AND90012/D
A “pfcOK” Signal

The circuit detects whether the PFC stage is in steady state or on the contrary, in a start−up or fault condition. In the first case,the “pfcOK” pin (pin 2) sources a current proportional to the feedback pin voltage and is grounded otherwise. When in highstate, the external resistor to be placed between the pfcOK pin and ground, forms a voltage representative of the output voltage.
Thus, the pfcOK signal provides the downstream converter with both an enable and a feedforward signal. On the other hand,the pfcOK pin turns low in the event of a major fault like a brown−out situation or the bulk voltage drop to too low a level (seeBUV protection) so that, finally, the downstream converter can be optimally designed for the narrow voltage provided by the
PFC stage when the pfcOK pin is high.
Safety Protections

The NCP1618A permanently monitors the input and output voltages, the input current and the die temperature to protect
the system from possible over−stresses and make the PFC stage extremely robust and reliable. In addition to the aforementioned
OVP protection, one can list:• Over−Current and Overstress Protections: the circuit permanently senses the total input current and prevents it fromexceeding the programmed current limit. In addition, the circuit enters a low duty−cycle operation mode in an
overstress situation, that is, when the current reaches 150% of the current limit as this can happen if the inductor
saturates• In−rush detection: when in frequency−clamped critical conduction mode, the NCP1618A prevents the power switchesfrom turning on in the presence of the large in−rush currents which typically take place when the power supply isplugged in• Under−Voltage Protection: this feature prevents operation in case of a failure in the feedback monitoring network (e.g.,
accidental grounding of the FB pin)
• Bulk Under−Voltage Detection (BUV): The BUV function is implemented to prevent the downstream converter fromoperating when the buck voltage is too low. Practically, a BUV situation is detected when the feedback pin voltage
drops below 1.8 V typically• Line−Sag and Brown−Out Detection: the circuit prevents CCM operation and gradually reduces power delivery if too
low a line magnitude is detected (line sag) to protect the PFC stage from the excessive stress possibly occurring in suchconditions. If the mains interruption is long enough (650 ms typically), a brown−out fault is detected and pfcOK isgrounded to disable the downstream converter• Thermal Shutdown: the circuit stops pulsing when its junction temperature exceeds 145 °C typically and resumes
operation once it drops below about 110°C (35°C hysteresis)

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AND90012/D
MULTIMODE CAPABILITY
The NCP1618A naturally transitions from one conduction mode to another depending on the conditions so that the operation
is optimized over the line/load range:• The circuit operates in critical conduction mode (CrM) by default. CrM is an efficient and popular mode of operation
where the inductor current ramps up to twice the line instantaneous current, ramps down to zero then immediately
ramps positive again. The input current ripple is large (2 times the line instantaneous current) but the MOSFET turn−on
losses are minimized. This is because, the current being at a null when the MOSFET closes, there are no
reverse−recovery losses of the boost diode to worry about but also, because valley turn−on of the MOSFET can beobtained. Zero voltage switching is even possible when the input voltage is less than 50% of the output voltage• The CrM switching frequency is by essence variable and tends to increase near the line zero crossing and moregenerally at light load. The NCP1618A prevents the switching frequency from exceeding a maximum level (130 kHz
typically) by generating a dead−time. This is the so−called frequency−clamped critical conduction mode (FCCrM).
When the frequency is clamped, the PFC stage operates in discontinuous conduction mode (DCM) while keeping
properly shaping the line current by appropriately compensating for dead−times. The system automatically transitions
between DCM and CrM with no discontinuity in operation and with no power factor degradation• In addition, when the load further decreases, the frequency clamp level decays, thus, lowering the DCM frequency(frequency foldback). This method is an effective solution to maintain the low−power range efficiency at a high level
while otherwise it would sag because of the switching losses dramatic impact. However, the minimum frequency isfirmly maintained above 25 kHz to stay outside the audible range• In heavy−load and low−line conditions, the input current becomes high and the inductor current ripple, ΔIL, can take toolarge a value, leading to an increased inductor size, excessive conduction losses and significant EMI filtering pains, if
the PFC remains operated in CrM. In this case, the NCP1618A can enter the continuous conduction mode (CCM),
which is more suitable in heavy load conditions• In very light−load conditions, the circuit can be operated in a soft−SKIP mode where the output voltage swings between
103% and 98% of its nominal level. During the idle phase for which the bulk capacitor discharges, the NCP1618A
consumption is minimized (250 mA). This mode is externally set using the pfcOK or VM pins

Figure 1. The Mode is Selected Based on the Current Cycle Duration(Tclamp is the DCM Period Clamp, TCCM is the CCM Switching Period)

Figure 1 provides a simplified description of how the conduction mode is selected. This is based on the duration of theinductor current cycle.

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3

AND90012/D• The circuit tends to operate in critical conduction mode as long as the current switching cycle is short enough not toenter the CCM mode. However, if the current cycle happens to be shorter than the frequency−clamp period (Tclamp
which is about 7.7 ms typically leading to a 130 kHz DCM frequency), the circuit delays the next cycle until the Tclamp
time has elapsed. Thus, the circuit enters DCM operation. The switching cycle is actually a bit longer than Tclamp since
the next cycle is further delayed until the next valley is detected (left of Figure 1). Doing so, valley turn−on is obtained
for minimized turn−on losses• This is the frequency−Clamped Critical conduction Mode (FCCrM) where transitions between CrM and DCM aremanaged cycle−by−cycle so that the circuit can transition from DCM to CrM and vice versa within a half−line cycle.
Practically, DCM is more likely to occur near the line zero crossing and CrM at the top of the sinusoid. As the load
further decays, current cycles become too short to cause CrM cycles and DCM operation is obtained over the entire line
sinusoid. At very light load, the DCM period clamp is increased (a longer minimum switching period is forced causing
frequency foldback)• In heavy−load conditions, the circuit enters CCM when the current cycle is longer than 112% of the CCM period (about
17 ms). The circuit cannot leave CCM on a cycle−by−cycle basis. It permanently operates in CCM until no current cycle
longer than the CCM period is detected for a blanking time of several line cycles. In other words, the circuit remains in
CCM over the entire half−line cycle until the load is decreased enough to recover the FCCrM mode
The inductor value sets the power above which the circuit will enter CCM. Equation 1 gives the CrM switching frequency
at the top of the line sinusoid:f SW

vin (t )= 2 ⋅Vin ,rms=(

Vin ,rms 2 ⋅ Vout − 2 ⋅ Vin ,rms
2 ⋅ L ⋅ Pin ,avg ⋅ Vout)(eq. 1)

We can then compute L leading the switching frequency (at the top of the line sinusoid) to become as low as the CCM one(fCCM ) when the power exceeds the wished level for CCM entering (Pin,transition ). Practically, about 89% of fCCM is actually
to be targeted since the NCP1618A implements the hysteresis necessary to avoid repeated and unwanted transitions between
modes:

L=(

Vin ,rms 2 ⋅ Vout − 2 ⋅ Vin ,rms)

2 ⋅ 89% ⋅ fCCM ⋅ Pin,transition ⋅ Vout(eq. 2)As an example, if we target Pin,transition = 275 W at low line (90 V), fCCM being 65 kHz, a 175 mH inductor is to be chosen.
It comes from this that at low line (90 Vrms) and with a 175 mH inductor, the system will operate in FCCrM for powers below
275 W and in CCM for powers above 275 W. Also, whatever the full load is, the maximum input current ripple to be filteredby the EMI filter is the current ripple obtained at this FCCrM−to−CCM power threshold. In other words, the inductor value
can be selected so that the circuit enters CCM when the FCCrM current ripple gets too high for optimal operation.
Selecting the Power Threshold for FCCrM to CCM Transition
The power for transition must be considered at the lowest−line level of the application. This threshold (Pin,transition )LL isgenerally set in the range 300 W, that is, to a power level above which CCM is considered as the most appropriate conduction
mode. However, the ratio (Pin,transition )LL over (Pin,avg )max must not be too low. First, a very deep CCM operation would leadto too large an inductor. Second, if too low, the control signal range may not be sufficient to provide the full power. Practically,(Pin,transition )LL over (Pin,avg )max must be set to 20% or above in a wide−mains application. More flexibility is possible in a
reduced line range. In any cases, the computation of the VM pin resistor which sets the CCM gain enables to check that the
selection is correct. We will see that Eq. 27 gives the maximum VM pin resistance enabling to provide the full power (RM,max ).
Eq. 29 provides the VM pin resistance for constant−power transition (RM,CP ). (RM,CP ) must be lower than (RM,max ) for fullpower delivery. Even, for the sake of margin, (RM,CP ) should be set lower than (80%*RM,max ). Thus, if (RM,CP ) is higher than
(80%*RM,max ), it is recommended to increase (Pin,transition )LL .

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AND90012/D
DESIGN STEPSKey Specifications

We must first identify the main specification points of the PFC stage:• fline : Line frequency. 50 Hz /60 Hz applications are targeted. Practically, they are often specified in a range of 47−63 Hz
and for calculations such as hold−up time, one has to factor in the lowest specified value.

• (Vin,rms )LL : Lowest level of the line voltage. This is the minimum line rms voltage for which the PFC stage must operate
nominally. Such a level is usually 10−12% below the minimum typical voltage which could be 100 V in many
countries. We will take: (Vin,rms ) LL = 90 V . The circuit is however able to operate down to the thresholds of the
NCP1618A brown−out and line sag protections:− (Vin,rms ) = VBO ( start ) / 2 ≅ 78 V
boH

− (Vin,rms )boL= VBO ( stop ) / 2 = 71 V

− Where VBO(start) is the line−sag and BO upper threshold (111 V typically − see data sheet) and VBO(stop) is the line sag
and BO lower threshold (100 V typically − see data sheet)(• Vin,rms ) HL : Highest rms level for the line voltage. It is usually 10% above the maximum typical voltage (240 V in many
countries). We will use: (Vin,rms )HL = 264 V .

• Vout ,nom : Nominal output voltage. This is the regulation level for the PFC output voltage (also designated as bulk
voltage). Vout ,nom must be higher than ( 2 ⋅ (Vline,rms ) HL ) . 390 V is our target value.

• ( ΔVout ) pk − pk : Peak−to−peak output voltage ripple. This parameter is often specified in percentage of output voltage. It

must be selected equal or lower than 8% to avoid triggering the over−voltage protection (softOVP) and/or the dynamic
response enhancer (DRE) in normal operation.
• tHOLD −UP : Hold−up time. This parameter specifies the amount of time the output will remain valid during a line dropout
event. One line cycle is typically specified. This requirement requires knowing the minimum voltage on the PFC stage
output necessary for the proper operation in your application (Vout ,min ) . No hold−up time will be considered here.
• Pout : Output power. This is the power consumed by the PFC load.

• Pout, max : Maximum output power. This is the maximum output power level, that is, 500 W in our application.
• (Pin, avg)max : Maximum input power. This is the maximum power which can be absorbed from the mains in normal

operation. This level is typically obtained at full load, lowest line. As a starting point, we will assume an efficiency of500

92.5% which leads to: (Pin,avg )max = 92.5% ≅ 540 W• (Pin, transition)LL: Input power above which the circuit enters the CCM mode. This power threshold is considered at thelowest line of the application. We will set it to 300 W. Note that typically, it should be set to 20% of (Pin,avg)max orabove. See the “CCM Duty Ratio control” section for more details.

We can now compute the value of the components shown in the generic application schematic of Figure 2.

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5AND90012/D

Figure 2. NCP1618A Generic Application Schematic

Inductor Selection
The inductance is the parameter which sets the power level above which the PFC stage enters the CCM mode of operation.
Practically, The PFC stage will enter CCM when the CrM frequency will drop to (65 kHz / 112%), that is, 58 kHz.
The CrM witching frequency (at the top of the sinusoid) can be approximated as follows [1]:f SW =(

Vin ,rms 2 ⋅ Vout − 2 ⋅ Vin ,rms
2 ⋅ L ⋅ Pin ,avg ⋅ Vout)(eq. 3)

We will target CCM for powers higher than 275 W at the lowest line (90 V rms). In other words, the CrM frequency @ 90 V
rms, 275 W must be 58 kHz. This criterion leads to the following L expression:L=) ⋅ (V − 2 ⋅ (V ) )2 ⋅ ( f ) ⋅ (P
) ⋅V

(V

2

in , rms LL
SW

in , rms LL

out

in ,transition LLth(eq. 4)

out

Where (fSW )th is the 58 kHz frequency threshold, (Vin,rms)LL is the lowest−line rms voltage and (Pin,transition )LL is the input
average power above which the circuit must enter the CCM mode at (Vin,rms = (Vin,rms)LL ).
It comes:L=(

902 ⋅ 390 − 2 ⋅ 90)≅ 175 μ H

2 ⋅ 58 ⋅103 ⋅ 300 ⋅ 390(eq. 5)One can show that in CCM, the current peak−to−peak ripple at the top of the sinusoid, is given by:

V(ΔI L )pp = out− 2 ⋅ Vin , rms
L ⋅ f CCM

2 ⋅ Vin ,rms

⋅

Vout

(eq. 6)The inductor peak current will hence be:

I L , pk =2 ⋅ Pin,avg
Vin,rms+(ΔI L )pp

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62(eq. 7)

AND90012/D
Combining equations 7 and 6 leads to:

2 ⋅ Pin , avg

I L , pk =Vin , rms

⎛ V − 2 ⋅ Vin , rms
2 ⋅ Vin , rms ⎞+ ⎢ out⋅⎟⎢ 2 ⋅ L ⋅ f CCM
⎟
Vout
⎝
⎠

(eq. 8)Computing at the lowest line level (90 V rms), the maximum inductor current is obtained:(I )L , pk max

2 ⋅ (Pin ,avg )

=

(V

)

max

in , rms LL⎛ Vout − 2 ⋅ (Vin ,rms )2 ⋅ (Vin ,rms )LL ⎞
LL
⎟
+⎢
⋅
⎢
⎟
2 ⋅ L ⋅ fCCM
Vout
⎝
⎠

(eq. 9)In our application, the maximum peak value and the lowest−line peak−to−peak ripple ( ( ΔI L ) pp − LL ) of the inductor current
will hence be:390 − 2 ⋅ 90
2 ⋅ 90⋅≅ 7.5 A
−6
3
175 ⋅10 ⋅ 65 ⋅10390(eq. 10)2 ⋅ 90 ⎞2 ⋅ 540 ⎛ 390 − 2 ⋅ 90⋅
+ ⎢⎢⎟ ≅ 12.2 A
3−6390 ⎟⎠
90⎝ 2 ⋅175 ⋅10 ⋅ 65 ⋅10(eq. 11)(ΔI L )pp − LL =(I )L , pk max=

Finally, the following expression gives an estimate of the inductor rms current:222⎛ 16 2 ⋅ (V
⎛ (Pin , avg ) ⎞ ⎛ (Vin , rms )3 ⋅ (Vin , rms )LL ⎞ ⎞in , rms )LL
max ⎟
LL
⎢
⎢
⎟ ⎟ ≅ 6 .2 A
⎢
+
⋅ 1−
+
(I L,rms )max = ⎢ V⎟ ⎢⎢ 12 ⋅ (L ⋅ f CCM )2 ⎢3π ⋅ Vout
2 ⋅ Vout 2 ⎟ ⎟⎟(in , rms )LL
⎝
⎠ ⎝
⎝
⎠⎠

(eq. 12)

PQ3230 inductor ref. 750317557 from Wurth Elektronik is selected. It exhibits an auxiliary winding (naux/nP = 10%) which
is used to feed the NCP1618A VCC voltage and to provide the zero current detection signal necessary for valley turn on in bothcritical and discontinuous conduction modes.
Note that if the PFC stage is designed so that the circuit permanently remains in frequency−clamped critical conduction mode
(no CCM operation over the load/line range), the following equations would provide the electrical specification of the inductor:

I L ,max =2 2 ⋅ (Pin ,avg )

(V

)

max

(eq. 13)in , rms LL(ΔI L )pp −90V =(I

2 2 ⋅ (Pin ,avg )(eq. 14)

I L ,max(eq. 15)(Vin,rms )LL)

L , rms max

=

6

max

This would happen for L lower than the value by returned by Eq.4 if the transition power (Pin,transition ) was set above themaximum input power, that is, in our application, for L < 90 mH.
Current Sensing and CCM Control
The NCP1618A is designed to monitor a negative voltage proportional to the inductor current (IL ). As portrayed by Figure 3,
a current sense resistor (Rsense ) is inserted in the return path to generate a negative voltage (VRsense ) proportional to IL . The
circuit uses VRsense to detect when IL exceeds its maximum permissible level. Practically, the circuit incorporates an operational
amplifier that sources the current necessary to maintain the CS pin voltage at a null. By inserting a resistor ROCP between the
CS pin and Rsense , we adjust the current that is sourced by the CS pin (ICS ) as follows:
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7AND90012/D− (Rsense ⋅ I L ) + (ROCP ⋅ ICS ) = 0(eq. 16)

Which leads to:
I CS =

RsenseIL
ROCP(eq. 17)

In other words, the CS pin current (ICS ) is proportional to the inductor current. The following three protecting functions
compare ICS to internal current references for:• Over current protection: if ICS gets higher than internal threshold IILIMIT1 (200 mA typically), the MOSFET
immediately turns off. This is the traditional cycle−by−cycle current limitation.
• Overstress protection: if ICS exceeds a second internal threshold IILIMIT2 which is 50% higher than IILIMIT1 , the circuit
detects an abnormal condition. In this case, the circuit disables the CCM mode (if set) and stops operation for 800 ms.
This protection can trip if the inductor happens to saturate or if its auxiliary winding is accidently shorted. It may also
help protect the circuit if the MOSFET turns on during an in−rush sequence.
• In−rush current detection. When in frequency−clamped critical conduction mode, the circuit cannot restart a new cycle
until ICS has dropped below Iinrush (10 mA typically that is 5% of the maximum current threshold IILIMIT1 ). The inrush
current detector stabilizes operation by providing a rough second ZCD signal, when (during the start−up phase and atvery high line for instance), the auxiliary winding voltage is too low to provide an accurate ZCD signal. It also protects
the circuit by preventing operation during the inrush phase (1).
Internal current ICS is also used in CCM to control the power−switch duty−ratio.

Figure 3. Current Sense Block

As we have two external components to set the current limit (ROCP and Rsense ), the current sense resistor can be optimized
to have the best trade−off between losses and noise immunity.
The following equations give an estimate of the Rsense maximum losses:
PRsense = Rsense ⋅ (I L , rms )max
2

(eq. 18)

1. If an inrush sequence happens when the circuit operates, the overstress protection will trip (provided that the inrush current exceeds theoverstress level) and stop operation for 800 ms. At the end of this delay, the inrush protection prevents operation until the inrush event
is finished.

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AND90012/D
One can choose Rsense as a function of its relative impact on the PFC stage efficiency at low line and full power. If α is therelative percentage of the power that can be consumed by Rsense , this criterion leads to:(eq. 19)

PRsense ≤ α ⋅ Pin ,maxFinally:
Rsense ≤α ⋅ Pin ,max(I(eq. 20))2

L , rms max

In our application, we choose (a = 0.25 %),Rsense ≤(eq. 21)

0.25% ⋅ 540≅ 35 mW
6 .2 2

In practice, we will use Rsense = 30 mW and hence, since the maximum inductor current is 12.2 A (see inductor computation):
ROCP =

Rsense ⋅ I L ,max

(I)

ILIMIT 1( LL ) min=

30 ⋅ 10 −3 ⋅ 12.2
≅ 1 .9 k Ω
190 ⋅ 10 −6(eq. 22)Since the CS pin is designed to source a current, it is not recommended to add a capacitor directly on the pin for filtering.
Instead, the network of Figure 4 is actually used where the resistor ROCP is split into 2 resistors ROCP1 and ROCP2 and a capacitor
CCS is placed between the ROCP1 and ROCP2 common node and ground. To offer some margin both ROCP1 and ROCP2 are set
to 1 kΩ (ROCP = ROCP1 + ROCP1 = 2 kΩ) and a 220 pF capacitor is implemented for CCS .

Diodes Bridge+

Vin
NCP1618

IN

1−

CS pin

ROCP1

ROCP2

Rsense

10

2
3

8

4

7

5

6

CCS

Figure 4. Filtering the CS Pin

Important notes:− The current sense resistor sees the startup inrush current and must be able to sustain it in the worse conditions of theapplication. As shown by Figure 1, a diode may have to be placed across Rsense to divert a large part of the hugein−rush current which can take place during start−up or faulty phases. This diode is actually optional but should be
added if the in−rush stress can damage Rsense or if the Rsense voltage may become large enough to cause ICS to exceed
the 2 mA maximum rating. The forward voltage of this diode must be high enough not to clamp the Rsense voltage to
too low a value which may prevent the NCP1618A from detecting overcurrent or overstress situations. Practically, it
should be higher than ROCP times the overstress threshold (IILIMIT2 which is 330 mA maximum). In our application,
ROCP being 2 kW, the diode forward voltage must be higher than 660 mV.
− If a filtering capacitor (CCS of Figure 4) is implemented, its negative terminal should be connected to the circuit
ground rather than to the power ground− The NCP1618A senses the CS pin impedance before starting operation (or before restarting operation after aninterruption) and prevents MOSFET switching until it is high enough. The NCP1618A redoes it at the end of any
switching cycle during which the CS pin current (ICS ) does not exceed the inrush level (5% of the overcurrent
threshold) while the line instantaneous voltage is higher than its brown−out threshold. This impedance test is
performed to detect and protect the PFC stage if the CS pin is accidentally grounded. Not to improperly detect a CS
fault, ROCP or (ROCP1 + ROCP2 ) should be higher than 1.5 k

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9AND90012/D• CCM Duty Ratio control
For CCM control, the NCP1618A re−uses the proven “predictive method” scheme implemented in the NCP1653 and NCP1654
CCM PFC controllers. In other words, it directly computes the power switch on−time as a function of the inductor current.
Practically, as shown by Figure 5, the ICS current is modulated by the control signal and sourced by the VM pin to build the CCM
current information. The VM pin signal is:
VM = 0.4 ⋅ RM ⋅VRAMP , pk
VREGUL⋅ I CS(eq. 23)

Where VRAMP,pk and RM respectively are the peak value of the CCM PWM ramp and the VM pin resistor value. The CCM
regulation voltage (VREGUL ) is proportional to the regulation control signal provided by the internal regulation block(VCONTROL ) as follows for line feedforward:− (VCONTROL ) in low−line conditions (2)− (VCONTROL / 4) in high−line conditions (2)As detailed in the data sheet [2], this leads to the following input power expressions:− Low−line conditions:

2.5 ⋅ ROCP ⋅ Vin , rms 2 VCONTROL⋅RM ⋅ RsenseVout(eq. 24)0.625 ⋅ ROCP ⋅ Vin , rms 2 VCONTROL⋅RM ⋅ RsenseVout(eq. 25)

Pin , avg =− High−line conditions:

Pin , avg =CCM Oscillator Ramp

Generationof the VM pincurrent

VRAMP , pk
RAM P

Clock

CLOCK
S

VM
RM

CM

I M = 0.4 x I CS x

VRAMP , pk
VREGULvM (t)

Q

vRAMP (t)

+

DRV

Q

+

VRAMP , pk

R−

Figure 5. CCM Duty Ratio Control

2. The circuit detects low−line conditions if the HV pin voltage remains below 222 V for 25 ms or more (typical values – see data sheet)and it remains in low−line conditions until the HV pin voltage exceeds 236 V typically. At that moment, it enters the high−line mode.

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10AND90012/D
As highlighted by above equations, resistor RM adjusts the PFC stage power capability, leading to the two following RM
selection criteria:()− This resistance must be low enough for full−power delivery: Pin , avg VCONTROL ,max >Pout ,maxη

whatever the line

magnitude is. Due to the CCM gain change in high−line conditions, we need to check that the full power can bedelivered at the lowest rms voltage of both the low−line and high−line ranges:

max

⎛
⎢
⎝

⎛ Vlineselect ( LL )⎢V
2.5 ⋅ ROCP VCONTROL ,max ( in ,rms )LL 0.625 ⋅ ROCP VCONTROL ,max ⎝2⋅⋅,
RM ≤ RM ,max = MIN
R
V
R
V
P
P
( in,avg )( in,avg )
sense
out
sense
out
2

2

(eq. 26)

max

Where Vlineselect(LL) is the lowest line peak voltage for high−line operation (Vlineselect(LL) is the threshold for low−linedetection − 222 V typically). Note that if the line lowest level of the application was within the high−line range( 2 (V ) ≥ V
in , rms LL

lineselect ( LL )), the max value for RM simplifies as follows:

0.625 ⋅ ROCP VCONTROL ,max (Vin ,rms )LL⋅
RM ,max =RsenseVout(Pin,avg )2(eq. 27)max− This resistance should preferably be selected so that there is no power discontinuity (constant−power transition) when
the PFC stage transitions between FCCrM and CCM. In low−line conditions, VCONTROL is abruptly discharged to(VCONTROL / 4) at the FCCrM to CCM transition (and charged to 4×VCONTROL at the CCM to FCCrM transition), in
order to provide a large CCM VCONTROL range. Due to this VCONTROL division by four at low line and the change ingain for feed−forward at high line (division by four), the constant−power constraint leads to one single equation
where the left side is the instantaneous power delivered in FCCrM and the right side the instantaneous power
delivered in CCM just after the transition:

vin2 (t )V
R⋅ CONTROL = 2.5 ⋅ OCP
RM
2 ⋅ L ⋅ fCCM VCONTROL ,max

VCONTROL
vin2 (t )4⋅
RsenseVout(eq. 28)

From Eq. 28, we can deduce the following equation which provides the RM resistance for constant−power transition:

RM ,CP = 1.25 ⋅ L ⋅ fCCM ⋅ROCP VCONTROL ,max⋅RsenseVout(eq. 29)

In our application, the maximum RM value to meet the full−power delivery constraint (RM,max ) is:⎛ 2.5 ⋅ 2 ⋅103 3.75 902 0.625 ⋅ 2 ⋅103 3.75 157 2 ⎞,RM ,max = MIN ⎢⋅⋅⎟ ≅ 18.3 k Ω
0.03 390540
0.03 390 ⎠⎝ 540(eq. 30)

The RM value to meet the constant−power transition criterion is:

RM ,CP = 1.25 ⋅175 ⋅10−6 ⋅ 65 ⋅103 ⋅2 ⋅103 3.75⋅
≅ 9.1 k Ω
30 ⋅10−3 390(eq. 31)

As aforementioned, for the sake of margin, we want (RM,CP ) to be 20% below (RM,max ). This is the case here()

(RM,CP <80%×RM,max ). Our (Pin,transition )LL selection is hence correct since with RM = RM ,CP = 9.1 k Ω , the PFC stage canprovide the full power (since (RM,CP ) is less than (80%×M,max )) and can smoothly transition between the FCCrM and CCM
modes.
NOTE: Note that if (RM,CP ) was higher than (80%×RM,max ), we should increase (Pin,transition )LL to be able to provide thefull power and ensure a constant−power transition.
Also note that if (RM,CP ) provides the optimal value for smooth transition, a power step in the range of ±50% whentransitioning can be managed by the circuit without a risk of erratic operation (repeated transitions between the two modes).
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11

AND90012/D
No need hence to look for the exact computed value (as long as it remains below (80%×RM,max )). In addition, a different
resistance can be wished to meet some application constraints. For instance, you may want to reduce the CCM gain (using RM
closer RM,max ) to reduce the gap between the power capability of the PFC stage and the power actually needed in your(application. To that extend, using RM = 0.8 ⋅ RM ,max ⋅ RM ,CP) can be a good option too.

In our case, we select (RM = 7.8 k Ω ) .
A capacitor CM is to be placed across the VM pin to filter out the switching ripple. The time constant (RM ×CM ) should beselected in the range of 50 ms or 100 ms, that is, sufficiently large to filter the switching ripple but low enough not to distort
the low frequency component (that is the 100 or 120 Hz rectified sinusoid). Thus:CM ≅75 ⋅ 10 −6
RM(eq. 32)

In our application, this criterion leads to the following CM value: 9 nF. We take the closest standard value: CM = 10 nF.
As discussed in [3], dividing the VM resistors in two resistors as shown by Figure 2, is recommended to clean the operation
at very high line where the VM voltage is close to the threshold of the internal comparator for MOSFET turn off (3.75 V
typically). If not, due to the VM resistors inertia, the circuit may skip cycles at the top of the sinusoid.
Practically, RM1 and RM2 are selected so that the sum of them equals the computed RM value and RM2 is chosen in the rangeof 15% of RM . CM1 is computed similarly to CM as follows:
CM 1 ≅

75 ⋅ 10 −6
RM 1(eq. 33)

A small capacitor CM2 is generally recommended to filter out possible surrounding noise but it is low enough to keep alow−inertia signal across RM2.
In our case, we finally opt for:− RM1 = 6.8 kΩ
− RM2 = 1 kΩ
− CM1 = 10 nF− CM2 not connected
NOTE: The RM resistance must be selected higher than 4.5 kΩ. If not, the circuit may not be able to charge the VM pin to
SKIP threshold (VSKIP(th)).
Power Components• Diodes bridge
The diodes bridge is mainly selected based on the voltage it must sustain and on the power it must dissipate. [5] shows thata good approximate value of the maximum power loss is given by:(Pout )max

4 2
ηPbridge =⋅V f ⋅
πVin, rms

(

)LL

500
0
≅ 1.8 ⋅ V f ⋅ .92 ≅ 11⋅ V f
90(eq. 34)

Assuming a 0.85−V forward voltage per diode (Vf = 0.85 V), the bridge approximately dissipates 9.4 W. Diodes bridge
GSIB1580 from Vishay is implemented. A 4.5°C/W heatsink (SK481−50 from Fischer Elektronik) limits the temperature rise
to about 45°.

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12

AND90012/D• Boost diodeAs discussed in [5], the boost diode selection is critical in CCM applications. The diode current at its turn−off being non−zero,
there is significant reverse recovery phenomenon that leads to dissipation in the diode and in the MOSFET. For best efficiency
ratios, SiC diodes are to be preferred even if its higher forward voltage offsets some of the gains of reduced switching losses.
In this application, SiC diode FFSPF0865 from ON Semiconductor is selected.
The output diode conduction losses can be roughly approximated to (Iout,max × Vf ), where Iout,max is the load maximum
current and Vf the diode forward voltage. The maximum output current being nearly 1.3 A (500 W / 390 V), the diodeconduction losses are roughly estimated in the range of 2.6 W (assuming Vf = 2.0 V – max instantaneous forward voltage @125°C and 8 A specified in the FFSPF0865 data sheet).
A more precise computation could however consist of considering the resistive contribution in the total losses:
PD = (VT 0 ⋅ I LOAD ) + (rD ⋅ I D2 , rms )(eq. 35)

where VT0 is the threshold voltage, rD is the dynamic resistance and ID,rms is the diode rms current which can be computed
using:I D ( rms ) ≅ I L, rms

8 2 ⋅ Vin, rms(eq. 36)

3π ⋅ Vout• Power MOSFETs
The MOSFET is selected based on the peak voltage stress (Vout,max + margin) and on the maximum rms current flowing throughit ((IQ(rms))max) which can be approximated using the following equation:(

8 2 ⋅ Vin, rms)(IQ,rms )max ≅ (I L,rms )max ⋅ 1 − 3π ⋅ Vout ,nom LL(eq. 37)⋅ 90≅ 5 .3 A(IQ,rms )max ≅ 6.2 ⋅ 1 − 83π 2⋅ 390(eq. 38)

In our application, Eq. 37 leads to:

Two FCPF165N65 MOSFETs from ON Semiconductor are placed in parallel. Each of them exhibits a maximum
drain−to−source on−resistance (rDS(on)) of 165 mW @ 25°C. Considering a 100% rDS(on) increase at high temperature, themaximum conduction losses are given by:(Pcond )max ≅(200% ⋅ rDS (on )2)25_C ⋅ 5.32 ≅ 2 ⋅ 0.165 ⋅ 5.32 ≅ 4.6 W(eq. 39)2

As aforementioned, the MOSFETs switching losses are hard to predict. They highly depend on the diode choice, on the
MOSFET drive speed and on the possible presence of some snubbering circuitry. Hence, their prediction is a tough andinaccurate exercise that will not be made in this paper. Instead, we will place the MOSFETs and the boost diode on the sameheat−sink and consider that as a rule of the thumb, the total power to be dissipated by the heatsink is 4% of the output power(3).
NOTE: Note that to further improve the efficiency, the MOSFET opening can be accelerated using the schematic of
Figure 6, where Q1 , a small pnp transistor, amplifies the MOSFET turn off gate current.

3. We rather consider 6% of the output power if the diode bridge is placed on the heatsink. In a single−mains application, this figure could
be halved.

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13

AND90012/D

DRV

D2
1N4148

R2

R1
M1
R10
10k

Q1

Figure 6. Q1 Speeds Up the MOSFET Turn Off• Heatsinks
Like in [4], as a rule of thumb, one can estimate that the total power to be dissipated by heatsinks is around:− 6% of the output power in wide−mains applications− 3% of the output power in single−mains applications
Such a losses budget must be pessimistic. If experimental tests show that they are worse, the design and/or the components
selection must be tweaked if it wished to meet a high efficiency.
No fan is implemented in our 500 W application. It is cooled down by the heatsinks as follows:− The diodes bridge is fitted on a 4.5°C/W heatsink (SK481−50 from Fischer Elektronik) to limit its temperature rise toabout 45°C (about 9.4 W are dissipated)− The two MOSFETs and the boost diodes share a second heat−sink. Assuming that as a rule of thumb, it will have todissipate 4% of Pout (4% × 500 W ≅ 20 W), a 2.8°C/W heat−sink (ref. SK481−50 from Fischer Elektronik) is
implemented which limits the temperature rise to about 56 °C compared to the ambient temperature• Bulk capacitor design
In addition to the rated voltage, the output capacitor is generally designed considering the 3 following factors:− The maximum permissible low−frequency ripple of the output voltage. The input current and voltage being bothsinusoidal, PFC stages deliver a squared sinusoidal power that matches the load power demand in average only. As aconsequence, the output voltage exhibits a low frequency ripple (e.g., 120 Hz in USA) that is inherent to the PFC
function− The rms current flowing through the bulk capacitor. Based on this computation, one must estimate the maximal
permissible ESR for an acceptable heating− The hold−up time specification. The hold−up time is the time for which the power supply must keep providing thefull power while the line is gone. The duration of the mains interruption (hold−up time) is generally in the range of
10 or 20 ms
The output voltage peak−to−peak ripple is given by:
ΔVout ( p − p ) =Pout
2π ⋅ fline ⋅ Cbulk ⋅ Vout , nom(eq. 40)

This ripple must keep lower than ±4% of the output voltage (8% peak−to−peak) not to trigger the DRE and OVP functions
in normal operation. Thus, we can derive the capacitance the bulk capacitor must exceed not to exhibit too large alow−frequency ripple:
Cbulk ≥

Pout ,max

2π ⋅ ( fline )min ⋅ 8% ⋅ Vout , nom 2

www.onsemi.com
14(eq. 41)

AND90012/D
In our application, taking into account the line frequency minimum value (47 Hz), this leads to:
Cbulk ≥

500
2π ⋅ 47 ⋅ 8% ⋅ 3902

≅ 139 μF

(eq. 42)

The following equation gives an approximate value of the capacitor rms current:⎛
2 8 2 ⋅ Vin, rms ⎞ ⎛ Pout ⎞⎟−⎢I C ( rms ) ≅ ⎢ I L, rms ⋅⎟⎢3π ⋅ Vout ⎟⎠ ⎢⎝ Vout , nom ⎟⎠
⎝

(

)

2

(eq. 43)

We can derive from Eq. 43 the following estimate of the bulk capacitor maximum rms current:2⎛
2 8 2 ⋅ 90 ⎞ ⎛ 500 ⎞I C ( rms )max ≅ ⎢ (6.2 ) ⋅−⎢≅ 3.0 A⎟⎢3π ⋅ 390 ⎠⎟ ⎝ 390 ⎟⎠⎝(eq. 44)

Finally the following expression expresses the minimum bulk capacitance necessary to meet a specified hold−up time
(thold−up ), where Vout,min is the minimum bulk voltage for proper operation of the downstream converter:
Cbulk ≥

2 ⋅ Pout ,max ⋅ thold −up
Vout 2 − Vout ,min 2(eq. 45)

The hold−time being not considered here, a 330 mF / 450 V capacitor (861141486022 from Wurth Elektronik) is chosen tosatisfy the two other above conditions.
VCC and Sequencing Management
Forward or half−bridge converters take a significant advantage of a narrow input voltage range. In such applications, the PFC
stage is expected to start first and to keep on as long as the power supply is powered, the downstream converter being disabled
when the output of the PFC stage is nominal. The NCP1618A is specially designed for these applications:− It incorporates a start−up current source providing a fast charge of the VCC capacitor, thus, easing the PFC stage startof operation− It features a “pfcOK” pin to enable/disable the downstream converter. Practically, it is in high state when the PFC
stage is in nominal state and low otherwise (fault or start−up condition). In particular, the pfcOK pin is grounded if aline brown−out or a bulk under−voltage is detected• Input voltage sensing
The NCP1618A monitors the HV pin for line sag and brownout protections and for line range detection. The brownout andline−sag circuitry detects too low line levels and the line range detector determines the presence of either 110 V or 220 V ac
mains. Depending on the detected input voltage range device parameters are internally adjusted to optimize the system
performance. As shown by Figure 7, line and neutral can be diode “ORed” before connecting to the HV pin (Figure 7a) case)or the HV pin can be simply connected to the rectified voltage (Figure 7b) case). The diodes prevent the pin voltage from going
below ground.

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15

AND90012/D
Ac lineAc lineEMI
Filter

FB

1

10

Vm 3
ZCD

FB

Vcc

pfcOK 2CS

EMI
Filter

HV

1

10

HV

Vcc

pfcOK 2
Vm 3

8

4

7

DRV

CS

5

GND
6

ZCD

a) The line terminals are sensed

8

DRV

4

7

5

GND
6

b) The input voltage is sensed

Figure 7. High−Voltage Input Connection

A resistor in series with the diodes is recommended to limit the current during transient events. A low value resistor (5.6 kΩ
or less) is generally used to reduce the voltage drop and thus allow more accurate measurement of the input voltage when thestart−up circuit is enabled. Also, this resistor must be able to sustain the power dissipation the startup current source causes
across it.
Computing the VCC Capacitor Charge Time
The start−up current sourced by the VCC pin (Istart2) is 12 mA typically. As detailed in the data sheet, the start−up current
is limited to Istart1 (1 mA typically) when the VCC voltage is below VCC(inhibit) (0.8 V typically). This feature prevents the circuitfrom overheating if the VCC pin is accidentally grounded.
Thus, the following equation provides the VCC capacitor charge time:tch =CVCC ⋅ VCC ( inhibit )I start1+

CVCC ⋅ (VCC ( on ) − VCC ( inhibit ) )I start 2(eq. 46)

In our case, using the typical values for VCC(on),VCC(inhibit), Istart1 and Istart2, it comes for a 100 mF VCC capacitance:
tch =

−6
100 ⋅ 10−6 ⋅ 0.8 100 ⋅ 10 ⋅ (17 − 0.8 )+≅ 215 ms
−3
10
12 ⋅ 10−3(eq. 47)

Where:− VCC(on) is the typical value of the VCC start−up threshold (17 V)− VCC(inhibit) is the typical value of the VCC threshold below which the start−up current is reduced (0.8 V)
Using the maximum values for VCC(inhibit) (1.2 V) and VCC(on) (18.2 V) and the minimum values for Istart1 (0.7 mA) andIstart2 (6.5 mA), we obtain the following conservative, very worst−case charge time:
tchWorstCase=−6
100 ⋅ 10 −6 ⋅ 1.2 100 ⋅ 10 ⋅ (18.2 − 1.2 )+≅ 313 ms
−3
0.7 ⋅ 1012 ⋅ 10 −3(eq. 48)• pfcOK
As aforementioned, the pfcOK pin is designed to control the operation of the downstream converter. It is in high state when
the PFC stage is in nominal operation. On the contrary, the pfcOK pin is grounded when the PFC stage is in start−up phase orin a fault condition. Using the pfcOK signal to enable/disable it, the downstream converter can be optimally designed for the
narrow voltage range nominally provided by the PFC stage in normal operation.
When in high state, the pfcOK pin sources a current proportional to the feedback voltage (k × VFB), where k is 10 mA/V
typically. In other words, the pfcOK pin typically sources 25 mA when the FB voltage is 2.5 V (regulation level). An external
resistor is to be placed between the pfcOK and GND pins to obtain a voltage VpfcOK which is proportional to the bulk voltage
and can serve as a feedforward signal for the downstream converter.

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16

AND90012/D
In our application, a 56 kΩ resistor is used so that the pfcOK voltage is (56 ⋅ 103 × 25 ⋅ 10−6 = 1.4 V) when the output voltage
is nominal. A capacitor should be placed between the pfcOK and ground pins for decoupling. The pin should not be too muchfiltered not to degrade the feedforward function. A good trade−off generally consists of setting the filter corner frequency about
5 times higher than the line frequency:
1
10π ⋅ R pf cOK ⋅ ( f line )max

(eq. 49)

1≅ 9 nF10π ⋅ 56 ⋅ 103 ⋅ 63

(eq. 50)

C pf cOK ≤In our case, Eq. 49 leads to:
Cp f cOK ≤A 10 nF ceramic capacitor is placed between the pfcOK and GND pins for decoupling.

• Feedback network
The output voltage of the PFC stage is externally scaled−down by a resistors divider (RFB1 and RFB2 of Figure 2) andmonitored by the feed−back input (pin1). The bias current of the feedback pin is minimized (less than 500 nA) to allow theuse of a high−impedance feed−back network. It is neglected in below calculations. The feedback voltage must equate theinternal reference voltage (VREF = 2.5 V) when Vout is nominal. In other words:
RFB 2⋅ Vout , nom = VREF
RFB1 + RFB 2(eq. 51)

RFB1 Vout , nom
=
−1
RFB 2
VREF

(eq. 52)

Or:

Another constraint on the feedback resistors relates to the power RFB1 and RFB2 dissipate as they are biased by the Vouthigh−voltage rail (in the range of 390 V typically). If the impedance (RFB1 + RFB2) is low, RFB1 and RFB2 can easily consume
several hundreds of milliwatts and degrade the standby performance.
In steady−state, the feedback voltage is in the range of the 2.5 V regulation reference voltage (VREF ). The nominal feedback
bias current can hence be defined as a function of feedback bottom resistor (RFB2) as follows:
I FB =VREF
RFB 2(eq. 53)

Trade−off between losses and noise immunity dictates the choice of this resistor. Resistors up to 56 kΩ (IFB ≅ 50 mA)
generally give good results. Higher values can be considered if allowed by the board PCB layout and if the impedance remains
compatible which the 250 nA sink current (500 nA max. on the −40°C to 125°C temperature range) built−in to ground thefeedback pin and disable the driver if the pin is accidentally open. If IFB is set below 50 mA, the regulation level may besignificantly impacted by the 250 nA sink current. In our application, we target a bias current in the range of 100 mA which
generally gives a good trade−off between losses and noise immunity. This criterion leads to:
RFB 2 =

VREF
= 25 k Ω
100 μA(eq. 54)(RFB2 = 27 kW is finally selected. Following Eq. 52, RFB1 is given by:⎛ Vout , nom⎞
RFB1 = RFB 2 ⋅ ⎢⎢− 1⎟⎟
⎝ VREF⎠(eq. 55)⎛ 390 ⎞
RFB1 = 27 k Ω ⋅ ⎢− 1⎟ = 4185 k Ω⎝ 2.5⎠(eq. 56)

We target a 390 V regulation level, hence:

For safety reasons, several resistors should be placed in series instead of a single RFB1 resistor. In our application, we choosea (1800 kW + 1800 kW + 560 kW) network. This selection together with (RFB2 = 27 kW) leads to:
Vout , nom =RFB1 + RFB 2
1800 + 1800 + 560 + 27
⋅ VREF =⋅ 2.5 V ≅ 388 V
RFB 2
27

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17(eq. 57)

AND90012/D
Zero Current Detection (ZCD)
The NCP1618A optimizes the efficiency by turning on the MOSFET at the very valley when operating in critical anddiscontinuous conduction modes. For this purpose, the circuit is designed to monitor the voltage of a small winding taken offof the boost inductor. This auxiliary winding (called the “zero current detector” or ZCD winding) gives a scaled version of
the inductor voltage which is easily usable by the controller. The PFC stage being a boost converter, this auxiliary winding
voltage provides:⎛ N AUX⎞⋅ vin (t )⎟ during the MOSFET conduction time
N
⎝ P
⎠

− −⎢

⎛ N AUX

− ⎢ N
⎝

P

⎞

(V − v (t ))⎟ during the demagnetization time. This voltage used to detect the zero current detection can be
out

in

⎠

small when the input voltage is nearly the output voltage.
− A voltage oscillating around zero during dead−times
The NCP1618A embeds an internal comparator to monitor such a signal. Practically, during the off−time, it compares the
ZCD pin voltage to an upper threshold VZCDH (1 V typically) and to a lower threshold VZCDL (0.5 V typically) to detect fallingedges of the ZCD signal, these events being indicative of the end of the demagnetization phase and/or of the valleys of the
MOSFET Drain−source voltage.
Several options are possible for an accurate ZCD and OVP2 as discussed in [7]. Among them, the circuitry of Figure 8 isrecommended when the direct sensing of the output voltage rail may be too dissipative to meet standby low power⎛ N AUX⎞⋅ vin (t )⎟ during the on−time. If C1 is⎝ NP⎠

requirements. In this circuit, R1 being small (e.g. 22 W), capacitor C1 is charged to ⎢lightly loaded, its voltage remains almost unchanged during the off−time and thus, the D1 cathode voltage becomes⎛ ⎛ N AUX
⎞ ⎛N
⎞⎞
⎛
⎞
Vout − vin (t ))⎟ + ⎢ AUX ⋅ vin (t )⎟ ⎟ , that is, ⎢ N AUX ⋅ Vout ⎟ during the demagnetization time. This voltage is stored and clamped
(
⎢⎢ ⎢
⎟
N
N
N
P
P
⎝
⎠
⎝
⎠
⎝
⎠
⎝ P
⎠
⎛
⎞
N
by D7, C2 so that the C2 voltage is (N × VOUT) where ⎢ N = AUX ⎟ . C2 delays the OVP2 activation. This is particularly usefulN
P ⎠⎝when the system restarts after an interruption. In this case, it prevents that an incorrect initial value of the C2 voltage causes
OVP2 spurious tripping. Note that as the rule of thumb, C2 can be selected 10 times higher than C1 (C2 ≅ 10 × C1). Note thatcapacitor C2 can also be referenced to VCC instead of ground so that a voltage for proper ZCD immediately exists wheneverthe circuit enters operation.
This circuitry hence provides a voltage representative of the output is obtained for a redundant over−voltage protection. As
detailed in [8], a good starting point for the time constants could be in the following range for a 50− or 60−Hz line:
R1 ⋅ C1 ≅ 100 ns(eq. 58)(R2 + R 3)⋅ C1 ≅ 600 μs(eq. 59)

Diode D2 ensures that the ZCD/OVP2 pin gets below the ZCD internal threshold, when the auxiliary winding drops to zero.
NOTE: Time constant (R1×C1) can actually be increased to 500 ns or 1 ms. This can help avoid charging C1 on spikes
and limit the impact of the input voltage ripple on the generated image of the output voltage. R1 must however
remain low enough to properly force the ZCD pin voltage below VZCD(th)L (0.5 V typically) when the auxiliary
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AND90012/D

R1

C1

N*Vout

D7

D1

+
−
S

C2

Q

VZCD(th)H/ VZCD(th)L

R2

D2

fsw,min

Auxiliary
winding

DT

S
Q
Q

Q

ramp

reset
D3

Ics < Iinrush

RR

ZCD / OVP2
DRV

R3

C3

OVP2
+

800−μs interruption

−

VOVP2
Latch−off

VFB <VDRE−L

Figure 8. Zero Current Detection Block

As shown by Figure 8, the ZCD signal is compared to VOVP2 (4 V typically) for OVP2 detection (4). The ratio (R2/R3) will
set the OVP2 threshold. During the demagnetization phase, the ZCD voltage is:
VZCD =⎞⎞
R3 ⎛ ⎛ N AUX⋅ Vout ⎟ − VD3 ⎟⎢⎢ ⎢⎟R2 + R3 ⎝ ⎝ N P⎠⎠(eq. 60)

Thus, if Vout,OVP2 is the output voltage level above which an OVP2 fault is detected, replacing VZCD by the OVP2 threshold
VOVP2, we obtain:
R2 + R3 ⎛ N AUX Vout , OVP 2 ⎞ VD3
=⎢
⋅
⎟−
R3
VOVP 2 ⎠ VOVP 2⎝ NP(eq. 61)

The R3 value is generally selected equal to 10 kΩ.
R3 ≅ 10 k Ω(eq. 62)

⎛⎛ N
⎞
V
⎞ VD3
⎛ ⎛ 1 440 ⎞ 0.6 ⎞R2 ≅ R3 ⋅ ⎢ ⎢ AUX ⋅ out , OVP 2 ⎟ −− 1⎟ ≅ 10 ⋅ 103 ⋅ ⎢ ⎢ ⋅− 1⎟ ≅ 98.5 kW⎟−⎢ N⎟
VOVP 2 ⎠ VOVP 2⎝ ⎝ 10 4 ⎠ 4
⎠
⎝⎝ P
⎠

(eq. 63)If we target 440 V for Vout,OVP2, it comes:

Finally, using 59 , we can compute C1:C1 ≅600 ⋅ 10−6600 ⋅ 10−6=
≅ 5.5 nF
R2 + R3
100 ⋅ 103 + 10 ⋅ 103(eq. 64)

A 4.7 nF capacitor was used.

4. (This function provides a redundant OVP protection for safety. If VZCD exceeds VOVP2, the PFC stage stops operating for 800 µs. In addition,
if when an OVP2 fault is detected, the dynamic response enhancer is engaged (indicating an undershoot being detected by the feedbackpin), the circuit detects that one of the two networks for output voltage sensing is wrong. As a consequence, the circuit latches off. See
Figure 8.

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19

AND90012/D
Layout and Noise Immunity Considerations
The NCP1618A is not particularly sensitive to noise. However, usual layout rules for power supply apply. Among them, let
us remind the following ones:− The loop area of the power train must be minimized− Star configuration for the power ground that provides the current return path
− Star configuration for the circuit ground− The circuit ground and the power ground should be connected by one single path
− This path should preferably connect the circuit ground to the power ground at a place that is very near the grounded
terminal of the current sense resistor (RSENSE ).
− A 100 nF or 220 nF ceramic capacitor should be placed between the circuit VCC and GND pins, with a minimized
connection length− If a filtering capacitor (CCS of Figure 4) is implemented for current sensing, its negative terminal should be connectedto the circuit ground rather than to the power ground− The components (resistors or capacitors) that program the circuit operation must be placed as close as possible to thepin they drive.
− As aforementioned, it is furthermore recommended to filter the signal applied to the FB, CS, pfcOK, VM and ZCD
pins to protect them from possible surrounding noise. It must not be excessive however not to distort the voltage
sensed by these pins. See the corresponding sections for more details.

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AND90012/D
APPLICATION SCHEMATICS• Power Section
Some common PFC stage elements not discussed in the application note since nonspecific to the controller like the inrush
current management or a circuitry for X2 capacitors discharge are not included in this schematic.
Vaux

R1
10

C 11
10n

D8
1N 4148

VCC
VCC

D Z1
MMSZ 24T1

U1
GSIB1580

C2470nF
Type = X2

PGND

D2
1N 5406

C 19
220μF/35V

PGND
Vout

+

C 3a
0.68 μ F / 450 V

IN

C 3b
0.68 μ F / 450 V

.
.

L1

−

PGND

VCC

C 5x
1 nF
Type = Y2

Vaux

R2
10

C7
220nF

C6
1 nF
Type = Y2

D1
FFSPF0865

D9
1N 4148

R5
100k

D5
1N 4148

D6
1N 4148

C 10
10n

C4
330μF / 450 V

R4
100k

VZCDinD 12
1N 4148

CM1

R8
2.2

Q4
MMBT 589LT1G

R 9x
2.2
Q1a
FC PF165N65S3L1

Q1b
FC PF165N65S3L1

R 11
27k

R 12
27k

L2
56 μ H
R 15
10

C1
470nF
Type = X2

R 14
30m / 3 W

D3
1N 5406

DRV

R 10
27k

GND

V1
TVR 10471

PGND
I sense

R

L
F1

Earth

N

L

N

90-265 Vrms

Figure 9. Power Section of the Application SchematicV ZCDinN

V out

I se nse

D11
1N4007

R18
0

L

R20
0
R21
560k

R22
1800k

D10
1N4007

R23
1800k

FB
C14
2.2 nF

R26
910

R19
5.6k

R24
27k

pfcOK
C15
10nF

R25
56k

R27
1k

Vm
CS
ZCD

1

10

2
3

8

4

7

5

6

HV

Vcc

Vcc

D15
1N4148

C22
220nF

DRV
GND

C16
220pF
R28
C18 1k
10nF

R29
6.8k

GND
DRV

Vcc
V CC

Figure 10. Control Section of the Application Schematic

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21

C23
22pF

R30
10k

AND90012/D
Conclusion

This application note proposes a systematic process for the eased design of an efficient multimode PFC stage. Morespecifically, this paper provides the key equations and design criteria. This dimensioning process is illustrated by the practicalexample of the 500 W, wide−mains evaluation board [9]. Note that a design spreadsheet [10] automates the dimensioning
process.
References[1] Laszlo Huber, Brian Irving and Milan M. Jovanovic, “Line Current Distortions of DCM/CCM Boundary BoostPFC Converter”, APEC2008[2] NC1618 Data Sheet, http://www.onsemi.com/pub/Collateral/NCP1618A−D.PDF[3] Patrick Wang, “Four Key Steps to Design a Continuous Conduction Mode PFC Using the NCP1654”, Applicationnote AND8322, https://www.onsemi.com/pub/Collateral/AND8322−D.PDF[4] Joel Turchi, “Four Key Steps to Design a Continuous Conduction Mode PFC Using the NCP1653”, Applicationnote AND8184, https://www.onsemi.com/pub/Collateral/AND8184−D.PDF[5] Joel Turchi, “A High−Efficiency, 300−W Bridgeless PFC Stage”, Application Note AND8481,
http://www.onsemi.com/pub/Collateral/AND8481−D.PDF[6] Peter Haaf and Jon Harper, “Understanding Diode Reverse Recovery and its Effect on Switching Losses”, Fairchild
Power Seminar 2007,[7] Joel Turchi, “NCP1618A Tips and Tricks”, Application note AND90011,
https://www.onsemi.com/pub/Collateral/AND90011−D.PDF[8] José Capilla, “How to Use Auxiliary Winding Voltage for Biasing the NCP1602 CSZCD Pin”, Application note
AND9455/D, https://www.onsemi.com/pub/Collateral/AND9455−D.PDF[9] Joel Turchi, NCP1618A Evaluation Board User’s Manual,
http://www.onsemi.com/pub_link/Collateral/EVBUM2049−D.PDF[10] NCP1618A Design & Development Tool,
http://www.onsemi.com/PowerSolutions/supportDoc.do?type=tools&rpn=NCP1618A

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