APPLICATION NOTE
www.onsemi.com

Key Steps to Design A Compact, High-Efficiency
PFC Stage Using NCP1623A
AND90156/D• Low VCC startup threshold:

Description

This paper describes the key steps to rapidly design a
CrM/DCM PFC stage driven by the NCP1623. The process
is illustrated in a practical 100−W, universal mains
application:• Maximum Output Power: 100 W• Rms Line Voltage Range: from 90 V to 264 V• Regulation output voltage:♦ 250 V in low line (115−V mains)♦ 390 V in high line (230−V mains)

NCP1623A is designed to start up when its VCC voltage
exceeds 10.5 V typically, making it ideal in applications
where the controller is fed by an external power source(from an auxiliary power supply or from a downstream
converter). Its maximum start−up level (11.25 V) is set
low enough to be powered from traditional 12−V rails.
After start−up, the high VCC maximum rating allows alarge operating range from 9.5 V up to 30 V, thus easing
the circuit feeding.
• Fast Line / Load Transient Compensation:
Since the regulation loop bandwidth of PFC stages must
be low, abrupt changes in the load or input voltage (e.g.
at start−up) may cause excessive over− or
under−voltages. The over−voltage protection interrupts
the power delivery when the output voltage is excessive.
The circuit dramatically speeds up the regulation loop
when the output voltage goes below the low detect
threshold (dynamic response enhancer − DRE). Thisfunction is enabled only after the PFC stage has started up
to allow normal soft−start operation to occur.
• Safety Protections:
The system permanently monitors the input and output
voltages, the MOSFET current and the die temperature toprotect the system from possible over−stress making the
PFC stage extremely robust and reliable. In addition to the
OVP protection, the following methods of protection areprovided:♦ Maximum Current Limit: The circuit senses the
MOSFET current and turns it off if the sensed current
exceeds the set current limit. In addition, the circuit
enters a low duty−cycle operation mode when thecurrent reaches 150% of the current limit as a result of
an inductor saturation or a short of the bypass diode.
♦ Under−Voltage Protection: This circuit turns off when
the feedback pin voltage (VFB) drops below 300 mV
and remains off until VFB exceeds 530 mV. When thefollower boost is enabled at low−line, FB pin sources
25 uA current (IFB(LL)) to regulate lowered output
voltage and UVP hysteretic thresholds are increased to
1.2/1.3 V. This feature protects the PFC stage if the acline is too low at startup or if there is a failure in the
feedback network (e.g., accidental short−to−groundfailure of the feedback pin).

Introduction

There’re several options of the NCP1623. Thisapplication note focuses on the A version (NCP1623A)
which mainly differs from the other versions in the follower
boost capability.
Housed in either SOIC−8 or TSOP−6 packages, theNCP1623A is an extremely compact PFC controller
designed to optimize the efficiency of your PFC stage
throughout the load range. It also incorporates protection
features for a rugged operation. More generally, NCP1623A
is ideal in systems where cost−effectiveness, reliability, highpower−factor and efficiency ratios are key requirements:• Valley Synchronized Frequency Fold−back:
NCP1623A classically operates in Critical conduction
Mode (CrM) until the power drops below a thresholdlevel. At that moment, the PFC stage enters the
Discontinuous Conduction Mode (DCM) with adead−time which prolongs as the load further decays(frequency foldback). This novel technique also provides
stable valley turn−on for a maximized efficiency. In
addition, the minimum frequency clamp (33 kHz
typically) prevents audible frequencies and the on−time ismodulated to ensure near−unity power factor in both CrM
and DCM operations.
• Compactness:
NCP1623A features the CS/ZCD multifunctional pin
based on a novel technique which provides the input
signals for an enhanced control and a large number ofprotections in a small TSOP6 (or SOIC8) package withfew external components. In addition, the NCP1623A
forces a lower output regulation level in low−line
conditions to maximize the PFC stage efficiency andreduce its size. This 2−level Follower Boost techniquebest fits for applications where the downstream converter(like a flyback power supply) can withstand input voltage
variations in a cost−effective and efficient manner.
© Semiconductor Components Industries, LLC, 2022

August, 2023 − Rev. 2

1

Publication Order Number:AND90156/D

AND90156/D♦ Redundant over−voltage protection (OVP2): CS/ZCD

troubles. In particular, adjacent pins of controllers can beshorted, grounded or badly connected. It is often requiredthat such open/short situations do not cause fire, smoke
nor loud noise. The NCP1623A integrates enhanced
functions that help address the requirement, for instance,
in case of an improper pin connection (including GND)
or of a short of the boost or bypass diode.
Compared to the TSOP−6 version, the SOIC−8 option
further features the sleep mode controlled by the DIS pin. A
high level or open circuit on this pin disables the controller
and reduces ICC bias current to less than 20 mA typically.
This function helps meet the most severe standby power
requirements.

multi−functional pin is used to detect excessive output
voltage levels and prevent a destructive output voltage
runaway if the feedback network happens to be wrong(incorrect resistors value, aging effects...)♦ Thermal Shutdown: An internal thermal circuitry
disables the gate drive when the junction temperature
exceeds 150°C (typically). The circuit resumes
operation once the temperature drops below
approximately 100°C (50°C hysteresis).
• Eased Manufacturing and Safety Testing:Elements of the PFC stage can be accidently shorted,
badly soldered or damaged as a result of manufacturing or
handling incidents, excessive operating stress or other
L BST

D BST

L
EMI
Filter

V AUX

C IN

C BULK

Load

N
R FB1
CP
VCTRL

FB

1

6

C Z RZ

GND
2

NCP1623TSOP6

CS/ZCD
3

VCC
5

R FB2

VEXT

C FB

V DS
DRV
4

RCS2
R SENSENCP1623

VDS

R CS1

SOIC8

Option 1: Drain ZCD sensing

RCS1

5

DIS

PFC
ENALBE
SIGNALVAUX
C AUX R AUX

C DIS

D AUX

opto
Option 2: Auxiliary−winding ZCD sensing

Figure 1. System Board Schematic

www.onsemi.com
2

Disable circuit example

AND90156/D
STEP 1: DEFINE KEY SPECIFICATIONS• Line frequency, fline :50 Hz /60 Hz applications are targeted. Practically, they
are often specified in a range of 47 − 63 Hz. For
calculations such as hold−up time, one has to factor in thelowest value specified.
• The lowest line voltage, (V line,rms) LL:
This is the minimum rms input voltage for which the PFC
stage must operate. Such a level is usually 10 − 12% below
the minimum typical voltage which could be 100 V inmany countries. We will take: (V line,rms) LL + 90V.

STEP 2: POWER STAGE DESIGNIn heavy load conditions, the NCP1623A operates in
Critical conduction Mode (CrM). Hence, the inductor, thebulk capacitor and the power silicon devices are
dimensioned as usually done with any other CrM PFC. This
chapter does not detail this process, but simply highlights
key points.
PFC Inductor

The on−time of the circuit is internally limited. The power
the PFC stage can deliver, depends on the inductor since L
will determine the current rise for a given on−time. Morespecifically, the following equation gives the power
capability of the PFC stage:• The highest line voltage, (V line,rms) HL:

This is the maximum input rms voltage. It is usually 10%
above the maximum typical voltage (240 V in many
countries). We select: (V line,rms) HL + 264V.

ǒPin,avgǓ

• Nominal voltage, Vout,nom :HLǓ• Output voltage at low line, Vout,LL :Lv

The NCP1623A follower boost function provides thecapability to select a lower regulation level at low line fora size and efficiency optimization of the PFC stage. It is
generally set just above the high−line detection threshold.
250 V is our target value.
• Peak−to−peak output voltage ripple, (dVout )pk−pk :This parameter is often specified in percentage of output
voltage. It must be selected equal or lower than 6% VFB
peak−to−peak ripple to avoid triggering the Dynamic
Response Enhancer (DRE) in normal operation.
• Hold−up time, tHOLD−UP :This parameter specifies the amount of time the output
will remain valid during line drop−out. One line cycle istypically specified. This requirement requires knowing
the minimum voltage on the PFC stage output necessary
for the proper operation in your application (Vout,min ). We
have assumed (Vout,min = 180 V) is high enough to provide
the downstream converter with a sufficient input voltage.
• Output power, Pout :This is the power consumed by the PFC load.
• Maximum output power, Pout,max :This is the maximum output power level, that is, 150 W
in our application.
• Maximum input power, (P in,avg) max :This is the maximum power that can be absorbed from themains in normal operation. This level is obtained at fullload, low line. Assuming an efficiency of 95% in these
conditions, we will use:ǒPin,avgǓ

max

+

100
^ 105 W95%

V line,rms

22L@ T on,max(eq. 2)The smaller the inductor, the higher the PFC stage power
capability. Hence, L must be low enough so that the fullpower can be provided at the lowest line level:

This is the high−line regulation level. Vout,nom must be
higher than Ǹ2 @ (V line,rms) . 390 V is our target value.

ǒ

max

+

ǒV line,rmsǓ

2LL

2 @ ǒP in,avgǓ

@ T on,max(eq. 3)max

Like in traditional CrM applications, the following
equations give the other parameters of importance:• Maximum peak current:

ǒIL,pkǓ

max+ 2 Ǹ2ǒPin,avgǓ

max

ǒV line,rmsǓ

(eq. 4)
LL• Maximum rms current:
ǒLL,pkǓ
ǒIL,rmsǓ

max

+

max

Ǹ6

(eq. 5)In our application, the inductor must then meet thefollowing requirements:Lv

90 2@ 10.8 m ^ 417 mH
2 @ 105105+ 2 Ǹ2^ 3.3 A90
ǒIL,rmsǓ + 3.3 ^ 1.35 AmaxǸ6ǒIL,pkǓ

max(eq. 6)The minimum value for Ton,max (the typical value being
12.5 ms) is 10.8 ms which is used in equation 6 since this is
the worst case when calculating L. It is recommended to
select an inductor value that is at least 25% less than that
returned by equation 6 for a healthy margin. A 200−mH
inductor is selected for system compactness. It consists of a
10:1 auxiliary winding for zero current detection. One cannote that the switching frequency in CrM operation depends
on the inductor value:(eq. 1)f sw +

www.onsemi.com
3

V line(t) 2 @ ǒV out * V line(t)Ǔ
4 @ P in,avg @ V out @ L(eq. 7)

AND90156/D
The boost diode is the source of the following conduction
losses: IOUT · Vf , where IOUT is the load current and Vf thediode forward voltage. The maximum output current being
0.4 A at low line (when the regulation level is set to 250 V),
the diode conduction loss is in the range of 0.4 W (assuming
Vf = 1 V). PDIODE = 0.4 W.

For instance, at low line, full load (top of the sinusoid), theswitching frequency is:2

f sw +

ǒǸ2 @ 90Ǔ @ ǒ250 * Ǹ2 @ 90Ǔ

^ 95 kHz

4 @ 105 @ 250 @ 200 @ 10 *6(eq. 8)

Above calculation takes into account that the low−line
regulation voltage is 250 V.
In the real design, PFC output power is not ideallydelivered at input voltage zero cross so that the actualturn−on time is increased to regulate the desired load. As theturn−on time is lengthened, the inductor peak and rms
current are higher and the switching frequency is lowered
compared to the calculation results in equation 4, equation 5and equation 7. Therefore, it is recommended to add at least
20% margin in the equations.

PFC Output Bulk Capacitor

There generally are three main criteria / constraints whendefining the bulk capacitor:• Peak−to−peak output voltage ripple:
ǒdV outǓ pk*pk +Generally, the diode bridge and the power switch areplaced on the same heat−sink. As a rule of the thumb, one canestimate that the heat−sink will have to dissipate around:• 4% of the output power in wide mains applications (95 %being generally the targeted minimum efficiency)• 2% of the output power in single mains applications.
In our wide−mains application, about 4 W are then to bedissipated.
Among the sources of losses that contribute to thisheating, one can list:• The diodes bridge conduction losses that can be estimatedby the following equation:

[

R FB2
R FB1 ) R FB2

LL

@

ǒ

1*

ǒ

LL

+
(eq. 9)P out,maxh @ ǒV line,rmsǓ

8 Ǹ2 @ ǒV line,rmsǓ
3p @ V out,LL

LL

Ǔ

LL

Ǔ

R FB2
R FB1 ) R FB2
V REF(eq. 13)

V out,nom

Therefore, minimum CBULK to limit the VFB ripple in 6%
at 47 Hz line frequency is:
P out,max
6% @ V out,nom @ w @ V out,LL
100^ 50 mF
6% @ 390 @ 2p @ 47 @ 250(eq. 14)• Hold−up time specification:

where Vf is the forward voltage of the bridge diodes.
• The MOSFET conduction losses are given by:ǒP on Ǔ max + 4 @ R
DS(on) @3(eq. 12)+ ǒdV outǓ pk*pk

C BULK w@h

V REF
V out,nomǒdV FBǓpk*pk + ǒdV outǓpk*pk

1.8 @ V f @ P out,maxǒVline,rmsǓ

+So, peak−to−peak FB voltage is:2Ǹ2 P out.maxhp @ǒVline,rmsǓ

(eq. 11)C BULK @ w @ V out,LL

where (w = 2p · fline ) is the line frequency.
The peak−to−peak FB pin voltage ripple, (dVFB )pk−pk , isgenerally kept lower than ±3% (6% peak−to−peak) fromFB reference voltage (VREF = 2.5 V), not to trig the OVP
and DRE functions with a good margin in nominal
operation. Feedback resistor divider ratio is given by:

Power DevicesǒPbridgeǓmax + 2 @ Vf @P out,max

C BULK w

2+

2 @ P out,max @ t HOLD*UP
2

V out,LL * V out,min
2 @ 100 @ 10m
250 2 * 180 2

2^ 66 mF(eq. 15)

where hold−up time is 10 ms• Rms capacitor current:

The rms current depends on the load characteristic.
Assuming a resistive load, we can derive the following
approximate expression of its magnitude:(eq. 10)In our application, we have:• Pbridge = 2.1 W, assuming that Vf is 1 V.
• (Pon )max = 1.03 · RDS(on) W. Assuming that RDS(on)doubles at high temperature, the maximum conduction
losses are about 2.6 · RDS(on) W.
Switching losses cannot be easily computed. We will not
attempt to predict them. Instead, as a rule of the thumb, wewill assume a loss budget equal to that of the MOSFET
conduction ones. Experimental tests will check that they are
not under−estimated.

ǒI c,rmsǓ

max

^

Ǹ

32 Ǹ2
@
9p
ǒV

ǒPin,avgǓ

2
max

Ǔ

line,rms LL @ V out,LL*ǒ

P out,max
V out,LLǓ2(eq. 16)

In our application, we have:ǒI c,rmsǓ

www.onsemi.com
4

max

^

Ǹ

32 Ǹ2
100
105 2
@
*
9p
90 @ 250250ǒ Ǔ ^ 0.79 A
2(eq. 17)

AND90156/D
STEP 3: IC CONTROL CIRCUIT DESIGN

After selecting RFB1 and RFB2 , FB pin−related functions
are defined as below in our application:• Feedback resistor ratio, KFB :FB Pin Circuit

As shown by Figure 1, the feed−back arrangement
consists of:• A resistor divider that scales down the bulk voltage toprovide the FB pin with the feedback signal. The upper
resistor of the divider generally consists of two or threeresistors for safety considerations. If not, any accidental
shortage of RFB1 would apply the output high voltage tothe controller and destroy it.
• A filtering capacitor that is often placed between the FB
pin and ground to prevent switching noise from distorting
the feedback signal. A 1−nF capacitor is often
implemented. Generally speaking, the pole it forms withthe feedback resistors must remain at a veryhigh−frequency compared to the line one. Practically,
C FB v

K FB +R FB1 ) R FB2
R FB2

+

5.6 MW ) 36 kW
36kW

[ 157

• Follower boost offset voltage, VOFF(LL) :V OFF(LL) + R FB1 @ I FB(LL) + 5.6 MW @ 25 m + 140 V

V OUT(DRE*ENńEX*HL) + V REF @ K FB(DRE*XX) @ K FB

V OUT(DRE*ENńEX*LL) + V REF @ K FB(DRE*XX) @ K FB * V OFF(LL)(eq. 26)(eq. 18)

Enter: 2.5 · 95.5% · 157 − 140 ≈ 235 V
Exit: 2.5 · 97.5% · 157 − 140 ≈ 243 V• SOVP enter/exit VOUT at high−line,

generally gives good results.

V OUT(SOVP*ENńEX*HL) + V REF @ K FB(SOVP*XX) @ K FB

capacitors and of one resistor, this circuitry sets the
crossover frequency and the loop characteristic.
The A version (NCP1623A) features the follower boost
capability. This technique consists of reducing the output
voltage to optimize the PFC stage efficiency andsignificantly shrink its size and cost. In particular, the boost
inductance and the MOSFET losses can be dramaticallyreduced. Since the output voltage must remain higher thanthe line voltage, the output voltage is lowered in low line
only while it remains regulated to the default nominal level(Vout,nom generally set to 400 V or so) in high line conditions.
Practically, the NCP1623A controls this 2−level follower
boost operation through the feedback pin which sources thecurrent IFB(LL) (25 mA typically) enabled only at low line.
As detailed in the data sheet, this leads to the following
regulation levels:• Output voltage at high−line, Vout,HL = Vout,nom :V OUT(SOVP*ENńEX*LL)+ V REF @ K FB(SOVP*XX*LL) @ K FB * V OFF(LL)

V OUT(FOVP*ENńEX*HL) + V REF @ K FB(FOVP*XX) @ K FB

V OUT(FOVP*ENńEX*LL)+ V REF @ K FB(FOVP*XX*LL) @ K FB * V OFF(LL)I FB(LL)+390 * 250
25 m

+ 5.6 MWV OUT(UVP*ENńEX*HL) + V FB(UVP*XX) @ K FBR FB1 @ V REF
V out,nom * V REF+

5.6 M @ 2.5(eq. 21)390 * 2.5

V OUT(UVP*ENńEX*LL) + V FB(UVP*XX) @ K FB * V OFF(LL)+ 36 kW(eq. 31)Enter: 0.3 V · 157 ≈ 47 V
Exit: 0.53 V · 157 ≈ 83 V
• UVP enter/exit VOUT at low−line,• Lower feedback resistor, RFB2
R FB2 +

(eq. 30)

Enter: 2.5 V · 114% · 157 − 140 ≈ 307 V
Exit: 2.5 V · 112% · 157 − 140 ≈ 300 V• UVP enter/exit VOUT at high−line,(eq. 20)

Based on the output voltage spec at high and low line of
our application, the feedback resistor values are obtained by:• Upper feedback resistor, RFB1
V out,nom * V out,LL(eq. 29)Enter: 2.5 V · 107% · 157 ≈ 420 V
Exit: 2.5 V · 105% · 157 ≈ 412 V• FOVP enter/exit VOUT at low−line,• Output voltage at low line, Vout,LL :R FB1 +

(eq. 28)

Enter: 2.5 V · 110% · 157 − 140 ≈ 292 V
Exit: 2.5 V · 108% · 157 − 140 ≈ 284 V• FOVP enter/exit VOUT at high−line,(eq. 19)

V out,LL + V out,nom * R FB1 @ I FB(LL)(eq. 27)

Enter: 2.5 V · 105% · 157 ≈ 412 V
Exit: 2.5 V · 103% · 157 ≈ 404 V• SOVP enter/exit VOUT at low−line,

R FB1 ) R FB2
R FB2(eq. 25)

Enter: 2.5 · 95.5% · 157 ≈ 375 V
Exit: 2.5 · 97.5% · 157 ≈ 383 V• DRE enter/exit VOUT at low−line,• A type−2 compensation network. Consisting of two

V out,nom + V REF @(eq. 24)• DRE enter/exit VOUT at high−line,

1
150 @ ǒR FB1 ø R FB2Ǔ @ f line

(eq. 23)(eq. 22)

Enter: 1.2 V · 157 − 140 ≈ 48 V
Exit: 1.3 V · 157− 140 ≈ 64 V

www.onsemi.com
5(eq. 32)

AND90156/D
VCTRL Pin Circuit

Using equation 38 and equation 39, the output to control
transfer function is obtained by:

In order to find the control to output transfer function, theoutput voltage is defined by the multiplication of the output
current and the output impedance. Using equation 2 andassuming the efficiency is 100%, the output current is givenby:
i out ǒv ctrl, v outǓ +

p in
v out

dv ctrl(s)dv out(s)

[*

2

+

V line,rms @ t on

V line,rms @ T on.max @ ǒv ctrl * 0.5Ǔ
(eq. 33)

8 @ L @ v out

VOUT

The output current partial differentiation by the output
voltage is equivalently the output load resistance, Rload ,based on the equation:
di outdv out+*V out@ G EA @ z ctrl(s)1 ) s @ RZ @ CZ
1@
s @ R0 @ CZ 1 ) s @ RZ @ CP

CP

RFB1

V line,rms @ T on.max @ ǒV ctrl * 0.5Ǔ

CZ RZ

+*

v out

OTA

FB

8 @ L @ v out 2
i out

−

1
(eq. 34)

R load

VREF

RFB2

+

G EA

Therefore, diout / dvout can be included in the output
impedance and total output impedance is:z out(s) + R load ø R load ø1s @ C BULK

dv ctrl

Pole in equation 37 and zero in equation 40 are closely
located and cross−over frequency, fC , is placed between zeroand second pole in equation 40. Phase margin, fm (inradians), is adjusted by CP. From this, we obtain following
equations:• Feedback zero capacitor, CZ :2+*

V line,rms @ T on.max(eq. 36)

8 @ L @ V out

As a result, the control to output transfer function isdefined by:
dv out(s)dv ctrl(s)+di outdv ctrlG0(eq. 41)

2pf C @ R 0• Feedback zero resistor, RZ :V line,rms @ T on.max @ R load

+ G0 @CZ +@ z out(s)
2

+

PWM
comparator

Figure 2. FB and VCTRL Circuit(eq. 35)

The output current partial differentiation by the control
voltage is:di out(eq. 40)I CTRL

VCTRL

2

+*

V REF

where R0 = Vout / (VREF · GEA ) and the compensation
network circuits are CZ , RZ and CP ( << CZ ) as shown in
Figure 2.

2 @ L @ v out
2

+

+*

16 @ L @ V out

@

1

RZ +

1 ) s @ R load @ C BULK ń 2(eq. 37)tanwhere Ton.max is 12.5 ms at low−line and 5 ms at high−line
in A version and G0 is static gain.
The output to control transfer function is obtained by FB
resistive network ratio, OTA transconductance and VCTRL
compensation network as below:
v ctrl + i ctrl @ z ctrl(s)CP +R load +

V Ref
V out

Ǔ

(eq. 43)

2pf C @ R Z

V out,nom

2

P out,max+

390 V 2100 W

+ 1.52 kW(eq. 44)

The cross−over frequency, fC , should be higher than PFC
boost stage pole, fP :where ictrl is OTA output current and zctrl (s) is VCTRL
compensation circuit impedance.
The OTA output current is defined by:ǒǒp2 * fmǓLoad resistance, Rload is calculated by:(eq. 38)i ctrl + ǒV REF * v FBǓ @ G EA + V REF *(eq. 42)

2 @ CZ• Feedback pole capacitor, CP :11 ) s @ R load @ C BULK ń 2

R load @ C BULKfP +@ v out @ G EA

1
1+
+ 3.1 Hz
p @ R load @ C BULK
p @ 1.52 kW @ 68 mF(eq. 45)

The condition of the highest cross−over frequency is theworst case of the phase margin where the line voltage is highto widen the bandwidth of the control to output transfer
function. If we target a 25−Hz crossover frequency anda 60−degree phase margin (p/3 in radians) in ourapplication, we have:(eq. 39)

where GEA is OTA transconductance gain and Vout is DC
output voltage.

www.onsemi.com
6

AND90156/D
R0 +
G0 +

390 V
2.5 V @ 20 mS

The drain sensing based ZCD circuitry is shown in
Figure 3. Drain voltage is sensed by CS resistor network andscaled down by KCS :+ 780 kW

264 V 2 @ 5 ms @ 1.52 kW
16 @ 200 mH @ 390 V+ 424

K CS +

424+ 3.46 mF [ 3.3 mF
CZ +2p @ 25 Hz @ 780 kW
RZ +1.52 kW @ 68 mF
2 @ 3.3 mF
tan

CP +

2p @ 25 Hz @ 15 kW+ 245 nF [ 220 pF(eq. 46)

P CS,STBY +CS/ZCD Pin Circuit

0.5 V

ǒIL,pkǓ

(eq. 47)
max

Combining the result in equation 6 leads to:
R SENSE +

0.5 V
3.3 A

+ 0.15 W(eq. 48)

In our practical case, 0.12 W resistor is selected to have a
bit of margin. RSENSE losses can be computed using
equation 10 giving the MOSFET conduction losses where
RSENSE replaces RDS(on) :ǒP RSENSE Ǔ max + 4 @ RSENSE @
3

@

ǒ

1*

ǒ

P out,maxh @ ǒV line,rmsǓ

8 Ǹ2 @ ǒV line,rmsǓ
3p @ V out,LL

LL

Ǔ

LL

Ǔ

2

(eq. 49)

ǒV line,rmsǓ

Hence, our 0.12 W current sense resistor will dissipate
about 124 mW at full load, low line.
V IN

L BST

D BST

ǒVmains,rms @ Ǹ2Ǔ

2(eq. 51)

R CS1 ) R CS2

The NCP1623 integrates leading edge blanking on the
CS/ZCD pin that prevents the need for a filtering capacitor.
No capacitor is allowed in the CS/ZCD circuitry as this will
result in distorting the CS/ZCD signal leading to wrong or
no ZCD detection. Care must be taken when probing the
CS/ZCD signal with a scope probe as the scope probe will
add typically a 10−pF capacitance.
In a boost converter, the averaged drain voltage which is
one pin of the boost inductor is equal to the Vin voltage
which is on the other pin of the boost inductor and this isbecause the average voltage drop across the inductor is zero
volts in volt−sec balance if we neglect the series resistanceof the inductor. Therefore, VCS/ZCD is averaged to obtain the
input voltage information.
The averaged VCS/ZCD, VSNS, is used for ZCD, line
detection, OVP2 (C version only) and brown−out (disabledin A and C version) in our application as below:• Line range detection threshold:

The circuit detects an over−current situation if the voltage
across the current sense resistor exceeds 0.5 V. Hence:
R SENSE +(eq. 50)

R CS2

where KCS is 133 and RCS2 is 62 kW in general.
The values of RCS1 and RCS2 must be chosen high for notconsuming too much power during standby. During standby,
there is no switching and the voltage seen by RCS1 in series
with RCS2 is a constant voltage equal to Vmains,rms · /2. The
power consumed during standby is given by:+ 15.6 kW [ 15 kW

ǒp2 * p3ǓR CS1 ) R CS2

ǒV line,rmsǓ

HL

LL

+

+

K CS @ V CSńZDC(HL)Ǹ2
K CS @ V CSńZDC(LL)
Ǹ2

V OUT

+

+

133 @ 1.8 V
Ǹ2133 @ 1.55 V
Ǹ2+ 169 V(eq. 52)+ 146 V(eq. 53)• OVP2 threshold (C version only):

V DRAIN

V OUT(OVP2) + K CS @ V ZCD(OVP2*EN) + 133 @ 3.77 V + 501 V

RCS1a

DRV

RCS1b

(eq. 54)• Brown−out threshold (Disabled in A and C version):

RCS1

ǒV line,rmsǓ
RCS2

RCS1c

BO*EN

+

+

CS/ZCDR SENSEǒV line,rmsǓ

BO*EX

+

Figure 3. Drain Sensing for ZCD+

www.onsemi.com
7

K CS @ V CSńZCD(BO*EN)Ǹ2
133 @ 0.79 V
Ǹ2+ 74 V(eq. 55)

K CS @ V CSńZCD(BO*EX)Ǹ2
133 @ 0.94 V
Ǹ2+ 88 V(eq. 56)

AND90156/D

VAUX

D BST

N PRI

V IN
L BST

One easy way to avoid the effect of parasitic capacitors is
to reduce the value of the resistors, while keeping thedividing ratio KCS around 133. Reducing the CS/ZCD
bridge resistors value (RCS1 + RCS2 ) is at the expense of highstandby power consumption.
If the RCS1a + RCS1b + RCS1c in Figure 3 should be above
5 MW, it is advised to have one 500−V SMD high−value
resistor on the drain side (e.g. RCS1a = 5.1 MW) with two low
value (e.g. RCS1b = RCS1c = 240 kW) 200−V SMD resistors
in series. This is to avoid inter−resistor capacitance to GND
to have difficulties to be discharged before the FET turn−on
cycle. Experience shows that it is not recommended to use
3 equal value resistors to balance the drain voltage.
Bench experiments have proven SMD1206 & 0805
superiority, parasitic capacitance wise, over trough hole
resistors.
RCS1 and RCS2 must be placed as close as possible to
CS/ZCD pin. PCB traces connecting the RCS resistors must
be kept as short as possible, the width of the trace being as
small as possible (minimum parasitic capacitance). It is wise
to keep a safety distance of 1 cm between RCS resistors andDRV, VIN, VDRAIN copper traces to avoid coupling.

VOUT
VAUX

NAUX
NPRI /N AUX = 10

RAUX
CAUX

DRV

RCS2

DAUX
RCS1
CS/ZCDRSENSE

Figure 4. Aux. Winding Sensing for ZCD

It is possible to use the schematic shown in Figure 4 togenerate the signal of CS/ZCD pin. Thanks to the auxiliary
winding voltage capacitor CAUX, RAUX and DAUX, it ispossible to generate at the cathode of DAUX a voltage equal
to the power MOSFET drain voltage multiplied by theauxiliary (NAUX) to primary (NPRI) transformer turns ratio.
The parameter KCS previously described is now defined by:
K CS +

N PRI
N AUX

@

Layout and Noise Immunity Considerations

The NCP1623 is not particularly sensitive to noise.
However, usual layout rules for power supply design
apply. Among them, let us remind the following ones:• The loop area of the power train must be minimized.
• Star configuration for the power ground that provide thecurrent return path.
• Star configuration for the circuit ground.
• The circuit ground and the power ground should beconnected by one single path, no loop is allowed.
• This path should preferably connect the circuit ground to
the power ground at a place that is very near the grounded
terminal of the current sense resistor (RSENSE ).
• A 100 or 220−nF capacitor should be placed between thecircuit VCC and GND pins, with minimized connection
length.
• RCS resistors must be placed as close as possible to the
CS/ZCD pin, and capacitance coupling with GND or any
other signal must be avoided.
• It is recommended to place a filtering capacitor on the FB
pin to protect the pin from possible surrounding noise. It
must be small however not to distort the voltage sensed by
the FB pin.

R CS1 ) R CS2
R CS2(eq. 57)

where KCS is 133, NPRI /NAUX is 10 and RCS2 is 22 kW ingeneral.
With this approach, a lower voltage is carried and also low
RCS1 values reduce the sensitivity to parasitic capacitors.
Another benefit of this circuitry is that there is no current
consumption during standby (No switching activity hence
no Vaux voltage).
It has to be mentioned that product version withbrown−out feature activated will not operate with thiscircuitry. Everything else will work exactly the same asalready described when the power MOSFET drain voltage
is used for ZCD.
CSZCD Resistor Design Guideline

When the RCS resistor bridge totals a resistance in the MW
range at drain sensing circuit like Figure 3, it is very sensitive
to parasitic capacitances as low as few hundreds of fF.
Parasitic capacitances can be made from RCS resistors nodes
to GND or power MOSFET drain. These parasitic
capacitances effect can lead to permanent false fault
detection events: OCP, OVS or OVP2 triggering, making thecontroller unable to operate properly.

www.onsemi.com
8

AND90156/D
SUMMARY
Table 1. MAIN EQUATIONS
Step
Step 1:
Key
Specifications

Components

FormulaComments

fline : Line frequency. It is generally specified in a range of 47 − 63 Hz for 50 Hz/60 Hz applications.

ǒV line,rmsǓ
ǒV line,rmsǓ

: Lowest Level of the line voltage, e.g., 90 V.

HL
LL: Level for the line voltage, e.g., 264 V.

Vout,nom : Nominal Output Voltage at high−line, e.g., 390 V.
Vout,LL : Output voltage at low−line (by follower boost) , e.g., 250 V.

ǒdV outǓ pk*pk : Peak−to−Peak output voltage ripple in the line frequency
tHOLD−UP : Hold−up Time that is the amount of time the output will remain valid during line drop−out, e.g., 10 ms.
Vout,min : Minimum output voltage allowing for operation of the downstream converter, e.g., 180 V.
Pout,max : Maximum output power consumed by the PFC load, e.g., 100 W.
h: System efficiency, e.g., 95%.

ǒPin,avgǓ
Step 2:
Power Stage
Designmax: Maximum input power from the mains line at full load and low−line, e.g., 105 W assuming h = 95%.

PFC InductorLvǒV line,rmsǓ

2 @ ǒP in,avgǓ

ǒIL,pkǓ

max

ǒIL,rmsǓ
Bridge DiodeǒPin,avgǓ
ǒIL,pkǓMaximum rms current

Ǹ6

Boost Diode

Bulk Capacitor

ǒV line,rmsǓ

1*

ǒP diodeǓmax + V f @C BULK w

C BULK w

ǒI c,rmsǓ^Maximum power loss
Vf : bridge diode forward voltage

1.8 @ V f @ P out,max

ǒP on Ǔ max + 4 @ R
DS(on) @
3

ǒ

LL

max

MOSFET@

Maximum peak currentmax

ǒV line,rmsǓ

+ 2 Ǹ2ǒPbridgeǓmax [@ T on,max

max+ 2 Ǹ2max

Maximum inductanceTon,max : max turn−on time

2
LL

LL

ǒ

@h
P out,maxh @ ǒV line,rmsǓ

8 Ǹ2 @ ǒV line,rmsǓ
3p @ V out,LL

LL

Ǔ

LL

Ǔ

Maximum conduction loss
RDS(on) : FET on−state resistance2

Maximum conduction loss

P out,max
V out,LL

Minimum capacitanceto meet output ripple spec

P out,maxǒdV outǓ pk*pk @ w @ V out,LL

Minimum capacitanceto meet hold−up time spec

2 @ P out,max @ t HOLD*UP
2

V out,LL * V out,min

2

Maximum rms currentmaxǸǒPin,avgǓ
32 Ǹ2
max
@
9p
ǒV
Ǔ @V
line,rms LL

2*
out,LLwww.onsemi.com
9ǒ

P out,max
V out,LLǓ

2

AND90156/D
Table 1. MAIN EQUATIONS (continued)
Step

Components

Step 3:
IC Control
Circuit Design

FB Pin Circuit

FormulaI FB(LL)R FB2 +VCTRL Pin Circuit

R0 +

CZ +
RZ +

V out,nom * V REF

Maximum FB capacitor

1

vou t/ictrl resistanceiCTRL : OTA output current
GEA : OTA gain

V out,nom
V REF @ G EA
V out,nom

Load resistance at full load and high−line2

P out,max

ǒV line,rmsǓ

2
HL

DC gain in the control to output
transfer function@ T on.max @ R load

16 @ L @ V out
Zero capacitor
fC : cross−over frequency

G0
2pf C @ R 0

Zero resistor

R load @ C BULK
2 @ CZtan

CP +CS/ZCD Pin Circuit

FB2 resistor
VREF : FB reference voltage, 2.5 V.

R FB1 @ V REF

150 @ ǒR FB1 ø R FB2Ǔ @ f line

R load +G0 +FB1 resistor
IFB(LL) : Follower boost FB current

V out,nom * V out,LL

R FB1 +C FB vComments

ǒp2 * fmǓPole capacitor
fm : phase margin in radians

2pf C @ R Z

R SENSE +Sensing resistor

0.5 VǒIL,pkǓ

max

ǒP RSENSE Ǔ max + 4 @ RSENSE @3@

K CS +

ǒ

N PRI
N AUX

1*

@

h @ ǒV line,rmsǓ

8 Ǹ2 @ (V line,rms) LL
3p @ V out,LL

R CS1 ) R CS2
R CS2

ǒ

ǒ

P out,max

R CS1 + R CS2 @ 133 @

N AUX
N PRI

Ǔ

Maximum conduction loss

Ǔ

+ 133

Ǔ

*1

www.onsemi.com
10

LL

2

CS resistor ratio
NPRI /NAUX = 1 (Figure 3), 10 (Figure 4)
RCS2 = 62 kW (Figure 3), 22 kW (Figure 4)
CS1 resistor
NPRI /NAUX = 1 (Figure 3), 10 (Figure 4)
RCS2 = 62 kW (Figure 3), 22 kW (Figure 4)

AND90156/D
Fuse
1.6 A
L

CM
30 mH

CM
30 uH
RX
4.8 M

D BRIDGE
8 A, 1 kV

DM
100 m HL BST,
200 m N PRI = 40T

C IN2
680 n

C IN1
220 n

C IN3
680 n

D BST
5 A, 520 V

C IN4 RM8
100 n

Secondstage
C BULK
68 m F, 420 V

N
R FB1
5.6 M

CP
220 n

System spec
* Input voltage: 90~264 Vrms
* Output power: 100 W* Output voltage:
250 V in low−line (115 Vrms)
390 V in low−line (230 Vrms)

R
C Z 15Zk
3.3 m

VCTRL

FB

1

6

GND
2

VCC
NCP1623

V EXT

C FB
100 p

R FB2
36 k

DRV

CS/ZCD
3
R AUX
47

5

4

C AUX
2.2 n
R CS1
270 k

R CS2
22 k

DAUX
0.2 A, 250 V

R SENSE
0.12

N AUX = 4T

Figure 5. System Schematic of 100 W Design

onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATIONONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales

TECHNICAL PUBLICATIONS:Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com◊

www.onsemi.com
11