スケーラブルな高集積量子誤り訂正システムの開発

Development of Scalable Highly Integrated
Quantum Bit Error Correction System
プロジェクトマネージャー 小林和淑（京都工芸繊維大学）
Project Manager: Kazutoshi Kobayashi

Kyoto Institute of Technology (KIT), Japan

Search “QUBECS”
https://www.greenlab.kit.ac.jp/qubecs/index.html

Outline

dilutionrefrigerator

Qubit
Controller

NISQ=Noisy Intermediate-Scale Quantum, FTQC=Fault Tolerant Quantum Computer

Backend to correct
errors9U

FPGA and SoCs for
scalability up to 1M Qubit

Consists of
discrete parts

RT

Frontend qubit
controller

microwaves

Small and low powerby SoC(70K)

To reduce # of wires

3-4K

Optical and Cryo
CMOS IC

0.8K

Above Qubit

10mK
16 Superconducting Qubit

Current small-size QC
2Scalable
Network

Our research Area

12Gsps/16bit DAC
6Gbps/12bit ADC

From NISQ to FTQC

Qubit is from RIKEN
100-1000 Superconducting Qubit

Our targeted scalable QC
Moonshot Target6 "Quantum computer" by Kobayashi PM

Our Goals on 2025 and 2030
~300K

4K~300K⚫ 2025ASIC protypes withsignal generator,
microwave tx/rx, andlow-jitter ADC, DAC, RFcircuits

ASICASI✓ Develop a prototype system for FTQC
with ~100 physical qubits⚫ 2030

✓ Develop a system for FTQC scalable up
to 1M physical qubits

10mK
Quantum
Quantum
Quantum
devicesQubit
devices
devices
devices

CSoC

Network
Quantum-classicalinterface module

FPGA cluster forerror analysis

Frontend for
qubit control

Backend for error
syndrome analysis

Qubits (100 physicalqubits as 1 logical qubit)

2025: Prototype system for FTQC with ~100 physicalqubits~300K

4K
Cryo ASICs

10mK

70K

Quantum
Quantum
Quantum
devicesQubit
devices
devices
devices

Qubits (10,000 physicalas 10 logical qubits)

Network

OpticalcircuitFrontendsystem

SoC

SoC

FPGAFPGA

Backendsystem

100 x clustersof F&B

2030: System for FTQC scalable up to 1,000,000 physical qubits
3Moonshot Target6 "Quantum computer" by Kobayashi PM

Principal Investigators*: Subject Leader

Dr. Sano*(RIKEN)Prof. Kadomoto Prof. Osana(U. Tokyo)(Kumamoto U.)

Prof. Sato
Prof. Shiomi*
Prof. Shintani(Kyoto U.)(Osaka U.)(KIT)
Subject 3: Scalable Classical-Quantum Interface by Photonic/CryoCMOS Integrated Circuits

Subject 1: Backend for error correction
Subject 2: Advanced Qubit
Control Frontend

Prof. Kobayashi* Prof. Tsuchiya(Shiga Pref. U.)(KIT)Prof. Takai(KIT)Prof. Miyahara(KEK)

Subject 4: Cryo CMOS ASICs for Frontend/backend

Dr. Miyoshi*(Quel-inc)
Quel-1: Qubit controller

Subject 5: Frontend ASICs at room temperature(will be included soon)

Experts of qubit-controllers, computer architectures and integrated circuits
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Moonshot Target6 "Quantum computer" by Kobayashi PM

Qubits from RIKEN vs. IBM vs. GoogleGoogle⚫ Our first target issuperconducting qubit fromRIKEN

2-qubit gateschemeTunable Coupling

RIKEN
Prof. Nakamura

2-d array⚫ 2-qubit gate scheme

Cross Resonant✓ Cross resonance gate – RIKEN, IBM✓ Tunable coupling – Google

qubittopology
Heavyhexagon⚫ Qubit topology✓ 2-d array - RIKEN, Google✓ Heavy hexagon - IBM*https://arstechnica.com/science/2019/10/insi
de-googles-quantum-computing-efforts/**https://www.ibm.com/blogs/research/202
0/09/hardware-aware-quantum/*** Shuhei TAMATE et al. ”Toward realization of scalable
packaging and wiring for large-scale superconducting
quantum computers,”
IEICE Transactions on Electronics, Article ID 2021SEP0007

5Google*RIKEN Prof. Nakamura ***IBM**IBMSubject 1: Backend for Error Correction

Theme 1: Scalable backend system for error correction by Dr. Sano
Theme 2: ASIC implementation of QEC cores by Prof. Kadomoto
Theme 3: Dependable error correction backend by Prof. OsanaSubject 1: Backend for Error Correction⚫

Overview✓ Develop a backend system for error correction scalable to 1M physical qubits⚫

Research Target✓ Prototype a backend system for qubit error correction✓ Demonstrate error syndrome analysis on a scale of 100s of physical qubits
at an acceptable throughput and latency✓ Show scalability for more physical qubits
Subjects２,３,４⚫

R&D themes✓ Theme 1 (RIKEN)
Scalable backend system for error correction✓ Theme 2 (The University of Tokyo)
Error correction algorithm
for ASIC-based backend system✓ Theme 3 (University of the Ryukyus)
Dependable error correction backend

Subject１~300K

4K~300K
ASIC
ASI

10mK
Quantum
Quantum
Quantum
devicesQubit
devices
devices
devices

Qubits (100 physicalqubits as 1 logical qubit)

CSoC

ASIC protypes withsignal generator,
microwave tx/rx, andlow-jitter ADC, DAC, RF
circuits

Network
Quantum-classicalinterface module

FPGA cluster forerror analysis

Frontend forqubit controlBackend for error
syndrome analysis

Expected system for FTQC with 100 physical qubits
72022/11/18

Theme 1 : Scalable Backend System for ErrorCorrection⚫ Goal✓ Proof-of-concept of scalable QEC with FPGA-based backend system prototype⚫ R&D sub-themes

Dr. Sano(RIKEN)✓ Sub-theme 1:
Algorithm and hardware for QEC decoder➢ Develop QEC decoder algorithms for hardware➢ Design and implement QEC decoder hardware with FPGAs✓ Sub-theme 2:
FPGA cluster for backend system✓ Sub-theme 3:
Interface with upper layer andsystem architecture82023/3/26

Theme 1 : Progress⚫ Algorithm and hardware for QEC decoder✓ Survey QEC decoder algorithms✓ Identify promising one for hardware, Union find (UF) decoder➢ Lower latency, higher scalability

N. Delfosse et.al, Quantum 5, 595, 2021

➢ acceptable accuracy close to MWPM

1098765432
100 1 2 3 4 5 6 7 8 9 10

Model graph of 2D ancillary qubits✓ Propose systolic-array for UF, andevaluate it by software-based emulation✓ Submit a paper to Q-CASA workshop⚫ FPGA cluster for backend system✓ Design and prototype Shell (system-on-chip) for FPGA
✓ Start considering specification of FPGA cluster for the backend⚫ Interface with upper layer and system architecture✓ Survey existing interfaces
9Concept of systolic array for UF
2023/3/26

Theme 2 : ASIC Implementation of QEC Cores⚫ Goal✓ Highly-integrated low-power ASIC-based QEC core for scalability⚫ R&D sub-themes✓ Sub-theme 1: Design of ASIC-based QEC architecture➢ Design QEC core architecture and construct a systemby connecting a prototype ASIC chip and the FPGA cluster

ASIC

Prof. Kadomoto(U. Tokyo)✓ Sub-theme 2: Performance evaluation of ASIC-based
QEC core➢ Evaluate the performance through simulation, anddemonstrate improvement of the overallsystem performance✓ Sub-theme 3: Development of QEC TEG chip
➢ Implement each functional block of
the QEC core as an ASIC and verify
the performance improvement through measurements

FPGA Cluster
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Moonshot Target6 "Quantum Computer" by Kobayashi PM

2023/3/28

Theme 2 : Progress and Plans⚫ Set up ASIC design/simulation environment✓ 28-nm CMOS technology⚫ Survey on the various components of QEC backend⚫ Developed some QEC decoders in HDL
Y. Suzuki, et al. IEEE Micro, 2022 1110-1125✓ Greedy decoder
N. Delfosse et.al, Quantum 5, 595, 2021
✓ Union-Find (UF) decoder⚫ Near-term milestones✓ Evaluate the decoders through RTL simulations in ASIC technologies (28, 7-nm CMOS)✓ Prepare the design environment for TEG chip 1 (22-nm CMOS)

11Moonshot Target6 "Quantum Computer" by Kobayashi PM

2023/3/28

Theme3: Dependable Error Correction
Backend⚫ Interconnection network for the backend FPGA cluster✓ Intra-backend and backend-frontend interconnect➢ Scalable option: 100 Gbps Ethernet➢ Low-latency option: 100+ Gbps direct links

Prof. Osana(Kumamoto U.)✓ Development & evaluation on a mock-up

Dependability of FPGA clusters✓ Investigate SEU (Single Event Upset) and other dependability
problems on large-scale FPGA clusters

12Moonshot Target6 "Quantum Comuter" by Kobayashi PM

2023/3/28

Interconnect for FPGA clusters
f⚫

µ400

✓ To fit within gate operation period✓ FPGA processing latency + interconnect latency✓ Low-latency interconnect is crucial

Kyokko300

RTT (ns)➢ Ethernet switch has too much latency ~700 nsAurora

200100⚫ Developing Kyokko✓ Xilinx Aurora 64b66b compatible, 100 Gbps
capable✓ Fits with both the frontend (Xilinx) and backend (Intel)✓ Reliability features are scheduled in 2023

0Xilinx GTH Xilinx GTY Xilinx GTY Arria 10 Cyclone 10 S10 L-tile
10G10G
25G
10G
10G10G

RTT: Round Trip Time

⚫ Towards the ultra low-latency interconnect✓ Less than 100 ns latency with Xilinx GTY✓ Agilex version for RIKEN FPGA cluster in 2023
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Moonshot Target6 "Quantum Computer" by Kobayashi PM2023/3/28

Subject 2: Advanced Qubit Control Frontend

By Dr. Miyoshi
Dr. Miyoshi*(Quel-inc)Subject 2 Goal
Error correction backend⚫

Goal: Establish the qubit control andRealtime TX/RX
Error Syndrome✓ Realtime TX/RX qubit data b/w frontend-backend✓ Highly-accurate signal transmission✓ Synchronization for scalability⚫

Issues✓ Signal quality and stability✓ How to synchronize✓ Efficient connection with backend
w/ Prof. Osana➢ Low-latency feedback➢ Optimized data scatter/gather✓ Downsizing ( Currently 9 U/4 qubit)✓ Optimization in 300K, 70K, 3-4K, (10mK)

Qubit Control Frontend

measurement frontend system

I/O Frontend

I/O FE

Digital Signal Processing
Wave-refinement
qubit decoder
synchronization

Downsizing by SoC/SiP
Optimization between
300K, 70K, 4K, (10mK) stages

Qubit ・・・ Qubit

I/O FE・・・

Analog circuit
High-accuracy
High-density

Synchronization ofTX/RX timing
15

Low-latency
feedback

Qubit

Qubit

Downsizing by SoC/SiP
9-10GHz, 20GHz RF frontend:
Downsizing by combining a component
supports multiple I/Os.

Analog Mixer for RF:
Downsizing by packing modules as a SiPFPGA and AD/DA chips:
Downsizing by packing modules as a SoM

Power management and drivers fortemperature control:
Downsizing by adoption lightweighttemperature control
Our current system for 4-Qubit control/measurement
16

SiP (System in aPackage)
Totally downsizing for much more
qubit control/measurement

SoM (System ona Module)
https://japan.xilinx.com/products/som/what-is-a-som.html

Control/Measurement Qubit for FTQC
Frontend
Syndrome
data

Repeat measurementand decoding in lowlatency

Measurement &Decode・・・

Optimize communication protocol
with high-throughput and lowlatency

PhysicalQubit

Frontend
Backend-System(Subject 1)

Efforts to reduce latency for shorter
feedback cycles, resulting in faster
quantum computing speed.
17Intervals must provide
sufficient Fidelity(ex. T1 / 1000 ≒ 500nsec)

Network

Error collection
resultFrontend
Feedback control(ex. S-gate)

LogicalQubit

Highly-accurate synchronous signal processing
clock source

Event source

Frontend 1Sensor+ Peltier

Frontend 2

Fixed-delay✓ Suppress phase fluctuation for eachmicrowave TX✓ Optimization for wave-figure forindividual qubit

Q

Current system depends on temperature
control.
-> Next-gen system must be much simpler bycompensation using digital signal processing.
[degree]Sensor+ Peltier

100 ADC output signals[us]Fixed-delay in repeated sending/receiving multiple
waves in our current system for ~100 nodes
Scalable clock distribution and precise
time synchronization for optimized event
execution
18

Frontend nSensor+ Peltier[s]

Current system achieves fluctuation of 2.5 deg.
RMS in 120 sec. with temperature control

Subject 3: Scalable Classical-Quantum
Interface by Photonic/Cryo-CMOS
Integrated Circuits
Theme 1: Exploring photonic integrated circuits operating in the extremely
low-temperature environment by Prof. Shiomi

Theme 2: Development of transistor model for Si CMOS devices in theextremely low-temperature range of 4K to 70K by Prof. Shintani
Theme 3: Cryo-CMOS integrated circuits with extremely low power
consumption by Prof. Sato

Subject 3 Goal

✓ Scalable Classical-Quantum Interface
by Photonic/Cryo-CMOS Integrated Circuits

Syndrome Analysis

RT

Cryo-Optical I/F
Encoder/Decoder

Frontend

Cryo CMOS
Microcontroller

(70K)
4K
0.8K

Analog frontend

10mK
100~1000 Qubits

Quantum Computer Overview
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Moonshot Target6 "Quantum computer" by Kobayashi PM

Cryo PDKPerformanceoptimization
by Cryo PDKTheme 1: Exploring photonic integrated circuits operating in
the extremely low-temperature environment
Analysis & Modeling⚫ Cryo-Optical I/F✓ Milestone➢ 2022 Measurement at cryogenic environment➢ 2023 Optical device measurement and characterization➢ 2024-2025 Modeling and prototype design✓ Challenges

Prof. Shiomi*(Osaka U.)
Chip fabrication and Measurement➢ Optical HW architecture for Photonic/Cryo-CMOS Integrated Circuits➢ Design methodology for optical-electronical encoder/decoder design

Electrode Fiber⚫ Progress✓ Prototype chip design✓ Measurement setup for cryogenic environment➢ Progress explanation at next page
21

Moonshot Target6 "Quantum computer" by Kobayashi PMLHeChip

Cryo Environment Measurement

Progress of Theme 1: Prototype chip design
ElectrodePartial circuit design (TO @ 2023 Feb.)
Electrode

Fiber

Light

Fiber

MZM, MZI

QAM

Si-Photonics chipElectrode

Electrode
30 GHz BW @ room temp.
→ To do: how fast at cryogenic temp.?

Future work: Characterization at cryogenic environment
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Moonshot Target6 "Quantum computer" by Kobayashi PM

Theme ２: Cryo CMOS PDK Development
10-3⚫ Cryo CMOS PDK development✓ Milestone➢ 2022: Measurement at cryogenic environment➢ 2023: Alpha version development（CryoPDK_v1）➢ 2024～2025: Alpha version release
Modeling non-ideal characteristics, such asprocess variation and self-heating effect

10-5
10-6300K
228K
153K

78K

4KnMOS
L=45nm
W=1um
BSIM4

Prof. Shintani(KIT)

10-7Vgs [V]Discontinuous effect observed in industrial model✓ Challenges➢ Development of a new Tr. model that can reproduce thecharacteristics at 4K➢ Incorporation of physical phenomena that is notconsidered in industry standard model⚫ Progress✓ Designed 65nm Tr. Array TEG using a CMOS circuit
prototype (Jan. T.O.)
23

Id [A]

10-4≥ 4K> Few watt

10mKQubits

Self-heating effectMoonshot Target6 "Quantum computer" by Kobayashi PM

Tr. array TEG

Theme 3: Cryo-CMOS Design Platform⚫ Cryo-CMOS Design Platform

Energy Consumption of RO Circuit at 300K

✓ Milestone➢ 2022 exploration and implementation ofmeasurement methods for cryogenic temperatureenvironments➢ 2023 prototype, measure, and model basic circuit
blocks such as flip-flops, SRAMs, PLLs for operation
at cryogenic temperatures➢ 2024-2025 optimize and minimize power
consumption of circuits for cryogenic applications

Prof. Sato(Kyoto U.)
If Leakage Current Decreases,
Minimum Energy Operating
Voltage Shifts to Lower Voltage

Prof. Awano(Kyoto U.)✓ Challenges➢R u‘ y am p' amamyunchanged even in extremely low temperatures➢ Exploration of circuit paradigms specialized forcryogenic temperature, focusing on ultra-lowleakage-current dynamic circuits

Dynamic DFF w/o clkb
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Moonshot Target6 "Quantum computer" by Kobayashi PM

Setups for Cryo Measurement Environments⚫ Optical circuit @ Osaka Univ.

✓ Cryogenic environment
Electrode Fiber

LHe
Chip

⚫ Digital CMOS circuits @ Kyoto Univ.

✓ Cryogenic environment
Over 100 I/Os

• Cryo dewar designfor photonic chip
• Prototype deliveredin 2023 Summer• Rod design for
cryogenic dewar• Over 100 I/Os
LHe

Chip

⚫ Analog CMOS circuits @ KIT✓ LHe circulating type prober✓ 10K to room temperature✓ Connect to B1500 (Keysight)

25✓ Cryocooler-based environment• Temperature can be changed from
4K to room temperature• ~24 I/Os.

Moonshot Target6 "Quantum computer" by Kobayashi PMSubject 4: Cryo CMOS ASICs forFrontend/backend
Theme 1: Digital circuit implementation and reliability enhancement techniquesby Prof. Kobayashi
Theme 2: RF front-end circuit by Prof. Tsuchiya
Theme 3: High-speed DAC for frontend by Prof. Takai
Theme 4:High speed ADC for frontend by Prof. Miyahara

Subject 4: Cryo CMOS ASICs for Frontend/backend⚫ Goal: To implement ASICs operating at a cryogenic

temperature to control qubits (Frontend) and to correct errors(Backend)⚫ Research items

Final Goal
Cryo CMOS SoCs

✓ Digital circuit implementation and reliability enhancement techniques (Prof.
Kobayashi, KIT, Japan)✓ RF frontend circuit (Prof. Tsuchiya, Shiga Pref. Univ., Japan)✓ High-speed DAC for front-end (Prof. Takai, KIT, Japan)
3K-4K✓ High speed ADC for front end (Prof. Miyahara, KEK, Japan)⚫ Fabrication process will be a 22nm bulk CMOS (Scaled from 28 nm)✓ High-performance and cost-effective! 2mmx3mm chip can be fabricated byaround a few M JPY.
✓ 28nm bulk is used by many research projects such as Google.
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Moonshot Target6 "Quantum computer" by Kobayashi PMQubitsTheme 1: Digital circuit implementation andreliability enhancement techniques⚫ For frontend

Prof. Kobayashi*(KIT)➢ Not easy-going. Synchronous reset on FPGA vs Asynchronous reset on ASIC. IP onFPGAs must be replaced by random logics.
➢ LVDS interface from qubit by Prof. Miyahara✓ Migrate FPGA-based design by Quel (Miyoshi) to ASIC

⚫ For backend✓ Implementing an error correction decoder to an FPGA using the HLS code byDr. Suzuki [1][1] Y. Suzuki, et al. IEEE Micro, 2022 1110-1125
28

Moonshot Target6 "Quantum computer" by Kobayashi PMReliability Enhancement⚫ FTQC w/ 1M qubit will be similar to a particle

accelerator✓ Huge classical electronics must be operated withhigh fidelity⚫ Reliability issues must be considered✓ Qubit suffer from cosmic ray (by muon) [1, 2]✓ Classical computers also suffer from cosmic ray(mainly by neutron).
➢ Super computers must mitigate soft errors [2]✓ Will conduct soft error measurement at cryotemperature.

LHe

Chip

Neutron beamSoft error measurement at Cryoenvironment in 2023-2024[1] "Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays“, by Y. Suzuki et.al, Micro-55, 2022
[2] “Suppressing quantum errors by scaling a surface code logical qubit,” Google Quantum AI, Nature 614, 676–681, 2023
[3] "Predicting the number of fatal soft errors in Los Alamos national laboratory's ASC Q supercomputer," S. E. Michalak et.al., TDMR,vol. 5, no. 3, 2005
29

Moonshot Target6 "Quantum computer" by Kobayashi PMTheme 2: RF Frontend Circuit
Goal: Establish Cryo- and RF-CMOS design for RF frontend
Discrete ICs

Current implementation:
large board, many wires … NOT-scalable

DACControl

DigitalReadout

ADC

Classical-Quantum IF

ClassicalRF-FE

X0 cm

Interface SoC

30Qubit

Challenges:✓ Proper cryo- (4K) and RF- (~20GHz) PDK✓ Low-power PLL and mixer✓ Isolation technique among blocks✓ New architecture for scalability
toward 1M qubits

DigitalC-Q IF C-Q IF … C-Q IF

Quantum

Prof. Tsuchiya(Shiga Pref. U.)

Long-term goal:
SoC in cryogenic environment

X mm
Moonshot Target6 "Quantum computer" by Kobayashi PM

Milestones⚫ Current status✓ Design basic block (e.g.: PLL) for various operating frequencies⚫ Cryo-CMOS RF PDK✓ High frequency characteristics at 4K, including passives (resistor, inductor, capacitor)✓ Challenges: measurement scheme and physical modeling➢ Special behavior in cryo and RF, ex. anomalous skin effect✓ Output: Establish RF circuit design environment at 4K⚫ RF frontend circuits for scalability✓ 10 GHz, <10 mW RF to meet 4K power budget✓ Output: Provide silicon-proven IPs of element circuits✓ Challenges: extremely low-power and high-isolation circuit/architecture

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Moonshot Target6 "Quantum computer" by Kobayashi PM

Theme3: Automatic Design/Synthesis of D/AConverter
Goal
Explore an appropriate architecture for low-power/high-speed/small-area
DAC by the automatic design/synthesis of the element circuit of DAC undercryo enviroments.
⚫ Automatic Design of DAC

Prof. Takai(KIT)⚫ Automatic Synthesis of DAC

GAN: Generative Adversarial Network
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Moonshot Target6 "Quantum computer" by Kobayashi PM

Automatic Design/Synthesis of D/A Converter
Milestone
2022: Building simulation, machine learning and DAC evaluation environment.
2023: Automatic design of DAC and verification of its operation through fabrication.
2024: Automatic design of high-speed DAC and operation verification through IC.
2025: Automatic design/synthesis of high-speed and high-resolution DAC andverification of its operation through IC.

Progress• Built an enviroment of high-speed simulation ,machine learning using GPU, and DAC circuit
evaluation.
• Training data are collected for automatic design.

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Moonshot Target6 "Quantum computer" by Kobayashi PM

Theme 4: High speed ADC for frontend
Reference
Voltage⚫ Milestone

Analog
Input

BUF

ADC

12

BUF

ADC

BUF

ADC

BUF

ADC

BUF

ADC

345626 735814Time

BUF

ADC

BUF

ADC

ADC CLK✓ Development of scalable ADC
architecture suitable for1interleaved operation✓ Development of calibration
techniques for channel-to-channel
mismatches with flexibility

ADC

Gain, BWControl⚫ Challenges

Analog input✓ 2022: Development of evaluation environment✓ 2023: Development and evaluation of a single ADC
operating at up to 12 bits, 1 GS/s
✓ 2024-2025: Development and evaluation of aninterleaving ADC operating at up to 12 bits, 6 GS/s

12bit

BUF

78

Cal. Logic
Serializer

N bit

LVDS

ADC Do7Cal. Logic
Serializer

LVDS

ADC Do6Cal. Logic
Serializer

LVDS

ADC Do5Cal. Logic
Serializer

LVDS

ADC Do4Cal. Logic
Serializer

LVDS

ADC Do3Cal. Logic
Serializer

LVDS

ADC Do2Cal. Logic
Serializer

LVDS

ADC Do1Cal. Logic
Serializer

LVDS

ADC Do0

Frame
Gen.

LVDS

Frame CLK

LVDS

Data CLKSPI

Timing Gen.

SPIInterface

Reference
CLK

Time-interleaved ADC (8x)34

Moonshot Target6 "Quantum computer" by Kobayashi PM

Prof. Miyahara(KEK)Progress status⚫ Development of ADC and measurement

Gain mismatch errorenvironment✓ Measurement environment➢ Installation of low noise analog and clock signal generators➢ Investigation of measurement system in Cryo environment✓ Circuit design

Without calibration➢ Investigation of ADC conversion schemes for interleaving➢ Investigation of calibration method using downscaling model➢ Circuit block design using 28/22nm PDK

15dB spur reduction

18.5μm2.3μm
28nm Comparator(Scaled to 22nm →85.5%)
35

With calibration

Downscaling interleaved ADC
10bit, 125MS/s×8ch=1GS/s

Moonshot Target6 "Quantum computer" by Kobayashi PMMismatch calibration

Summary⚫ Oj“QUC ”

TQC

1Mq.

✓ All upper layers above qubit are our targets: from error correction to qubit control✓ Current target is superconducting qubit from RIKEN⚫ 11(+1) PIs for these 4(+1) subjects (research topics)✓ Subject 1: Scalable error correction system (Backend)✓ Subject 2: Qubit Controller (Frontend)✓ Subject 3: Photonic/Cryo-CMOS Integrated Circuits✓ Subject 4: Cryo CMOS ASICs for Frontend/Backend✓ Subject 5: CMOS ASICs for Frontend at Room Temp. (will joinsoon)

RIKEN Quantum Computer

RIKEN superconducting qubit
https://rqc.riken.jp/en/
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Moonshot Target6 "Quantum computer" by Kobayashi PM