TND6237/D
Rev. 3, August − 2023

SiC MOSFETs:
Gate Drive Optimization© Semiconductor Components Industries, LLC, 2017

August, 2023 − Rev. 3

1

Publication Order Number:
TND6237/D

SiC MOSFETs:
Gate Drive Optimization

current capability. SiC and GaN each have mobility
parameters on the same order of magnitude as silicon,
making both materials well suited for high−frequency
switching applications. However, the parameter mostdifferentiating SiC is its thermal conductivity being morethan 3 times greater compared to silicon and GaN. Higher
thermal conductivity translates to lower temperature rise fora given power dissipation. The guaranteed maximum
operating temperature for commercially available SiC
MOSFETs is 150°C < TJ < 200°C. Comparatively, SiC
junction temperatures as high as 600°C are attainable but
mostly limited by bonding and packaging techniques. This
makes SiC the superior WBG semiconductor material forhigh−voltage, high−speed, high−current, high−temperature,switching power applications.

ABSTRACTFor high−voltage switching power applications, siliconcarbide or SiC MOSFETs bring notable advantages
compared to traditional silicon MOSFETs and IGBTs.
Switching high−voltage power rails in excess of 1,000 V,
operating at hundreds of kHz is non−trivial and beyond thecapabilities of even the best superjunction silicon
MOSFETs. IGBTs are commonly used but are restricted tolower operating frequencies due to their “tailing current”
and slow turn−off. As a result, silicon MOSFETs are
preferred for lower voltage, high−frequency operation while
IGBTs are better suited for higher voltage, high−current,
low−frequency applications. SiC MOSFETs offer the best
combination of high−voltage, high frequency, switching
performance benefits. They are voltage−controlled,
field−effect devices capable of switching the same highvoltages of an IGBT at or above the switching frequencies
of much lower voltage silicon MOSFETs.
SiC MOSFETs have unique gate drive requirements. In
general, they require a 20−V, VDD gate drive during theon−state to provide lowest on−resistance. Compared to theirsilicon counterparts, they exhibit lower transconductance,
higher internal gate resistance and the gate turn−on
threshold can be less than 2 V. As a result, the gate must be
pulled below ground (typically −5 V) during the off−state.
Understanding and optimizing the gate drive circuitry has
a profound effect on reliability and the overall switching
performance that can be achieved.
This paper highlights the unique device characteristics
associated with SiC MOSFETs. Critical design
requirements related to optimal gate−drive design for
maximizing SiC switching performance will be described.
System level considerations such as start−up, fault
protection and steady state switching will also be discussed.

Table 1. SEMICONDUCTOR MATERIALPROPERTIES
Properties

Si

4H−SiCGaN

Bandgap Energy
(eV)

1.12

3.26

3.50

Electron Mobility(cm2/Vs)

1400

900

1250

Hole Mobility(cm2/Vs)

600

100

200

Breakdown Field(MV/cm)

0.3

3.0

3.0

Thermal Conductivity(W/cm°C)

1.5

4.9

1.3

Maximum Junction
Temperature (°C)

150

600

400

SiC MOSFETs are commonly available in the range of
650 V < BVDSS <1.7 kV, with the majority focus being
1.2 kV and above. At the lower range of 650 V, traditional
silicon MOSFETs and GaN outperform SiC. However, one
reason to consider lower voltage SiC MOSFETs might be totake advantage of their superior thermal characteristics.
Although the dynamic switching behavior of SiC
MOSFETs is quite similar to standard silicon MOSFETs,
there are unique gate drive requirements dictated by theirdevice characteristics that must be taken into consideration.

INTRODUCTION
Silicon carbide (SiC) is part of the wide bandgap (WBG)
family of semiconductor materials used to fabricate discrete
power semiconductors. As shown in Table 1, conventional
silicon (Si) MOSFETs have a bandgap energy of 1.12 eVcompared to SiC MOSFETs possessing 3.26 eV.
The wider bandgap energy associated with SiC and (GaN)
Gallium Nitride means that it takes approximately 3 times
the energy to move electrons from their valence band to the
conduction band, resulting in a material that behaves more
like an insulator and less like a conductor. This allows WBG
semiconductors to withstand much higher breakdown
voltages, highlighted by their breakdown field robustness
being 10 times that of silicon. A higher breakdown fieldenables a reduction in device thickness for a given voltage
rating which translates to lower on−resistance and higher

SiC MOSFET CHARACTERISTICS
TransconductanceA silicon MOSFET used in a switching power supply
switches as quickly as possible between one of two
operating modes or regions. The cutoff region is definedwhere the gate−source voltage, VGS, is less than thegate−threshold voltage, VTH and the semiconductor is ina high blocking state. During cutoff, the drain−source
resistance, RDS, is high impedance and the drain current, ID= 0 A. The saturation region occurs when the MOSFET isfully enhanced, VGS >> VTH, and RDS(on) is at or near theminimum value, ID is maximum and the semiconductor is ina high conduction state. As highlighted by the red trace

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(4), shows that the resistance and therefore, conduction loss
is 2.3 times higher when operating at VGS = 12 V.
As a result, SiC MOSFETs perform best when applying amaximum gate−source voltage between 18 V < VGS < 20 V
and some can even be as high as VGS = 25 V. Operating a SiC
MOSFET at low VGS can result in thermal stress or possible
failure due to high RDS. The extenuating effect associatedwith the low gm cannot be overstated. It has a direct impact
upon several important dynamic characteristics that must be
considered when designing an adequate gate−drive circuit:specifically, on−resistance, gate charge (Miller plateau) andover−current (DESAT) protection.

shown in Figure 1, the transition between the linear (ohmic)
and saturation regions is very sharp and distinct, so that assoon as VGS > VTH, drain current flows through a relatively
low RDS. The transconductance, gm, is the ratio of thechange in drain current to the change in gate voltage anddefines the output to input gain of the MOSFET, which is theslope of the I−V output characteristic curve for any given
VGS.
gm +

I d
V GS

(eq. 1)

On−Resistance

As a WBG semiconductor, a SiC MOSFET presents
a lower associated on−resistance per unit area for a given
voltage. The on−resistance of a MOSFET consists of thecontributions from several internal, VGS dependent,
resistive elements. Most notable are the channel resistance(RCH), JFET resistance (RJ) and drift region resistance(RDRIFT). RCH has a negative temperature coefficient(NTC) and dominates RDS at lower VGS. Conversely, RJ andRDRIFT have a positive temperature coefficient (PTC) andare dominant at higher VGS levels. For VGS > 18 V, theon−resistance has a distinct PTC characteristic. However,during lower VGS, the on−resistance versus junction
temperature characteristic appears parabolic as shown in
Figure 2. Specifically at VGS = 14 V, where RCH isdominant, RDS appears to have a NTC characteristic where
resistance is decreasing with increasing temperature. This
unique distinction of a SiC MOSFET is directly attributed to
low gm. For a silicon MOSFET, whenever VGS > VTH, RDS
always has a PTC.

A
Si MOSFET

3.75

8.75

Figure 1. SiC MOSFET Output Characteristics

The slope for a silicon MOSFET I−V curve is steep in thelinear region (large ID) and nearly flat when operating insaturation so it experiences very high gain (high gm)
whenever VGS > VTH. The fact that ID is flat for a given VGS
means that the silicon MOSFET behaves much likea non−ideal current source when operating in saturation.
Conversely, it can be seen from the output characteristic
curves shown in Figure 1, that a SiC MOSFET does notexhibit a sharp transition between the linear and saturation
operating modes. In fact there is no defined “saturation
region” and from this point of view a SiC MOSFET behaves
more like a variable resistance than a non−ideal current
source. The I−V output characteristic of a SiC MOSFET
does not exhibit a large ID for a small VGS, therefore, SiC
MOSFETs are considered low gain (low gm) devices.
ID + gm(V GS * V TH)(eq. 2)The only way to compensate for the low gain and force
a large change in ID is to apply a very large VGS, which has
a profound impact on RDS. To further illustrate this point,consider the two operating points labeled A and B in
Figure 1.
8.75 V+ 438 mΩ, (V GS + 12 V)
20 A(eq. 3)3.75 VR DS(B) ++ 188 mΩ, (V GS + 20 V)
20 A(eq. 4)

R DS(A) +Figure 2. SiC MOSFET On−Resistancevs. Junction Temperature

The PTC attribute is heavily relied upon for current
balancing whenever two or more MOSFETs are placed inparallel, as would be the case for most high current
applications. During parallel operation, when one MOSFET
experiences a rise in junction temperature, the PTC causes
an increase in RDS, decreasing the current and forcing the

A fixed drain current of ID = 20 A, yields VDS = 8.75 V
when VGS = 12 V compared to VDS = 3.75 V when VGS isincreased to 20 V. Comparing the results of equations (3) and

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parallel MOSFET to take on additional current until anatural balance occurs. If two or more SiC MOSFETs wereplaced in parallel while operating with low VGS (negative
NTC), the result would be catastrophic. Therefore, parallel
operation between SiC MOSFETs is only recommended
when VGS is sufficient to ensure reliable NTC operation(typically VGS > 18 V).

designer more freedom to control VDS, dV/dt transitions byadding or reducing external gate resistance.
Gate Charge

When VGS is applied, a certain amount of charge istransferred to change the gate voltage between VGS(MIN)(VEE) and VGS(MAX) (VDD) as fast as possible. Since the
MOSFET internal capacitances are non−linear, a VGS
versus gate charge (QG) curve is helpful to identify how
much charge must be delivered for a given VGS level.
A typical gate charge curve for a SiC MOSFET is shown in
Figure 3.

Internal Gate Resistance

The internal gate resistance, RGI, is inversely proportional
to die size and for a given breakdown voltage, since a SiC
MOSFET die is much smaller compared to a silicon
MOSFET die, internal gate resistance tends to be higher.
The real benefit of the smaller SiC MOSFET die comes in
the form of lower input capacitance, CISS, which translates
to lower required gate charge, QG. Table 2 highlights several
important parameter comparisons between two different
manufacturers of SiC MOSFETS (SiC_1 and SiC_2) andtwo best in class, 900−V and 650−V super junction, Si
MOSFETs (Si_1 and Si_2).
Table 2. SEMICONDUCTOR MATERIALPROPERTIES
III.

SiC_1

SiC_2

Si_1
SJ FET

Si_2
SJ FET

BVDSS (V)

1200

1200

900

650

ID (A)

19

22

36

15

RDS (m)

160

160

120

130

QG (nC)

34

62

270

35

QGD (nC)

14

20

115

11

CISS (pF)

525

1200

6800

1670

COSS(pF)

47

45

330

26

VGS (V)−5 to 20

−6 to 22±20

±20

VGS(TH) (V)

2.5

2.8

3

3.5

RGI ()

6.5

13.7

0.9

1

RGIxCISS
(ns)

221

850

243

35

Figure 3. SiC MOSFET,
Gate−Source Voltage vs. Gate Charge

It is interesting that the Miller plateau for a SiC MOSFET
occurs at higher VGS and is not flat as would be expected fora silicon MOSFET. A non−flat Miller plateau implies that
VGS is not constant over the corresponding range of charge,
QG. This is another consequence arising from the low gm
associated with SiC MOSFETs. It is also notable that QG =0 nC does not occur at VGS = 0 V. VGS must be pulled below
ground (−5 V in this case) to fully discharge the gate of a SiC
MOSFET. A second reason to switch the gate negative
during turn−off arises from the fact that the worse case VTH
can be as low as low as 1 V. Switching VGS between 0V <VGS < VDD, with VTH ~ 1 V leaves no margin for inadvertentturn−on due to spurious gate noise or VDS, dV/dt−inducedturn−on. As a result, nearly all SiC MOSFETs require aminimum VGS of −5 V < VGS(MIN) < −2 V but somemanufacturers specify as much as −10 V.

From a gate drive viewpoint, it is interesting to compare
the RGIxCISS time constants. The Si_2 device has the lowest
time constant of 35 ns but is also a lower current, lower
voltage rated MOSFET. For comparison purposes the650−V, Si_2 MOSFET is interesting because the 1200−V,
SiC_1 sample has parameters closely matched but has asignificantly lower CISS at nearly twice the rated BVDSS. In
terms of BVDSS, the Si_1 sample is a closer comparison toeither of the SiC samples. Because of the low QG associatedwith SiC_1, the time constants between Si_1 and SiC_1 areclosely matched even though the internal gate resistance of
SiC_1 is 7 times higher.
Internal gate resistance limits the gate drive current thatcan be injected into the CISS. A high performance, SiC gate
drive circuit needs to provide extremely low output
impedance so that the driver does not become a limiting
factor by adding to the already high RGI. This allows the

DESAT Protection

DESAT protection is a type of over−current detection thatoriginated with circuits used to drive IGBTs. During theon−time, if the IGBT could no longer be held in saturation(“de−saturation”), the collector−emitter voltage would
begin to rise while the full collector current was flowing.
Obviously this would have a negative impact on efficiency
or in the worst case, could lead to failure of the IGBT.
Possible reasons for this might include: insufficient basewww.onsemi.com
4current due to beta tolerance or temperature effects or shortcircuit or overload operation. The purpose of the so called“DESAT” function is to monitor the collector−emitter
voltage of the IGBT and detect whenever such a potentiallydestructive condition is present.
Although the fault mechanism is slightly different, a SiC
MOSFET can suffer a similar fate where VDS can rise while
maximum ID is flowing. This undesirable condition canarise if the maximum VGS during turn−on is too low or thegate drive turn−on edge is too slow or a short circuit oroverload condition exists. The RDS can increase while thefull ID is present, causing an unexpected but slow rise in
VDS.
Because a SiC MOSFET does not operate in a clearly
defined saturation region, it never appears asconstant−current source. This can be problematic, as mostover−current protection schemes depend on a MOSFET
emulating a non−ideal, constant current source during anover−current condition. When a SiC MOSFET undergoes ade−saturation event, VDS responds very slowly, while themaximum drain current continues flowing through anincreasing on−resistance. As a result, it can be possible thatthe drain current could reach a level 10−20 times the
maximum rated pulse current (during high RDS), before thedrain−source voltage can respond. For a high−frequency
power converter, numerous switching cycles can occur
before a de−saturation fault is recognized. DESAT istherefore an important and necessary protection functionthat should be assigned as part of the gate drive circuitry, in
addition to any over−current protection that might also bepart of the power supply control.

ID

VDD
D
CDD
RHI

CGD
CDS

RGI

RGATE
G

CGS
S
VEE

Figure 4. SiC MOSFET Source Current

VDD(~20 V)
VGS
VGS(MP)(8 V)
VTH( V)t
VEE(3 V)

IG
t

VDS

t

SiC MOSFET DYNAMIC SWITCHING
Turn−OnID

The switching profile for a SiC MOSFET is very similar
to a Si MOSFET except for the main difference being the20−V gate−drive amplitude during turn−on and the fact thatthe gate must be pulled below ground during turn−off. The
turn−on transition requires a large, peak, source current
capable of charging the SiC internal gate capacitance as
quickly as possible to minimize switching loss. As an
estimate, the entire turn−on event should occur within t <10 ns, for a full VGS swing of VGS = 30 V and an estimated
CISS = CGS + CGD = 1000 pF which yields a required peakcurrent, IG(SRC)=3 A according to equation (5):I G(SRC) +(C GS ) C GD)
t

V GS

t

t0 t1

t2

t3

t4

Figure 5. SiC MOSFET Turn−On Sequencet0→t1: VGS ramps from VEE to VTH as the gate drive
circuit must deliver a large peak of instantaneous gate
current, IG(SRC), supplied primarily from the charge stored
in the gate driver bulk capacitor, CVDD. This time interval isoften referred to as “turn−on delay” since ID and VDS areunaffected while VGS is below VTH. Most of the gate current
is used to charge CGS and CGD. Notice from the schematic
diagram shown in Figure 4, the sourcing current flows
through three resistors, RHI, RGATE and RGI. RHI is theequivalent internal resistance of the driver source, RGATE is
the resistance of the trace impedance plus any additional(eq. 5)The turn−on transition for a SiC MOSFET is defined byfour distinct timing intervals, as shown in Figure 5. The
timing intervals shown in Figure 5 and Figure 7 arerepresentative of what would be expected from an ideal
clamped inductive switching application, typical of theoperating mode used in switching power supplies.

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5added dampening resistance and RGI is the SiC MOSFET
internal gate resistance. RHI and RGATE are on the order ofa few ’s but for a SiC MOSFET RGI can be on the order of
10’s of ’s which is an order of magnitude higher compared
to a high−voltage, Si MOSFET. Since these three resistors
form an RC time constant with the SiC internal gate
capacitance, sourcing adequate peak gate current isnecessary to assure a fast rising edge of the gate drive signal.
t1→t2: As VGS continues to ramp from VTH to the Miller
plateau, ID begins to increase through RJ + RDRIFT since the
RDS channel resistance is not fully enhanced at low VGS.
VDS remains at its maximum level because the SiC intrinsicbody−diode is not yet in the blocking state due to the low
value of ID and the high resistive state of RDS. It is advised
not to operate a SiC MOSFET with VGS < 13 V because of
the risk of thermal runaway due to the high RDS at low VGS.
Therefore, it is critical that the gate drive circuit be able totransition from VTH to VGS > 13 V as fast as possible. The
time spent for VTH < VGS < 13 V should be less than a few
ns to minimize ID2xRDS dynamic power loss.
t2→t3: VGS is at the Miller plateau which happens around
8 V for a SiC MOSFET. During this time the full load current
is flowing through RDS and the intrinsic body−diode nolonger in its blocking state, allowing the drain voltage to fall.
The channel resistance continues decreasing but RDS is still
dominated by RCH. Although the full load current is flowing
through the MOSFET drain, RDS remains quite high at thislow VGS. Therefore, it is imperative that VGS transition
through this region as quickly as possible. Since the speedof this transition is driven by IG, the peak drive current
capability during the Miller plateau (~ 1/2 VDD) region
should be more interesting than the peak rating shown on
any gate driver IC data sheets.
t3→t4: At VGS(MP) just near the end of the Miller plateau,
VDS falls to ID x RDS above zero. As VGS transitions from
~8 V < VGS < 20 V, the channel resistance, RCH, continues
to decrease and now RJ + RDRIFT are dominant over RCH,
resulting in a proportional decrease in VDS. Most SiC
MOSFETs become fully enhanced when VGS > 16 V but thelowest RDS value is ultimately determined by the final
maximum value of VGS. The remaining gate current, IG, issplit to fully charge CGD and CGS.

ID

VDD
D
CDD
RLO

CGD
CDS

RGI

RGATE
G

CGS
S
V

Figure 6. SiC MOSFET Sink Current

VDD(~20 V)
VGS
VGS(MP)(8 V)
VTH( V)t

VEE(3 V)

IG
t

VDS

t
ID

t

t0

t1

t2 t3 t4

Figure 7. SiC MOSFET Turn−Off Sequencet0→t1: VGS ramps down from VDD to the Miller plateau,
VGS(MP). The sink current, IG(SINK), is primarily supplied
from the charge stored in CGD and CGS while the gate driverbulk capacitor, CVDD, is recharged by VDD. The draincurrent, ID, remains unchanged. As VGS is decreasing, thechannel resistance is increasing causing a slight increase in
VDS by IDxRDS volts. The marginal increase in VDS would
be hardly noticeable except possibly near the end of the
t0→t1 time interval.
t1→t2: During this time interval, the provision of gate
current is dominated by CGD since the CGS capacitor sees anearly constant VGS. Across the Miller plateau, VDS
increases from ID x RDS to the VDS rail voltage where it isclamped by the SiC intrinsic body−diode. The drain current,

Turn−OffThe turn−off procedure for a SiC MOSFET is essentiallythe reverse of the turn−on sequence described previously.
The role of the gate drive circuit is to sink a large amount ofpeak current, capable of discharging the CGD and CGS
capacitance of the SiC MOSFET as quickly as possible. In
addition, the gate driver impedance during turn−off must be
as low as possible to hold the MOSFET gate low. This canbe especially problematic due to the low VTH associatedwith SiC MOSFETs. Not only does this necessitate the SiC
gate being pulled below ground but the sink current
capability of the gate driver must also be significantly higher
compared to the rated source current. The flow of gate drive
current, IG(SINK), is highlighted in Figure 6.

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1. A SiC MOSFET specifies an asymmetricalmax/min VGS near the range of +25 V/−10 V. The
gate drive circuit must be capable of providing
nearly the full range of 35 V, VGS swing to takefull advantage of the SiC performance benefits.
Most SiC MOSFETs will perform best whendriven between −5 V > VGS > 20 V. To cover thewidest range of available SiC MOSFETs, the gate
drive circuit should be able to withstand VDD = 25
V and VEE = −10 V
2. VGS must have fast rise and fall edges, on theorder of a few ns
3. Must be able to source high peak gate current on
the order of several amps, across the entire Miller
plateau region
4. Sink current capability is driven by the need toprovide a very low impedance hold−down or“clamp” as the VGS falls below the Miller plateau.
The sink current rating should exceed what would
be required by merely having to discharge theinput capacitance of a SiC MOSFET. A minimum,
peak sink current rating on the order of 10 A
should be considered appropriate to cover highperformance, half−bridge power topologies
5. Must have VDD under−voltage lockout (UVLO)
level that is matched to the requirement that VGS >~16 V before switching begins
6. Must have VEE UVLO monitoring capability toassure the negative voltage rail is within an
acceptable range
7. Must have a de−saturation function capable ofdetection, fault reporting and protection for longterm reliable operation of the SiC MOSFET
8. Low parasitic inductance for high−speed switching
9. Small driver package able to be located as close as
possible to the SiC MOSFET

ID, remains unchanged from the previous interval. Since
RDS is increasing due to VGS <1 3 V and VDS x ID
simultaneously appear across the MOSFET, the gate drive
circuit should be rated to sink a significant amount of current
during this time interval. During turn−off, this is the portionof the gate drive current that is most interesting to designers
since it is imperative to transition through the Miller plateau
region as quickly as possible.
t2→t3: As VGS continues to decrease from the Miller
plateau toward VTH, ID is ramping down to near zero during
this interval. VDS is now fully clamped to the drain voltage
rail by the SiC intrinsic body−diode which means the CGD
capacitor is fully charged. As a result, most of the sinkcurrent is now flowing through CGS.
t3→t4: ID and VDS remain unchanged. During the finalturn−off interval, the SiC internal input capacitors are notfully discharged until VGS falls below 0 V. Since VTH is only
~1 V and to fully discharge CISS, VGS must complete theturn−off sequence at a negative voltage. The importance ofthe gate drive circuit to provide as low impedance aspossible cannot be overstated. This is especially true forhigh−voltage, half−bridge power topologies where the
midpoint is pulled up by a high dV/dt when the high−side
MOSFET conducts. A low impedance pull−down isessential for preventing inadvertent, dV/dt−inducedturn−on.
In summary, the turn−on and turn−off switching states fora SiC MOSFET involve four distinct time intervals. The
dynamic switching waveforms shown in Figure 5 andFigure 7 are representative of ideal operating conditions. In
reality, package parasitics such as lead and bond wire
inductance, parasitic capacitances and PCB layout can havea profound effect on measured waveforms. Propercomponent selection, best PCB layout practices and anemphasis on providing a well−designed gate−drive circuit
are each essential for optimizing performance of SiC
MOSFETs used in switching power applications.

Without exception, the requirements for driving a SiC
MOSFET efficiently and reliably call for a very specific typeof gate driver. However, most reference designs currently
shown in the industry are designed based on using general
purpose low−side gate drivers. One such example is shownin Figure 8.

DISCRETE SiC GATE DRIVE
Compensating for the low gain while achieving efficient,high−speed switching imposes the following criticalrequirements for a SiC gate drive circuit:www.onsemi.com
7

Figure 8. Standard Low−Side Driver, SiC Discrete Gate Drive Design Example

drivers are rated for a maximum VDD = 20 V, may notprovide adequate source/sink current and may not be
available in low inductance packages, selection can belimited to only a few specific choices.
These types of gate drivers are intended to drive silicon
MOSFETs and from this point of view, they lack several
important requirements needed for SiC MOSFETs. For
example, there is no over−current fault reporting or DESAT
monitoring function available from these gate drivers. Also,
the UVLO thresholds of generic gate drivers are typicallydefined based on 5 V < VDD < 12 V. This could be
problematic since the “safe” VDD operating level for a SiC
MOSFET is approximately VDD > ~16 V at startup. And
there is no UVLO monitoring available for the VEE voltage
rail as shown in the reference design of Figure 8. Standard
Low−Side Driver, SiC Discrete Gate Drive Design
Example. These voltage rails would need to be monitored
elsewhere to assure that levels are acceptable for driving the
SiC MOSFET into a low resistive state during turn−on andholding the gate below ground during turn−off.
Although the solution shown in Figure 8 provides thenecessary functions for driving a SiC MOSFET, it isincomplete, at least according to the gate drive requirements
stated at the beginning of section Discrete SIC Gate Drive.
Nonetheless, without a dedicated SiC driver, most SiC gate
drive circuits are presently designed this way. Any
additional functions such as DESAT, voltage rail
monitoring, sequencing, etc are either handled by additional
dedicated circuits or ignored all together.

The circuit shown is floating with respect to ground so it
can be used as either a low−side or high−side referenced gate
drive. For either case, in the event of a power stage failure,isolation is desired to protect the control circuitry from thehigh−voltage seen at the power stage. Two isolated dc−dc
converters, PS1 providing VDD = 24 V (post−regulated to 20V) and PS2 configured to regulate at VEE = −5 V, are used
to provide the VDD and VEE voltage rails. It should also bementioned that these converters are dedicated to driving asingle SiC load and so two would be needed for each SiC
load. This is especially true for high−side gate drive
applications such as the upper switch in a half−bridge,full−bridge or motor drive application. The voltage seen by
the main driver, U1, is floating by several hundred volts andis very susceptible to the high dV/dt associated with aswitching SiC MOSFET. Assuming a dV/dt=100 V/ns, withjust 1 pF of stray parasitic capacitance across the isolation
barrier of the PS1 (or PS2) transformer results in 100 mA ofpeak current. 100 mA per pF emphasizes the need for low
parasitic capacitance, low stray inductance and tightcoupling between the VEE (and VDD) voltage rails and thegate driver IC.
The digital isolator, U2, isolates the gate drive signal fromthe power stage and also provides the necessary level
shifting. The secondary side of U2 is then used as the input
to main driver, U1. U1 is a generic, low−side gate driver but
must be rated to handle the full VGS voltage swing of 25 V(−5 V < VGS < 20 V) and provides the desired source/sinkcurrent levels. Since most general purpose, low−side gate

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NCP51705 SiC GATE DRIVER
The NCP51705 is a SiC gate driver that includes a highlevel of flexibility and integration making it fullycompatible with any SiC MOSFET in the market. The
NCP51705 top level block diagram, shown in Figure 9,
includes many basic functions common to what might be
expected from any general purpose gate driver, including:
1. VDD positive supply voltage up to 28 V
2. High peak output current of 6 A source and 10 A
sink
3. Internal 5 V reference made accessible for biasing
5 V, low−power loads up to 20 mA (digitalisolator, opto−coupler, C, etc)
4. Separate signal and power ground connections
5. Separate source and sink output pins
6. Internal thermal shutdown protection
7. Separate non−inverting and inverting TTL, PWM
inputs

NCP51705
DESAT Function
200 ADESAT 22

23

100 k
Q S
Q R
1.25 V

5V REGDESAT /CURRENTUVSET 24

20

DESAT
/CS
VDD

19

VDD

22

UVLO
TSD

DESAT_FLT
RUN_OKVDD UVLOVEE UVLO
V5V_OK

1

IN−

2

DRIVER
LOGIC
&
LEVEL
SHIFT

XEN 3

17 OUTSRC
14 OUTSNK
13 OUTSNKCHARGE
PUMP REG CPCLK

16 PGND

CHARGE PUMP
POWER STAGE

5

6

7

8

11

12

VCH

C+

C−

VEE

VEE

PGND

15 PGND
9VEESET

SGND 4

10

18

SiC
Drive

OUTSNK

17

VDS
Q1

14
13

During the time that Q1 is off several hundred volts canappear across the drain−source terminals. Once Q1 is turned
on, the drain−source voltage rapidly falls and this transition
from high−voltage to near zero voltage is expected tohappen in less than a few hundred nano−seconds. During theturn−on transition, the leading edge of the DESAT signal isblanked by a 500−ns timer, consisting of a 5−, low
impedance pull−down resistance. This allows sufficient
time for VDS to fall while at the same time ensuring DESAT
is not inadvertently activated. After 500 ns, the DESAT pin
is released and the 200−A current source provides aconstant current through R1, D1 and the SiC MOSFET
on−resistance. During the on−time, if the DESAT pin rises
above 7.5 V, the DESAT comparator output goes HIGH
which triggers the clock input of an RS latch. Such a fault
will automatically terminate the trailing edge of the Q_NOT
output on a cycle−by−cycle basis. The gate drive to the SiC
MOSFET is thereby effectively reduced by an amount oftime proportional to the de−saturation fault time.
The 200−A current source is sufficient to ensure
a predictable forward voltage drop across D1 while also
allowing the voltage drop across R1 to be independent of
VDS during the on−time of the SiC MOSFET. If desired,
DESAT protection can be disabled by connecting the
DESAT pin to ground. Conversely, if the DESAT pin is left
floating, or R1 fails open, the 200−A current source
flowing through the 20−k resistor, puts a constant 4 V on
the non−inverting input of the DESAT comparator. Thiscondition essentially disables the gate drive to the SiC

18 OUTSRC
INPUT
LOGIC

PGND

IN+

I

Figure 10. NCP51705 DESAT Function

RUN

PROTECTION
LOGIC

D1

500ns
Timer

OUTSRC

5V_OK
VDD_OK
VEE_OK

20 k
Remove(Option)5IN

21 SVDD

25 A

R1

3.3 V

NCP51705
V5V

VDD

Figure 9. NCP51705 SiC Gate Driver Block Diagram

In addition, the NCP51705 is differentiated by several
unique features (listed at the beginning of section Discrete
SIC Gate Drive) necessary for designing a reliable SiC
MOSFET gate drive circuit using minimal external
components. The advantages of the NCP51705
distinguishing features are detailed in the following section.
Over−Current Protection − DESAT

The implementation of the NCP51705 DESAT function
can be realized using only two external components. As
shown in Figure 10, the drain−source voltage of the SiC
MOSFET, Q1 is monitored via the DESAT pin through R1
and D1.

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9

MOSFET. Some applications may prefer to sense the draincurrent using a current sense transformer and drive the
DESAT pin externally. In this case the NCP51705 includes
an IC metal option to remove the 20−k resistor, allowing
the DESAT pin to be used as a traditional pulse−by−pulse,over−current protection function.
The voltage on the DESAT pin, VDESAT, is determined byequation (6) as:
V DESAT + (200 AR 1) ) V D1 ) (I D

5

V DESAT ) V D * (I D1
200 AR DS)

VEESET
VDD

GLDO

LDO
9V
6

CCH

VCH
P

P

N

N

ID

R DS) (eq. 6)

SiC
Drive

After assigning the maximum value for ID (plus allowing
any additional design margin) R1 and ID are selected suchthat VDESAT < 7.5 V. Rearranging equation (6) and solving
for R1 gives:
R1 +NCP51705
VEE Charge
Pump(SINK)

VDS
14

Q1

13

OUTSNK
C

C

7

CF(eq. 7)

In addition to setting the maximum allowable VDESAT
voltage, R1 also serves the dual purpose of limiting the
instantaneous current through the junction capacitance of
D1. Because the drain voltage on the SiC MOSFET sees
extremely high dV/dt, the current through the p−n junction
capacitance of D1 can become very high if R1 is not sized
appropriately. Therefore, selecting a fast, high−voltage
diode with lowest junction capacitance should be a priority.
Typical values for R1 will be near the range of 5 k < R1 <10 k but this can vary according to the ID and RDS
parameters of the selected SiC MOSFET. If R1 is muchsmaller than 5 k, the instantaneous current into the DESAT
pin can be hundreds of milliamps. Conversely, if R1 is muchlarger than 10 k, a RC delay ensues as a product of R1 andthe junction capacitance of D1. The delay can be on the orderof 100 s, resulting in an additional delay time responding
to a DESAT fault.

VEE
8

11

12

CVEE

Figure 11. NCP51705 VEE Charge Pump

An external flying capacitor, CF, is connected between the
midpoints of each leg of the bridge as shown. The switch
timing is such that whenever the two upper PMOS devices
are conducting simultaneously, VDD appears across CF.
Similarly whenever, the two lower NMOS devices are
conducting simultaneously, −VEE appears across CF. The
switching frequency is internally set at 390 kHz, with thetwo upper PMOS devices switching asynchronous withrespect to the two lower NMOS devices. A 290 kHz, IC
metal option is also available for applications desiring alower charge pump switching frequency.
VEE is regulated to the voltage set at VCH which isdetermined by the internal low dropout regulator (LDO)
voltage, programmable by VEESET. The voltage present at
VEESET varies the gain (GLDO) seen by the internal LDO.
If VEESET is left floating (a 100−pF bypass capacitor fromVEESET to SGND is recommended), then VEE is set toregulate at −3 V. For a −5−V VEE voltage, the VEESET pinshould be connected directly to V5V (pin 23). If VEESET
is connected to any voltage between 9 V and VDD, then VEE
is clamped and set to regulate at the minimum charge pumpvoltage of −8 V. The charge pump starts when VDD > 7.5 V
and the VEE voltage rail includes an internally fixed UVLO
set to 80% of the programmed VEE value. Since VDD and
VEE are each monitored by independent UVLO circuits, theNCP51705 is smart enough to realize when both voltage
rails are within limits deemed safe for a given SiC MOSFET
load.
Alternatively, 0 V < OUT < VDD switching can beachieved by disabling the charge pump entirely. WhenVEESET is connected to SGND the charge pump is
disabled. With the charge pump disabled and VEE tied

Charge Pump – VEE (VEESET)The NCP51705 operates from a single, positive supply
voltage. Operating from a single VDD supply voltage
implies the negative VEE voltage must be generated from thegate driver IC. The use of a switched capacitor charge pumpis a natural choice for producing the required negative VEE
voltage rail. There are many different options forarchitecting a charge pump. The main challenges aremaintaining accurate voltage regulation during transientconditions, switching at a frequency to decrease the size ofcapacitors and minimize external component count, thereby
reducing cost and increasing reliability.
As can be seen from the charge pump functional block
diagram shown in Figure 11, only three external capacitors
are required to establish the negative VEE voltage rail. The
charge pump power stage essentially consists of two PMOS
and two NMOS switches arranged in a bridge configuration.

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10

The UVSET resistor, RUVSET, is chosen according toa desired UVLO turn−on voltage, VON, as defined inequation (8).

directly to PGND, the output switches between 0 V < OUT< VDD. It is important to note that whenever VEESET is tied
to SGND, VEE must be tied to PGND. During this mode ofoperation the internal VEE UVLO function is also disabledaccordingly.
Another possible configuration is to disable the charge
pump but allow the use of an external negative VEE voltage
rail. This option permits –VEE < OUT < VDD switching witha slight savings in IC power dissipation, since the charge
pump is not switching. With VEESET connected to SGND,
an external negative voltage rail can be connected directly
between VEE and PGND. A word of caution, since VEESET
is 0 V, the internal VEE UVLO is disabled and therefore the
NCP51705 is unaware if the VEE voltage level is within the
expected range.
This simple VEESET adjustment enables the highest
degree of flexibility using the fewest external components
while meeting the broadest range of SiC MOSFET voltage
requirements. For convenience, the configurability of
VEESET is summarized in Table 3.

R UVSET+(eq. 8)25 A

NCP51705
UVSET Function
V5V
25 A

G UVSET=6UVLO

Table 3. SEMICONDUCTOR MATERIALPROPERTIESUVSETRUVSET
24

Figure 12. NCP51705 UVSET Programmable UVLOVEEVEESET

COMMENTVEE(UVLO)

VDD

9 V < VEESET < VDD−8 V−6.4 V

V5V

V ON
6

−5 V

−4 V

OPEN

Add CVEE (100 pF) fromVEESET to SGND

−3 V

−2.4 V

GND

Remove CVEE andconnect VEE to PGND

0V

NA

GND

Connect VEE toexternal negative
voltage supply

−VEXT

NA

The value for VON is typically determined from the SiC
MOSFET output characteristic curves, such as thosehighlighted in Figure 1. Because the on−resistance of a SiC
MOSFET dramatically increases even for a slight decrease
in VGS, the allowable UVLO hysteresis must be small. For
this reason, the NCP51705 has a fixed 1−V hysteresis so thatthe turn−off voltage, VOFF, is always 1 V less than the set
VON.
For power supplies that include a dedicated housekeeping
bias supply, VDD is assumed to be above the desired VON
threshold before the power system initiates soft−start or
restart due to a fault recovery. For such systems, having
a 1−V UVLO hysteresis is desirable and should not have any
impact due to start−up considerations. However, somepower systems start from a high−voltage and then rely on
VDD from a bootstrap winding as shown in Figure 13.

Programmable Under Voltage Lockout − UVSETUVLO for a gate driver IC is important for protecting the
MOSFET by disabling the output until VDD is above aknown threshold. This not only protects the load but verifies
to the controller that the applied VDD voltage is above theturn−on threshold. Because of the low gm value associatedwith SiC MOSFETs, the optimal UVLO turn−on threshold
is not a “one size fits all.” Allowing the driver output toswitch at low VDD can be detrimental for one SiC MOSFET
but may be acceptable for another depending onheat−sinking, cooling and VDD start−up time. The optimal
UVLO turn−on threshold can also vary depending on how
the VDD voltage rail is derived. Some power systems may
have a dedicated, housekeeping, bias supply while others
might rely on a VDD bootstrapping technique similar to
Figure 13.
The NCP51705 addresses this need through a
programmable UVLO turn−on threshold that can be set witha single resistor between UVSET and SGND. As shown in
Figure 12, the UVSET pin is internally driven by a 25−Acurrent source with a series gain of 6.

HV

VCC/VDD

HV
PWM
17 VON9 VOFF

VCC

VDD
C

NCP51705
VON<VON(PWM)
VOFF=VON−1 V Q1

Figure 13. PWM Bootstrap Start−Up Example

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11

Digital Synchronization and Fault Reporting – XEN

A PWM controller with high−voltage (HV) start−up
capability and fixed UVLO thresholds of VON = 17 V and
VOFF = 9 V is shown. As HV is applied, the internal pass
switch opens when HV = VON = 17 V and the PWM
controller draws start−up current from CVCC. During thistime, CVCC is discharging and Q1 must begin switching tobuild up voltage in the transformer bootstrap winding. This
imposes a restriction on the allowable VON that can be
programmed from RUVSET. UVSET must be set to a valueless than the UVLO VON of the PWM controller. These
start−up details are further illustrated in Figure 14 where thePWM voltage thresholds are shown in blue and the
NCP51705 in red.

The XEN signal is a 5 V digital representation of theinverse of VGS. For the purpose of reporting driver “status”,
it is considered more accurate that the PWM input since it isderived from the SiC gate voltage, propagation delays are
greatly decreased. The intent of this signal is that it can beused in half−bridge power topologies as a fault flag andsynchronization signal as the basis for implementing crossconduction (overlap) protection. Whenever XEN is HIGH,
VGS is LOW and the SiC MOSFET is OFF. Therefore if
XEN and the PWM input signal are both HIGH, a fault
condition is detected and can be digitally assigned to takewhatever precautions might be desired.

V

Packaging
V PWM(MAX)27

WBG semiconductors have enabled high−voltage
converters to operate much closer to low−voltage (less than
100 V) switching frequencies. For low−voltage converters,
the evolution of semiconductor packaging played a key role
toward the modern achievement of switching performance
seen today. Dual−sided cooling, clip bonding, thermallyenhanced power packages and lower inductance, leadlesspackages are a few examples of silicon MOSFET packaging
advancements. Similarly, the size of gate driver IC packages
has undergone a tremendous size reduction. Shorter die tolead, bond wire connections combined with molded leadlesspackages (MLP) have been essential for minimizing
parasitic inductance from the driver side. The co−packagingof the driver and MOSFET (DrMOS) is the latest step
toward reducing parasitic inductance, raising efficiency andreducing board area. Advancements such as DrMOS areachievable because of the comparable low−voltages
involved.
In the high−voltage converter realm, minimum spacing
requirements such as creepage and clearance have left highperformance SiC MOSFETs stuck in low−performanceTO−220 and TO−247 type packages. These packages arewell established and have long been an industry standard.
They are well suited for industrial applications, robust andeasy to heat sink but have higher parasitic inductance due totheir long leads and internal bond wires. SiC MOSFETs
have now subjected these parasitic inductances to thermal
stresses, frequencies and dV/dt rates never before
envisioned with high−voltage, silicon transistors. Suffice tosay, SiC is providing the stimulus for rethinking
high−voltage discrete packaging.
Although not the case with discrete components, a SiC
gate driver is able to take full advantage of the same

VSIC(MAX)
VBOOT(REG)2220
V PWM(ON)1716

17 VON/16 VOFF
12 VON /11 VOFF

12
11
9

V BOOT(MIN)0t1

V PWM(OFF)t2tFigure 14. Bootstrap Start−Up Timing

For the purpose of switching the SiC MOSFET with thehighest possible VGS, it is desired to set VON as close to the
UVLO turn−on of the PWM controller as possible. The trade
off in doing so means V = 1 V during t (t2−t1). The
discharge of CVCC is very shallow so a large capacitor value
is required. For example, assuming the start−up current to be
1 mA, t = 3 ms and V = 1 V, a 3−F capacitor for CVCC
is required. Conversely, if VON is set to 1 V above theminimum bootstrap discharge voltage, VBOOT(MIN), CVCC
is allowed to discharge over a wider V (17 V − 11 V) anda much smaller capacitor value can be used. Given the same
1 mA, t = 3 ms and allowing V = 6 V, the required CVCC
capacitor value is reduced to 500 nF; a reduction by a factorof 6. However, the incurred penalty can be quite severe as the
SiC MOSFET will be switching with VGS = 11 V. Clearly,
having the NCP51705 biased prior to start−up is thepreferred approach.

www.onsemi.com
12the V5V regulator. For 7 V < VDD < 22 V, IDD was measured
to be 0.6 mA < IDD < 2.3 mA. The flat line across the middle
is a ~1−mA increase in IDD current when VDD crosses the
UVLO threshold.
The red trace represent the case where a 100 kHz, 50%
pulsed input was applied to IN+ while the internal charge
pump is disabled. A 4.99  + 2.2 nF load was used which isthe equivalent input for a typical SiC MOSFET. The externalsource and sink resistance was 3. For 12 V < VDD < 22 V,
IDD was measured to be 3.7 mA < IDD < 5.5 mA.

IN+

19 VDD

20 VDD

21 SVDD

22 DESAT / CS

23 V5V

24 UVSET

packaging advancements used with drivers intended forlow−voltage converters. The NCP5170 die is packaged intoa 24 pin, 4 × 4 mm, thermally−enhanced MLP as shown in
Figure 15.

1

18 OUTSRC

2

17 OUTSRC

XEN

3

SGND

4

16 PGND

NCP51705(Top View)

NCP51705, VDD vs IDD
I_V5V = 0 mA, OUT_Load = 3  + 4.99  + 2.2 nF

15 PGNDVEESET 5

14 OUTSNKVCH

13 OUTSNK

25

20

VEE 1215

VDD (V)

9PGND

VEE 118

PGND 10

7
C+

C−

6

Figure 15. NCP51705 24 pin, 4  4 mm, MLP
Packaging and Pin Out

10Non− Switching
0 V<OUT<VDD, 100 kHz, 50%

5All the high−current, power pins are doubled and locatedon the right−half of the IC. In addition to doubling the pins,
each doubled pin connects to the die through internal doublebond wires for achieving the lowest possible inductance. All
low−power, digital signals are single pins only and arelocated on the left−half of the IC, providing a convenient,direct interface to the PWM or digital controller.
The bottom of the NCP51705 package consists of anelectrically isolated, thermally conductive, exposed pad.
This pad is not connected to PGND or SGND but is intended
to be connected through thermal vias to an isolated copper
PCB land for heat−sinking.
If thermal dissipation becomes a concern, specificattention should be paid to four dominant power dissipation
contributors:
1. OUTSRC and OUTSNK losses associated withdriving the external SiC MOSFET. These are gatecharge related losses proportional to switchingfrequency. Reducing switching frequency will
decrease power dissipation
2. LDO between VDD and V5V, capable of sourcing
up to 20 mA. Do not load the V5V any more thanbiasing a digital isolator or optocoupler
3. LDO between VDD and VCH which is part of theinternal charge pump
4. Internal charge pump power switches which canbe disabled and replaced with an external negative
bias, as mentioned in section Charge Pump–VEE

0
0.0

1.0

2.0

3.0

4.0

5.0

6.0

IDD(mA)

Figure 16. VDD versus IDD,
Non−Switching versus Switching

The start−up waveform shown in Figure 17 shows IN +appearing prior to VDD. VDD is rising from 0 V to 20 V, withUVSET = 2 V (not shown) which equates to VDD(UVLO) =12 V. VEE is set to regulate at −5 V with VEESET = V5V (notshown) which equates to VEE(UVLO) = −4 V. The output isenabled when VEE = −4 V, even though VDD > 12 V (VDD
= 15 V). Notice also that OUT (VGS) is less than 20 V for
almost 100 s. Depending on the dV/dt rate of VDD start−up,
this time could be longer and therefore, the thermal stress to
the SiC MOSFET should be taken into consideration when
programming UVSET.

(VEESET)SYSTEM PERFORMANCEFor VDD > 7 V, the quiescent current ramps up linearly
until the set UVLO threshold is crossed. The blue trace
shown in Figure 16, represents VDD versus IDD with no input
applied (non−switching), VDD(UVLO) = 12 V and no load on

Figure 17. CH1−IN+, CH2−VDD, CH3−OUT, CH4−VEE;
VDD(UVLO) = 12 V, VEE(UVLO) = −4 V

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13

The same start−up waveform is shown in Figure 18 but
UVSET = 3 V (not shown) which equates to VDD(UVLO) =18 V. In this case, OUT (VGS) is enabled when VDD = 18 V,
even though VEE < −4 V (VEE = −5 V). Which UVLO isdominant will depend on the dV/dt rate of VDD versus VEE.
The key point is that the NCP51705 output is disabled until
both, VDD and VEE are above and below their respective
UVLO thresholds. Compared to Figure 17, notice the effectthat a higher UVLO setting has on OUT (VGS), where thefirst OUT pulse appears near 20 V and −5 V.

is unloaded. The discharge time from −5 V to 0 V for VEE
is approximately 300 ms.

Figure 20. CH1−IN+, CH2−VDD,
CH3−OUT, CH4−VEE; Shut−Down

A zoom of the time base from Figure 20 is shown in

Figure 21. UVSET is configured for 3 V (VDD(UVLO) = 18
V) and the internal VDD UVLO hysteresis is internally fixedat 1 V. The curser position reveals that VDD = 17 V (18 V−1
V hysteresis), when the output is disabled, even though VEE= −4.5 V (VEESET = V5V) and is still active according it’s
−4 V UVLO. Although the decay of VDD is slow, a clean
termination of the last output pulse can also be observed withno spurious pulses or glitches after UVLO_OFF.

Figure 18. CH1−IN+, CH2−VDD, CH3−OUT, CH4−VEE;
VDD(UVLO) = 18 V, VEE(UVLO) = −4 V

The NCP51705 internal charge pump has a slow control
loop and the effect of this is seen by the slight undershoot and<400 s correction observed during VEE start−up shown in
Figure 19. Beyond 400 s, the VEE voltage settles to theregulation set point of −3 V, −5 V or −8 V.

Figure 21. CH1−IN+, CH2−VDD, CH3−OUT, CH4−VEE;
Shut−Down, VDD_UVLO(OFF) = 17 V

The turn−on propagation delay is measured from 90%
IN+ rising to 10% OUT rising. Although a SiC driver will
operate at higher VDD, most MOSFET propagation delays
are specified switching into a 1−nF load with VDD = 12 V.

Figure 19. VEE Start−Up

Shutdown operation is smooth with no glitches. As shownin Figure 20, OUT ceases switching and tracks VEE whichwww.onsemi.com
14

external capacitor can be used on the DESAT pin forhigh−frequency noise filtering.
The XEN signal is the inverse of the OUT signal. Whether
the driver is operating normal or under a DESAT fault, theXEN signal is shown to accurately track the inverse OUT
signal for either case.

Figure 22 shows the measured turn−on, propagation delay,
under these standard test conditions, to be 19 ns.

Figure 22. CH1−IN+, CH2−VDD, CH4−OUT;
Rising Edge Prop Delay

Similarly, the turn−off propagation delay is measured
from 10% IN+ falling to 90% OUT falling. Figure 23 shows
the measured turn−off, propagation delay under the same
standard test conditions is 22 ns. The output rise and falltimes for each edge are approximately 5 ns.

Figure 24. CH1−IN+, CH2−OUT, CH3−DESAT,
CH4−XEN; VDESAT < 7.5 V

Figure 25. CH1−IN+, CH2−OUT, CH3−DESAT,
CH4−XEN; VDESAT = 7.5 V
Figure 23. CH1−IN+, CH2−VDD, CH4−OUT;
Falling Edge Prop Delay

APPLICATIONS
SiC MOSFETs can penetrate any application spaces
where IGBTs are presently used. Some of the more common
uses include high−voltage switching power supplies, hybrid
and electric vehicle chargers, electric railway
transportation, welders, lasers, industrial equipment andenvironments where high−temperature operation is critical.
Two areas that are particularly interesting for SiC are solar
inverters and high−voltage data centers. Higher dc voltages
are beneficial for reducing wire gauge thickness, junction
boxes, interconnections and ultimately minimizing
conduction loss thereby increasing efficiency. Most
large−scale, photovoltaic systems currently operate from a
1−kV dc bus and the trend is moving toward a 1.5−kV bus.
Similarly, data centers using a 380−V distribution network
can boost dc voltages as high as 800 V.

The DESAT and XEN waveforms are shown in Figure 24
and Figure 25 respectively. Since testing was done to verify
IC validation only (no power stage), a 100−pF, fixedcapacitor is connected to the DESAT pin. The waveforms
shown in Figure 24 indicate DESAT is below the 7.5 V
threshold and the output is switching under normal
operation. If the IN+ frequency is decreased (increased
on−time), the 100−pF DESAT capacitor will be allowed tocharge to a higher voltage. This is shown in Figure 25 where
the DESAT voltage has reached the 7.5−V threshold. The
output trailing edge is terminated before the input voltage
switches LOW. A shallow DESAT ramp is used to highlightthe fact that no glitches appear on the terminated OUT pulse.
In a switching power supply application, a small (<100 pF)

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15the need for two digital isolators. Depending on the amountof IO crossing the isolation boundary, a strong debate forsecondary−side control could be made for such applications.
In this simplified example, IN+ and IN− (Enable) are theonly two signals sourced from the digital controller and
XEN is read back from the NCP51705. XEN is can be usedas the timing information basis for developing gate drive
timing, cross conduction prevention, dead−time adjustment
and fault detection. In addition, temperature sensing,thermal management (fan control) and higher levels of fault
response may also be done by the digital controller. The
V5V from the NCP51705 can be used to power thesecondary side of each digital isolator as shown Figure 27.

Several fundamental application examples highlighting
the NCP5170 are shown as follows.
Low−Side Switching

Figure 26 shows a top level schematic highlighting the
NCP51705 used in a low−side switching application. No
isolation is shown so the interface between the controller anddriver is direct, though this may not always be the case. This
schematic is shown to raise awareness of how few external
components are required to provide a fully functional,
reliable and robust SiC gate drive circuit. It should also bementioned that although only a single VDD voltage rail isrequired it should be rated for at least 50 V/ns to prevent
spurious current pulses described in the discrete gate drive
description in section Discrete SIC Gate Drive. If the VDD
voltage rail is provided by a dedicated auxiliary
housekeeping power supply, special attention should begiven to design a transformer featuring ultra−low,primary−secondary stray capacitance.

CONTROLLER BIAS (3.3 V or 5 V)

Digital Controller
FAULT_HS

XEN_HS

SVDD

VDD

VDD

21

20

19

22

V5V
23

PWM_LS

17
16

NCP51705(Top View)

15

9

10

11

12

PGND

PGND

VEE

VEE

8

7
C+

OFF
−3.5 V
−5 V
−8 V

C−

VCH 6
VEESET=SGND
VEESET=OPEN
VEESET=V5V
VEESET=SVDD

OUTSRC
XEN_LSOUTSRC
PGND
PGND

14 OUTSNKOUTSNK
13

5

DigitalIsolators ISOLATOR BIAS

FAULT_LS

18

SGND 4VEESET

DESAT

UVSET
24

ENABLE

IN+ 1
IN−
2
XEN 3

20 V BIAS (isolated)

PWM_HS

20 V

Controller

ISOLATOR BIAS

Isolation
Boundary

Figure 27. Half−Bride Concept
Quasi Resonant (QR) Flyback

A 100−W, QR flyback converter operating from a wide
input range of 300 V < VIN < 1 kV was designed using the
NCP1340B1 controller and NCP51705 SiC driver.
Converters of this class can typically be found inphotovoltaic and industrial applications but when based on
IGBT power stages, switching frequencies are in the rangeof 65 kHz. The schematic shown in Figure 28 is a QR
flyback and the frequency is varying between 377 kHz < FS
< 430 kHz, from 100% to 25% load, at VIN = 300 V.

Figure 26. Low−Side Switching Example
Half−Bridge Concept

A more realistic use of SiC MOSFETs can be found inhalf−bridge power topologies such as the one shown in
Figure 27. High power applications tend to prefer isolated
drivers for both, the high−side and low−side. This implies

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16

Figure 28. 1000 V to 24 V, 100 W, 400 kHz, QR Flyback
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17

For VIN = 300 V, the drain−source voltage waveform is thesum of the input voltage and the reflected output voltage.
The waveform shown in Figure 29 highlights the converter
operating at full duty cycle operation (VIN = 300 V) with 720
V appearing on drain−source of the SiC MOSFET. The VDS
rising transition is ~30 ns which equates to dVDS/dt = 24
V/ns. The NCP1340B1, QR control enables a soft, resonanttransition and valley switching (“near ZVS” turn−on atminimum VDS resonance) on the VDS falling edge and thisis clearly visible on the blue waveform. Because the
QR−flyback is a low−side only application and the fallingdVDS/dt edge is resonant, it may be possible for the SiC
MOSFET to reliably switch between 0 V < VGS < 20 V.
Nonetheless, the design shown in Figure 28 opted forswitching between −5 V < VGS < 20 V resulting in morerobust switching at the slight penalty of increased gatecharge.

Figure 30. NCP5170 Mini EVB Schematic

Figure 29. CH3 = VDS, CH4 = VGS; VIN = 300 V, VOUT
= 24 V, IOUT = 4 A, FS = 377 kHz

General Purpose NCP5170 Customer EVB

A general purpose evaluation board (EVB) has been
designed for the purpose of evaluating the NCP51705
performance in new or existing designs. The EVB does notinclude a power stage and is generic from the point of viewthat it is not dedicated to any particular topology. It can beused in any low−side or high−side power switching
application. For bridge configurations two or more of these
EVBs can be used at each SiC MOSFET in a totem pole typedrive configuration. The EVB can be considered as an
isolator + driver + TO−247 discrete module. The EVB
schematic is shown in Figure 30.
The focus is to provide an ultra−compact design, where
the leads of a TO−247 SiC MOSFET can be connected
directly to the printed circuit board (PCB). Figure 31 shows
simultaneous, top and bottom views of the EVB next to an
adjacent TO−247 package for size scaling.

Figure 31. NCP5170 Mini EVB –Top View (35 mm x 15 mm)

When mounting into an existing power supply design andthere is available PCB area in front of the TO−247, the EVB
can be installed horizontally to the main power board, as
shown in Figure 32. If possible, this should is the preferred
mounting method.

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VIN

Option – Cut T0−247 gate lead
T0−247SiC
PWM Input(flying lead)
Kaptontape

L1

Mini EVBSide View

S

VIN

Main
PCB

T0−247SiC

T0−247SiC
Mini EVB
Kapton tapeS D GMini EVB
Main
PCB

L1
VL1

S D G

VL1

D1

DUT

Figure 32. Horizontal EVB Installation

VAFG

If large components on the main power board prevent
horizontal installation, a second option is to install the EVB
vertically so that it is parallel to the T0−247 package, or
angled slightly away. Installing this way is less preferred dueto the close proximity of the driver to the high dV/dt emitted
from the TO−247 drain tab. In either case, the back tab of the
TO−247 package remains exposed and can be attached to aheat−sink if necessary. Installation and operation details areavailable in the EVB User Guide.

U1

D1

DUT

U1

VAFG

(Turn−Off)(Turn−On)

VDD (20 V)
VGSt

VEE (−5 V)

IL1t

Option – Cut T0−247 gate lead

IDS

Mini EVB T0−247
SiC
PWM Input(flying lead)

S
Side View

Main
PCB

T0−247SiC

T0−247SiC

Mini EVB

Mini EVB
Main
PCB

S D G

t

T0−247
SiC

VDS
S D G

t
tOFF

t ON

Figure 34. Double Pulse Test Circuit
and Waveforms

Figure 33. Vertical EVB Installation

The EVB comes initially configured to accept a PWM
signal that is positive input logic (IN− connected to GND1).
However, IN− can easily be used as an active enable orreconfigured for inverting input logic if desired. The driver
output comes preconfigured for 0 V < VOUT < VDD
switching. All the connections and resistor placeholders areavailable to reconfigure VEESET for −3 V, −5 V or −8 V VEE
switching. Finally, the UVSET option is preprogrammed for
17−V turn−on operation which is considered a safe level for
SiC MOSFETs.

The on−time of the first pulse is adjusted to achieve adesired peak drain−source current. The inductor is large andthe off−time is short enough such that IL1 remains nearly
constant during the off−time, freewheeling period. As aresult, a second, shorter pulse is applied with the same
amplitude of drain−source current. This test method allows
precise control of ID and VDS necessary for establishing
dynamic switching, parametric performance as well as
benchmarking one device against another.
The double pulse test method can also be used tocharacterize gate driver performance. Leaving the SiC,
DUT fixed, various gate drive circuits can be characterized
as U1 becomes the new “DUT.” dV/dt and dI/dt switching
performance is compared between the NCP5170 EVB
shown in Figure 30 and Figure 31 and the simple
optocoupler gate drive circuit shown in Figure 35.

PARAMETRIC PERFORMANCE
MOSFETs and IGBTs are parametrically characterizedusing the well know double pulse test platform. The double
pulse test method essentially applies two pulses to thegate−source of a low−side SiC MOSFET considered to be
the device under test (DUT). The DUT is inserted into asocket connected to a clamped inductive switching circuit
similar to the one shown in Figure 34.

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Figure 35. FOD8384 SiC Opto Gate Drive Circuit

The FOD8384 optocoupler driver is capable ofwithstanding VDD bias up to 30 V, making it well suited for−5 V < VGS < 20 V switching. Similar to the example shownin Figure 8, the FOD8384 driver is not a complete SiC
MOSFET gate drive circuit. Therefore, since features
between the two circuits are not comparable, test results andcomparisons are limited to dynamic switching only.
The rising and falling VGS waveforms for both circuits
are show for comparison in Figure 36 and Figure 37
respectively. Both circuits are using 1  source and sink gate
resistors. These gate drive edges are shown driving a 1.2 kV,
SiC MOSFET with 600 V present on VDS and 30 A flowing
through ID. The NCP51705, VGS rising edge appears as
purely resistive from −5 V < VGS < 10 V and then capacitive
RC charging from 10 V < VGS < 20 V. This is indicative of
the NCP51705, 6 APK sourcing current compared to the 1
APK sourcing current from the FOD8384. As a result the
NCP51705 has a VGS rise time of 37.5 ns, compared to 57.6
ns for the FOD8384 switching under the same test
conditions. Similarly, the VGS fall time for the NCP51705
is 25.2 ns, compared to 34.5 ns for the FOD8384.

Figure 37. VGS Falling Edge Comparison

A well designed gate driver IC includes low source andsink impedance so that the SiC MOSFET drain can be
accurately controlled by the gate. Secondly, minimizing
driver output impedance is essential for allowing the highest
natural dV/dt of the SiC MOSFET. The natural dV/dt limitof a SiC MOSFET is inversely proportional to RLO + RGATE+ RGI. When RLO is higher than necessary, the natural dV/dt
limit of the SiC MOSFET is lowered. This makes the device
more susceptible to dV/dt induced turn−on and limits theamount of dVDS/dt control that can be achieved by theselection of RGATE. The NCP51705 VDS waveforms shownin Figure 38 reveal the high degree of dVDS/dt control thatis possible by simply varying RGATE. For RGATE = 1 ,
dVDS/dt = 72 V/ns. Increasing RGATE from 1  to 15 
reduces dVDS/dt from 72 V/ns to 68 V/ns. This demonstrates
that a much higher RGATE can be used to obtain very fineincremental steps toward reducing dVDS/dt, if desired.

Figure 36. VGS Rising Edge Comparison

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Figure 38. NCP51705 VDS Rising Edge,
Vary Gate Resistance

Figure 40. VDS Rising Edge Compare,
1 W Gate Resistance

The same experiment was completed using the FOD8384
opto gate driver. Notice from the waveforms shown in
Figure 39, a change in RGATE from 1  to 15 , results in
a dVDS/dt rate change by more than 2:1. dVDS/dt control ismore influenced by smaller changes in RGATE due to thehigher output impedance of the FOD8384 driver. Also,
notice the dVDS/dt rise of the NCP51705 is more linear
comparatively.

Another way the NCP51705 enables dVDS/dt control is byvarying the level of negative amplitude of VEE. This can bedone by configuring the VEESET pin according to Table 3
or by using an external negative DC power supply applied
to VEE. The waveforms in Figure 41 show the change in
dVDS/dt as VEE is varied between −6 V < VEE < 0 V. Noticethe strong inflection and capacitive nature at low VDS, forthe case that 0 V < VGS < 20 V. This is due to some residualgate charge from the SiC MOSFET not being fully turned off
and highlights the importance of driving VGS negative
during turn−off.

Figure 39. FOD8384 VDS Rising Edge,
Vary Gate Resistance

The waveforms shown in Figure 40 compare VDS for eachdriver switching the same load from −5 V < VGS < 20 V withRGATE = 1 . The dVDS/dt rates are comparable at 72 V/ns
verses 64 V/ns. The NCP51705 shows better damping andlower amplitude ringing.

Figure 41. NCP51705 VDS Rising Edge, Vary VEE

The drain current measurements shown in Figure 42 weretaken using a Pearson current probe. The NCP51705 current

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21when designing a high performance gate drive circuit. The
low gm or modest transconductance associated with SiC
MOSFETs is particularly troublesome from a gate drive
point of view. General purpose low−side gate drivers areoften used but lack the necessary functions to drive a SiC
MOSFET efficiently and reliably. Wide market adoption of
SiC MOSFETs is, to some degree, attached to their ease ofuse. The NCP5170 offers designers a simple,
high−performance, high−speed, solution for driving SiC
MOSFETs efficiently and reliably.

is falling at dID/dt = 3.2 A/ns yet exhibits less ringing
compared to the FOD8384 drive circuit. The faster dID/dt of
the NCP51705 correlates well to the VGS falling edge
waveforms shown in Figure 37.

Steve Mappus is a Member of the Technical Staff working
as a Principal Applications Engineer in Advanced Power
Conversion group from onsemi located in Bedford, NH,
USA. In his current role, he is responsible for technology
development related to power−supply controllers and
MOSFET gate drive ICs. He has more than 25 years of
power supply design experience, including ten years
designing military and commercial power systems foravionic applications. He has spent the last fifteen years
working within the field of power management
semiconductors, specializing in Systems and Applications
Engineering. His areas of interest include high−power
converter
topologies,
soft−switching
converters,
synchronous rectification, high−frequency
power
conversion, WBG devices and power factor correction.

Figure 42. ID Falling Edge Comparison

The double pulse test methodology is a test procedure
traditionally used to characterize dynamic switching
performance of discrete power semiconductor devices.
Since the applied VDS and initial ID can be accurately
controlled during turn−on and turn−off, this measuring
technique has been shown to be a reliable method forcharacterizing gate driver IC performance in a clamped
inductive switching application circuit.

REFERENCES[1] “NCP5170 – SiC MOSFET Driver”, Datasheet,onsemi, August 2017[2] “NCP5170 Mini EVB”, User Guide,
onsemi, August 2017

CONCLUSION
This paper has highlighted some of the uniquecharacteristics of SiC MOSFETs that must be considered

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