When using this document, keep the following in mind:ntialGeneral Notice

1. This document is confidential. By accepting this document you acknowledge that you are boundby the terms set forth in the non-disclosure and confidentiality agreement signed separately and /inthe possession of SEGA. If you have not signed such a non-disclosure agreement, please contact
SEGA immediately and return this document to SEGA.

de2. This document may include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new versions of the
document. SEGA may make improvements and/or changes in the product(s) and/or the
program(s) described in this document at any time.

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3. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without SEGA’S written permission. Request for copies of this document and for technicalinformation about SEGA products must be made to your authorized SEGA Technical Services
representative.

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4. No license is granted by implication or otherwise under any patents, copyrights, trademarks, orother intellectual property rights of SEGA Enterprises, Ltd., SEGA of America, Inc., or any third
party.
5. Software, circuitry, and other examples described herein are meant merely to indicate the characteristics and performance of SEGA’s products. SEGA assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples
describe herein.

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6. It is possible that this document may contain reference to, or information about, SEGA products(development hardware/software) or services that are not provided in countries other than Japan.
Such references/information must not be construed to mean that SEGA intends to provide such
SEGA products or services in countries other than Japan. Any reference of a SEGA licensed product/program in this document is not intended to state or simply that you can use only SEGA’slicensed products/programs. Any functionally equivalent hardware/software can be used instead.
7. SEGA will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s equipment, or programs according to this document.

SE

NOTE: A reader's comment/correction form is provided with thisdocument. Please address comments to :(6/27/95- 002)

SEGA of America, Inc., Developer Technical Support (att. Evelyn Merritt)
150 Shoreline Drive, Redwood City, CA 94065
SEGA may use or distribute whatever information you supply in any way
it believes appropriate without incurring any obligation to you.

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SaturnSCSP
User's ManualDoc. # ST-77-R2-052594© 1994 SEGA. All Rights Reserved.

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READER CORRECTION/COMMENT SHEETKeep us updated!
If you should come across any incorrect or outdated information while reading through the attacheddocument, or come up with any questions or comments, please let us know so that we can make therequired changes in subsequent revisions. Simply fill out all information below and return this form to
the Developer Technical Support Manager at the address below. Please make more copies of this form if
more space is needed. Thank you.
General Information:

Phone

Document number
Document name

Date

ST-77-R2-052594
Saturn SCSP User's ManualCorrections:
Correction

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pg. #

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Chpt.

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Your NameSE

Questions/comments:

Fax:

Where to send your corrections:(415) 802-3963
Attn: Manager,
Developer Technical Support

Mail:

SEGA OF AMERICA
Attn: Manager,
Developer Technical Support
275 Shoreline Dr. Ste 500
Redwood City, CA 94065

First Edition: (November 30, 1993)• New manualntialHistory(January 8, 1994)• Corrected page numbers

Third Edition:(February 24, 1994)• Revisions based on the Feb. 8, 1994, meeting.

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Second Edition:

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Introduction
Definitions
Terms used in this manual are defined below.

SCSP (Saturn Custom Sound Processor)

A multi-function game sound generator LSI that combines a PCM
sound generator and sound DSP.

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Data

A bit indicates 0 or 1 and is the smallest unit. 8 bits combined
together is called a byte, and 16 bits (or 2 bytes) is called a word.
When upper and lower grade is divided into 4 bits respectively,
they are called nibbles.

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PAN-POT

Determines the direction or location from which the sound seems tocome from in localization.
Direct Data

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Sound that does not pass through the DSP, or even if it did, noeffects were applied. Also called “dry data”.
Effect Data

The sound generated, as a result of sending it through DSP with aneffect created in the sound generator. Also called “wet data”.
MIDI Standard (Musical Instrument Digital Interface)GA

Conversion standard for sound interval and sound length used tocommunicate between electronic instruments and computers.

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Pulse Code Modulation Sound Generator

Sound is converted to PCM data and stored in memory. Refers to
the sound source in a method by which sound data is read frommemory during performance to generate the sound output. PCM
divides the sound (wave form) along the time axis and converts
each of the wave high values to digital data. The data that resultsfrom this operation is called PCM data.

FM (Frequency Modulation)

Indicates frequency modulation. In the context of a sound generator, it indicates the FM sound generator.

iLinearnti
alShows a straight line. This means that the relation of the input andoutput are proportional. Therefore, if the wave form data is linear,a high wave value proportional to the size of the data is produced.
In other words, the quantized step is in equal intervals.
LFO (Low Frequency Oscillator)

Indicates a functional frequency generator that generates wave
forms with frequencies that are below the range that is audible tothe human ear. The output wave form of this LFO is used for
amplitude and modulation of frequency.

deDSP (Digital Signal Processor)

nfiThis is mainly for calculation (multiplication and addition) andcontains a circuit for high-speed calculations. The DSP within
SCSP is specially customized for audio editing functions and isused when directing sound effects such as echo, reverb, chorus andfilter.
Sample Count

Indicates the data count of the wave form data.
dB (Decibel)

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A unit for expressing the relative intensity of sounds by using alogarithm to show that unit. The equation would be:
Sound Ratio [dB] = 20 • LOG10 N

N=

Sound Volume being comparedStandard Sound Volume

Modulator

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Specifically, if the comparative volume is twice the standard volume (wave form amplitude). the sound comparitor would be 6[dB]. Once would be 0 [dB], and three times would be 10 [dB] · · ·.
On the other hand, if the comparative volume is smaller than thestandard, the value [dB] would be negative (minus value). For
example, if it was 1/2 of the standard, it would be -6 [dB].

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Indicates the modulator slot when multiple slots are connected. In
the diagram below, SLOT0 and SLOT1 are modulators.

Carrier

Indicates the slot which is modulated when multiple slots areconnected. In the diagram below, SLOT2 is the carrier.

PrescalerThis function allows required time to be set when the counterincreases one increment. Time selection and settings are done foreach timer.
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Symbols
The following symbols are used in this manual.
Binary

Displayed with a “B” at the end. For example, 100 B. However, inthe case of 1bit, it may be shortened to just B.
Hexadecimal

Displayed with an “H” at the end. For example, 00 H, FFH.

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Units

1KByte indicates 1,024 Bytes; 1Mbit indicates 1,048,576bits.
MSB, LSB

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In byte and word configuration, left is the high bit (MSB, Most
Significant Bit), while right is the low bit (LSB, Least Significant
Bit).
Undefined bits

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In the sound generator block register or the DSP block register, bitsthat are not defined are shown with “–”. When writing data to
undefined bits, please write a “0B”.

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Table of Contents
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Introduction
Definitions
Symbols
Contents
Figures
Tables

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Chapter 3 SCSP Functions
3.1 Interface
Sound CPU Interface
Main CPU Interface
3.2 Memory Access Control

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Chapter 2 SCSP Overview
2.1 LSI Overview
2.2 LSI Specifications
2.3 SCSP Chip Block DiagramdeChapter 1 Sound System Configuration
1.1 System Configuration
Relation to the Main CPU
Relation to the Sound CPU
Sound Memory Map
Relation to the D/A Converter
Positioning of the Sound System
Starting Up the Sound System
Sound System Communication

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101
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Chapter 5 DSP Operation in the SCSP
5.1 DSP Configuration
5.2 DSP Internal RAM

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107

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Chapter 4 SCSP Registers
4.1 Register Map
4.2 Sound Source Register
Loop Control Register
EG Register
FM Modulation Control Register
Using the FM Sound Generator Method
Volume Register
PITCH Register
LFO Register
MIXER Register
Slot Status Register
Sound Memory Configuration Register
MIDI Register
Timer Register
Interrupt Control Register
DMA Transfer Register
4.3 DSP Memory Control Registeriv

(Chapter 1 Sound System Configuration)
Figure 1.1 Sound System and Peripherals
Figure 1.2 Sound System Configuration
Figure 1.3 Memory Map of the Sound Memory Register
Figure 1.4 Sound Memory Range
Figure 1.5 Interrupt Relations(Chapter 2 SCSP Overview)
Figure 2.1 SCSP Chip Block Diagramnti
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3
4
5
6

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(Chapter 3 SCSP Functions)Figure 3.1 Access Overview
Figure 3.2 Memory Access Priority

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(Chapter 4 SCSP Registers)
Figure 4.1 SCSP Memory Map (1906W)
Figure 4.2 Individual Slot Control Register
Figure 4.3 SCSP Common Control Register
Figure 4.4 Sound Data Stack
Figure 4.5 DSP Control Register
Figure 4.6 DSP Micro Program Map
Figure 4.7 DSP Internal Buffer Map
Figure 4.8 KEY_ON and KEY_OFF Sequence
Figure 4.9 Block Diagram Relating to Noise Occurrence and LFOFigure 4.10 Loop Types
Figure 4.11 Loop Wave Forms
Figure 4.12 KEY_OFF During Attack State Transition
Figure 4.13 KEY_OFF During Decay State Transition
Figure 4.14 Change in the Attenuation Volume
Figure 4.15 Transition (1) from the Attack State to Decay 1
Figure 4.16 Transition (2) from the Attack State to Decay 1
Figure 4.17 Transition (3) from the Attack State to Decay 1
Figure 4.18 SLOT Block Diagram
Figure 4.19 Wave Form Address Creation Calculation Block
Figure 4.20 Creating Wave Form Addresses and Reading Wave Form Data
Figure 4.21 Expanded Address Pointer Output Diagram
Figure 4.22 Frequency Address Pointer Output Value
Figure 4.23 Address Pointer Output Value During FM Voice Mixing (1)Figure 4.24 Address Pointer Output Value During FM Voice Mixing (2)Figure 4.25 Normal Loop
Figure 4.26 Reversal Loop
Figure 4.27 Alternative Loop
Figure 4.28 FM Sound Generator Configuration
Figure 4.29 Averaging Calculation Equation
Figure 4.30 Slot Calculation and Sound Stack Conditions
Figure 4.31 Time Lag until the Slot Is Written to the Sound Stack
Figure 4.32 Slot Averaging Calculation
Figure 4.33 4Slot Configuration Algorithm
Figure 4.34 SLOT0 Algorithm
Figure 4.35 SLOT2 Algorithm
Figure 4.36 SLOT2 Algorithm (by Input Slot)
Figure 4.37 SLOT3 Algorithm
Figure 4.38 MDL Modulation Rate
Figure 4.39 Maximum Displacement of the Wave Form Read Address

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20

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(Chapter 5 DSP Operation in the SCSP)
Figure 5.1 DSP Configuration Diagram

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Figure 4.40 Address Displacement during FM Voice Mixing
Figure 4.41 Wave Data During Clipping Process
Figure 4.42 Slot Connection Count
Figure 4.43 Self-Feedback Modulation
Figure 4.44 Step Feedback
Figure 4.45 Composite Feedback
Figure 4.46 Composite Modulation
Figure 4.47 FM Configuration Algorithm Pattern 1
Figure 4.48 FM Configuration Algorithm Pattern 2
Figure 4.49 7 SLOT FM Configuration
Figure 4.50 Wave Data when TL bit 4=1
Figure 4.51 Relation of OCT and FNS
Figure 4.52 LFO Block Diagram
Figure 4.53 Digital MIXER Block Diagram
Figure 4.54 Direct Component and Effect Component Circuits
Figure 4.55 Fixed Position Calculation through the DSP
Figure 4.56 Digital Mixing Block Diagram
Figure 4.57 SCSP and DAC Connections
Figure 4.58 Memory Address Mapping Diagram
Figure 4.59 MIDI-I/F Block Diagram
Figure 4.60 MIDI IN Block and the Interrupt Generation Block
Figure 4.61 MIDI OUT Block and the Interrupt Generation Block
Figure 4.62 Sound Interrupt Signal Connection Diagram
Figure 4.63 Interrupt Register Bit Accomodation
Figure 4.64 3 bit Code and Register Accomodation
Figure 4.65 Format of the Interrupt Level Setting Register
Figure 4.66 DMA Controller Block Diagram

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Tables(Chapter 1 Sound System Configuration)
Table 1.1 Sound CPU Address 100400H, 100401H
Table 1.2 Sound CPU Interrupt Vector Table

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7(Chapter 2 SCSP Overview)
Table 2.1 Sound CPU Specifications
Table 2.2 SCSP LSI Specifications (1)Table 2.3 SCSP LSI Specifications (2)

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(Chapter 4 SCSP Registers)
Table 4.1 Individual Slot Control Register (1)Table 4.2 Individual Slot Control Register (2)Table 4.3 Individual Slot Control Register Address Map
Table 4.4 SCSP Common Control Register
Table 4.5 Sound Data Stack
Table 4.6 DSP Control Register
Table 4.7 DSP Micro Program
Table 4.8 DSP Internal Buffer
Table 4.9 Sound Generator Block Register Allocation
Table 4.10 KYONB Function
Table 4.11 SBCTL Function
Table 4.12 SSCTL Internal Configuration
Table 4.13 Types of Sound Data
Table 4.14 Types of Loops
Table 4.15 Register Set Values and the Modulation Rate
Table 4.16 Relation of MDXSL/MDYSL and SLOT
Table 4.17 Address Maximum Displacement Value According to the Register Setting
Table 4.18 TL, Attenuation, and Waveform Amplitude
Table 4.19 Actual Frequency in Relation to Cent Count
Table 4.20 FNS.OCT Parameter Table
Table 4.21 Oscillation Frequency of the Oscillator
Table 4.22 LFO AM Modulation Wave Form
Table 4.23 LFO PM Modulation Wave Form
Table 4.24 Degrees of Amplitude and Frequency Modulation
Table 4.25 Relation of the Sources Available to Input into “IMXL” and “MIXS”
Table 4.26 Mix Stack Register Input level

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Chapter 1
Sound System Configuration

Saturn SCSP User's Manual

Chapter 1 Contents
1.1 System Configuration .................................. 2
Relation to the Main CPU ............................ 3
Relation to the Sound CPU ......................... 3
Sound Memory Map .................................... 3
Relation to the D/A Converter ..................... 4
Positioning of the Sound System ................ 4
Starting Up the Sound System ................... 5
Sound System Communication ................... 6

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1.1

System Configuration

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SCSP is a multi-function game sound generator LSI that consists of a PCM soundgenerator and a sound DSP. Figure 1.1 shows the sound system and peripheral
configuration. The sound processing CPU that makes up the Saturn sound block is
the MC68EC000. This CPU controls the various sound blocks.
The SCSP creates and processes sound mixes. It contains a 32 slot sound generator
and sound effect DSP, digital mixer and timer, and an interrupt controller.

SDRAM
WORK-RAMnfi

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The sound memory is connected directly to the SCSP. It has a capacity of 4Mbit(512KByte) and is used to store the sound programs and data sound wave form data,etc. This memory is accessed by the sound CPU, SCSP and the main CPU (SH-2,
SCU). Besides the memory, the SCSP is connected to the main CPU, sound CPU andthe D/A converter. The sound system can function independently of the main
system.

MASK-ROM

CD-ROM

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SCU

SH-2

A-BUS

B-BUS

MC68EC000

RESET

DAC

RESET

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SMPC

SCSP

4MbitDRAM

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Figure 1.1 Sound System and Peripherals

2

Lch OUTPUT
Audio OutRch OUTPUT

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Main CPU(Game Program)

SCSP

Sound CPUInterface

MC68EC00

PCM (FM)PCM Sound Data
DSP Delay Data

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DSP

Sound Memory(DRAM)SCPU Program

MIXER

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D/A Converter

Figure 1.2 Sound System Configuration

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Relation to the Main CPU

The SCSP has a main CPU interface incorporated to allow communication between
the sound system and the main system (including the main CPU). As shown in
Figure 1.2, the main system can access the memory and registers controlled by the
SCSP through the main CPU interface.
Relation to the Sound CPUGA

The SCSP also incorporates a dedicated sound processing CPU interface (for the
MC68EC000) to allow independent operation of the sound system against the main
system. From the SCSP’s point of view, the sound CPU is like a controller.
Sound Memory Map

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Saturn has 4Mbit of internal sound memory. The sound memory can be accessed by
the sound CPU, the SCSP, and the main CPU (SH-2, SCU). Similarly, the SCSP
control register that controls the SCSP sound source (block) and DSP control that areused in the generation and processing of sound can also be accessed.
Figure 1.3 shows a sound memory map. Be aware that the memory map is referenced from the sound block side, making the addresses different when accessing
from the main CPU. (See the SCU user’s manual for more details.)

Saturn SCSP User's Manual3Sound Memory Map

ntialAddress
000000H

Sound Memory (RAM) Usable
Capacity : 4Mbit

07FFFFH
080000H

Sound Memory Expansion Area

0FFFFFH
100000H
100EE3Hde

Not installed. Access is Forbidden
Control Register Area

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Figure 1.3 Memory Map of the Sound Memory RegisterCPU programs and data, wave form data, and DSP work area (DSP delay area) arestored in the sound memory.

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Relation to the D/A Converter

The D/A converter converts and outputs the digital sound signal created by the
SCSP to analog sound signal.
Positioning of the Sound System

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The sound system (sound CPU, SCSP), based on the sound memory, can operate
independently from the main system (main CPU, video system, etc.) During thistime, the sound system operates on a RAM base and so it must get the programs anddata required for the sound CPU from the main system. Furthermore, since synchronization between the image and sound is required, an interface for two-way
communication is also required.
To facilitate this communication the SCSP has an interface for the main system
included to enable communication with the main system.

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The sound CPU cannot independently read data from or write data to the main
system. Information exchange between the main system and the sound system isaccomplished by the main system reading data from or writing data to the soundmemory (RAM).

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Starting Up the Sound SystemntialAfter the sound system power is turned on, it is reset by the SMPC. In this state,neither the sound CPU or SCSP will operate.
RESET

The sound system will operate after the SCSP reset has been released by the SMPC.
The SCSP will initialize the internal registers, etc. for about 30µ sec after the reset has
been released. For this reason, access is not allowed during the 30µ sec.

deAfter the internal registers, etc., are initialized, the SCSP can be accessed by the main
CPU (SH-2, SCU). Once in this state, the sound program can be downloaded. Before downloading anything, make sure to set MEM4MB bit to 1 and DAC18B bit to 0
within the sound CPU (address) 10400H address. Once done, accessing the memoryand downloading files can be begun.

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Table 1.1 Sound CPU Address 100400H, 100401H(100400 H)(100401 H)
b15 b14 b13 b12 b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
VER [3 : 0]
MVOL [3 : 0]
–
–
–
–
–
–
M4 D8 D3
D2 D1 D0
D3 D2 D1
D0
0
0
0
0
0
0
1
0

M4: MEM4MB

D8:DAC18BCo

The sound CPU reads the reset vector from the 8 bits of the sound CPU address(000000H~000007H), so always transfer the CPU reset vector to this area.

Address in the
MC68EC000 15··············

0000000 H

Stack Address

Upper Word

000001H

000002 H

Stack Address

Lower Word

000003H

000004 H

Program Counter

Upper Word

000005 H

000006 H

Program Counter

Lower Word

000007HDRAM Area

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·
·

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·
·

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RESET VECTOR 0··············

8 7

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RESET VECTOR 1

Figure 1.4 Sound Memory Range (MC68EC000, SCSP)

After the reset is released, the sound CPU reads the reset vector and jumps to the PC
value address.

Saturn SCSP User's Manual

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After download has finished, the sound CPU is reset by the SMPC enabling thesound CPU to operate.
Sound System Communication
Communication with the Main System

Communication between the main system and the sound system takes placethrough the SCU. The sound CPU cannot access the main system through the SCSP.
Access is limited to access from the main system only.
Interrupt Signalde

The main system uses the SCSP interrupt register when it sends an interrupt to thesound CPU (explained in detail later on). This is executed by writing a “1B” to bit 5of the interrupt register (SCIPD).

All interrupts that can be applied to the sound CPU can be used as interrupts for themain CPU.

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Please refer to the register explanations for sending interrupts from the sound system to the main system.

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Main System
SCU

Interrupt

Main System (Main CPU) Interrupt

SCSP

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MC68EC000

Sound CPU Interrupt

External Expansion Interrupt(Not yet connected in Saturn)Interrupt Control Block

Figure 1.5 Interrupt Relations

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Interrupts to the sound CPU use an auto vector method. Vector data is shown in
Table 1.2.
Interrupt levels for the sound CPU can be set at different levels for each interrupt
factor. (See register explanations for settings.)

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Table 1.2 Sound CPU Interrupt Vector Table

16~23
24
25
26
27
28
29
30
31

000040 H~00005F H
000060 H
000064 H
000068 H
00006C H
000070 H
000074 H
000078 H
00007C H

32~47000080 H~0000BF H

TRAP command vector

0000C0 H~0000FF H

Undefined (Reserved)000100 H~0003FF H

User interrupt vector

48~63
64~255Interrupt Vector Contents
Reset vector initial SSP value
Reset vector initial PC value
Bus error
Address error
Invalid command
Calculation by 0 (Zero)
CHK command
TRAPV command
Privilege violation
Trace
Line 1010 emulator
Line 1111 emulator
Undefined (Reserved)
Undefined (Reserved)
Undefined (Reserved)
Uninitialized interrupt vector

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2
3
7
5
6
7
8
9
10
11
12
13
14
15

MC68EC000 Address
000000 H
000004 H
000008 H
00000C H
000010 H
000014 H
000018 H
00001C H
000020 H
000024 H
000028 H
00002C H
000030 H
000034 H
000038 H
00003C H

Undefined (Reserved)
Spurious interrupt
Auto vector level 1 interrupt
Auto vector level 2 interrupt
Auto vector level 3 interrupt
Auto vector level 4 interrupt
Auto vector level 5 interrupt
Auto vector level 6 interrupt
Auto vector level 7 interrupt

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Vector No.
0

Normal use vectors.

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Vectors open to users.

Note:

The sound development tools supplied by this company use the auto vector level 7 interrupt,
so users will not be able to use that level.

Interrupt Signals to the Main and the SCU DMA

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The interrupt signal to the main CPU can also be used as triggers for the DMA
transfer start that have a SCU. (Refer to the SCU manual for details.)

Saturn SCSP User's Manual

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Chapter 2
SCSP Overview

Saturn SCSP User's Manual

Chapter 2 Contents
2.1 LSI Overview ..................................................... 10
2.2 LSI Specifications .............................................. 11
2.3 SCSP Chip Block Diagram ................................ 13

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2.1 LSI Overview

ntialSince SCSP was developed with multi-media in mind, the audio features have better
functions and higher quality than before. The calculation block is equipped withsynthesizers that have performance comparable to those currently on the market
enabling a wide variety of sounds to be produced. Also, with future expansion inmind, various interfaces are equipped. The DSP block can also produce composite
sound stages, and perform special effects such as play back of various sound stages
and special 3D sound positioning.
The characteristics of LSI are described below.

Wave form data sampling frequencyde• Sampling Frequency
Sound generator block re-sampling frequency (set playback rate)
44.1KHz

0 (DC) ~ 44.1KHz

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• Characteristics- 32 slots for FM or PCM use built-in.
- One per slot (completely independent) incorporates the total of 32 LFOs.
- Incorporation of 32 EGs of 4 segment .
- Interface for a built-in CPUs: The main CPU and the sound CPU- Built-in MIDI interface.
- Built-in 128 step DSP- Built-in input mixer that selects DSP input- Built-in output mixer to mix sound generating output and DSP outputs.
- Incorporation of a new FM calculation method.

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2.2 LSI Specifications

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detailed specifications.
Table 2.1 Sound CPU Specifications

Table 2.2 SCSP LSI Specifications (1)deSOUND CPU MC68EC000-12
12.5MHz version(Operating frequency 11.2896MHz)
No. Included
Function
Special Comments
CPU commands
Command system that is completely compatible with theMC68000 CPU.
Interrupt signal
level 1~7 interrupt by auto vector .
Hardware configuration
MC68000 CPU with the MC6800 (8 bit) interface removed

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SOUND LSI SCSP (SATURN CUSTOM SOUND PROCESSOR) (Operating frequency 22.5792MHz)
No. Included
Function
Special Comments
Sound Source
Sound mixing method
PCM sound mixing and FM sound mixing methods ( 1)noise source (can be used for mixing)
Sound source block
44.1KHz fixed, primary interpolation
re-sampling frequency
Wave form data format
16 and 8 bit linear 2’S complement method
Sound processor slots
32
Equal to 1 operator (1slot) in PCM and FM sound sources.
When all are 4 operator (slot) type FM sounds: 8 sounds
when all are PCM sounds, a total of 32 sounds.
Maximum number of
1~32(The number of slots per FM sound can be freely set. It issimultaneous sounds
also possible to mix FM and PCM sounds.
As long as the total number of slots does not exceed 32,
then any combination is possible.
Wave form loop function
Select from normal, reverse and alternative loops for each
slot.
EG
32
4 segment AMPLITUDE-EG (Each slot has 1 baseincluded)
LFO
32
Each slot has one installed ( for amplitude/frequency
modulation)
Types of LFO output wave
4
Four types: sawtooth, rectangular, triangular, and whiteform
noise.
Sound source-8~+7 octaves with 1024 steps between octaves
oscillation frequency(nonlinear) can be set
Effect DSP block
DSP processor speed
128 steps/Fs (multiple parallel processing type DSP
Fs=44.1KHz)
Program RAM
128W
1 2 8 wo rd s x 6 0 b it s
Coefficient data RAM
64W
6 4 wo rd s x 1 3 b it s
Temporary (universal) RAM
128W
1 2 8 wo rd s x 2 4 b it sMultiplier accuracy
2 4 wo rd s x 1 3 b it s = 2 6 b it o u t p u t
Adder accuracy
2 6 wo rd s +2 6 b it s = 2 6 b it o u t p u t
DSP internal bus width
2 4 b it d at a b u s

1 FM sound mixing is not limited to the 4 operator (slot) types
used in the past, but 2~32 operators can be freely used for FM
connections. You may also freely set the feedback.

Saturn SCSP User's Manual11Table 2.3 SCSP LSI Specifications (2)

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No. Included
Function
Special Comments
Digital mixer block
Output level adjustment
8 steps (for each slot sound, DSP output sound)
steps
Panpot level adjustment
31 steps (center 1 step, left and right, 15 steps each)steps
DSP effect send channel
16Able to mix and store multiple slot output in each channel
count
DSP effect return channel
16Able to set level and panpot for each channel.
count
Master volume set function
Stereo capable
CPU interface
Main CPU interface
1
SCU B-BUS interface
Sound CPU interface
1
MC68EC000 interface
Other functions, interfaces
Timer3
8 bit timers with prescaler
DMAC
1
DMA controller for transfer between SCSP~DRAM
Interrupt controller
1Interrupt controller for the main and sound CPUs
MIDI interface
IN: 1 OUT: 1
Digital audio interface
1
Input stereo interface: 1
Sound memory interface
1
DRAM interface
DAC output interface
1
16 bit/ 18 bit stereo DAC interface
External interrupt signal
3
Not connected/used in the Saturninterface
DSP program library
REVERB (HALL, ROOM, VOCAL, PLATE, ETC.)EARLY REFLECTIONECHO / DELAY (STEREO, MONORAL)
Various types of effect
PITCH SHIFTER (SINGLE, DOUBLE, TRIPLE)
programs
CHORUS, FLANGERSYMPHONIC, SURROUNDVOICE CANCEL, AUTOPAN
PHASER, DISTORTIONFILTERPARAMETRIC EQUALIZER

12

Figure 2.1 shows the SCSP chip block diagram.

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2.3 SCSP Chip Block Diagram

LFO

Sound CPUInterface

PLFO

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AFLO

PLFO

Main CPUInterface

Phase
Generator
PHASE

DMA Transfer
Interface

External
Input

ADSR-L

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MIDI
Interface

PHASE

Address
Pointer
ADSR-RADSR-R

MemoryController
DATA

ADSR-L

Envolope
Generator

DATA

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Interpolator

EG

EG

DATA

PCM-DATA

ALFO

PCM_DATA

Level Calculator

EXTS

MIXS

MEMS

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DSP

Saturn SCSP User's Manual

EFREG
SEL

DIR

EFREG

OutputMixer

Figure 2.1 SCSP Chip Block Diagram

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Items shown in SCSP Chip Block Diagram Figure 2.1 are explained below.

Sound CPU Interface

Interface that connects to the MC68EC000.

Main CPU Interface

Interface that connects the system controller (SCU).

deDMA Transfer Interface

This is the SCSP built-in DMA controller. It enables datatransfer between the SCSP and the sound memory.

MIDI Interface

nfiThis serial interface complies with MIDI specifications;however, some external circuits will be needed to make itcompatible with a MIDI connector.

External Input (External Digital Audio Input Interface)

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Interface that inputs a digital audio signal from an external instrument (external device).

L F O (Low Frequency Oscillator)

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Indicates a function generator that generates wave formsof a frequency that is below the range that the human ear
can hear, and is used as a wave form for various modulation.

Phase Generator

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Block that calculates and outputs frequency data basedon the sound generation frequency setting of the PCM
data.

Address Pointer14

Creates the wave form address value based on the phase
information, etc., from the phase generator.

Memory ControllerntialBlock that outputs the address created by the address
pointer to the memory and reads data, etc.; it controls thesound memory.

Interpolator

Block that interpolates the wave form data.

Envelope Generator (EG)Level Calculator BlockdeFunctional calculation block that controls the soundoutput level with time.

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Block that calculates the wave form output level based on
the level coefficient created by EG, TL (Total Level), and
ALFO.

DSP

Output Mixer

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Audio DSP that receives and holds the SCSP special
sound effects.

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Final block that contains functions that calculate various
positions and level adjustments needed to compile eachsound output in stereo.

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Chapter 3
SCSP Functions

Saturn SCSP User's Manual

Chapter 3 Contents
Chapter 3 Contents
3.1 Interface
Sound.......................................................
CPU Interface
3.1 Interface
Main
CPUInterface
Sound CPU Interface....................................
3.2
Access......................................
Control
MainMemory
CPU Interface
3.2 Memory Access Control ...............................

18
18
18
18
18
20
18
20

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3.1 Interface

ntial

The SCSP has two internal CPU (main CPU and sound CPU) interfaces. The main
CPU has higher priority than the sound CPU, so the processing speed of the soundCPU depends on the operation of the main CPU.
Sound CPU Interface

The sound CPU interface is a block with specialized functions to enable it to connect
to the sound CPU. By adding this interface, the sound CPU can be directly connected to the SCSP without external circuits.

dePrograms for the sound CPU reside in the sound memory. For this reason, all CPU
programs are placed in the sound CPU address space available.
Main CPU Interface

Access between the main CPU and the interface is shown in Figure 3.1.

SCU

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SCSP

D

MCD
MCCSN

A

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MCRDYN

Address

Data

DRAM

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Figure 3.1 Access Overview

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At the trailing edge of the select signal (MCCSN) from the main CPU, the interface isstarted; at the leading edge of the select signal, the interface is ended. Also, when "1"
is output with respect to the ready signal (MCRDYN) to the main CPU, the selectsignal (MCCSN) from the main CPU and the main CPU data bus (MCD[7:0]) do notchange.

18

The following cautions should be observed with interfacing with the main CPU.
Because the main CPU cannot access in units of 8 bits, so read and write in 16
bit units.

(2)

When there is a request to read or write, the SCSP buffer gets the address anddata. Because of this, a “1” is output to the ready signal (MCRDYN) going to
the main CPU causing a wait. This wait continues until the internal processingof the LSI is finished. For this reason, continuous read and writes that cause
many waits to occur should be avoided except when turning on the power.

(3)

When the power is turned on, the time necessary for initialization of soundmemory by continuous writing is approximately 100 msec for 4Mbit DRAM.

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(1)

Saturn SCSP User's Manual

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3.2 Memory Access Control
When accessing sound memory from the SCSP, the following priorities are maintained.
1. PCM Data Read by PCM sound generator, accessed by DSP.
2. DRAM refresh cycle.
3. DMA transfer.
4. Access by the main CPU.
5. Access by the sound CPU.

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When there is an access request with a high priority, there will be a wait state against
an access request with a low priority. Also, a high priority access request will notoccur while a low priority access is requested because the decision on which device
to be permitted to access memory (PCM sound generator block, DSP block, main
CPU, sound CPU, DMA, etc.) is made before any actual memory access is performed.

CYCLE 0CYCLE 1CYCLE 2CYCLE 3

DSP
Access

PCM
AccessDSP
Access

PCM
AccessRefreshcycle

Refreshcycle

Refreshcycle

Refreshcycle

DMA
AccessDMA
AccessDMA
AccessDMA
AccessMCPU(SCU)
AccessMCPU(SCU)
AccessMCPU(SCU)
AccessMCPU(SCU)
AccessSCPU
AccessSCPU
AccessSCPU
AccessSCPU
Access

Low

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High

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Memory AccessPriority

Figure 3.2 Memory Access Priorities

The performance of the SCSP / sound CPU is determined by the distribution of thememory cycles.

SE

There are 128 memory cycles within one sample (1/44.1K= 22.68µ sec). These 128
cycles are distributed among the various devices. The number of times the CPU
accesses changes with the application, so there is no best way to access memory, but
be aware of the items on the following page.

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• Sound memory uses DRAM, so refresh cycles are required. In the Saturn soundsystem, two empty cycles are required between each sample, so the number ofmemory cycles that can be used by other devices is 126.
• The sound generator and DSP memory cycles have the highest priority memory
cycles.

de• The sound generator uses two memory cycles to produce sound from one slot.
With a maximum of 32 slots, a total of 64 times of memory cycle may be used.
When the EG is at the maximum attenuation state (“3FFH”), the sound generator
does not access memory. Do KEY_OFF for those slots that are not producing
sound.
• The DSP accesses memory a maximum of 64 times. This changes with the DSP
application. Try to use the internal DSP registers as much as possible whenstoring data temporarily.

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• The sound CPU operating speed will decrease when using the SCSP built-in
DMA due to the extent of the wait state imposed on the sound CPU.

Saturn SCSP User's Manual

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Chapter 4
SCSP Register

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Chapter 4 Contents

Saturn SCSP User's Manual

Chapter 4 Contents

4.1 Register Map .......................................................... 24
Register
Map
4.2 4.1Sound
SourceRegister .......................................... 24
34
4.2LoopSound
SourceRegister
Control Register............................................ 34
35
Control Register
35
EG Loop
Register............................................................
40
RegisterControl Register ............................. 40
FM EG
Modulation
46
FM
Modulation
Control
RegisterUsing theFM SoundGenerator
Method ................ 46
47
Using
the FMSound .........................................
Generator Method
47
Sound
VolumeRegister72
Sound
VolumeRegister
72
PITCH
Register......................................................
73
Register
LFOPITCH
Register.......................................................... 73
76
LFO
Register
MIXER Register ..................................................... 76
80
Register ............................................... 80
SlotMIXER
Status Register
89
SlotMemory
Status Register
Sound
Structure Register ......................... 89
89
MemoryStructure Register
89
MIDISound
Register.........................................................
89
MIDI
Register
Timer
Register........................................................ 89
92
TimerRegisterInterrupt Control Register ....................................... 92
95
Interrupt
Register
95
DMA
TransferControl
Register........................................... 101
DMA
Transfer
Register
101
4.3 DSP Memory Control Register ............................... 103
4.3 DSP Memory Control Register
103

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4.1 Register Map
The SCSP carries a wave form calculator unit called SLOT to realize FM soundmixing.

Figure 4.1 describes the SCSP memory map and the allocation of the individual
registers that make up the memory map.

de100000 H

Individual Slot Control Register( 5 0 8 W )1003F8 H
100400 H

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SCSP Common Control Register( 2 4 W )10042FH
100600 H

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Sound Data Stack( 6 4 W )10067FH
100700 H

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DSP Control Register(1 0 1 0 W )100EE3 H

SENote) W: Word = 16bit

24

Figure 4.1 SCSP Memory Map (1906W)

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The individual slot control register represents the allocation of the registers configured in each of the 32 slots (SLOT0~SLOT31).
The location of bit allocation for each register is described as [3 : 0]. For example, SA[19 : 16] represents the allocation from the 16th bit through the 19th bit of SA.

00 H
KX

KB

SBCTL

SSCTL
SA[15:0]

8BSA[19:16]

deLSA[15:0]

LPCTL

LEA[15:0]
D2R[4:0]LS

KRS[3:0]nfi

LFOF[4:0]

DISDL[2:0]
18 H

TL[7:0]MDYSL[5:0]FNS[9:0]

PLFOWSCoRESD

MDXSL[5:0]

OCT[3:0]

RR[4:0]DL[4:0]SI
MDL[3:0]

AR[4:0]HO

D1R[4:0]

DIPAN[4:0]

KX:KYONEXHO:EGHOLD
SD:SDIRALFOWS

PLFOS[2:0]

ISEL[3:0]

EFSDL[2:0]

KB:KYONB
LS:LPSLNK
RE:LFORE

ALFOS[2:0]
IMXL[2:0]
EFPAN[4:0]

8B:PCM8B
SI:STWINH

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Figure 4.2 Individual Slot Control Register

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Table 4.1 Individual Slot Control Register (1)Designation
KYONEX (KX)KYONB (KB)
SBCTL
SSCTL
LPCTL
PCM8B (8B)SA
LSA

Saturn SCSP User's ManualContents
Execute KEY_ON
Record KEY_ON, KEY_OFF
Source bit control
Sound source control
Loop control
Select wave form data format
Start address
Loop start address

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Loop end address
Decay 2 rate
Decay 1 rate
EG hold mode
Attack rate
Loop start link
Key rate scaling
Decay level
Release rate
Stack write inhibit
Sound direct
Total level
Modulation level
Select modulation input X
Select modulation input Y
OctaveFrequency number switch
LFO reset
LFO frequency

Select LFO frequency modulation wave form

LFO frequency modulation level
Select LFO amplitude modulation wave form

LFO amplitude modulation level
Input selectInput mix level
Direct data send level
Direct data, fixed position
Effect data send level
Effect data, fixed position

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LEA
D2R
D1R
EGHOLD (HO)AR
LPSLNK (LS)
KRS
DL
RR
STWINH (SI)SDIR (SD)
TL
MDL
MDXSL
MDYSL
OCT
FNS
LFORE (RE)LFOF
PLFOWS
PLFOS
ALFOWS
ALFOS
ISEL
IMXL
DISDL
DIPAN
EFSDL
EFPAN

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Table 4.2 Individual Slot Control Register (2)Table 4.3 Individual Slot Control Register Address Map

Address
100200 H ~ 100217 H
100220 H ~ 100237 H
100240 H ~ 100257 H
100260 H ~ 100277 H
100280 H ~ 100297 H
1002A0 H ~ 1002B7 H
1002C0 H ~ 1002D7 H
1002E0 H ~ 1002F7 H
100300 H ~ 100317 H
100320 H ~ 100337 H
100340 H ~ 100357 H
100360 H ~ 100377 H
100380 H ~ 100397 H
1003A0 H ~ 1003B7 H
1003C0 H ~ 1003D7 H
1003E0 H ~ 1003F7 H

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Slot
16
17
18
19
20
21
22
23
24
25
26
27
27
29
30
31

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Address
100000 H ~ 100017 H
100020 H ~ 100037 H
100040 H ~ 100057 H
100060 H ~ 100077 H
100080 H ~ 100097 H
1000A0 H ~ 1000B7 H
1000C0 H ~ 1000D7 H
1000E0 H ~ 1000F7 H
100100 H ~ 100117 H
100120 H ~ 100137 H
100140 H ~ 100157 H
100160 H ~ 100177 H
100180 H ~ 100197 H
1001A0 H ~ 1001B7 H
1001C0 H ~ 1001D7 H
1001E0 H ~ 1001F7 H

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Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Saturn SCSP User's Manual27100400 H

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The SCSP control register allocates the interrupt register and timer register, etc., thatare commonly used.

DB

MVOL[3:0]

RBL
OF

OE

IO

IF

RBP[19:13]

IE

MIBUF[7:0]
MOBUF[7:0]

MSLC[4:0]

CA[3.0]10040F H
100410 H
DMEA[15:1]

DI

EX

DTLG[11:1]

TACTL[2:0]

TIMA[7:0]

TBCTL[2:0]

TIMB[7:0]

TCCTL[2:0]

TIMC[7:0]

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DRGA[11:1]

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DMEA[19:16]

de100409 H
10040A HSCIEB[10:0]
SCIPD[10:0]

10042F H
100430 H

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SCIRE[10:0]

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M4:MEM4MB
OE:MOEMP
IE:MIEMP
EX:DEXESCILV0[7:0]
SCILV1[7:0]
SCILV2[7:0]
MCIEB[10:0]
MCIPD[10:0]
MCIRE[10:0]

DB:DAC18B
IO:MIOVF
GA:DGATE

OF:MOFULL
IF:MIFULL
DI:DDIR

Figure 4.3 SCSP Common Control Register28

Table 4.4 SCSP Common Control Registernti
alContents
Memory size designation

Use the 18 bit D/A converter on the digital output

deVersion number
Master volume
Ring buffer length
Ring buffer lead address
Output FIFO is full
Output FIFO is empty
Input FIFO overflow
Input FIFO full
Input FIFO empty
MIDI input data buffer
MIDI output data buffer
Monitor Slot
Call Address
DMA transfer start memory address
DMA transfer start register address

DMA transfer gate 0 clear
DMA transfer direction
DMA transfer start
DMA transfer data countTimer A pre-scaler control
Timer A count data
Timer B pre-scaler control
Timer B count data
Timer C pre-scaler control
Timer C count data
Allow sound CPU interrupt
Request sound CPU interrupt
Reset sound CPU interrupt
Sound CPU interrupt level bit0
Sound CPU interrupt level bit1
Sound CPU interrupt level bit2
Allow main CPU interrupt
Request main CPU interrupt
Reset main CPU interrupt

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Designation
MEM4MB (M4)
DAC18B (DB)
VER
MVOL
RBL
RBP
MOFULL (OF)MOEMP (OE)MIOVF (IO)MIFULL (IF)MIEMP (IE)
MIBUF
MOBUF
MSLC
CA
DMEA
DRGA
DGATE (GA)DDIR (DI)DEXE (EX)
DTLG
TACTL
TIMA
TBCTL
TIMB
TCCTL
TIMC
SCIEB
SCIPD
SCIRE
SCILV0SCILV1SCILV2
MCIEB
MCIPD
MCIRE

Saturn SCSP User's Manual29100600Hntial

The sound data stack is where sound data is stored. Sound data is in two generation
configuration (GENERATION A and B). Each generation can control up to 32 sounddata.

DIRECT SOUND SLOT DATA STACK (GENERATION A) "SOUS[15:0]"(32W)

DIRECT SOUND SLOT DATA STACK (GENERATION A) "SOUS[15:0]"
DIRECT SOUND SLOT DATA STACK (GENERATION B) "SOUS[15:0]"

de10063FH
100640 H(32W)
10067FH

DIRECT SOUND SLOT DATA STACK (GENERATION B) "SOUS[15:0]"

Table 4.5 Sound Data Stack

Contents

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Sound stackSE

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Designation
SOUS

30

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Figure 4.4 Sound Data Stack

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On the DSP control register, the interface block area of DSP is defined which is built
within SCSP.

100700 H

COEF REG "COEF[12:0]"

O

O

O

COEF REG "COEF[12:0]"

O

O

0

(64W)
10077F H
100780 H

MEMORY ADDRESS REG "MADRS[16:1]"

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(32W)

MEMORY ADDRESS REG "MADRS[16:1]"

1007BFH
100800 H(512W)nfi

DSP MICRO PROGRAM

100BFF H
100C00 H

DSP INTERNAL BUFFER(370W)

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100EE3 H

Figure 4.5 DSP Control Register

Table 4.6 DSP Control Register

Contents
DSP coefficient buffer
Memory address register

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Designation
COEF
MADRS

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100800 H

DSP MICRO PROGRAM (STEP_0) "MPRO[63:48]"
DSP MICRO PROGRAM (STEP_0) "MPRO[47:32]"

DSP MICRO PROGRAM (STEP_0) "MPRO[31:16]"
DSP MICRO PROGRAM (STEP_0) "MPR0[15:0]"100807 H
100808 H

DSP MICRO PROGRAM (STEP_1) "MPRO[63:48]"
512W

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DSP MICRO PROGRAM (STEP_126) "MPRO[15:0]"
100BF8 H

DSP MICRO PROGRAM (STEP_127) "MPRO[63:48]"

DSP MICRO PROGRAM (STEP_127) "MPRO[47:32]"

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DSP MICRO PROGRAM (STEP_127) "MPRO[31:16]"
DSP MICRO PROGRAM (STEP_127) "MPRO[15:0]"

100BFFH

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Figure 4.6 DSP Micro Program Map

Table 4.7 DSP Micro Program

Contents
Micro program register

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Designation
MPRO

32

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100C00 H"TEMP[7:0]"

WORK BUFFER 00 "TEMP[23:8]"(256W)"TEMP[7:0]"

WORK BUFFER 127 "TEMP[23:8]"

100DFFH
100E00 H" MEMS[7:0]"

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SOUND MEMORY 00 "MEMS[23:8]"(64W)"MEMS[7:0]"

SOUND MEMORY 31 "MEMS[23:8]"

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100E7FH
100E80 H"MIXS[3:0]"

MIX SOUND SLOT DATA STACK 00 "MIXS[19:4]"

100EBFH
100EC0 H(16W)
100EDFH
100EE0 H"MIXS[3:0]"

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(32W)

MIX SOUND SLOT DATA STACK 15 "MIXS[19:4]"
EFFECTED DATA OUTPUT 00 "EFREG[15:0]"

EFFECTED DATA OUTPUT 15 "EFREG[15:0]"

GA

100EE3 H

Figure 4.7 DSP Internal Buffer Map

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Table 4.8 DSP Internal Buffer

Designation
TEMP
MEMS
MIXS
EFREG

Saturn SCSP User's ManualContents
DSP temporary (universal) buffer
Memory data stackMix stackEffect register

33

4.2

Sound Source Register

Table 4.9 Sound Source (Block) Register Allocation

Register Name
Loop Control Register

Bit Name

KYONEX, KYONB, SBCTL, SSCTL, SA, LSA,
LEA, PCM8B, LPCTL

EG RegisterntialThe sound source (block) register is made up of the allocations shown in Table 4.9.

EGHOLD, AR, D1R, D2R, RR, DL, KRS, LPSLNKSound Volume Register
PITCH Register
LFO Register

SOUS, MDL, MDXSL, MDYSL, STWINH
TL, SDIR
OCT, FNSdeFM Modulation Control Register

LFORE, LFOF, ALFOWS, ALFOS,
PLFOWS,PLFOS

MIXER Register

IMXL, ISEL, DISDL, DIPAN, EFSDL, EFPAN,

Sound Memory Config. Register
MIDI Register

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MVOL, DAC18B

Slot Status Register

MSLC, CAMEM4MBMIBUF, MIOVF, MIFULL, MIEMP, MOFULL,
MOEMP, MOBUFTACTL, TIMA,TBCTL, TIMB, TCCTL, TIMC

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Timer Register

Interrupt Control Register

SCIPD, SCIEB, SCIRE, SCILVO, SCILV1, SCILV2,MCIPD, MCIEB, MCIRESEGADMA Transfer Register

34

DGATE, DDIR, DEXE, DMEA, DRGA,DTLG

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Below is the definition of the bit in terms of the sound generator block register,
based on the classifications in Table 4.9. The symbols following the register names
have the following meanings: (R) read only, (W) write only, (R/W) both read andwrite are possible.
When reading data from the write only register (bit), that value becomes “0B”.
When writing data to the read only register (bit), always write “0B”.
Loop Control Register
KYONEX (W) ;KeY_ON EXecution
A “1B” written here will execute KEY_ON, OFF for all of the slots.

Table 4.10 KYONB Function

Function
Registers KEY_OFF
Registers KEY_ON

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bit
0
1

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KYONB (R/W) ;KeY_ON Bit
Registers KEY_ON,OFF. (If you wish to KEY_ON simultaneously, the “KYONB” ofthe slot you want to turn ON must be set to “1B”.)

Co“KYONEX” and “KYONB” exist in each slot. The sequence of KEY_ON and
KEY_OFF is shown in Figure 4.8.
There is no need to write a “0B” in “KYONEX” after writing a “1B”. Also a “1B” in“KYONEX” is used for all slots, so you don’t need to set to “1B” per a specific slot.

"0"

KYONB
REGISTER

"1"

"1"

"1"

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"1" WRITE
"0"

KEYON
TRIGGER"OFF"

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KYONEXREGISTER

"0"

"0"

"0"

"0"

"1" "0""1" "0"Time"0" WRITE"1" "0""1" "0""1" WRITE"1" WRITE

"ON"
"ON"
ON Execute
Ignore"0""1"WRITE

Time"1"WRITE

"OFF"
"ON"
Time
No Meaning
OFF Execute

Figure 4.8 KEY_ON and KEY_OFF Sequence

SBCTL[1:0] (R/W) ;Source Bit ConTroL
Specifies bit reversal operation of the sound input data. The reversal function becomes valid for bits with “1B” written to them.

Saturn SCSP User's Manual35

Table 4.11 SBCTL Function
Function
Reverse selection for bits other than the source wave form
data sign bit.
Reverse selection for the source wave form data sign bit.

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Bit
SBCTL0SBCTL1

SSCTL[1:0] (R/W) ;Sound Source ConTroL
Designates the data to be used as sound input data. When using the wave form datain sound memory to produce a sound, write “0B”. When this register is “1B”, theslot with respect to which setting has been applied (the LFO accompanied with eachslot) will output noise.

LEO Waveform Generator
Sawtooth
Wave

ALFOS

* Alfo is Attached Herenfi

ALFOWSALFOWSdeThe block diagram of noise generated when “SSCTL”=“1B” and the relation to LFO
is shown with ALFO added in Figure 4.9

SELECTOR

4SquareWave

Amplitude Modulation Rate
Adjustment

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TO
1

Triangle
Wave

LFORE

LFOF

GA

EG

Level
Coeffici- Level
ent
Coefficient
Calculater
Block
Level
Calculater
BlockWhite Noise

SLOT
Wave Form Data Buffer

TL

SELECTOR
Noise

Normal Sound

2
TO
1
Sound DataSE

Waveform Data From
Wave Form Memory (RAM)SSCTL Noise On/Off
Function

Figure 4.9 Relation of the Noise Generation Block Diagram and LFO

36

nti
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Each slot utilizes the LFO noise oscillator output to output noise. Here, the LFOparameters in Figure 4.9 (“LFORE”, “LFOF”, “ALFOWS”, “ALFOS”, “PLFOWS”,“PLFOS”) will not affect noise as voice data.

Also, when using LFO in low-frequency modulation with the LFO wave form selection at noise (ALFOWS=“3H”, or PLFOWS=“3H”) as in Figure 4.9, reset with the“LFORE” will not function. The frequency also cannot be changed. This means thatwhen selecting noise, the LFO can select wave form but cannot change in terms ofother parameters.
Table 4.12 SSCTL Internal Configuration

Data Used
External DRAM data
Internally generated data (noise)Internally generated data (ALL “0”)Cannot be used

de

SSCTL
0
1
2
3

nfi

SA[19:0] (R/W) ;Start Address
Specifies the waveform data start address in byte address when using memory
waveform data to generate sound. However, if the waveform data is “16 bit PCM”(“PCM8B”=“0”), always set the register’s lsb (SA0) to “0B”.

Co

LSA[15:0] (R/W) ; Loop Start Address
Represents the sound data loop start address in sample count from the “SA”.
LEA[15:0] (R/W) ; Loop End Address
Represents the sound data loop end address in sample count from the “SA”.
PCM8B (R/W) ; PCM 8Bit
Designates the format of the wave form data.

GA

Table 4.13 Types of Sound Data

Sound Data
16Bit PCM data 2’S complement
8Bit PCM data 2’S complement

SE

PCM8B
0
1

Saturn SCSP User's Manual

37

nti
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LPCTL[1:0] (R/W) LooP ConTroL
Sets the loop format.
Table 4.14 Types of Loops
LPCTL
0
1
2
3

Loop Format
Loop OFF
Normal loop
Reverse loop
Alternative loop

Loop processing or sound memory access will end with either of the following two
conditions:
After release, when the attenuation volume reaches maximum, orWhen the loop is OFF, and the read point reaches the loop end point.

de

(1)
(2)

nfi

When using normal or reverse loops, set the data corresponding to“SA+LSA” (loop start address) and the “SA+LEA” (loop end address) to thesame value. Using the same method with the alternative loop can make thepitch the same as the normal or reverse loops.
Figure 4.10 shows specific examples of loop types.

hiiii

huuuu

Attack Data

SA

heeee

hoooo

Loop Data

LSA

Co

haaaa

LEA

Using the sounds "ha- hi- hu- he- ho" as wave form data, the following sounds are produced when thestart address (SA), loop start address (LSA), and loop end address (LEA) are set as shown above.
● Normal Loop
haaaa

hiiii

huuuu heeee hoooo huuuu heeee hoooo huuuu heeee hoooo huu

haaaa

SA

LEA(LSA)

GA

SA
LSA
● Reversal Loophiiii

ooooh eeeeh uuuuh

LEA

LEA(LSA)LEA(LSA)ooooh eeeeh uuuuh ooooh eeeeh uuuuh ooo

LSA(LEA)LSA(LEA)LSA(LEA)● Alternative Loophiiii

huuuu heeee hoooo ooooh eeeeh uuuuh huuuu heeee hoooo ooo

SE

haaaa

SA

38

LSA

LEA

Figure 4.10 Loop Types

LSA

LEA

nti
al

The wave form for each of the normal loop, reversal loop and the alternative loop
can be represented as in figure 4.11. Note that the uuuu, eeee, oooo wave forms arereversed from huuh, heeh, hooh wave forms.

Co

AttackDatanfi

Normal LoopdeThe wave form for each of "huuu, heee, hooo" are defined as shown
below.

Reversal LoopGA

AttackData

SE

Alternative Loop

AttackData

Saturn SCSP User's Manual

Figure 4.11 Loop Wave Forms

39

EG Registerntial

EG represents the change occurred by sound attenuation time, and has the following
four states.

de• Attack State (Attack segment)
Indicates the start of the sound (start up).
• Decay 1 state (Decay 1 segment)
Indicates attenuation from the maximum volume.
• Decay 2 state (Decay 2 segment)
Indicates attenuation even lower than decay 1.
However, if DR2 is set to “0”, the sound is maintained rather than attenuated.
• Release state (Release segment)
Indicates the attenuation until the sound disappears after KEY_OFF.

(a)

nfi

However, in all cases of sound generation state, EG does not necessarily go throughall four states. Depending on the timing of KEY_OFF various envelope curves are
drawn. An example is shown below.
When KEY_OFF is executed during attack state transition(Figure 4.12).

EG

Co

000H

KEY-OFF
LEVEL

3FFH

Time

KEY-OFFGA

KEY-ON

Attack State

Release State

Figure 4.12 KEY_OFF During Attack State Transition

SE

When KEY_OFF is executed, from that level (KEY_OFF LEVEL) thesound is attenuated following the release rate (“RR”) setting.
Therefore, in this case, the envelope curve skips the decay 1 anddecay 2 states. In this case, EG value does not reach “000H”, rather,with KEY_OFF as a turning point, it increases to “3FFH”.

40

EG
000 H
KEY-OFF
LEVEL
DL

3FFH
KEY-OFFTime

deKEY-ONntial(b) When KEY_OFF is executed during decay 1 segment transition.
(Figure 4.13).

Attack State
Release State
Decay 1 State

nfi

Figure 4.13 KEY_OFF During Decay State Transition

When the decay 1 state starts, it attenuates towards the DL (decay
level) following the D1R (decay 1 rate) set value.

Co

If KEY_OFF is executed during the above operation, the sound starts
to attenuate from the level KEY_OFF was executed (KEY_OFFLEVEL) according to the value set in RR (release rate).

GA

AR[4:0] (R/W) ; Attack Rate
Designates the change volume of EG in the attack state. When“AR”=“00H”, the change volume (level attenuation volume) is
minimum (0). When “AR”=“1FH”, the change volume (level attenuation volume) is maximum (MAX).

SEEGHOLD (R/W) EG HOLD mode
Designates whether to maintain or change the attack value. As shownin Figure 4.12, when this bit is “1B” the attack value is held at “000H”.
Also when this bit is “0B”, it changes according to the value designatedby the AR register. In the hold mode, the time that EG retains “000H”(time until it reaches segment 2) is determined by the “AR” value.

Saturn SCSP User's Manual41

When EGHOLD=1

nti
al

EG
000H
D1R[4:0]

DL[4:0]

D2R[4:0]

RR[4:0]AR[4:0]

AttackState

Decay 1State

Decay 2
State

When EGHOLD=0
EG000H

AR[4:0]

Release
State

Time

nfi

D1R[4:0]de

3FFH

D2R[4:0]

DL[4:0]3FFH
AttackState

Co

RR[4:0]Decay 1State

Decay 2State

Release
State

Time

GA

Figure 4.14 Change in the Attenuation Volume

D1R[4:0] (R/W) ; Decay-1 Rate
Designates the EG change volume in the decay 1 state. When
“D1R”=“00H”, the change volume (level attenuation volume) is
minimum (0). When “D1R”=“1FH”, the change volume (level
attenuation volume) is maximum (MAX).

SE

D2R[4:0] (R/W) ; Decay-2 Rate
Designates the EG change volume in the decay 2 state.When“D2R”=“00H”, the change volume (level attenuation volume) is
minimum (0). When “D2R”=“1FH”, the change volume (level
attenuation volume) is maximum (MAX).

42

nti
al

RR[4:0] (R/W) ; Release Rate
Designates the change volume of the EG in the release state.
When “RR”=“00H”, the change volume (level attenuation
volume) is minimum (0). When “RR”=“1FH”, the change
volume (level attenuation volume) is maximum (MAX).

deDL{4:0] (R/W) ; Decay Level
Designates the upper 5 bit of the attenuation level (EG) thatmoves from decay 1 state to decay 2 state. When the upper
decay 1 state attenuation level upper 5 bits match the DL value,
the state moves to decay state 2. When “DL”=“00H”, the levelis maximum (MAX). When “DL”=“1FH”, the level is minimum(MIN).

nfi

KRS[3:0] (R/W) Key Rate Scaling
Designates the level of EG key rate scaling condition. 00H
indicates minimum scaling; 0EH designates maximum scaling.
When set to 0FH, it designates that scaling OFF.

Co

LPSLNK (R/W) ; LooP Start LiNKThe function of the “LPSLNK” (loop start link) is to synchronize
the transition to decay 1 state from the loop start and EG attack
states.
When “LPSLNK” =“0” there is no relation between the EG statetransition and the loop start point position. When “LPSLNK”=“1”, the following two changes can be seen.

SEGA1) When, in terms of time, EG reaches “000H” in the attack state faster than when
the wave form read address reaches the loop start point (“SA”+”LSA”) (Figure4.15). In this case, EG will reach the MAX level first (P.1). However, since
moving to the next segment is not possible (decay 1 state) until the wave form
read address reaches the loop start point, EG is maintained at MAX level. Next,
when the wave form read address reaches the loop start point (P.2) EG will moveto the decay 1 state.

Saturn SCSP User's Manual

43

P.1

P.2

000 H

EG
DL

3FFH
AttackState

AttackState

Time

Decay 1StateADDRESSdeWave Form
Data

nti
al

EG

SA

LSP (SA+LSA) :LOOP START POINT

nfi

Figure 4.15 Transition (1) from the Attack State to Decay 1

2) In terms of time, EG reaches “000H” in the attack state slower than when the
wave form read address reaches the loop start point (“SA”+”LSA”).
This pattern has an additional two patterns.

EGCo- When the wave form read address reaches the loop start point, and the “SCL”
at this point (EG level) is larger than the “DL” (decay level) (reversed whencompared to the actual EG level). (Figure 4.16)

SCL: SEGMENT CHANGE LEVEL

000 H
P.
1

SCL>DL

GA

EG
3FFH

AttackState

Decay 1
State

P.2
DL
Time
Decay 2
State

SE

Wave Form
Data

SA

LSP (SA+LSA) :LOOP START POINT

Figure 4.16 Transition (2) from the Attack State to Decay 1

44

ADDRESSnti
alAfter the wave form read address reaches the loop start point, the EG will shift tothe decay 1 state (P.1). Next, when the EG value reaches the DL (decay level), it will
shift to the decay 2 state (P.2).
- When the wave form read address reaches the loop start point, and the “SCL”
at this point (EG level) is smaller than the “DL” (decay level) (reversed whencompared to the actual EG level). (Figure 4.17)

EG
000 H

EG

de

SCL: SEGMENT CHANGE LEVEL
P.1

SCL<DL (SCL=DL)

DL

3FFH

Wave Form
Data

ADDRESSLSP (SA+LSA) :LOOP START POINT

Co

SA

Time

nfi

Decay 1
StatusFigure 4.17 Transition (3) from the Attack State to Decay 1

SE

GA

After the wave form read address reaches the loop start point, the EG will shift tothe decay 1 state (P.1). After this, since the EG value will no longer reach the“DL” (decay level), it will continue to retain level 0 (EG value is “3FFH”) without moving to decay 2 state.

Saturn SCSP User's Manual45

FM Modulation Control Registernti
alSOUS[15:0] (R/W) ; SOUnd Stack
This is a data buffer for a slot output. It is a 64 word ring bufferthat can hold two generations of sampling data. This is used inaddition to processing between slots and modulation.
MDL[3:0] (R/W) ; MoDuLation level
Specifies the effects (modulation rate) of modulation to themodulation input source.

MDL

[3:0]

de

Table 4.15 Modulation Rate According to the Register Set Value

0 ~ 4

5

6

7

8

9

A

B

C

D

E

F

0

1/16

1/8

1/4

1/2

1

2

4

8

16

32

64

Modulation Rate (± n π)

Co

nfi

MDXSL[5:0] (R/W) ; MoDulation input-X SeLect
Designates the source to be used as modulation input X. The
modulation input X source slot is specified by two complimentary numbers showing the relative number from the current
slot. Also, when this value is within the range “1CH” to 3BH” itshows the latest generation; if out of range it shows one sample
past the latest generation. (See Table 4.16)

GA

MDYSL[5:0] (R/W) ; MoDulation input-Y SeLect
Designates the source to be used as modulation input Y. The
modulator input Y source slot is indicated by two complimentary numbers showing the relative number from the current
slot. Also, when this value is within the range of “1CH” to 3BH”
it represents the latest generation; if out of range it represents 1
sample past the latest generation. (See Table 4.16)

SE

STWINH (R/W) ; STack Write INHibit
When this bit is “1B”, writing the slot output to the direct data
stack (“SOUS”) is inhibited. Normally “0B” is fine.

46

Using the FM Sound Generator Method

SOUND
STACK
DATA

SOUND
STACK
DATA

de

PLFO

nti
al

The FM sound generator method is a method in which modulation is performed byadding different wave form generator output to the wave form generator phase
input. FM voice mixing is accomplished by a wave form calculator unit called a slot.
Figure 4.18 shows a block diagram of a slot.

Averaging Operation
Unit

PG

nfi

Waveform Phase
Value

PHASE ADDEREGMEMORY ADDRESS

Waveform
Data
BufferWAVE DATA

Co

ALFO

GA

Level Coefficient(Volume)SE

Output to DIRECT & DSP

Saturn SCSP User's Manual

Waveform RAM

Waveform
Address
Pointer

Waveform Level
Calculation

SLOT OUTPUT

Figure 4.18 SLOT Block Diagram

47

nti
al

To output a sound from a slot, wave form data required to run the slot is written to
the wave form RAM. Sound is started by the wave form read address, loop start
address, loop end address, sound pitch, sound level, setting the various EG settings,
and turning KEY_ON. SCSP operates as one large cycle of 22.68[µ sec] as a whole.

X SOUSY SOUS

AveragingOperation Unit
Modulation
Operation Unit

ADDRESS
POINTER

Adder/
Subtractor

Co

Phase Adder

nfi

P G

de

The PG (Phase Generator) controls the reading rate of the waveform, which is determined by the sound generation frequency setting. As long as the sound frequency
isn’t changed, the PG creates a fixed value per 1Fs cycle (22.68[µ sec] = 1/44.1KHz),
and it does a cumulative addition per Fs cycle and outputs. As shown in Figure
4.19, this is added to each address pointer. The resulting values are output to theaddress bus as wave form address and the wave form data in RAM corresponding
to those wave form addresses are read.

MDL

SA

Coincidence/
Comparitor Circuit

LSA

Coincidence/
Comparitor Circuit

LEA

Address Output

GA

Figure 4.19 Wave Form Address Generator

Wave Form
ADDRESSSE

Amplitude(Wave Form on the
Wave Form RAM)Time / Phase
Correlation

TIME(Address PointerOutput Value)(Wave Form Readout
Value)

Figure 4.20 Creating Wave Form Addresses and Reading Wave Form Data

48

nti
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When the oscillation frequency is constant (PG internal generations are constant for
all Fs cycles), the address pointer output becomes a straight line (as shown in Figure4.20), and can be read without changing wave form on the wave form RAM.
The address pointer may appear to be a straight line, but because calculations are
performed per 1Fs cycle, they will create a line like the stairs shown in Figure 4.21.
These steps become the PG internal generator value.

WAVE
ADDRESSdePG Internallygenerated value.

TIME

nfi

Each 22.68 µ sec intervals

Figure 4.21 Expanded Address Pointer Output Diagram

Co

If the frequency is increased, the PG creation value will increase, causing sharp slope
for the PG output and address pointer output value (function).

SE

GA

On the other hand, if the frequency is decreased, the PG creation value will be reduced, causing a softer slope for the PG output value and address pointer output
value (function) as shown in Figure 4.22.

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49

Wave Form
ADDRESS• If the frequency
is increased

Amplitude(Wave Form in the
Wave Form RAM)nti
alTime Phase Correlation(Output value of theaddress pointer)de

Wave Form
ADDRESS(Wave form read value)• If the frequency
is decreased.

nfiTime Phase Correlation

Amplitude(Wave Form in the
Wave Form RAM)

(Output value of theaddress pointer)(Wave form read value)Co

Figure 4.22 Frequency Address Pointer Output Value

When FM voice mixing is performed, short cycle wave forms are looped. Therefore,
the output value (function) of the address pointer is similar to Figure 4.23 below.

Wave Form
ADDRESS

Address Pointer Output(Phase)

GA

RAM
Data

SE

Amplitude(Wave Form in the
Wave Form RAM)

TIME
(Output value of the address pointer)(Wave form read value)

Loop Start Address (LSA)a: Start Address (SA)b: Loop End Address (LEA)

Figure 4.23 Address Pointer Output Value During FM Voice Mixing Execution(1)50

Wave Form
Address Address Pointer Output(Phase)deLinear (A)ntialThe start address is set in address “a”, while the loop start address is set to “0000H”.
The wave form read address and the wave form loop start address are both set to thesame address. Furthermore, the “b” address is set with the loop end address, so it
becomes the wave form loop end address. Results are shown in Figure 4.23.

Nonlinear (B)(Output value of the address pointer)(Wave form read value)nfi

Amplitude(Wave Form in the
Wave Form RAM)

Figure 4.24 Frequency Address Pointer Output Value During FM Voice Mixing Execution (2)Co

If you take the address pointer values and plot them linearly (Wave form A) it
would show the RAM wave form output (wave form 1). However, if it is a nonlinear function (wave form B) then the wave form read method will be different and(2) wave form will be output. If the wave form changes in this manner, the tone of
the sound will change.

SE

GA

The FM voice mixing method is applied by changing the phase value over time todistort the wave form. The FM voice mixing method uses the address pointer output value (phase value) in a non-linear form. Actually, it uses the method whichadds the output values of other (in some cases, it adds its own) slots shown in Figure
4.24 where the output values from other slots (same slot depending on conditions)are added. Up until this point, normal mode has been used, but it is possible to set
reverse loop and alternative loop by changing the “LPCTL” register. Loop data thatcan be designated in “LPCTL” register are shown in Figures 4.25, 4.26 and 4.27.

Attack Data

Saturn SCSP User's Manual

Loop Data
Figure 4.25 Normal Loop

51

de

nti
al

Loop Data

Attack Data

Attack Data

Co

nfi

Figure 4.26 Reverse Loop

Loop Data

Figure 4.27 Alternative LoopGA

Because the premise is that the data corresponding to “LSA” and “LEA” to be thesame in terms of normal loop and reverse loop, create the loop data by copying“LSA” data to “LEA”.

SE

The set value of alternative loop must always be set so that “LSA”<“LEA.” (If in anyof the loops “LSA”>“LEA”, operation can not be guaranteed.) Also, by placing datawith overlapping loop start point and loop end points the alternative pitch can bemade to match the pitch in other loop modes. When all of the wave form loop
modes are limited to the alternative loop, data corresponding to “LSA” and “LEA”
need not be the same.

52

X IN

Y IN

SOUND
STACK
DATA

PLFO

Wave Form
Phase Value
Phase Adder
Address PointerWave Form
Address
Pointer

Wave Form
Data
BufferEG

MDL

Wave Form RAM

SOUND
STACK

MEMORY ADDRESSWAVE DATA

Co

"O H"
SELECTOR
2 TO 1

MDYSL

nfi

ALFO

SOUND STACK2deAveragingOperation Unit

SOUND STACK0
SOUND STACK1

SOUND
STACK
DATA

MDXSL
PG

nti
al

Figure 4.28 shows how the actual FM voice mixing is performed in a block diagram.

Level (Volume)
Coefficient

Waveform
Data

Level Multiplier

EGDIS

SOUND STACK61
SOUND STACK62GA

SLOT OUTPUTSLOT OUTPUT(TO DIGITAL MIXER)WRITE to
SOUND STACKSOUND STACK63

STWINHSE

Figure 4.28 FM Sound Generator Configuration

Saturn SCSP User's Manual53Each block in the FM sound generator configuration diagram is explained below.

ntialSOUND STACKStores the output of each slot. The output values (soundstack internal data) from two slots can be input into the
SCSP slot.
Averaging Operation Unit

nfi

de

Each slot has X and Y modulator input slots. These
values must be added together to combine them into one.
To avoid having the results of the addition go into overflow, the two input values are multiplied by 1/2 before
adding them together. By incorporating this method, the
SCSP can take two input values and convert them into
one output data.
By showing input data as XD and YD and the output
data as ZD, the following equation can be produced.

YD

XD

+ YD
2

Averaging Operation Unit

Co

ZD =

XD

ZD

Figure 4.29 Averaging Operation Equation

GA

Because this equation is the same as the equation for
obtaining the average value, this block is called theaveraging operation unit.
MDL[Modulation Level (Variation Amount)]
Used to adjust the degree of the FM effect through theexternal slot input.

SE

Phase Adder

54

Adds (subtracts) the phase value generated by PG (phase
generator), and the phase value generated by the MDL
calculation after passing through the averaging arithmetic unit.

Level Multiplier

Wave Form RAM
RAM for sound.

ntialMultiplies the wave form read from the wave form
memory, the ALFO, TL (Total Level), and the level coefficient generated by the EG. Also adjusts the actual wave
form output level.

nfi

Wave Form Data BufferdeWave Form Address PointerThis block generates the actual wave form memory
address by taking the SA (start address) set for each slot
and the wave form phase value output from the phaseadder and adding or subtracting them. The loop control
and the loop status determines whether to add or subtract.

Memory used for temporary storage of wave forms readfrom the wave form memory.
PG (Phase Generator)

Co

Controls the read speed of the sound frequency wave
form. (Actually, it performs skip reading.)

EG (Envelope Generator)

SE

GA

Generates the time-based variations of the value (envelope curve) based on each rate or level setting. The value
created here is multiplied with the wave form data after
it is sent to the level multiplier. This causes timingchanges in the wave form output.

Saturn SCSP User's Manual55

Numbers in boxes indicate slot numbers.

(1/44.1K)/32=708nsec
Past Cycle

Current Cycle

26

27

28

29

30

31

0

1

2

3

4

O P 2

25

26

27

28

29

30

31

0

1

2

3

O P 3

24

25

26

27

28

29

30

31

0

1

2

O P 4

23

24

25

26

27

28

29

30

31

O P 5

22

23

24

25

26

27

28

29

30

O P 6

21

22

23

24

25

26

27

28

29

O P 7

20

21

22

23

24

25

26

27

28

S.STK

20

21

22

23

24

25

26

:

O P 4 :OPERATION 4:

O P 5 :OPERATION 5
O P 6 :OPERATION 6
O P 7 :OPERATION 7

:
:
:

7

4

5

6

3

4

5

0

1

2

3

4

31

0

1

2

3

30

31

0

1

2

29

30

31

0

1

0

1

nfi

O P 3 :OPERATION 3

6

27

28

29

30

31

PG Calculation Process, PLFO Calculation Process
Address pointer
ADP (Address
Panter) Calculation Process
MD (Modulation Data) Read (From the Sound Stack)Executing in timing shown byin drawing
Read Wave Form Data (FROM DRAM)
Executing in timing shown byin drawing
Interpolate Calculation Process, EG
Calculation Processing ALFO Calculation Process
Level Calculation Process
Level Calculation Process
Writes the Wave Form Output Value to the Sound
Stack.
Executes in the timing shown by the -->and ↓ inthe drawing.

Co

:
:

5

de

O P 1

O P 1 :OPERATION 1
O P 2 :OPERATION 2

ntial

The connections between the slots (actually, connections between the sound stackand the slots) are important for FM voice mixing. The slot calculations in Figure 4.28
FM voice mixing diagram can be shown like Figure 4.30 below.

GA

Figure 4.30 Slot Calculation and Sound Stack StateSE

Slot calculation starts with the PG calculation process and the PLFO calculation
process (OP1), with the remainder executed in the following cycle: ADP (address
pointer) calculation processing and MD (modulation) data read (OP2), wave form
data read (OP3), interpolate function process and EG calculation processing and
ALFP calculation processing (OP4), level calculation processing (OP5) (OP6), wave
form output value sound stack write (OP7). The calculation process of the levelcalculation takes a long time, so two cycles are required. If looking at a snapshot of
the calculation process, for example, slot 3 is doing PG calculation processing and
PLFO calculation processing while ADP calculation processing and MD read are donein slot 2. Meanwhile, wave form read in slot 1, interpolate calculation process, EG
calculation process and ALFO calculation process in slot 0, level calculation process
in slot 31 and slot 30, and sound stack writing in slot 30 are also being executed.

56

nti
al

Because slot calculation starts at slot 0 and moves towards slot 31, the data written to
the sound stacks also start at a low number and move up. However, there is a timedifference between the time the slot calculation starts and the time the slot is written
to the sound stack, which is equal to the calculation execution time. For example
Figure 4.31 shows that it would take six cycles worth of time for slot 0 to be written
to the sound stack.
As shown in Figure 4.30, when connecting a slot to another slot, the slot being connected to must already have written its data to the sound stack when it is in the OP2state or the connection cannot be done.

deFor example, since up to 27 slots are written to the sound stack, up to “27” colorcoded sound data sets are applicable to slots that can be connected to slot 0 whenOP2 is slot 0. An equation expressing this would be as follows.

{Current slot number + 32 –number of the slot to be connected (sound stack) + A} ≥ 5nfi

The current slot number represents the register slot number. However, if the soundstack of the slot to connect is in the current slot, then A is “32”; for past cycles, enter“0”. Here the past cycle indicates the cycle data from one sample previous.

Co

Past
Cycle

op1

30

31

0

1

2

3

4

5

6

7

op2

29

30

31

0

1

2

3

4

5

6

op3

28

29

30

31

0

1

2

3

4

5

op4

27

28

29

30

31

0

1

2

3

4

op5

26

27

28

29

30

31

0

1

2

3

op6

25

26

27

28

29

30

31

0

1

2

op7

24

25

26

27

28

29

30

31

0

1

S.STK

24

25

26

27 28 29 30
31
6 Cycles Worth ofTime Until SLOT0 is
Written to the Sound
Stack

0

1

GA
SE

Current
Cycle

S.STK: Sound Stack

Figure 4.31 Time Lag until the Slot Is Written to the Sound Stack

Saturn SCSP User's Manual

57

nti
al

At least two slots must be connected to enable voice mixing. Explained below is thecalculation method used for “MDXSL” and “MDYSL” (each 6 bits).
When two slots are connected, the slot applying modulation (Modulator) is M, while
the slot being modulated (carrier) is called C. The results of M–C are called J, withthe resulting equation shown below.
M

–

C

=

J

.

.

.

.

equation 4.1

The resulting J value changes the “MDYSL” and MDSYL” highest bit (6th in MSB)
value. The conditions for this are shown below.

de• Condition 1 J ≥ 28
- Convert the J value into hexadecimal 5 bit value.
- If it is the newest sample then MSB (6th bit) is “0B”; if pastsamples, it is “1B”.

nfi• Condition 2 J < 0 (J is negative)- Calculate 32 + J (calculate 10 decimal)- Next convert the value from (1) to a hexadecimal 5 bit value.
- If it is the newest sample then MSB (6th bit) is “0B”, if pastsamples, then it is “1B”.

Co• Condition 3 When the value J does not fit in neither condition 1 nor 2 above.
- Convert the J value into hexadecimal 5 bit value.
- If it is the newest sample then MSB (6th bit) is “1B”, if pastsamples, then it is “0B”.
Following are items to be aware of when using FM voice mixing.

GA

Slot Input Output
X

Modulator Input

Y ··· Modulator Input

SLOT

Waveform Data Output

X

AveragingOperation Block
To ADDRESS POINTER

SE

Figure 4.32 Slot Averaging Calculation

58

Y
=

X+Y
2

nti
al

The source input into a slot is the data in the sound stack (“SOUS”). Therefore,
modulating with a slot indicates that the sound stack corresponding to the modulation slot is assigned and connected to a non-modulation slot. Actual functions
include selecting the sound stacks input for modulator input Y and X, using“MDXSL” and “MDYXL”; therefore, the parameters obtained using the calculation
method explained at the beginning of this register is required.

deAlso, there are two modulator inputs to the slot, X and Y. Be aware that these may
be cut in half through the averaging calculation. Therefore, if only one slot is being
connected to the slot, X and Y are set with the same parameters and the same slot
sound stack data should be input. If only one side is set for input, then unexpected
data may get in and make the FM modulation rate could seem smaller, or other such
effects.
Next, determine each parameter using the “MDXSL” and “MDYSL” calculation
method withfour slot configurations using the actual FM voice mixer as an example.

S1

S0

Sn: Shows Slot n

S2

CoArrow shows
data flow.

nfi

First, explain how to get the FM voice mixer algorithm as shown in Figure 4.33.

S3

Algorithm sample(Y M 2 1 5 1 : FM CONNECTION)

GA

Figure 4.33 4SLOT configuration AlgorithmSE• Slot0
Slot0 output is used as input for slot 2, but the output of slot0 is used for the
input of slot0. This is called self feedback.
• Slot1
Slot1 output is used as input for slot2.
• Slot2
Slot2 uses the output of slot1 and slot0 as its input. This output is used as input
for slot3.

Saturn SCSP User's Manual59

(1) Parameters set in SLOT0.

SOUND STACK
SLOT0

nti
al

• Slot3
Slot3 uses slot2 output as input. Slot3 output is not connected to anything, but isused as voice output.

SLOT0
Y

de

X

SLOT0

[FM Algorithm][Actual diagram]

nfi

SLOT0

Figure 4.34 SLOT0 AlgorithmCo

For a self feedback type configuration such as slot 0, connect the sound stack that
stores the slot 0 output data to the modulation input X and Y.
There are three different ways of input methods to input the latest and past sample
to both modulation input X and Y, or latest sample to one side and past sample toanother since there are latest and past sample currently calculated in sound stack.
In the case of self feedback, oscillation may occur as the same sample is input. So
please input latest samples to one side and past samples to the other.
The values of <MDXSL and MDYSL are both 0 for the modulator slot and themodulated slot, so entering these values into equation 4.1 produces the following
results.

GA

Caution:

0

–

0

=

0

This meets the requirements of condition 3 in equation 4.1, so MSB of MDXSL and
MDYSL are as follows.

SE

Latest samples
Past samples

60

MSB=1 (100000)B
MSB=0 (000000)B

= 20H
= 00H

SLOT1ntial(2) Parameters set in SLOT2SOUND STACK
SLOT1
SLOT0
X(Y)
Y(X)

SLOT0

SLOT2

SLOT2

[Actual diagram]de[FM Algorithm]

Figure 4.35 SLOT2 Algorithm

nfi

Because slot 2 is input for multiple slots, there is no need to worry about whether touse latest or past samples.
The “MDXSL” and “MDYSL” values input (slot 1 side) into slot 1 are “1” for themodulator slot and “2” for the modulated slot. Applying this to equation 4.1 resultsin the following.
–

2

=

–1

Co

1

This meets the requirements of condition 2 in equation 4.1, so the MSB of “MDXSL”
and “MDYSL” are as follows.

GA

32 + (–1) =Latest samples
Past samples

SE

SLOT1

31

= 1FH = (011111)B
MSB=0 (011111)B = 1FH
MSB=1 (111111)B = 3FH

SLOT0

SLOT2

SLOT2

SLOT1 Side

SLOT0 Side

Figure 4.36 SLOT2 Algorithm (By input slot)

Saturn SCSP User's Manual

61

0

–

2

=

nti
al

The “MDXSL” and “MDYSL” values input (slot 0 side) into slot 0 are “0” for themodulator slot and “2” for the modulated slot. Applying this to equation 4.1 resultsin the following.
–2

This meets the requirements of condition 2 in equation 4.1, so the MSB of “MDXSL”
and “MDYSL” are as follows.

Note:

30

= 1EH = (011111)B
MSB=0 (011110)B = 1EH
MSB=1 (111110)B = 3EHde32 + (–2) =Latest samples
Past samples

As a rule, always input the same generation sample when inputting slots with different
numbers. Past FM sound generators have used this method, so when replacing an FM
sound generator tone library, use this method.

nfi(3) Parameters Set in Slot 3

SOUND STACK
SLOT2

SLOT3

Co

SLOT2

SLOT3

[FM Algorithm][Actual diagram]

GA

Figure 4.37 SLOT3 Algorithm

Because there is only one input for slot 3, input the output of slot 2 for the modulator input of both X and Y.

SE

If the connected slots are different, there is no chance of oscillation, so both modulator input X and Y can have just the latest sample, or just the past samples, or thelatest in one side and past in the other side. If replacing an existing FM sound generator tone library, use one sample or the other.

62

2

–

3

=

–1

nti
al

The “MDXSL” and “MDYSL” values input into slot 2 are “2” for the modulator slotand “3” for the modulated slot. Applying this to equation 4.1 results in the following.

This meets the requirements of condition 2 in equation 4.1, so the MSB of “MDXSL”
and “MDYSL” are as follows.
31= 1FH = (011111)B
MSB=0 (011111)B = 1FH
MSB=1 (111111)B = 3FH

SE

GA

Co

nfi

de

32 + (–1) =Latest samples
Past samples

Saturn SCSP User's Manual

63

nti
al

Up until now, “MDXSL” and “MDYSL” values have been achieved through calculation. However, by using the parameter table shown in Table 4.16, and from themodulator and carrier slot numbers, we can get the output of the “MDXSL” and“MDYSL” values.
Below, using the parameter table, the values for “MDXSL” and “MDYSL” can befound in Figure 4.33.

Parameters set in slot0
Slot 0 is a self-feedback configuration so the carrier slot number and themodulator slot number are “00”. From this, “MDXSL” and “MDYSL” values
from the parameter table are as follows.
Latest samples
20H
Past samples
00H

de

(1)

As explained earlier, if the same generation samples are used in the selffeedback configuration, there is a chance for oscillation, so avoid this method.

nfiParameters set in slot2
Slot 2 uses the multiple input configuration.
First, when slot 1 is input, the carrier slot number is “02” and the modulator
slot number is “01”. The MDXSL” and “MDYSL” values from the parameter
table are as follows.
Latest samples
1FH
Past samples
3FH

Co

(2)

Next, when slot 0 is an input, the carrier slot number is “02” and the modulator
slot number becomes “00”. The MDXSL” and “MDYSL” values from theparameter table are as follows.
Latest samples
1EH
Past samples
3EH
Parameters set in slot3
Slot 3 uses the output of slot 2, thus the carrier slot number is “03” and themodulator slot number is “02”. The “MDXSL” and “MDYSL” values from theparameter table are as follows.
Latest samples
1FH
Past samples
3FH

SE

GA

(3)

64

GA

Co

nfi

de

nti
al

Table 4.16 Relation of MDXSL/MDYSL and SLOTSE

How to use the table
First find the carrier side slot number and then find the modulator slot number
which is input into the carrier side. Find the number of sample that correspondsin the horizontal column.

Saturn SCSP User's Manual

65

nti
al

Next, the “MDL” (Modulation Level) will be explained. “MDL” is the modulation
rate (how much modulation) parameter used to set the modulation signal added tothe modulation input X and Y. If this value becomes large, the frequency modulation will be quite deep; if the value becomes small, the level will be more shallow.
(Figure 4.38)

de

MDL Largenfi

The only thingthat changes in
the MDL variations
is the amplitude.
(The intersection
does not change.)

MDL SmallIntersection

Co

Figure 4.38 MDL Modulation Rate

Here the modulation rate of the “MDL” set value is explained. Table 4.15 shows themodulation rate becomes ± n π by the “MDL” setting.

GA

Each sound slot data item input into the modulation input X and Y is averaged in
the averaging calculation block. Data input into X is XD, into Y is YD, and let theoutput to averaging calculation block be ZD, then the following equation can be
represented.
ZD

=

(

XD

+

YD

)

/

2

SE

This “ZD” is adjusted by the “MDL” and sent to the slot address pointer (phaseadder).

66

No modulation input

Read
wave
form
address

With modulation input(sine wave input)

nti
al

Phase

Phase

At negative
maximumshift

At positive
maximum
shift

Time

Time

de

Figure 4.39 Maximum Shift of the Wave Form Read Addressnfi

When modulation wave form is not added to FM voice mixing, the time phasefunction is linear. However, if the modulation waveform is added, because a phaseshift equivalent to the modulation waveform will be added, the linear time-phase
waveform will then become non-linear. This shift becomes maximum when ZD
assumes the ± maximum value. MDL modulation rate indicates the wave form
address shift (maximum shift) when the wave form data (sine wave) is at 1 cycle =1Kword and ZD is ± the maximum value.
Table 4.17 Address Maximum Shift Value According to the Register Setting Value

0 ~ 4
0

5

6

7

8

Co

MDL [3:0]
Address max.
shift ±

32

64

128

256

9

A

B

C

D

512

1024 2048 4096 8192

E

F

16384

32768

GA

Compare Table 4.16 and Table 4.17 to get the function π = 512 (when MDL=AH). In
Table 4.16, there is wave form data (sine wave) consideration where 1 cycle = 1K
word (1024 words), but mathematically 1 wave form cycle length is defined as 2π.
Therefore, in the current FM voice mixer the sine wave used is 1 cycle = 1 Kword so
the maximum shift of 512 can be expressed as π. Using π to express the shift is only
valid when 1 cycle of wave form data is 1 K word. Otherwise, use the expression
method by address shift shown in Table 4.17.

SE

When using the FM voice mixer, always have three cycles of wave form data. The
reason has to do with address shift. The SCSP hardware must hold up to 1Kword
address shift (MDL=“AH”), but if the amount exceeds 1Kword, the hardware willautomatically execute clipping processing, so there is no need to have extra wave
form data equal or greater than 1Kword.

Saturn SCSP User's Manual

67

LEA
+π shift range

ntialSA/LSA-π shift range-2 π shift range+2 π shift range
1 K

However, be aware that 1 K=210 =1024.

de

1 K

1 K

Figure 4.40 Address Shift during FM Voice Synthesis

nfi

During FM voice mixing, place only the additional amount required for address
shift. As a rule, operation will run without problems if π worth of wave form data is
set before “SA”, and after “LEA” and is ± π. However, using three cycles worth ofdata as shown in Figure 4.40 is the ideal setting method.

Co

Concerning Clipping ProcessThis relates to the address shift described earlier. The address shift range shifts a
maximum of ± 32768 addresses, so before and after the basic wave form respectively 32 cycles (32Kwords) and 16 cycles (16Kword) worth of wave form data isrequired for total memory requirements of 65Kwords.

SEGA

For this reason, the SCSP clips (process to prevent shift from exceeding a limit) shiftthat exceeds 1K word and returns the shift to 0. So if there is 3K word worth ofwave form data no matter how much shift there is, it is more than enough to coverrequirements. Clipping process was done because the valid address bits available
for shift was 10.

0

Phase

2π

Auxiliary wave form

Figure 4.41 Wave Data During Clipping Process

As shown in Figure 4.41, even if the wave form exceeds the auxiliary waveform after
the shift, it returns to 0 at the point where phase exceeds 2π.

68

SLOT

SLOT

SLOT

SLOT

nti
al

The following is an explanation of the SCSP FM configuration (algorithm). The
SCSP slot is configured with two inputs and one output so the number of slots thatcan be connected (modulation can be applied) to one slot is a maximum of two.

SLOT

SLOT

SLOT

This is not possible

deThis is possible

Figure 4.42 Slot Connection Countnfi

As shown in Figure 4.42, modulation is possible if it’s up to two modulators. Also if
the modulation data (source) is brought up from the sound stack, FM configurations
shown in Figure 4.43, Figure 4.44, Figure 4.45, and Figure 4.46 are possible.

SLOT

SLOT

The algorithm for bothleft and right diagramsis the same

GA

SLOT

Co

(Figure 4.43 is a self-feedback slot with still another slot modulating the first slot;
Figure 4.44 combines multi-stage slots for a multi-stage feedback; Figure 4.45 combines the multi-stage feed back and self feedback for a composite-type feedback;Figure 4.46 shows a composite modulation type slot modulated by a multi-stage
feed back and further modulated by another slot.)

SLOT

SE

Figure 4.43 Self-Feedback Modulation

SLOT

SLOT

SLOT

SLOT

Figure 4.44 Multi-Stage Feedback

Saturn SCSP User's Manual

Figure 4.45 Composite Feedback

69

nti
al

SLOT

SLOT
SLOT

SLOT

SLOT

SLOT

SLOT

de

Figure 4.46 Composite Modulation

Figure 4.47 and 4.48 show specific examples of a basic FM configuration whichshould be used as a reference for FM voice mixing. Each slot upper side has two
modulation inputs while the line on the lower side shows the slot output.

SLOT

SLOT

SLOT

Co

SLOT

nfi

In addition, make sure that the dotted lines are also connected (refer to theforementioned figures.

SLOT

SLOT

SLOT

SLOT

SLOT

SLOT

SLOT

GA

SLOT

SLOT

SLOT

SLOT

SE

SLOT

SLOT

SLOT

SLOT

SLOT

This is acomplished by mixing the lower stage slot output.

Figure 4.47 FM Configuration Algorithm Pattern 1

70

SLOT

SLOT

SLOT

SLOT

SLOT

SLOT

nti
al

SLOT

SLOT

SLOT

SLOT

de

SLOT

SLOT

Figure 4.48 FM Configuration Algorithm Pattern 2

nfi

If the uppermost slot in FM voice mixing does not have self-feedback, there is nothing to be connected. In this situation, set “0~4” values to “MDL” value and themodulation rate to “0”. This is how modulation input is set to “0”.

Co

Definition of the uppermost slot.
The uppermost slot is the highest slot in each of the algorithm towers. In Figure
4.49, there are three towers: the S0 tower, the S1, S2 tower, and the S3, S4, S5, S6
tower. The uppermost slots are S0, S1, and S6.

S6

S1
S2

S3

S4

1 SOUND OUTPUT
Figure 4.49 7 SLOT FM Configuration

SE

GA

SO

S5

Saturn SCSP User's Manual71Volume Register
TL[7:0] (R/W) ;Total Level

de

nti
al

The total value of attenuation volume of the area where
bit is set to “1”, which is within total level 8 bit, becomesthe actual attenuation volume [dB]. Therefore, the larger
the value set in “TL”, the larger the attenuation volume,
making the sound volume less. On the other hand, thesmaller the value set in “TL,” the smaller the attenuationlevel, and the greater the sound volume will be .
For example, “the attenuation volume with “FFH” would
be as shown below.
- 48 - 24 - 12 - 6 - 3 - 1.5 - 0.8 - 0.4 = -95.7[dB]
Table 4.18 TL, Attenuation, and Waveform Amplitude
TL
Attenuation
Amplitude
Ratio
Real Number
Ratio (times)

bit 7

bit 6

bit 5

bit 4

- 48

- 24

- 12

-6

1/256

1/16

1/4

1/2

0.00391

0.062500.25000

bit 3

bit 2

bit 1

bit 0

-3

- 1.5

- 0.8

- 0.4

8

1/ 16 2

1/

2

1/

4

2

nfi

TL bit0.50000

0.707110.840901/20.91700

0.95760

Co

If only bit 4 is set to “1”, then the amplitude of the output
wave form after the TL calculation will be 1/2 of theamplitude of the wave form in memory, as shown in
Figure 4.50.
1

GA

1/2

Data in the wave
form memory

Amplitude after TL
operation

SE

Figure 4.50 Wave Data when TL bit 4 = 1

SDIR (R/W) ; Sound DIRect
This flag is used to determine whether or not to directly
output the sound data. When this bit is “1,” then sounddata is output without being multiplied by EG, TL,
ALFO, etc., calculations.

72

PITCH Registernti
al

OCT[3:0] (R/W) ; OCTave
The function of the “OCT” register is to increase or decrease the sound generation frequency by octave withrespect to the wave form data stored in memory.

deFNS[9:0] (R/W) ; Frequency Number Switch
The function of this register is to adjust the tone between
the octaves raised or lowered with “OCT.” When the“FNS” and “OCT” values are both “0,” the tone matches
the sampling source data. Figure 4.51 shows the relationof the “FNS” and “OCT” values.
... OCT="DH" OCT="EH" OCT="FH" OCT="OH" OCT="1H" OCT="2H" OCT="3H" ...
... FNS="0H" FNS="0H" FNS="0H" FNS="0H" FNS="0H" FNS="0H" FNS="0H" ...
F/8
F/4
F/2
1F
2F
4F
8F

nfi

Frequency

FNS set range

Figure 4.51 Relation of OCT and FNS

Co

The actual pitch (n) is calculated by the equations shown
below.
1024 + FNS 



1024


n(Cent) = 1200 × LOG 2 1024 + FNS 



1024
LOG102
GA= 1200 ×SE1024 + FNS 



1024
0.30103= 1200 ×

Saturn SCSP User's Manual

LOG10 = 1200 ×

LOG10 LOG10(1024 + FNS) − 10 × 0.30103
0.30103

The value found with this equation is expressed in unitsof “Cents.”73

Fn [Hz] = Fox 2n/1200

ntial

One “cent” is 21/1200=1.000577789 times. Also, one
octave is 1200 cents. When cent = n, then 2n/1200 times{=(1.000577789)n} against the original frequency. Therefore, the equation below is used to find the n cent hightone frequency Fn [Hz] in relation to the basic frequency
tone Fo [Hz].

Table 4.19 shows the actual frequencies corresponding to
the cent count (number of cents).

Cent Count01.059463094

500
600

1.189207115
1.259921050
1.334839854
1.414213562
1.498307077

Co

700

1.122462048

nfi

200

400

Actual Frequency Value (XFo)
1.000000000

100

300

de

Table 4.19 Actual Frequency Corresponding to Cent Count800

1.587401052

900

1.681792830

1000

1.781797436

1100

1.887748625

1200

2.000000000

GA

Next, using the sound of C4 (do) sampled at a rate of
44.1KHz as an example, the method for setting “FNS” and“OCT” will be explained.
FNS = 210x (2P/1200_ 1)

SE

By setting each parameter as shown in Table 4.20 from thisequation, you can output at any frequency.

74

Table 4.20 FNS.OCT Parameter Table

59
60
61
61
63
64
65
66
67
68
69
70
71
72

FNS [9:0]
[DEC]
909.1
0.0
60.9
125.4
193.7
266.2
342.9
424.2
510.3
601.5
698.2
800.6
909.1
0.0

FNS [9:0]
[HEX]
38D
0
03D
07D
0C2
10A
157
1A8
1FE
25A
2BA
321
38D
0

OCT [3:0]
[HEX]
F
0
0
0
0
0
0
0
0
0
0
0
0
1

nti
al

B3
C4
C4#
D4
D4#
E4
F4
F4#
G4
G4#
A4
A4#
B4
C5

PITCH
[Cent]
1100
0
100
200
300
400
500
600
700
800
900
1000
1100
0

de

Note No.

SE

GA

Co

nfi

Note Name

Saturn SCSP User's Manual75

LFO Registernti
al

LFO is a low-frequency oscillator that is used for modulation of sound signals
The LFO is contained in each slot and has the amplitude modulation output andfrequency modulation output for that slot.

There are four types of output wave form from the LFO. These are: sawtooth wave,
rectangular wave, triangle wave, and noise (white noise). All of these can be selected
freely.

de

The LFO block diagram is shown in Figure 4.52. All waves (except the noise) can bereset and the frequency changed. Excluding the noise waveform, resetting as well aschanging the frequency of sawtooth waveform, rectangular waveform, and triangular waveform are allowed. Also, the modulation rate and the LFO wave form can be
set independently for both the amplitude modulation and the frequency modulation
side.

LFO wave form oscillator

nfi

ALFOWS

Sawtooth
wave

ALFOS

SELECTOR

Co

4

Rectangularwave

Triangularwave

To Amplitude
ModulationTO
1

Amplitude Modulation
Rate Adjustment

PLFOWS
LFOF

GA

LFORE

SE

White noise

PLFOS
SELECTOR
4TO
1

The MSB side is reversed so the
ALFO wave form and the
PLO wave form are different.

76

Figure 4.52 LFO Block Diagram

To Frequency
Modulation
Frequency Modulation
Rate Adjustment

LFORE (R/W) ;LFO REsetntialSets the LFO reset to yes or no. If this bit is set to “1”, the
LFO is reset. If “0” is written then operation starts.
LFOF [4:0] (R/W) ;LFO Frequency
Designates the LFO oscillation frequency.
Table 4.21 Oscillation Frequency of the Oscillator

Oscillation Frequency (Hz)
2.87
3.31
3.92
4.79
6.15
7.18
8.6
10.8
14.4
17.2
21.5
28.7
43.1
57.4
86.1
172.3

de

LFOF
10 H
11 H
12 H
13 H
14 H
15 H
16 H
17 H
18 H
19 H
1A H
1B H
1CH
1DH
1E H
1F H

nfi

Oscillation Frequency (Hz)
0.17
0.19
0.23
0.27
0.34
0.39
0.45
0.55
0.68
0.78
0.92
1.10
1.39
1.60
1.87
2.27

Co

LFOF
00 H
01 H
02 H
03 H
04 H
05 H
06 H
07 H
08 H
09 H
0A H
0B H
0CH
0DH
0E H
0F H

SE

GA

ALFOS[2:0] (R/W) ;Amplitude-LFO Sensitivity
Sets the degree of amplitude modulation through the
LFO. The tremor effect (a phenomenon that occurs when
the sound volume is changed in a cyclic pattern) can be
expressed through this amplitude modulation.

Saturn SCSP User's Manual

77

nti
al

ALFOWS[1:0] (R/W) ; Amplitude-LFO Wave SelectDesignates AM modulation wave form as shown in Table
4.22.
Table 4.22 LFO AM Modulation Wave Form by LFOALFOWS
Volume-0 dB

AM Modulation (ALFO)
ALFO[7:0]
0

0

-0 dB

FF
0

-0 dB

FF
0

2

-0 dB

FF
0

**************************************************************************Noise***************************************************************************

nfi

3

de

1

FF

Co

PLFOWS[1:0] (R/W) ; Pitch-LFO Wave SelectDesignates PM modulation wave form as shown in Table
4.23.
Table 4.23 LFO PM Modulation Wave Form
PLFOWS

Pitch

0

GA

1

2

SE

3

78

AM Modulation (PLFO)
PLFO[7:0]

+

7F

0

00

–

80

+

7F

0

00

–

80

+

7F

0

00

–

80

+

7F

0

00

–

80

**************************************************************************Noise***************************************************************************

ALFO[7:0] and PLFO[7:0] show the LFO output bit width(data).

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PLFOS[2:0] (R/W) ; Pitch-LFO Sensitivity
Specifies the degree of frequency modulation through the
LFO. The vibrato effect (a phenomenon that occurs when
the sound frequency is changed in a cyclic pattern) can be
expressed through this frequency modulation (Table
4.24).
Table 4.24 Rates of Amplitude and Frequency Modulation
PLFOS
0
1
2
3
4
5
6
7

Effect on Pitch
No effect
Displacement of ±7 cent
Displacement of ±13.5 cent
Displacement of ±27 cent
Displacement of ±55 cent
Displacement of ±112 cent
Displacement of ±230 cent
Displacement of ±494 centdeMixing to the EG
No effect
Displacement of 0.4 dB
Displacement of 0.8 dB
Displacement of 1.5 dB
Displacement of 3 dB
Displacement of 6 dB
Displacement of 12 dB
Displacement of 24 dB

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ALFOS
0
1
2
3
4
5
6
7

Saturn SCSP User's Manual79

MIXER Registerntial

The digital mixer block in the SCSP is used to adjust the level and balance of thevarious sound signals. It is made up of the direct mixer adjustment block, the DSP
input (stage adjust) mixer block, the DSP output (stage adjust) mixer block and thelast output (stage adjustment) mixer block. Figure 4.53 shows the digital mixer
block diagram.

DIRECT

IN
MIXER

OUT
MIXER

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DSP

de

LAST
MIXER

Figure 4.53 Digital mixer block diagram.
Direct Sound Adjustment Block

Co

This mixer block controls the circuit that connects the output of each slot directly to
the DAC output. It can control the output level (“DISDL”) and output balance(“DIPAN”) for each slot.
DSP Input Step Adjustment Block

Conducts mixings required to input the output of each slot to the DSP (“MIXS”). In
reality, in the “ISEL” of each slot, the “MIXS” that inputs audio signal is selected andthe input level is adjusted by the “IMXL”. When mixing multiple sounds with the“ISEL”, each of the sounds must be balanced.

GA

Because the “MIXS” can mix the output from multiple slots and then input theresult, the same effect like BGM reverb can be applied to many sounds. If effects at
the DSP are applied, the sound data is sent to “MIXS”.
DSP Output Step Adjustment BlockSE

The sounds that have had effects applied in the DSP or sounds that were brought infrom an external digital input pass through mixing processing and are eventuallycompiled in stereo. The output level (“EFSDL”) and output balance (“EFPAN”) canbe adjusted for sound signals that are output from the “EFREG” that correspond to
DSP, and “EXTS” that receive external digital audio input. The data compiled hereis mixed with the direct sound mixer.

80

Final Step Output Adjustment Blocknti
alCombines the direct component and the effect component of the sound and adjusts
the output level to the DAC. The final output level is adjusted by “MVOL”.

deAbout the direct component and the effect component
When effects are applied to sound, the sound without effects applied (dry) andsounds with effects applied (wet) are mixed with the appropriate balance foreach of the screens. The internal effect program separates the dry and wet datain the DSP. Because the sounds are mixed together in the end, when creating
dry and wet data in the DSP, there is no need to output the direct component.
This is accomplished by setting DISDL to “0” for no output. Figure 4.54 shows
the circuits of the direct component and the effect component.

From Slot

DSP Circuit

EFFECT

nfi

DSP

DIRECT
Component

MIXINGCo

EFFECT
Processing
MIXING
Processing

OutputDIRECT (DRY)+
EFFECT (WET)

DIRECT
Processing

When creating both direct andeffect components on the DSP
side, use the "DISDL" = "0" to cut
the direct component circuit.

GA

Figure 4.54 Direct and Effect Component Circuits

SE

When rewriting the DSP program, the DSP operation becomes unstable andthe sound will not be output properly from “EFREG”. Set “EFSDL” to “0H”
to prevent sound from being output.

Saturn SCSP User's Manual81Source Data

From Slot, etc.

DSP Block
Coefficient Data/ RAM

Source Data

Source Data X
Multiply

ESREG XESREG Y

Send levelcalculator

Send levelcalculator

Settings are optional, but it isbest to have both channels the same.

EFPAN X

Fixed position
calculator

Setting 1FH

X, Y values
are arbitrary

Fixed position
calculator

SE

GA

Figure 4.56 shows a digital mixer block diagram.

EFPAN Y
Setting 0FH

Right channel output

Figure 4.55 DSP Panning Calculation

82

EFSDL Y

Setting is arbitraryCo

Left channel output

Coefficient DatadeEFSDL X

Coefficient Data/ RAM

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Coefficient DataX
MultiplyntialAbout fixed position
The SCSP digital mixer supports 31 levels of panning, but to set it in even moredetail, use the DSP built into SCSP, as shown in Figure 4.55, to perform(process) panning.

Saturn SCSP User's Manual

83

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Cumulative Adder Block

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de

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Effect DSP

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Next, the method for setting each of the parameters based on Figure 4.56 will be
explained.
The settings of “IMXL”, “ISEL”, “DISDL”, and “EPSDL” are required as described
below to prevent overflow when many sounds are produced, and to prevent theoverall volume from being too low when only a few sounds are produced.

DSP Input Side Mixer
The parameters that are equivalent to the DSP input side mixer are the “IMXL”
and “ISEL” parameters.
“MIXS” (the mix stack will be explained later) can input the output of multiple
slots. This register has the ability to mix multiple data. Here the “IMXL” value
must be set at the correct level to prevent “MIXS” from overflowing.

de

(a)

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The number of available input sounds when the “IMXL” value is changed isshown in Table 4.25. For example, if “IMXL” is set to 7H against the input
source and the input level of “MIXS” to “0[dB]”, then the number of available
input slots would be one sound worth.
Table 4.25 Relation of the source count that can input into “IMXL” and “MIXS”
Level
Magnification
X0.000000
X0.015625
X0.031250
X0.062500
X0.125000
X0.250000
X0.500000
X1.000000

Sounds Available for Input(source count)– – Sounds
64 Sounds
32 Sounds
16 Sounds
8 Sounds
4 Sounds
2 Sounds
1 Sounds“DISDL” and “EFSDL”“DISDL” and “EFSDL” have basically the same philosophy as “IMXL,” butthey must determine the sound output total count.

GA

(b)

[dB]
–MAX
–36
–30
–24
–18
–12
–6
–0

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“IMXL” Value
[2:0]
0H
1H
2H
3H
4H
5H
6H
7H

SE

The sound output total count is the total sound output including the direct,
effect and external input components. This indicates the cumulative totalsources of L/R in Figure 4.56 that is being output. (L/R are counted as 1
together.) From this it is clear that the sum total of slots outputting sound is
not equal.

84

“DIPAN” and “EFPAN”
These registers are set at the center when setting value is either “00H” or“10H”. By setting the MSB to “0B” and increasing the size of the lower 4 bits
value, the fixed position will move to the right side.

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(c)

By setting the MSB to “1B” and increasing the size of the lower 4 bits value, thefixed position will move to the left side.

deIMXL[2:0] (R/W) ; Input MiXing Level
Designates the mix stack input level by slot when thesound slot output data is input into the DSP mix stack(“MIXS”).
Table 4.26 Mix Stack Register Input level

Level [dB]
– MAX (does not mix)
–36
–30
–24
–18
–12
–6
–0

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IMXL
0
1
2
3
4
5
6
7

Co

ISEL[3:0] (R/W) ; Input SELect
Designates the mix stack number for each slot when thesound slot output data is input into the DSP mix stack(“MIXS”).

SEGA

The mix stack (“MIXS”) finds the total of the input for all
the slots for DSP input. The mix stack does not have aprotect function for overflows, so set it so that the total of
all slots does not exceed “0 [dB].”

Saturn SCSP User's Manual85

Table 4.27 D/A Converter Output Level

Level [dB]
– ∞ (not sent)
–36
–30
–24
–18
–12
–6
–0

de

DISDL
0
1
2
3
4
5
6
7

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DISDL[2:0] (R/W) ; Direct SenD Level
Designates the output level by slot when direct data is
output to the D/A converter.

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DIPAN[4:0] (R/W) ; Direct PANpot
Specifies the fixed position (pan) for each slot when
direct data is sent out.
Table 4.28 Fixed Position (Pan) Data by DIPAN

DIPAN
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

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DIPAN Left Fixed (dB) Rt Fixed (dB)
00H
–00.0
–00.0
01H
–03.0
–00.0
02H
–06.0
–00.0
03H
–09.0
–00.0
04H
–12.0
–00.0
05H
–15.0
–00.0
06H
–18.0
–00.0
07H
–21.0
–00.0
08H
–24.0
–00.0
09H
–27.0
–00.0
0AH
–30.0
–00.0
0BH
–33.0
–00.0
0CH
–36.0
–00.0
0DH
–39.0
–00.0
0EH
–42.0
–00.0
0FH
–∞
–00.0

86

Left Fixed (dB) Rt Fixed (dB)
–00.0
–00.0
–00.0
–03.0
–00.0
–06.0
–00.0
–09.0
–00.0
–12.0
–00.0
–15.0
–00.0
–18.0
–00.0
–21.0
–00.0
–24.0
–00.0
–27.0
–00.0
–30.0
–00.0
–33.0
–00.0
–36.0
–00.0
–39.0
–00.0
–42.0
–00.0
–∞

Table 4.29 Send Level to the D/A Converter

Level [dB]
– ∞ (does not send)
–36
–30
–24
–18
–12
–6
–0

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EFSDL
0
1
2
3
4
5
6
7

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EFSDL[2:0] (R/W) ; EFfect SenD Level
Specifies the output level for each slot when wave form
data that has passed through the DSP and had effectprocess applied (effect data) is output to the D/A converter.

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EFPAN[4:0] (R/W) ; EFfect PANpot
Specifies by slot the fixed position of the external input
waveform data and the waveform data that passed
through the DSP and had the effect process applied(effect data).

Co

Table 4.30 Fixed Position Data from EFPANSEGA

EFPAN Left Output (dB) Rt Output (dB)
00H
–00.0
–00.0
01H
–03.0
–00.0
02H
–06.0
–00.0
03H
–09.0
–00.0
04H
–12.0
–00.0
05H
–15.0
–00.0
06H
–18.0
–00.0
07H
–21.0
–00.0
08H
–24.0
–00.0
09H
–27.0
–00.0
0AH
–30.0
–00.0
0BH
–33.0
–00.0
0CH
–36.0
–00.0
0DH
–39.0
–00.0
0EH
–42.0
–00.0
0FH
–∞
–00.0

Saturn SCSP User's Manual

EFPAN
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

Left Output (dB) Rt Output (dB)
–00.0
–00.0
–00.0
–03.0
–00.0
–06.0
–00.0
–09.0
–00.0
–12.0
–00.0
–15.0
–00.0
–18.0
–00.0
–21.0
–00.0
–24.0
–00.0
–27.0
–00.0
–30.0
–00.0
–33.0
–00.0
–36.0
–00.0
–39.0
–00.0
–42.0
–00.0
–∞

“EFSDL” and EFPAN” can set individual settings foreach of “EFREG” or “EXTS”. Figure 4.31 shows theregister address for “EFSDL” and EFPAN” that correspond to each “EFREG” or “EXTS”.

87

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Table 4.31 EFSDL, and EFPAN Register Addresses for Each EFREG and EXTS

Co

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MVOL[3:0] (W) ; Master VOLume
Represents the master volume output to the D/A converter. Because it is used to control the overall output
level, lowering the “MVOL” for an output that has
overflowed to a lower level will not remove the clipping
noise. (To remove the clipping noise, correct the“DISDL” and “EFSDL” settings to remove the overflow.)
DAC18B[3:0] (W) ; DAC out 18Bit
When setting the digital output as 18bit D/A converterinterface, set this bit to “1B”. When 16 bit, set “0B.” (Normally connected to an 16 bit type D/A converter so thisregister should be set to “0B”.)

SE

GA

SCSP

DAC
16bit format

Figure 4.57 SCSP and DAC Connections

88

Slot Status Registernti
alMSLC (w) ; Monitor SLot Call
Sets the number of the slot to be monitored with the“CA” register. In “0H” it is “SLOT0”, in “1FH” it is“SLOT31”
CA (R) ; Call AddressdeThe slot which has its number set in this register can readout the number of samples (number of samples = thenumber of wave form data samples) from the current
output waveform data “SA” (start address) address.
The value output here in the LSB (least significant bit)indicates 4K (4096) samples, so when the output value is“1H”, the slots being monitored are outputting at least
more than “SA” to 4K samples of wave form addresses.

nfiSound Memory Configuration Register

MEM4MB (w) ; MEMory 4MBit
Designates the capacity of the memory connected to the
SCSP.
Table 4.32 Memory Size

000000H

4Mbit
4Mbit

(1st)
(2nd)

Memory Capacity
Uses 1Mbit DRAM
Uses 4Mbit DRAM

When 1Mbit
1Mbit
1Mbit

000000H~01FFFFH
000000H~03FFFFH

(1st)

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07FFFFH
080000H

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MEM4MB
0
1

0FFFFFH

4Mbit

(2nd)

SE

Figure 4.58 Memory Address Mapping Diagram

MIDI Register
The SCSP has a 31.25Kbps transfer rate MIDI serial interface, however, a MIDI
peripheral circuit and MIDI DIN connector are not included. As a result, MIDI
applications cannot be created. Figure 4.59 shows the MIDI interface block diagram.

Saturn SCSP User's Manual89

M I D I- O U TSPP Converter

S Converter

STATUS

1 Byte BUFFER

1 Byte BUFFER

MIOVF

1 Byte BUFFER

1 Byte BUFFERMIFULL

1 Byte BUFFER

1 Byte BUFFERMOFOLLMIENP

1 Byte BUFFER

1 Byte BUFFER

MOEMPSCSP Internal Data Bus
P Conversion: Serial
Parallel Conversion)(P

S Converter: Paralle
Serial Conversion)de(S

MIDI-OUTntial

MIDI-INSTATUSM I D I- I N

Figure 4.59 MIDI-I/F Block Diagram

nfi

MIBUF[7:0] (R) ; Midi Input BUFfer
This is a MIDI input data buffer.
External data transferred into the MIDI-IN side is automatically stored in the MIDI-IN buffer “MIBUF”.

Co

MIOVF (R) ; Midi Input OVer-Flow
When the MIDI-IN buffer is completely full of data andmore data is transferred to the MIDI-IN, “MIOVF”
changes to “1B” to indicate an overflow has taken place.
When an overflow happens, the MIDI communications
will not work correctly, causing a MIDI transmission
error.

GA

MIFULL (R) ; Midi Input FULL
When all 4bytes of the MIDI-IN buffer is completely fullof data, the “MIFULL” will change to “1B” to indicatethat the buffer is full.

SE

MIEMP (R) ; Midi Input EMPty“1B” is set when the input FIFO is empty. When theinternal MIDI-IN buffer is emptied through the CPU, etc.,
reading data, and when there is nothing in the MIDI-IN
buffer, the “MIEMP” changes to “1B” to show that thebuffer is empty.

90

Figure 4.60 is a diagram of the MIDI-IN and the interrupt
generation block. Interrupts occur when the “MIEMP” is“1B” and receives external data and changes to “0B”.
When the MIDI-IN buffer is emptied through reading,etc., and MIEMP changes back to 1B, then the interrupt isreleased.

SCSPInterrupt for the
SCPU (MC86EC000)

ntialInterrupt for the
MCPU (SCU)
Interrupt Block
Interrupt flag

Interrupt command

M I D I Block

de

MIEMP
MIFULL
MIOVF

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Figure 4.60 MIDI IN Block and the Interrupt Generation BlockCo

MOFULL (R) ; Midi Output FULL
When all 4bytes of the MIDI-OUT buffer is completely
full of data, the “MOFULL” will change to “1B” to indicate that the buffer is full.

GA

MOEMP (R) ; Midi Output EMPty
When all of the data in the MIDI-OUT buffer has been
sent out and no data is transferred into the MIDI buffer,“MOEMP” changes to “1B” to indicate that the buffer is
empty. At the same time, an interrupt can be used to tellthe CPU that the buffer is empty. Figure 4.61 shows the
MIDI-OUT and interrupt generation block.
Interrupt for the
MCPU (SCU)

SE

Interrupt for the
SCPU (MC68EC000)SCSPInterrupt Block
Interrupt flag
Interrupt command
M I D I Block
MOEMP
MOFULL

Figure 4.61 MIDI OUT Block and the Interrupt Generation Block

Saturn SCSP User's Manual

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MOBUF[7:0] (W) ; Midi Output BUFfer
This is a MIDI output data buffer. For MIDI-OUT-side
transfer, write data (to be transferred) into “MOBUF”.
Afterwards, the data is automatically transferred.
Timer Register

The SCSP has three pre-scaler 8 bit up count timers: A, B and C. The pre-scaler
execute time is set individually by “TACTL”, “TBCTL” and “TCCTL.”

Table 4.33 Increment Cycle for Timer A

Increment Cycle
O n c e e v e ry s amp le
O n c e e v e ry 2 s amp le s
O n c e e v e ry 4 s amp le s
O n c e e v e ry 8 s amp le s
O n c e e v e ry 1 6 s amp le s
O n c e e v e ry 3 2 s amp le s
O n c e e v e ry 6 4 s amp le s
O n c e e v e ry 1 2 8 s amp le s

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TACTL
0
1
2
3
4
5
6
7

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TACTL[2:0] (W) ; Timer-A ConTroL
Designates the increment cycle for timer A.

Co

TBCTL[2:0] (W) ; Timer-B ConTroL
Designates the increment cycle for timer B.
Table 4.34 Increment Cycle for Timer B

Increment Cycle
O n c e e v e ry s amp le
O n c e e v e ry 2 s amp le s
O n c e e v e ry 4 s amp le s
O n c e e v e ry 8 s amp le s
O n c e e v e ry 1 6 s amp le s
O n c e e v e ry 3 2 s amp le s
O n c e e v e ry 6 4 s amp le s
O n c e e v e ry 1 2 8 s amp le s

SE

GA

TBCTL
0
1
2
3
4
5
6
7

92

Table 4.35 Increment Cycle for Timer C

Increment Cycle
O n c e e v e ry s amp le
O n c e e v e ry 2 s amp le s
O n c e e v e ry 4 s amp le s
O n c e e v e ry 8 s amp le s
O n c e e v e ry 1 6 s amp le s
O n c e e v e ry 3 2 s amp le s
O n c e e v e ry 6 4 s amp le s
O n c e e v e ry 1 2 8 s amp le s

de

TCCTL
0
1
2
3
4
5
6
7

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TCCTL[2:0] (W) ; Timer-C ConTroL
Designates the increment cycle for timer C.

Table 4.36

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Table 4.36 shows the count cycle in relation to the setting values ineach of “TACTL”, “TBCTL” and “TCCTL”. Table 4.37 shows theshortest interrupt time (“TIMA”=“TIMB”=“TIMC”=“FEH”) andthe longest interrupt time (“TIMA”=“TIMB”=“TIMC”=“00H”).
Count Cycle in Relation to the Settings of TACTL, TBCTL and TCCTL

TACTL, TBCTL, TCCTL
Setting values

Co

0H
1H
2H
3H
4H
5H
6H
7H

Count Cycle(Compared with
1Fs=1/44.1K)
Fs
F s/2
F s/4
F s/8
F s/16
F s/32
F s/64
F s/128

Actual Count Cycle Time[µsec]
22.6757
45.351590.7029181.4059
362.8118
725.6236
1451.2472
2902.4943

GA

Table 4.37 Shortest and Longest Interrupt TimeSETACTL, TBCTL, TCCTL
Values
0H
1H
2H
3H
4H
5H
6H
7H

Saturn SCSP User's Manual

Shortest Interrupt Time[µsec]
22.6757
45.351590.7029181.4059
362.8118
725.6236
1451.2472
2902.4943

Longest Interrupt Time[msec]
5.805011.6100
23.2200
46.4399
92.8798
185.7596
371.5193
743.0385

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Based on Tables 4.36 and 4.37, the following equation can be used to find the interrupt time.
Interrupt Time = {255 (FFH) – TIMA (B, C) settings} X count cycle time

Counting begins immediately after the settings are set to “TIMA”, “TIMB” and“TIMC”. When the count reaches FFH, an interrupt is sent from the timer valid for
an interrupt. (When the timer is not used, please prohibit the use of interrupt.)de

TIMA[7:0] (W) ; TIMer-A count data
This is timer A. This timer is an up counter. When all of
the bits reach “1B” a request for an interrupt occurs.

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TIMB[7:0] (W) ; TIMer-B count data
This is timer B. This timer is an up counter. When all of
the bits reach “1B” a request for an interrupt occurs.

SE

GA

Co

TIMC[7:0] (W) ; TIMer-C count data
This is timer C. This timer is an up counter. When all of
the bits reach “1B” a request for an interrupt occurs.

94Interrupt Control Registerntial

The SCSP has an internal interrupt controller that includes functions that control theinterrupt signals for both the main CPU and the sound CPU.

SCU

INTERRUPTCONTROLLER

SH-2
DMAC

B-BUS
(DMA)

de

INT
(Interrupt Signal)

MCINTN(Interrupt Signal)

SCSP
REGISTER
MC68EC000

DATA-BUS

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INTERRUPTCONTROLLERSCIPL0~2
Interrupt Signal

External Interrupt Input
INT0N, INT1N, INT2N(Currently not used)Co

4Mbit DRAM

Figure 4.62 Sound Interrupt Signal Connections DiagramGA

The SCSP interrupt controller is at the center of the sound block interrupt signal
system and is connected to each CPU. Interrupt signals for the sound CPU havelevels 1 through 7 auto vector interrupts. Level setting of interrupts for the main
CPU cannot be set from the sound CPU side; vector settings also cannot be done.

SE

Interrupts for the main CPU are not just interrupts, but can also be used as start
triggers for SCU DMA transfers. This function allows the timing of DMA transfersof large data such as wave form data to be controlled through the sound CPU.
When using this function, set the main CPU (SCU, etc.) to send a sound interrupt tostart the DMA transfer in advance. (See the SCU user’s manual for more detailed
information.)

Saturn SCSP User's Manual

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Registers are explained below. There are two types of registers: those that control
interrupts for the main (these have names that begins with MC~); and those that
control the interrupts for the sound (these have names that begins with SC~).

deSCIPD[10:0] ; Sound-Cpu Interrupt PenDing
This register monitors the interrupts for the sound CPU(interrupt flag). When an interrupt request occurs, theappropriate interrupt request flag is set to “1B”, so by
reading the CPU “SCIPD” register, it can be determinedwhich interrupt just occurred. Also, no matter what theenable register (“SCIEB”) is set at, all interrupt requests
are monitored. The corresponding flag can be reset by
the interrupt reset register (“SCIRE”). Only bit 5 can beread or written; all others are read only. Writing “1B” tobit 5 applies an interrupt to the sound CPU. However,writing “0B” is invalid.

Co

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SCIEB[10:0] (R/W) ; Sound-Cpu Interrupt EnaBle
This register enables interrupts to the sound CPU. Setting it to “1B” enables the corresponding hardware interrupt. Reading “SCIPD” will determine whether there areinterrupts, regardless of the “SCIEB” setting. Setting to“0B” is invalid
SCIRE[10:0] (W) ; Sound-Cpu Interrupt REset
This is the sound CPU, interrupt request reset flag.
When set to “1B”, the corresponding hardware interrupt
is reset. (If the “SCIRE” for the bit with an interrupt
occurring is set to “1B”, the “SCIPD” also will change
from “1B” to “0B”.)

SE

GA

MCIPD[10:0] (R) ; Main-Cpu Interrupt PenDing
This register monitors the interrupts for the main CPU(interrupt flag). When an interrupt request occurs, theappropriate interrupt request flag is changed to “1B,” soby having the CPU read the “MCIPD” register, it can be
determined which interrupt just occurred. Also, allinterrupt requests are monitored regardless of what theenable register (“MCIEB”) is set to. The corresponding
flag can be reset by the interrupt reset register(“MCIRE”). Only bit 5 can be read or written; all others
are read only. Writing “1B” to bit 5 applies an interrupt tothe main CPU. However, writing “0B” is invalid.

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MCIEB[10:0] (R) ; Main-Cpu Interrupt EnaBle
This register enables interrupts to the main CPU. Setting
it to “1B” enables the corresponding hardware interrupt.
Reading “MCIPD” determines whether there are interrupts, regardless of the “MCIEB” setting. Setting to “0B”
is invalid.
MCIRE[10:0] (R) ; Main-Cpu Interrupt REset

b15 b14 b13 b12 b11 b10 b9

SCIEB

MCIRE

b7

b6

b5

b4

b3

b2

b1

b0

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R

R

R

R

R

RW

R

R

R

R

R

W

W

W

W

W

W

W

W

W

W

W

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SCIRE

MCIPD

b8

RW RW RW RW RW RW RW RW RW RW RW

SCIPD

MCIEB

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This is the main CPU interrupt request reset flag. Whenset to “1”, the corresponding hardware interrupt request
is reset. (If the “MCIRE” for the bit with an interrupt
occurring is set to “1B”, the “MCIPD” also will change
from “1B” to “0B”.)

W

W

W

W

W

W

W

W

W

W

W

R

R

R

R

R

RW

R

R

R

R

R

W

W

W

W

W

W

W

W

W

W

W

GA

1 Sample (1Fs) Interrupt
MIDI Output Interrupt
Timer C Interrupt
Timer B Interrupt
Timer A Interrupt
CPU Interrupt

DMA Transfer End Interrupt

SE

MIDI Input Interrupt

External Interrupt "INT2N"
External Interrupt "INT1N"
External Interrupt "INT0N"
R: Read Only

W: Write Only

RW: Read and Write

Figure 4.63 Interrupt Register Bit Accommodation

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Table 4.38 Bit Factor Interrupt Registers
Reason for Interrupt
Applicable to the external interrupt input “INT0N” interrupt input.
Applicable to the external interrupt input “INT1N” interrupt input.
Applicable to the external interrupt input “INT2N” interrupt input.
Applicable to the MIDI input interrupt
Interrupt occurs when the MIDI-IN side FIFO buffer memory captures data from an empty state.

4

Applicable to DMA transfer end interrupt

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Bit
0
1
2
3

Automatic cancellation occurs when data is all read from the FIFO buffer and the buffer is empty.
Interrupt occurs when the DMA transfer using the SCSP internal DMA is finished. (When datatransfer of the block set in “DLG” [length (volume)] is completely finished.)

5

Applicable to the CPU manual interrupt

By writing to the CPU (main or sound), an interrupt can be applied to the sound or main CPU.
Interrupt is applied when “1B” is written. ( “0B” is invalid.)

Applicable to a timer A interrupt
Applicable to a timer B interrupt
Applicable to a timer C interrupt
Applicable to the MIDI output interrupt

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6
7
8
9

An interrupt request occurs when the MIDI-OUT side FIFO buffer memory becomes empty. Theinterrupt is automatically cancelled when data is written into the MIDI-OUT buffer memory(register) and it is no longer empty.

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10Applicable to one interrupt each sample (1 sample= 22.68µsec= 1/44.1K intervals).
11~15 Invalid

About SCILV0, 1, 2This is the register that sets the auto vector interrupt level for the sound CPU.
Each register is partitioned in units of one bit per every interrupt factor. Whensetting, view Figure 4.65 vertically.

4

SCILV22

1SCILV1SCILV0LSB (lower)

GA

MSB (upper)Co

In the example of bit 7, timers B, C and MIDI output interrupts, and theinterrupt level for each sample are all set at once. Level is set with a 3 bit code,
but each bit is distributed among SCILV0, 1 and 2.

Figure 4.64 3 Bit Code and Register AccommodationSE

The 3 bit code used to set the level is like Figure 4.64. For example, if it is set at
101B, the interrupt level is 5. “000B” is level 0 interrupt, so an interrupt would
not be applied.
However, the actual format of the register is shown in Figure 4.65. Be carefulwhen setting the values.

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b6

b5

b4

b3

b2

b1

b0

SCILV0

W

W

W

W

W

W

W

W

SCILV1

W

W

W

W

W

W

W

W

SCILV2

W

W

W

W

W

W

W

W

CPU Software Interrupt
DMA Transfer End
MIDI-IN
External Interrupt 2External Interrupt 1

Co

External Interrupt 0

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Timer A

b8

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b7

Timer B, C & MIDI-OUT & 1Fs

b9deb15 b14 b13 b12 b11 b10

Figure 4.65 Format of the Interrupt Level Set RegisterGA

SCILV0[7:0] (W) ;Sound-Cpu Interrupt LeVel bit0
Specifies bit0 of the sound CPU interrupt level code as
defined in bit application.

SCILV1[7:0] (W) ;Sound-Cpu Interrupt LeVel bit1
Specifies bit1 of the sound CPU interrupt level code as
defined in bit application.

SE

SCILV2[7:0] (W) ;Sound-Cpu Interrupt LeVel bit2
Specifies bit2 of the sound CPU interrupt level code as
defined in bit application.

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Examples of interrupt settings are explained below.
Apply a level 6 interrupt to the sound CPU while timer A applies aninterrupt to the main CPU.

Procedure:

Currently, items without an interrupt applied set the timer after all of
the interrupt settings are finished, .

nti
alConditions:Set the sound CPU interrupt level to 6
- Level 6 in the 3 bit code is “110B”.
- The bit that controls timer A is bit 6, so set bit 6 in “SCILV0” to “0B”.
(At 100425H address in byte, “00H”, or at 100424H address in words “0000H”.)- Bit 6 in “SCILV0” to “1B”.
(At 100427H address in byte, “40H”, or at 100426H address in words “0040H”.)- Bit 6 in “SCILV0” to “1B”.
(At 100429H address in byte, “40H”, or at 100428H address in words “0040H”.)

2:

Set parameters in registers “MCIEB” and “SCIEB” so that interrupts will beapplied to both the main and sound CPUs.
- Set bit 6 in register “MCIEB” to “1B” so that an interrupt will be applied bytimer A.
(At 10042BH address in byte, “40H”, or at 10042AH address in words “0040H”.)- Set bit 6 in register “SCIEB” to “1B” so that an interrupt will be applied tothe sound CPU as well.
(At 100421H address in bytes, “40H”, or at 10042EH address in words “0040H”.)- Furthermore, by setting the parameters in the timer, count will begin
immediately afterwards. When an overflow occurs, an interrupt will beapplied.

3:

Use the reset registers to remove the interrupts from either the sound or main
CPUs.

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1:

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DMA Transfer Registerntial

The DMA inside the SCSP can only transfer between the SCSP internal control
register and the sound memory. From this the maximum bytes transferable is 3812
bytes (EE4H), (allocated in the empty memory from 100000H~100EE3H). Also, theregisters relating to the DMA cannot be changed with the DMA transfer.
During DMA transfer address continually move in the increase direction.

de• The speed of the main CPU and sound CPU may drop during DMA transfer.
• Access through DMA transfer to the control register of the DMA controller isabsolutely prohibited. The operation when this transfer is performed is notguaranteed at all.
• DMA transfer is word (16bit) transfer.

DMAC

Co

S C S PCONTROLREGISTER

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DGATE (R/W) ;Dma GATE (and “0”)The DMA controller block diagram is shown in Figure
4.66.
It can freely initialize the areas in the sound memory andthe SCSP internal control register to “0”. When this bit is“1B”, “0” clear is executed (When actually starting,“DEXE” must be executed).
Deleting DGATE transfer (“0” write) will not affect thetransfer source data. In addition, data will not be lost.

100000H

Internal data
Bus

000000H~

0FFFFFH

GA~
100EE3H

SOUND MEMORY

SE

Figure 4.66 DMA Controller Block Diagram

Saturn SCSP User's Manual101Table 4.39 DMA Transfer Direction
DDIR
0
1

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DDIR (R/W) ; Dma (transferring) DIRection
Designates the DMA transfer direction. When this bit is“0B”, data is transferred from the sound memory to the
LSI block register; “1” transfers data in the opposite
direction.
Transfer Direction
From sound memory to LSI internal register
From LSI internal register to sound memory

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Table 4.40 DMA Transfer

de

DEXE (R/W) ; Dma EXEcution
Designates the start of the DMA transfer. When this bit is“1”, the DMA transfer starts. Writing “0” is invalid.
Also, when DMA transfer ends, this bit is automatically
reset to “0”.
Transfer Status

DEXE
0
1

Co

Invalid or transfer has ended
Starts DMA transfer

DMEA[19:1] (W) ; Dma MEmory start Address
Designates the sound memory address (word units) thatstarts the DMA transfer.

GA

DRGA[11:1] (W) ; Dma ReGister start Address
Designates the block register byte address in the LSI(word units) that starts the DMA transfer.

SE

DTLG[11:1] (W) ; Dma (Transferring) LenGth
Designates the word count being transferred during
DMA transfer. At that time, be careful that the area of thetransfer origin or destination does not exceed the area ofthe sound memory area or the LSI internal block register
area.

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DSP Memory Control Register

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4.3

RBL[1:0] (W) ; Ring Buffer Length
Designates the length of the ring buffer.
Table 4.41 RBL and the Ring Buffer Length

Buffer Length
8K word
16K word
32K word
64K word

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bit
0
1
2
3

RBP[19:13] (W) ; Ring Buffer (header) PointerDesignates the first address of the ring buffer. Thisaddress designation is per 4K-word boundary.

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The important base of DSP effect processing is delay
processing. Delay is accomplished by storing the input
data in memory and reading it out again after a certain
time lag is applied. This storage area is called the ringbuffer.

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By combining the number of effect programs used andthe effect delay timer used simultaneously, the ringbuffer area settings can be set to perform the “RBL” and“RBP” registers.

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Chapter 5
SCSP Internal DSP Operation

Saturn SCSP User's Manual

Chapter 5 Contents
Chapter 5 Contents
5.1 DSP Configuration
106
5.1 5.2
DSPDSP
Configuration..................................... 107
106
Internal RAM
5.2 DSP Internal RAM ...................................... 107

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DSP Configuration

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5.1

Figure 5.1 DSP Configuration Diagram

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DSP Internal RAM

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5.2

EXTS[15:0] ; EXTernal Stack
Represents the digital audio input data buffer. (Thisregister cannot be accessed.)

MIXS[19:0] (R/W) ; MIX Stack
Represents the sound data buffer from the input mixer.

deMEMS[23:0] (R/W) ; MEMory Stack
Represents the input data buffer from the sound memory.
TEMP[23:0] (R/W) ; TEMPorary register
Represents the DSP work buffer (128 words). The DSP
work buffer is in ring buffer configuration, the pointerdecreases at every sample.

nfi

COEF[12:0] (R/W) ; COEFficient register
Represents the DSP coefficient buffer.

Co

MADRS[16:1] (R/W) ; Memory ADdReSs register
Represents the DSP address buffer.
MPRO[63:0] (R/W) ; Micro PROgram register
Represents the DSP micro program buffer.

SE

GA

EFREG[15:0] (R/W) ; EFfect REGister
Represents the DSP output buffer.

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