When using this document, keep the following in mind:ntialGeneral Notice

1. This document is confidential. By accepting this document you acknowledge that you are boundby the terms set forth in the non-disclosure and confidentiality agreement signed separately and /inthe possession of SEGA. If you have not signed such a non-disclosure agreement, please contact
SEGA immediately and return this document to SEGA.

de2. This document may include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new versions of the
document. SEGA may make improvements and/or changes in the product(s) and/or the
program(s) described in this document at any time.

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3. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without SEGA’S written permission. Request for copies of this document and for technicalinformation about SEGA products must be made to your authorized SEGA Technical Services
representative.

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4. No license is granted by implication or otherwise under any patents, copyrights, trademarks, orother intellectual property rights of SEGA Enterprises, Ltd., SEGA of America, Inc., or any third
party.
5. Software, circuitry, and other examples described herein are meant merely to indicate the characteristics and performance of SEGA’s products. SEGA assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples
describe herein.

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6. It is possible that this document may contain reference to, or information about, SEGA products(development hardware/software) or services that are not provided in countries other than Japan.
Such references/information must not be construed to mean that SEGA intends to provide such
SEGA products or services in countries other than Japan. Any reference of a SEGA licensed product/program in this document is not intended to state or simply that you can use only SEGA’slicensed products/programs. Any functionally equivalent hardware/software can be used instead.
7. SEGA will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s equipment, or programs according to this document.

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NOTE: A reader's comment/correction form is provided with thisdocument. Please address comments to :(6/27/95- 002)

SEGA of America, Inc., Developer Technical Support (att. Evelyn Merritt)
150 Shoreline Drive, Redwood City, CA 94065
SEGA may use or distribute whatever information you supply in any way
it believes appropriate without incurring any obligation to you.

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VDP2
User's Manual
Version 1.1
Doc. #ST-58-R2-060194© 1994 SEGA. All Rights Reserved.

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READER CORRECTION/COMMENT SHEETKeep us updated!
If you should come across any incorrect or outdated information while reading through the attacheddocument, or come up with any questions or comments, please let us know so that we can make therequired changes in subsequent revisions. Simply fill out all information below and return this form to
the Developer Technical Support Manager at the address below. Please make more copies of this form if
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VDP2 User's ManualdeYour Name

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Questions/comments:

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REFERENCES

KenKyusha New Japanese-English Dictionary
1974 Edition

2.

Nelson’s Japanese-English Character Dictionary
2nd revised version

3.

Microsoft Computer Dictionary

4.

Japanese-English Computer Terms Dictionary
Nichigai Associates
4th version

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1.

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In translating/creating this document, certain technical words and/or phrases were interpretedwith the assistance of the technical literature listed below.

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PrefaceThis manual describes the VDP2 (Video Display Processor 2) and how to use it. The VDP2
controls the scroll screen control and the display priority control.

Manual Notations
Notations within this manual are described below.

deBinary, hexadecimal
Binary notation has a B attached at the end (as in 100B); however, B may be omitted whenbinary notation is obvious. Hexadecimal notation has an H attached at the end (as in 00H
and FFH).

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Units
1 Kbyte is 1024 bytes. 1 Mbit is 1024 Kbits, or 1,048,576 bits.

MSB, LSB
The structure of byte and word shows the MSB (most significant bit) on the left and LSB (leastsignificant bit) on the right.

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An undefined bit
A bit not defined by the register is shown as a dash. A “0” should be written into an undefined
bit of the register. Bits not defined by data of tables defined by VRAM are shown as shaded.
As a rule, a 0 should be written, providing that the undefined bit is ignored.
Byte, word, bit
Bits, as in digits of 0 and 1, are the lowest unit of data. A byte consists of 8 bits. A word consistsof 2 bytes, and begins from an even address.

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Boundary
A boundary defines data from an address divisible by a selected value. For example, data for a
20H-byte boundary is defined at addresses beginning from 20H, 40H, and so on. A word is a
2-byte boundary.

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Address
All addresses defined by VDP2 are relative addresses within VDP2. The first address of VDP2
begins from 5E00000H. For example, VRAM is at 000000H address of the relative address, andbegins from 5E00000H address of the absolute address. The TV screen mode register is at
180000H address of the relative address, and is set at address 5F80000H of the absolute address.

iThe main items described in each chapter are as follows.
Table 1.

Chapters and Main Items

Contents
VDP2 Functions
TV Screen Mode, Normal, Hi-Res, Exclusive
Monitor, Interlace Mode, External Signal,- H
Counter, V-Counter, Exclusive Hi-Res Setting
VRAM Size, Address Map, VRAM, Color RAM,
Register, VRAM Change, VRAM Bank
Partition, VRAM Access Method, Color RAM
Mode
Cell, Character Color Count, Transparent Dot,
Character Pattern, Pattern Name Table,
Special Function Bit, Reverse Function Bit,
Page, Plane, Map, Bitmap, Screen-Over
Process, Mosaic Process
Screen Scroll, Scaling, Line Scroll, Vertical Cell
Scroll Coordinates
Rotation Scroll Increment, Rotation Scroll
Screen Display, Rotation Parameter
Coefficient Table
Line Color Screen, Back Screen
Normal Rectangular Window, Normal Line
Window, Sprite Window
Sprite Type, Sprite Color Mode, Priority, Color
Calculation
Palette Format, RGB Format, Sprite Dot, Scroll
Dot, Special Function CodePriority Number, Line Color Screen Insertion
Color Calculation, Extended Color Calculation,
Special Color Calculation, Gradation
Calculation
Color Offset
Normal Shadow, MSB Shadow
Operation Flow Chart, How to use RAM, Bit
StructuredeChapter Name
Chapter 1 VDP2 Functions
Chapter 2 TV Screen

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Chapter 3 RAM

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Chapter 4 Scroll Screen

Chapter 5 Normal Scroll Screen

Chapter 6 Rotation Scroll Screen
Chapter 7 Line Screen
Chapter 8 WindowntialManual StructureGA

Chapter 9 Sprite Data

Chapter 10 Dot Color Data

Chapter 11 Priority Function
Chapter 12 Color Calculation

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Chapter 13 Color Offset Function
Chapter 14 Shadow Function
Chapter 15 How To Use VDP2

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Functions, their chapters and sections

Function
Overview

Details
Chapter~1
VDP2 Functions
TV Screen Configuration, Designate Display
2.1
TV Screen Configuration
Area, Boarder Area
TV Screen Mode, Normal, Hi-Res, Exclusive
2.2
TV Screen Mode
MonitorInterlace, Non-interlace, Single-Density Interlace, 2.3
Interlace Mode
Double-Density Interlace
Address Map
3.1
Address Map
Size
3.1
Address Map
VRAM
Change3.2
VRAM ChangeBank Partition
3.3
VRAM Bank Partition
Access During Display
3.4
How to Access VRAM
During Display
Color RAM Mode
3.5
Color RAM Mode
Screen Display
4.1
Screen Display Control
Character
4.3
Cell
Color Count
Bitmap Color
Count
Palette Format 10.1 Palette Format Dot Color
Color
Dot Color Data
Data
RGB Format
10.2 RGB Format Dot Color Data
Normal Scroll
Dot Color Data
ScreenRotation Scroll
Color RAM
3.5
Color RAM Mode
Screen
Mode
Cell
4.3
Cell
Character
4.4
Character Pattern
Pattern
Cell Format
Pattern Name 4.6
Pattern Name Table (Page)
Table (Page)
Plane
4.7
Plane
Map
4.8
Map
Bitmap Format
4.9
Bitmap
Display Area, Screen-Over
4.10 Display Area
Mosaic Process
4.11 Mosaic Process
Screen Scroll Function
5.1
Screen Scroll Function
Scale Function
5.2
Scale Function
Line Scroll Function, Vertical
5.3
Line & Vertical Cell Scroll
Cell Scroll Function
Function

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Scroll Screen

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TV Screennti
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Functions, their chapters and sections (continued)

Function

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Chapter
6.1
Rotation Scroll Coordinates
Calculation
Rotation
Display Control
6.2
Rotation Scroll Screen
Display Control
Scroll Screen Rotation Parameter Control
6.3
Rotation Parameter Control
8
Window
Scroll Screen
Coefficient Control
6.4
Coefficient Table Control
Line Color Screen
7.1
Line Color ScreenLine Screen
6.4
Coefficient Table Control
11.3
Line Color Screen Insertion
Back Screen
7.2
Back Screen
Window
Normal Rectangular Window, Normal Line
8
Window
Window, Sprite Window, Window Effective Area 9.1
Sprite Data
Sprite Data, Type, Color Mode
9.1
Sprite Data
Priority and Color Calculation
9.2
Priority and Color
Calculation
SpriteSprite Window
8
Window
9.1
Sprite Data
Dot Color
Palette Format
10.1 Palette Format Dot Color
Data
Data
RGB Format
10.2 RGB Format Dot Color Data
Color RAM Mode
3.5
Color RAM Mode
Priority Function
11.1 Priority Function
9.2
Priority and Color
Calculation
Priority
Special Priority Function
11.2
Special Priority Function
10.3
Special Function CodeLine Color Screen Insertion
11.3 Line Color Screen Insertion
7.1
Line Color Screen
Color Calculation Function,
12.1
Color Calculation Function
Extended Color Calculation
7.1
Line Color Screen
Function
Color
Special Color Calculation
12.3
Special Color Calculation
Image Process
Function
Function
10.3
Special Function CodeGradation Calculation Function 12.2 Gradation Calculation
Function
Color Calculation Window
8
Window
Color Offset Function
13
Color Offset Function
Shadow
Normal Shadow, MSB Shadow 14
Shadow Function
9.1
Sprite Data

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Coordinates Calculationv

Table of ContentsntialPreface ............................................................................................................................ i
Manual Notation .................................................................................................. i
Manual Structure ............................................................................................... iii

List of Figures................................................................................................................ xi
List of Tables ............................................................................................................... xiv

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Chapter 1 VDP2 Functions ........................................................................................... 1
Introduction......................................................................................................... 2
1.1 System Configuration ................................................................................... 2
1.2 Address Map ................................................................................................ 3
VRAM ..................................................................................................... 3
Color RAM .............................................................................................. 3
Register .................................................................................................. 4
1.3 Scroll Function.............................................................................................. 5
Display Screen ....................................................................................... 5
Scroll Screen .......................................................................................... 6
Line Screen ............................................................................................ 7
Windows ................................................................................................. 7
1.4 Priority Function ........................................................................................... 8
Priority Function...................................................................................... 8
Color Calculation Function ..................................................................... 8
Color Offset Function .............................................................................. 8
Shadow Function .................................................................................... 9GA

Chapter 2 TV Screen .................................................................................................. 11
2.1 TV Screen Mode ........................................................................................12
Special High Resolution Graphic Mode ................................................ 13
2.2 Interlace Mode............................................................................................ 14
2.3 TV Screen Structure ................................................................................... 15
2.4 TV Screen Mode Register .......................................................................... 16
2.5 External Signals and Scan Conditions ....................................................... 19
External Signal Enable Register ........................................................... 19
Screen Status Register ........................................................................ 21
H Counter Register ............................................................................... 23
V Counter Register ............................................................................... 24

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Chapter 3 RAM ...........................................................................................................25
Introduction.......................................................................................................26
3.1 Address Map ..............................................................................................26
VRAM Size Register .............................................................................28
3.2 VRAM Bank Partitioning .............................................................................29
RAM Control Register .......................................................................... 29
3.3 Accessing VRAM During Display Interval .................................................. 31
VRAM Access During Display Interval ................................................. 31
Image Data Access ..............................................................................32
Vertical Cell Scroll Table Data Access .................................................. 35
Read/Write Access by the CPU ............................................................ 35
VRAM Cycle Pattern Selection Process ............................................... 37

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VRAM Cycle Pattern Register .............................................................. 39
3.4 Color RAM Mode ........................................................................................ 43
RAM Control Register .......................................................................... 45

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Chapter 4 Scroll Screen .............................................................................................. 47
4.1 Screen Display Control .............................................................................. 48
Screen Display Enable Register ........................................................... 48
4.2 Scroll Screen Structure .............................................................................. 50
Cell Format ....................................................................................................... 50
Bit Map Format ................................................................................................. 52
4.3 Cell ............................................................................................................. 53
Character Color Number ...................................................................... 53
Cell Data Configuration ........................................................................ 53
Transparent Dots .................................................................................. 57
RGB Format Dot Data .......................................................................... 58
4.4 Character Patterns ..................................................................................... 59
Character Size and Cell Arrangement .................................................. 59
4.5 Character Control Register ........................................................................ 60
4.6 Pattern Name Table (Page) ........................................................................ 64
Pattern Name Table Data Configuration ............................................... 64
Pattern Name Data ............................................................................... 69
Character Number ................................................................................ 74
Palette Number..................................................................................... 74
Special Function Bit .............................................................................. 74
Reverse (Flip) Function Bit ................................................................... 75
Pattern Name Control Register ............................................................ 76
4.7 Planes ........................................................................................................ 79
Plane Size ............................................................................................ 79
Plane Size Register .............................................................................. 80
4.8 Maps ........................................................................................................... 82
Map Selection Register ........................................................................ 82
Map Size ............................................................................................... 84
Map Offset Register .............................................................................. 85
Normal Scroll Screen Map Register ..................................................... 87
Rotation Scroll Surface Map Register .................................................. 89
4.9 Bit Maps ..................................................................................................... 93
Bit Map Size ......................................................................................... 93
Bit Map Color Number .......................................................................... 93
Bit Map Pattern ..................................................................................... 95
Bit Map Palatte Number ..................................................................... 111
Special Function Bit ............................................................................ 111
Bit Map Palatte Number Register ....................................................... 112
4.10 Display Area ........................................................................................... 114
Display Area ....................................................................................... 114
Screen-Over Process ......................................................................... 115
Display-Over Pattern Name ............................................................... 115
Screen-Over Pattern Name Register ................................................. 116
4.11 Mosaic Process ...................................................................................... 117
Mosaic Control Register ..................................................................... 118

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Chapter 5 Normal Scroll Screen ............................................................................... 121
Introduction..................................................................................................... 122
5.1 Screen Scroll Function ............................................................................. 122
Screen Scroll Value Register .............................................................. 123
5.2 Expansion/Contraction Function .............................................................. 126
Coordinate Increment Register .......................................................... 127
Reduction Enable Register ................................................................. 129
5.3 Line and Vertical Cell Scroll Function ....................................................... 131
Line Scroll Function ............................................................................131
Vertical Cell Scroll Function ................................................................ 134
Line and Vertical Cell Scroll Control Register..................................... 137
Line Scroll Table Address Register ..................................................... 140
Vertical Cell Scroll Table Address Register ........................................ 141

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Chapter 6 Rotation Scroll Screen ............................................................................. 143
Introduction..................................................................................................... 144
6.1 Rotation Scroll Coordinate Operation ...................................................... 144
6.2 Rotation Scroll Screen Display Control .................................................... 148
RAM Control Register ........................................................................ 148
6.3 Rotation Parameter Control ..................................................................... 151
Data Configuration of the Rotation Parameter Table .......................... 153
Rotation Parameter Table ................................................................... 155
Rotation Parameter Read Control Register ........................................ 157
Rotation Parameter Table Address Register ...................................... 158
Rotation Read Out of the Frame Buffer .............................................. 159
Rotation Parameter Change ............................................................... 160
Rotation Parameter Mode Register .................................................... 162
6.4 Coefficient Table Control .......................................................................... 163
Line Color Screen Data ...................................................................... 164
Bit Configuration of Coefficient Table Data ......................................... 165
Coefficient Table Lead Address .......................................................... 165
Most Significant Bit of Coefficient Data .............................................. 166
RAM Control Register ........................................................................ 167
Coefficient Table Control Register ...................................................... 168
Coefficient Table Address Offset Register .......................................... 170

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Chapter 7 Line Screen ..............................................................................................171
Introduction..................................................................................................... 172
7.1 Line Color Screen .................................................................................... 172
Line Color Screen Table Address Register ......................................... 174
7.2 Back Screen ............................................................................................. 175
Back Screen Table Address Register ................................................. 176
Chapter 8 Windows ................................................................................................... 179
8.1 Window Area ............................................................................................ 180
Normal Rectangular Window .............................................................. 180
Window Position Register .................................................................. 181
Normal Line Window .......................................................................... 184
Line Window Table Address Register ................................................. 186
Sprite Window .................................................................................... 187

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Sprite Control Register ....................................................................... 188
Window’s Active Area for the Screen.................................................. 189
8.2 Window Process .......................................................................................190
Window Control Register .................................................................... 193

deChapter 9 Sprite Data ...............................................................................................199
9.1 Sprite Data ...............................................................................................200
Sprite Types ........................................................................................ 200
Sprite Color Mode............................................................................... 203
9.2 Priority and Color Calculation ................................................................... 204
Priority Number Selection ................................................................... 204
Color Calculation Enable Conditions .................................................. 205
Color Calculation Ratio Selection ....................................................... 206
Sprite Control Register ....................................................................... 207
Priority Number Register .................................................................... 209
Color Calculation Ratio Registers ...................................................... 210

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Chapter 10 Pixels ......................................................................................................213
Introduction..................................................................................................... 214
10.1 Palette Format Pixels .............................................................................214
Sprite Dot Pixels ................................................................................. 214
Scroll Dot Pixels ................................................................................. 216
Color RAM Address Offset Register ................................................... 217
10.2 RGB Format Pixels ................................................................................ 218
Sprite Pixels........................................................................................ 218
Scroll Pixels ........................................................................................ 218
10.3 Special Function Code ........................................................................... 220
Special Function Code Select Register .............................................. 221
Special Function Code Register ......................................................... 222

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Chapter 11 Priority Function......................................................................................223
Introduction..................................................................................................... 224
11.1 Priority Function ......................................................................................224
Priority Number................................................................................... 224
Priority Number Register .................................................................... 225
11.2 Special Priority Function ......................................................................... 227
Special Priority Mode Register ........................................................... 229
11.3 Insertion of Line Color Screen ............................................................... 230
Line Color Screen Enable Register .................................................... 231

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Chapter 12 Color Calculations ................................................................................... 233
Introduction..................................................................................................... 234
12.1 Color Calculation Function ..................................................................... 234
Normal Color Calculation ................................................................... 234
Extended Color Calculation Function ................................................. 236
12.2 Gradation Calculation Function .............................................................. 238
Color Calculaton Control Register ...................................................... 240
Color Calculation Ratio Register ........................................................ 243
12.3 Special Color Calculation Function ........................................................ 245
Special Color Calculation Mode Register ........................................... 247

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Chapter 13 Color Offset Function ............................................................................. 249
Introduction..................................................................................................... 250
13.1 Color Offset Selection ............................................................................250
Color Offset Enable Register .............................................................. 251
Color Offset Select Register ............................................................... 252
Color Offset Register .......................................................................... 253

deChapter 14 Shadow Function ................................................................................... 255
Introduction..................................................................................................... 256
14.1 Shadow Process .................................................................................... 256
Normal Shadow .................................................................................. 256
MSB Shadow ......................................................................................258
Shadow Control Register ................................................................... 259

Chapter 15 How to Use VDP2 .................................................................................. 261
15.1 Operation Flow ....................................................................................... 262
15.2 How to Use RAM .................................................................................... 264
15.3 Bit Configuration Map ............................................................................. 267

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Chapter 16 Quick Reference .................................................................................... 295
16.1 Register Map .......................................................................................... 296
16.2 Register Bit List ......................................................................................315
16.3 Register Bit Functions ............................................................................328
16.4 Table List ................................................................................................389x

Table of Figuresnti
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Figure 1.1 System Configuration ........................................................................ 2
Figure 1.2 Address Map ..................................................................................... 3

Chapter 2 TV Screen
Figure 2.1 Display Method by Interlace Setting ............................................... 14
Figure 2.2 TV Screen Structure........................................................................ 15

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Chapter 3 RAM
Figure 3.1 Different Capacities of VRAM Address Map ................................... 27
Figure 3.2 VRAM Cycle Pattern Register ......................................................... 32
Figure 3.3 Access Selection Limits of Pattern Name Table Data ..................... 33
Figure 3.4 Example of Character Pattern Data Read AccessSelection ......................................................................................... 34
Figure 3.5 Access Select Limits of Vertical Cell Scroll Table Data ................... 35
Figure 3.6 CPU Read/Write Access Selection when
VRAM is not Divided into Two Bank ............................................... 36
Figure 3.7 CPU Read/Write Access Selection when
VRAM is Divided into Two Banks ................................................... 37
Figure 3.8 VRAM Cycle Pattern Selection ....................................................... 39
Figure 3.9 Color Data Configuration on Color RAM ......................................... 44
Figure 3.10 Color Data of the Color RAM ........................................................ 45

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Chapter 4 Scroll Screen
Figure 4.1 Scroll Screen Configuration of Cell Format ..................................... 50
Figure 4.2 Scroll Screen Configuration of Cell Format andCorresponding Data Settings ......................................................... 51
Figure 4.3 Scroll Screen Configuration of Bit Map Format............................... 52
Figure 4.4 Relationship of bit map format scroll screen and data settings....... 52
Figure 4.5 Configuration of Cells by Character Color Count ............................ 54
Figure 4.6 RGB Format Dot Data ..................................................................... 58
Figure 4.7 Cell Arrangement by Character Size ............................................... 59
Figure 4.8 Data Configuration of Pattern Name Tables ................................... 65
Figure 4.9 Bit Configuration when Pattern Name Data is 2 Word .................... 69
Figure 4.10 Configuration when Pattern Name Data is 1 Word ....................... 71
Figure 4.11 Dot Color Data by Character Number of Colors ............................ 74
Figure 4.12 Reverse Display of Character Patterns......................................... 75
Figure 4.13 Arrangement of Pattern Name Table by Plane Size ...................... 79
Figure 4.14 Map Selection Register ................................................................. 82
Figure 4.15 Map Size ....................................................................................... 84
Figure 4.16 Plane Arrangement of Map by Reduction Settings ....................... 85
Figure 4.17 Bit Map Pattern Configuration ....................................................... 96
Figure 4.18 Dot Color Data by Bit Map Number of Colors ............................. 111
Figure 4.19 Mosaic Pattern ............................................................................ 117

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Chapter 5 Normal Scroll Screen
Figure 5.1 Screen Scroll Value Bit Configuration ........................................... 122
Figure 5.2 Configuration of Coordinate Increment Register........................... 126
Figure 5.3 Line Scroll Function ...................................................................... 131
Figure 5.4 Bit Configuration of Line Scroll Table Data ................................... 132
Figure 5.5 Line Scroll Table ............................................................................133
Figure 5.6 Vertical Cell Scroll Function .......................................................... 134
Figure 5.7 Data Configuration on Vertical Cell Scroll Table ........................... 135
Figure 5.8 Vertical Cell Scroll Table................................................................ 136

deChapter 6 Rotation Scroll Screen
Figure 6.1 Rotation Scroll Screen Display Method ........................................ 145
Figure 6.2 Rotation Parameter data Configuration ........................................ 153
Figure 6.3 Rotation Parameter Table ............................................................. 156
Figure 6.4 How to Store to the Rotation Parameter Table VRAM .................. 157
Figure 6.5 Rotation Parameter Change ......................................................... 161
Figure 6.6 Line Color Screen Data Using Coefficient Data ............................ 164
Figure 6.7 Bit Configuration of Coefficient Table Data ................................... 165

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Chapter 7 Line Screen
Figure 7.1 Line Screen ................................................................................... 172
Figure 7.2 Configuration of Line Color Screen Table ..................................... 173
Figure 7.3 Bit Configuration of Line Color Screen Table Data ....................... 173
Figure 7.4 Configuration of Back Screen Table .............................................. 175
Figure 7.5 Bit Configuration of Back Screen Table Data ................................ 176

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Chapter 8 Windows
Figure 8.1 Normal Rectangle Window ........................................................... 180
Figure 8.2 Normal Line Window ..................................................................... 184
Figure 8.3 Bit Configuration of Normal Line Window Table Data ................... 184
Figure 8.4 Configuration of Normal Line Window Table ................................. 185
Figure 8.5 Sprite Window ............................................................................... 187
Figure 8.6 Active Area of Windows ................................................................ 189
Figure 8.7 Window Process ........................................................................... 191
Chapter 9 Sprite Data
Figure 9.1 Sprite Types .................................................................................. 201

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Chapter 10 Dot Color Data
Figure 10.1 Palette Format Sprite Dot Color Data ......................................... 215
Figure 10.2 Sprite Color RAM Address .......................................................... 215
Figure 10.3 Palette Format Scroll Dot Color Data .......................................... 216
Figure 10.4 Scroll Color RAM Address .......................................................... 216
Figure 10.5 RGB Format Sprite Dot Color Data ............................................. 218
Figure 10.6 RGB Format Scroll Dot Color Data ............................................. 219
Figure 10.7 Dot Color Code Corresponding to Special Function Code ......... 220

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Chapter 11 Priority Function
Figure 11.1 Priority Function .......................................................................... 224
Figure 11.2 Line Color Screen Insertion ......................................................... 230
Chapter 12 Color Operations
Figure 12.1 Color Calculation Function ......................................................... 234
Figure 12.2 Color Calculation Ratio Mode ..................................................... 236
Figure 12.3 Expand Color Operation Function ............................................... 237
Figure 12.4 Gradation Calculation Function ................................................... 239

Chapter 13 Color Offset Function
Figure 13.1 Color Offset Data ........................................................................ 250

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Chapter 14 Window Function
Figure 14.1 Shadow Function ........................................................................ 256
Figure 14.2 Sprite Data Write of a Normal Shadow ....................................... 257
Figure 14.3 Sprite Data of a Normal Shadow ................................................ 257
Figure 14.4 Sprite Shadow and Transparent Shadow ................................... 258
Figure 14.5 Sprite Data of MSB Shadow ....................................................... 259

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List of TablesntialChapter 1 VDP2 Functions
Table 1.1 TV Screen Mode ................................................................................. 5
Table 1.2 Scroll Screen ..................................................................................... 5
Table 1.3 Windows ............................................................................................. 6
Table 1.4 Scroll Screen Function ....................................................................... 6

deChapter 2 TV Screen
Table 2.1 TV Screen Mode ............................................................................... 12
Table 2.2 Register for Setting the External Screen .......................................... 21
Table 2.3 H Counter Register Bit Content ........................................................ 24
Table 2.4 V Counter Register Bit Content ........................................................ 24

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Chapter 3 RAM
Table 3.1 Data Defined in VRAM ..................................................................... 26
Table 3.2 Access Numbers of Required Pattern Name Table Data
during 1 Cycle .................................................................................. 33
Table 3.3 Character Pattern Data (Bit Map Pattern Data)
Read Access Number ...................................................................... 34
Table 3.4 Character Pattern Data Read Access Selection Limits .................... 34
Table 3.5 Access Command .............................................................................40

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Chapter 4 Scroll Screen
Table 4.1 Character Color Count and Dot Data Size ....................................... 53
Table 4.2 Cell Data Configuration ....................................................................53
Table 4.3 Transparent Dot Data Values ........................................................... 58
Table 4.4 Pattern Name Table Capacity Page Boundary of One Page ............ 64
Table 4.5 Character Number Auxiliary Mode .................................................... 69
Table 4.6 Bit Configuration when Pattern Name Table is 1 Word .................... 70
Table 4.7 Reverse Function Bit ........................................................................ 75
Table 4.8 Address Value of Map Designation Register by Setting ................... 83
Table 4.9 Bit Map Size .....................................................................................93
Table 4.10 Bit Map Color Count ....................................................................... 94
Table 4.11 Bit Map Pattern Capacity per Surface ........................................... 95
Table 4.12 Normal Scroll Screen Display Area .............................................. 114
Table 4.13 Rotation Scroll Screen Display Area ............................................. 114
Chapter 5 Normal Scroll Screen
Table 5.1 Horizontal Coordinate Increment and Reduction Setting ............... 128
Table 5.2 Display Screen Limits by Setting of Reduction Enable Bit ............. 130

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Chapter 6 Rotation Scroll Screen
Table 6.1 Rotation Scroll Screen ................................................................... 144
Table 6.2 Rotation Parameters ....................................................................... 151
Table 6.3 Lease significant bit of Coefficient Parameter
Data Showing the Address Value Separate from
Coefficient Parameter Data Size ..................................................... 166
Table 6.4 Image Processing using RGB0 Coefficient Data MGB Value. ........ 167

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Chapter 8 Windows
Table 8.1 Bit Content of Window Position Register for Horizontal
Coordinates. .................................................................................... 182
Table 8.2 Bit Content of Window Position Register for Vertical
Coordinates. .................................................................................... 183

Chapter 9 Sprite Data
Table 9.1 Shared Bits .....................................................................................200
Table 9.2 Selection of Sprite Priority Number Register .................................. 204
Table 9.3 Selection of Sprite Color Calculation Ratio Register ...................... 206

deChapter 11 Priority Function
Table 11.1 Priority when the Priority Numbers are Equal ............................... 225
Table 11.2 Special Priority Function by Mode ................................................ 228

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Chapter 12 Color Operation
Table 12.1 Color Operation Function when in High Resolution
Mode or Special Monitor Mode .................................................... 236
Table 12.2 Expanded Color Calculation Ratio................................................ 238
Table 12.3 Special Color Calculation Mode ................................................... 246

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Chapter 15 Method of Using VDP2
Table 15.1 Register Connected with Data Defined in VRAM ......................... 265

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Chapter 1 VDP2 Functions

ST-58-R2

Introduction .......................................................... 2
1.1 System Configuration .................................. 2
1.2 Address Map ............................................... 3
VRAM .................................................... 3
Color RAM ............................................. 3
Register ................................................. 4
1.3 Scroll Function ............................................ 5
Display Screen ...................................... 5
Scroll Screen ......................................... 6
Line Screen .......................................... 7
Windows.......................................... 7
1.4 Priority Function .......................................... 8
Priority Function .................................... 8
Color Calculation Function .................... 8
Color Offset Function ............................ 8
Shadow Function ................................... 91

IntroductionntialVDP2 has a scroll and priority function. The scroll function defines the scroll screen,
moves the screen up, down, right, left, and rotates the screen. The priority function
prioritizes the display of multiple scroll screens, sprites, and external screens. It also
processes the images in operations such as color calculation and color offset.

1.1 System Configuration

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VDP2 is connected to 4 Mbit or 8 Mbit VRAM and contains 32K bits of color RAM.
Image data is defined in the VRAM and color RAM from the CPU via the SCU.
Image display controlling information is set by each register in the same way. Datadefined by VRAM is read according to the setting of the register, then becomes theimage data of each scroll screen. Image data of each scroll screen and sprite image
data received from VDP1, as well as the external image data received from outside,
become image display data. Display priority is decided by the register setting.
When display image data is in a palette format, color data defined in the color RAM
according to that value is read and displayed. When display image data is in the
RGB format, it is shown as is. In this way, the acquired display color data is output
to the display device. The VDP2 system configuration is shown in Figure 1.1.

Co

External Screen
Circuitry(OPTION)

VDP1

VDP2

Register

SCU

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CPU

Color RAM

VRAM

Figure 1.1 System Configuration2

Display Device

1.2 Address Map

000000H

0FFFFFH
100000H

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VRAM

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In order to define pattern name tables and character pattern data, VDP2 is connected
to two VRAMs. VDP2 contains 32K bits of color RAM for defining color data, andtogether with internal registers control VRAM. Figure 1.2 shows VDP2 controlled
VRAM, color RAM, and register address maps.

COLOR-RAM
17FFFFH
180000H

REGISTER
1BFFFFH

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Figure 1.2 Address Map

VRAM

Color RAMCo

VRAM stores scroll screen image data and data tables needed in each function.
Read access by VDP2 is always given priority over read/write access through the
CPU or DMA controller. Consequently, the wait cycle enters the CPU or DMA
controller through the access timing. Access through the CPU or DMA controller ispossible in units of byte, word, and long word.

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Color RAM stores color data of sprites and scroll screens. It also defines the enable
bit of the color calculation function as it applies to the most significant bit whennecessary. Read/write access from the CPU or DMA controller is possible, but theimage may be disturbed by the access timing. Access through the CPU or DMA
controller is possible only in word units and long word units. Access in bytes is notallowed.

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Register

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Registers set each VDP2 function. Because the values of most registers are cleared to
0 after power on or reset, the values must be set. Read/write access from the CPU or
DMA controller is always possible, but the image may be poor due to the accesstiming. Access by the CPU or DMA controller is possible only in word units andlong word units. Access in bytes is not allowed.

4

1.3 Scroll Function

Display Screenntial

The VDP2 scroll function has a scroll screen and a window.

The TV screen mode has the following characteristics.
Table 1.1 TV Screen Mode

NormalGraphic A
NormalGraphic B
Hi-ResGraphic A
Hi-ResGraphic B
Exclusive Normal
Graphic A
Exclusive Normal
Graphic B
Exclusive Hi-Res
Graphic A
Exclusive Hi-Res
Graphic B

Hi-ResExclusive
MonitorVerticalResolution(Pixels)

Display Device

224

NTSC Format

240

or

640

256

PAL Format

704

selection

TV

320

480

31kHz Monitor

352

480

Hi-Vision Monitor

640

480

31kHz Monitor

704

480

Hi-Vision Monitor

320
352

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NormalHorizontal
Resolution(Pixels)nfi

Graphic ModeCo

TV ScreenMode

The scroll screen which can be displayed has the following characteristics.
Table 1.2 Scroll Screen

Scroll Screen Name

Name

Remarks

Rotation
Scroll Screen
Line

Normal Scroll 0
Normal Scroll 1
Normal Scroll 2
Normal Scroll 3
Rotation Scroll 0
Rotation Scroll 1
Line Color Screen

NBG0
NBG1
NBG2
NBG3
RBG0
RBG1
LNCL

Can move up/down/left/right. Can scale
Can move up/down/left/right.
Can scale/rotate

ScreenBack Screen

BACK

Expandable Screen

External Input Screen

EXBG

Used only in color
calculations
Displayed only whenother screens are notdisplayed
Screen input externally

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NormalScroll Screen

ST-58-R2

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The following windows exist:

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Table 1.3 Windows
Window Name

Name

Remarks

Normal Window

W0
W1
SW

Line Window allowed

Sprite Window

Sprite Character Window

Scroll Screen

The functions of the scroll screen are listed in the table below.
Table 1.4 Scroll Screen Function

Character
Color Count

Normal Scroll Screen
NBG0
NBG1

16 colors
256 colors
2048 colors

16 colors
256 colors
2048 colors

32,768 colors

32,768 colors

16,770,000 colors

selection

NBG2

NBG3

Rotation Scroll Screen
RBG0
RBG1

16 colors
256 colors
selection

16 colors
256 colors
selection

16 colors
256 colors
2048 colors

16 colors
256 colors
2048 colors

32,768 colors

32,768 colors

16,770,000 colors

16,770,000 colors

selection

selection

selection
1 Cell H x 1 Cell V; 2 Cells H x 2 Cells V

deFunction

512 H x 512 V Dots1024 H x 256 V Dots1024 H x 512 V Dots

Vertical Cell
Scroll Function
MosaicProcess
Function

Note:

None

None
Yes

Yes

Yes

Yes

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Scale
Function
Rotation
FunctionLine Scroll
Function

selection
1/4~256 ratio

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Character
Size
Pattern Name 1 Word, 2 Words selection
Data Size
Plane Size
1 H x 1 V 1 Pages; 2 H x 1 V 1 Pages; 2 H x 2 V Pages
Plane Count 44
44
Bitmap
Display
Display
Display Not
Display Not
Display
AllowedAllowedAllowedAllowed512 H x 256 V Dots
None
Bitmap Size

Yes

16
Display
Allowed16
Display Not
Allowed512 H X 256 V None
Dots
512 H X 512 V

selection
Any Ratio
Yes

No

No

No

No

No

No
Yes (Horizontal Direction Only)*There are 2048 colors when the color RAM is in mode 1, and 1024 colors when in mode
0 or 2.

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Normal scroll screen changes the number of screens that can be displayed througheach setting.

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The normal scroll screen can be displayed simultaneously with one rotation scroll
screen. If two rotation scroll screens are displayed, the normal scroll screen cannot
be displayed (the register that sets RBG1 is used for NBG0). When an external input
screen is displayed, NBG1 cannot be displayed. The register setting the external
input screen can be used for NBG1.
Line Screen

The line color screen works for color calculation and on other screens. It can indicate
whether the entire screen consists of one color, or if there is a color for each line, but
it cannot display characters.

deThe back screen is displayed when all other screens are transparent. The entire
screen is displayed in one color, or a color can be selected for each line, but characters cannot be displayed.
Windows

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A rectangular window can be selected by using the two screen coordinate value
points in the upper left and lower right corners of a normal window. The sprite
window is a window based on sprite characters. There are three types of windowsthat can be used and stacked individually for each screen: the “transparent control
window” designates the transparent area; the “color calculation window” designates
the area in which color calculation is not performed; the “rotation parameter window” changes screens by two rotation parameters.

ST-58-R2

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1.4 Priority FunctionntialThere are four types of VDP2 priority functions: priority function, color calculation
function, color offset function, and shadow function.
Priority FunctiondeThe display priority of the sprite and scroll screen is decided by a 3-bit priority
number. The sprite priority number can be set at a maximum value of 8, one ofwhich is designated by character units. The scroll screen priority number is usuallydesignated by surface units. When the special priority function is used, character
units and dot units can change the scroll screen priority number.
Color Calculation Functionnfi

By adding color data of multiple screens, the color calculation function produces aneffect in which the back screen can be seen through the front screen. It is normally
performed by two screen images, the top image and the second image, but up to
four screens can be peformed when the expanded color calculation function is used.
Surface units determine whether the color calculation is performed. Sprites can beselected by character units through sprite color calculation condition settings. Whena scroll screen uses the special color calculation function, sprites can be selected bycharacter units and dot units.

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The color calculation ratio of the top and second images can be selected from 32
steps. Sprites can set a maximum of 8 color calculation ratios, among which one canbe selected by character units. The scroll screen is selected by surface units.
When the Gradation function is used, one selected screen can be gradated horizontally and displayed.
Color Offset Function

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The color offset function is used for displaying the offset value calculation (subtraction) for color data, and for fade in and fade out purposes. The color offset function
can be specified by surface unit. Up to two color offset values can be selected foreach RGB, one of which can be specified by surface units.

8

Shadow Function

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The shadow function adds shadow to the shapes of sprite characters on each screen.
There are two types of sprite shadow: normal shadow by data, and MSB shadow.
The normal shadow can only add a shadow to the scroll screen. The MSB shadow
can add a shadow to scroll screens and to sprites.

ST-58-R2

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(This page was blank in the original Japanese document.)

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Chapter 2 TV Screen

ST-58-R2

2.1
2.2
2.3
2.4
2.5

TV Screen Mode .................................................. 12
Special High Resolution Graphics Mode ............. 13
Interlace Mode ..................................................... 14
TV Screen Structure ............................................ 15
TV Screen Mode Register ................................... 16External Signals and Scan Conditions ................ 19
External Signal Enable Register .................... 19
Screen Status Register .................................. 21
H Counter Register ........................................ 23
V Counter Register ........................................ 24

11

2.1 TV Screen ModentialVDP2 can display images in 31 kHz monitors as well as high-vision monitors, and in
NTSC and PAL standards for TV. There are three kinds of image displaying TV
screen modes: normal, high-resolution, and special monitor. Screen scan format canbe selected from three types: non-interlace, single-density interlace, and doubledensity interlace. A register showing TV scan conditions is also provided.

Table 2.1 TV Screen ModeTV Screen
Mode

Graphics Mode

Interlace Mode

NormalNon-interlace

InterlaceNon-interlace
NormalGraphic B

Hi-ResNon-interlace

Hi-ResGraphic A

InterlaceNon-interlace

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Hi-ResGraphic B

InterlaceSE

Non-interlace
Non-interlace
Non-interlace
Non-interlace

12

320 X 224
320 X 240
320 X 256
320 X 448
320 X 480
320 X 512
352 X 224
352 X 240
352 X 256
352 X 448
352 X 480
352 X 512
640 X 224
640 X 240
640 X 256
640 X 448
640 X 480
640 X 512
704 X 224
704 X 240
704 X 256
704 X 448
704 X 480
704 X 512
320 X 480
352 X 480
640 X 480
704 X 480

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Interlace

Horiz X Vertical.
Resolution(Pixels)

Restrictions DuringUse

PAL standard only

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NormalGraphic A

deTable 2.1 shows the TV screen modes that are selectable, the graphics mode, and thecurrent resolution. Furthermore, special settings are required when indicating
special high-resolution graphics A and special high-resolution graphics B.

PAL standard only

PAL standard only

PAL standard only

PAL standard only

PAL standard only

PAL standard only

PAL standard only
31kHz monitor onlyHi-vision monitor only
31kHz monitor onlyHi-vision monitor onlySpecial High-Resolution Graphics Modential

The graphics mode of special high-resolution graphics A or B displays one screen by
joining the NBG0 and NBG1 screens. If the following setting is not performed, thedisplay will not appear correctly.

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• Must be able to display only NBG0 and NBG1.
• The NBG0 and NBG1 character pattern tables (or, bit map pattern) and patternname tables must use the exact same data.
• Must be able to reduce both NBG0 and NBG1 horizontally up to 50%.
• Set the vertical direction screen scroll values of NBG0 and NBG1 so that they
are identical.
• Set the NBG1 horizontal screen scroll value at the NBG0 horizontal screen
scroll value plus 1.
• Set both NBG0 and NBG1 horizontal coordinate increments at 2.
• Set the color RAM mode to 0.
• Set the priority numbers of NBG0 and NBG1 at the same value.
• Do not enter the line color screen.
• Special priority of both NBG0 and NBG1 should be in mode 0.
• Do not use the color calculation function.
• For registers other than those listed above, NBG0 and NBG1 settings shouldbe the same.

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2.2 Interlace Modenfi

8X8 Do t Char act er Pat ter n

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VDP2 interlace mode (screen scan method) consists of non-interlace, single-density
interlace, and double-density interlace modes. The non-interlace mode is 1 field perframe (1/60 sec.). The single-density interlace mode is 2 fields (1/30 sec.) per frame;
the same image is displayed in even and odd fields. The double-density interlace
mode is 2 fields (1/30 sec.) per 1 frame with separate images being displayed in evenand odd fields. There is no space between scan lines in both the single-density anddouble-density interlace modes, but the actual resolution in the vertical direction of
the single-density interlace mode is the same as the resolution in the vertical directionof the non-interlace mode. Figure 2.1 shows display methods by interlace settings.

● No n- Inter lace Mo deCo

Be cau se sca nn ing occu rs a t the same a rea i neve ry fiel d, some area s may n ot be scan ne d, thu s
crea ting some g ap s.
1 frame p er 1 fiel d (1/60 se c.)GA● Singl e Densi ty Int erl ace Mod e

Sca nn in g occu rs i n ea ch o dd an d even field ,ho weve r, sin ce the same pi cture i s di sp la yed , thevertica l resol utio n wi ll be si milar to that in the N onInterl ace M ode .
1 frame p er 2 fiel ds (1/30 se c.)SE●Å Doub le Den sit y Inter lace Mo de

Sca nn in g occu rs i n ea ch o dd an d even field ,ho weve r, sin ce di fferent pi ctures are di spl ayed ,the ve rtica l resol ution wil l b e d ou bl e tha t i n theNon -Interlace mod e.
1 frame p er 2 fiel ds (1/30 se c.)

Figure 2.1 Display Method by Interlace Setting

14

2.3 TV Screen Structure

Hor izo nt al Tr acin g
Per iod

Ho rizo nt al Disp lay
Per iod

Hor izon tal Tra ci ng
Per iodnfi

Ver tica l Traci ng
Peri od

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In response to the TV screen mode, VDP2 outputs image signals corresponding totheir respective NTSC standard or PAL standard TV, 31 kHz monitor, and highvision monitor. The TV screen is a collection of rasters constructed by vertical display intervals, vertical blank intervals (V blank interval), and their respective horizontal display intervals and horizontal blank intervals (H blank interval). The TV
screen structure is shown in Figure 2.2. The location where horizontal display intervals and vertical display intervals overlap is the standard display area of the various
TV formats. The set display area, where VDP2 is able to display the image, isslightly smaller than the standard display area. The border area excludes the set
display area from the standard display, and can output either black or the backscreen.

Ve rtical Displ ay
Per iod

Set ting
Displ ay Are aGA

Ver tica l Traci ng
Peri od

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Boar de rA re a

Stan da rd
Displ ay Are a

Stand ar d Displ ayA re a= Setting Displ ay Area+ Boar de r Area

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Figure 2.2 TV Screen Structure

ST-58-R2

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2.4 TV Screen Mode Register

TVMD
180000H

15
DISP
7
LSMD1

14
~
6
LSMD0

13
~
5
VRESO1

12~
4
VRESO011~3~• TV screen display bit : Display bit (DISP), bit 15

10~
2
HRESO2

9~
1
HRESO18BDCLMD
0
HRESO0deControls picture display to the TV screen.

ntial

The TV screen mode register controls the TV screen display. It is a read/write 16 bit
register and is at address 180000H. After the power on or reset, the value is cleared
to 0 and therefore must be set.

DISP

Process

01

Picture is not displayed on TV screen
Picture is displayed on TV screen• Border color mode bit (BDCLMD), bit 8

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Because it is in the blank condition during the display interval when this bit is 0, theVRAM can be accessed from the CPU or DMA controller at any time. The colors
displayed when this bit is 0 are selected by the BDCLMD bit. Please make sure tochange this bit from 0 to 1 during V blank.
Controls colors displayed by the border area.
Process

01

Displays black
Display back screen

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BDCLMD

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Selects colors of all the standard display areas when the DISP bit is 0. However, after
the power on or reset, if this bit is set to 1 without setting DISP bit to 1 even once, theback screen will not be correctly displayed. When the setting allows the back screen
selection by line, the color displayed in the border area will become the same color
as the lowermost line in the display area.

16• Interlace mode bit (LSMD1, LSMD0) bits 7 and 6

Designates the interlace mode.
LSMD0Process

0
0
1
1

0
1
0
1

Non-Interlace
Setting not allowed
Single-density interlace
Double-density interlace

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Single-density interlace is a mode that shows the same pictures in odd and evenfields; double-density interlace is a mode that shows different pictures in odd andeven fields. In either case, the spaces between scan lines are not vacant. The verticalresolution for double-density interlace is twice that of non-interlace, but the verticalresolution of the actual picture for single-density interlace is the same for noninterlace. Pictures displayed in double-density interlace are vertically half the sizeof pictures displayed in single-density interlace or non-interlace. When the horizontal resolution (HRESO2 to HRESO0) setting is in the exclusive monitor mode, makesure to select the noninterlaced mode (00B).
• Vertical resolution bit (VRESO1, VRESO0), bit 5, 4
VRESO0

0
0
1
1

0
1
0
1

Vertical Resolution

Display Monitor

224 Lines
240 Lines
256 Lines
Not Allowed

NTSC or PAL format TV
NTSC or PAL format TV
PAL format TV-

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Designates vertical resolution when a picture is displayed on the TV screen.

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Increments when vertical resolution is increased, then are added to the top andbottom of the screen without changing the screen’s center. When set in the special
monitor mode, the horizontal resolution (HRESO2 to HRESO0) is set to 480 lines.
Settings of this bit are ignored.

ST-58-R217

• Horizontal resolution bit (HRESO2 to HRESO0), bit 2 to 0

Selects the horizontal resolution when a picture is displayed on the TV screen.
HRESO1HRESO0

Horizontal
Resolution

Graphic Mode

0

0

0

320 Pixels

0

0

1

352 Pixels

0

1

0

640 Pixels

0

1

1

704 Pixels

NormalGraphic A
NormalGraphic B
Hi-ResGraphic A
Hi-ResGraphic B

1

00

320 Pixels

1

0

1

352 Pixels

1

1

0

640 Pixels

1

1

1

704 Pixels

Display
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HRESO2

31kHz Monitor

Hi-Vision MonitordeExclusive Normal
Graphic A
Exclusive Normal
Graphic B
Exclusive Normal
Graphic A
Exclusive Normal
Graphic B

NTSC
Format or
PAL
Format TV

31kHz Monitor

Hi-Vision Monitor

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When special high-resolution graphics A or B is selected, other registers must be set
as directed. See “Special High Resolution Graphics Mode” on page 13 for more
information. When switching the TV mode from exclusive monitor mode to normal
mode or hi-res mode, make sure to reset the VDP2.

18

2.5 External Signals and Scan Conditions

External Signal Enable Registerntial

The register controlling external signals has an external signal enable register. The
register displaying TV scan conditions has a screen status register, H counter register, and V counter register.

The external signal enable register controls signals from the VDP2 exterior. It is aread/write 16 bit register and is at address 180002H. After the power is turned on or
reset, the value is cleared to 0 and must be set.
15
~
7
~

14
~
6
~

13
~
5
~

• External latch enable bit (EXLTEN), bit 9

12
~
4
~

11
~
3
~

10
~
2
~

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EXTEN
180002H

9
EXLTEN
1DASEL

8EXSYEN0
EXBGEN

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Selects the condition for latching the HV counter value to the HV counter register.
EXLTEN

Condition

01

Latches when reading external signal enable register
Latches through external signal

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The latched H counter value can read with the H counter register; V counter value
can read with the V counter register. When reading H and V counter values throughexternal signals such as laser guns, the bit should be set at 1. Otherwise, it should be
set at 0.
• EXSYNC enable bit (EXSYEN), bit 8

Controls input to the internal synchronous circuit of the external sync signal.
EXSYEN

Process

Does not input external sync signal
Inputs external sync signal, and synchronizes TV screen display with theexternalGA

0
1

When synchronizing with other devices and screen displays, set to 1 and input an
EXSYNC signal. The normal setting is 0.
• Display area select bit (DASEL), bit1

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Designates the image display area. Valid only when the EXBGEN bit is 1.

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Process

01

Displays screen image only in the set display area
Displays screen in the standard display area

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DASEL

When displaying the entire standard display area, images from external screen data
are displayed correctly. Images not in set display areas (sprite, scroll screen, etc.)
need to be made transparent using a window because they are not displayed correctly.
• EXBG enable bit (EXBGEN), bit 0
EXBGEN

Process01

Does not input external screen data
Inputs external screen datadeControls input of external screen data.

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Because the data becomes NBG1 screen data when inputting external screen data,
the external screen settings are used for NBG1 as well. Table 2.2 shows the register
bit for setting the external screen.

20

Table 2.2 Register for setting the external screen
Bit Name

9
13,12
8
9
10
11
12
13
15
1
6~4
1
3,2
1
3,2
10~8
12~8
1
1

N1TPONN1CHCN1, N1CHCN0
N1W0A
N1W0E
N1W1A
N1W1E
N1SWA
N1SWE
N1LOG
N1SDENN1CAOS2~N1CAOS0
N1LCENN1SPRM1, N1SPRM0
N1CCENN1SCCM, N1SCCM0N1PRIN2~N1PRIN0N1CCRT4~N1CCRT0
N1COENN1COSL

1800E2H
1800E4H
1800E8H
1800EAH
1800ECH
1800EEH
1800F8H
180118H
180110H
180112H

Screen Status Register

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1800D0H

Transparent display enable
Character Color CountW0 window area
W0 window enable
W1 window area
W1 window enable
SW window area
SW window enable
Window logic
Shadow enable
Color RAM address offset
Line color screen insertion enable
Special priority mode
Color calculation enable
Special color calculation mode
Priority number
Color Calculation Ratio
Color offset enable
Color offset selectnti
alBit Number

180020H
180028HdeAddress

The screen status register displays TV screen information. This read exclusive 16-bit
register is at address 180004H.
14
~
6
~

13
~
5
~

12
~
4
~

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15
~
7
~

11
~
3
VBLANK

10~2
HBLANK

9
EXLTFG
1ODD

8EXSYFG
0
PAL

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TVSTAT
180004H

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• External latch flag (EXLTFG), bit 9

EXLTFGHV Counter Value Status01

Not latched in register
Latched in registerntialThrough external signals, this displays whether the HV counter value is latched to
the HV counter register. Clears to 0 when the screen status register reads out.

• External SYNC flag (EXSYFG), bit 8

EXSYFG

External Sync Status01

Not synchronizedInternal circuit synchronized• Vertical blank flag (VBLANK), bit 3

Displays the vertical scan status of the TV screen.
Vertical Scan Status01

During vertical scan
During vertical re-trace (VBLANK)• Horizontal blank flag (HBLANK), bit 2

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VBLANKde

Displays whether the internal routes through External SYNC flag are in sync.
Clears to 0 when the screen status register reads out.

Displays the horizontal scan status of the TV screen.
Horizontal Scan Status01

During horizontal scan
During horizontal re-trace (HBLANK)

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HBLANK

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ODD

Display01

During even field scan
During odd field scan

• TV standard flags : PAL/NTSC flag (PAL), bit 0
PAL

Display

0
1

NTSC standard
PAL standard

H Counter Registerde

Displays TV standards.

ntial• Scan Field Flag : Odd/even field flag (ODD), bit 1
Scan conditions are shown when the TV screen mode is the interlace mode. The
non-interlace mode is always 1.

The H counter register shows the H counter value. This read exclusive 16-bit register is at address 180008H.
15
~
7
HCT7

14
~
6
HCT6

13
~
5
HCT5

12
~
4
HCT4

11
~
3
HCT3

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HCNT
180008H

10
~
2
HCT2

9
HCT9
1
HCT1

8
HCT8
0
HCT0

• H counter bit (HCT9 to HCT0), bits 9 to 0

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Signals controlled through EXLTEN external signal enable register show the latched
H counter values. The bit configuration of this bit changes according to the settingof the graphics mode, as seen in Table 2.3. For normal graphics of H counter values,
the HCT0 of the least significant bit is invalid data. For special normal graphics of
H counter values, the HCT9 of the most significant bit is invalid data. For the
H counter value of special high-resolution graphics, the most significant bit of HCT9
becomes invalid. Because there is no bit for H0, it shows a value of 2 dot units.

ST-58-R2

23

Table 2.3

H counter register bit content

Graphic
Mode
NormalHi-ResExclusive
NormalExclusive
Hi-Res

HCT9

HCT7

HCT6

HCT5

HCT4

HCT3

HCT2

HCT1

HCT0

H8
H7
H9
H8
Invalid H8

H6
H7
H7

H5
H6
H6

H4
H5
H5

H3
H4
H4

H2
H3
H3

H1
H2
H2

H0
H1
H1

Invalid
H0
H0

Invalid H9

H8

H7

H6

H5

H4

H3

H2

H1

nti
al

HCT8

V Counter Register

14
~
6
VCT6

13
~
5
VCT5

12
~
4
VCT4

11
~
3
VCT3

10
~
2
VCT2

9
VCT9
1
VCT1

8
VCT8
0
VCT0

nfi

VCNT
18000AH

15
~
7
VCT7

de

The V counter register shows the V counter value. This read exclusive 16-bit register
is at address 18000AH.

• V counter value bit : V counter bit (VCT9~VCT0), bit 9 to 0

Co

Signals controlled through EXLTEN external signal enable register show the latched
V counter values. The bit configuration of this register changes according to thesettings of the TV screen mode, as shown in Table 2.4. The V counter values for
single density interlace of the normal and high resolution modes show V countervalues in their various even and odd fields. The V counter values for double density
interlace of normal and high resolution modes show the odd fields when 0 and evenfield when the least significant bit of VCT0 is 1. VCT1~VCT9 show the V countervalues in their respective fields.
Table 2.4 V counter register bit content
VCT7

VCT6

VCT5

VCT4

VCT3

VCT2

VCT1

VCT0

V7

V6

V5

V4

V3

V2

V1

V0

Invalid

V9

V7

V6

V5

V4

V3

V2

V1

V0

0: Odd fields
1: Even fields

V8

V7

V6

V5

V4

V3

V2

V1

V0

SE

Exclusive
MonitorVCT8GATV Screen
VCT9(Interlace) Mode
Normal Hi-Res
V8(Non-Interlace,Single-Density
Interlace)Normal Hi-Res
V8(Double-Density
Interlace)

24

nti
al

SE

GA

Co

nfi

de

Chapter 3 RAM

ST-58-R2

Introduction...................................................................... 26
3.1 Address Map ............................................................. 26
VRAM Size Register ............................................... 28
3.2 VRAM Bank Partitioning ............................................ 29
RAM Control Register ............................................ 29
3.3 Accessing VRAM During Display Interval ................. 31
VRAM Access During Display Interval ................... 31
Image Data Access ................................................ 32
Vertical Cell Scroll Table Data Access .................... 35
Read/Write Access by the CPU .............................. 35
VRAM Cycle Pattern Selection Process................. 37
VRAM Cycle Pattern Register ................................ 39
3.4 Color RAM Mode ....................................................... 43
RAM Control Register ............................................ 45

25

IntroductionntialVDP2 is connected to special VRAM for defining pattern name tables, character
patterns, and so on. VRAM has two divisions called VRAM-A and VRAM-B, eachhaving equal capacity. VRAM-A and VRAM-B can each be divided into two banks,called bank 0 and bank 1. Banks divided with four equal capacities are called
VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1. VRAM data is defined in table
3.1. Also contained is color RAM for defining the color data of scroll screens andsprites.
Table 3.1 Data defined in VRAM

nfi

de

Data that must be defined when Data that must be defined when Data defined as necessary
display format is cell (format)
display format is bitmap (format)
Pattern name table data
Bitmap pattern data
Line scroll table data
Character pattern data
Vertical cell scroll table data
Rotation parameter table data
Coefficient table data
Line color screen table data
Back screen table data
Line window table data

3.1 Address Map

SE

GA

Co

VDP2 can be applied to two types of VRAM: 4 Mbit and 8 Mbit. Programs createdfor systems using a 4 Mbit VRAM can also be used in systems using 8 Mbit VRAM,
but programs created for systems using an 8 Mbit VRAM cannot be used in systems
using 4 Mbit VRAM.

26

● VRAM Size: 4M Bit
000000H
VRAM-A0
01FFFFH
020000H
VRAM-A1
03FFFFH
040000Hde

VRAM-B0
05FFFFH
060000Hntial

The address map changes according to VRAM capacity being used in the system, as
shown in Figure 3.1.

VRAM-B1

07FFFFH

nfi● VRAM Size: 8M Bit
000000H

VRAM-A0

Co

03FFFFH
040000H

VRAM-A1

07FFFFH
080000H

VRAM-B0GA

0BFFFFH
0C0000H

VRAM-B1
0FFFFFH

SE

Figure 3.1 Different Capacities of VRAM Address Map

ST-58-R2

27

VRAM Size Register

VRSIZE
180006H

15
VRAMSZ
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
VER3

Indicates the VRAM capacity used in the system.
VRAMSZVRAM Size0
1

4 Mbit
8 Mbit

10
~
2
VER2

This bit must be set before data is written to VRAM.

nfi

Version Number Bit (VER3 to VER0), Bits 3 to 0

SE

GA

Co

Shows the VDP2 version number; the first is 0.

28

9
~
1
VER1

de

VRAM size bit (VRAMSZ), bit 15.

ntial

The VRAM size register indicates the VRAM capacity to be used in the system. It isa read/write 16-bit register and is at the 180006H address. Bits 3 to 0 are exclusively
for read only. Because the value of bit15 (VRAMSZ) is cleared to 0 after the power isturned on or reset, it must be reset.
8
~
0
VER0

nti
al

3.2 VRAM Bank Partitioningde

VDP2 can access VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1 at the same time
when both VRAM-A and VRAM-B are divided in half. As a result, more image data
can be obtained at once, a higher number of scroll screens can be displayed simultaneously, and a screen with multiple colors can be displayed. However, there arelimitations when selecting of VRAM read/write access through the CPU during thedisplay. Therefore, don’t partition the VRAM into two areas when accessing (read/
write) through the CPU during the display. Normally, accessing can be efficiently
done if divided into two areas.
RAM Control Register

RAMCTL
18000EHnfi

RAM control register selects VRAM bank partitions with the objective of using therotation scroll screen VRAM as well as the color RAM mode. It is a read/write
16-bit register and is at the 18000EH address. Also, because the value is cleared to 0,
it must be set after the power is turned on or reset.
15
14
13
12
11
10
9
8
CRKTE
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00

Co

Color RAM Coefficient Table Enable Bit (CRKTE), Bit 15

See “6.4 Coefficient Table Control.”Color RAM Mode Bit (CRMD1, CRMD0), Bits 13 and 12

See “3.4 Color RAM Mode.” Set the Color RAM mode to mode 1 when the CRKTE
bit is 1. At that time, color data can no longer be stored because the second half ofthe color RAM (100800H ~ 100FFFH) is used for the coefficient table data.
VRAM Mode Bit (VRBMD, VRAMD), Bits 9 and 8

GA

Controls VRAM bank partitions.
18000EH
18000EH

Bit 8
Bit 9

For VRAM-A
For VRAM-B

SE

VRAMD
VRBMD

ST-58-R2

29

Note:

Process
Do not partition in 2 banks
Partition in 2 banks

nti
al

VRxMD
0
1

Enter A or B into bit name for x.

Rotation Data Bank Select bit: RBG0 DataBank Select Bit (RDBSA00 to RDBSB11), Bits 7 to 0

SE

GA

Co

nfi

de

See “6.2 Rotation Scroll Screen Display Control”.
When the CRKTE bit is 1, do not designate to allow the 4 banks of VRAM to be used
as RAM for the coefficient table data.

30

3.3 Accessing VRAM During Display IntervalntialVRAM Access During Display Interval

VDP2 synchronizes scroll screen data with the TV scan and displays them while
reading from VRAM. VRAM access during display repeats the cycle as four or eightaccess operating units (1 cycle). When the TV screen mode is the Normal mode, 1cycle accesses eight times. Also, 1 cycle is accessed four times when in the highresolution or special monitor mode. Below are the ten types of VRAM accesses
performed in one cycle:deNormal scroll screen pattern name data read access.
Normal scroll screen character pattern data read access or bit map pattern data read access.
NBG0, NBG1 vertical cell scroll table data read access.
Read/Write access through the CPU.
Does not access.
RGB0 pattern name data read access.
RGB0 character pattern data read access or bit map pattern data read access.
RGB0 coefficient table data read access.
RGB1 pattern name data read access.
RGB1 character pattern data read access.

nfi

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)

Co

The timing during the 1 cycle when the above (1) through (5) are performed must be
selected for each bank of VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1. This
selection is performed by writing the values of 4 bits, called access commands, to the
VRAM cycle pattern register. Access Commands correspond to the several types of
VRAM access.
Each VRAM access in the above items (6) through (8) occupies a full one cycle,
therefore, for one bank only one type may be selected. This is accomplished bywriting the value corresponding to each VRAM access type to the RAM control
register rotation data bank select bit. The setting of the bank VRAM cycle patternregister, which select (6) through (8) VRAM access, will become invalid.

SE

GA

Each VRAM access in the above items (9) and (10) occupies a full one cycle. (9) is
fixed in VRAM-B1 and (10) in VRAM-B0. While items (9) and (10) are selected automatically with the display of RGB1, the setting of the VRAM-B0 and VRAM-B1
VRAM cycle pattern registers will become invalid.

ST-58-R2

31

T0

T1

T2

T3

T4

T5

T6

T7

de

1 pa rtition= 4 Bit, sel ect for VRA M accessntial

The VRAM cycle pattern register has registers that correspond to the following
banks: VRAM-A0, VRAM-A1, VRAM-B0, VRAM-B1. When the VRAM is not divided into two partitions, the VRAM-A0 register is used for VRAM-A, and the
VRAM-B0 register is used for VRAM-B. Registers for VRAM-A1 and VRAM-B1 are
not used. Registers that correspond to the various banks are separated into eight (T0
to T7) access timings. Access is performed in order, beginning from VRAM access,showing the access command selected in the T0 bit. T0 to T7 are in effect when the
TV screen is in Normal mode, but only T0 to T3 are in effect for the high-resolution
or special monitor mode; T4 to T7 are ignored. Figure 3.2 shows the VRAM cycle
pattern register used during 1 cycle.

Fo r VRAM-A0 (o r VRAM-A )For VRAM-A 1

nfi

Fo r VRAM-B0 (o r VRAM-B )For VRAM-B 1

Regi st er ena bl ed ran ge (T 0~T 3) in Hi-R es or Excl usive Mon ti or Mod e.

CoRe gi st er en abl ed ran ge (T0~ T7) in Norm al Mod e

Figure 3.2 VRAM Cycle Pattern RegisterGA

Be sure to set “do not access” for the remaining access time after selecting the VRAM
access required in the display. If the VRAM access address selected in the VRAM
cycle pattern register is not the address in the selected bank, access won’t be done
and the correct screen will not be displayed.
Image Data AccessSE

The required image data must be read from VRAM for normal scroll screens (NBG0
to NBG3) to be displayed. When the display format is the cell format, the required
image data is pattern name data and character pattern data. When in a bit map
format, the necessary image data is bit map pattern data . The VRAM access number for obtaining this image data during 1 cycle is decided by the conditions.

32

nti
al

Pattern name data read access during 1 cycle must be set to a maximum of twobanks, one being either VRAM-A0 or VRAM-B0, and the other being VRAM-A1 or
VRAM-B1. When the VRAM is not divided into two partitions, the VRAM-A0
register is used as VRAM-A, and the VRAM-B0 register is used as VRAM-B; therefore, one or the other must be set. Any access timing may be selected if within theregister’s effective range in all TV screen modes. The access number must be thesame as the number as determined by conditions, but the related timing does notneed to be selected.
The pattern name data read access number is shown in Table 3.2. The pattern namedata read access selection limits are shown in Figure 3.3.

NBG0~NBG3

Reduction setting x1
Number of VRAM 1
accesses required
during 1 cycle

Only on e
can besel ect ed

x1/2
2

T0

T2

T3

T4

Co

Only on e
can besel ect ed

T1

x1/4
4

nfi

Item

de

Table 3.2 Access numbers of required pattern name table data during 1 cycle

T5

T6

T7

For VRA M- A0 (or VRAM- A)
For VRAM-A 1
For VRA M- B0 (or VRAM- B)
For VRAM-B 1

Reg ist er en ab led ra ng e (T0~ T3) in Hi -Res or Excl usi ve Mo ni tor Mo de

Reg ist er en ab led ra ng e (T0~ T7) in No rma l Mo de

Figure 3.3 Access selection limits of pattern name table data

SEGA

As a rule, the character pattern data read access during 1 cycle can select any timingfrom four banks. However, the timing that can be selected through pattern namedata access timing is limited. Only when the pattern name data access of NBG0 and
NBG1 are selected in T0 can select various character pattern data read accesses
through the timings of any of the four banks be selected with are no limits. The
access number must be selected so that it is the same as the number as determinedby the conditions. The related timing does not need to be selected. Character patterndata read access numbers are shown in Table 3.3. Character pattern data read accessselection limits are shown in Table 3.4.

ST-58-R2

33

Item

NBG0~NBG3

Character
Color Count
Reduction
setting

16
1

1/2

1/4

1

Number of
VRAM
accessesrequired
during 1 cycle

1

2

4

2

2048

32,768

16,770,000

1/2

1

1

1

4

4

4

8

256

Table 3.4 Character pattern data read access selection limits
Item

TV Screen
Mode

Pattern Name Table Data Access Timing
T0
T1
T2
T3
T4

Timing thatcan selectcharacterpattern data
accessNormal

T0~T2,
T4~T7
T0~T2

T0~T3,
T6~T7
T0, T2,T3

T0~T3,T7
T0, T1,
T3

T6

T7

T0~T3 T1~T3 T2,
T3
-

T5

T3

de

Hi-Res,exclusivemonitor

T0~T3,
T5~T7
T1~T3

nti
al

Table 3.3 Character pattern data (bit map pattern data) read access number

-

T0

T1

T2

T3

Co

nfi

When the reduction setting is one, all of the character pattern data read access mustobserve selection limits if the character pattern data read access is to be two or
greater. If the reduction setting is 1/2 or 1/4, the required access number when the
reduction setting is 1 (one time for 16 colors and two times for 256 colors) mustobserve selection limits through one time pattern name data read access. Figure 3.4
shows character pattern data read access selection limits when the pattern namedata read access is selected in T1 and T3, with 256 colors and 1/2 reduction.
T4

T5

T6

T7

For VRAM-A0 (o r VRAM-A )For VRA M- A1
For VRAM-B0 (o r VRAM-B )GA

For VRA M- B1

T1 's Pat ter n Na me Dat a Read Access with re spe ct to se le ct ab le ran ge (T0~ T3, T5~T 7)

T3 's Pat ter n Na me Dat a Read Access with re spe ct to se le ct ab le ran ge (T0~ T3, T7)

SE

Not e: Ch ar act er Pattern Dat a Rea d Acce ss must be sel ect ed twice in each se le ct ab leran ge.

Figure 3.4 Example of character pattern data read access selection

34

Vertical Cell Scroll Table Data Accessnti
alWhen using the vertical cell scroll function in NBG0 and NBG1 {Translator’s Note:
The original document reads NB1, we believe this is an error.}, vertical cell scroll tabledata must also be read.

Vertical cell scroll table data read access must be performed for one surface during 1
cycle. Vertical cell scroll table data read access for NBG0 must be selected in T0 or
T1 timing. NBG1 vertical cell scroll table data read access must be selected within
the timing of T0 to T2. Also, access for NBG0 and NBG1 must be by the same bankand NBG0 access must be selected first.

deWhen specifying the same vertical cell scroll table data read access against multiple
banks, make sure to specify the same access timing.
Figure 3.5 shows access selection limits of vertical cell scroll table data.
T0

T1

T2

T3

T4

T5

T6

T7

nfi

For VRA M- A0 (or VRAM-A)
For VRAM-A 1
For VRA M- B0 (or VRAM-B)
For VRAM-B 1

Co

NBG0 ver tical scr oll tabl e acce ss sel ect ab le ran ge (T0 , T1)

NBG1 ver tical scr oll tabl e acce ss sel ect ab le ran ge (T0 ~T2 )Not e: For NB G0 and NBG1 access timing , NBG0 access must be first sel ect ed in
the sa me bank.

GA

Figure 3.5 Access select limits of vertical cell scroll table data

Read/Write Access by the CPU

SE

When performing read/write access to the VRAM by the CPU during the screen
display interval, the timing must be set to the VRAM cycle pattern register. VDP2
waits for the selected timing in the CPU read/write access when VRAM access isrequested by the CPU, and approves access only in that timing. When read/write
access is not requested by the CPU, nothing will be performed for VRAM, even for
selected timings. Moreover, during read access through the CPU, the wait cycle willenter the CPU until it is able to read. The write access wait cycle will not be enteredif the two word write access is at least two times.

ST-58-R2

35

nti
al

VRAM access by the CPU can be selected only in units of access to VRAM-A or
VRAM-B, and can not be selected in bank units.
When selecting VRAM access by the CPU for the VRAM without two partitions, you
should select the CPU read/write access command in the VRAM cycle patternregister of the timing performing the access. Selecting an access command that does
not access in place of the CPU read/write access command is the same as before. In
the screen display enable register, when the access command (pattern name data
read, character pattern data read, or bit map pattern data read) used for a screen not
set to be displayed is also set, it becomes the CPU read/write access. See “4.1 Screen
Display Control” about the screen display enable register.

deWhen selecting an access command for not to access or CPU read/write with respect
to every access timing of the VRAM that is not partitioned into two areas, the CPU
access will then be always allowed during display period. This allows to use one of
the VRAMs as an auxiliary work RAM. In addition, by switching the VRAM used in
the image display as a frame buffer, the image can be displayed while being rewritten at a high speed.

T2

T4

T5

No
AccessO the rAccessComm an ds

VRAM Cycle Pattern
Regi st er f or VRAM-ACo

CPU Read /Wri teT3
O the rAccessComm an ds

nfi

Figure 3.6 illustrates the VRAM cycle pattern register selection if CPU read/write
access is being performed in T2 and T4 when VRAM-A is not partitioned.

Figure 3.6 CPU Read/Write Access Selection when VRAM is not Divided into Two BankGA

When setting the CPU read/write access for the VRAM that is partitioned into twoareas, the CPU read/write access command must be set in the VRAM cycle patternregister of both bank 0 and bank 1 of the timing performing access. Further, in theregisters of both bank 0 and bank 1 of the timing before the set CPU read/write
access command timing, the access command that won’t access must be selected.
However, when selecting CPU read/write access in linked timing, only the timing
before the lead of the linked access timing may be selected.

SE

Figure 3.7 illustrates the selection of the VRAM cycle pattern register when performing CPU read/write access linked to T4 and T5 while VRAM-B is divided into twopartitions.

36

NoA ccess

NoA ccess

T4

T5

T6

CPU Rea d/
Wr iteCPU Rea d/Wri teOthe rAccessComm an ds

VRAM Cycle pa ttern Reg ist er
for VRAM-B0

CPU Re ad /Writ eCP U Re ad /Wr ti eOthe rAccessComm an ds

VRA M Cycl e pa ttern Reg ist er
for VRAM-B1

nti
al

T3

Figure 3.7 CPU Read/Write Access Selection when VRAM is Divided into Two Banks

VRAM Cycle Pattern Selection ProcessdeSelection process to the VRAM cycle pattern register is listed below.

SE

GA

Co

nfi

1. Decide the TV screen mode.
2. Decide whether to partition the VRAM into two segments.
3. Decide the number of character colors of the scroll screen being displayed
and the reduction setting. Also, decide whether to use the vertical cell scroll
function.
4. Decide the VRAM bank that will store the required image data (patternname
data, character pattern data, bit map pattern data) for all scroll screens. Decide
the VRAM bank for storing vertical cell scroll table data when the vertical cell
scroll function is used.
5. Decide whether to read/write access through the CPU.
6. To observe selection limits of various access timings, select access command in
the VRAM cycle pattern register.

ST-58-R2

37

nti
al

An example of VRAM cycle pattern register selection is shown in Figure 3.8.

<Condition>
Set TV screen in normal mode.
Partition both VRAM-A and VRAM-B into two areas.
Set the scroll screen as follows:

Vertical Cell Scroll
Character Colors Reduction
SettingFunction

NBG0

256 Colors

x1/2

Do not use

NBG1

256 Colors

x1

Use

NBG3

256 Colors

x1

-

nfi

Banks that store data per each scroll screen:deScreen Name

Pattern Name

Character Pattern

Vertical Cell Scroll Table

NBG0

A0

B0,B1

-

NBG1

A0,A1

B0,B1

A0

NBG3

A1

A1,B0

-

Co

Screen Name

A0: VRAM-A0 A1: VRAM-A1 B0: VRAM-B0 B1: VRAM-B1
Allow CPU read/write access to VRAM-A<VRAM CYCLE PATTERN REGISTER>
T1

T4

T5

T6

T7

N1CE N0PN N1PN N0PN

NA

CPU

CPU

NA

For VRAM-A0 (or VRAM-A)

N3PN

NA

CPU

CPU

N3CG

For VRAM-A1

NA

T2

N1PN

T3

NA

GA

T0

N0CG N0CG N1CG N1CG

NA

N0CG N0CG N3CG

For VRAM-B0 (or VRAM-B)

N0CG N0CG N1CG N1CG

NA

N0CG N0CG

For VRAM-B1

NASE

N0PN : Pattern name data read for NBG0, N0CG : Character pattern Data Read for NBG
N1PN : Pattern name data read for NBG1, N1CG : Character pattern Data Read for NBG
N3PN : Pattern name data read for NBG3, N3CG : Character pattern Data Read for NBG
N1CE: NBG1 vertical cell scroll table data read, CPU : CPU Read/Write
NA : No accessFigure 3.8 VRAM Cycle Pattern Selection

38

VRAM Cycle Pattern Registerntial

The VRAM cycle pattern register controls the VRAM access during the display
interval. It is a 16-bit write only register with addresses from 180010H to 18001EH.
Because the value is cleared to 0 after the power is turned on or reset, it must be
reset.

CYCA0U
180012H

15
14
13
12
11
10
9
8
VCP4A03 VCP4A02 VCP4A01 VCP4A00 VCP5A03 VCP5A02 VCP5A01 VCP5A00
7
6
5
4
3
2
1
0
VCP6A03 VCP6A02 VCP6A01 VCP6A00 VCP7A03 VCP7A02 VCP7A01 VCP7A00

CYCA1L
180014H

15
14
13
12
11
10
9
8
VCP0A13 VCP0A12 VCP0A11 VCP0A10 VCP1A13 VCP1A12 VCP1A11 VCP1A10
7
6
5
4
3
2
1
0
VCP2A13 VCP2A12 VCP2A11 VCP2A10 VCP3A13 VCP3A12 VCP3A11 VCP3A10

CYCA1U
180016H

15
14
13
12
11
10
9
8
VCP4A13 VCP4A12 VCP4A11 VCP4A10 VCP5A13 VCP5A12 VCP5A11 VCP5A10
7
6
5
4
3
2
1
0
VCP6A13 VCP6A12 VCP6A11 VCP6A10 VCP7A13 VCP7A12 VCP7A11 VCP7A10CYCB0L
180018H

15
14
13
12
11
10
9
8
VCP0B03 VCP0B02 VCP0B01 VCP0B00 VCP1B03 VCP1B02 VCP1B01 VCP1B00
7
6
5
4
3
2
1
0
VCP2B03 VCP2B02 VCP2B01 VCP2B00 VCP3B03 VCP3B02 VCP3B01 VCP3B00

CYCB0U
18001AH

15
14
13
12
11
10
9
8
VCP4B03 VCP4B02 VCP4B01 VCP4B00 VCP5B03 VCP5B02 VCP5B01 VCP5B00
7
6
5
4
3
2
1
0
VCP6B03 VCP6B02 VCP6B01 VCP6B00 VCP7B03 VCP7B02 VCP7B01 VCP7B00

GA

Co

nfi

de

CYCA0L
180010H

15
14
13
12
11
10
9
8
VCP0A03 VCP0A02 VCP0A01 VCP0A00 VCP1A03 VCP1A02 VCP1A01 VCP1A00
7
6
5
4
3
2
1
0
VCP2A03 VCP2A02 VCP2A01 VCP2A00 VCP3A03 VCP3A02 VCP3A01 VCP3A00

15
14
13
12
11
10
9
8
VCP0B13 VCP0B12 VCP0B11 VCP0B10 VCP1B13 VCP1B12 VCP1B11 VCP1B10
7
6
5
4
3
2
1
0
VCP2B13 VCP2B12 VCP2B11 VCP2B10 VCP3B13 VCP3B12 VCP3B11 VCP3B10CYCB1U
18001EH

15
14
13
12
11
10
9
8
VCP4B13 VCP4B12 VCP4B11 VCP4B10 VCP5B13 VCP5B12 VCP5B11 VCP5B10
7
6
5
4
3
2
1
0
VCP6B13 VCP6B12 VCP6B11 VCP6B10 VCP7B13 VCP7B12 VCP7B11 VCP7B10SECYCB1L
18001CHST-58-R2

39

Table 3.5 Access command
Access Command Value
VCPnxx3
VCPnxx2

VCPnxx1

VCPnxx0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

de

NBG0 Pattern Name Data Read
NBG1 Pattern Name Data Read
NBG2 Pattern Name Data Read
NBG3 Pattern Name Data Read
NBG0 Character Pattern Data Read
NBG1 Character Pattern Data Read
NBG2 Character Pattern Data Read
NBG3 Character Pattern Data Read
Setting not allowed
Setting not allowed
Setting not allowed
Setting not allowed

NBG0 Vertical Cell Scroll Table Data Read
NBG1 Vertical Cell Scroll Table Data Read

CPU Read/Write
No Access

nfi

Note:

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

VRAM Accessnti
al

Table 3.5 shows access command that corresponds to the content of the VRAM
access during 1 cycle.

n: 0 to 7 (corresponds to access timing T0 to T7)
xx: A0, A1, B0, B1 (corresponds to VRAM-A0, VRAM-A1, VRAM-B0, VRAM-B1)

Co

VRAM cycle pattern (for VRAM-A0) bit: VRAM cycle pattern bit (VCP0A00 to VCP0A03,
VCP1A00 to VCP1A03, VCP2A00 to VCP2A03, VCP3A00 to VCP3A03, VCP4A00 to VCP4A03,
VCP5A00 to VCP5A03, VCP6A00 to VCP6A03, VCP7A00 to VCP7A03)

SE

GA

Sets the access command of VRAM access that performs in VRAM-A0 (or VRAM-A)
timing T0 to T7.

40

180010H
180010H
180010H
180010H
180012H
180012H
180012H
180012H

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3

VRAM-A0 (or VRAM-A) Timing for T0
VRAM-A0 (or VRAM-A) Timing for T1
VRAM-A0 (or VRAM-A) Timing for T2
VRAM-A0 (or VRAM-A) Timing for T3
VRAM-A0 (or VRAM-A) Timing for T4
VRAM-A0 (or VRAM-A) Timing for T5
VRAM-A0 (or VRAM-A) Timing for T6
VRAM-A0 (or VRAM-A) Timing for T7

ntial

VCP0A00~VCP0A03
VCP1A00~VCP1A03
VCP2A00~VCP2A03
VCP3A00~VCP3A03
VCP4A00~VCP4A03
VCP5A00~VCP5A03
VCP6A00~VCP6A03
VCP7A00~VCP7A03

VRAM cycle pattern (for VRAM-A1) bit: VRAM cycle pattern bit (VCP0A10 to VCP0A13,
VCP1A10 to VCP1A13, VCP2A10 to VCP2A13, VCP3A10 to VCP3A13, VCP4A10 to VCP4A13,
VCP5A10 to VCP5A13, VCP6A10 to VCP6A13, VCP7A10 to VCP7A13)

180014H
180014H
180014H
180014H
180016H
180016H
180016H
180016H

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3

VRAM-A1 Timing for T0
VRAM-A1 Timing for T1
VRAM-A1 Timing for T2
VRAM-A1 Timing for T3
VRAM-A1 Timing for T4
VRAM-A1 Timing for T5
VRAM-A1 Timing for T6
VRAM-A1 Timing for T7

nfi

VCP0A10~VCP0A13
VCP1A10~VCP1A13
VCP2A10~VCP2A13
VCP3A10~VCP3A13
VCP4A10~VCP4A13
VCP5A10~VCP5A13
VCP6A10~VCP6A13
VCP7A10~VCP7A13

deSets the access command of the VRAM access that performs in VRAM-A1 timing T0
to T7.

When VRAM is not partitioned in two, the value of this register is ignored.

Co

VRAM cycle pattern (for VRAM-B0) bit: VRAM cycle pattern bit (VCP0B00 to VCP0B03,
VCP1B00 to VCP1B03, VCP2B00 to VCP2B03, VCP3B00 to VCP3B03, VCP4B00 to VCP4B03,
VCP5B00 to VCP5B03, VCP6B00 to VCP6B03, VCP7B00 to VCP7B03)

SE

GA

Sets the access command of VRAM access that performs in VRAM-B0 (or VRAM-B)
timing T0 to T7.

ST-58-R2

41

180018H
180018H
180018H
180018H
18001AH
18001AH
18001AH
18001AH

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3

VRAM-B0 (or VRAM-B) Timing for T0
VRAM-B0 (or VRAM-B) Timing for T1
VRAM-B0 (or VRAM-B) Timing for T2
VRAM-B0 (or VRAM-B) Timing for T3
VRAM-B0 (or VRAM-B) Timing for T4
VRAM-B0 (or VRAM-B) Timing for T5
VRAM-B0 (or VRAM-B) Timing for T6
VRAM-B0 (or VRAM-B) Timing for T7

ntial

VCP0B00~VCP0B03
VCP1B00~VCP1B03
VCP2B00~VCP2B03
VCP3B00~VCP3B03
VCP4B00~VCP4B03
VCP5B00~VCP5B03
VCP6B00~VCP6B03
VCP7B00~VCP7B03

VRAM cycle pattern (for VRAM-B1) bit: VRAM cycle pattern bit (VCP0B10 to VCP0B13,
VCP1B10 to VCP1B13, VCP2B10 to VCP2B13, VCP3B10 to VCP3B13, VCP4B10 to VCP4B13,
VCP5B10 to VCP5B13, VCP6B10 to VCP6B13, VCP7B10 to VCP7B13).

18001CH
18001CH
18001CH
18001CH
18001EH
18001EH
18001EH
18001EH

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3

VRAM-B1 Timing for T0
VRAM-B1 Timing for T1
VRAM-B1 Timing for T2
VRAM-B1 Timing for T3
VRAM-B1 Timing for T4
VRAM-B1 Timing for T5
VRAM-B1 Timing for T6
VRAM-B1 Timing for T7

nfi

VCP0B10~VCP0B13
VCP1B10~VCP1B13
VCP2B10~VCP2B13
VCP3B10~VCP3B13
VCP4B10~VCP4B13
VCP5B10~VCP5B13
VCP6B10~VCP6B13
VCP7B10~VCP7B13

deSets the access command of VRAM access that performs in VRAM-B1 timing T0 to
T7.

SE

GA

Co

When VRAM is not partitioned into two areas, the value of this register is ignored.

42

nti
al

3.4 Color RAM Mode
With 32 Kbits (2 Kword) of color RAM, color data that is stored is used for all scroll
screens and palette format sprites. The color data selects and stores either RGB-5 bit(15 bit data) or RGB-8 bit (24 bit data). In addition, when dividing it into 16K bits
(1K word) and storing various color data of the same type, the expansion color
calculation function can also be used. There are three methods for storing color datain color RAM:de(1) Mode 0: RGB in each of 5 bits for a total of 15 bits, 1024 color settings(2) Mode 1: RGB in each of 5 bits for a total of 15 bits, 2048 color settings(3) Mode 2: RGB in each of 8 bits for a total of 24 bits, 1024 color settings

SE

GA

Co

nfi

Because color data must be set to RGB-8 bit when it is output, a 0 will be added to
the lowest 3 bits if RGB-5 bit color data is stored in the color RAM, . When thespecial color calculation mode is set to mode 3, the most significant bit of color RAM
data becomes the color calculation enable bit. See “12.3 Special Color Calculation
Function” about the special color calculation mode.

ST-58-R2

43

Dat a se t for RG B 5-b ti
14

8
7
6
5
5 Bit G re en Dat a

4

3
2
1
0
5 Bit Re d Data

Blue Data O ut put

5 Bit Blue Dat a00Gree n Da ta Out put

5 Bit Green Da ta00

Red Dat a Outpu t

5 Bit Red DataCC

Colo r Da ta

13 12 11 10
5 Bit Blue Dat a

9

0

0

de

Bit 15ntialFigure 3.9 shows the color data configuration of the color RAM.

0

0

0

Dat a se t for RG B 8-b ti
Bit 31
Co lor Dat a

28

27

30

29

26

25

24

23

22 21 20 19
8 Bit Blue Dat a14

13 12 11 10
8 Bit Gre en Dat a

9

8

7

6

CC

Bit 15

18

17

16

5
4
3
2
8 Bit Red Dat a

1

0

Co

Col or Datanfi

No te: The MSB CC is ena bl e bi t when spe cia l col or ca lcul at ion mode is mo de 3.

Blue Dat a O ut put

8 Bit Blue Dat a

Gree n Data Out put

8 Bit Gree n Dat a

Red Dat a Outpu t

8 Bit Red Dat a

GA

Not e: The MSB CC is en abl e bi t wh en spe ci al co lo r cal cul ation mo de is mode 3.
Sha ded bit ar ea s are ign or ed .

SE

Figure 3.9 Color data configuration on the color RAM

44

nti
al

Color data written to the color RAM is illustrated in Figure 3.10.
Bit 0
100000H

1K Word
16 bit X 1024 Colors

Same Color Data

16 bit X 1024 Colors

1K Word

100FFFH
Bit 1
100000H

100FFFH

Bit 2

nfi

100000H

32 bit X 1024 Colors
100FFFH

2K Wordde

16 bit X 2048 Colors

2K WordCo

Figure 3.10 Color Data of the Color RAM

RAM Control Register

The RAM control register selects the bank partitions of the VRAM, the purpose ofusing the rotation scroll screen of VRAM, and the color RAM mode. It is a read/
write 16-bit register and is at the 18000EH address. Also, because the value iscleared to 0, it must be set after the power is turned on or reset.
15
14
13
12
11
10
9
8
CRKTE
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00

GA

RAMCTL
18000EH

Color RAM Coefficient Table Enable Bit (CRKTE), Bit 15

SE

See “6.4 Coefficient Table Control.”

ST-58-R2

45

Color RAM mode bit (CRMD1, CRMD0), bits 13 and 12

nti
al

Selects the color RAM mode. See “3.4 Color RAM mode.”
Set the Color RAM mode to mode 1 when the CRKTE bit is 1. At that time, color
data can no longer be stored because the second half of the color RAM (100800H ~100FFFH) is used for the coefficient table data.
CRMD1

CRMD0

Mode

Process

0
0
1
1

0
1
0
1

0
1
2
-

RGB each 5 bits, 1024 color settings
RGB each 5 bits, 2048 color settings
RGB each 8 bits, 1024 color settings
Setting not allowedde

Saving color data to the color RAM must be done after thes bits have been set.
When mode 0 is set, data written to the first half of the color RAM will be written to
the second half at the same time.
VRAM mode bit (VRBMD and VRAMD), bits 9 and 8. (See “ 3.2 VRAM Bank Partition.”)Rotation data bank select bit: Data bank select bit (RDBSA01, RDBSA00, RDBSA11,
RDBSA10, RDBSB01, RDBSB00, RDBSB11, RDBSB10)

SE

GA

Co

nfi

Designates the use objective of the VRAM of the rotation scroll screen. This bit is
only in effect when the rotation scroll screen is displayed. (See “6.2 Rotation Scroll
Screen Display Control.”)

46

nti
al

Chapter 4 Scroll Screen

SE

GA

Co

nfi

de

4.1 Screen Display Control .............................................................................. 48
Screen Display Enable Register ........................................................... 48
4.2 Scroll Screen Structure .............................................................................. 50
Cell Format ........................................................................................... 50
Bit Map Format ..................................................................................... 52
4.3 Cell ............................................................................................................. 53
Character Color Number ...................................................................... 53
Cell Data Configuration ........................................................................ 53
Transparent Dots .................................................................................. 57
RGB Format Dot Data .......................................................................... 58
4.4 Character Patterns ..................................................................................... 59
Character Size and Cell Arrangement .................................................. 59
4.5 Character Control Register ........................................................................ 60
4.6 Pattern Name Table (Page) ........................................................................ 64
Pattern Name Table Data Configuration ............................................... 64
Pattern Name Data ............................................................................... 69
Character Number ................................................................................ 74
Palette Number..................................................................................... 74
Special Function Bit .............................................................................. 74
Reverse (Flip) Function Bit ................................................................... 75
Pattern Name Control Register ............................................................ 76
4.7 Planes ........................................................................................................ 79
Plane Size ............................................................................................ 79
Plane Size Register .............................................................................. 80
4.8 Maps ........................................................................................................... 82
Map Selection Register ........................................................................ 82
Map Size ............................................................................................... 84
Map Offset Register .............................................................................. 85
Normal Scroll Screen Map Register ..................................................... 87
Rotation Scroll Surface Map Register .................................................. 89
4.9 Bit Maps ..................................................................................................... 93
Bit Map Size ......................................................................................... 93
Bit Map Color Number .......................................................................... 93
Bit Map Pattern ..................................................................................... 95
Bit Map Palatte Number ..................................................................... 111
Special Function Bit ............................................................................ 111
Bit Map Palatte Number Register ....................................................... 112
4.10 Display Area ........................................................................................... 114
Display Area ....................................................................................... 114
Screen-Over Process ......................................................................... 115
Display-Over Pattern Name ............................................................... 115
Screen-Over Pattern Name Register ................................................. 116
4.11 Mosaic Process ...................................................................................... 117
Mosaic Control Register ..................................................................... 118

ST-58-R2

47

nti
al

4.1 Screen Display Control
The scroll screen selects screens not displayed by controlling VRAM access used in
the display of each screen, and can also indicate whether to invalidate the dot color
code (transparency code) in each screen, which are the transparent dots of the screen
being displayed.
Screen Display Enable Register

BGON
180020H

15
~
7
~

14
~
6
~

13
~
5
R1ON

12
R0TPON
4
R0ON

de

The screen display enable register controls the screen display and transparency code.
With a write-only 16-bit register, its address is 180020H. Because the value of theregister is cleared to 0 after power on or reset, the value must be set.
11
N3TPON
3
N3ON

10
N2TPON
2N2ON

9N1TPON
1
N1ON

8
N0TPON0
N0ON

nfi

Transparent display enable bit (N0TPON, N1TPON, N2TPON, N3TPON, R0TPON)

Designates whether to nullify the transparency code. For more specifics about thetransparency code see Transparent Dots in section “4.3 Cell.”
180020H
180020H
180020H
180020H
180020H

Bit 8
Bit 9
Bit 10
Bit 11
Bit 12Co

N0TPONN1TPONN2TPON
N3TPONR0TPONFor NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0xxTPON

Process01

Validates transparency code (transparency code dots become transparent)
Invalidates transparency code (transparency code dots are displayed according to davalues)SE

GA

Note: N0, N1, N2, N3, or R0 is entered into bit name for xx.

48

Screen display enable bit: On bit (N0ON, N1ON, N2ON, N3ON, R0ON, R1ON)

Designates whether to display each scroll screen.
180020H
180020H
180020H
180020H
180020H

Bit 8
Bit 9
Bit 10
Bit 11
Bit 12For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0nti
al

N0TPONN1TPONN2TPON
N3TPONR0TPONxxTPON

Process01

Validates transparency code (transparency code dots become transparent)
Invalidates transparency code (transparency code dots are displayed according to davalues)deNote: N0, N1, N2, N3, R0, or R1 is entered into bit name xx.

When the screen access command (which has a 0 bit) is set in the VRAM cycle pattern register, the access command is ignored and the VRAM access for displaying
the screen will not be performed.
When R0ON is 0, do not set R1ON at 1.

nfi

When both R0ON and R1ON are 1, the normal scroll screen can no longer be displayed. At this time, VRAM-B0 is fixed in RAM used for RBG1 character pattern
tables; and VRAM-B1 is fixed in RAM used for RBG1 pattern name tables.

SE

GA

Co

When a specific screens can no longer be displayed by register settings, the screen bit
should be set to 0. For example, when both R0ON and R1ON are 1, set the N0ON,
N1ON, N2ON, N3ON bits at 0. See section “6.2 Rotation Scroll Surface Display
Control” for more about rotation scroll surfaces.

ST-58-R2

49

4.2

Scroll Screen Structurential

The scroll screen has two screen formats, the cell format and the bit map format.
Cell Format

Pag e

1 H cel lX
1 V cel lor
2 H cel lX
2 V cel l

32 H X 32 Vor
64 H X 64 V
ch ar act er pa ttern(64 H X 64 V ce l )Plane

1 H pa ge
X
1 V pa geor
2 H pa ge
X
1 V pa geor
2 H pa ge
X
2 V pa geCo

8 H do t
X
8 V dot

Cha ra ct er
Pat ter n

Map

nfi

Cell

de

The cell format scroll screen is composed of picture pattern “cells” that are 8 H dotsby 8 V dots; cells are arranged in 1 H X 1 V or 2 H X 2 V to form “character patterns.” A “page” is an arrangement of character patterns in 32 H X 32 V or 64 H X 64
V. A “plane” is an arrangement of pages 1 H X 1 V, 2 H X 1 V, or 2 H X 2 V. A
“map” is an arrangement of planes 2 H X 2 V (for normal scroll screens), or 4 H X 4
V (for rotation scroll surface). Figure 4.1 shows the cell format configuration of thescroll screen.

2 H pl an eX
2 V pl an e(n or mal scr ol l scr ee n)or
4 H pl an eX
4 V pl an e(r ot at ion scr ol l scr ee n)

Figure 4.1 Scroll screen configuration of the cell format

SEGA

Dot color data stored as character pattern tables in VRAM becomes cell data. Colordata is composed of 4, 8, 16, or 32-bit character color. Character pattern data is celldata arranged in one or four pieces. Page data is character pattern name data (address of character pattern table) stored as a pattern name table. Page data arranged
in one, two, or four pieces is a plane. The map selects the lead address of the patternname table in the map register and map offset register. Figure 4.2 shows the configuration of a cell format of the scroll screen and corresponding data settings.

50

Map Register + Ma p Offse t Reg is ter

Map

Plane A

Plane BTo p Address o f Pla ne C PNTTo p Addre ss of Plane D PN T
Plane CPla ne D
PNT : Patte rn N ame Ta ble

Pa ttern Name Ta ble (V R AM)

Pla neC P0 Pa t e rn N a me Da ta

Page 1Page 0de

Pag e 0nti
al

To p Addre ss of Pla n e A PN T
To p A d dre ss of Plane B PNTCP 10 2 3 Pa tter n Na me D at a

Pag e 2

C P0 Pat te rn N a me D a ta

Page 3

Page 1

Plane A
Plane Size R egist e r

Page

C P1 0 23 Pa t e rn N a me Da ta

CP0

CP31

CP99 2

CP10 23

CP 0 P at ter n N am e D at a

Page 2Pla n e Sizenfi

C P1 02 3 Pa t e rn N a me Da ta
C P0 Pat te rn N a me D a ta

Page 3

C P1 02 3 P at ter n N am e D at a

Patte rn N ame C ontrol Register
Pattern Na me D ata Size

C haract er Pa ttern

Co

CP : Character Pattern

C haract er Pat tern Ta ble (VRAM )D ot 0 C olor D ata

Cell 0 Cell 1
Cell 2 Cell 3

C ell 0Dot 63 Co lo r Da ta
Dot 0 Color Dat a
C ell 1GA

C haract er C ontrol RegisterSE

C hara ct e r Size

Cha ra cter
Patte rn 0

Dot 63 Co lo r Da ta
Ce l

Dot 0 Color Dat a

Dot 0

Do t 7

Dot 56

Do t 63

C ell 2
Dot 63 Co lo r Da ta
Dot 0 Color Dat a
C ell 3
Dot 63 Co lo r Da ta

C haracter C ontrol Register
Ch ara cter Co lo r Co unt

N ote: Character pattern and pla ne siz e vary depen din g on the re g is ter setting; ma p siz e varie sd epending on the scro l scre en type. T he above f ig u re is an exam ple of the ca se w hen cha ra cterp attern is 2 H cells X 2 V ce l s. Th e plane is 2 H p ages X 2 V p ages and norm al sc roll scre en(2 H planes X 2 V plane s) .

Figure 4.2

ST-58-R2

Scroll screen configuration of cell format and corresponding data settings.

51

Bit Map Formatntial

The scroll screen of the bit map format is composed of a bit map pattern 512 H (or1024) dots and 256 V (or 512) dots. When a screen is displayed by the bit map format, the size of the bit map must be set in the register and the set size of the bit map
pattern must be stored in VRAM. Figure 4.3 shows the scroll screen configuration of
the bit map format. Figure 4.4 shows the relationship of the register and the scroll
screen of the bit map format.
Bitmapnfi

512 H X 256 V dot s
512 H X 512 V dot s
102 4 H X 25 6 Vdo ts
or1024 H X 51 2 V do ts

de1 Do tMap Offset Re gi st er

VRAM

Map Offset

Dot 0 Col or Data

Bit ma p

Cha ra ct er Con trol Reg ist er
Cha ra ct er Colo r Coun tGABitmap Shap eCo

Figure 4.3 Scroll screen configuration of the bit map format

Cha ra ct er Cont rol Regi st er

SE

Bitma p Size

Figure 4.4

52

Relationship of bit map format scroll screen and data settings

4.3

Cell

nti
al

The cell is a picture pattern 8 H dots by 8 V dots, and is stored in VRAM. The character color count (number of colors per one cell) can be selected from among 16, 256,
2048, 32,768, or 16,777,216 colors. The amount of RAM required in the size of each
dot color data and in data of one cell changes according to the color count.
Character Color Number

deThere are two color formats for displaying characters: the palette format and the
RGB format. The palette format treats display color data as color RAM address data
selected by the dot color code within cell data, and palette number within patternname data. The RGB format treats cell data as display color data. Table 4.1 shows
the character color count and the number of bits per dot at that time in the various
color formats.
Table 4.1 Character color count and dot data size

Character Color Count

Bit Count for 1 Dot

16 colors
256 colors
2048 colors
32,768 colors
16,770,000 colors

4 bits8 bits
16 bits (Only use lower 11 bits)
16 bits
32 bits (Only use MSB and lower 24 bits)

nfi

Color Format

Palette Format
RGB Format

Co

Note: In color RAM modes 0 and 2, 2048-color becomes 1024-color.

Cell Data Configuration

The data configuration of each cell stored in a character pattern table changes according to the bit count of one dot. The boundary when stored in VRAM is 20H andhas no relationship to the bit count of one dot. Cell data configuration is shown in
Table 4.2 and Figure 4.5.

GA

Table 4.2 Cell Data Configuration
Cell Data

Boundary

4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot

32 bytes/cell64 bytes/cell
128 bytes/cell
256 bytes/cell

20H byte
20H byte
20H byte
20H byteSE

Bit Count for 1 Dot

ST-58-R2

53

Cha ra ct er Pat ter n Ta bl e (V RA M)
11

10
9
8
Dot 0- 1 Da ta+02HDo t 0-4 Dat a

Dot 0-5 Dat a

Dot 0- 6 Da ta

Dot 0- 7 Da ta+1E H

Do t 7-4 Dat a

Dot 7- 5 Da ta

Do t 7-6 Dat a

Dot 7- 7 Da ta

Dot 0

1

2
+01

1

+04

+05

2

+08

+09

3

+ 0C

+ 0D

4

+10

+11

5

+14

+15

6
7

6
5
4
Dot 0- 2 Da ta

4

5
+02

3

2
1
0
Dot 0- 3 Da ta

6

7

+03

+06

+07

+0A

+0B

+0E

+0F

+12

+13

+16

+17

Cel l

Co

+00

Dot 0

3

7

de

+00H

14 13 12
Dot 0- 0 Dat anfi

bit 15ntial(1) 4 bi ts/ dot (32 byt es/ cel l)

+18

+19

+1A

+1B

+ 1C

+ 1D

+1E

+1F

GA

Not e 1: The up pe r le ft not at ion in the cel l is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Num be rs in the cel ls ar e VRAM addr esses (Hexa de cim al ) of do t (2do ts) da ta, wit h VRA M ad dr ess of dot 0- 0, 0- 1 dat a as theref ere nce .

SE

Figure 4.5 Data configuration of cells by character color count

54

nti
al

(2) 8 bi ts/ dot (64 byt es/ cel l)

Cha ra ct er Pat ter n Ta bl e (V RA M)

+00H

14

13 12 11 10
Dot 0- 0 Dat a+02H

Dot 0- 2 Da ta+3E H

Dot 7- 6 Da ta

Dot 0

9

8

7

6

5

4
3
2
1
Dot 0- 1 Dat a

0

Do t 0-3 Dat a

Dot 7- 7 Dat a

1

2

de

Bit 15

3

4

5

6

7

+00 +01 +02 +03 +04 +05 +06 +07

Dot 0+08 +09 +0A +0B +0C +0D +0E +0F

2+10 +11 +12 +13 +14 +15 +16 +17

3+18 +19 +1A +1B +1C +1D +1E +1F

4+20 +21 +22 +23 +24 +25 +26 +27

5+28 +29 +2A +2B +2C +2D +2E +2F

Cel l

Co

nfi

1

6

+30 +31 +32 +33 +34 +35 +36 +37

7+38 +39 +3A +3B + 3C + 3D +3E +3F

GA

Not e 1: The uppe r lef t no tat ion in the ce l is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Num ber s in the cel ls ar e VRAM ad dr esse s (Hexad eci mal ) of do t
da ta, with VRAM ad dr ess of dot 0- 0 dat a as the ref er en ce.

SE

Figure 4.5 Data configuration of cells by character color count (continued)

ST-58-R2

55

Cha ra ct er Pat ter n Ta bl e (V RA M)
14

13

12

11

8
7
6
Dot 0- 0 Dat a+02H

Dot 0- 1 Dat a+7 EH

Dot 7- 7 Dat a

Dot 0

10

1

9

2

3

4

5

5

6

4

3

2

1

0

7

+00 +02 +04 +06 +08 +0A +0C +0E

Dot 0+10 +12 +14 +16 +18 +1A + 1C +1E

2+20 +22 +24 +26 +28 +2A + 2C +2E

3+30 +32 +34 +36 +38 +3A + 3C +3E

4+40 +42 +44 +46 +48 +4A + 4C +4E

5+50 +52 +54 +56 +58 +5A + 5C +5E

6+60 +62 +64 +66 +68 +6A + 6C +6E

7+70 +72 +74 +76 +78 +7A +7C +7E

nfi

1

Cel l

Co

Bit 15

de

+00H

nti
al

(3) 16 bits/ do t (1 28 byt es/ ce l )GA

Not e 1: The upp er lef t no tat io n in the ce ll is dot 0- 0; to the righ t ar e do t 0-1 ,dot 0- 2, dot 0- 3, ...
Not e 2: Numb er s in the cel ls are VRAM add re sses (Hexa de cim al) of dot
dat a, with VRAM ad dr ess of dot 0- 0 da ta as the re fer en ce.

SE

Figure 4.5 Data configuration of cells by character color count (continued)

56

(4) 32 bits/ do t (2 56 byt es/ ce l )

14

13

12

+00H

11 10
9
8
7
6
5
4
Dot 0- 0 Da ta (M ost si gn fi ica nt wor d)+02H

Dot 0- 0 Da ta (L ea st si gn ificant wor d)+0 4H

Dot 0- 1 Da ta (M ost si gn fi ica nt wor d)+FCH

Dot 7- 7 Da ta (M ost si gn fi ica nt wor d)+F EH

Dot 7- 7 Da ta (L ea st si gn ificant wor d)

Do t 0

1

2

3

2

1

0

de

BIT 15nti
alCha ra ct er Pat ter n Ta bl e (V RA M)

3

4

5

6

7

+00 +04 +08 +0C +10 +14 +18 +1C

1+20 +24 +28 + 2C +30 +34 +38 +3C

2+40 +44 +48 + 4C +50 +54 +58 +5C

3+60 +64 +68 + 6C +70 +74 +78 +7C

4+80 +84 +88 + 8C +90 +94 +98 +9C

nfi

Do t 0Cel l

Co

5 +A0 +A4 +A8 +AC +B0 +B4 +B8 +BC
6 +C0 + C4 + C8 +CC + D0 +D4 +D8 +D C
7

+E0 +E4 +E8 + EC +F 0 +F 4 +F 8 +F C

GA

Not e 1: The uppe r lef t no tat io n in the ce l is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Numb er s in the cel ls ar e VRAM addr esses (Hexadeci mal ) of do t
da ta (M SW), with VRAM ad dr ess of dot 0- 0 da ta (MSW) as theref ere nce .

Figure 4.5 Data configuration of cells by character color count (continued)

Transparent DotsSE

Dot color code, which are transparent dots (transparency code), changes according
to the color format. When the color format is the palette format, the transparent dot
applies when all bits per one dot is 0; when the RGB format, the transparent dot
applies when the most significant bit of the dot data is 0.
When in the palette format, lead color data of the palette corresponds to the transparency code; therefore, it normally cannot be used. If the transparency code isnullified, this color data can be used. Control is done by the screen display enableregister. Table 4.3 shows the transparent dot data values.

ST-58-R2

57

Table 4.3 Transparent dot data values

Palette Format
RGB Format

Character ColorCount

Bit Count for 1 Dot

Transparency Code16 colors
256 colors
2048 colors
32,768 colors
16,770,000 colors

4 bits/dot
8 bits/dot
16 bits/dot
16 bits/dot
32 bits/dot

0H (4 bit)
00H (8 bit)
000H (lower 11 bits)
MSB (bit 15) is 0
MSB (bit 31) is 0ntialColor Format

RGB Format Dot Data

nfi

de

When the color format is the RGB format, the character color count can be selectedfrom two groups: 32,768 colors and 16,770,000 colors. 16,770,000 colors are designated by RGB 8-bit; but 32,768 colors designate the higher 5 bits within RGB 8-bit,
and the lower 3 bits are set to 0. The transparency bit designates whether it is atransparent dot. The most significant bit is a transparent dot when 0. In the screen
display enable register, when the transparency code is indicated as invalid, thetransparent bit is ignored. Figure 4.6 shows the dot data of the RGB format.

Wh en 32 76 8 Colo rs
147

13 12 11
Blue Dat a

10

6

3

5

Wh en 16 ,770, 00 0 Col ors
Bit 32Tr an spa re nt
Bit

8

7

6

5

7

6

5

4

3

7

4

13

12

11

7

6

5

2

1

0

6

5

4

3

10

9

8

7

6

5

6

5

4

3

2

1

0

7

6

5

2

1

0

4
3
2
Red Dat a

1

0

1

0

GA

Not e: Shade d bi ts are ign or ed

SE

Figure 4.6 RGB format dot data

58

3

Re d Da ta

Gre en Dat a7

4

Gree n Da ta

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Blue Da ta

14

Bit 154

9Co

Bit 15Tra nsp ar en t
Bit

4

3

3

2

4.4 Character PatternsntialCharacter patterns are perfect squares composed of 1 or 4 cells; the size is specified
in their respective registers.
Character Size and Cell Arrangement

Cha ra ct er Pat ter n Ta bl e

When 1 H cel l X 1 V cel l

Cell Data 0

Ce ll Da ta 0

8 dot

nfi

Select ed
Cha ra ct er
Pattern
Addr essHea de r
Addr essdeWhen the character pattern is composed of four cells, the data of a cell that is used in
the same character pattern must be linked to and stored in a character pattern table.
The relationship of cell arrangement by character size (cell number of character
pattern) and character pattern table is shown in Figure 4.7.

Ce ll Da ta 1

8 dot

When 2 H cel ls X 2 V cel ls

Co

Cel l Dat a 2

Ce ll Da ta 0

Cel l Dat a 1

16 do tCel l Dat a 3

GA

Cell Data 4

Cel l Dat a 2

Cel l Dat a 3

16 do tSE

Figure 4.7 Cell Arrangement by Character Size

ST-58-R2

59

4.5

Character Control RegisterntialThe character control register selects cell and bit map formats, the number of character (bit map) colors, and the size of the character pattern or bit map. This register isa write only 16-bit register located in addresses 180028H to 18002AH. Because thevalue of the register is cleared to 0 after the power is turned on or reset, the value
must be set.
15
~
7
~

14
13
12
11
10
9
~
N1CHCN1 N1CHCN0 N1BMSZ1 N1BMSZ0 N1BMEN
6
5
4
3
2
1
N0CHCN2 N0CHCN1 N0CHCN0 N0BMSZ1 N0BMSZ0 N0BMEN

CHCTLB
18002AH

15
~
7
~

14
13
12
R0CHCN2 R0CHCN1 R0CHCN0654~N3CHCN N3CHSZdeCHCTLA
180028H

11
~
3
~

10
R0BMSZ
2~

9
R0BMEN
1
N2CHCN

8
N1CHSZ0N0CHSZ
8
R0CHSZ
0N2CHSZ

nfi

Character color number bit (N0CHCN2 to N0CHCN0, N1CHCN1, N1CHCN0, N2CHCN, N3CHCN,
R0CHCN2 to R0CHCN0)

Designates the character color count of each screen, and the bit map color countwhen displaying by the bit map format.
180028H
180028H
18002AH
18002AH
18002AH

N0CHCN2

N0CHCN0

0
0
0
0
1

0
0
1
1
0

1
1
1

0
1
1

1
0
1

60

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0

Exclusive
Monitor16 colors
16 colors
16 colors
256 colors
256 colors
256 colors
2048 colors
2048 colors
2048 colors
32,786 colors 32,786 colors 32,786 colors
16,770,000
Setting not
Setting notcolorsallowedallowedSetting not allowed (Please do not set.)
Setting not allowed (Please do not set.)
Setting not allowed (Please do not set.)

Cannot be displayed by the exclusive monitor mode when used as RBG1.

SE

Note:

0
1
0
1
0

TV Screen Mode
NormalHi-ResGA

N0CHCN1

Bit 6~4
Bit 13,12
Bit 1
Bit 5
Bit 14~12Co

N0CHCN2~N0CHCN0
N1CHCN1,N1CHCN0
N2CHCN
N3CHCNR0CHCN2~R0CHCN0

Color
FormatPalette Format
Palette Format
Palette Format

RGB Format
RGB Format

N1CHCN0

0
0
1
1

0
1
0
1

16 colors
256 colors
2048 colors
32,786 colors

16 colors
256 colors
2048 colors
32,786 colors

16 colors
256 colors
2048 colors
32,786 colors

Palette Format
Palette Format
Palette Format
RGB Format

When used as EXBG, and when the set values are N1CHCN1 = 1, N1CHCN0 = 1 there are
16,770,000 colors

NnCHCN0TV Screen Mode
NormalHi-Res01

16 colors
256 colors

Note:

Color Format
Exclusive
Monitor

2 or 3 is entered in bit name for n.

R0CHCN2

R0CHCN1

R0CHCN0

1
1
1

0
1
1

1
0
1

Exclusive
MonitorColor
Format16 colors
16 colors
Cannot Display Palette Format
256 colors
256 colors
Cannot Display Palette Format
2048 colors
2048 colors
Cannot Display Palette Format
32,786 colors 32,786 colors Cannot Display RGB Format
16,770,000
Setting not
Cannot Display RGB Format
colorsallowedSetting not allowed (Please do not set.)
Setting not allowed (Please do not set.)
Setting not allowed (Please do not set.)

nfi

0
1
0
1
0

Hi-ResPalette Format
Palette Format

Co

0
0
1
1
0

16 colors
256 colors

TV Screen Mode
Normal00001

16 colors
256 colors

Color Format

Exclusive
MonitordeNote:

TV Screen Mode
NormalHi-Resnti
al

N1CHCN1

SEGA

Depending on the color count of NBG0 and NBG1, the scroll screen that cannot be
displayed will appear. When NBG0 is set at 2048 or 32,768 colors, NBG2 can nolonger be displayed. When NBG0 is set at 16,770,000 colors, NBG1 to NBG3 can nolonger be displayed. When NBG1 is set at 2048 or 32,768 colors, NBG3 can no longer
be displayed.

ST-58-R2

61

Bit map size bit (N0BMSZ1, N0BMSZ0, N1BMSZ1, N1BMSZ0, R0BMSZ)

Designates the bit map size of each screen when display is in a bit map format.
180028H
180028H
18002AH

Bit 3,2
Bit 11,10
Bit 10NnBMSZ1

NnBMSZ0

Bitmap Size

0
0
1
1

0
1
0
1

512 H dots X 256 V dots
512 H dots X 512 V dots
1024 H dots X 256 V dots
1024 H dots X 512 V dots

ROBMSZ

Bitmap Size

01

512 H dots X 256 V dots
512 H dots X 512 V dots

Bit map enable bit (N0BMEN, N1BMEN, R0BMEN)de

Note: 0 or 1 is entered in bit name for n.

For NBG0
For NBG1
For RBG0nti
al

N0BMSZ1,N0BMSZ0N1BMSZ1,N1BMSZ0R0BMSZ

Designates whether to display the scroll screen in a bit map format.
180028H
180028H
18002AH

xxBMEN

Screen Display Format

01

Cell Format
Bitmap Format

Bit 1
Bit 9
Bit 9

SE

GA

Co

Note: N0, N1, or R0 is entered in bit name for xx.

62

For NBG0
For NBG1
For RBG0nfi

N0BMEN
N1BMEN
R0BMENCharacter size bit (N0CHSZ, N1CHSZ, N2CHSZ, N3CHSZ, R0CHSZ)

Designates the character size when the scroll screen is in a cell format.
180028H
180028H
18002AH
18002AH
18002AH

Bit 0
Bit 8
Bit 0
Bit 4
Bit 8

xxCHSZ

Character Pattern Size

01

1 H Cell X 1 V Cell
2 H Cells X 2 V Cells

SE

GA

Co

nfi

de

Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0nti
al

N0CHSZN1CHSZN2CHSZN3CHSZROCHSZ

ST-58-R2

63

4.6

Pattern Name Table (Page)nti
alPattern name table (or page) stores the method of arrangement when the character
pattern is in a square the size of a 64 X 64 cell in the VRAM. It also arranges patternname data in table form and stores it in VRAM. Pattern name data selects the leadaddress of the character pattern stored in VRAM and the control information foreach character pattern. Pattern name data in a pattern name table is in one-word or
two-word. When in one-word, auxiliary data of the least significant 10 bits of thepattern name control register is added to make up for insufficient bits.
Pattern Name Table Data ConfigurationdeThe boundary stored in VRAM and VRAM capacity required in a pattern name tableof 64 X 64 cells (1 page) change depending on the pattern name data size (wordcount) and character size. The capacity and data configuration of pattern nametables are shown in Table 4.4 and Figure 4.8.

Pattern Name Data
Size

Character Size

1 Word1 H Cell X 1 V Cell
2 H Cells X 2 V Cells
1 H Cell X 1 V Cell
2 H Cells X 2 V Cells

Contents of 1
Page

Boundary During
VRAM Storage

8192 Bytes
2048 Bytes
16,384 Bytes
4096 Bytes

2000H
800H
4000H
1000H

SE

GA

Co

2 Words

nfi

Table 4.4 Pattern name table capacity and page boundary of one page

64

nti
al

(1) Pat tern Nam e Dat a Size : 1 wor dChar act er Pat ter n Size : 1 H cel l X 1 V cel lPattern Nam e Ta bl e (V RA M)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

+00 02H

Char act er Patter n 0- 1 Pat ter n Na me Dat a+1F FEH

Char act er Pattern 63- 63 Patter n Nam e Data

+0080 +0082 +0084

Co

1

nfi

Ch ar act er
Pattern 0
1
2
Char act er+000 0 +0002 +000 4
Pat ter n 0

2

1

de

+00 00H

Cha ract er Pat ter n 0- 0 Pat ter n Name Dat a

61

62

0

63

+007A +007C +007E+00FA +00FC +00F E

Page

62

+1F0 0 +1F0 2 +1F0 4+1F7 A +1F7 C +1F7 E

63+1F8 0 +1F8 2 +1F8 4+1F FA +1FFC +1F FE

GA

No te 1: The up per -lef t no tat ion in the page is ch ar act er pa ttern 0- 0; to the right ar echar act er pat terns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr
addresses
esse s (He(Hexadecimal)
xad eci mal ) ofofpapattern
ttern naname
me da
data
ta
of ch ar act er pa ttern s, with VRAM addr ess of cha ra ct er pat ter n 0-0 pat ter n nam e
dat a as the ref er en ce.

SE

Figure 4.8 Data configuration of pattern name tables

ST-58-R2

65

Pattern Nam e Ta bl e (V RA M)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

Cha ract er Pat ter n 0- 0 Pat ter n Name Dat a+00 2HChar act er Pattern 0-1 Pattern Nam e Da ta+7FE H

Cha ra ct er Pat ter n 31- 31 Pattern Nam e Da ta

1

2

+000

+002

+004

+040

+042

+044

30

+780

+782

31

+7C0

+7C2

Co

Cha ra ct er
Pat ter n 0

1

1

0

29

30

31

+03A

+03C

+03E

+07A

+07C

+07E

nfi

Cha ract er
Pat ter n 0

2

de+00 0Hntial(2) Pat tern Nam e Dat a Size : 1 wor dChar act er Pat ter n Size : 2 H cel ls X 2 V cel ls

+784

+7BA

+7BC

+7BE

+7C4

+7FA

+7FC

+7FE

GA

No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar echa ra ct er pat ter ns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr
addresses
esse s (Hexad(Hexadecimal)
eci mal ) ofofpapattern
ttern nanamemeda ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as the re fere nce .

SE

Figure 4.8 Data configuration of pattern name tables (continued)

66

Pag e

nti
al

(3) Pat tern Nam e Dat a Size : 2 wor ds
Char act er Pat ter n Size : 1 H cel l X 1 V cel lPattern Nam e Ta bl e (V RA M)
Bit 1514 13 12 11 10
9
8
7
6
5
4
3
2
1
Ch ar act er Pattern 0- 0 Patter n Nam e Data (Most sig ni fica nt word )+000 2H

Cha ract er Pat ter n 0- 0 Pat ter n Name Dat a (Le ast si gni fican t word )+000 4H

Char act er Pat ter n 0- 1 Pat ter n Name Dat a (Mo st si gni fican t wor d)0de+000 0H

Char act er Patter n 63 -6 3 Pat ter n Name Dat a (Most si gni fican t wor d)+3F FEH

Char act er Pat ter n 63 -6 3 Pat ter n Name Dat a (Le ast sig ni fican t word )nfi+3F FCHCh ar act er
Pattern 0
1
2
Cha ra ct er+0000 +0004 +0008
Pat ter n 0 +0002+0006 +000A+00F4 +00F8 +00FC+00F6 +00FA +00FE+0100 +0104 +0108+0102 +0106 +010A+ 01 F 4 + 01 F 8 +01FC+ 01 F 6 +01FA +01FE

Co

1

61

62

63

Pag e

62

+3E00 +3E04 +3E0 8+3E02 +3E06 +3E0A+3EF 4 +3EF8 +3EFC+3EF 6 +3EFA +3EFE

63+3F0 0 + 3F 04 +3F0 8+3F0 2 + 3F 06 +3F0 A+3FF4 +3F F8 +3FF C+3FF6 +3FFA +3F FE

SEGA

No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar echa ra ct er pat ter ns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr
addresses
esse s (Hexad(Hexadecimal)
eci mal ) of ofpapattern
ttern nanamemeda ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as the re fere nce .

ST-58-R2

Figure 4.8 Data configuration of pattern name tables (continued)

67Pattern Nam e Ta bl e (V RA M)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

nti
al

(4) Pat tern Nam e Dat a Size : 2 wor ds
Char act er Pat ter n Size : 2 H cel ls X 2 V cel ls

10

Cha ra ct er Pat ter n 0-0 Pat tern Nam e Dat a (Mo st si gn ificant wor d)+0 02 HChar act er Patter n 0- 0 Pat ter n Na me Dat a (Le ast si gni fica nt wo rd )+0 04 H

Ch ar act er Pattern 0- 1 Pat ter n Na me Data (Most sig ni fica nt word )+FFCH

Ch ar act er Pattern 31 -3 1 Pat ter n Na me Dat a (Most si gni fican t word )+FFEH

Char act er Patter n 31 -3 1 Pat ter n Name Dat a (Le ast sig ni fica nt word )Ch ar act er
Pattern 0

2

+000
+002

+004
+006

+008
+00A

1

+080
+082

+084
+086

+088
+08A

30

+ F0 0+ F0 2+ F0 4+ F0 6

31

+F8 0
+F8 2

+ F8 4+ F8 6

Co

1

Char act er
Pat ter n 0

nfi

de

+0 00 H

29

30

31

+074
+076

+078
+07A

+07C
+07E

+ 0F 4+ 0F 6

+0F8
+0FA

+0F C
+0FE

Pag e

+ F0 8
+F0 A

+F7 4
+F7 6

+ F7 8
+F7 A

+F 7C
+F7 E

+F8 8
+F8 A

+F F4
+F F6

+FF8
+F FA

+F FC
+F FE

GA

No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar echa ra ct er pat ter ns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr
addresses
esse s (Hexad(Hexadecimal)
eci mal ) of ofpapattern
ttern nanamemeda ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as the re fere nce .

SE

Figure 4.8 Data configuration of pattern name tables (continued)

68Pattern Name Data

• Character number• Palette number• Special function bits
• Reverse function bits

nti
alPattern name data is composed of the following four fields, for a total of 26 bits.
15 bits
7 bits2 bits2 bitsde

The character number designates the address of the character pattern (VRAM).
The palette number designates the address of the palette (color RAM) used by thecharacter. The special function bits designate whether that character will use thespecial function. The reverse function bits designate whether to use the up-down
reverse or left-right reverse functions.

Co

nfi

The size of the pattern name data in the pattern name table can select either 1-wordor 2-word. Because all required pattern name data cannot be designated when 1
word is selected, it is supplemented by auxiliary data of the least significant 10 bitsof the pattern name control register. The composition of pattern name data changes
depending on character size, character number color, and the character number
auxiliary mode. The character number auxiliary mode designates the number of bits
per character number when the pattern name table size in the pattern name table is
1-word, and whether that character can use the reverse function. Table 4.5 shows thecharacter number auxiliary mode. Figure 4.9 shows the configuration of 2-wordpattern name data, and Figure 4.10 shows the configuration of 1 word pattern namedata.
Table 4.5 Character number auxiliary mode
Character Number
Auxiliary Mode

Process

0

Character number that can be specified in pattern name data is 10 bits.
Flip function can be specified in character units.
Character number that can be specified in pattern name data is 12 bits.
Flip function cannot be used.

GA

1

Flip
Function

Bit 31

30

29

28

PR

CC

14

13

12

11

14

13

12

11

VerticalSE

Horizontal
Bit 15

ST-58-R2

Special Function
27

26

25

24

22

21 20 19 18 17
Palette Number

16

6

5

4

3

2

1

0

10

9
8
7
6
5
Character Number

4

3

2

1

0

10

9

4

3

2

1

0

8

23

7

6

5

.

Note: Shaded bits are ignored
PR: Special Priority Bit
CC: Special Color Calculation Bit

Figure 4.9 Bit configuration when the pattern name data is 2 word69

Table 4.6 Bit configuration when pattern name data is 1 word.

*1
*2
*3
*4

Auxiliary
Mode
0
1
0
1
0
1
0
1

Character
Number
15*1
15*2
15*1
15*2
15*3
15*4
15*3
15*4
15

Designates bits 9 to 0 in pattern name data.
Designates bits 11 to 0 in pattern name data.
Designates bits 11 to 2 in pattern name data.
Designates bits 13 to 2 in pattern name data.

PaletteNumber
7
7
3
3
7
7
3
3
7

Special
Function
2
2
2
2
2
2
2
2
2

SE

GA

Co

nfi

Note:

Character
Color Count16
16
other than 16
other than 161616
other than 16
other than 16deCharacter
Size
1X1
1X1
1X1
1X1
2X2
2X2
2X2
2X2
2 Wordsnti
alTable 4.6 shows the bit configuration when the pattern name data is 1 word.

70

Flip Function

2
2
2
2
2

Pattern Nam e Data in Pattern Nam e Ta bl e
Bit 1514 13 12 11

10

9

8

Fli p Fun ct ion
7

Palet te Num be r
3

2

1

nti
al

(1) Ch ar act er Size : 1 H cel l X 1 V cel lChar act er Col or Coun t: 16 co lor sChar act er Num be r Suppl eme nt Mo de : Mod e 0

6

5

4

3

2

1

0

2

1

0

Cha ra ct er Num ber

0

9

8

7

6

5

4

3

Vert ica l
Hori zon tal
Supp le me nt al Dat a in Pat ter n Na me Con trol Reg ist er

PR

8

7
6
5
Pale tte No.

4

CC

6

14

5

4

3

2

1

0

Cha ra ct er Numb er
13

12

11

10

PR: Sp ecia l Pr io ri ty Bit
CC: Speci al Color Calc ula tion Bit

de

Bit 9
Spe ci al
Funct io n(2) Ch ar act er Size : 1 H cel l X 1 V cel lChar act er Col or Coun t: 16 co lor sChar act er Num be r Suppl eme nt Mo de : Mod e 1

Bit 15nfi

Pattern Nam e Data in Pattern Nam e Ta bl e
14 13 12 11

10

9

8

10

9

8

Palet te Num be r
3

2

1

0

7

6

5

4

3

2

1

0

3

2

1

0

Cha ra ct er Num ber

11

7

6

5

4

Not e: Bot h ve rt ica l an d hor izont al flip fun ct ion bi ts are se t to 0.
Supp le me nt al Dat a in Pat ter n Na me Con trol Reg ist er
8

7

6

5

4

Co

Bit 9

Speci alFun ct ion

PR

CC

3

2

1

0

Pale tte No.

Ch ar act er Num be r

6

14

5

4

13

PR: Speci al Pri ori ty Bit
CC: Sp ecia l Colo r Calcu latio n Bit

12Not e: Sha de d bit s ar e ig no re d(3) Ch ar act er Size : 1 H cel l X 1 V cel lChar act er Col or Coun t:16
Char act er Num be r Suppl eme nt Mo de : Mod e 0

GA

Pattern Nam e Data in Pattern Nam e Ta bl e
Bit 1514 13 12 11

10

9

8

Fl ip Funct io n
7

Palet te Num be r
6

5

6

5

4

3

2

1

0

2

1

0

Cha ra ct er Num ber

4

9

8

7

6

5

4

3

SE

Ver tical
Hor izon tal
Not e: Sha de d bit is ign or ed
Sup pl em ent al Da ta in Pat tern Nam e Cont ro l Regi st er

ST-58-R2

Bit 9Speci alFun ct ion

8

PR

CC

7

6

5

Pal ette No .

4

3

2

1

0

Ch ar act er Num be r
14

13

12

11

10

PR: Spec ial Prio rit y Bi t
C C: Speci al Color Calc ula tion Bi t

Not e: Sha de d bits ar e ign or ed

Figure 4.10 Configuration when pattern name data is one word71

Pattern Nam e Da ta in Pat tern Name Tab le
14 13 12
Bit 15Pal et te Numb er

11

6

11

5

4

10

9

8

7

6

5

4

3

Cha ra ct er Numb er
10

9

8

7

6

5

4

3

Not e: Bot h ver tica l and hor izo nt al flip fun ct ion bi ts are se t to 0.
Shad ed bi t is ig no re d
Suppl eme nt al Dat a in Pat t er n Na me Con trol Reg ist er
8
PR

7
6
5
Pal et te No.

CC

4
3
2
1
0
Cha ra ct er Num ber
14 13

12

No te: Shad ed bi ts ar e igno re d

3

2

1

10

9

0

2

1

0

PR: Sp ecia l Pr io ri ty Bit
CC: Spec ial Colo r Calc ul atio n Bit

Flip Fun ct ion

Pattern Nam e Da ta in Pat tern Name Tab le
11

1

nfi

(5 ) Cha ra ct er Size : 2 H ce l s X 2 V ce l s
Cha ra ct er Colo r Coun t : 16 Col or s
Cha ra ct er Num ber Supp le me nt Mo de : Mod e 0

Bit 15 14 13 12
Pal et te Numb er

2

de

Bit 9
Speci alFun ct ion

ntial(4 ) Cha ra ct er Size : 1 H ce l X 1 V ce l
Cha ra ct er Colo r Coun t : Exce pt 16 col or s
Cha ra ct er Num ber Supp le me nt Mo de : Mod e 1

8

7

10

9

6

5

4

3

2

1

0

4

3

2

Cha ra ct er Numb er

011

Vert ica l

8

7

6

5

Ho ri zo nt alSpeci alFun ct ion
PR

CC

Co

Supp le me nt al Dat a in Pat ter n Na me Con trol Reg ist er
Bit 9
8
7
6
5
4
3
2
1
0
Pal et te No.

Cha ra ct er Num ber

6

14 13

5

4

12

0

PR : Speci al Pri orit y Bi t
CC: Sp ecia l C ol or Calcu lat ion Bi t

6

5

1

(6 ) Cha ra ct er Size : 2 H ce l s X 2 V ce l s
Cha ra ct er Colo r Coun t : 16 Col or s
Cha ract er Nu mb er Supp lem en t Mod e: Mo de 1

GA

Pattern Nam e Da ta in Pat tern Name Tab leBit 15

14

13

12

11

10

9

8

Pal et te Numb er
3

2

1

0

13 12

7

4

3

2

1

0

5

4

3

2

Char act er Nu mber
11 10

9

8

7

6

Not e: Bot h ve rt ica l an d hor izon tal f li p fun ct ion bi ts ar e set t o 0.

Sup pl em ent al Da ta in Pat t er n Name Con tro l Reg ist er

Bit 9

8

SE

Spe cia lFunct ion

PR

CC

7

6

5

4

3

2

1

0

Pal et te No.

Cha ra ct er Num ber

6

14

5

4

1

0

PR : Speci al Pri orit y Bi t
CC: Sp ecia l C ol or Calcu lat ion Bi t

No te: Shad ed bi ts ar e igno re d

Figure 4.10 Configuration when pattern name data is one word (continued)

72

Flip Funct ion

Pattern Nam e Da ta in Pattern Nam e Tabl e
Bit 15

14

13

12

11

10

9

8

7

Palet te Num be r
6

5

nti
al

(7 ) Cha ra ct er Size : 2 H ce l s X 2 V ce l s
Cha ract er Co lor Cou nt : Exce pt 16 col or s
Cha ract er Nu mb er Supp lem en t Mod e: Mo de 0

6

5

4

3

2

1

0

4

3

2

Cha ra ct er Nu mb er

4

11 10 9Ver tical
Hor izo nt al
Note: Shad ed bi t is ig no re d

8

7

6

5

Not e: Sha ded bit s ar e ig no re ddeSuppl eme nt al Dat a in Pat ter n Na me Con trol Reg ist er
Bit 9
8
7
6
5
4
3
2
1
0
Speci al
Pal et t e No.
Cha ra ct er Nu mb er
PR: Sp ecia l Pr io ri ty Bit
Fun ct ion
PR CC
14 13 12 1
0 CC: Spec ial Colo r Calc ula tio n Bit

nfi(8 ) Cha ra ct er Size : 2 H ce l s X 2 V ce l s
Cha ract er Co lor Cou nt : Exce pt 16 col or s
Cha ract er Nu mb er Supp lem en t Mod e: Mo de 1

9

8

Co

Pattern Nam e Da ta in Pattern Nam e Tabl e
Bit 15

14

13

12

10

Palet t e Numb er
6

5

4

11

13

10

12

11

7
6
5
4
Cha ra ct er Nu mb er
9

8

7

6

3

2

1

0

5

4

3

2

Not e: Bot h ve rt ica l an d hor izon tal f li p fun ct ion bi ts ar e se t t o 0.
Sha de d bit is ign or ed
Suppl eme nt al Dat a in Pat ter n Na me Con trol Reg ist er
Bit 9Speci alFun ct ion

8

PR

CC

7
6
5
Pal et t e No.

4

3

2

1

0

Char act er Num be r

14

1

0

PR: Sp ecia l Pr io ri ty Bit
CC: Spec ial Colo r Calc ula tio n Bit

GA

Not e: Shade d bi ts are ign or ed

SE

Figure 4.10 Configuration when pattern name data is one word (continued)

ST-58-R2

73

Character Numberntial

The character number is 15-bit data, and designates the address of the character
pattern being displayed in that position. The boundary of the character pattern fromthis character number is always 20H. Moreover, when the VRAM size is 4M bits, themost significant bit of the character number (bit 14) is not used.
Palette Number

Cha ra ct er Colo r Co un t : 16 Col or s
Pal ette Nu mbe r
5

4

3

2

Dot Col or Cod e
1

0

3

2

1

0

nfi

6

de

The palette number is 7-bit data, and designates the address of the color palette usedin the character pattern being displayed in that position. This data can be used only
when the color format is the palette format, not the RGB format. The palette number
is added to the dot color code of the character pattern. Because there is a total of 11
bits of dot color data, the bits that are used change depending on the character color
number. Figure 4.11 shows the configuration of 11-bit dot color data.

Cha ra ct er Colo r Coun t : 25 6 Colo rs
Pal ette No .
65

4

Dot Col or Code
7

6

5

4

3

2

1

0

1

0

Co

Cha ra ct er Colo r Coun t : 20 48 Col or s
Do t Colo r Co de

10

9

8

7

6

5

4

3

2

Figure 4.11 Dot color data by character color number

GA

Special Function Bit

SE

The special function bit is 2-bit data, and designates whether to use the special
function for the character pattern being displayed at that position. The special
function bit has a special priority bit that controls the priority number, and a special
color calculation bit that controls color operation. See “11.2 Special Priority Function” for more about the special priority bit, and “12.3 Special Color Calculation
Function” for more about the special color calculation bit.

74

Reverse (Flip) Function Bit

Table 4.7 Reverse Function Bit

ntial

The reverse function bit is 2-bit data, and designates whether to use the reverse
function for the character pattern being displayed at that position. The reverse
function bit has a top-bottom reverse bit that reverses the top and bottom of a character pattern, and a left-right reverse bit that reverses left and right. The reverse
function bit is shown in Table 4.7, and a reverse display of a character pattern inshown in Figure 4.12.

Horizontal Flip Bit

Process

0
0
1
1

0
1
0
1

Cannot flip vertically or horizontally
Horizontal flipping only
Vertical flipping only
Can flip both vertically and horizontally

Hori z. Flipnfi

Ver tical Flip Bit =0
Hor izon tal Flip Bit =0

deVertical Flip Bit

Ver tical Flip Bit =0
Hor izo nt al Flip Bit =1

Hori z. and Ver t. Fli p

Co

Ve rt. Flip

Ver tica l Fl ip Bit =1
Hor izon tal Flip Bit =0

Vert ica l Fli p Bit =1
Hori zon tal Fl ip Bit =1

SE

GA

Figure 4.12 Reverse display of character patterns

ST-58-R2

75

Pattern Name Control RegisterntialThe pattern name control register assigns pattern name data size, character number
supplement mode, and pattern name supplement data. This register is a write only
16-bit register located in addresses 180030H to 180038H. Because the value of theregister is cleared to 0 after the power is turned on or reset, the value must be set.
12~
4
N0SCN411~
3
N0SCN310~
2N0SCN2

9N0SPR
1N0SCN18
N0SCC
0N0SCN0PNCN1180032H

15
14
13
N1PNB
N1CNSM~
7
6
5
N1SPLT6 N1SPLT5 N1SPLT412~4N1SCN411~
3
N1SCN310~
2N1SCN29N1SPR
1N1SCN18
N1SCC
0N1SCN0PNCN2180034H

15
14
13
N2PNB
N2CNSM~
7
6
5
N2SPLT6 N2SPLT5 N2SPLT412~4N2SCN411~
3
N2SCN310~
2
N2SCN29N2SPR
1N2SCN18N2SCC
0N2SCN0PNCN3180036H

15
14
13
N3PNB
N3CNSM~
7
6
5
N3SPLT6 N3SPLT5 N3SPLT412~4N3SCN411~
3
N3SCN310~
2N3SCN29N3SPR
1N3SCN18N3SCC
0N3SCN0PNCR
180038H

15
14
13
R0PNB
R0CNSM~
7
6
5
R0SPLT6 R0SPLT5 R0SPLT410~2
R0SCN2

9R0SPR
1R0SCN1

8R0SCC
0R0SCN0

Co

nfi

de

PNCN0
180030H

15
14
13
N0PNB
N0CNSM~
7
6
5
N0SPLT6 N0SPLT5 N0SPLT412~4R0SCN411~
3
R0SCN3

Pattern name data size bit (N0PNB, N1PNB, N2PNB, N3PNB, R0PNB)
180030H
180032H
180034H
180036H
180038H

SE

N0PNB
N1PNB
N2PNB
N3PNB
R0PNB

GA

Designates the pattern name data size when displaying in the cell format.

76

Bit 15
Bit 15
Bit 15
Bit 15
Bit 15For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0Pattern Name Data Size

01

2 Words
1 WordNote: N0, N1, N3, or R0 is entered in bit name for xx.

nti
al

xxPNB

Character number supplement bit (N0CNSM, N1CNSM, N2CNSM, N3CNSM, R0CNSM)

Designates the character number supplement mode when the pattern name data sizein the pattern name table is 1-word.
Bit 14
Bit 14
Bit 14
Bit 14
Bit 14xxCNSM

Character Number
Auxiliary Mode

0

0

1

1

de

180030H
180032H
180034H
180036H
180038H

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0

Process

Character number in pattern name data is 10 bits.
Flip function can be selected in character units.
Character number in pattern name data is 12 bits.
Flip function cannot be used.

nfi

N0CNSM
N1CNSM
N2CNSM
N3CNSM
R0CNSM

Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.

Special priority bit (for pattern name supplement data): Supplementary special priority bit(N0SPR, N1SPR, N2SPR, N3SPR, R0SPR)

N0SPR
N1SPR
N2SPR
N3SPR
R0SPR

Co

Designates the pattern name supplement data as the special priority bit when thepattern name data size is 1-word.
180030H
180032H
180034H
180036H
180038H

Bit 9
Bit 9
Bit 9
Bit 9
Bit 9

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0

SE

GA

See “11.2 Special Color Priority Function” for how this bit is used.

ST-58-R2

77

Special color calculation bit (for pattern name supplement data): Supplementary special color
calculation bit (N0SCC, N1SCC, N2SCC, N3SCC, R0SCC)

N0SCC
N1SCC
N2SCC
N3SCC
R0SCC

180030H
180032H
180034H
180036H
180038Hntial

The special color calculation bit is designated as pattern name supplement datawhen the pattern name data size is 1-word.
Bit 8
Bit 8
Bit 8
Bit 8
Bit 8

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0

See “12.2 Special Color Calculation Function” to learn how this bit is used.

deSupplementary palette number bit (N0SPLT6 to N0SPLT4, N1SPLT6 to N1SPLT4, N2SPLT6 to
N2SPLT4, N3SPLT6 to N3SPLT4, R0SPLT6 to R0SPLT4)

Designates the palette number bit as pattern name supplement data when the pattern name data size is 1-word. Three bits are added to the palette number bit of thepattern name data for the supplementary palette number bit.
180030H
180032H
180034H
180036H
180038H

Bit 7~5
Bit 7~5
Bit 7~5
Bit 7~5
Bit 7~5

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0nfi

N0SPLT6~N0SPLT4N1SPLT6~N1SPLT4N2SPLT6~N2SPLT4N3SPLT6~N3SPLT4R0SPLT6~R0SPLT4

Supplementary character number bit (N0SCN4 to N0SCN0, N1SCN4 to N1SCN0, N2SCN4 to
N2SCN0, N3SCN4 to N3SCN0, R0SCN4 to R0SCN0)180030H
180032H
180034H
180036H
180038HSEGA

N0SCN4~N0SCN0N1SCN4~N1SCN0
N2SCN4~N2SCN0
N3SCN4~N3SCN0
R0SCN4~R0SCN0Co

Designates the character number bit as the pattern name supplement data when thepattern name data size is 1-word. Five bits are added to the palette number bit of
the pattern name data for the supplementary palette number bit.

78

Bit 4~0
Bit 4~0
Bit 4~0
Bit 4~0
Bit 4~0

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0

4.7 PlanesntialPlane arranges the pattern name table (page) in sizes of 1 x 1, 2 x 1, or 2 x 2. Size isdesignated in its respective register.
Plane Size

Pat ter n Na me Tab leWhe n 1 H page X 1 V pa ge

Pag e 0Pag e 1Page 064 Cel ls

nfi

Select ed
Pattern Nam e
Tab le Heade r
Addr essdeWhen the plane consists of more than one pattern name table (page), the patternname table used by one plane should be linked to VRAM and stored. Figure 4.13
shows the relationship of the pattern name table arranged by plane size (number ofplane page) and pattern name table.

64 Cel lsCo

Whe n 2 H pa ge s X 1 V pa ge

Pag e 2Pag e 3Pag e 0Pag e 164 Ce lls

12 8 Cel ls

Wh en 2 H pag es X 2 V page s

Pag e 0Pag e 1SE

GA

Pag e 4

ST-58-R2

12 8 Cel ls

Pag e 2Pag e 3

12 8 Cel ls

Figure 4.13 Arrangement of pattern name table by plane size

79Plane Size Register

PLSZ
18003AHntial

The plane size register controls the plane size and setting of the screen-over processof the rotation scroll surface. This register is a write only 16-bit register located ataddress 18003AH. Because the value of the register is cleared to 0 after the power isturned on or reset, the value must be set.

15
14
13
12
11
10
9
8
RBOVR1 RBOVR0 RBPLSZ1 RBPLSZ0 RAOVR1 RAOVR0 RAPLSZ1 RAPLSZ0
7
6
5
4
3
2
1
0
N3PLSZ1 N3PLSZ0 N2PLSZ1 N2PLSZ0 N1PLSZ1 N1PLSZ0 N0PLSZ1 N0PLSZ0dePlane size bit (N0PLSZ1, N0PLSZ0, N1PLSZ1, N1PLSZ0, N2PLSZ1, N2PLSZ0, N3PLSZ1,N3PLSZ0, RAPLSZ1, RAPLSZ0, RBPLSZ1, RBPLSZ0)

Designates the plane size (number of pages) of each scroll screen.
18003AH
18003AH
18003AH
18003AH
18003AH
18003AH

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6
Bit 9,8
Bit 13,12

For NBG0
For NBG1
For NBG2
For NBG3
For Rotation Parameter A
For Rotation Parameter B

nfi

N0PLSZ1, N0PLSZ0N1PLSZ1, N1PLSZ0N2PLSZ1, N2PLSZ0N3PLSZ1, N3PLSZ0RAPLSZ1, RAPLSZ0RBPLSZ1, RBPLSZ0xxPLSZ0

Plane Size

0
0
1
1

0
1
0
1

1 H Page X 1 V Page
2 H Pages X 1 V Page
Invalid (Do not set.)
2 H Pages X 2 V Pages

Co

xxPLSZ1

Note: N0, N1, N2, N3, RA, or RB is entered in bit name for xx.

SE

GA

When the reduction display is set up to a factor of 1/4 in NBG0 and NBG1, do not
set the plane size of that screen to 2 H pages x 2 V pages.

80Screen-over process bit: Over bit (RAOVR1, RAOVR0, RBOVR1, RBOVR0)RAOVR1, RAOVR0
RBOVR1, RBOVR0

18003AH
18003AH

Bit 11,10
Bit 15,14nti
alDesignates control (screen-over process) when the display coordinate value exceeds
the display area in the rotation scroll surface.
For Rotation Parameter A
For Rotation Parameter B

RxOVR0Screen Over Process

0
0

0
1

1
1

0
1

Outside the display area, the image set in the display area is repeatedOutside the display area, the character pattern specified by screen ove
pattern name register is repeated. (Only when the rotation scroll
surface is in cell format.)Outside the display area, the scroll screen is transparent,
Set the display area as 0≤X≤512, 0≤Y≤512 regardless of plane size or
bitmap size and make that area transparent.

Note: A or B is entered in bit name for x.

deRxOVR1

SE

GA

Co

nfi

When the rotation scroll surface is in bit map, the character pattern designated by
the screen-over pattern name register must not be set to repeat process. With therotation scroll surface in bit map, and when the length of the bit map is 256 dots, if
the display area is set to 0 ≤ X < 512 and 0 ≤ Y < 512 and all the outer area is set to betransparent, two of the same images will be displayed for each 256 V dots.

ST-58-R2

81

4.8

Maps

nti
al

Maps are square patterns consisting of 2 x 2 or 4 x 4 planes. A map of a Normal
scroll screen consists of a 2 x 2 plane, and a map of a rotation scroll surface consistsof a 4 x 4 plane. The method of arranging the plane is made by selecting the patternname table lead address in various plane registers.
Map Selection Registerde

Maps are organized into four planes (normal scroll screen) or 16 planes (rotation
scroll surface). Each screen has for each plane number a 6-bit map register to selectthe pattern name table lead address for various planes. It also has a map offset
register of three bits added to the highest map register. The total 9-bit map selection
register changes the bit used and the register displaying the address value, depending on the pattern name data size and character size. Figure 4.14 shows the relationship of the map register and map offset register.

87

Map Reg ist er A

nfi

Map Offse t Reg ist er
5

6

4

3

2

1

0

1

0

Ma p Re gi st er B

Map Offse t Regi st er
73

2

Ma p Re gi st er

6

5

GA

8

4

Co

5

4

3

2

1

0

Figure 4.14 Map selection register

SE

Table 4.8 shows the address values of register and bits that are used for the map
selection register by the pattern name data size and character size.

82

Table 4.8 Address value of map designated register by setting

1 H page X
1 V page

Pattern Name
Data Size

Character Size

1 Word1 H Cell X 1 V Cell
2 H Cells X 2 V Cells
1 H Cell X 1 V Cell
2 H Cells X 2 V Cells
1 H Cell X 1 V Cell
2 H Cells X 2 V Cells
1 H Cell X 1 V Cell
2 H Cells X 2 V Cells
1 H Cell X 1 V Cell
2 V Cells X 2 V Cells
1 H Cell X 1 V Cell
2 H Cells X 2 V Cells

2 Words
1 Word2 H pages X
1 V page

2 Words
1 Word2 Words(Value of bit 6~0) X 2000H(Value of bit 8~0) X 800H
(Value of bit 5~0) X 4000H(Value of bit 7~0) X 1000H(Value of bit 6~1) X 4000H(Value of bit 8~1) X 1000H(Value of bit 5~1) X 8000H(Value of bit 7~1) X 2000H(Value of bit 6~2) X 8000H(Value of bit 8~2) X 2000H(Value of bit 5~2) X 10000H(Value of bit 7~2) X 4000H

de2 H pages X
2 V pages

Bits and AddressesntialPlane Size

SE

GA

Co

nfi

Note: When the VRAM capacity is set at 4M bits, the most significant bit among the bits used is notused.

ST-58-R2

83

Map Sizential

Map size (number of planes in the map) will change depending on if the screen is anormal scroll screen or rotation scroll surface. The normal scroll screen has a map 2
H planes X 2 V planes in each screen. The rotation scroll surface has a map 4 H
planes X 4 V planes in both of rotation parameters A and B. Figure 4.15 shows theplane arrangements of different map sizes.

Plane
B

Plane
C

Plane
D

Rotation Scroll Screen

nfi

Plane
A

de

Normal Scroll Screen

Plane
B

Plane
C

Plane
D

Plane
E

Plane
F

Plane
G

Plane
H

Plane
J

Plane
K

Plane
L

Plane
N

Plane
O

Plane
P

Plane
I

GA

Plane
M

Co

Plane
A

SE

Figure 4.15 Map size

84

nti
al

When NBG0 and NBG1 enable bits (N0ZMQT and N1ZMQT) are set to allow reduction up to a factor of 1/4, the map size of NBG0 and NBG1 become normal. A set
screen plane size, that can be reduced up to 1/4 should not be 2 H pages X 2 V
pages. Figure 4.16 shows the map size by the reduction setting.
Whe n se tting NBG1, ca n
be red uce d up to 1/4.

Plan e A
For NB G0

Plan e B
Fo r NBG0

Plane AFor NBG1

Plane BFor NBG1

Plane CFor NBG0

Pla ne D
For NBG0

Plan e C
For NB G1

Plane DFor NBG1

Plan e A
For NB G2

Plan e B
Fo r NBG2

Plane AFor NBG3

Plane BFor NBG3

Plane CFor NBG2

Pla ne D
For NBG2

Plan e C
For NB G3

Plane DFor NBG3

nfi

de

When se tting NBG0, ca n
be red uce d up to 1/4.

Co

Figure 4.16 Plane arrangement of map by reduction settings

Map Offset Register

The map offset register designates the map offset value. This is a write-only 16-bit
register, with addresses located at 18003CH to 18003EH. Because the value of theregister is cleared to 0 after the power is turned on or reset, the value must be set.
15
~
7
~

14
N3MP8
6
N1MP8

13
N3MP7
5
N1MP7

12
N3MP6
4
N1MP6

11
~
3
~

10
N2MP8
2
N0MP8

9
N2MP7
1
N0MP7

8
N2MP6
0
N0MP6

MPOFR
18003EH

15
~
7
~

14
~
6
RBMP8

13
~
5
RBMP7

12
~
4
RBMP6

11
~
3
~

10
~
2
RAMP8

9
~
1
RAMP7

8
~
0
RAMP6

SE

GA

MPOFN
18003CHST-58-R2

85

Map offset bit (N0MP8 to N0MP6, N1MP8 to N1MP6, N2MP8 to N2MP6, N3MP8 to N3MP6,
RAMP8 to RAMP6, RBMP8 to RBMP6)

N0MP8~N0MP6
N1MP8~N1MP6
N2MP8~N2MP6
N3MP8~N3MP6
RAMP8~RAMP6
RBMP8~RBMP6

18003CH
18003CH
18003CH
18003CH
18003EH
18003EH

Bit 2~0
Bit 6~4
Bit 10~8
Bit 14~12
Bit 2~0
Bit 6~4ntialWhen the scroll screen display format is the cell format, the map offset value of 3 bits
is added to the highest 6 bits of the map register. This designates the bit map patternboundary when in the bit map format.
For NBG0
For NBG1
For NBG2
For NBG3
For Rotation Parameter A
For Rotation Parameter B

SE

GA

Co

nfi

de

Boundary address of the bit map pattern is shown below:(boundary address value of the bit map pattern) = (map offset register value 3 bit) x
20000H.

86

Normal Scroll Screen Map RegisterntialNormal scroll screen map register designates the lead address of the pattern nametable of each plane when the normal scroll screen is displayed in the cell format.
This register is a write-only 16-bit register, with addresses located at 180040H to
18004EH. Because the value of the register is cleared to 0 after the power is turnedon or reset, the value must be set.
15
~
7
~

14
~
6
~

13
N0MPB55
N0MPA512
N0MPB4
4
N0MPA4

11
N0MPB3
3
N0MPA3

10
N0MPB2
2
N0MPA29N0MPB1
1
N0MPA18
N0MPB00
N0MPA0MPCDN0180042H

15
~
7
~

14
~
6
~

13
N0MPD55N0MPC512
N0MPD44N0MPC4

11
N0MPD3
3
N0MPC3

10
N0MPD2
2
N0MPC29N0MPD1
1
N0MPC18
N0MPD00
N0MPC0MPABN1
180044H

15
~
7
~

14
~
6
~

13
N1MPB55
N1MPA512
N1MPB4
4
N1MPA411
N1MPB3
3
N1MPA3

10
N1MPB2
2
N1MPA29
N1MPB11
N1MPA18
N1MPB00
N1MPA0MPCDN1
180046H

15
~
7
~

14
~
6
~

13
N1MPD55N1MPC512
N1MPD44N1MPC4

11
N1MPD33
N1MPC3

10
N1MPD2
2
N1MPC29N1MPD1
1
N1MPC18
N1MPD00
N1MPC0MPABN2180048H

15
~
7
~

14
~
6
~

13
N2MPB55
N2MPA512
N2MPB4
4
N2MPA411
N2MPB3
3
N2MPA3

10
N2MPB22
N2MPA29
N2MPB1
1
N2MPA18
N2MPB00
N2MPA0MPCDN218004AH

15
~
7
~

14
~
6
~

13
N2MPD55N2MPC512
N2MPD44N2MPC411
N2MPD3
3
N2MPC3

10
N2MPD22
N2MPC29
N2MPD1
1
N2MPC18
N2MPD00N2MPC0MPABN318004CH

15
~
7
~

14
~
6
~

13
N3MPB55
N3MPA512
N3MPB4
4
N3MPA411
N3MPB3
3
N3MPA3

10
N3MPB2
2
N3MPA29
N3MPB1
1
N3MPA1

8
N3MPB00
N3MPA0

15
~
7
~

14
~
6
~

13
N3MPD55
N3MPC512
N3MPD44N3MPC4

11
N3MPD33
N3MPC3

10
N3MPD2
2
N3MPC29N3MPD1
1
N3MPC1

8
N3MPD00N3MPC0ST-58-R2

nfi

Co

GA

SE
MPCDN318004EHdeMPABN0180040H

87

nti
al

Map bit (for normal scroll): (N0MPA5 to N0MPA0, N0MPB5 to N0MPB0,
N0MPC5 to N0MPC0, N0MPD5 to N0MPD0, N1MPA5 to N1MPA0, N1MPB5 to N1MPB0, N1MPC5
to N1MPC0, N1MPD5 to N1MPD0, N2MPA5 to N2MPA0, N2MPB5 to N2MPB0, N2MPC5 to
N2MPC0, N2MPD5 to N2MPD0, N3MPA5 to N3MPA0, N3MPB5 to N3MPB0, N3MPC5 to N3MPC0,
N3MPD5 to N3MPD0)

The lead address for the pattern name table is designated for each plane, when theNormal scroll screen is displayed by the cell format.

GA
SE
88

For NBG0 Plane A
For NBG0 Plane B
For NBG0 Plane C
For NBG0 Plane D
For NBG1 Plane A
For NBG1 Plane B
For NBG1 Plane C
For NBG1 Plane D
For NBG2 Plane A
For NBG2 Plane B
For NBG2 Plane C
For NBG2 Plane D
For NBG3 Plane A
For NBG3 Plane B
For NBG3 Plane C
For NBG3 Plane D

deBit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8nfi

180040H
180040H
180042H
180042H
180044H
180044H
180046H
180046H
180048H
180048H
18004AH
18004AH
18004CH
18004CH
18004EH
18004EHCo

N0MPA5~N0MPA0N0MPB5~N0MPB0N0MPC5~N0MPC0N0MPD5~N0MPD0N1MPA5~N1MPA0N1MPB5~N1MPB0N1MPC5~N1MPC0N1MPD5~N1MPD0N2MPA5~N2MPA0N2MPB5~N2MPB0
N2MPC5~N2MPC0
N2MPD5~N2MPD0N3MPA5~N3MPA0N3MPB5~N3MPB0
N3MPC5~N3MPC0
N3MPD5~N3MPD0Rotation Scroll Surface Map Registerntial

The Rotation Scroll Surface Map Register designates the lead address of the patternname table arranged in each plane by rotation parameters A and B. When a writeonly 16-bit register, with addresses located at 180050H to 18006EH. Because thevalue of the register is cleared to 0 after the power is turned on or reset, the value
must be set.
15
~
7
~

14
~
6
~

13
RAMPB55RAMPA5

12
RAMPB4
4RAMPA4

11
RAMPB3
3
RAMPA3

10
RAMPB2
2
RAMPA2

9RAMPB1
1
RAMPA1

8
RAMPB00RAMPA0MPCDRA
180052H

15
~
7
~

14
~
6
~

13
RAMPD5
5RAMPC512
RAMPD4
4RAMPC4

11
RAMPD3
3
RAMPC310
RAMPD2
2
RAMPC2

9RAMPD1
1
RAMPC1

8
RAMPD00RAMPC0MPEFRA
180054H

15
~
7
~

14
~
6
~

13
RAMPF55RAMPE512
RAMPF4
4RAMPE411
RAMPF3
3
RAMPE310
RAMPF2
2
RAMPE2

9RAMPF1
1
RAMPE1

8
RAMPF00
RAMPE0MPGHRA
180056H

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RAMPH5 RAMPH4 RAMPH3 RAMPH2 RAMPH1 RAMPH0
5
4
3
2
1
0
RAMPG5 RAMPG4 RAMPG3 RAMPG2 RAMPG1 RAMPG0MPIJRA
180058H

15
~
7
~

14
~
6
~

13
RAMPJ5
5
RAMPI5

12
RAMPJ4
4
RAMPI4

11
RAMPJ3
3
RAMPI3

10
RAMPJ2
2
RAMPI2

9RAMPJ1
1
RAMPI1

8
RAMPJ00
RAMPI0MPKLRA
18005AH

15
~
7
~

14
~
6
~

13
RAMPL55RAMPK5

12
RAMPL4
4
RAMPK4

11
RAMPL3
3
RAMPK310
RAMPL2
2
RAMPK2

9RAMPL1
1
RAMPK1

8
RAMPL00RAMPK0MPMNRA
18005CH

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RAMPN5 RAMPN4 RAMPN3 RAMPN2 RAMPN1 RAMPN0
5
4
3
2
1
0
RAMPM5 RAMPM4 RAMPM3 RAMPM2 RAMPM1 RAMPM0

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RAMPP5 RAMPP4 RAMPP3 RAMPP2 RAMPP1 RAMPP0
5
4
3
2
1
0
RAMPO5 RAMPO4 RAMPO3 RAMPO2 RAMPO1 RAMPO0

ST-58-R2

nfi

Co

GA

SE
MPOPRA
18005EHdeMPABRA
180050H

89

14
~
6
~

13
RBMPB5
5
RBMPA5

12
RBMPB4
4
RBMPA4

11
RBMPB3
3
RBMPA3

10
RBMPB2
2
RBMPA2

9
RBMPB1
1
RBMPA1

8
RBMPB00
RBMPA0MPCDRB
180062H

15
~
7
~

14
~
6
~

13
RBMPD55
RBMPC5

12
RBMPD4
4
RBMPC4

11
RBMPD3
3
RBMPC3

10
RBMPD2
2
RBMPC2

9
RBMPD1
1
RBMPC1

8
RBMPD00
RBMPC0MPEFRB
180064H

15
~
7
~

14
~
6
~

13
RBMPF5
5
RBMPE5

12
RBMPF4
4
RBMPE4

11
RBMPF3
3
RBMPE3

10
RBMPF2
2
RBMPE2

9
RBMPF1
1
RBMPE1

8
RBMPF00
RBMPE0MPGHRB
180066H

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RBMPH5 RBMPH4 RBMPH3 RBMPH2 RBMPH1 RBMPH0
5
4
3
2
1
0
RBMPG5 RBMPG4 RBMPG3 RBMPG2 RBMPG1 RBMPG0MPIJRB
180068H

15
~
7
~

14
~
6
~

13
RBMPJ5
5
RBMPI5

12
RBMPJ4
4
RBMPI4

11
RBMPJ3
3
RBMPI3

10
RBMPJ2
2
RBMPI2

9
RBMPJ1
1
RBMPI1

8
RBMPJ00
RBMPI0MPKLRB
18006AH

15
~
7
~

14
~
6
~

13
RBMPL55
RBMPK5

12
RBMPL4
4
RBMPK4

11
RBMPL3
3
RBMPK3

10
RBMPL2
2
RBMPK2

9
RBMPL1
1
RBMPK1

8
RBMPL00
RBMPK0MPMNRB
18006CH

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RBMPN5 RBMPN4 RBMPN3 RBMPN2 RBMPN1 RBMPN0
5
4
3
2
1
0
RBMPM5 RBMPM4 RBMPM3 RBMPM2 RBMPM1 RBMPM0MPOPRB
18006EH

15
~
7
~

90

de

nfi

Co

GA

SE

14
~
6
~

nti
al

MPABRB
180060H

15
~
7
~

13
12
11
10
9
8
RBMPP5 RBMPP4 RBMPP3 RBMPP2 RBMPP1 RBMPP0
5
4
3
2
1
0
RBMPO5 RBMPO4 RBMPO3 RBMPO2 RBMPO1 RBMPO0

nti
al

Map bit (for rotation scroll): Map bit (RAMPA5 to RAMPA0, RAMPB5 to RAMPB0,RAMPC5 to RAMPC0, RAMPD5 to RAMPD0, RAMPE5 to RAMPE0,
RAMPF5 to RAMPF0, RAMPG5 to RAMPG0, RAMPH5 to RAMPH0,
RAMPI5 to RAMPI0, RAMPJ5 to RAMPJ0, RAMPK5 to RAMPK0,
RAMPL5 to RAMPL0, RAMPM5 to RAMPM0, RAMPN5 to RAMPN0,RAMPO5 to RAMPO0, RAMPP5 to RAMPP0, RBMPA5 to RBMPA0,RBMPB5 to RBMPB0, RBMPC5 to RBMPC0, RBMPD5 to RBMPD0,RBMPE5 to RBMPE0, RBMPF5 to RBMPF0, RBMPG5 to RBMPG0,
RBMPH5 to RBMPH0, RAMPI5 to RBMPI0, RBMPJ5 to RBMPJ0,RBMPK5 to RBMPK0, RBMPL5 to RBMPL0, RBMPM5 to RBMPM0,
RBMPN5 to RBMPN0, RBMPO5 to RBMPO0, RBMPP5 to RBMPP0)

SE

GA

Co

nfi

de

When a rotation scroll surface is displayed in the cell format, it designates the leadaddress of the pattern name table being arranged in each plane .

ST-58-R2

91

SE
92

de

nti
al

Rotation Parameter A for Screen Plane A
Rotation Parameter A for Screen Plane B
Rotation Parameter A for Screen Plane C
Rotation Parameter A for Screen Plane D
Rotation Parameter A for Screen Plane E
Rotation Parameter A for Screen Plane F
Rotation Parameter A for Screen Plane G
Rotation Parameter A for Screen Plane H
Rotation Parameter A for Screen Plane I
Rotation Parameter A for Screen Plane J
Rotation Parameter A for Screen Plane K
Rotation Parameter A for Screen Plane L
Rotation Parameter A for Screen Plane M
Rotation Parameter A for Screen Plane N
Rotation Parameter A for Screen Plane O
Rotation Parameter A for Screen Plane P
Rotation Parameter B for Screen Plane A
Rotation Parameter B for Screen Plane B
Rotation Parameter B for Screen Plane C
Rotation Parameter B for Screen Plane D
Rotation Parameter B for Screen Plane E
Rotation Parameter B for Screen Plane F
Rotation Parameter B for Screen Plane G
Rotation Parameter B for Screen Plane H
Rotation Parameter B for Screen Plane I
Rotation Parameter B for Screen Plane J
Rotation Parameter B for Screen Plane K
Rotation Parameter B for Screen Plane L
Rotation Parameter B for Screen Plane M
Rotation Parameter B for Screen Plane N
Rotation Parameter B for Screen Plane O
Rotation Parameter B for Screen Plane P

nfi

Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8Co

180050H
180050H
180052H
180052H
180054H
180054H
180056H
180056H
180058H
180058H
18005AH
18005AH
18005CH
18005CH
18005EH
18005EH
180060H
180060H
180062H
180062H
180064H
180064H
180066H
180066H
180068H
180068H
18006AH
18006AH
18006CH
18006CH
18006EH
18006EHGA

RAMPA5~RAMPA0RAMPB5~RAMPB0RAMPC5~RAMPC0RAMPD5~RAMPD0RAMPE5~RAMPE0
RAMPF5~RAMPF0
RAMPG5~RAMPG0
RAMPH5~RAMPH0RAMPI5~RAMPI0RAMPJ5~RAMPJ0RAMPK5~RAMPK0RAMPL5~RAMPL0
RAMPM5~RAMPM0
RAMPN5~RAMPN0RAMPO5~RAMPO0RAMPP5~RAMPP0RBMPA5~RBMPA0
RBMPB5~RBMPB0
RBMPC5~RBMPC0
RBMPD5~RBMPD0
RBMPE5~RBMPE0
RBMPF5~RBMPF0
RBMPG5~RBMPG0
RBMPH5~RBMPH0
RBMPI5~RBMPI0
RBMPJ5~RBMPJ0RBMPK5~RBMPK0
RBMPL5~RBMPL0
RBMPM5~RBMPM0
RBMPN5~RBMPN0
RBMPO5~RBMPO0RBMPP5~RBMPP0

4.9 Bit MapsntialWhen displaying the bit map format, select from sizes, 512 H dots x 256 V dots, 512
H dots x 512 V dots, 1024 H dots x 256 V dots, or 1024 H dots X 512 V dots. All dot
bit map pattern data is stored in the VRAM.
Bit Map Size

Table 4.9 Bit map size
ScreendeDifferent types of bit map sizes can be selected by the normal scroll screen androtation scroll surface. When a high-resolution graphics mode that is greater than
512 H pixels is selected in a Normal scroll screen, if a 512 H dot bit map size is selected, the same picture is repeated in the horizontal direction. Furthermore, whenthe vertical resolution selects the exclusive monitor mode or double-density interlace
mode with more than 256 pixels when a 256 V dot bit map size is selected, the same
picture is repeated in the vertical direction. Table 4.9 shows bit map sizes.

Bitmap Size Selections

Rotation
Scroll Screen

Co

Bit Map Color Numbernfi

512 H dots X 256 V dots
512 H dots X 512 V dots
1024 H dots X 256 V dots
1024 H dots X 512 V dots
512 H dots X 256 V dots
512 H dots X 512 V dots

NormalScroll Screen

SEGA

The color format for displaying the bit map format screen combines the bit map
palette number and dot color code within bit map pattern data. It has a paletteformat, which designates the color RAM address, and RGB format that directly
designates display RGB data. Table 4.10 shows, in various color formats the bit map
surface per color number and the bit number per dot of the bit map pattern data.
Furthermore, the bit map color count is set to the character color count bit of thecharacter control register.

ST-58-R2

93

Table 4.10 Bit map color countPaletteRGB

Bitmap Pattern Data Bit Count For 1
Dot

16 colors
256 colors
2048 colors
32,768 colors
16,770,000 colors

4 bits8 bits
16 bits (only use lower 11 bits)
16 bits
32 bits (only use MSB and lower 24 bits)

2028 colors become 1024 colors when the color RAM mode is 0 or 2.

SE

GA

Co

nfi

de

Note:

Bitmap Color CountntialColor Format

94

Bit Map Patternntial

The required VRAM capacity in a 1-bit map pattern surface depends upon the bitmap size and bit map color count (bit map pattern data size). Changes in the data
configuration of each bit map pattern stored in VRAM are identical. The bit map
size and bit map color count can be set to exceed the VRAM capacity, but the same
picture would be repeated in the vertically. Table 4.11 shows bit map pattern capacities and Figure 4.17 shows the bit map pattern configuration.

deThe boundary that stores bit map patterns in the VRAM is 20000H, and is independent of the bit map size and the bit map color count. The designation is performedin the map offset register.
Table 4.11 Bit map pattern capacity per 1 surface

512 H dots X
512 V dots

1024 H dots X
256 V dots

Size per Surface

4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot
4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot
4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot
4 bits/dot
8 bits/dot
16 bits/dot

16 colors
256 colors
2048 colors, 32,768 colors
16,770,000 colors
16 colors
256 colors
2048 colors, 32,768 colors
16,770,000 colors
16 colors
256 colors
2048 colors, 32,768 colors
16,770,000 colors
16 colors
256 colors
2048 colors, 32,768 colors

64K bytes
128K bytes
256K bytes
512K bytes
128K bytes
256K bytes
512K bytes
1024K bytes
128K bytes
256K bytes
512K bytes
1024K bytes
256K bytes
512K bytes
1024K bytes(512K bits)(1M bits)(2M bits)(4M bits)(1M bits)(2M bits)(4M bits)(8M bits)(1M bits)(2M bits)(4M bits)(8M bits)(2M bits)(4M bits)(8M bits)

SE

GA

1024 H dots X
512 V dots

Bitmap Color Countnfi

512 H dots X
256 V dots

Bitmap Pattern
Data SizeCo

Bitmap Size

ST-58-R2

95

Bit ma p Pat ter n (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

nti
al

(1) Bit ma p Size : 512 H dot s X 25 6 V dot s
Bit ma p Colo r Coun t : 4 bits/ dot (1 6 co lor s)

10

Dot 0- 0

Dot 0- 1

Dot 0- 2

Dot 0- 3+0 00 2H

Dot 0- 4

Dot 0- 5

Dot 0- 6

Dot 0- 7+FFFEH

Dot 25 5- 50 8

Dot 25 5- 50 9

Dot 25 5- 51 0

Dot 25 5- 511

1

3+ 00 00

+0001

+0100

+0101

50 8

50 9

51 0

511

+00FE

+00F F

+01FE

+01FF

Co

Dot 0

2

nfi

1

Dot 0

de

+0 00 0H

25 4

+F E0 0

+FE 01+FE FE+FE FE

25 5+F F0 0

+F F0 1+FFF E+FF FF

GA

Note 1: The upp er lef t not ation in the cel l is do t 0-0 ; to the righ t are do t 0-1 ,dot 0- 2, do t 0-3 , ...
Note 2: Nu mber s in the ce l s are VRAM ad dr esse s (h exa de cim al) of dot (2dot s) dat a, with VRAM add re ss of do t 0-0 , 0-1 da ta as therefer en ce.

SE

Figure 4.17 Bit map pattern configuration

96

BitmapBitmap Pattern (VRAM)
14 13 12 11

10+00 00 0H

Dot 0- 0+00 00 2H

Do t 0-2+1F FFEH

Do t 255 -5 10

Do t 0
Dot 0

1

2

8

7

6

5

4

3

2

1

0

Do t 0-1
Do t 0-3

3

Do t 255 -5 11

508

509

510

511

+0 01F C +00 1F D +001 FE +0 01F F

nfi+000 00 +0 000 1 +000 02 +0 000 3+002 00 +0 020 1 +002 02 +0 020 3

Co

1

9

de

Bit 15ntial(2 ) Bitmap Size : 512 H do ts X 25 6 V do ts
Bitmap Col or Coun t : 8 bit s/ do t (25 6 co lor s)+0 03F C +00 3F D +003 FE +0 03F F

25 4 +1F C0 0 +1F C01 +1F C0 2 +1F C03+1F DF C +1 FD FD +1F DF E +1F DF F

25 5 +1 FE0 0 +1F E01 +1 FE0 2 +1F E03+1F FFC +1F FF D +1 FF FE +1F FFF

BitmapGA

Note 1: The upp er lef t no tation in the cel l is do t 0-0 ; to the righ t are do t 0-1 ,dot 0- 2, do t 0-3 , ...
Note 2: Nu mb er s in the ce l s are VRAM add re sses (h exadeci mal ) of do t
dat a, with VRAM add re ss of do t 0-0 da ta as the re fer ence.

Bit map pattern configuration (continued)

SE

Figure 4.17

ST-58-R2

97

Bitmap Pat ter n (VRAM)
14

13

12

11

10

9

8

7

Dot 0- 0+00 00 2H

Dot 0-1+3F FFEH

Do t 255 -5 11

1

2

3

+00 000 +000 02 +00 004 +000 06

Do t 0+00 400 +004 02 +00 404 +004 06

4

3

2

50 8

50 9

1

51 0

0

511

+0 03F 8 +0 03F A +003 FC +0 03F E+0 07F 8 +0 07F A +007 FC +0 07F E

Co

1

5

nfi

Dot 0

6

de

Bit 15+00 00 0H

ntial(3) Bit ma p Size : 512 H dot s X 25 6 V dot s
Bit ma p Colo r Coun t : 16 bi ts/ dot (204 8 col or s, 327 68 col ors)

25 4 +3F 80 0 +3 F8 02 +3F 80 4 +3 F8 06+3F BF8 +3F BFA +3 FBF C +3F BF E

25 5 +3 FC 00 +3F C0 2 +3 FC 04 +3F C0 6

+3F FF8 +3F FFA +3 FF FC +3F FFEGA

Not e 1: The upp er lef t no tat io n in the ce ll is dot 0- 0; to the righ t ar e do t 0-1 ,dot 0- 2, dot 0- 3, ...
Not e 2: Numb er s in the cel ls are VRAM add re sses (hexad eci mal ) of do t
dat a, with VRAM ad dr ess of dot 0- 0 da ta as the re fer en ce.

SE

Figure 4.17 Bit map pattern configuration (continued)

98

Bitmapntial(4) Bit ma p Size : 512 H dot s X 25 6 V dot s
Bit ma p Colo r Coun t : 32 bi ts/ do t (16 ,77 0, 000 col ors)

Bitmap Pat ter n (V RA M)
Bit 15

14

13

12

11

10

9

8

7

6

5

+0 00 02 H

Dot 0- 0 (l ow er wo rd )+0000 4H

Dot 0-1 (upp er wor d)+7 FFFCH

Do t 255 -5 11 (up pe r wo rd )+7F FFEH

Dot 25 5- 511 (lo wer wor d)

254
255

nfi

1

2

3

2

1

0

509

+0 000 0 +00 004 +0 000 8 +0 000 C+007 F0+00 7F 4 +007 F8 +007 FC+0 080 0 +00 804 +0 080 8 +0 080 C+0 0F F0 +00 FF 4 +0 0F F8 +0 0F FC

Co

1

3

508

Dot 0
Dot 0

4

de

+0 00 00 H

Dot 0-0 (upp er wor d)

510

511

Bitma p+7 F0 00 +7F 004+7 F0 08 +7 F0 0C+7F 7F 0 +7F 7F 4 +7 F7 F8 +7 F7 FC+7 F8 00 +7F 804+7 F8 08 +7 F8 0C+7 FF F0 +7F FF 4 +7 FF F8 +7 FF FC

GA

No te 1: The up per left not ation in the cel l is do t 0-0 ; to the ri gh t are dot 0-1,
dot 0- 2, do t 0-3 , ...
No te 2: Num be rs in the ce lls ar e VRA M ad dr esse s (h exa de cim al) of dot
dat a (up pe r wo rd) , with VRAM ad dr ess of dot 0- 0 da ta (uppe r wor d) as
the ref ere nce .

SE

Figure 4.17 Bit map pattern configuration (continue)

ST-58-R2

99

Bitmap Pattern (VRAM)
10+0 00 00H

Do t 0-0

Do t 0-1

Do t 0-2

Do t 0-3+0 00 02H

Do t 0-4

Do t 0-5

Do t 0-6

Do t 0-7+1F FFEH

Do t 511- 50 8

Do t 511- 50 9

Do t 511- 51 0

Do t 511- 511

Dot 0

1

2

+00000+00001+00100+00101

3

8

7

6

5

4

3

2

1

0

50 8

50 9

51 0

511

nfi

1

Do t 09

de

14 13 12 11+000FE+000FF+001FE+001FFCo

Bit 15ntial(5 ) Bitmap Size : 512 H do ts X 51 2 V do ts
Bitmap Col or Coun t : 4 bit s/ do t (16 col ors)

510

+1F E0 0+1F E0 1+1F EFE+ 1F EF F

511+1FF0 0

+1FF0 1

+ 1F FFE+1FFFFGA

Not e 1: The upp er lef t no tat io n in the ce l is dot 0- 0; to the right ar e do t 0- 1,
dot 0-2, dot 0- 3, ...
Not e 2: Numb er s in the cel ls ar e VRAM add re sses (hexadeci mal ) of do t (2dot s) dat a, with VRAM ad dr ess of dot 0- 0, 0- 1 da ta as theref erence .

SE

Figure 4.17 Bit map pattern configuration (continued)

100

Bitmapntial(6) Bitmap Size : 512 H dots X 512 V dots
Bitmap Color Count : 8 bits/dot (256 colors)

Bitmap Pattern (VRAM)
14

13

12

11

10

+00000H

Dot 0-0+00002H

Dot 0-2+3FFFEH

Dot 511-510

Dot 0
Dot 0

1

2

8

7

6

5

4

3

2

1

0

Dot 0-1
Dot 0-3

3

Dot 511-511

508

509

510

511

+001FC +001FD +001FE +001FF

nfi+00000 +00001 +00002 +00003+00200 +00201 +00202 +00203

Co

1

9

de

Bit 15+003FC +003FD +003FE +003FF

510+3FC00 +3FC01 +3FC02 +3FC03+3FDFC +3FDFD +3FDFE +3FDFF

511+3FE00 +3FE01 +3FE02 +3FE03+3FFFC +3FFFD +3FFFE +3FFFF

BitmapGA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

ST-58-R2

101

Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

Dot 0-0+00002H

Dot 0-1+7FFFEH

Dot 511-511

Dot 0

1

2

3

+00000 +00002 +00004 +00006+00400 +00402 +00404 +00406

4

3

2

508

509

1

510

0

511

+003F8 +003FA +003FC +003FE+007F8 +007FA +007FC +007FE

Co

1

5

nfi

Dot 0

6

de

+00000Hntial(7) Bitmap Size : 512 H dots X 512 V dots
Bitmap Color Count : 16 bits/dot (2048 colors, 32768 colors)

510+7F800 +7F802 +7F804 +7F806+7FBF8 +7FBFA +7FBFC +7FBFE

511+7FC00 +7FC02 +7FC04 +7FC06+7FFF8 +7FFFA +7FFFC +7FFFEGA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

102

Bitmapntial(8) Bitmap Size : 512 H dots X 512 V dots
Bitmap Color Count : 32 bits/dot (16,770,000 colors)

Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

Dot 0-0 (upper word)+00002H

Dot 0-0 (lower word)+00004H

Dot 0-1 (upper word)+FFFFCH

Dot 511-511 (upper word)+FFFFEH

Dot 511-511 (lower word)

510
511

2

3

3

2

1

0

508

509

510

511

+00000 +00004 +00008 +0000C+007F0 +007F4 +007F8 +007FC+00800 +00804 +00808 +0080C+00FF0 +00FF4 +00FF8 +00FFC

Co

1

1

nfi

Dot 0
Dot 0

4

de

+00000H

Bitmap+FF000 +FF004 +FF008 +FF00C+FF7F0 +FF7F4 +FF7F8 +FF7FC+FF800 +FF804 +FF808 +FF80C+FFFF0 +FFFF4 +FFFF8 +FFFFC

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data (upper word), with VRAM address of dot 0-0 data (upper word) as
the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

ST-58-R2

103

Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

nti
al

(9) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 4 bits/dot (16 colors)

2

1

0

Dot 0-0

Dot 0-1

Dot 0-2

Dot 0-3+00002H

Dot 0-4

Dot 0-5

Dot 0-6

Dot 0-7+1FFFEH

Dot 255-1020

Dot 255-1021

Dot 255-1022

Dot 255-1023

1+00000+00001+00200+00201254+1FC00255+1FE00

3

1020

Co

Dot 0

2

1021 1022

1023+001FE+001FF+003FE+003FF

nfi

1

Dot 0

de

+00000H+1FC01+1FDFE+1FDFF+1FE01+1FFFE+1FFFF

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot (2dots) data, with VRAM address of dot 0-0, 0-1 data as thereference.

SE

Figure 4.17 Bit map pattern configuration (continued)

104

BitmapBitmap Pattern (VRAM)
14

13

12

11

10

+00000H

Dot 0-0+00002H

Dot 0-2+3FFFEH

Dot 255-1022

Dot 0
Dot 0

1

2

255

7

6

5

4

3

2

1

0

Dot 0-3

3

Dot 255-1023

1020

1021 1022

1023+003FC +003FD +003FE +003FF

nfi+00400 +00401 +00402 +00403

Co

254

8

Dot 0-1+00000 +00001 +00002 +00003

1

9

de

Bit 15ntial(10) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 8 bits/dot (256 colors)+007FC +007FD +007FE +007FF+3F800 +3F801 +3F802 +3F803+3FBFC +3FBFD +3FBFE +3FBFF+3FC00 +3FC01 +3FC02 +3FC03+3FFFC +3FFFD +3FFFE +3FFFF

BitmapGA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

ST-58-R2

105

Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

Dot 0-0+00002H

Dot 0-1+7FFFEH

Dot 255-1023

Dot 0

1

2

3

+00000 +00002 +00004 +00006+00800 +00802 +00804 +00806

4

3

2

1

0

1020

1021 1022

1023+007F8 +007FA +007FC +007FE+00FF8 +00FFA +00FFC +00FFE

Co

1

5

nfi

Dot 0

6

de

+00000Hntial(11) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 16 bits/dot (2048 colors, 32768 colors)

254+7F000 +7F002 +7F004 +7F006+7F7F8 +7F7FA +7F7FC +7F7FE

255+7F800 +7F802 +7F804 +7F806+7FFF8 +7FFFA +7FFFC +7FFFEGA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

106

BitmapBitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

nti
al

(12) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 32 bits/dot (16,770,000 colors)5

Dot 0-0 (upper word)+00002H

Dot 0-0 (lower word)+00004H

Dot 0-1 (upper word)+FFFFCH

Dot 255-1023 (upper word)+FFFFEH

Dot 255-1023 (lower word)

2

3

3

2

1

0

1020

1021 1022

1023+00000 +00004 +00008 +0000C+00FF0 +00FF4 +00FF8 +00FFC+01000 +01004 +01008 +0100C+01FF0 +01FF4 +01FF8 +01FFC

Co

1

1

nfi

Dot 0
Dot 0

4

de

+00000H

Bitmap254+FE000 +FE004 +FE008 +FE00C+FEFF0 +FEFF4 +FEFF8 +FEFFC

255+FF000 +FF004 +FF008 +FF00C+FFFF0 +FFFF4 +FFFF8 +FFFFC

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data (upper word), with VRAM address of dot 0-0 data (upper word)
as the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

ST-58-R2

107

Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

nti
al

(13) Bitmap Size : 1024 H dots X 512 V dots
Bitmap Color Count : 4 bits/dot (16 colors)

10

Dot 0-0

Dot 0-1

Dot 0-2

Dot 0-3+00002H

Dot 0-4

Dot 0-5

Dot 0-6

Dot 0-7+3FFFEH

Dot 511-1020

Dot 511-1021

Dot 511-1022

Dot 511-1023

1

3+00000+00001+00200+002011020

1021 1022

1023+001FE+001FF+003FE+003FF

Co

Dot 0

2

nfi

1

Dot 0

de

+00000H

510+3FC00+3FC01+3FDFE+3FDFF

511+3FE00+3FE01+3FFFE+3FFFF

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot (2dots) data, with VRAM address of dot 0-0, 0-1 data as thereference.

SE

Figure 4.17 Bit map pattern configuration (continued)

108

BitmapBitmap Pattern (VRAM)
14

13

12

11

10

Dot 0-0+00002H

Dot 0-2+7FFFEH

Dot 511-1022

Dot 0
Dot 0

1

2

8

7

6

5

4

3

2

1

0

Dot 0-1
Dot 0-3

3

Dot 511-1023

1020

1021 1022

1023+003FC +003FD +003FE +003FF

nfi+00000 +00001 +00002 +00003+00400 +00401 +00402 +00403

Co

1

9

de

Bit 15+00000Hntial(14) Bitmap Size : 1024 H dots X 512 V dots
Bitmap Color Count : 8 bits/dot (256 colors)+007FC +007FD +007FE +007FF

510+7F800 +7F801 +7F802 +7F803+7FBFC +7FBFD +7FBFE +7FBFF

511+7FC00 +7FC01 +7FC02 +7FC03+7FFFC +7FFFD +7FFFE +7FFFF

BitmapGA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

ST-58-R2

109

Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

Dot 0-0+00002H

Dot 0-1+FFFFEH

Dot 511-1023

Dot 0

1

2

3

+00000 +00002 +00004 +00006+00800 +00802 +00804 +00806

3

2

1

1020

1021 1022

0

1023+007F8 +007FA +007FC +007FE+00FF8 +00FFA +00FFC +00FFE

Co

1

4

nfi

Dot 0

5

de

+00000Hntial(15) Bitmap Size : 1024 H dots X 512 V dots
Bitmap Color Count : 16 bits/dot (2048 colors, 32768 colors)

510+FF000 +FF002 +FF004 +FF006+FF7F8 +FF7FA +FF7FC +FF7FE

511+FF800 +FF802 +FF804 +FF806+FFFF8 +FFFFA +FFFFC +FFFFE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

SE

Figure 4.17 Bit map pattern configuration (continued)

110

BitmapBit Map Palette Number

Bitmap Color Count : 16 colors
Palette Number
5

4

3

2

Dot Color Code
1

0

3

2

1

0

de

6

nti
al

The bit map palette number designates the lead address of the palette used in the bit
map pattern. With the 3-bit data designated by the bit map palette number register,
the bit map palette number can only be used when the color format is in the paletteformat. It cannot be used when in the RGB format. Because the palette number isadded to the dot color code of the bit map pattern to make an 11 bit dot color code, thebit count that is used by the color count on each surface changes. Figure 4.18 shows
dot color data by bit map number colors.

Fixed at 0

Bitmap Palette Number Register Setting
Bitmap Color Count : 256 colors

6

5

4

Dot Color Code

nfi

Palette No.

7

6

5

4

3

2

1

0

1

0

Bitmap Palette Number Register Setting
Bitmap Color Count : 2048 colors

Co

Dot Color Code

10

9

8

7

6

5

4

3

2

Figure 4.18 Dot color data by bit map color numbers

Special Function Bit

SEGA

The special function bit designates whether to use the special function for bit map
patterns. The special function bit has a special priority bit that controls the priority
number and the special color calculation bit that controls color calculation. For more
information on the special priority bit see “11.2 Special Priority Function.” For more
information on the color calculation bit see “12.2 Special Color Calculation Function.”

ST-58-R2

111

Bit Map Palette Number Registerntial

Bit map palette number register selects the palette number when the scroll screen isdisplayed by the bit map format and special function bit. This register is a writeonly 16-bit register located in addresses 18002CH to 18002EH. Because the value iscleared to 0 after the power is turned on or reset, make sure the value is set.
15
~
7
~

14
~
6
~

13
N1BMPR
5
N0BMPR

12
N1BMCC
4
N0BMCC

11
~
3
~

10
N1BMP6
2
N0BMP6

9
N1BMP5
1
N0BMP5

8
N1BMP40
N0BMP4

BMPNB
18002EH

15
~
7
~

14
~
6
~

13
~
5
R0BMPR

12~
4
R0BMCC

11
~
3
~

10
~
2
R0BMP6

9~
1
R0BMP5

8~
0
R0BMP4de

BMPNA
18002CHSpecial priority bit (for bit map): Bit map special priority bit (N0BMPR, N1BMPR, R0BMPR)

N0BMPR
N1BMPR
R0BMPR

18002CH
18002CH
18002EH

nfi

Designates the special priority bit when the scroll screen is displayed by the bit map
format.
Bit 5
Bit 13Bit 5

For NBG0
For NBG1
For RBG0

See section “11.2 Special Priority Function” on how to use this bit.

Co

Special color calculation bit (for bit map): Bit map special color calculation bit (N0BMCC,
N1BMCC, R0BMCC)

Designates the special color calculation bit when the scroll screen is displayed by the
bit map format.
N0BMCCN1BMCCR0BMCC

18002CH
18002CH
18002EH

Bit 4
Bit 12Bit 4

For NBG0
For NBG1
For RBG0SEGA

See section “12.2 Special Color Calculation Function” on how to use this bit.

112

Palette number bit (for bit map): Bit map palette number bit (N0BMP2 to N0BMP0, N1BMP2 to
N1BMP0, R0BMP2 to R0BMP0)

N0BMP6~N0BMP4
N1BMP6~N1BMP4R0BMP6~R0BMP418002CH
18002CH
18002EH

Bit 2~0
Bit 10~8
Bit 2~0ntialDesignates the highest three bits of the palette number when the scroll screen isdisplayed in the bit map format.
For NBG0
For NBG1
For RBG0

SE

GA

Co

nfi

de

When the bit map color count is 16 colors, a “0” is attached to the lowest four bits
and used as the 7-bit palette number.

ST-58-R2

113

4.10 Display Areantial

The display area of the scroll screen changes depending on the register setting. The
display area image is repeated and displayed when display coordinate values exceed the display area in the Normal scroll screen. Control is executed by the registersetting when display coordinate values exceed the display area in the rotation scroll
surface.
Display Area

Table 4.12 Normal scroll screen display area
Plane Size

1 H page X
1 V pageNo reduction~ 1/2 2 H pages X
reduction
1 V page
2 H pages X
2 V pages
Up to 1/4
1 H page X
reduction
1 V page
2 H pages X
1 V page-

Bitmap Size

Display Area-0≤X<1024, 0≤Y<1024

nfi

Cell format

Reduction
Setting-0≤X<2048, 0≤Y<1024-

0≤X<2048, 0≤Y<2048-

0≤X<1024, 0≤Y<2048-

0≤X<2048, 0≤Y<2048

Co

DisplayFormatde

The display area changes according to the plane size when scroll screen display
format is the cell format, and according to the bit map size when in the bit map
format. NBG0 and NBG1 also change by setting the reduction display up to 1/4.
Tables 4.12 and 4.13 show the display areas.

Bitmap Format ---512 H dots X
256 V dots
512 H dots X
512 V dots
1024 H dots X
256 V dots
1024 H dots X
512 V dots0≤X<512, 0≤Y<256
0≤X<512, 0≤Y<512
0≤X<1024, 0≤Y<256
0≤X<1024, 0≤Y<512

Display Format

Cell format

Bitmap Format

GA

Table 4.13 Rotation Scroll Surface display area
Plane Size

Bitmap Size

Display Area

1 H page X
1 V page
2 H pages X
1 V page
2 H pages X
2 V pages--0≤X<2048, 0≤Y<2048-

0≤X<4096, 0≤Y<2048-

0≤X<4096, 0≤Y<4096

512 H dots X
256 V dots
512 H dots X
512 V dots0≤X<512, 0≤Y<256

SE

-

114

0≤X<512, 0≤Y<512

Screen-Over Process

3.
4.

The outside of the display area repeats the image set in the display area.
The outside of the display area repeats the character pattern designated by thescreen-over pattern name register (only when the rotation scroll surface is in thecell format).
The outside of the display area is transparent.
With no relationship to the plane size and bit map size, the display area is at
0 ≤ X < 512 and 0 ≤ Y < 512. The outside of the display area is all made to betransparent.

Display-Over Pattern Name

de

1.
2.

nti
al

While the rotation scroll surface is displayed, and if the calculated results of display
coordinate values of an display area have been exceeded, select one of the four below
and set it to the register. The setting of the screen-over process is not performed for
RBG0 and RBG1, but is performed for the scroll screen by rotation parameter A andthe scroll screen by rotation parameter B.

Co

nfi

When the designated character pattern is made to be repeated, pattern name data
selects the screen-over control setting in a16-bit screen-over pattern name register.
The screen-over pattern name data selected in the register is handled the same as
when the data size of the scroll surface pattern name table is 1-word; it uses supplemental data in the lowest 10 bits of the pattern name control register, supplements
insufficient bits, and does screen-over pattern name data of a total 26 bits. The bit
configuration of the screen-over pattern name register is the same as when the patternname data size is 1-word, as in “Pattern Name Table” of section 4.6; and changes
depending on character size, character color number, and the character number
supplement mode. The size of the repeated character pattern follows the setting of
the character size.

SEGA

16-bit screen over pattern name data designates for the scroll screen by rotation parameter A and scroll screen by rotation parameter B, but you should be careful when
designating for RBG0 and RBG1 by 10-bit supplement data designated by the patternname control register. Besides, screen-over pattern name data cannot be used when
the rotation scroll screen is displayed in the bit map format.

ST-58-R2

115

Screen-Over Pattern Name Registerntial

In the screen-over process of the rotation scroll surface, the screen-over pattern nameregister selects pattern name data when the repetition of the character pattern is set.
This register is a write-only 16-bit register and is in addresses 1800B8H to 1800BAH.
Because the value is cleared to 0 after the power is turned on or reset, be sure to set
the value.
15
14
13
12
11
10
9
RAOPN15 RAOPN14 RAOPN13 RAOPN12 RAOPN11 RAOPN10 RAOPN9
7
6
5
4
3
2
1
RAOPN7 RAOPN6 RAOPN5 RAOPN4 RAOPN3 RAOPN2 RAOPN18RAOPN80
RAOPN0OVPNRB
1800BAH

15
14
13
12
11
10
9
RBOPN15 RBOPN14 RBOPN13 RBOPN12 RBOPN11 RBOPN10 RBOPN9
7
6
5
4
3
2
1
RBOPN7 RBOPN6 RBOPN5 RBOPN4 RBOPN3 RBOPN2 RBOPN1

8
RBOPN80
RBOPN0de

OVPNRA
1800B8HOver pattern name bit (RAOPN15 to RAOPN0, RBOPN15 to RBOPN0)

RAOPN15~RAOPN0RBOPN15~RBOPN0

1800B8H
1800BAH

nfi

Designates pattern name data when the screen-over process repeating the character
pattern is set.
Bit 15~0
Bit 15~0

For Rotation Parameter A
For Rotation Parameter B

Co

The bit configuration is the same as when the data size of the pattern name table isone-word; and changes depending on the settings of the character size, character
color number, and character number supplement mode.

SE

GA

This register action is executed for the scroll screen by rotation parameter A and B,
but the character size that decides the bit configuration as well as the character
number supplement mode performs in RBG0 and RBG1. Therefore, be careful whensimultaneously displaying screens by rotation parameter A and B in RBG0.

116

4.11 Mosaic Process

de

nti
al

The mosaic process can be done for each screen using the scroll surface. The mosaic
size can be set for the respective horizontal and vertical directions. The mosaic
process divides each scroll screen into several areas of pre-determined size. Thisfunction displays all dots within various areas of colored dots in the upper left. The
mosaic pattern can be achieved by aligning different color areas. The size of themosaic area can be individually selected. Size in the horizontal direction can selectfrom 1 to 16 dots in single dot units. Size in the vertical direction can select from 1 to
16 dots in the non-interlace mode in single dot units, and 2 to 32 dots in the interlace
mode in two-dot units. If the register is set to do mosaic processing when in the
double-density interlace mode, the screen is made to display in the single-density
interlace mode.

nfi

When using the mosaic process in NBG0 or NBG1, the vertical cell scroll function
can no longer be used. Also, mosaic processing of RBG0 and RBG1 can only be donein the horizontal direction. Figure 4.19 shows the mosaic pattern.

Horizontal
Mosaic Size

Area A

Area B

Area CArea D

Figure 4.19 Mosaic Pattern

SE

GA

Co

VerticalMosaic Size

The color of dots in the upper-left corner of
each area is used for all dots in that area.

ST-58-R2

117

Mosaic Control Register

MZCTL
180022H15
MZSZV37~14
MZSZV26~13
MZSZV15~12
MZSZV04R0MZE11MZSZH33N3MZE

10MZSZH22
N2MZE

Mosaic size bit (MZSZH3 to MZSZH0, MZSZV3 to MZSZV0)180022H
180022H

Bit 15~12
Bit 11~8

MZSZH2MZSZH1MZSZH0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Co

GA
SE
118

8
MZSZH00
N0MZEFor vertical mosaic size
For horizontal mosaic size

Horizontal Mosaic Size

1 dot
2 dots3 dots4 dots5 dots
6 dots7 dots
8 dots9 dots
10 dots
11 dots
12 dots
13 dots
14 dots
15 dots
16 dotsnfi

MZSZH39
MZSZH11
N1MZEdeDesignates the horizontal and vertical mosaic size.
MZSZV3~MZSZV0MZSZH3~MZSZH0nti
al

The mosaic control register selects whether to perform the mosaic process. It is awrite-only 16-bit register and is in address 180022H. Because the value is cleared to
0 after the power is turned on or reset, be sure to set the value.

MZSZV3MZSZV2MZSZV1MZSZV0

Vertical Mosaic Size
Non-Interlace
Interlace

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1 dot
2 dots3 dots4 dots5 dots
6 dots7 dots
8 dots9 dots
10 dots
11 dots
12 dots
13 dots
14 dots
15 dots
16 dots

de

nti
al

2 dots4 dots
6 dots
8 dots
10 dots
12 dots
14 dots
16 dots
18 dots
20 dots
22 dots
24 dots
26 dots
28 dots
30 dots
32 dots

Note: There is no relationship with the interlace setting.

Mosaic enable bit (N0MZE, N1MZE, N2MZE, N3MZE, R0MZE)

xxMZE
0
1

180022H
180022H
180022H
180022H
180022H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0

Co

N0MZE
N1MZE
N2MZE
N3MZE
R0MZE

nfi

Designates the screen performing mosaic process.

Process
Does not execute mosaic process
Processes mosaic process

Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.

SE

GA

Only horizontal mosaic processing is performed when the mosaic process is in therotation scroll surface. If performing mosaic processing in the double-density interlace mode, the screen is made to be displayed by the single-density interlace mode.
If performing mosaic processing in NBG0 or NBG1, the mosaic screen will not beable to use the vertical cell-scroll function. As a result, the mosaic process is done on
the display screen for screens that don’t cell-scroll vertically.

ST-58-R2

119

nti
al

SE

GA

Co

nfi

de

(This page was blank in the original Japanese document)

120

nti
al

SE

GA

Co

nfi

de

Chapter 5 Normal Scroll Screen

ST-58-R2

Introduction.......................................................................... 122
5.1 Screen Scroll Function .................................................. 122
Screen Scroll Value Register ...................................... 123
5.2 Expansion/Contraction Function ................................... 126
Coordinate Increment Register .................................. 127
Reduction Enable Register ......................................... 129
5.3 Line and Vertical Cell Scroll Function ............................ 131
Line Scroll Function .................................................... 131
Vertical Cell Scroll Function ........................................ 134
Line and Vertical Cell Scroll Control Register............. 137
Line Scroll Table Address Register............................. 140
Vertical Cell Scroll Table Address Register ................ 141

121

Introductionntial

The normal scroll screen has four surfaces, NBG0 to NBG3; each surface can be
scrolled up and down, left and right. NBG0 and NBG1 can be expanded and reduced, line scrolled, and cell scrolled vertically.

5.1 Screen Scroll Function

nfi

de

All four surfaces of the normal scroll screen can dot scroll up, down, left, or right insurface units. The screen scroll value selects, in the screen scroll value register, thedot coordinates displayed in the upper left of the TV screen. The screen scroll value
is in effect up to and including values that don’t exceed the display area set for eachscreen. The display area of the screen is repeated when a value that exceeds thedisplay area is selected. The fractional part of the screen scroll value for NBG0 and
NBG1 is used only in calculating coordinates; the final display coordinate values are
discarded. The horizontal (X) coordinate is selected by the horizontal screen scroll
value integer part bit and horizontal screen scroll value fractional part bit. The
vertical (Y) coordinate is selected by the vertical screen scroll value integer part bit
and vertical screen scroll value fractional part bit. The fractional part bit is added
immediately below the integer bit. Figure 5.1 shows the bit configuration.

Horizontal and Vertical Screen Scroll Value Register (NBG0, NBG1)
26

15

Co

Bit 31

Integer Part

8

Fractional Part

Horizontal and Vertical Screen Scroll Value Register (NBG2, NBG3)
Bit 15100GAInteger partSE

Figure 5.1 Screen scroll value bit configuration

122

0Screen Scroll Value Register

SCXDN0180072H

15
14
13
12
11
10
9
8
N0SCXD1 N0SCXD2 N0SCXD3 N0SCXD4 N0SCXD5 N0SCXD6 N0SCXD7 N0SCXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SCYIN0180074H

15~
7
N0SCYI7SCYDN0180076H

15
14
13
12
11
10
9
8
N0SCYD1 N0SCYD2 N0SCYD3 N0SCYD4 N0SCYD5 N0SCYD6 N0SCYD7 N0SCYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SCXIN1
180080H

15~
7
N1SCXI7SCXDN1
180082H

15
14
13
12
11
10
9
8
N1SCXD1 N1SCXD2 N1SCXD3 N1SCXD4 N1SCXD5 N1SCXD6 N1SCXD7 N1SCXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

14
~
6
N0SCYI6

13~
5
N0SCYI512~4
N0SCXI412~
4N0SCYI413~
5
N1SCXI512~4N1SCXI4

GA

Co

14
~
6
N1SCXI6

13~
5
N0SCXI51110
9~N0SCYI10 N0SCYI932
1
N0SCYI3 N0SCYI2 N0SCYI113~5
N1SCYI512~4N1SCYI41110
9~N1SCXI10 N1SCXI9321
N1SCXI3 N1SCXI2 N1SCXI1

11
10
9
~
N1SCYI10 N1SCYI9321
N1SCYI3 N1SCYI2 N1SCYI18N0SCXI80
N0SCXI08
N0SCYI80
N0SCYI08
N1SCXI80N1SCXI0SCYIN1
180084H

15~
7N1SCYI78N1SCYI80
N1SCYI0SCYDN1
180086H

15
14
13
12
11
10
9
8
N1SCYD1 N1SCYD2 N1SCYD3 N1SCYD4 N1SCYD5 N1SCYD6 N1SCYD7 N1SCYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SE

14
~
6
N1SCYI61110
9~N0SCXI10 N0SCXI9321
N0SCXI3 N0SCXI2 N0SCXI1deSCXIN0180070H

15~
7
N0SCXI7

nfi

14
~
6
N0SCXI6

ntial

The screen scroll value register designates the screen scroll value. It is a write-only
16- or 32-bit register located at addresses 180070H to 180076H, 180080H to 180086H,
and 180090H to 180096H. Because the value is cleared to 0, it must be set after
power on or reset.

ST-58-R2

123

15
~
7
N2SCX714~
6
N2SCX613~
5
N2SCX512~
4N2SCX411~
3
N2SCX310
N2SCX102
N2SCX29
N2SCX91
N2SCX18N2SCX80N2SCX0SCYN2180092H

15~
7
N2SCY714~
6N2SCY613~
5N2SCY512~4N2SCY411~
3
N2SCY310
N2SCY102
N2SCY29N2SCY91
N2SCY18N2SCY80N2SCY0SCXN3180094H

15~
7
N3SCX714~
6
N3SCX613~
5
N3SCX512~
4
N3SCX4

11~
3
N3SCX310
N3SCX10
2
N3SCX29N3SCX91
N3SCX18
N3SCX80N3SCX0SCYN3180096H

15~
7N3SCY714~
6N3SCY613~
5N3SCY512~4N3SCY411~
3
N3SCY310
N3SCY102
N3SCY29N3SCY91
N3SCY18
N3SCY80N3SCY0

nfi

de

nti
al

SCXN2
180090H

Screen scroll value bit: Scroll bit (N0SCXI10 to N0SCXI0, N0SCXD1 to
N0SCXD8, N0SCYI10 to N0SCYI0, N0SCYD1 to N0SCYD8, N1SCXI10 to N1SCXI0, N1SCXD1 to
N1SCXD8, N1SCYI10 to N1SCYI0, N1SCYD1 to N1SCYD8, N2SCX10 to N2SCX0, N2SCY10 to
N2SCY0, N3SCX10 to N3SCX0, N3SCY10 to N3SCY0)180070H
180072H
180074H
180076H
180080H
180082H
180084H
180086H
180090H
180092H
180094H
180096H

Bit 10~0
Bit 15~8
Bit 10~0
Bit 15~8
Bit 10~0
Bit 15~8
Bit 10~0
Bit 15~8
Bit 10~0
Bit 10~0
Bit 10~0
Bit 10~0SE

GA

N0SCXI10~N0SCXI0N0SCXD1~N0SCXD8N0SCYI10~N0SCYI0
N0SCYD1~N0SCYD8N1SCXI10~N1SCXI0N1SCXD1~N1SCXD8N1SCYI10~N1SCYI0N1SCYD1~N1SCYD8N2SCX10~N2SCX0N2SCY10~N2SCY0N3SCX10~N3SCX0
N3SCY10~N3SCY0

Co

Designates the horizontal and vertical screen scroll values (coordinate values) of theNormal scroll screen.

124

For NBG0 horizontal direction (integer part)
For NBG0 horizontal direction (fractional part)
For NBG0 vertical direction (integer part)
For NBG0 vertical direction (fractional part)
For NBG1 horizontal direction (integer part)
For NBG1 horizontal direction (fractional part)
For NBG1 vertical direction (integer part)
For NBG1 vertical direction (fractional part)
For NBG2 horizontal direction
For NBG2 vertical direction
For NBG3 horizontal direction
For NBG3 vertical direction

SE

GA

Co

nfi

de

nti
al

The value of the screen scroll value register is effective up to a range not exceeding
the display area of each screen. When the display area is exceeded, the screen of thedisplay area is repeatedly displayed. All screen scroll values must be identified as
positive values. By changing the value during the horizontal retrace, the scroll value
can also be changed in the middle of the image screen.

ST-58-R2

125

5.2 Expansion/Contraction Function

Display coordinates are calculated by the expressions below.
Note: the fractional part of the calculated results are discarded.

ntial

NBG0 and NBG1 can expand and reduce the entire screen both horizontally andvertically. Controlling expansion and reduction is done by selecting horizontal andvertical coordinate increments required in display coordinate calculations. When
reducing in horizontally, the reduction enable register must be set as certain screenscannot be displayed, depending on this setting.

de(display coordinate value X) = (coordinate increment X) X (H counter value) + (screen scroll value X)(display coordinate value Y) = (coordinate increment Y) X (V counter value) + (screen scroll value Y)

nfi

Screen expansion and reduction are controlled by setting the horizontal and verticalcoordinate increments in the coordinate increment register. The horizontal coordinate increment is selected by the horizontal coordinate increment integer part bit
and horizontal coordinate increment fractional part bit. The vertical coordinate
increment is selected by the vertical coordinate increment integer part bit and horizontal coordinate increment fractional part bit.

Co

The fractional part bit is added immediately below the integer bit part. Figure 5.2
shows the bit configuration
Hor izon tal and Ver tical Coo rdi na te Incr em ent s
Bit 3118

15

Int ege r Part

8

Fr act iona l PartSE

GA

Figure 5.2 Configuration of coordinate increment register.

126

0Coordinate Increment RegisterZMYDN018007EH

ZMXIN1
180088HZMYIN1
18008CH

11
~
3
~

10
9
8
~
~
~
2
1
0
N0ZMXI2 N0ZMXI1 N0ZMXI0

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N0ZMYI2 N0ZMYI1 N0ZMYI0

15
14
13
12
11
10
9
8
N0ZMYD1 N0ZMYD2 N0ZMYD3 N0ZMYD4 N0ZMYD5 N0ZMYD6 N0ZMYD7 N0ZMYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N1ZMXI2 N1ZMXI1 N1ZMXI0

15
14
13
12
11
10
9
8
N1ZMXD1 N1ZMXD2 N1ZMXD3 N1ZMXD4 N1ZMXD5 N1ZMXD6 N1ZMXD7 N1ZMXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N1ZMYI2 N1ZMYI1 N1ZMYI0

15
14
13
12
11
10
9
8
N1ZMYD1 N1ZMYD2 N1ZMYD3 N1ZMYD4 N1ZMYD5 N1ZMYD6 N1ZMYD7 N1ZMYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SE

ZMYDN1
18008EH

12
~
4
~

15
14
13
12
11
10
9
8
N0ZMXD1 N0ZMXD2 N0ZMXD3 N0ZMXD4 N0ZMXD5 N0ZMXD6 N0ZMXD7 N0ZMXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

GA

ZMXDN1
18008AH

13
~
5
~

de

ZMYIN018007CH

14
~
6
~

nfi

ZMXDN018007AH

15
~
7
~

Co

ZMXIN0180078Hntial

The coordinate increment register designates the coordinate increment when calculating the coordinates of the scroll screen. This is a write-only 32-bit register locatedat addresses 180078H to 18007EH, and 180088H to 18008EH. Because the value ofthe register is cleared to 0 after power on or reset, the value must be set.

ST-58-R2

127

Coordinate increment bit: Zoom bit (N0ZMXI2 to N0ZMXI0, N0ZMXD1 to
N0ZMXD8, N0ZMYI2 to N0ZMYI0, N0ZMYD1 to N0ZMYD8, N1ZMXI2 to N1ZMXI0, N1ZMXD1 to
N1ZMXD8, N1ZMYI2 to N1ZMYI0, N1ZMYD1 to N1ZMYD8)N0ZMXI2~N0ZMXI0N0ZMXD1~N0ZMXD8N0ZMYI2~N0ZMYI0
N0ZMYD1~N0ZMYD8N1ZMXI2~N1ZMXI0N1ZMXD1~N1ZMXD8N1ZMYI2~N1ZMYI0N1ZMYD1~N1ZMYD8180078H
18007AH
18007CH
18007EH
180088H
18008AH
18008CH
18008EH

Bit 2~0
Bit 15~8
Bit 2~0
Bit 15~8
Bit 2~0
Bit 15~8
Bit 2~0
Bit 15~8nti
alDesignates horizontal and vertical coordinate increments for calculating display
coordinates when expanding and reducing all Normal scroll screens.

For NBG0 horizontal direction (integer part)
For NBG0 horizontal direction (fractional part)
For NBG0 vertical direction (integer part)
For NBG0 vertical direction (fractional part)
For NBG1 horizontal direction (integer part)
For NBG1 horizontal direction (fractional part)
For NBG1 vertical direction (integer part)
For NBG1 vertical direction (fractional part)deThe coordinate increment should be a value smaller than “1” in the expansion display, and larger than “1” in the reduction display. The normal display is when thecoordinate increment is 1. Selections are all by positive values. The coordinate partsof NBG2 and NBG3 are fixed at “1”.

nfi

By changing the value during the horizontal retrace, the coordinate increment value
can also be changed.

Co

The reduction enable register must be set when reduction display is horizontal.
Depending on the setting of the reduction enable bit, do not set horizontal coordinate increment to a value other than the set range decided upon. Table 5.1 shows
coordinate increments and reduction settings in the horizontal direction.
Table 5.1 Horizontal coordinate increments and reduction settings

SE

GA

Horizontal Reduction Display Setting
Not allowed
Up to 1/2
Up to 1/4

128

Horizontal Coordinate Increment Setting Range
0 ≤ (Horizontal Coordinate Increment) ≤ 1
0 ≤ (Horizontal Coordinate Increment) ≤ 2
0 ≤ (Horizontal Coordinate Increment) ≤ 4

Reduction Enable Register

ZMCTL
180098H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

nti
al

The reduction enable register is a write-only 16 bit register that controls the horizontal reduction display, and is located at address 180098H. Because the value of theregister is cleared to 0 after power on or reset, the value must be set.
10
~
2
~

9
N1ZMQT
1
N0ZMQT

8
N1ZMHF
0N0ZMHF

Reduction enable bit: Zoom quarter/half bit (N1ZMQT, N1ZMHF, N0ZMQT, N0ZMHF)

N0ZMHF
N0ZMQT
N1ZMHF
N1ZMQTde

Designates the maximum reducible range of each Normal scroll screen in the horizontal direction.
180098H
180098H
180098H
180098H

Bit 0
Bit 1
Bit 8
Bit 9

NxZMHF
0
1

Horizontal Reduction Display
Not allowed
Up to 1/2

10

Up to 1/4

1

1

Up to 1/4

Restriction Items
None
The number of character colors can be
set for 16 or 256 colors only.
The number of character colors can be
set for 16 colors only.
The number of character colors can be
set for 16 colors only.

Co

nfi

NxZMQT
00

For NBG0
For NBG0
For NBG1
For NBG1

Note: 0 or 1 is entered in bit name for x.

SEGA

For reduction of up to 1/2, set the corresponding screen character color count (bitmap pattern color count) to 16 or 256 colors. For reduction of up to 1/4, set to 16
colors. The horizontal coordinate increment should not exceed the set range of thesebits.

ST-58-R2

129

nti
al

Certain screens cannot display depending on the reduction setting. Limits areshown in Table 5.2.
Table 5.2

Display screen limits by setting of reduction enable bit

ScreenCharacter Color Count(Bitmap Color Count)
16 Colors

NBG0
256 Colors
16 Colors
NBG1

Up to 1/2
Up to 1/4
Up to 1/2
Up to 1/2
Up to 1/4
Up to 1/2

Screens That Cannot
Display
None
NBG2
NBG2
None
NBG3
NBG3

SE

GA

Co

nfi

de

256 Colors

Reduction Enable Setting

130

5.3 Line and Vertical Cell Scroll Functionnti
alWithin the Normal scroll screen, there is a line scroll function and vertical cell scroll
function in NBG0 and NBG1. The line scroll function selects the horizontal andvertical screen scroll value and horizontal coordinate increment in line units. The
vertical cell scroll function selects the vertical screen scroll value in horizontal cell
units. Both functions can be used without relationship to the cell format and bit map
format.
Line Scroll Function

nfi

de

The line scroll function selects the horizontal and vertical screen scroll value andhorizontal coordinate increment in line units, and specifies by line scroll tables
stored in VRAM. Data values of line scroll tables are designated by relative values.
To values stored in line scroll tables, values selected in the screen scroll value registerare added, becoming display coordinates. The table data read interval can be selected from four types, one line, two line, four line, and eight line. Values of thevertical coordinate increment register are used for vertical coordinate calculations
when two-line intervals or greater are selected.

Co

The horizontal coordinate increment should not set a value that the exceeds thesetting of the reduction enable register. The line scroll function is shown in Figure
5.3.
Line Scroll Table (VRAM)

Horizontal Screen Scroll value
for 1st line

Horizontal
Coordinate
Increment

Vertical Screen Scroll value for1st line
Horiz. Coordinate
increment for 1st line
Horizontal Screen Scroll value
for 2nd line

Scroll Screen
1st Line
2nd Line
3rd Line
4th Line
5th Line

GA

Vertical Screen Scroll value
for 2nd lineSE

Horiz. Coordinate
increment for 2nd line

Figure 5.3 Line scroll function

Line scroll tables store from small addresses in order of the horizontal screen scroll
value, vertical screen scroll value, and horizontal coordinate increments. Stored line
scroll data is only composed of data required by the line scroll register setting.

ST-58-R2

131

Bit 15+OH
Bit 15
+2H

8

7

6
5
4
3
2
Intege r Part : 11 b its

1

0

14 13 12 11 10 98
Fr act iona l Part : 8 bit s

7

6

5

4

3

1

0

7

6

5

4

de

Hor izon tal , Vert ica l Scr ee n Scro ll Va lue
14 13 12 11109

Hor izon tal Coo rdi na te Incr em en t
Bit 1514 13 12 11

10

9

8

+0H

3

2

2

1

0

Integ er Part : 3 bi ts

14 13 12 11 10 98
Fr act iona l Part : 8 bi ts

No te: Shad ed ar ea s ar e ig no re d

7

6

5

4

3

2

1

0

nfi

Bit 15+2H

ntialEach horizontal screen scroll value, vertical screen scroll value, and horizontal coordinate increment configuration is identical to the data configuration set in eachregister. Figure 5.4 shows the bit configuration of line scroll table data. Table 5.5
shows the configuration of line scroll tables.

SE

GA

Co

Figure 5.4 Bit configuration of line scroll table data132

When selecting horizontal and vertical screen scroll values andhorizontal coordinate increment for every 1 line.
Bit 15
Line Scroll Table (VRAM)+00H Line 1 Horiz. Screen Scroll Value (Integer Part)

0

nti
al

Line Scroll Table
Address+02H Line 1 Horiz. Screen Scroll Value (Fractional Part)+04H Line 1 Vertical Screen Scroll Value (Integer Part)+06H Line 1 Vertical Screen Scroll Value (Fractional Part)+08H Line 1 Horiz. Coordinate Increment (Integer Part)+0AH Line 1 Horiz. Coordinate Increment (Fractional Part)+0CH Line 2 Horiz. Screen Scroll Value (Integer Part)+0EH Line 2 Horiz. Screen Scroll Value (Fractional Part)+10H Line 2 Vertical Screen Scroll Value (Integer Part)de+12H Line 2 Vertical Screen Scroll Value (Fractional Part)+14H Line 2 Horiz. Coordinate Increment (Integer Part)+16H Line 2 Horiz. Coordinate Increment (Fractional Part)

When selecting vertical screen scroll value and horizontal coordinate
increment for every 2 lines (no horizontal line scroll).

Bit 15
Line Scroll Table (VRAM)+00H Line 1 Vertical Screen Scroll Value (Integer Part)

nfi

Line Scroll Table
Address

0+02H Line 1 Vertical Screen Scroll Value (Fractional Part)+04H Line 1, 2 Horiz. Coordinate Increment (Integer Part)+06H Line 1, 2 Horiz. Coordinate Increment (Fractional Part)

Co+08H Line 3 Vertical Screen Scroll Value (Integer Part)+0AH Line 3 Vertical Screen Scroll Value (Fractional Part)+0CH Line 3, 4 Horiz. Coordinate Increment (Integer Part)+0EH Line 3, 4 Horiz. Coordinate Increment (Fractional Part)

Note: Display coordinates in the vertical direction for lines not
specified are obtained by adding coordinate increments in thevertical direction to the vertical screen scroll values for the lines
specified.

GA

When selecting horizontal screen scroll value and horizontal
coordinate increment for every 4 lines (no horizontal line scroll).
Line Scroll Table (VRAM)
Bit 15

SE

Line Scroll Table
Address

ST-58-R2

0+00H Line 1~4 Horiz. Screen Scroll Value (Integer Part)+02H Line 1~4 Horiz. Screen Scroll Value (Fractional Part)+04H Line 1~4 Horiz. Coordinate Increment (Integer Part)+06H Line 1~4 Horiz. Coordinate Increment (Fractional Part)+08H Line 5~8 Horiz. Screen Scroll Value (Integer Part)+0AH Line 5~8 Horiz. Screen Scroll Value (Fractional Part)+0CH Line 5~8 Lines Horiz. Coordinate Increment (Integer Part)+0EH Line 5~8 Lines Horiz. Coordinate Increment (Fractional Part)

Figure 5.5 Line scroll table

133

Vertical Cell Scroll Functionnti
al

The vertical cell scroll function selects the vertical screen scroll value in horizontal
cell units in each vertically separated area, and is selected by the vertical cell scroll
table stored in VRAM. The data value of the vertical cell scroll table is designated byrelative values. The value selected by the screen scroll value register is added to thescreen scroll value stored in the vertical cell scroll table, becoming the display coordinate. Selection can be done in horizontal 8 dot units when displaying in bit map
format.

de

NBG0 and NBG1 have the only vertical cell scroll functions inside the Normal scroll
screen. This vertical cell scroll function and mosaic function can not be used simultaneously; the mosaic function has priority. Figure 5.6 shows the vertical cell scroll
function.
Ver tical Cell Scro ll Tabl e (VRAM)
1st Cel l Ver tica l
Scr een Scr ol l Val ue

nfi

2nd Cel l Ver tical
Scre en Scr ol l Val ue
3r d Cel l Ver tical
Scr ee n Scr ol l Val ue

Co

TV Scr een

GA

Vert ica l Scr ee n Scro l va lue -e na bl ed ar ea for the 1st cel lFigure 5.6 Vertical cell scroll function

The bit configuration of the vertical screen scroll value is the same when set in all
registers. Data of the vertical cell scroll table is treated as a table in the order fromdata in the left side cell of the TV screen.

SE

When both NBG0 and NBG1 use the vertical cell scroll function, the various verticalcell scroll table data should be alternately stored in NBG0 and NBG1, one cell at a
time.

134

Vertical Screen Scroll Value
Bit 15

14

13

12

11

10

9

8

7

14

13 12 11 10 9
8 bit fractional part

8

7

+0H

Bit 15
+2H

6

5

4

3

2

1

0

2

1

0

Data configuration on the vertical cell scroll table

SE

GA

Co

nfi

Figure 5.7

6
54
3
11 bit integer partdeNote: Shaded area is ignoredntialFigure 5.7 shows the bit configuration of the vertical cell scroll table data. Figure 5.8
shows the vertical cell scroll table configuration.

ST-58-R2

135

NBG0 Vertical Cell Scroll
Bit 15
Vertical Cell Scroll Table (VRAM)+00H NBG0 1st cell vertical screen scroll value (integer part)

0

nti
al

Vertical Cell Scroll
Table Address+02H NBG0 1st cell vertical screen scroll value (fractional part)+04H NBG0 2nd cell vertical screen scroll value (integer part)+06H NBG0 2nd cell vertical screen scroll value (fractional part)+08H NBG0 3rd cell vertical screen scroll value (integer part)+0AH NBG0 3rd cell vertical screen scroll value (fractional part)+0CH NBG0 4th cell vertical screen scroll value (integer part)+0EH NBG0 4th cell vertical screen scroll value (fractional part)

NBG1 Vertical Cell Scroll
Bit 15

Vertical Cell Scroll Table (VRAM)

0

+00H

NBG1 1st cell vertical screen scroll value (integer part)+02H

NBG1 1st cell vertical screen scroll value (fractional part)+04H

NBG1 2nd cell vertical screen scroll value (integer part)+06H

NBG1 2nd cell vertical screen scroll value (fractional part)+08H

NBG1 3rd cell vertical screen scroll value (integer part)nfi

Vertical Cell Scroll
Table Addressde+10H NBG0 5th cell vertical screen scroll value (integer part)+12H NBG0 5th cell vertical screen scroll value (fractional part)+0AH NBG1 3rd cell vertical screen scroll value (fractional part)+0CH NBG1 4th cell vertical screen scroll value (integer part)Co+0EH NBG1 4th cell vertical screen scroll value (fractional part)+10H NBG1 5th cell vertical screen scroll value (integer part)+12H

NBG1 5th cell vertical screen scroll value (fractional part)

NBG0 and NBG1 Vertical Cell Scroll
Bit 15
Vertical Cell Scroll
Table Address

Vertical Cell Scroll Table (VRAM)

0+00H NBG0 1st cell vertical screen scroll value (integer part)+02H NBG0 1st cell vertical screen scroll value (fractional part)+04H NBG1 1st cell vertical screen scroll value (integer part)

GA+06H NBG1 1st cell vertical screen scroll value (fractional part)+08H NBG0 2nd cell vertical screen scroll value (integer part)+0AH NBG0 2nd cell vertical screen scroll value (fractional part)+0CH NBG1 2nd cell vertical screen scroll value (integer part)+0EH NBG1 2nd cell vertical screen scroll value (fractional part)SE+10H NBG0 3rd cell vertical screen scroll value (integer part)+12H NBG0 3rd cell vertical screen scroll value (fractional part)

136

Figure 5.8 Vertical cell scroll tableLine and Vertical Cell Scroll Control Register

SCRCTL
18009AH

15
~
7
~

14
~
6
~

13
N1LSS1
5
N0LSS112N1LSS04
N0LSS0nti
al

The line and vertical cell scroll control register is a write-only 16-bit register that
controls the line scroll function and vertical cell scroll function, and is at address
18009AH. Because the value of the register is cleared to 0 after the power is turnedon or reset, the value must be set.
11
N1LZMX
3
N0LZMX

10
N1LSCY
2
N0LSCY

9N1LSCX
1
N0LSCX

8
N1VCSC0
N0VCSCLine Scroll Interval Bit: Line scroll select bit (N0LSS1, N0LSS0, N1LSS1, N1LSS0)

18009AH
18009AHNxLSS1NxLSS0

0
0
1
1

0
1
0
1

Interlace Setting
Non-Interlace
Each line
Every 2 lines
Every 4 lines
Every 8 lines

Bit 5, 4
Bit 13,12

For NBG0
For NBG1

Single-Density Interlace
Every 2 lines
Every 4 lines
Every 8 lines
Every 16 lines

Double-Density Interlace
Each line
Every 2 lines
Every 4 lines
Every 8 lines

nfi

N0LSS1, N0LSS0N1LSS1, N1LSS0

deDesignates the interval that reads line scroll table data from the table. The intervalchanges depending on the interlace of the TV screen.

Co

Note: 0 or 1 is entered in bit name for x.

SEGA

When reading line scroll table data at intervals of two lines or greater, line horizontal
scroll screen value not read and horizontal coordinate increments use line scroll datathat has been previously read. The vertical scroll screen value is calculated fromvertical coordinate increment register value and line scroll data that was previously
read.

ST-58-R2

137

Line zoom enable bit: Line zoom X enable bit (N1LZMX, N0LZMX)

Designates whether expansion-reduction is done horizontally in line units.
18009AH
18009AHNxLZMX01

Bit 3
Bit 11For NBG0
For NBG1ntial

N0LZMX
N1LSCX

Process
Does not scale horizontally per line units
Scales horizontally per line units

Note: 0 or 1 is entered in bit name for x.

deWhen using this function, the horizontal coordinate increment must be stored in theline scroll table of VRAM. Make sure that the horizontal coordinate increment does
not exceed the reduction setting.
Line scroll enable bit (for the vertical screen scroll value): Line scroll Y enable bit (N1LSCY,
N0LSCY)

Designates whether scroll is performed by vertical line units.
18009AH
18009AH

NxLSCY01

Bit 2
Bit 10For NBG0
For NBG1

nfi

N0LSCYN1LSCY

Process
Does not scroll vertically per line units
Scrolls vertically per line units

Co

Note: 0 or 1 is entered in bit name for x.

SEGA

When using this function, the vertical screen scroll value must be stored in the line
scroll table of VRAM.

138

Line scroll enable bit (for the horizontal screen scroll value): Line scroll X enable bit (N1LSCX,
N0LSCX)

N0LSCX
N1LSCX

18009AH
18009AH

Bit 1
Bit 9

NxLSCX01

ntialDesignates whether scroll is performed by horizontal line units.

For NBG0
For NBG1

Process
Does not scroll horizontally per line units
Scrolls horizontally per line units

Note: 0 or 1 is entered in bit name for x.

deWhen using this function, be sure to store the horizontal scroll screen value in the
VRAM line scroll table.
Vertical cell scroll enable bit (N1VCSC, N0VCSC)

Designates whether to perform vertical cell scroll.
18009AH
18009AH

Bit 0
Bit 8

For NBG0
For NBG1

nfi

N0VCSCN1VCSCNxVCSC0
1

Process
Does not cell-scroll vertically
Cell-scrolls verticallyNote: 0 or 1 is entered in bit name for x.

SE

GA

Co

When using the vertical cell scroll function, make sure the access command of thevertical cell scroll table data read is designated in the VRAM cycle pattern register.
In addition, vertical cell scroll data must be stored in VRAM. The vertical cell scroll
function cannot be used simultaneously with the mosaic function; the mosaic function has priority.

ST-58-R2

139

Line Scroll Table Address Register

15
~
7
~

LSTA0L
1800A2H

15
14
13
12
11
10
9
N0LSTA15 N0LSTA14 N0LSTA13 N0LSTA12 N0LSTA11 N0LSTA10 N0LSTA9
7
6
5
4
3
2
1
N0LSTA7 N0LSTA6 N0LSTA5 N0LSTA4 N0LSTA3 N0LSTA2 N0LSTA1

LSTA1U
1800A4H

15~
7~

LSTA1L
1800A6H

15
14
13
12
11
10
9
N1LSTA15 N1LSTA14 N1LSTA13 N1LSTA12 N1LSTA11 N1LSTA10 N1LSTA9
7
6
5
4
3
2
1
N1LSTA7 N1LSTA6 N1LSTA5 N1LSTA4 N1LSTA3 N1LSTA2 N1LSTA1

13
~
5
~

12
~
4
~

12
~
4
~

11
~
3
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N0LSTA18 N0LSTA17 N0LSTA168
N0LSTA8
0
~

10
9
8
~
~
~
2
1
0
N1LSTA18 N1LSTA17 N1LSTA16

nfi

14
~
6
~

13
~
5
~

de

LSTA0U
1800A0H

Co

14
~
6
~

nti
al

The line scroll table address register is a write-only 32-bit register that selects thelead address of the line scroll table, and is at addresses 1800A0H to 1800A6H. Because the value of the register is cleared to 0 after power on or reset, the value must
be set.

8
N1LSTA80~Line scroll table address bit (N0LSTA18 to N0LSTA16, N0LSTA15 to N0LSTA1, N1LSTA18 to
N1LSTA16, N1LSTA15 to N1LSTA1)

Designates the lead address of the line scroll table on the VRAM.
N0LSTA18~N0LSTA16
N0LSTA15~N0LSTA1
N1LSTA18~N1LSTA16
N1LSTA15~N1LSTA1

1800A0H
1800A2H
1800A4H
1800A6H

Bit 2~0
Bit 15~1
Bit 2~0
Bit 15~1

For NBG0 (upper bit)
For NBG0 (lower bit)
For NBG1 (upper bit)
For NBG1 (lower bit)GA

The actual lead VRAM address is calculated by the expression below. When the
VRAM has a 4 Mbit capacity, the address of the most significant bit is ignored.

SE(line scroll table lead address)= (line scroll table address register value 18 bit) X 4H

140

Vertical Cell Scroll Table Address Register

15
~
7
~

VCSTAU
18009CH

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
VCSTA18 VCSTA17 VCSTA16

15
14
13
12
11
10
VCSTA15 VCSTA14 VCSTA13 VCSTA12 VCSTA11 VCSTA10
7
6
5
4
3
2
VCSTA7 VCSTA6 VCSTA5 VCSTA4 VCSTA3 VCSTA2deVCSTAL
18009EH

14
~
6
~

nti
al

The vertical cell scroll table address register is a write-only 32-bit register that selects
the lead address of the vertical cell scroll table, and is at addresses 18009CH to18009EH. Because the value of the register is cleared to 0 after power on or reset, thevalue must be set.

9
VCSTA91
VCSTA1

8
VCSTA80~

Vertical cell scroll table address bit (VCSTA18 to VCSTA1),

Designates the lead address of the vertical cell scroll table on the VRAM.
18009CH
18009EH

Bit 2~0
Bit 15~1

nfi

VCSTA18~VCSTA16
VCSTA15~VCSTA1

The actual lead VRAM address is calculated by the expression below. When the
VRAM has a 4 Mbit capacity, the address of the most significant bit is ignored.

SE

GA

Co

(vertical cell scroll table lead address)= (vertical cell scroll table address register value 18 bit) X 4H

ST-58-R2

141

nti
al

SE

GA

Co

nfi

de

(This page is blank in the original Japanese document)

142

nti
al

Co

nfi

de

Chapter 6 Rotation Scroll Screen

SE

GA

Introduction ............................................................................. 144
6.1 Rotation Scroll Coordinate Operation ............................... 144
6.2 Rotation Scroll Screen Display Control ............................ 148
RAM Control Register ................................................... 148
6.3 Rotation Parameter Control .............................................. 151
Data Configuration of the Rotation Parameter Table .... 153
Rotation Parameter Table ............................................. 155
Rotation Parameter Read Control Register .................. 157
Rotation Parameter Table Address Register ................. 158
Rotation Read Out of the Frame Buffer ........................ 159
Rotation Parameter Change ......................................... 160
Rotation Parameter Mode Register .............................. 162
6.4 Coefficient Table Control ................................................... 163
Line Color Screen Data ................................................. 164
Bit Configuration of Coefficient Table Data ................... 165
Coefficient Table Lead Address..................................... 165
Most Significant Bit of Coefficient Data ......................... 166
RAM Control Register ................................................... 167
Coefficient Table Control Register................................. 168
Coefficient Table Address Offset Register ..................... 170

ST-58-R2

143

Introductionntial

The rotation scroll screen has two sets of parameter tables called “Rotation parameter A” and “Rotation parameter B” that can be simultaneously displayed by various
parameter tables. Besides being stored as rotation parameters in VRAM, the two
sets of parameters can hold various correlated coefficient tables in VRAM.

Table 6.1 Rotation scroll screen
ScreenRBG0

Not allowed (RBG0 must also be
displayed)

In Relation to Rotation Parameters
Screen specified by either rotation parameter
A or B, or 2 screens specified by rotation
parameters A and B are displayed concurrently
Screen specified by rotation parameter B isdisplayed

nfi

RBG1

Single Display
AlloweddeThere are two sets of rotation parameters, rotation parameter A and rotation parameter B, each stored in a table. RBG0 can simultaneously display one screen selectedby rotation parameter A or rotation parameter B, or two screens selected by rotation
parameter A and rotation parameter B. RBG1 can display only the screen designated by rotation parameter B. Table 6.1 shows the relationship between the rotation
scroll screen and rotation parameters.

Co

Rotation parameter A and rotation parameter B can each have a coefficient table;
there can be multiple displays by reading the coefficient data in each line or eachdot. Using rotation parameter A, expansion-reduction rotation of sprite frame
buffers can also be done.

6.1 Rotation Scroll Coordinate Calculation

SEGA

The display screen of the rotation scroll screen, which causes rotational conversion(including parallel moving) of the viewpoint reference center point and TV screen, isa collection of points intersecting the line of vision that passes through the TV screen
from the viewpoint after conversion with the fixed scroll map. Figure 6.1 shows
display method of the rotation scroll screen.

144

nti
al

Z

View po in t after conve rsio n (Xp, Yp, Zp)

Vie wpoi nt bef ore con ver si on (Px, Py, Pz)

Cent ra l po in t (Cx, Cy, Cz)

X
Poi nt on the scr ee n bef or e
co nve rsi on (Sx, Sy, Sz)dePoint on the scr een aftercon ver si on (Xs, Ys, Zs)
Y

Poin t disp laye d on the scro ll ma p
(X , Y, Z)

nfi

Not e: X axi s run s ve rt ica l y thr ou gh the pag e to the back.

Figure 6.1 Rotation scroll screen display method

Xp
Yp
Zp

=

A B C

Px - Cx

D E F
G H I

Py - CyPz - Cz

A B C
D E F

Sx - Cx
Sy - Cy

GA

Xs
Ys

Co

From the rotation conversion formula, view coordinates and TV screen coordinates
after conversion are expressed by the following equations.

=

Zs

SE

A, B, C, D, E, F, G, H, I:
Px, Py, Pz:
Sx, Sy, Sz:
Cx, Cy, Cz:
Mx, My, Mz:
Xp, Yp, Zp:
Xs, Ys, Zs:

ST-58-R2

G H I

Sz - Cz

Cz
+

+

Cy

Mx
+

My

Cz

Mz

Cz
Cy

Mx
My

Cz

+

Mz

Rotational matrix parameter
View coordinate before rotational conversion
TV screen coordinates before rotational conversion
Rotational center coordinate
Amount of parallel movement
View coordinate after rotational conversion
TV screen coordinates after rotational conversion

145

X - Xp
Xs - Xp =Y - YpYs - Yp =Z - ZpZs - Zp

nti
al

The line of vision that passes through the TV screen after rotational conversion, fromthe viewpoint after rotational conversion, is expressed by the equation below.

Because the scroll map is fixed by the XY plane (Z = 0), display coordinates (X, Y) on
the scroll map are found by the equation below.
X = k (Xs – Xp) + Xp
Y = k (Ys – Yp) + Yp

deHowever,-Zpk=
Zs - Zp

nfi

This “k”, called the perspective conversion coefficient, rotates only in the verticaldirection of the TV screen along the X axis rotation and is fixed in the horizontal
direction. Furthermore, the Y axis rotation only changes in the horizontal directionof the TV screen, and is fixed in the vertical direction. Z axis rotation is always fixed.

a b 0

Sx
Sy

=

c d 0
0 0 1

Hcnt - Csx
Vcnt - Csy
0

GA

Sz

Co

Because the screen prior to rotational conversion is normally identical to the TV
screen, Sx is the horizontal coordinate value (H counter value) in the TV screen, Sy isthe vertical coordinate value (V counter value) in the TV screen, and Sz is 0. The
screen coordinate value when the screen rotates in the vertical axis (SZ axis) is foundby the equations below.

a, b, c, d:Hcnt, Vcnt:
Csx, Csy:
Msx, Msy, Msz:

+

Csx
Csy
0

TV screen rotation matrix parameter
HV counter value
TV screen rotation center coordinate
TV screen parallel movement amountThe previously mentioned expression is as shown below.

SE

Sx = Xst + DX • Hcnt + DXst • Vcnt
Sy = Yst + DY • Hcnt + DYst • Vcnt
Sz = Zst

However,146

Xst = –a • Csx – b • Csy + Csx + Msx
Yst = –c • Csx – d • Csy + Csy + Msy

Msx
+

Msy
Msz

nti
al

Zst = Msz
∆X = a∆Y = c∆Xst = b∆Yst = dXst, Yst, Zst:
DX, DY:
DXst, DYst:

TV screen start coordinate
TV screen horizontal coordinate increment
TV screen vertical coordinate increment

X = kx (Xsp + dX • Hcnt) + Xp
Y = ky (Ysp + dY • Hcnt) + Yp

However,deBelow are the calculation equations of the display coordinates (X, Y) when performing both TV screen 3 axis rotation and TV screen rotation from the equations above.

TV screen start coordinates
TV screen vertical coordinate increments
TV screen horizontal coordinate increments
Rotational matrix parameter
View coordinates
Center coordinates
Amount of parallel movement
Expansion reduction coefficient
HV counter value

Co

Xst, Yst, Zst:
∆Xst, ∆Yst:∆X, ∆Y:
A, B, C, D, E, F:
Px, Py, Pz:
Cx, Cy, Cz:
Mx, My:kx, ky:Hcnt, Vcnt:

nfi

Xsp = A{(Xst + ∆Xst • Vcnt) – Px} + B{(Yst + ∆Yst • Vcnt) – Py} + C(Zst – Pz)
Ysp = D{(Xst + ∆Xst • Vcnt) – Px} + E{(Yst + ∆Yst • Vcnt) – Py} + F(Zst – Pz)
Xp = A(Px – Cx) + B(Py – Cy) + C(Pz – Cz) + Cx + Mx
Yp = D(Px – Cx) + E(Py – Cy) + F(Pz – Cz) + Cy + My
dX = A • ∆X + B • ∆Y
dY = D • ∆X + E • ∆Y

SE

GA

VDP2 reads per line all parameters from the rotation parameter table stored on
VRAM, calculates Xsp, Ysp, Xp, Yp, dX, dY used for the above calculation equation,and uses these results to find the display coordinates (X, Y) of each dot. Expansion
reduction coefficients kx and ky usually use values read from the rotational parameter table. By using the coefficient table, values in all lines and dots can be changed.

ST-58-R2

147

6.2 Rotation Scroll Screen Display Control

ntial

The rotation scroll screen has two surfaces, RBG0 and RBG1. When RBG1 is displayed, RBG0 must also be displayed (RBG0 appears when only one surface isdisplayed.) The Normal scroll screens can no longer be displayed at that time.

deThe image data (pattern name table or bitmap pattern) being displayed in the rotation scroll screen cannot be with image data of the Normal scroll screen; neither can
image data of RBG0 and RBG1 be used in common. Furthermore, image data of therotation scroll screen must be stored in separate VRAM. Among image data, theRBG1 pattern name table is stored in VRAM-B1, and character pattern table is storedin VRAM-B0.
When RBG0 needs coefficient only data with lines, the coefficient table can be stored
in any VRAM bank. Image data must be stored in different banks when requiredwith dots.

nfi

The register that controls the display of the rotation scroll screen has a screen display
enable register and RAM control register. The screen display enable register controls
the screen display and transparency code. The register content is the same as theNormal scroll screen. See “4.1 Screen Display Control” for details.
RAM Control Register

RAMCTL
18000EH

Co

The RAM control register selects the VRAM bank partition, the objective for using
the rotation scroll screen VRAM, and the color RAM mode. It is a read-write 16 bit
register and is at address 18000EH. Because the value of the register is cleared to 0
after power on or reset, you must set the value.
15
14
13
12
11
10
9
8
CRKTE
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00

GA

Color RAM Coefficient Table Enable bit (CRKTE)

SE

See “6.4 Coefficient Table Control.”148

Color RAM mode bit (CRMD1, CRMD0)

ntial

See “3.4 Color RAM mode.”
Set the Color RAM mode to mode 1 when the CRKTE bit is 1. At that time, color
data can no longer be stored because the second half of the color RAM (100800H ~100FFFH) is used for the coefficient table data.
VRAM mode bit (VRAMD, VRBMD)

See “3.2 VRAM Bank Partition.”

Rotation data bank select bit: Data bank select bit (RDBSA01, RDBSA00, RDBSA11,
RDBSA10, RDBSB01, RDBSB00, RDBSB11, RDBSB10)

RDBSx1001118000EH
18000EH
18000EH
18000EH

RDBSx001
01

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6

For VRAM-A0 (or VRAM-A)
For VRAM-A1
For VRAM-B0 (or VRAM-B)
For VRAM-B1

VRAM Use
Not used as RBG0 RAM
RAM for RBG0 End table
RAM for RGB0 Pattern Name table
RAM for RBG0 Character Pattern table (or Bitmap Pattern)nfi

RDBSA00, RDBSA01
RDBSA10, RDBSA11
RDBSB00, RDBSB01
RDBSB10, RDBSB11

deDesignates the use objective of the VRAM of the rotation scroll screen. This bit is
only in effect when the rotation scroll screen is displayed.

Note: A0, A1, B0, or B1 is entered in bit name for x.

SE

GA

Co

When there are no bank partitions in VRAM, the VRAM-A0 bit is used for VRAM-A,
and the VRAM-B0 bit is used for VRAM-B. When coefficient data is not treated as
being needed in all dots, there is no need to set the coefficient table RAM (01B).
When displaying by the bit map format, do not set the pattern name table RAM(10B). VRAM cycle pattern register settings of the VRAM bank selected in RAM
used for the rotational scroll are ignored. Data will not be read out when there is no
image data read-out address in the selected bank. Therefore, the correct screen can
no longer be displayed.

ST-58-R2

149

SE

GA

Co

nfi

de

nti
al

When displaying RBG1, 00B must be set in bits used for VRAM-B0 and VRAM-B1.
When the coefficient data read address is not the address within the selected bank,the coefficient data can not be read properly and therefore correct screen image can
not be displayed. In addition, when storing the coefficient table in the color RAM,
RBG0 coefficient table RAM (01B) must not be set.

150

6.3 Rotation Parameter Control

ntialWhen displaying the rotation scroll screen, be sure to store the rotation parameter onwhich control is performed as a table in VRAM. The rotation scroll screen reads therotation parameter tables stored in VRAM for each line. The screen is displayed
according to that value. The rotation parameter is shown below.
Table 6.2 Rotation Parameters

Definition
Xst
Screen upper left corner (or left edge) X coordinate
Screen Start Coordinate
Yst
Screen upper left corner (or left edge) Y coordinate
Zst
Screen upper left corner (or left edge) Z coordinate
Screen Vertical Coordinate∆Xst Screen coordinates X increment per each line
Increments∆Yst Screen coordinates Y increment per each line
Screen Horizontal Coordinate ∆ X
Screen coordinates X increment per each dot
Increments∆Y
Screen coordinates Y increment per each dot
Rotation Matrix Parameter
A
These parameters are include in 3X3 rotation matrix.
B
ABC
C
D
DEF
E
GHI
F
Px
Viewpoint X coordinate
Viewpoint Coordinates
Py
Viewpoint Y coordinate
Pz
Viewpoint Z coordinate
Cx
Center X coordinate
Center Coordinates
Cy
Center Y coordinate
Cz
Center Z coordinate
Amount of Horizontal
Mx
Shift in X direction for screen, viewpoint, and center
Shift
My
Shift in Y direction for screen, viewpoint, and center
Scaling Coefficientskx
Scale coefficient of display screen in X direction
ky
Scale coefficient of display screen in Y direction
Coefficient Table Start Address KAst Table start address when using coefficients table
Coefficient Table Vertical∆KAst Address increment per each line when using
Address Increment
coefficients table
Coefficient Table Horizontal∆KAx Address increment when using coefficients table per
Address Increment
each dot

Co

nfi

de

Rotation Parameter

SE

GA

Note: * denotes when reading to each line.

ST-58-R2

151

(Screen X coordinate)= Xst + ∆Xst x (V counter value) + ∆X x (H counter value)(Screen Y coordinate)= Yst + ∆Yst x (V counter value) + ∆Y x (H counter value)(coefficient table address)= KAst + ∆KAst x (V counter value) + ∆KAx x (H counter value)ntialOnly Xst, Yst, and KAst among rotation parameters can be read by the first line ofthe display screen. The value of Xst, Yst, and KAst (when ∆Xst, ∆Yst, ∆ X, ∆Y, ∆KAst,and ∆KAx don’t change inside one screen) are expressed by the equation below.

deMoreover, the first line can be read (in addition to Xst, Yst, and KAst) by setting therotation parameter read control register. Values on and after the second lines of Xst,
Yst, and KAst (when ∆Xst, ∆Yst, ∆ X, ∆Y, ∆KAst, and ∆KAx do not change within
screen one) are expressed by the equation below.

nfi(Screen X coordinate)= Xst+ ∆Xst x {(V counter value) – (V counter value when Xst is read out)}+ ∆X x (H counter value)

Co(Screen Y coordinate)= Yst+ ∆Yst x {(V counter value) – (V counter value when Yst is read out)}+ ∆Y x (H counter value)(coefficient table address)= KAst+ ∆KAst x {(V counter value) – (V counter value when KAst is read out)}+ ∆KAx x (H counter value)SE

GA

The rotation scroll screen has two sets of parameter tables, called “Rotation Parameter A” and “Rotation Parameter B.” The display screen of RBG1 is carried out byrotation parameter B. RBG0 selects which of the two sets of parameter tables isused, and can change within the display screen. Through this, RBG0 can simultaneously display two different rotation scroll screens on one screen.

152

nti
al

In addition, the rotation parameter table moves by storing rotation parameter tables
using RBG0 and RBG1, and does not always have to store two sets of rotation parameter tables.
Data Configuration of the Rotation Parameter Table

Figure 6.2 shows various bit configurations of rotation parameters. Negative numbers indicate by two complements. The shaded part of the bit is ignored.

Scre en Star t Coo rd ina tes (Xst , Yst , Zst )
10

9

8

Sig n
14 13 12 11 10 9
8
10 bi t fract ion al par t

7
6
5
4
3
12 bi t integ er par t

2

1

0

7

3

2

1

0

3

2
1
Sign

0

de

Bit 15+2 H

14 13 12 11

6

5

4

nfi

Bit 15+0 H

Scr ee n Vert ica l Coor din at e Incre ment s (∆X st , ∆Yst )Bit 1514 13 12 11

+0 H

9

8

14 13 12 11 10 9
8
10 bi t fract ion al par t

Co

Bit 15
+2 H

10

7

7

6

5

4

2 bi tint eg er
par t

6

5

4

3

2

1

0

6

5

4

3

2
1
Sign

0

2

0

Scre en Hor izo nt al Coo rd ina te Incr em en ts (∆X, ∆Y )Bit 15+0 H
Bit 151098

14 13 12 11 10 9
8
10 bi t fract ion al par t

GA

+2 H

14 13 12 11

7

7

6

5

4

3

1

2 bi tinteg er
pa rt

Not e: Sha ded are as are ign or ed .

Rotation parameter data configuration

SE

Figure 6.2

ST-58-R2

153

Rotation Matrix Parameter (A, B, C, D, E, F)
14

13

12

11

10

9

8

7

6

5

4

+0H
Bit 15

14

13

+2H

12 11 10 9
8
10 bit fractional part

7

6

5

3
2
Sign

4

3

2

3

2

Viewpoint Coordinates (Px, Py, Pz)
14

13 12
Sign

11

10

9

8

7
6
5
4
13 bit integer part

10

9

8

7
6
5
4
3
13 bit integer part

9

8

13 12
Sign

11

Amount of horizontal shift (Mx, My)
14

13 12
Sign

14

13

+0H
Bit 15+2H

11

10

12 11 10 9
8
10 bit fractional part

1

0

1

0

2

1

0

7
6
5
4
3
13 bit integer part

2

1

0

7

2

1

0

7
6
5
4
3
2
7 bit integer part
Sign

1

0

6

5

Co

Bit 153 bit
integer part

nfi

Center Coordinates (Cx, Cy, Cz)
Bit 15 14

0

de

Bit 151nti
al

Bit 15

4

3

Scaling Coefficients (kx, ky)
Bit 15

14

13

12

14

13

12

+0H
Bit 15

11

10

9

11

10

9
8
7
6
5
16 bit fractional part

GA

+2H

8

4

3

2

1

0

4

3

2

1

0

4

3

2

1

0

Coefficient Table Start Address (KAst)
Bit 15

14

13

12

11

14

13

12 11 10 9
8
10 bit fractional part+0H

Bit 15

SE

+2H

10

9

8
7
6
5
16 bit integer part

7

6

5

Note: Shaded areas are ignored.

Figure 6.2

154

Rotation parameter data configuration (continued)

Bit 15
+0 H

14

13

12

9
8
Sig n

7

6

5
4
3
2
9 bit int eg er pa rt

1

0

Bit 1514

13

12 11 10 9
8
10 bi t fra ct ion al par t

7

6

5

2

1

0

+2 H

11

10

nti
al

Coef fici en t tabl e ver tical add re ss incr em en t (∆KAst )Coe ffici en t tabl e hor izon tal add re ss incr em ent (∆KAx)
11

14

13

12

9
8
Sign

7

6

5
4
3
2
9 bi t int eg er pa rt

1

0

14

13

12 11 10 9
8
10 bi t fra ct ion al par t

7

6

5

1

0

+0 H
Bit 15+2 H

Figure 6.2

4

3

2

nfi

Not e: Sha ded are as are ign or ed

10

3

de

Bit 15

4

Rotation parameter data configuration (continued)

Co

Rotation Parameter TableSEGA

One set of rotation parameter tables at a size of 60H is stored in VRAM. Figure 6.3
shows the configuration of one set of tables.

ST-58-R2

155

(Integer Part)

Screen Start Coordinate Xst(Fractional Part)

+02H
+04H

Screen Start Coordinate Yst(Integer Part)(Fractional Part)

+06H
+08H

Screen Start Coordinate Zst(Integer Part)(Fractional Part)

+0AH
+0CH

Screen Vertical Coordinate Increment ∆Xst
Screen Vertical Coordinate Increment ∆Yst

Screen Horiz. Coordinate Increment ∆X(Integer Part)(Fractional Part)+16H
Screen Horiz. Coordinate Increment ∆Y

+1AH
+1CH

Rotation Matrix Parameter A

Rotation Matrix Parameter B

Rotation Matrix Parameter C+26H(Fractional Part)(Fractional Part)(Fractional Part)(Integer Part)

Rotation Matrix Parameter F(Fractional Part)+32H

Viewpoint Coordinate Px(Integer Part)+36H

Viewpoint Coordinate Py+38H

Viewpoint Coordinate Pz(Integer Part)(Integer Part)

Co

+34H

+3AH

This data is ignored+3CH

Center Point Coordinate Cx(Integer Part)+3EH

Center Point Coordinate Cy(Integer Part)+40H

Center Point Coordinate Cz(Integer Part)

+42H
+44H

This data is ignored

GA
+48H

SE

(Fractional Part)(Integer Part)(Fractional Part)

Coefficient Table Vertical Address Increment ∆KAst(Integer Part)(Fractional Part)

+5AH

+5CH

(Integer Part)

Coefficient Table Start Address KAst

+56H
+58H

(Integer Part)(Fractional Part)

Scaling Coefficient ky

+52H
+54H

(Integer Part)(Fractional Part)

Scaling Coefficient kx

+4EH
+50H

(Fractional Part)

Horizontal Shift My

+4AH
+4CH

(Integer Part)

Horizontal Shift Mx+46H

Coefficient Table Horiz. Address Increment ∆KAx

(Integer Part)(Fractional Part)

+5EH

156

(Integer Part)

Rotation Matrix Parameter E

+2EH
+30H

(Integer Part)

Rotation Matrix Parameter D

+2AH
+2CH

(Integer Part)

nfi

+28H

(Integer Part)(Fractional Part)

+22H
+24H

(Integer Part)(Fractional Part)

+1EH
+20H

(Integer Part)(Fractional Part)

de

+18H

(Integer Part)(Fractional Part)

+12H
+14H

(Integer Part)(Fractional Part)

+0EH
+10H

nti
al

+00H

Figure 6.3

Rotation parameter table

nti
al

When storing two sets of tables of rotation parameter A and rotation parameter B,
store the rotation parameter A from the lead address of the rotation parameter table,
then enter the 20H part of invalid data and store tables of rotation parameter B. The
rotation parameter table does not always have to store two sets, but can store only
the tables needed. Figure 6.4 shows the method of storing two sets of tables fromrotation parameters A and B.
Rot ation Para met er A To p Addr ess
+00H

+5E H
+60 H

The da ta in this ar ea is not used as
rot ation pa ra met er

nfi

+7E H
+80 H

de

Rotat ion Par am et er A Ta bl e

Rotat ion Par am et er B Ta bl e

Co

+DE H
+EOH

Figure 6.4 How to store to the rotation parameter table VRAM

Rotation Parameter Read Control RegisterGA

The rotation parameter read control register is a write-only 16 bit register that indicates whether to read Xst, Yst, and KAst in each line, and is at address 1800B2H.
Because the value is cleared to 0, it must be set after power on or reset.
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10

9

RBKASTRE RBYSTRE

2

1

RAKASTRE RAYSTRE

8
RBXSTRE0
RAXSTRESE

RPRCTL
1800B2H

ST-58-R2

157

Parameter read enable bit (RAXSTRE, RBXSTRE, RAYSTRE, RBYSTRE, RAKASTRE,
RBKASTRE)

RAXSTRE
RBXSTRERAYSTRE
RBYSTRERAKASTRE
RBKASTRE

1800B2H
1800B2H
1800B2H
1800B2H
1800B2H
1800B2HntialDesignates the coefficient table start address KAst and TV screen start coordinates
Xst and Yst, and whether to read from the rotation parameter table in that line.
Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 10For Xst of Rotation Parameter A
For Xst of Rotation Parameter B
For Yst of Rotation Parameter A
For Yst of Rotation Parameter B
For KAst of Rotation Parameter A
For KAst of Rotation Parameter B

Process
Selected parameters are not read for that line
Selected parameters are read for that linedeRxSTRE
01

Note: AX, BX, AY, BY, AKA, or BKA is entered in bit name for x.

nfi

If this bit is 1, selected parameters are read when the next rotation parameters are
read. At the same time, this bit is cleared to 0. Therefore, to read parameters foreach 1 line, this bit must be set to 1 for each line.
Rotation Parameter Table Address Register

15
~
7
~

14
~
6
~

RPTAL
1800BEH

15
RPTA157
RPTA7

14
RPTA14
6
RPTA6

SE
158

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
RPTA189~1
RPTA178~
0
RPTA16

13
RPTA13
5
RPTA5

12
RPTA12
4
RPTA4

11
RPTA11
3
RPTA3

10
RPTA10
2
RPTA2

9
RPTA9
1
RPTA1

8
RPTA8
0
~

GA

RPTAU
1800BCHCo

The rotation parameter table address register is a write-only 16-bit register that
selects the lead address of the rotation parameter table, and is at address 1800BCH to
1800BEH. Because the value is cleared to 0, it must be set after power on or reset.

Rotation parameters table address bit (RPT
A18 to RPTA1)

RPTA18~RPTA16
RPTA15~RPTA1

1800BCH
1800BEH

Bit 2~0
Bit 15~1nti
alDesignates the lead address of rotation parameter tables.

RPTA6 bit is ignored even if data is written. The bit is set at 0 for rotation parameter
A, and fixed at 1 for rotation parameter B.
The actual lead address of a rotation parameter table is calculated as shown in theequation below. When the VRAM size is 4 Mbit, the most significant bit of theaddress is ignored.

de(Lead address of rotation parameter A)= (rotation parameter table address register value highest 12 bit) X 100H+ (rotation parameter table address register value lowest 5 bit) X 4H

nfi

(Lead address of rotation parameter B)= (rotation parameter table address register value highest 12 bit) X 100H+ (rotation parameter table address register value lowest 5 bit) X 4H + 80H

For example, when 00170H or 00130H is selected, the lead address of rotation parameter A is 00260H, and the lead address of rotation parameter B is 002E0H.
Rotation Read Out of the Frame BufferCo

Rotation reading of the frame buffer is executed using the TV screen start coordinates (Xst, Yst) of rotation parameter A, TV screen vertical coordinate increments(∆Xst, ∆ Yst), and TV screen horizontal coordinate increments (∆X, ∆Y). If the image
selected by rotation parameter A in the rotation scroll screen is to be displayed, theentire sprite and rotation scroll screen can be made to rotate identically. If the image
selected by rotation parameter B in the rotation scroll screen is to be displayed, theentire sprite and rotation scroll screen can be made to rotate separately.

GA

The frame buffer display coordinate value calculates from the TV screen starting
coordinate, the display coordinate of the left end of the line calculated in each linefrom the TV screens vertical coordinate increment and horizontal coordinate. The
bit will be discarded and calculated from the coordinate range of the frame buffer sothat the display coordinate value of the line’s left end is calculated in 20 bits
(code+integer10-bit +decimal part 9-bit), and the horizontal coordinate increment ina total of 12 bits (code+integer part 2-bit+decimal part 9-bit).
In order to read frame buffer rotation using rotation parameter A, VDP1 TV mode must be set
to rotation 16 or rotation 8. For details, please refer to VDP1 user manual.

SE

Note:

ST-58-R2

159

nti
al

Rotation parameters
Rotation Parameter
Changetable address bit (RPTA18 to RPTA1)
Designates the lead address of rotation parameter tables.
RBG0 indicates which of two sets of rotation parameter tables is used, and canchange in part the rotation parameter on one screen display. The method of using
the rotation parameter can be selected from the four rotation parameter modes
below.
RPTA6 bit is ignored even if data is written. The bit is set at 0 for rotation parameter
A, andfixed at 1 for rotation parameter B.
Mode 0:Uses rotation parameter A
Mode 1:
Uses rotation parameter B
The actual
lead address of a rotation parameter table is calculated as shown in theMode 2:
Changes the image by coefficient data read from the coefficient table of rotation
equation
below.
parameter
A When the VRAM size is 4 Mbit, the most significant bit of theaddressis
ignored.
Mode 3:
Changes by the rotation parameter window.

(Lead address of rotation parameter B)

de

(Lead
address ofthe
rotationparameterA) through each rotation parameter table set.
Modes 0 and
1 display
image
obtained= (rotation parameter table address register value highest 12 bit) X 100H
Modes 2 and 3 display
the parameter
images within
one screen
through+ (rotationtable address
registerobtained
value lowest
5 bit) Xrotation
4H
parameters A and B.

nfi

Set Mode 2 to use=the
coefficient
table
ofaddress
rotationparameter
A by setting
RAKTE(rotation
parameter
table
registervalue highest
12 bit) X the
100H
bit of the coefficient
table control
registerto 1. The
value
oflowest
the most+ (rotation
parameter
table address
registervalue
5 bit)significant
X 4H + 80H bitof coefficient data read from the coefficient table displays the image obtained byrotation parameter
A whenit is0, but or
displaystheobtained
byaddress
rotationofpaFor example,
when00170H
00130His imageselected,
the leadrotation parameter B rameteras an RBG0
when
is 1.
When
set tocoefficient
dataBusedfor
A isimage00260H,
anditthelead
address
ofreadrotationparameter
is 002E0H.
rotation parameter A in each dot, two images can also be changed in each dot, butcoefficientRotation
data usedReadfor rotation
cannot be read in each dot.
Out of parameter
the FrameBBufferCo

Rotation
reading
the frametobuffer
is usedexecutedusing
the TV
screen start coordiMode 3 changes
twoimagesofaccording
the bitin therotationparameter
nates
(Xst,
Yst)
of
rotationparameterA,TV
screenverticalcoordinate
increments
window of the rotation window control register. When the window is used as the(∆Xst,∆ Yst),and TVthe
screencoordinate(∆X,transpar∆Y). If the imagetransparent
process
window,
part horizontalof the screenthat is cutincrements
off and madeselectedbyrotationparameterAintherotation
scrollscreenistobeent displays the image obtained by rotation parameter B; the remaining part isdisplayed, thesprite image
and rotation
scrollscreen canbe madeA.
to rotate identically. If the image
displayed entire
as an RBG0
obtainedby rotation
parameter
selected by rotation parameter B in the rotation scroll screen is to be displayed, theentire sprite and rotation scroll screen can be made to rotate separately.

SEGA

The frame buffer display coordinate value calculates from the TV screen starting
coordinate, the display coordinate of the left end of the line calculated in each linefrom the TV screens vertical coordinate increment and horizontal coordinate. The
bit will be discarded and calculated from the coordinate range of the frame buffer sothat the display coordinate value of the line’s left end is calculated in 20 bits
(code+integer10-bit +decimal part 9-bit), and the horizontal coordinate increment ina total of 12 bits (code+integer part 2-bit+decimal part 9-bit).

160

ST-58-R2

159

nti
al

An example of image display from above modes 0 to 3 is shown in Figure 6.5.

When Rot at ion Param et er Mo de 0

Image ob tai ne d thr ou gh
rot at ion par am et erAImage ob tai ne d thr ou gh
rot at ion par am et er Bnfi

Whe n Rotat ion Par am et er Mode 2
Imag e obt ai ne d thr ou gh
ro tation pa ra me ter B

The MSB=1 pa rt of the coe ffici en ttabl e for rot ation pa ram et er A.

The MSB=0 par t of the co ef fici ent
tab le for ro tat io n par am eter A.

Co

Image ob tai ne dthroug h ro tat io n
par am et er A

deWhen Rot at ion Param et er Mo de 1

Rot ation Para met er Mo de 3: Switche d thr ou gh Rot ation Para me ter Wind ow an d di spl aye d.
Ima ge obt ain ed thro ug hro tat io n par ame ter B

The pa rt di sp la yed witho ut cut tin g the scre en intran spa re nt pr oce ssin g wi ndo w.

GA

Ima ge ob tai ned thr oughrot at ion par am et er A

The pa rt cut from the scr een an d mad e tra nsp ar en t intran spa re nt pr oce ssin g wi ndo w.

SE

Figure 6.5 Rotation parameter change

ST-58-R2

161

Rotation Parameter Mode Register

RPMD
1800B0H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

Rotation parameters mode bit (RPMD1, RPMD0), bits 1 and 0ntial

The rotation parameter mode register is a write-only 16 bit register that controls
rotation parameter tables used in RBG0, and is at address 1800B0H. Because thevalue is cleared to 0, it must be set after power on or reset.
10
~
2
~

9
~
1
RPMD1

8
~
0
RPMD0

RPMD0
0
1
0

Mode
0
1
2

1

1

3

Rotation Parameter
Rotation Parameter A
Rotation Parameter B
A screen and B screen are switched via
coefficient data read from rotation parameter A
coefficient table.
A screen and B screen are switched via
rotation parameter window

nfi

RPMD1
0
0
1

de

When displaying RGB0, designates which rotation parameter of A or B will be used.

The value of this bit is always in effect, therefore, be careful in timing reloading.

Co

When mode 2 is selected, coefficient data cannot be read to each dot from the coefficient table for rotation parameter B while coefficient data for rotation parameter A isbeing read to each dot. Therefore, the designation is ignored even if a register isdesignated so that coefficient data is read to each dot from the coefficient table used
for rotation parameter B.
In mode 3, coefficient data can be read to each dot in both coefficient tables forrotation parameter A and B.

SEGA

Mode 0 must be set when displaying RBG1.

162

6.4 Coefficient Table Control

ntial

The rotation scroll screen stores parameters used in calculating display coordinatesin VRAM or color RAM in a table separate from the rotation parameter table, andcan express various images by reading parameters per line or per dot. This table isreferred to as “coefficient table.”
The timing required for the coefficient table data, depending on how display coordinates are calculated, falls under the following cases:
Required per line
Required per dot

de

1.
2.

When coefficient table data is required per line, the coefficient table must be storedin VRAM. The VRAM address to read the stored coefficient table data is specified
via KAst, ∆KAst, and ∆KAx in rotation parameter table and coefficient table addressoffset register.

Co

nfi

When coefficient table data is required per dot, the coefficient table must be stored ineither VRAM or color VRAM. When stored in VRAM, at least 1 bank in RAM control
register “rotation data bank selection” must be selected to become coefficient table.
The VRAM address to read the stored coefficient table data is specified via KAst,∆KAst, and ∆KAx in rotation parameter table and coefficient table address offset
register. Also, when storing coefficient table in color RAM, it should be stored in thelatter half of color RAM (100800H to 100FFFH). The color RAM address to read thestored coefficient table data is specified via KAst, ∆KAst, and ∆KAx in rotation
parameter table. As for the address to read coefficient table data, only the lower 10
bits in the integer part of the calculated coefficient table address become valid.
To select parameters for which the data read from the coefficient table are to be used,
the following 4 modes (coefficient data modes) are provided:

GA

Mode 0: Used as Scale coefficient kx and ky
Mode 1: Used as Scale coefficient kx
Mode 2: Used as Scale coefficient kyMode 3: Used as viewpoint coordinate Xp after rotation conversion

In mode 0, kx and ky read from the rotation parameter table become invalid; dataread from the coefficient table is used as kx and ky.

SEWhen mode 1 is selected, ky read from the rotation parameter table is used, but dataread from the coefficient table is used for kx.

ST-58-R2

163

nti
al

When mode 2 is selected, kx read from the rotation parameter table is used, but dataread from the coefficient table is used for ky.
When mode 3 is selected, X direction viewpoint coordinate Xp, converted
rotationally as data read from the rotation parameter table, becomes invalid. Dataread from the coefficient table is used for Xp.
Line Color Screen DatadeCoefficient data can be used not only as rotation parameters, but as part of line color
screen data. In this case, the highest 4-bit data read from the line color screen table isadded to the highest of 7-bit data that is part of coefficient data. Figure 6.6 showsline color screen data using coefficient data.

Read from Coe fficie nt Tab leLine Co lor Scr ee n Da ta (7 bit )nfi

Re ad from Lin e Co lor Scr ee n
Li ne Col or Scre en Dat a (11 bit )Co

Li ne Colo r Scr ee n Data after com po sit io n

Figure 6.6 Line color screen data using coefficient data

GA

When specifying mode 0 for rotation parameter mode, line color screen per rotation
parameter A coefficient table is used. When specifying mode 1, line color screen per
rotation parameter B coefficient table is used.
When specifying mode 2, for both rotation parameter A graphics and rotation parameter B graphics, line color screen per rotation parameter A coefficient table isused.
When specifying mode 3, for rotation parameter A graphics, line color screen per
rotation parameter A coefficient table is used, whereas for rotation parameter B
graphics, line color screen per rotation parameter B coefficient table is used.

SE

Also, when displaying RBG1, for both RBG0 and RBG1, line color screen per rotation
parameter A coefficient table is used.

164

Bit Configuration of Coefficient Table Data

Coe ffici en t Dat a Mod e 0~2

Bit 15

14

13

12

11

10

+2 H

7
6
Sign

5

9
8
7
6
5
16 bi t fra ct ion al par t

9

8

4
3
2
1
7 bi t integ er par t

7

4

3

0

2

1

0

6
5
4
3
2
10 bi t fra ct ion al pa rt

1

0

nfi

Coe ffici en t Dat a Size : 1 wor d
Tra nsp ar en cy
Bit 1514 13 12 11 10+0 H
Sign 4 bit int ege r pa rt

8de

Coe ffici en t Dat a Size : 2 wor ds
Tra nsp ar en cy
Bit 1514 13 12 11 10 9
7 bi t line col or scre en da ta
+0 H

nti
al

Either “1-word” or “2-word” can be chosen as the data size on the coefficient table.
The data configuration changes depending on this coefficient data size and coefficient data mode. Figure 6.7 shows the bit configuration of coefficient table data.

No te: The MS B are si gn -e xpa nd ed by 3 bit s an d the LS B are 0- exp an de dby 6 bi ts to be of equ al to the num ber of bi ts as in the case of 2 wo rd s.

Co

Coe ffici ent Dat a Mod e 3

Coe ffici ent Dat a Size : 2 wo rds
Tr an spa re ncy
Bit 1514 13 12 11 10 9
7 bi t line col or scre en da ta+0 H
Bit 15 14+2 H

13 12 11 10 9Int eg er pa rt LS B 8 bi ts

GA

Coe ffici ent Dat a Size : 1 wo rd
Tr an spa re ncy
Bit 1514 13 12 11
Sign
+0 H

10

8

7
6
Sign

5
4
3
2
1
0
Integ er par t MSB 7 bits

8

7

5
4
3
2
1
8 bi t fra ct ion al par t

6

9
8
7
6
5
12 bit int ege r pa rt

4

3

2

1

0

0
2 bit fract iona l pa rt

SE

Not e: The MSB ar e sig n- exp an de d by 3 bi ts and the LSB ar e 0-expa nd edby 6 bits to be of eq ua l to the nu mbe r of bits as in the ca se of 2 wor ds.

ST-58-R2

Figure 6.7 Bit configuration of coefficient table data

165

Coefficient Table Lead Addressntial

The coefficient table lead address is obtained from the coefficient table start address(KAst integer part 16-bit) read from the coefficient table address offset register androtation parameter table. The coefficient table vertical address increment (∆KAst
integer part 9-bit) and coefficient table horizontal address increment (∆KA integer
part 9-bit) are also read from the rotation parameter table.

deThe address value of the address offset, start address and address increment change
according to the data size of the coefficient table. Table 6.3 shows the address value
showing the least significant bit of each value. For example, when 4H is 2-word (theleast significant bit of integer KAst signifies the expression of the 4H address value),it can be calculated as shown below.
(Coefficient table start address) = (KAst integer part 16 bit) X 4H

Coefficient
Data Size
2 Words
1 WordAddress values shown by the least significant bits of coefficient parameter dataof separate coefficient data sizes
Address Value Indicated by the LSB
Coefficient Table Address
KAst, ∆KAst, ∆KAx Integer
Offset Register Value
part value
40000H
4H
20000H
2H

nfi

Table 6.3

Co

Most Significant Bit of Coefficient Data

SEGA

The most significant bit of coefficient data is usually used as transparent bits; dotsthat used coefficient data in which this bit is 1 are forced to be transparent dots.
However, when rotation parameter mode 2 is selected by RBG0, the most significant
bit of data read from the coefficient table used for rotation parameter A is used forswitching rotation parameters. When the most significant bit is 0, the designatedimage is displayed by rotation parameter A. When the most significant bit is 1, thedesignated image is displayed by rotation parameter B. Here, the most significant
bit of coefficient data read from the coefficient table used for rotation parameter B isused as a transparent bit. The most significant bit of coefficient data for RBG1 isalways used as a transparent bit. Table 6.4 shows image processing by the mostsignificant bit values of coefficient data.

166

Table 6.4 Image processing using RBG0 coefficient data MSB value
MSB Function MSB Value

Image Process

Transparent

Displays image obtained using thecoefficient data
Forces the dot to be transparent
using the coefficient data
Displays image obtained using thecoefficient data
Forces the dot to be transparent
using the coefficient data
Displays image obtained using thecoefficient data
Invalidates the coefficient data anddisplays image obtained using
rotation parameter B
Displays image obtained using thecoefficient data
Forces the dot to be transparent
using the coefficient data
Displays image obtained using thecoefficient data
Forces the dot to be transparent
using the coefficient data

0

0
1

B
A
B

1

Not Used
Not UsedTransparent

0

A
2
B

Parameter0

Switching

1

Transparent

0

3

A, B

nfi

1

de

1

Transparent

0

1

Co

RAM Control RegisterntialRotation
Rotation
Parameter Parameter
Mode
A

The RAM control register is a read/write 16-bit register that selects the VRAM bankpartition, rotation scroll screen VRAM use, and color RAM mode. After power-on or
reset, the value will be cleared and therefore must be set.

GA

RAMCTL
18000EH

15
14
13
12
11
10
9
8
CRKTE
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RBBSB00 RDBSA11 RDBSA10 RDBSA01 RBBSA00

Color RAM Coefficient Table Enable (CRKTE), bit 15.

Selects whether to store the coefficient table in the color RAM.
CRKTE

Function

Coefficient table is stored in VRAM
Coefficient table is stored in color RAM

SE

0
1

ST-58-R2

167

Color RAM Mode Bit: (CRMD1, CRMD0), bits 13 and 12

Please see color RAM mode in 3.4.

ntialWhen CRKTE is set to 1, please set color RAM mode to 1. Here, the latter half of thecolor RAM (100800H-100FFFH) will be used for coefficient table data, therefore, thecolor data cannot be stored.
VRAM Mode Bit: (VRAMD, VRBMD), bits 9 and 8

Please see VRAM bank partition in 3.2.

Rotation Data Bank Select Bit: (RDBSA00-11, RDBSB00-11), bits 7 through 0

Please see rotation scroll display control in 6.2.

deWhen CRKTE is set to 1, VRAM bank 4 may not be selected to be used as coefficient
table data RAM.
Coefficient Table Control Register

15
~
7
~

14
~
6
~

13
~
5
~

12
RBKLCE
4RAKLCE

11
RBKMD1
3
RAKMD1Co

KTCTL
1800B4Hnfi

The coefficient table control register is a write-only 16-bit register that controls thecoefficient table, and is at address 1800B4H. Because the value is cleared to 0, it
must be set after power on or reset.
10
RBKMD02
RAKMD09
RBKDBS1RAKDBS

8
RBKTE
0
RAKTE

Coefficient line color enable bit (RAKLCE, RBKLCE)

Designates whether to use line color screen data in coefficient data.
RAKLCERBKLCE

1800B4H
1800B4H

Bit 4
Bit 12For Rotation Parameter A
For Rotation Parameter B

This bit uses the corresponding coefficient table and is effective only when the data
size is 2-word.
Process
Line color screen data within coefficient data is not usedLine color screen data within coefficient data is usedGA

RxKLCE
0
1

SE

Note: A or B is entered in the bit name for x.

168

Coefficient data mode bit: Coefficient mode bit (RAKMD1, RAKMD0, RBKMD1, RBKMD0)

Designates what parameters the coefficient data is used as.
1800B4H
1800B4H

Bit 3,2
Bit 11,10

For Rotation Parameter A
For Rotation Parameter B

ntial

RAKMD1, RAKMD0
RBKMD1, RBKMD0

Because this bit is always in effect, be careful in rewriting timing.
RxKMD1
00
1
1

RxKMD0
0
1
0
1

Mode
0
1
2
3

Coefficient Data Function
Use as scale coefficient kx, ky
Use as scale coefficient kx
Use as scale coefficient ky
Use as viewpoint Xp after rotation conversion

Coefficient data size bit (RAKDBS, RBKDBS)

deNote: A or B is entered in the bit name for x.

Designates the size of the coefficient data.
RAKDBSRBKDBS

1800B4H
1800B4H

Bit 1
Bit 9

For Rotation Parameter A
For Rotation Parameter B

nfi

This bit is in effect only when the corresponding coefficient table is used.
RxKDBS01

Coefficient Data Size
2 Words
1 WordNote: A or B is entered in the bit name for x.

Co

Coefficient table enable bit (RAKTE, RBKTE)Designates whether the coefficient table is used.
RAKTE
RBKTE
RxKTE
0
1

1800B4H
1800B4H

Bit 0
Bit 8

For Rotation Parameter A
For Rotation Parameter B

Process
Do not use coefficient table
Use coefficient table

SE

GA

Note: A or B is entered in the bit name for x.

ST-58-R2

169

Coefficient Table Address Offset Register

KTAOF
1800B6H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

nti
al

Coefficient table address offset register is a write-only 16-bit register that designates
the coefficient table lead address offset value, and is at address 1800B6H. Because
the value is cleared to 0, it must be set after power on or reset.
11
~
3
~

10

9

8

RBKTAOS2 RBKTAOS1 RBKTAOS0

2

1

0

RAKTAOS2 RAKTAOS1 RAKTAOS0

Coefficient table address offset bit (RAKTAOS2 to RAKTAOS0, RBKTAOS2 to RBKTAOS0)RAKTAOS2~RAKTAOS0RBKTAOS2~RBKTAOS0

1800B6H
1800B6H

Bit 2~0
Bit 10~8

deDesignates the lead address offset value of the coefficient table stored in the rotation
parameter table.
For Rotation Parameter A
For Rotation Parameter B

When the coefficient data size is 2 word:

nfi

These bits are added to the highest coefficient table start address (KAst) read fromthe rotation parameter table. The actual lead address of the coefficient table changes
according to the size of the coefficient data, and is calculated by the expression
below. When VRAM size is 4 Mbits, the most significant bit of the address is ignored.

Co(coefficient table lead address)= (coefficient table address offset register value lowest 2 bits)
X 40000H + (KAst integer part 16 bit) X 4H

When the coefficient data size is 1 word:SEGA(coefficient table lead address)= (coefficient table address offset register value 3 bits)
X 20000H + (KAst integer part 16 bit) X 2H

170

nti
al

SE

GA

Co

nfi

de

Chapter 7 Line Screen

ST-58-R2

Introduction ..........................................................................172
7.1 Line Color Screen .......................................................172
Line Color Screen Table Address Register .............. 174
7.2 Back Screen ................................................................175
Back Screen Table Address Register ....................... 176

171

Introduction

Line Screen Table (VRAM)

Line ScreenLine Screen Data for
1st LinentialThere are two line screen surfaces: the line color screen (LNCL) and the back screen(BACK). The line screen designates the color in each line, or the entire screen in asingle color. Unlike the scroll screen, the line screen cannot display characters. Theline color screen stores the data of each line in VRAM as a line color screen table. If
single colored, lead data of the table is used in the entire screen. The line screen isshown in Figure 7.1.

1st Line

2nd LineLine Screen Data for
2nd Linede3rd LineLine Screen Data for
3rd Line

Note: In the case of single color, the 1st line data is used in the entire screen.

nfi

Figure 7.1 Line Screen

7.1 Line Color Screen

Co

The line color screen is used only for color calculations, and chooses whether todesignate the entire screen in a single color, or designate the color for each line. The
color RAM address of the color used is stored in VRAM as line color screen data.
The line number designated by one line color screen data changes, depending on theinterlace setting. The non-interlace and double-density interlace modes can designate the color for each line; the single-density interlace mode can designate for each
two lines.

SEGA

The line color screen can also be made to rotate if line color screen data is usedwithin coefficient data. For more about coefficient data see section “6.4 Coefficient
Table Control.” Figure 7.2 shows the configuration of the line color screen table
separate of the interlace mode. Figure 7.3 shows the configuration of data on theline color screen table.

172

nti
al

Non-interlace and double-density interlace modeBit 15

Line Color Screen Table (VRAM)+00H

1st Line Color RAM Address+02H

2nd Line Color RAM Address+04H

3rd Line Color RAM Address+06H

4th Line Color RAM Address+08H

5th Line Color RAM Address+0AH

6th Line Color RAM Address0deNote: In the case of single color, the first line color RAM
address is used in the entire line color screen. In thcase of double-density interlace, line data of odd aneven fields are stored together.

Single-density interlace mode

+02H

Line Color Screen Table (VRAM)

nfi

Bit 15+00H0

1st and 2nd Line Color Ram Address
3rd and 4th Line Color Ram Address+04H

5th and 6th Line Color Ram Address+06H

7th and 8th Line Color Ram Address

+08H

Co

9th and 10th Line Color Ram Address+0AH

11th and 12th Line Color Ram Address

Note: In the case of single color, the first and second line
color RAM addresses are used in the entire line
color screen.

GA

Figure 7.2 Configuration of line color screen tableSE

Bit 15

ST-58-R2

14

13

12

11

10

9

8
7
6
5
4
3
11 bit color Ram address

2

1

0

Note: Shaded areas are ignored. Also, when color RAM is in mode 0 or mode 2,
the MSB of the address is ignored.

Figure 7.3 Bit configuration of line color screen table data

173

Line Color Screen Table Address RegisterntialThe line color screen table address register is a 32-bit register, and designates thelead address of the table and the color mode of the line color screen. Its addresses
are 1800A8H through 1800AAH. Because the value is cleared to 0, it must be set
after power on, or reset.
15
LCCLMD
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
LCTA189~1
LCTA17

8~
0
LCTA16LCTAL
1800AAH

15
LCTA157LCTA714LCTA146LCTA613LCTA135LCTA512LCTA12
4LCTA4

11LCTA11
3LCTA3

10LCTA10
2
LCTA2

9
LCTA9
1
LCTA1

8
LCTA8
0
LCTA0

de

LCTAU
1800A8H

Line color screen mode bit: LNCL color mode bit (LCCLMD), bit 15

Designates the color mode of the line color screen.

Line Color Screen Color
Single color
Select per each line

nfi

LCCLMD0
1

Line color screen table address bit: LNCL table address bit (LCTA18 to LCTA0)

Designates the lead address of the line color screen table on the VRAM.
1800A8H
1800AAH

Bit 2~0
Bit 15~0

Co

LCTA18~LCTA16LCTA15~LCTA0

The actual lead VRAM address is calculated by the expression below. When the
VRAM size is 4 Mbits, the most significant bit of the address is ignored.

SE

GA(Line color screen table lead address)= (Line color screen table address register value 19 bit) X 2H

174

7.2 Back Screenntial

The back screen (BACK) is displayed only when other screens aren’t, and chooses
whether to designate a single color for the entire screen or for each line. Color data
used by a line is designated by each 5-bit RGB. The non-interlace and double-density interlace mode designates the color in each line, but the single-density interlace
mode can designate only in each two lines. Figure 7.4 shows the configuration of theback screen table by the interlace mode. Figure 7.5 shows the configuration of dataon the back screen table.

Bit 15+00HdeNon-interlace and double-density interlace mode

Back Screen Table (VRAM)
2nd Line RGB Data

+04H

3rd Line RGB Data

+06H

4th Line RGB Data

+08H

5th Line RGB Data

nfi

+02H

+0AH

0

1st Line RGB Data

6th Line RGB DataCo

Note: In the case of single color, the first line RGB data is us
in the entire line color screen. In the case of
double-density interlace, line data of odd and even fiel
are stored together.

Single-density interlace modeBit 15

+00H

+02H
+04H

GA

+06H

Back Screen Table (VRAM)0

1st and 2nd Line RGB Data
3rd and 4th Line RGB Data
5th and 6th Line RGB Data
7th and 8th Line RGB Data

+08H

9th and 10th Line RGB Data

+0AH

11th and 12th Line RGB DataSE

Note: In the case of single color, the first and second line RGB
data are used in the entire line color screen.

ST-58-R2

Figure 7.4 Configuration of back screen table175

14 13 12 11
5 bit Blue Data

10

9
8
7
6
5 bit Green Data

5

4
3
2
1
5 bit Red Data

0

nti
al

Bit 15

Note: Shaded area is ignored. Add 0 bit 3 bits at a time to the lower bits of
RGB to make 8 bits.

Figure 7.5

Bit configuration of back screen table data

Back Screen Table Address Register

15
BKCLMD
7
~

14
~
6
~

13
~
5
~

12
~
4
~

BKTAL
1800AEH

15
BKTA157BKTA714BKTA146BKTA613
BKTA135BKTA512BKTA12
4
BKTA4

11
~
3
~

10
~
2
BKTA18nfi

BKTAU
1800ACHdeBack screen table address register is a write-only 32-bit registers, and selects the backscreen color mode and table lead address. Its addresses are 1800ACH through
1800AEH. Because the value is cleared to 0, it must be set after power on or reset.

11
BKTA11
3
BKTA3

10
BKTA10
2
BKTA2

9
~
1
BKTA178~0
BKTA16

9
BKTA9
1
BKTA1

8
BKTA8
0
BKTA0

Co

Back screen color mode bit: BACK color mode bit (BKCLMD), bit 15

Designates color mode of the back screen.
BKCLMD
0
1

Back Screen Color
Single color
Select per each line

Back screen table address bit: BACK color table address bit (BKTA18 to BKTA0)

Designates the lead address of the back screen table on the VRAM.
1800ACH
1800AEHSEGA

BKTA18~BKTA16BKTA 15~BKTA0176

Bit 2~0
Bit 15~0ntial

The actual lead VRAM address is calculated by the expression below. When the
VRAM capacity is 4 Mbits, the most significant bit of the address is ignored.
(Back screen table lead address)= (Back screen table address register value 19 bit) X 2H

SE

GA

Co

nfi

de

When the back screen color mode bit is set to “single color”, color data selected by
the back screen table address bit is used in the entire screen.

ST-58-R2

177

nti
al

SE

GA

Co

nfi

de

(This page is blank in the original Japanese document)

178

nti
al

SE

GA

Co

nfi

de

Chapter 8 Windows

ST-58-R2

8.1

8.2

Window Area ......................................................... 180
Normal Rectangular Window ............................. 180
Window Position Register .................................. 181
Normal Line Window .......................................... 184
Line Window Table Address Register ................ 186
Sprite Window .................................................... 187
Sprite Control Register ....................................... 188
Window Active Area in the Screen ..................... 189
Window Process ................................................... 190
Window Process Register .................................. 193

179

8.1 Window Areantial

The scroll IC window has two Normal windows, W0 and W1, and one sprite window, SW. The Normal window selects start and end coordinates on the TV screen;
the sprite window designates the most significant bit value of sprite data written to
the frame buffer. Various windows can designate which scroll screen is to be put
into effect, and whether the inside or outside of the area will go into effect. Moreover, when more than one window is used, they can be overlapped other by AND or
OR logic.

de

The Normal window selects the Normal rectangular window designated throughthe horizontal and vertical start and end coordinates, and selects the Normal line
window designated through horizontal start and end coordinates in each line. The
start and end coordinates set the coordinate values on the TV screen in each register,and not on the scroll screen.
Normal Rectangular Windownfi

The normal rectangular window is obtained by selecting the start coordinates in theupper left corner in the window position register, and the end coordinates in thelower right corner of the window. The area surrounded by selected coordinates is
inside, the rest of area is outside. The border line of the window is considered partof the inside.

Co

If the start coordinate of either the horizontal or vertical direction is larger than theend coordinate, then the whole screen is considered an area outside the window.
Figure 8.1 shows the Normal rectangular window.

Start Point Coordinates

TV ScreenGA

Start Point Coordinates
Window
InsideOutsideSE

Window Boundary

Figure 8.1

180

Normal rectangular window

End Point
Coordinates

Window Position RegisterntialThe window position register is a write-only 16-bit register that selects the horizontal and vertical start and end coordinates of the Normal window, and is located fromaddresses 1800C0H through 1800CEH. Because the value is cleared to 0, it must be
set after power on or reset.
15
~
7
W0SX7

14
~
6
W0SX6

13
~
5
W0SX5

12
~
4
W0SX4

11
~
3
W0SX3

10
~
2
W0SX2

9
W0SX9
1
W0SX1

8
W0SX8
0
W0SX0

WPSY0
1800C2H

15
~
7
W0SY7

14
~
6
W0SY6

13
~
5
W0SY5

12
~
4
W0SY4

11
~
3
W0SY3

10
~
2
W0SY2

9
~
1
W0SY1

8
W0SY8
0
W0SY0

WPEX0
1800C4H

15
~
7
W0EX7

14
~
6
W0EX6

13
~
5
W0EX5

12
~
4
W0EX4

11
~
3
W0EX3

10
~
2
W0EX2

9
W0EX9
1
W0EX1

8
W0EX8
0
W0EX0

WPEY0
1800C6H

15
~
7
W0EY7

14
~
6
W0EY6

13
~
5
W0EY5

12
~
4
W0EY4

11
~
3
W0EY3

10
~
2
W0EY2

9
~
1
W0EY1

8
W0EY8
0
W0EY0

WPSX1
1800C8H

15
~
7
W1SX7

WPSY1
1800CAH

15
~
7
W1SY7

Co

nfi

de

WPSX0
1800C0H

13
~
5
W1SX5

12
~
4
W1SX4

11
~
3
W1SX3

10
~
2
W1SX2

9
W1SX9
1
W1SX1

8
W1SX8
0
W1SX0

14
~
6
W1SY6

13
~
5
W1SY5

12
~
4
W1SY4

11
~
3
W1SY3

10
~
2
W1SY2

9
~
1
W1SY1

8
W1SY8
0
W1SY0

GA

14
~
6
W1SX6

15
~
7
W1EX7

14
~
6
W1EX6

13
~
5
W1EX5

12
~
4
W1EX4

11
~
3
W1EX3

10
~
2
W1EX2

9
W1EX9
1
W1EX1

8
W1EX8
0
W1EX0

WPEY1
1800CEH

15
~
7
W1EY7

14
~
6
W1EY6

13
~
5
W1EY5

12
~
4
W1EY4

11
~
3
W1EY3

10
~
2
W1EY2

9
~
1
W1EY1

8
W1EY8
0
W1EY0

SE

WPEX1
1800CCHST-58-R2

181

Window position bit (for horizontal coordinates): Window start/end X bit (W0SX9 to W0SX0,
W0EX9 to W0EX0, W1SX9 to W1SX0, W1EX9 to W1EX0)

W0SX9~W0SX0
W0EX9~W0EX0
W1SX9~W1SX0
W1EX9~W1EX0

1800C0H
1800C4H
1800C8H
1800CCHnti
alDesignates the horizontal start and end coordinates. Designated coordinate value isthe coordinate value (H counter value) on the TV screen.
Bit 9~0
Bit 9~0
Bit 9~0
Bit 9~0

For W0 start point coordinates
For W0 end point coordinates
For W1 start point coordinates
For W1 end point coordinatesdeThe bit configuration of the register changes according to the setting of the graphics
mode. For normal graphics, the least significant bit becomes invalid data. For
exclusive normal graphics, the most significant bit becomes invalid data; moreover,for special high-resolution graphics, the most significant bit becomes invalid data.
Since it doesn’t have an HO bit, values are in 2 pixel units. Table 8.1 shows the bitcontent of the window position register by graphic mode setting.
Table 8.1 Bit content of window position register for horizontal coordinates

WxxX9 WxxX8 WxxX7 WxxX6 WxxX5 WxxX4 WxxX3 WxxX2 WxxX1 WxxX0
H8
H7
H9
H8
Invalid H8

H6
H7
H7

H5
H6
H6

H4
H5
H5

H3
H4
H4

Invalid H9

H8

H7

H6

H5

H2
H3
H3

H1
H2
H2

H0
H1
H1

Invalid
H0
H0

H4

H3

H2

H1

nfi

Graphics
Mode
NormalHi-ResExclusive
NormalExclusive
Hi-ResCo

Note: 0S, 0E, 1S, or 1E is entered in bit name for xx.

Window position bit (for vertical coordinates): Window start/end Y bit (W0SY8 to W0SY0,W0EY8 to W0EY0, W1SY8 to W1SY0, W1EY8 to W1EY0)

Designates the vertical start and end coordinates. The designated coordinate value
is the coordinate value (V counter value) on the TV screen.
1800C2H
1800C6H
1800CAH
1800CEH

Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0GA

W0SY8~W0SY0
W0EY8~W0EY0
W1SY8~W1SY0
W1EY8~W1EY0For W0 start point coordinates
For W0 end point coordinates
For W1 start point coordinates
For W1 end point coordinates

SE

The bit configuration of the register changes according to the screen mode setting.
Single-density interlace of Normal and high-resolution modes designate the V
counter value in the respective even-numbered and odd-numbered fields.

182

Bit content of the window position register used for vertical coordinates

TV Screen(Interlace) Mode
Normal, Hi-Res(Non-interlace,Single-Density
Interlace)Normal, Hi-Res(Double-Density
Interlace)Exclusive Monitor

WxxY8 WxxY7 WxxY6 WxxY5 WxxY4 WxxY3 WxxY2 WxxY1 WxxY0
V8

V7

V6

V5

V4

V7

V6

V5

V4

V3

V8

V7

V6

V5

V3

V2

V1

V0

V2

V1

V0

Invalid

V1

V0

de

Table 8.2ntial

The lowest significant bit is invalid for the double-density interlace of Normal andhigh-resolution modes. Remaining bits designate the V counter value in various
fields. Bit content of the window position register by setting of the screen mode isshown in Table 8.2.

V4

V3

V2

SE

GA

Co

nfi

Note: 0S, 0E, 1S or 1E is entered in bit name for xx.

ST-58-R2

183

Normal Line Windowntial

The Normal line window stores the horizontal start and end coordinates of eachwindow line as a table in VRAM, and is obtained by designating the vertical startand end coordinates in the window position register. The area surrounded by selected coordinates is inside, the rest of the area is outside. The border line of thewindow is considered part of the inside. The Normal line window is illustrated in
Figure 8.2.

The bit configuration of data stored in the line window table of horizontal start andend coordinates is shown in Figure 8.3.

nfi

de

Coordinates in each line can be selected in the non-interlace and double-density
interlace modes, and in the single-density interlace mode for each two lines. Configuration of the Normal line window table is shown in Figure 8.4.
If the start coordinate of either the horizontal or vertical direction is larger than theend coordinate, then the whole screen is considered an area outside the window.

Horizontal Start Point Coordinates

TV Screen

OutsideCo

Window
InsideVertical Start
Point
Coordinates
Vertical End
Point
Coordinates

Horizontal End Point Coordinates for Each Line
Horizontal Start Point Coordinates for Each Line

Window BoundaryGA

Figure 8.2 Normal line window

Bit 15

14

13

12

11

10

9
8
7
6
5
4
3
2
1
0
Horizontal Start Point Coordinates (10 bits)

14

13

12

11

10

9
8
7
6
5
4
3
2
1
0
Horizontal End Point Coordinates (10 bits)

+0H

SE

Bit 15+2H

Note: Shaded areas are ignored

Figure 8.3 Bit configuration of Normal line window table data

184

Line Window Table (VRAM)

nti
alNon-interlace or double-density interlace
Bit 15+00H

1st line horizontal start point coordinates+02H

1st line horizontal end point coordinates+04H

2nd line horizontal start point coordinates+06H

2nd line horizontal end point coordinates+08H

3rd line horizontal start point coordinates

0+0AH 3rd line horizontal end point coordinates

Single-density interlacedeNote: In the case of double-density interlace, store line data ofboth even and odd fields.

1st & 2nd line horizontal start point coordinates

Line Window Table (VRAM)+02H

1st & 2nd line horizontal end point coordinates+04H

3rd & 4th line horizontal start point coordinates+06H

3rd & 4th line horizontal end point coordinates+08H

5th & 6th line horizontal start point coordinates0

nfi

Bit 15+00H

Co+0AH 5th & 6th line horizontal end point coordinates

Configuration of Normal line window table

SE

GA

Figure 8.4

ST-58-R2

185

Line Window Table Address Register

LWTA0L
1800DAH

15
W0LWE
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2

9
~
1

8
~
0

W0LWTA18

W0LWTA17W0LWTA16

15

14

13

12

11

10

9

8

W0LWTA15W0LWTA14W0LWTA13W0LWTA12W0LWTA11W0LWTA10W0LWTA9W0LWTA8

7

6

5

4

de

LWTA0U
1800D8Hntial

The line window table address register is a write-only 16-bit register that designates
whether to make the Normal window the line window, as well as the lead address ofthat table. It is located from addresses 1800D8H through 1800DEH. Because thevalue is cleared to 0, it must be set after power on or reset.

3

2

1

W0LWTA7 W0LWTA6 W0LWTA5 W0LWTA4 W0LWTA3 W0LWTA2 W0LWTA1

LWTA1L
1800DEH

14
~
6
~

W1LWE

7
~

13
~
5
~

12
~
4
~

11
~
3
~

~

10
~
2

9
~
1

8
~
0

W1LWTA18W1LWTA17W1LWTA16

nfi

15
LWTA1U
1800DCH

0

15

14

13

12

11

10

9

8

W1LWTA15W1LWTA14W1LWTA13W1LWTA12W1LWTA11W1LWTA10W1LWTA9W1LWTA8

7

6

5

4

3

2

1

0

Co

W1LWTA7 W1LWTA6 W1LWTA5 W1LWTA4 W1LWTA3 W1LWTA2 W1LWTA1~Line window enable bit (W0LWE, W1LWE)

Designates whether to make the Normal window a line window.

WxLWE
0
1

1800D8H
1800DCH

GA

W0LWE
W1LWE

Bit 15
Bit 15For W0For W1

Process
Does not process Normal Window to Line Window
Processes Normal Window to Line Window

Note: 0 or 1 is entered in bit name for x.

SE

When this bit is “1”, the line window table must be stored in VRAM.

186

Line window table address bit (W0LWTA18 to W0LWTA1, W1LWTA18 to W1LWTA1)W0LWTA18~W0LWTA16
W0LWTA15~W0LWTA1W1LWTA18~W1LWTA16
W1LWTA15~W1LWTA1

1800D8H
1800DAH
1800DCH
1800DEH

ntialDesignates the lead address of the line window table in VRAM.
Bit 2~0
Bit 15~1
Bit 2~0
Bit 15~1

For W0For W0For W1For W1

The actual lead address is calculated by the expression below. The most significant
bit of the address is ignored when VRAM is 4 Mbits.

de(Lead address of the line window table)= (Line window table address register value 18 bits) X 4H

Sprite Window

Frame Buffer
MSB
0
0
1
1
1
1
0
0

0
0
1
1
1
1
0
0

0 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
0 1 1

TV Screen
Window

InsideOutsideFigure 8.5 Sprite Window

SE

GA

Co

1 1 0
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 0

nfi

The sprite window is obtained by selecting the most significant bit of data when all
frame buffer data of the sprite is palette format data and sprite types are 2 through 7.
The most significant single bit is inside, and the rest of the area is outside. For more
about sprite types see “Sprite types” in section “9.1 Sprite Data.” Figure 8.5 shows asprite window.

ST-58-R2

187

Sprite Control Register

SPCTL
1800E0H

15
~
7
~

14
~
6
~

nti
al

The sprite control register controls sprites. This is a write-only 16-bit register that is
at address 1800E0H. Because the value is cleared to 0, it must be set after power onor reset.

13
12
11
10
9
8
SPCCCS1 SPCCCS0~SPCCN2 SPCCN1 SPCCN0
5
4
3
2
1
0
SPCLMD SPWINEN SPTYPE3 SPTYPE2 SPTYPE1 SPTYPE0

Sprite color calculation condition bit (SPCCCS1, SPCCCS0)

de

See “9.2 Priority and Color Calculation”
Sprite color calculation condition number bit (SPCCN2 to SPCCN0)

See “9.2 Priority and Color Calculation”
Sprite color mode bit (SPCLMD)

See “9.1 Sprite Data”

nfi

Sprite window enable bit: SW enable bit (SPWINEN), bit 4

Designates whether to use the sprite window SW.

Process
Does not use sprite window
Uses sprite windowCo

SPWINEN
01

This bit is only effective when the sprite color mode is mode 0, and for only sprites
2 to 7. WHen this bit is “1”, the most significant bit of the sprite frame buffer is usedas the bit for the sprite window. As a result, MSB shadow can no longer be used.
For more about shadows see “14.1 Shadow Process.”
Do not set this bit to 1, when setting SPCLMD bit to 1.
Sprite type bit (SPTYPE3 to SPTYPE0)

SE

GA

See “9.1 Sprite Data”

188

Window’s Active Area for the Screen

TV Screen

TV Screen

TV Screen

OutsideInsidenti
alNormal and sprite windows can designate whether to use a window in each scroll
screen. The window being used can select inside or outside, in each window, as wellas perform color calculation and transparent processes in active areas. When using
multiple windows, the method of overlap can be selected from AND or OR logic.
Figure 8.6 shows the active area when normal and sprite windows are overlaid by
AND or OR logic.

InsideOutsideInsideNormal Window (W1)

Normal Window (SW)nfi

Normal Window (W0)deOutsideW0 and SW overlap

W1 and SW overlap

•OR

•AND

Co

W0: Outside the area
is valid
W1: Not used
SW: Inside the area
is valid
Valid Area

W0: Not Used
W1: Inside the area
is valid
SW: Inside the area
is valid
Valid Area

SE

GA

Figure 8.6 Active area of window

ST-58-R2

189

8.2 Window Processntial

The three window processes are:
1. Transparency process window
2. Rotation parameter window
3. Color calculation window

The transparency process window forces the selected window effective area to betransparent, and can be used in each screen.

deWhen displaying the RBG0 screen, the rotation parameter window designates thearea displaying the image obtained by rotation parameter A, and designates which
image obtained by rotation parameter B is displayed. Images obtained by rotation
parameter B are displayed in the active area of the designated window; images
obtained by rotation parameter A are displayed outside the window’s active area.

SE

GA

Co

nfi

The color calculation window is a window in which color calculation in the active
area of the designated window is not performed, and is effective for screens using
the color calculation function.

190

Transparency Processing WindowntialWindow process is shown in Figure 8.7.

ABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGH
IJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXTransparent

Screen A

Screen Bde

ABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGH
IJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWX

nfi

ABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGH
IJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXWindow
EnabledArea

Screen A Transparency
Processing Window

Co

Display Image

Rotation Parameter Window

GA

Image acquired via
rotation parameter A

Image acquired via
rotation parameter B

Window
EnabledArea

Image BSE

Image A

ST-58-R2

Rotation Parameter
Window

Display Image

Figure 8.7

Window Process

191

nti
al

Color Calculation Window
Transparent

deScreen that uses
Color Calculation
Function

Window
EnabledArea

nfi

Color Calculation Window

Area that does not
calculate color

Window Process (continued)

SE

GA

Figure 8.7

Co

Display Image

192

Window Control RegisterntialWindow control register designates the method for using windows in each screen,
and is a write-only 16-bit register that is located from addresses 1800D0H through
1800D6H. Because the value is cleared to 0, it must be set after power on or reset.
15
N1LOG
7
N0LOG

14
~
6
~

13
N1SWE
5
N0SWE

12
N1SWA
4
N0SWA

11
N1W1E
3
N0W1E

10
N1W1A
2
N0W1A

9
N1W0E
1
N0W0E

8
N1W0A
0
N0W0A

WCTLB
1800D2H

15
N3LOG
7
N2LOG

14
~
6
~

13
N3SWE
5
N2SWE

12
N3SWA
4
N2SWA

11
N3W1E
3
N2W1E

10
N3W1A
2
N2W1A

9
N3W0E
1
N2W0E

8
N3W0A
0
N2W0A

WCTLC
1800D4H

15
SPLOG
7
R0LOG

14
~
6
~

13
SPSWE
5
R0SWE

12
SPSWA
4
R0SWA

11
SPW1E
3
R0W1E

10
SPW1A
2
R0W1A

9
SPW0E
1
R0W0E

8
SPW0A
0
R0W0A

WCTLD
1800D6H

15
CCLOG
7
RPLOG

14
~
6
~

13
CCSWE
5
~

10
CCW1A
2
RPW1A

9
CCW0E
1
RPW0E

8
CCW0A
0
RPW0A

nfi

de

WCTLA
1800D0H

12
CCSWA
4
~

11
CCW1E
3
RPW1E

Co

Window logic bit: Logic bit (N0LOG, N1LOG, N2LOG, N3LOG, R0LOG, SPLOG, RPLOG, CCLOG)

Designates the method of overlapping windows used in each screen.
1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

SE

GA

N0LOG
N1LOG
N2LOG
N3LOG
R0LOG
SPLOG
RPLOG
CCLOG

ST-58-R2

193

Overlaid LogicOR
AND

Note: N0, N1, N2, N3, R0, SP, RP or CC is entered in bit name for xx.

nti
al

xxLOG
0
1

When W0, W1, and SW window enable bits are all 0, with this bit set to 0, the whole
screen will be window disabled area, and with this bit set to 1, the whole screen will
become window enabled area.

Window enable bit (for W0): W0 enable bit (N0W0E, N1W0E, N2W0E, N3W0E, R0W0E, SPW0E,
RPW0E, CCW0E)
1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window
Process
Does not use W0 window
Uses W0 window

Co

xxW0E
0
1

nfi

N0W0E
N1W0E
N2W0E
N3W0E
R0W0E
SPW0E
RPW0E
CCW0E

de

Designates whether to use the Normal window W0 in each screen.

Note: N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.
Window enable bit (for W1): W1 enable bit (N0W1E, N1W1E, N2W1E, N3W1E, R0W1E, SPW1E,
RPW1E, CCW1E)

SE

GA

Designates whether to use the Normal window W1 in each screen.

1941800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

nti
al

N0W1E
N1W1E
N2W1E
N3W1E
R0W1E
SPW1E
RPW1E
CCW1E
xxW1E
0
1

Process
Does not use W1 window
Uses W1 window

deNote: N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.

Window enable bit (for SW): SW enable bit (N0SWE, N1SWE, N2SWE, N3SWE, R0SWE,
SPSWE, CCSWE)

Designates whether to use the sprite window SW in each screen.

Note:

Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 13

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Color Calculation Window

nfi

xxSWE
0
1

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H

Co

N0SWE
N1SWE
N2SWE
N3SWE
R0SWE
SPSWE
CCSWE

Process
Does not use SW window
Uses SW window

N0, N1, N2, N3, R0, SP, or CC is entered in bit name for xx.

When using the sprite window, set the sprite window enable bit (SPWINEN) of the
sprite control register to 1.

GA

Window area bit (for W0): W0 area bit (N0W0A, N1W0A, N2W0A, N3W0A, R0W0A, SPW0A,
RPW0A, CCW0A)

SE

Designates the valid area of the Normal window W0 used in each screen.

ST-58-R2

195

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

xxW0A
0
1

Process
Enables the inside of W0 window
Enables the outside of W0 window

N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.

de

Note:

nti
al

N0W0A
N1W0A
N2W0A
N3W0A
R0W0A
SPW0A
RPW0A
CCW0A

Window area bit (for W1): W1 area bit (N0W1A, N1W1A, N2W1A, N3W1A, R0W1A, SPW1A,
RPW1A, CCW1A)

Designates the valid area of the Normal window W1 used in each screen.
1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window
Process
Enables the inside of W1 window
Enables the outside of W1 window

Co

xxW1A
0
1

Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10

nfi

N0W1A
N1W1A
N2W1A
N3W1A
R0W1A
SPW1A
RPW1A
CCW1A

Note: N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.
Window area bit (for SW): SW area bit (N0SWA, N1SWA, N2SWA, N3SWA, R0SWA, SPSWA,CCSWA)SEGA

Designates the valid area of the sprite window SW used in each screen.

196

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H

Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 12

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Color Calculation Window

nti
al

N0SWA
N1SWA
N2SWA
N3SWA
R0SWA
SPSWA
CCSWA
xxSWA
0
1

Process
Enables the inside of SW window
Enables the outside of SW window

SE

GA

Co

nfi

de

Note: N0, N1, N2, N3, R0, SP or CC is entered in bit name for xx.

ST-58-R2

197

nti
al

SE

GA

Co

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de

(This page was blank in the original Japanese document)

198

nti
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SE

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Co

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Chapter 9 Sprite Data

ST-58-R2

9.1

9.2

Sprite Data ............................................................200
Sprite Types ....................................................... 200
Sprite Color Mode .............................................. 203
Priority and Color Calculation ............................... 204
Priority Number Selection .................................. 204
Color Calculation Enable Conditions ................. 205
Color Calculation Ratio Selection ...................... 206
Sprite Control Register ....................................... 207
Priority Number Register .................................... 209
Color Calculation Ratio Registers ...................... 210

199

nti
al

9.1 Sprite Data
Sprite frame buffer data received from VDP1 may be either 8-bit pixel or 16-bit
pixels. When the 16-bit pixel format is read, the data may be either RGB or paletteformat, but the frame buffer must be either all 8-bit pixel or all 16-bit pixels.
Sprite TypesdeWhen VDP2 receives palette format sprite data written by VDP1 in the frame buffer,
there are eight types of bit configurations for 16 bits per pixel and eight types of bit
configurations for 8 bits per pixel, for a total of 16 types. These are called sprite
types. Data per one dot consists of dot color data, priority bit, color calculation ratio
bit, and shadow bit composed from dot color code and palette number. Each bit
number changes depending on the sprite type. The value of a bit not having a highenough order in the various bits is regarded as 0.

nfi

Sprite data of RGB format is composed of data of RGB for each 5-bit and color format discriminator bit. Priority bits, color calculation ratio bits, and shadow bits are
considered to be 0.

Table 9.1 Shared Bits
Sprite TypeTpye CType D
Type E
Type FSP1
PR1 and DC7-

Co

Sprite data, when 16-bit per pixel, designates types 0 through 7; when 8 bit per pixel,
designates types 8 through F. When types C through F are designated, priority bit,color calculation ratio bit, and dot color data bit have a shared bit. The shared bits
are shown in Table 9.1.

Shared Bits
SP0
SC1
PR0 and DC7
PR0 and DC7
PR0 and DC6
CC1 and DC7SC0
CC0 and DC6
CC0 and DC6SEGA

SP: Priority bit, color RAM address shared bit
SC: Color calculation ratio bit, color RAM address shared bit
PR: Priority bit
DC: Dot color data
CC: Color calculation ratio bit200• Type 0
Bit 15

14

13

12

11

10

9

8

7

6

nti
al

Sprite types are shown in Figure 9.1.

5

4

3

2

1

0

PR1 PR0 CC2 CC1 CC0 DC10 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0• Type 1
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PR2 PR1 PR0 CC1 CC0 DC10 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

Bit 15

14
SD

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PR0 CC2 CC1 CC0 DC10 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0• Type 3
Bit 15de• Type 2

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

• Type 4
Bit 15

14

13

nfi

SD PR1 PR0 CC1 CC0 DC10 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

12

11

10

9

8

7

6

5

4

3

2

1

0

SD PR1 PR0 CC2 CC1 CC0 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0• Type 5
14

13

12

11

10

9

8

Co

Bit 15

7

6

5

4

3

2

1

0

SD PR2 PR1 PR0 CC0 DC10 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0• Type 6
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SD PR2 PR1 PR0 CC1 CC0 DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0• Type 7
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GA

SD PR2 PR1 PR0 CC2 CC1 CC0 DC8 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

SE

SD : For Shadow Bit (or for Sprite Window Bit)
PR : For Priority Bit
CC : For Color Calculation Ratio Bit
DC : Dot Color Data

ST-58-R2

Figure 9.1

Sprite types

201

14

13

12

11

10

9

8

7

6

5

4

3

nti
al

• Type 8
Bit 152

1

0

PR0 DC6 DC5 DC4 DC3 DC2 DC1 DC0• Type 9
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PR0 CC0 DC5 DC4 DC3 DC2 DC1 DC0• Type A
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

• Type B
Bit 15

14

13

12

11

10

9

8

7

6

de

PR1 PR0 DC5 DC4 DC3 DC2 DC1 DC0

5

4

3

2

1

0

CC1 CC0 DC5 DC4 DC3 DC2 DC1 DC0• Type C
14

13

12

11

10

9

8

7

6

5

4

3

2

nfi

Bit 15

1

0

SP0 DC6 DC5 DC4 DC3 DC2 DC1 DC0• Type D
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

• Type E
Bit 15

14

13

Co

SP0 SC0 DC5 DC4 DC3 DC2 DC1 DC0

12

11

10

9

8

7

6

5

4

3

2

1

0

SP1 SP0 DC5 DC4 DC3 DC2 DC1 DC0• Type F
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SC1 SC0 DC5 DC4 DC3 DC2 DC1 DC0

GA

SD : For Shadow Bit (or for Sprite Window Bit)
PR : For Priority Bit
CC : For Color Calculation Ratio Bit
DC : Dot Color Data
SP : For Priority Bit, Color RAM address shared bits
SC : For Color Calculation Ratio Bit, Color RAM address shared bits
Note: Shaded areas are ignored.

SE

Figure 9.1

202

Sprite types (continued)

Sprite Color ModentialSprite character data has a palette and RGB format, the same as the scroll screen.
When the bit count per one dot is 16 (bits), all 16-bits composed of bits selected by
the sprite type can be used when data inside the frame buffer is only the paletteformat. However, when data of the palette and RGB formats are mixed (because themost significant bit is used to discriminate the color format,) palette format data is
be set to 0 and RGB format set to “1”. Palette format data is then processed with thevalue of the selected sprite type MSB (priority bit or shadow bit) as 0. Sprite datawhen data of palette and RGB formats are mixed is shown in Figure 9.2.
Palette Bank Format
14

13

12

11

0

10 9
8
7
6
5
4
15 bits other than dot color data

RGB Code Format
Bit 1514 13 12 11
5 Bit Blue Data

10

9
8
7
6
5 Bit Green Data

5

4

2

1

0

3
2
1
5 Bit Red Data

0

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1

3

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Bit 15SE

GA

Co

Figure 9.2 Sprite data when palette format and RGB format data are mixed

ST-58-R2

203

9.2 Priority and Color Calculationntial

The priority of sprite and scroll screen is selected according to the size of 3-bit value
called the priority number. Sprites can designate a maximum of eight priority numbers and can select one for each character according to the priority bit within sprite
data.

When using the color calculation function between the sprite and scroll screen, it canbe determined whether to perform color calculation by the value of priority number
selected by sprite character. Up to eight color calculation ratios can be selected; with
one of each character being selected by color calculation ratio in sprite data.

dePriority Number Selection

nfi

Sprite priority number selects one from among eight priority numbers in each spritecharacter by the priority bit of the selected sprite type. When the priority bit of theselected sprite type is 2 bits or less, bits lower than 2 are read as 0, and a 3-bit without a priority number bit are read as 0. When sprite data is in an RGB format, sprite
register 0 is selected. The priority number register selected through the value of thepriority bit is shown in Table 9.2.
Table 9.2 Selection of sprite priority number register

Priority Number Register SelectionCo

For Sprite Register 0 (1800F0H bit 2~0)
For Sprite Register 1 (1800F0H bit 10~8)
For Sprite Register 2 (1800F2H bit 2~0)
For Sprite Register 3 (1800F2H bit 10~8)
For Sprite Register 4 (1800F4H bit 2~0)
For Sprite Register 5 (1800F4H bit 10~8)
For Sprite Register 6 (1800F6H bit 2~0)
For Sprite Register 7 (1800F6H bit 10~8)

SE

GA

For Priority Bits
PR2
PR1
PR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

204

Color Calculation Enable Conditionsnti
al

A sprite not only designates whether to do color calculation by the entire sprite, but
can also designate by the value of the priority number selected in each character andthe value of the most significant bit of color data selected in each dot. There are four
conditions that can be selected.
1. When (priority number) ≤ (color calculation condition number)
2. When (priority number) = (color calculation condition number)
3. When (priority number) ≥ (color calculation condition number)
4. When color data most significant bit is 1

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The color calculation condition number is designated in the sprite control register by
the value of the priority number selected in each sprite character, and the 3-bit value
for comparing size. These conditions are in effect only when the SPCCEN bit of thecolor calculation control register is 1; color calculation will not be done when theregister is 0.

ST-58-R2

205

Color Calculation Ratio Selectionntial

The color calculation ratio of sprites select one of eight color calculation ratios ineach sprite character by the color calculation ratio bit of the designated sprite type
data. When two or less bits are used for color calculation ratio of the designatedsprite type, the low bit is read as 0. When there is no color calculation ratio bit, 8-bit
is also read as 0. When sprite data is in an RGB format, the sprite register 0 is selected.

Selection of the color calculation ratio register through the value of the color calculation ratio bit is shown in Table 9.3.
Table 9.3 Selection of sprite color calculation ratio registerdeColor Calculation Ratio Register Selectionnfi

For Sprite Register 0 (180100H bit 4~0)
For Sprite Register 1 (180100H bit 12~8)
For Sprite Register 2 (180102H bit 4~0)
For Sprite Register 3 (180102H bit 12~8)
For Sprite Register 4 (180104H bit 4~0)
For Sprite Register 5 (180104H bit 12~8)
For Sprite Register 6 (180106H bit 4~0)
For Sprite Register 7 (180106H bit 12~8)

SE

GA

Co

For Color Calculation Ratio Bits
CC2
CC1
CC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

206

Sprite Control Register

SPCTL
1800E0H

15
~
7
~

14
~
6
~

nti
al

The sprite control register controls sprite data, and is a write-only 16-bit register
located at address 1800E0H. Because the value is cleared to 0 after power on or
reset, it must be set.

13
12
11
10
9
8
SPCCCS1 SPCCCS0~SPCCN2 SPCCN1 SPCCN0
5
4
3
2
1
0
SPCLMD SPWINEN SPTYPE3 SPTYPE2 SPTYPE1 SPTYPE0

Sprite color calculation condition bit (SPCCCS1, SPCCCS0), bits 13, 12
SPCCCS
0123

SPCCCS10011

SPCCCS0
0
1
0
1

de

Designates the color calculation condition of sprites.
Condition(Priority number) ≤ (Color calculation condition number) only
(Priority number) = (Color calculation condition number) only
(Priority number) ≥ (Color calculation condition number) only
Only when Color Data MSB is 1.

nfi

When the sprite color format is RGB, color calculation is always performed if
SPCCCS is set to “3”.
Sprite color calculation number bit (SPCCN2 to SPCCN0), bits 10 to 8

Co

Designates the color calculation condition number of sprites.
This value is ignored when SPCCCS is set to “3”.
Sprite color mode bit (SPCLMD), bit 5

Designates the sprite color mode.
SPCLMD
0
1

Sprite Color Format Data
Sprite data is all in palette format
Sprite data is in palette format and RGB format

SEGA

Do not designate a “1” when sprite data are 8-bit pixels.

ST-58-R2

207

Sprite window enable bit (SPWINEN), bit 4nti
alSee “8.1 Window Area”
Sprite type bit (STYPE3 to STYPE0), bits 3 to 0

STYPE2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

STYPE1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

STYPE0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Sprite Data TypeType 0Type 1
Type 2Type 3
Type 4
Type 5
Type 6
Type 7
Type 8Type 9Type A
Type B
Type CType D
Type E
Type F

nfi

STYPE3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

de

Designates the sprite type.

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Co

When sprite data are 16-bit pixels, designate type 0 to 7; and when 8-bit pixels,
designate type 8 to F.

208

Priority Number Register

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

10
S1PRIN2
2
S0PRIN29S1PRIN1
1
S0PRIN18
S1PRIN00
S0PRIN0PRISB
1800F2H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
S3PRIN22
S2PRIN29S3PRIN1
1
S2PRIN18
S3PRIN00
S2PRIN0PRISC
1800F4H

15
~
7
~

14
~
6
~

13
~
5
~

11
~
3
~

10
S5PRIN2
2
S4PRIN29S5PRIN1
1
S4PRIN18
S5PRIN00
S4PRIN0PRISD
1800F6H

15
~
7
~

14
~
6
~

10
S7PRIN2
2
S6PRIN29S7PRIN1
1
S6PRIN18
S7PRIN00S6PRIN0

de

11
~
3
~

nfi

PRISA
1800F0Hntial

The priority number register designates the priority number, and is a write-only 16bit register located at addresses 1800F0H through 1800F6H. Because the value iscleared to 0 after power on or reset, it must be set.

13
~
5
~

12
~
4
~
12
~
4
~

11
~
3
~

Co

Sprite priority number bit (for sprite) (S0PRIN2 to S0PRIN0, S1PRIN2 to S1PRIN0, S2PRIN2 to
S2PRIN0, S3PRIN2 to S3PRIN0, S4PRIN2 to S4PRIN0, S5PRIN2 to S5PRIN0, S6PRIN2 toS6PRIN0, S7PRIN2 to S7PRIN0)

Designates the sprite priority number.
1800F0H
1800F0H
1800F2H
1800F2H
1800F4H
1800F4H
1800F6H
1800F6H

Bit 2~0
Bit 10~8
Bit 2~0
Bit 10~8
Bit 2~0
Bit 10~8
Bit 2~0
Bit 10~8

For Sprite Register 0
For Sprite Register 1
For Sprite Register 2
For Sprite Register 3
For Sprite Register 4
For Sprite Register 5
For Sprite Register 6
For Sprite Register 7SE

GA

S0PRIN2~S0PRIN0S1PRIN2~S1PRIN0S2PRIN2~S2PRIN0S3PRIN2~S3PRIN0S4PRIN2~S4PRIN0S5PRIN2~S5PRIN0S6PRIN2~S6PRIN0S7PRIN2~S7PRIN0

ST-58-R2

209

nti
al

Display priority order increases with the size of the priority number. Sprite characters that use the register set to a priority number value of 0 are treated as transparent
and are not displayed.
Color Calculation Ratio Registers

The color calculation ratio registers selects the color calculation ratio, and are writeonly 16-bit registers located at addresses 180100H through 180106H. Because they
are cleared to 0 after power on or reset, they must be set.
15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
S1CCRT4 S1CCRT3 S1CCRT2 S1CCRT1 S1CCRT0
4
3
2
1
0
S0CCRT4 S0CCRT3 S0CCRT2 S0CCRT1 S0CCRT0

CCRSB
180102H

15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
S3CCRT4 S3CCRT3 S3CCRT2 S3CCRT1 S3CCRT0
4
3
2
1
0
S2CCRT4 S2CCRT3 S2CCRT2 S2CCRT1 S2CCRT0

CCRSC
180104H

15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
S5CCRT4 S5CCRT3 S5CCRT2 S5CCRT1 S5CCRT0
4
3
2
1
0
S4CCRT4 S4CCRT3 S4CCRT2 S4CCRT1 S4CCRT0

CCRSD
180106H

15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
S7CCRT4 S7CCRT3 S7CCRT2 S7CCRT1 S7CCRT0
4
3
2
1
0
S6CCRT4 S6CCRT3 S6CCRT2 S6CCRT1 S6CCRT0

Co

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CCRSA
180100H

Sprite color calculation ratio bit (S0CCRT4 to S0CCRT0, S1CCRT4 to
S1CCRT0, S2CCRT4 to S2CCRT0, S3CCRT4 to S3CCRT0, S4CCRT4 to S4CCRT0, S5CCRT4 to
S5CCRT0, S6CCRT4 to S6CCRT0, S7CCRT4 to S7CCRT0)

SE

GA

Designates the sprite color calculation ratio. The color calculation ratio is for a value
1/32 of RGB various color data.

210

Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8

For Sprite Register 0
For Sprite Register 1
For Sprite Register 2
For Sprite Register 3
For Sprite Register 4
For Sprite Register 5
For Sprite Register 6
For Sprite Register 7ntial180100H
180100H
180102H
180102H
180104H
180104H
180106H
180106H

SE

GA

Co

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S0CCRT4~S0CCRT0S1CCRT4~S1CCRT0S2CCRT4~S2CCRT0S3CCRT4~S3CCRT0S4CCRT4~S4CCRT0S5CCRT4~S5CCRT0S6CCRT4~S6CCRT0S7CCRT4~S7CCRT0

ST-58-R2

211

xxCCRT1

xxCCRT0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Color Calculation Ratio
Top Image : Second Image
31:1
30:2
29:3
28:4
27:5
26:6
25:7
24:8
23:9
22:10
21:11
20:12
19:13
18:14
17:15
16:16
15:17
14:18
13:19
12:20
11:21
10:22
9:23
8:24
7:25
6:26
5:27
4:28
3:29
2:30
1:31
0:32

nti
al

xxCCRT2

dexxCCRT3

Co

nfi

xxCCRT4

Note: S0 to S7 are entered in bit name for xx.

SE

GA

This register is in effect only when the CCMD bit of the color calculation control
register is 0, and is ignored when “1”.

212

nti
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SE

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Co

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de

Chapter 10 Pixels

ST-58-R2

Introduction .................................................................... 214
10.1 Palette Format Pixels ........................................... 214
Sprite Dot Pixels ............................................... 214
Scroll Dot Pixels ................................................ 216
Color RAM Address Offset Register ................. 217
10.2 RGB Format Pixels .............................................. 218
Sprite Pixels ...................................................... 218
Scroll Pixels ...................................................... 218
10.3 Special Function Code ......................................... 220
Special Function Code Select Register ............ 221
Special Function Code Register ....................... 222

213

IntroductionntialWhen sprites and dot color data of each scroll screen are in a palette format, thecolor RAM address offset register value added to the dot color data (configured fromthe palette number and dot color code) becomes the color RAM address. Color dataof that address is output as color data. In the RGB format, dot color data composedof individual red, green and blue values are pixels.

10.1 Palette Format Pixels

deScroll screen dot color data in a palette format designates whether to use special
priority and special color calculation functions according to the lowest 4-bit color
data.

nfi

Palette format pixels are 11 bits wide, and is the color RAM addresses that store pixel
data—the value of the color RAM address offset register of the corresponding screen
added to the highest 3-bits.
Sprite Dot Pixels

SE

GA

Co

Palette format sprite pixels change according to the sprite type that has been designated. When pixels designate sprite types that are 10-bit or lower, missing highorder bits are taken as 0, and the sprite color RAM address offset value is added tothe highest 3 bits and is treated as the color RAM address of that dot. When thecolor RAM mode is set to mode 0 or mode 2, the highest bit of the color RAM address will be ignored.

214•When Sprite Type 0~3, 5
Bit 1098
7
6
11 Bit pixel

5

4

3

2

1

0

7
6
5
10 Bit pixel

4

3

2

1

0

•When Sprite Type 4, 6
Bit 10

9

8

0

0

9
0

8

7
6
5
9 Bit pixel•When Sprite Type C~F
0

9
0

8
0

7

4

3

2

1

0

6
5
4
8 Bit pixel

3

2

1

0

nfi

Bit 10de•When Sprite Type 7
Bit 10nti
alPalette format sprite pixels are shown in Figure 10.1. The sprite color RAM address
is shown in Figure 10.2.

•When Sprite Type 8
Bit 10
0

9
0

8
0

7
0

6
5
4
7 Bit pixel

3

2

1

0

5
4
3
6 Bit pixel

2

1

0

•When Sprite Type 9~B
9
0

8
0

7
0

6
0

Co

Bit 10
0GA

Figure 10.1

Palette format sprite dot color data

SpriteDot Color Data
Color RAM Address
Offset Value for Sprite

11 Bit pixel

Offset Value
3 Bit

SE

Dot Color RAM
Address

ST-58-R2

+
0

0

0

0

0

0

0

0

11 Bit Color RAM Address

Note: When Color RAM is in mode 0 or mode 2, the MSB of the color
RAM address is ignored.

Figure 10.2

Sprite Color RAM Address215

Scroll Dot Pixels

ntial

Scroll pixels in a palette format changes according to the designated character color
count. The color RAM address offset value corresponding to each surface is added
to the highest 3 bits of 11-bit dot color data, and is treated as the color RAM addressof that dot. When color RAM mode is set to mode 0 or mode 2, the highest bit ofcolor RAM address will be ignored.

deBecause the line color screen doesn’t have a corresponding color RAM address offset
value, the 11-bit value read from line color screen table becomes the color RAM
address. Palette format scroll dot color data is shown in Figure 10.3. The scroll
screen color RAM address is shown in Figure 10.4.

• When Character Color count is 16 Colors
9 8
7
6
5
7 Bit Palette Number

Bit 104

32
1
0
4 Bit Dot Color Code• When Character Color count is 256 Colors
87

3 Bit Palette No.

6
5
4
3
2
8 Bit Dot Color Code

1

0

1

0

nfi

9

Bit 10• When Character Color count is 2048 Colors
9

8
7
6
5
4
3
11 Bit Dot Color Code2

Co

Bit 10Figure 10.3

GA

ScrollDot Color Data

Palette format scroll dot color data

Color RAM Address
Offset Value For Each
ScrollSE

Dot Color RAM
Address

11 Bit Dot Color Data

Offset Value
3 Bit
0

+
0

0

0

0

0

0

0

11 Bit Color Ram Address

Note: When the color RAM mode is 0 or 2, the color RAM address MSB isignored.

216

Figure 10.4

Scroll Color RAM Address

Color RAM Address Offset Register

15
~
7
~

14
13
12
N3CAOS2 N3CAOS1 N3CAOS0
6
5
4
N1CAOS2 N1CAOS1 N1CAOS0

CRAOFB
1800E6H

15
~
7
~

14
13
12
~
~
~
6
5
4
SPCAOS2 SPCAOS1 SPCAOS0

11
~
3
~

10
9
8
N2CAOS2 N2CAOS1 N2CAOS0
2
1
0
N0CAOS2 N0CAOS1 N0CAOS0

11
~
3
~

10
9
8
~
~
~
2
1
0
R0CAOS2 R0CAOS1 R0CAOS0de

CRAOFA
1800E4Hntial

The color RAM address offset register is a write only 16-bit register that designates
the sprite and color RAM address offset values corresponding to each scroll screen.
It is located at addresses 1800E4H through 1800E7. Because the value is cleared to 0
after power on or reset, you must set it.

Color RAM address offset bit (N0CAOS2 to N0CAOS0, N1CAOS2 to1800E4H
1800E4H
1800E4H
1800E4H
1800E6H
1800E6HCo

N0CAOS0~N0CAOS2N1CAOS0~N1CAOS2N2CAOS0~N2CAOS2N3CAOS0~N3CAOS3
R0CAOS0~R0CAOS2SPCAOS0~SPCAOS2

nfi

N1CAOS0, N2CAOS2 to N2CAOS0, N3CAOS2 to N3CAOS0, R0CAOS2 to
R0CAOS0, SPCAOS2 to SPCAOS0)
Designates color RAM address offset values with respect to the sprite and each scroll
screen.
Bit 2~0
Bit 6~4
Bit 10~8
Bit 14~12
Bit 2~0
Bit 6~4

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Sprite

The actual color RAM address offset value is calculated by the expression below.
When the color RAM mode is set to mode 0 or mode 2, the highest bit of color RAM
address that calculated the color RAM address offset value will be ignored.

GA

When color RAM mode is mode 0 or mode 2:(color RAM address offset value [= offsetReg << 9] )= (color RAM address offset register 3-bit value) X 200H
When color RAM mode is mode L:SE(color RAM address offset value [= offsetReg << 10] )= (color RAM address offset register 3-bit value) X 400H

ST-58-R2

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10.2 RGB Format Pixels

ntial

RGB format dot color data is 15-bit in sprite and 15-bit or 24-bit data, depending on
character color count in scroll, and becomes dot color data without going throughcolor RAM. When dot color data is 15-bit, the lowest three bits of each individual isfixed at 0 and used.
Sprite Pixels

Bit 149Output Blue Data

5 Bit Blue Data

0

0

0

Output Green Data

5 Bit Green Data

0

0

0

Output Red Data

5 Bit Red Data

0

0

0

Scroll Pixels

43
2
1
5 Bit Red Data

0

Co

Figure 10.587
655 Bit Green Datanfi

13 12 11 10
5 Bit Blue Data

SpriteDot Color DatadeRGB format sprite dot color data is RGB 5-bit data that outputs each of the lowest 3
bits fixed at 0. RGB format sprite dot color data is shown in Figure 10.5.

RGB format sprite dot color data

RGB format scroll dot color data changes according to the character color count.
When 15-bit, the lowest three bits of each individual RGB is fixed at 0 and output.

SE

GA

The back screen is output by fixing the lower 3-bit of each RGB at 0, the same as
when the character color count of the scroll screen is 32,768 colors.

218

nti
al

Scroll dot color data of the RGB format is shown in Figure 10.6.

• When Character Color Count is 32768 Colors
13 12 11 10
5 Bit Blue Data

87655 Bit Green Data

4

3
2
1
0
5 Bit Red Data

Output Blue Data

5 Bit Blue Data

0

0

0

Output Green Data

5 Bit Green Data

0

0

0

Output Red Data9de

Bit 14ScrollSpriteDot Color Data

5 Bit Red Data

0

0

0

• When Character Color Count is 16,770,000 Colors
22

21 20 19 18
8 Bit Blue Data

Bit 1514

13 12 11 10
8 Bit Green Data

16

9

8

7

6

5

4
3
2
8 Bit Red Data

10

8 Bit Blue DataCo

Output Blue Data

17

nfi

Bit 23ScrollDot Color Data

Output Green Data

8 Bit Green Data

Output Red Data

8 Bit Red Data

RGB Format Scroll Dot Color Data

SE

GA

Figure 10.6

ST-58-R2

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10.3 Special Function Codential

The special function, which performs in all scroll screens, has two functions: thespecial priority function, and the special color calculation function. When used inevery dot, the dot color code that activates the special function can designate two
special function code registers. Also, each scroll screen designates which of the two
special function code registers will be used.

de

The special function code register has two 8-bit registers: special function code A,
and special function code B. Each bit corresponds to two dot color code lower 4-bit
values using the special function. The dot color code changes the bit number according to the character color count of each scroll screen. However, each bit of thespecial function code register will always correspond to the value of the lowest four
bits of the dot color code. Moreover, the special function code is used only when thecolor format of scroll screen is the palette format.

nfi

See “11.2 Special Priority Function” and “12.2 Special Color Calculation Function”
for using the special function. Figure 10.7 shows the dot color code that corresponds
to special function code.

• When Character Color Count is 16 Colors
Bit 3
2
1
0

Co

Corresponding 4 bits

• When Character Color Count is 256 Colors
Bit 7

6

5

4

3
2
1
0
Corresponding 4 bits

• When Character Color Count is 2048 Colors
9

8

GA

Bit 10SE

Figure 10.7

220

7

6

5

4

3
2
1
0
Corresponding 4 bits

Dot Color Data Corresponding to Special Function CodeSpecial Function Code Select Register

SFSEL
180024H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
R0SFCSnti
al

The special function code select register is a write-only 16-bit register that designates
the special function code that activates all scroll screens. It is located at address
180024H. Because the value is cleared to 0 after power on or reset, it must be set.
11~
3
N3SFCS

10~2
N2SFCS

9~1
N1SFCS

8~0
N0SFCSSpecial function code select bit (N0SFCS, N1SFCS, N2SFCS, N3SFCS,
R0SFCS)
180024H
180024H
180024H
180024H
180024H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0nfi

N0SFCS
N1SFCSN2SFCS
N3SFCS
R0SFCSdeDesignates the special function code effecting every scroll screen.

xxSFCS
0
1

Process
Enables special function code A
Enables special function code B

SE

GA

Co

Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.

ST-58-R2

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Special Function Code Register

SFCODE
180026H

15
SFCDB7
7SFCDA7

14
SFCDB6
6SFCDA6

13
SFCDB55SFCDA512
SFCDB44SFCDA4

11
SFCDB3
3
SFCDA3

10
SFCDB2
2
SFCDA2

Special function code bit (SFCDA7 to SFCDA0, SFCDB7 to SFCDB0)SFCDA7~SFCDA0
SFCDB7~SFCDB0

180026H
180026H

Bit Name
SFCDx0
SFCDx1SFCDx2SFCDx3SFCDx4SFCDx5SFCDx6SFCDx7

Dot Color Code
When lower 4 bits of dot color code are, 0H or 1H
When lower 4 bits of dot color code are, 2H or 3H
When lower 4 bits of dot color code are, 4H or 5H
When lower 4 bits of dot color code are, 6H or 7H
When lower 4 bits of dot color code are, 8H or 9H
When lower 4 bits of dot color code are, AH or BH
When lower 4 bits of dot color code are, CH or DH
When lower 4 bits of dot color code are, EH or FH

For Special Function Code A
For Special Function Code B

Co

Note: A or B is entered in bit name x.
Settings
0
1

8
SFCDB00
SFCDA0nfi

Bit 7~0
Bit 15~8

9
SFCDB1
1
SFCDA1deDesignates special function codes A and B.

ntial

The special function code register is a write-only 16-bit register that designates
special function code A and special function code B. It is located at address
180026H. Because the value is cleared to 0 after power on or reset, it must be set.

Process
Does not use special functions
Uses special functions

SEGA

The special function code is used when mode 2 is designated in the special priority
mode registers or when designating mode 2 in the special color calculation mode
register. For more information see “11.2 Special Priority Function” or “12.2 Special
Color Calculation Function.”

222

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Chapter 11 Priority Function

ST-58-R2

Introduction ....................................................................224
11.1 Priority Function ................................................... 224
Priority Number ................................................. 224
Priority Number Register .................................. 225
11.2 Special Priority Function ...................................... 227
Special Priority Mode Register ......................... 229
11.3 Insertion of Line Color Screen ............................. 230
Line Color Screen Enable Register .................. 231

223

IntroductionntialVDP2 compares the priority number values of sprites and scroll screens and decides
the display priority order from the top three. The priority number of a sprite thenselects each character from a maximum of eight values. The priority number of all
scroll screens can also change the value of each dot and character by using the special priority function.
The line color screen can be inserted into the number two position, one below thescreen, when the designated screen is at the highest priority.

de11.1 Priority Function

Priority
Number= 6

nfi

The priority (display priority order) of sprites and scroll screens compares sizes ofthe values of the screen priority number without transparent dots positioned in thesame TV screen coordinates for each dot. The screen priority increases as the valueof the priority number increases. The top image is made of the highest priority dots;
the second image is made of the second highest dots; and the third image is made of
the third highest dots. All sprite and scroll screen dots display the back screen in thetransparent position. Figure 11.1 shows the priority function.
Priority
Number= 4

Priority
Number= 2

Transparent

Co

Transparent

Priority
Number= 1

Transparent

GA

Back Screen

Top Image

Figure 11.1

Second Image

Back Screen

Third Image

Priority Function

SE

Priority Number

The scroll screen has one 3-bit priority number register in each screen. This priority
number normally is used in the entire surface, but can change the value of the leastsignificant bit in each dot and character according to the special priority mode. The
sprite priority number can select one of eight 3-bit priority number registers for eachcharacter. For information about selecting a sprite priority number register see“Priority Number Selection” in section “9.2 Priority and Color Calculation.”

224

Table 11.1 Priority when the priority numbers are equal
NormalWhen inputting
external image data

Highest::::LowestSprite
RBG0
NBG0
NBG1
NBG2
NBG3

Sprite
RBG0
NBG0
EXBG
NBG2
NBG3

When displaying 2
screens of the rotation
scroll screen
SpriteRBG0
RBG1-When inputting external
images per 2 screens of
the rotation scroll screen
Sprite
RBG0
RBG1
EXBG
-

de

PriorityntialScreen priority increases when the value of the priority number increases. Whenpriority numbers are equal, they follow the order shown in Table 11.1. When thevalue of a priority number is OH, it is read as transparent.

Priority Number Register

14
~
6
~

PRINB
1800FAH

15
~
7
~

14
~
6
~

PRIR
1800FCH

15
~
7
~

13
~
5
~

12
~
4
~

11
~
3
~

10
N1PRIN2
2
N0PRIN29
N1PRIN1
1
N0PRIN18
N1PRIN00
N0PRIN0

13
~
5
~

12
~
4
~

11
~
3
~

10
N3PRIN2
2
N2PRIN29
N3PRIN1
1
N2PRIN18
N3PRIN00
N2PRIN0

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
R0PRIN2

9~
1
R0PRIN1

8~
0
R0PRIN0Co

PRINA
1800F8H

15
~
7
~

nfi

The priority number register designates the priority number. This is a write-only 16bit register located at addresses 1800F8H to 1800FCH. Because the value is cleared
to 0 after power on or reset, it must be set.

SE

GA

14
~
6
~

ST-58-R2

225

Designates the priority number of each screen scroll.
N0PRIN2~N0PRIN0
N1PRIN2~N1PRIN0
N2PRIN2~N2PRIN0
N3PRIN2~N3PRIN0R0PRIN2~R0PRIN01800F8H
1800F8H
1800FAH
1800FAH
1800FCHBit 2~0
Bit 10~8
Bit 2~0
Bit 10~8
Bit 2~0ntialPriority number bit (for scroll screen) (N0PRIN2 to N0PRIN0, N1PRIN2 to
N1PRIN0, N2PRIN2 to N2PRIN0, N3PRIN2 to N3PRIN0, R0PRIN2 to R0PRIN0)

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0

SE

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Co

nfi

de

Larger priority numbers are given a higher display priority order. When the valueof the priority number is 0, it is treated as transparent and not displayed. For more
about priority number register of sprites, see “Priority Number Register” of “9.2Priority and Color Calculation.”226

11.2 Special Priority Function

Designates the least significant bit of the priority number in each screen
Designates the least significant bit of the priority number in each character
Designates the least significant bit of the priority number in each dot

de

1.
2.
3.

nti
al

The special priority function changes the least significant bit of the 3-bit priority
number corresponding to every scroll screen in each character and dot. Using thisfunction to change the priority of a portion of the scroll screen displays one surface
as multiple screens. Furthermore, the least significant bit of the priority number
changes only by the special priority function; the highest 2 bits are used with theregister values. The special priority function has the following three modes.

When designating the least significant bit of the priority number in each screen, thevalue of the priority number register in each scroll screen is used unchanged.

nfi

When designating each character, the value of a special priority bit within patternname data is used as the least significant bit of the priority number. For more information about special priority bits, see “4.6 Pattern Name Table (Page).”Co

When designating each dot in character patterns designating 1 (the special priority
bit within pattern name data), only dots that coincide with the dot color code aredesignated in the special function code. The least significant bit of the priority
number is set to 1, the rest are fixed at 0. Do not set this mode when the color formatof scroll screen is RGB. For more about the dot color code see “10.3 Special Function
Code.”SEGA

When the 3-bit priority number value obtained by the special priority function isOH, that screen, character, or dots are treated as transparent. Table 11.2 shows the
special priority function by mode.

ST-58-R2

227

Special priority function by mode

Special Priority Special Priority
Mode
Selection
Mode 0
Selected per eachscreenMode 1
Select per eachcharacter
Mode 2
Setting not allowed

Color Format

Priority Number LSB Valuenti
al

Table 11.2

Palette Format or RGB Priority number register LSB
Formatvalue
Palette Format or RGB Value of the special priority bit
Formatin the pattern name data
Palette Format
When the special priority bit in
the pattern name data is equal
to one, only the dot coinciding
with the dot color code
selected for special function
code becomes 1, while therest become 0.
RGB Format
Setting Invalid

SE

GA

Co

nfi

de

When the display format designates mode 1 or 2 in the scroll screen of the bit map
format, it is not the special priority bit within the pattern name data, but the special
priority bit of the bit map palette number register that is used.

228

Special Priority Mode Register

SFPRMD
1800EAHntial

The special priority mode register is a write-only 16-bit register that designates themode of the special priority function corresponding to each scroll screen, and islocated at address 1800EA. Because the value clears to 0 after power on or reset, it
must be set.
15
14
13
12
11
10
9
8
~
~
~
~
~
~
R0SPRM1 R0SPRM0
7
6
5
4
3
2
1
0
N3SPRM1 N3SPRM0 N2SPRM1 N2SPRM0 N1SPRM1 N1SPRM0 N0SPRM1 N0SPRM0deSpecial priority mode bit (N0SPRM1, N0SPRM0, N1SPRM1, N1SPRM0,N2SPRM1, N2SPRM0, N3SPRM1, N3SPRM0, R0SPRM1, R0SPRM0)

Designates the special priority function mode of each screen scroll.

xxSPRM100111800EAH
1800EAH
1800EAH
1800EAH
1800EAH

xxSPRM001
01

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6
Bit 9,8

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0nfi

N0SPRM1, N0SPRM0
N1SPRM1, N1SPRM0N2SPRM1, N2SPRM0
N3SPRM1, N3SPRM0R0SPRM1, R0SPRM0

Mode
Mode 0Mode 1Mode 2-

Process
Select the priority number LSB per each screen
Select the priority number LSB per each character
Select the priority number LSB per each dot
Selection not allowedCo

Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.

SEGA

Do not set mode 2 when the scroll screen color format is the RGB mode.
Do not set in EXBG any other mode but 0.
Character or dot in which priority number is 0 is considered transparent.

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229

11.3 Insertion of Line Color Screen

Priority
Number= 6

Priority
Number= 4

Priority
Number= 2

Priority
Number= 1

Transparent

Transparent

Screen that forces
the insertion of line
color screen

nfi

Screen that forces
the insertion ofline color screendeTransparentntial

The line color screen does not have a priority number register; it forcefully inserts
the top image as the second image, and calculates color. Meanwhile, the original
second image becomes the new third image, and the old third image becomes the
fourth image. Figure 11.2 shows insertion of the line color screen.

Line Color Screen

Back Screen

Co

Back Screen

Top Image

Second Image

Third Image

SE

GA

Figure 11.2 Line Color Screen Insertion

230

Back Screen

Fourth ImageLine Color Screen Enable Register

LNCLEN
1800E8H

15
~
7
~

14
~
6
~

13
~
5
SPLCEN

12~
4
R0LCENntial

The line color screen enable register designates whether to insert the line color
screen when each screen is a top image. This is a write-only 16-bit register located ataddress 1800E8H. Because the value is cleared to 0 after power on or reset, you must
set it.
11~
3
N3LCEN

10~
2
N2LCEN

9~
1
N1LCEN

8~
0
N0LCENdeLine color enable bit (N0LCEN, N1LCEN, N2LCEN, N3LCEN, R0LCEN,SPLCEN)

Designates whether to insert the line color screen when each screen is a top image.
1800E8H
1800E8H
1800E8H
1800E8H
1800E8H
1800E8H

xxLCEN
0

Note:

Co

1

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5

nfi

N0LCENN1LCENN2LCEN
N3LCENR0LCENSPLCENFor NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Sprite

Process
Does not insert the line color screen whencorresponding screen is top image
Inserts the line color screen when corresponding
screen is top image

N0, N1, N2, N3, R0, or SP is entered in the bit name for xx.

SEGA

A line color screen is inserted only in the second image section of the screen designated for insertion, thus becoming the top image. Sprites can only be designated intheir entirety. To designate each character, they must be controlled by their color
calculation ratio value. This register cannot be used at the same time as the gradation calculation function.

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(This is page was blank in the original Japanese document)

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Chapter 12 Color Calculations

ST-58-R2

Introduction ....................................................................234
12.1 Color Calculation Function................................... 234
Normal Color Calculation .................................. 234
Extended Color Calculation Function ............... 236
12.2 Gradation Calculation Function ........................... 238
Color Calculation Control Register ................... 240
Color Calculation Ratio Register....................... 243
12.3 Special Color Calculation Function ...................... 245
Special Color Calculation Mode Register ......... 247

233

IntroductionntialVDP2 calculates, by a designated ratio, color data of second and top images obtained
comparing priorities of sprite and each scroll screen. The sprite and color calculation ratio can select each character from one of eight values. The color calculation
enable of every scroll screen can designate each character and dot by using thespecial color calculation function.

deWith the second and third images at a fixed ratio, the colors of up to four screens canbe calculated by doing color calculations in the second image. In addition, distantbackgrounds can be shaded causing the gradation calculation function to be enabled.

12.1 Color Calculation Function

nfi

The color calculation function calculates with a ratio designating the top and second
images (or three images, the second image, third image, forth image, images calculated at a set ratio) by individual RGB color, and is able to produce an effect of overlapping a group of semi-transparent screens. The color calculation function isshown in Figure 12.1.
Priority Number = 4

Priority Number = 2

Transparent

Co

Transparent

GA

Back
ScreenF igure 12.1

Color calculation function

SE

Normal Color Calculation

There are two types of modes when calculating color by the top and second images:
1. Top and second images add according to the value of the color calculation ratio.
2. Top and second images add by the value unchanged.

234

de

1. Designates by the top image
2. Designates by the second imagential

The value of the color calculation ratio of each screen is designated in the registerwhen using the color calculation mode to add in proportion to the value of color
calculation ratio. The color calculation ratio of the sprite can designate one registerfrom a maximum of eight for each character; the scroll screen color calculation ratio
designates to the register of each screen. For more about sprite color calculation
ratio see “Color Calculation Ratio Register” in “9.2 Priority and Color Calculation.”
The color calculation ratio of each screen is designated by 5 bits, and a total of 32
steps: top image : second image = 31 : 1 to 0 : 32 can be selected. There are two kindsof modes for designating the value of that ratio.

nfi

When designating with the top image, the sprite that becomes the top image or thecolor calculation ratio value of the scroll screen is used without any relation to thesecond image screen. When designating with the second image, the color calculation ratio can be changed by the screen of the second image. The sprite, scroll screen
values, line color screen, and back screen color calculation ratio values can be used.

SE

GA

Co

When using the color calculation mode to add by the value, gradually rewrite fromthe top image color data from 00H to the original color to create a fade-in effect of
the top image over the second image. Be aware that doing so may result in colorthat is concurrent with fade-in becoming brighter than the original. Addition resultsthat exceed FFH are treated as FFH. Figure 12.2 shows the color calculation ratiomode.

ST-58-R2

235

Priority Number = 4

Priority Number = 2

Screen B

Transparent
ScreenC

Transparent

Color Calculation Ratio
16:16

Color Calculation Ratio
24:8

Color Calculation Ratio
20:12

When selecting the top screen image
Screen B

Screen C

Figure 12.2

Back
ScreenScreen C

Screen A : Screen B = 20 : 12
Screen A : Screen C = 24 : 8
Screen A : Back = 28 : 4

nfi

Screen A : Screen B =16 : 16
Screen A : Screen C =16 : 16
Screen A : Back =16 : 16

Color Calculation Ratio
28:4

When selecting the second screen image
Screen B

Back
ScreenBack Screen

deScreen A

ntialPriority Number = 6

Color calculation ratio mode

Co

There is no limitation in calculating color when the TV screen mode is the Normal
mode. But when the TV screen mode is the high resolution mode or Exclusive monitor mode, the color RAM mode and second image color format hav limitations.
Table 12.1 shows limitations of the color calculation function.
Table 12.1 Color calculation function when in the high resolution mode or special monitor mode
Color RAM Mode
Mode 0Mode 1GA

Mode 2

Second Image Color Format
Palette format or RGB format
Palette format
RGB format
Palette format
RGB format

Color Calculation Function
Can be used
Cannot be used
Can be used
Cannot be used
Can be used

Extended Color Calculation Function

SE

The extended color calculation function makes second image data of the result of thesecond and third images calculated by a fixed ratio. Calculating the color of thesecond and top images makes possible three screen color calculation. Inserting aline color screen creates third image data resulting from color calculation of the thirdand fourth images calculated by a fixed ratio, and makes second image data byadding the third image and line color data calculated by a fixed ratio. Therefore, four
screen color calculation is possible. The extended color calculation function can beused only when in the TV screen mode is the Normal mode.

236

nti
al

When performing extended color calculation, whether to add the third and fourth
images complies with the screen color calculation enable bit of the third image
screen, and whether to add the second and third images complies with the color
calculation enable bit of the second image screen.
When the extended color calculation function is used, the extended color calculation
ratio changes according to the color RAM mode, the line color screen insertion, thecolor calculation enable bit value of second and third images and color format, andthe color format of the fourth image.

Normal CasedeFigure 12.3 shows the extended color calculation function; Table 12.2 shows theextended color calculation ratios.

When inserting line color screen

When second
image screen
color calculation
enable bit =0

When second
image screen
color calculation
enable bit =1

Second image
after expanded
color
calculation

Second image
after expanded
color
calculation

When line color
calculation
enable bit =1,
third image
screen color
calculation
enable bit =1

Second image
after expanded
color
calculation

Second image
after expanded
color
calculation

Second ImageLine Color
ScreenLine Color
Screen+++Third image

Third image

Third image

Co

nfi

When line color
calculation
enable bit =1,
third image
screen color
calculation
enable bit =0

SE

GA

Second image

ST-58-R2

Figure 12.3+
Fourth Image

Extended Color Calculation Function237

Extended Color Calculation Ratio

Mode
0

Does notInsertInserts
Does notInsert

Mode
1
or
Mode
2

Color Calculation
Enable Bit Value

Extended Color
Calculation Ratio

2nd Image 3rd Image 4th Image 2nd Image 3rd Image 2nd:3rd:4th (Image)
Palette or
Palette or0
4:0:0
RGB format RGB format
1
2:2:0
PalettePalette00 or 1
4:0:0
or RGBor RGB10
2:2:0
formatformat11
2:1:0
PalettePalette0 or 1
4:0:0
or RGB
formatformatRGB0
4:0:0
format1
2:2:0
PalettePalette or
0 or 10 or 1
4:0:0
formatRGB format
Palette00 or 1
4:0:0
RGB
format1
0 or 1
2:2:0
formatRGB
00 or 1
4:0:0
format
1
0
2:2:0
1
1
2:1:1

The extended color calculation function cannot be used when the TV screen mode in is thehigh-resolution or Exclusive monitor mode. When inserting the line color screen, the color
format of the second image becomes the palette format. The extended color calculation ratio
is for a value that is 1/4 times the individual RGB data.

nfi

Note:

Inserts

Color FormatntialColor Line ColorRAM
ScreenModedeTable 12.2

Co

12.2 Gradation Calculation Function

The gradation calculation function calculates the horizontal color data of the designated one screen by a fixed ratio, and can create a gradation effect of the distantbackground. This function can only be used when the TV screen mode is the Normal mode, and the color RAM mode is mode 0. Gradation Calculation adds color
data of a designated screen for values 1/4 times that of individual RGB by the ratio
below.

GA(2 dots left display coordinates : (1 dot left display coordinates :color data)
color data)(display coordinates = 1:1:2
color data)SE

Here, the added results of the area in which the designated screen becomes the top
or second images is forced to be the second image. By calculating color of the second and top images, it is possible to display pictures in which gradation calculations
have been done. The second image of the area, in which the gradation calculation
designated screen is not a top or second image, becomes the image determined bynormal priority.

238

Priority number = 4

transparent

transparent

Screen A

Screen B

ScreenB
Screen A

Screen C
Screen designated to be shaded

Second Image
Back Screen

nfi

Top Image
Screen C

Priority number = 2

dePriority number = 6ntialScreens using gradation calculation have no transparent dots. If gradation calculation is performed for screens having transparent dots, correct calculation cannot bedone by that boundary. If the gradation calculation function is used, yit is not possible to insert the line color screen. In addition, the extended color calculation function can no longer be used. Figure 12.4 shows the gradation calculation function.

ScreenC
Screen BCo

The area in screen C thatis the top image or second
image is forced to switch to
shaded screen C

Second Image
ShadedScreen C

Screen B
Color Operation

SE

GA

Color Function used in Screen C

ST-58-R2

Figure 12.4

Display Image
ShadedScreen C
ScreenB
Screen A

Gradation Calculation Function239

Color Calculation Control Register

1800ECH

15
BOKEN
7
~

14
BOKN2
6
SPCCEN

13BOKN1
5LCCCEN

12
BOKN0
4R0CCEN

11~3
N3CCEN

Gradation enable bit (BOKEN), bit 15

Determines whether to use the gradation function.

10
EXCCEN
2
N2CCEN

9CCRTMD
1
N1CCEN

8CCMD
0N0CCEN

Process
Do not use gradation calculation function
Use gradation calculation function

de

BOKEN
0
1

nti
al

The color calculation control register is a write-only 16-bit register that controls color
calculation, and is located at address 1800ECH. Because the value is cleared to 0
after power on or reset, the value must be set.

nfi

If this bit is 1, the extended color calculation function can no longer be used.
The gradation calculation function can only be used when the TV screen mode is theNormal mode, and the color RAM mode is mode 0.
Gradation screen number bit: Gradation number bit (BOKN2 to BOKN0), bits 14 to 12

Designates the screen using the gradation (shading) calculation function.
BOKN1
0
0
1
1
0
0
1
1

BOKN0
0
1
0
1
0
1
0
1

Screen Using Gradation Calculation Function
SpriteRBG0
NBG0 or RBG1
Invalid
NBG1 or EXBG
NBG2
NBG3
Invalid

Co

BOKN2
0
0
0
0
1
1
1
1

Extended color calculation enable bit (EXCCEN), bit 10

SEGA

Determines whether to use the extended color calculation function.

240

Process
Do not use extended color calculation
Use extended color calculation

nti
al

EXCCEN0
1

The above calculation function cannot be used at the same time as the gradation
calculation function. When the BOKEN bit is 1, this bit is ignored. The extended
color calculation function can only be used when in the TV screen and Normal
modes, and cannot be used when in the high-resolution mode or Exclusive monitor
mode.
Color calculation ratio mode bit (CCRTMD), bit 9

Designates the color calculation ratio mode.
Mode
0
1

Process
For color calculation ratio, select per top screen side
For color calculation ratio, select per second screen sidede

CCRTMD
0
1

The top image always designates whether to perform normal color calculation.
Color calculation mode bit (CCMD), bit 8

CCMD
0
1

Mode
0
1

nfi

Designates the color calculation mode.

Process
Add according to the color calculation register value
Add as is

SE

GA

Co

When in mode 1, the values of the color calculation ratio registers of each screen are
ignored.

ST-58-R2

241

Color calculation enable bit (N0CCEN, N1CCEN, N2CCEN, N3CCEN,
R0CCEN, LCCCEN, SPCCEN)

N0CCEN
N1CCEN
N2CCEN
N3CCEN
R0CCENLCCCENSPCCEN

1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6

Process
Does not color-calculate
Color-calculatesdexxCCEN
01

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For LNCL
For SpritentialDesignates whether to perform color calculation (color calculation enable)

Note: N0, N1, N2, N3, R0, LC, or SP is entered in bit name for xx.

SE

GA

Co

nfi

When calculating color between the top and second images, calculation is controlled
by the color calculation enable bit of the top image. When using the extended color
calculation function, control between the second and third images is done by thecolor calculation enable bit of the second image, and control between the third andfourth images is done by the color calculation enable bit of the third image.

242

Color Calculation Ratio RegisterntialThe color calculation ratio register is a write-only 16-bit register that designates thecolor calculation ratio, and is located at addresses 180108H to 18010EH. Because thevalue is cleared to 0 after power on or reset, the value must be set.
15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
N1CCRT4 N1CCRT3 N1CCRT2 N1CCRT1 N1CCRT0
4
3
2
1
0
N0CCRT4 N0CCRT3 N0CCRT2 N0CCRT1 N0CCRT0

CCRNB
18010AH

15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
N3CCRT4 N3CCRT3 N3CCRT2 N3CCRT1 N3CCRT0
4
3
2
1
0
N2CCRT4 N2CCRT3 N2CCRT2 N2CCRT1 N2CCRT0

CCRR18010CH

15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
~
~
~
~
~
4
3
2
1
0
R0CCRT4 R0CCRT3 R0CCRT2 R0CCRT1 R0CCRT0

CCRLB
18010EH

15
~
7
~

14
~
6
~

nfi

de

CCRNA
180108H

13
~
5
~

12
11
10
9
8
BKCCRT4 BKCCRT3 BKCCRT2 BKCCRT1 BKCCRT0
4
3
2
1
0
LCCCRT4 LCCCRT3 LCCCRT2 LCCCRT1 LCCCRT0Co

Color calculation ratio bit (for scroll screens): (N0CCRT4 to N0CCRT0,
N1CCRT4 to N1CCRT0, N2CCRT4 to N2CCRT0, N3CCRT4 to N3CCRT0, R0CCRT4 to R0CCRT0,LCCCRT4 to LCCCRT0, BKCCRT4 to BKCCRT0)

Designates the color calculation ratio of each scroll screen. The color calculation
ratio corresponds to a value 1/32 times R,G,B color data.
180108H
180108H
18010AH
18010AH
18010CH
18010EH
18010EH

Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8
Bit 4~0
Bit 4~0
Bit 12~8

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For LNCLFor BackSE

GA

N0CCRT4~NOCCRT0
N1CCRT4~N1CCRT0
N2CCRT4~N2CCRT0
N3CCRT4~N3CCRT0R0CCRT4~R0CCRT0LCCCRT4~LCCCRT0BKCCRT4~BKCCRT0

ST-58-R2

243

xxCCRT3

xxCCRT2

xxCCRT1

xxCCRT0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Color Calculation Ratio
Top Image : Second Image
31:1
30:2
29:3
28:4
27:5
26:6
25:7
24:8
23:9
22:10
21:11
20:12
19:13
18:14
17:15
16:16
15:17
14:18
13:19
12:20
11:21
10:22
9:23
8:24
7:25
6:26
5:27
4:28
3:29
2:30
1:31
0:32

Co

nfi

de

nti
al

xxCCRT4

Note: N0, N1, N2, N3, R0, LC, or BK is entered in bit name for xx.

SEGA

For more about the color calculation ratio register of sprites see “Color Calculation
Ratio Register” in “9.2 Priority and Color Calculation.”244

12.3 Special Color Calculation Function

1.
2.
3.
4.

nti
al

The special color calculation function designates the color calculation enable not
only by the entire screen but by character units and dot units. See the four modes
below.
Color calculation enable designates each screen.
Color calculation enable designates each character.
Color calculation enable designates each dot.
Color calculation enable designates by the most significant bit of color data.

deWhen designating color calculation enable for each screen, color calculation is performed when the color calculation enable bit value in the color calculation control
register that corresponds to each scroll screen is 1.

nfi

When designating each character in a scroll screen that the color calculation enable
bit has designated 1, color calculation is performed only in character patterns of a
special color calculation bit value of 1 in pattern name data. For more about the
special color calculation bit in pattern name data see “4.6 Pattern Name Table.”Co

When designating each dot, color calculation is performed only in dots that agreewith the dot color code designated in the special function code, and in the character
pattern designated 1 in which the value of the special color calculation bit within thepattern name data of the scroll screen has a color calculation enable bit of 1. Do not
set this mode when the color format of the scroll screen is the RGB format. For more
about the special function code see “10.3 Special Function Code.”GA

When designating with the most significant bit of color data, color calculation is
performed only in dots that used color data when the most significant bit is set at 1,
and when the scroll screen where the color calculation enable bit is designated 1 is ina palette format. Color calculation will always be performed if this mode is designated when the scroll screen, where the color calculation enable bit is designated 1,
is in the RGB format.

SE

When mode 1 or 2 is designated in a bit map format scroll screen, the special color
calculation bit of the bit map number register is used, not the special color calculation bit within pattern name data. Table 12.3 shows the special color calculation
mode.

ST-58-R2

245

Table 12.3 Special Color Calculation Mode
Special Color
Calculation Selection
Select per screen

Mode 1

Select per character

Mode 2

Select per dot

Mode 3

Select with color data
MSB

Color Format
Palette format or RGB
formatPalette format or RGB
formatRGB format
Palette format
RGB format

Color calculation bit = 1 andpattern name data special
color calculation bit = 1
Color calculation bit = 1 andpattern name data special
color calculation bit = 1 and
The dot that matches dot color
code selected per special
function code
Invalid
Color calculation bit = 1 and
The dot using color data
where MSB = 1
Color calculation enable bit =1

dePalette format

Color Calculation Enable
Condition
Color calculation enable bit =1nti
alSpecial Color
Calculation Mode
Mode 0

SE

GA

Co

nfi

The special color calculation mode can designate only for top images. Otherwise, it
is fixed at 0.

246

Special Color Calculation Mode Register

SFCCMD
1800EEHntial

The special color calculation mode register is a write-only 16-bit register that designates the special color calculation function mode for each scroll screen, and is located at address 1800EEH. Because the value is cleared to 0 after power on or reset,
you must set the value.
15
14
13
12
11
10
9
8
~
~
~
~
~
~
R0SCCM1 R0SCCM0
7
6
5
4
3
2
1
0
N3SCCM1 N3SCCM0 N2SCCM1 N2SCCM0 N1SCCM1 N1SCCM0 N0SCCM1 N0SCCM0

Special color calculation mode bit (N0SCCM1, N0SCCM0, N1SCCM1,
N1SCCM0, N2SCCM1, N2SCCM0, N3SCCM1, N3SCCM0, R0SCCM1, R0SCCM0)

xxSCCM100111800EEH
1800EEH
1800EEH
1800EEH
1800EEH

xxSCCM001
01

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6
Bit 9,8

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0nfi

N0SCCM1, N0SCCM0
N1SCCM1, N1SCCM0
N2SCCM1, N2SCCM0
N3SCCM1, N3SCCM0
R0SCCM1, R0SCCM0

de

Designates the special color calculation function mode of each scroll screen.

Mode
0
1
2
3

Process
Select color calculation enable per screen
Select color calculation enable per character
Select color calculation enable per dot
Select color calculation enable with color data MSB

Co

Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.

SE

GA

Special color calculation mode designation is effective only when each screen is a top
image. Otherwise, the mode must be set at 0. When the color format of scroll screen
is the RGB format, do not fixed at mode 2. Color is calculated by all dots whenmode 3 has been designated. Finally, do not designate modes 1 and 2 in EXBG.

ST-58-R2

247

nti
al

SE

GA

Co

nfi

de

(This page was blank in the original Japanese document)

248

nti
al

SE

GA

Co

nfi

de

Chapter 13 Color Offset Function

ST-58-R2

Introduction ....................................................................250
13.1 Color Offset Selection .......................................... 250
Color Offset Enable Register ............................ 251
Color Offset Select Register ............................. 252
Color Offset Register ........................................ 253

249

Introductionntial

The color offset function causes a change in the screen color without changing color
RAM data by adding the offset value when sprite and data of each screen are output.
Can also be used for fade-in and fade-out.

13.1 Color Offset SelectiondeThe color offset value can set two values, color offset A and color offset B in each
RGB, and can designate which of the two values to use for each screen. The color
offset value is 9-bit data corresponding to individual RGB. When resulting color
data added to individual RGB is smaller than 00H, the data is treated as 00H; whenlarger than FFH, the data is treated as FFH.

Bit 7

6

5

4

3

2

1

0

Co

8 Bit Color Datanfi

Because the color offset function process follows the color calculation function process, the color offset value is added to the color data resulting from color calculations. In addition, because the result screen of color calculation is treated as the top
image screen, designation of the color offset enable register is done with the screen
bit of that top image. Figure 13.1 shows the color offset data.

+

Bit 8

7

Sign

6

5

4

3

2

1

Color Offset A

8 Bit Color Offset Data

Bit 7

6

5

4

3

2

1

GA

8 Bit Output Color DataSE

Figure 13.1

250

0Color Offset Data0

Color Offset B
Select per screenColor Offset Enable Register

CLOFEN
180110H

15
~
7
~

14
~
6
SPCOEN

13~
5
BKCOEN

12~
4
R0COENnti
al

The color offset enable register is a write-only 16-bit register that designates whether
to use the color offset function for each screen, and is located at address 180110H.
Because the value is cleared to 0 after power on or reset, it must be set.
11~
3
N3COEN

10~
2
N2COEN

9~
1
N1COEN

8~0
N0COEN

Color offset enable bit (N0COEN, N1COEN, N2COEN, N3COEN, R0COEN,
BKCOEN, SPCOEN)
180110H
180110H
180110H
180110H
180110H
180110H
180110H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Back
For Sprite

nfi

N0COENN1COENN2COEN
N3COEN
R0COENBKCOENSPCOENdeDesignates whether to use the color offset function.

xxCOEN
0
1

Process
Do not use color offset function
Use color offset function

Co

Note: N0, N1, N2, N3, R0, BK, or SP is entered in bit name for xx.

SE

GA

Using the color calculation function designates the color offset enable bit of the top
image screen.

ST-58-R2

251

Color Offset Select Register

CLOFSL
180112H

15
~
7
~

14
~
6
SPCOSL

13~
5
BKCOSL

12~
4
R0COSL

11~
3
N3COSLntial

The color offset select register designates the color offset register used for eachscreen. This is a write-only 16-bit register located at address 180112H. Because thevalue is cleared to 0 after power on or reset, it must be set.
10~
2
N2COSL

9~
1
N1COSL

8~0
N0COSL

Color offset select bit (N0COSL, N1COSL, N2COSL, N3COSL, R0COSL,BKCOSL, SPCOSL)
180112H
180112H
180112H
180112H
180112H
180112H
180112H

xxCOSL
0
1

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Back
For Sprite

nfi

N0COSLN1COSLN2COSL
N3COSLR0COSLBKCOSLSPCOSLdeDesignates the color offset register to use when using the color offset function.

Process
Use color offset A value
Use color offset B value

Co

Note: N0, N1, N2, N3, R0, BK, or SP is entered in bit name for xx.

SE

GA

When using the color calculation function, designates with the color offset select bitof the top image screen.

252

Color Offset RegisterntialThe color offset register is a write-only 16-bit register that designates RGB individual
values of the color offset value, and is located at addresses 180114H to 18011EH.
Because the value is cleared to 0 after power on or reset, it must be set.
15~
7
COARD7

14~
6
COARD6

13~
5
COARD5

12~
4
COARD4

11~
3
COARD3

10~
2
COARD2

9~
1
COARD1

8
COARD80
COARD0COAG
180116H

15~
7COAGR714~
6COAGR613~
5COAGR512~
4COAGR411~
3COAGR310~
2COAGR29~1COAGR18COAGR80
COAGR0COAB
180118H

15~
7COABL714~
6COABL613~
5COABL512~
4COABL411~
3
COABL310~
2COABL29~
1
COABL18COABL80
COABL0COBR
18011AH

15~
7
COBRD714~
6COBRD613~
5COBRD512~
4COBRD4

11~
3COBRD310~
2COBRD2

9~
1
COBRD18COBRD80
COBRD0COBG
18011CH

15~7COBGR714~
6COBGR613~
5COBGR512~
4COBGR4

11~
3COBGR310~
2COBGR2

9~
1COBGR18
COBGR80
COBGR0COBB
18011EH

15~
7
COBBL714~
6
COBBL613~
5COBBL512~
4COBBL4

11~
3
COBBL310~
2COBBL2

9~
1COBBL1

8COBBL80
COBBL0

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COAR
180114H

Color offset value bit: Color offset data bit (COARD8 to COARD0, COAGR8 to
COAGR0, COABL8 to COABL0, COBRD8 to COBRD0, COBGR8 to COBGR0, COBBL8 to
COBBL0)SE

Sets the RGB individual value of color offset A and B. Negative numbers should be
set by two’s- complement values.

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Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0

For color offset A RED data
For color offset A GREEN data
For color offset A BLUE data
For color offset B RED data
For color offset B GREEN data
For color offset B BLUE datantial180114H
180116H
180118H
18011AH
18011CH
18011EH

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COARD8~COARD0COAGR8~COAGR0COABL8~COABL0COBRD8~COBRD0COBGR8~COBGR0
COBBL8~COBBL0

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Chapter 14 Shadow Function

ST-58-R2

Introduction ....................................................................256
14.1 Shadow Process .................................................. 256
Normal Shadow ................................................ 256
MSB Shadow .................................................... 258
Shadow Control Register .................................. 259

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Introduction
This function projects a shadow on a sprite or scroll screen by using a sprite. There
are two types of sprite shadows: the Normal shadow and the MSB shadow. The
MSB shadow is used when the sprite is type 2 through 7, and is used when the sprite
shadow priority is highest. The shadow function is processed after the color calculation and color offset functions. The shadow function is shown in Figure 14.1.
Scroll Screen

+

=

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Shadow Sprite
Normal Sprite

Output ImagedeFrame Buffer Data
Transparent

Figure 14.1 Shadow Function

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14.1 Shadow Process

When the sprite priority of the Normal shadow or MSB shadow is highest, theshadow process makes the sprite transparent and divides in half the brightness ofthe part of the sprite in the top image.
Normal Shadow

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With Normal shadow sprite, the number of bits to be determined by the sprite typechanges with dot color data of the least significant bit in the designated sprite type at
0, and all other dot color data at 1.

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Sprite data of a Normal shadow designates the color control word such that all bitsof dot color data remaining from the dot color code are 1, with only the least significant bit at 0. Also, sprite data of a Normal shadow is created by writing sprite characters of the dot color code whose remaining bits are 1 to the frame buffer. In Figure
14.1, a shadow cannot be projected because it has already been directed to the frame
buffer. As a result, write to the frame buffer first. For more about color control
word, see “VDP1 User’s Manual.”
The scroll screen and back screen, which project a shadow by the Normal shadow
sprite, can designate in all screens.

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A Normal shadow is shown in Figure 14.2 and sprite data of a Normal shadow isshown in Figure 14.3.
Normal Shadow Sprite

Normal Shadow

Transparent

Transparent

Figure 14.2

Frame Buffer After Write

Sprite data write of a Normal shadow• When Sprite Type 0~3, 5
14

13

12

• When Sprite Type 4, 6
14

13

12

10

4

3

2

1

0

1

1

9

1

1

1

1

1

1

1

1

0

11

10

9

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

1

1

0

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

1

0

8

7

6

5

4

3

2

1

0

1

1

1

1

1

1

1

0

7

6

5

4

3

2

1

0

1

1

1

1

1

1

0

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Bit 15

11

8

7

6

5

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Bit 15

deFrame Buffer Before Write• When Sprite Type 7
Bit 15

14

13

12

11

10

9

• When Sprite Type C~F
14

13

12

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Bit 15

12

Bit 15

12

11

10

9

• When Sprite Type 8
Bit 15

14

13

11

10

9

8

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• When Sprite Type 9~B

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13

11

10

9

8

7

6

5

4

3

2

1

0

1

1

1

1

1

0

Note: The bits in the shaded areas are used in judging the normal shadow.

Figure 14.3 Sprite data of a Normal shadow

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MSB Shadowntial

MSB shadow is enabled only when sprite types are type 2 through 7, with sprite
data MSB at 1. Depending on the value of 15 bits other than MSB, there are two
types of shadow: sprite shadow and the transparent shadow. The sprite shadow
MSB is 1 and all the values of 15 bits, other than the MSB, not 0. The transparent
shadow MSB is 1, with all the values of 15 bits, other than the MSB, at 0. When dot
color data satisfies Normal shadow conditions, it is judged to be a Normal shadoweven if sprite shadow conditions are satisfied.

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MSB shadow sprite data is created by changing only MSB to 1 in the form of an MSB
shadow sprite for frame buffer data that the VDP1 has already written to. (See“MSB On” in the “VDP1 User’s Manual.”) A shadow is added to the sprite character when all frame buffer data bits before the MSB changes are not 0; i.e., when anormal sprite that has already been written becomes a sprite shadow.

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A shadow is added for a scroll screen priority that is one less than the sprite of thetransparent shadow when all frame buffer data bits before the MSB is changed are 0;i.e., a transparent shadow will result when transparent. Scroll screen and backscreen that add shadows by sprites of the transparent shadow sprites can be selectedon each screen.

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The MSB shadow can not be used when using the sprite window. For more details
about the sprite window, see “8.1 Window Area.” The sprite shadow and transparent shadow are shown in Figure 14.4. Sprite data of the MSB shadow is shown in
Figure 14.5.

MSB Shadow Sprite

Sprite Shadow

Transparent

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Transparent

Frame Buffer before changing MSB

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Transparent Shadow

Frame Buffer after changing MSB

Sprite shadow and transparent shadow

Sprite Shadow

1

14

13

12

11

10

9

8

7

6

X

X

X

X

X

X

X

X

X

5

4

3

2

1

0

X

X

X

X

X

X

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Bit 15The Xed bits could be either 0 or 1 as long as the dot color data in the selected sprite
type does not meet the conditions of Normal Shadow.
Transparent Shadow
Bit 15
1

14

13

12

11

10

9

8

7

6

0

0

0

0

0

0

0

0

0

5

4

3

2

1

0

0

0

0

0

0

0

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Figure 14.5 Sprite data of MSB shadow

Shadow Control Register

14
~
6
~

13
~
5
BKSDEN

12~
4
R0SDENCo

SDCTL
1800E2H

15
~
7
~

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The shadow control register is a write-only 16-bit register that designates whether to
use the shadow function for the scroll screen and back screen, and is located ataddress 1800E2H. Because the value is cleared to 0 after power on or reset, the value
must be set.
11~
3
N3SDEN

10~
2
N2SDEN

9~
1
N1SDEN8TPSDSL0
N0SDEN

Shadow enable bit (N0SDEN, N1SDEN, N2SDEN, N3SDEN, R0SDEN,
BKSDEN)

This bit determines in sprites of the Normal shadow and transparent shadow
whether to use the shadow function for the scroll screen and back screen.
1800E2H
1800E2H
1800E2H
1800E2H
1800E2H
1800E2HGA

N0SDENN1SDENN2SDEN
N3SDEN
R0SDENBKSDEN

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For BackSE

The sprite of a sprite shadow always uses the shadow function for itself.

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Process
Does not use shadow function (shadow not added)
Uses shadow function (shadow added)

Note: N0, N1, N2, N3, R0, or BK is entered in bit name for xx.
Transparent shadow select bit (TPSDSL), bit 8

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xxSDEN
01

Determines whether to activate the sprite of the transparent shadow.
TPSDSL
0
1

Process
Disables transparent shadow sprite
Enables transparent shadow sprite

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When the sprite of a transparent shadow is nullified, a shadow will no longer be
projected on a screen by the transparent shadow sprite.

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Chapter 15 How to Use VDP2

ST-58-R2

15.1
15.2
15.3

Operation Flow ......................................................... 262
How to Use RAM ...................................................... 264
Bit Configuration Map ............................................. 267

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15.1 Operation Flow
Below is an overview of the steps for defining and setting VDP2 data.

Step 1 Set the TV screen mode.
• Select normal graphics, high-resolution graphic, or exclusive monitor• Set interlace mode
• Set vertical and horizontal resolutionGA(B) Bit map format• Bit map color count• Bit map size
• Scaling function• Rotation function• Mosaic process function

Co(A) Cell format• Character color count• Character size
• Pattern name data size
• Plane size
• Scaling function• Line scroll function• Vertical cell scroll function• Mosaic process function

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Step 3 Select the functions of each screen.
• Select cell format or bit map format

deStep 2 Select the scroll screen to be used.
• Normal scroll screen (NBG0, NBG1, NBG2, NBG3)• Rotation scroll screen (RBG0, RBG1)• External input screen (EXBG)• Line color screen (LNCL)• Back screen (BACK)Step 4 Select the color RAM mode.

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Step 5 Select the window to be used.
When using the Normal window, store the line window table in VRAM.

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Step 6 Calculate the size of VRAM to determine whether the tables can be stored
there.
• VRAM size
• Character pattern (number and size)• Pattern name table (number and size)• Bit map pattern (number and size)• Line scroll table• Vertical cell scroll table• Rotation parameter table• Coefficient table• Line color screen table• Back screen table• Line window table

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Step 7 Select VRAM use.
• VRAM bank partition• VRAM access method

Step 8 Create character pattern and pattern name table.
• Select the character number supplement mode.
• Set reverse function bit.
Creates a bit map pattern when in the bit map format.

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Step 9 Create other VRAM tables.

Step 10 Define priority and color calculation in terms of sprite data.

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Step 11 Set special functions.
• Special function code
• Special priority function• Extended color calculation function• Gradation calculation function• Color offset function• Shadow function (Normal, MSB)

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Step 12 Reset the screen, redefine and reset VRAM and registers in terms of story.

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15.2 How to Use RAM

nti
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• VRAM
Data defined in VRAM differs depending on the scroll screen to be used, screen
format, screen size, and the image process functions to be used. Data is defined in
VRAM according to the register setting; defined addresses are set in the various
address registers. Table 15.1 shows the main register connected with data defined in
VRAM.

264

Table 15.1 Register connected with data defined in VRAM
Definition

Register
Setting Data
Pattern Name Control Register Pattern Name Data Size,(180030H~180038H)
Character Number
Supplementary Mode, Pattern
Name Supplementary Data
Plane size register (18003AH) Plane size when in displaying
in cell format
Pattern name Character pattern lead Normal scroll screen map
Pattern Name Data lead
table
address
register (180040H~18004EH) address for each plane
Rotation scroll screen map
Pattern Name Data leadregister (180050H~18006EH) address for each plane
Map offset register3 bits map offset value(18003CH~18003EH)
attached to map register upper
bits
CharacterDot data of cell
Character control register
Character color count,pattern(180028H, 18002AH)
character size
Bitmap pattern Bitmap pattern data Character control register
Character color count (bitmap(180028H, 18002AH)
color count), bitmap size,
bitmap enable
Map offset register
Boundary address of bitmap(18003CH~18003EH)
patternLine scroll
Horizontal and vertical Line scroll table addressLine scroll table lead address
table
screen scroll value,
register (1800A0H~1800A6H)
horizontal coordinate Line & vertical cell scroll
Scroll configuration control
increment
control register (18009AH)
data
Vertical cell
Vertical screen scroll Vertical cell scroll table
Vertical cell scroll table lead
scroll tablevalue
address register (18009CH,
address
18009EH)
Line & vertical cell scroll
Scroll configuration control
control register (18009AH)
data
RAM control register
VRAM use per rotation scroll
Rotation Parameter, (18000EH)
screenRotation
Coefficient Table
Rotation parameter table
Parameter table lead address
parameter
Related Registers
address register (1800BCH,
table
1800BEH)
Rotation parameter mode
Rotation parameter mode
register (1800B0H)
setting
Coefficient table data RAM control register
VRAM use per rotation scroll(Zoom Coefficients kx, (18000EH)
screenCoefficientky, and start point
Coefficient table control
Coefficient data mode, data
table
coordinate Xp after
register (1800B4H)
size of coefficient data,rotation conversion)coefficient table enable
Coefficient table address
Coefficient table lead addressoffset register (1800B6H)
offset value
Line color
Color RAM addressLine color screen table
Line color screen color mode,
screen tableaddress register (1800A8H,
line color screen table lead
1800AAH)
address
Back screen
RGB color data
Back screen table address
Back screen color mode, backtable
register (1800ACH,
screen table lead address
1800AEH)
Line window
Horizontal start point Line window table addressLine window enable, line
table
coordinate, horizontal register
window table lead address
end point coordinate (1800D8H~1800DEH)

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Data

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• Color RAM Definition
Defines the sprite of the palette format and scroll screen color data. Color datastored in color RAM is in RGB format and has three modes. Mode selection designates in the color RAM mode (CRMD1, CRMD0, bits 13 and 12) of the RAM control
register (18000EH).

The most significant bit of color data stored in color RAM is the enable bit when thespecial color calculation mode is mode 3. Color is calculated in dot units for dots
using color data when the most significant bit color data is 1, the special color calculation mode is mode 3, the color format is the palette format, and the color calculation enable bit is 1.

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• Color RAM Reference
Color RAM is referred from character patterns, bit map patterns, and line color
screen table data. The color RAM address is expressed by 11 bits. When the character color count or bit map color count is 16-color, the 7-bit palette number added tothe host becomes 11 bits; when 256-color, the 3-bit palette number added to the host
becomes 11 bits. The palette number of the character pattern is in pattern name dataand supplement data of the pattern name control register; the palette number of the
bit map pattern is in the bit map palette number register.

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• Register
The register is, as a rule, a write-only, 16-bit register that designates the VDP2 function. One function may extend in several registers, and several functions may bearrange in one register. Set registers corresponding to the functions to be used whenneeded.

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15.3 Bit Configuration Map

TV Screen ModedeTV Screen Display (DISP, 180000H, bit 15 )0 : Does not display picture on TV screen
1 : Displays picturentialEvery register bit register is related to various other bits. The bit map configurationof separate scroll screens and separate priority functions is shown in the bit map
configuration below.

Boarder Color Mode (BDCLMD, 180000H, bit 8)
0 : Displays Black
1 : Displays Back Screen

nfiInterlace mode (LSMD, 180000H, bit 7~6 )00 : Non-interlace
10 : Single-density Interlace
11 : Double-density Interlace

Vertical Resolution (VRESO, 180000H, bit 5~4)00 : 224 Lines (NTSC format or PAL format TV)
01 : 240 Lines (NTSC format or PAL format TV)
10 : 256 Lines (PAL format TV)

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Horizontal Resolution (HRESO, 180000H, bit 2~0 )000 : 320 Pixels (Normal Graphics A, NTSC format or PAL format TV)
001 : 352 Pixels (Normal Graphics B, NTSC format or PAL format TV)
010 : 640 Pixels (Hi-Res Graphics A, NTSC format or PAL format TV)
011 : 704 Pixels (Hi-Res Graphics B, NTSC format or PAL format TV)
100 : 320 Pixels (Exclusive Normal Graphics A, 31kHz monitor)
101 : 352 Pixels (Exclusive Normal Graphics B, Hi-Vision monitor)
110 : 640 Pixels (Exclusive Hi-Res Graphics A, 31kHz monitor)
111 : 704 Pixels (Exclusive Hi-Res Graphics B, Hi-Vision monitor)

GA

External Signal Enable
External Latch Enable (EXLTEN, 180002H, bit 9)
0 : Latch when External Enable Register is read
1 : Latches via external signal

External Synchronization Enable (EXSYEN, 180002H, bit 8)
0 : Does not input External Sync. Signal
1 : Inputs External Sync. Signal and synchronizes TV screen display externallySE

Image Display Area Select (DASEL, 180002H, bit 1)
0 : Displays image in set display area only
1 : Displays image in specified display area only

External Screen Enable (EXBGEN, 180002H, bit 0)
0 : Does not input External Screen Data
1 : Inputs External Screen Data

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Screen Status

External Latch Flag (EXLTFG, 180004H, bit 9)
0 : Register is not latched (Register will be cleared when status is read)
1 : HV Counter Value is latched in register
External Synchronization Flag (EXSYFG, 180004H, bit 8)
0 : Does not synchronize (Register will be cleared when status is read)
1 : Internal Circuitry Synchronized

Scan Field Flag (ODD, 180004H, bit 1 )0 : Scans during even fields
1 : Scans during odd fields
TV Format Flag (PAL, 180004H, bit 0 )0 : NTSC Format
1 : PAL Format
H-Counter Value (HCT, 180008H, bit 9~0)

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V-Counter Value (VCT, 18000AH, bit 9~0)

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H-Blank ( HBLANK, 180004H, bit 2)
0 : Scans during horizontal display
1 : Scans during horizontal retrace (HBLANK)deV-Blank (VBLANK, 180004H, bit 3)
0 : Scans during vertical display
1 : Scans during vertical retrace (VBLANK)

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RAM
VRAM
VRAM Size (VRAMSZ, 180006H, bit 15)
0 : 4 Mbit
1 : 8 Mbit

VRAM Select (VRAMSL, 18000CH, bit 0)
0 : Uses VRAM-A for CPU VRAM
1 : Uses VRAM-B for CPU VRAMdeVRAM Change Enable (VRAMCE, 18000CH, bit 8 )0 : Does not use change function (uses both VRAM-A and VRAM-B as display VRAM)
1 : Uses change function (uses either VRAM-A or VRAM-B as display VRAM)

VRAM Mode (VRAMD, 18000EH, bit 8)
VRAM Mode (VRBMD, 18000EH, bit 9)
0 : Does not make 2 bank partitions
1 : Makes 2 bank partitions

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VRAM Cycle Pattern (For VRAM-A0 (or VRAM-A )) (VCPnA0, 180010H, 180012H )VRAM Cycle Pattern (For VRAM-A1 )(VCPnA1, 180014H, 180016H )VRAM Cycle Pattern (For VRAM-B0 (or VRAM-B )) (VCPnB0, 180018H, 18001AH )VRAM Cycle Pattern (For VRAM-B1 )(VCPnB1, 18001CH, 18001EH )For Timing T0 (VCP0xx, 18001yH, bit 15~12 )For Timing T1 (VCP1xx, 18001yH, bit 11~8 )For Timing T2 (VCP2xx, 18001yH, bit 7~4 )For Timing T3 (VCP3xx, 18001yH, bit 3~0 )For Timing T4 (VCP4xx, 18001zH, bit 15~12 )For Timing T5 (VCP5xx, 18001zH, bit 11~8 )For Timing T6 (VCP6xx, 18001zH, bit 7~4 )For Timing T7 (VCP7xx, 18001zH, bit 3~0 )0000 : NBG0 Pattern Name Data Read
0001 : NBG1 Pattern Name Data Read
0010 : NBG2 Pattern Name Data Read
0011 : NBG3 Pattern Name Data Read
0100 : NBG0 Character Pattern Data Read
0101 : NBG1 Character Pattern Data Read
0110 : NBG2 Character Pattern Data Read
0111 : NBG3 Character Pattern Data Read
1100 : Vertical Cell Scroll Table Data Read for NBG01101 : Vertical Cell Scroll Table Data Read for NBG11110 : CPU Read/Write
1111 : No AccessSE

Color RAM
Color RAM Mode (CRMD, 18000EH, bit 13~12)00 : Mode 0 : RGB, each 5 bits; 1024 color settings
01 : Mode 1 : RGB, each 5 bits; 2048 color settings
10 : Mode 2 : RGB, each 5 bits; 1024 color settings

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Scroll Screen
Normal Scroll Screen
NBG0
NBG1
NBG2
NBG3
Rotation Scroll Screen
RBG0
RBG1
External Input Screen : EXBG

deLine ScreenLine Color Screen : LNCL
Back Screen : BACK

Normal Scroll Screen (NBG0)

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Transparent Display Enable (N0TPON, 180020H, bit 8)
0 : Enables Transparent Code
(Transparent coded dots become transparent)
1 : Disables Transparent Code
(Transparent coded dots are displayed according to their data value)

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Screen Display Enable (N0ON, 180020H, bit 0)
0 : Cannot Display (Does not access VRAM)
1 : Can Display

Character Color Count (N0CHCN, 180028H, bit 6~4)000 :16 colors (Palette Format)
001 :256 colors (Palette Format)
010 :2048 colors (Palette Format)
011 :32,768 colors (RGB Format)
100 : 16,770,000 colors (RGB Format)

0: Display in Cell Format

See Cell Format (NBG0)

1

GA

Bitmap Enable (N0BMEN, 180028H, bit 1): Display in Bitmap Format

See Bitmap Format (NBG0 )Mosaic Enable (N0MZE, 180022H, bit 0)
0 : Does not execute Mosaic Process
1 : Executes Mosaic Process
Mosaic Size (MZSZx, 180022H )Horizontal Mosaic Size (MZSZH, 180022H, bit 11~8 )Vertical Mosaic Size(MZSZV, 180022H, bit 15~12)

SE(Continued)

270

Character Size (N0CHSZ, 180028H, bit 0 )0 : 1 H Cell X 1 V Cell
1 : 2 H Cells X 2 V Cells
Pattern Name Data Size (N0PNB, 180030H, bit 15)
0 : 2 Words
1 : 1 Word
1 Word (Pattern Name Data Size)ntialCell Format (NBG0 )deCharacter Number Supplementary Mode (N0CNSM, 180030H, bit 14 )0 : Character number in pattern name data is 10 bits; reverse function
can be selected in character units
1 : Character number in pattern name data is 12 bits; reverse function
cannot be selected.
Special Priority (N0SPR, 180030H, bit 9)(For Pattern Name Supplementary Data)nfi

Special Color Calculation (N0SCC, 180030H, bit 8)(For Pattern Name Supplementary Data)

Supplementary Palette Number (N0SPLT, 180030H, bit 7~5 )Supplementary Character Number (N0SCN, 180030H, bit 4~0)

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Plane Size (N0PLSZ, 18003AH, bit 1~0)00 : 1 H Page X 1 V Page
01 : 2 H Pages X 1 V Page
10 : 2 H Pages X 2 V Pages
Map Offset (N0MP, 18003CH, bit 2~0)GA

Map (N0MPx, 180040H~180042H )For Plane A (N0MPA, 180040H, bit 5~0 )For Plane B (N0MPB, 180040H, bit 13~8 )For Plane C ( N0MPC, 180042H, bit 5~0)
For Plane D ( N0MPD, 180042H, bit 13~8)

Bitmap Format (NBG0)

Bitmap Size (N0BMSZ, 180028H, bit 3~2)00 : 512 H Dots X 256 V Dots
01 : 512 H Dots X 512 V Dots
10 : 1024 H Dots X 256 V Dots
11 : 1024 H Dots X 512 V DotsSE

Special Priority (N0BMPR, 18002CH, bit 5)Special Color Calculation (N0BMCC, 18002CH, bit 4)

Supplementary Palette Number (N0BMP, 18002CH, bit 2~0)
Map Offset (N0MP, 18003CH, bit 2~0)

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Screen Scroll Value (N0SCx, 180070H~180076H)
For Horizontal Direction (N0SCX, 180070H, bit 10~180072H, bit 8)
For Vertical Direction(N0SCY, 180074H, bit 10~180076H, bit 8)
Coordinate Increment (N0ZMx, 180078H~18007EH)
For Horizontal Direction (N0ZMX, 180078H, bit 2~18007AH, bit 8 )For Vertical Direction(N0ZMY, 18007CH, bit 2~18007EH, bit 8)
Reduction Enable (N0ZMQT, N0ZMHF, 180098H, bit 1~0)00 : Reduction can not be displayed horizontally
01 : Reduction can be displayed up to 1/2 horizontally
10 : Reduction can be displayed up to 1/4 horizontally
11 : Reduction can be displayed up to 1/4 horizontally

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Line Scroll Space (N0LSS, 18009AH, bit 5~4)00 : Every 1 Line (Non-interlace, Double-density Interlace),
Every 2 Lines (Single-density Interlace)
01 : Every 2 Lines (Non-interlace, Double-density Interlace),
Every 4 Lines (Single-density Interlace)
10 : Every 4 Line (Non-interlace, Double-density Interlace),
Every 8 Lines (Single-density Interlace)
11 : Every 8 Line (Non-interlace, Double-density Interlace),
Every 16 Lines (Single-density Interlace)ntialNormal Scroll Screen (NBG0) (continued)

Line Zoom Enable (N0LZMX, 18009AH, bit 3)
0 : Does not scale horizontally in line units
1 : Scales horizontally in line units

CoLine Scroll Enable (N0LSCY, 18009AH, bit 2 )(For Vertical Screen Scroll Values)
0 : Does not scroll vertically in line units
1 : Scrolls vertically in line units

Line Scroll Enable (N0LSCX, 18009AH, bit 1 )(For Horizontal Screen Scroll Values)
0 : Does not scroll horizontally in line units
1 : Scrolls horizontally in line units

Vertical Cell Scroll Enable (N0VCSC, 18009AH, bit 0)
0 : No vertical cell scroll
1 : Allows vertical cell scroll

GA

Line Scroll Table Address (N0LSTA, 1800A0H, bit 2~1800A2H, bit 1)

SE

Vertical Cell Scroll Table Address (VCSTA, 18009CH, bit 2~18009EH, bit 1 )272

Normal Scroll Screen (NBG1)

ntial

Transparent Display Enable (N1TPON, 180020H, bit 9)
0 : Turns on Transparent Code
(Transparent coded dots become transparent)
1 : Turns off Transparent Code
(Transparent coded dots are displayed as per their data value)
Screen Display Enable (N1ON, 180020H, bit 1)
0 : Cannot Display (Cannot access VRAM during display)
1 : Can Display

Bitmap Enable (N1BMEN, 180028H, bit 9)deCharacter Color Count (N1CHCN, 180028H, bit 13~12)00 :16 colors (Palette Format)
01 :256 colors (Palette Format)
10 :2048 colors (Palette Format)
11 :32,768 colors (RGB Format)

0: Display in Cell Format

See Cell Format (NBG1)

1: Display in Bitmap Format

See Bitmap Format (NBG1 )nfi

Mosaic Enable (N1MZE, 180022H, bit 1)
0 : Does not execute Mosaic Process
1 : Executes Mosaic Process
Mosaic Size (MZSZx, 180022H )Horizontal Mosaic Size (MZSZH, 180022H, bit 11~8 )Vertical Mosaic Size(MZSZV, 180022H, bit 15~12)

SE

GA

Co

(Continued)

ST-58-R2

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Cell Format (NBG1 )Character Size (N1CHSZ, 180028H, bit 8 )0 : 1 H Cell X 1 V Cell
1 : 2 H Cells X 2 V Cells
Pattern Name Data Size (N1PNB, 180032H, bit 15)
0 : 2 Words
1 : 1 Word
1 Word (Pattern Name Data Size)

Special Priority (N1SPR, 180032H, bit 9)(For Pattern Name Supplementary Data)deCharacter Number Supplementary Mode (N1CNSM, 180032H, bit 14)
0 : Character number in pattern name data is 10 bits; reverse function can beselected in character units
1 : Character number in pattern name data is 12 bits; reverse function cannot be
selected.

nfi

Special Color Calculation (N1SCC, 180032H, bit 8)(For Pattern Name Supplementary Data)

Supplementary Palette Number (N1SPLT, 180032H, bit 7~5 )Supplementary Character Number (N1SCN, 180032H, bit 4~0)

Co

Plane Size (N1PLSZ, 18003AH, bit 3~2)00 : 1 H Page X 1 V Page
01 : 2 H Pages X 1 V Page
10 : 2 H Pages X 2 V Pages
Map Offset (N1MP, 18003CH, bit 6~4)

GA

Map (N1MPx, 180044H~180046H )For Plane A (N1MPA, 180044H, bit 5~0 )For Plane B (N1MPB, 180044H, bit 13~8 )For Plane C ( N1MPC, 180046H, bit 5~0)
For Plane D ( N1MPD, 180046H, bit 13~8)

Bitmap Format (NBG1)

Bitmap Size (N1BMSZ, 180028H, bit 11~10)00 : 512 H Dots X 256 V Dots
01 : 512 H Dots X 512 V Dots
10 : 1024 H Dots X 256 V Dots
11 : 1024 H Dots X 512 V DotsSE

Special Priority (N1BMPR, 18002CH, bit 13)
Special Color Calculation (N1BMCC, 18002CH, bit 12)

Supplementary Palette Number (N1BMP, 18002CH, bit 10~8)
Map Offset (N1MP, 18003CH, bit 6~4)

274

nti
al

Normal Scroll Screen (NBG1) (Continued)
Screen Scroll Value (N1SCx, 180080H~180086H)
For Horizontal Direction (N1SCX, 180080H, bit 10~180082H, bit 8)
For Vertical Direction(N1SCY, 180084H, bit 10~180086H, bit 8)
Coordinate Increment (N1ZMx, 180088H~18008EH)
For Horizontal Direction (N1ZMX, 180088H, bit 2~18008AH, bit 8 )For Vertical Direction(N1ZMY, 18008CH, bit 2~18008EH, bit 8)

deReduction Enable (N1ZMQT, N1ZMHF, 180098H, bit 9~8)00 : Reduction can not be displayed horizontally
01 : Reduction can be displayed up to 1/2 horizontally
10 : Reduction can be displayed up to 1/4 horizontally
11 : Reduction can be displayed up to 1/4 horizontallynfiLine Scroll Space (N1LSS, 18009AH, bit 13~12)00 : Every 1 Line (Non-interlace, Double-density Interlace),
Every 2 Lines (Single-density Interlace)
01 : Every 2 Lines (Non-interlace, Double-density Interlace),
Every 4 Lines (Single-density Interlace)
10 : Every 4 Line (Non-interlace, Double-density Interlace),
Every 8 Lines (Single-density Interlace)
11 : Every 8 Line (Non-interlace, Double-density Interlace),
Every 16 Lines (Single-density Interlace)Line Zoom Enable (N1LZMX, 18009AH, bit 11)
0 : No zoom horizontally in line units
1 : Allows zoom horizontally in line units

CoLine Scroll Enable (N1LSCY, 18009AH, bit 10 )(For Vertical Screen Scroll Values)
0 : No zoom vertically in line units
1 : Allows zoom vertically in line units

Line Scroll Enable (N1LSCX, 18009AH, bit 9 )(For Horizontal Screen Scroll Values)
0 : No scroll horizontally in line units
1 : Allows scroll horizontally in line units

GA

Vertical Cell Scroll Enable (N1VCSC, 18009AH, bit 8)
0 : No vertical cell scroll
1 : Allows vertical cell scroll
Line Scroll Table Address (N1LSTA, 1800A4H, bit 2~1800A6H, bit 1)

SE

Vertical Cell Scroll Table Address (VCSTA, 18009CH, bit 2~18009EH, bit 1 )ST-58-R2

275

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al

Normal Scroll Screen (NBG2)
Transparent Display Enable (N2TPON, 180020H, bit 10)
0 : Turns on Transparent Code
(Transparent coded dots become transparent)
1 : Turns off Transparent Code
(Transparent coded dots are displayed as per their data value)
Screen Display Enable (N2ON, 180020H, bit 2)
0 : Cannot Display (Cannot access VRAM during display)
1 : Can DisplaydeCharacter Color Count (N2CHCN, 18002AH, bit 1)
0 :16 colors (Palette Format)
1 :256 colors (Palette Format)

See Cell Format (NBG2)

nfi(Display in Cell Format)

Mosaic Enable (N2MZE, 180022H, bit 2)
0 : Does not execute Mosaic Process
1 : Executes Mosaic Process
Mosaic Size (MZSZx, 180022H )Horizontal Mosaic Size (MZSZH, 180022H, bit 11~8 )Vertical Mosaic Size(MZSZV, 180022H, bit 15~12)

SE

GA

Co

Screen Scroll Value (N2SCx, 180090H~180092H)
For Horizontal Direction (N2SCX, 180090H, bit 10~0 )For Vertical Direction (N2SCY, 180092H, bit 10~0)276

Character Size (N2CHSZ, 18002AH, bit 0 )0 : 1 H Cell X 1 V Cell
1 : 2 H Cells X 2 V Cells
Pattern Name Data Size (N2PNB, 180034H, bit 15)
0 : 2 Words
1 : 1 Word
1 Word (Pattern Name Data Size)ntialCell Format (NBG2 )deCharacter Number Supplementary Mode (N2CNSM, 180034H, bit 14)
0 : Character number in pattern name data is 10 bits; reverse function canbe selected in character units
1 : Character number in pattern name data is 12 bits; reverse function
cannot be selected
Special Priority (N2SPR, 180034H, bit 9)(For Pattern Name Supplementary Data)nfi

Special Color Calculation (N2SCC, 180034H, bit 8)(For Pattern Name Supplementary Data)

Supplementary Palette Number (N2SPLT, 180034H, bit 7~5 )Supplementary Character Number (N2SCN, 180034H, bit 4~0)

Co

Plane Size (N2PLSZ, 18003AH, bit 5~4)00 : 1 H Page X 1 V Page
01 : 2 H Pages X 1 V Page
10 : 2 H Pages X 2 V Pages
Map Offset (N2MP, 18003CH, bit 10~8)SEGA

Map (N2MPx, 180048H~18004AH )For Plane A (N2MPA, 180048H, bit 5~0 )For Plane B (N2MPB, 180048H, bit 13~8 )For Plane C ( N2MPC, 18004AH, bit 5~0)
For Plane D ( N2MPD, 18004AH, bit 13~8)

ST-58-R2

277

Normal Scroll Screen (NBG3)

Screen Display Enable (N3ON, 180020H, bit 3)
0 : Cannot Display (Cannot access VRAM during display)
1 : Can DisplaydeCharacter Color Count (N3CHCN, 18002AH, bit 5)
0 :16 colors (Palette Format)
1 :256 colors (Palette Format)ntialTransparent Display Enable (N3TPON, 180020H, bit 11)
0 : Turns on Transparent Code
(Transparent coded dots become transparent)
1 : Turns off Transparent Code
(Transparent coded dots are displayed as per their data value)(Display in Cell Format)

See Cell Format (NBG3)

nfi

Mosaic Enable (N3MZE, 180022H, bit 3)
0 : Does not execute Mosaic Process
1 : Executes Mosaic Process
Mosaic Size (MZSZx, 180022H )Horizontal Mosaic Size (MZSZH, 180022H, bit 11~8 )Vertical Mosaic Size(MZSZV, 180022H, bit 15~12)

SE

GA

Co

Screen Scroll Value (N3SCx, 180094H~180096H)
For Horizontal Direction (N3SCX, 180094H, bit 10~0 )For Vertical Direction (N3SCY, 180096H, bit 10~0)278

Character Size (N3CHSZ, 18002AH, bit 4 )0 : 1 H Cell X 1 V Cell
1 : 2 H Cells X 2 V Cells
Pattern Name Data Size (N3PNB, 180036H, bit 15)
0 : 2 Words
1 : 1 Word
1 Word (Pattern Name Data Size)ntialCell Format (NBG3 )deCharacter Number Supplementary Mode (N3CNSM, 180036H, bit 14)
0 : Character number in pattern name data is 10 bits; reverse function canbe selected in character units
1 : Character number in pattern name data is 12 bits; reverse function
cannot be selected
Special Priority (N3SPR, 180036H, bit 9)(For Pattern Name Supplementary Data)

Special Color Calculation (N3SCC, 180036H, bit 8)(For Pattern Name Supplementary Data)nfi

Supplementary Palette Number (N3SPLT, 180036H, bit 7~5 )Supplementary Character Number (N3SCN, 180036H, bit 4~0)

Co

Plane Size (N3PLSZ, 18003AH, bit 7~6)00 : 1 H Page X 1 V Page
01 : 2 H Pages X 1 V Page
10 : 2 H Pages X 2 V Pages

Map Offset (N3MP, 18003CH, bit 14~12)

SEGA

Map (N3MPx, 18004CH~18004EH)
For Plane A (N3MPA, 18004CH, bit 5~0)
For Plane B (N3MPB, 18004CH, bit 13~8)
For Plane C ( N3MPC, 18004EH, bit 5~0)
For Plane D ( N3MPD, 18004EH, bit 13~8)

ST-58-R2

279

Rotation Scroll Screen (RBG0 )Character Color Count (R0CHCN, 18002AH, bit 14~12)000 :16 colors (Palette Format)
001 :256 colors (Palette Format)
010 :2048 colors (Palette Format)
011 :32,768 colors (RGB Format)
100 : 16,770,000 colors (RGB Format)
Bitmap Enable (R0BMEN, 18002AH, bit 9)

deScreen Display Enable (R0ON, 180020H, bit 4)
0 : Cannot Display (Cannot access VRAM during display)
1 : Can Display

0: Display in Cell Format

See Cell Format (RBG0)

1: Display in Bitmap Format

See Bitmap Format (RBG0 )nfi

Mosaic Enable (R0MZE, 180022H, bit 4)
0 : Does not execute Mosaic Process
1 : Executes Mosaic Process
Mosaic Size (MZSZx, 180022H )Horizontal Mosaic Size (MZSZH, 180022H, bit 11~8 )Vertical Mosaic Size(MZSZV, 180022H, bit 15~12)

SE

GA

Co

(Continued)

280

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Transparent Display Enable (R0TPON, 180020H, bit 12)
0 : Turns on Transparent Code
(Transparent coded dots become transparent)
1 : Turns off Transparent Code
(Transparent coded dots are displayed as per their data value)Cell Format (RBG0 )ntialCharacter Size (R0CHSZ, 18002AH, bit 8 )0 : 1 H Cell X 1 V Cell
1 : 2 H Cells X 2 V Cells
Pattern Name Data Size (R0PNB, 180038H, bit 15)
0 : 2 Words
1 : 1 Word
1 Word (Pattern Name Data Size)deCharacter Number Supplementary Mode (R0CNSM, 180038H, bit 14)
0 : Character number in pattern name data is 10 bits; reverse function canbe selected in character units
1 : Character number in pattern name data is 12 bits; reverse function
cannot be selected
Special Priority (R0SPR, 180038H, bit 9)(For Pattern Name Supplementary Data)

Special Color Calculation (R0SCC, 180038H, bit 8)(For Pattern Name Supplementary Data)nfi

Supplementary Palette Number (R0SPLT, 180038H, bit 7~5 )Supplementary Character Number (R0SCN, 180038H, bit 4~0)

Rotation Parameter Mode (RPMD, 1800B0H, bit 1~0)

See Rotation Parameter A (RBG0 )01 : Mode 1 : Use for Rotation Parameter B

See Rotation Parameter B (RBG0 )

SE

GA

Co

00 : Mode 0 : Use for Rotation Parameter A

ST-58-R2

281

For Rotation Parameter A (RBG0 )ntialPlane Size (RAPLSZ, 18003AH, bit 9~8)00 : 1 H Page X 1 V Page
01 : 2 H Pages X 1 V Page
10 : 2 H Pages X 2 V Pages

Map Offset (RAMP, 18003EH, bit 2~0)

SE

GA

Co

nfi

Map (RAMPx, 180050H~18005EH )For Plane A (RAMPA, 180050H, bit 5~0 )For Plane B (RAMPB, 180050H, bit 13~8 )For Plane C (RAMPC, 180052H, bit 5~0 )For Plane D (RAMPD, 180052H, bit 13~8 )For Plane E (RAMPE, 180054H, bit 5~0 )For Plane F (RAMPF, 180054H, bit 13~8 )For Plane G (RAMPG, 180056H, bit 5~0 )For Plane H (RAMPH, 180056H, bit 13~8 )For Plane I (RAMPI, 180058H, bit 5~0)
For Plane J (RAMPJ, 180058H, bit 13~8 )For Plane K (RAMPK, 18005AH, bit 5~0 )For Plane L (RAMPL, 18005AH, bit 13~8 )For Plane M (RAMPM, 18005CH, bit 5~0 )For Plane N (RAMPN, 18005CH, bit 13~8 )For Plane O (RAMPO, 18005EH, bit 5~0 )For Plane P (RAMPP, 18005EH, bit 13~8 )deScreen Over Process (RAOVR, 18003AH, bit 11~10 )00 : Outside the display area it repeats the image set in the display area
01 : Outside the display area it repeats the image set in the
Screen Over Pattern Register
10 : Everything outside the display area is transparent
11 : Sets display area to 0 ≤ x < 512 and 0 ≤ y <512 regardless of the plane size or bitmap size.
Everything outside the display area is transparent.
Screen Over Pattern Name (RAOPN, 1800B8H, bit 15~0 )

282

nti
al

For Rotation Parameter B (RBG0 )Plane Size (RBPLSZ, 18003AH, bit 13~12)00 : 1 H Page X 1 V Page
01 : 2 H Pages X 1 V Page
10 : 2 H Pages X 2 V Pages

Map Offset (RBMP, 18003EH, bit 6~4)

deScreen Over Process (RBOVR, 18003AH, bit 15~14 )00 : Outside the display area it repeats the image set in the display area
01 : Outside the display area it repeats the image set in the
Screen Over Pattern Register
10 : Everything outside the display area is transparent
11 : Sets display area to 0 ≤ x < 512 and 0 ≤ y <512 regardless of the plane size or bitmap size.
Everything outside the display area is transparent.
Screen Over Pattern Name (RBOPN, 1800BAH, bit 15~0 )Bitmap Format (RBG0)

Co

nfi

Map (RBMPx, 180060H~18006EH )For Plane A (RBMPA, 180060H, bit 5~0 )For Plane B (RBMPB, 180060H, bit 13~8 )For Plane C (RBMPC, 180062H, bit 5~0 )For Plane D (RBMPD, 180062H, bit 13~8 )For Plane E (RBMPE, 180064H, bit 5~0 )For Plane F (RBMPF, 180064H, bit 13~8 )For Plane G (RBMPG, 180066H, bit 5~0 )For Plane H (RBMPH, 180066H, bit 13~8 )For Plane I (RBMPI, 180068H, bit 5~0)
For Plane J (RBMPJ, 180068H, bit 13~8 )For Plane K (RBMPK, 18006AH, bit 5~0 )For Plane L (RBMPL, 18006AH, bit 13~8 )For Plane M (RBMPM, 18006CH, bit 5~0 )For Plane N (RBMPN, 18006CH, bit 13~8 )For Plane O (RBMPO, 18006EH, bit 5~0 )For Plane P (RBMPP, 18006EH, bit 13~8 )GA

Bitmap Size (R0BMSZ, 18002AH, bit 10)
0 : 512 H Dots X 256 V Dots
1 : 512 H Dots X 512 V Dots

Special Priority (R0BMPR, 18002EH, bit 5)Special Color Calculation (R0BMCC, 18002EH, bit 4 )Supplementary Palette Number (R0BMP, 18002EH, bit 2~0 )SERotation Parameter Mode (RPMD, 1800B0H, bit 1~0)00 : Mode 0 : Use for Rotation Parameter A
01 : Mode 1 : Use for Rotation Parameter B
Map Offset (For Rotation Parameter A) (RAMP, 18003EH, bit 2~0 )Map Offset (For Rotation Parameter B) (RBMP, 18003EH, bit 6~4 )ST-58-R2

283

Rotation Data Bank Setting (RDBSxx, 18000EH )For VRAM-A0 (or VRAM-A )(RDBSA0, 18000EH, bit 1~0 )For VRAM-A1(RDBSA1, 18000EH, bit 3~2 )For VRAM-B0 (or VRAM-B )(RDBSB0, 18000EH, bit 5~4 )For VRAM-B1(RDBSB1, 18000EH, bit 7~6 )00 : Not used as RAM for RBG0
01 : RAM for RBG0 Coefficient Data Table
10 : RAM for RBG0 Pattern Name Table
11 : RAM for RBG0 Character Pattern Table(or Bitmap Pattern)deParameter Read Enable (RxxxSTRE, 1800B2H )For Rotation Parameter A Xst (RAXSTRE, 1800B2H, bit 0)
For Rotation Parameter B Xst (RBXSTRE, 1800B2H, bit 8)
For Rotation Parameter A Yst (RAYSTRE, 1800B2H, bit 1)
For Rotation Parameter B Yst (RBYSTRE, 1800B2H, bit 9)
For Rotation Parameter A KAst (RAKASTRE, 1800B2H, bit 2)
For Rotation Parameter B KAst (RBKASTRE, 1800B2H, bit 10)
0 : Selected parameter is not read per line
1 : Selected parameter is read per linentialRotation Scroll Screen (RBG0 ) (Continued)

nfi

Rotation Parameter Table Address (RPTA, 1800BCH, bit 2~1800BEH, bit 1)

Co

Rotation Parameter Mode (RPMD, 1800B0H, bit 1~0)00 : Mode 0 : Rotation Parameter A
01 : Mode 1 : Rotation Parameter B
10 : Mode 2 : A image and B image are switched according to coefficient data readfrom rotation parameter A coefficient table
11 : Mode 3 : A image and B image are switched according to rotation parameter window
Coefficient Line Color Enable (RxKLCE, 1800B4H)
For Rotation Parameter A (RAKLCE, 1800B4H, bit 4 )For Rotation Parameter B (RBKLCE, 1800B4H, bit 12 )0 : Line color screen data in coefficient data is not used
1 : Line color screen data in coefficient data is usedGA

Coefficient Data Mode (RxKMD, 1800B4H)
For Rotation Parameter A (RAKMD, 1800B4H, bit 3~2)
For Rotation Parameter B (RBKMD, 1800B4H, bit 11~10)00 : Mode 0 : Used as zoom coefficients kx and ky
01 : Mode 1 : Used as zoom coefficient kx
10 : Mode 2 : Used as zoom coefficient ky
11 : Mode 3 : Used as viewpoint coordinate Xp after conversion
Coefficient Data Size (RxKDBS, 1800B4H)
For Rotation Parameter A (RAKDBS, 1800B4H, bit 1 )For Rotation Parameter B (RBKDBS, 1800B4H, bit 9 )0 : 2 Words
1 : 1 WordSE

Coefficient Table Enable (RxKTE, 1800B4H)
For Rotation Parameter A (RAKTE, 1800B4H, bit 0 )For Rotation Parameter B (RBKTE, 1800B4H, bit 8 )0 : Does not use Coefficient Table
1 : Uses Coefficient Table
Coefficient Table Address Offset (RxKTAOS, 1800B6H)
For Rotation Parameter A (RAKTAOS, 1800B6H, bit 2~0 )For Rotation Parameter B (RBKTAOS, 1800B6H, bit 10~8 )

284

nti
al

Rotation Scroll Screen (RBG1 )Transparent Display Enable (For NBG0) (N0TPON, 180020H, bit 8)
0 : Turns on Transparent Code
(Transparent coded dots become transparent)
1 : Turns off Transparent Code
(Transparent coded dots are displayed as per their data value)
Screen Display Enable (R1ON, 180020H, bit 5)
0 : Cannot Display (Cannot access VRAM during display)
1 : Can Display(Display in Cell Format)

deCharacter Color Count (For NBG0) (N0CHCN, 180028H, bit 6~4)000 :16 colors(Palette Format)
001 :
256
colors(Palette Format)
010 :2048 colors(Palette Format)
011 :32786 colors(RGB Format)
100 : 16,770,000 colors(RBG Format)

See Cell Format (RBG1)

SE

GA

Co

nfi

Mosaic Enable (For NBG0) (N0MZE, 180022H, bit 0)
0 : Does not execute Mosaic Process
1 : Executes Mosaic Process
Mosaic Size (MZSZx, 180022H )Horizontal Mosaic Size (MZSZH, 180022H, bit 11~8 )Vertical Mosaic Size(MZSZV, 180022H, bit 15~12)

ST-58-R2

285

Character Size (For NBG0 ) (N0CHSZ, 180028H, bit 0 )0 : 1 H Cell X 1 V Cell
1 : 2 H Cells X 2 V Cells
Pattern Name Data Size (For NBG0) (N0PNB, 180030H, bit 15)
0 : 2 Words
1 : 1 Word
1 Word (Pattern Name Data Size)ntialCell Format (RBG1 )deCharacter Number Supplementary Mode (For NBG0) (N0CNSM, 180030H, bit 14)
0 : Character number in pattern name data is 10 bits, reverse function
can be selected per character unit
1 : Character number in pattern name data is 12 bits, reverse function
cannot be selected
Special Priority (For NBG0) (N0SPR, 180030H, bit 9)(For Pattern Name Supplementary Data)

Special Color Calculation (For NBG0 ) (N0SCC, 180030H, bit 8)(For Pattern Name Supplementary Data)nfi

Supplementary Palette Number (For NBG0 ) (N0SPLT, 180030H, bit 7~5 )Supplementary Character Number (For NBG0) (N0SCN, 180030H, bit 4~0)
(For use of Rotation Parameter B)
For Rotation Parameter B (RBG1 )Co

Plane Size (RBPLSZ, 18003AH, bit 13~12)00 : 1 H Page X 1 V Page
01 : 2 H Pages X 1 V Page
10 : 2 H Pages X 2 V Pages

See Rotation Parameter B (RBG1)

GA

Screen Over Process (RBOVR, 18003AH, bit 15~14 )00 : Outside the display area it repeats the image set in the display area
01 : Outside the display area it repeats the image set in the
Screen Over Pattern Register
10 : Everything outside the display area is transparent
11 : Sets display area to 0 ≤ x < 512 and 0 ≤ y <512 regardless of the plane size or bitmap size.
Everything outside the display area is transparent.
Screen Over Pattern Name (RBOPN, 1800BAH, bit 15~0 )Map Offset (RBMP, 18003EH, bit 6~4)

SE

Map (RBMPx, 180060H~18006EH )For Plane A (RBMPA, 180060H, bit 5~0 )For Plane B (RBMPB, 180060H, bit 13~8 )For Plane C (RBMPC, 180062H, bit 5~0 )For Plane D (RBMPD, 180062H, bit 13~8 )For Plane E (RBMPE, 180064H, bit 5~0 )For Plane F (RBMPF, 180064H, bit 13~8 )For Plane G (RBMPG, 180066H, bit 5~0 )For Plane H (RBMPH, 180066H, bit 13~8 )For Plane I (RBMPI, 180068H, bit 5~0)
For Plane J (RBMPJ, 180068H, bit 13~8 )For Plane K (RBMPK, 18006AH, bit 5~0 )For Plane L (RBMPL, 18006AH, bit 13~8 )For Plane M (RBMPM, 18006CH, bit 5~0 )For Plane N (RBMPN, 18006CH, bit 13~8 )For Plane O (RBMPO, 18006EH, bit 5~0 )For Plane P (RBMPP, 18006EH, bit 13~8 )286

Line Color Screen Color Mode (LCCLMD, 1800A8H, bit 15)
0 : Single Color
1 : Select per linentialLine Color Screen (LNCL)Line Color Screen Table Address (LCTA, 1800A8H, bit 2~1800AAH, bit 0)

Back Screen (BACK)Back Screen Color Mode (BKCLMD, 1800ACH, bit 15)
0 : Single Color
1 : Set each line

Normal Rectangular Windownfi

Window
Normal Rectangular Window
W0
W1
Normal Line Window
Sprite Window : SWdeBack Screen Table Address (BKTA, 1800ACH, bit 2~1800AEH, bit 0)

Co

Window Position (For Horizontal Coordinate)(WxxX, 1800C0H~1800CCH )W0 Start Point Coordinate (W0SX, 1800C0H, bit 9~0)
W0 End Point Coordinate (W0EX, 1800C4H, bit 9~0)
W1 Start Point Coordinate (W1SX, 1800C8H, bit 9~0)
W1 End Point Coordinate (W1EX, 1800CCH, bit 9~0)
Window Position (For Vertical Coordinate)(WxxY, 1800C2H~1800CEH )W0 Start Point Coordinate (W0SY, 1800C2H, bit 8~0)
W0 End Point Coordinate (W0EY, 1800C6H, bit 8~0)
W1 Start Point Coordinate (W1SY, 1800CAH, bit 8~0)
W1 End Point Coordinate (W1EY, 1800CEH, bit 8~0)

GA

Normal Line Window
Line Window Enable (WxLWE, 1800D8H~1800DCH)
For W0 (W0LWE, 1800D8H, bit 15)
For W1 (W1LWE, 1800DCH, bit 15 )0 : Does not set normal window to line window
1 : Sets normal window to line window

Line Window Table Address (WxLWTA, 1800D8H~1800DEH)
For W0 (W0LWTA, 1800D8H, bit 2~1800DAH, bit 1 )For W1 (W1LWTA, 1800DCH, bit 2~1800DEH, bit 1)

SE

Sprite Window

Sprite Window Enable (SPWINEN, 1800E0H, bit 4)
0 : Does not use Sprite Window
1 : Uses Sprite Window

ST-58-R2

287

Window Control(N0L0G, 1800D0H, bit 7)(N1L0G, 1800D0H, bit 15)(N2L0G, 1800D2H, bit 7)(N3L0G, 1800D2H, bit 15)(R0L0G, 1800D4H, bit 7)(SPL0G, 1800D4H, bit 15)(RPL0G, 1800D6H, bit 7)(CCL0G, 1800D6H, bit 15)de(N0W0E, 1800D0H, bit 1)(N1W0E, 1800D0H, bit 9)(N2W0E, 1800D2H, bit 1)(N3W0E, 1800D2H, bit 9)(R0W0E, 1800D4H, bit 1)(SPW0E, 1800D4H, bit 9)(RPW0E, 1800D6H, bit 1)(CCW0E, 1800D6H, bit 9)

nfi

Window Enable (For W0 ) (xxW0E, 1800D0H~1800D6H )For NBG0 of Transparent Process Window (or RBG1 )For NBG1 of Transparent Process Window (or EXBG)For NBG2 of Transparent Process Window
For NBG3 of Transparent Process Window
For RBG0 of Transparent Process Window
For Sprite of Transparent Process Window
For Rotation Parameter Window
For Color Calculation Window
0 : Does not use W0 Window
1 : Uses W0 WindowntialWindow Logic (xxLOG, 1800D0H~1800D6H)
For NBG0 of Transparent Process Window (or RBG1 )For NBG1 of Transparent Process Window (or EXBG)For NBG2 of Transparent Process Window
For NBG3 of Transparent Process Window
For RBG0 of Transparent Process Window
For Sprite of Transparent Process Window
For Rotation Parameter Window
For Color Calculation Window
0 : OR
1 : AND

Co

Window Enable (For W1 ) (xxW1E, 1800D0H~1800D6H )For NBG0 of Transparent Process Window (or RBG1 )For NBG1 of Transparent Process Window (or EXBG)For NBG2 of Transparent Process Window
For NBG3 of Transparent Process Window
For RBG0 of Transparent Process Window
For Sprite of Transparent Process Window
For Rotation Parameter Window
For Color Calculation Window
0 : Does not use W1 Window
1 : Uses W1 Window

SE(Continued)

GA

Window Enable (For SW ) (xxSWE, 1800D0H~1800D6H )For NBG0 of Transparent Process Window (or RBG1 )For NBG1 of Transparent Process Window (or EXBG)For NBG2 of Transparent Process Window
For NBG3 of Transparent Process Window
For RBG0 of Transparent Process Window
For Sprite of Transparent Process Window
For Color Calculation Window
0 : Does not use SW Window
1 : Uses SW Window

288(N0W1E, 1800D0H, bit 3)(N1W1E, 1800D0H, bit 11)(N2W1E, 1800D2H, bit 3)(N3W1E, 1800D2H, bit 11)(R0W1E, 1800D4H, bit 3)(SPW1E, 1800D4H, bit 11)(RPW1E, 1800D6H, bit 3)(CCW1E, 1800D6H, bit 11)(N0SWE, 1800D0H, bit 5)(N1SWE, 1800D0H, bit 13)(N2SWE, 1800D2H, bit 5)(N3SWE, 1800D2H, bit 13)(R0SWE, 1800D4H, bit 5)(SPSWE, 1800D4H, bit 13)(CCSWE, 1800D6H, bit 13)

Window Area (For W0 ) (xxW0A, 1800D0H~1800D6H )For NBG0 of Transparent Process Window (or RBG1 )For NBG1 of Transparent Process Window (or EXBG)For NBG2 of Transparent Process Window
For NBG3 of Transparent Process Window
For RBG0 of Transparent Process Window
For Sprite of Transparent Process Window
For Rotation Parameter Window
For Color Calculation Window
0 : Activates Inside of W0 Window
1 : Activates Outside of W0 Window(N0W0A, 1800D0H, bit 0)(N1W0A, 1800D0H, bit 8)(N2W0A, 1800D2H, bit 0)(N3W0A, 1800D2H, bit 8)(R0W0A, 1800D4H, bit 0)(SPW0A, 1800D4H, bit 8)(RPW0A, 1800D6H, bit 0)(CCW0A, 1800D6H, bit 8)(N0W1A, 1800D0H, bit 2)(N1W1A, 1800D0H, bit 10)(N2W1A, 1800D2H, bit 2)(N3W1A, 1800D2H, bit 10)(R0W1A, 1800D4H, bit 2)(SPW1A, 1800D4H, bit 10)(RPW1A, 1800D6H, bit 2)(CCW1A, 1800D6H, bit 10)

nfi

de

Window Area (For W1 ) (xxW1A, 1800D0H~1800D6H )For NBG0 of Transparent Process Window (or RBG1 )For NBG1 of Transparent Process Window (or EXBG)For NBG2 of Transparent Process Window
For NBG3 of Transparent Process Window
For RBG0 of Transparent Process Window
For Sprite of Transparent Process Window
For Rotation Parameter Window
For Color Calculation Window
0 : Activates Inside of W1 Window
1 : Activates Outside of W1 WindowntialWindow Control (Continued)(N0SWA, 1800D0H, bit 4)(N1SWA, 1800D0H, bit 12)(N2SWA, 1800D2H, bit 4)(N3SWA, 1800D2H, bit 12)(R0SWA, 1800D4H, bit 4)(SPSWA, 1800D4H, bit 12)(CCSWA, 1800D6H, bit 12)

SE

GA

Co

Window Area (For SW ) (xxSWA, 1800D0H~1800D6H )For NBG0 of Transparent Process Window (or RBG1 )For NBG1 of Transparent Process Window (or EXBG)For NBG2 of Transparent Process Window
For NBG3 of Transparent Process Window
For RBG0 of Transparent Process Window
For Sprite of Transparent Process Window
For Color Calculation Window
0 : Activates Inside of SW Window
1 : Activates Outside of SW Window

ST-58-R2

289

SpriteSprite Color Calculation Condition Number (SPCCN, 1800E0H, BIT 10~8)

Sprite Window Enable (SPWINEN, 1800E0H, bit 4 )0 : Does not use Sprite Window
1 : Uses Sprite Window
Sprite Type (SPTYPE, 1800E0H, bit 3~0)nfi

Priority Number (For Sprite) (SxPRIN, 1800F0H~1800F6H)
For Sprite Register 0(S0PRIN, 1800F0H, bit 2~0)
For Sprite Register 1(S1PRIN, 1800F0H, bit 10~8)
For Sprite Register 2(S2PRIN, 1800F2H, bit 2~0)
For Sprite Register 3(S3PRIN, 1800F2H, bit 10~8)
For Sprite Register 4(S4PRIN, 1800F4H, bit 2~0)
For Sprite Register 5(S5PRIN, 1800F4H, bit 10~8)
For Sprite Register 6(S6PRIN, 1800F6H, bit 2~0)
For Sprite Register 7(S7PRIN, 1800F6H, bit 10~8)deSprite Color Mode (SPCLMD, 1800E0H, bit 5)
0 : All sprite data is palette format only
1 : Sprite data is a combination of palette format and RGB formatntialSprite Color Calculation Condition (SPCCCS, 1800E0H, bit 13~12)00 : When (Priority Number) ≤ (Color Calculation Condition Number)
01 : When (Priority Number) = (Color Calculation Condition Number)
10 : When (Priority Number) ≥ (Color Calculation Condition Number)
11 : When the MSB of the Color Data is 1

SE

GA

Co

Color Calculation Ratio (For Sprite) (SxCCRT, 180100H~180106H)
For Sprite Register 0(S0CCRT, 180100H, bit 4~0)
For Sprite Register 1(S1CCRT, 180100H, bit 12~8)
For Sprite Register 2(S2CCRT, 180102H, bit 4~0)
For Sprite Register 3(S3CCRT, 180102H, bit 12~8)
For Sprite Register 4(S4CCRT, 180104H, bit 4~0)
For Sprite Register 5(S5CCRT, 180104H, bit 12~8)
For Sprite Register 6(S6CCRT, 180106H, bit 4~0)
For Sprite Register 7(S7CCRT, 180106H, bit 12~8)290

Do t Col or Dat adeSpec ial F unct ion C ode Sel ec t (xx SFC S, 180024H)
Fo rNBG0 ( or RBG1)(N0 SFC S, 180024H, bi t 0)
Fo r NBG1 ( or EXBG)(N1 SFC S, 180024H, bi t 1)
Fo r NBG2(N2 SFC S, 180024H, bi t 2)
Fo r NBG3(N3 SFC S, 180024H, bi t 3)
Fo r RBG0(R0 SFC S, 180024H, bi t 4)
0 : Act ivat es Speci al Func ti on
Code A
1 : Act ivat es Speci al Func ti on
Code Bntial

Co lor RAM Addr es s Offs et (xx CAOS, 1800E4H ~1800E6H )FoNBG0r( or RBG1)(N0 CAOS, 1800E4H , bi t 2~0)
Fo rNBG1 ( or EXBG)(N1 CAOS, 1800E4H , bi t 6~4)
Fo rNBG2(N2 CAOS, 1800E4H , bi t 10~8)
Fo rNBG3(N3 CAOS, 1800E4H , bi t 14~12)
Fo rRBG0(R0 CAOS, 1800E6H , bi t 2~0)
Fo r Spr ite(SPC AOS, 1800E6H, bi t 4~0)

SE

GA

Co

nfi

Spec ial F unct ion C ode ( SF CD xx , 180026H)
Fo r Spec ial F unct ion Code A (SFC DAx , 180026H, bi t 7~0)
Fo r Spec ial F unct ion Code B (SFC DBx , 180026H, bi t 15~8)
SF CDx 0 : Wh en D ot Col or Code' s owerl
4 bi ts ar e 0H or 1H
SF CDx 1 : Wh en D ot Col or Code' s owerl
4 bi ts ar e 2H or 3H
SF CDx 2 : Wh en D ot Col or Code' s owerl
4 bi ts ar e 4H or 5H
SF CDx 3 : Wh en D ot Col or Code' s owerl
4 bi ts ar e 6H or 7H
SF CDx 4 : Wh en D ot Col or Code' s owerl
4 bi ts ar e 8H or 9H
SF CDx 5 : Wh en D ot Col or Code' s owerl
4 bi ts ar e AH or BH
SF CDx 6 : Wh en D ot Col or Code' s owerl
4 bi ts ar e CH or D H
SF CDx 7 : Wh en D ot Col or Code' s owerl
4 bi ts ar e EH or FH
0: Do es not use Speci al Func ti on
1: Us es Spec ial F unct ion

ST-58-R2

291

PrioritydeSpecial Priority Mode (xxSPRM, 1800EAH)For NBG0 (or RBG1)(N0SPRM, 1800EAH, bit 1~0)
For NBG1 (or EXBG)(N1SPRM, 1800EAH, bit 3~2)
For NBG2(N2SPRM, 1800EAH, bit 5~4)
For NBG3(N3SPRM, 1800EAH, bit 7~6)
For RBG0(R0SPRM, 1800EAH, bit 9~8)00 : Mode 0 : Selects number LSB per screen
01 : Mode 1 : Selects number LSB per character
10 : Mode 2 : Selects number LSB per dot

ntialLine Color Screen Insert Enable (xxLCEN, 1800E8H )For NBG0 (or RBG1)(N0LCEN, 1800E8H, bit 0)
For NBG1 (or EXBG)(N1LCEN, 1800E8H, bit 1)
For NBG2(N2LCEN, 1800E8H, bit 2)
For NBG3(N3LCEN, 1800E8H, bit 3)
For RBG0(R0LCEN, 1800E8H, bit 4)
For Sprite(SPLCEN, 1800E8H, bit 5 )0 : Does not insert line color screen when the corresponding screen is the top image
1 : Inserts line color screen when the corresponding screen is the top image

SE

GA

Co

nfi

Special Priority Number (For Scroll Screen) (xxPRIN, 1800F8H~1800FCH)
For NBG0 (or RBG1)(N0PRIN, 1800F8H, bit 2~0)
For NBG1 (or EXBG)(N1PRIN, 1800F8H, bit 10~8)
For NBG2(N2PRIN, 1800FAH, bit 2~0)
For NBG3(N3PRIN, 1800FAH, bit 10~8)
For RBG0(R0PRIN, 1800FCH, bit 2~0)292

Gradation Calculation Enable (BOKEN, 1800ECH, bit 15)
0 : Does not use Gradation Calculation Function
1 : Uses Gradation Calculation Function
Gradation Screen Number (BOKN, 1800ECH, bit 14~12)000 : Sprite
001 : RBG0010 : NBG0 or RBG1
100 : NBG1 or EXBG
101 : NBG2
110 : NBG3

ntial

Color CalculationdeExpanded Color Calculation Enable (EXCCEN, 1800ECH, bit 10)
0 : Does not use Expanded Color Calculation
1 : Uses Expanded Color Calculation

Color Calculation Ratio Mode (CCRTMD, 1800ECH, bit 9 )0 : Mode 0 : In the case of color calculation, select per top image side
1 : Mode 1 : In the case of color calculation, select per second image sidenfi

Color Calculation Mode (CCMD, 1800ECH, bit 8)
0 : Mode 0 : Add according to the register value color calculation ratio
1 : Mode 1 : Add as is

Co

Color Calculation Enable (xxCCEN, 1800ECH)
For NBG0 (or RBG1)(N0CCEN, 1800ECH, bit 0)
For NBG1 (or EXBG)(N1CCEN, 1800ECH, bit 1)
For NBG2(N2CCEN, 1800ECH, bit 2)
For NBG3(N3CCEN, 1800ECH, bit 3)
For RBG0(R0CCEN, 1800ECH, bit 4)
For LNCL(LCCCEN, 1800ECH, bit 5)
For Sprite(SPCCEN, 1800ECH, bit 6 )0 : Does not do Color Calculation
1 : Does Color Calculation

GA

Special Color Calculation Mode (xxSCCM, 1800EEH)
For NBG0 (or RBG1)(N0SCCM, 1800EEH, bit 1~0)
For NBG1 (or EXBG)(N1SCCM, 1800EEH, bit 3~2)
For NBG2(N2SCCM, 1800EEH, bit 5~4)
For NBG3(N3SCCM, 1800EEH, bit 7~6)
For RBG0(R0SCCM, 1800EEH, bit 9~8)00 :Mode 0 : Select color calculation enable per screen
01 :Mode 1 : Select color calculation enable per character
10 :Mode 2 : Select color calculation enable per dot
11 :Mode 3 : Select color calculation enable per MSB of color data

SE

Color Calculation Ratio (For Scroll Screen) (xxCCRT, 180108H~18010EH)For NBG0 (or RBG1)(N0CCRT, 180108H, bit 4~0)
For NBG1 (or EXBG)(N1CCRT, 180108H, bit 12~8)
For NBG2(N2CCRT, 18010AH, bit 4~0)
For NBG3(N3CCRT, 18010AH, bit 12~8)
For RBG0(R0CCRT, 18010CH, bit 4~0)
For LNCL(LCCCRT, 18010EH, bit 4~0)
For BACK(BKCCRT, 18010EH, bit 12~8 )ST-58-R2

293

Color Offset

deColor Offset Select (xxCOSL, 180112H)
For NBG0 (or RBG1)(N0COSL, 180112H, bit 0)
For NBG1 (or EXBG)(N1COSL, 180112H, bit 1)
For NBG2(N2COSL, 180112H, bit 2)
For NBG3(N3COSL, 180112H, bit 3)
For RBG0(R0COSL, 180112H, bit 4)
For BACK(BKCOSL, 180112H, bit 5)
For Sprite(SPCOSL, 180112H, bit 6)
0 : Uses value of Color Offset A
1 : Uses value of Color Offset B

ntialColor Offset Enable (xxCOEN, 180110H )For NBG0 (or RBG1)(N0COEN, 180110H, bit 0)
For NBG1 (or EXBG)(N1COEN, 180110H, bit 1)
For NBG2(N2COEN, 180110H, bit 2)
For NBG3(N3COEN, 180110H, bit 3)
For RBG0(R0COEN, 180110H, bit 4)
For BACK(BKCOEN, 180110H, bit 5)
For Sprite(SPCOEN, 180110H, bit 6 )0 : Does not use Color Offset Function
1 : Uses Color Offset Function

Shadow Function

Co

nfi

Color Offset Value (COxxx, 180114H~18011EH)For Color Offset A Red Data
(COARD, 180114H, bit 8~0 )For Color Offset A Green Data (COAGR, 180116H, bit 8~0 )For Color Offset A Blue Data
(COABL, 180118H, bit 8~0 )For Color Offset B Red Data
(COARD, 18011AH, bit 8~0 )For Color Offset B Green Data (COAGR, 18011CH, bit 8~0 )For Color Offset B Blue Data
(COABL, 18011EH, bit 8~0 )GA

Shadow Enable (xxSDEN, 1800E2H)
For NBG0 (or RBG1)(N0SDEN, 1800E2H, bit 0)
For NBG1 (or EXBG)(N1SDEN, 1800E2H, bit 1)
For NBG2(N2SDEN, 1800E2H, bit 2)
For NBG3(N3SDEN, 1800E2H, bit 3)
For RBG0(R0SDEN, 1800E2H, bit 4)
For BACK(BKSDEN, 1800E2H, bit 5 )0 : Does not use Shadow Function (Does not add shadow)
1 : Uses Shadow Function (Adds shadow)

SE

Transparent Shadow Select (TPSDSL, 1800E2H)
0 : Disables Transparent Shadow Sprite
1 : Enables Transparent Shadow Sprite

294

nti
al

SE

GA

Co

nfi

de

Chapter 16 Quick Reference

ST-58-R2

16.1
16.2
16.3
16.4

Register Map.......................... . 296
Register Bit List...................... . 315
Register Bit Functions........... .. 328
Table List................................. 389

295

Quick reference contains registers and VRAM tables as follows:
Register Map:

Shows registers in order of addresses; shows
register bit abbreviations.

(2)Register Bit List:

Shows in order of register names; shows register
bit names, bit abbreviations, addresses and bit
positions.

(3)Register Bit Functions:Shows register bit functions in order of register
address.

(4)

Table List:

Shows VRAM table configuration.

de

nti
al

(1)

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16.1 Register Map

SE

GA

Co

(A listing of the register maps begin on the next page.)296

• TV SCREEN MODE (READ ALLOWED)
15
DISP
7
LSMD1

14
~
6
LSMD0

13
~
5
VRESO1

12~
4
VRESO0

11
~
3
~

10
~
2
HRESO2

9~
1
HRESO18BDCLMD
0
HRESO09
EXLTEN
1DASEL

8EXSYEN0
EXBGEN

nti
al

TVMD
180000H• EXTERNAL SIGNAL ENABLE REGISTER (READ ALLOWED)
15
~
7
~

EXTEN
180002H

14
~
6
~

13
~
5
~

TVSTAT
180004H

14
~
6
~

12
~
4
~

11
~
3
VBLANK

10~2
HBLANK

9
EXLTFG
1ODD

8EXSYFG
0
PAL

12
~
4
~

11
~
3
VER3

10
~
2
VER2

9
~
1
VER1

8
~
0
VER0

13
~
5
HCT5

12
~
4
HCT4

11
~
3
HCT3

10
~
2
HCT2

9
HCT9
1
HCT1

8
HCT8
0
HCT0

13
~
5
VCT5

12
~
4
VCT4

11
~
3
VCT3

10
~
2
VCT2

9
VCT9
1
VCT1

8
VCT8
0
VCT0

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
~

9
~
1
~

8
~
0
~

13
~
5
~

• VRAM SIZE (READ ALLOWED)VRSIZE
180006H

15
VRAMSZ
7
~

14
~
6
~

• H-COUNTER (READ ONLY)
14
~
6
HCT6

13
~
5
~

Co

15
~
7
HCT7

HCNT
180008H

10
~
2
~

de

15
~
7
~

11
~
3
~

nfi

• SCREEN STATUS (READ ONLY)

12
~
4
~

• V-COUNTER (READ ONLY)
15
~
7
VCT7

14
~
6
VCT6

GA

VCNT
18000AH• RESERVE

15
~
7
~

18000CH

14~
6~• RAM CONTROL (READ ALLOWED)
15
14
13
12
11
10
9
8
~
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00

SE
RAMCTL
18000EH

ST-58-R2

297

• VRAM CYCLE PATTERN (BANK A0)
15
14
13
12
11
10
9
8
VCP0A03 VCP0A02 VCP0A01 VCP0A00 VCP1A03 VCP1A02 VCP1A01 VCP1A00
7
6
5
4
3
2
1
0
VCP2A03 VCP2A02 VCP2A01 VCP2A00 VCP3A03 VCP3A02 VCP3A01 VCP3A00

nti
al

CYCA0L
180010H• VRAM CYCLE PATTERN (BANK A0)• VRAM CYCLE PATTERN (BANK A1)
CYCA1L
180014H

15
14
13
12
11
10
9
8
VCP0A13 VCP0A12 VCP0A11 VCP0A10 VCP1A13 VCP1A12 VCP1A11 VCP1A10
7
6
5
4
3
2
1
0
VCP2A13 VCP2A12 VCP2A11 VCP2A10 VCP3A13 VCP3A12 VCP3A11 VCP3A10• VRAM CYCLE PATTERN (BANK A1)
CYCA1U
180016H

15
14
13
12
11
10
9
8
VCP4A13 VCP4A12 VCP4A11 VCP4A10 VCP5A13 VCP5A12 VCP5A11 VCP5A10
7
6
5
4
3
2
1
0
VCP6A13 VCP6A12 VCP6A11 VCP6A10 VCP7A13 VCP7A12 VCP7A11 VCP7A10• VRAM CYCLE PATTERN (BANK BO)

15
14
13
12
11
10
9
8
VCP0B03 VCP0B02 VCP0B01 VCP0B00 VCP1B03 VCP1B02 VCP1B01 VCP1B00
7
6
5
4
3
2
1
0
VCP2B03 VCP2B02 VCP2B01 VCP2B00 VCP3B03 VCP3B02 VCP3B01 VCP3B00

Co

CYCB0L
180018H

de

15
14
13
12
11
10
9
8
VCP4A03 VCP4A02 VCP4A01 VCP4A00 VCP5A03 VCP5A02 VCP5A01 VCP5A00
7
6
5
4
3
2
1
0
VCP6A03 VCP6A02 VCP6A01 VCP6A00 VCP7A03 VCP7A02 VCP7A01 VCP7A00

nfi

CYCA0U
180012H• VRAM CYCLE PATTERN (BANK BO)

GA

CYCB0U
18001AH

15
14
13
12
11
10
9
8
VCP4B03 VCP4B02 VCP4B01 VCP4B00 VCP5B03 VCP5B02 VCP5B01 VCP5B00
7
6
5
4
3
2
1
0
VCP6B03 VCP6B02 VCP6B01 VCP6B00 VCP7B03 VCP7B02 VCP7B01 VCP7B00• VRAM CYCLE PATTERN (BANK B1)
CYCB1L
18001CH

15
14
13
12
11
10
9
8
VCP0B13 VCP0B12 VCP0B11 VCP0B10 VCP1B13 VCP1B12 VCP1B11 VCP1B10
7
6
5
4
3
2
1
0
VCP2B13 VCP2B12 VCP2B11 VCP2B10 VCP3B13 VCP3B12 VCP3B11 VCP3B10• VRAM CYCLE PATTERN (BANK B1)
15
14
13
12
11
10
9
8
VCP4B13 VCP4B12 VCP4B11 VCP4B10 VCP5B13 VCP5B12 VCP5B11 VCP5B10
7
6
5
4
3
2
1
0
VCP6B13 VCP6B12 VCP6B11 VCP6B10 VCP7B13 VCP7B12 VCP7B11 VCP7B10SECYCB1U
18001EH

298

• SCREEN DISPLAY ENABLE
BGON
180020H

14
~
6
~

13
~
5
R1ON

12
R0TPON
4
R0ON

11
N3TPON
3
N3ON

10
N2TPON
2N2ON

9N1TPON
1
N1ON

8
N0TPON0N0ON

14MZSZV26~13
MZSZV15~12
MZSZV04R0MZE11MZSZH33N3MZE

10MZSZH22N2MZE

9MZSZH11N1MZE

8MZSZH0
0
N0MZE

nti
al

15
~
7
~

MZCTL
180022H15
MZSZV37~• SPECIAL FUNCTION CODE SELECT
15
~
7
~

SFSEL
180024H

14
~
6
~

13
~
5
~

12
~
4
R0SFCS

11~3
N3SFCS

10~2
N2SFCS

9~1
N1SFCS

8~0
N0SFCS

13
SFCDB55SFCDA512
SFCDB44SFCDA4

11
SFCDB3
3
SFCDA3

10
SFCDB2
2
SFCDA29
SFCDB1
1
SFCDA1

8
SFCDB00
SFCDA0

14
13
12
11
10
9
~
N1CHCN1 N1CHCN0 N1BMSZ1 N1BMSZ0 N1BMEN
6
5
4
3
2
1
N0CHCN2 N0CHCN1 N0CHCN0 N0BMSZ1 N0BMSZ0 N0BMEN

8
N1CHSZ0N0CHSZ

15
SFCDB7
7SFCDA7

14
SFCDB6
6SFCDA6nfi• SPECIAL FUNCTION CODESFCODE
180026Hde• MOSAIC CONTROLCHCTLA
180028H

15
~
7
~

Co

• CHARACTER CONTROL (NBG0, NBG1)• CHARACTER CONTROL (NBG2, NBG3, RBG0)
15
~
7
~

14
13
12
R0CHCN2 R0CHCN1 R0CHCN0654~N3CHCN N3CHSZGA

CHCTLB
18002AH

11
~
3
~

10
R0BMSZ
2~

9
R0BMEN
1
N2CHCN

8
R0CHSZ
0N2CHSZ

12N1BMCC
4
N0BMCC

11
~
3
~

10
N1BMP6
2
N0BMP6

9
N1BMP5
1
N0BMP5

8
N1BMP40
N0BMP412~
4R0BMCC

11
~
3
~

10
~
2
R0BMP6

9~
1
R0BMP5

8~
0
R0BMP4• BITMAP PALETTE NUMBER (NBGO, NBG1)
BMPNA
18002CH

15
~
7
~

14
~
6
~

13
N1BMPR
5
N0BMPRSE• BITMAP PALETTE NUMBER (RBG0)
BMPNB
18002EH

ST-58-R2

15
~
7
~

14
~
6
~

13
~
5
R0BMPR

299

• PATTERN NAME CONTROL (NBG0)
15
14
13
N0PNB
N0CNSM~
7
6
5
N0SPLT6 N0SPLT5 N0SPLT412~4N0SCN411~
3
N0SCN310~
2N0SCN2

9N0SPR
1N0SCN18
N0SCC
0N0SCN012~
4N1SCN411~
3
N1SCN310~
2N1SCN29N1SPR
1N1SCN18
N1SCC
0N1SCN012~
4N2SCN411~
3
N2SCN310~
2
N2SCN29N2SPR
1N2SCN18N2SCC
0N2SCN012~
4N3SCN411~
3
N3SCN310~
2N3SCN29N3SPR
1N3SCN18N3SCC
0N3SCN012~
4
R0SCN411~
3
R0SCN310~
2R0SCN2

9R0SPR
1R0SCN1

8R0SCC
0R0SCN0PNCN1180032H

15
14
13
N1PNB
N1CNSM~
7
6
5
N1SPLT6 N1SPLT5 N1SPLT4• PATTERN NAME CONTROL (NBG2)PNCN2180034H

15
14
13
N2PNB
N2CNSM~
7
6
5
N2SPLT6 N2SPLT5 N2SPLT4PNCN3180036H

15
14
13
N3PNB
N3CNSM~
7
6
5
N3SPLT6 N3SPLT5 N3SPLT4• PATTERN NAME CONTROL (RBG0)
15
14
13
R0PNB
R0CNSM~
7
6
5
R0SPLT6 R0SPLT5 R0SPLT4

Co

PNCR
180038H• PLANE SIZE

15
14
13
12
11
10
9
8
RBOVR1 RBOVR0 RBPLSZ1 RBPLSZ0 RAOVR1 RAOVR0 RAPLSZ1 RAPLSZ0
7
6
5
4
3
2
1
0
N3PLSZ1 N3PLSZ0 N2PLSZ1 N2PLSZ0 N1PLSZ1 N1PLSZ0 N0PLSZ1 N0PLSZ0

GA

PLSZ
18003AH

nfi• PATTERN NAME CONTROL (NBG3)de• PATTERN NAME CONTROL (NBG1)

nti
al

PNCN0
180030H• MAP OFFSET (NBG0~NBG3)
MPOFN
18003CH

15
~
7
~

14
N3MP8
6
N1MP8

13
N3MP7
5
N1MP7

12
N3MP6
4
N1MP6

11
~
3
~

10
N2MP8
2
N0MP8

9
N2MP7
1
N0MP7

8
N2MP6
0
N0MP6

11
~
3
~

10
~
2
RAMP8

9
~
1
RAMP7

8
~
0
RAMP6

• MAP OFFSET (ROTATION PARAMETER A,B)
15
~
7
~

14
~
6
RBMP8

SE

MPOFR
18003EH

300

13
~
5
RBMP7

12
~
4
RBMP6

12
N0MPB4
4
N0MPA4

11
N0MPB3
3
N0MPA3

10
N0MPB2
2
N0MPA29N0MPB1
1
N0MPA18
N0MPB00
N0MPA013
N0MPD55N0MPC512
N0MPD44N0MPC4

11
N0MPD3
3
N0MPC3

10
N0MPD2
2
N0MPC29N0MPD1
1
N0MPC18
N0MPD00
N0MPC013
N1MPB55
N1MPA512
N1MPB4
4
N1MPA411
N1MPB3
3
N1MPA3

10
N1MPB2
2
N1MPA28
N1MPB00
N1MPA013
N1MPD55N1MPC5de

9
N1MPB11
N1MPA112
N1MPD44N1MPC4

11
N1MPD33
N1MPC3

10
N1MPD2
2
N1MPC29N1MPD1
1
N1MPC18
N1MPD00
N1MPC013
N2MPB55
N2MPA512
N2MPB4
4
N2MPA411
N2MPB3
3
N2MPA3

10
N2MPB22
N2MPA29
N2MPB1
1
N2MPA18
N2MPB00
N2MPA0

14
~
6
~

13
N2MPD55N2MPC512
N2MPD44N2MPC411
N2MPD3
3
N2MPC3

10
N2MPD22
N2MPC29
N2MPD1
1
N2MPC18
N2MPD00N2MPC013
N3MPB55
N3MPA512
N3MPB4
4
N3MPA411
N3MPB3
3
N3MPA3

10
N3MPB2
2
N3MPA29
N3MPB1
1
N3MPA1

8
N3MPB00
N3MPA013
N3MPD55
N3MPC512
N3MPD44N3MPC4

11
N3MPD33
N3MPC3

10
N3MPD2
2
N3MPC29N3MPD1
1
N3MPC1

8
N3MPD00N3MPC0MPABN0180040H

15
~
7
~

14
~
6
~

• MAP (NBG0, PLANE C,D)
MPCDN0180042H

15
~
7
~

14
~
6
~

• MAP (NBG1, PLANE A,B)
MPABN1
180044H

15
~
7
~

14
~
6
~

MPCDN1
180046H

15
~
7
~

14
~
6
~

• MAP (NBG2, PLANE A,B)
15
~
7
~

14
~
6
~

Co

MPABN2180048H

nfi• MAP (NBG1, PLANE C,D)

nti
al

13
N0MPB55
N0MPA5GA• MAP (NBG0, PLANE A,B)

• MAP (NBG2, PLANE C,D)
MPCDN218004AH

15~
7~• MAP (NBG3, PLANE A,B)
MPABN318004CH

15
~
7
~

14
~
6
~

SE

• MAP (NBG3, PLANE C,D)
MPCDN318004EH

ST-58-R2

15
~
7
~

14
~
6
~

301

• MAP (ROTATION PARAMETER A, PLANE A,B)
15
~
7
~

14
~
6
~

13
RAMPB55RAMPA5

12
RAMPB4
4RAMPA4

11
RAMPB3
3
RAMPA3• MAP (ROTATION PARAMETER A, PLANE C,D)
15
~
7
~

14
~
6
~

13
RAMPD5
5RAMPC512
RAMPD4
4RAMPC4

11
RAMPD3
3
RAMPC3• MAP (ROTATION PARAMETER A, PLANE E,F)
MPEFRA
180054

15
~
7
~

14
~
6
~

13
RAMPF55RAMPE512
RAMPF4
4RAMPE411
RAMPF3
3
RAMPE3• MAP (ROTATION PARAMETER A, PLANE G,H)
15
~
7
~

14
~
6
~

8
RAMPB00RAMPA010
RAMPD2
2
RAMPC2

9RAMPD1
1
RAMPC1

8
RAMPD00RAMPC010
RAMPF2
2
RAMPE2

9RAMPF1
1
RAMPE1

8
RAMPF00
RAMPE0

13
12
11
10
9
8
RAMPH5 RAMPH4 RAMPH3 RAMPH2 RAMPH1 RAMPH0
5
4
3
2
1
0
RAMPG5 RAMPG4 RAMPG3 RAMPG2 RAMPG1 RAMPG0nfi

MPGHRA
180056H

9RAMPB1
1
RAMPA1de

MPCDRA
180052H

10
RAMPB2
2
RAMPA2nti
al

MPABRA
180050H• MAP (ROTATION PARAMETER A, PLANE I,J)
14
~
6
~

13
RAMPJ5
5
RAMPI5

12
RAMPJ4
4
RAMPI4

11
RAMPJ3
3
RAMPI3

10
RAMPJ2
2
RAMPI2

9RAMPJ1
1
RAMPI1

8
RAMPJ00
RAMPI011
RAMPL3
3
RAMPK310
RAMPL2
2
RAMPK2

9RAMPL1
1
RAMPK1

8
RAMPL00RAMPK0Co

MPIJRA
180058H

15~
7~• MAP (ROTATION PARAMETER A, PLANE K,L)
14
~
6
~

13
RAMPL55RAMPK5GAMPKLRA
18005AH

15
~
7
~

12
RAMPL4
4
RAMPK4• MAP (ROTATION PARAMETER A, PLANE M,N)
MPMNRA
18005CH

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RAMPN5 RAMPN4 RAMPN3 RAMPN2 RAMPN1 RAMPN0
5
4
3
2
1
0
RAMPM5 RAMPM4 RAMPM3 RAMPM2 RAMPM1 RAMPM0• MAP (ROTATION PARAMETER A, PLANE O,P)
15
~
7
~

SE

MPOPRA
18005EH

302

14
~
6
~

13
12
11
10
9
8
RAMPP5 RAMPP4 RAMPP3 RAMPP2 RAMPP1 RAMPP0
5
4
3
2
1
0
RAMPO5 RAMPO4 RAMPO3 RAMPO2 RAMPO1 RAMPO0• MAP (ROTATION PARAMETER B, PLANE A,B)
14
~
6
~

13
RBMPB5
5
RBMPA5

12
RBMPB4
4
RBMPA4

11
RBMPB3
3
RBMPA3• MAP (ROTATION PARAMETER B, PLANE C,D)
MPCDRB
180062H

15
~
7
~

14
~
6
~

13
RBMPD55
RBMPC5

12
RBMPD4
4
RBMPC4

11
RBMPD3
3
RBMPC3

15
~
7
~

14
~
6
~

13
RBMPF5
5
RBMPE5

9
RBMPB1
1
RBMPA1

8
RBMPB00
RBMPA010
RBMPD2
2
RBMPC2

9
RBMPD1
1
RBMPC1

8
RBMPD00
RBMPC09
RBMPF1
1
RBMPE1

8
RBMPF00
RBMPE0de• MAP (ROTATION PARAMETER B, PLANE E,F)
MPEFRB
180064

10
RBMPB2
2
RBMPA2nti
al

MPABRB
180060H

15
~
7
~

12
RBMPF4
4
RBMPE4

11
RBMPF3
3
RBMPE3

10
RBMPF2
2
RBMPE2• MAP (ROTATION PARAMETER B, PLANE G,H)
15
~
7
~

14
~
6
~

13
12
RBMPH5 RBMPH454
RBMPG5 RBMPG4

11
10
9
8
RBMPH3 RBMPH2 RBMPH1 RBMPH03210
RBMPG3 RBMPG2 RBMPG1 RBMPG0nfi

MPGHRB
180066H• MAP (ROTATION PARAMETER B, PLANE I,J)
15
~
7
~

14
~
6
~

13
RBMPJ5
5
RBMPI5

12
RBMPJ4
4
RBMPI4Co

MPIJRB
180068H

11
RBMPJ3
3
RBMPI3

10
RBMPJ2
2
RBMPI2

9
RBMPJ1
1
RBMPI1

8
RBMPJ00
RBMPI011
RBMPL3
3
RBMPK3

10
RBMPL2
2
RBMPK2

9
RBMPL1
1
RBMPK1

8
RBMPL00
RBMPK0• MAP (ROTATION PARAMETER B, PLANE K,L)
15
~
7
~

14
~
6
~

GA

MPKLRB
18006AH

13
RBMPL55
RBMPK5

12
RBMPL4
4
RBMPK4• MAP (ROTATION PARAMETER B, PLANE M,N)
MPMNRB
18006CH

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RBMPN5 RBMPN4 RBMPN3 RBMPN2 RBMPN1 RBMPN0
5
4
3
2
1
0
RBMPM5 RBMPM4 RBMPM3 RBMPM2 RBMPM1 RBMPM0

SE• MAP (ROTATION PARAMETER B, PLANE O,P)
MPOPRB
18006EH

ST-58-R2

15
~
7
~

14
~
6
~

13
12
RBMPP5 RBMPP45
4RBMPO5 RBMPO4

11
10
9
8
RBMPP3 RBMPP2 RBMPP1 RBMPP032
10
RBMPO3 RBMPO2 RBMPO1 RBMPO0303

• SCREEN SCROLL VALUE (NBG0, HORIZONTAL INTEGER PART)
15~
7
N0SCXI7

14~
6
N0SCXI6

13~
5
N0SCXI512~4
N0SCXI41110
9~N0SCXI10 N0SCXI9321
N0SCXI3 N0SCXI2 N0SCXI18N0SCXI80
N0SCXI0ntial

SCXIN0180070H• SCREEN SCROLL VALUE (NBG0, HORIZONTAL FRACTIONAL PART)SCXDN0180072H

15
14
13
12
11
10
9
8
N0SCXD1 N0SCXD2 N0SCXD3 N0SCXD4 N0SCXD5 N0SCXD6 N0SCXD7 N0SCXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SCYIN0180074H

15~
7
N0SCYI7

14~
6
N0SCYI6

13~
5
N0SCYI512~4
N0SCYI4de• SCREEN SCROLL VALUE (NBG0, VERTICAL INTEGER PART)

11
10
9
~
N0SCYI10 N0SCYI932
1
N0SCYI3 N0SCYI2 N0SCYI1

8
N0SCYI80
N0SCYI0• SCREEN SCROLL VALUE (NBG0, VERTICAL FRACTIONAL PART)

15
14
13
12
11
10
9
8
N0SCYD1 N0SCYD2 N0SCYD3 N0SCYD4 N0SCYD5 N0SCYD6 N0SCYD7 N0SCYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

nfi

SCYDN0180076H• COORDINATE INCREMENT (NBG0, HORIZONTAL INTEGER PART)
14
~
6
~

13
~
5
~

12
~
4
~

Co

ZMXIN0180078H

15
~
7
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N0ZMXI2 N0ZMXI1 N0ZMXI0• COORDINATE INCREMENT (NBG0, HORIZONTAL FRACTIONAL PART)
15
14
13
12
11
10
9
8
N0ZMXD1 N0ZMXD2 N0ZMXD3 N0ZMXD4 N0ZMXD5 N0ZMXD6 N0ZMXD7 N0ZMXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

GA

ZMXDN018007AH• COORDINATE INCREMENT (NBG0, VERTICAL INTEGER PART)ZMYIN018007CH

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N0ZMYI2 N0ZMYI1 N0ZMYI0• COORDINATE INCREMENT (NBG0, VERTICAL FRACTIONAL PART)
15
14
13
12
11
10
9
8
N0ZMYD1 N0ZMYD2 N0ZMYD3 N0ZMYD4 N0ZMYD5 N0ZMYD6 N0ZMYD7 N0ZMYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SE

ZMYDN018007EH

304

• SCREEN SCROLL VALUE (NBG1, HORIZONTAL INTEGER PART)
15~
7
N1SCXI7

14~
6
N1SCXI6

13~
5
N1SCXI512~4N1SCXI41110
9~N1SCXI10 N1SCXI9321
N1SCXI3 N1SCXI2 N1SCXI18N1SCXI80N1SCXI0ntial

SCXIN1
180080H• SCREEN SCROLL VALUE (NBG1, HORIZONTAL FRACTIONAL PART)SCXDN1
180082H

15
14
13
12
11
10
9
8
N1SCXD1 N1SCXD2 N1SCXD3 N1SCXD4 N1SCXD5 N1SCXD6 N1SCXD7 N1SCXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SCYIN1
180084H

15~
7N1SCYI714~6N1SCYI613~5N1SCYI5de• SCREEN SCROLL VALUE (NBG1, VERTICAL INTEGER PART)12~4N1SCYI411109~N1SCYI10 N1SCYI9321
N1SCYI3 N1SCYI2 N1SCYI18N1SCYI80
N1SCYI0• SCREEN SCROLL VALUE (NBG1, VERTICAL FRACTIONAL PART)
15
14
13
12
11
10
9
8
N1SCYD1 N1SCYD2 N1SCYD3 N1SCYD4 N1SCYD5 N1SCYD6 N1SCYD7 N1SCYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

nfi

SCYDN1
180086H• COORDINATE INCREMENT (NBG1, HORIZONTAL INTEGER PART)ZMXIN1
180088H

14
~
6
~

13
~
5
~

Co

15
~
7
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N1ZMXI2 N1ZMXI1 N1ZMXI0• COORDINATE INCREMENT (NBG1, HORIZONTAL FRACTIONAL PART)
15
14
13
12
11
10
9
8
N1ZMXD1 N1ZMXD2 N1ZMXD3 N1ZMXD4 N1ZMXD5 N1ZMXD6 N1ZMXD7 N1ZMXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

GA

ZMXDN1
18008AH• COORDINATE INCREMENT (NBG1, VERTICAL INTEGER PART)
15
~
7
~

ZMYIN1
18008CH

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N1ZMYI2 N1ZMYI1 N1ZMYI0• COORDINATE INCREMENT (NBG1, VERTICAL FRACTIONAL PART)
15
14
13
12
11
10
9
8
N1ZMYD1 N1ZMYD2 N1ZMYD3 N1ZMYD4 N1ZMYD5 N1ZMYD6 N1ZMYD7 N1ZMYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SE
ZMYDN1
18008EH

ST-58-R2

305

• SCREEN SCROLL VALUE (NBG2, HORIZONTAL)
15~7
N2SCX714~
6
N2SCX613~
5
N2SCX512~
4N2SCX411~
3
N2SCX310
N2SCX102
N2SCX29
N2SCX91
N2SCX18N2SCX80N2SCX011~
3
N2SCY310
N2SCY102
N2SCY29N2SCY91
N2SCY18N2SCY80N2SCY0• SCREEN SCROLL VALUE (NBG2, VERTICAL)SCYN2180092H

15~
7
N2SCY714~
6N2SCY613~
5N2SCY512~4N2SCY4SCXN3180094H

15~
7
N3SCX714~
6
N3SCX68
N3SCX80N3SCX013~5N3SCY512~4N3SCY4de• SCREEN SCROLL VALUE (NBG3, HORIZONTAL)

11~3
N3SCY310
N3SCY102
N3SCY29N3SCY91
N3SCY18
N3SCY80N3SCY0

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
~

9
N1ZMQT
1
N0ZMQT

8
N1ZMHF
0N0ZMHF

9
N1LSCX
1
N0LSCX

8
N1VCSC0
N0VCSC

13~
5
N3SCX512~
4
N3SCX4SCYN3180096H

14~
6N3SCY6

ZMCTL
180098H

15
~
7
~

14
~
6
~

10
N3SCX10
2
N3SCX29N3SCX91
N3SCX1

Co• REDUCTION ENABLE

11~
3
N3SCX3nfi• SCREEN SCROLL VALUE (NBG3, VERTICAL)
15~7N3SCY7

nti
al

SCXN2
180090H• LINE AND VERTICAL CELL SCROLL CONTROL (NBGO, NBG1)
15
~
7
~

14
~
6
~

13
N1LSS1
5
N0LSS1GASCRCTL
18009AH

12
N1LSS04
N0LSS011
N1LZMX
3
N0LZMX

10
N1LSCY
2
N0LSCY• VERTICAL CELL SCROLL TABLE ADDRESS (NBGO, NBG1)VCSTAU
18009CH

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
VCSTA18 VCSTA17 VCSTA16• VERTICAL CELL SCROLL TABLE ADDRESS (NBGO, NBG1)
15
14
13
12
11
10
VCSTA15 VCSTA14 VCSTA13 VCSTA12 VCSTA11 VCSTA10
7
6
5
4
3
2
VCSTA7 VCSTA6 VCSTA5 VCSTA4 VCSTA3 VCSTA2SEVCSTAL
18009EH

306

9
VCSTA91
VCSTA1

8
VCSTA80~• LINE SCROLL TABLE ADDRESS (NBGO)
14
~
6
~

13
~
5
~

12
~
4
~

• LINE SCROLL TABLE ADDRESS (NBGO)
15
LSTA0L
1800A2H

14

13

12

11
~
3
~

10
~
2

7

6

5

4

N0LSTA6

N0LSTA5N0LSTA4

11

10

15
~
7
~

LSTA1U
1800A4H

14
~
6
~

13
~
5
~

12
~
4
~

9

8

N0LSTA9N0LSTA83

2

1

N0LSTA3

N0LSTA2

N0LSTA1

0
~

9
~
1

8
~
0

de

• LINE SCROLL TABLE ADDRESS (NBG1)8~0N0LSTA18 N0LSTA17 N0LSTA16

N0LSTA15 N0LSTA14 N0LSTA13 N0LSTA12 N0LSTA11 N0LSTA10
N0LSTA7

9
~
1

nti
al

15
~
7
~

LSTA0U
1800A0H

11
~
3
~

10
~
2

N1LSTA18 N1LSTA17 N1LSTA16• LINE SCROLL TABLE ADDRESS (NBG1)
LSTA1L
1800A6H

14

13

12

11

nfi

15

10

N1LSTA15 N1LSTA14 N1LSTA13 N1LSTA12 N1LSTA11 N1LSTA1076N1LSTA7

N1LSTA698

N1LSTA9N1LSTA8

5

4

3

2

1

N1LSTA5N1LSTA4

N1LSTA3

N1LSTA2

N1LSTA1

0
~

11
~
3
~

10
~
2
LCTA189~1
LCTA17

8~
0
LCTA16

12
LCTA12
4LCTA4

11LCTA11
3LCTA3

10LCTA10
2
LCTA2

9
LCTA9
1
LCTA1

8
LCTA8
0
LCTA0

12
~
4
~

11
~
3
~

10
~
2
BKTA189~1
BKTA178~0
BKTA16

12
BKTA12
4BKTA4

11
BKTA11
3
BKTA3

10
BKTA10
2
BKTA2

9
BKTA9
1
BKTA1

8
BKTA8
0
BKTA0

• LINE COLOR SCREEN TABLE ADDRESS
15
LCCLMD
7
~

14
~
6
~

13
~
5
~

Co

LCTAU
1800A8H

12~
4~• LINE COLOR SCREEN TABLE ADDRESS
15
LCTA157LCTA714LCTA14
6
LCTA6

GA

LCTAL
1800AAH

13
LCTA135LCTA5• BACK SCREEN TABLE ADDRESSBKTAU
1800ACH

15
BKCLMD
7
~

14
~
6
~

13
~
5
~

• BACK SCREEN TABLE ADDRESS
15
BKTA15
7
BKTA7

SE
BKTAL
1800AEH

ST-58-R2

14
BKTA146BKTA613
BKTA13
5
BKTA5

307

• ROTATION PARAMETER MODE
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

• ROTATION PARAMETER READ CONTROLRPRCTL
1800B2H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

12
RBKLCE
4RAKLCE

11
RBKMD1
3
RAKMD1KTCTL
1800B4H

15
~
7
~

14
~
6
~

13
~
5
~

9
~
1
RPMD1

10

9

RBKASTRE RBYSTRE

8
~
0
RPMD0

2

8

RBXSTRE

1

0

RAKASTRE RAYSTRERAXSTRE

10
RBKMD02
RAKMD0

8
RBKTE
0
RAKTE

9
RBKDBS1RAKDBSde• COEFFICIENT TABLE CONTROL

10
~
2
~

nti
al

RPMD
1800B0H• COEFFICIENT TABLE ADDRESS OFFSET (ROTATION PARAMETER A, B)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10

nfi

KTAOF
1800B6H

9

8

RBKTAOS2 RBKTAOS1 RBKTAOS0

2

1

0

RAKTAOS2 RAKTAOS1 RAKTAOS0• SCREEN OVER PATTERN NAME (ROTATION PARAMETER A)
15
14
13
12
11
10
9
RAOPN15 RAOPN14 RAOPN13 RAOPN12 RAOPN11 RAOPN10 RAOPN9
7
6
5
4
3
2
1
RAOPN7 RAOPN6 RAOPN5 RAOPN4 RAOPN3 RAOPN2 RAOPN1CoOVPNRA
1800B8H

8RAOPN80
RAOPN0• SCREEN OVER PATTERN NAME (ROTATION PARAMETER B)
15
14
13
12
11
10
9
RBOPN15 RBOPN14 RBOPN13 RBOPN12 RBOPN11 RBOPN10 RBOPN9
7
6
5
4
3
2
1
RBOPN7 RBOPN6 RBOPN5 RBOPN4 RBOPN3 RBOPN2 RBOPN1GAOVPNRB
1800BAH

8
RBOPN80
RBOPN0• ROTATION PARAMETER TABLE ADDRESS (ROTATION PARAMETER A,B)
RPTAU
1800BCH

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
RPTA189~1
RPTA178~
0
RPTA16• ROTATION PARAMETER TABLE ADDRESS (ROTATION PARAMETER A, B)
14
RPTA14
6
RPTA6

SE

15
RPTA15
7
RPTA7

RPTAL
1800BEH

308

13
RPTA13
5
RPTA5

12
RPTA12
4
RPTA4

11
RPTA11
3
RPTA3

10
RPTA10
2
RPTA2

9
RPTA9
1
RPTA1

8
RPTA8
0
~

• WINDOW POSITION (W0, HORIZONTAL START POINT)
15
~
7
W0SX7

14
~
6
W0SX6

13
~
5
W0SX5

12
~
4
W0SX4

11
~
3
W0SX3

10
~
2
W0SX2

9
W0SX9
1
W0SX1

8
W0SX8
0
W0SX0

10
~
2
W0SY2

9
~
1
W0SY1

8
W0SY8
0
W0SY0

10
~
2
W0EX2

9
W0EX9
1
W0EX1

8
W0EX8
0
W0EX0

10
~
2
W0EY2

9
~
1
W0EY1

8
W0EY8
0
W0EY0

10
~
2
W1SX2

9
W1SX9
1
W1SX1

8
W1SX8
0
W1SX0

10
~
2
W1SY2

9
~
1
W1SY1

8
W1SY8
0
W1SY0

10
~
2
W1EX2

9
W1EX9
1
W1EX1

8
W1EX8
0
W1EX0

10
~
2
W1EY2

9
~
1
W1EY1

8
W1EY8
0
W1EY0

nti
al

WPSX0
1800C0H• WINDOW POSITION (W0, VERTICAL START POINT)WPSY01800C2H

15
~
7
W0SY7

14
~
6
W0SY6

13
~
5
W0SY5

12
~
4
W0SY4

11
~
3
W0SY3

• WINDOW POSITION (W0, HORIZONTAL END POINT)
14
~
6
W0EX6

13
~
5
W0EX5

12
~
4
W0EX4

11
~
3
W0EX3

de

WPEX0
1800C4H

15
~
7
W0EX7

• WINDOW POSITION (W0, VERTICAL END POINT)
15
~
7
W0EY7

14
~
6
W0EY6

13
~
5
W0EY5

12
~
4
W0EY4

11
~
3
W0EY3

nfi

WPEY0
1800C6H• WINDOW POSITION (W1, HORIZONTAL START POINT)
15
~
7
W1SX7

14
~
6
W1SX6

13
~
5
W1SX5

12
~
4
W1SX4

Co

WPSX1
1800C8H

11
~
3
W1SX3

• WINDOW POSITION (W1, VERTICAL START POINT)
15
~
7
W1SY7

14
~
6
W1SY6

GA

WPSY1
1800CAH

13
~
5
W1SY5

12
~
4
W1SY4

11
~
3
W1SY3

• WINDOW POSITION (W1, HORIZONTAL END POINT)WPEX11800CCH

15
~
7
W1EX7

14
~
6
W1EX6

13
~
5
W1EX5

12
~
4
W1EX4

11
~
3
W1EX3

• WINDOW POSITION (W1, VERTICAL END POINT)

SE

15
~
7
W1EY7

WPEY1
1800CEH

ST-58-R2

14
~
6
W1EY6

13
~
5
W1EY5

12
~
4
W1EY4

11
~
3
W1EY3

309

• WINDOW CONTROL (NBG0, NBG1)
15
N1LOG
7
N0LOG

14
~
6
~

13
N1SWE
5
N0SWE

12
N1SWA
4
N0SWA

11
N1W1E
3
N0W1E

10
N1W1A
2
N0W1A

9
N1W0E
1
N0W0E

8
N1W0A
0
N0W0A

12
N3SWA
4
N2SWA

11
N3W1E
3
N2W1E

10
N3W1A
2
N2W1A

9
N3W0E
1
N2W0E

8
N3W0A
0
N2W0A

12
SPSWA
4
R0SWA

11
SPW1E
3
R0W1E

WCTLB
1800D2H

15
N3LOG
7
N2LOG

14
~
6
~

13
N3SWE
5
N2SWE

• WINDOW CONTROL (RBG0, SPRITE)
WCTLC
1800D4H

15
SPLOG
7
R0LOG

14
~
6
~

13
SPSWE
5
R0SWE

de

• WINDOW CONTROL (NBG2, NBG3)

nti
al

WCTLA
1800D0H

10
SPW1A
2
R0W1A

9
SPW0E
1
R0W0E

8
SPW0A
0
R0W0A

• WINDOW CONTROL (PARAMETER WINDOW, COLOR CALC. WINDOW)
14
~
6
~

13
CCSWE
5
~

12
CCSWA
4
~

• LINE WINDOW TABLE ADDRESS (W0)
15
W0LWE
7
~

14
~
6
~

13
~
5
~

10
CCW1A
2
RPW1A

9
CCW0E
1
RPW0E

8
CCW0A
0
RPW0A

12
~
4
~

11
~
3
~

10
~
2

9
~
1

8
~
0

W0LWTA18

W0LWTA17W0LWTA16

Co

LWTA0U
1800D8H

11
CCW1E
3
RPW1E

nfi

WCTLD
1800D6H

15
CCLOG
7
RPLOG

• LINE WINDOW TABLE ADDRESS (W0)
LWTA0L
1800DAH

15

14

W0LWTA15W0LWTA14

7

6

13

12

11

10

9

8

W0LWTA13W0LWTA12W0LWTA11W0LWTA10W0LWTA9W0LWTA8

5

4

3

2

1

0

GA

W0LWTA7 W0LWTA6 W0LWTA5 W0LWTA4 W0LWTA3 W0LWTA2 W0LWTA1~• LINE WINDOW TABLE ADDRESS (W1)15

LWTA1U
1800DCH

14
~
6
~

W1LWE

7
~

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2

9
~
1

8
~
0

W1LWTA18W1LWTA17W1LWTA16• LINE WINDOW TABLE ADDRESS (W1)
15

14

13

12

11

10

9

8

W1LWTA15W1LWTA14W1LWTA13W1LWTA12W1LWTA11W1LWTA10W1LWTA9W1LWTA8

7

6

5

4

3

2

1

0

SE

LWTA1L
1800DEH

W1LWTA7 W1LWTA6 W1LWTA5 W1LWTA4 W1LWTA3 W1LWTA2 W1LWTA1

310~

• SPRITE CONTROL
SPCTL
1800E0H

14
~
6
~

13
12
11
10
9
8
SPCCCS1 SPCCCS0~SPCCN2 SPCCN1 SPCCN0
5
4
3
2
1
0
SPCLMD SPWINEN SPTYPE3 SPTYPE2 SPTYPE1 SPTYPE0• SHADOW CONTROL
15
~
7
~

SDCTL
1800E2H

14
~
6
~

13
~
5
BKSDEN

12~
4
R0SDEN

11~
3
N3SDEN

15
~
7
~

10
~
2
N2SDEN

9~
1
N1SDEN8TPSDSL0
N0SDENde• COLOR RAM ADDRESS OFFSET (NBG0~NBG3)CRAOFA
1800E4H

nti
al

15
~
7
~

14
13
12
N3CAOS2 N3CAOS1 N3CAOS0
6
5
4
N1CAOS2 N1CAOS1 N1CAOS0

11
~
3
~

10
9
8
N2CAOS2 N2CAOS1 N2CAOS0
2
1
0
N0CAOS2 N0CAOS1 N0CAOS0• COLOR RAM ADDRESS OFFSET (RBG0, SPRITE)
14
13
12
~
~
~
6
5
4
SPCAOS2 SPCAOS1 SPCAOS0

11
~
3
~

nfi

15
~
7
~

CRAOFB
1800E6H

10
9
8
~
~
~
2
1
0
R0CAOS2 R0CAOS1 R0CAOS0• LINE COLOR SCREEN ENABLE
14
~
6
~

13
~
5
SPLCEN

12~
4
R0LCEN

Co

15
~
7
~

LNCLEN
1800E8H

11~
3
N3LCEN

10~
2
N2LCEN

9~
1
N1LCEN

8~
0
N0LCEN• SPECIAL PRIORITY MODE

15
14
13
12
11
10
9
8
~
~
~
~
~
~
R0SPRM1 R0SPRM0
7
6
5
4
3
2
1
0
N3SPRM1 N3SPRM0 N2SPRM1 N2SPRM0 N1SPRM1 N1SPRM0 N0SPRM1 N0SPRM0GA

SFPRMD
1800EAH• COLOR CALCULATION CONTROL
CCCTL
1800ECH

15
BOKEN
7
~

14
BOKN2
6
SPCCEN

13BOKN1
5LCCCEN

12
BOKN0
4R0CCEN

11~3
N3CCEN

10EXCCEN
2
N2CCEN

9CCRTMD
1
N1CCEN

8CCMD
0N0CCEN• SPECIAL COLOR CALCULATION MODE

SE

15
14
13
12
11
10
9
8
~
~
~
~
~
~
R0SCCM1 R0SCCM0
7
6
5
4
3
2
1
0
N3SCCM1 N3SCCM0 N2SCCM1 N2SCCM0 N1SCCM1 N1SCCM0 N0SCCM1 N0SCCM0

SFCCMD
1800EEH

ST-58-R2

311

• PRIORITY NUMBER (SPRITE 0,1)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
S1PRIN2
2
S0PRIN29S1PRIN1
1
S0PRIN18
S1PRIN00
S0PRIN0

12
~
4
~

11
~
3
~

10
S3PRIN22
S2PRIN29S3PRIN1
1
S2PRIN18
S3PRIN00
S2PRIN0

12~4~• PRIORITY NUMBER (SPRITE 2,3)
PRISB
1800F2H

15
~
7
~

14
~
6
~

13
~
5
~

14
~
6
~

13
~
5
~

de

PRISC
1800F4H

15
~
7
~

11
~
3
~

10
S5PRIN2
2
S4PRIN29S5PRIN1
1
S4PRIN18
S5PRIN00
S4PRIN0

nfi• PRIORITY NUMBER (SPRITE 4,5)

11
~
3
~

10
S7PRIN2
2
S6PRIN29S7PRIN1
1
S6PRIN18
S7PRIN00S6PRIN0

12
~
4
~

11
~
3
~

10
N1PRIN2
2
N0PRIN29
N1PRIN1
1
N0PRIN18
N1PRIN00
N0PRIN0

12
~
4
~

11
~
3
~

10
N3PRIN2
2
N2PRIN29
N3PRIN1
1
N2PRIN18
N3PRIN00
N2PRIN0• PRIORITY NUMBER (SPRITE 6,7)
PRISD
1800F6H

15
~
7
~

14
~
6
~

13
~
5
~

• PRIORITY NUMBER (NBG0, NBG1)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

Co

PRINA
1800F8H

nti
al

PRISA
1800F0H• PRIORITY NUMBER (NBG2, NBG3)
15
~
7
~

14
~
6
~

13
~
5
~

GA

PRINB
1800FAH• PRIORITY NUMBER (RBG0)PRIR
1800FCH

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
R0PRIN2

9~
1
R0PRIN1

8~
0
R0PRIN0

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
~

9
~
1
~

8
~
0
~

SE

• RESERVE

15
~
7
~

1800FEH

312• COLOR CALCULATION RATIO (SPRITE 0,1)
15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
S1CCRT4 S1CCRT3 S1CCRT2 S1CCRT1 S1CCRT0
4
3
2
1
0
S0CCRT4 S0CCRT3 S0CCRT2 S0CCRT1 S0CCRT0• COLOR CALCULATION RATIO (SPRITE 2,3)
CCRSB
180102H

15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
S3CCRT4 S3CCRT3 S3CCRT2 S3CCRT1 S3CCRT0
4
3
2
1
0
S2CCRT4 S2CCRT3 S2CCRT2 S2CCRT1 S2CCRT0

CCRSC
180104H

14
~
6
~

13
~
5
~

de

• COLOR CALCULATION RATIO (SPRITE 4,5)
15
~
7
~

nti
al

CCRSA
180100H

12
11
10
9
8
S5CCRT4 S5CCRT3 S5CCRT2 S5CCRT1 S5CCRT0
4
3
2
1
0
S4CCRT4 S4CCRT3 S4CCRT2 S4CCRT1 S4CCRT0• COLOR CALCULATION RATIO (SPRITE 6,7)
14
~
6
~

13
~
5
~

12
11
10
9
8
S7CCRT4 S7CCRT3 S7CCRT2 S7CCRT1 S7CCRT0
4
3
2
1
0
S6CCRT4 S6CCRT3 S6CCRT2 S6CCRT1 S6CCRT0

nfi

CCRSD
180106H

15~
7~• COLOR CALCULATION RATIO (NBG0, NBG1)
15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
N1CCRT4 N1CCRT3 N1CCRT2 N1CCRT1 N1CCRT0
4
3
2
1
0
N0CCRT4 N0CCRT3 N0CCRT2 N0CCRT1 N0CCRT0

Co

CCRNA
180108H

14
~
6
~

13
~
5
~

GA

• COLOR CALCULATION RATIO (NBG2, NBG3)

13
~
5
~

CCRNB
18010AH

15
~
7
~

12
11
10
9
8
N3CCRT4 N3CCRT3 N3CCRT2 N3CCRT1 N3CCRT0
4
3
2
1
0
N2CCRT4 N2CCRT3 N2CCRT2 N2CCRT1 N2CCRT0• COLOR CALCULATION RATIO (RBG0)
CCRR
18010CH

15
~
7
~

14
~
6
~

12
11
10
9
8
~
~
~
~
~
4
3
2
1
0
R0CCRT4 R0CCRT3 R0CCRT2 R0CCRT1 R0CCRT0

SE• COLOR CALCULATION RATIO (LINE COLOR SCREEN, BACK SCREEN)
CCRLB
18010EH

ST-58-R2

15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
BKCCRT4 BKCCRT3 BKCCRT2 BKCCRT1 BKCCRT0
4
3
2
1
0
LCCCRT4 LCCCRT3 LCCCRT2 LCCCRT1 LCCCRT0313

• COLOR OFFSET ENABLE
14~6SPCOEN

13~
5
BKCOEN

12~
4
R0COEN

11~
3
N3COEN

10~
2
N2COEN

9~
1
N1COEN

8~0
N0COEN

13~
5
BKCOSL

12~
4
R0COSL

11~
3
N3COSL

10~
2
N2COSL

9~
1
N1COSL

8~0
N0COSL

13~
5COARD5

12~
4
COARD4

11~
3
COARD3

10~
2
COARD2

9~
1
COARD1

8
COARD80
COARD013~5COAGR512~
4COAGR411~
3COAGR310~
2COAGR29~1COAGR18COAGR80
COAGR013~5COABL512~
4COABL411~
3
COABL310~
2COABL29~
1
COABL18COABL80
COABL013~
5COBRD512~
4COBRD4

11~
3COBRD310~
2COBRD2

9~
1
COBRD18COBRD80
COBRD013~
5COBGR512~
4COBGR4

11~
3COBGR310~
2COBGR2

9~
1COBGR18
COBGR80
COBGR013~
5COBBL512~
4COBBL4

11~
3
COBBL310~
2COBBL2

9~
1COBBL1

8COBBL80
COBBL0

CLOFSL
180112H

15
~
7
~

14
~
6
SPCOSL• COLOR OFFSET A (RED)
COAR
180114H

15~
7COARD7

14~
6
COARD6

COAG
180116H

15~
7COAGR714~
6COAGR6

COAB
180118H

15~
7COABL714~
6COABL6• COLOR OFFSET B (RED)15~
7
COBRD714~
6COBRD6GA

COBR
18011AH

Co• COLOR OFFSET A (BLUE)

nfi• COLOR OFFSET A (GREEN)de• COLOR OFFSET SELECTntial

CLOFEN
180110H

15~
7~• COLOR OFFSET B (GREEN)
COBG
18011CH

15~7COBGR714~
6COBGR6• COLOR OFFSET B (BLUE)
14~
6
COBBL6SE

15~
7COBBL7COBB
18011EH

314

Bit
Abbreviation

Bit

180000H
180000H
180000H
180000H
180000H

15
8
7,6
5,4
2~0

180002H
180002H
180002H
180002H

9810180004H
180004H
180004H
180004H
180004H
180004H

9
8
3
2
1
0

180006H
180006H

15
3~0180008H

9~018000AH

9~018000EH
18000EH
18000EH
18000EH
18000EH
18000EH
18000EH

13,12
8
9
1,0
3,2
5,4
7,6

Application

For VRAM-A
For VRAM-B
For VRAM-A0 (or VRAM-A)
For VRAM-A1
For VRAM-B0 (or VRAM-B)
For VRAM-B1

SE

GA

Co

nfi

• TV Screen ModeTV Screen Display
DISP
Boarder Color Mode
BDCLMDInterlace Mode
LSMD
Vertical Definition
VRESO
Horizontal Definition
HRESO• External Signal Enable
External Latch Enable
EXLTEN
External Sync Enable
EXSYEN
Image Display Area Select
DASEL
External Screen Enable
EXBGEN• Screen Status (Read Only)
External Latch Flag
EXLTFG
External Sync Flag
EXSYFG
V Blank Flag
VBLANK
H Blank Flag
HBLANK
Scan Field FlagODDTV System FlagPAL
• VRAM Size (Version Number is Read Only)
VRAM SizeVRAMSZ
Version Number
VER• H-Counter (Read Only)
H Counter ValueHCT• V-Counter (Read Only)
V Counter Value
VCT• RAM Control
Color RAM Mode
CRMD
VRAM Mode
VRAMD
VRAM Mode
VRBMD
Rotation Data Bank Selection RDBSA0
Rotation Data Bank Selection RDBSA1
Rotation Data Bank Selection RDBSB0
Rotation Data Bank Selection RDBSB1

Addressde

Bit Namential16.2 Register Bit List

ST-58-R2

315

Address

Bit• VRAM Cycle Pattern
VRAM Cycle Pattern

VCPA0

VRAM Cycle Pattern

VCPA1

VRAM Cycle Pattern

VCPB0

VRAM Cycle Pattern

VCPB1

180010H
180012H
180014H
180016H
180018H
18001AH
18001CH
18001EH

15~0
15~0
15~0
15~0
15~0
15~0
15~0
15~0

For VRAM-A0
For VRAM-A0
For VRAM-A1
For VRAM-A1
For VRAM-B0
For VRAM-B0
For VRAM-B1
For VRAM-B1

180020H
180020H
180020H
180020H
180020H
180020H
180020H
180020H
180020H
180020H
180020H

8
9
10
11
12
0
1
2
3
4
5

For NBG0 (or RBG0)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For NBG0
For NBG1
For NBG2
For NBG3
For RBG0
For RBG1

180022H
180022H
180022H
180022H
180022H
180022H
180022H

0
1
2
3
4
11~8
15~12

180024H
180024H
180024H
180024H
180024H

012
34180026H
180026H

7~0
15~8

SE

GA

de

Co

• Screen Display Enable
Transparent Display Enable
N0TPON
Transparent Display Enable
N1TPON
Transparent Display Enable
N2TPON
Transparent Display Enable
N3TPON
Transparent Display Enable
R0TPON
Screen Display Enable
N0ON
Screen Display Enable
N1ON
Screen Display Enable
N2ON
Screen Display Enable
N3ON
Screen Display Enable
R0ON
Screen Display Enable
R1ON• Mosaic Control
Mosaic Enable
N0MZE
Mosaic Enable
N1MZE
Mosaic Enable
N2MZE
Mosaic Enable
N3MZE
Mosaic Enable
R0MZE
Mosaic Size
MZSZH
Mosaic SizeMZSZV• Special Function Code SelectSpecial Function Code Select N0SFCS
Special Function Code Select N1SFCS
Special Function Code Select N2SFCS
Special Function Code Select N3SFCS
Special Function Code Select R0SFCS• Special Function CodeSpecial Function
SFCDA
Special Function
SFCDB

316

Application

nti
al

Bit
Abbreviation

nfi

Bit Name

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0
For Horizontal Mosaic Size
For Vertical Mosaic Size
For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0
For Special Function Code A
For Special Function Code B

Special Color Calculation (for Bitmap)
Special Color Calculation (for Bitmap)
Special Color Calculation (for Bitmap)

Application

N0CHSZN1CHSZN2CHSZN3CHSZR0CHSZN0BMEN
N1BMEN
R0BMEN
N0BMSZN1BMSZR0BMSZ
N0CHCNN1CHCNN2CHCN
N3CHCNR0CHCN

180028H
180028H
18002AH
18002AH
18002AH
180028H
180028H
18002AH
180028H
180028H
18002AH
180028H
180028H
18002AH
18002AH
18002AH

0
8
0
4
8
1
9
9
3,2
11,10
10
6~4
13,12
1
5
14,12

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0
For NBG0
For NBG1
For RBG0
For NBG0
For NBG1
For RBG0
For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0

N0BMPR
N1BMPR
R0BMPR
N0BMCCN1BMCCR0BMCC
N0BMP
N1BMP
R0BMP

18002CH
18002CH
18002EH
18002CH
18002CH
18002EH
18002CH
18002CH
18002EH

5
13
5
4
12
4
2~0
10~8
2~0

For NBG0
For NBG1
For RBG0
For NBG0
For NBG1
For RBG0
For NBG0
For NBG1
For RBG0

N0PNB
N1PNB
N2PNB
N3PNB
R0PNB
N0CNSM

180030H
180032H
180034H
180036H
180038H
180030H

15
15
15
15
15
14

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0
For NBG0 (or RBG1)

N1CNSM

180032H

14For NBG1

N2CNSM

180034H

14For NBG2

N3CNSM

180036H

14

For NBG3

R0CNSM

180038H

14For RBG0

nti
al

Bit

SE

GA

Co

Palette Number (for Bitmap)
Palette Number (for Bitmap)
Palette Number (for Bitmap)• Pattern Name Control
Pattern Name Data Size
Pattern Name Data Size
Pattern Name Data Size
Pattern Name Data Size
Pattern Name Data Size
Character Number
Supplement Mode
Character Number
Supplement Mode
Character Number
Supplement Mode
Character Number
Supplement Mode
Character Number
Supplement Mode

Addressde• Character Control
Character Size
Character Size
Character Size
Character Size
Character Size
Bitmap Enable
Bitmap Enable
Bitmap Enable
Bitmap Size
Bitmap Size
Bitmap Size
Number of Character Colors
Number of Character Colors
Number of Character Colors
Number of Character Colors
Number of Character Colors• Bitmap Palette Number
Special Priority (for Bitmap)
Special Priority (for Bitmap)
Special Priority (for Bitmap)

Bit
Abbreviation

nfi

Bit Name

ST-58-R2

317

For NBG0 (or RBG1)

180032H

9For NBG1

180034H

9For NBG2

180036H

9For NBG3

180038H

9For RBG0

180030H

8

For NBG0 (or RBG1)

180032H

8For NBG1

180034H

8180036H

8180038H

8180030H
180032H
180034H
180036H
180038H
180030H
180032H
180034H
180036H
180038H

7~5
7~5
7~5
7~5
7~5
4~0
4~0
4~0
4~0
4~0

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0
For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0

18003AH
18003AH
18003AH
18003AH
18003AH
18003AH
18003AH
18003AH

1,0
3,2
5,4
7,6
9,8
13,12
11,10
15,14

For NBG0
For NBG1
For NBG2
For NBG3
For Rotation Parameter A
For Rotation Parameter B
For Rotation Parameter A
For Rotation Parameter B

18003CH
18003CH
18003CH
18003CH
18003EH
18003EH

2~0
6~4
10~8
14~12
2~0
6~4

For NBG0
For NBG1
For NBG2
For NBG3
For Rotation Parameter A
For Rotation Parameter B

de

nti
al

9

SE

GA

Co

Special Priority (For Pattern
N1SPR
Name Supplement Data)
Special Priority (For Pattern
N2SPR
Name Supplement Data)
Special Priority (For Pattern
N3SPR
Name Supplement Data)
Special Priority (For Pattern
R0SPR
Name Supplement Data)
Special Color Calculation
N0SCC(For Pattern Name
Supplement Data)
Special Color Calculation
N1SCC(For Pattern Name Supplement
Data)
Special Color Calculation
N2SCC(For Pattern Name Supplement
Data)
Special Color Calculation
N3SCC(For Pattern Name Supplement
Data)
Special Color Calculation
R0SCC(For Pattern Name Supplement
Data)
Supplement Palette Number
N0SPLT
Supplement Palette Number
N1SPLT
Supplement Palette Number
N2SPLT
Supplement Palette Number
N3SPLT
Supplement Palette Number
R0SPLT
Supplement Character Number N0SCN
Supplement Character Number N1SCN
Supplement Character Number N2SCN
Supplement Character Number N3SCN
Supplement Character Number R0SCN• Plane Size
Plane Size
N0PLSZ
Plane Size
N1PLSZ
Plane Size
N2PLSZ
Plane Size
N3PLSZ
Plane Size
RAPLSZ
Plane Size
RBPLSZ
Screen Over Processing
RAOVR
Screen Over Processing
RBOVR• Map Offset
Map Offset
N0MP
Map Offset
N1MP
Map Offset
N2MP
Map Offset
N3MP
Map Offset
RAMP
Map Offset
RBMP

180030H

318

For NBG2
For NBG3
For RBG0

nfi• Pattern Name Control (Continued)
Special Priority (For Pattern
N0SPR
Name Supplement Data)

Bit

N0MPA
N0MPB
N0MPC
N0MPD
N1MPA
N1MPB
N1MPC
N1MPD
N2MPA
N2MPB
N2MPC
N2MPD
N3MPA
N3MPB
N3MPC
N3MPD
RAMPA
RAMPB
RAMPC
RAMPD
RAMPE
RAMPF
RAMPG
RAMPH
RAMPI
RAMPJ
RAMPK
RAMPL
RAMPM
RAMPN
RAMPO
RAMPP
RBMPA
RBMPB
RBMPC
RBMPD
RBMPE
RBMPF
RBMPG
RBMPH
RBMPI
RBMPJ

180040H
180040H
180042H
180042H
180044H
180044H
180046H
180046H
180048H
180048H
18004AH
18004AH
18004CH
18004CH
18004EH
18004EH
180050H
180050H
180052H
180052H
180054H
180054H
180056H
180056H
180058H
180058H
18005AH
18005AH
18005CH
18005CH
18005EH
18005EH
180060H
180060H
180062H
180062H
180064H
180064H
180066H
180066H
180068H
180068H

5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8
5~0
13~8

de

For NBG0 Plane A
For NBG0 Plane B
For NBG0 Plane C
For NBG0 Plane D
For NBG1 Plane A
For NBG1 Plane B
For NBG1 Plane C
For NBG1 Plane D
For NBG2 Plane A
For NBG2 Plane B
For NBG2 Plane C
For NBG2 Plane D
For NBG3 Plane A
For NBG3 Plane B
For NBG3 Plane C
For NBG3 Plane D
Rotation Parameter-A Screen Plane-A
Rotation Parameter-A Screen Plane-B
Rotation Parameter-A Screen Plane-C
Rotation Parameter-A Screen Plane-D
Rotation Parameter-A Screen Plane-E
Rotation Parameter-A Screen Plane-F
Rotation Parameter-A Screen Plane-G
Rotation Parameter-A Screen Plane-H
Rotation Parameter-A Screen Plane-I
Rotation Parameter-A Screen Plane-J
Rotation Parameter-A Screen Plane-K
Rotation Parameter-A Screen Plane-L
Rotation Parameter-A Screen Plane-M
Rotation Parameter-A Screen Plane-N
Rotation Parameter-A Screen Plane-O
Rotation Parameter-A Screen Plane-P
Rotation Parameter-B Screen Plane-A
Rotation Parameter-B Screen Plane-B
Rotation Parameter-B Screen Plane-C
Rotation Parameter-B Screen Plane-D
Rotation Parameter-B Screen Plane-E
Rotation Parameter-B Screen Plane-F
Rotation Parameter-B Screen Plane-G
Rotation Parameter-B Screen Plane-H
Rotation Parameter-B Screen Plane-I
Rotation Parameter-B Screen Plane-J

SEGA

ApplicationntialAddressCo• Map
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Normal Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)
Map (For Rotation Scroll)Bit
Abbreviation

nfi

Bit Name

ST-58-R2

319

Application

18006AH
18006AH
18006CH
18006CH
18006EH
18006EH

5~0
13~8
5~0
13~8
5~0
13~8

Rotation Parameter-B Screen Plane-K
Rotation Parameter-B Screen Plane-L
Rotation Parameter-B Screen Plane-M
Rotation Parameter-B Screen Plane-N
Rotation Parameter-B Screen Plane-O
Rotation Parameter-B Screen Plane-P

180070H
180072H
180074H
180076H
180080H
180082H
180084H
180086H
180090H
180092H
180094H
180096H

10~0
15~8
10~0
15~8
10~0
15~8
10~0
15~8
10~0
10~0
10~0
10~0

For NBG0 Horizontal (Integer Part)
For NBG0 Horizontal (Fractional Part)
For NBG0 Vertical (Integer Part)
For NBG0 Vertical (Fractional Part)
For NBG1 Horizontal (Integer Part)
For NBG1 Horizontal (Fractional Part)
For NBG1 Vertical (Integer Part)
For NBG1 Vertical (Fractional Part)
For NBG2 Horizontal
For NBG2 Vertical
For NBG3 Horizontal
For NBG3 Vertical

180078H
18007AH
18007CH
18007EH
180088H
18008AH
18008CH
18008EH

2~0
15~8
2~0
15~8
2~0
15~8
2~0
15~8

For NBG0 Horizontal (Integer Part)
For NBG0 Horizontal (Fractional Part)
For NBG0 Vertical (Integer Part)
For NBG0 Vertical (Fractional Part)
For NBG1 Horizontal (Integer Part)
For NBG1 Horizontal (Fractional Part)
For NBG1 Vertical (Integer Part)
For NBG1 Vertical (Fractional Part)

180098H
180098H
180098H
180098H

01
89For NBG0
For NBG0
For NBG1
For NBG1

18009AH
18009AH
18009AH

08
1

For NBG0
For NBG1
For NBG0

18009AH

9

For NBG1

18009AH

2

For NBG0

GA

SE
320

nti
al

Bit

Co

• Map (Continued)
Map (For Rotation Scroll)
RBMPK
Map (For Rotation Scroll)
RBMPL
Map (For Rotation Scroll)
RBMPM
Map (For Rotation Scroll)
RBMPN
Map (For Rotation Scroll)
RBMPO
Map (For Rotation Scroll)
RBMPP• Screen Scroll Value
Screen Scroll ValueN0SCXI
Screen Scroll ValueN0SCXD
Screen Scroll ValueN0SCYI
Screen Scroll ValueN0SCYD
Screen Scroll ValueN1SCXI
Screen Scroll ValueN1SCXD
Screen Scroll ValueN1SCYI
Screen Scroll ValueN1SCYD
Screen Scroll Value
N2SCX
Screen Scroll Value
N2SCX
Screen Scroll Value
N3SCY
Screen Scroll Value
N3SCY• Coordinate Increment
Coordinate Increment
N0ZMXI
Coordinate Increment
N0ZMXD
Coordinate Increment
N0ZMYI
Coordinate Increment
N0ZMYD
Coordinate Increment
N1ZMXI
Coordinate Increment
N1ZMXD
Coordinate Increment
N1ZMYI
Coordinate Increment
N1ZMYD• Reduction Enable
Reduction Enable
N0ZMHF
Reduction Enable
N0ZMQT
Reduction Enable
N1ZMHF
Reduction Enable
N1ZMQT• Line & Vertical Cell Scroll Control
Vertical Cell Scroll Enable
N0VCSC
Vertical Cell Scroll Enable
N1VCSCLine Scroll Enable (For Horiz
N0LSCX
ontal Screen Scroll Values)
Line Scroll Enable (For Horiz
N1LSCX
ontal Screen Scroll Values)
Line Scroll Enable (For Vertical N0LSCY
Screen Scroll Values)

AddressdeBit
Abbreviation

nfi

Bit NameBitAbbreviation

Address

Application

10

For NBG1

3
11
5,4
13,12

For NBG0
For NBG1
For NBG0
For NBG1

2~0
15~1
2~0
15~1
2~0
15~1

For NBG0 (Most Significant Bits)
For NBG0 (Least Significant Bits)
For NBG1 (Most Significant Bits)
For NBG1 (Least Significant Bits)de• Line & Vertical Cell Scroll Control (Continued)
Line Scroll Enable (For Vertical N1LSCY
18009AH
Screen Scroll Values)
Line Zoom Enable
N0LZMX
18009AH
Line Zoom Enable
N1LZMX
18009AH
Line Scroll Space
N0LSS
18009AH
Line Scroll Space
N1LSS
18009AH• Vertical Cell Scroll Table Address
Vert. Cell Scroll Table Address VCSTA
18009CH
18009EH• Line Scroll Table AddressLine Scroll Table Address
N0LSTA
1800A0H
1800A2H
Line Scroll Table Address
N1LSTA
1800A4H
1800A6H• Line Color Screen Table AddressLine Color Screen Color Mode LCCLMD
1800A8H
Line Color Screen Table Add.
LCTA
1800A8H
1800AAH• Back Screen Table Address
Back Screen Color ModeBKCLMD
1800ACH
Back Screen Table Address
BKTA
1800ACH
1800AEH• Rotation Parameter Mode
Rotation Parameter Mode
RPMD
1800B0H• Rotation Parameter Read Control
Parameter Read Enable
RAXSTRE
1800B2H
Parameter Read Enable
RBXSTRE
1800B2H
Parameter Read Enable
RAYSTRE
1800B2H
Parameter Read Enable
RBYSTRE
1800B2H
Parameter Read Enable
RAKASTRE 1800B2H
Parameter Read Enable
RBKASTRE 1800B2H• Coefficient Table Control
Coefficient Table Enable
RAKTE
1800B4H
Coefficient Table Enable
RBKTE
1800B4H
Coefficient Data SizeRAKDBS
1800B4H
Coefficient Data SizeRBKDBS
1800B4H
Coefficient Data Mode
RAKMD
1800B4H
Coefficient Data Mode
RBKMD
1800B4H
Coefficient Line Color Enable
RAKLCE
1800B4H
Coefficient Line Color Enable
RBKLCE
1800B4H

Bit

nti
al

Bit Name

15
2~0
15~0
1,0
0
8
1
9
2
10

0
8
1
9
3,2
11,10
4
12

For Rotation Parameter-A Xst
For Rotation Parameter-B Xst
For Rotation Parameter-A Yst
For Rotation Parameter-B Yst
For Rotation Parameter-A KAst
For Rotation Parameter-B KAst
For Rotation Parameter-A
For Rotation Parameter-B
For Rotation Parameter-A
For Rotation Parameter-B
For Rotation Parameter-A
For Rotation Parameter-B
For Rotation Parameter-A
For Rotation Parameter-B

SE

GA

Co

nfi

15
2~0
15~0

ST-58-R2

321

Bit
Abbreviation

Address

Bit

1800B6H
1800B6H

2~0
10~8

For Rotation Parameter-A
For Rotation Parameter-B

1800B8H
1800BAH

15~0
15~0

For Rotation Parameter-A
For Rotation Parameter-B

1800BCH
1800BEH

2~0
15~1

W0SX

1800C0H

9~0

For W0 Start Point Coordinates

W0SY

1800C2H

8~0

For W0 Start Point Coordinates

W0EX

1800C4H

9~0

For W0 End Point Coordinates

W0EY

1800C6H

8~0

For W0 End Point Coordinates

W1SX

1800C8H

9~0

For W1 Start Point Coordinates

W1SY

1800CAH

8~0

For W1 Start Point Coordinates

W1EX

1800CCH

9~0

For W1 End Point Coordinates• Coefficient Table Address Offset
Coefficient Table Add. Offset RAKTAOS
Coefficient Table Add. Offset RBKTAOS• Screen Over Pattern Name
Screen Over Pattern Name
RAOPN
Screen Over Pattern Name
RBOPN
• Rotation Parameter Table Address
Rotation Parameter Table Add. RPTA

Applicationnti
al

Bit Name

W1EY

1800CEH

8~0

For W1 End Point Coordinates

N0W0E

1800D0H

1

For Transparent Processing Window NBGO(or RBG1)

W0 Enable

N1W0E

1800D0H

9

For Transparent Processing Window NBG1(or EXBG)

W0 Enable
W0 Enable
W0 Enable
W0 Enable
W0 Enable
W0 Enable
W0 Area

N2W0E
N3W0E
R0W0E
SPW0E
RPW0E
CCW0E
N0W0A

1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H
1800D0H

1
9
1
9
1
9
0

For Transparent Processing Window NBG2

N1W0A

1800D0H

8

For Transparent Processing Window NBG1(or EXBG)

N2W0A
N3W0A
R0W0A
SPW0A
RPW0A
CCW0A

1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

0
8
0
8
0
8

For Transparent Processing Window NBG2For Transparent Processing Window NBG3
For Transparent Processing Window RBG0
For Transparent Processing Window Sprite
For Rotation Parameter Window
For Color Calculation Window

322

nfi

Co

SE

W0 Area
W0 Area
W0 Area
W0 Area
W0 Area
W0 AreaGA

W0 Areade• Window Position
Window Position(For Horizontal Coordinates)
Window Position(For Vertical Coordinates)
Window Position(For Horizontal Coordinates)
Window Position(For Vertical Coordinates)
Window Position(For Horizontal Coordinates)
Window Position(For Vertical Coordinates)
Window Position(For Horizontal Coordinates)
Window Position(For Vertical Coordinates)• Window Control
W0 Enable

For Transparent Processing Window NBG3
For Transparent Processing Window RBG0
For Transparent Processing Window Sprite
For Rotation Parameter Window
For Color Calculation Window
For Transparent Processing Window NBGO(or RBG1)

Address

Bit• Window Control (Continued)
W1 Enable

N0W1E

1800D0H

3

W1 Enable

N1W1E

1800D0H

11

W1 Enable
W1 Enable
W1 Enable
W1 Enable
W1 Enable
W1 Enable
W1 Area

N2W1E
N3W1E
R0W1E
SPW1E
RPW1E
CCW1E
N0W1A

1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H
1800D0H

3
11
3
11
3
11
2

W1 Area

N1W1A

1800D0H

10

W1 Area
W1 Area
W1 Area
W1 Area
W1 Area
W1 Area
SW Enable

N2W1A
N3W1A
R0W1A
SPW1A
RPW1A
CCW1A
N0SWE

1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H
1800D0H

2
10
2
10
2
10
5

SW Enable

N1SWE

1800D0H

13

SW Enable
SW Enable
SW Enable
SW Enable
SW Enable
SW Area

N2SWE
N3SWE
R0SWE
SPSWE
CCSWE
N0SWA

1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D0H

5
13
5
13
13
4

N1SWA

1800D0H

12

N2SWA
N3SWA
R0SWA
SPSWA
CCSWA
N0LOG

1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D0H

4
12
4
12
12
7

Window Logic

N1LOG

1800D0H

15

Window Logic
Window Logic
Window Logic
Window Logic

N2LOG
N3LOG
R0LOG
SPLOG

1800D2H
1800D2H
1800D4H
1800D4H

7
15
7
15

de

For Transparent Processing Window NBG0
(or RBG1)
For Transparent Processing Window NBG1(or EXBG)For Transparent Processing Window NBG2For Transparent Processing Window NBG3
For Transparent Processing Window RBG0
For Transparent Processing Window Sprite
For Rotation Parameter Window
For Color Calculation Window
For Transparent Processing Window NBG0
(or RBG1)
For Transparent Processing Window NBG1(or EXBG)For Transparent Processing Window NBG2For Transparent Processing Window NBG3
For Transparent Processing Window RBG0
For Transparent Processing Window Sprite
For Rotation Parameter Window
For Color Calculation Window
For Transparent Processing Window NBG0
(or RBG1)
For Transparent Processing Window NBG1(or EXBG)For Transparent Processing Window NBG2For Transparent Processing Window NBG3
For Transparent Processing Window RBG0
For Transparent Processing Window Sprite
For Color Calculation Window
For Transparent Processing Window NBG0
(or RBG1)
For Transparent Processing Window NBG1(or EXBG)For Transparent Processing Window NBG2For Transparent Processing Window NBG3
For Transparent Processing Window RBG0
For Transparent Processing Window Sprite
For Color Calculation Window
For Transparent Processing Window NBG0
(or RBG1)
For Transparent Processing Window NBG1(or EXBG)For Transparent Processing Window NBG2For Transparent Processing Window NBG3
For Transparent Processing Window RBG0
For Transparent Processing Window SpriteSE

GA

SW Area
SW Area
SW Area
SW Area
SW Area
Window LogicCo

SW Area

Application

nti
al

Bit
Abbreviation

nfi

Bit Name

ST-58-R2

323

Bit Name

Bit
Abbreviation

Address

Bit

Application

RPLOG
CCLOG

1800D6H
1800D6H

715For Rotation Parameter Window
For Color Calculation Window

W0LWE
W1LWE
W0LWTALine Window Table Address

W1LWTA

1800D8H
1800DCH
1800D8H
1800DAH
1800DCH
1800DEH

15
15
2~0
15~1
2~0
15~1

For W0For W1For W0For W0For W1For W1SPTYPESPWINEN
SPCLMD
SPCCCS

1800E0H
1800E0H
1800E0H
1800E0H

3~0
4
5
13,12

SPCCN

1800E0H

10~8

TPSDSLN0SDENN1SDENN2SDEN
N3SDEN
R0SDENBKSDEN

1800E2H
1800E2H
1800E2H
1800E2H
1800E2H
1800E2H
1800E2H

8
0
1
2
3
4
5

SE
324

de

nfi

Co

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Back

N0CAOS
N1CAOSN2CAOS
N3CAOS
R0CAOSSPCAOS

1800E4H
1800E4H
1800E4H
1800E4H
1800E6H
1800E6H

2~0
6~4
10~8
14~12
2~0
6~4

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Sprite

N0LCEN

1800F8H

0

For NBG0 (or RBG1)

N1LCEN

1800F8H

1For NBG1 (or EXBG)

N2LCEN

1800F8H

2For NBG2N3LCEN

1800F8H

3For NBG3

R0LCEN

1800F8H

4For RBG0SPLCEN

1800F8H

5For SpriteGA• Sprite Control
Sprite Type
Sprite Window Enable
Sprite Color Mode
Sprite Color Calculation
Condition
Sprite Color Calculation
Number• Shadow Control
Transparent Shadow SelectShadow Enable
Shadow Enable
Shadow Enable
Shadow Enable
Shadow Enable
Shadow Enable• Color RAM Address Offset
Color RAM Address Offset
Color RAM Address Offset
Color RAM Address Offset
Color RAM Address Offset
Color RAM Address Offset
Color RAM Address Offset• Line Color Screen Enable
Line Color Screen Insertion
EnableLine Color Screen Insertion
EnableLine Color Screen Insertion
EnableLine Color Screen Insertion
EnableLine Color Screen Insertion
EnableLine Color Screen Insertion
Enablential• Window Control (Continued)
Window Logic
Window Logic• Line Window Table AddressLine Window Enable
Line Window Enable
Line Window Table Address

Bit

Application

1800EAH
1800EAH
1800EAH
1800EAH
1800EAH

1,0
3,2
5,4
7,6
9,8

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0

1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH

0
1
2
3
4
5
6
8
9
10

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For LNCL
For Sprite

1800ECH
1800ECH15
14~121800EEH
1800EEH
1800EEH
1800EEH
1800EEH

1,0
3,2
5,4
7,6
9,8

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0

2~0
10~8
2~0
10~8
2~0
10~8
2~0
10~8

For Sprite Register 0
For Sprite Register 1
For Sprite Register 2
For Sprite Register 3
For Sprite Register 4
For Sprite Register 5
For Sprite Register 6
For Sprite Register 7

Co

nfi

• Special Priority Mode
Special Priority Mode
N0SPRM
Special Priority Mode
N1SPRM
Special Priority Mode
N2SPRM
Special Priority Mode
N3SPRM
Special Priority Mode
R0SPRM• Color Calculation Control
Color Calculation Enable
N0CCEN
Color Calculation Enable
N1CCEN
Color Calculation Enable
N2CCEN
Color Calculation Enable
N3CCEN
Color Calculation Enable
R0CCEN
Color Calculation Enable
LCCCEN
Color Calculation Enable
SPCCEN
Color Calculation Mode
CCMD
Color Calculation Ratio Mode
CCRTMD
Extended Color Calculation
EXCCEN
EnableGradation Calculation Enable
BOKEN
Gradation Screen Number
BOKN• Special Color Calculation Mode
Special Color Calculation Mode N0SCCM
Special Color Calculation Mode N1SCCM
Special Color Calculation Mode N2SCCM
Special Color Calculation Mode N3SCCM
Special Color Calculation Mode R0SCCM• Priority Number
Priority Number (for Sprite)
S0PRIN
Priority Number (for Sprite)
S1PRIN
Priority Number (for Sprite)
S2PRIN
Priority Number (for Sprite)
S3PRIN
Priority Number (for Sprite)
S4PRIN
Priority Number (for Sprite)
S5PRIN
Priority Number (for Sprite)
S6PRIN
Priority Number (for Sprite)
S7PRIN

Address

nti
al

Bit
AbbreviationdeBit Name

SE

GA

1800F0H
1800F0H
1800F2H
1800F2H
1800F4H
1800F4H
1800F6H
1800F6H

ST-58-R2

325

Address

Bit

N0PRIN

1800F8H

2~0

For NBG0 (or RBG1)N1PRIN

1800F8H

10~8For NBG1 (or EXBG)

N2PRIN

1800FAH

2~0

For NBG2

N3PRIN

1800FAH

10~8

For NBG3

R0PRIN

1800FCH

2~0

For RBG0S0CCRTS1CCRTS2CCRT
S3CCRTS4CCRTS5CCRTS6CCRTS7CCRT
N0CCRT

180100H
180100H
180102H
180102H
180104H
180104H
180106H
180106H
180108H

4~0
12~8
4~0
12~8
4~0
12~8
4~0
12~8
4~0

For Sprite Register 0
For Sprite Register 1
For Sprite Register 2
For Sprite Register 3
For Sprite Register 4
For Sprite Register 5
For Sprite Register 6
For Sprite Register 7
For NBG0 (or RBG1)N1CCRT

180108H

12~8For NBG1 (or EXBG)

N2CCRT

18010AH

4~0

For NBG2N3CCRT

18010AH

12~8

For NBG3R0CCRT

18010CH

4~0

For RBG0LCCCRT

18010EH

4~0

For LNCLBKCCRT

18010EH

12~8

For BACK

N0COENN1COENN2COEN
N3COEN
R0COENBKCOENSPCOEN

180110H
180110H
180110H
180110H
180110H
180110H
180110H

0
1
2
3
4
5
6

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For BACKFor Sprite

N0COSLN1COSLN2COSL
N3COSLR0COSLBKCOSLSPCOSL

180112H
180112H
180112H
180112H
180112H
180112H
180112H

0
1
2
3
4
5
6

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For BACKFor SpriteSE

GA• Color Offset Enable
Color Offset Enable
Color Offset Enable
Color Offset Enable
Color Offset Enable
Color Offset Enable
Color Offset Enable
Color Offset Enable• Color Offset SelectColor Offset SelectColor Offset SelectColor Offset SelectColor Offset SelectColor Offset SelectColor Offset SelectColor Offset Select

326

de

Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Sprite)
Color Calculation Ratio (For Scroll
Screen)Color Calculation Ratio (For Scroll
Screen)Color Calculation Ratio (For Scroll
Screen)Color Calculation Ratio (For Scroll
Screen)Color Calculation Ratio (For Scroll
Screen)Color Calculation Ratio (For Scroll
Screen)Color Calculation Ratio (For Scroll
Screen)nfi• Priority Number (Continued)
Priority Number(for Scroll Screen)
Priority Number for(for Scroll Screen)
Priority Number for(for Scroll Screen)
Priority Number for(for Scroll Screen)
Priority Number for(for Scroll Screen)• Color Calculation Ratio

Application

nti
al

Bit
Abbreviation

Co

Bit NameBitAbbreviation

Address

Bit

COARD
COAGR
COABL
COBRD
COBGR
COBBL

180114H
180116H
180118H
18011AH
18011CH
18011EH

8~0
8~0
8~0
8~0
8~0
8~0

For Color Offset A Red Data
For Color Offset A Green Data
For Color Offset A Blue Data
For Color Offset B Red Data
For Color Offset B Green Data
For Color Offset B Blue Data

SE

GA

Co

nfi

de

• Color Offset
Color Offset Value
Color Offset Value
Color Offset Value
Color Offset Value
Color Offset Value
Color Offset Value

Applicationnti
al

Bit Name

ST-58-R2

327

• TV Mode (Read Allowed)
TVMD
180000H

15
DISP
7
LSMD1

14
~
6
LSMD0

13
~
5
VRESO1

12~
4
VRESO011~
3~

TV screen display bit : Display bit (DISP), bit 15

DISP

Process

01

Picture is not displayed on TV screen
Picture is displayed on TV screen

Border color mode bit (BDCLMD), bit 8

BDCLMD

Process

01

Displays black
Display back screen

9~
1
HRESO18BDCLMD
0
HRESO0nfi

Controls colors displayed by the border area.

10~
2
HRESO2deControls picture display to the TV screen.

nti
al16.3 Register Bit Functions

Interlace mode bit (LSMD1, LSMD0) bits 7 and 6

LSMD1

LSMD0

0
0
1
1

0
1
0
1

Co

Designates the interlace mode.

Process

Non-Interlace
Setting not allowed
Single-density interlace
Double-density interlace

Vertical resolution bit (VRESO1, VRESO0), bit 5, 4

VRESO1VRESO0

Vertical Resolution

Display Monitor

0
1
0
1

224 Lines
240 Lines
256 Lines
Not Allowed

NTSC or PAL format TV
NTSC or PAL format TV
PAL format TV
-

SE

0
0
1
1

GA

Designates vertical resolution when a picture is displayed on the TV screen.

328

Horizontal resolution bit (HRESO2 to HRESO0), bit 2 to 0

HRESO2HRESO1HRESO0

Horizontal
Resolution

0

0

0

320 Pixels

0

0

1

352 Pixels

0

1

0

640 Pixels

0

1

1

704 Pixels

1

0

0

320 Pixels

1

0

1

352 Pixels

nti
al

Selects the horizontal resolution when a picture is displayed on the TV screen.

1

1

0

640 Pixels

31kHz Monitor

1

1

1

Graphic Mode

NormalGraphic A
NormalGraphic B
Hi-ResGraphic A
Hi-ResGraphic BdeExclusive Normal
Graphic A
Exclusive Normal
Graphic B
Exclusive Normal
Graphic A
Exclusive Normal
Graphic B

704 Pixels

Display
MonitorNTSC
Format or
PAL
Format TV

31kHz Monitor

Hi-Vision Monitor

Hi-Vision Monitor

EXTEN
180002H

15
~
7
~

14
~
6
~

nfi

• External Signal Enable Register (Read Allowed)
13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
~

9
EXLTEN
1DASEL

8EXSYEN0
EXBGEN

External latch enable bit (EXLTEN), bit 9

EXLTEN

0
1

Co

Selects the condition for latching the HV counter value to the HV counter register.
Condition

Latches when reading external signal enable register
Latches through external signal

EXSYNC enable bit (EXSYEN), bit 8

Controls input to the internal synchronous circuit of the external sync signal.
Process

Does not input external sync signal
Inputs external sync signal, and synchronizes TV screen display with theexternal

SE

0
1

GA

EXSYEN

ST-58-R2

329

Display area select bit (DASEL), bit1

nti
alDesignates the image display area. Valid only when the EXBGEN bit is 1.
DASEL

Process

01

Displays screen image only in the set display area
Displays screen in the standard display area

EXBG enable bit (EXBGEN), bit 0

EXBGEN

Process01

Does not input external screen data
Inputs external screen data

• Screen Status (Read Only)
15
~
7
~

14
~
6
~

13
~
5
~

External latch flag (EXLTFG), bit 9

12
~
4
~

11
~
3
VBLANK

10~2
HBLANK

9
EXLTFG
1
ODD

nfi

TVSTAT
180004HdeControls input of external screen data.

8
EXSYFG
0
PAL

Through external signals, this displays whether the HV counter value is latched to
the HV counter register. Clears to 0 when the screen status register reads out.
HV Counter Value Status01

Not latched in register
Latched in registerCo

EXLTFG

External SYNC flag (EXSYFG), bit 8

Displays whether the internal routes through External SYNC flag are in sync.
Clears to 0 when the screen status register reads out.
External Sync Status01

Not synchronizedInternal circuit synchronizedSE

GA

EXSYFG

330

Vertical blank flag (VBLANK), bit 3

VBLANK

Vertical Scan Status01

During vertical scan
During vertical re-trace (VBLANK)

Horizontal blank flag (HBLANK), bit 2

nti
al

Displays the vertical scan status of the TV screen.

Displays the horizontal scan status of the TV screen.
HBLANK

Horizontal Scan Status01

During horizontal scan
During horizontal re-trace (HBLANK)deScan Field Flag : Odd/even field flag (ODD), bit 1

Scan conditions are shown when the TV screen mode is the interlace mode.
non-interlace mode is always 1.
Display01

During even field scan
During odd field scan

nfi

ODD

The

TV standard flags : PAL/NTSC flag (PAL), bit 0

Displays TV standards.
Display

0
1

NTSC standard
PAL standard

Co

PAL

• VRAM Size (Read Allowed)
15
VRAMSZ
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
VER3

10
~
2
VER2

9
~
1
VER1

8
~
0
VER0

SE

GA

VRSIZE
180006H

ST-58-R2

331

VRAM size bit (VRAMSZ), bit 15.

VRAMSZVRAM Size0
1

4M bit8M bitVersion Number Bit (VER3 to VER0), Bits 3 to 0

Shows the VDP2 version number; the first is 0.
• H Counter (Read Only)
15
~
7
HCT7

14
~
6
HCT6

13
~
5
HCT5

12
~
4
HCT4

11
~
3
HCT3

10
~
2
HCT2

9
HCT9
1
HCT1

8
HCT8
0
HCT0

de

HCNT
180008Hnti
alIndicates the VRAM capacity used in the system.

H counter bit (HCT9 to HCT0), bits 9 to 0

HCT9

HCT8

HCT7

HCT6

HCT5

HCT4

HCT3

HCT2

HCT1

HCT0

H8
H7
H9
H8
Invalid H8

H6
H7
H7

H5
H6
H6

H4
H5
H5

H3
H4
H4

H2
H3
H3

H1
H2
H2

H0
H1
H1

Invalid
H0
H0

Invalid H9

H8

H7

H6

H5

H4

H3

H2

H1

• V Counter (Read Only)
15
~
7
VCT7

14
~
6
VCT6

13
~
5
VCT5

SE

GA

VCNT
18000AH

Co

Graphic
Mode
NormalHi-ResExclusive
NormalExclusive
Hi-Res332

nfi

Signals controlled through EXLTEN external signal enable register show the latched
H counter values.

12
~
4
VCT4

11
~
3
VCT3

10
~
2
VCT2

9
VCT9
1
VCT1

8
VCT8
0
VCT0

V counter value bit : V counter bit (VCT9~VCT0), bit 9 to 0

TV Screen(Interlace) Mode
Normal Hi-Res(Non-Interlace,Single-Density
Interlace)Normal Hi-Res(Double-Density
Interlace)

VCT9

VCT8

VCT7

VCT6

VCT5

VCT4

V8

V7

V6

V5

V4

V3

V8

V7

V6

V5

V4

V3

Exclusive
Monitor

V9

V8

V7

V6

V5

V4

VCT2

VCT1

VCT0

V2

V1

V0

Invalid

V2

V1

V0

0: Odd fields
1: Even fields

V3

V2

V1

V0

15
14
13
12
11
10
9
8
CRKTE
~
CRMD1
CRMD0
~
~
VRBMD
VRAMD
7
6
5
4
3
2
1
0
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00

nfi

RAMCTL
18000EH

VCT3

de• RAM Control (Read Allowed)ntialSignals controlled through EXLTEN external signal enable register show the latched
V counter values.

Color RAM coefficient table enable bit (CRKTE), bit 15

Designates whether to store the coefficient table in color RAM.
Process0

Coefficient table is stored in VRAM.

1

Coefficient table is stored in color RAM.

Co

CRKTE

Color RAM mode bit (CRMD1, CRMD0), bits 13 and 12

Selects the color RAM mode
CRMD0

Mode

Process

0
0
1
1

0
1
0
1

0
1
2
-

RGB each 5 bits, 1024 color settings
RGB each 5 bits, 2048 color settings
RGB each 8 bits, 1024 color settings
Setting not allowed

GA

CRMD1

VRAM Mode Bit (VRBMD, VRAMD), Bits 9 and 8SE

Controls VRAM bank partitions

ST-58-R2

333

18000EH
18000EH

VRxMD

Process0
1

Do not partition in 2 banks
Partition in 2 banks

Note:

Bit 8
Bit 9

For VRAM-A
For VRAM-B

nti
al

VRAMD
VRBMD

Enter A or B into bit name for x.

Rotation data bank select bit: Data bank select bit (RDBSA01, RDBSA00, RDBSA11,
RDBSA10, RDBSB01, RDBSB00, RDBSB11, RDBSB10)

Designates the use objective of the VRAM of the rotation scroll screen. This bit is
only in effect when the rotation scroll screen is displayed.

Note:

RDBSx001
01

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6

For VRAM-A0 (or VRAM-A)
For VRAM-A1
For VRAM-B0 (or VRAM-B)
For VRAM-B1

deRDBSx1001118000EH
18000EH
18000EH
18000EH

VRAM Use
Not used as RAM for RBG0
RAM for RBG0 End table
RAM for RBG0 Pattern Name table
RAM for RBG0 Character Pattern table (or Bitmap Pattern)nfi

RDBSA00, RDBSA01
RDBSA10, RDBSA11
RDBSB00, RDBSB01
RDBSB10, RDBSB11

A0, A1, B0, or B1 is entered in bit name for x.

• VRAM Cycle Pattern (Bank A0)

15
14
13
12
11
10
9
8
VCP0A03 VCP0A02 VCP0A01 VCP0A00 VCP1A03 VCP1A02 VCP1A01 VCP1A00
7
6
5
4
3
2
1
0
VCP2A03 VCP2A02 VCP2A01 VCP2A00 VCP3A03 VCP3A02 VCP3A01 VCP3A00

Co

CYCA0L
180010H

VRAM Cycle Pattern (Bank A0)

15
14
13
12
11
10
9
8
VCP4A03 VCP4A02 VCP4A01 VCP4A00 VCP5A03 VCP5A02 VCP5A01 VCP5A00
7
6
5
4
3
2
1
0
VCP6A03 VCP6A02 VCP6A01 VCP6A00 VCP7A03 VCP7A02 VCP7A01 VCP7A00

GA

CYCA0U
180012HSE

VRAM cycle pattern (for VRAM-A0) bit: VRAM cycle pattern bit (VCP0A00 to
VCP0A03, VCP1A00 to VCP1A03, VCP2A00 to VCP2A03, VCP3A00 to VCP3A03,
VCP4A00 to VCP4A03, VCP5A00 to VCP5A03, VCP6A00 to VCP6A03, VCP7A00 to
VCP7A03)334

VCP0A00~VCP0A03
VCP1A00~VCP1A03
VCP2A00~VCP2A03
VCP3A00~VCP3A03
VCP4A00~VCP4A03
VCP5A00~VCP5A03
VCP6A00~VCP6A03
VCP7A00~VCP7A03

180010H
180010H
180010H
180010H
180012H
180012H
180012H
180012H

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3• VRAM Cycle Pattern (Bank A1)

15
14
13
12
11
10
9
8
VCP0A13 VCP0A12 VCP0A11 VCP0A10 VCP1A13 VCP1A12 VCP1A11 VCP1A10
7
6
5
4
3
2
1
0
VCP2A13 VCP2A12 VCP2A11 VCP2A10 VCP3A13 VCP3A12 VCP3A11 VCP3A10

nfi• VRAM Cycle Pattern (Bank A1)
CYCA1U
180016H

VRAM-A0 (or VRAM-A) Timing for T0
VRAM-A0 (or VRAM-A) Timing for T1
VRAM-A0 (or VRAM-A) Timing for T2
VRAM-A0 (or VRAM-A) Timing for T3
VRAM-A0 (or VRAM-A) Timing for T4
VRAM-A0 (or VRAM-A) Timing for T5
VRAM-A0 (or VRAM-A) Timing for T6
VRAM-A0 (or VRAM-A) Timing for T7

de

CYCA1L
180014Hnti
alSets the access command of VRAM access that performs in VRAM-A0 (or VRAMA) timing T0 to T7.

15
14
13
12
11
10
9
8
VCP4A13 VCP4A12 VCP4A11 VCP4A10 VCP5A13 VCP5A12 VCP5A11 VCP5A10
7
6
5
4
3
2
1
0
VCP6A13 VCP6A12 VCP6A11 VCP6A10 VCP7A13 VCP7A12 VCP7A11 VCP7A10

Co

VRAM cycle pattern (for VRAM-A1) bit: VRAM cycle pattern bit (VCP0A10 to
VCP0A13, VCP1A10 to VCP1A13, VCP2A10 to VCP2A13, VCP3A10 to VCP3A13,
VCP4A10 to VCP4A13, VCP5A10 to VCP5A13, VCP6A10 to VCP6A13, VCP7A10 to
VCP7A13)

Sets the access command of the VRAM access that performs in VRAM-A1 timing T0
to T7.
180014H
180014H
180014H
180014H
180016H
180016H
180016H
180016H

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3

VRAM-A1 Timing for T0
VRAM-A1 Timing for T1
VRAM-A1 Timing for T2
VRAM-A1 Timing for T3
VRAM-A1 Timing for T4
VRAM-A1 Timing for T5
VRAM-A1 Timing for T6
VRAM-A1 Timing for T7

SE

GA

VCP0A10~VCP0A13
VCP1A10~VCP1A13
VCP2A10~VCP2A13
VCP3A10~VCP3A13
VCP4A10~VCP4A13
VCP5A10~VCP5A13
VCP6A10~VCP6A13
VCP7A10~VCP7A13

ST-58-R2

335

CYCB0L
180018H

ntial• VRAM Cycle Pattern (Bank B0)
15
14
13
12
11
10
9
8
VCP0B03 VCP0B02 VCP0B01 VCP0B00 VCP1B03 VCP1B02 VCP1B01 VCP1B00
7
6
5
4
3
2
1
0
VCP2B03 VCP2B02 VCP2B01 VCP2B00 VCP3B03 VCP3B02 VCP3B01 VCP3B00• VRAM Cycle Pattern (Bank B0)

de

CYCB0U
18001AH

15
14
13
12
11
10
9
8
VCP4B03 VCP4B02 VCP4B01 VCP4B00 VCP5B03 VCP5B02 VCP5B01 VCP5B00
7
6
5
4
3
2
1
0
VCP6B03 VCP6B02 VCP6B01 VCP6B00 VCP7B03 VCP7B02 VCP7B01 VCP7B00

VRAM cycle pattern (for VRAM-B0) bit: VRAM cycle pattern bit(VCP0B00 to VCP0B03, VCP1B00 to VCP1B03, VCP2B00 to VCP2B03, VCP3B00 to
VCP3B03, VCP4B00 to VCP4B03, VCP5B00 to VCP5B03, VCP6B00 to VCP6B03,
VCP7B00 to VCP7B03)

180018H
180018H
180018H
180018H
18001AH
18001AH
18001AH
18001AH

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3

VRAM-B0 (or VRAM-B) Timing for T0
VRAM-B0 (or VRAM-B) Timing for T1
VRAM-B0 (or VRAM-B) Timing for T2
VRAM-B0 (or VRAM-B) Timing for T3
VRAM-B0 (or VRAM-B) Timing for T4
VRAM-B0 (or VRAM-B) Timing for T5
VRAM-B0 (or VRAM-B) Timing for T6
VRAM-B0 (or VRAM-B) Timing for T7

Co

VCP0B00~VCP0B03
VCP1B00~VCP1B03
VCP2B00~VCP2B03
VCP3B00~VCP3B03
VCP4B00~VCP4B03
VCP5B00~VCP5B03
VCP6B00~VCP6B03
VCP7B00~VCP7B03

nfi

Sets the access command of VRAM access that performs in VRAM-B0 (or VRAM-B)
timing T0 to T7.

• VRAM Cycle Pattern (Bank B1)

GA

CYCB1L
18001CH

15
14
13
12
11
10
9
8
VCP0B13 VCP0B12 VCP0B11 VCP0B10 VCP1B13 VCP1B12 VCP1B11 VCP1B10
7
6
5
4
3
2
1
0
VCP2B13 VCP2B12 VCP2B11 VCP2B10 VCP3B13 VCP3B12 VCP3B11 VCP3B10• VRAM Cycle Pattern (Bank B1)

15
14
13
12
11
10
9
8
VCP4B13 VCP4B12 VCP4B11 VCP4B10 VCP5B13 VCP5B12 VCP5B11 VCP5B10
7
6
5
4
3
2
1
0
VCP6B13 VCP6B12 VCP6B11 VCP6B10 VCP7B13 VCP7B12 VCP7B11 VCP7B10SECYCB1U
18001EH

336

nti
al

VRAM cycle pattern (for VRAM-B1) bit: VRAM cycle pattern bit(VCP0B10 to VCP0B13, VCP1B10 to VCP1B13, VCP2B10 to VCP2B13, VCP3B10 to
VCP3B13, VCP4B10 to VCP4B13, VCP5B10 to VCP5B13, VCP6B10 to VCP6B13,
VCP7B10 to VCP7B13).

Sets the access command of VRAM access that performs in VRAM-B1 timing T0 to
T7.
18001CH
18001CH
18001CH
18001CH
18001EH
18001EH
18001EH
18001EH

Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3
Bit 12~15
Bit 8~11
Bit 4~7
Bit 0~3

VCPnxx1

VCPnxx0

VRAM Access

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

NBG0 Pattern Name Data Read
NBG1 Pattern Name Data Read
NBG2 Pattern Name Data Read
NBG3 Pattern Name Data Read
NBG0 Character Pattern Data Read
NBG1 Character Pattern Data Read
NBG2 Character Pattern Data Read
NBG3 Character Pattern Data Read
Setting not allowed
Setting not allowed
Setting not allowed
Setting not allowed

Co

nfi

Access Command Value
VCPnxx3
VCPnxx2

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

VRAM-B1 Timing for T0
VRAM-B1 Timing for T1
VRAM-B1 Timing for T2
VRAM-B1 Timing for T3
VRAM-B1 Timing for T4
VRAM-B1 Timing for T5
VRAM-B1 Timing for T6
VRAM-B1 Timing for T7

de

VCP0B10~VCP0B13
VCP1B10~VCP1B13
VCP2B10~VCP2B13
VCP3B10~VCP3B13
VCP4B10~VCP4B13
VCP5B10~VCP5B13
VCP6B10~VCP6B13
VCP7B10~VCP7B13

NBG0 Vertical Cell Scroll Table Data Read
NBG1 Vertical Cell Scroll Table Data Read

CPU Read/Write
No AccessSE

GA

Note: n: 0 to 7 (corresponds to access timing T0 to T7)
xx: A0, A1, B0, B1 (corresponds to VRAM-A0, VRAM-A1, VRAM-B0, VRAM-B1)

ST-58-R2

337

• Screen Display Enable
15
~
7
~

14
~
6
~

13
~
5
R1ON

12
R0TPON
4
R0ON

11
N3TPON
3
N3ON

10
N2TPON
2N2ON

9N1TPON
1
N1ON

8
N0TPON
0
N0ON

nti
al

BGON
180020H

Transparent display enable bit (N0TPON, N1TPON, N2TPON, N3TPON, R0TPON)

Designates whether to nullify the transparency code.
180020H
180020H
180020H
180020H
180020H

Bit 8
Bit 9
Bit 10
Bit 11
Bit 12For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0de

N0TPONN1TPONN2TPON
N3TPONR0TPONxxTPON

Process01

Validates transparency code (transparency code dots become transparent)
Invalidates transparency code (transparency code dots are displayed according to data
values)N0, N1, N2, N3, or R0 is entered into bit name for xx.

nfi

Note:

Screen display enable bit: On bit (N0ON, N1ON, N2ON, N3ON, R0ON, R1ON)

Designates whether to display each scroll screen.
180020H
180020H
180020H
180020H
180020H
180020H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5

Co

N0ON
N1ON
N2ON
N3ON
R0ON
R1ON

For NBG0
For NBG1
For NBG2
For NBG3
For RBG0
For RBG1xxON

Process01

Cannot display (Does not execute VRAM access for display)
Can display

Note:

N0, N1, N2, N3, R0, or R1 is entered into bit name xx.

15
MZSZV37~14
MZSZV2
6
~

SE

MZCTL
180022HGA• Mosaic Control

338

13
MZSZV15~12
MZSZV04R0MZE11MZSZH33N3MZE

10MZSZH22N2MZE

9MZSZH11N1MZE

8MZSZH00
N0MZEMosaic size bit (MZSZH3 to MZSZH0, MZSZV3 to MZSZV0)Note:

MZSZH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Bit 15~12
Bit 11~8

MZSZH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

MZSZH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

For vertical mosaic size
For horizontal mosaic size

Horizontal Mosaic Size
1 dot
2 dots3 dots4 dots5 dots
6 dots7 dots
8 dots9 dots
10 dots
11 dots
12 dots
13 dots
14 dots
15 dots
16 dotsdeMZSZH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

180022H
180022Hnfi

MZSZV3~MZSZV0MZSZH3~MZSZH0ntialDesignates the horizontal and vertical mosaic size.

There is no relationship with the interlace setting.
MZSZV2MZSZV1MZSZV0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Vertical Mosaic Size
Non-Interlace
Interlace
1 dot
2 dots2 dots4 dots3 dots
6 dots4 dots
8 dots5 dots
10 dots
6 dots12 dots
7 dots
14 dots
8 dots16 dots
9 dots18 dots
10 dots
20 dots
11 dots
22 dots
12 dots
24 dots
13 dots
26 dots
14 dots
28 dots
15 dots
30 dots
16 dots
32 dots

SE

GA

Co

MZSZV3

ST-58-R2

339

Mosaic enable bit (N0MZE, N1MZE, N2MZE, N3MZE, R0MZE)

180022H
180022H
180022H
180022H
180022H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4

xxMZE
0
1

Process
Does not execute mosaic process
Processes mosaic process

Note:

N0, N1, N2, N3, or R0 is entered in bit name for xx.

• Special Function Code Select
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
R0SFCS

11~3
N3SFCS

10~2
N2SFCS

nfi

SFSEL
180024HFor NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0

de

N0MZE
N1MZE
N2MZE
N3MZE
R0MZE

nti
al

Designates the screen performing mosaic process.

9~
1
N1SFCS

8~0
N0SFCSSpecial function code select bit (N0SFCS, N1SFCS, N2SFCS, N3SFCS,
R0SFCS)

Designates the special function code effecting every scroll screen.
180024H
180024H
180024H
180024H
180024H

xxSFCS

Enables special function code A
Enables special function code B

GA

N0, N1, N2, N3, or R0 is entered in bit name for xx.

SE
340

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0

Process

0
1
Note:

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4

Co

N0SFCS
N1SFCSN2SFCS
N3SFCS
R0SFCS• Special Function Code15
SFCDB7
7SFCDA7

14
SFCDB6
6SFCDA6

13
SFCDB55SFCDA512
SFCDB44SFCDA4

11
SFCDB3
3
SFCDA3

10
SFCDB2
2
SFCDA29
SFCDB1
1
SFCDA1

8
SFCDB00
SFCDA0nti
al

SFCODE
180026H

Special function code bit (SFCDA7 to SFCDA0, SFCDB7 to SFCDB0)

Designates special function codes A and B.
180026H
180026H

Bit Name
SFCDx0
SFCDx1SFCDx2SFCDx3SFCDx4SFCDx5SFCDx6SFCDx7

Dot Color Code
When lower 4 bits of dot color code are, 0H or 1H
When lower 4 bits of dot color code are, 2H or 3H
When lower 4 bits of dot color code are, 4H or 5H
When lower 4 bits of dot color code are, 6H or 7H
When lower 4 bits of dot color code are, 8H or 9H
When lower 4 bits of dot color code are, AH or BH
When lower 4 bits of dot color code are, CH or DH
When lower 4 bits of dot color code are, EH or FH

For Special Function Code A
For Special Function Code B

nfi

Note:

Bit 7~0
Bit 15~8de

SFCDA7~SFCDA0
SFCDB7~SFCDB0

A or B is entered in bit name x.

Process
Does not use special functions
Uses special functions

Co

Settings
01• Character Control (NBG0, NBG1)CHCTLA
180028H

15
~
7
~

14
13
12
11
10
9
~
N1CHCN1 N1CHCN0 N1BMSZ1 N1BMSZ0 N1BMEN
6
5
4
3
2
1
N0CHCN2 N0CHCN1 N0CHCN0 N0BMSZ1 N0BMSZ0 N0BMEN

8
N1CHSZ0N0CHSZGA• Character Control (NBG2, NBG3, RBG0)
15
~
7
~

14
13
12
R0CHCN2 R0CHCN1 R0CHCN0654~N3CHCN N3CHSZ

11
~
3
~

10
R0BMSZ
2~

9
R0BMEN
1
N2CHCN

8
R0CHSZ
0N2CHSZSECHCTLB
18002AH

ST-58-R2

341

Character color number bit (N0CHCN2 to N0CHCN0, N1CHCN1, N1CHCN0, N2CHCN,
N3CHCN, R0CHCN2 to R0CHCN0)

180028H
180028H
18002AH
18002AH
18002AH

N0CHCN2

N0CHCN1

N0CHCN0

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

1
1
1

0
1
1

1
0
1

N1CHCN0
0
1
0
1

Color
FormatPalette Format
Palette Format
Palette Format

RGB Format
RGB Format

TV Screen Mode
NormalHi-Res16 colors
16 colors
256 colors
256 colors
2048 colors
2048 colors
32,786 colors 32,786 colors

Color Format

Exclusive Monitor

16 colors
256 colors
2048 colors
32,786 colors

Palette Format
Palette Format
Palette Format
RGB Format

When used as EXBG, and when the set values are N1CHCN1 = 1, N1CHCN0 = 1 there are
16,770,000 colors

NnCHCN0TV Screen Mode
NormalHi-Res16 colors
16 colors
256 colors
256 colors

GA

0
1

2 or 3 is entered in bit name for n.

SE
342

nfi

0
0
1
1

Note:

TV Screen Mode
Exclusive Monitor
NormalHi-Res16 colors
16 colors
16 colors
256 colors
256 colors
256 colors
2048 colors
2048 colors
2048 colors
32,786 colors 32,786 colors 32,786 colors
16,770,000
Setting not
Setting notcolorsallowedallowedSetting not allowed (Please do not set.)
Setting not allowed (Please do not set.)
Setting not allowed (Please do not set.)

Cannot be displayed by the exclusive monitor mode when used as RBG1.

N1CHCN1Note:

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0

Co

Note:

Bit 6~4
Bit 13,12
Bit 1
Bit 5
Bit 14~12

de

N0CHCN2~N0CHCN0
N1CHCN1,N1CHCN0
N2CHCN
N3CHCNR0CHCN2~R0CHCN0nti
alDesignates the character color count of each screen and the bit map color countwhen displaying by the bit map format.

Color Format
Exclusive Monitor

16 colors
256 colors

Palette Format
Palette Format

R0CHCN1

R0CHCN0

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

1
1
1

0
1
1

1
0
1

TV Screen ModeColor
Exclusive Monitor
NormalHi-ResFormat16 colors
16 colors
Cannot Display Palette Format
256 colors
256 colors
Cannot Display Palette Format
2048 colors
2048 colors
Cannot Display Palette Format
32,786 colors 32,786 colors Cannot Display RGB Format
16,770,000
Setting not
Cannot Display RGB Format
colorsallowedSetting not allowed (Please do not set.)
Setting not allowed (Please do not set.)
Setting not allowed (Please do not set.)nti
al

R0CHCN2

Bit map size bit (N0BMSZ1, N0BMSZ0, N1BMSZ1, N1BMSZ0, R0BMSZ)

180028H
180028H
18002AH

NnBMSZ1

NnBMSZ0

0
0
1
1

0
1
0
1

Bit 3,2
Bit 11,10
Bit 10For NBG0
For NBG1
For RBG0

Bitmap Size

512 H dots X 512 V dots
512 H dots X 512 V dots
512 H dots X 512 V dots
512 H dots X 512 V dots

nfi

N0BMSZ1,N0BMSZ0N1BMSZ1,N1BMSZ0R0BMSZdeDesignates the bit map size of each screen when display is in a bit map format.

Note: 0 or 1 is entered in bit name for n.
Bitmap Size

01

512 H dots X 256 V dots
512 H dots X 512 V dots

Co

ROBMSZ

Bit map enable bit (N0BMEN, N1BMEN, R0BMEN)

Designates whether to display the scroll screen in a bit map format.
180028H
180028H
18002AH

Bit 1
Bit 9
Bit 9

For NBG0
For NBG1
For RBG0SEGA

N0BMEN
N1BMEN
R0BMEN

ST-58-R2

343

Screen Display Format

01

Cell Format
Bitmap Format

Note: N0, N1, or R0 is entered in bit name for xx.
Character size bit (N0CHSZ, N1CHSZ, N2CHSZ, N3CHSZ, R0CHSZ)

nti
alxxBMEN

Designates the character size when the scroll screen is in a cell format.
180028H
180028H
18002AH
18002AH
18002AH

Bit 0
Bit 8
Bit 0
Bit 4
Bit 8

xxCHSZ

Character Pattern Size

01

1 H Cell X 1 V Cell
2 H Cells X 2 V Cells

Note: N0, N1, N2, N3, or R0 is entered in bit name for xx.

BMPNA
18002CH

15
~
7
~

14
~
6
~

13
N1BMPR
5
N0BMPR

BMPNB
18002EH

15
~
7
~

14
~
6
~

12
N1BMCC
4
N0BMCCCo• Bit Map Palette Number (RBG0)

nfi• Bit Map Palette Number (NBG0, NBG1)For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0de

N0CHSZN1CHSZN2CHSZN3CHSZROCHSZ

13~
5
R0BMPR

12~
4
R0BMCC

11
~
3
~

10
N1BMP6
2
N0BMP6

9
N1BMP5
1
N0BMP5

8
N1BMP40
N0BMP4

11
~
3
~

10
~
2
R0BMP6

9~
1
R0BMP5

8~
0
R0BMP4

Special priority bit (for bit map): Bit map special priority bit (N0BMPR, N1BMPR,
R0BMPR)

18002CH
18002CH
18002EHSE

N0BMPR
N1BMPR
R0BMPRGA

Designates the special priority bit when the scroll screen is displayed by the bit map
format.

344

Bit 5
Bit 13Bit 5

For NBG0
For NBG1
For RBG0

Special color calculation bit (for bit map): Bit map special color calculation bit(N0BMCC, N1BMCC, R0BMCC)

N0BMCCN1BMCCR0BMCC

18002CH
18002CH
18002EH

Bit 4
Bit 12
Bit 4

nti
al

Designates the special color calculation bit when the scroll screen is displayed by the
bit map format.
For NBG0
For NBG1
For RBG0

Palette number bit (for bit map): Bit map palette number bit (N0BMP6 to N0BMP4,
N1BMP6 to N1BMP4, R0BMP6 to R0BMP4)

Designates the highest 3 bits of the palette number when the scroll screen isdisplayed in the bit map format.
18002CH
18002CH
18002EH

Bit 2~0
Bit 10~8
Bit 2~0• Pattern Name Control (NBG0)For NBG0
For NBG1
For RBG012~
4
N0SCN411~
3
N0SCN310~
2N0SCN2

9N0SPR
1N0SCN18
N0SCC
0N0SCN012~
4N1SCN411~
3
N1SCN310~
2N1SCN29N1SPR
1N1SCN18
N1SCC
0N1SCN012~
4N2SCN411~
3
N2SCN310~
2
N2SCN29N2SPR
1N2SCN18N2SCC
0N2SCN012~
4N3SCN411~
3
N3SCN310~
2N3SCN29N3SPR
1N3SCN18N3SCC
0N3SCN0nfi

PNCN0180030H

15
14
13
N0PNB
N0CNSM~
7
6
5
N0SPLT6 N0SPLT5 N0SPLT4de

N0BMP6~N0BMP4
N1BMP6~N1BMP4R0BMP6~R0BMP4• Pattern Name Control (NBG1)

15
14
13
N1PNB
N1CNSM~
7
6
5
N1SPLT6 N1SPLT5 N1SPLT4

Co

PNCN1
180032H• Pattern Name Control (NBG2)

GA

PNCN2
180034H

15
14
13
N2PNB
N2CNSM~
7
6
5
N2SPLT6 N2SPLT5 N2SPLT4• Pattern Name Control (NBG3)
15
14
13
N3PNB
N3CNSM~
7
6
5
N3SPLT6 N3SPLT5 N3SPLT4

SE

PNCN3
180036H

ST-58-R2

345

• Pattern Name Control (RBG0)
15
14
13
R0PNB
R0CNSM~
7
6
5
R0SPLT6 R0SPLT5 R0SPLT412~4R0SCN411~
3
R0SCN310~
2R0SCN2

Pattern name data size bit (N0PNB, N1PNB, N2PNB, N3PNB, R0PNB)

9
R0SPR
1
R0SCN1

8R0SCC
0R0SCN0

nti
al

PNCR
180038H

Designates the pattern name data size when displaying in the cell format.
180030H
180032H
180034H
180036H
180038H

xxPNB
0
1

Pattern Name Data Size
2 Words
1 Word
N0, N1, N3, or R0 is entered in bit name for xx.

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0

nfi

Note:

Bit 15
Bit 15
Bit 15
Bit 15
Bit 15

de

N0PNB
N1PNB
N2PNB
N3PNB
R0PNB

Character number supplement bit (N0CNSM, N1CNSM, N2CNSM, N3CNSM, R0CNSM)

Designates the character number supplement mode when the pattern name data
size in the pattern name table is 1-word.
180030H
180032H
180034H
180036H
180038H

xxCNSM

Character Number
Auxiliary Mode

Process

0

0

1

1

Character number in pattern name data is 10 bits.
Flip function can be selected in character units.
Character number in pattern name data is 12 bits.
Flip function cannot be used.

GA

N0, N1, N2, N3, or R0 is entered in bit name for xx.

SE

Note:

346

Bit 14
Bit 14
Bit 14
Bit 14
Bit 14Co

N0CNSM
N1CNSM
N2CNSM
N3CNSM
R0CNSM

For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0

Special priority bit (for pattern name supplement data): Supplement special priority bit(N0SPR, N1SPR, N2SPR, N3SPR, R0SPR)

N0SPR
N1SPR
N2SPR
N3SPR
R0SPR

180030H
180032H
180034H
180036H
180038H

Bit 9
Bit 9
Bit 9
Bit 9
Bit 9

nti
al

Designates the pattern name supplement data as the special priority bit when thepattern name data size is 1-word.
For NBG0 (or RBG1)For NBG1
For NBG2
For NBG3
For RBG0

Special color calculation bit (for pattern name supplement data): Supplementary
special color calculation bit (N0SCC, N1SCC, N2SCC, N3SCC, R0SCC)

180030H
180032H
180034H
180036H
180038H

Bit 8
Bit 8
Bit 8
Bit 8
Bit 8

nfi

N0SCC
N1SCC
N2SCC
N3SCC
R0SCC

de

The special color calculation bit is designated as pattern name supplement datawhen the pattern name data size is 1-word.

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0

Supplementary palette number bit (N0SPLT6 to N0SPLT4, N1SPLT6 to N1SPLT4,N2SPLT6 to N2SPLT4, N3SPLT6 to N3SPLT4, R0SPLT6 to R0SPLT4)

Designates the palette number bit as pattern name supplement data when thepattern name data size is 1-word. Three bits are added to the palette number bit of
the pattern name data for the supplementary palette number bit.
180030H
180032H
180034H
180036H
180038HCo

N0SPLT6~N0SPLT4N1SPLT6~N1SPLT4N2SPLT6~N2SPLT4N3SPLT6~N3SPLT4R0SPLT6~R0SPLT4

Bit 7~5
Bit 7~5
Bit 7~5
Bit 7~5
Bit 7~5

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0SE

GA

Supplementary character number bit (N0SCN4 to N0SCN0, N1SCN4 to N1SCN0,N2SCN4 to N2SCN0, N3SCN4 to N3SCN0, R0SCN4 to R0SCN0)

ST-58-R2

347

N0SCN4~N0SCN0N1SCN4~N1SCN0
N2SCN4~N2SCN0
N3SCN4~N3SCN0
R0SCN4~R0SCN0180030H
180032H
180034H
180036H
180038HntialDesignates the character number bit as the pattern name supplement data when thepattern name data size is 1-word. Five bits are added to the palette number bit of thepattern name data for the supplementary palette number bit.
Bit 4~0
Bit 4~0
Bit 4~0
Bit 4~0
Bit 4~0

For NBG0 (or RBG 1)
For NBG1
For NBG2
For NBG3
For RBG0

Plane Size

de

PLSZ
18003AH

15
14
13
12
11
10
9
8
RBOVR1 RBOVR0 RBPLSZ1 RBPLSZ0 RAOVR1 RAOVR0 RAPLSZ1 RAPLSZ0
7
6
5
4
3
2
1
0
N3PLSZ1 N3PLSZ0 N2PLSZ1 N2PLSZ0 N1PLSZ1 N1PLSZ0 N0PLSZ1 N0PLSZ0

Plane size bit (N0PLSZ1, N0PLSZ0, N1PLSZ1, N1PLSZ0, N2PLSZ1, N2PLSZ0,N3PLSZ1, N3PLSZ0, RAPLSZ1, RAPLSZ0, RBPLSZ1, RBPLSZ0)

Designates the plane size (number of pages) of each scroll screen.

xxPLSZ1
00
1
1xxPLSZ001
01

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6
Bit 9,8
Bit 13,12

Plane Size
1 H Page X 1 V Page
2 H Pages X 1 V Page
Invalid (Do not set.)
2 H Pages X 2 V Pages

SE

GA

Note: N0, N1, N2, N3, RA, or RB is entered in bit name for xx.

348

For NBG0
For NBG1
For NBG2
For NBG3
For Rotation Parameter A
For Rotation Parameter B

nfi

18003AH
18003AH
18003AH
18003AH
18003AH
18003AHCo

N0PLSZ1, N0PLSZ0N1PLSZ1, N1PLSZ0N2PLSZ1, N2PLSZ0N3PLSZ1, N3PLSZ0RAPLSZ1, RAPLSZ0RBPLSZ1, RBPLSZ0

Screen-over process bit: Over bit (RAOVR1, RAOVR0, RBOVR1, RBOVR0)18003AH
18003AH

RxOVR10
0

RxOVR0
0
1

1
1

0
1

Note:

Bit 11,10
Bit 15,14

Screen Over Process
Outside the display area, the image set in the display area is repeated.
Outside the display area, the character pattern specified by screen overpattern name register is repeated. (Only when the rotation scroll screen
is in cell format.)Outside the display area, the scroll screen is transparent,
Set the display area as 0≤X≤512, 0≤Y≤512 regardless of plane size or
bitmap size and make that area transparent.

A or B is entered in bit name for x.

• Map Offset (NBG0~NBG3)
14
N3MP8
6
N1MP8

13
N3MP7
5
N1MP7

12
N3MP6
4
N1MP6

11
~
3
~

10
N2MP8
2
N0MP8

9
N2MP7
1
N0MP7

8
N2MP6
0
N0MP6

12
~
4
RBMP6

11
~
3
~

10
~
2
RAMP8

9
~
1
RAMP7

8
~
0
RAMP6

nfi

MPOFN
18003CH

15~
7~

For Rotation Parameter A
For Rotation Parameter BdeRAOVR1, RAOVR0
RBOVR1, RBOVR0

ntialDesignates control (screen-over process) when the display coordinate value exceeds
the display area in the rotation scroll screen.

• Map Offset (Rotation Parameter A, B)
15
~
7
~

14
~
6
RBMP8

13
~
5
RBMP7

Co

MPOFR
18003EH

Map offset bit (N0MP8 to N0MP6, N1MP8 to N1MP6, N2MP8 to N2MP6, N3MP8 to
N3MP6, RAMP8 to RAMP6, RBMP8 to RBMP6)GA

When the scroll screen display format is the cell format, the map offset value of 3
bits is added to the highest 6 bits of the map register. This designates the bit map
pattern boundary when in the bit map format.
18003CH
18003CH
18003CH
18003CH
18003EH
18003EH

Bit 2~0
Bit 6~4
Bit 10~8
Bit 14~12
Bit 2~0
Bit 6~4

For NBG0
For NBG1
For NBG2
For NBG3
For Rotation Parameter A
For Rotation Parameter B

SE

N0MP8~N0MP6
N1MP8~N1MP6
N2MP8~N2MP6
N3MP8~N3MP6
RAMP8~RAMP6
RBMP8~RBMP6

ST-58-R2

349

• Map (NBG0, Plane A, B)
15
~
7
~

14
~
6
~

13
N0MPB55
N0MPA512
N0MPB4
4
N0MPA4

11
N0MPB3
3
N0MPA3

10
N0MPB2
2
N0MPA29N0MPB1
1
N0MPA18
N0MPB00
N0MPA013
N0MPD55N0MPC512
N0MPD44N0MPC4

11
N0MPD3
3
N0MPC3

10
N0MPD2
2
N0MPC29N0MPD1
1
N0MPC18
N0MPD00
N0MPC013
N1MPB55
N1MPA512
N1MPB4
4
N1MPA411
N1MPB3
3
N1MPA3

10
N1MPB2
2
N1MPA29
N1MPB11
N1MPA18
N1MPB00
N1MPA013
N1MPD55N1MPC512
N1MPD44N1MPC4

11
N1MPD33
N1MPC3

10
N1MPD2
2
N1MPC29N1MPD1
1
N1MPC18
N1MPD00
N1MPC013
N2MPB55
N2MPA512
N2MPB4
4
N2MPA411
N2MPB3
3
N2MPA3

10
N2MPB22
N2MPA29
N2MPB1
1
N2MPA18
N2MPB00
N2MPA013
N2MPD55N2MPC512
N2MPD44N2MPC411
N2MPD3
3
N2MPC3

10
N2MPD22
N2MPC29
N2MPD1
1
N2MPC18
N2MPD00N2MPC013
N3MPB55
N3MPA512
N3MPB4
4
N3MPA411
N3MPB3
3
N3MPA3

10
N3MPB2
2
N3MPA29
N3MPB1
1
N3MPA1

8
N3MPB00
N3MPA0MPCDN0180042H

15
~
7
~

14
~
6
~

MPABN1
180044H

15
~
7
~

14
~
6
~

MPCDN1
180046H

15
~
7
~

14
~
6
~

• Map (NBG2, Plane A, B)
MPABN2180048H

15
~
7
~

14
~
6
~

Co

• Map (NBG1, Plane C, D)nfi• Map (NBG1, Plane A, B)de• Map (NBG0, Plane C, D)

ntial

MPABN0180040HMPCDN218004AHGA• Map (NBG2, Plane C, D)
15
~
7
~

14
~
6
~

SE

• Map (NBG3, Plane A, B)
MPABN318004CH

350

15
~
7
~

14
~
6
~

• Map (NBG3, Plane C, D)
15
~
7
~

14
~
6
~

13
N3MPD55
N3MPC512
N3MPD44N3MPC4

11
N3MPD33
N3MPC3

10
N3MPD2
2
N3MPC29N3MPD1
1
N3MPC1

8
N3MPD00N3MPC0nti
al

MPCDN318004EH

Map bit (for normal scroll): (N0MPA5 to N0MPA0, N0MPB5 to N0MPB0,
N0MPC5 to N0MPC0, N0MPD5 to N0MPD0, N1MPA5 to N1MPA0, N1MPB5 to
N1MPB0, N1MPC5 to N1MPC0, N1MPD5 to N1MPD0, N2MPA5 to N2MPA0, N2MPB5
to N2MPB0, N2MPC5 to N2MPC0, N2MPD5 to N2MPD0, N3MPA5 to N3MPA0,N3MPB5 to N3MPB0, N3MPC5 to N3MPC0, N3MPD5 to N3MPD0)

Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8nfi

Co180040H
180040H
180042H
180042H
180044H
180044H
180046H
180046H
180048H
180048H
18004AH
18004AH
18004CH
18004CH
18004EH
18004EH

For NBG0 Plane A
For NBG0 Plane B
For NBG0 Plane C
For NBG0 Plane D
For NBG1 Plane A
For NBG1 Plane B
For NBG1 Plane C
For NBG1 Plane D
For NBG2 Plane A
For NBG2 Plane B
For NBG2 Plane C
For NBG2 Plane D
For NBG3 Plane A
For NBG3 Plane B
For NBG3 Plane C
For NBG3 Plane DSE

GA

N0MPA5~N0MPA0N0MPB5~N0MPB0N0MPC5~N0MPC0N0MPD5~N0MPD0N1MPA5~N1MPA0N1MPB5~N1MPB0N1MPC5~N1MPC0N1MPD5~N1MPD0N2MPA5~N2MPA0N2MPB5~N2MPB0
N2MPC5~N2MPC0
N2MPD5~N2MPD0N3MPA5~N3MPA0N3MPB5~N3MPB0
N3MPC5~N3MPC0
N3MPD5~N3MPD0

deWhen the Normal scroll screen is displayed by the cell format, the lead address forthe pattern name table is designated for each plane.

ST-58-R2

351

• Map (Rotation Parameter A, Plane A, B)
14
~
6
~

13
RAMPB55RAMPA5

12
RAMPB4
4RAMPA4

11
RAMPB3
3
RAMPA3

10
RAMPB2
2
RAMPA2

9RAMPB1
1
RAMPA1

8
RAMPB00RAMPA011
RAMPD3
3
RAMPC310
RAMPD2
2
RAMPC2

9RAMPD1
1
RAMPC1

8
RAMPD00RAMPC0MPCDRA
180052H

15
~
7
~

14
~
6
~

13
RAMPD5
5RAMPC512
RAMPD4
4RAMPC4• Map (Rotation Parameter A, Plane E, F)
15
~
7
~

14
~
6
~

13
RAMPF55RAMPE512
RAMPF4
4RAMPE411
RAMPF3
3
RAMPE310
RAMPF2
2
RAMPE2

11
RAMPH3
3
RAMPG31098RAMPH2 RAMPH1 RAMPH0210
RAMPG2 RAMPG1 RAMPG011
RAMPJ3
3
RAMPI3

10
RAMPJ2
2
RAMPI2

9RAMPJ1
1
RAMPI1

8
RAMPJ00
RAMPI011
RAMPL3
3
RAMPK310
RAMPL2
2
RAMPK2

9RAMPL1
1
RAMPK1

8
RAMPL00RAMPK0nfi

MPEFRA
180054Hde• Map (Rotation Parameter A, Plane C, D)

ntial

MPBRAB
180050H

15
~
7
~

9
RAMPF1
1
RAMPE1

8
RAMPF00
RAMPE0• Map (Rotation Parameter A, Plane G, H)
15
~
7
~

14
~
6
~

13
12
RAMPH5 RAMPH454RAMPG5 RAMPG4Co

MPGHRA
180056H• Map (Rotation Parameter A, Plane I, J)MPIJRA
180058H

15
~
7
~

14
~
6
~

13
RAMPJ5
5
RAMPI5

12
RAMPJ4
4
RAMPI4MPKLRA
18005AHGA• Map (Rotation Parameter A, Plane K, L)
15
~
7
~

14
~
6
~

13
RAMPL55RAMPK5

12
RAMPL4
4
RAMPK4SE• Map (Rotation Parameter A, Plane M, N)
MPMNRA
18005CH

352

15
~
7
~

14
~
6
~

13
12
11
10
9
8
RAMPN5 RAMPN4 RAMPN3 RAMPN2 RAMPN1 RAMPN0
5
4
3
2
1
0
RAMPM5 RAMPM4 RAMPM3 RAMPM2 RAMPM1 RAMPM0• Map (Rotation Parameter A, Plane O, P)
15
~
7
~

14
~
6
~

13
12
RAMPP5 RAMPP454RAMPO5 RAMPO4• Map (Rotation Parameter B, Plane A, B)
14
~
6
~

13
RBMPB5
5
RBMPA5

12
RBMPB4
4
RBMPA4

11
RBMPB3
3
RBMPA3

10
RBMPB2
2
RBMPA2de

MPABRB
180060H

15
~
7
~

11
10
9
8
RAMPP3 RAMPP2 RAMPP1 RAMPP03210RAMPO3 RAMPO2 RAMPO1 RAMPO0ntial

MPOPRA
18005EH

9
RBMPB1
1
RBMPA1

8
RBMPB00
RBMPA0• Map (Rotation Parameter B, Plane C, D)
15
~
7
~

14
~
6
~

13
RBMPD55
RBMPC5

12
RBMPD4
4
RBMPC4

11
RBMPD3
3
RBMPC3

10
RBMPD2
2
RBMPC2

9
RBMPD1
1
RBMPC1

8
RBMPD00
RBMPC011
RBMPF3
3
RBMPE3

10
RBMPF2
2
RBMPE2

9
RBMPF1
1
RBMPE1

8
RBMPF00
RBMPE0nfi

MPCDRB
180062H• Map (Rotation Parameter B, Plane E, F)
15
~
7
~

14
~
6
~

13
RBMPF5
5
RBMPE5

12
RBMPF4
4
RBMPE4Co

MPEFRB
180064H• Map (Rotation Parameter B, Plane G, H)
MPGHRB
180066H

15
~
7
~

14
~
6
~

13
12
RBMPH5 RBMPH454
RBMPG5 RBMPG4

11
10
9
8
RBMPH3 RBMPH2 RBMPH1 RBMPH03210
RBMPG3 RBMPG2 RBMPG1 RBMPG0

GA• Map (Rotation Parameter B, Plane I, J)MPIJRB
180068H

15
~
7
~

14
~
6
~

13
RBMPJ5
5
RBMPI5

12
RBMPJ4
4
RBMPI4

11
RBMPJ3
3
RBMPI3

10
RBMPJ2
2
RBMPI2

9
RBMPJ1
1
RBMPI1

8
RBMPJ00
RBMPI011
RBMPL3
3
RBMPK3

10
RBMPL2
2
RBMPK2

9
RBMPL1
1
RBMPK1

8
RBMPL00
RBMPK0SE• Map (Rotation Parameter B, Plane K, L)
MPKLRB
18006AH

ST-58-R2

15
~
7
~

14
~
6
~

13
RBMPL55
RBMPK5

12
RBMPL4
4
RBMPK4353

• Map (Rotation Parameter B, Plane M, N)
15
~
7
~

14
~
6
~

13
12
11
10
9
8
RBMPN5 RBMPN4 RBMPN3 RBMPN2 RBMPN1 RBMPN0
5
4
3
2
1
0
RBMPM5 RBMPM4 RBMPM3 RBMPM2 RBMPM1 RBMPM0• Map (Rotation Parameter B, Plane O, P)
15
~
7
~

14
~
6
~

13
12
RBMPP5 RBMPP45
4RBMPO5 RBMPO4

11
RBMPP3
3
RBMPO310
9
8
RBMPP2 RBMPP1 RBMPP02
10
RBMPO2 RBMPO1 RBMPO0de

MPOPRB
18006EH

ntial

MPMNRB
18006CHnfi

Map bit (for rotation scroll): Map bit (RAMPA5 to RAMPA0, RAMPB5 to RAMPB0,RAMPC5 to RAMPC0, RAMPD5 to RAMPD0, RAMPE5 to RAMPE0,
RAMPF5 to RAMPF0, RAMPG5 to RAMPG0, RAMPH5 to RAMPH0,
RAMPI5 to RAMPI0, RAMPJ5 to RAMPJ0, RAMPK5 to RAMPK0,
RAMPL5 to RAMPL0, RAMPM5 to RAMPM0, RAMPN5 to RAMPN0,RAMPO5 to RAMPO0, RAMPP5 to RAMPP0, RBMPA5 to RBMPA0,RBMPB5 to RBMPB0, RBMPC5 to RBMPC0, RBMPD5 to RBMPD0,RBMPE5 to RBMPE0, RBMPF5 to RBMPF0, RBMPG5 to RBMPG0,
RBMPH5 to RBMPH0, RAMPI5 to RBMPI0, RBMPJ5 to RBMPJ0,RBMPK5 to RBMPK0, RBMPL5 to RBMPL0, RBMPM5 to RBMPM0,
RBMPN5 to RBMPN0, RBMPO5 to RBMPO0, RBMPP5 to RBMPP0)

SE

GA

Co

Designates the lead address of the pattern name table being arranged in each plane
when a rotation scroll screen is displayed in the cell format.

354

nti
al

Rotation Parameter A for Screen Plane A
Rotation Parameter A for Screen Plane B
Rotation Parameter A for Screen Plane C
Rotation Parameter A for Screen Plane D
Rotation Parameter A for Screen Plane E
Rotation Parameter A for Screen Plane F
Rotation Parameter A for Screen Plane G
Rotation Parameter A for Screen Plane H
Rotation Parameter A for Screen Plane I
Rotation Parameter A for Screen Plane J
Rotation Parameter A for Screen Plane K
Rotation Parameter A for Screen Plane L
Rotation Parameter A for Screen Plane M
Rotation Parameter A for Screen Plane N
Rotation Parameter A for Screen Plane O
Rotation Parameter A for Screen Plane P
Rotation Parameter B for Screen Plane A
Rotation Parameter B for Screen Plane B
Rotation Parameter B for Screen Plane C
Rotation Parameter B for Screen Plane D
Rotation Parameter B for Screen Plane E
Rotation Parameter B for Screen Plane F
Rotation Parameter B for Screen Plane G
Rotation Parameter B for Screen Plane H
Rotation Parameter B for Screen Plane I
Rotation Parameter B for Screen Plane J
Rotation Parameter B for Screen Plane K
Rotation Parameter B for Screen Plane L
Rotation Parameter B for Screen Plane M
Rotation Parameter B for Screen Plane N
Rotation Parameter B for Screen Plane O
Rotation Parameter B for Screen Plane P

deBit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8
Bit 5~0
Bit 13~8nfi

180050H
180050H
180052H
180052H
180054H
180054H
180056H
180056H
180058H
180058H
18005AH
18005AH
18005CH
18005CH
18005EH
18005EH
180060H
180060H
180062H
180062H
180064H
180064H
180066H
180066H
180068H
180068H
18006AH
18006AH
18006CH
18006CH
18006EH
18006EH

SE

GA

Co

RAMPA5~RAMPA0RAMPB5~RAMPB0RAMPC5~RAMPC0RAMPD5~RAMPD0RAMPE5~RAMPE0
RAMPF5~RAMPF0
RAMPG5~RAMPG0
RAMPH5~RAMPH0RAMPI5~RAMPI0RAMPJ5~RAMPJ0RAMPK5~RAMPK0RAMPL5~RAMPL0
RAMPM5~RAMPM0
RAMPN5~RAMPN0RAMPO5~RAMPO0RAMPP5~RAMPP0RBMPA5~RBMPA0
RBMPB5~RBMPB0
RBMPC5~RBMPC0
RBMPD5~RBMPD0
RBMPE5~RBMPE0
RBMPF5~RBMPF0
RBMPG5~RBMPG0
RBMPH5~RBMPH0
RBMPI5~RBMPI0
RBMPJ5~RBMPJ0RBMPK5~RBMPK0
RBMPL5~RBMPL0
RBMPM5~RBMPM0
RBMPN5~RBMPN0
RBMPO5~RBMPO0RBMPP5~RBMPP0

ST-58-R2

355

SCXIN0180070H

15~
7
N0SCXI7

14~
6
N0SCXI6

13~
5
N0SCXI512~4
N0SCXI41110
9~N0SCXI10 N0SCXI9321
N0SCXI3 N0SCXI2 N0SCXI1• Screen Scroll Value (NBG0, Horizontal Fractional Part)• Screen Scroll Value (NBG0, Vertical Integer Part)
15~
7
N0SCYI7

14~
6
N0SCYI6

13~
5
N0SCYI512~4
N0SCYI41110
9~N0SCYI10 N0SCYI932
1
N0SCYI3 N0SCYI2 N0SCYI1nfi

SCYIN0180074H

8
N0SCXI80
N0SCXI0

15
14
13
12
11
10
9
8
N0SCXD1 N0SCXD2 N0SCXD3 N0SCXD4 N0SCXD5 N0SCXD6 N0SCXD7 N0SCXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

de

SCXDN0180072Hntial• Screen Scroll Value (NBG0, Horizontal Integer Part)

8
N0SCYI80
N0SCYI0• Screen Scroll Value (NBG0, Vertical Fractional Part)

15
14
13
12
11
10
9
8
N0SCYD1 N0SCYD2 N0SCYD3 N0SCYD4 N0SCYD5 N0SCYD6 N0SCYD7 N0SCYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

Co

SCYDN0180076H• Coordinate Increment (NBG0, Horizontal Integer Part)ZMXIN0180078H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N0ZMXI2 N0ZMXI1 N0ZMXI0ZMXDN018007AHGA• Coordinate Increment (NBG0, Horizontal Fractional Part)
15
14
13
12
11
10
9
8
N0ZMXD1 N0ZMXD2 N0ZMXD3 N0ZMXD4 N0ZMXD5 N0ZMXD6 N0ZMXD7 N0ZMXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

SE

• Coordinate Increment (NBG0, Vertical Integer Part)ZMYIN018007CH

356

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N0ZMYI2 N0ZMYI1 N0ZMYI0• Coordinate Increment (NBG0, Vertical Fractional Part)
15
14
13
12
11
10
9
8
N0ZMYD1 N0ZMYD2 N0ZMYD3 N0ZMYD4 N0ZMYD5 N0ZMYD6 N0ZMYD7 N0ZMYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

nti
al

ZMYDN018007EH• Screen Scroll Value (NBG1, Horizontal Integer Part)
15~
7
N1SCXI7

14~
6
N1SCXI6

13~
5
N1SCXI512~4N1SCXI41110
9~N1SCXI10 N1SCXI9321
N1SCXI3 N1SCXI2 N1SCXI18N1SCXI80N1SCXI0de

SCXIN1
180080H• Screen Scroll Value (NBG1, Horizontal Fractional Part)

15
14
13
12
11
10
9
8
N1SCXD1 N1SCXD2 N1SCXD3 N1SCXD4 N1SCXD5 N1SCXD6 N1SCXD7 N1SCXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

nfi

SCXDN1
180082H• Screen Scroll Value (NBG1, Vertical Integer Part)
14~
6N1SCYI613~5N1SCYI512~4N1SCYI4Co

SCYIN1
180084H

15~
7N1SCYI711109~N1SCYI10 N1SCYI9321
N1SCYI3 N1SCYI2 N1SCYI18N1SCYI80
N1SCYI0• Screen Scroll Value (NBG1, Vertical Fractional Part)SCYDN1
180086H

15
14
13
12
11
10
9
8
N1SCYD1 N1SCYD2 N1SCYD3 N1SCYD4 N1SCYD5 N1SCYD6 N1SCYD7 N1SCYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

GA

• Coordinate Increment (NBG1, Horizontal Integer Part)
15
~
7
~

ZMXIN1
180088H

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
9
8
~
~
~
2
1
0
N1ZMXI2 N1ZMXI1 N1ZMXI0

SE• Coordinate Increment (NBG1, Horizontal Fractional Part)ZMXDN1
18008AH

ST-58-R2

15
14
13
12
11
10
9
8
N1ZMXD1 N1ZMXD2 N1ZMXD3 N1ZMXD4 N1ZMXD5 N1ZMXD6 N1ZMXD7 N1ZMXD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

357

• Coordinate Increment (NBG1, Vertical Integer Part)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

• Coordinate Increment (NBG1, Vertical Fractional Part)

15
14
13
12
11
10
9
8
N1ZMYD1 N1ZMYD2 N1ZMYD3 N1ZMYD4 N1ZMYD5 N1ZMYD6 N1ZMYD7 N1ZMYD8
7
6
5
4
3
2
1
0
~
~
~
~
~
~
~
~

• Screen Scroll Value (NBG2, Horizontal)
15~
7
N2SCX714~
6
N2SCX613~
5
N2SCX512~
4N2SCX411~
3
N2SCX310
N2SCX102
N2SCX29
N2SCX91
N2SCX18N2SCX80N2SCX012~4N2SCY411~
3
N2SCY310
N2SCY102
N2SCY29N2SCY91
N2SCY18N2SCY80N2SCY012~
4N3SCX4

11~
3
N3SCX310
N3SCX10
2
N3SCX29N3SCX91
N3SCX18
N3SCX80N3SCX012~4N3SCY411~
3
N3SCY310
N3SCY102
N3SCY29N3SCY91
N3SCY18
N3SCY80N3SCY0nfi

SCXN2
180090H• Screen Scroll Value (NBG2, Vertical)
14~
6
N2SCY613~
5N2SCY5Co

SCYN2180092H

15~
7
N2SCY7de

ZMYDN1
18008EH

10
9
8
~
~
~
2
1
0
N1ZMYI2 N1ZMYI1 N1ZMYI0nti
alZMYIN1
18008CH• Screen Scroll Value (NBG3, Horizontal)
SCXN3
180094H

15~
7
N3SCX714~
6
N3SCX613~
5
N3SCX5SCYN3180096HGA• Screen Scroll Value (NBG3, Vertical)
15~
7
N3SCY714~
6N3SCY613~
5N3SCY5SE

Screen scroll value bit: Scroll bit (N0SCXI10 to N0SCXI0, N0SCXD1 to
N0SCXD8, N0SCYI10 to N0SCYI0, N0SCYD1 to N0SCYD8, N1SCXI10 to N1SCXI0,N1SCXD1 to N1SCXD8, N1SCYI10 to N1SCYI0, N1SCYD1 to N1SCYD8, N2SCX10 toN2SCX0, N2SCY10 to N2SCY0, N3SCX10 to N3SCX0, N3SCY10 to N3SCY0)

Designates the horizontal and vertical screen scroll values (coordinate values) of theNormal scroll screen.

358

180070H
180072H
180074H
180076H
180080H
180082H
180084H
180086H
180090H
180092H
180094H
180096H

Bit 10~0
Bit 15~8
Bit 10~0
Bit 15~8
Bit 10~0
Bit 15~8
Bit 10~0
Bit 15~8
Bit 10~0
Bit 10~0
Bit 10~0
Bit 10~0

For NBG0 horizontal direction (integer part)
For NBG0 horizontal direction (fractional part)
For NBG0 vertical direction (integer part)
For NBG0 vertical direction (fractional part)
For NBG1 horizontal direction (integer part)
For NBG1 horizontal direction (fractional part)
For NBG1 vertical direction (integer part)
For NBG1 vertical direction (fractional part)
For NBG2 horizontal direction
For NBG2 vertical direction
For NBG3 horizontal direction
For NBG3 vertical direction

nti
al

N0SCXI10~N0SCXI0N0SCXD1~N0SCXD8N0SCYI10~N0SCYI0
N0SCYD1~N0SCYD8N1SCXI10~N1SCXI0N1SCXD1~N1SCXD8N1SCYI10~N1SCYI0N1SCYD1~N1SCYD8N2SCX10~N2SCX0N2SCY10~N2SCY0N3SCX10~N3SCX0
N3SCY10~N3SCY0de

Coordinate increment bit: Zoom bit (N0ZMXI2 to N0ZMXI0, N0ZMXD1 to
N0ZMXD8, N0ZMYI2 to N0ZMYI0, N0ZMYD1 to N0ZMYD8, N1ZMXI2 to N1ZMXI0,
N1ZMXD1 to N1ZMXD8, N1ZMYI2 to N1ZMYI0, N1ZMYD1 to N1ZMYD8)

Designates horizontal and vertical coordinate increments for calculating display
coordinates when expanding and reducing all Normal scroll screens.
180078H
18007AH
18007CH
18007EH
180088H
18008AH
18008CH
18008EH

ZMCTL
180098H

15
~
7
~

Co

• Reduction EnableBit 2~0
Bit 15~8
Bit 2~0
Bit 15~8
Bit 2~0
Bit 15~8
Bit 2~0
Bit 15~8

14~
6~For NBG0 horizontal direction (integer part)
For NBG0 horizontal direction (fractional part)
For NBG0 vertical direction (integer part)
For NBG0 vertical direction (fractional part)
For NBG1 horizontal direction (integer part)
For NBG1 horizontal direction (fractional part)
For NBG1 vertical direction (integer part)
For NBG1 vertical direction (fractional part)

nfi

N0ZMXI2~N0ZMXI0N0ZMXD1~N0ZMXD8N0ZMYI2~N0ZMYI0
N0ZMYD1~N0ZMYD8N1ZMXI2~N1ZMXI0N1ZMXD1~N1ZMXD8N1ZMYI2~N1ZMYI0N1ZMYD1~N1ZMYD8

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
~

9
N1ZMQT
1
N0ZMQT

8
N1ZMHF
0N0ZMHF

Reduction enable bit: Zoom quarter/half bit (N1ZMQT, N1ZMHF, N0ZMQT, N0ZMHF)

SEGA

Designates the maximum reducible range of each Normal scroll screen in thehorizontal direction.

ST-58-R2

359

180098H
180098H
180098H
180098H

Bit 0
Bit 1
Bit 8
Bit 9

NxZMQT
00

NxZMHF
0
1

Horizontal Reduction Display
Not allowed
Up to 1/2

10

Up to 1/4

1

1

Up to 1/4

Restriction Items
None
The number of character colors can be
set for 16 or 256 colors only.
The number of character colors can be
set for 16 colors only.
The number of character colors can be
set for 16 colors only.

0 or 1 is entered in bit name for x.

de

Note:

For NBG0
For NBG0
For NBG1
For NBG1nti
al

N0ZMHF
N0ZMQT
N1ZMHF
N1ZMQT• Line and Vertical Cell Scroll Control (NBG0, NBG1)
14
~
6
~

13
N1LSS1
5
N0LSS112N1LSS04
N0LSS011
N1LZMX
3
N0LZMX

10
N1LSCY
2
N0LSCY

9N1LSCX
1
N0LSCX

8
N1VCSC0
N0VCSC

nfi

15
~
7
~

SCRCTL
18009AH

Line Scroll Interval Bit: Line scroll select bit (N0LSS1, N0LSS0, N1LSS1, N1LSS0)

Designates the interval that reads line scroll table data from the table. The intervalchanges depending on the interlace of the TV screen.

NxLSS1
0
0
1
1
Note:

18009AH
18009AHNxLSS00
1
0
1

Bit 5, 4
Bit 13,12Co

N0LSS1, N0LSS0N1LSS1, N1LSS0

Non-Interlace
Each line
Every 2 lines
Every 4 lines
Every 8 lines

Interlace Setting
Single-Density Interlace
Every 2 lines
Every 4 lines
Every 8 lines
Every 16 lines

For NBG0
For NBG1

Double-Density Interlace
Each line
Every 2 lines
Every 4 lines
Every 8 lines

0 or 1 is entered in bit name for x.

GA

Line zoom enable bit: Line zoom X enable bit (N1LZMX, N0LZMX)

Designates whether expansion-reduction is done horizontally in line units.
18009AH
18009AHSE

N0LZMX
N1LSCX360

Bit 3
Bit 11For NBG0
For NBG1

Note:

Process
Does not scale horizontally per line units
Scales horizontally per line units

0 or 1 is entered in bit name for x.

nti
al

NxLZMX
0
1

Line scroll enable bit (for the vertical screen scroll value): Line scroll Y enable bit(N1LSCY, N0LSCY)

Designates whether scroll is performed by vertical line units.
18009AH
18009AH

Bit 2
Bit 10NxLSCY
01
Note:

For NBG0
For NBG1

Process
Does not scroll vertically per line units
Scrolls vertically per line units

0 or 1 is entered in bit name for x.

de

N0LSCYN1LSCYLine scroll enable bit (for the horizontal screen scroll value): Line scroll X enable bit(N1LSCX, N0LSCX)

Designates whether scroll is performed by horizontal line units.
18009AH
18009AH

NxLSCX
0
1

For NBG0
For NBG1

Process
Does not scroll horizontally per line units
Scrolls horizontally per line units

0 or 1 is entered in bit name for x.

Co

Note:

Bit 1
Bit 9

nfi

N0LSCX
N1LSCX

Vertical cell scroll enable bit (N1VCSC, N0VCSC)

Designates whether to perform vertical cell scroll.
N0VCSCN1VCSCGA

NxVCSC0118009AH
18009AH

For NBG0
For NBG1

Process
Does not cell-scroll vertically
Cell-scrolls vertically0 or 1 is entered in bit name for x.

SE

Note:

Bit 0
Bit 8

ST-58-R2

361

• Vertical Cell Scroll Table Address (NBG0, NBG1)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

• Vertical Cell Scroll Table Address (NBG0, NBG1)

15
14
13
12
11
10
VCSTA15 VCSTA14 VCSTA13 VCSTA12 VCSTA11 VCSTA10
7
6
5
4
3
2
VCSTA7 VCSTA6 VCSTA5 VCSTA4 VCSTA3 VCSTA29VCSTA91
VCSTA1

8
VCSTA80~de

VCSTAL
18009EH

10
9
8
~
~
~
2
1
0
VCSTA18 VCSTA17 VCSTA16ntial

VCSTAU
18009CH

Vertical cell scroll table address bit (VCSTA18 to VCSTA1),

Designates the lead address of the vertical cell scroll table on the VRAM.
18009CH
18009EH

Bit 2~0
Bit 15~1• Line Scroll Table Address (NBG0)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

Co

LSTA0U
1800A0Hnfi

VCSTA18~VCSTA16
VCSTA15~VCSTA1

10
~
2

9
~
1

8
~
0

N0LSTA18 N0LSTA17 N0LSTA16• Line Scroll Table Address (NBG0)
15
LSTA0L
1800A2H

14

13

12

11

10

N0LSTA15 N0LSTA14 N0LSTA13 N0LSTA12 N0LSTA11 N0LSTA1076N0LSTA7

N0LSTA69

8

N0LSTA9N0LSTA8

5

4

3

2

1

N0LSTA5N0LSTA4

N0LSTA3

N0LSTA2

N0LSTA1

0
~

12
~
4
~

11
~
3
~

10
~
2

9
~
1

8
~
0

12

11

LSTA1U
1800A4HGA• Line Scroll Table Address (NBG1)
15
~
7
~

14
~
6
~

13
~
5
~

N1LSTA18 N1LSTA17 N1LSTA16• Line Scroll Table Address (NBG1)
15SELSTA1L
1800A6H

14

362

13

10

N1LSTA15 N1LSTA14 N1LSTA13 N1LSTA12 N1LSTA11 N1LSTA1098N1LSTA9N1LSTA8

0
~

7

6

5

4

3

2

1

N1LSTA7

N1LSTA6N1LSTA5N1LSTA4

N1LSTA3

N1LSTA2

N1LSTA1

Line scroll table address bit (N0LSTA18 to N0LSTA16, N0LSTA15 to N0LSTA1,N1LSTA18 to N1LSTA16, N1LSTA15 to N1LSTA1)

N0LSTA18~N0LSTA16
N0LSTA15~N0LSTA1
N1LSTA18~N1LSTA16
N1LSTA15~N1LSTA1

1800A0H
1800A2H
1800A4H
1800A6Hnti
alDesignates the lead address of the line scroll table on the VRAM.
Bit 2~0
Bit 15~1
Bit 2~0
Bit 15~1

For NBG0 (upper bit)
For NBG0 (lower bit)
For NBG1 (upper bit)
For NBG1 (lower bit)

• Line Color Screen Table Address
15
LCCLMD
7
~

14
~
6
~

13
~
5
~

• Line Color Screen Table Address
15
LCTA157LCTA714LCTA146LCTA613LCTA13
5
LCTA5

11
~
3
~

10
~
2
LCTA189~1
LCTA17

8~
0
LCTA16

12
LCTA12
4LCTA4

11LCTA11
3LCTA3

10LCTA10
2
LCTA2

9
LCTA9
1
LCTA1

8
LCTA8
0
LCTA0

nfi

LCTAL
1800AAH

12
~
4
~

de

LCTAU
1800A8H

Line color screen mode bit: LNCL color mode bit (LCCLMD), bit 15

LCCLMD
0
1

Co

Designates the color mode of the line color screen.

Line Color Screen Color
Single color
Select per each line

Line color screen table address bit: LNCL table address bit (LCTA18 to LCTA0)

Designates the lead address of the line color screen table on the VRAM.
LCTA18~LCTA16LCTA15~LCTA0

1800A8H
1800AAH

Bit 2~0
Bit 15~0

GA• Back Screen Table Address
15
BKCLMD
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
BKTA189~1
BKTA178~0
BKTA16SE

BKTAU
1800ACHST-58-R2

363

• Back Screen Table Address
15
BKTA157BKTA714BKTA146BKTA613
BKTA135BKTA512BKTA12
4BKTA4

11
BKTA11
3
BKTA3

10
BKTA102
BKTA2

Back screen color mode bit: BACK color mode bit (BKCLMD), bit 15

Designates color mode of the back screen.
Back Screen Color
Single color
Select per each line

8
BKTA8
0
BKTA0

de

BKCLMD
0
1

9
BKTA9
1
BKTA1

nti
al

BKTAL
1800AEH

Back screen table address bit: BACK color table address bit (BKTA18 to BKTA0)

Designates the lead address of the back screen table on the VRAM.
1800ACH
1800AEH

Bit 2~0
Bit 15~0• Rotation Parameter Mode
RPMD
1800B0H

15
~
7
~

14
~
6
~

13
~
5
~

nfi

BKTA18~BKTA16BKTA 15~BKTA0

12
~
4
~

11
~
3
~

10
~
2
~

9
~
1
RPMD1

8
~
0
RPMD0

Co

Rotation parameters mode bit (RPMD1, RPMD0), bits 1 and 0

When displaying RGB0, designates which rotation parameter of A or B will be used.
RPMD0
0
1
0

Mode
0
1
2

1

1

3

GA

RPMD1
0
0
1

Rotation Parameter
Rotation Parameter A
Rotation Parameter B
A screen and B screen are switched via
coefficient data read from rotation parameter A
coefficient table.
A screen and B screen are switched via
rotation parameter window• Rotation Parameter Read Control
15
~
7
~

SE

RPRCTL
1800B2H

364

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10

9

RBKASTRE RBYSTRE

2

1

RAKASTRE RAYSTRE

8
RBXSTRE0
RAXSTRE

Parameter read enable bit (RAXSTRE, RBXSTRE, RAYSTRE, RBYSTRE, RAKASTRE,
RBKASTRE)

1800B2H
1800B2H
1800B2H
1800B2H
1800B2H
1800B2H

Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 10For Xst of Rotation Parameter A
For Xst of Rotation Parameter B
For Yst of Rotation Parameter A
For Yst of Rotation Parameter B
For KAst of Rotation Parameter A
For KAst of Rotation Parameter B

RxSTRE
01
Note:

Process
Selected parameters are not read for that line
Selected parameters are read for that linede

RAXSTRE
RBXSTRERAYSTRE
RBYSTRERAKASTRE
RBKASTRE

ntialDesignates the coefficient table start address KAst and TV screen start coordinates Xst
and Yst and whether to read from the rotation parameter table in that line.

AX, BX, AY, BY, AKA, or BKA is entered in bit name for x.

• Coefficient Table Control
15
~
7
~

14
~
6
~

13
~
5
~

12
RBKLCE
4RAKLCE

11
RBKMD1
3
RAKMD1nfi

KTCTL
1800B4H

10
RBKMD02
RAKMD09
RBKDBS1RAKDBS

8
RBKTE
0
RAKTE

Coefficient line color enable bit (RAKLCE, RBKLCE)

Designates whether to use line color screen data in coefficient data.

RxKLCE
01
Note:

1800B4H
1800B4HCo

RAKLCERBKLCE

Bit 4
Bit 12For Rotation Parameter A
For Rotation Parameter B

Process
Line color screen data within coefficient data is not usedLine color screen data within coefficient data is used

A or B is entered in the bit name for x.

GA

Coefficient data mode bit: Coefficient mode bit (RAKMD1, RAKMD0, RBKMD1,
RBKMD0)Designates what parameters the coefficient data is used as.
1800B4H
1800B4H

Bit 3,2
Bit 11,10

For Rotation Parameter A
For Rotation Parameter B

SE

RAKMD1, RAKMD0
RBKMD1, RBKMD0ST-58-R2

365

Note:

RxKMD0
0
1
0
1

Mode
0
1
2
3

Coefficient Data Function
Use as scale coefficient kx, ky
Use as scale coefficient kx
Use as scale coefficient ky
Use as viewpoint Xp after rotation conversion

A or B is entered in the bit name for x.

Coefficient data size bit (RAKDBS, RBKDBS)

Designates the size of the coefficient data.
RAKDBSRBKDBS

1800B4H
1800B4H

Bit 1
Bit 9

Note:

Coefficient Data Size
2 Words
1 WordA or B is entered in the bit name for x.

Coefficient table enable bit (RAKTE, RBKTE)

RAKTE
RBKTE

1800B4H
1800B4H

nfi

Designates whether the coefficient table is used.
Bit 0
Bit 8

RxKTE
0
1

For Rotation Parameter A
For Rotation Parameter B

Process
Do not use coefficient table
Use coefficient table

A or B is entered in the bit name for x.

Co

Note:

For Rotation Parameter A
For Rotation Parameter BdeRxKDBS
01

nti
al

RxKMD100
1
1• Coefficient Table Address Offset (Rotation Parameter A, B)
KTAOF
1800B6H

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10

9

8

RBKTAOS2 RBKTAOS1 RBKTAOS0

2

1

0

RAKTAOS2 RAKTAOS1 RAKTAOS0

GA

Coefficient table address offset bit (RAKTAOS2 to RAKTAOS0, RBKTAOS2 toRBKTAOS0)SE

Designates the lead address offset value of the coefficient table stored in the rotation
parameter table.

366

1800B6H
1800B6H

Bit 2~0
Bit 10~8

For Rotation Parameter A
For Rotation Parameter B

ntial

RAKTAOS2~RAKTAOS0RBKTAOS2~RBKTAOS0• Screen-over Pattern Name (Rotation Parameter A)
OVPNRA
1800B8H

15
14
13
12
11
10
9
RAOPN15 RAOPN14 RAOPN13 RAOPN12 RAOPN11 RAOPN10 RAOPN9
7
6
5
4
3
2
1
RAOPN7 RAOPN6 RAOPN5 RAOPN4 RAOPN3 RAOPN2 RAOPN18RAOPN80
RAOPN0• Screen-over Pattern Name (Rotation Parameter B)

15
14
13
12
11
10
9
RBOPN15 RBOPN14 RBOPN13 RBOPN12 RBOPN11 RBOPN10 RBOPN9
7
6
5
4
3
2
1
RBOPN7 RBOPN6 RBOPN5 RBOPN4 RBOPN3 RBOPN2 RBOPN1deOVPNRB
1800BAH

8
RBOPN80
RBOPN0Over pattern name bit (RAOPN15 to RAOPN0, RBOPN15 to RBOPN0)

RAOPN15~RAOPN0RBOPN15~RBOPN0

1800B8H
1800BAH

nfi

Designates pattern name data when the screen-over process repeating the character
pattern is set.
Bit 15~0
Bit 15~0

For Rotation Parameter A
For Rotation Parameter B• Rotation Parameter Table Address (Rotation Parameter A, B)
14
~
6
~

13
~
5
~

Co

15
~
7
~

RPYAU
1800BCH

12
~
4
~

11
~
3
~

10
~
2
RPTA189~1
RPTA178~
0
RPTA16

9
RPTA9
1
RPTA1

8
RPTA8
0
~

• Rotation Parameter Table Address (Rotation Parameter A, B)
14
RPTA14
6
RPTA6

GA

RPTAL
1800BEH

15
RPTA15
7
RPTA7

13
RPTA13
5
RPTA5

12
RPTA12
4
RPTA4

11
RPTA11
3
RPTA3

10
RPTA102
RPTA2

Rotation parameters table address bit (RPTA18 to RPTA1)

Designates the lead address of rotation parameter tables.
1800BCH
1800BEH

Bit 2~0
Bit 15~1

SE

RPTA18~RPTA16
RPTA15~RPTA1

ST-58-R2

367

• Window Position (W0, Horizontal Start Point)
15
~
7
W0SX7

14
~
6
W0SX6

13
~
5
W0SX5

12
~
4
W0SX4

11
~
3
W0SX3

10
~
2
W0SX2

9
W0SX9
1
W0SX1

8
W0SX8
0
W0SX0

11
~
3
W0SY3

10
~
2
W0SY2

9
~
1
W0SY1

8
W0SY8
0
W0SY0

WPSY0
1800C2H

15
~
7
W0SY7

14
~
6
W0SY6

13
~
5
W0SY5

12
~
4
W0SY4

• Window Position (W0, Horizontal End Point)
15
~
7
W0EX7

14
~
6
W0EX6

13
~
5
W0EX5

12
~
4
W0EX4

8
W0EX8
0
W0EX0

11
~
3
W0EY3

10
~
2
W0EY2

9
~
1
W0EY1

8
W0EY8
0
W0EY0

11
~
3
W1SX3

10
~
2
W1SX2

9
W1SX9
1
W1SX1

8
W1SX8
0
W1SX0

11
~
3
W1SY3

10
~
2
W1SY2

9
~
1
W1SY1

8
W1SY8
0
W1SY0

11
~
3
W1EX3

10
~
2
W1EX2

9
W1EX9
1
W1EX1

8
W1EX8
0
W1EX0

11
~
3
W0EX3

10
~
2
W0EX2

nfi

WPEX0
1800C4Hde• Window Position (W0, Vertical Start Point)

nti
al

WPSX0
1800C0H

9
W0EX9
1
W0EX1

• Window Position (W0, Vertical End Point)
15
~
7
W0EY7

14
~
6
W0EY6

13
~
5
W0EY5

12
~
4
W0EY4

Co

WPEY0
1800C6H• Window Position (W1, Horizontal Start Point)
WPSX1
1800C8H

15
~
7
W1SX7

14
~
6
W1SX6

13
~
5
W1SX5

12
~
4
W1SX4

WPSY1
1800CAHGA• Window Position (W1, Vertical Start Point)
15
~
7
W1SY7

14
~
6
W1SY6

13
~
5
W1SY5

12
~
4
W1SY4

• Window Position (W1, Horizontal End Point)
15
~
7
W1EX7

14
~
6
W1EX6

SE

WPEX1
1800CCH

368

13
~
5
W1EX5

12
~
4
W1EX4

• Window Position (W1, Vertical End Point)
15
~
7
W1EY7

14
~
6
W1EY6

13
~
5
W1EY5

12
~
4
W1EY4

11
~
3
W1EY3

10
~
2
W1EY2

9
~
1
W1EY1

8
W1EY8
0
W1EY0

nti
al

WPEY1
1800CEH

Window position bit (for horizontal coordinates): Window start/end X bit (W0SX9 to
W0SX0, W0EX9 to W0EX0, W1SX9 to W1SX0, W1EX9 to W1EX0)

Designates the horizontal start and end coordinates. Designated coordinate value isthe coordinate value (H counter value) on the TV screenNote:

Bit 9~0
Bit 9~0
Bit 9~0
Bit 9~0

For W0 start point coordinates
For W0 end point coordinates
For W1 start point coordinates
For W1 end point coordinates

WxxX9 WxxX8 WxxX7 WxxX6 WxxX5 WxxX4 WxxX3 WxxX2 WxxX1 WxxX0
H8
H7
H9
H8
Invalid H8

H6
H7
H7

Invalid H9

H8

H5
H6
H6

H4
H5
H5

H3
H4
H4

H2
H3
H3

H1
H2
H2

H0
H1
H1

Invalid
H0
H0

H7

H6

H5

H4

H3

H2

H1

nfi

Graphics
Mode
NormalHi-ResExclusive
NormalExclusive
Hi-Res

1800C0H
1800C4H
1800C8H
1800CCHde

W0SX9~W0SX0
W0EX9~W0EX0
W1SX9~W1SX0
W1EX9~W1EX0

0S, 0E, 1S, or 1E is entered in bit name for xx.

Co

Window position bit (for vertical coordinates): Window start/end Y bit (W0SY8 toW0SY0, W0EY8 to W0EY0, W1SY8 to W1SY0, W1EY8 to W1EY0)

Designates the vertical start and end coordinates. The designated coordinate value
is the coordinate value (V counter value) on the TV screen.
1800C2H
1800C6H
1800CAH
1800CEH

Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0

For W0 start point coordinates
For W0 end point coordinates
For W1 start point coordinates
For W1 end point coordinates

SE

GA

W0SY8~W0SY0
W0EY8~W0EY0
W1SY8~W1SY0
W1EY8~W1EY0

ST-58-R2

369

Note:

WxxY8 WxxY7 WxxY6 WxxY5 WxxY4 WxxY3 WxxY2 WxxY1 WxxY0
V8

V7

V6

V5

V4

V3

V2

V7

V6

V5

V4

V3

V2

V1

V0

Invalid

V8

V7

V6

V5

V4

V3

V2

V1

V0

0S, 0E, 1S or 1E is entered in bit name for xx.

• Window Control (NBG0, NBG1)
14
~
6
~

13
N1SWE
5
N0SWE

12
N1SWA
4
N0SWA

11
N1W1E
3
N0W1E

10
N1W1A
2
N0W1A

9
N1W0E
1
N0W0E

8
N1W0A
0
N0W0A

12
N3SWA
4
N2SWA

11
N3W1E
3
N2W1E

10
N3W1A
2
N2W1A

9
N3W0E
1
N2W0E

8
N3W0A
0
N2W0A

10
SPW1A
2
R0W1A

9
SPW0E
1
R0W0E

8
SPW0A
0
R0W0A

9
CCW0E
1
RPW0E

8
CCW0A
0
RPW0A

15
N3LOG
7
N2LOG

14
~
6
~

13
N3SWE
5
N2SWE

WCTLC
1800D4H

15
SPLOG
7
R0LOG

14
~
6
~

Co

• Window Control (RBG0, Sprite)nfi• Window Control (NBG2, NBG3)WCTLB
1800D2H

13
SPSWE
5
R0SWE

V0

de

WCTLA
1800D0H

15
N1LOG
7
N0LOG

V1

nti
al

TV Screen(Interlace) Mode
Normal, Hi-Res(Non-interlace,Single-Density
Interlace)Normal, Hi-Res(Double-Density
Interlace)Exclusive Monitor

12
SPSWA
4
R0SWA

11
SPW1E
3
R0W1E

• Window Control (Rotation Window, Color Calculation Window)
15
CCLOG
7
RPLOG

14
~
6
~

13
CCSWE
5
~

GA

WCTLD
1800D6H

12
CCSWA
4
~

11
CCW1E
3
RPW1E

10
CCW1A
2
RPW1A

Window logic bit: Logic bit (N0LOG, N1LOG, N2LOG, N3LOG, R0LOG, SPLOG,
RPLOG, CCLOG)SE

Designates the method of overlapping windows used in each screen.

370

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

nti
al

N0LOG
N1LOG
N2LOG
N3LOG
R0LOG
SPLOG
RPLOG
CCLOG
xxLOG
0
1
Note:

Overlaid Logic
OR
AND

N0, N1, N2, N3, R0, SP, RP or CC is entered in bit name for xx.

deWindow enable bit (for W0): W0 enable bit (N0W0E, N1W0E, N2W0E, N3W0E, R0W0E,
SPW0E, RPW0E, CCW0E)

Designates whether to use the Normal window W0 in each screen.

Note:

Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

nfi

xxW0E
0
1

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Co

N0W0E
N1W0E
N2W0E
N3W0E
R0W0E
SPW0E
RPW0E
CCW0E

Process
Does not use W0 window
Uses W0 window

N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.

Window enable bit (for W1): W1 enable bit (N0W1E, N1W1E, N2W1E, N3W1E, R0W1E,
SPW1E, RPW1E, CCW1E)

SE

GA

Designates whether to use the Normal window W1 in each screen.

ST-58-R2

371

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

xxW1E
0
1
Note:

nti
al

N0W1E
N1W1E
N2W1E
N3W1E
R0W1E
SPW1E
RPW1E
CCW1E

Process
Does not use W1 window
Uses W1 window
N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.

deWindow enable bit (for SW): SW enable bit (N0SWE, N1SWE, N2SWE, N3SWE,
R0SWE, SPSWE, CCSWE)

Designates whether to use the sprite window SW in each screen.
1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H

Note:

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Color Calculation Window
Process
Does not use SW window
Uses SW window

Co

xxSWE
0
1

Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 13

nfi

N0SWE
N1SWE
N2SWE
N3SWE
R0SWE
SPSWE
CCSWE

N0, N1, N2, N3, R0, SP, or CC is entered in bit name for xx.

Window area bit (for W0): W0 area bit (N0W0A, N1W0A, N2W0A, N3W0A, R0W0A,
SPW0A, RPW0A, CCW0A)

SEGA

Designates which area is the valid area of the Normal window W0 used in eachscreen.

372

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

nti
al

N0W0A
N1W0A
N2W0A
N3W0A
R0W0A
SPW0A
RPW0A
CCW0A
xxW0A
0
1
Note:

Process
Enables the inside of W0 window
Enables the outside of W0 window
N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.

deWindow area bit (for W1): W1 area bit (N0W1A, N1W1A, N2W1A, N3W1A, R0W1A,
SPW1A, RPW1A, CCW1A)

Designates which area is the valid area of the Normal window W1 used in eachscreen.

Note:

Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Rotation Parameter Window
For Color Calculation Window

nfi

xxW1A
0
1

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H
1800D6H

Co

N0W1A
N1W1A
N2W1A
N3W1A
R0W1A
SPW1A
RPW1A
CCW1A

Process
Enables the inside of W1 window
Enables the outside of W1 window

N0, N1, N2, N3, R0, SP, RP, or CC is entered in bit name for xx.

Window area bit (for SW): SW area bit (N0SWA, N1SWA, N2SWA, N3SWA, R0SWA,SPSWA, CCSWA)

SE

GA

Designates which area is the valid area of the sprite window SW used in eachscreen.

ST-58-R2

373

1800D0H
1800D0H
1800D2H
1800D2H
1800D4H
1800D4H
1800D6H

Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 12

Transparent Process Window for NBG0 (or RBG1)
Transparent Process Window for NBG1 (or EXBG)
Transparent Process Window for NBG2
Transparent Process Window for NBG3
Transparent Process Window for RBG0
Transparent Process Window for Sprite
For Color Calculation Window

xxSWA
0
1
Note:

nti
al

N0SWA
N1SWA
N2SWA
N3SWA
R0SWA
SPSWA
CCSWA

Process
Enables the inside of SW window
Enables the outside of SW window
N0, N1, N2, N3, R0, SP or CC is entered in bit name for xx.

LWTA0U
1800D8H

15
W0LWE
7
~

14
~
6
~

13
~
5
~

12
~
4
~

LWTA0L
1800DAH

11
~
3
~

10
~
2

9
~
1

8
~
0

W0LWTA18

W0LWTA17W0LWTA16

nfi• Line Window Table Address (W0)de• Line Window Table Address (W0)

15

14

13

12

11

10

9

8

W0LWTA15W0LWTA14W0LWTA13W0LWTA12W0LWTA11W0LWTA10W0LWTA9W0LWTA8

7

6

5

4

3

2

1

0

W0LWTA7 W0LWTA6 W0LWTA5 W0LWTA4 W0LWTA3 W0LWTA2 W0LWTA1

15
LWTA1U
1800DCH

14
~
6
~

W1LWE

7
~

Co

• Line Window Table Address (W1)
13
~
5
~

12
~
4
~

11
~
3
~

~

10
~
2

9
~
1

8
~
0

W1LWTA18W1LWTA17W1LWTA16• Line Window Table Address (W1)
14

13

12

11

10

9

8

W1LWTA14W1LWTA13W1LWTA12W1LWTA11W1LWTA10W1LWTA9W1LWTA8

7

6

5

4

3

2

1

0

GA

LWTA1L
1800DEH

15

W1LWTA15W1LWTA7 W1LWTA6 W1LWTA5 W1LWTA4 W1LWTA3 W1LWTA2 W1LWTA1Line window enable bit (W0LWE, W1LWE)

Designates whether to make the Normal window a line window.
1800D8H
1800DCH

SE

W0LWE
W1LWE

374

Bit 15
Bit 15For W0For W1~

Note:

Process
Does not process Normal Window to Line Window
Processes Normal Window to Line Window

0 or 1 is entered in bit name for x.

nti
al

WxLWE
0
1

Line window table address bit (W0LWTA18 to W0LWTA1, W1LWTA18 to W1LWTA1)

Designates the lead address of the line window table in VRAM.
W0LWTA18~W0LWTA16
W0LWTA15~W0LWTA1W1LWTA18~W1LWTA16
W1LWTA15~W1LWTA1

1800D8H
1800DAH
1800DCH
1800DEH

Bit 2~0
Bit 15~1
Bit 2~0
Bit 15~1

SPCTL
1800E0H

15
~
7
~

14
~
6
~

de

• Sprite Control

For W0For W0For W1For W1

13
12
11
10
9
8
SPCCCS1 SPCCCS0~SPCCN2 SPCCN1 SPCCN0
5
4
3
2
1
0
SPCLMD SPWINEN SPTYPE3 SPTYPE2 SPTYPE1 SPTYPE0

Sprite color calculation condition bit (SPCCCS1, SPCCCS0), bits 13, 12

SPCCCS001
01

Condition(Priority number) ≤ (Color calculation condition number) only
(Priority number) = (Color calculation condition number) only
(Priority number) ≥ (Color calculation condition number) only
Only when Color Data MSB is 1

Co

SPCCCS1
0
0
1
1

nfi

Designates the color calculation condition of sprites.

Sprite color calculation number bit (SPCCN2 to SPCCN0), bits 10 to 8

Designates the color calculation condition number of sprites.
This value is ignored when the color calculation condition is set to perform color
calculations only if the most significant bit of color data is 1.
Sprite color mode bit (SPCLMD), bit 5

SE

GA

Designates the sprite color mode.

ST-58-R2

375

Sprite Color Format Data
Sprite data is all in palette format
Sprite data is in palette format and RGB format

ntial

SPCLMD
0
1

Sprite window enable bit: SW enable bit (SPWINEN), bit 4

Designates whether to use the sprite window SW.
SPWINEN
0
1

Process
Does not use sprite window
Uses sprite window

Sprite type bit (STYPE3 to STYPE0), bits 3 to 0

Designates the sprite type.

• Shadow Control
15
~
7
~

14
~
6
~

13
~
5
BKSDENGA

SDCTL
1800E2H

STYPE0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Sprite Data TypeType 0Type 1
Type 2Type 3
Type 4
Type 5
Type 6
Type 7
Type 8Type 9Type A
Type B
Type CType D
Type E
Type FdeSTYPE1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

nfi

STYPE2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Co

STYPE3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

12
~
4
R0SDEN

11~
3
N3SDEN

10~
2
N2SDEN

9~
1
N1SDEN

Shadow enable bit (N0SDEN, N1SDEN, N2SDEN, N3SDEN, R0SDEN,
BKSDEN)SE

This bit designates in sprites of the Normal shadow and transparent shadow
whether to use the shadow function for the scroll screen and back screen.

376

8
TPSDSL0
N0SDEN

1800E2H
1800E2H
1800E2H
1800E2H
1800E2H
1800E2H

xxSDEN
0
1
Note:

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Backnti
al

N0SDENN1SDENN2SDEN
N3SDEN
R0SDENBKSDEN

Process
Does not use shadow function (shadow not added)
Uses shadow function (shadow added)

N0, N1, N2, N3, R0, or BK is entered in bit name for xx.

Transparent shadow select bit (TPSDSL), bit 8

deDesignates whether to activate the sprite of the transparent shadow.
TPSDSL
0
1

Process
Disables transparent shadow sprite
Enables transparent shadow sprite• Color RAM Address Offset (NBG0~NBG3)
15
~
7
~

14
13
12
N3CAOS2 N3CAOS1 N3CAOS0
6
5
4
N1CAOS2 N1CAOS1 N1CAOS0

11
~
3
~

10
9
8
N2CAOS2 N2CAOS1 N2CAOS0
2
1
0
N0CAOS2 N0CAOS1 N0CAOS0

11
~
3
~

10
9
8
~
~
~
2
1
0
R0CAOS2 R0CAOS1 R0CAOS0

nfi

CRAOFA
1800E4H

CRAOFB
1800E6H

15
~
7
~

Co

• Color RAM Address Offset (RBG0, Sprite)

14
13
12
~
~
~
6
5
4
SPCAOS2 SPCAOS1 SPCAOS0

Color RAM address offset bit (N0CAOS2 to N0CAOS0, N1CAOS2 to
N1CAOS0, N2CAOS2 to N2CAOS0, N3CAOS2 to N3CAOS0, R0CAOS2 to R0CAOS0,
SPCAOS2 to SPCAOS0)SE

GA

Designates color RAM address offset values with respect to the sprite and each scroll
screen.

ST-58-R2

377

1800E4H
1800E4H
1800E4H
1800E4H
1800E6H
1800E6H

Bit 2~0
Bit 6~4
Bit 10~8
Bit 14~12
Bit 2~0
Bit 6~4

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Sprite• Line Color Screen Enable
LNCLEN
1800E8H

15
~
7
~

14
~
6
~

13
~
5
SPLCEN

12~
4
R0LCEN

11~
3
N3LCENnti
al

N0CAOS2~N0CAOS0
N1CAOS2~N1CAOS0
N2CAOS2~N2CAOS0
N3CAOS2~N3CAOS0
R0CAOS2~R0CAOS0
SPCAOS2~SPCAOS0

10~
2
N2LCEN

8~
0
N0LCENdeLine color enable bit (N0LCEN, N1LCEN, N2LCEN, N3LCEN, R0LCEN,SPLCEN)

9~
1
N1LCEN

Designates whether to insert the line color screen when each screen is a top image.
1800E8H
1800E8H
1800E8H
1800E8H
1800E8H
1800E8H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5

xxLCEN0

Process
Does not insert the line color screen whencorresponding screen is top image
Inserts the line color screen when corresponding
screen is top image

Co

1
Note:

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Sprite

nfi

N0LCENN1LCENN2LCEN
N3LCENR0LCENSPLCEN

N0, N1, N2, N3, R0, or SP is entered in the bit name for xx.

• Special Priority Mode

15
14
13
12
11
10
9
8
~
~
~
~
~
~
R0SPRM1 R0SPRM0
7
6
5
4
3
2
1
0
N3SPRM1 N3SPRM0 N2SPRM1 N2SPRM0 N1SPRM1 N1SPRM0 N0SPRM1 N0SPRM0GA

SFPRMD
1800EAH

Special priority mode bit (N0SPRM1, N0SPRM0, N1SPRM1, N1SPRM0,N2SPRM1, N2SPRM0, N3SPRM1, N3SPRM0, R0SPRM1, R0SPRM0)

SE

Designates the special priority function mode of each screen scroll.

378

xxSPRM1
0
0
1
1
Note:

1800EAH
1800EAH
1800EAH
1800EAH
1800EAH

xxSPRM001
01

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6
Bit 9,8Mode
Mode 0Mode 1Mode 2-For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0nti
al

N0SPRM1, N0SPRM0
N1SPRM1, N1SPRM0N2SPRM1, N2SPRM0
N3SPRM1, N3SPRM0R0SPRM1, R0SPRM0

Process
Select the priority number LSB per each screen
Select the priority number LSB per each character
Select the priority number LSB per each dot
Selection not allowed

N0, N1, N2, N3, or R0 is entered in bit name for xx.

CCCTL
1800ECH

15
BOKEN
7
~

14
BOKN2
6
SPCCEN

13BOKN1
5LCCCEN

Gradation enable bit (BOKEN), bit 15

de• Color Calculation Control
12
BOKN0
4
R0CCEN

11~3
N3CCEN

10EXCCEN
2
N2CCEN

9CCRTMD
1
N1CCEN

8CCMD
0N0CCEN

nfi

Designates whether to use the gradation function.
BOKEN
0
1

Process
Do not use gradation calculation function
Use gradation calculation function

Gradation screen number bit: Gradation number bit (BOKN2 to BOKN0), bits 14 to 12

BOKN1
0
0
1
1
0
0
1
1

BOKN0
0
1
0
1
0
1
0
1

Screen Using Gradation Calculation Function
SpriteRBG0
NBG0 or RBG1
Invalid
NBG1 or EXBG
NBG2
NBG3
Invalid

SE

GA

BOKN2
0
0
0
0
1
1
1
1

Co

Designates the screen using the gradation (shading) calculation function

ST-58-R2

379

Extended color calculation enable bit (EXCCEN), bit 10

EXCCEN01

ntialDesignates whether to use the extended color calculation function
Process
Do not use extended color calculation
Use extended color calculation

Color calculation ratio mode bit (CCRTMD), bit 9

Designates the color calculation ratio mode.
CCRTMD
0
1

Mode
0
1

Process
For color calculation ratio, select per top screen side
For color calculation ratio, select per second screen side

Designates the color calculation mode.
CCMD
0
1

Mode
0
1

de

Color calculation mode bit (CCMD), bit 8

Process
Add according to the color calculation register value
Add as isnfi

Color calculation enable bit (N0CCEN, N1CCEN, N2CCEN, N3CCEN,
R0CCEN, LCCCEN, SPCCEN)

Designates whether to perform color calculation (color calculation enable)
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECH
1800ECHxxCCEN01

N0, N1, N2, N3, R0, LC, or SP is entered in bit name for xx.

SE
380

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For LNCL
For Sprite

Process
Does not color-calculate
Color-calculates

GA

Note :

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6

Co

N0CCEN
N1CCEN
N2CCEN
N3CCEN
R0CCENLCCCENSPCCEN• Special Color Calculation Modential

SFCCMD
1800EEH

15
14
13
12
11
10
9
8
~
~
~
~
~
~
R0SCCM1 R0SCCM0
7
6
5
4
3
2
1
0
N3SCCM1 N3SCCM0 N2SCCM1 N2SCCM0 N1SCCM1 N1SCCM0 N0SCCM1 N0SCCM0

Special color calculation mode bit (N0SCCM1, N0SCCM0, N1SCCM1,
N1SCCM0, N2SCCM1, N2SCCM0, N3SCCM1, N3SCCM0, R0SCCM1, R0SCCM0)

Designates the special color calculation function mode of each scroll screen.

Note:

xxSCCM001
01

Bit 1,0
Bit 3,2
Bit 5,4Bit 7,6
Bit 9,8de

xxSCCM100111800EEH
1800EEH
1800EEH
1800EEH
1800EEH
Mode
0
1
2
3

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0

Process
Select color calculation enable per screen
Select color calculation enable per character
Select color calculation enable per dot
Select color calculation enable with color data MSB

nfi

N0SCCM1, N0SCCM0
N1SCCM1, N1SCCM0
N2SCCM1, N2SCCM0
N3SCCM1, N3SCCM0
R0SCCM1, R0SCCM0

N0, N1, N2, N3, or R0 is entered in bit name for xx.

• Priority Number (Sprite 0, 1)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
S1PRIN2
2
S0PRIN29S1PRIN1
1
S0PRIN18
S1PRIN00
S0PRIN0

13
~
5
~

12
~
4
~

11
~
3
~

10
S3PRIN22
S2PRIN29S3PRIN1
1
S2PRIN18
S3PRIN00
S2PRIN0

13
~
5
~

12
~
4
~

11
~
3
~

10
S5PRIN2
2
S4PRIN29S5PRIN1
1
S4PRIN18
S5PRIN00
S4PRIN0Co

PRISA
1800F0H• Priority Number (Sprite 2, 3)
15
~
7
~

14
~
6
~

GA

PRISB
1800F2H• Priority Number (Sprite 4, 5)
14
~
6
~

SE

PRISC
1800F4H

15~
7~

ST-58-R2

381

• Priority Number (Sprite 6, 7)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

11
~
3
~

10
S7PRIN2
2
S6PRIN29S7PRIN1
1
S6PRIN18
S7PRIN00S6PRIN0

nti
al

PRISD
1800F6H

Sprite priority number bit (for sprite) (S0PRIN2 to S0PRIN0, S1PRIN2 to S1PRIN0,
S2PRIN2 to S2PRIN0, S3PRIN2 to S3PRIN0, S4PRIN2 to S4PRIN0, S5PRIN2 to
S5PRIN0, S6PRIN2 to S6PRIN0, S7PRIN2 to S7PRIN0)

Designates the sprite priority number.
Bit 2~0
Bit 10~8
Bit 2~0
Bit 10~8
Bit 2~0
Bit 10~8
Bit 2~0
Bit 10~8• Priority Number (NBG0, NBG1)
15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

Co

PRINA
1800F8HFor Sprite Register 0
For Sprite Register 1
For Sprite Register 2
For Sprite Register 3
For Sprite Register 4
For Sprite Register 5
For Sprite Register 6
For Sprite Register 7de1800F0H
1800F0H
1800F2H
1800F2H
1800F4H
1800F4H
1800F6H
1800F6H

nfi

S0PRIN2~S0PRIN0S1PRIN2~S1PRIN0S2PRIN2~S2PRIN0S3PRIN2~S3PRIN0S4PRIN2~S4PRIN0S5PRIN2~S5PRIN0S6PRIN2~S6PRIN0S7PRIN2~S7PRIN0

11
~
3
~

10
N1PRIN2
2
N0PRIN29
N1PRIN1
1
N0PRIN18
N1PRIN00
N0PRIN0• Priority Number (NBG2, NBG3)PRINB
1800FAH

15
~
7
~

14
~
6
~

• Priority Number (RBG0)
15
~
7
~

14
~
6
~

12
~
4
~

11
~
3
~

10
N3PRIN2
2
N2PRIN29
N3PRIN1
1
N2PRIN18
N3PRIN00
N2PRIN0

13
~
5
~

12
~
4
~

11
~
3
~

10
~
2
R0PRIN2

9~
1
R0PRIN1

8~
0
R0PRIN0GA

PRIR
1800FCH

13~
5~

Priority number bit (for scroll screen) (N0PRIN2 to N0PRIN0, N1PRIN2 to N1PRIN0,
N2PRIN2 to N2PRIN0, N3PRIN2 to N3PRIN0, R0PRIN2 to R0PRIN0)

SE

Designates the priority number of each screen scroll.

382

1800F8H
1800F8H
1800FAH
1800FAH
1800FCHBit 2~0
Bit 10~8
Bit 2~0
Bit 10~8
Bit 2~0• Reserve
1800FEH

15
~
7
~

14
~
6
~

13
~
5
~

12
~
4
~

CCRSA
180100H

15
~
7
~

14
~
6
~

13
~
5
~

CCRSB
180102H

15
~
7
~

14
~
6
~

10
~
2
~

9
~
1
~

8
~
0
~

12
11
10
9
8
S1CCRT4 S1CCRT3 S1CCRT2 S1CCRT1 S1CCRT0
4
3
2
1
0
S0CCRT4 S0CCRT3 S0CCRT2 S0CCRT1 S0CCRT0

nfi• Color Calculation Ratio (Sprite 2, 3)

11
~
3
~

de

• Color Calculation Ratio (Sprite 0, 1)

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0nti
al

N0PRIN2~N0PRIN0
N1PRIN2~N1PRIN0
N2PRIN2~N2PRIN0
N3PRIN2~N3PRIN0R0PRIN2~R0PRIN0

13
~
5
~

12
11
10
9
8
S3CCRT4 S3CCRT3 S3CCRT2 S3CCRT1 S3CCRT0
4
3
2
1
0
S2CCRT4 S2CCRT3 S2CCRT2 S2CCRT1 S2CCRT0

CCRSC
180104H

15
~
7
~

Co

• Color Calculation Ratio (Sprite 4, 5)
14
~
6
~

13
~
5
~

12
11
10
9
8
S5CCRT4 S5CCRT3 S5CCRT2 S5CCRT1 S5CCRT0
4
3
2
1
0
S4CCRT4 S4CCRT3 S4CCRT2 S4CCRT1 S4CCRT0• Color Calculation Ratio (Sprite 6, 7)
14
~
6
~

GA

15
~
7
~

CCRSD
180106H

13
~
5
~

12
11
10
9
8
S7CCRT4 S7CCRT3 S7CCRT2 S7CCRT1 S7CCRT0
4
3
2
1
0
S6CCRT4 S6CCRT3 S6CCRT2 S6CCRT1 S6CCRT0

Sprite color calculation ratio bit (S0CCRT4 to S0CCRT0, S1CCRT4 to S1CCRT0,S2CCRT4 to S2CCRT0, S3CCRT4 to S3CCRT0, S4CCRT4 to S4CCRT0, S5CCRT4 to
S5CCRT0, S6CCRT4 to S6CCRT0, S7CCRT4 to S7CCRT0)

SE

Designates the sprite color calculation ratio. The color calculation ratio is for a value
1/32 of RGB various color data.

ST-58-R2

383

180100H
180100H
180102H
180102H
180104H
180104H
180106H
180106H

Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8

For Sprite Register 0
For Sprite Register 1
For Sprite Register 2
For Sprite Register 3
For Sprite Register 4
For Sprite Register 5
For Sprite Register 6
For Sprite Register 7nti
al

S0CCRT4~S0CCRT0S1CCRT4~S1CCRT0S2CCRT4~S2CCRT0S3CCRT4~S3CCRT0S4CCRT4~S4CCRT0S5CCRT4~S5CCRT0S6CCRT4~S6CCRT0S7CCRT4~S7CCRT0• Color Calculation Ratio (NBG0, NBG1)
15
~
7
~

14
~
6
~

13
~
5
~

12
11
10
9
8
N1CCRT4 N1CCRT3 N1CCRT2 N1CCRT1 N1CCRT0
4
3
2
1
0
N0CCRT4 N0CCRT3 N0CCRT2 N0CCRT1 N0CCRT0• Color Calculation Ratio (NBG2, NBG3)
15
~
7
~

14
~
6
~

13
~
5
~

• Color Calculation Ratio (RBG0)
14
~
6
~

13
~
5
~

12
11
10
9
8
~
~
~
~
~
4
3
2
1
0
R0CCRT4 R0CCRT3 R0CCRT2 R0CCRT1 R0CCRT0

Co

CCRR
18010CH

15
~
7
~

12
11
10
9
8
N3CCRT4 N3CCRT3 N3CCRT2 N3CCRT1 N3CCRT0
4
3
2
1
0
N2CCRT4 N2CCRT3 N2CCRT2 N2CCRT1 N2CCRT0

nfi

CCRNB
18010AHde

CCRNA
180108H• Color Calculation Ratio (Line Color Screen, Back Screen)
14
~
6
~

13
~
5
~

GA

CCRLB
18010EH

15
~
7
~

12
11
10
9
8
BKCCRT4 BKCCRT3 BKCCRT2 BKCCRT1 BKCCRT0
4
3
2
1
0
LCCCRT4 LCCCRT3 LCCCRT2 LCCCRT1 LCCCRT0

Color calculation ratio bit (for scroll screens): (N0CCRT4 to N0CCRT0, N1CCRT4 to
N1CCRT0, N2CCRT4 to N2CCRT0, N3CCRT4 to N3CCRT0, R0CCRT4 to R0CCRT0,LCCCRT4 to LCCCRT0, BKCCRT4 to BKCCRT0)

SE

Designates the color calculation ratio of each scroll screen. The color calculation
ratio corresponds to a value 1/32 times R,G,B color data.

384

xxCCRT4

xxCCRT3

xxCCRT2

xxCCRT1

xxCCRT0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Color Calculation Ratio
Top Image : Second Image
31:1
30:2
29:3
28:4
27:5
26:6
25:7
24:8
23:9
22:10
21:11
20:12
19:13
18:14
17:15
16:16
15:17
14:18
13:19
12:20
11:21
10:22
9:23
8:24
7:25
6:26
5:27
4:28
3:29
2:30
1:31
0:32

nfi

Co

GA

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For LNCLFor Back

N0, N1, N2, N3, R0, LC, or BK is entered in bit name for xx.

SE

Note:

Bit 4~0
Bit 12~8
Bit 4~0
Bit 12~8
Bit 4~0
Bit 4~0
Bit 12~8nti
al180108H
180108H
18010AH
18010AH
18010CH
18010EH
18010EHde

N0CCRT4~NOCCRT0
N1CCRT4~N1CCRT0
N2CCRT4~N2CCRT0
N3CCRT4~N3CCRT0R0CCRT4~R0CCRT0LCCCRT4~LCCCRT0BKCCRT4~BKCCRT0

ST-58-R2

385

• Color Offset Enable
15
~
7
~

14
~
6
SPCOEN

13~
5
BKCOEN

12~
4
R0COEN

11~
3
N3COEN

10~
2
N2COEN

9~
1
N1COEN

8~0
N0COENnti
al

CLOFEN
180110H

Color offset enable bit (N0COEN, N1COEN, N2COEN, N3COEN, R0COEN,
BKCOEN, SPCOEN)

Designates whether to use the color offset function.
180110H
180110H
180110H
180110H
180110H
180110H
180110H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6

Note:

Process
Do not use color offset function
Use color offset function

nfi

xxCOEN
01

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Back
For Sprite

de

N0COENN1COENN2COEN
N3COEN
R0COENBKCOENSPCOEN

N0, N1, N2, N3, R0, BK, or SP is entered in bit name for xx.

• Color Offset Select
15
~
7
~

14
~
6
SPCOSL

13~
5
BKCOSL

12~
4
R0COSL

11~
3
N3COSLCo

CLOFSL
180112H

10~
2
N2COSL

9~
1
N1COSL

Color offset select bit (N0COSL, N1COSL, N2COSL, N3COSL, R0COSL,BKCOSL, SPCOSL)

SEGA

Designates the color offset register to use when using the color offset function.

386

8
~
0
N0COSL180112H
180112H
180112H
180112H
180112H
180112H
180112H

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6

xxCOSL
01
Note:

For NBG0 (or RBG1)For NBG1 (or EXBG)For NBG2
For NBG3
For RBG0
For Back
For Spritenti
al

N0COSLN1COSLN2COSL
N3COSLR0COSLBKCOSLSPCOSL

Process
Use color offset A value
Use color offset B value

N0, N1, N2, N3, R0, BK, or SP is entered in bit name for xx.

14~
6
COARD6• Color Offset A (GREEN)
15~
7COAGR714~
6COAGR6

12~
4
COARD4

11~
3
COARD3

10~
2
COARD2

9~
1
COARD1

8
COARD80
COARD011~
3COAGR39~1COAGR18COAGR80
COAGR010~2COAGR213~
5COABL512~
4COABL411~
3
COABL310~
2COABL29~
1
COABL18COABL80
COABL013~
5COBRD512~
4COBRD4

11~
3COBRD310~
2COBRD2

9~
1
COBRD18COBRD80
COBRD013~
5COBGR512~
4COBGR4

11~
3COBGR310~
2COBGR2

9~
1COBGR18
COBGR80
COBGR013~5COAGR512~
4COAGR4Co

COAG
180116H

13~
5COARD5nfi

COAR
180114H

15~
7COARD7de• Color Offset A (RED)• Color Offset A (BLUE)
COAB
180118H

15~
7COABL714~
6COABL6• Color Offset B (RED)15~
7
COBRD714~
6COBRD6GA

COBR
18011AH• Color Offset B (GREEN)
15~
7COBGR7SE

COBG
18011CHST-58-R2

14~
6
COBGR6387

• Color Offset B (BLUE)
14~
6
COBBL613~
5COBBL512~
4COBBL4

11~
3
COBBL310~
2COBBL2

9~
1COBBL1

Color offset value bit: Color offset data bit (COARD8 to COARD0, COAGR8 to
COAGR0, COABL8 to COABL0, COBRD8 to COBRD0, COBGR8 to COBGR0, COBBL8
to COBBL0)

Sets the RGB individual value of color offset A and color offset B. Negative
numbers should be set by two complements.
Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0
Bit 8~0

For color offset A RED data
For color offset A GREEN data
For color offset A BLUE data
For color offset B RED data
For color offset B GREEN data
For color offset B BLUE datade180114H
180116H
180118H
18011AH
18011CH
18011EH

SE

GA

Co

nfi

COARD8~COARD0COAGR8~COAGR0COABL8~COABL0COBRD8~COBRD0COBGR8~COBGR0
COBBL8~COBBL0

388

8
COBBL80
COBBL0

nti
al

COBB
18011EH

15~
7
COBBL7

Table List

Character Pattern Tables(2)

Pattern Name Tables(3)

Bitmap Pattern Tables(4)

Line Scroll Tables(5)

Vertical Cell Scroll Tables(6)

Rotation Parameter Tables(7)

Coefficient Tables(8)

Line Color Screen Tables(9)

Back Screen Tables(10)

Normal Line Window Tables

SE

GA

Co

nfi

(1)

de

The following tables are shown in the table list:

nti
al

16.4

ST-58-R2

389

• Character Pattern Table Data Specifications
Cell Data
32 bytes/cell64 bytes/cell
128 bytes/cell
256 bytes/cellBoundary
20H byte
20H byte
20H byte
20H byte• Character Pattern Table(1) 4 bi ts/ dot (32 byt es/ cel l)
Cha ra ct er Pat ter n Ta bl e (V RA M)
10 9
8
Dot 0- 1 Da ta+02HDo t 0-4 Dat a

Dot 0-5 Dat a

Dot 0- 6 Da ta

Dot 0- 7 Da ta+1E H

Do t 7-4 Dat a

Dot 7- 5 Da ta

Do t 7-6 Dat a

Dot 7- 7 Da ta

Dot 0

1

2

3

7

6
5
4
Dot 0- 2 Da ta

4

5

6

2
1
0
Dot 0- 3 Da ta

7

+00

+01

+02

+03

1

+04

+05

+06

+07

2

+08

+09

3

+ 0C

+ 0D

4

+10

+11

5

+14

+15

6

+18

+19

7

+ 1C

+ 1D

Dot 0

3

nfi

11

de

+00H

14 13 12
Dot 0- 0 Dat a

Co

bit 15

+0A

+0B

+0E

+0F

+12

+13

+16

+17

+1A

+1B

+1E

+1F

Cel l

SE

GA

Not e 1: The up pe r le ft not at ion in the cel l is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Num be rs in the cel ls ar e VRAM addr esses (Hexa de cim al ) of do t (2do ts) da ta, wit h VRA M ad dr ess of dot 0- 0, 0- 1 dat a as theref ere nce .

390

nti
al

Bit Count for 1 Dot
4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot

(2) 8 bi ts/ dot (64 byt es/ cel l)
Cha ra ct er Pat ter n Ta bl e (V RA M)
Bit 1514

13 12 11 10
Dot 0- 0 Dat a+02H

Dot 0- 2 Da ta

Do t 0-3 Dat a+3E H

Dot 7- 6 Da ta

Dot 7- 7 Dat a

Dot 0

1

9

2

8

3

7

4

6

5

5

6

4
3
2
1
Dot 0- 1 Dat a

0

de

+00H

nti
al

• Character Pattern Table (Continued)

7+00 +01 +02 +03 +04 +05 +06 +07

Dot 0+08 +09 +0A +0B +0C +0D +0E +0F

2+10 +11 +12 +13 +14 +15 +16 +17

3+18 +19 +1A +1B +1C +1D +1E +1F

4+20 +21 +22 +23 +24 +25 +26 +27

5+28 +29 +2A +2B +2C +2D +2E +2F

6+30 +31 +32 +33 +34 +35 +36 +37

7+38 +39 +3A +3B + 3C + 3D +3E +3F

nfi

1

Co

Cel l

SE

GA

Not e 1: The uppe r lef t no tat ion in the ce l is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Num ber s in the cel ls ar e VRAM ad dr esse s (Hexad eci mal ) of do t
da ta, with VRAM ad dr ess of dot 0- 0 dat a as the ref er en ce.

ST-58-R2

391

(3) 16 bits/ do t (1 28 byt es/ ce l )Cha ra ct er Pat ter n Ta bl e (V RA M)
Bit 15

14

13

12

11

8
7
6
Dot 0- 0 Dat a+02H

Dot 0- 1 Dat a+7 EH

Dot 7- 7 Dat a

Dot 0

10

9

1

2

3

4

5

5

4

6

7

3

2

+00 +02 +04 +06 +08 +0A +0C +0E

0

nfi

Dot 0

1

de

+00H

+10 +12 +14 +16 +18 +1A + 1C +1E

2+20 +22 +24 +26 +28 +2A + 2C +2E

3+30 +32 +34 +36 +38 +3A + 3C +3E

4+40 +42 +44 +46 +48 +4A + 4C +4E

5+50 +52 +54 +56 +58 +5A + 5C +5E

6+60 +62 +64 +66 +68 +6A + 6C +6E

7+70 +72 +74 +76 +78 +7A +7C +7E

Cel l

Co

1

GA

Not e 1: The upp er lef t no tat io n in the ce ll is dot 0- 0; to the righ t ar e do t 0-1 ,dot 0- 2, dot 0- 3, ...
Not e 2: Numb er s in the cel ls are VRAM add re sses (Hexa de cim al) of dot
dat a, with VRAM ad dr ess of dot 0- 0 da ta as the re fer en ce.

• Vertical Cell Scroll Table Data Bit Configuration
Vertical Screen Scroll Value
Bit 15

14

12

11

10

9

8

7

13 12 11 10 9
8 bit fractional part

8

7

SE

+0H

13

Bit 15+2H

14

Note: Shaded area is ignored

392

nti
al

• Character Pattern Table (Continued)

65
4
3
11 bit integer part

6

5

4

3

2

1

0

2

1

0

• Character Pattern Table (Continued)

Cha ra ct er Pat ter n Ta bl e (V RA M)
BIT 15

14

13

12

11 10
9
8
7
6
5
4
Dot 0- 0 Da ta (M ost si gn fi ica nt wor d)+02H

Dot 0- 0 Da ta (L ea st si gn ificant wor d)+0 4H

Dot 0- 1 Da ta (M ost si gn fi ica nt wor d)+FCH

Dot 7- 7 Da ta (M ost si gn fi ica nt wor d)+F EH

Dot 7- 7 Da ta (L ea st si gn ificant wor d)

Do t 0

1

2

3

4

5

6

3

2

1

0

de

+00H

nti
al

(4) 32 bits/ do t (2 56 byt es/ ce l )7+00 +04 +08 +0C +10 +14 +18 +1C

1+20 +24 +28 + 2C +30 +34 +38 +3C

2+40 +44 +48 + 4C +50 +54 +58 +5C

3+60 +64 +68 + 6C +70 +74 +78 +7C

4+80 +84 +88 + 8C +90 +94 +98 +9C

nfi

Do t 0Cel l

Co

5 +A0 +A4 +A8 +AC +B0 +B4 +B8 +BC

6 +C0 + C4 + C8 +CC + D0 +D4 +D8 +D C
7

+E0 +E4 +E8 + EC +F 0 +F 4 +F 8 +F C

SEGA

Not e 1: The uppe r lef t no tat io n in the ce l is dot 0- 0; to the rig ht ar e dot 0- 1,
do t 0-2 , dot 0- 3, ...
Not e 2: Numb er s in the cel ls ar e VRAM addr esses (Hexadeci mal ) of do t
da ta (M SW), with VRAM ad dr ess of dot 0- 0 da ta (MSW) as theref ere nce .

ST-58-R2

393

• Pattern Name Table Data Specifications

1 WordContents of 1 Page Boundary During VRAM
Storage8192 Bytes
2000H
2048 Bytes
800H
16,384 Bytes
4000H
4096 Bytes
1000H

nti
al

Pattern Name Data Size Character Size
1 H Cell X 1 V Cell
2 H Cells X 2 V Cells
1 H Cell X 1 V Cell
2 H Cells X 2 V Cells

2 Words• Pattern Name Table(1) Pat tern Nam e Dat a Size : 1 wor dChar act er Pat ter n Size : 1 H cel l X 1 V cel l

Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

Cha ract er Pat ter n 0- 0 Pat ter n Name Dat a+00 02H

Char act er Patter n 0- 1 Pat ter n Na me Dat a+1F FEH

Char act er Pattern 63- 63 Patter n Nam e Data

Char act er
Pat ter n 0

1

1

2

+000 0 +0002 +000 4+0080 +0082 +0084+1F0 0 +1F0 2 +1F0 4

63+1F8 0 +1F8 2 +1F8 4

61

GA

62

1

0

62

63

Co

Ch ar act er
Pattern 0

2

nfi+00 00HdePattern Nam e Ta bl e (V RA M)+007A +007C +007E+00FA +00FC +00F E

Page+1F7 A +1F7 C +1F7 E+1F FA +1FFC +1F FE

SENo te 1: The up per -lef t no tat ion in the page is ch ar act er pa ttern 0- 0; to the right ar echar act er pat terns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr esse s (He xad eci mal ) of pa ttern na me dat aof ch ar act er pa ttern s, with VRAM addr ess of cha ra ct er pat ter n 0-0 pat ter n nam e
dat a as the ref er en ce.

394

(2) Pat tern Nam e Dat a Size : 1 wor dChar act er Pat ter n Size : 2 H cel ls X 2 V cel ls
Pattern Nam e Ta bl e (V RA M)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

Cha ract er Pat ter n 0- 0 Pat ter n Name Dat a+00 2HChar act er Pattern 0-1 Pattern Nam e Da ta+7FE H

Cha ra ct er Pat ter n 31- 31 Pattern Nam e Da ta

1

1

2

+000

+002

+004

+040

+042

+044

30

+780

+782

31

+7C0

+7C2

+784

Co

Cha ra ct er
Pat ter n 0

+7C4

1

0

29

30

31

+03A

+03C

+03E

+07A

+07C

+07E

nfi

Cha ract er
Pat ter n 0

2

de+00 0Hntial• Pattern Name Table (Continued)

+7BA

+7BC

+7BE

+7FA

+7FC

+7FE

Pag e

SE

GA

No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar echa ra ct er pat ter ns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr esse s (Hexad eci mal ) of pa ttern na me
da ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as the re fere nce .

ST-58-R2

395

• Pattern Name Table (Continued)

ntial(3) Pat tern Nam e Dat a Size : 2 wor ds
Char act er Pat ter n Size : 1 H cel l X 1 V cel lPattern Nam e Ta bl e (V RA M)
Bit 15+000 0H

14 13 12 11 10
9
8
7
6
5
4
3
2
1
Ch ar act er Pattern 0- 0 Patter n Nam e Data (Most sig ni fica nt word )+000 2H

Cha ract er Pat ter n 0- 0 Pat ter n Name Dat a (Le ast si gni fican t word )+000 4H

Char act er Pat ter n 0- 1 Pat ter n Name Dat a (Mo st si gni fican t wor d)Char act er Patter n 63 -6 3 Pat ter n Name Dat a (Most si gni fican t wor d)+3F FEH

Char act er Pat ter n 63 -6 3 Pat ter n Name Dat a (Le ast sig ni fican t word )Ch ar act er
Pattern 0
1
2
Cha ra ct er+0000 +0004 +0008
Pat ter n 0 +0002
1

63+00F4 +00F8 +00FC+00F6 +00FA +00FE+0006 +000A+0100 +0104+0102 +0106

62

nfi

61

de

+3F FCH

0

+0108
+010A

+ 01 F 4 + 01 F 8 +01FC+ 01 F 6 +01FA +01FE

62+3E00 +3E04 +3E0 8+3E02 +3E06 +3E0A

63+3F0 0 + 3F 04 +3F0 8+3F0 2 + 3F 06 +3F0 A

Co

Pag e

+3EF 4 +3EF8 +3EFC+3EF 6 +3EFA +3EFE+3FF4 +3F F8 +3FF C+3FF6 +3FFA +3F FE

SEGA

No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar echa ra ct er pat ter ns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr esse s (Hexad eci mal ) of pa ttern na me
da ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as the re fere nce .

396

(4) Pat tern Nam e Dat a Size : 2 wor ds
Char act er Pat ter n Size : 2 H cel ls X 2 V cel ls
Pattern Nam e Ta bl e (V RA M)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

nti
al

• Pattern Name Table (Continued)

0+0 02 HChar act er Patter n 0- 0 Pat ter n Na me Dat a (Le ast si gni fica nt wo rd )+0 04 H

Ch ar act er Pattern 0- 1 Pat ter n Na me Data (Most sig ni fica nt word )+FFCH

Ch ar act er Pattern 31 -3 1 Pat ter n Na me Dat a (Most si gni fican t word )+FFEH

Char act er Patter n 31 -3 1 Pat ter n Name Dat a (Le ast sig ni fica nt word )

1

2

+000
+002

+004
+006

+008
+00A

1

+080
+082

+084
+086

+088
+08A

30

+ F0 0+ F0 2+ F0 4+ F0 6

31

+F8 0
+F8 2

+ F8 4+ F8 6

Co

Char act er
Pat ter n 0

29

30

31

+074
+076

+078
+07A

+07C
+07E

+ 0F 4+ 0F 6

+0F8
+0FA

+0F C
+0FE

nfi

Ch ar act er
Pattern 0

de+0 00 H

Cha ra ct er Pat ter n 0-0 Pat tern Nam e Dat a (Mo st si gn ificant wor d)+ F0 8
+F0 A

+F7 4
+F7 6

+ F7 8
+F7 A

+F 7C
+F7 E

+F8 8
+F8 A

+F F4
+F F6

+FF8
+F FA

+F FC
+F FE

Pag e

SE

GA

No te 1: The up pe r- lef t no tat io n in the pag e is ch ar act er pa ttern 0- 0; to the righ t ar echa ra ct er pat ter ns 0-1 , 0-2 , 0-3 , ...
No te 2: Num be rs in the pag es are VRAM adr esse s (Hexad eci mal ) of pa ttern na me
da ta of ch ar act er pa ttern s, with VRAM ad dr ess of char act er pat tern 0-0
pa tter n na me da ta as the re fere nce .

ST-58-R2

397

• Bitmap Pattern Data Specifications

512 H dots X
512 V dots

1024 H dots X
256 V dots

Size per Surface

16 colors
256 colors
2048 colors, 32,768 colors
16,770,000 colors
16 colors
256 colors
2048 colors, 32,768 colors
16,770,000 colors
16 colors
256 colors
2048 colors, 32,768 colors
16,770,000 colors
16 colors
256 colors
2048 colors, 32,768 colors

64K bytes
128K bytes
256K bytes
512K bytes
128K bytes
256K bytes
512K bytes
1024K bytes
128K bytes
256K bytes
512K bytes
1024K bytes
256K bytes
512K bytes
1024K bytes

SE

GA

Co

nfi

1024 H dots X
512 V dots

Bitmap Color Countntial

512 H dots X
256 V dots

Bitmap Pattern
Data Size
4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot
4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot
4 bits/dot
8 bits/dot
16 bits/dot
32 bits/dot
4 bits/dot
8 bits/dot
16 bits/dot

398(512K bits)(1M bits)(2M bits)(4M bits)(1M bits)(2M bits)(4M bits)(8M bits)(1M bits)(2M bits)(4M bits)(8M bits)(2M bits)(4M bits)(8M bits)deBitmap Size• Bitmap Patternntial(1) Bit ma p Size : 512 H dot s X 25 6 V dot s
Bit ma p Colo r Coun t : 4 bits/ dot (1 6 co lor s)
Bit ma p Pat ter n (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Dot 0- 0

Dot 0- 1

Dot 0- 2

Dot 0- 3+0 00 2H

Dot 0- 4

Dot 0- 5

Dot 0- 6

Dot 0- 7+FFFEH

Dot 25 5- 50 8

Dot 25 5- 50 9

Dot 25 5- 51 0

Dot 25 5- 511

1

Dot 0

1

3

50 8

50 9

51 0

511

+ 00 00

+0001

+00FE

+00F F

+0100

+0101

+01FE

+01FF

+F E0 0

+FE 01

25 5+F F0 0

+F F0 1+FE FE

Co

25 4

nfi

Dot 0

2

de

+0 00 0H

+FFF E

Bitmap+FE FE+FF FF

SE

GA

Note 1: The upp er lef t not ation in the cel l is do t 0-0 ; to the righ t are do t 0-1 ,dot 0- 2, do t 0-3 , ...
Note 2: Nu mber s in the ce l s are VRAM ad dr esse s (h exa de cim al) of dot (2dot s) dat a, with VRAM add re ss of do t 0-0 , 0-1 da ta as therefer en ce.

ST-58-R2

399

Bitmap Pattern (Continued)ntial(2 ) Bitmap Size : 512 H do ts X 25 6 V do ts
Bitmap Col or Coun t : 8 bit s/ do t (25 6 co lor s)

14 13 12 11

10

9

8

7

6

5

4

3

+00 00 0H

Dot 0- 0

Do t 0-1+00 00 2H

Do t 0-2

Do t 0-3+1F FFEH

Do t 255 -5 10

Do t 255 -5 11

Do t 0

1

2

3

508

509

1

0

510

511

+000 00 +0 000 1 +000 02 +0 000 3+0 01F C +00 1F D +001 FE +0 01F F+002 00 +0 020 1 +002 02 +0 020 3+0 03F C +00 3F D +003 FE +0 03F F

nfi

Dot 0

1

2

de

Bitmap Pattern (VRAM)
Bit 15

Bitmap25 5 +1 FE0 0 +1F E01 +1 FE0 2 +1F E03+1F DF C +1 FD FD +1F DF E +1F DF F

Co

25 4 +1F C0 0 +1F C01 +1F C0 2 +1F C03+1F FFC +1F FF D +1 FF FE +1F FFF

SE

GA

Note 1: The upp er lef t no tation in the cel l is do t 0-0 ; to the righ t are do t 0-1 ,dot 0- 2, do t 0-3 , ...
Note 2: Nu mb er s in the ce l s are VRAM add re sses (h exadeci mal ) of do t
dat a, with VRAM add re ss of do t 0-0 da ta as the re fer ence.

400(3) Bit ma p Size : 512 H dot s X 25 6 V dot s
Bit ma p Colo r Coun t : 16 bi ts/ dot (204 8 col or s, 327 68 col ors)
Bitmap Pat ter n (VRAM)
Bit 15

14

13

12

11

10

9

8

7

+00 00 2H

Dot 0-1+3F FFEH

Do t 255 -5 11

1

2

3

+00 000 +000 02 +00 004 +000 06

Do t 01+00 400 +004 02 +00 404 +004 06

4

3

2

1

0

50 8

50 9

51 0

511

+0 03F 8 +0 03F A +003 FC +0 03F E+0 07F 8 +0 07F A +007 FC +0 07F E

Bitmap+3F BF8 +3F BFA +3 FBF C +3F BF E

Co

25 4 +3F 80 0 +3 F8 02 +3F 80 4 +3 F8 06

5

nfi

Dot 0

6

de

+00 00 0H

Dot 0- 0ntial• Bitmap Pattern (Continued)

25 5 +3 FC 00 +3F C0 2 +3 FC 04 +3F C0 6

+3F FF8 +3F FFA +3 FF FC +3F FFE

SEGA

Not e 1: The upp er lef t no tat io n in the ce ll is dot 0- 0; to the righ t ar e do t 0-1 ,dot 0- 2, dot 0- 3, ...
Not e 2: Numb er s in the cel ls are VRAM add re sses (hexad eci mal ) of do t
dat a, with VRAM ad dr ess of dot 0- 0 da ta as the re fer en ce.

ST-58-R2

401

(4) Bit ma p Size : 512 H dot s X 25 6 V dot s
Bit ma p Colo r Coun t : 32 bi ts/ do t (16 ,77 0, 000 col ors)
Bitmap Pat ter n (V RA M)
Bit 15

14

13

12

11

10

9

8

7

6

+0 00 00 H

Dot 0-0 (upp er wor d)+0 00 02 H

Dot 0- 0 (l ow er wo rd )+0000 4H

Dot 0-1 (upp er wor d)

3

2

509

510

1

0

1

2

3

508

511

nfi

Dot 0

de

Dot 25 5- 511 (lo wer wor d)+7F FFEH

1

4

Do t 255 -5 11 (up pe r wo rd )+7 FFFCH

Dot 0

5

nti
al

• Bitmap Pattern (Continued)+0 000 0 +00 004 +0 000 8 +0 000 C+007 F0 +00 7F 4 +007 F8 +007 FC+0 080 0 +00 804 +0 080 8 +0 080 C+0 0F F0 +00 FF 4 +0 0F F8 +0 0F FC

254+7 F0 00 +7F 004 +7 F0 08 +7 F0 0C

255+7 F8 00 +7F 804 +7 F8 08 +7 F8 0C

CoBitma p+7F 7F 0 +7F 7F 4 +7 F7 F8 +7 F7 FC+7 FF F0 +7F FF 4 +7 FF F8 +7 FF FC

SEGA

No te 1: The up per left not ation in the cel l is do t 0-0 ; to the ri gh t are dot 0-1,
dot 0- 2, do t 0-3 , ...
No te 2: Num be rs in the ce lls ar e VRA M ad dr esse s (h exa de cim al) of dot
dat a (up pe r wo rd) , with VRAM ad dr ess of dot 0- 0 da ta (uppe r wor d) as
the ref ere nce .

402

• Bitmap Pattern (Continued)ntial(5 ) Bitmap Size : 512 H do ts X 51 2 V do ts
Bitmap Col or Coun t : 4 bit s/ do t (16 col ors)
Bitmap Pattern (VRAM)
10

Do t 0-0

Do t 0-1

Do t 0-2

Do t 0-3+0 00 02H

Do t 0-4

Do t 0-5

Do t 0-6

Do t 0-7+1F FFEH

Do t 511- 50 8

Do t 511- 50 9

Do t 511- 51 0

Do t 511- 511

1

Do t 0
Dot 0

1

2

3

9

8

7

6

5

4

3

2

1

0

50 8

50 9

51 0

511

+00000+00001+000FE+000FF+00100+00101+001FE+001FF+1F E0 0+1F E0 1511+1FF0 0

+1FF0 1

+1F EFE

Co

510

nfi

Bit 15de

14 13 12 11+0 00 00H

+ 1F FFE

Bitmap+ 1F EF F+1FFFFSEGA

Not e 1: The upp er lef t no tat io n in the ce l is dot 0- 0; to the right ar e do t 0- 1,
dot 0-2, dot 0- 3, ...
Not e 2: Numb er s in the cel ls ar e VRAM add re sses (hexadeci mal ) of do t (2dot s) dat a, with VRAM ad dr ess of dot 0- 0, 0- 1 da ta as theref erence .

ST-58-R2

403

• Bitmap Pattern (Continued)

ntial(6) Bitmap Size : 512 H dots X 512 V dots
Bitmap Color Count : 8 bits/dot (256 colors)

Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

+00000H

Dot 0-0

Dot 0-1+00002H

Dot 0-2

Dot 0-3+3FFFEH

Dot 511-510

Dot 511-511

Dot 0

1

2

3

508

509

1

0

510

511

+00000 +00001 +00002 +00003+001FC +001FD +001FE +001FF+00200 +00201 +00202 +00203+003FC +003FD +003FE +003FF

nfi

Dot 0

1

2

de

Bitmap Pattern (VRAM)

Bitmap+3FC00 +3FC01 +3FC02 +3FC03

511+3FE00 +3FE01 +3FE02 +3FE03+3FDFC +3FDFD +3FDFE +3FDFF

Co

510

+3FFFC +3FFFD +3FFFE +3FFFF

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

404

(7) Bitmap Size : 512 H dots X 512 V dots
Bitmap Color Count : 16 bits/dot (2048 colors, 32768 colors)
Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

Dot 0-0+00002H

Dot 0-1+7FFFEH

Dot 511-511

Dot 0

1

2

3

5

4

3

2

1

0

508

509

510

511

+00000 +00002 +00004 +00006+003F8 +003FA +003FC +003FE+00400 +00402 +00404 +00406+007F8 +007FA +007FC +007FE+7F800 +7F802 +7F804 +7F806

511+7FC00 +7FC02 +7FC04 +7FC06

Bitmap+7FBF8 +7FBFA +7FBFC +7FBFE+7FFF8 +7FFFA +7FFFC +7FFFE

Co

510

nfi

Dot 0

1

6

de

+00000Hntial• Bitmap Pattern (Continued)

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

ST-58-R2

405

(8) Bitmap Size : 512 H dots X 512 V dots
Bitmap Color Count : 32 bits/dot (16,770,000 colors)
Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

2

509

510

1

0

Dot 0-0 (lower word)+00004H

Dot 0-1 (upper word)+FFFFCH

Dot 511-511 (upper word)+FFFFEH

Dot 511-511 (lower word)

1

2

3

508

511

nfi

Dot 0

de

+00002H

1

3

Dot 0-0 (upper word)+00000H

Dot 0

4

nti
al

• Bitmap Pattern (Continued)+00000 +00004 +00008 +0000C+007F0 +007F4 +007F8 +007FC+00800 +00804 +00808 +0080C+00FF0 +00FF4 +00FF8 +00FFC

510+FF000 +FF004 +FF008 +FF00C

511+FF800 +FF804 +FF808 +FF80C

Co

Bitmap+FF7F0 +FF7F4 +FF7F8 +FF7FC+FFFF0 +FFFF4 +FFFF8 +FFFFC

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data (upper word), with VRAM address of dot 0-0 data (upper word) as
the reference.

406

• Bitmap Pattern (Continued)

ntial(9) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 4 bits/dot (16 colors)
Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Dot 0-0

Dot 0-1

Dot 0-2

Dot 0-3+00002H

Dot 0-4

Dot 0-5

Dot 0-6

Dot 0-7+1FFFEH

Dot 255-1020

Dot 255-1021

Dot 255-1022

Dot 255-1023

1

Dot 0

1

3

1020

1021 1022

1023+00000+00001+001FE+001FF+00200+00201+003FE+003FF+1FC00+1FC01255+1FE00+1FE01+1FDFE

Co

254

nfi

Dot 0

2

de

+00000H+1FFFE

Bitmap+1FDFF+1FFFF

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot (2dots) data, with VRAM address of dot 0-0, 0-1 data as thereference.

ST-58-R2

407

(10) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 8 bits/dot (256 colors)
Bitmap Pattern (VRAM)
14

13

12

11

10

9

8

7

6

5

4

3

2

+00000H

Dot 0-0

Dot 0-1+00002H

Dot 0-2

Dot 0-3+3FFFEH

Dot 255-1022

Dot 255-1023

Dot 0

1

2

3

1020

0

1021 1022

1023+00000 +00001 +00002 +00003+003FC +003FD +003FE +003FF+00400 +00401 +00402 +00403+007FC +007FD +007FE +007FF

nfi

Dot 0

1

1

de

Bit 15ntial• Bitmap Pattern (Continued)

Bitmap+3F800 +3F801 +3F802 +3F803

255+3FC00 +3FC01 +3FC02 +3FC03+3FBFC +3FBFD +3FBFE +3FBFF

Co

254

+3FFFC +3FFFD +3FFFE +3FFFF

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

408

(11) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 16 bits/dot (2048 colors, 32768 colors)
Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

Dot 0-0+00002H

Dot 0-1+7FFFEH

Dot 255-1023

Dot 0

1

2

3

4

3

2

1

0

1020

1021 1022

1023+00000 +00002 +00004 +00006+007F8 +007FA +007FC +007FE+00800 +00802 +00804 +00806+00FF8 +00FFA +00FFC +00FFE+7F000 +7F002 +7F004 +7F006

255+7F800 +7F802 +7F804 +7F806

Bitmap+7F7F8 +7F7FA +7F7FC +7F7FE

Co

254

nfi

Dot 0

1

5

de

+00000H

6ntial• Bitmap Pattern (Continued)+7FFF8 +7FFFA +7FFFC +7FFFE

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

ST-58-R2

409

(12) Bitmap Size : 1024 H dots X 256 V dots
Bitmap Color Count : 32 bits/dot (16,770,000 colors)
Bitmap Pattern (VRAM)
14

13

12

11

10

9

8

7

6

5

Dot 0-0 (upper word)+00002H

Dot 0-0 (lower word)+00004H

Dot 0-1 (upper word)+FFFFCH

Dot 255-1023 (upper word)+FFFFEH

Dot 255-1023 (lower word)

Dot 0

1

1

2

3

1020

3

2

1

0

1021 1022

1023

nfi

Dot 0

4

de

Bit 15+00000Hntial• Bitmap Pattern (Continued)+00000 +00004 +00008 +0000C+00FF0 +00FF4 +00FF8 +00FFC+01000 +01004 +01008 +0100C+01FF0 +01FF4 +01FF8 +01FFC

254+FE000 +FE004 +FE008 +FE00C

255+FF000 +FF004 +FF008 +FF00C

Co

Bitmap+FEFF0 +FEFF4 +FEFF8 +FEFFC+FFFF0 +FFFF4 +FFFF8 +FFFFC

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data (upper word), with VRAM address of dot 0-0 data (upper word)
as the reference.

410

(13) Bitmap Size : 1024 H dots X 512 V dots
Bitmap Color Count : 4 bits/dot (16 colors)
Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

5

4

3

2

nti
al

• Bitmap Pattern (Continued)

10

Dot 0-0

Dot 0-1

Dot 0-2

Dot 0-3+00002H

Dot 0-4

Dot 0-5

Dot 0-6

Dot 0-7+3FFFEH

Dot 511-1020

Dot 511-1021

Dot 511-1022

Dot 511-1023

1

Dot 0

1

3

1020

1021 1022

1023+00000+00001+001FE+001FF+00200+00201+003FE+003FF+3FC00+3FC01511+3FE00+3FE01+3FDFE

Co

510

nfi

Dot 0

2

de

+00000H+3FFFE

Bitmap+3FDFF+3FFFF

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot (2dots) data, with VRAM address of dot 0-0, 0-1 data as thereference.

ST-58-R2

411

(14) Bitmap Size : 1024 H dots X 512 V dots
Bitmap Color Count : 8 bits/dot (256 colors)
Bitmap Pattern (VRAM)
14

13

12

11

10

9

8

7

6

5

4

3

2

Dot 0-0

Dot 0-1+00002H

Dot 0-2

Dot 0-3+7FFFEH

Dot 511-1022

Dot 511-1023

Dot 0

1

2

3

1020

0

1021 1022

1023+00000 +00001 +00002 +00003+003FC +003FD +003FE +003FF+00400 +00401 +00402 +00403+007FC +007FD +007FE +007FF

nfi

Dot 0

1

1

de

Bit 15+00000Hntial• Bitmap Pattern (Continued)

Bitmap+7F800 +7F801 +7F802 +7F803

511+7FC00 +7FC01 +7FC02 +7FC03+7FBFC +7FBFD +7FBFE +7FBFF

Co

510

+7FFFC +7FFFD +7FFFE +7FFFF

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

412

(15) Bitmap Size : 1024 H dots X 512 V dots
Bitmap Color Count : 16 bits/dot (2048 colors, 32768 colors)
Bitmap Pattern (VRAM)
Bit 15

14

13

12

11

10

9

8

7

6

+00002H

Dot 0-1+FFFFEH

Dot 511-1023

Dot 0

1

2

3

4

3

2

1

0

1020

1021 1022

1023+00000 +00002 +00004 +00006+007F8 +007FA +007FC +007FE+00800 +00802 +00804 +00806+00FF8 +00FFA +00FFC +00FFE+FF000+FF002 +FF004

511+FF800+FF802 +FF804+FF006

Bitmap+FF7F8 +FF7FA +FF7FC +FF7FE

Co

510

nfi

Dot 0

1

5

de

+00000H

Dot 0-0ntial• Bitmap Pattern (Continued)+FF806+FFFF8 +FFFFA +FFFFC +FFFFE

SE

GA

Note 1: The upper left notation in the cell is dot 0-0; to the right are dot 0-1,
dot 0-2, dot 0-3, ...
Note 2: Numbers in the cells are VRAM addresses (hexadecimal) of dot
data, with VRAM address of dot 0-0 data as the reference.

ST-58-R2

413

Hor izon tal , Vert ica l Scr ee n Scro ll Va lue
Bit 15+OH
Bit 15+2H

14 13 12 11

10

9

8

7

6
5
4
3
2
Intege r Part : 11 b its

1

0

14 13 12 11 10 98
Fr act iona l Part : 8 bit s

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Hor izon tal Coo rdi na te Incr em en t
Bit 1514 13 12 11

10

9

8

+0H

14 13 12 11 10 98
Fr act iona l Part : 8 bi ts

7

6

4

3

2

1

0

SE

GA

Co

nfi

No te: Shad ed ar ea s ar e ig no re d5deInteg er Part : 3 bi ts

Bit 15+2Hntial• Line Scroll Table Data Bit Configuration

414

When selecting horizontal and vertical screen scroll values andhorizontal coordinate increment for every 1 line.

Line Scroll Table
Address

Bit 15
Line Scroll Table (VRAM)+00H Line 1 Horiz. Screen Scroll Value (Integer Part)nti
al• Example of Line Scroll Table

0+02H Line 1 Horiz. Screen Scroll Value (Fractional Part)+04H Line 1 Vertical Screen Scroll Value (Integer Part)+06H Line 1 Vertical Screen Scroll Value (Fractional Part)+08H Line 1 Horiz. Coordinate Increment (Integer Part)+0AH Line 1 Horiz. Coordinate Increment (Fractional Part)+0CH Line 2 Horiz. Screen Scroll Value (Integer Part)+0EH Line 2 Horiz. Screen Scroll Value (Fractional Part)de+10H Line 2 Vertical Screen Scroll Value (Integer Part)+12H Line 2 Vertical Screen Scroll Value (Fractional Part)+14H Line 2 Horiz. Coordinate Increment (Integer Part)+16H Line 2 Horiz. Coordinate Increment (Fractional Part)Line Scroll Table
Addressnfi

When selecting vertical screen scroll value and horizontal coordinate
increment for every 2 lines (no horizontal line scroll).

Bit 15
Line Scroll Table (VRAM)+00H Line 1 Vertical Screen Scroll Value (Integer Part)

0+02H Line 1 Vertical Screen Scroll Value (Fractional Part)+04H Line 1, 2 Horiz. Coordinate Increment (Integer Part)+06H Line 1, 2 Horiz. Coordinate Increment (Fractional Part)

Co+08H Line 3 Vertical Screen Scroll Value (Integer Part)+0AH Line 3 Vertical Screen Scroll Value (Fractional Part)+0CH Line 3, 4 Horiz. Coordinate Increment (Integer Part)+0EH Line 3, 4 Horiz. Coordinate Increment (Fractional Part)

Note: Display coordinates in the vertical direction for lines not
specified are obtained by adding coordinate increments in thevertical direction to the vertical screen scroll values for the lines
specified.

GA

When selecting horizontal screen scroll value and horizontal
coordinate increment for every 4 lines (no horizontal line scroll).
Line Scroll Table (VRAM)
Bit 15
Line Scroll Table
Address

0+00H Line 1~4 Horiz. Screen Scroll Value (Integer Part)+02H Line 1~4 Horiz. Screen Scroll Value (Fractional Part)+04H Line 1~4 Horiz. Coordinate Increment (Integer Part)+06H Line 1~4 Horiz. Coordinate Increment (Fractional Part)+08H Line 5~8 Horiz. Screen Scroll Value (Integer Part)+0AH Line 5~8 Horiz. Screen Scroll Value (Fractional Part)

SE+0CH Line 5~8 Lines Horiz. Coordinate Increment (Integer Part)

ST-58-R2+0EH Line 5~8 Lines Horiz. Coordinate Increment (Fractional Part)

415

• Vertical Cell Scroll Table Data Bit Configuration

Bit 15

14

13

12

11

10

9

8

7

14

13 12 11 10 9
8 bit fractional part

8

7

+0H

Bit 15+2H

6
54
3
11 bit integer part

6

5

4

3

2

1

0

2

1

0

SE

GA

Co

nfi

de

Note: Shaded area is ignorednti
alVertical Screen Scroll Value

416

NBG0 Vertical Cell Scroll
Bit 15
Vertical Cell Scroll
Table Address

Vertical Cell Scroll Table (VRAM)

ntial• Example of Vertical Cell Scroll Table

0+00H NBG0 1st cell vertical screen scroll value (integer part)+02H NBG0 1st cell vertical screen scroll value (fractional part)+04H NBG0 2nd cell vertical screen scroll value (integer part)+06H NBG0 2nd cell vertical screen scroll value (fractional part)+08H NBG0 3rd cell vertical screen scroll value (integer part)+0AH NBG0 3rd cell vertical screen scroll value (fractional part)+0CH NBG0 4th cell vertical screen scroll value (integer part)+0EH NBG0 4th cell vertical screen scroll value (fractional part)

NBG1 Vertical Cell Scroll
Bit 15

Vertical Cell Scroll Table (VRAM)

0

+00H

NBG1 1st cell vertical screen scroll value (integer part)+02H

NBG1 1st cell vertical screen scroll value (fractional part)+04H

NBG1 2nd cell vertical screen scroll value (integer part)+06H

NBG1 2nd cell vertical screen scroll value (fractional part)+08H

NBG1 3rd cell vertical screen scroll value (integer part)nfi

Vertical Cell Scroll
Table Addressde+10H NBG0 5th cell vertical screen scroll value (integer part)+12H NBG0 5th cell vertical screen scroll value (fractional part)+0AH NBG1 3rd cell vertical screen scroll value (fractional part)+0CH NBG1 4th cell vertical screen scroll value (integer part)+0EH NBG1 4th cell vertical screen scroll value (fractional part)
NBG1 5th cell vertical screen scroll value (integer part)+12H

NBG1 5th cell vertical screen scroll value (fractional part)

Co

+10H

NBG0 and NBG1 Vertical Cell Scroll
Bit 15
Vertical Cell Scroll
Table Address

Vertical Cell Scroll Table (VRAM)

0+00H NBG0 1st cell vertical screen scroll value (integer part)+02H NBG0 1st cell vertical screen scroll value (fractional part)+04H NBG1 1st cell vertical screen scroll value (integer part)

GA+06H NBG1 1st cell vertical screen scroll value (fractional part)+08H NBG0 2nd cell vertical screen scroll value (integer part)+0AH NBG0 2nd cell vertical screen scroll value (fractional part)+0CH NBG1 2nd cell vertical screen scroll value (integer part)+0EH NBG1 2nd cell vertical screen scroll value (fractional part)+10H NBG0 3rd cell vertical screen scroll value (integer part)SE+12H NBG0 3rd cell vertical screen scroll value (fractional part)ST-58-R2

417

• Rotation Parameter Table(Fractional Part)
Screen Start Coordinate Yst(Integer Part)(Fractional Part)

+06H
+08H

Screen Start Coordinate Zst(Integer Part)(Fractional Part)

+0AH
+0CH

Screen Vertical Coordinate Increment ∆Xst

+10H

Screen Vertical Coordinate Increment ∆Yst

Screen Horiz. Coordinate Increment ∆X(Integer Part)(Fractional Part)

+16H
+18H

Screen Horiz. Coordinate Increment ∆Y(Integer Part)(Fractional Part)

+1AH
+1CH

(Integer Part)

Rotation Matrix Parameter A(Fractional Part)

+1EH
+20H

(Integer Part)

Rotation Matrix Parameter B(Fractional Part)

+22H
+24H

(Integer Part)

Rotation Matrix Parameter C

+26H
+28H

(Fractional Part)(Integer Part)

Rotation Matrix Parameter D(Fractional Part)

+2AH
+2CH

(Integer Part)

Rotation Matrix Parameter E(Fractional Part)

+2EH
+30H

(Integer Part)

Rotation Matrix Parameter F(Fractional Part)+34H

Viewpoint Coordinate Px+36H

Viewpoint Coordinate Py+38H

Viewpoint Coordinate Pz
This data is ignored+3CH

Center Point Coordinate Cx+3EH

Center Point Coordinate Cy+40H

Center Point Coordinate Cz

+44H
+46H
+48H
+4AH
+4CH
+4EH
+50H
+52H
+54H
+56H

Horizontal Shift Mx

Horizontal Shift My

+5EH

418

(Integer Part)(Integer Part)(Integer Part)(Integer Part)(Integer Part)(Fractional Part)

Scaling Coefficient kx(Integer Part)(Fractional Part)

Scaling Coefficient ky(Integer Part)(Fractional Part)

Coefficient Table Start Address KAst

(Integer Part)(Fractional Part)

Coefficient Table Vertical Address Increment ∆KAst (Integer Part)

+5AH
+5CH

(Integer Part)(Integer Part)(Fractional Part)

SE

+58H

This data is ignored(Integer Part)

GA

+42H

Co

+32H

+3AH

(Integer Part)(Fractional Part)

+12H
+14H

(Integer Part)(Fractional Part)

+0EH

de

+04H

nti
al

(Integer Part)

Screen Start Coordinate Xst

nfi

+00H
+02H

Coefficient Table Horiz. Address Increment ∆KAx

(Fractional Part)(Integer Part)(Fractional Part)• Coefficient Table Data Bit Configuration
Coe ffici en t Dat a Mod e 0~2

Bit 15

14

13

12

11

10

+2 H

8

7
6
Sign

5

9
8
7
6
5
16 bi t fra ct ion al par t

Coe ffici en t Dat a Size : 1 wor d
Tra nsp ar en cy
14 13 12 11 10
Sign 4 bit int ege r pa rt

Bit 15
+0 H

9

8

7

4
3
2
1
7 bi t integ er par t

4

3

2

1

0

0

de

Coe ffici en t Dat a Size : 2 wor ds
Tra nsp ar en cy
Bit 1514 13 12 11 10 9
7 bi t line col or scre en da ta
+0 H

nti
al

Mode 0: Used as Scale Coefficients kx and ky
Mode 1: Used as Scale Coefficients coefficient kx
Mode 2: Used as Scale Coefficients coefficient kyMode 3: Used as viewpoint coordinate Xp after rotation conversion

6
5
4
3
2
10 bi t fra ct ion al pa rt

1

0

Coe ffici ent Dat a Mod e 3

Bit 15 14
+2 H

8

7
6
Sign

5
4
3
2
1
0
Integ er par t MSB 7 bits

7

5
4
3
2
1
8 bi t fra ct ion al par t

Co

Coe ffici ent Dat a Size : 2 wo rds
Tr an spa re ncy
Bit 1514 13 12 11 10 9
7 bi t line col or scre en da ta
+0 H

nfi

No te: The MS B are si gn -e xpa nd ed by 3 bit s an d the LS B are 0- exp an de dby 6 bi ts to be of equ al to the num ber of bi ts as in the case of 2 wo rd s.

13 12 11 10 9Int eg er pa rt LS B 8 bi ts

10

6

9
8
7
6
5
12 bit int ege r pa rt

4

3

2

1

0

0
2 bit fract iona l pa rt

GA

Coe ffici ent Dat a Size : 1 wo rd
Tr an spa re ncy
Bit 1514 13 12 11
Sign
+0 H

8

SE

Not e: The MSB ar e sig n- exp an de d by 3 bi ts and the LSB ar e 0-expa nd edby 6 bits to be of eq ua l to the nu mbe r of bits as in the ca se of 2 wor ds.

ST-58-R2

419

Bit 15

14

13

12

11

10

9

8
7
6
5
4
3
11 bit color Ram address

2

1

0

Note: Shaded are is ignored. Also, when color RAM is in mode 0 or mode 2, theMSB of the address is ignored.

• Line Color Screen Table
Non-interlace and double-density interlace mode

1st Line Color RAM Address+02H

2nd Line Color RAM Address+04H

3rd Line Color RAM Address+06H

4th Line Color RAM Address+08H

5th Line Color RAM Address+0AH

6th Line Color RAM Address0Note: In the case of single color, the 1st line color RAM
address is used in the entire line color screen. In the case of
double-density interlace, line data of odd and even fields are
stored together.

Single-density interlace modeBit 15+00H

1st and 2nd Line Color Ram Address+02H

3rd and 4th Line Color Ram Address+04H

5th and 6th Line Color Ram Address

0CoLine Color Screen Table (VRAM)+06H

7th and 8th Line Color Ram Address+08H

9th and 10th Line Color Ram Address+0AH

11th and 12th Line Color Ram Address

SE

GA

Note: In the case of single color, the 1st and 2nd line color
RAM addresses are used in the entire line color screen.

420

de

Line Color Screen Table (VRAM)

nfi

Bit 15
+00H

nti
al

• Line Color Screen Table Data Bit Configuration

Bit 15

14 13 12 11
5 bit Blue Data

10

9
8
7
6
5 bit Green Data

5

4
3
2
1
5 bit Red Data

Note: Shaded area is ignored. Add 0 bit 3 bits at a time to the lower bitsof RGB to make 8 bits.

• Back Screen Table
Non-interlace and double-density interlace mode

Back Screen Table (VRAM)

0

1st Line RGB Data

+02H

2nd Line RGB Data

+04H

3rd Line RGB Data

+06H

4th Line RGB Data

+08H

5th Line RGB Data

+0AH

6th Line RGB Datade

Bit 15
+00H

0

nti
al

• Back Screen Table Data Bit Configuration

Single-density interlace mode

+02H

Back Screen Table (VRAM)+06H

5th and 6th Line RGB Data
7th and 8th Line RGB Data

+08H

9th and 10th Line RGB Data

+0AH

11th and 12th Line RGB Data

+04H

0

1st and 2nd Line RGB Data
3rd and 4th Line RGB DataCo

Bit 15+00H

nfi

Note: In the case of single color, the 1st line RGB data is usedin the entire line color screen. In the case of double-density
interlace, line data of odd and even fields are stored together.

SE

GA

Note: In the case of single color, the 1st and 2nd line RGB data
are used in the entire line color screen.

ST-58-R2

421

Bit 15

14

13

12

11

10

9
8
7
6
5
4
3
2
1
0
Horizontal Start Point Coordinates (10 bits)

14

13

12

11

10

9
8
7
6
5
4
3
2
1
0
Horizontal End Point Coordinates (10 bits)+0H
Bit 15+2H

Note: Shaded areas are ignored• Normal Line Window Table

Bit 15+00H

1st line horizontal start point coordinates+02H

1st line horizontal end point coordinates+04H

2nd line horizontal start point coordinates+06H

2nd line horizontal end point coordinates+08H

3rd line horizontal start point coordinates

Line Window Table (VRAM)0nfi+0AH 3rd line horizontal end point coordinatesdeNon-interlace or double-density interlace

Note: In the case of double-density interlace, store line data ofboth even and odd fields.

Single-density interlace
Bit 15+00H

1st & 2nd line horizontal start point coordinates+02H

1st & 2nd line horizontal end point coordinates+04H

3rd & 4th line horizontal start point coordinates+06H

3rd & 4th line horizontal end point coordinates+08H

5th & 6th line horizontal start point coordinates

SE

GA+0AH 5th & 6th line horizontal end point coordinates

422

0

Co

Line Window Table (VRAM)

ntial• Normal Line Window Table Data Bit Configuration