105B4329876

Power supply system management & Audio IC

CXD5247GF
Description
The combination of CXD5247and CXD5602 for high performance wearable applications realizes ideal power supply management withlow power consumption.
In addition, CXD5247 also realizes audio input/output functions for the CXD5602 System.

FeaturesPower management block◆Low power consumption (RTC block IQ=3 ㎂ typ.)◆Voltage step down type PFM control DC-DC converter (3ch)◆LDO (5ch)◆RTC (32.768 kHz clock output)◆I2C serial interface◆GPO (8ch)◆Load switch : 1.8V(4ch)◆USB charge function◆Analog front-end for battery power level detection
Audio block◆Original data format for CXD5602◆Amplifier for analog microphone + A/D converter◆Number of channels : 4ch◆PGA setting : 0dB to 21dB, 0.5dB increments◆SNR : 90dB(typ.)◆THD+N : -80dB(typ.)◆Input referred noise : 10uVrms◆S-master BTL Speaker Driver◆Speaker impedance : 8Ω◆THD+N : 54dB
◆Noise level : 10uVrms(typ.)◆POP noise reduction function◆Other functions◆Supported crystals : 24.576MHz/49.152MHz◆GPO(1ch)

1

CXD5247GF

Package
XFBGA 156pin

Structure
CMOS Si monolithic IC

2

CXD5247GF

Contents
Description ................................................................................................................................................................................................. 1
Features....................................................................................................................................................................................................... 1
Package ....................................................................................................................................................................................................... 2
Structure ..................................................................................................................................................................................................... 2
Contents ...................................................................................................................................................................................................... 3
Block Diagram............................................................................................................................................................................................ 6
◆Power management block ................................................................................................................................................................... 6
◆Audio Block ........................................................................................................................................................................................ 7
Application Circuit ..................................................................................................................................................................................... 8
◆Power management block ................................................................................................................................................................... 8
◆Audio block (Case1：Speaker BTL Drive / 4ch Analog MIC)...................................................................................................... 11
◆Audio block (Cace2：External Speaker Amp / 8ch Digtal MIC) ..................................................................................................... 12
Pin Configuration ..................................................................................................................................................................................... 13
Pin Table ................................................................................................................................................................................................... 14
Pin Description ......................................................................................................................................................................................... 19
Absolute Maximum Ratings ..................................................................................................................................................................... 25
Recommended Operating Conditions ....................................................................................................................................................... 26
Electrical Characteristics .......................................................................................................................................................................... 27
◆Power supply Block .......................................................................................................................................................................... 27
Power supply input (VDD, VIO_IN) ................................................................................................................................................ 27
RTC (XI_P, XO_P) ........................................................................................................................................................................... 27
LOAD SW (SW_18_IN, SW_18_OUT1-4) ..................................................................................................................................... 27
IF-IN (PWR_EN, xINT_WKUP_S, xINT_WKUP_L, xINT_SYNC, SCL_P, SDA_P) ................................................................... 27
IF-OUT (CLK_OUT, INT_OUT, xRST_OUT, VBUS_OUT, GPO0-7, DDC_ON) ......................................................................... 28
DDC_IO............................................................................................................................................................................................ 28
DDC_ANA ....................................................................................................................................................................................... 29
DDC_CORE ..................................................................................................................................................................................... 29
LDO_EMMC .................................................................................................................................................................................... 29
LDO_PERI ....................................................................................................................................................................................... 30
LDO_ANA ....................................................................................................................................................................................... 30
1.0V output for USBPHY (LDO_USB10) ........................................................................................................................................ 30
List of DC-DC converter and LDO output register settings .............................................................................................................. 31
◆Analog front-end block for battery power level detection ................................................................................................................ 32
Power supply input (AFE_VDD) ...................................................................................................................................................... 32
Battery voltage, battery temperature measurement (VBAT_VS, TH) ............................................................................................... 32
Battery charge / discharge current measurement (VBT_CS, VSYS_CS).......................................................................................... 32
Battery temperature detection and control (VREF, TH_REF)........................................................................................................... 32
◆Charge control block ......................................................................................................................................................................... 33

3

CXD5247GF

Power path control, shared (VIN, VBT, VSYS)................................................................................................................................ 33
Battery voltage detection and control (VBAT).................................................................................................................................. 33
Charge current detection snd control (CHG_ISET) .......................................................................................................................... 33
Battery temperature detection and control (VREF, TH) .................................................................................................................... 34
3.3V output for USBPHY (LDO_USB33) ........................................................................................................................................ 34
USB detection (DP, DM, DLINE_SW) ............................................................................................................................................. 34
Timers and setup times ..................................................................................................................................................................... 34
◆Audio block ...................................................................................................................................................................................... 35
MICs to serial output characteristics ................................................................................................................................................. 35
serial input to SPOUTs characteristics (Loop OFF) .......................................................................................................................... 35
serial input to SPOUTs characteristics (Loop ON) ........................................................................................................................... 36
DC characteristics ............................................................................................................................................................................. 36
Crystal switching specification ......................................................................................................................................................... 36
Switching specifications and characteristics (serial audio interface form CXD5602)....................................................................... 37
Switching specifications and characteristics (serial audio interface to CXD5602) ........................................................................... 37
digital microphone interface ............................................................................................................................................................. 38
I2C bus switching specification ........................................................................................................................................................ 39
digital input / output signal threshold level ....................................................................................................................................... 39
Power consumption (audio block) .................................................................................................................................................... 40
Description of Functions........................................................................................................................................................................... 41
◆Power supply block........................................................................................................................................................................... 41
◆Analog front-end block for battery power level detection ................................................................................................................ 41
◆Charge control block ......................................................................................................................................................................... 41
◆Audio block ...................................................................................................................................................................................... 42
Power Up constraint.......................................................................................................................................................................... 42
Power Up/Reset assert sequence constraint ...................................................................................................................................... 43
Supported crystals / clocks................................................................................................................................................................ 43
Description of Operation .......................................................................................................................................................................... 44
◆Powersupply block operation sequence ........................................................................................................................................ 44

◆Power supply block state transition diagram..................................................................................................................................... 46
◆AFE block operation timing chart for battery power level detection ................................................................................................ 47
◆Charge control block state transition diagram ................................................................................................................................... 48
◆Charge control block operation timing.............................................................................................................................................. 49
◆Power block – I2C specifications...................................................................................................................................................... 51
◆Power register list ............................................................................................................................................................................. 52
Output control registers..................................................................................................................................................................... 56
Power supply operating mode setting registers ................................................................................................................................. 58
Status control registers ...................................................................................................................................................................... 61
RTC control registers 1 ..................................................................................................................................................................... 65
RTC control registers 2 ..................................................................................................................................................................... 68

4

CXD5247GF

RTC control description .................................................................................................................................................................... 69
Information storage registers ............................................................................................................................................................ 71
Charge control registers .................................................................................................................................................................... 72
AFE control registers ........................................................................................................................................................................ 78
◆Audio interface specifications........................................................................................................................................................... 80
StartUP signal generation.................................................................................................................................................................. 82
PWM conversion .............................................................................................................................................................................. 83
SP Driver........................................................................................................................................................................................... 84
◆MIC signal path ................................................................................................................................................................................ 87
Analog microphone input configuration ........................................................................................................................................... 88
PGA setting ....................................................................................................................................................................................... 88
Digital Microphone interface ............................................................................................................................................................ 92
Serialize ............................................................................................................................................................................................ 92
◆Clock specifications .......................................................................................................................................................................... 95
X’tal Buffer ....................................................................................................................................................................................... 95
I2C specifications ............................................................................................................................................................................. 97
Register Description ................................................................................................................................................................................. 98
◆Power register list ............................................................................................................................................................................. 98
◆Audio register list ........................................................................................................................................................................... 102Package Outline ...................................................................................................................................................................................... 105
Notice ..................................................................................................................................................................................................... 106Purpose of Use of the Products: .......................................................................................................................................................... 106
Safe Design:........................................................................................................................................................................................ 106
Product Information: ........................................................................................................................................................................... 106
EXCLUSION OF WARRANTY ON THE PRODUCTS: .................................................................................................................. 106
LIMITATION OF LIABILITY: .......................................................................................................................................................... 107Compliance with Laws: ...................................................................................................................................................................... 107Governing Law: .................................................................................................................................................................................. 107Notes:.................................................................................................................................................................................................. 1075

CXD5247GF

Block Diagram◆Power management block

Charger

AFE for Fuel Gauge

CHG_VDD

AFE_VDD

AFE_GNDVSYS
VSYS_CS

VIN

CHG_GND

VBAT_CS

CHG_CNT

VIN_DE T

AFE

VIN_OVDETVBAT＿VSVREF

ADC_AMP

VIN_UVDE T

TH_VREF

CHG_STATE

ADC_MUX

CC/CV_Control

TH

ADC_VREF
TH

VSYS

VBAT_VS

TSD

Power Supply

33kHz

OSC

T o Po wer
C on tr ol L og ic

CHG_REF
BGR

adc_data

ADC_CORE

CHG_ISETPWR_EN
VPP
VDD
GND

USB

DM
DP

PWR

Charge Control Logic
DLINE_SW（3.3V）LDO_USB33

DC-DC Controller

PVDD1（DDC_IO）

LX_IO

USB_DM/DP det

PGND1Register

SNS_IO

ChargeState Machine

DC-DC Controller（DDC_CORE）

LDO_USBPHY33

PVDD2
LX_CORE
PGND2
SNS_CORE

DC-DC Controller（DDC_ANA）

PVDD3
LX_ANA
PGND3

RTC

SNS_ANA

XI_P

Power Control Logic
Xʼtal
OSC

RegisterLDO_ANA

32kHz

LDO_ANA_IN
LDO_ANA_OUT

Power
State Machine

XO_P

LDO_EMM C

LDO_EMMC_IN
LDO_EMMC_OUT

adc_dataIF

LDO_PE RI

VIO_IN

SDA_P
SCL_P

LDO_PERI_OUT

I2C slave

LDO_USBPHY10

CLK_OUTINT_OUTVBUS_OUTxRST_OUT
xINT_SYNC

xINT_WKUPSxINT_WKUPLGPOLDO_USB10PWR_REF
BGR

IO_INT_WKUP_S

LOAD SW
SW_18_IN

OTP
SW_18_OUT1
SW_18_OUT2
SW_18_OUT3
SW_18_OUT4

IO_INT_WKUP_L

TESTC2TESTA2TESTA3TESTA4TESTA5TEST1_P
TEST2_P
TEST3_PTESTP1TESTP2TESTC1TESTA1

GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7

DDC_ON6

CXD5247GF◆Audio BlockAGND_DRVAMICA
MICAREF

Gate
DriverΔΣADC

MICBREFSPAN
AGND_DRVAB

MICC

ΔΣADC

MICCREF
MICD

ADC
SignalProc.

S-Master
Encoder

Gate
DriverGate
DriverREFGENMICBIAS

VBAT2
AGND_OSC

Xʼtal Oscillator
BufferSPBP
AGND_DRVBSP REFGENLDO

VMBFILTMICBIASAMICBIASBSPBN
AVDD_DRVBΔΣADC

MICDREF

AVDD_MICVBAT1
AGND_MICSPAP
AVDD_DRVAMICB

MIC_REF

Gate
Driver

ΔΣADC

CKGEN

Control Logic
CXD5602 I/F

REG
I/F

XO_A
XI_A

7

AVDD_DRVSPVM
AGND_DRVDVDD
DGND
MCLKOUTFSCLK
AD_DATA
DA_DATAXRESETCXD5247GF

Application Circuit◆Power management block

ChargerUSB

AFE for Fuel Gauge

CHG_VDD

AFE_GND

VIN

V

AFE_VDDVSYS
VSYS_CSDD+

CHG_GND

VBAT_CS

CHG_CNT

VIN_DETGAFE

VIN_OVDETVBAT＿VSVREF

ADC_AMP

VIN_UVDET

TH_VREF

CHG_STATE

ADC_MUX

CC/CV_Control

TH

Battery Pack

ADC_VREF
TH

VSYS

VBAT_VS

TSD

Protec tion
IC

Power Supply

33kHz

OSC

adc_data

CHG_REF
BGR

T o Po wer
C on tr ol L og ic

ADC_CORE

CHG_ISETPWR_EN
VPP
VDD
GND

USB

DM
DP

PWR
PVDD1

（DDC_IO）

LX_IO

DLINE_SW（3.3V）

1.8V

PGND1

RegisterCharge Control Logic

LDO_USB33

DC-DC Controller
USB_DM/DP det

SNS_IO

ChargeState Machine

DC-DC Controller（DDC_CORE）

LDO_USBPHY33

PVDD2

1.0V
LX_CORE
PGND2

3.3V

SNS_CORE

DC-DC Controller（DDC_ANA）

PVDD3
LX_ANA

0.9V

PGND3

RTC

SNS_ANA

XI_P

Power Control Logic
Xʼtal
OSC

RegisterLDO_ANA

32kHz

LDO_ANA_IN

XO_P

LDO_EMM C

LDO_EMMC_IN
LDO_EMMC_OUT

adc_dataIF

1.8V

LDO_PERILDO_PERI_OUT

VIO_IN

SDA_P
SCL_P

I2C slave

LDO_USBPHY10GPO

CLK_OUTINT_OUTVBUS_OUTxRST_OUT
xINT_SYNC

xINT_WKUPSxINT_WKUPL

0.7V

LDO_ANA_OUT

Po werState Machine

LOAD SW

BGR

SW_18_IN

IO_INT_WKUP_S

OTP
SW_18_OUT1
SW_18_OUT2
SW_18_OUT3
SW_18_OUT4

IO_INT_WKUP_L

TESTC2TESTA2TESTA3TESTA4TESTA5TEST1_P
TEST2_P
TEST3_PTESTP1TESTP2TESTC1TESTA1

GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7

DDC_ON

8

3.3V

1.0V
LDO_USB10PWR_REF

3.3V

CXD5247GF

Power management block
Open-pin
Connect-pin:: VIN, CHG_STATE, CHG_ISET, DP, DM, DLINE_SW, LDO_USB33
CHG_GND to GND

Power management block
Open-pin
Connect-pin:(Case : Nonuse of charge function)(Case : Nonuse of charge function and fuel gauge function): VIN, CHG_STATE, CHG_ISET, DP, DM, DLINE_SW, LDO_USB33,TH_VREF, TH
VSYS, VSYS_CS, VBAT_CS, VBAT_VS, AFE_VDD (VDD), CHG_GND to GND

External-part: VREF - 0.22uF, VBAT_VS - 1uF

9

CXD5247GF

Power management block
Open-pin(Case : Nonuse of power supply): LX_xxx

Connect-pin : SNS_xxx to PVDD (VDD), LDO_EMMC_OUT( or PERI_OUT or USB10) to LDO_EMMC_IN

DC-DC Controller（DDC_xxx）

PVDDx
LX_xxx
PGNDx
SNS_xxx

LDO_ANALDO_ANA_IN
LDO_ANA_OUT

LDO_EMMCLDO_EMMC_IN
LDO_EMMC_OUT

LDO_PERILDO_PERI_OUT

LDO_USBPHY10
LDO_USB1010

CXD5247GF◆Audio block (Case1：Speaker BTL Drive / 4ch Analog MIC)


VBAT1
VBAT2

CLKOUT_DMIC

Open

MIC_REF

22uF

VMBFILT

10uF

AVDD_MIC
AVDD_DRVA
AVDD_DRVBAVDD_DRVDVDD

AGND_MICAGND_OSC

MICA

1.0uF

MICA_REFOpen

MICB_REF

Open

MICB

1.0uF

Microphone

2.2kΩ

MICBIASA

2.2kΩ

2.2uF

Microphone

AGND_DRVA

DGND

xxΩ

xxΩ

DVDD

1.0uF

MICC_REFOpen

MICD_REF

Open

MICD

1.0uF

MICBIASB
SDA_A

2.2uF

SCL_A

SPAP

XRESET

CXD5602

MCLKOUTSPAN

AD_DATA

SPBP

FSCLK
DA_DATA

SPBN
SPVM

xxF

10uF

XI_A
GPO_A
XO_A
xxF

xxΩ

11

Open

Microphone
2.2kΩ

AGND_DRV

MICC

2.2kΩ

AGND_DRVB

MicrophoneCXD5247GF◆Audio block (Cace2：External Speaker Amp / 8ch Digtal MIC)12

CXD5247GF

Pin Configuration

A

B

C

D

E

F

G

H

J

K

L

M

LDO_EM
MC_IN

LDO_PER
I_OUT

LDO_USB
10

GND1

XI_P

１

VIN2

VIN4

VSYS2

VSYS4

VREF

AFE_GNDLDO_EM
MC_OUT

２

VIN1

VIN3

VSYS1

VSYS3

TH_VREF

AFE_VDD

N.C.

N.C.

GND

GND

GND

XO_P

３

DP

CHG_
GND1

CHG_
GND2

VBAT_VS

TH

N.C.

N.C.

GND

GPO7

GPO6

GPO5

GPO4

４

LDO_
USB33

CHG_
ISET

DM

CHG_
STATE

VBAT_CS

VSYS_CS

N.C.

N.C.

GPO3

GPO2

GPO1

VDD1

５

PVDD2

PVDD2_SDLINE_
SW

GND

N.C.

N.C.

N.C.

N.C.

GPO0

N.C.

GND

LDO_
ANA_IN６

LX_CORE

N.C.

SNS_
CORE

N.C.

N.C.

N.C.

GND2

N.C.

xRST_
OUT

SNS_ANA

VPP

LDO_AN
A_OUT

７

PGND2

PGND2_S

GND3

DDC_ONGND

DA_DATA

N.C.

N.C.

SDA_P

xINT_
SYNC

PGND3_S

PGND3

８

PVDD1

PVDD1_S

PWR_EN

xINT_
WKUPL

MCLK
OUT

SW_18_
OUT2

SW_18_
OUT3

N.C.

SCL_P

CLK_OUT

N.C.

LX_ANA

SW_18_
OUT1

SW_18_
IN1

SW_18_
IN2

SW_18_
OUT4

GND4

VBUS_
OUT

PVDD3_S

PVDD3
GND5

９

LX_IO

N.C.

VDD2

xINT_
WKUPS

１０

PGND1

PGND1_S

SNS_IO

SDA_A

GPO_A

CLKOUT_DMIC

MIC_REF

AGND_
MIC

MICDREF

INT_OUT

VIO_IN

１１

XRESETFSCLK

AD_DATA

SCL_A

GND

MICA

MICB

AVDD_
MIC

MICD

MIC
BIASB

VMBFILT

SPVM

１２

XI_A

AGND_
OSC

N.C.

DVDD

DGND

MICAREFMICBREF

MICC

MICCREF

MIC
BIASA

VBAT1

AVDD_
DRV

１３

XO_A

VBAT2

AGND_
DRVA

SPAP

AVDD_
DRVA

SPAN

AGND_
DRVAB

SPBN

AVDD_DR
VB

SPBP

AGND_
DRVB

AGND_
DRV

Audio

Power

BOTTOM VIEW13

CXD5247GF

Pin Table
No.

Ball #

Ball NamePower Supply

Type

Description

1

A1

VIN2 (=VIN1)

CHG_GND

Power Supply

Power Supply for USB

2

A2

VIN1

CHG_GND

Power Supply

Power Supply for USB

3

A3

DP

VIN,CHG_GND

AnalogUSB bus, D + input

4

A4

LDO_USB33

VIN,CHG_GND

Analog

5

A5

PVDD2

PGND2

Power Supply

Power Supply for DDC_core

6

A6

LX_CORE－

AnalogSwitching output for DDC_core

7

A7

PGND2

－

Power Supply

Ground for DDC_core

8

A8

PVDD1

PGND1

Power Supply

Power Supply for DDC_IO

9

A9

LX_IO

－

AnalogSwitching output for DDC_IO

10

A10

PGND1

－

Power Supply

Ground for DDC_IO

11

A11

XRESET

DVDD,DGND

Digital INPUT

System Reset

12

A12

XI_A

VBAT2,AGND_OSC

AnalogCrystal Oscillator Input

13

A13

XO_A

VBAT2,AGND_OSC

AnalogCrystal Oscillator Output

14

B1

VIN4 (=VIN1)

CHG_GND

Power Supply

Power Supply for USB

15

B2

VIN3 (=VIN1)

CHG_GND

Power Supply

Power Supply for USB

16

B3

CHG_GND1－

Power Supply

Ground for Chager

17

B4

CHG_ISET

VIN,CHG_GND

Analog

Charge current setting input

18

B5

PVDD2_SPGND2Power Supply

Power Supply for DDC_core

USB Power Supply LDO

3.3V output(=PVDD2)
19

B6

N.C.

－

－

－

20

B7

PGND2_S－

Power Supply

Ground for DDC_core

21

B8

PGND1

Power Supply

Power Supply for DDC_IO

22

B9

N.C.

－

－

－

23

B10

PGND1_S－

Power Supply

Ground for DDC_IO(=PGND2)
PVDD1_S(=PVDD1)(=PGND1)
24

B11

FSCLK

DVDD,DGND

Digital INPUT

Serial Data Frame Clock

25

B12

AGND_OSC－

Power Supply

Ground for Oscillator

26

B13

VBAT2

AGND_OSC

Power Supply

Power Supply from Battery

27

C1

VSYS2

CHG_GND

Power Supply

Power Supply for SYTEM(=VSYS1)
28

C2

VSYS1

CHG_GND

Power Supply

Power Supply for SYTEM

29

C3

CHG_GND2－Power Supply

Ground for Chager(=CHG_GND1)
30

C4

DM

VIN,CHG_GND

AnalogUSB bus, D - input

31

C5

DLINE_SW

VIN,CHG_GND

Digital OUTPUT

USB bus connection signal

32

C6

SNS_COREVDD,GND

AnalogFeedback input for DDC_CORE

14

CXD5247GF

No.

Ball #

Ball NamePower Supply

Type

Description

33

C7

GND3 (=GND)－

Power Supply

Ground for PM

34

C8

PWR_ENVDD,GND

Digital INPUT

Enable input

35

C9

VDD2 (=VDD)

GND

Power Supply

Power Supply for PM

36

C10

SNS_IOVDD,GND

AnalogFeedback input for DDC_IO

37

C11

AD_DATA

DVDD,DGND

Digital OUTPUTADC Serial Data Output

38

C12

N.C.

－

－

Test output (ATB_OSC)

39

C13

AGND_DRVA－

Power Supply

Ground for Ach Speaker Driver

40

D1

VSYS4

CHG_GND

Power Supply

Power Supply for SYTEM

CHG_GND

Power Supply

Power Supply for SYTEM(=VSYS1)
41

D2

VSYS3
(=VSYS1)42

D3

VBAT_VS

CHG_GND

AnalogBattery voltage sense input

43

D4

CHG_STATE

VIN,CHG_GND

Digital OUTPUT

Charge status output

44

D5

GND

－

－

Test input (TESTC1)

45

D6

N.C.

－

－

－

46

D7

DDC_ONVDD,GND

Digital OUTPUT

DDC_CORE start-up output

47

D8xINT_WKUPLVDD,GND

Digital INPUTLong time interrupt input

48

D9xINT_WKUPSVDD,GND

Digital INPUT

Short time interrupt input

49

D10

SDA_A

DVDD,DGND

Digital OUTPUTI2C Serial Control Data

50

D11

SCL_A

DVDD,DGND

Digital INPUTI2C Serial Control Port Clock

51

D12

DVDD

DVDD,DGND

Power Supply

Power Supply for 1.8V Digital Domain

52

D13

SPAP

AVDD_DRVA,AGND_DRVA

AnalogPositive Speaker Output of Ach

53

E1

VREF

AFE_VDD,AFE_GND

AnalogVREF output

54

E2

TH_VREF

AFE_VDD,AFE_GND

Analog

Thermistor monitor input

55

E3

TH

AFE_VDD,AFE_GND

Analog

Thermistor input

56

E4

VBAT_CS

CHG_GND

AnalogBattery current sense input

57

E5

N.C.

－

－

Test output (TESTC2)

58

E6

N.C.

－

－

－

59

E7

GND

－

－

Test input (TESTP1)60

E8

MCLKOUT

DVDD,DGND

Digital OUTPUT

Master Clock Output

61

E9

SW_18_OUT1

SW_18_IN,GND

AnalogLoad switch output (for USB)

62

E10

GPO_A

DVDD,DGND

Digital OUTPUT

General Purpose Output

63

E11

GND

－

－

Test input (TESTMODE)

64

E12

DGND (=GND)－

Power Supply

Ground for 1.8V Digital Domain

65

E13

AVDD_DRVAAGND_DRVA

Power Supply

Power Supply for Ach Speaker Driver

66

F1

AFE_GND－

Power Supply

Ground for AFE

67

F2

AFE_VDD

AFE_GND

Power Supply

Power Supply for AFE

68

F3

N.C.

－

－

Test output (TESTA5)15

CXD5247GF

No.

Ball #

Ball NamePower Supply

Type

Description69

F4

VSYS_CS

VSYS,CHG_GND

AnalogVSYS current sense input

70

F5

N.C.

－

－

－

71

F6

N.C.

－

－

－

72

F7

DA_DATA

DVDD,DGND

Digital INPUTDAC Serial Data Input

73

F8

SW_18_OUT2

SW_18_IN,GND

AnalogLoad switch output

74

F9

SW_18_IN1

VDD,GND

AnalogLoad switch input

75

F10

CLKOUT_DMIC

DVDD,DGND

Digital OUTPUT

Clock Output for Digital Microphone

76

F11

MICA

AVDD_MIC,AGND_MIC

AnalogMicrophone Input

77

F12

MICAREF

AVDD_MIC,AGND_MIC

AnalogReference terminal for Microphone Input

78

F13

SPAN

AVDD_DRVA,AGND_DRVA

AnalogNegative Speaker Output of Ach79

G1

LDO_EMMC_OUT

LDO_EMMC_IN,GND

AnalogPower supply LDO output for EMMC

80

G2

N.C.

－

－

Test output (TESTA2)

81

G3

N.C.

－

－

Test output (TESTA4)

82

G4

N.C.

－

－

－

83

G5

N.C.

－

－

－

84

G6

GND2 (=GND)－

Power Supply

Ground for PM

85

G7

N.C.

－

－

－

86

G8

SW_18_OUT3

SW_18_IN,GND

AnalogLoad switch output

87

G9

SW_18_IN2

VDD,GND

AnalogLoad switch input(=SW_18_IN1)
88

G10

MIC_REF

AVDD_MIC,AGND_MIC

AnalogCommon Reference for MIC ADC

89

G11

MICB

AVDD_MIC,AGND_MIC

AnalogMicrophone Input

90

G12

MICBREF

AVDD_MIC,AGND_MIC

AnalogReference terminal for Microphone Input

91

G13

AGND_DRVAB－Power Supply

Ground for Ach/Bch Speaker Driver92

H1

LDO_EMMC_IN

GND

AnalogPower supply LDO input for EMMC

93

H2

N.C.

－

－

Test output (TESTA3)

94

H3

GND

－

－

Test input (TESTA1)

95

H4

N.C.

－

－

－

96

H5

N.C.

－

－

－

97

H6

N.C.

－

－

－

98

H7

N.C.

－

－

－

99

H8

N.C.

－

－

－

100

H9

SW_18_OUT4

SW_18_IN,GND

AnalogLoad switch output

101

H10

AGND_MIC－

Power Supply

Ground for MIC Input and MIC bias

102

H11

AVDD_MICAGND_MIC

Power Supply

Power Supply for Microphone Input

103

H12

MICC

AVDD_MIC,AGND_MIC

AnalogMicrophone Input

104

H13

SPBN

AVDD_DRVB,AGND_DRVＢ

AnalogNegative Speaker Output of Bch

16

CXD5247GF

No.

Ball #

Ball NamePower Supply

Type

105

J1

LDO_PERI_OUT

LDO_EMMC_IN,GND

AnalogDescription
Power supply LDO output for peripheral
equipment

106

J2

GND

－

－

Test input (TEST1_P)

107

J3

GPO7

VDD,GND

Digital OUTPUT

General-purpose output

108

J4

GPO3

VDD,GND

Digital OUTPUT

General-purpose output

109

J5

GPO0

VDD,GND

Digital OUTPUT

General-purpose output

110

J6

xRST_OUT

VIO_IN,GND

Digital OUTPUT

Reset output

111

J7

SDA_P

VIO_IN,GND

Digital INPUT

Serial data input

112

J8

SCL_P

VIO_IN,GND

Digital INPUT

Serial clock input

113

J9

GND4 (=GND)－

Power Supply

Ground for PM

114

J10

MICDREF

AVDD_MIC,AGND_MIC

AnalogReference terminal for Microphone Input

115

J11

MICD

AVDD_MIC,AGND_MIC

AnalogMicrophone Input

116

J12

MICCREF

AVDD_MIC,AGND_MIC

AnalogReference terminal for Microphone Input

117

J13

AVDD_DRVBAGND_DRVBPower Supply

Power Supply for Bch Speaker Driver

118

K1

LDO_USB10

LDO_EMMC_IN,GND

AnalogPower supply LDO output for USB

119

K2

GND

－

－

Test input (TEST2_P)

120

K3

GPO6

VDD,GND

Digital OUTPUT

General-purpose output

121

K4

GPO2

VDD,GND

Digital OUTPUT

General-purpose output

122

K5

N.C.

－

－

－

123

K6

SNS_ANA

VDD,GND

AnalogFeedback input for DDC_ANA

124

K7

xINT_SYNC

VIO_IN,GND

Digital INPUTInterrupt input for time synchronization

125

K8

CLK_OUT

VIO_IN,GND

Digital OUTPUT

Clock output

126

K9

VBUS_OUT

VIO_IN,GND

Digital OUTPUT

USB connection detection output

127

K10

INT_OUT

VIO_IN,GND

Digital OUTPUT

Interrupt output

128

K11

MICBIASB

VBAT1,AGND_MIC

AnalogMicrophone Bias

129

K12

MICBIASAVBAT1,AGND_MIC

AnalogMicrophone Bias

130

K13

SPBP

AVDD_DRVB,AGND_DRVB

AnalogPositive Speaker Output of Bch

131

L1

GND1 (=GND)－

Power Supply

Ground for PM

132

L2

GND

－

－

Test input (TEST3_P)

133

L3

GPO5

VDD,GND

Digital OUTPUT

General-purpose output

134

L4

GPO1

VDD,GND

Digital OUTPUT

General-purpose output

135

L5

GND

－

－

Test input (TESTP2)

136

L6

VPP

GND

AnalogPower supply for OTP write

137

L7

PGND3_S－

Power Supply

Ground for DDC_ANA

138

L8

N.C.

－

－

－

139

L9

PVDD3_SPGND1Power Supply

Power Supply for DDC_ANA(=PGND3)(=PVDD3)

17

CXD5247GF

No.

Ball #

Ball NamePower Supply

Type

Description

140

L10

VIO_IN

GND

Power Supply

Power Supply for IO

141

L11

VMBFILTVBAT1,AGND_MIC

AnalogBias voltage of Microphone Bias

142

L12

VBAT1

VBAT1,AGND_MIC

Power Supply

Power Supply from Battery

143

L13

AGND_DRVB－Power Supply

Ground for Bch Speaker Driver

144

M1

XI_P

VDD,GND

AnalogCrystal input

145

M2

XO_P

VDD,GND

AnalogCrystal output

146

M3

GPO4

VDD,GND

Digital OUTPUT

General-purpose output

147

M4

VDD1 (=VDD)

GND

Power Supply

Power Supply for PM

148

M5

LDO_ANA_IN

GND

AnalogPower supply LDO input for Analog Core

149

M6

LDO_ANA_OUT

LDO_ANA_IN,GND

AnalogPower supply LDO output for Analog Core

150

M7

PGND3

－

Power Supply

Ground for DDC_ANA

151

M8

LX_ANA－

AnalogSwitching output for DDC_ANA

152

M9

PVDD3

PGND1

Power Supply

Power Supply for DDC_ANA

153

M10

GND5 (=GND)－

Power Supply

Ground for Digital

154

M11

SPVM

AVDD_DRV,AGND_DRV

AnalogReference for Speaker Driver

155

M12

AVDD_DRVAGND_DRVPower Supply

Power Supply for Driver Analog circuits

156

M13

AGND_DRV－Power Supply

Ground for Driver Analog circuits

18

CXD5247GF

Pin Description
Pin No.

SymbolI/OStandard pin voltage

Equivalent circuit
PVDD*

A9,B9

LX_IO

A6,B6

LX_CORE

M8,L8

LX_ANAPVDD1～PGND1

PVDD*
LX_*

O

PVDD2～PGND2
PGND*

PVDD3～PGND3
PGND*
VDD

C10

SNS_IOC6

SNS_CORE

K6

SNS_ANA

1.8V
I

SNS_*

1.0V
0.9V
GND
LDO_ANA_IN

M5

LDO_ANA_IN

I

VDD～GND

M6

LDO_ANA_OUT

O

3.3V

LDO_ANA_OUT

GND

H1

LDO_EMMC_INI

VDD～GND

G1

LDO_EMMC_OUT

O

3.3V

J1

LDO_PERI_OUT

O

3.3V

K1

LDO_USB10

O

1.0V

VIO_INK10

INT_OUTK8

CLK_OUTGND

O
J6xRST_OUTK9

VBUS_OUT

GND/VIO_IN
VDD

GND

19

CXD5247GF

Pin No.

Symbol

J5

GPO0

L4

GPO1

K4

GPO2

J4

GPO3

I/O

Standard pin voltage

Equivalent circuit
VDD

GND

O
M3

GPO4

L3

GPO5

K3

GPO6

J3

GPO7

GND/VDD

VDD

Internal
test
circuit

GND

CautionBe sure to pull up or pull down the GPO pin.
VDD

GND

D7

DDC_ONO

GND/VDD
VDD

GND

F9

SW_18_IN1

I

1.8V～GND

G9

SW_18_IN2

I

1.8V～GND

E9

SW_18_OUT1

O

SW_18_IN1,2

F8

SW_18_OUT2O

SW_18_IN1,2

G8

SW_18_OUT3O

SW_18_IN1,2

H9

SW_18_OUT4O

SW_18_IN1,2

VDD

SW_18_IN1,2

SW_18_OUT＊

GND

VDD

GND

C8

PWR_ENIVDD～GND
VDD

GND

VIO_IN

J7

SDA_P

I/O

VIO_IN～GND

J8

SCL_P

I

VIO_IN～GND

K7

xINT_SYNCI

VIO_IN～GND

GND

VDD

GND

20

CXD5247GF

Pin No.

SymbolI/OStandard pin voltage

M1

XI_P

I

VDD～GND

M2

XO_P

O

VDD～GND

Equivalent circuit

VDD

D9

xINT_WKUPSI

VDD～GND

D8xINT_WKUPLI

VDD～GND

GND

D4

CHG_STATEO

VIN～CHG_GND

CHG_VDD1（internal node）

DP

A3

DP

O

0.6V

CHG_GND
CHG_VDD1（internal node）

DM

C4

DM

I

0～0.6VCHG_GND21

CXD5247GF

Pin No.

SymbolI/OStandard pin voltage

Equivalent circuit
CHG_VDD1（internal node）

CHG_ISET

B4

CHG_ISETO

0～1.3VCHG_GND
CHG_VDDP（internal node）

VSYS

C1

C2
C3
C4

VSYS

O

0～4.2VCHG_GND
TH_VDD（internal node）
CVREF（internal node）
100kΩ

E2

TH_REF

I

0.6V

TH_REF

E3

TH

I

0.6V

TH

CHG_GND

F4

VSYS_CSI

0～4.2V

E4

VBAT_CSI

0～4.2V

D3

VBAT_VSI

0～4.2V

E1

VREF

O

2.0V

22

CXD5247GF

Pin No.

SymbolI/OStandard pin voltage

Equivalent circuit
CHG_VDD2（internal node）

LDO_USB33

A4

LDO_USB33

O

3.3V

CHG_GND
CHG_VDD2（internal node）

CHG_GNDC5DLINE_SWO

DLINE_SW

0V/ 3.3V
CHG_VDD2

CHG_GNDF10

CLKOUT_DMC,

O

C11

AD_DATA,O

F7

DA_DATA,IB11FSCLK,I

E8

MCLKOUT,O

A11

XRESET,

I

E10

GPO_A

O

D10

SDA_A

I/O

D11

SCL_A

I

F11

MICA

G11

MICB

H12

MICC

J11

MICD

0V/1.8V

0V/1.8V

I

0.9V±0.225V

23

CXD5247GF

Pin No.

SymbolI/OStandard pin voltage

Equivalent circuit

AVDD_DRVx
D13

SPAP

F13

SPAN

K13

SPBP

H13

SPBN

O

SPAP
SPAN
APBP
APBN

0V/3.3V

AGND_DRVx

K12

MICBIASA

K11

MICBIASBL11

VMBFILT

O

2V

VBAT2

A12

XI_A

I

A13

XO_A

O

0V/1.8V

XO_A

XI_A

AGND_OSCF12MICAREFG12MICBREFJ12MICCREFJ10MICDREFG10

MIC_REF

OI

0.9V

AVDD_DRV

M11

SPVM

O

SPVM

1.65V

AGND_DRV24

CXD5247GF

Absolute Maximum Ratings
Item

SymbolRatingUnit

Maximum input voltage (Power)

VIN_MAX

16.0

V

VIN*, CHG_STATE

Power supply (Power)

VVDD_MAX

7.0

V

VSYS*,VDD*,PVDD*,AFE_VDD,VIO_IN

VBAT_MAX

5.5

V

VBAT*,AVDD_DRV*VDVDD_MAX

2.0

V

DVDD,AVDD_MIC

I/O pin voltage 1 (Power)

VIO1-0.3～VDD+0.3

V

I/O pin voltage 2 (Power)

VIO2-0.3～VIO_IN+0.3

V

xRST_OUT, CLK_OUT, INT_OUT, SDA_P, SCL_P,
VBUS_OUT

I/O pin voltage 3 (Audio)

VIO3-0.3～DBAT*+0.3

V

SPAP,SPAN,SPBP,SPBN,MICBIASA,MICBIASB,
VMBFILT,XI_A,XO_A,SPVM

I/O pin voltage 4 (Audio)

VIO4-0.3～DVDD+0.3

V

SDA_A,SCL_A,XRESET,MCLKOUT,AD_DATA,FSCLK,DA_DATA,,CLKOUT_DMIC,GPO_A,
MIC_REF,,MICA,MICB,MICC,MICD,MICAREF,MICBREF,MICCREF,MICDREF,

Maximum junction temperature

Tj_max+ 125°C

Storage temperature

Tstg-65 ~ +150

°CPower supply (Audio)

25

Remarks

Except for maximum input voltage, Power Supply,I/O pin voltage 2~4, and output pins

CXD5247GF

Recommended Operating Conditions
Item
Ambient operating temperature

SymbolRatingUnit

Ta-25 ~ +85℃

Remarks

Supply voltage range 1

VIN

4.5 ~ 5.5

V

VIN*

Supply voltage range 2

VSYS

2.5 ~ 4.4

V

VSYS*,VDD*, PVDD*, AFE_VDD

Supply voltage range 3

VIO_IN

1.62 ～ 1.98

V

VIO_IN

Supply voltage range 4

DVDD1.62 ～ 1.98

V

DVDD,AVDD_MIC

Supply voltage range 5

AVDD_DRV

3.0 ～ 3.6

V

AVDD_DRV*

Supply voltage range 6

VBAT

2.5 ～ 5.5

V

VBAT*

Lo1

2.2

μH

Lo2

10

μH

Co_DDC1

22*2 parallel connection

μF

Co_DDC2

22

μF

Co_LDO1

1μF

LDO_USB33, LDO_USB10, LDO_PERI_OUT

Co_LDO2

10μF

LDO_EMMC_OUT

Co_LDO3

22μF

LDO_ANA_OUT

VREF output capacitance

Co_VREF

0.22

μF

VREF

VBAT capacitance

Co_VBAT

1

μF

VBAT

VSYS output capacitance

Co_VSYS

1

μF

VSYS

VSYS line total capacitance

C_VSYSALL

10~100μF

Total including the VDD and PVDD line input
capacitance (effective capacitance)kHz

The capacity in the CHIP is 9.5pF (Typ). The CL levelof the crystal assumes a thing of 5.0-6.0pF.

DC-DC converter output inductor

DC-DC converter output capacitanceLDO output capacitance

DDC_IO, DDC_CORE
VLS2010ET-2R2M(TDK)
DDC_ANA
VLS2010ET-100M(TDK)
DDC_IO, DDC_CORE
AMK107BBJ226MA-T (Taiyo Yuden Co., Ltd.)DDC_ANA
AMK107BBJ226MA-T(Taiyo Yuden Co., Ltd.)NX3215SA(NDK), TFX-04(RIVER ELETEC)
Crystal oscillation frequency

fXT

32.76832768 Hz crystal is allowed 55kohm max ESR.
Current sense resistor
Lithium ion battery capacity
Rapid charge current
Thermistor resistance B constant

Rimon

100

mohm

Li-ion_cap

~500

mAh

Ichg_set

100~500

mA

4250

K

26

Set as Ichgmax*Rimon≒50mV

Riset=100~20kohm
NCP15WF104F03RC(Murata Manufacturing Co., Ltd.)CXD5247GF

Electrical Characteristics◆Power supply Block(Unless otherwise specified: Ta = 27 °C, VDD = PVDD1 = PVDD2 =PWR_EN = 3.6 V, VIO_IN = SW_IN = 1.8 V )Power supply input (VDD, VIO_IN)
Item

Symbol

Measurement conditions

Min

Typ.

Power consumption in VDD
operating state

IVDD1

Power ON state, No Switching

Power consumption in VDD
stop state

IVDD2

PWR_EN = 0V

Power consumption in VDD
Deep Sleep state

IVDD3

VDD=3.6, Deep Sleep state , VIO_IN=OPEN

2

Power consumption in VIO_IN
operating state

IVIO1

I2C operation state3

Power consumption in VIO_IN
stop state

IVIO2

I2C stop state (SDA_P and SCL_P pulled up)

UVLO detection voltage

VUVLO_LUVLO cancel voltage

VUVLO_HUVLO hysteresis width⊿VUVLO⊿VUVLO = VUVLO_H - VUVLO_L

Max

60

Unit
μA

1

μA

5

μA
uA

0.1

uA
V

2.40

2.45

2.50

2.50

2.55

2.60

V

-

100

-

mV

Min

Typ.

Max

Unit

RTC (XI_P, XO_P)
Item

SymbolCrystal oscillation frequency

fXT

CLK_OUT output Duty

Xduty

Measurement conditions

32.768* Design guarantee item

10

kHz
90

%

LOAD SW (SW_18_IN, SW_18_OUT1-4)
Item

SymbolON resistor 1 (exclusively for
USB-PHY)

RON_SW

ON resistor 2

RON_SW

Measurement conditions

Min

Typ.

Max

Unit

ISW = 50mA; SW_18_IN = 1.75V, SW_18_OUT1

-

0.8

1

Ω

ISW = 50mA; SW_18_IN = 1.75V, SW_18_OUT2~4

-

0.8

1

Ω

Min
VDD
－ 0.3

Typ.

Max

Unit

-

-

V

VIPE_L

-

-

0.3

V

VIxINT_WKUP_H

VDD
－ 0.3

-

-

V

VIxINT_WKUP_L

-

-

0.3

V

VIxINT_SYNC_H

VIO_IN
－ 0.3

-

-

V

VIxINT_SYNC_L

-

-

0.3

V

VISCL_P_H

VIO_IN
－ 0.3

-

-

V

VISCL_P_L

-

-

0.3

V

VISDA_P_H

VIO_IN
－ 0.3

-

-

V

VISDA_P_L

-

-

0.3

V

IF-IN (PWR_EN, xINT_WKUP_S, xINT_WKUP_L, xINT_SYNC, SCL_P, SDA_P)
Item
PWR_EN pin
H level input voltage
PWR_EN pin
L level input voltage
xINT_WKUP pin
H level input voltage
xINT_WKUP pin
L level input voltage
xINT_SYNC pin
H level input voltage
xINT_SYNC pin
L level input voltage
SCL_P pin
H level input voltage
SCL_P pin
L level input voltage
SDA_P pin
H level input voltage
SDA_P pin
L level input voltage

Symbol

Measurement conditions

VIPE_H27

CXD5247GF

IF-OUT (CLK_OUT, INT_OUT, xRST_OUT, VBUS_OUT, GPO0-7, DDC_ON)
Item
CLK_OUT pin
H level output voltage
CLK_OUT pin
L level output voltage
INT_OUT pin
H level output voltage
INT_OUT pin
L level output voltage
xRST_OUT pin
H level output voltage
xRST_OUT pin
L level output voltage
VBUS_OUT pin
H level output voltage
VBUS_OUT pin
L level output voltage
GPO0~7 pin
H level output voltage
GPO0~7 pin
L level output voltage
DDC_ON pin
H level output voltage
DDC_ON pin
L level output voltage

Symbol

Measurement conditions

Min

Typ.

Max

Unit

VOCLK_OUT_H IOUT =-2mA

VIO_IN –
0.2V

-

-

V

VOCLK_OUT_L IIN =+2mA

-

-

0.2

V

VOINT_OUT_H IOUT =-2mA

VIO_IN –
0.2V

-

-

V

VOINT_OUT_L IIN =+2mA

-

-

0.2

V

VOxRST_OUT_H IOUT =-2mA

VIO_IN –
0.2V

-

-

V

VOxRST_OUT_L IIN =+2mA

-

-

0.2

V

VOVBUS_OUT_H IOUT =-2mA

VIO_IN –
0.2V

-

-

V

VOVBUS_OUT_L IIN =+2mA

-

-

0.2

V

VOGPO1_H

IOUT =-2mA

VDD –
0.2V

-

-

V

VOGPO1_L

IIN =+2mA

-

-

0.2

V

VDDC_ON_H

IOUT =-2mA

VDD –
0.2V

-

-

V

VDDC_ON_L

IIN =+2mA

-

-

0.2

V

Min

Typ.

Max

Unit

DDC_IO
Item

Symbol*1

Maximum output current*1

Measurement conditions

IDIO_MAX

Inductor peak current

IDIO_LP

Output voltage*1

VDIO

Output feedback voltage

VDIO_FB

Maximum operating
frequency*1

FDIO_FMAX

Output start-up time*1

TDIO

200

VDD=2.5~4.4V, Io=1~200mA

mA
1000

mA

1.65

1.80

1.95

V

1.77

1.80

1.83

V

1

MHz

0.4

ms

Io = 0 mA, maximum frequency at start-up
0.2

Output ON resistor (H side)

RONH_DIO

0.3

ohm

Output ON resistor (L side)

RONL_DIO

0.15

ohm

*1 Design guarantee item when using the recommended parts

28

CXD5247GF

DDC_ANA
Item

SymbolMaximum output current*1*1

Inductor peak current*1

Measurement conditions

IDANA_MA

Min

Typ.

Max

6

Unit
mA

IDANA_LP

150mA

Output voltage

VDANA

VDD=2.5~4.4V, Io=0~6mA, VO_D_ANA[5:0] = 0Ch

0.65

0.70

0.75

V

Output feedback voltage

VDANA_FB

VO_D_ANA[5:0] = 0Ch

0.690

0.700

0.710

V

Maximum operating
frequency*1

FDANA_FMAX Io=0mA, maximum frequency at start-up

2

MHz

Output start-up time*1

1ms

Output ON resistor (H side)

RONH_DANA

TDANA

0.5

2

ohm

Output ON resistor (L side)

RONL_DANA

1

ohm

Max

Unit

*1 Design guarantee item when using the recommended parts

DDC_CORE
Item

SymbolMaximum output current*1*1

Measurement conditions

IDCORE_MA

Typ.

100

Inductor peak current

IDCORE_LP

Output voltage 1*1

VDCORE1

Output voltage 2*1

VDCORE2

Output feedback voltage

VDCORE_FB

Maximum operating
frequency*1

FDCORE_FMAX Io = 0 mA, maximum frequency at start-up

Output start-up time*1

Min

VDD=2.5~4.4V, Io=0~100mA,
VO_D_CORE[5:0] = 0Ch
VDD=2.5~4.4V, Io=0~100mA,
VO_D_ CORE [5:0] = 24h
VO_D_ CORE [5:0] = 0Ch

mA
500

mA

0.65

0.70

0.75

V

0.90

1.00

1.10

V

0.69

0.70

0.71

V

2

MHz

1

ms

TDCORE

0.4

Output ON resistor (H side)

RONH_DCORE

0.8

ohm

Output ON resistor (L side)

RONL_DCORE

0.6

ohm

Max

Unit

*1 Design guarantee item when using the recommended parts

LDO_EMMC
Item
PSRR

LDO_IN

Symbol

Measurement conditionsMin

PSRRLEMMC 1kHz~100KHzPeak（Io=0A, 100mA）

Maximum output current

ILEMMCmax

Output voltage

VLEMMC

Register setting: VO_L_EMMC[1:0] = 00h (Default)

Input stability

VLEMMCivs

Output stability
Voltage difference between
input and output

Typ.
30

dB

100

mA
3.45

V

VDD= VLEMMC +0.2~4.4V

10mV

VLEMMCAls

Io=0~100mA

2

mV

VLEMMCIO

LDO_EMMC_IN = 3.0 V, Io = 100 mA, Vo = 3.3 V
settings

29

3.15

2.8

3.3

V

CXD5247GF

LDO_PERI
Item
PSRR

LDO_IN

Symbol

Measurement conditionsMin

PSRRLPERI 1kHz~100KHzPeak（Io=0A, 10mA）

Maximum output current

ILPERImax

Output voltage

VLPERI

Register setting: VO_L_PERI[1:0] = 00h (Default)

Input stability

VLPERIvs

Output stability
Voltage difference between input
and output

Typ.

Max

30

dB

10
3.15

Unit

mA
3.3

3.45

V

VDD=2.5~4.4V

10mV

VLPELIls

Io=0~10mA

2

mV

VLPELIIOLDO_EMMC_IN=3.0V, Io=10mA, Vo=3.3V settings

2.8

V

LDO_ANA
Item

SymbolInput voltage range

VLANA_IN

PSRR

LDO_INPSRRLANA1 10kHz～2MHzPeak（Io=0A, 100uA, 1mA, 6mA）

55

dB

PSRR

VDD

PSRRLANA2 10kHz～2MHzPeak（Io=0A, 100uA, 1mA, 6mA）

50

dB

Maximum output current

Measurement conditions

Min

Typ.

VLANA
+0.2

ILANAmax

Max

Unit

VDD

V

6
0.65

mA

Output voltage

VLANA

Register setting: VO_L_ANA[5:0] = 0Ch (Default)

0.75

V

Input stability

VLANAivs

VDD=2.5~4.4V

0.700

3

mV

Output stability

VLANAls

Io=0~6mA

2

mV

Max

Unit

1.0V output for USBPHY (LDO_USB10)
Item
PSRR

LDO_IN

Symbol

Measurement conditionsMin

PSRRLVIN2 1kHz~100KHzPeak（Io=0A, 10mA）

Maximum output current

IUSB10max

Output voltage

VUSB10

Input stability

VLUSB10ivs

Output stability

VLUSB10ls* Max. 50 mA due to overcurrent limiter

Typ.
30

10

dB
50

mA

1.05

V

VIN=2.5~5.5V

10mV

Io=0~10mA

2

mV

0.95

30

1.00

CXD5247GF

List of DC-DC converter and LDO output register settings
Setting voltage of each power supply and code
Address

DDC_ANA

DDC_CORELDO_ANA

Unit[V]LDO_EMMCLDO_PERI

Unit[V]
Address

DDC_ANA

DDC_CORE
1.0125

00h

0.55

3.3

3.3

25h

1.012501h

0.5625

3.2

3.2

26h

1.025

1.025

02h

0.575

3.1

3.1

27h

1.03751.037503h

0.5875

3.0

3.0

28h

1.05

1.05

0.6

2.9

2.9

29h

1.06251.06250.6125

0.6

2.8

2.8

2Ah

1.075

1.075

0.625

0.625

2.7

2.7

2Bh

1.08751.08750.63750.6375

0.625

2.6

2.6

2Ch

1.1

1.1

0.65

0.65

0.65

2.5

2.5

2Dh

1.1125

1.1125

04h

0.6

0.6

05h

0.6125

06h

0.625

07h
08h
09h

0.66250.6625

0.65

2.4

2.4

2Eh

1.125

0Ah

0.675

0.675

0.675

2.3

2.3

2Fh

1.13750Bh

0.68750.6875

0.675

2.2

2.2

30h

1.15

0Ch

0.7

0.7

0.7

2.1

2.1

31h

1.16250Dh

0.71250.7125

0.7

2.0

2.0

32h

1.175

0Eh

0.725

0.725

0.725

1.9

1.9

33h

1.18750Fh

0.73750.7375

0.725

1.8

1.8

34h

1.2

10h

0.75

0.75

0.75

35h

1.212511h

0.76250.7625

0.75

36h

1.225

12h

0.775

0.775

0.775

37h

1.237513h

0.78750.7875

0.775

38h

1.25

14h

0.8

0.8

0.8

39h

1.262515h0.81250.8125

0.8

3Ah

1.275

16h

0.825

0.825

0.825

* Blue cell values cannot be set (input).

17h

0.83750.8375

0.825* Yellow cell values are the default settings

18h

0.85

0.85

0.85

19h

0.86250.8625

0.85

1Ah

0.875

0.875

0.875

1Bh

0.88750.8875

0.875

1Ch

0.9

0.9

0.9

1Dh

0.91250.9125

0.9

1Eh

0.925

0.925

0.925

1Fh

0.93750.9375

0.925

20h

0.95

0.95

0.95

21h

0.96250.9625

0.95

22h

0.975

0.975

0.975

23h

0.98750.9875

0.975

24h

1.0

1.0

1.0

31

CXD5247GF◆Analog front-end block for battery power level detection(Unless otherwise specified: Ta = 27 °C, VBAT = VSYS = VDD_AFE = 3.6 V)

Power supply input (AFE_VDD)
Item

SymbolSupply voltage range

Measurement conditions

VDD

Operating power consumption

IAVD_ACT

Current consumption when
stopped

IAVD_SLP

Min

Typ.

2.5
At the time of measurement

100

Max

Unit

4.4

V

200

μA

0.2

μA

Max

Unit

4.5

V

Battery voltage, battery temperature measurement (VBAT_VS, TH)
Item

SymbolBattery voltage measurement
range

Measurement conditions
VBAT_VS voltage measurement

Min
2.5

Battery voltage measurement
resolution

1.1

Battery voltage measurement
accuracy
Measurement cycle*2

Register：82h/83h ※Default 125ms

Battery temperature
measurement range

TH voltage measurement

mV/LSB-4.4(-4)+4.4(4)

125ms

18.2h

0

2.0

Battery temperature
measurement resolution

0.5

Battery temperature
measurement accuracy*2

Measurement cycle
*2

Typ.

Register：82h/83h ※Default 125ms

mV(LSB)V
mV/LSB

-1

+1

125ms

18.2h

℃

Measurement is performed at a 7.8 ms cycle during charge.

Battery charge / discharge current measurement (VBT_CS, VSYS_CS)
Item

Symbol

Measurement conditions

Min

Current measurement range

Between VSYS_CS and VBAT_CS

Current measurement resolution

Between VSYS_CS and VBAT_CS

Current measurement accuracy

Between VSYS_CS and VBAT_CS =10mV-5

Current measurement offset

When VSYS_CS=VBAT_CS (0mA setting) output-5

Measurement cycle *2

Register：82h/83h ※Default 125ms

*2

Typ.

-50

Max

Unit

50

mV

30
0

125ms

uV/LSB
+5

%

+5

LSB

18.2h

Measurement is performed at a 7.8 ms cycle during charge.

Battery temperature detection and control (VREF, TH_REF)
Item

SymbolReference voltage
Reference
resistor

voltage

Measurement conditions

Min

Vref
SW_ON

RON_THREF

Typ.

Max

2
ITHSW = 20uA-

* Shared with the charge control block

32

(10)

Unit
V

100

Ω

CXD5247GF◆Charge control block(Unless otherwise specified: Ta = 27 °C, VIN = 5V, VBAT=3.6V )Power path control, shared (VIN, VBT, VSYS)
Item

Symbol

Measurement conditions

Min

Typ.

Max

Unit

VIN detection L side

Vvinl

When the VIN voltage rises* 200 mV hysteresis

3.6

3.8

4.0

V

VIN detection H side

Vvinh

When the VIN voltage rises* 100 mV hysteresis

5.6

5.8

6.0

V

VSYS detection relative to VIN

Vinbat

VSYS

VSYS

-0.2

-0.1

VSYS

V

Battery discharge current 1

Idc1

VIN=5V, VBAT=4.2V, when power supply block
stopped, charge complete

2uA

Battery discharge current 2

Idc2

VIN=0V , VBAT=4.2V , when power supply block
stopped

1

uA

Circuit current

Icc

VIN=5V , when power supply block stopped ※VIN
current

1

mA

Chip temperature control

Tcc* Design guarantee item

100℃

Thermal shutdown

Tsd* Design guarantee item

150℃

* The battery discharge current is measured at the VSYS pin.

Battery voltage detection and control (VBAT)
Item

SymbolPrecharge start voltage

Vpcstart

Weak battery judgment voltage

Vweakbat

Rapid charge start voltage

Vqcstart

Charge control voltage

Vchg

Recharge start voltage

Vrcstart

Charge complete voltage

Vfv

Measurement conditions

Min

Typ.

Max

Unit

When the VBAT voltage rises

1.3

1.4

1.5

V

When the VBAT voltage rises

3.3

3.4

3.5

V

Resistor variable range 20mV-step

2.6

-

3.6

V

When the VBAT voltage rises

2.9

3.0

3.1

V

Resistor variable range 200mV-step

2.6

-

3.2

V

Ichg=10mA ※Ta=0~60℃

4.17

4.20

4.23

V

Resistor variable range 50mV-step

4.0

-

4.4

V

During VBAT voltage step down

Vchg-0.45

Vchg-0.4

Vchg-0.35

V

Resistor variable range 100mV-step

Vchg-0.4-

Vchg-0.25

V

Function enable/disable is selected by the register.

Vrcstart+0.1* Default: enable

V

Charge current detection and control (CHG_ISET)
Item

Symbol

Measurement conditions

Min

Typ.

Max

Unit

250

300

350

mA

Rapid charge current

Ichg

Riset=33kohm , VBAT=3.6V

Precharge current

Ipchg

Riset=33kohm , VBAT=2.2V,

Initial charge current

Ippchg

VBAT=1.0V

5

10

20

mA

Charge complete current

Ifc

When setting to 30mA

25

30

35

mA

Resistor variable range10mA-step

10

-

50

mA

* The charge current can be varied by an external resistor. :Ichg=10000/Riset

33※Ichg*0.2

60

mA

CXD5247GF

Battery temperature detection and control (VREF, TH)※The thermistor resistor for temperature measurement assumes the NCP15WF104F03RC
Item

Symbol

Measurement conditions

Min

Typ.

Max

Unit

Reference voltage fortemperature detection

TrefBattery connection detection

Tthc

Temperature detection 1-1*3

Tth1-1

Temperature detection 1-2*4

Tth1-1

Temperature detection 2*3

Tth2

Hysteresis of 2.5°C on the temperature rise side relative
to 10°C

10℃

Temperature detection 3*3

Tth3

Hysteresis of 2.5°C on the temperature rise side relative
to 45°C

45℃

Temperature detection 4-1*3

Tth4-1

Hysteresis of 2.5°C on the temperature rise side relative
to 60°C

60℃

Temperature detection 4-2*4

Tth4-2*3*4

Ro=200kohm

Hysteresis of 2.5°C on the temperature rise side relative
to 0°C

2

V

Tref*0.9

V

0

℃

0.0

15.0

45.0

℃

60.0

℃

Max

Unit

Judged by the digital comparator output (set by 78h to 7Fh)
Temperature detection 1-2 and 4-2 are when VBAT < Vqcstart (before rapid charge, before HOST start-up).

3.3V output for USBPHY (LDO_USB33)
Item
PSRR

SymbolLDO_IN

Measurement conditionsMin

PSRRLVIN1 1kHz~100KHzPeak（Io=0A, 10mA）

Maximum output current

IUSB33max* Max. 50 mA due to overcurrent limiter

Typ.
-20

10
3.2

dB
50

3.3

mA

Output voltage

VUSB33

3.4

V

Input stability

VLUSB33ivs

VIN=4.5~5.5V

10mV

Output stability

VLUSB33ls

Io=0~10mA

2

mV

USB detection (DP, DM, DLINE_SW)
Item

SymbolDP pin output voltage
DP pincurrent

maximumVdpsourceMeasurement conditions
Idpo=0~150uA

Idm

Voltage detection
DLINE_SW pin
H level output voltage
DLINE_SW pin
L level output voltage

Typ.

Max

Unit

0.5

0.6

0.7

V

150

Idp

DM pin sink current

Min

uA

Vdpo=0.6V

50

150

uA

Vdpm

0.25

0.4

V

VODL_HIOUT =-2mA

VUSB33 –
0.2V

-

-

V

VODL_LIIN =+2mA

-

-

0.2

V

Min

Typ.

Max

Unit

Timers and setup times
Item

Symbol

Measurement conditions

Initial charge timer

Tppc

7

10

13

sec

Weak Battery timer

Twb

24

34

44

min

Precharge timer

Tpc

Changeable to 120 min by the register

54

60

66

min

Rapid charge timer

Tqc

Changeable to 300 min by the register

540

600

660

min

3

4

Clk

3

4

Clk

Battery voltage setup time
Battery temperature setup time
Charge current setup time

Tbvd
Tbcd

Setup by the 31 ms-clk matching 4 times
Setup by the 31 ms-clk matching 4 times
Setup by the 250ms-clk matching 4 times* Changeable to x10 by the register34

CXD5247GF◆Audio block

MICs to serial output characteristics(Unless otherwise specified: Ta = 25 °C, AVDD_MIC = 1.8 V, DVDD = 1.8 V, VBAT = 3.7 V, GND_MIC =DGND = 0 V, OSCIN =512•48 kHz, Input test signal is a 1 kHz sine wave, Measurement bandwidth is 20 Hz to 20 kHz )Parameters

SymbolMin

Typ

Input impedance

RMICINDC voltage at MICx

VCM-

Full-scale input voltage

FSMIC

-

Signal to noise ratio

SNRMIC

-

50
AVDD_
MIC/2
AVDD_
MIC/2
90

THD+N

THDMIC-

Dynamic range

DRMIC

-

Crosstalk

CTMIC

-

Max

Condition

Units
kΩ

-

V

-

Vpp

-

A-weight, MICGAINx=0dB

dB

-80

-

-6dBFS, MICGAINx=0dB

dB

90

-

A-weight, MICGAINx=0dB

dB

100

-

1kHz

dB

MICGAIN range

MICGAINx

0

-

15

dB

MICGAIN step

MICSTEPx

2.9

3

3.1

dB

PGAGAIN range

PGAGAINx

0

-

6

dB

PGAGAIN step

PGASTEPx

0.4

0.5

0.6

dB

serial input to SPOUTs characteristics (Loop OFF)
(Unless otherwise specified: Ta = 25 °C, AVDD_MIC = 1.8 V, DVDD = 1.8 V, VBAT = 3.7 V, AGND_MIC = DGND = 0 V, OSCIN= 512•48 kHz, Input test signal is a 1 kHz sine wave, Measurement bandwidth is 20 Hz to 20 kHz, test load RL = 8Ω, CL = 150 pF forbridge tied an ear speaker load. )Parameters
Power output per channel

Symbol
PO

Min
-

Typ
400

Max
-

Condition
0dB FS input/Codec gain=24dB

Units
mW

Total harmonic distortion + noise

THDSP

-

-60

-54

Input Amplitude=-6dBFS

dB

Output Noise

Vnoise-10-

A-weight

35

uVrms

CXD5247GF

serial input to SPOUTs characteristics (Loop ON)(Unless otherwise specified: Ta = 25 °C, AVDD_MIC = 1.8 V, DVDD = 1.8 V, VBAT = 3.7 V, AGND_MIC = DGND = 0 V, OSCIN= 512•48 kHz, Input test signal is a 1 kHz sine wave, Measurement bandwidth is 20 Hz to 20 kHz, test load RL = 8Ω, CL = 150 pF forbridge tied an ear speaker load. )Parameters
Power output per channel

Symbol
PO

Min
-

Typ
400

Max
-

Condition
0dB FS input/Codec gain=24dB

Units
mW

Total harmonic distortion + noise

THDSP

-

-66

-60

Input Amplitude=-6dBFS

dB

Output Noise

Vnoise-10-

A-weight

uVrms

DC characteristics(Unless otherwise specified: Ta = 25 °C, AVDD_MIC = 1.8 V, DVDD = 1.8 V, VBAT = 3.7 V, AGND_MIC = DGND = 0 V, OSCIN =512•48 kHz)Parameters

Symbol

Min

Typ

Max

Condition

Units

-

0

-

1.8

2.0

2.2

-

Hi-Z

-

Stand by mode

-

-

2.0

low noise mode

mA
μVrms

MICx_BIASVOMICBS

Low Output modeV

Output current

IOMICBS

Output noise

NOMICBS--5

low noise mode

Output impedance

ROMICBS

40

60

80

low noise mode

-

60

-

16k

20k

24k

80k

100k

120k

1.62

1.8

1.98

Output impedance

ROMICBSlow power modeΩLDO for MICINLDOOUT voltage

VREG18V

Crystal switching specification(Unless otherwise specified: Ta = 25 °C, AVDD_MIC =.8 V, DVDD = 1.8 V, VBAT = 3.7 V, AGND_MIC = DGND = 0 V )Parameters
XI_A frequency

Symbol
FREQ

Min

Typ

Max

-

24.576--49.152-

36

Condition

Units
MHz

CXD5247GF

Switching specifications and characteristics (serial audio interface form CXD5602)
Parameters

Symbol

Min

Typ

Max

Condition

Units

Serial data input1 - FSCLK/DA_DATAMCLK clock frequency--

24.576-MHz

MCLK clock duty cycle

-

40

50

60

%

MCLK clock periodtAC

Rise time

tR

5.0

ns

Fall time

tF

5.0

ns

Setup time

tDS

5.0

ns

Hold time

tDH

0.0

ns

40.69

ns

MCLK
FSCLK
DA_DATAMCLK/FSCLK/DA_DATA timing

Switching specifications and characteristics (serial audio interface to CXD5602)
Parameters

Symbol

Min

Typ

Max

Condition

Units

Serial data output - MCLK/AD_DATAMCLK clock frequency--

24.576-MHz

MCLK clock duty cycle

-

40

50

60

%

MCLK clock periodtAC

Rise time

tR

5.0

ns

Fall time

tF

5.0

ns

Data Delay

tDO

15.0

ns

40.69

3.0

ns

MCLK

AD_DATAMCLK/AD_DATA timing37

CXD5247GF

digital microphone interface
Parameters

Symbol

Min

Typ

Max

-

3.072

-

MHz

40

50

60

%

Digital MIC input1 - DMCLK = 3.072 MHz
CLKOUT_DMIC
clock
frequency
CLKOUT_DMIC clock duty
cycle
CLKOUT_DMIC
clock
tAC
periodRise timetR
Fall time

325.52tF

Condition

Units

ns
5.0

ns

5.0

ns

Setup time

tDSr/tDSf

5.0

ns

Hold time

tDHf/tDHr

0.0

ns

Digital MIC input1 - DMCLK = 1.024 MHz (DDR input)
CLKOUT_DMIC
clock
frequency
CLKOUT_DMIC clock duty
40
cycle
CLKOUT_DMIC
clock
tAC
periodRise timetR
Fall time

1.024

-

MHz

50

60

%

976.56

tF

ns
5.0

ns

5.0

ns

Setup time

tDSr/tDSf

5.0

ns

Hold time

tDHf/tDHr

0.0

ns

ｔAC
ｔR

ｔF

CLKOUT_DMIC

MICA/MICB/MICC/MICD
ｔDHｒ

ｔDSｆ

ｔDHｆ

ｔDSｒ

DMCLK/DMIC timing

38

CXD5247GF

I2C bus switching specification
Parameters

Symbol

Min

Typ

Max

fSCL

0

-

400

kHz

tBUF

1.3

-

-

μs

tHD:STA

0.6

-

-

μs

tLOW

1.3

-

-

μs

tHIGH

0.6

-

-

μs

Start setup waiting time

tSU:STA

0.6

-

-

μs

Data hold time

tHD:DATA

0

-

-

μs

Data setup time

tSU:STA

100

-

-

ns

Rise time

tR

-

-

300

ns

Fall time

tF

-

-

300

ns

tSU:STO

0.6

-

-

μs

Clock frequency
Data charge minimum
waiting time
Data transfer start
waiting time
Low level clock pulse widthHigh level clock pulse width

Stop setup waiting time

Condition

Units

I2C timing

digital input / output signal threshold level
Parameters

SymbolHigh-level output voltage

VOH

Low-level output voltage

VOL

High-level input voltage

VIH

Low-level input voltage

VIL

Min
DVDD 0.2
0.7 x
DVDD

Typ

Max

-

-

V

-

0.2

V

-

-

V

-

-

0.3 x
DVDD

V

39

ConditionUnits

CXD5247GF

Power consumption (audio block)
The table below lists the current consumed by each Adonis internal power supply pin. This enables to calculate the overall power inaccordance with the use case.
Block

Operating state

Pin

When reset
Logic

Analog Mic input

Min

Typ

Max

0.1

-

DVDD

5

SPOUT output

MICIN

CrystalbufferMICBIASuA
When Xtal 24.576MHzmA

FSCLK/AD_DATA pin load 10 pF

101ch operation

3.6

Typ: approximately 2.5 mA

mA

6.6

Typ: approximately 5 mA

mA

4ch operation

12.6

Typ: approximately 10 mA

mA

Digital MIC

１When using Digital MIC

ｍA

2ch operation

AVDD_MIC

uA

Sleep

0.05

2

XRESET=Low

uA

24.576MHz

1

1.5

SPOUT not used, oscillation stablemA

49.152MHz

1.2

1.8

SPOUT not used, oscillation stable

mA

1.1

1.65

SPOUT BTL mono, oscillation stablemA

24.576MHz Stereo

1.2

1.8

SPOUT BTL stereo, oscillation stablemA

49.152MHz mono

1.4

2.1

SPOUT BTL mono, oscillation stablemA

49.152MHz Stereo

1.6

2.4

SPOUT BTL stereo, oscillation stable

mA

Sleep

0.05

1

0.23

0.32

0.16

0.24

1.2

1.7

24.576MHz mono

VBAT2

MICBIAS 1ch
VBAT1Active
Sleep

SPOUT

Unit

Sleep

MICBIAS 2ch
MICINLDO

ConditonuA
MICBIAS only operating

mA
MICIN block current not included

0.1

Stereo 16fs

1.6

Stereo 32fs

3.2

AVDD_DRV*

Stereo 16fs Loop

8.6

Stereo 32fs Loop

7.8

40

mA

mA
uA

BTLstereo24.576MHz

mA

Max = about 3.6mA
BTL stereo 49.152MHz

mA

Max= abount 5.34mA
BTLstereo24.576MHz, Loop ON

mA

Max= about 10.18mA
BTL stereo 49.152MHz, Loop ON
Max= about 11.94mAmA

CXD5247GF

Description of Functions◆Power supply block
RTC

Low power consumption IQ = 3 μA(typ.)

Clock, start-up timer

Voltage step down type PFM control DC-DC converter
Low power consumption IQ = 10μA (per channel)


DDC_IO/ Vout = 1.8 V/ Iomax = 200mA(min)

DDC_ANA/ Vout = 0.600 V～1.275 V, 25 mV-step / Iomax = 6 mA(min)

DDC_CORE / Vout = 0.5500 V～1.1125 V, 12.5mV-step / Iomax = 100 mA(min)

LDO






Low power consumption IQ = 6 μA (1ch per channel)
LDO_ANA / Vout = 0.600 V～1.000 V, 25 mV-step / Iomax = 6 mA(min)LDO_EMMC / Vout = 1.8V～3.3V,100mV-step / Iomax = 100 mA(min)LDO_PERI / Vout = 1.8V～3.3V,100mV-step / Iomax = 10 mA(min)LDO_USB10 for USB-PHY / Vout = 1.0V/ Iomax = 10 mA(min)External interface
Load switch (4ch for 1.8 V)Communication (I2C serial interface, 32.768 kHz clock, reset, interrupt start-up control)GPO (8 systems, general-purpose switch drive, enable drive)USB detection (USB connection signal, Data line switch control signal)◆Analog front-end block for battery power level detectionOn-chip 12-bit ADC (1ch: time sharing control) for battery power level detection and battery voltage, current and temperature
measurement in the CXD5602 System◆Charge control block






Standalone type charge function
Protective function
Conformity to USB battery charging 1.2 (conformance as a system)
USB detection (USB connection signal, Data line switch control signal)
LDO_USB33 for USB-PHY / Vout =3.3V / Iomax = 10 mA(min)41

CXD5247GF◆Audio block
CXD5247 Audio is an analog audio I/O IC developed for the CXD5602 System. CXD5602 performs signal transfer using an originalformat. The two crystal types of 24.576 MHz and 49.152 MHz are supported as the clock source. The input systems include a ΔΣ
ADC that supports four analog MIC inputs and an 8-channel digital MIC interface. The analog MIC input and digital MIC input pins
are shared and used exclusively. The output system is a BTL configuration S-Master Speaker Driver (L/R) output. In addition, twosystems of MIC bias circuits and a 1.8 V output LDO for MIC input are mounted.
Definition of fs
This specification defines fs as follows: fs = 48 kHz

Power Up constraintCXD5247 Audio power-on (including reset signal assert) is subject to the restrictions noted in the table below.
(When external AVDD_MIC is supplied)
VBAT1/VBAT2

DVDD

AVDD_MIC

AVDD_DRV*XRESET

Restrictions

OFF

OFF

OFF

OFF

0

Allowed

OFF

OFF

OFF

OFF

1

Not Allowed

OFF

OFF

OFF

ON

0

Not Allowed

OFF

OFF

OFF

ON

1

Not Allowed

OFF

OFF

ON

OFF

0

Not Allowed

OFF

OFF

ON

OFF

1

Not Allowed

OFF

OFF

ON

ON

0

Not Allowed

OFF

OFF

ON

ON

1

Not Allowed

OFF

ON

OFF

OFF

0

Not Allowed

OFF

ON

OFF

OFF

1

Not Allowed

OFF

ON

OFF

ON

0

Not Allowed

OFF

ON

OFF

ON

1

Not Allowed

OFF

ON

ON

OFF

0

Not Allowed

OFF

ON

ON

OFF

1

Not Allowed

OFF

ON

ON

ON

0

Not Allowed

OFF

ON

ON

ON

1

Not Allowed

ON

OFF

OFF

OFF

0

Allowed

ON

OFF

OFF

OFF

1

Not Allowed

ON

OFF

OFF

ON

0

Allowed

ON

OFF

OFF

ON

1

Not Allowed

ON

OFF

ON

OFF

0

Allowed

ON

OFF

ON

OFF

1

Not Allowed

ON

OFF

ON

ON

0

Allowed

ON

OFF

ON

ON

1

Not Allowed

ON

ON

OFF

OFF

0

Allowed

ON

ON

OFF

OFF

1

Allowed

ON

ON

OFF

ON

0

Allowed42

CXD5247GF

ON

ON

OFF

ON

1

Allowed

ON

ON

ON

OFF

0

Allowed

ON

ON

ON

OFF

1

Allowed

ON

ON

ON

ON

0

Allowed

ON

ON

ON

ON

1

AllowedPower Up/Reset assert sequence constraint
The CXD5247 Audio power-on sequence and reset cancel restrictions are shown below. Figure ? shows the timing sequence. (Whenexternal AVDD_MIC is applied)• XRESET is canceled after VBAT1, VBAT2 and DVDD have risen.
• AVDD_DRV* should rise after VBAT1 and VBAT2 have risen.
• AVDD_DRV* also supports use cases when power supply is not turned on.

Power Up sequence
Supported crystals / clocks
This IC supports the following crystal frequencies.

Symbol
XI_A
XO_A

Frequency
24.576MHz
49.152MHz

Supported crystal frequencies
Description
Master clock, 512fs
Master clock, 1024 fs, Hi-Res operation

An external clock (0 V - 1.8 V square wave) can also be applied to the OSCIN pin.

SymbolXI_A

Frequency
24.576MHz
49.152MHz

Frequency when applying an external clock
Description
Master clock, 512fs
Master clock, 1024fs Hi-Res operation

43

CXD5247GF

Description of Operation◆Powersupply block operation sequence

Timing chart (Start UP to Stop)
VDD

System operating voltage
2.55V

2.45V

2.05V

①

②

③

⑤

⑥

⑦

2.0V

Power for CXD5602

XRST_RTCOTP ReadInternal
SignalADC

ActivePGD④
EN_SYS

RCOSC

XOSC

CLK

⑧
(2s)

⑨

CLK_OUTxRST_OUT
State
Reset

No.
1
2
3
4
5

Ready

StartUPPowerON

Description
Detect 2.05 V and cancel the internal circuit reset state.
* Read and reflect the OTP data for the analog circuits after reset cancel.
Detect 2.55 V and start ADC operation. (Only the battery voltage is measured in the Ready state.)
Detect the system operating voltage (3Ch: Def BDh) or more and start up the power supply block.
This detection is performed by comparing the register setting value and the ADC data (digital comparator).
Perform state transition by detecting the rise of the CXD5602 power supplies(4 systems: DDC_IO/ANA/CORE and LDO_ANA).
Detect the system operating voltage or less and stop power supply output (power supply block operation).
* 4-bit (72 mV) hysteresis control is performed on the voltage step down side relative to the 3Ch setting value.

6

Detect 2.45 V (100 mV hysteresis control relative to the rise 2.55 V) and stop ADC operation.

7

Detect 2.0 V (50 mV hysteresis control relative to the rise 2.05 V) and stop operation.

8
9

Ready

Operation uses the internal RC oscillation circuit (15 kHz) until the crystal oscillation circuit (XOSC) starts up.
The transition from the RC oscillation circuit to the crystal oscillation circuit is performed automatically inside
Approximately 2 s (typ.) is required after reset cancel until the crystal oscillation circuit starts up and the clock
is output to CXD5602 (output from the CLK_OUT pin).

44

Reset

S tateReset →Ready
Ready
Ready →StartUP
StartUP→PowerON
PowerON→Ready
Ready
Ready →ResetーーCXD5247GF

Deep Sleep（ｘINT_WKUP) 〜 Power ON

xINT_WKUP
Power for CXD5602
DDC_IO

1.8V

1.5V

standby

PGD

CLK_OUT

Deep Sleep〜Power ON 〜2.84ms
xRST_OUT〜0.61msState〜1.5msStart UP0.73msStartUP

DeepSleep

PowerON

Deep Sleep 〜 USB ON〜 USB OFF

VIN

USB ONUSB OFF
DDIO(1.8V)

DDC_IOLDO_USB10
SW_OUT_1

LDO_USB10(1.0V)
SW_OUT_1(1.8V)

LDO_USB33

LDO_USB33(3.3V)

USB_IN

CLK_OUTxRST_OUT

VBUS_OUTDLINE_SW

State
DeepSleep

StartUPPowerON45

CXD5247GF◆Power supply block state transition diagram
Shutdown※1 SET_VSYS_ACT (register 3Ch)
※2 Select of the on/off condition by the register.
Blue : Pin
Green : register

DDC/LDO=OFF
I2C=OFF
CLK_OUT=OFF
xRST_OUT=Lo
AFE=OFFPWR_EN=”Hi”

PWR_EN=”Lo”

Timing chart of CHG_BAT1 (Case the voltage of VSYS rises slowly)
Reset
VSYS

DDC/LDO=OFF
I2C=OFF
CLK_OUT=OFF
xRST_OUT=Lo
AFE=OFFSET_VSYS_ACT(register:3Ch)

VDD>2.0V“BD-4”h*0.018V=3.324V

2.55V

UVLO cancel

VDD<2.0V“4”bit“BD”h(Def)*0.018V=3.396V

2.45V

125ms(Def)Ready
DDC/LDO=OFF
I2C=OFF
CLK_OUT=OFF
xRST_OUT=Lo
AFE=OFF→ON

CHG_VBAT1＊moving average = 1

AFE operating

CHG_VBAT1＊moving average = 2

CHG_VBAT=1(※1)
and UVLO detection (VDD>2.55V)

Startup

SET_AFE_1 (register:82h)

CHG_VBAT=0(※1)
or UVLO detection (VDD<2.45V)

CHG_VBAT=0(※1)
or UVLO detection(VDD<2.45V)

DDC/LDO=ON
I2C=OFF
CLK_OUT=ON
xRST_OUT=Lo
AFE=ON

PGD=1（DDC/LDO Voltage detection）

xINT_WKUPS=”Lo”(※2)
or xINT_WKUPL=”Lo”(※2)
or VIN=”Hi”(VBUS connect)
or CMD_WKUP=1(※2)
or ALARM=1(※2)
or SET_DWN_PRE=1(※2)
and CHG_VBAT1=1(※1)

SET_AFE_3 (register:84h)

Timing chart of CHG_BAT1 (Case the voltage of VSYS rises quickly)
VSYS
SET_VSYS_ACT(register:3Ch)UVLO detection (VDD<2.45V)
or CHG_VBAT1=0(※1)
or WDT=1(※2)
or CMD_SYS_RST=1(※2)“BD”h(Def)*0.018V=3.396V

UVLO cancel

2.55V“4”bit“BD-4”h*0.018V=3.324V
2.45V

125ms(Def)Power ON

DeepSleep

DDC/LDO=ON
I2C=ON
CLK_OUT=ON
xRST_OUT=Hi
AFE=ON

DDC/LDO=OFF
I2C=OFF
CLK_OUT=OFF
xRST_OUT=Lo
AFE=ONCMD_SLP=1(※2) orxINT_WKUPL=”Lo”(※2)

SET_AFE_1 (register:82h)
CHG_VBAT1＊moving average = 1
CHG_VBAT1＊moving average = 2

46

AFE operating

Stop by UVLO

The initial value of the moving
average register is "1".

CXD5247GF◆AFE block operation timing chart for battery power level detection
Timing chart of AFE operation
Measurement period

digitalSET_AFE_1 (register:82h)Tsanalog

AFE start〜Measurement〜Stop 〜4.51ms

digital processing
1

2

3

4

5

6

1

2

3

4

5

6

1

2

3

4

5

6

1

2

3

4

5

6

clock(8.192kHz)
1

2

3

4

5

1

2

3

4

5

1

2

3

4

5

1

2

3

4

5

VREF

measurement

Voltage“zero” Current
3clk

Data for the state transition ofPower Supply

Current
3clk

Voltage
Cal＆Ave update

Temperature
3clk

3clk

”zero” Current
Cal&Ave update

Current
Cal&Ave update

Data of the AFE measurement
value storage register

Temperature
Cal&Ave update

Vol.,Cur.＆
Temp. update

Timing chart (During the measurement cycle change)
SET_AFE_1 (register:82h)
Ts=125ms
Ts=1sec

Ts=1sec

Ts=500ms

ADC Operating: ”Hi”

Ts=125ms

Ts=500ms

Battery information measurement value read
The measurement data is reflected to the AFE measurement value storage register (registers 85h to 8Ah and 8Dh to 8Eh) by setting“1” in LRQ_AFE (register 8Bh). LRQ_AFED_STATE (register 8Ch) goes to “1” after the data is reflected.
The moving average values set by SET_AFE3 (register 84h[1:0]) are reflected to the storage registers.
- Battery voltage (DATA_AFEV1,2 register 85h,86h)Battery voltage = Register value ×1.12mV Ex.：C85h×1.12mV=3.6V- Battery charge/discharge current (DATA_AFEI1,2 register 87h,88h)Battery charge/discharge current ＝ (Register value - 800h) ÷ Current detection resistor ×0.02929 Ex.：（6ABh-800h）÷0.1Ω×0.02929=‐100mA* “－” is the discharge direction and “＋” is the charge direction.
- Battery temperature (DATA_AFET1,2 register 89h,8Ah)
Battery temperature (thermistor voltage) = Register value ×0.4883mV Ex.: 712h×0.4883mV=0.884V* The temperature is determined according to the thermistor resistor (B constant) and the measurement value. When the B
constant is B4250K, 0.884 V corresponds to a battery temperature of 30°C.

47

CXD5247GF◆Charge control block state transition diagram48

CXD5247GF◆Charge control block operation timing
Charge timing chart
Vqcstart > Vweakbat
Battery voltage
Vchg
Vrcstart

Vqcstart
Vweakbat
Vpcstart(4.2V)(4.0V)(3.0V)(2.5V)(2.0V)

Charge current(1C-300mA)

Ichg(0.2C-60mA)

Ipchg
Ifc
Iwbchg(0.1C-30mA)(10mA)State
STBY

InitialchargePre-charge

10 sec.

Rapid charge

60 min.

Chargecomplete

600 min.

Max 45 min.
Weak Battery timer

Vqcstart < Vweakbat
Battery voltage
Vchg
Vrcstart
Vweakbat
Vqcstart

Vpcstart(4.2V)(4.0V)(3.4V)(3.0V)(2.0V)

Charge current(1C-300mA)

Ichg(0.2C-60mA)

Ipchg
Ifc

Iwbchg(0.1C-30mA)(10mA)State
STBY

InitialchargePre-charge

10 sec.

Rapid charge
600 min.

Max 45 min.
Weak Battery timer

49

ChargecompleteCXD5247GF

JEITA Guidelines

Charge control voltage

Vchg (4.2V)
Low temperature Wait

Hightemperature
Wait

Vchg-0.15V (4.05V)
Register setting・High temperature Wait
・Vchg
・Vchg-0.15

Register setting
・Low temperature Wait
・Ichg
・Ichg*0.5

Charge current

Ichg(1.0C)
High
temperature
Wait

Low temperature Wait
Ichg*0.5(0.5C)

Batterytemperature

0℃

10℃

45℃

60℃

State
Low temperature
Wait

Lowtemperature
chargeHigh
Hightemperature temperature
Wait
chargeNormal charging

The control by the chip temperature in during Charge
Chip temperature
100℃

CHG_HOT

15ms 4times match

15ms 4times match
CHG_CCHF
1 minute

1 minute

Charge current
Ichg(1.0C)

Ichg*0.5(0.5C)
Ichg*0.2(0.2C)

State
Pre-charge

Rapid charge

50

15ms 4times matchCXD5247GF◆Power block – I2C specifications
Symbol

Item

Min.

Max.

Unit

fSCL_P

SCL_P clock frequency

0

400

kHz

0.6

-

us

Hold time (repeat) start conditiontHD:STA(The first clock pulse is generated after this period.)tLOW

SCL_P clock Low period

1.3

-

us

tHIGH

SCL_P clock High period

0.6

-

us

tSU:STA

Repeat start condition setup time

0.6

-

us

tHD:DAT

Data hold time

0

-

us

tSU:DAT

Data setup time

100

-

ns

tr

SDA_P signal and SCL_P signal rise time

-

300

ns

tf

SDA_P signal and SCL_P signal fall time

-

300

ns

tSU:STO

Stop condition setup time

0.6

-

us

tBUF

Bus free time between Stop and Start conditions

1.3

-

us

Cb

Capacitance load of each bus line

-

400

pF

t R , tF

tBUF

SDA
tSU:DATtHD:STAtHD:DATtSU:STAtSU:STO

SCL
tLOW

tHIGH

symboldescription
Start ConditionSR
Repeat Start Condition
P
Stop Condition
Slave Address
7'h2C
W
Write mode (Host→CXD5247)
R
Read mode(CXD5247→HOST)
A
ACK
N
NACK
Sub Address
Command Register
Data
Write/Read DataS

Write mode
S

Slave
W A
Address

Sub
Address

A

Sub
Address

A SR

Data

A P

Read mode
S

Slave
W A
AddressSlave
R A
Address

Data

51

N P

bit
7
1
1
1
1
8
8

CXD5247GF◆Power register list
No.

Category

Address

Register nameApplication

10h

EN_CTRL1

11h

EN_CTRL2

12h

LOAD_SW_CTRL1

13h

GPO_CTRL1

14h

GPO_CTRL2

15h

VO_DDC_ANA

Sets the DDC_ANA output voltage

16h

VO_DDC_CORE

Sets the DDC_CORE output voltage

17h

VO_LDO_EMMC/PERI

Sets the LDO_EMMC/PERI output voltage

18h

VO_LDO_ANA

Sets the LDO_ANA output voltage

20h

CONFIG_DDC_IO_1

21h

CONFIG_DDC_IO_2

22h

CONFIG_DDC_IO_3

23h

CONFIG_DDC_CORE_1

24h

CONFIG_DDC_CORE_2

25h

CONFIG_DDC_CORE_3

26h

CONFIG_DDC_ANA_1

27h

CONFIG_DDC_ANA_2

28h

CONFIG_DDC_ANA_3

29h

CONFIG_LDO

Sets the LDO operating mode

30h

WKUP_STATUSStores the start-up factor

31h

WKUP_STATUS_CLR

Clears the start-up factor_STATUS

32h

WKUP_TRGStores the start-up factor output trigger

33h

WKUP_TRG_CLR

Clears the start-up factor output trigger

34h

INTO_STATUSStores the INT_OUT output trigger

35h

INTO_STATUS_CLR

Clears the INT_OUT output trigger

36h

VMIN_DDC_CORE

Holds the setting voltage before WDT issues

37h

CMD_CTRLStores the I2C control command

38h

CONFIG_INT_WKUP

Sets the xINT_WKUP condition

39h

CONFIG_WDT

WDT setting

3Ah

SET_DWN_PRE1

System operation lower limit voltage pre-notification

3Bh

SET_DWN_PRE2

voltage setting status

3Ch

SET_VSYS_ACTSets the system operating voltage

3Dh

LRQ_SET_VSYS

Reflects the 3Ah to 3Ch settings

3Eh

LRQ_VSYS_STATE

VSYS setting status

D/D converter and LDO enable control

GPO0～7 Output control(Power supply block)1

LOAD_SW enable control

Output control registers(Power supply block)2

Sets the DDC_IO operating mode

Sets the DDC_CORE operating mode

Power supply operating
mode setting registers

Sets the DDC_ANA operating mode

(Power supply block)3
Status control registers

52

CXD5247GF

No.

Category

Address

Register nameApplication

3Fh

INT_SEL

Selects the INT_OUT output

40h

CURT_PRE_CNTR_1

41h

CURT_PRE_CNTR_2

42h

CURT_POST_CNTR_1

43h

CURT_POST_CNTR_2

44h

CURT_POST_CNTR_3

45h

CURT_POST_CNTR_4

46h

RRQ_TIME

47h

SET_PRE_CNTR_1

48h

SET_PRE_CNTR_2

49h

SET_POST_CNTR_1

4Ah

SET_POST_CNTR_2

4Bh

SET_POST_CNTR_3

4Ch

SET_POST_CNTR_4

4Dh

LRQ_TIME

Set time load request to the counter

4Eh

LRQ_OFST

Reflects the offset time

4Fh

WKUP_PRE_CNTR_1

50h

WKUP_PRE_CNTR_2

51h

WKUP_POST_CNTR_1

52h

WKUP_POST_CNTR_2

53h

WKUP_POST_CNTR_3

54h

WKUP_POST_CNTR_4

55h

LRQ_WU

Reflects the WakeUp time registers

56h

CONFIG_WKUP

Condition settings of WakeUp

57h

CNTR_STOP

Enable control of RTC counter

58h

ALM_PRE_CNTR_1

59h

ALM_PRE_CNTR_2

5Ah

ALM_POST_CNTR_1

Sets the interrupt output alarm time (absolute time,

5Bh

ALM_POST_CNTR_2

relative time)

5Ch

ALM_POST_CNTR_3

5Dh

ALM_POST_CNTR_4

5Eh

LRQ_ALM

Reflects the interrupt output alarm time setting registers

5Fh

CONFIG_ALARM

Sets the alarm condition

60h

RRQ_LRQ_STATUS

Time data status(Power supply block)61h

DATA_GPS1

Information storage62h

DATA_GPS2

registers63h

DATA_GPS3Stores the current time

(Power supply block)4
RTC control registers

Current time read request

Stores the set time to the counter(Power supply block)4
RTC control registers 1

Sets the WakeUp time (absolute time, relative time)(Power supply block)5
RTC control registers 2

6Stores the GPS data53

CXD5247GF

No.

Category

Address

Register name64h

DATA_GPS465h

DATA_GPS566h

DATA_GPS667h

DATA_GPS768h

DATA_GPS869h

DATA_GPS96Ah

DATA_GPS10

6Bh

DATA_GPS11

6Ch

DATA_GPS12

6Dh

DATA_GPS13

6Eh

DATA_GPS14

6Fh

DATA_GPS1570h

DATA_GPS1671h

DATA_FREE1

72h

DATA_FREE2

73h

DATA_FREE374h

DATA_FREE475h

CNT_CHG1

76h

CNT_CHG2

77h

CNT_CHG378h

SET_T60_1

79h

SET_T60_2

7Ah

SET_T45_1

7Bh

SET_T45_2

7Ch

SET_T10_1

7Dh

SET_T10_2

7Eh

SET_T0_1

7Fh

SET_T0_2

80h

CNT_USB1

81h

CNT_USB282h

SET_AFE1

83h

SET_AFE284h

SET_AFE385h

DATA_AFEV_1

86h

DATA_AFEV_2

87h

DATA_AFEI_1

88h

DATA_AFEI_2

Application

Stores the information required by the software side

Battery voltage judgment and control registers(Charge block)7
Control registers

Battery temperature control registers

USB charge control registers

AFE operation setting registers(AFE block)8
Control registers
Stores the AFE measurement data

54

CXD5247GF

No.

Category

Address

Register nameApplication

89h

DATA_AFET_1

8Ah

DATA_AFET_2

8Bh

LRQ_AFE

Reflects the AFE measurement data to the registers

8Ch

LRQ_AFED_STATE

AFE data status* Note that addresses 8Dh and higher are assigned as test registers, and should not be used.

55

CXD5247GF

Output control registers
EN_CTRL1
Addressbit

AccessName

Default

10h

7
6
5
4
3
2
1
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

EN_L_PERI1
EN_D_CORE1
EN_L_ANA1
EN_D_ANA1
EN_L_EMMC1
EN_D_IO1

0
0
1
1
1
1
1
1

Description
Reserved
Reserved
LDO_PERI enable control
DDC_CORE enable control
LDO_ANA enable control
DDC_ANA enable control
LDO_EMMC enable control
DDC_IO enable control

Clear State

0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable

Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep

EN_CTRL2
Addressbit

AccessName

Default

11h

0

R/W

EN_USBPHY

1

Description
Power control for USB-PHY

Clear State
0:disable, 1:enable

Ready&DeepSleep* Effective at the time of USB connection. (LDO_USB33, LDO_USB10, SW_18_OUT1)

LOAD_SW_CTRL1
Addressbit

AccessName

Default

12h

7
6
5
4
3
2
1
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

EN_SW18_4
EN_SW18_3
EN_SW18_2
-

0
0
0
1
1
1
1
1

Description
Reserved
Reserved
Reserved
SW_18_OUT4 enable control
SW_18_OUT3 enable control
SW_18_OUT2 enable control
Reserved
Reserved

Clear State

0:open, 1:short
0:open, 1:short
0:open, 1:short

Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep
Ready&DeepSleep

GPO_CTRL1
Addressbit

AccessName

Default

13h

7
6
5
4
3
2
1
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

GPO[3]_EN
GPO[2]_EN
GPO[1]_EN
GPO[0]_EN
GPO[3]
GPO[2]
GPO[1]
GPO[0]

0
0
0
0
0
0
0
0

Description
GPO3 output control
GPO2 output control
GPO1 output control
GPO0 output control
GPO3 logic
GPO2 logic
GPO1 logic
GPO0 logic

0:Hi-Z, 1:GPO[3] reflection
0:Hi-Z, 1:GPO[2] reflection
0:Hi-Z, 1:GPO[1] reflection
0:Hi-Z, 1:GPO[0] reflection
0:Low output, 1:High output
0:Low output, 1:High output
0:Low output, 1:High output
0:Low output, 1:High output

Clear State
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset

GPO_CTRL2
Addressbit

AccessName

Default

14h

7
6
5
4
3
2
1
0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

GPO[7]_EN
GPO[6]_EN
GPO[5]_EN
GPO[4]_EN
GPO[7]
GPO[6]
GPO[5]
GPO[4]

0
0
0
0
0
0
0
0

Description
GPO7 output control
GPO6 output control
GPO5 output control
GPO4 output control
GPO7 logic
GPO6 logic
GPO5 logic
GPO4 logic

56

0:Hi-Z, 1:GPO[7] reflection
0:Hi-Z, 1:GPO[6] reflection
0:Hi-Z, 1:GPO[5] reflection
0:Hi-Z, 1:GPO[4] reflection
0:Low output, 1:High output
0:Low output, 1:High output
0:Low output, 1:High output
0:Low output, 1:High output

Clear State
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset

CXD5247GF

VO_DDC_ANA
Addressbit

AccessName

Default

Description

Clear State

15h

5:0

R/W

VO_D_ANA[5:0]1Ch

Output voltage setting register at PowerON.
The setting voltage and the cord refer to table 1

Ready&DeepSleep

VO_DDC_CORE
Address

Bit

AccessName

Default

Description

Clear State

16h

5:0

R/W

VO_D_CORE[5:0]24hOutput voltage setting register at PowerON.
The setting voltage and the cord refer to table 1

Ready&DeepSleep

Description

Clear State

VO_LDO_EMMC/PERI
Address

Bit

AccessName

Default

7:4

R/W

VO_L_PERI[3:0]

00h

3:0

R/W

VO_L_EMMC[3:0]

00h

17h

Output voltage setting register at PowerON.
The setting voltage and the cord refer to table 1
Output voltage setting register at PowerON.
The setting voltage and the cord refer to table 1

Ready&DeepSleep
Ready&DeepSleep

VO_LDO_ANA
Address

Bit

AccessName

Default

Description

Clear State

18h

5:0

R/W

VO_L_ANA[5:0]0Ch

Output voltage setting register at PowerON.
The setting voltage and the cord refer to table 1

Ready&DeepSleep

Table.1
Setting voltage of each power supply and code
Address

DDC_ANA

DDC_CORELDO_ANA

Unit[V]LDO_EMMCLDO_PERI

Unit[V]
Address

DDC_ANA

DDC_CORE
1.0125

00h

0.55

3.3

3.3

25h

1.012501h

0.5625

3.2

3.2

26h

1.025

1.025

02h

0.575

3.1

3.1

27h

1.03751.037503h

0.5875
0.6

3.0

3.0

28h

1.05

1.05

2.9

2.9

29h

1.06251.0625

04h

0.6

0.6

05h

0.61250.6125

0.6

2.8

2.8

2Ah

1.075

1.075

06h

0.625

0.625

0.625

2.7

2.7

2Bh

1.08751.087507h

0.63750.6375

0.625

2.6

2.6

2Ch

1.1

1.1

08h

0.65

0.65

0.65

2.5

2.5

2Dh

1.1125

1.112509h

0.66250.6625

0.65

2.4

2.4

2Eh

1.125

0Ah

0.675

0.675

0.675

2.3

2.3

2Fh

1.13750Bh

0.68750.6875

0.675

2.2

2.2

30h

1.15

0Ch

0.7

0.7

0.7

2.1

2.1

31h

1.16250Dh

0.71250.7125

0.7

2.0

2.0

32h

1.175

0Eh

0.725

0.725

0.725

1.9

1.9

33h

1.18750Fh

0.73750.7375

0.725

1.8

1.8

34h

1.2

10h

0.75

0.75

0.75

35h

1.212511h

0.76250.7625

0.75

36h

1.225

12h

0.775

0.775

0.775

37h

1.237513h

0.78750.7875

0.775

38h

1.25

14h

0.8

0.8

0.8

39h

1.262515h0.81250.8125

0.8

3Ah

1.275

16h

0.825

0.825

0.825

* Blue cell values cannot be set (input).

17h

0.83750.8375

0.825* Yellow cell values are the default settings

18h

0.85

0.85

0.85

19h

0.86250.8625

0.85

1Ah

0.875

0.875

0.875

1Bh

0.88750.8875

0.875

1Ch

0.9

0.9

0.9

1Dh

0.91250.9125

0.9

1Eh

0.925

0.925

0.925

1Fh

0.93750.9375

0.925

20h

0.95

0.95

0.95

21h

0.96250.9625

0.95

22h

0.975

0.975

0.975

23h

0.98750.9875

0.975

24h

1.0

1.0

1.0

57

CXD5247GF

Power supply operating mode setting registers
CONFIG_DDC_IO_1
Addressbit

AccessName

Default

Description

Output setting register at disable
00b:10kohm, 01b:3.10kohm, 10b:Hi-z, 11b:3.6Mohm
Maximum output current setting at the time of start
20h
3:2
R/W
IOST_D_IO[1:0]10b00b:x0.5, 01b:x0.67, 10b:x1.0
Maximum output current setting
1:0
R/W
IOMAX_D_IO[1:0]10b00b:x0.5, 01b:x0.67, 10b: x1.0
*PM_D_IO : Setting register to remove an electric charge from output capacity at the time of a power supply output stop
5:4

R/W

PM_D_IO[1:0]00bClear State
Reset
Reset
Reset

*IOST_D_IO : When the rush electric current which is at the time of a CXD5247GF start is a problem, please establish it. But, please
pay attention to be connected with the starting time.
*IOMAX_D_IO : When there is fear of noise mainly, it's established. But, please pay attention to the maximum loading capacity's
falling. (200mA to 100mA@x0.5)
CONFIG_DDC_IO_2
Addressbit

AccessName

Default

Description

Clear State

Pre-driver OFF ability setting for output Low side-SW
Reset
0:x1.0, 1:x0.75
Pre-driver OFF ability setting for output High side-SW
6R/W
PDRVOFF_D_IO
0Reset
0:x1.0, 1:x0.75
Pre-driver ON ability setting for output Low side-SW
21h
5:4
R/W
NDRVON_D_IO[1:0]
10b
Reset
00b:x0.5, 01b:x0.75, 10b:x1.0, 11b:x1.25
Pre-driver ON ability setting for output High side-SW
3:2
R/W
PDRVON_D_IO[1:0]
10b
Reset
00b:x0.5, 01b:x0.75, 10b:x1.0, 11b:x1.25
Output dead time setting
1:0
R/W
DT_D_IO[1:0]
10b
Reset
00b:5ns, 01b:10ns 10b:15ns, 11b:25ns*21h[7:2] : When noise of a DDC is a problem, it's established (It's set as the minus side.) The effect can be expected by the order of theA [5:4] >= [3:2] >> [7] >= [6]. But, for the performance as the DDC to become the deterioration direction, a change judgment of pros
and cons is recommended with a set evaluation result.
7

R/W

NDRVOFF_D_IO

0*DT_D_IO : This register is used to slight adjustment of the electric power change efficiency. When it's short, it'll be the way of theefficient good, but when it passes the optimum point, please be careful about deteriorating.

CONFIG_DDC_IO_3
Address

Bit

AccessName

Default

Description

ZCD detection threshold value setting
00b:x0.88, 01b:x0.94, 10b:x1.0, 11b:x1.06*ZCD_D_IO : This register is used to slight adjustment of the electric power change efficiency.
22h

1:0

R/W

ZCD_D_IO[1:0]

10b

58

Clear StateResetCXD5247GF

CONFIG_DDC_CORE_1
Addressbit

AccessName

Default

Description

Output setting register at disable
00b:10kohm, 01b:10kohm, 10b:Hi-z, 11b:220ohm
Maximum output current setting at the time of start23h
3:2 R/W
IOST_D_CORE[1:0]10b00b:x0.5, 01b:x0.67, 10b:x1.0, 11b:Reserved
Maximum output current setting
1:0 R/W
IOMAX_D_CORE[1:0]10b00b:x0.5, 01b:x0.67, 10b:x1.0, 11b:Reserved*PM_D_CORE : Setting register to remove an electric charge from output capacity at the time of a power supply output stop
5:4

R/W

PM_D_CORE[1:0]00bClear State
Reset
Reset
Reset

*The time of Power ON can also move only 11b in 23h [5:4]. When changing the DDC_CORE voltage, when also making them reachthe setting voltage by a short time in untensioned, it's established. (1.0V→0.7V)*IOST_D_CORE : When the rush electric current which is at the time of a CXD5247GF start is a problem, please establish it. But,
please pay attention to be connected with the starting time.
*IOMAX_D_CORE : When there is fear of noise mainly, it's established. But, please pay attention to the maximum loading capacity's
falling.(100mA to 50mA@x0.5)
CONFIG_DDC_ CORE _2
Addressbit

AccessName

Default

Description

Clear State

Pre-driver OFF ability setting for output Low side-SW
Reset
0:x1.0, 1:x0.75
Pre-driver OFF ability setting for output High side-SW
6R/W
PDRVOFF_D_CORE0Reset
0:x1.0, 1:x0.75
Pre-driver ON ability setting for output Low side-SW
24h
5:4 R/W NDRVON_D_CORE[1:0] 10b
Reset
00b:x0.5, 01b:x0.75, 10b:x1.0, 11b:x1.25
Pre-driver ON ability setting for output High side-SW
3:2 R/W PDRVON_D_CORE[1:0]
10b
Reset
00b:x0.5, 01b:x0.75, 10b:x1.0, 11b:x1.25
Output dead time setting
1:0 R/W
DT_D_CORE[1:0]
10b
Reset
00b:5ns, 01b:10ns 10b:15ns, 11b:25ns*24h[7:2] : When noise of a DDC is a problem, it's established (It's set as the minus side.) The effect can be expected by the order of theA [5:4] >= [3:2] >> [7] >= [6]. But, for the performance as the DDC to become the deterioration direction, a change judgment of pros
and cons is recommended with a set evaluation result.
7

R/W

NDRVOFF_D_CORE

0*DT_D_IO : This register is used to slight adjustment of the electric power change efficiency. When it's short, it'll be the way of theefficient good, but when it passes the optimum point, please be careful about deteriorating.

CONFIG_DDC_ CORE _3
Addressbit

AccessName

Default

Description

ZCD detection threshold value setting
00b:x0.88, 01b:x0.94, 10b:x1.0, 11b:x1.06*ZCD_D_CORE : This register is used to slight adjustment of the electric power change efficiency.
25h

1:0

R/W

ZCD_D_CORE[1:0]

10b

59

Clear StateResetCXD5247GF

CONFIG_DDC_ANA_1
Addressbit

AccessName

Default

Description

Output setting register at disable
00b:10kohm, 01b:10kohm, 10b:Hi-z, 11b:3.6Mohm
Maximum output current setting at the time of start
26h
3:2 R/W
IOST_D_ANA[1:0]10b00b:x0.5, 01b:x0.67, 10b:x1.0, 11b:Reserved
Maximum output current setting
1:0 R/W
IOMAX_D_ANA[1:0]10b00b:x0.5, 01b:x0.67, 10b:x1.0, 11b:Reserved*PM_D_ANA : Setting register to remove an electric charge from output capacity at the time of a power supply output stop
5:4

R/W

PM_D_ANA[1:0]00bClear State
Reset
Reset
Reset

*IOST_D_ANA : When the rush electric current which is at the time of a CXD5247GF start is a problem, please establish it. But,
please pay attention to be connected with the starting time.
*IOMAX_D_ANA : When there is fear of noise mainly, it's established. But, please pay attention to the maximum loading capacity's
falling.(10mA to 5mA@x0.5)
CONFIG_DDC_ ANA _2
Addressbit

AccessName

Default

Description

Clear State

Pre-driver OFF ability setting for output Low side-SW
Reset
0:x1.0, 1:x0.75
Pre-driver OFF ability setting for output High side-SW
6R/W
PDRVOFF_D_ANA
0
Reset
0:x1.0, 1:x0.75
Pre-driver ON ability setting for output Low side-SW
27h
5:4 R/W
NDRVON_D_ANA[1:0]
10b
Reset
00b:x0.5, 01b:x0.75, 10b:x1.0, 11b:x1.25
Pre-driver ON ability setting for output High side-SW
3:2 R/WPDRVON_D_ANA[1:0]
10b
Reset
00b:x0.5, 01b:x0.75, 10b:x1.0, 11b:x1.25
Output dead time setting
1:0 R/W
DT_D_ANA[1:0]
10b
Reset
00b:5ns, 01b:10ns 10b:15ns, 11b:25ns*27h[7:2] : When noise of a DDC is a problem, it's established (It's set as the minus side.) The effect can be expected by the order of theA [5:4] >= [3:2] >> [7] >= [6]. But, for the performance as the DDC to become the deterioration direction, a change judgment of pros
and cons is recommended with a set evaluation result.
7

R/W

NDRVOFF_D_ANA

0*DT_D_IO : This register is used to slight adjustment of the electric power change efficiency. When it's short, it'll be the way of theefficient good, but when it passes the optimum point, please be careful about deteriorating.

CONFIG_DDC_ ANA _3
Addressbit

AccessName

Default

Description

ZCD detection threshold value setting
00b:x0.88, 01b:x0.94, 10b:x1.0, 11b:x1.06*ZCD_D_ANA : This register is used to slight adjustment of the electric power change efficiency.
28h

1:0

R/W

ZCD_D_ANA[1:0]10bAccessName

Default

Clear StateReset

CONFIG_LDO
Addressbit

Description

LDO_USB1000b:1Mohm, 01b:HiZ, 10b:1kohm,11b:1kohm
7:6 R/W
ZCONT_L_UPHY[1:0]00bLDO_USB33
00b:3.3Mohm, 01b:HiZ, 10b:1kohm,11b:1kohm
LDO_PERI_OUT
29h
5:4 R/W
ZCONT_L_PERI[1:0]00b00b:0.5Mohm, 01b:HiZ, 10b:1kohm,11b:1kohm
LDO_ANA_OUT
3:2 R/W
ZCONT_L_ANA[1:0]00b00b:0.5Mohm, 01b:HiZ, 10b:1kohm,11b:1kohm
LDO_EMMC_OUT
1:0 R/W
ZCONT_L_EMMC[1:0]00b00b:0.5Mohm, 01b:HiZ, 10b:1kohm,11b:1kohm*ZCONT_L_* : Setting register to remove an electric charge from output capacity at the time of a power supply output stop

60

Clear State

Reset
Reset
Reset
Reset

CXD5247GF

Status control registers
WKUP_STATUS (Return factor to “Power ON”)
Address30h

bit Access

Name

Default

Description

Clear State

0:normal, 1:SET_DWN_PRE
00b:normal, 01b:USB connect1(from Deep Sleep）, 10b:USB
connect2(from Dead Battery)Reset

00b:normal, 01b: CMD_SYS_RST, 10b:WDT
000b:normal, 001b:xINT_WKUPS pin “low”,
010b:xINT_WKUPL
pin“low”,
100b:CMD_WKUP, 101b:CMD_SLP[2:0]=001

Reset

7

R

VSYS_WKUP

0b

6:5

R

USB_WKUP[1:0]

00b

4:3

R

RST_WKUP[1:0]

00b

2:0

R

NORMAL_WKUP[2:0]

000b

Ready

CHG_VBAT=0(※1)
or UVLO detection (VDD<2.45V)

DDC/LDO=OFF
I2C=OFF
CLK_OUT=OFF
xRST_OUT=Lo
AFE=OFF→ON
CHG_VBAT=1(※1)
and UVLO detection (VDD>2.55V)

Startup

011b:Alarm,

30h[2:0]xINT_WKUPS=”Lo”
or xINT_WKUPL=”Lo” 30h[2:0]30h[6:5]or VIN=”Hi”(VBUS connect)
30h[2:0]or CMD_WKUP=1
30h[2:0]or ALARM=1
or SET_DWN_PRE=1 30h[7]and CHG_VBAT1=1

CHG_VBAT=0(※1)
or UVLO detection(VDD<2.45V)

DDC/LDO=ON
I2C=OFF
CLK_OUT=ON
xRST_OUT=Lo
AFE=ON

PGD=1（DDC/LDO Voltage detection）

UVLO detection (VDD<2.45V)
or CHG_VBAT1=030h[4:3]or WDT=1
or CMD_SYS_RST=1 30h[4:3]Power ON

DeepSleep

DDC/LDO=ON
I2C=ON
CLK_OUT=ON
xRST_OUT=Hi
AFE=ON

DDC/LDO=OFF
I2C=OFF
CLK_OUT=OFF
xRST_OUT=Lo
AFE=ONCMD_SLP=1(※2) orxINT_WKUPL=”Lo”(※2)

61

Reset

Reset

CXD5247GF

WKUP_STATUS_CLR
Address

bit Access

Name

Default3
R/W
VSYS_WKUP_CLR
2
R/W
USB_WKUP_CLR
1
R/W
RST_WKUP_CLR
0
R/W
NORMAL_WKUP_CLR*After having cleared “WKUP_STATU”, “0” is stored.
31h

0
0
0
0

Description
Clear “VSYS_WKUP”
Clear “USB_WKUP[1:0]”
Clear “RST_WKUP[1:0]”
Clear “NORMAL_WKUP[2:0]”

0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable

Clear State
Reset
Reset
Reset
Reset

WKUP_TRG
Address

bit Access

Name

Default

6R
TRG_VSYS_WKUP
5
R
TRG_USB2_WKUP
4
R
TRG_USB1_WKUP
32h
3R
TRG_CMD_WKUP
2
R
TRG_ALARM_WKUP
1R
TRG_INT_WKUPL
0R
TRG_INT_WKUPS*Start factor maintenance register

0
0
0
0
0
0
0

Description
SET_DWN_PRE signal
USB connect at Dead Battery
USB connect at Good Battery
CMD_WKUP signal
Alarm signal
xINT_WKUPL pin
xINT_WKUPS pin

0:no signal, 1:signal
0:disconnect, 1:connect
0:disconnect, 1:connect
0:no signal, 1:signal
0:no signal, 1:signal
0:Hi , 1:Lo
0:Hi , 1:Lo

Clear State
Reset
Reset
Reset
Reset
Reset
Reset
Reset

WKUP_TRG_CLR
Address

bit Access

Name

Default

6
R/W TRG_VSYS_WKUP_CLR
5R/W
TRG_USB2_WKUP_CLR
4R/W
TRG_USB1_WKUP_CLR
33h
3
R/W
TRG_CMD_WKUP_CLR
2
R/W TRG_ALARM_WKUP_CLR
1
R/W
TRG_INT_WKUPL_CLR
0R/W
TRG_INT_WKUPS_CLR*After having cleared “WKUP_TRG”, “0” is stored.

0
0
0
0
0
0
0

Description
Clear “TRG_VSYS_WKUP”
Clear “TRG_USB2_WKUP”
Clear “TRG_USB1_WKUP”
Clear “TRG_CMD_WKUP”
Clear “TRG_ALARM_WKUP”
Clear “TRG_INT_WKUPL”
Clear “TRG_INT_WKUPS”

0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable

Clear State
Reset
Reset
Reset
Reset
Reset
Reset
Reset

INTO_STATUS
Address

bit Access

Name

Default

3
R
REG_VSYS_INTO
2
R
REG_WKUPL_INTO
1
R
REG_WKUPS_INTO
0R
REG_ALARM_INTO* “INT_OUT pin output” factor maintenance register

0
0
0
0

34h

Description
SET_DWN_PRE signal
xINT_WKUPL pin
xINT_WKUPS pin
Alarm signal

0:no signal, 1:signal
0:Hi , 1:Lo
0:Hi , 1:Lo
0:no signal, 1:signal

Clear State
Reset
Reset
Reset
Reset

INTO_STATUS_CLR
Address

bit Access

Name

Default

3
R/W
REG_VSYS_INTO_CLR
2
R/W
REG_WKUPL_INTO_CLR
35h
1
R/W REG_WKUPS_INTO_CLR
0
R/W REG_ALARM_INTO_CLR*After having cleared “INTO_STATUS”, “0” is stored.

0
0
0
0

Description
Clear “REG_VSYS_INTO”
Clear “REG_WKUPL_INTO”
Clear “REG_WKUPS_INTO”
Clear “REG_ALARM_INTO”

0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable

Clear State
Reset
Reset
Reset
Reset

VMIN_DDC_CORE
Address36h

bit Access
5:0

R

Name

Default

Description

Clear State

VMIN_D_CORE[5:0]24h

The setting voltage before the WDT effect is maintained tothis register. The setting voltage and the cord refer to Table 1.

Reset

62

CXD5247GF

CMD_CTRL
Address Bit Access

Name

Default

Description

6
R/W CMD_WDT_RST[1]0
WDT enable command
5
R/W CMD_WDT_RST[0]0
WDT reset command
4
R/W
CMD_SYS_RST0
System reset command
37h
3
R/W
CMD_WKUP
0
Return to “Power ON” command2
R/W
CMD_SLP[2]1
Return to “Power ON” by xINT_WKUP pin.
1
R/W
CMD_SLP[1]1Return to “Power ON” by Alarm WakeUp.
0
R/W
CMD_SLP[0]0Sleep command*1 In CMD_SLP [0], “0” is stored by moving to "Start Up" state.

Clear State
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable

Reset
Reset
Reset
Reset
Reset
Reset
Reset

*2 When CMD_SLP [2:0]=001 is set, the state automatically moves from “Deep Sleep” to “Power ON”.
*3 In CMD_WKUP, “0” is stored by moving to "Start Up" state.
*4 In CMD_SYS_RST, “0” is stored by moving to “Ready” state.
*5 In CMD_WDT_RST [0], "0" is stored by "reset to WDT" or "clear of WKUP_TRG".

CONFIG_INT_WKUP
Address

bit Access

Name

Default

Description

Clear State

1
R/W SET_xINT_WKUPL
0
State transition of “Deep Sleep” and “Start UP” 0:disable, 1:enable
Reset
0
R/W MODE_xINT_WKUPS
0
Kind of the trigger of "the xINT_WKUPS pin" 0:level, 1:edge
Reset*SET_xINT_WKUPL : The transition to "Deep Sleep" is effective only in "Power ON", the transition to "Start UP" is effective only in"Deep Sleep".
38h* As for the transition time by " xINT_WKUPL pin", it is fixed for three seconds.
CONFIG_WDT
Address39h

bit Access
7:4
3:0

R/W
R/W

Name
INTVL_WDT[3:0]
PREC_WDT[3:0]Default

Description

0000b Time-up time setting is higher
0000b Time-up time setting is lower

63

Clear State
Reset
Reset

CXD5247GF

SET_DWN_PRE1
Address3Ah

bit Access
7:0

R/W

Name

Default

Description

Clear StateDWN_PRE_DET1[7:0]00hVoltage setting register to notify of before system movement
lower limit voltage (the LSB side: 7 - 0bit)

Reset

Name

Default

Description

Clear StateSET_DWN_PRE2
Address

bit Access

Voltage setting register to notify of before system movementResetlower limit voltage (the LSB side: 1 - 0bit)*Automatically returning it to a "Power ON" state by the battery voltage drop in "Deep Sleep" state and outside notice (INT_OUT pin)
are possible by setting 3A/3Bh.
3Bh

1:0

R/W

*Setting of the voltage

DWN_PRE_DET2[1:0]03h4.492mV×“3A/3Bh” Default 4.492mV×“0300h”=3.45V

SET_VSYS_ACT
Address
3Ch

Bit Access
7:0

R/W

Name

Default

SET_VSYS_DET[7:0]BDh

Description

Clear State

System movement lower limit voltage (18mV*Data)

Reset*SET_VSYS_ACT links CHG_VBAT1(judgment of Good/Dead Battery)*Setting of the voltage

18mV×“3Ch”

Default : 18mV×“BDh”=3.396V*The setting in 3C is a value at the time of the rises in voltage. The hysteresis is 4bit fixation.
Default: a value at the time of the voltage drop 3.396V-72mV(18mV*4bit)=3.324V

LRQ_SET_VSYS
Address
3Dh

Bit Access
1
0

R/W
R/W

Name

Default

LRQ_DWN_PRE
LRQ_VSYS_ACT

0
0

Name

Default

Description
Setting SET_DWN_PRE(3A,3Bh）
Setting SET_VSYS_ACT(3Ch)

Clear State
0:disable, 1:enable
0:disable, 1:enable

Reset
Reset

LRQ_VSYS_STATE
Address

Bit Access

Description

1

R

LRQ_DWN_STATE

0

Status of LRQ_DWN_PRE

0

R

LRQ_VSYS_STATE

0

Status of LRQ_VSYS_ACT

NameDefault

SEL_INT_OUT
INT_SEL[3]INT_SEL[2]INT_SEL[1]INT_SEL[0]

0
1
1
1
1

3Eh

Clear State

0: Setting non-completion,
1: Setting completion
0: Setting non-completion,
1: Setting completion

Reset
Reset

LRQ_SET_VSYS
Address

3Fh

Bit Access
4
3
2
1
0

R/W
R/W
R/W
R/W
R/W

Description
Output mode select of the INT_OUT pin
SYS_DWN_PRE[9:0]xINT_WKUPS pin
xINT_WKUPL pin
Alarm

64

Clear State
0:CMOS, 1:Hiz
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable
0:disable, 1:enable

Ready
Reset
Reset
Reset
Reset

CXD5247GF

RTC control registers 1
CURT_PRE_CNTR_1
Address40h

bit Access
7:0

R/W

Name

Default

CURT_PRE_1[7:0]

00h

Name

Default

CURT_PRE_2[6:0]

00h

Name

Default

CURT_POST_1[7:0]

00h

Name

Default

CURT_POST_2[7:0]

00h

Name

Default

CURT_POST_3[7:0]

00h

Name

Default

CURT_POST_4[7:0]

00h

Name

Default

Description
Stores a "pre-counter value"

Clear State

from the LSB side.(7-0bit)

Reset

CURT_PRE_CNTR_2
Address41h

bit Access
6:0

R/W

Description
Stores a "pre-counter value"

Clear State

from the LSB side.(14-8bit)

Reset

CURT_POST_CNTR_1
Address42h

bit Access
7:0

R/W

Description
Stores a "post-counter value"

Clear State

from the LSB side.(7-0bit)

Reset

CURT_POST_CNTR_2
Address43h

bit Access
7:0

R/W

Description
Stores a "post-counter value"

Clear State

from the LSB side.(15-8bit)

Reset

CURT_POST_CNTR_3
Address44h

bit Access
7:0

R/W

Description
Stores a "post-counter value"

Clear State

from the LSB side.(23-16bit)

Reset

CURT_POST_CNTR_4
Address45h

bit Access
7:0

R/W

Description
Stores a "post-counter value"

Clear State

from the LSB side.(31-24bit)

Reset

RRQ_TIME
Address

bit Access

Description

46h
0
R/W
RRQ_TIME
0
Hold request of the present time register* After stored the present time to a present time register, "0" is stored

Clear State
0:disable, 1:enable

Reset

SET_PRE_CNTR_1
Address47h

bit Access
7:0

R/W

Name

Default

Description

Clear State

SET_PRE_1[7:0]00hStores a set value to the pre-counter from the LSB side (7-0bit)

Reset

Name

Default

Description

Clear State

SET_PRE_2[6:0]00hStores a set value to the pre-counter from the LSB side (14-8bit)

Reset

SET_PRE_CNTR_2
Address48h

bit Access
6:0

R/W

65

CXD5247GF

SET_POST_CNTR_1
Address49h

bit Access
7:0

R/W

Name

Default

Description

Clear State

SET_POST_1[7:0]

00h

Name

Default

Description

Clear State

SET_POST_2[7:0]00hStores a set value to the post-counter from the LSB side (15-8bit)

Reset

Name

Default

Description

Clear State

SET_POST_3[7:0]00hStores a set value to the post-counter from the LSB side (23-16bit)

Reset

Name

Default

Description

Clear State

SET_POST_4[7:0]00hStores a set value to the post-counter from the LSB side (31-24bit)

Reset

Name

Default

Description

Clear StateStores a set value to the post-counter from the LSB side (7-0bit)

Reset

SET _POST_CNTR_2
Address
4Ah

bit Access
7:0

R/W

SET _POST_CNTR_3
Address
4Bh

bit Access
7:0

R/W

SET _POST_CNTR_4
Address
4Ch

bit Access
7:0

R/W

LRQ_TIME
Address

bit AccessRoad request to the present time register of the 0:disable, 1:enable
time road register*After loaded a time load register value to a present time register, "0" is stored
4Dh

0

R/W

LRQ_TIME

0

Name

Default

Reset

LRQ_OFST
Address

bit Access

4Eh
0
R/W
LRQ_OFST*After reflect offset time, "0" is stored

0

Description
Let reflect offset time

Clear State
0:disable, 1:enableReset

WKUP_PRE_CNTR_1
Address
4Fh

bit Access
7:0

R/W

Name

Default

Description

Clear StateWKUP_PRE_1[7:0]00hStores an offset time for time revision to a pre-counter from the
LSB side.(7-0bit)

Reset

Name

Default

Description

Clear StateWKUP_PRE_2[6:0]00hStores an offset time for time revision to a pre-counter from the
LSB side.(14-8bit)

Reset

WKUP_PRE_CNTR_2
Address
50h

bit Access
6:0

R/W

66

CXD5247GF

WKUP_POST_CNTR_1
Address51h

bit Access
7:0

Name

Default

Description

Clear State00hStores an offset time for time revision to a post-counter from the
LSB side.(7-0bit)

Reset

Default

Description

Clear State00hStores an offset time for time revision to a post-counter from the
LSB side.(15-8bit)

Reset

Default

Description

Clear State00hStores an offset time for time revision to a post-counter from the
LSB side.(23-16bit)

Reset

Default

Description

Clear State00hStores an offset time for time revision to a post-counter from the
LSB side.(31-24bit)

Reset

Name

Default

Description

Clear State

LRQ_WU

0

R/W WKUP_POST_1[7:0]

WKUP _POST_CNTR_2
Address52h

bit Access
7:0

Name

R/W WKUP_POST_2[7:0]

WKUP _POST_CNTR_3
Address53h

bit Access
7:0

Name

R/W WKUP_POST_3[7:0]

WKUP _POST_CNTR_4
Address54h

bit Access
7:0

Name

R/W WKUP_POST_4[7:0]

LRQ_WU
Address55h

bit Access
0

R/W

Let reflect WakeUp time register and0:disable, 1:enable
WakeUp condition setting register.

Reset*After reflect WakeUp time register, "0" is stored
CONFIG_WKUP
AddressName

Default

CONFIG_WKUP[1]00R/W CONFIG_WKUP[0]*Reflected at after writing in 1 to LRQ_WU

0

Repetition select in case of the
0:Not Repeat, 1:Repeat
relative time
Select of the WakeUp time
0:absolute time, 1:relative time

Name

Default

Description

CNTR_STOP

1

56h

bit Access
1

R/W

Description

Clear State
Reset
Reset

CNTR_STOP
Address57h

bit Access
0

R/W

Clock enable of the RTC counter

67

Clear State
0:disable, 1:enableReset

CXD5247GF

RTC control registers 2
ALM_PRE_CNTR_1
Address
58h

bit Access
7:0

R/W

Name

Default

ALM_PRE_1[7:0]

00h

Name

Default

ALM_PRE_2[6:0]

00h

Name

Default

ALM_POST_1[7:0]

00h

Name

Default

ALM_POST_2[7:0]

00h

Name

Default

ALM_POST_3[7:0]

00h

Name

Default

ALM_POST_4[7:0]00hDescription
Stores a pre-counter value from the LSB side.(7-0bit)

Clear StateReset

ALM_PRE_CNTR_2
Address59h

bit Access
6:0

R/W

Description
Stores a pre-counter value from the LSB side.(14-8bit)

Clear StateReset

ALM_POST_CNTR_1
Address
5Ah

bit Access
7:0

R/W

Description
Stores a post-counter value from the LSB side.(7-0bit)

Clear StateReset

ALM_POST_CNTR_2
Address
5Bh

bit Access
7:0

R/W

Description
Stores a post-counter value from the LSB side.(15-8bit)

Clear StateReset

ALM_POST_CNTR_3
Address
5Ch

bit Access
7:0

R/W

Description
Stores a post-counter value from the LSB side.(23-16bit)

Clear StateReset

ALM_POST_CNTR_4
Address
5Dh

bit Access
7:0

R/W

Description

Clear StateStores a post-counter value from the LSB side.(31-24bit)

Reset

LRQ_ALM
Address
5Eh

bit Access
0

R/W

Name

Default

Description

Clear State

LRQ_ALM0

Let reflect the interrupt output Alarm time 0:disable, 1:enableregister and Alarm condition setting register.

Reset

Description

Clear State*After reflect Alarm time setting register, "0" is stored.
CONFIG_ALARM
AddressName

Default

CONFIG_ALM[1]

0

0
R/W
CONFIG_ALM[0]* Reflected at after writing in 1 to LRQ_ALM

0

Repetition select in case of the
0:Not Repeat, 1:Repeat
relative time
Select of the Alarm time
0:absolute time, 1:relative time

Name

Default

Description

5Fh

bit Access
1

R/W

Reset
Reset

RRQ_LRQ_STATUS
Address

60h

bit Access
4

R

RRQ_TIME_STATE

0

3

R

LRQ_TIME_STATE

0

2

R

LRQ_OFST_STATE

0

1
0

R
R

LRQ_WU_STATE
LRQ_ALM_STATE

00

Status of the present time hold 0:non-completion, 1:completion
setting
Status of the present time setting 0:non-completion, 1:completion
Status of the offset reflection 0:non-completion, 1:completion
setting
Status of the WakeUp time setting 0:non-completion, 1:completion
Status of the Alarm time setting 0:non-completion, 1:completion

68

Clear State
Reset
Reset
Reset
Reset
Reset

CXD5247GF

RTC control description
The RTC function is controlled using the 6. RTC control register and the 7. Interrupt control register. (Each register is described indetail hereafter.)・Reading the current time
The current time can be acquired by setting “1” in RRQ_TIME using an I2C command, waiting approximately 8 ms, and thenreading CURT_PRE_1, CURT_PRE_2, CURT_POST_1, CURT_POST_2, CURT_POST_3 and CURT_POST_4 using an I2C
command.
・Reading the Deep Sleep transition time
The time when the IC transitioned from normal operation to the Deep Sleep state can be acquired by returning from the Deep
Sleep state, and then reading CURT_PRE_1, CURT_PRE_2, CURT_POST_1, CURT_POST2, CURT_POST_3 and
CURT_POST_4 using an I2C command.
・Loading the time (absolute time)
Set the preset time in SET_PRE_1, SET_PRE_2, SET_POST_1, SET_POST_2, SET_POST_3 and SET_POST_4 using an I2C
command. However, note that SET_PRE_1[5:0] is not used.
- Loading the time by external interrupt
The time set in SET_PRE_1, SET_PRE_2, SET_POST_1, SET_POST_2, SET_POST_3 and SET_POST_4 is loaded to the
RTC in 3.9 ms or more to 6 ms or less when an external interrupt is input in the state with “1” set in INT_LRQ_TIME using
an I2C command.
* In order to prevent unanticipated operation, it is recommended to set bit 2 of address 50h to “0” (default: 1) before
inputting the interrupt. (When this processing is not performed, bit 0 of address 43h must be set to “1” before
transitioning to the Deep Sleep state.)- Loading the time by issuing a load request using I2C
The time set in SET_PRE_1, SET_PRE_2, SET_POST_1, SET_POST_2, SET_POST_3, and SET_POST_4 is loaded to
the RTC in 3.9 ms or more to 6 ms or less by setting “1” in LRQ_TIME using an I2C command.
・Loading the time (relative time)
Set the preset time in SET_PRE_1, SET_PRE_2, SET_POST_1, SET_POST_2, SET_POST_3, SET_POST_4 using an I2C
command. However, note that SET_PRE_1[5:0] is not used. In this case, set the relative time from the current RTC time in two’s
complement format.
Example: To set +2 s
SET_PRE_1=00h, SET_PRE2=00h, SET_POST_1=02h, SET_POST_2=00h, SET_POST_3=00h, SET_POST_4=00h
Example: To set -1 s
SET_PRE_1=00h, SET_PRE2=00h, SET_POST_1=FFh, SET_POST_2=FFh, SET_POST3=FFh, SET_POST_4=FFh
The relative time set in SET_PRE_1, SET_PRE_2, SET_POST_1, SET_POST_2, SET_POST_3 and SET_POST_4 is added tothe current RTC time in 3.9 ms or more to 6 ms or less by setting “1” in LRQ_OFST using an I2C command.

69

CXD5247GF

・Setting the return time from Deep Sleep
Set the time to return from the Deep Sleep state beforehand in WU_PRE_1, WU_PRE_2, WU_POST_1, WU_POST_2,
WU_POST_3 and WU_POST_4 using an I2C command. However, note that WU_PRE_1[5:0] is not used. WU_PRE_1,
WU_PRE_2, WU_POST_1, WU_POST_2, WU_POST_3, WU_POST_4, and CONFIG_WKUP[1:0] noted below are enabled in
3.9 ms or more to 6 ms or less by setting “1” in LRQ_WU using an I2C command.
- Setting the return time by the absolute time
Set CONFIG_WKUP[1] = 0 and CONFIG_WKUP[0] = 0 (default settings) using an I2C command. In this case theabsolute time is set by WU_PRE_1, WU_PRE_2, WU_POST_1, WU_POST_2, WU_POST_3 and WU_POST_4.
- Setting the return time by the relative time (with repeat)
Set CONFIG_WKUP[1] = 1 and CONFIG_WKUP[0] = 1 using an I2C command. In this case the time to return from the
Deep Sleep state is the relative time from the current time, and is set in two’s complement format in WU_PRE_1,
WU_PRE_2, WU_POST_1, WU_POST_2, WU_POST_3 and WU_POST_4. In addition, when the return time is reached,
the time obtained by further adding the relative time is repeatedly set.
- Setting the return time by the relative time (without repeat)
Set CONFIG_WKUP[1] = 0 and CONFIG_WKUP[0] = 1 using an I2C command. In this case the time to return from the
Deep Sleep state is the relative time from the current time, and is set in two’s complement format in WU_PRE_1,
WU_PRE_2, WU_POST_1, WU_POST_2, WU_POST_3 and WU_POST_4.
・Stop
RTC counter operation stops within 2 ms after “1” is set in CNTR_STOP using an I2C command.

Selecting the interrupt output signal
Two different types of interrupt output can be selected by setting INT_SEL using an I2C command. When other values are set, aninterrupt signal is not output.
3’d0 : Outputs an interrupt signal for a 3.9 ms period starting 2 ms after the time designated below.
3’d1 : Outputs an interrupt signal in 2 ms or more to 4 ms or less when an external interrupt is input.
・Setting the interrupt output time
Set the time to output an interrupt signal beforehand in WU_PRE_1, WU_PRE_2, WU_POST_1, ALM_POST_2, ALM_POST_3
and ALM_POST_4 using an I2C command. However, note that ALM_PRE_1[5:0] is not used. ALM_PRE_1, ALM_PRE_2,
ALM_POST_1, ALM_POST_2, ALM_POST_3, ALM_POST_4 and CONFIG_ALM[1:0] noted below are enabled in 3.9 ms ormore to 6 ms or less by setting “1” in LRQ_ALM using an I2C command.
- Setting the interrupt output time by the absolute time
Set CONFIG_ALM[1] = 0 and CONFIG_ALM[0] = 0 (default settings) using an I2C command. In this case the absolute
time is set by ALM_PRE_1, ALM_PRE_2, ALM_POST_1, ALM_POST_2, ALM_POST_3 and ALM_POST_4.
- Setting the interrupt output time by the relative time (with repeat)
Set CONFIG_ALM[1] = 1 and CONFIG_ALM[0] = 1 using an I2C command. In this case the time to output the interrupt
signal is the relative time from the current time, and is set in two’s complement format in ALM_PRE_1, ALM_PRE_2,
ALM_POST_1, ALM_POST_2, ALM_POST_3 and ALM_POST_4. In addition, when the set time is reached, the time
obtained by further adding the relative time is repeatedly set.
-

Setting the interrupt output time by the relative time (without repeat)
Set CONFIG_ALM[1] = 0 and CONFIG_ALM[0] = 1 using an I2C command. In this case the time to output the interrupt
signal is the relative time from the current time, and is set in two’s complement format in ALM_PRE_1, ALM_PRE_2,
ALM_POST_1, ALM_POST_2, ALM_POST_3 and ALM_POST_4.

70

CXD5247GF

Information storage registers
DATA_GPS_ 1~16
Address
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h

bit Access
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Name

Default

DATA_GPS1[7:0]
DATA_GPS2[7:0]
DATA_GPS3[7:0]
DATA_GPS4[7:0]
DATA_GPS5[7:0]
DATA_GPS6[7:0]
DATA_GPS7[7:0]
DATA_GPS8[7:0]
DATA_GPS9[7:0]
DATA_GPS10[7:0]
DATA_GPS11[7:0]
DATA_GPS12[7:0]
DATA_GPS13[7:0]
DATA_GPS14[7:0]
DATA_GPS15[7:0]
DATA_GPS16[7:0]

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Name

Default

DATA_FREE1[7:0]
DATA_FREE2[7:0]
DATA_FREE3[7:0]
DATA_FREE4[7:0]

0
0
0
0

Description
Stores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot startStores necessary information at the time of GPS Hot start

Clear State
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset

DATA_FREE_ 1~4
Address
71h
72h
73h
74h

bit Access
7:0
7:0
7:0
7:0

R/W
R/W
R/W
R/W

Description
Stores necessary information for software sideStores necessary information for software sideStores necessary information for software sideStores necessary information for software side71

Clear State
Reset
Reset
Reset
Reset

CXD5247GF

Charge control registers
Please carry out the setting of data of 75h~7Fh in the condition of 77h[7]=0(SET_BATDATA=0).
The data of 75h~7Fh are reflected in “Stop” state72

CXD5247GF

CNT_CHG 1
Address

bit Access

Name

Default

Description

Recharge start judgment voltage(for Vo_CHG_CNT3[4:0])
Rapid charge start
4:3 R/W VO_CHG_DET2[1:0] 10b
judgment voltage
75h
2
R/W SEL_CHG_TIME20
Rapid charge timer
1
R/W SEL_CHG_TIME1
0
Pre-charge timer
Charge completion current
0
R/W SEL_CHG_TIME00
judgment time
*SEL_CHG_TIME0 links the VBUS loser detection time in the Rapid charge state.
6:5

R/W VO_CHG_DET4[1:0]00bClear State00b: -0.4V, 01b: -0.35V,
10b: -0.30V, 11b: -0.25V
00b:2.6V, 01b:2.8V,
10b:3.0V, 11b:3.2V
0:600min, 1:300min
0:60min, 1:120min
0:4clk(250ms*4clk),
1:40clk(250ms*40clk)

Reset
Reset
Reset
Reset
Reset

CNT_CHG2
Address

bit Access

Name

Default

7:5

R/W

SET_CHG_IFIN

010b

4

R/W

-

0

Description
Charge completion
judgment current
Reserved
Charge control voltage
4.0V~4.4V 50mVstep

Clear State

000b: 50mA, 001b: 40mA, 010b: 30mA,
011b: 20mA, 100b: 10mA

Reset

Reset
0000b:4.00V, 0001b:4.05V, 0010b:4.10V,
0011b:4.15V, 0100b:4.20V, 0101b:4.25V,
3:0 R/W VO_CHG_CNT3[4:0] 0100b
Reset
0110b:4.30V, 0111b:4.35V,
1000b:4.40V, 1001b~1111b:4.20V*SET_CHG_IFIN: Resistance between VSYS_CS-VBAT_CS in the case of 0.1ohm, in addition, it is effective only at Rapid charge.
76hBattery voltage
Vchg
Vrcstart

Vqcstart
Vweakbat
Vpcstart

76h[3:0](4.2V)(4.0V)
75h[6:5](3.0V)
75h[4:3](2.5V)(2.0V)

Charge current(1C-300mA)

Ichg

Ifc
Iwbchg76h[7:5](0.2C-60mA)

Ipchg(0.1C-30mA)(10mA)

75h[0]State
STBY

InitialchargePre-charge

10 sec.
Max 45 min.

Rapid charge

60 min.

600 min.

75h[1]

75h[2]

Weak Battery timer

73

ChargecompleteCXD5247GF

CNT_CHG3
Address

bit Access
7

R/W

Name

Default

SET_BATDATA

0

Description

Clear State

Battery data input
0:non-entry, 1:entry
Low temperature
00b: Charge 1C to 0deg
3:2 R/W SET_CHG_THL
00b charge setting
01b: Charge 1C to 10deg
77h(Rapid charge current)
10b: Charge 0.5C between 0deg and 10deg
High temperature
00b: 4.2V to 60deg
1:0 R/W SET_CHG_THH
00b charge setting
01b: 4.2V to 45deg*Vo_CHG_CNT3[4:0]=4.2V 10b: 4.05V between 45deg and 60deg*When "0" is storing in SET_BATDATA, the charge is not started (at Good battery).

Charge control voltage

Vchg (4.2V)
Low temperature Wait

77h[1:0]

Vchg-0.15V (4.05V)

High
temperature
Wait

Charge current

Ichg(1.0C)
Low temperature Wait

Hightemperature
Wait

77h[3:2]

Ichg*0.5(0.5C)

0℃

10℃

45℃

60℃

7Eh,7Fh

7Ch,7Dh

7Ah,7Bh78h,79h

Batterytemperature
State

Low temperature
Wait

Lowtemperature
chargeNormal charging

74

High
Hightemperature temperature
Wait
charge

Reset
Reset
Reset

CXD5247GF

SET_T60_1
Address78h

bit Access
7:0

R/W

Name

Default

Description

Clear StateSET_T60_1[7:0]E8hStores battery temperature 60 degrees from the LSB side(7-0bit)

Reset

Name

Default

Description

Clear StateSET_T60_2[3:0]2hStores battery temperature 60 degrees from the LSB side(11-8bit)

Reset

Name

Default

Description

Clear StateSET_T45_1[7:0]A4hStores battery temperature 45 degrees from the LSB side(7-0bit)

Reset

Name

Default

Description

Clear StateSET_T45_2[3:0]4hStores battery temperature 45 degrees from the LSB side(11-8bit)

Reset

Name

Default

Description

Clear StateSET_T10_1[7:0]D5hStores battery temperature 10 degrees from the LSB side(7-0bit)

Reset

Name

Default

Description

Clear StateSET_T10_2[3:0]AhStores battery temperature 10 degrees from the LSB side(11-8bit)

Reset

Name

Default

Description

Clear StateSET_T0_1[7:0]07hStores battery temperature 0 degrees from the LSB side(7-0bit)

Reset

Name

Default

Description

Clear StateSET_T0_2[3:0]ChStores battery temperature 0 degrees from the LSB side(11-8bit)

Reset

SET_T60_2
Address79h

bit Access
4:0

R/W

SET_T45_1
Address
7Ah

bit Access
7:0

R/W

SET_T45_2
Address
7Bh

bit Access
4:0

R/W

SET_T10_1
Address
7Ch

bit Access
7:0

R/W

SET_T10_2
Address
7Dh

bit Access
4:0

R/W

SET_T0_1
Address
7Eh

bit Access
7:0

R/W

SET_T0_2
Address
7Fh

bit Access
4:0

R/W

75

CXD5247GF

Ratio
Temperature[deg]
-40
97.8%
-35
96.9%
-30
95.6%
-25
94.1%
-20
92.0%
-15
89.4%
-10
86.3%
-5
82.5%
0
78.1%
2.5
75.6%
272.5
5
73.2%
209.71
10
67.7%
12.5
64.8%
162.65115
61.9%
127.08
20
56.0%
100
25
50.0%
79.22230
44.2%
63.16735
38.7%
50.677
40
33.6%
42.5
31.3%
40.90445
29.0%
33.19550
24.9%
27.091
55
21.3%
57.5
19.7%
22.22460
18.2%
18.32365
15.5%
15.18470
13.2%
12.63575
11.2%
10.566
80
9.6%
8.873
85
8.1%
7.481
90
7.0%
6.337
95
6.0%
5.384
100
5.1%
4.594
105
4.4%
3.934
110
3.8%
3.38
115
3.3%
2.916
120
2.8%
2.522
125
2.5%
Input value of TH terminal at using NCP15WF104F03RC
R[kohm]4397.123088.62197.23
1581.881151.04
846.579628.988471.632
357.012

DEC
4005
3968
3918
3852
3769
3663
3534
3379
3200
3098
2996
2773
2655
2536
2292
2048
1810
1586
1378
1283
1189
1021
873
809
745
634
540
459
391
334
285
244
209
180
155
134
116
101

76

HEX
FA4
F7F
F4D
F0C
EB8
E4F
DCE
D33
C7F
C19
BB4
AD5
A5E
9E8
8F4
7FF
712
631
561
503
4A4
3FC
369
328
2E8
27A
21B
1CB
187
14D
11D
F4
D1
B3
9B
85
74
64

SET_T0: detection side
SET_T0: cancellation side
SET_T10: detection side
SET_T10: cancellation side

SET_T45: cancellation side
SET_T45: detection side

SET_T60: cancellation side
SET_T60: detection sideCXD5247GF

CNT_USB1
Address

bit Access

Name

Default

5:1 R/W
STATE_CHG
0
R/W
USB_PORT_TYPE*STATE_CHG reflects in “8Bh=1”80h80h[5:1]
5'd0
5'd1
5'd2
5'd3
5'd4
5'd5
5'd6
5'd7
5'd8
5'd9
5'd10
5'd11
5'd12
5'd13
5'd14
5'd15
5'd16
5'd17
5'd18
5'd19
5'd20
5'd21
5'd22
5'd23
5'd24
5'd25

00h
0

Description
Charge state storage register
USB port classification

0:SDP, 1:DCP/CDP

Clear State
Reset
Reset

STATE
P_S_INIT_RST
P_S_INIT_WAIT
P_S_INIT_CHK
P_S_DBP_START
P_S_DB_INICHARGE
P_S_DB_PRECHARGE
P_S_DCON_WAIT
P_S_PD_START
P_S_DM_COMPARE
P_S_PD_END
P_S_BAT_WAIT
P_S_CHG_STOP
P_S_GB_PRECHARGE
P_S_GB_QCKCHARGE
P_S_GB_LOWCHARGE
P_S_GB_HIGHCHARGE
P_S_CHG_JUDGE
P_S_CHG_COMPLETE
P_S_GB_CONWAIT
P_S_GB_CPTEMPWAIT1
P_S_GB_CPTEMPWAIT2
P_S_GB_TEMPWAIT
P_S_DB_TEMPWAIT
P_S_DB_CONWAIT
P_S_BAT_UNUSUAL
P_S_BAT_DISCON

CNT_USB2
Address

bit Access

Name

Default

Description

2
R/W
SET_CHGOFF
0Forced charge reset signal 0:normal, 1:reset
1:0 R/W
USB_CUR_LIM
00b Charge current setting
00b:<2.5mA, 01b:<100mA, 10b:<500mA* Charge and all the USB detection functions are initialized by “SET_CHGOFF=1”
81h

77

Clear State
Reset
Reset

CXD5247GF

AFE control registers
SET_AFE_1
Address

bit Access

Name

Default

Description

Clear State00h

Measurement period “Ts” setting in Ready,StartUP,PowerON.

Reset

82h
5:0 R/W
SET_ACT_1[5:0]*The measurement period is cf. list shown below.

*As for the data of 82h~84h, setting is recommended in 84h[3:2]=00b (measurement stop).
*After a measurement period changed, a measurement is carried out immediately.
SET_AFE_2
Address

bit Access

Name

83h
5:0 R/W
SET_ACT_1[5:0]*The measurement period is cf. list shown below

Default
0Ch

HEX
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13

Description
Measurement period “Ts” setting in Deep Sleep.

DEC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Ts
125
250
500
1
2
4
8
16
32
1.067
2.133
4.267
8.533
17.06734.133
1.138
2.276
4.551
9.102
18.204

Clear State
Reset

ms
ms
ms
sec
sec
sec
sec
sec
sec
min
min
min
min
min
min
h
h
h
h
h

SET_AFE3
Address

bit Access

Name

Default

3:2

R/W

SET_ACT_4

01b

1:0

R/W

SET_ACT_3[1:0]

00b

84h

Description
00b:Mesurement stop,
01b: repetition measurement,
02b:once measurement
00b:one time,
Moving average number of times 01b:two times,
10b:four times

Movement measurement mode

*SET_ACT_3 is 00b after 02b note movement*SET_ACT_3 is applied to 3C register, 85~8A,8D,8E register

78

Clear State
Reset
Reset

CXD5247GF

DATA_AFE* of 85h~8Ah is taken in in 8Bh= "1"
DATA_AFEV_1
Address85h

bit Access
7:0

R

Name

Default

DATA_AFEV_1[7:0]

00h

Name

Default

DATA_AFEV_2[3:0]

00h

Name

Default

DATA_AFEI_1[7:0]

00h

Name

Default

DATA_AFEI_2[3:0]

00h

Name

Default

DATA_AFET_1[7:0]

00h

Name

Default

DATA_AFET_2[3:0]

00h

Name

Default

Description
Stores the battery voltage from the LSB side (7-0bit)

Clear StateReset

DATA_AFEV_2
Address
86h

bit Access
3:0

R

Description
Stores the battery voltage from the LSB side (11-8bit)

Clear StateReset

DATA_AFEI_1
Address87h

bit Access
7:0

R

Description
Stores the battery current from the LSB side (7-0bit)

Clear StateReset

DATA_AFEI_2
Address
88h

bit Access
3:0

R

Description
Stores the battery current from the LSB side (11-8bit)

Clear StateReset

DATA_AFET_1
Address89h

bit Access
7:0

R

Description
Stores the battery temperature from the LSB side (7-0bit)

Clear StateReset

DATA_AFET_2
Address
8Ah

bit Access
3:0

R

Description
Stores the battery temperature from the LSB side (11-8bit)

Clear StateReset

LRQ_AFE
Address

bit Access

8Bh
0
R/W
LRQ_AFED*After reflect DATA_AFE register, "0" is stored.

0

Description
Reflect AFE register0:disable, 1:enable

Clear StateReset

LRQ_STATUS
Address
8Ch

bit Access
0

R

Name

Default

LRQ_AFED_STATE

0

Description
Status of AFE data

79

0: Setting non-completion,
1: Setting completion

Clear StateResetCXD5247GF◆Audio interface specifications
CXD5247 performs signal transfer with the CXD5602 using an original format. The timing chart is shown below. The output signals
to the SP can be set to the two modes of 16fs or 32fs, and the MIC output can be set to the two modes of 64fs (8Mic) or 128fs (4Mic).

Interface Timing
SP Signal PathSP Signal Path
The serialized audio signals (DA_DATA, FS_CLK) output from the CXD5602 are input to the Deserialize circuit and converted into
two channels of 6-bit PDM signals. These signals are converted into 1-bit PWM signals by the PDMtoPWM conversion circuit, andthen output as audio signals from the drivers. In addition, a StartUP signal generation circuit is provided separately from the main line
signal as a popping noise countermeasure during power-on, and when the popping noise countermeasure is set, the generated StartUp
signal is selected by the register and output.

80

CXD5247GF

Deserialize
There are two types of the input format (16fs/32fs)..

16fs Mode Timing

32fs Mode Timing
There are no settings for this circuit. Operation switches between 16fs and 32fs mode in accordance with the input signal.
This circuit has a function that checks for the presence of a separately input FSCLK, and the result is stored in the internal register as
the FS_LOCK status information.

81

CXD5247GF

StartUP signal generation

StartUP Block
A sequence circuit raises the output pin voltage gradually from 0 V to 1/2 AVDD_DRV* in order to reduce the popping noise generated
during power-on when a headphone speaker is connected to the CXD5247 Audio SP output by capacitor coupling. In addition, popping
noise generated during power-off can be reduced by operating this circuit in the reverse direction. The PWM conversion circuit input
switches during sequence operation.

StartUP/SleepDOWN sequence

CLK_SU
STR_PWM_OUT

1

6

ON
0(fix Lo)2

51(Start UP Sig)

COUNT_UD

OFF（or ON）

OFF（or ON）

2(Sig)

2(Sig)XXX

Lo = Up

9ON

101(Start UP Sig)

11

XXX

0(fix Lo)High = Down

3

COUNT_RSTX

4

COUNT_EN

12

COUNT_ZERO(Status)
COUNT_FULL(Status)

5

STR_SIG_SEL

10
7

Pch Analog
outputSpritzer Mute

8
13

Vcc
1/2VccDuty50

Duty50

Duty50

Duty50

Duty50

Duty50

Duty50

Duty500V

Nch Analog
outputVcc
1/2Vcc0V

Mute OFFLo

Start UP

Mute ON

CXD5602 signal

CXD5602 signal

Sleep DOWNLoPower off possible period
CXD5602 operates withthe mute stateThis is the setting sequence when using the sequence circuit. Follow the sequence below and make the settings after the CLK setting
sequence.

82

CXD5247GF

StartUP (power-on)

Set the CXD5602 side to the MUTE state.

1. CLK_SU 0(default)→1
2. STR_PWM_OUT

Set the StartUP circuit CLK to on.

0(default)→1

Select the StartUP circuit signal.

3. COUNT_RSTX / COUNT_EN 0→1

The StartUP circuit operates. At this time COUNT_UD = 0 (default).

4. Change COUNT_EN from “1” to “0” after the set STR_TC time or when COUNT_FULL = 1 (Status).
5. STR_SIG_SEL

0(default)→1、STR_PWM_OUT

6. CLK_SU 1→0

1→2

Select the audio signal from CXD5602.

Turn off the StartUP circuit CLK to save power. (The CLK can also be left on without problem.)

7. Cancel the CXD5602 MUTE.
SleepDOWN (power-off)
8. Set the CXD5602 side to the MUTE state.
9. CLK_SU 0→1

Set the StartUP circuit CLK to on.

10. STR_SIG_SEL

1→0、STR_PWM_OUT

2→1

Select the StartUP circuit signal.

11. COUNT_UD 0(default)→1
12. COUNT_EN 0→1

The StartUP circuit operates. (SleepDOWN operation)

13. Operation ends (power-off) after the set STR_TC time or when COUNT_ZERO = 1 (Status).

* Do not change the other register values during the period while COUNT_EN = 1.

PWM conversion
The input 6-bit PDM signals are converted to PWM signals. 2-bit (Pos/Neg) signals are output on each of Ach and Bch. 24.576 MHz
operation is set in 16fs mode, and 49.152 MHz is set in 32fs mode.

Register name

Description

MCKSELI

Sets operation according to the CLK frequency. Pleasechange the value below in accordance with the operatingmode.
1: 16fs mode with 24.576MHz or 32fs mode with49.152MHz
0: 16fs mode with 49.152MHz

CHSEL

Replace Ach and Bch
0: standard <default>
1: replace Ach and Bch

OUT2DLYPWM delay of negative signal (SPAN, SPBN)
0 : <default<
1: 1clk@master clock
N: n-clk@master clock
15: 15clk@master clock83

CXD5247GF

Register name

Description

PWMMD

Selects PWM convert mode
0 : One side modulation mode
1: Both side modulation mode <default>
2: Alternated one side modulation mode
3: Alternated one side modulation mode

PWM_OUTSEL_LR

Selects negative signal (SPAN/SPBN) of driver output
0: standard operation <default>
1: ~LP/~RP
2/6/7: Low
3: High
4: 50% duty cycle signal
5: inverse of 50%duty cycle signal

STR_PWM_OUT

Selects startup signal
0: Low<default>
1: Select Startup signal
2/3: normal operation

SP DriverAn external speaker (8Ω) is driven by a low resistance driver circuit. The input Ach and Bch 2-bit (Pos/Neg) PWM data is switched to
the low jitter clock domain to reduce output noise due to clock jitter. This driver has a pulse width correction circuit called a feedback
loop that enables to effectively correct driver error due to factors such as power supply fluctuation, driver Pos/Neg mismatch, or deadtime distortion. The driver clock settings are described in the clock generation block section.

84

CXD5247GF

SP Driver Block
Register name

Description

SP_EN_SPAPControl the driver output

SP_EN_SPAN

0: disable

SP_EN_SPBP

1: enable

SP_EN_SPBN
SP_DELAYSELAP<1:0>

Selects the driver’s dead time

SP_DELAYSELAN<1:0>

0 : shortest <default>

SP_DELAYSELBP<1:0>

1: shorter

SP_DELAYSELBN<1:0>

2: longer
3: longest85

CXD5247GF

Register name

Description

SP_LOOPSEL

Selects the output
0: normal operation <default>
1: select the loop signal

SP_LOOPEN

Control loop circuit
0: disable
1: enable

SP_CAPSEL

Selects the feedback capacitor
0: 16fs mode (24.576MHz) <default<
1: 32fs mode (49.152MHz)

SP_LAMPISELInternal bias current setting
0: normal <default>
1: test only

SP_EN_BGR

Sets the reference voltage
0: normal operation <default>
1: please set if loop circuits is enable

SP_EN_BIas

Sets the internal bias
0 normal operation <default>
1: please set of loop circuits is enable86

CXD5247GF◆MIC signal path
This IC has four systems of analog microphone interfaces (microphone amplifier with PGA function: ΔΣADC) and eight systemsof digital microphone interfaces. The analog microphone input pins and digital microphone input pins are shared and used exclusively.
The analog microphone interfaces convert the analog microphone signals to digital data. A clock generation circuit and a dither
generation circuit are provided as ADC control signals. The data output by the ADC is digitally processed and converted to 1-bit PDM
signals. This processing consists of a CIC-Decimator, offset adjustment circuit, gain adjustment circuit, and ΔΣModulator circuit.
The output data rate can be set to 64fs or 128fs. In addition, the digital microphone interfaces perform DDR-SDR conversion on thesignals. The above microphone signals (analog 4ch + digital 8ch, total 12ch) are input to the serialize circuit, converted to 8 channels
or 4 channels of 1-bit serial data, and output from CXD5247 as AD_DATA.

MIC Signal Path87

CXD5247GF

Analog microphone input configuration
Each analog microphone input is dc-biased to center voltage between AVDD_MIC and AGND_MIC. Two types setting for biasing canbe selected. First is the individually biased using each reference pins(MICAREF/MICBREF/MICCREF/MICDREF), second is theshared biasing using common bias pins(MIC_REF). To minimize the external components (remove decoupling capacitor), sharedbiasing type is useful. Table * shows the input bias setting.

Table MIC bias configuration
Register name

Description

MIC_EN_VM

MIC_REF control
0: disable
1:enable

MICA_VM_EXC_SEL

Analog microphone input A bias setting
0: shared
1:indivisual

MICB_VM_EXC_SEL

Analog microphone input B bias setting
0: shared
1:indivisual

MICC_VM_EXC_SEL

Analog microphone input C bias setting
0: shared
1:indivisual

MICD_VM_EXC_SEL

Analog microphone input D bias setting
0: shared
1:indivisual

PGA setting
Analog microphones inputs have two stages of programmable gain amplifiers(PGAs). A coarse preamplifier gain stage offers selectable
0dB, 3dB, 6dB, 9dB, 12dB and 15dB gain settings. A fine stage is a PGA adjustable from 0dB to 6dB in 0.5dB steps. (Tables * and *).
The two stages provide up to 21dB of signal gain for the analog microphone inputs. To maximize the signal-to-noise ratio, use thecoarse gain setting of the first stage whenever possible.

Table MIC Gain configuration
Register name

Description

MICA_MICGAIN<2:0>

Microphone A input MICGAIN setting
101 +15dB
100 +12dB
011 +9dB
010 +6dB
001 +3dB
000 0dB <default>
Other prohibited88

CXD5247GF

Register name

Description

MICB_MICGAIN<2:0>

Microphone B input MICGAIN setting
101 +15dB
100 +12dB
011 +9dB
010 +6dB
001 +3dB
000 0dB <default>
Other prohibited

MICC_MICGAIN<2:0>

Microphone C input MICGAIN setting
101 +15dB
100 +12dB
011 +9dB
010 +6dB
001 +3dB
000 0dB <default>
Other prohibited

MICD_MICGAIN<2:0>

Microphone D input MICGAIN setting
101 +15dB
100 +12dB
011 +9dB
010 +6dB
001 +3dB
000 0dB <default>
Other prohibited89

CXD5247GF

Table PGA gain configration
Register name

Description

MICA_PGAGAIN<3:0>

Microphone A input PGA gain setting
1100 +6.0dB
1011 +5.5dB
1010 +5.0dB
1001 +4.5dB
1000 +4.0dB
0111 +3.5dB
0110 +3.0dB
0101 +2.5dB
0100 +2.0dB
0011 +1.5dB0010 +1.0dB
0001 +0.5dB
0000 0dB <default>
Others : prohibited

MICB_PGAGAIN<3:0>

Microphone B input PGA gain setting
1100 +6.0dB
1011 +5.5dB
1010 +5.0dB
1001 +4.5dB
1000 +4.0dB
0111 +3.5dB
0110 +3.0dB
0101 +2.5dB
0100 +2.0dB
0011 +1.5dB0010 +1.0dB
0001 +0.5dB
0000 0dB <default>
Others : prohibited90

CXD5247GF

Register name

Description

MICC_PGAGAIN<3:0>

Microphone C input PGA gain setting
1100 +6.0dB
1011 +5.5dB
1010 +5.0dB
1001 +4.5dB
1000 +4.0dB
0111 +3.5dB
0110 +3.0dB
0101 +2.5dB
0100 +2.0dB
0011 +1.5dB0010 +1.0dB
0001 +0.5dB
0000 0dB <default>
Others : prohibited

MICD_PGAGAIN<3:0>

Microphone D input PGA gain setting
1100 +6.0dB
1011 +5.5dB
1010 +5.0dB
1001 +4.5dB
1000 +4.0dB
0111 +3.5dB
0110 +3.0dB
0101 +2.5dB
0100 +2.0dB
0011 +1.5dB0010 +1.0dB
0001 +0.5dB
0000 0dB <default>
Others : prohibited91

CXD5247GF

Table MIC control pins
Register name

Description

Digital Microphone interface

The digital microphone transfers the L/R signal at both the rising and falling edges of DMCLK (CLK for
digital microphone), so this function separates the input signal into the two L and R signals. The I/O timing
chart is shown below.

DMCLK
3.072MHzDMIC input
Lch output
Rch output
DMIC Timing
Table Digital MIC interface configuration
Register name

Description

MICA_EN_DMIC12MICA, Digital microphone interface enabler
0:disable
1:enable

MICA_EN_DMIC34

MICB, Digital microphone interface enabler
0:disable
1:enable

MICA_EN_DMIC56

MICC, Digital microphone interface enabler
0:disable
1:enable

MICA_EN_DMIC78

MICD, Digital microphone interface enabler
0:disable
1:enable

Serialize

This function selects and serializes the 4 channels of analog microphone signals and 8 channels of digital
microphone signals (total 12 channels of microphone signals). The signals are output from AD_DATA ofCXD5247 synchronized with FSCLK, which is the timing reference for the interface with the CXD5602.
Two output formats are available: 64fs (3.072 MHz/sample) and 128fs (6.144 MHz/sample). The 64fs format
enables 8-channel signal transfer, and the 128fs format enables 4-channel signal transfer. The timing chart foreach format is shown below.
* The digital microphone signal supports only the 64fs format, and cannot be used with the 128fs format.

92

CXD5247GF

64fs Mode Digital MIC Interface Timing
MCLK
24.576MHz
FSCLK

2MCLK

MICA

AMIC1-0

AMIC1-1

AMIC1-2

MICB

AMIC2-0

AMIC2-1

AMIC2-2

MICC

AMIC3-0

AMIC3-1

AMIC3-2

MICD

AMIC4-0

AMIC4-1

AMIC4-2

AD_DATA

64fs Mode Analog MIC Interface Timing

128fs Mode Analog MIC Interface Timing

Serialize mode of 64fs and 128fs is selected by SER_MODE register. Data order in AD_DATA such as D1-0, A1-0 is optionallyselectable using configuration register SEL_CHx. (talble * and *)93

CXD5247GF

Table serializer configuration
Register name

Description

SER_MODE

Selects serialize mode 64fs or 128fs
0: 64fs mode (8ch data can be transferred)
1:128fs mode (4ch data can be transferred)

SEL_CHx

Selects serial output data order. X=1..8
0: 0
1: selects AMIC1
2: selects AMIC2
3: selects AMIC3
4: selects AMIC4
5: selects DMIC1
6: selects:DMIC2
7: selects DMIC3
8: selects DMIC4
9: selects DMIC5
10: selects DMIC6
11: selects DMIC7
12: selects DMIC8
13-15:094

CXD5247GF◆Clock specifications
X’tal Buffer
CXD5247 Audio block has a low jitter crystal oscillator amplifier for the system clock and class-D amplifier reference clock. To
minimize the clock jitter, macro has an LDO for internal power supply and internal load capacitance. Load capacitances controlled by
CAPCG/CAPCD are integrated to remove external capacitances and selectable for x’tal matching. This is very effective to achieve low
jitter performance avoiding noise from uncontrolled GND bounce. Drive strength is selectable for both oscillation frequency of
24.576MHz and 49.152MHz, and also enables to reduce the operating current at stable oscillation. Figure * shows the oscillator block
diagram with control register. Internal series resister can be used for control drive level.

IIC_XO_OCI_I

IIC_XO_EN_CLK_DIG

IIC_XO_EN_CLK_ANA_B

IIC_XO_EN_CLK_ANA_A

IIC_XO_OCI_I

IIC_XO_EN_OSC

IIC_XO_CAP_CD

IIC_XO_CAPCGIIC_XO_RD

Clocks can be controlled by XO_EN_CLK_DIG/XO_CLK_ANA_A/ XO_CLK_ANA_B for several use-case.

Register name

Description

XO_CAP_CG<7:0>

Selects internal load capacitance

XO_CAP_CD<7:0>

0: 0[pF] <default>
19: 9.5[pF] for 49.152MHz
26: 13[pF] for 24.576MHz
Othersdata: data/2 [pF]95

CXD5247GF

Register name

Description

XO_OSC_I<7:0>

Selects driver strength0 : 0[uA] <default>
6 : 360[uA] for stable oscillation at 49.152MHz, less than
100uW of maximum oscillation level
8 : 480[uA] for stable oscillation at 24.576MHz, less than
200uW of maximum oscillation level
9 : 540[uA] for stable oscillation at 49.152MHz, less than
200uW of maximum oscillation level.
13 : 780[uA] for start-up at 24.576MHz
15:900[uA] for start-up at 49/152MHz
OthersData: data x 60 [uA]

XO_RD<1:0>

Selects series resistance of XO_A from driver
0 : 450 ohm for start-up of 49MHz oscillation
1: 550 ohm (spare)2:650 ohm for stable oscillation of 49MHz
3: 750 ohm for startup and stable oscillation of 24MHz

Start up sequence is shown in Figure *.
Internal LDO is controlled by the register (EN_BGR/EN_LDO) to generate the internal power supply. After load capacitance, series
resister and drive current registers are set, oscillation is started controlled by EN_OSC register. Drive current can be reduced at stableoscillation.

96

CXD5247GF

I2C specifications
Symbol
fSCL

Item

Min.

Max.

Unit

SCL clock frequency

0

400

kHz

0.6

-

us

Hold time (repeat) start conditiontHD:STA(The first clock pulse is generated after this period.)tLOW

SCL clock Low period

1.3

-

us

tHIGH

SCL clock High period

0.6

-

us

tSU:STA

Repeat start condition setup time

0.6

-

us

tHD:DAT

Data hold time

0

-

us

tSU:DAT

Data setup time

100

-

ns

tr

SDA signal and SCL signal rise time

-

300

ns

tf

SDA signal and SCL signal fall time

-

300

ns

tSU:STO

Stop condition setup time

0.6

-

us

tBUF

Bus free time between Stop and Start conditions

1.3

-

us

Cb

Capacitance load of each bus line

-

400

pF

t R , tF

tBUF

SDA
tSU:DATtHD:STAtHD:DATtSU:STA

SCL
tLOW

tHIGH

Slave Address of CXD5247 Audio is 7’h1E.

97

tSU:STOCXD5247GF

Register Description◆Power register list
No.

Category

Address

Register nameApplication

10h

EN_CTRL1

11h

EN_CTRL2

12h

LOAD_SW_CTRL1

13h

GPO_CTRL1

14h

GPO_CTRL2

15h

VO_DDC_ANA

Sets the DDC_ANA output voltage

16h

VO_DDC_CORE

Sets the DDC_CORE output voltage

17h

VO_LDO_EMMC/PERI

Sets the LDO_EMMC/PERI output voltage

18h

VO_LDO_ANA

Sets the LDO_ANA output voltage

20h

CONFIG_DDC_IO_1

21h

CONFIG_DDC_IO_2

22h

CONFIG_DDC_IO_3

23h

CONFIG_DDC_CORE_1

24h

CONFIG_DDC_CORE_2

25h

CONFIG_DDC_CORE_3

26h

CONFIG_DDC_ANA_1

27h

CONFIG_DDC_ANA_2

28h

CONFIG_DDC_ANA_3

29h

CONFIG_LDO

Sets the LDO operating mode

30h

WKUP_STATUSStores the start-up factor

31h

WKUP_STATUS_CLR

Clears the start-up factor_STATUS

32h

WKUP_TRGStores the start-up factor output trigger

33h

WKUP_TRG_CLR

Clears the start-up factor output trigger

34h

INTO_STATUSStores the INT_OUT output trigger

35h

INTO_STATUS_CLR

Clears the INT_OUT output trigger(Power supply block)36h

VMIN_DDC_CORE

Holds the setting voltage before WDT issues

Status control registers

37h

CMD_CTRLStores the I2C control command

38h

CONFIG_INT_WKUP

Sets the xINT_WKUP condition

39h

CONFIG_WDT

WDT setting

3Ah

SET_DWN_PRE1

System operation lower limit voltage pre-notification

3Bh

SET_DWN_PRE2

voltage setting status

3Ch

SET_VSYS_ACTSets the system operating voltage

3Dh

LRQ_SET_VSYS

Reflects the 3Ah to 3Ch settings

D/D converter and LDO enable control

GPO0～7 Output control(Power supply block)1

LOAD_SW enable control

Output control registers(Power supply block)2

Sets the DDC_IO operating mode

Sets the DDC_CORE operating mode

Power supply operating
mode setting registers

Sets the DDC_ANA operating mode

398

CXD5247GF

No.

Category

Address

Register nameApplication

3Eh

LRQ_VSYS_STATE

VSYS setting status

3Fh

INT_SEL

Selects the INT_OUT output

40h

CURT_PRE_CNTR_1

41h

CURT_PRE_CNTR_2

42h

CURT_POST_CNTR_1

43h

CURT_POST_CNTR_2

44h

CURT_POST_CNTR_3

45h

CURT_POST_CNTR_4

46h

RRQ_TIME

47h

SET_PRE_CNTR_1

48h

SET_PRE_CNTR_2

49h

SET_POST_CNTR_1

4Ah

SET_POST_CNTR_2

4Bh

SET_POST_CNTR_3

4Ch

SET_POST_CNTR_4

4Dh

LRQ_TIME

Set time load request to the counter

4Eh

LRQ_OFST

Reflects the offset time

4Fh

WKUP_PRE_CNTR_1

50h

WKUP_PRE_CNTR_2

51h

WKUP_POST_CNTR_1

52h

WKUP_POST_CNTR_2

53h

WKUP_POST_CNTR_3

54h

WKUP_POST_CNTR_4

55h

LRQ_WU

Reflects the WakeUp time registers

56h

CONFIG_WKUP

Condition settings of WakeUp

57h

CNTR_STOP

Enable control of RTC counter

58h

ALM_PRE_CNTR_1

59h

ALM_PRE_CNTR_2

5Ah

ALM_POST_CNTR_1

Sets the interrupt output alarm time (absolute time,(Power supply block)

5Bh

ALM_POST_CNTR_2

relative time)

Interrupt output control

5Ch

ALM_POST_CNTR_3

registers

5Dh

ALM_POST_CNTR_4

5Eh

LRQ_ALM

Reflects the interrupt output alarm time setting registers

5Fh

CONFIG_ALARM

Sets the alarm condition

60h

RRQ_LRQ_STATUS

Time data status(Power supply block)61h

DATA_GPS1

Information storage62h

DATA_GPS2Stores the current time

(Power supply block)4
RTC control registers

Current time read request

Stores the set time to the counter(Power supply block)4
RTC control registers

Sets the WakeUp time (absolute time, relative time)

5

6

Stores the GPS data99

CXD5247GF

No.

Category

Address

Register nameregisters63h

DATA_GPS364h

DATA_GPS465h

DATA_GPS566h

DATA_GPS667h

DATA_GPS768h

DATA_GPS869h

DATA_GPS96Ah

DATA_GPS10

6Bh

DATA_GPS11

6Ch

DATA_GPS12

6Dh

DATA_GPS13

6Eh

DATA_GPS14

6Fh

DATA_GPS1570h

DATA_GPS1671h

DATA_FREE1

72h

DATA_FREE2

73h

DATA_FREE374h

DATA_FREE475h

CNT_CHG1

76h

CNT_CHG2

77h

CNT_CHG378h

SET_T60_1

79h

SET_T60_2

7Ah

SET_T45_1

7Bh

SET_T45_2

7Ch

SET_T10_1

7Dh

SET_T10_2

7Eh

SET_T0_1

7Fh

SET_T0_2

80h

CNT_USB1

81h

CNT_USB282h

SET_AFE1

83h

SET_AFE2(AFE block)84h

SET_AFE3

Control registers

85h

DATA_AFEV_1

86h

DATA_AFEV_2

87h

DATA_AFEI_1

Application

Stores the information required by the software side

Battery voltage judgment and control registers(Charge block)7
Control registers

Battery temperature control registers

USB charge control registers

AFE operation setting registers

8Stores the AFE measurement data

100

CXD5247GF

No.

Category

Address

Register nameApplication

88h

DATA_AFEI_2

89h

DATA_AFET_1

8Ah

DATA_AFET_2

8Bh

LRQ_AFE

Reflects the AFE measurement data to the registers

8Ch

LRQ_AFED_STATE

AFE data status

8Dh

DATA_AFEI_OF1

8Eh

DATA_AFEI_OF2

Stores the DC offset data for AFE current measurement* Note that addresses 90h and higher are assigned as test registers, and should not be used.

101

CXD5247GF◆Audio register list
No.

1CategoryBank

Address

Register nameApplication

00h

00h

Bank Setting

00h

01h

REG Freeze

00h

02h

REG Clear

00h

08h

Repeater Setting

00h

10h

MICIN Control

00h

11h

MICGAIN_1

00h

12h

MICGAIN_2

00h

13h

PGA GAIN_1

00h

14h

PGA GAIN_2

00h

15h

ADC Control_1

00h

16h

ADC Control_2

00h

17h

ADC Control_3

00h

18h

ADC Ref Control

MIC AMP setting

00h

19h

BGR Control

Reference Circuit enable control

00h

1Ah

MIC Bias Control_1

00h

1Bh

MIC Bias Control_2

00h

1Ch

DMIC Control

DMIC Buffer enable control

00h

1Fh

MIC LDO control

MIC LDO control

00h

20h

Speaker Control_1

00h

21h

Speaker Control_2

00h

22h

Speaker loop control

Speaker Loop control

00h

23h

SP LDO control

Speaker LDO enable control

00h

24h

SP Delay control

Speaker Dead Time select

00h

26h

MIC LDO control

MIC LDO enable control

00h

27h

MIC control

MIC VM Exclude pin select

00h

30h

XOSC control_1

00h

31h

XOSC control_2

00h

33h

XOSC setting_1

00h

34h

XOSC setting_2

00h

35h

XOSC setting_3

00h

36h

XOSC setting_4

00h

37h

XOSC setting_5

00h

38h

XOSC setting_6

00h

39h

XOSC setting_7

00h

80h

Logic I/O_1

Audio REG Setting

MIC AMP enable control
MIC AMP Ｇａｉｎ Setting

MIC pre AMP

2Ｇａｉｎ Setting

MIC ADC enable control

MIC Setting

MIC Bias enable control

Speaker enable control
3

Speaker Setting

XOSC enable control

4

OSC Setting

102

XOSC Setting

LOGIC IO Setting

CXD5247GF

No.

CategoryBank

Address

Register name

00h

81h

Logic I/O_2

00h

82h

Logic I/O_3

00h

FDh

chipidApplication

Chip ID103

CXD5247GF

No.

CategoryBank

Address

Register nameApplication

01h

10h

CLK_SEL

CLK Setting

01h

11h

CLK_EN01h

12h

CLK_OUT_EN

01h

14h

SEL_CH1201h

15h

SEL_CH34

01h

16h

SEL_CH56

01h

17h

SEL_CH78

01h

18h

SER_CTRL

01h

19h

STARTUP_CTRL_1

01h

1Ah

STARTUP_CTRL_2

01h

1Bh

PWM_OUTSEL

01h

1Ch

SMSTR_PWM_CTRL_1

01h

1Dh

SMSTR_PWM_CTRL_2

01h

1Fh

LOGIC_STATUS

01h

20h

ADSEL

01h

21h

ADGAIN_1

01h

22h

ADGAIN_2

01h

23h

ADGAIN_3

01h

24h

ADGAIN_4

01h

25h

DITHER_CTRL

01h

26h

OFST_101h

27h

OFST_201h

28h

OFST_301h

29h

OFST_4

CLK enable control

Serializer setting

Startup control

SMASTER PWM

Other Setting
Status monitor

ADC Post-circuit control

104

CXD5247GF

Package Outline

CautionThe product of the WLCSP package should be used under light-shielded conditions.
Since the WLCSP package has a structure that a silocon wafer is exposed,
if light hits the wafer, the device may malfunction.

105

CXD5247GF

NoticePurpose of Use of the Products:
Customer shall use the Products with the utmost concern for safety, and shall not use the Products for any purpose that may endanger
life or physical wellbeing, or cause serious damage to property or the environment, either through normal use or malfunction.
Use of the Products for purposes other than those stipulated in this specification is strictly prohibited.
Furthermore, usage of the Products for military purposes is strictly prohibited at all times.

Safe Design: Customer is responsible for taking due care to ensure the product safety design of its products in which the Products areincorporated, such as by incorporating redundancy, anti-conflagration features, and features to prevent mis-operation, in order toprevent accidents resulting in injury, death, fire, or other social damage as a result of failure.

Product Information: The product specifications, circuit examples, and any and all other technical information and content contained in this specification,
as well as any other information and materials provided to Customer in connection with the Products (collectively, “Product
Information”) have been provided to Customer for reference purpose only, and the availability and disclosure of such Product
Information and its usage by Customer shall not be construed as giving any indication that Sony, its subsidiaries and/or its licensors
will license any right, including intellectual property rights in such Product Information by any implication or otherwise.
 Furthermore, even if circuit examples are included in this specification, they are provided only for reference purpose only, and are
merely examples of application. Sony, its Subsidiaries and/or their authorized representatives shall not be liable for any damage
arising out of their usage.

EXCLUSION OF WARRANTY ON THE PRODUCTS:
 UNLESS OTHERWISE NOTIFIED BY US IN WRITING, OTHERWISE AGREED BETWEEN THE CUSTOMER AND SONY,ITS SUBSIDIARIES OR ANY OF THEIR AUTHORIZED REPRESENTATIVES IN WRITING, OR TO THE EXTENTPERMITTED BY LAW, THE FOLLOWING TEMS AND CONDITIONS SHALL APPLY TO THE USAGE OF THE
PRODUCTS AND THE PRODUCT INFORMATION:
THE PRODUCTS AND THE PRODUCT INFORMATION ARE PROVIDED BY SONY, ITS SUBSIDIARIES AND/OR THEIRAUTHORIZED REPRESENTATIVES "AS IS" AND WITHOUT WARRANTY OF ANY KIND AND SONY, ITSSUBSIDIARIES AND/OR THEIR AUTHORIZED REPRESENTATIVES MAKE OR HAVE MADE NO REPRESENTATION OR
WARRANTY, EXPRESS OR IMPLIED, STATUTORY OR OTHERWISE, AND EXPRESSLY DISCLAIMS ANYREPRESENTATION OR WARRANTY (I) WITH RESPECT TO ACCURACY, RELIABILITY, VALUE, UTILITY OR SAFETY
OF THE PRODUCTS AND THE PRODUCT INFORMATION, OR THE ABILITY OF CUSTOMER TO MAKE USE THEREOF,(II) WITH RESPECT TO ANY IMPLEMENTATION OF THE PRODUCTS AND THE TECHNICAL INFORMATION; (III)WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE; OR (IV) THAT THE PRODUCTS
AND THE PRODUCT INFORMATION OR ANY IMPLEMENTATION THEREOF IS OR WILL BE FREE FROMINFRINGEMENT, MISAPPROPRIATION OR VIOLATION OF ANY INTELLECTUAL PROPERTY RIGHT OR ANY OTHERRIGHT OF ANY THIRD PARTY, AND ANY EQUIVALENTS OF ANY OF THE FOREGOING UNDER THE LAWS OF ANYJURISDICTION.
CUSTOMER HEREBY ACKNOWLEDGES AND AGREES THAT USE OF THE PRODUCTS AND THE PRODUCTINFORMATION IS AT CUSTOMER’S SOLE RISK AND THAT CUSTOMER IS RESPONSIBLE FOR THE USE OF THE
PRODUCTS AND THE PRODUCT INFORMATION, INCLUDING DEFENDING ANY INFRINGEMENT CLAIM MADE
AGAINST THE CUSTOMER IN RELATION WITH CUSOMTER’S USAGE OF THE PRODUCTS AND TECHNICALINFORMATION.
NO ORAL OR WRITTEN INFORMATION OR ADVICE GIVEN BY SONY, ITS SUBSIDIARIES OR THEIR AUTHORIZEDREPRESENTATIVES SHALL CREATE A WARRANTY, DUTY OR CONDITION OR IN ANY WAY INCREASE THE SCOPE
OF THIS WARRANTY.

106

CXD5247GF

LIMITATION OF LIABILITY: TO THE EXTENT PERMITTED BY LAW, SONY, ITS SUBSIDIARIES AND/OR THEIR AUTHORIZED REPRESENTATIVESSHALL NOT BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR BREACH OF ANY EXPRESSOR IMPLIED WARRANTY, BREACH OF CONTRACT, NEGLIGENCE, STRICT LIABILITY OR UNDER ANY OTHERLEGAL THEORY RELATED TO THE PRODUCTS AND PRODUCT INFORMATION, INCLUDING, BUT NOT LIMITED TO,
ANY DAMAGES ARISING OUT OF LOSS OF PROFITS, LOSS OF REVENUE, LOSS OF DATA, LOSS OF USE OF THE
PRODUCTS OR ANY ASSOCIATED HARDWARE, DOWN TIME AND USER’S TIME, EVEN IF ANY OF THEM HAVEBEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Compliance with Laws:
 Customer shall comply with all applicable laws, ordinances, rules and regulations in connection with the usage of the Products,
including the export control laws or regulations of various countries and shall be fully responsible for obtaining approvals inconnection with the export of the Products in accordance with such said laws, ordinances, rules and/or regulations.

Governing Law: This specification and the terms and conditions contained herein shall be governed by and construed in accordance with the laws ofJapan, without reference to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or
relating to this specification and the terms and conditions contained herein shall be submitted to the exclusive jurisdiction of theTokyo District Court in Japan as the court of first instance.

Notes:
 The product specifications, circuit examples, technical information and any and all other information and content relating to the
Products contained in this specification may be revised or updated by Sony at Sony’s sole discretion without prior notice to theCustomer and Customer shall abide by their latest versions. Such revisions or updates will be made available to Customer in a
way as Sony deems appropriate.
 Ensure that you have read and reviewed the notices contained in our delivery specification as well as this specification whenpurchasing and using the Products.

107