SuperH RISC Engine
SH-1/SH-2
Programming Manual

September 3, 1996
Hitachi America Ltd.

Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, thewhole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit according to thisdocument.
4. Circuitry and other examples described herein are meant merely to indicate thecharacteristics and performance of Hitachi’s semiconductor products. Hitachi assumes noresponsibility for any intellectual property claims or other problems that may result fromapplications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICALAPPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers ofHitachi’s products are requested to notify the relevant Hitachi sales offices when planning
to use the products in MEDICAL APPLICATIONS.

Introduction
The SuperH RISC engine family incorporates a RISC (Reduced Instruction Set Computer)type CPU. A basic instruction can be executed in one clock cycle, realizing highperformance operation. A built-in multiplier can execute multiplication and addition as
quickly as DSP.
The SuperH RISC engine has SH-I CPU, SH-2 CPU, and SH-3 CPU cores.
The SH-1 CPU, SH-2 CPU and SH-3 CPU have an instruction system with upward
compatibility at the binary level.

MMU support:
68 instructions

SH-3 CPU
SH-2 CPUSH-1 CPU
56 basic instructions

Operation instruction
enhancement:
62 instructions

Refer to the programming manual for the method of executing the instructions or for thearchitecture. You can also refer to this programming manual to know the operation of thepipe line, which is one of the features of the RISC CPU.
This programming manual describes in detail the instructions for the SH-1 CPU and SH-2
CPU instructions. For the SH-3 CPU, refer to the separate volume of SH-3 CPU programming
manual.
For the hardware, refer to individual hardware manuals for each unit.

HITACHI 1

Organization of This Manual
Table 1 describes how this manual is organized. Table 2 lists the relationships between theitems and the sections listed within this manual that cover those items.
Table 1

Manual Organization

Category

Section Title

Contents

Introduction

1. Features

CPU features

Architecture (1)2. Register
Configuration

Types and configuration of general registers,
control registers and system registers

3. Data Formats

Data formats for registers and memory

4. Instruction
Features

Instruction features, addressing modes, andinstruction formats

5. Instruction Sets

Summary of instructions by category and list inalphabetic order

Detailed information
on instructions

6. Instruction
Descriptions

Operation of each instruction in alphabeticalorder

Architecture (2)7. Pipeline Operation

Pipeline flow, and pipeline flows with operationfor each instruction

Instruction code

Appendixes:
Instruction CodeOperation code map

Introduction to
instructions

2 HITACHI

Table 2

Subjects and Corresponding Sections

Category

TopicIntroduction and CPU featuresfeatures

Section Title
1.

Features

Instruction features

4.1 RISC-Type Instruction Set

Pipelines

7.1 Basic Configuration of
Pipelines
7.2 Slot and Pipeline FlowArchitecture

Introduction to
instructions

List ofinstructions

Register configuration

2.

Register Configuration

Data formats

3.

Data Formats

Pipeline operation

7.

Pipeline Operation

Instruction features

4.

Instruction Features

Addressing modes

4.2 Addressing Modes

Instruction formats

4.3 Instruction Formats

Instruction sets

5.1 Instruction Set byClassification
5.2 Instruction Set in
Alphabetical OrderAppendix A.1 Instruction Set by
Addressing Mode
Appendix A.2 Instruction Set by
Instruction Format

Instruction code

Appendix A.3 Instruction Set in
Order byInstruction CodeAppendix A.4 Operation Code
Map

Detailed
information on
instructions

Detailed information on instruction
operation

6.

Instruction Description

Number of instruction execution states

7.3 Number of Instruction
Execution States

7.7 Instruction Pipeline
Operations

HITACHI 3

Functions Listed by CPU Type
This manual is common for both the SH-1 and SH-2 CPU. However, not all CPUs can use all
the instructions and functions. Table 3 lists the usable functions by CPU type.
Table 3Functions by CPU Type

Item
Instructions

SH-1 CPU

SH-2 CPU

BF/S

No

Yes

BRAF

No

Yes

BSRF

No

Yes

BT/S

No

Yes

DMULS.LNo

Yes

DMULU.L

No

Yes

DT

No

Yes

MAC.L

No

Yes

MAC.W*1 (MAC)*2

16 x 16 + 42 →42

16 x 16 + 64 → 64

MUL.L

No

Yes

All others

Yes

Yes

Executed in 1–
3* 3 states

Executed in 1–3* 3states

States for
16 x 16 → 32
multiplication operation (MULS.W,
MULU.W)*2

States for multiply andaccumulate operation

32 x 32 → 32 (MUL.L) No

Executed in 2–4 *3states

32 x 32 → 64
No
(DMULS.L, DMULU.L)

Executed in 2–4 *3states

16 x 16 + 42 → 42
(SH-1, MAC.W)

Executed in
3/(2)*3 statesNo

16 x 16 + 64 → 64
(SH-2, MAC.W)

No

Executed in states 3/(2)* 3

32 x 32 + 64 → 64
(MAC.L)No

Executed in 2–4 states
3/(2~4)*3

Notes: 1. MAC.W works differently on different LSIs.
2. MAC and MAC.W are the same. MULS is also the same as MULS.W and MULU thesame as MULU.W.
3. The normal minimum number of execution cycles (The number in parentheses in thenumber in contention with preceding/following instructions).

4 HITACHI

Contents
Section 1 Features .............................................................................................................................................. 14
Section 2 Register Configuration............................................................................................................ 16
2.1 General Registers................................................................................................................................................
2.2 Control Registers.................................................................................................................................................
2.3 System Registers.................................................................................................................................................
2.4 Initial Values of Registers.............................................................................................................................

16
16
19
19

Section 3 Data Formats.................................................................................................................................. 21
3.1 Data Format in Registers................................................................................................................................ 21
3.2 Data Format in Memory.................................................................................................................................. 21
3.3 Immediate Data Format................................................................................................................................... 22

Section 4 Instruction Features................................................................................................................... 23
4.1 RISC-Type Instruction Set.............................................................................................................................. 23
4.1.1 16-Bit Fixed Length.......................................................................................................................... 23
4.1.2 One Instruction/Cycle ...................................................................................................................... 23
4.1.3 Data Length.......................................................................................................................................... 23
4.1.4 Load-Store Architecture.................................................................................................................. 23
4.1.5 Delayed Branch Instructions......................................................................................................... 23
4.1.6 Multiplication/Accumulation Operation ................................................................................. 24
4.1.7 T Bit ......................................................................................................................................................... 24
4.1.8 Immediate Data.................................................................................................................................. 25
4.1.9 Absolute Address................................................................................................................................ 25
4.1.10 16-Bit/32-Bit Displacement........................................................................................................ 25
4.2 Addressing Modes............................................................................................................................................... 26
4.3 Instruction Format............................................................................................................................................... 29

Section 5 Instruction Set................................................................................................................................ 34
5.1 Instruction Set by Classification..................................................................................................................
5.1.1 Data Transfer Instructions ..............................................................................................................
5. 1.2 Arithmetic Instructions...................................................................................................................
5.1.3 Logic Operation Instructions.........................................................................................................
5.1.4 Shift Instructions.................................................................................................................................
5.1.5 Branch Instructions............................................................................................................................
5.1.6 System Control Instructions..........................................................................................................
5.2 Instruction Set in Alphabetical Order........................................................................................................

34
39
42
44
45
46
47
48

Section 6 Instruction Descriptions......................................................................................................... 57
6.1 Sample Description (Name): Classification.......................................................................................... 57
HITACHI 5

6.2 ADD (ADD Binary): Arithmetic Instruction.......................................................................................... 60
6.3 ADDC (ADD with Carry): Arithmetic Instruction.............................................................................. 61
6.4 ADDV (ADD with V Flag Overflow Check): Arithmetic Instruction........................................ 62
6.5 AND (AND Logical): Logic Operation Instruction ............................................................................ 63
6.6 BF (Branch if False): Branch Instruction............................................................................................... 65
6.7 BF/S (Branch if False with Delay Slot): Branch Instruction (SH-2 CPU) ............................ 66
6.8 BRA (Branch): Branch Instruction............................................................................................................ 68
6.9 BRAF (Branch Far): Branch Instruction (SH-2 CPU)..................................................................... 70
6.10 BSR (Branch to Subroutine): Branch Instruction............................................................................. 72
6.11 BSRF (Branch to Subroutine Far): Branch Instruction (SH-2 CPU)...................................... 74
6.12 BT (Branch if True): Branch Instruction.............................................................................................. 75
6.13 BT/S (Branch if True with Delay Slot): Branch Instruction (SH-2 CPU)............................ 76
6.14 CLRMAC (Clear MAC Register): System Control Instruction................................................. 78
6.15 CLRT (Clear T Bit): System Control Instruction............................................................................. 79
6.16 CMP/cond (Compare Conditionally): Arithmetic Instruction.................................................... 80
6.17 DIV0S (Divide Step 0 as Signed): Arithmetic Instruction........................................................... 84
6.18 DIV0U (Divide Step 0 as Unsigned): Arithmetic Instruction..................................................... 85
6.19 DIV1 (Divide Step 1): Arithmetic Instruction.................................................................................... 86
6.20 DMULS.L (Double-Length Multiply as Signed): Arithmetic Instruction (SH-2 CPU).. 91
6.21 DMULU.L (Double-Length Multiply as Unsigned): Arithmetic Instruction(SH-2 CPU)..................................................................................................................................................... 93
6.22 DT (Decrement and Test): Arithmetic Instruction (SH-2 CPU)............................................... 95
6.23 EXTS (Extend as Signed): Arithmetic Instruction........................................................................... 96
6.24 EXTU (Extend as Unsigned): Arithmetic Instruction..................................................................... 97
6.25 JMP (Jump): Branch Instruction............................................................................................................... 98
6.26 JSR (Jump to Subroutine): Branch Instruction.................................................................................. 99
6.27 LDC (Load to Control Register): System Control Instruction.................................................... 101
6.28 LDS (Load to System Register): System Control Instruction .................................................... 103
6.29 MAC.L (Multiply and Accumulate Long): Arithmetic Instruction (SH-2 CPU)............... 105
6.30 MAC (Multiply and Accumulate): Arithmetic Instruction (SH-1 CPU)............................... 108
6.31 MAC.W (Multiply and Accumulate Word): Arithmetic Instruction....................................... 109
6.32 MOV (Move Data): Data Transfer Instruction................................................................................... 112
6.33 MOV (Move Immediate Data): Data Transfer Instruction........................................................... 117
6.34 MOV (Move Peripheral Data): Data Transfer Instruction............................................................ 119
6.35 MOV (Move Structure Data): Data Transfer Instruction .............................................................. 122
6.36 MOVA (Move Effective Address): Data Transfer Instruction .................................................... 125
6.37 MOVT (Move T Bit): Data Transfer Instruction............................................................................... 126
6.38 MUL.L (Multiply Long): Arithmetic Instruction (SH-2 CPU)................................................... 127
6.39 MULS.W (Multiply as Signed Word): Arithmetic Instruction................................................... 128
6.40 MULU.W (Multiply as Unsigned Word): Arithmetic Instruction............................................. 129
6.41 NEG (Negate): Arithmetic Instruction................................................................................................... 130
6.42 NEGC (Negate with Carry): Arithmetic Instruction........................................................................ 131
6.43 NOP (No Operation): System Control Instruction............................................................................ 132

6 HITACHI

6.44 NOT (NOT—Logical Complement): Logic Operation Instruction........................................... 133
6.45 OR (OR Logical) Logic Operation Instruction................................................................................... 134
6.46 ROTCL (Rotate with Carry Left): Shift Instruction......................................................................... 136
6.47 ROTCR (Rotate with Carry Right): Shift Instruction..................................................................... 137
6.48 ROTL (Rotate Left): Shift Instruction.................................................................................................... 138
6.49 ROTR (Rotate Right): Shift Instruction................................................................................................ 139
6.50 RTE (Return from Exception): System Control Instruction ......................................................... 140
6.51 RTS (Return from Subroutine): Branch Instruction ......................................................................... 141
6.52 SETT (Set T Bit): System Control Instruction................................................................................... 143
6.53 SHAL (Shift Arithmetic Left): Shift Instruction................................................................................ 144
6.54 SHAR (Shift Arithmetic Right): Shift Instruction............................................................................ 145
6.55 SHLL (Shift Logical Left): Shift Instruction....................................................................................... 146
6.56 SHLLn (Shift Logical Left n Bits): Shift Instruction...................................................................... 147
6.57 SHLR (Shift Logical Right): Shift Instruction................................................................................... 149
6.58 SHLRn (Shift Logical Right n Bits): Shift Instruction................................................................... 150
6.59 SLEEP (Sleep): System Control Instruction....................................................................................... 152
6.60 STC (Store Control Register): System Control Instruction.......................................................... 153
6.61 STS (Store System Register): System Control Instruction .......................................................... 155
6.62 SUB (Subtract Binary): Arithmetic Instruction................................................................................. 157
6.63 SUBC (Subtract with Carry): Arithmetic Instruction...................................................................... 158
6.64 SUBV (Subtract with V Flag Underflow Check): Arithmetic Instruction............................. 159
6.65 SWAP (Swap Register Halves): Data Transfer Instruction......................................................... 160
6.66 TAS (Test and Set): Logic Operation Instruction............................................................................. 161
6.67 TRAPA (Trap Always): System Control Instruction....................................................................... 162
6.68 TST (Test Logical): Logic Operation Instruction............................................................................. 163
6.69 XOR (Exclusive OR Logical): Logic Operation Instruction........................................................ 165
6.70 XTRCT (Extract): Data Transfer Instruction....................................................................................... 167

Section 7 Pipeline Operation...................................................................................................................... 168
7.1 Basic Configuration of Pipelines................................................................................................................. 168
7.2 Slot and Pipeline Flow..................................................................................................................................... 169
7.2.1 Instruction Execution........................................................................................................................ 169
7.2.2 Slot Sharing.......................................................................................................................................... 169
7.2.3 Slot Length............................................................................................................................................ 170
7.3 Number of Instruction Execution States................................................................................................... 171
7.4 Contention Between Instruction Fetch (IF) and Memory Access (MA)................................. 172
7.4.1 Basic Operation When IF and MA are in Contention...................................................... 172
7.4.2 The Relationship Between IF and the Location of Instructions in On-Chip
ROM/RAM or On-Chip Memory ......................................................................................... 173
7.4.3 Relationship Between Position of Instructions Located in On-Chip
ROM/RAM or On-Chip Memory and Contention Between IF and MA............. 174
7.5 Effects of Memory Load Instructions on Pipelines ............................................................................. 175
7.6 Programming Guide ........................................................................................................................................... 176

HITACHI 7

7.7 Operation of Instruction Pipelines.............................................................................................................. 177
7.7.1 Data Transfer Instructions.............................................................................................................. 184
7.7.2 Arithmetic Instructions.................................................................................................................... 186
7.7.3 Logic Operation Instructions........................................................................................................ 237
7.7.4 Shift Instructions................................................................................................................................ 238
7.7.5 Branch Instructions ........................................................................................................................... 239
7.7.6 System Control Instructions.......................................................................................................... 242
7.7.7 Exception Processing....................................................................................................................... 248

Appendix A Instruction Code................................................................................................................... 251
A.1 Instruction Set by Addressing Mode......................................................................................................... 251
A.1.1 No Operand.......................................................................................................................................... 253
A.1.2 Direct Register Addressing.......................................................................................................... 254
A.1.3 Indirect Register Addressing....................................................................................................... 257
A.1.4 Post Increment Indirect Register Addressing...................................................................... 257
A.1.5 Pre Decrement Indirect Register Addressing ...................................................................... 258
A.1.6 Indirect Register Addressing with Displacement .............................................................. 259
A.1.7 Indirect Indexed Register Addressing..................................................................................... 259
A.1.8 Indirect GBR Addressing with Displacement..................................................................... 260
A.1.9 Indirect Indexed GBR Addressing............................................................................................ 260
A.1.10 PC Relative Addressing with Displacement..................................................................... 260
A.1.11 PC Relative Addressing with Rm.......................................................................................... 261
A.1.12 PC Relative Addressing.............................................................................................................. 261
A.1.13 Immediate.......................................................................................................................................... 262
A.2 Instruction Sets by Instruction Format..................................................................................................... 262
A.2.1 0 Format................................................................................................................................................ 264
A.2.2 n Format................................................................................................................................................ 265
A.2.3 m Format .............................................................................................................................................. 267
A.2.4 nm Format............................................................................................................................................ 269
A.2.5 md Format............................................................................................................................................ 272
A.2.6 nd4 Format........................................................................................................................................... 272
A.2.7 nmd Format ......................................................................................................................................... 272
A.2.8 d Format................................................................................................................................................ 273
A.2.9 d12 Format........................................................................................................................................... 274
A.2.10 nd8 Format ........................................................................................................................................ 274
A.2.11 i Format .............................................................................................................................................. 274
A.2.12 ni Format............................................................................................................................................ 275
A.3 Instruction Set in Order by Instruction Code ........................................................................................ 276
A.4 Operation Code Map........................................................................................................................................ 284
Appendix B Pipeline Operation and Contention......................................................................................... 288

FiguresFigure 2.1

8 HITACHI

General Registers............................................................................................................................. 16

Figure 2.2 Control Registers............................................................................................................................... 18
Figure 2.3 System Registers............................................................................................................................... 19
Figure 3.1 Longword Operand............................................................................................................................ 21
Figure 3.2 Byte, Word, and Longword Alignment................................................................................... 21
Figure 3.3 Byte, Word, and Longword Alignment in little endian format (SH7604 only)... 22
Figure 6.1 Using R0 after MOV........................................................................................................................ 119
Figure 6.2 Using R0 after MOV........................................................................................................................ 122
Figure 6.3 Rotate with Carry Left.................................................................................................................... 136
Figure 6.4 Rotate with Carry Right................................................................................................................. 137
Figure 6.5 Rotate Left ........................................................................................................................................... 138
Figure 6.6 Rotate Right ........................................................................................................................................ 139
Figure 6.7 Shift Arithmetic Left ....................................................................................................................... 144
Figure 6.8 Shift Arithmetic Right.................................................................................................................... 145
Figure 6.9 Shift Logical Left.............................................................................................................................. 146
Figure 6.10 Shift Logical Left n Bits............................................................................................................. 147
Figure 6.11 Shift Logical Right........................................................................................................................ 149
Figure 6.12 Shift Logical Right n Bits.......................................................................................................... 150
Figure 6.13 Extract.................................................................................................................................................. 167
Figure 7.1 Basic Structure of Pipeline Flow.............................................................................................. 168
Figure 7.2 Impossible Pipeline Flow 1.......................................................................................................... 169
Figure 7.3 Impossible Pipeline Flow 2.......................................................................................................... 169
Figure 7.4 Slots Requiring Multiple Cycles............................................................................................... 170
Figure 7.5 How Instruction Execution States Are Counted................................................................. 171
Figure 7.6 Operation When IF and MA Are in Contention ................................................................. 172
Figure 7.7 Relationship Between IF and Location of Instructions in On-Chip Memory....... 174
Figure 7.8 Relationship Between the Location of Instructions in On-Chip Memory andContention Between IF and MA.............................................................................................. 175
Figure 7.9 Effects of Memory Load Instructions on the Pipeline ..................................................... 176
Figure 7.10 Register-Register Transfer Instruction Pipeline............................................................... 184
Figure 7.11 Memory Load Instruction Pipeline......................................................................................... 185
Figure 7.12 Memory Store Instruction Pipeline ........................................................................................ 186
Figure 7.13 Pipeline for Arithmetic Instructions between Registers Except
Multiplication Instructions.......................................................................................................... 187
Figure 7.14 Multiply/Accumulate Instruction Pipeline......................................................................... 188
Figure 7.15 Unrelated Instructions between MAC.W Instructions................................................... 189
Figure 7.16 Consecutive MAC.Ws without Misalignment.................................................................. 189
Figure 7.17 MA and IF Contention................................................................................................................. 190
Figure 7.18 MULS.W Instruction Immediately After a MAC.W Instruction............................... 191
Figure 7.19 STS (Register) Instruction Immediately After a MAC.W Instruction................... 192
Figure 7.20 STS.L (Memory) Instruction Immediately After a MAC.W Instruction............... 193
Figure 7.21 LDS (Register) Instruction Immediately After a MAC.W Instruction .................. 194
Figure 7.22 LDS.L (Memory) Instruction Immediately After a MAC.W Instruction .............. 195
Figure 7.23 Multiply/Accumulate Instruction Pipeline ......................................................................... 196

HITACHI 9

Figure 7.24 MAC.W Instruction That Immediately Follows Another MAC.W instruction.. 197
Figure 7.25 Consecutive MAC.Ws with Misalignment........................................................................ 197
Figure 7.26 MA and IF Contention................................................................................................................. 198
Figure 7.27 MAC.L Instructions Immediately After a MAC.W Instruction................................. 198
Figure 7.28 MULS.W Instruction Immediately After a MAC.W Instruction.............................. 199
Figure 7.29 DMULS.L Instructions Immediately After a MAC.W Instruction........................... 199
Figure 7.30 STS (Register) Instruction Immediately After a MAC.W Instruction.................. 200
Figure 7.31 STS.L (Memory) Instruction Immediately After a MAC.W Instruction.............. 201
Figure 7.32 LDS (Register) Instruction Immediately After a MAC.W Instruction.................. 202
Figure 7.33 LDS.L (Memory) Instruction Immediately After a MAC.W Instruction.............. 203
Figure 7.34 Multiply/Accumulate Instruction Pipeline......................................................................... 204
Figure 7.35 MAC.L Instruction Immediately After Another MAC.L Instruction....................... 205
Figure 7.36 Consecutive MAC.Ls with Misalignment .......................................................................... 205
Figure 7.37 MA and IF Contention................................................................................................................. 206
Figure 7.38 MAC.W Instruction Immediately After a MAC.L Instruction................................... 207
Figure 7.39 DMULS.L Instruction Immediately After a MAC.L Instruction ................................ 208
Figure 7.40 MULS.W Instruction Immediately After a MAC.L Instruction................................ 209
Figure 7.41 STS (Register) Instruction Immediately After a MAC.L Instruction .................... 210
Figure 7.42 STS.L (Memory) Instruction Immediately After a MAC.L Instruction ................ 211
Figure 7.43 LDS (Register) Instruction Immediately After a MAC.L Instruction.................... 212
Figure 7.44 LDS.L (Memory) Instruction Immediately After a MAC.L Instruction................ 213
Figure 7.45 Multiplication Instruction Pipeline........................................................................................ 214
Figure 7.46 MAC.W Instruction Immediately After a MULS.W Instruction.............................. 215
Figure 7.47 MULS.W Instruction Immediately After Another MULS.W Instruction.............. 216
Figure 7.48 MULS.W Instruction Immediately After Another MULS.W Instruction (IFand MA Contention)...................................................................................................................... 217
Figure 7.49 STS (Register) Instruction Immediately After a MULS.W Instruction................ 218
Figure 7.50 STS.L (Memory) Instruction Immediately After a MULS.W Instruction............ 219
Figure 7.51 LDS (Register) Instruction Immediately After a MULS.W Instruction ............... 220
Figure 7.52 LDS.L (Memory) Instruction Immediately After a MULS.W Instruction ........... 221
Figure 7.53 Multiplication Instruction Pipeline........................................................................................ 222
Figure 7.54 MAC.W Instruction Immediately After a MULS.W Instruction.............................. 223
Figure 7.55 MAC.L Instruction Immediately After a MULS.W Instruction................................ 223
Figure 7.56 MULS.W Instruction Immediately After Another MULS.W Instruction.............. 224
Figure 7.57 MULS.W Instruction Immediately After Another MULS.W Instruction (IFand MA contention)....................................................................................................................... 224
Figure 7.58 DMULS.L Instruction Immediately After a MULS.W Instruction.......................... 225
Figure 7.59 STS (Register) Instruction Immediately After a MULS.W Instruction................ 226
Figure 7.60 STS.L (Memory) Instruction Immediately After a MULS.W Instruction............ 227
Figure 7.61 LDS (Register) Instruction Immediately After a MULS.W Instruction ............... 228
Figure 7.62 LDS.L (Memory) Instruction Immediately After a MULS.W Instruction ........... 229
Figure 7.63 Multiplication Instruction Pipeline........................................................................................ 229
Figure 7.64 MAC.L Instruction Immediately After a DMULS.L Instruction............................... 231

10 HITACHIFigure 7.65 MAC.W Instruction Immediately After a DMULS.L Instruction............................. 231
Figure 7.66 DMULS.L Instruction Immediately After Another DMULS.L Instruction........... 232
Figure 7.67 DMULS.L Instruction Immediately After Another DMULS.L Instruction (IFand MA Contention)...................................................................................................................... 233
Figure 7.68 MULS.W Instruction Immediately After a DMULS.L Instruction........................... 233
Figure 7.69 MULS.W Instruction Immediately After a DMULS.L Instruction (IF and
MA Contention) ............................................................................................................................... 234
Figure 7.70 STS (Register) Instruction Immediately After a DMULS.L Instruction............... 234
Figure 7.71 STS.L (Memory) Instruction Immediately After a DMULS.L Instruction........... 235
Figure 7.72 LDS (Register) Instruction Immediately After a DMULS.L Instruction.............. 236
Figure 7.73 LDS.L (Memory) Instruction Immediately After a DMULS.L Instruction.......... 237
Figure 7.74 Register-Register Logic Operation Instruction Pipeline .............................................. 237
Figure 7.75 Memory Logic Operation Instruction Pipeline ................................................................. 238
Figure 7.76 TAS Instruction Pipeline............................................................................................................. 238
Figure 7.77 Shift Instruction Pipeline............................................................................................................ 239
Figure 7.78 Branch Instruction When Condition is Satisfied ............................................................. 240
Figure 7.79 Branch Instruction When Condition is Not Satisfied .................................................... 240
Figure 7.80 Branch Instruction When Condition is Satisfied ............................................................. 241
Figure 7.81 Branch Instruction When Condition is Not Satisfied .................................................... 241
Figure 7.82 Unconditional Branch Instruction Pipeline........................................................................ 242
Figure 7.83 System Control ALU Instruction Pipeline.......................................................................... 243
Figure 7.84 LDC.L Instruction Pipeline........................................................................................................ 243
Figure 7.85 STC.L Instruction Pipeline......................................................................................................... 243
Figure 7.86 LDS.L Instruction (PR) Pipeline............................................................................................. 244
Figure 7.87 STS.L Instruction (PR) Pipeline............................................................................................. 244
Figure 7.88 Register → MAC Transfer Instruction Pipeline............................................................... 245
Figure 7.89 Memory → MAC Transfer Instruction Pipeline............................................................... 245
Figure 7.90 MAC → Register Transfer Instruction Pipeline............................................................... 246
Figure 7.91 MAC → Memory Transfer Instruction Pipeline............................................................... 246
Figure 7.92 RTE Instruction Pipeline............................................................................................................. 247
Figure 7.93 TRAP Instruction Pipeline......................................................................................................... 247
Figure 7.94 SLEEP Instruction Pipeline....................................................................................................... 248
Figure 7.95 Interrupt Exception Processing Pipeline.............................................................................. 248
Figure 7.96 Address Error Exception Processing Pipeline................................................................... 249
Figure 7.97 Illegal Instruction Exception Processing Pipeline .......................................................... 249

TablesTable 1 Manual Organization............................................................................................................................... 2
Table 2 Subjects and Corresponding Sections............................................................................................. 3
Table 3 Functions by CPU Type......................................................................................................................... 4
Table 1.1 SH-1 and SH-2 CPU Features........................................................................................................ 15
Table 2.1 Initial Values of Registers................................................................................................................. 20
Table 4.1 Sign Extension of Word Data.......................................................................................................... 23

HITACHI 11

Table 4.2 Delayed Branch Instructions............................................................................................................ 24
Table 4.3 T Bit............................................................................................................................................................ 24
Table 4.4 Immediate Data Accessing.............................................................................................................. 25
Table 4.5 Absolute Address................................................................................................................................... 25
Table 4.6 Displacement Accessing................................................................................................................... 26
Table 4.7 Addressing Modes and Effective Addresses............................................................................. 26
Table 4.8 Instruction Formats............................................................................................................................... 30
Table 5.1 Classification of Instructions........................................................................................................... 34
Table 5.2 Instruction Code Format .................................................................................................................... 38
Table 5.3 Data Transfer Instructions ................................................................................................................. 40
Table 5.4 Arithmetic Instructions....................................................................................................................... 42
Table 5.5 Logic Operation Instructions............................................................................................................ 44
Table 5.5 Logic Operation Instructions (cont)............................................................................................. 45
Table 5.6 Shift Instructions.................................................................................................................................... 45
Table 5.7 Branch Instructions............................................................................................................................... 46
Table 5.8 System Control Instructions............................................................................................................. 47
Table 5.9 Instruction Set......................................................................................................................................... 49
Table 6.1 CMP Mnemonics .................................................................................................................................. 81
Table 7.1 Format for the Number of Stages and Execution States for Instructions.................... 177
Table 7.2 Number of Instruction Stages and Execution States ............................................................ 177
Table A.1 Instruction Set by Addressing Mode ........................................................................................... 252
Table A.2 No Operand............................................................................................................................................. 253
Table A.3 Destination Operand Only................................................................................................................ 254
Table A.4 Source and Destination Operand.................................................................................................. 254
Table A.5 Load and Store with Control Register or System Register.............................................. 256
Table A.6 Destination Operand Only................................................................................................................ 257
Table A.7 Data Transfer with Direct Register Addressing..................................................................... 257
Table A.8 Multiply/Accumulate Operation ................................................................................................... 257
Table A.9 Data Transfer from Direct Register Addressing..................................................................... 258
Table A.10 Load to Control Register or System Register...................................................................... 258
Table A.11 Data Transfer from Direct Register Addressing .................................................................. 258
Table A.12 Store from Control Register or System Register ................................................................ 259
Table A.13 Indirect Register Addressing with Displacement ............................................................... 259
Table A.14 Indirect Indexed Register Addressing ...................................................................................... 259
Table A.15 Indirect GBR Addressing with Displacement...................................................................... 260
Table A.16 Indirect Indexed GBR Addressing............................................................................................. 260
Table A.17 PC Relative Addressing with Displacement........................................................................ 260
Table A.18 PC Relative Addressing with Rm.............................................................................................. 261
Table A.19 PC Relative Addressing................................................................................................................. 261
Table A.20 Arithmetic Logical Operation with Direct Register Addressing................................. 262
Table A.21 Specify Exception Processing Vector...................................................................................... 262
Table A.22 Instruction Sets by Format............................................................................................................ 263
Table A.23 0 Format................................................................................................................................................. 264

12 HITACHITable A.24 Direct Register Addressing............................................................................................................ 265
Table A.25 Direct Register Addressing (Store with Control and System Registers)................. 265
Table A.26 Indirect Register Addressing......................................................................................................... 266
Table A.27 Pre Decrement Indirect Register................................................................................................ 266
Table A.28 Direct Register Addressing (Load with Control and System Registers) ................. 267
Table A.29 Indirect Register................................................................................................................................. 267
Table A.30 Post Increment Indirect Register................................................................................................ 267
Table A.31 PC Relative Addressing with Rm.............................................................................................. 268
Table A.32 Direct Register Addressing............................................................................................................ 269
Table A.33 Indirect Register Addressing......................................................................................................... 271
Table A.34 Post Increment Indirect Register (Multiply/Accumulate Operation)........................ 271
Table A.35 Post Increment Indirect Register................................................................................................ 271
Table A.36 Pre Decrement Indirect Register................................................................................................ 271
Table A.37 Indirect Indexed Register............................................................................................................... 272
Table A.38 md Format............................................................................................................................................. 272
Table A.39 nd4 Format ............................................................................................................................................ 272
Table A.40 nmd Format........................................................................................................................................... 272
Table A.41 Indirect GBR with Displacement............................................................................................... 273
Table A.42 PC Relative with Displacement................................................................................................. 273
Table A.43 PC Relative Addressing.................................................................................................................. 273
Table A.44 d12 Format ............................................................................................................................................ 274
Table A.45 nd8 Format ............................................................................................................................................ 274
Table A.46 Indirect Indexed GBR Addressing.............................................................................................. 274
Table A.47 Immediate Addressing (Arithmetic Logical Operation with Direct Register)...... 275
Table A.48 Immediate Addressing (Specify Exception Processing Vector).................................. 275
Table A.49 ni Format................................................................................................................................................ 275
Table A.50 Instruction Set by Instruction Code........................................................................................... 276
Table A.51 Operation Code Map ........................................................................................................................ 284
Table B.1 Instructions and Their Contention Patterns .............................................................................. 289

HITACHI 13

Section 1 Features
The SH-1 and SH-2 CPU have RISC-type instruction sets. Basic instructions are executed in
one clock cycle, which dramatically improves instruction execution speed. The CPU also has
an internal 32-bit architecture for enhanced data processing ability. Table 1.1 lists the SH-1
and SH-2 CPU features.

14 HITACHITable 1.1

SH-1 and SH-2 CPU Features

Item

FeatureArchitecture•

Original Hitachi architecture•

32-bit internal data paths•

Sixteen 32-bit general registers•

Three 32-bit control registers•

Four 32-bit system registers•

Instruction length: 16-bit fixed length for improved code
efficiency•

Load-store architecture (basic arithmetic and logic operations are
executed between registers)•

Delayed branch system used for reduced pipeline disruption

General-register machine

Instruction set•

Instruction set optimized for C language

Instruction executiontime•

One instruction/cycle for basic instructions

Address space•

Architecture makes 4 Gbytes available

On-chip multiplier(SH-1 CPU)•

Multiplication operations (16 bits × 16 bits → 32 bits) executedin 1 to 3 cycles, and multiplication/accumulation operations (16bits × 16 bits + 42 bits → 42 bits) executed in 3/(2)* cycles

On-chip multiplier(SH-2 CPU)•

Multiplication operations executed in 1 to 2 cycles (16 bits × 16
bits → 32 bits) or 2 to 4 cycles (32 bits × 32 bits → 64 bits), andmultiplication/accumulation operations executed in 3/(2)* cycles(16 bits × 16 bits + 64 bits → 64 bits) or 3/(2 to 4)* cycles (32bits × 32 bits + 64 bits → 64 bits)

Pipeline•

Five-stage pipeline

Processing states•

Reset state•

Exception processing state•

Program execution state•Power-down state•

Bus release state•

Sleep mode•Standby mode

Power-down states

Note: The normal minimum number of execution cycles (The number in parentheses in thenumber in contention with preceding/following instructions).

HITACHI 15

Section 2 Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers andfour 32-bit system registers.

2.1

General Registers

There are 16 general registers (Rn) numbered R0–R15, which are 32 bits in length (figure2.1). General registers are used for data processing and address calculation. R0 is also used as
an index register. Several instructions use R0 as a fixed source or destination register. R15 isused as the hardware stack pointer (SP). Saving and recovering the status register (SR) andprogram counter (PC) in exception processing is accomplished by referencing the stack using
R15.
31

0
1. R0 functions as an index register in theindirect indexed register addressing
mode and indirect indexed GBR
addressing mode. In some instructions,
R0 functions as a fixed source registeror destination register.

R0 *1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13

R14
R15, SP (hardware stack pointer) *2 2. R15 functions as a hardware stack
pointer (SP) during exception
processing.

Figure 2.1

2.2

General Registers

Control Registers

The 32-bit control registers consist of the 32-bit status register (SR), global base register(GBR), and vector base register (VBR) (figure 2.2). The status register indicates processing
states. The global base register functions as a base address for the indirect GBR addressing

16 HITACHImode to transfer data to the registers of on-chip peripheral modules. The vector base registerfunctions as the base address of the exception processing vector area (including interrupts).

HITACHI 17

31
SR

9 8 7 6 5 4 32 1 0
MQ I3 I2 I1 I0

ST

SR: Status register
T bit: The MOVT, CMP/cond, TAS, TST,BT (BT/S), BF (BF/S), SETT, and CLRT
instructions use the T bit to indicate
true (1) or false (0). The ADDV/C,
SUBV/C, DIV0U/S, DIV1, NEGC,
SHAR/L, SHLR/L, ROTR/L, and
ROTCR/L instructions also use bit T
to indicate carry/borrow or overflow/
underflow
S bit: Used by the multiply/accumulate
instruction.
Reserved bits: Always reads as 0, and should
always be written with 0.
Bits I3–I0: Interrupt mask bits.
M and Q bits: Used by the DIV0U/S and
DIV1 instructions.
Global base register (GBR):
0 Indicates the base address of the indirect
GBR addressing mode. The indirect GBR
addressing mode is used in data transfer
for on-chip peripheral module registerareas and in logic operations.

31
GBR

31

0 Vector base register (VBR):
Indicates the base address of the exception
processing vector area.

VBR

SW J04

Figure 2.2

18 HITACHI

Control Registers

2.3

System Registers

The system registers consist of four 32-bit registers: high and low multiply and accumulate
registers (MACH and MACL), the procedure register (PR), and the program counter (PC)(figure 2.3). The multiply and accumulate registers store the results of multiply andaccumulate operations. The procedure register stores the return address from the subroutine
procedure. The program counter stores program addresses to control the flow of the processing.
31(SH-1 CPU)9(sign extended)

0
MACH

MACL
31
(SH-2 CPU)

0
MACH
MACL
0

31
PR

0

31
PC

Figure 2.3

2.4

Multiply and accumulate (MAC)
registers high and low (MACH/L):Store the results of multiply andaccumulate operations. In theSH-1 CPU, MACH is sign-extended
to 32 bits when read because only
the lowest 10 bits are valid. In theSH-2 CPU, all 32 bits of MACH are
valid.
Procedure register (PR): Stores a
return address from a subroutine
procedure.
Program counter (PC): Indicates the
fourth byte (second instruction) after
the current instruction.

System Registers

Initial Values of Registers

Table 2.1 lists the values of the registers after reset.

HITACHI 19

Table 2.1

Initial Values of Registers

Classification

Register

Initial Value

General register

R0–R14

Undefined

R15 (SP)

Value of the stack pointer in the vector address table

SR

Bits I3–I0 are 1111 (H'F), reserved bits are 0, andother bits are undefined

GBR

Undefined

VBR

H'00000000

MACH, MACL, PR

Undefined

PC

Value of the program counter in the vector address
table

Control register

System register

20 HITACHISection 3 Data Formats
3.1

Data Format in Registers

Register operands are always longwords (32 bits) (figure 3.1). When the memory operand is
only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a
register.
31

0
Longword

Figure 3.1

3.2

Longword OperandData Format in Memory

Memory data formats are classified into bytes, words, and longwords. Byte data can beaccessed from any address, but an address error will occur if you try to access word data
starting from an address other than 2n or longword data starting from an address other than 4n.
In such cases, the data accessed cannot be guaranteed (figure 3.2). The hardware stack area,
which is referred to by the hardware stack pointer (SP, R15), uses only longword data startingfrom address 4n because this area holds the program counter and status register. See the SH
Hardware Manual for more information on address errors.
Address m + 1 Address m + 3

Address 2nAddress 4n

Address m
23
31

Address m + 2
7
15
0

Byte

Byte

Byte

Word

Byte

Word
Longword
Big endian

Figure 3.2

Byte, Word, and Longword Alignment

SH7604 has a function that allows access of CS2 space (area 2) in little endian format,
which enables memory to be shared with processors that access memory in little endian
format (figure 3.3). Byte data is arranged differently for little endian and the usual big
endian.

HITACHI 21

Address m + 2

Address m

Address m + 3 Address m + 1
23
7
15
0
31
Byte

Byte

Byte

Word

Byte

Word
Longword

Address 2nAddress 4n

Little endian*Note : Only CS2 space of SH7604 can be set.

Figure 3.3

3.3

Byte, Word, and Longword Alignment in little endian format (SH7604 only)

Immediate Data Format

Byte immediate data is located in an instruction code. Immediate data accessed by the
MOV, ADD, and CMP/EQ instructions is sign-extended and calculated with registers andlongword data. Immediate data accessed by the TST, AND, OR, and XOR instructions iszero-extended and calculated with longword data. Consequently, AND instructions withimmediate data always clear the upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code. Rather, it is stored ina memory table. The memory table is accessed by an immediate data transfer instruction(MOV) using the PC relative addressing mode with displacement. Specific examples are
given in section 4.1.8, Immediate Data.

22 HITACHISection 4 Instruction Features
4.1

RISC-Type Instruction Set

All instructions are RISC type. Their features are detailed in this section.
4.1.1

16-Bit Fixed Length

All instructions are 16 bits long, increasing program coding efficiency.
4.1.2

One Instruction/Cycle

Basic instructions can be executed in one cycle using the pipeline system. Instructions are
executed in 50 ns at 20 MHz, in 35 ns at 28.7MHz.
4.1.3

Data Length

Longword is the standard data length for all operations. Memory can be accessed in bytes,
words, or longwords. Byte or word data accessed from memory is sign-extended andcalculated with longword data (table 4.1). Immediate data is sign-extended for arithmetic
operations or zero-extended for logic operations. It also is calculated with longword data.
Table 4.1

Sign Extension of Word Data

SH-1/SH-2 CPU

Description

Example for Other CPU

MOV.W@(disp,PC),R1

ADD.W

ADD

R1,R0

Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.

.........
.DATA.W

H'1234#H'1234,R0

Note: The address of the immediate data is accessed by @(disp, PC).

4.1.4

Load-Store Architecture

Basic operations are executed between registers. For operations that involve memory access,data is loaded to the registers and executed (load-store architecture). Instructions such as
AND that manipulate bits, however, are executed directly in memory.
4.1.5

Delayed Branch Instructions

Unconditional branch instructions are delayed. Pipeline disruption during branching is reducedby first executing the instruction that follows the branch instruction, and then branching (table
4.2). With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order of delayedbranch instruction, then delay slot instruction. For example, even if the register in which the
HITACHI 23

branch destination address has been loaded is changed by the delay slot instruction, thebranch will still be made using the value of the register prior to the change as the branch
destination address.
Table 4.2

Delayed Branch Instructions

SH-1/SH-2 CPU

Description

Example for Other CPU

BRA

TRGET

ADD.W

R1,R0

ADD

R1,R0

Executes an ADD before
branching to TRGET.

BRA

TRGET

4.1.6

Multiplication/Accumulation Operation

SH-1 CPU: 16bit × 16bit → 32-bit multiplication operations are executed in one to threecycles. 16bit × 16bit + 42bit → 42-bit multiplication/accumulation operations are executed in
two to three cycles.
SH-2 CPU: 16bit × 16bit → 32-bit multiplication operations are executed in one to twocycles. 16bit × 16bit + 64bit → 64-bit multiplication/accumulation operations are executed in
two to three cycles. 32bit × 32bit → 64-bit multiplication and 32bit × 32bit + 64bit → 64-bit
multiplication/accumulation operations are executed in two to four cycles.
4.1.7

T Bit

The T bit in the status register changes according to the result of the comparison, and in turnis the condition (true/false) that determines if the program will branch (table 4.3). The
number of instructions after T bit in the status register is kept to a minimum to improve theprocessing speed.
Table 4.3

T Bit

SH-1/SH-2 CPU

Description

Example for Other CPU

CMP/GE

R1,R0

CMP.W

R1,R0

BT

TRGET0BGE

TRGET0BF

TRGET1

T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.

BLT

TRGET1ADD#–1,R0

SUB.W

#1,R0

CMP/EQ#0,R0

T bit is not changed by ADD. T
bit is set when R0 = 0. The
program branches if R0 = 0.

BEQ

TRGET

BT

TRGET

24 HITACHI

4.1.8

Immediate Data

Byte immediate data is located in instruction code. Word or longword immediate data is not
input via instruction codes but is stored in a memory table. The memory table is accessed by
an immediate data transfer instruction (MOV) using the PC relative addressing mode withdisplacement (table 4.4).
Table 4.4

Immediate Data Accessing

Classification

SH-1/SH-2 CPU

Example for Other CPU

8-bit immediate

MOV#H'12,R0

MOV.B#H'12,R016-bit immediate

MOV.W@(disp,PC),R0

MOV.W#H'1234,R0

MOV.L#H'12345678,R0.................

32-bit immediate.DATA.W

H'1234

MOV.L@(disp,PC),R0.................
.DATA.L

H'12345678

Note: The address of the immediate data is accessed by @(disp, PC).

4.1.9

Absolute Address

When data is accessed by absolute address, the value already in the absolute address isplaced in the memory table. Loading the immediate data when the instruction is executedtransfers that value to the register and the data is accessed in the indirect register addressing
mode.
Table 4.5

Absolute Address

Classification

SH-1/SH-2 CPU

Example for Other CPU

Absolute address

MOV.L@(disp,PC),R1

MOV.B

MOV.B

@R1,R0@H'12345678,R0..................
.DATA.L

4.1.10H'12345678

16-Bit/32-Bit Displacement

When data is accessed by 16-bit or 32-bit displacement, the pre-existing displacement value
is placed in the memory table. Loading the immediate data when the instruction is executedtransfers that value to the register and the data is accessed in the indirect indexed register
addressing mode.

HITACHI 25

Table 4.6

Displacement Accessing

Classification

SH-1/SH-2 CPU

Example for Other CPU

16-bit displacement

MOV.W@(disp,PC),R0

MOV.W

MOV.W

@(R0,R1),R2@(H'1234,R1),R2..................
.DATA.W

4.2

H'1234Addressing Modes

Addressing modes and effective address calculation are described in table 4.7.
Table 4.7

Addressing Modes and Effective Addresses

Addressin
g ModeInstruction
FormatDirectregisteraddressing

Effective Addresses Calculation

FormulaRn

The effective address is register Rn. (The operandis the contents of register Rn.)—

Indirect
registeraddressing@Rn

The effective address is the content of register Rn.

Rn

Postincrement
indirect
registeraddressing

@Rn +

Rn

Rn

The effective address is the content of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, or 4 for alongword operation.
Rn

Rn
Rn + 1/2/4@–Rn

Byte: Rn + 1→ Rn

Longword:
Rn + 4 → Rn

The effective address is the value obtained by
Byte: Rn – 1
subtracting a constant from Rn. 1 is subtracted for a → Rn
byte operation, 2 for a word operation, or 4 for a
Word: Rn – 2
longword operation.
→ Rn
Rn
Rn – 1/2/4
1/2/4

26 HITACHI(After the
instruction is
executed)

Word: Rn + 2
→ Rn

+

1/2/4
Predecrement
indirect
registeraddressing

Rn–

Rn – 1/2/4

Longword:
Rn – 4 → Rn
(Instruction
executed
with Rn after
calculation)

Table 4.7

Addressing Modes and Effective Addresses (cont)

Addressin
g ModeInstruction
FormatIndirect
registeraddressing
withdisplacement@(disp:4,
Rn)

Effective Addresses Calculation
The effective address is Rn plus a 4-bit
displacement (disp). The value of disp is zeroextended, and remains the same for a byte
operation, is doubled for a word operation, or isquadrupled for a longword operation.
Rndisp(zero-extended)+Rn+ disp × 1/2/4

FormulaByte: Rn +disp
Word: Rn +disp × 2
Longword:
Rn + disp × 4

×1/2/4
Indirectindexedregisteraddressing@(R0, Rn)

The effective address is the Rn value plus R0.

Rn + R0

Rn+

Rn + R0

R0
Indirect
GBR
addressing
withdisplacement@(disp:8,
GBR)

The effective address is the GBR value plus an 8bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte
operation, is doubled for a word operation, or isquadrupled for a longword operation.
GBR
disp(zero-extended)+

GBR+ disp × 1/2/4

Byte: GBR +disp
Word: GBR +disp × 2
Longword:
GBR + disp ×
4

×
1/2/4
IndirectindexedGBR
addressing

@(R0,
GBR)

The effective address is the GBR value plus R0.

GBR + R0

GBR+

GBR + R0R0

HITACHI 27

Table 4.7

Addressing Modes and Effective Addresses (cont)

Addressin
g ModeInstruction
FormatPC relative
addressing
withdisplacement@(disp:8,
PC)

Effective Addresses Calculation

FormulaThe effective address is the PC value plus an 8-bit
displacement (disp). The value of disp is zeroextended, and disp is doubled for a word
operation, or is quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC are masked.

Word: PC +disp × 2
Longword:PC &H'FFFFFFFC+ disp × 4

PC(for longword)&
H'FFFFFFFC

PC + disp × 2
or
PC&H'FFFFFFFC+ disp × 4+

disp(zero-extended)x
2/4
PC relative
addressing

disp:8The effective address is the PC value signextended with an 8-bit displacement (disp),
doubled, and added to the PC.

PC + disp ×
2

PC
disp
(sign-extended)+

PC + disp × 2

×2
disp:12The effective address is the PC value signextended with a 12-bit displacement (disp),
doubled, and added to the PC.
PC
disp(sign-extended)+×2

28 HITACHI

PC + disp × 2

PC + disp ×2

Table 4.7

Addressing Modes and Effective Addresses (cont)

Addressin
g ModeInstruction
FormatEffective Addresses Calculation

FormulaPC relative
addressing(cont)Rn

The effective address is the register PC plus Rn.

PC + RnPC+

PC + R0

R0
Immediate
addressing

4.3#imm:8

The 8-bit immediate data (imm) for the TST, AND,OR, and XOR instructions are zero-extended.

—#imm:8

The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions are sign-extended.

—#imm:8

Immediate data (imm) for the TRAPA instruction iszero-extended and is quadrupled.

—

Instruction Format

The instruction format table, table 4.8, refers to the source operand and the destination
operand. The meaning of the operand depends on the instruction code. The symbols are used
as follows:
•
•
•
•
•

xxxx: Instruction code
mmmm: Source register
nnnn: Destination registeriiii: Immediate data
dddd: Displacement

HITACHI 29

Instruction Formats

Table 4.8

Instruction Formats

SourceOperand

Destination
Operand

Example0 format

—

—

NOP

—

nnnn: Direct
register

MOVT

Rn

Control registeror system
register

nnnn: Direct
registerSTS

MACH,Rn

15

0
xxxx

xxxx

xxxx

xxxx

n format

15

0
xxxx

nnnn

30 HITACHI

xxxx

xxxx

Table 4.8

Instruction Formats (cont)SourceOperand

Destination
Operandn format (cont)Control registeror system
register

nnnn: Indirect
pre-decrement
registerm format

mmmm: Direct
register

Control registerLDC
or system register

Rm,SR

mmmm: Indirect
post-increment
register

Control register
LDC.L
or system register@Rm+,SR

mmmm: Direct
register

—

JMP

@Rm

mmmm: PC—
relative using Rm

BRAF

Rm

mmmm: Direct
register

nnnn: Direct
register

ADD

Rm,Rn

mmmm: Direct
register

nnnn: Indirect
register

MOV.L

Rm,@Rnmmmm: Indirect
post-increment
register(multiply/
accumulate)

MACH, MACL

MAC.W
@Rm+,@Rn+

mmmm: Indirect
post-increment
register

nnnn: Direct
register

MOV.L@Rm+,Rn

mmmm: Direct
register

nnnn: Indirect
pre-decrement
register

MOV.L

Rm,@-Rn

mmmm: Direct
register

nnnn: Indirectindexed register

MOV.L
Rm,@(R0,Rn)

mmmmdddd:
indirect registerwithdisplacement

R0 (Direct
register)

MOV.B@(disp,Rm),R0

Instruction Formats

150xxxx mmmm xxxx

xxxx

nm format
15

0
xxxx

nnnn mmmm xxxx

ExampleSTC.L

SR,@-Rn

nnnn*: Indirect
post-increment
register(multiply/
accumulate)

md format
15

0
xxxx

xxxx mmmm dddd

HITACHI 31

nd4 format
15

0
xxxx

xxxx

nnnn

dddd

R0 (Direct
register)

nnnndddd:
Indirect registerwith displacement

Note: In multiply/accumulate instructions, nnnn is the source register.

32 HITACHI

MOV.B
R0,@(disp,Rn)

Table 4.8

Instruction Formats (cont)

Instruction Formats
nmd format
15

0
xxxx

SourceOperand

Destination
Operandmmmm: Direct
register

nnnndddd:
Indirect registerwith displacement

nnnn mmmm dddd

nnnn: Direct
mmmmdddd:
Indirect register registerwithdisplacementd format
15

0
xxxx

xxxx

dddd

dddd

d12 format
15

0
xxxx

dddd

dddd

15

0
xxxx

nnnn

dddd

dddd

i format
15

0
xxxx

xxxx

iiii

15

0
xxxx

nnnn

iiii

MOV.L
@(disp,Rm),Rn

R0 (Direct
register)

MOV.L@(disp,GBR),R0

R0(Direct
register)

dddddddd:
Indirect GBR withdisplacement

MOV.L
R0,@(disp,GBR)

dddddddd: PC
relative withdisplacement

R0 (Direct
register)

MOVA@(disp,PC),R0

dddddddd: PC
relative

—

BF

label

ddddddddddd
d: PC relative

—

BRA

label

dddddddd: PC
relative withdisplacement

nnnn: Direct
register

MOV.L@(disp,PC),Rn

iiiiiiii: Immediate

Indirect indexed
GBR

AND.B
#imm,@(R0,GBR)

iiiiiiii: Immediate

R0 (Direct
register)AND#imm,R0iiiiiiii: Immediate

—

TRAPA

#imm

iiiiiiii: Immediate

nnnn: Direct
register

ADD#imm,Rniiii

ni format

MOV.L
Rm,@(disp,Rn)

dddddddd:
Indirect GBR
withdisplacement(label = disp
+ PC)

dddd

nd8 format

Exampleiiii

HITACHI 33

Section 5 Instruction Set
5.1

Instruction Set by Classification

Table 5.1 lists instructions by classification.
Table 5.1

Classification of Instructions
A pplicable
Instructions

Classification

Types

Operation
Code

Data transfer

5MOV

34 HITACHI

SH-1

No. of
Instructions

Data transfer
X
Immediate data transfer
Peripheral module data transfer
Structure data transfer

X

39

MOVA

Effective address transfer

X

MOVT

T-bit transfer

X

X

SWAP

Swap of upper and lower
bytes

X

X

XTRCT

Extraction of the middle ofregisters connected

X

X

Function

SH-2

X

Table 5.1

Classification of Instructions (cont)A pplicable
Instructions

Classification

Types

Operation
Code

Function

SH-2

SH-1

No. of
Instructions

Arithmetic
operations

21

ADD

Binary addition

X

X

33

ADDC

Binary addition with carry

X

X

ADDV

Binary addition with overflow
check

X

X

CMP/condComparison

X

X

DIV1

Division

X

X

DIV0S

Initialization of signed division

X

X

DIV0U

Initialization of unsigned
division

X

X

DMULS

Signed double-length
multiplication

X

DMULU

Unsigned double-length
multiplication

X

DT

Decrement and test

X

EXTS

Sign extension

X

X

EXTU

Zero extension

X

X

MAC

Multiply/accumulate, doublelength multiply/accumulate
operation*1

X

X

MUL

Double-length multiplication

X

MULS

Signed multiplication

X

X

MULU

Unsigned multiplication

X

X

NEG

Negation

X

X

NEGC

Negation with borrow

X

X

SUB

Binary subtraction

X

X

SUBC

Binary subtraction with borrow

X

X

SUBV

Binary subtraction with
underflow check

X

X

Notes 1. Double-length multiply/accumulate is an SH-2 function.

HITACHI 35

Table 5.1

Classification of Instructions (cont)
Applicable
Instructions

Classification

Types

Operation
Code

Function

Logic
operations

6

AND

Logical AND

NOT

Bit inversion

OR

Logical OR

X

X

Shift

Branch109No. of
Instructions

X

X

14

X

X

TAS

Memory test and bit set

X

X

TST

Logical AND and T-bit set

X

X

XOR

Exclusive OR

X

X

ROTL

One-bit left rotation

X

X

ROTR

One-bit right rotation

X

X

ROTCL

One-bit left rotation with T bit

X

X

ROTCR

One-bit right rotation with T bit X

X

SHAL

One-bit arithmetic left shift

X

X

SHAR

One-bit arithmetic right shift

X

X

SHLL

One-bit logical left shift

X

X

SHLLn

n-bit logical left shift

X

X

SHLR

One-bit logical right shift

X

X

SHLRn

n-bit logical right shift

X

X

BF

Conditional branch, conditional
branch with delay* 2 (T = 0)

X

X

BT

Conditional branch, conditional X
branch with delay* 2 (T = 1)

X

BRA

Unconditional branch

X

X

BRAF

Unconditional branch

X

BSR

Branch to subroutine
procedure

X

BSRF

Branch to subroutine
procedure

X

JMP

Unconditional branch

X

X

JSR

Branch to subroutine
procedure

X

X

RTS

Return from subroutine
procedure

X

X

Notes 2. Conditional branch with delay is an SH-2 CPU function.

36 HITACHI

SH-1

SH-2

X

14

11

Table 5.1

Classification of Instructions (cont)
Applicable
Instructions

Classification

Types

Operation
Code

Function

SH-2

SH-1

No. of
Instructions

Systemcontrol11

CLRT

T-bit clear

X

X

31

CLRMAC

MAC register clear

X

X

LDC

Load to control register

X

X

LDS

Load to system register

X

X

NOP

No operation

X

X

RTE

Return from exception
processing

X

X

SETT

T-bit set

X

X

SLEEP

Shift into power-down mode

X

X

STC

Storing control register data

X

X

STS

Storing system register data

X

X

TRAPA

Trap exception processing

X

X

Total: 62

142

HITACHI 37

Instruction codes, operation, and execution states are listed in table 5.2 in order byclassification.
Table 5.2

Instruction Code Format

Item

FormatExplanation

Instruction
mnemonic

OP.Sz SRC,DEST

OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*

Instructioncode

MSB ↔ LSB

mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1...........
1111: R15
iiii: Immediate data
dddd: Displacement

Operationsummary

→, ←
(xx)
M/Q/T
&
|
^
~
<<n, >>n

Direction of transfer
Memory operandFlag bits in the SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit left/right shift

Execution
cycle

Value when no wait states are inserted

Instruction
execution
cycles

The execution cycles shown in the table are minimums.
The actual number of cycles may be increased:
1. When contention occurs between instruction fetches
and data access, or
2. When the destination register of the load instruction(memory → register) and the register used by the next
instruction are the same.

T bit

Value of T bit after instruction is executed—

No change

Note: Scaling (x1, x2, x4) is performed according to the instruction operand size. See "6.
Instruction Descriptions" for details.

38 HITACHI

5.1.1

Data Transfer Instructions

Tables 5.3 to 5.8 list the minimum number of clock states required for execution.

HITACHI 39

Table 5.3

Data Transfer Instructions
Execution
State

T
Bit

Instruction

Instruction CodeOperation

MOV#imm,Rn

1110nnnniiiiiiii

imm → Sign extension →
Rn

1

—

MOV.W

@(disp,PC),Rn

1001nnnndddddddd(disp × 2 + PC) → Sign
extension → Rn

1

—

MOV.L

@(disp,PC),Rn

1101nnnndddddddd(disp × 4 + PC) → Rn

1

—

MOV

Rm,Rn

0110nnnnmmmm0011

Rm → Rn

1

—

MOV.B

Rm,@Rn0010nnnnmmmm0000

Rm → (Rn)

1

—

MOV.W

Rm,@Rn0010nnnnmmmm0001

Rm → (Rn)

1

—

MOV.L

Rm,@Rn0010nnnnmmmm0010

Rm → (Rn)

1

—

MOV.B

@Rm,Rn0110nnnnmmmm0000(Rm) → Sign extension →
Rn

1

—

MOV.W

@Rm,Rn0110nnnnmmmm0001(Rm) → Sign extension →
Rn

1

—

MOV.L

@Rm,Rn0110nnnnmmmm0010(Rm) → Rn

1

—

MOV.B

Rm,@–Rn

0010nnnnmmmm0100

Rn–1 → Rn, Rm → (Rn)

1

—

MOV.W

Rm,@–Rn

0010nnnnmmmm0101

Rn–2 → Rn, Rm → (Rn)

1

—

MOV.L

Rm,@–Rn

0010nnnnmmmm0110

Rn–4 → Rn, Rm → (Rn)

1

—

MOV.B

@Rm+,Rn

0110nnnnmmmm0100(Rm) → Sign extension →Rn,Rm + 1 → Rm

1

—

MOV.W

@Rm+,Rn

0110nnnnmmmm0101(Rm) → Sign extension →Rn,Rm + 2 → Rm

1

—

MOV.L

@Rm+,Rn

0110nnnnmmmm0110(Rm) → Rn,Rm + 4 → Rm

1

—

MOV.B

R0,@(disp,Rn)

10000000nnnndddd

R0 → (disp + Rn)

1

—

MOV.W

R0,@(disp,Rn)

10000001nnnndddd

R0 → (disp × 2 + Rn)

1

—

MOV.L

Rm,@(disp,Rn)

0001nnnnmmmmdddd

Rm → (disp × 4 + Rn)

1

—

MOV.B

@(disp,Rm),R0

10000100mmmmdddd(disp + Rm) → Sign
extension → R0

1

—

MOV.W

@(disp,Rm),R0

10000101mmmmdddd(disp × 2 + Rm) → Sign
extension → R0

1

—

MOV.L

@(disp,Rm),Rn

0101nnnnmmmmdddd(disp × 4 + Rm) → Rn

1

—

MOV.B

Rm,@(R0,Rn)

0000nnnnmmmm0100

Rm → (R0 + Rn)

1

—

MOV.W

Rm,@(R0,Rn)

0000nnnnmmmm0101

Rm → (R0 + Rn)

1—

40 HITACHITable 5.3

Data Transfer Instructions (cont)

Instruction

Instruction CodeOperation

Execution
State

MOV.L

Rm,@(R0,Rn)

0000nnnnmmmm0110

Rm → (R0 + Rn)

1

—

MOV.B

@(R0,Rm),Rn

0000nnnnmmmm1100(R0 + Rm) → Sign
extension → Rn

1

—

MOV.W

@(R0,Rm),Rn

0000nnnnmmmm1101(R0 + Rm) → Sign
extension → Rn

1

—

MOV.L

@(R0,Rm),Rn

0000nnnnmmmm1110(R0 + Rm) → Rn

1

—

MOV.B

R0,@(disp,GBR)

11000000dddddddd

R0 → (disp + GBR)

1

—

MOV.W

R0,@(disp,GBR)

11000001dddddddd

R0 → (disp × 2 + GBR)

1

—

MOV.L

R0,@(disp,GBR)

11000010dddddddd

R0 → (disp × 4+ GBR)

1

—

MOV.B

@(disp,GBR),R0

11000100dddddddd(disp + GBR) → Sign
extension → R0

1

—

MOV.W

@(disp,GBR),R0

11000101dddddddd(disp × 2 + GBR) → Sign
extension → R0

1

—

MOV.L

@(disp,GBR),R0

11000110dddddddd(disp × 4 + GBR) → R0

1

—

MOVA

@(disp,PC),R0

11000111dddddddd

disp × 4 + PC → R0

1

—

MOVT

Rn

0000nnnn00101001

T → Rn1—

SWAP.B Rm,Rn

0110nnnnmmmm1000

Rm → Swap upper andlower 2 bytes → Rn

1—

SWAP.W Rm,Rn

0110nnnnmmmm1001

Rm → Swap upper andlower word → Rn

1

—

XTRCT

0010nnnnmmmm1101

Center 32 bits of Rm and
Rn→ Rn

1

—

Rm,Rn

T
Bit

HITACHI 41

5. 1.2

Arithmetic Instructions

Table 5.4

Arithmetic Instructions

Instruction

Instruction CodeOperation

Execution
State
T Bit

ADD

Rm,Rn

0011nnnnmmmm110
0

Rn + Rm → Rn

1

—

ADD

#imm,Rn

0111nnnniiiiiii
i

Rn + imm → Rn

1

—

ADDC

Rm,Rn

0011nnnnmmmm111
0

Rn + Rm + T → Rn,
Carry → T

1

Carry

ADDV

Rm,Rn

0011nnnnmmmm111
1

Rn + Rm → Rn,
Overflow → T

1

Overflow

CMP/EQ #imm,R0

10001000iiiiiii
i

If R0 = imm, 1 → T

1Comparison result

CMP/EQ Rm,Rn

0011nnnnmmmm0000

If Rn = Rm, 1 → T

1Comparison result

CMP/HS Rm,Rn

0011nnnnmmmm001
0

If Rn ≥Rm with
unsigned data, 1 → T

1Comparison result

CMP/GE Rm,Rn

0011nnnnmmmm001
1

If Rn ≥ Rm withsigned data, 1 → T

1Comparison result

CMP/HI Rm,Rn

0011nnnnmmmm011
0

If Rn > Rm with
unsigned data, 1 → T

1Comparison result

CMP/GT Rm,Rn

0011nnnnmmmm011
1

If Rn > Rm withsigned data, 1 → T

1Comparison result

CMP/PL R n

0100nnnn0001010
1

If Rn > 0, 1 → T

1Comparison result

CMP/PZ R n

0100nnnn0001000
1

If Rn ≥ 0, 1 → T

1Comparison result

CMP/STR
Rm,Rn

0010nnnnmmmm1100

If Rn and Rm have an
equivalent byte, 1 →T

1Comparison result

DIV1

Rm,Rn

0011nnnnmmmm010
0Single-step division(Rn/Rm)1

Calculation
result

DIV0S

Rm,Rn

0010nnnnmmmm011
1

MSB of Rn → Q,
MSB of Rm → M, M
^Q→ T

1

Calculation
result000000000001100
1

0 → M/Q/T

1

0

DIV0U

42 HITACHITable 5.4

Arithmetic Instructions (cont)

Instruction

Instruction CodeOperation

DMULS.L
Rm,Rn*20011nnnnmmmm1101

Signed operation ofRn x Rm → MACH,
MACL

Execution
State
T Bit
2 to 4*1—

2 to 4*1—

32 x 32 → 64 bits
DMULU.L
Rm,Rn*20011nnnnmmmm0101

Unsigned operationof Rn x Rm →MACH, MACL
32 x 32 → 64 bits

Rn*2

0100nnnn00010000

Rn - 1 → Rn, when
Rn is 0, 1 → T. When
Rn is nonzero, 0 → T

1Comparison result

EXTS.B Rm,Rn

0110nnnnmmmm1110

A byte in Rm is signextended → Rn

1—

EXTS.W Rm,Rn

0110nnnnmmmm1111

A word in Rm is signextended → Rn

1—

EXTU.B Rm,Rn

0110nnnnmmmm1100

A byte in Rm is zeroextended → Rn

1—

EXTU.W Rm,Rn

0110nnnnmmmm1101

A word in Rm is zero- 1
extended → Rn

—

MAC.L

0000nnnnmmmm1111

Signed operation of(Rn) x (Rm) + MAC
→ MAC

DT

@Rm+,@Rn+*2

3/(2 to 4)* 1—

3/(2)*1—

32 x 32 + 64→ 64
bits
MAC.W

@Rm+,@Rn+

0100nnnnmmmm1111

Signed operation of(Rn) × (Rm) + MAC→ MAC(SH-2 CPU) 16 x 16
+ 64 → 64 bits
(SH-1 CPU) 16 x 16
+ 42 → 42 bits

MUL.L

Rm,Rn*2

MULS.W Rm,Rn

0000nnnnmmmm0111

Rn x Rm → MACL,
32 x 32 → 32 bits

2 to 4*1—0010nnnnmmmm1111

Signed operation of
Rn × Rm → MAC

1 to 3*1—

16 x 16 → 32 bits
Notes: 1. The normal minimum number of execution states (The number in parentheses is thenumber of states when there is contention with preceding/following instructions)
2. SH-2 CPU instructions

HITACHI 43

Table 5.4

Arithmetic Instructions (cont)

Instruction

Instruction CodeOperation

MULU.W Rm,Rn

0010nnnnmmmm1110

Unsigned operationof Rn × Rm → MAC

Execution
State
T Bit
1 to 3*1—

16 x 16 → 32 bits
NEG

Rm,Rn

0110nnnnmmmm1011

0–Rm → Rn

1

—

NEGC

Rm,Rn

0110nnnnmmmm1010

0–Rm–T → Rn,
Borrow → T

1

Borrow

SUB

Rm,Rn

0011nnnnmmmm1000

Rn–Rm → Rn

1

—

SUBC

Rm,Rn

0011nnnnmmmm1010

Rn–Rm–T → Rn,
Borrow → T

1

Borrow

SUBV

Rm,Rn

0011nnnnmmmm1011

Rn–Rm → Rn,
Underflow → T

1

Underflow

Notes: 1. The normal minimum number of execution states (The number in parentheses is thenumber of states when there is contention with preceding/following instructions)

5.1.3

Logic Operation Instructions

Table 5.5

Logic Operation Instructions

Instruction

Instruction CodeOperation

Execution State

T Bit

AND

Rm,Rn

0010nnnnmmmm1001

Rn & Rm → Rn

1

—

AND

#imm,R0

11001001iiiiiiii

R0 & imm → R0

1

—

AND.B

#imm,@(R0,GBR) 11001101iiiiiiii(R0 + GBR) & imm →(R0 + GBR)

3

—

NOT

Rm,Rn

0110nnnnmmmm0111~Rm → Rn

1

—

OR

Rm,Rn

0010nnnnmmmm1011

Rn | Rm → Rn

1

—

OR

#imm,R0

11001011iiiiiiii

R0 | imm → R0

1

—

OR.B

#imm,@(R0,GBR) 11001111iiiiiiii(R0 + GBR) | imm →(R0 + GBR)

3

—

TAS.B

@Rn

0100nnnn00011011

If (Rn) is 0, 1 → T; 1 →MSB of (Rn)4

TestresultTST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm; if the result is 1
0, 1 → T

Test
resultTST#imm,R0

11001000iiiiiiii

R0 & imm; if the result
is 0, 1 → T

Test
result44 HITACHI1

Table 5.5

Logic Operation Instructions (cont)

Instruction

Instruction Code

Execution StateOperation

T Bit

TST.B

#imm,@(R0,GBR) 11001100iiiiiiii(R0 + GBR) & imm; if
the result is 0, 1 → T

3

Test
resultXOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm → Rn

1

—

XOR

#imm,R0

11001010iiiiiiii

R0 ^ imm → R0

1

—

XOR.B

#imm,@(R0,GBR) 11001110iiiiiiii(R0 + GBR) ^ imm →(R0 + GBR)

3

—

5.1.4

Shift Instructions

Table 5.6

Shift Instructions

Instruction

Instruction CodeOperation

Execution State

T Bit

ROTL

Rn

0100nnnn00000100

T ← Rn ← M S B

1

MSB

ROTR

Rn

0100nnnn00000101

LSB → Rn → T

1

LSB

ROTCL

Rn

0100nnnn00100100

T ← Rn ← T

1

MSB

ROTCR

Rn

0100nnnn00100101

T → Rn → T

1

LSB

SHAL

Rn

0100nnnn00100000

T ← Rn ← 0

1

MSB

SHAR

Rn

0100nnnn00100001

MSB → Rn → T

1

LSB

SHLL

Rn

0100nnnn00000000

T ← Rn ← 0

1

MSB

SHLR

Rn

0100nnnn00000001

0 → Rn → T

1

LSB

SHLL2

Rn

0100nnnn00001000

Rn<<2 → Rn

1

—

SHLR2

Rn

0100nnnn00001001

Rn>>2 → Rn

1

—

SHLL8

Rn

0100nnnn00011000

Rn<<8 → Rn

1

—

SHLR8

Rn

0100nnnn00011001

Rn>>8 → Rn

1—

SHLL16 Rn

0100nnnn00101000

Rn<<16 → Rn

1—

SHLR16 Rn

0100nnnn00101001

Rn>>16 → Rn

1—

HITACHI 45

5.1.5

Branch Instructions

Table 5.7

Branch Instructions
Execution State

T Bit

3/1*3

—

BF/S label*2 10001111dddddddd

Delayed branch, if T = 0, disp × 2 + 2/1*3
PC → PC; if T = 1, nop—

BT

If T = 1, disp × 2 + PC → PC; if T
= 0, nop (where label is disp + PC)

3/1*3

—

BT/S label*2 10001101dddddddd

Delayed branch, if T = 1, disp × 2 + 2/1*3
PC → PC; if T = 0, nop—

BRA

Instruction
BF

label

label

Instruction CodeOperation

10001011dddddddd

If T = 0, disp × 2 + PC → PC; if T
= 1, nop (where label is disp × 2 +PC)

10001001dddddddd

label

1010dddddddddddd

Delayed branch, disp × 2 + PC →
PC

2

—

BRAF Rm*2

0000mmmm00100011

Delayed branch, Rm + PC → PC

2

—

BSR

label

1011dddddddddddd

Delayed branch, PC → PR, disp ×
2 + PC → PC

2—

BSRF Rm*2

0000mmmm00000011

Delayed branch, PC → PR, Rm +PC → PC

2

—

JMP

@Rm

0100mmmm00101011

Delayed branch, Rm → PC

2

—

JSR

@Rm

0100mmmm00001011

Delayed branch, PC → PR, Rm →
PC

2

—

0000000000001011

Delayed branch, PR → PC

2

—

RTS

Notes: 2. SH-2 CPU instruction
3. One state when it does not branch

46 HITACHI

5.1.6

System Control Instructions

Table 5.8

System Control Instructions

Instruction

Instruction CodeOperation

Execution State

T
Bit

CLRT

0000000000001000

0→T

1

0

CLRMAC

0000000000101000

0 → MACH, MACL

1

—

LDC

Rm,SR

0100mmmm00001110

Rm → SR

1

LSB

LDC

Rm,GBR

0100mmmm00011110

Rm → GBR

1

—

LDC

Rm,VBR

0100mmmm00101110

Rm → VBR

1

—

LDC.L

@Rm+,SR

0100mmmm00000111(Rm) → SR, Rm + 4 → Rm

3

LSB

LDC.L

@Rm+,GBR

0100mmmm00010111(Rm) → GBR, Rm + 4 → Rm

3

—

LDC.L

@Rm+,VBR

0100mmmm00100111(Rm) → VBR, Rm + 4 → Rm

3

—

LDS

Rm,MACH

0100mmmm00001010

Rm → MACH

1

—

LDS

Rm,MACL

0100mmmm00011010

Rm → MACL

1

—

LDS

Rm,PR

0100mmmm00101010

Rm → PR

1

—

LDS.L

@Rm+,MACH

0100mmmm00000110(Rm) → MACH, Rm + 4 → Rm 1

—

LDS.L

@Rm+,MACL

0100mmmm00010110(Rm) → MACL, Rm + 4 → Rm 1

—

LDS.L

@Rm+,PR

0100mmmm00100110(Rm) → PR, Rm + 4 → Rm

1

—

NOP

0000000000001001

No operation

1

—

RTE

0000000000101011

Delayed branch, stack area →
PC/SR

4

LSB

SETT

0000000000011000

1→T

1

1

0000000000011011

Sleep

3* 4

—

SLEEP
STC

SR,Rn

0000nnnn00000010

SR → Rn

1—

STC

GBR,Rn

0000nnnn00010010

GBR → Rn

1

—

STC

VBR,Rn

0000nnnn00100010

VBR → Rn

1

—

STC.L

SR,@–Rn

0100nnnn00000011

Rn–4 → Rn, SR → (Rn)

2

—

STC.L

GBR,@–Rn

0100nnnn00010011

Rn–4 → Rn, GBR → (Rn)

2

—

STC.L

VBR,@–Rn

0100nnnn00100011

Rn–4 → Rn, VBR → (Rn)

2

—

STS

MACH,Rn

0000nnnn00001010

MACH → Rn

1

—

STS

MACL,Rn

0000nnnn00011010

MACL → Rn

1

—

STS

PR,Rn

0000nnnn00101010

PR → Rn

1—

HITACHI 47

Table 5.8

System Control Instructions (cont)
Execution
State

T
Bit

0100nnnn00000010 Rn–4 → Rn, MACH → (Rn)1—

MACL,@–Rn

0100nnnn00010010 Rn–4 → Rn, MACL → (Rn)

1

—

STS.L

PR,@–Rn

0100nnnn00100010 Rn–4 → Rn, PR → (Rn)

1

—

TRAPA

#imm

11000011iiiiiiii PC/SR → stack area, (imm ×
4 + VBR) → PC

8—

Instruction

Instruction CodeSTS.L

MACH,@–Rn

STS.L

Operation

Notes: 4. The number of execution states before the chip enters the sleep state
5. The above table lists the minimum execution cycles. In practice, the number of
execution cycles increases when the instruction fetch is in contention with data
access or when the destination register of a load instruction (memory → register) is
the same as the register used by the next instruction.

5.2

Instruction Set in Alphabetical Order

Table 5.9 alphabetically lists instruction codes and number of execution cycles for each
instruction.

48 HITACHITable 5.9

Instruction Set

Instruction

Instruction CodeOperation

Execution
State

ADD

#imm,Rn

0111nnnniiiiiii
i

Rn + imm → Rn

1

—

ADD

Rm,Rn

0011nnnnmmmm110
0

Rn + Rm → Rn

1

—

ADDC

Rm,Rn

0011nnnnmmmm111
0

Rn + Rm + T → Rn,
Carry → T

1

Carry

ADDV

Rm,Rn

0011nnnnmmmm111
1

Rn + Rm → Rn,
Overflow → T

1

OverflowAND#imm,R0

11001001iiiiiii
i

R0 & imm → R0

1

—

AND

Rm,Rn

0010nnnnmmmm100
1

Rn & Rm → Rn

1

—

AND.B

#imm,@(R0,GBR)

11001101iiiiiii
i(R0 + GBR) & imm→ (R0 + GBR)

3

—

BF

label

10001011dddddddd

If T = 0, disp × 2 + 3/1*3
PC → PC; if T = 1,
nop

—

BF/S

label*2

10001111dddddddd

If T = 0, disp × 2+ 2/1*3
PC → PC; if T = 1,
nop

—

T Bit

HITACHI 49

Table 5.9

Instruction Set (cont)
Execution
State

T Bit

Instruction

Instruction CodeOperation

BRA

label

1010dddddddddddd

Delayed branch, disp× 2 + PC → PC

2

—

BRAF

Rm*2

0000mmmm00100011

Delayed branch, Rm +PC → PC

2

—

BSR

label

1011dddddddddddd

Delayed branch, PC → 2
PR, disp × 2 + PC →
PC

—

BSRF

Rm*2

0000mmmm00000011

Delayed branch, PC → 2
PR, Rm + PC → PC

—

BT

label

10001001dddddddd

If T = 1, disp × 2+ PC→ PC; if T = 0, nop

3/1*3

—

BT/S

label*2

10001101dddddddd

If T = 1, disp × 2 + PC
→ PC; if T = 0, nop

2/1*3

—

CLRMAC

0000000000101000

0 → MACH, MACL

1

—

CLRT

0000000000001000

0→T

1

0

CMP/EQ #imm,R0

10001000iiiiiiii

If R0 = imm, 1 → T

1Comparison
result

CMP/EQ Rm,Rn

0011nnnnmmmm0000

If Rn = Rm, 1 → T

1Comparison
result

CMP/GE Rm,Rn

0011nnnnmmmm0011

If Rn ≥ Rm with signed
data, 1 → T

1Comparison
result

CMP/GT Rm,Rn

0011nnnnmmmm0111

If Rn > Rm with signed
data, 1 → T

1Comparison
result

CMP/HI Rm,Rn

0011nnnnmmmm0110

If Rn > Rm with
unsigned data,
1→T

1Comparison
result

CMP/HS Rm,Rn

0011nnnnmmmm0010

If Rn ≥ Rm with
unsigned data,
1→T

1Comparison
result

CMP/PL Rn

0100nnnn00010101

If Rn>0, 1 → T

1Comparison
result

CMP/PZ Rn

0100nnnn00010001

If Rn ≥ 0, 1 → T

1Comparison
resultNotes: 2. SH-2 CPU instructions
3. One state when it does not branch

50 HITACHITable 5.9

Instruction Set (cont)
Execution
State

Instruction

Instruction CodeOperation

CMP/STR
Rm,Rn

0010nnnnmmmm1100

If Rn and Rm havean equivalent byte,
1→T

1Comparison
result

DIV0S0010nnnnmmmm0111

MSB of Rn → Q,
MSB of Rm → M,
M^Q →T

1

Calculation
result0000000000011001

0 → M/Q/T

100011nnnnmmmm0100

Single-step
division (Rn/Rm)

1

Calculation
resultDMULS.L
Rm,Rn*20011nnnnmmmm1101

Signed operationof Rn x Rm →MACH, MACL

2 to 4*1—

DMULU.L
Rm,Rn*20011nnnnmmmm0101

Unsigned
operation of Rn x
Rm → MACH,
MACL

2 to 4*1—

Rn*2

0100nnnn00010000

Rn - 1 → Rn, when
Rn is 0, 1 → T.
When Rn is
nonzero, 0 → T

1Comparison
result

EXTS.B Rm,Rn

0110nnnnmmmm1110

A byte in Rm issign-extended →
Rn

1

—

EXTS.W Rm,Rn

0110nnnnmmmm1111

A word in Rm issign-extended →
Rn

1

—

EXTU.B Rm,Rn

0110nnnnmmmm1100

A byte in Rm iszero-extended →
Rn

1

—

EXTU.W Rm ,Rn

0110nnnnmmmm1101

A word in Rm iszero-extended →
Rn

1

—

JMP

0100mmmm00101011

Delayed branch,
Rm → PC

2

—

Rm,Rn

DIV0U
DIV1

DT

Rm,Rn

@Rm

T Bit

Notes: 1. The normal minimum number of execution states
2. SH-2 CPU instructions

HITACHI 51

Table 5.9

Instruction Set (cont)
Execution
State

T Bit

Instruction

Instruction CodeOperation

JSR

@Rm

0100mmmm00001011

Delayed branch,
PC → PR, Rm →
PC

2

—

LDC

Rm,GBR

0100mmmm00011110

Rm → GBR

1

—

LDC

Rm,SR

0100mmmm00001110

Rm → SR

1

LSB

LDC

Rm,VBR

0100mmmm00101110

Rm → VBR

1

—

LDC.L

@Rm+,GBR

0100mmmm00010111(Rm) → GBR, Rm+ 4 → Rm

3

—

LDC.L

@Rm+,SR

0100mmmm00000111(Rm) → SR, Rm +4 → Rm

3

LSB

LDC.L

@Rm+,VBR

0100mmmm00100111(Rm) → VBR, Rm+ 4 → Rm

3

—

LDS

Rm,MACH

0100mmmm00001010

Rm → MACH

1

—

LDS

Rm,MACL

0100mmmm00011010

Rm → MACL

1

—

LDS

Rm,PR

0100mmmm00101010

Rm → PR

1

—

LDS.L

@Rm+,MACH

0100mmmm00000110(Rm) → MACH,
Rm + 4 → Rm

1

—

LDS.L

@Rm+,MACL

0100mmmm00010110(Rm) → MACL, Rm 1
+ 4 → Rm—

LDS.L

@Rm+,PR

0100mmmm00100110(Rm) → PR, Rm + 4
→ Rm

1

—

MAC.L

@Rm+,@Rn+* 20000nnnnmmmm1111

Signed operationof (Rn) × (Rm) +MAC → MAC

3/(2 to
4)* 1

—

MAC.W

@Rm+,@Rn+

0100nnnnmmmm1111

Signed operationof (Rn) × (Rm) +MAC → MAC

3/(2)*1—

MOV#imm,Rn

1110nnnniiiiiiii

imm → Sign
extension → Rn

1

—

MOV

Rm,Rn

0110nnnnmmmm0011

Rm → Rn

1—

Notes: 1. The normal minimum number of execution states (the number in parentheses is thenumber of states when there is contention with preceding/following instructions)
2. SH-2 instructions

52 HITACHITable 5.9

Instruction Set (cont)
Execution
State

T Bit

Instruction

Instruction CodeOperation

MOV.B@(disp,GBR),R0

11000100dddddddd(disp + GBR) → Sign
extension → R0

1

—

MOV.B

@(disp,Rm),R0

10000100mmmmdddd(disp + Rm) → Sign
extension → R0

1

—

MOV.B

@(R0,Rm),Rn

0000nnnnmmmm1100(R0 + Rm) → Sign
extension → Rn

1

—

MOV.B

@Rm+,Rn

0110nnnnmmmm0100(Rm) → Sign extension→ Rn, Rm + 1 → Rm

1

—

MOV.B

@Rm,Rn0110nnnnmmmm0000(Rm) → Sign extension
→ Rn

1

—

MOV.B

R0,@(disp,GBR)

11000000dddddddd

R0 → (disp + GBR)

1

—

MOV.B

R0,@(disp,Rn)

10000000nnnndddd

R0 → (disp + Rn)

1

—

MOV.B

Rm,@(R0,Rn)

0000nnnnmmmm0100

Rm → (R0 + Rn)

1

—

MOV.B

Rm,@–Rn

0010nnnnmmmm0100

Rn–1 → Rn, Rm →
(Rn)

1

—

MOV.B

Rm,@Rn0010nnnnmmmm0000

Rm → (Rn)

1

—

MOV.L

@(disp,GBR),R0

11000110dddddddd(disp × 4 + GBR) → R0

1

—

MOV.L

@(disp,PC),Rn

1101nnnndddddddd(disp × 4 + PC) → Rn

1

—

MOV.L

@(disp,Rm),Rn

0101nnnnmmmmdddd(disp × 4 + Rm) → Rn

1

—

MOV.L

@(R0,Rm),Rn

0000nnnnmmmm1110(R0 + Rm) → Rn

1

—

MOV.L

@Rm+,Rn

0110nnnnmmmm0110(Rm) → Rn, Rm + 4 →
Rm

1

—

MOV.L

@Rm,Rn0110nnnnmmmm0010(Rm) → Rn

1

—

MOV.L

R0,@(disp,GBR)

11000010dddddddd

R0 → (disp × 4 + GBR)

1

—

MOV.L

Rm,@(disp,Rn)

0001nnnnmmmmdddd

Rm → (disp × 4 + Rn)

1

—

MOV.L

Rm,@(R0,Rn)

0000nnnnmmmm0110

Rm → (R0 + Rn)

1

—

MOV.L

Rm,@–Rn

0010nnnnmmmm0110

Rn–4 → Rn, Rm →
(Rn)

1

—

MOV.L

Rm,@Rn0010nnnnmmmm0010

Rm → (Rn)

1

—

MOV.W

@(disp,GBR),R0

11000101dddddddd(disp × 2 + GBR) →Sign extension →
R0

1

—

HITACHI 53

Table 5.9

Instruction Set (cont)
Execution
State

T Bit

Instruction

Instruction CodeOperation

MOV.W@(disp,PC),Rn

1001nnnndddddddd(disp × 2 + PC) →Sign extension → Rn

1

—

MOV.W
@(disp,Rm),R0

10000101mmmmdddd(disp × 2 + Rm) →Sign extension → R0

1—

MOV.W @(R0,Rm),Rn

0000nnnnmmmm1101(R0 + Rm) → Sign
extension → Rn

1—

MOV.W @Rm+,Rn

0110nnnnmmmm0101(Rm) → Sign
1extension → Rn, Rm +2 → Rm—MOV.W @Rm,Rn

0110nnnnmmmm0001(Rm) → Sign
extension → Rn

1

—

MOV.W
11000001dddddddd
R0,@(disp,GBR)

R0 → (disp × 2+ GBR) 1

—

MOV.W
R0,@(disp,Rn)

10000001nnnndddd

R0 → (disp × 2 + Rn)

1—

MOV.W Rm,@(R0,Rn)

0000nnnnmmmm0101

Rm → (R0 + Rn)

1—

MOV.W Rm,@–Rn0010nnnnmmmm0101

Rn–2 → Rn, Rm →
(Rn)

1

—

MOV.W Rm,@Rn

0010nnnnmmmm0001

Rm → (Rn)1—

MOVA @(disp,PC),R0 11000111dddddddd

disp × 4 + PC → R0

1

—

MOVT

Rn

0000nnnn00101001

T → Rn

1

—

MUL.L

Rm,Rn*20000nnnnmmmm0111

Rn × Rm → MACL

2 to 4*1——

MULS.W Rm,Rn

0010nnnnmmmm1111

Signed operation of
Rn × Rm → MAC

1 to 3*1

MULU.W Rm,Rn

0010nnnnmmmm1110

Unsigned operation of
Rn × Rm → MAC

1 to 3*1

—

NEG

Rm,Rn

0110nnnnmmmm1011

0–Rm → Rn

1

—

NEGC

Rm,Rn

0110nnnnmmmm1010

0–Rm–T → Rn,
Borrow → T

1

Borrow

0000000000001001

No operation

1

—

NOP
NOT

Rm,Rn

0110nnnnmmmm0111~Rm → Rn

1—

OR

#imm,R0

11001011iiiiiiii

R0 | imm → R0

1

—

OR

Rm,Rn

0010nnnnmmmm1011

Rn | Rm → Rn

1—

Notes: 1. The normal minimum number of execution states
2. SH-2 CPU instructions

54 HITACHITable 5.9

Instruction Set (cont)
Execution
State

T Bit

Instruction

Instruction CodeOperation

OR.B#imm,@(R0,GBR)

11001111iiiiiiii(R0 + GBR) | imm →(R0 + GBR)

3

—

ROTCL

Rn

0100nnnn00100100

T ← Rn ← T

1

MSB

ROTCR

Rn

0100nnnn00100101

T → Rn → T

1

LSB

ROTL

Rn

0100nnnn00000100

T ← Rn ← M S B

1

MSB

ROTR

Rn

0100nnnn00000101

LSB → Rn → T

1

LSB

RTE

0000000000101011

Delayed branch,4
stack area → PC/SR

LSB

RTS

0000000000001011

Delayed branch, PR
→ PC

2

—

SETT

0000000000011000

1→T

1

1

SHAL

Rn

0100nnnn00100000

T ← Rn ← 0

1

MSB

SHAR

Rn

0100nnnn00100001

MSB → Rn → T

1

LSB

SHLL

Rn

0100nnnn00000000

T ← Rn ← 0

1

MSB

SHLL2

Rn

0100nnnn00001000

Rn<<2 → Rn

1

—

SHLL8

Rn

0100nnnn00011000

Rn<<8 → Rn

1—

SHLL16 Rn

0100nnnn00101000

Rn<<16 → Rn

1

—

SHLR

Rn

0100nnnn00000001

0 → Rn → T

1

LSB

SHLR2

Rn

0100nnnn00001001

Rn>>2 → Rn

1

—

SHLR8

Rn

0100nnnn00011001

Rn>>8 → Rn

1—

SHLR16 Rn

0100nnnn00101001

Rn>>16 → Rn

1

—

SLEEP

0000000000011011

Sleep

3

—

STC

GBR,Rn

0000nnnn00010010

GBR → Rn

1

—

STC

SR,Rn

0000nnnn00000010

SR → Rn

1—STC

VBR,Rn

0000nnnn00100010

VBR → Rn

1

—

STC.L

GBR,@–Rn

0100nnnn00010011

Rn–4 → Rn, GBR→ (Rn)

2

—

STC.L

SR,@–Rn

0100nnnn00000011

Rn–4 → Rn, SR →
(Rn)

2

—

STC.L

VBR,@–Rn

0100nnnn00100011

Rn–4 → Rn, VBR→ (Rn)

2—STS

MACH,Rn

0000nnnn00001010

MACH → Rn

1—

HITACHI 55

Table 5.9

Instruction Set (cont)

Instruction

Instruction CodeOperation

Execu
-tion
State

STS

MACL,Rn

0000nnnn00011010

MACL → Rn

1

—

STS

PR,Rn

0000nnnn00101010

PR → Rn

1

—

STS.L

MACH,@–Rn

0100nnnn00000010

Rn–4 → Rn,
MACH → (Rn)

1

—

STS.L

MACL,@–Rn

0100nnnn00010010

Rn–4 → Rn,
MACL → (Rn)

1

—

STS.L

PR,@–Rn

0100nnnn00100010

Rn–4 → Rn, PR →
(Rn)

1

—

SUB

Rm,Rn

0011nnnnmmmm1000

Rn–Rm → Rn

1

—

SUBC

Rm,Rn

0011nnnnmmmm1010

Rn–Rm–T → Rn,
Borrow → T

1

Borrow

SUBV

Rm,Rn

0011nnnnmmmm1011

Rn–Rm → Rn,
Underflow → T

1

Underflow

SWAP.B Rm,Rn

0110nnnnmmmm1000

Rm → Swap
upper and lower 2
bytes→ Rn

1—

SWAP.W Rm,Rn

0110nnnnmmmm1001

Rm → Swap upperand lower word →
Rn

1

—

TAS.B

@Rn

0100nnnn00011011

If (Rn) is 0, 1 → T;
1 → MSB of (Rn)4

Testresult

TRAPA

#imm

11000011iiiiiiii

PC/SR → stackarea, (imm × 4 +VBR) → PC

8

—

TST

#imm,R0

11001000iiiiiiii

R0 & imm; if theresult is 0, 1 → T

1Test
resultTST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm; if theresult is 0, 1 → T

1Test
resultTST.B#imm,@(R0,GBR)

11001100iiiiiiii(R0 + GBR) & imm;
if the result is 0, 1
→T

3

Test
resultXOR#imm,R0

11001010iiiiiiii

R0 ^ imm → R0

1

—

XOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm → Rn

1

—

XOR.B

#imm,@(R0,GBR)

11001110iiiiiiii(R0 + GBR) ^ imm→ (R0 + GBR)

3

—

XTRCT

Rm,Rn

0010nnnnmmmm1101

Center 32 bits of
Rm and Rn → Rn

1—

56 HITACHIT Bit

Section 6 Instruction Descriptions
This section describes instructions in alphabetical order using the format shown below insection 6.1. The actual descriptions begin at section 6.2.

6.1

Sample Description (Name): Classification

Class: Indicates if the instruction is a delayed branch instruction or interrupt disabled
instruction
FormatAbstract

Code

State

T Bit

Assembler input
format; imm and disp
are numbers,
expressions, or
symbols

A brief description ofoperation

Displayed inorder MSB to
LSB

Number ofstates when
there is no
wait state

The value ofT bit afterthe
instruction is
executed

Description: Description of operation
Notes: Notes on using the instruction
Operation: Operation written in C language. This part is just a reference to help
understanding of an operation. The following resources should be used.
• Reads data of each length from address Addr. An address error will occur if word data isread from an address other than 2n or if longword data is read from an address other than
4n:unsigned char

Read_Byte(unsigned long Addr);

unsigned short Read_Word(unsigned long Addr);
unsigned long Read_Long(unsigned long Addr);• Writes data of each length to address Addr. An address error will occur if word data is
written to an address other than 2n or if longword data is written to an address other than
4n:unsigned char

Write_Byte(unsigned long Addr, unsigned long Data);

unsigned short Write_Word(unsigned long Addr, unsigned long Data);
unsigned long Write_Long(unsigned long Addr, unsigned long Data);• Starts execution from the slot instruction located at an address (Addr – 4). For Delay_Slot(4);, execution starts from an instruction at address 0 rather than address 4. The following
instructions are detected before execution as illegal slot instruction (they become illegal
slot instructions when used as delay slot instructions):
BF, BT, BRA, BSR, JMP, JSR, RTS, RTE, TRAPA, BF/S, BT/S, BRAF, BSRF

HITACHI 57

Delay_Slot(unsigned long Addr);• List registers:
unsigned long R[16];unsigned long SR,GBR,VBR;
unsigned long MACH,MACL,PR;
unsigned long PC;• Definition of SR structures:
struct SR0 {unsigned long dummy0:22;
unsigned long M0:1;
unsigned long Q0:1;
unsigned long I0:4;
un signed long dummy1:2;
unsigned long S0:1;
unsigned long T0:1;};• Definition of bits in SR:#define M ((*(struct SR0 *)(&SR)).M0)#define Q ((*(struct SR0 *)(&SR)).Q0)#define S ((*(struct SR0 *)(&SR)).S0)#define T ((*(struct SR0 *)(&SR)).T0)• Error display function:
Error( char *er );The PC should point to the location four bytes (the second instruction) after the current
instruction. Therefore, PC = 4; means the instruction starts execution from address 0, notaddress 4.
Examples: Examples are written in assembler mnemonics and describe state before and after
executing the instruction. Characters in italics such as .align are assembler control
instructions (listed below). For more information, see the Cross Assembler User's Manual.

58 HITACHI

.org.data.w.data.l.sdata.align 2.align 4.arepeat 16.arepeat 32.aendrLocation counter set
Securing integer word data
Securing integer longword data
Securing string data
2-byte boundary alignment
2-byte boundary alignment
16-repeat expansion
32-repeat expansion
End of repeat expansion of specified number

Note: The SH-series cross assembler version 1.0 does not support the conditional
assembler functions.
Notes: 1. In the assembler descriptions in this manual for addressing modes that involve thefollowing displacements (disp), the value prior to scaling (x1, x2, x4) according tothe operand size is written. This is done to show clearly the operation of the LSI;
see the assembler notation rules for the actual assembler descriptions.
@(disp:4, Rn): Register indirect with displacement@(disp:8, GBR):
GBR indirect with displacement@(disp 8, PC): PC relative with displacement
disp:8, disp:12: PC relative
2. Among the 16 bits of the instruction code, a code not assigned as an instruction istreated as a general illegal instruction, and will result in illegal instruction
exception processing, This includes the case where an instruction code for the SH2 CPU only is executed on the SH-1 CPU.
Example 1: H'FFF[General illegal instruction in both SH-1 and SH-2 CPU]
Example 2: H'3105(=DMUL.L R0, R1)[Illegal instruction in SH-1 CPU]
3. If the instruction following a delayed branch instruction such as BRA, BT/S, etc.,
is a general illegal instruction or a branch instruction (known as a slot illegal
instruction), illegal instruction exception processing will be performed.
Example 1....
BRA Label. data. W H'FFFF ← Slot illegal instruction....
[H'FFF is fundamentally a general illegal
instruction]
Example 2
RTE
BT/S Label ← Slot illegal instruction

HITACHI 59

6.2

ADD (ADD Binary): Arithmetic Instruction

FormatAbstract

Code

State

T Bit

ADD

Rm,Rn

Rm + Rn → Rn

0011nnnnmmmm1100

1

—

ADD

#imm,Rn

Rn + imm → Rn

0111nnnniiiiiiii

1—

Description: Adds general register Rn data to Rm data, and stores the result in Rn. The
contents of Rn can also be added to 8-bit immediate data. Since the 8-bit immediate data issign-extended to 32 bits, this instruction can add and subtract immediate data.
Operation:
ADD(long m,long n)/* ADD Rm,Rn */{R[n]+=R[m];PC+=2;}ADDI(long i,long n) /* ADD #imm,Rn */{if ((i&0x80)==0) R[n]+=(0x000000FF & (long)i);
else R[n]+=(0xFFFFFF00 | (long)i);PC+=2;}

Examples:
ADD

ADD

ADD

R0,R1

#H'01,R2#H'FE,R3

60 HITACHI

Before execution

R0 = H'7FFFFFFF, R1 = H'00000001

After execution

R1 = H'80000000

Before execution

R2 = H'00000000

After execution

R2 = H'00000001

Before execution

R3 = H'00000001

After execution

R3 = H'FFFFFFFF

6.3

ADDC (ADD with Carry): Arithmetic Instruction

FormatADDC

Rm,Rn

Abstract

Code

State

T Bit

Rn + Rm + T → Rn, carry → T

0011nnnnmmmm1110

1

Carry

Description: Adds general register Rm data and the T bit to Rn data, and stores the result in
Rn. The T bit changes according to the result. This instruction can add data that has morethan 32 bits.
Operation:
ADDC (long m,long n)/* ADDC Rm,Rn */{unsigned long tmp0,tmp1;

tmp1=R[n]+R[m];tmp0=R[n];R[n]=tmp1+T;
if (tmp0>tmp1) T=1;
else T=0;
if (tmp1>R[n]) T=1;
PC+=2;}

Examples:
CLRT
ADDC

R3,R1

ADDC

R2,R0

R0:R1 (64 bits) + R2:R3 (64 bits) = R0:R1 (64 bits)
Before execution
T = 0, R1 = H'00000001, R3 = H'FFFFFFFF
After execution
T = 1, R1 = H'0000000
Before execution
T = 1, R0 = H'00000000, R2 = H'00000000
After execution
T = 0, R0 = H'00000001

HITACHI 61

6.4

ADDV (ADD with V Flag Overflow Check): Arithmetic Instruction

FormatADDV

Rm,Rn

Abstract

Code

State

T Bit

Rn + Rm → Rn, overflow → T

0011nnnnmmmm1111

1

Overflow

Description: Adds general register Rn data to Rm data, and stores the result in Rn. If an
overflow occurs, the T bit is set to 1.
Operation:
ADDV(long m,long n)/*ADDV Rm,Rn */{long dest,src,ans;if ((long)R[n]>=0) dest=0;
else dest=1;
if ((long)R[m]>=0) src=0;
else src=1;
src+=dest;
R[n]+=R[m];if ((long)R[n]>=0) ans=0;
else ans=1;
ans+=dest;if (s rc==0 || src==2) {if (ans==1) T=1;
else T=0;}
else T=0;
PC+=2;}

Examples:
ADDV

R0,R1

ADDV

R0,R1

62 HITACHI

Before execution
After execution
Before execution
After execution

R0 = H'00000001, R1 = H'7FFFFFFE, T = 0
R1 = H'7FFFFFFF, T = 0
R0 = H'00000002, R1 = H'7FFFFFFE, T = 0
R1 = H'80000000, T = 1

6.5

AND (AND Logical): Logic Operation Instruction

FormatAbstract

Code

State

T
Bit

AND

Rm,Rn

Rn & Rm → Rn

0010nnnnmmmm1001

1

—

AND

#imm,R0

R0 & imm → R0

11001001iiiiiiii

1—(R0 + GBR) & imm → (R0 +GBR)

11001101iiiiiiii

3

—

AND.B
#imm,@(R0,GBR)

Description: Logically ANDs the contents of general registers Rn and Rm, and stores theresult in Rn. The contents of general register R0 can be ANDed with zero-extended 8-bit
immediate data. 8-bit memory data pointed to by GBR relative addressing can be ANDed
with 8-bit immediate data.
Note: After AND #imm, R0 is executed and the upper 24 bits of R0 are always cleared to 0.
Operation:AND(long m,long n)/* AND Rm,Rn */{R[n]&=R[m]PC+=2;}
ANDI(long i) /* AND #imm,R0 */{R[0]&=(0x000000FF & (long)i);PC+=2;}ANDM(long i) /* AND.B #imm,@(R0,GBR) */{long temp;

temp=(long)Read_Byte(GBR+R[0]);temp&=(0x000000FF & (long)i);
Write_Byte(GBR+R[0],temp);
PC+=2;}HITACHI 63

Examples:
Before execution
After execution
AND #H'0F,R0
Before execution
After execution
AND.B #H'80,@(R0,GBR) Before execution
After execution
AND R0,R1

64 HITACHI

R0 = H'AAAAAAAA, R1 = H'55555555
R1 = H'00000000
R0 = H'FFFFFFFF
R0 = H'0000000F@(R0,GBR) = H'A5@(R0,GBR) = H'80

6.6

BF (Branch if False): Branch Instruction

Format
BF
la

Abstract

Code

State

T Bit

When T = 0, disp × 2 + PC → PC;
When T = 1, nop

10001011dddddddd

3/1

—

bel

Description: Reads the T bit, and conditionally branches. If T = 1, BF executes the next
instruction. If T = 0, it branches. The branch destination is an address specified by PC +displacement. The PC points to the starting address of the second instruction after the branch
instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relativeinterval from the branch destination is –256 to +254 bytes. If the displacement is too short toreach the branch destination, use BF with the BRA instruction or the like.
Note: When branching, three cycles; when not branching, one cycle.
Operation:
BF(long d) /* BF disp */{long disp;if ((d&0x80)==0) disp=(0x000000FF & (long)d);else disp=(0xFFFFFF00 | (long)d);if (T==0) PC=PC+(disp<<1)+4;
else PC+=2;}

Example:CLRT
BT

TRGET_T

BF

TRGET_F

T is always cleared to 0
Does not branch, because T = 0
Branches to TRGET_F, because T = 0

NOP
NOP

← The PC location is used to calculate thebranch destination address of the BF
instruction

TRGET_F:← Branch destination of the BF instruction

HITACHI 65

6.7

BF/S (Branch if False with Delay Slot): Branch Instruction (SH-2
CPU)

FormatAbstract

Code

State

T Bit

BF/S
label

When T = 0, disp × 2 + PC → PC;
When T = 1, nop

10001111dddddddd

2/1—

Description: Reads the T bit, and conditionally branches with delay slot. If T = 1, BF
executes the next instruction. If T = 0, it branches after executing the next instruction. The
branch destination is an address specified by PC + displacement. The PC points to thestarting address of the second instruction after the branch instruction. The 8-bit displacement
is sign-extended and doubled. Consequently, the relative interval from the branch destinationis –256 to +254 bytes. If the displacement is too short to reach the branch destination, use
BF/S with the BRA instruction or the like.
Note: Since this is a delayed branch instruction, the instruction immediately after is executed
before the branch. Between the time this instruction and the instruction immediately after are
executed, address errors or interrupts are not accepted. When the instruction immediately
after is a branch instruction, it is recognized as an illegal slot instruction.
When branching, this is a two-cycle instruction; when not branching, one cycle.
Operation:
BFS(long d)/* BFS disp */{long disp;
unsigned long temp;

temp=PC;if ((d&0x80)==0) disp=(0x000000FF & (long)d);else disp=(0xFFFFFF00 | (long)d);if (T==0) {PC=PC+(disp<<1)+4;
Delay_Slot(temp+2);}
else PC+=2;}66 HITACHIExample:
CLRT
BT/S TRGET_T

T is always 0
Does not branch, because T = 0

NOP
BF/S TRGET_F
ADD
NOP
TRGET_F:

R0,R1

Branches to TRGET, because T = 0
Executed before branch← The PC location is used to calculate the branch destination
address of the BF/S instruction← Branch destination of the BF/S instruction

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the registerprior to the change as the branch destination address.

HITACHI 67

6.8

BRA (Branch): Branch Instruction

Format
BRA

label

Abstract

Code

State

T Bit

disp × 2 + PC → PC

1010dddddddddddd2—

Description: Branches unconditionally after executing the instruction following this BRA
instruction. The branch destination is an address specified by PC + displacement. The PC
points to the starting address of the second instruction after this BRA instruction. The 12-bit
displacement is sign-extended and doubled. Consequently, the relative interval from thebranch destination is –4096 to +4094 bytes. If the displacement is too short to reach thebranch destination, this instruction must be changed to the JMP instruction. Here, a MOV
instruction must be used to transfer the destination address to a register.
Note: Since this is a delayed branch instruction, the instruction after BRA is executed before
branching. No interrupts or address errors are accepted between this instruction and the next
instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal slot
instruction.
Operation:
BRA(long d)/* BRA disp */{unsigned long temp;

long disp;if ((d&0x800)==0) disp=(0x00000FFF & d);else disp=(0xFFFFF000 | d);temp=PC;
PC=PC+(disp<<1)+4;
Delay_Slot(temp+2);}

Example:
BRA
ADD
NOP
TRGET:

Branches to TRGET
R0,R1 Executes ADD before branching← The PC location is used to calculate the branch destination
address of the BRA instruction← Branch destination of the BRA instruction
TRGET

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order of

68 HITACHI

delayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the register prior
to the change as the branch destination address.

HITACHI 69

6.9

BRAF (Branch Far): Branch Instruction (SH-2 CPU)

Format
BRAF

Rm

Abstract

Code

State

T Bit

Rm + PC → PC

0000mmmm00100011

2—

Description: Branches unconditionally. The branch destination is PC + the 32-bit contents ofthe general register Rm. PC is the start address of the second instruction after this instruction.
Note: Since this is a delayed branch instruction, the instruction after BRAF is executed
before branching. No interrupts or address errors are accepted between this instruction and thenext instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal
slot instruction.
Operation:
BRAF(long m) /* BRAF Rm */{unsigned long temp;

temp=PC;
PC+=R[m];Delay_Slot(temp+2);}

Example:MOV.L#(TRGET-BSRF_PC),R0

BRAF

@R0

ADD

R0,R1

BRAF_PC:

Sets displacement
Branches to TRGET
Executes ADD before branching← The PC location is used to calculate
the branch destination address of
the BRAF instruction

NOP
TRGET:

70 HITACHI← Branch destination of the BRAF instruction

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the register prior
to the change as the branch destination address.

HITACHI 71

6.10

BSR (Branch to Subroutine): Branch Instruction

Format
BSR

Abstract
label

Code

PC → PR, disp × 2 + PC → PC 1011dddddddddddd

State

T Bit

2

—

Description: Branches to the subroutine procedure at a specified address after executing the
instruction following this BSR instruction. The PC value is stored in the PR, and the program
branches to an address specified by PC + displacement. The PC points to the starting addressof the second instruction after this BSR instruction. The 12-bit displacement is sign-extended
and doubled. Consequently, the relative interval from the branch destination is –4096 to+4094 bytes. If the displacement is too short to reach the branch destination, the JSR
instruction must be used instead. With JSR, the destination address must be transferred to aregister by using the MOV instruction. This BSR instruction and the RTS instruction are used
for a subroutine procedure call.
Note: Since this is a delayed branch instruction, the instruction after BSR is executed before
branching. No interrupts or address errors are accepted between this instruction and the next
instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal slot
instruction.
Operation:
BSR(long d)/* BSR disp */{long disp;if ((d&0x800)==0) disp=(0x00000FFF & d);else disp=(0xFFFFF000 | d);
PR=PC;
PC=PC+(disp<<1)+4;
Delay_Slot(PR+2);}

72 HITACHIExample:
BSR

TRGET

MOV

R3,R4

ADD

R0,R1

Branches to TRGET
Executes the MOV instruction before branching← The PC location is used to calculate the branch destination
address of the BSR instruction (return address for when thesubroutine procedure is completed (PR data)).......
.......
← Procedure entrance

TRGET:
MOV

R2,R3

RTS
MOV #1,R0

Returns to the above ADD instruction
Executes MOV before branching

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the register prior
to the change as the branch destination address.

HITACHI 73

6.11

BSRF (Branch to Subroutine Far): Branch Instruction (SH-2 CPU)

Format
BSRF

Rm

Abstract

Code

State

T Bit

PC → PR, Rm + PC → PC

0000mmmm00000011

2—

Description: Branches to the subroutine procedure at a specified address after executing the
instruction following this BSRF instruction. The PC value is stored in the PR. The branch
destination is PC + the 32-bit contents of the general register Rm. PC is the start address ofthe second instruction after this instruction. Used as a subroutine procedure call in
combination with RTS.
Note: Since this is a delayed branch instruction, the instruction after BSR is executed before
branching. No interrupts or address errors are accepted between this instruction and the next
instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal slot
instruction.
Operation:
BSRF(long m) /* BSRF Rm */{PR=PC;
PC+=R[m];Delay_Slot(PR+2);}

Example:MOV.L #(TRGET-BSRF_PC),R0
BRSF
@R0
MOV
R3,R4
BSRF_PC:

ADD

Sets displacement
Branches to TRGET
Executes the MOV instruction before
branching← The PC location is used to
calculate the branch destination
with BSRF

R0,R1

.....
.....
← Procedure entrance

TRGET:
MOV

R2,R3

RTS
MOV #1,R0

Returns to the above ADD instruction
Executes MOV before branching

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order of delayedbranch instruction, then delay slot instruction. For example, even if the register in which
the branch destination address has been loaded is changed by the delay slot instruction,
the branch will still be made using the value of the register prior to the change as thebranch destination address.

74 HITACHI6.12

BT (Branch if True): Branch Instruction

FormatBT

label

Abstract

Code

State

T Bit

When T = 1, disp × 2 + PC →PC;
When T = 0, nop

10001001dddddddd

3/1—

Description: Reads the T bit, and conditionally branches. If T = 1, BT branches. If T = 0, BT
executes the next instruction. The branch destination is an address specified by PC +displacement. The PC points to the starting address of the second instruction after the branch
instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relativeinterval from the branch destination is –256 to +254 bytes. If the displacement is too short toreach the branch destination, use BT with the BRA instruction or the like.
Note: When branching, requires three cycles; when not branching, one cycle.
Operation:
BT(long d) /* BT disp */{long disp;if ((d&0x80)==0) disp=(0x000000FF & (long)d);else disp=(0xFFFFFF00 | (long)d);if (T==1) PC=PC+(disp<<1)+4;
else PC+=2;}

Example:SETT
BF

TRGET_FBT

TRGET_T

T is always 1
Does not branch, because T = 1
Branches to TRGET_T, because T = 1

NOP
NOP
TRGET_T:← The PC location is used to calculate the branch destination

address of the BT instruction← Branch destination of the BT instruction

HITACHI 75

6.13

BT/S (Branch if True with Delay Slot): Branch Instruction (SH-2
CPU)

FormatBT/S

label

Abstract

Code

State

T Bit

When T = 1, disp × 2 + PC →PC;
When T = 0, nop

10001101dddddddd

2/1—

Description: Reads the T bit, and conditionally branches with delay slot. If T = 1, BT/S
branches after the following instruction executes. If T = 0, BT/S executes the next instruction.
The branch destination is an address specified by PC + displacement. The PC points to thestarting address of the second instruction after the branch instruction. The 8-bit displacement
is sign-extended and doubled. Consequently, the relative interval from the branch destinationis –256 to +254 bytes. If the displacement is too short to reach the branch destination, use
BT/S with the BRA instruction or the like.
Note: Since this is a delay branch instruction, the instruction immediately after is executed
before the branch. Between the time this instruction and the immediately after instruction are
executed, address errors or interrupts are not accepted. When the immediately after
instruction is a branch instruction, it is recognized as an illegal slot instruction. Whenbranching, requires two cycles; when not branching, one cycle.
Operation:
BTS(long d)/* BTS disp */{long disp;
unsignedlong temp;

temp=PC;if ((d&0x80)==0) disp=(0x000000FF & (long)d);else disp=(0xFFFFFF00 | (long)d);if (T==1) {PC=PC+(disp<<1)+4;
Delay_Slot(temp+2);}
else PC+=2;}76 HITACHIExample:
T is always 1
BF/S TRGET_F Does not branch, because T = 1
SETT

NOP
BT/S TRGET_T Branches to TRGET, because T = 1
ADD
NOP
TRGET_T:

R0,R1

Executes before branching.
← The PC location is used to calculate the branch destination
address of the BT/S instruction← Branch destination of the BT/S instruction

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the registerprior to the change as the branch destination address.

HITACHI 77

6.14

CLRMAC (Clear MAC Register): System Control Instruction

FormatAbstract

Code

State

T Bit

CLRMAC

0 → MACH, MACL

0000000000101000

1—

Operation:
CLRMAC()/* CLRMAC */{MACH=0;
MACL=0;
PC+=2;}

Example:
CLRMAC
MAC.W
MAC.W@R0+,@R1+@R0+,@R1+

78 HITACHI

Initializes the MAC register
Multiply and accumulate operation

6.15

CLRT (Clear T Bit): System Control Instruction

FormatAbstract

Code

State

T Bit

CLRT

0→T

0000000000001000

10

Description: Clears the T bit.
Operation:
CLRT() /* CLRT */{T=0;
PC+=2;}

Example:
CLRT

Before execution
After execution

T=1
T=0

HITACHI 79

6.16

CMP/cond (Compare Conditionally): Arithmetic Instruction

FormatAbstract

Code

State

T Bit

CMP/EQ Rm,Rn

When Rn = Rm, 1 → T

0011nnnnmmmm0000

1

Comparison
result

CMP/GE Rm,Rn

When signed and Rn ≥Rm, 1 → T

0011nnnnmmmm0011

1

Comparison
result

CMP/GT Rm,Rn

When signed and Rn >Rm, 1 → T

0011nnnnmmmm0111

1

Comparison
result

CMP/HI Rm,Rn

When unsigned and Rn >Rm, 1 → T

0011nnnnmmmm0110

1

Comparison
result

CMP/HS Rm,Rn

When unsigned and Rn ≥Rm, 1 → T

0011nnnnmmmm0010

1

Comparison
result

CMP/PL R n

When Rn > 0, 1 → T

0100nnnn00010101

1

Comparison
result

CMP/PZ R n

When Rn ≥ 0, 1 → T

0100nnnn00010001

1

Comparison
result

CMP/STR
Rm,Rn

When a byte in Rn equals
a byte in Rm, 1 → T

0010nnnnmmmm1100

1

Comparison
resultWhen R0 = imm, 1 → T

10001000iiiiiiii

1

Comparison
result

CMP/EQ #imm,R0

Description: Compares general register Rn data with Rm data, and sets the T bit to 1 if a
specified condition (cond) is satisfied. The T bit is cleared to 0 if the condition is notsatisfied. The Rn data does not change. The following eight conditions can be specified.
Conditions PZ and PL are the results of comparisons between Rn and 0. Sign-extended 8-bit
immediate data can also be compared with R0 by using condition EQ. Here, R0 data does notchange. Table 6.1 shows the mnemonics for the conditions.

80 HITACHITable 6.1

CMP Mnemonics

Mnemonics

Condition

CMP/EQ Rm,Rn

If Rn = Rm, T = 1

CMP/GE Rm,Rn

If Rn ≥ Rm with signed data, T = 1

CMP/GT Rm,Rn

If Rn > Rm with signed data, T = 1

CMP/HI Rm,Rn

If Rn > Rm with unsigned data, T = 1

CMP/HS Rm,Rn

If Rn ≥ Rm with unsigned data, T = 1

CMP/PL Rn

If Rn > 0, T = 1

CMP/PZ Rn

If Rn ≥ 0, T = 1

CMP/STR Rm,Rn

If a byte in Rn equals a byte in Rm, T = 1

CMP/EQ #imm,R0

If R0 = imm, T = 1

Operation:
CMPEQ(long m,long n)/* CMP_EQ Rm,Rn */{if (R[n]==R[m]) T=1;
else T=0;
PC+=2;}CMPGE(long m,long n)/* CMP_GE Rm,Rn */{if ((long)R[n]>=(long)R[m]) T=1;
else T=0;
PC+=2;}
CMPGT(long m,long n)/* CMP_GT Rm,Rn */{if ((long)R[n]>(long)R[m]) T=1;
else T=0;
PC+=2;}HITACHI 81

CMPHI(long m,long n)/* CMP_HI Rm,Rn */{if ((unsigned long)R[n]>(unsigned long)R[m]) T=1;
else T=0;
PC+=2;}CMPHS(long m,long n)/* CMP_HS Rm,Rn */{if ((unsigned long)R[n]>=(unsigned long)R[m]) T=1;
else T=0;
PC+=2;}
CMPPL(long n)/* CMP_PL Rn */{if ((long)R[n]>0) T=1;
else T=0;
PC+=2;}CMPPZ(long n) /* CMP_PZ Rn */{if ((long)R[n]>=0) T=1;
else T=0;
PC+=2;}

82 HITACHICMPSTR(long m,long n)/* CMP_STR Rm,Rn */{unsigned long temp;
long HH,HL,LH,LL;

temp=R[n]^R[m];HH=(temp>>12)&0x000000FF;
HH=(temp>>8)&0x000000FF;
HH=(temp>>4)&0x000000FF;
LL=temp&0x000000FF;
HH=HH&&HL&&LH&&LL;
if (HH==0) T=1;
else T=0;
PC+=2;}CMPIM(long i)/* CMP_EQ #imm,R0 */{long imm;

if ((i&0x80)==0) imm=(0x000000FF & (long i));else imm=(0xFFFFFF00 | (long i));if (R[0]==imm) T=1;
else T=0;
PC+=2;}

Example:
CMP/GE

R0,R1

BT

TRGET_T

CMP/HS

R0,R1

BT

TRGET_T

CMP/STR

R2,R3

B T TRGET_T

R0 = H'7FFFFFFF, R1 = H'80000000
Does not branch because T = 0
R0 = H'7FFFFFFF, R1 = H'80000000
Branches because T = 1
R2 = “ABCD”, R3 = “XYCZ”
Branches because T = 1

HITACHI 83

6.17

DIV0S (Divide Step 0 as Signed): Arithmetic Instruction

Format
DIV0S

Rm,Rn

Abstract

Code

State

T Bit

MSB of Rn → Q, MSB of Rm→ M, M^Q → T

0010nnnnmmmm0111

1

Calculation
resultDescription: DIV0S is an initialization instruction for signed division. It finds the quotient by
repeatedly dividing in combination with the DIV1 or another instruction that divides for each
bit after this instruction. See the description given with DIV1 for more information.
Operation:
DIV0S(long m,long n)/* DIV0S Rm,Rn */{if ((R[n]&0x80000000)==0) Q=0;
else Q=1;
if ((R[m]&0x80000000)==0) M=0;else M=1;
T=!(M==Q);
PC+=2;}

Example: See DIV1.

84 HITACHI6.18

DIV0U (Divide Step 0 as Unsigned): Arithmetic Instruction

FormatAbstract

Code

State

T Bit

DIV0U

0 → M/Q/T

0000000000011001

10

Description: DIV0U is an initialization instruction for unsigned division. It finds the quotient
by repeatedly dividing in combination with the DIV1 or another instruction that divides foreach bit after this instruction. See the description given with DIV1 for more information.
Operation:
DIV0U()/* DIV0U */{M=Q=T=0;
PC+=2;}

Example: See DIV1.

HITACHI 85

6.19

DIV1 (Divide Step 1): Arithmetic Instruction

FormatDIV1

Rm,Rn

Abstract

Code

State

T Bit

1-step division (Rn ÷ Rm)

0011nnnnmmmm0100

1

Calculation
resultDescription: Uses single-step division to divide one bit of the 32-bit data in general register
Rn (dividend) by Rm data (divisor). It finds a quotient through repetition either independently
or used in combination with other instructions. During this repetition, do not rewrite thespecified register or the M, Q, and T bits.
In one-step division, the dividend is shifted one bit left, the divisor is subtracted and thequotient bit reflected in the Q bit according to the status (positive or negative). To find theremainder in a division, first find the quotient using a DIV1 instruction, then find theremainder as follows:(Dividend) – (divisor) × (quotient) = (remainder)

with the SH-2 CPU in which a divider is installed as a peripheral function, the remainder canbe found as a function of the divider.
Zero division, overflow detection, and remainder operation are not supported. Check for zero
division and overflow division before dividing.
Find the remainder by first finding the sum of the divisor and the quotient obtained and thensubtracting it from the dividend. That is, first initialize with DIV0S or DIV0U. Repeat DIV1
for each bit of the divisor to obtain the quotient. When the quotient requires 17 or more bits,
place ROTCL before DIV1. For the division sequence, see the following examples.

86 HITACHIOperation:
DIV1(long m,long n)/* DIV1 Rm,Rn */{unsigned long tmp0;
unsigned char

old_q,tmp1;

old_q=Q;
Q=(unsigned char)((0x80000000 & R[n])!=0);
R[n]<<=1;
R[n]|=(unsigned long)T;
switch(old_q){
case 0:switch(M){case 0:tmp0=R[n];R[n]-=R[m];tmp1=(R[n]>tmp0);
switch(Q){case 0:Q=tmp1;
break;
case 1:Q=(unsigned char)(tmp1==0);
break;}
break;
case 1:tmp0=R[n];R[n]+=R[m];tmp1=(R[n]<tmp0);
switch(Q){case 0:Q=(unsigned char)(tmp1==0);
break;
case 1:Q=tmp1;
break;}
break;}
break;HITACHI 87

case 1:switch(M){case 0:tmp0=R[n];R[n]+=R[m];tmp1=(R[n]<tmp0);
switch(Q){case 0:Q=tmp1;
break;
case 1:Q=(unsigned char)(tmp1==0);
break;}
break;
case 1:tmp0=R[n];R[n]-=R[m];tmp1=(R[n]>tmp0);
switch(Q){case 0:Q=(unsigned char)(tmp1==0);
break;
case 1:Q=tmp1;
break;}
break;}
break;}
T=(Q==M);
PC+=2;}

88 HITACHIExample 1:

SHLL16

R0

TST

R0,R0

BT

ZERO_DIVCMP/HS

R0,R1

BT

OVER_DIV

R1 (32 bits) / R0 (16 bits) = R1 (16 bits):Unsigned
Upper 16 bits = divisor, lower 16 bits = 0
Zero division check
Overflow check
Flag initialization

DIV0U.arepeat

16

DIV1

R0,R1

Repeat 16 times.aendr
ROTCL

R1

EXTU.W R1,R2

R1 = Quotient

Example 2:

TST

R0,R0

BT

ZERO_DIVCMP/HS

R0,R1

BT

OVER_DIV

R1:R2 (64 bits)/R0 (32 bits) = R2 (32 bits):Unsigned
Zero division check
Overflow check
Flag initialization

DIV0U.arepeat

32

ROTCL

R2

DIV1

R0,R1

Repeat 32 times.aendr
ROTCL

R2

R2 = Quotient

HITACHI 89

Example 3:

SHLL16

R0

EXTS.W

R1,R1

XOR

R2,R2

MOV

R1,R3

ROTCL

R3

SUBC

R2,R1

DIV0S

R0,R1

.arepeat

16

DIV1

R0,R1

R1 (16 bits)/R0 (16 bits) = R1 (16 bits):Signed
Upper 16 bits = divisor, lower 16 bits = 0
Sign-extends the dividend to 32 bits
R2 = 0Decrements if the dividend is negative
Flag initialization
Repeat 16 times.aendr
EXTS.W

R1,R1

ROTCL

R1

ADDC

R2,R1

EXTS.W R1,R1

R1 = quotient (one’ s complement)
Increments and takes the two’ s complement if the MSB of thequotient is 1
R1 = quotient (two’s complement)

Example 4:
R2 (32 bits) / R0 (32 bits) = R2 (32 bits):Signed
MOV

R2,R3

ROTCL

R3

SUBC

R1,R1

XOR

R3,R3

SUBC

R3,R2

DIV0S

R0,R1

.arepeat

32

ROTCL

R2

DIV1

R0,R1

Sign-extends the dividend to 64 bits (R1:R2)
R3 = 0Decrements and takes the one’ s complement if the dividend isnegative
Flag initialization
Repeat 32 times.aendr
ROTCL

R2

ADDC

R3,R2

90 HITACHI

R2 = Quotient (one’s complement)
Increments and takes the two’s complement if the MSB of thequotient is 1. R2 = Quotient (two’s complement)

6.20

DMULS.L (Double-Length Multiply as Signed): Arithmetic
Instruction (SH-2 CPU)

FormatAbstract

Code

State

T Bit

DMULS.L
Rm,Rn

With signed, Rn × Rm →MACH, MACL

0011nnnnmmmm1101

2 to 4—

Description: Performs 32-bit multiplication of the contents of general registers Rn and Rm,
and stores the 64-bit results in the MACL and MACH registers. The operation is a signed
arithmetic operation.
Operation:
DMULS(long m,long n) /* DMULS.L Rm,Rn */{unsignedlong RnL,RnH,RmL,RmH,Res0,Res1,Res2;

unsignedlong temp0,temp1,temp2,temp3;

long tempm,tempn,fnLmL;

tempn=(long)R[n];tempm=(long)R[m];if (tempn<0) tempn=0-tempn;
if (tempm<0) tempm=0-tempm;
if ((long)(R[n]^R[m])<0) fnLmL=-1;
else fnLmL=0;

temp1=(unsigned long)tempn;
temp2=(unsigned long)tempm;

RnL=temp1&0x0000FFFF;
RnH=(temp1>>16)&0x0000FFFF;
RmL=temp2&0x0000FFFF;
RmH=(temp2>>16)&0x0000FFFF;

temp0=RmL*RnL;
temp1=RmH*RnL;
temp2=RmL*RnH;
temp3=RmH*RnH;

HITACHI 91

Res2=0
Res1=temp1+temp2;
if (Res1<temp1) Res2+=0x00010000;

temp1=(Res1<<16)&0xFFFF0000;
Res0=temp0+temp1;
if (Res0<temp0) Res2++;

Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3;

if (fnLmL<0) {Res2=~Res2;
if (Res0==0)Res2++;
else
Res0=(~Res0)+1;}
MACH=Res2;
MACL=Res0;
PC+=2;}

Example:
DMULS

R0,R1

STS

MACH,R0

STS MACL,R0

92 HITACHI

Before execution R0 = H'FFFFFFFE, R1 = H'00005555
After execution MACH = H'FFFFFFFF, MACL = H'FFFF5556
Operation result (top)Operation result (bottom)

6.21

DMULU.L (Double-Length Multiply as Unsigned): Arithmetic
Instruction (SH-2 CPU)

FormatAbstract

Code

State

T Bit

DMULU.L
Rm,Rn

Without signed, Rn × Rm →MACH, MACL

0011nnnnmmmm0101

2 to 4—

Description: Performs 32-bit multiplication of the contents of general registers Rn and Rm,
and stores the 64-bit results in the MACL and MACH registers. The operation is an unsigned
arithmetic operation.
Operation:
DMULU(long m,long n) /* DMULU.L Rm,Rn */{unsignedlong RnL,RnH,RmL,RmH,Res0,Res1,Res2;

unsignedlong temp0,temp1,temp2,temp3;

RnL=R[n]&0x0000FFFF;
RnH=(R[n]>>16)&0x0000FFFF;

RmL=R[m]&0x0000FFFF;
RmH=(R[m]>>16)&0x0000FFFF;

temp0=RmL*RnL;
temp1=RmH*RnL;
temp2=RmL*RnH;
temp3=RmH*RnH;

HITACHI 93

Res2=0
Res1=temp1+temp2;
if (Res1<temp1) Res2+=0x00010000;

temp1=(Res1<<16)&0xFFFF0000;
Res0=temp0+temp1;
if (Res0<temp0) Res2++;

Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3;

MACH=Res2;
MACL=Res0;
PC+=2;}

Example:
DMULU

R0,R1

STS

MACH,R0STS

MACL,R0

94 HITACHI

Before execution R0 = H'FFFFFFFE, R1 = H'00005555
After execution MACH = H'00005554, MACL = H'FFFF5556
Operation result (top)Operation result (bottom)

6.22

DT (Decrement and Test): Arithmetic Instruction (SH-2 CPU)

FormatDT

Rn

Abstract

Code

State

T Bit

Rn - 1 → Rn;
When Rn is 0, 1 → T,
when Rn is nonzero, 0 → T

0100nnnn00010000

1Comparison
resultDescription: The contents of general register Rn is decremented by 1 and the result iscompared to 0 (zero). When the result is 0, the T bit is set to 1. When the result is not zero,
the T bit is set to 0.
Operation:
DT(long n) /* DT Rn */{R[n]--;
if (R[n]==0) T=1;
else T=0;
PC+=2;}

Example:MOV#4,R5 Sets the number of loops.

LOOP:
ADD

R0,R1

DT

RS

BF

LOOP

Decrements the R5 value and checks whether it has become 0.
Branches to LOOP if T=0. (In this example, loops 4 times.)

HITACHI 95

6.23

EXTS (Extend as Signed): Arithmetic Instruction

FormatAbstract

Code

State

T Bit

EXTS.B Rm,Rn

Sign-extended Rm from byte →Rn

0110nnnnmmmm1110

1—

EXTS.W Rm,Rn

Sign-extended Rm from word →Rn

0110nnnnmmmm1111

1—

Description: Sign-extends general register Rm data, and stores the result in Rn. If byte lengthis specified, the bit 7 value of Rm is transferred to bits 8 to 31 of Rn. If word length isspecified, the bit 15 value of Rm is transferred to bits 16 to 31 of Rn.
Operation:
EXTSB(long m,long n)/* EXTS.B Rm,Rn */{R[n]=R[m];if ((R[m]&0x00000080)==0) R[n]&=0x000000FF;
else R[n]|=0xFFFFFF00;
PC+=2;}
EXTSW(long m,long n)/* EXTS.W Rm,Rn */{R[n]=R[m];if ((R[m]&0x00008000)==0) R[n]&=0x0000FFFF;
else R[n]|=0xFFFF0000;
PC+=2;}

Examples:
EXTS.B R0,R1

EXTS.W R0,R1

96 HITACHI

Before execution
After execution
Before execution
After execution

R0 = H'00000080
R1 = H'FFFFFF80
R0 = H'00008000
R1 = H'FFFF8000

6.24

EXTU (Extend as Unsigned): Arithmetic Instruction

FormatAbstract

Code

State

T Bit

EXTU.B Rm,Rn

Zero-extend Rm from byte → Rn

0110nnnnmmmm1100

1—

EXTU.W Rm,Rn

Zero-extend Rm from word → Rn 0110nnnnmmmm1101

1—

Description: Zero-extends general register Rm data, and stores the result in Rn. If byte lengthis specified, 0 is transferred to bits 8 to 31 of Rn. If word length is specified, 0 is transferred tobits 16 to 31 of Rn.
Operation:
EXTUB(long m,long n) /* EXTU.B Rm,Rn */{R[n]=R[m];R[n]&=0x000000FF;
PC+=2;}EXTUW(long m,long n) /* EXTU.W Rm,Rn */{R[n]=R[m];R[n]&=0x0000FFFF;
PC+=2;}

Examples:
EXTU.B R0,R1

EXTU.W R0,R1

Before execution
After execution
Before execution
After execution

R0 = H'FFFFFF80
R1 = H'00000080
R0 = H'FFFF8000
R1 = H'00008000

HITACHI 97

6.25

JMP (Jump): Branch Instruction

Class: Delayed branch instruction
Format
JMP@Rm

Abstract

Code

State

T Bit

Rm → PC

0100mmmm00101011

2—

Description: Delayed-branches unconditionally to the address specified with register indirect.
The branch destination is an address specified by the 32-bit data in general register Rm.
Note: Since this is a delayed branch instruction, the instruction after JMP is executed before
branching. No interrupts or address errors are accepted between this instruction and the next
instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal slot
instruction.
Operation:
JMP(long m)/* JMP @Rm */{unsigned long temp;

temp=PC;
PC=R[m]+4;
Delay_Slot(temp+2);}

Example:JMP_TABLE:

MOV.L

JMP_TABLE,R0

JMP

@R0

MOV

R0,R1

.align4.data.l

TRGET

Address of R0 = TRGET
Branches to TRGET
Executes MOV before branching
Jump table.................
TRGET:ADD#1,R1← Branch destination

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the registerprior to the change as the branch destination address.

98 HITACHI6.26

JSR (Jump to Subroutine): Branch Instruction

Class: Delayed branch instruction
FormatJSR@Rm

Abstract

Code

State

T Bit

PC → PR, Rm → PC

0100mmmm00001011

2—

Description: Delayed-branches to the subroutine procedure at a specified address after
executing the instruction following this JSR instruction. The PC value is stored in the PR. The
jump destination is an address specified by the 32-bit data in general register Rm. The PC
points to the starting address of the second instruction after JSR. The JSR instruction and RTS
instruction are used for subroutine procedure calls.
Note: Since this is a delayed branch instruction, the instruction after JSR is executed before
branching. No interrupts and address errors are accepted between this instruction and the next
instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal slot
instruction.
Operation:
JSR(long m)/* JSR @Rm */{PR=PC;
PC=R[m]+4;
Delay_Slot(PR+2);}

Example:MOV.L

JSR_TABLE,R0

JSR

@R0

XOR

R1,R1

ADD

R0,R1

R0 = Address of TRGET
Branches to TRGET
Executes XOR before branching← Return address for when thesubroutine procedure is completed(PR data)...........

.align4

JSR_TABLE: .data.l TRGET
TRGET:

NOP
MOV

R2,R3

RTS
MOV

Jump table← Procedure entrance#70,R1Returns to the above ADD instruction
Executes MOV before RTS

HITACHI 99

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the registerprior to the change as the branch destination address.

100 HITACHI6.27

LDC (Load to Control Register): System Control Instruction

Class: Interrupt disabled instruction
FormatAbstract

Code

State

T Bit

LDC

Rm,SR

Rm → SR

0100mmmm00001110

1

LSB

LDC

Rm,GBR

Rm → GBR

0100mmmm00011110

1

—

LDC

Rm,VBR

Rm → VBR

0100mmmm00101110

1

—

LDC.L

@Rm+,SR(Rm) → SR, Rm + 4 → Rm

0100mmmm00000111

3

LSB

LDC.L

@Rm+,GBR(Rm) → GBR, Rm + 4 → Rm

0100mmmm00010111

3

—

LDC.L

@Rm+,VBR(Rm) → VBR, Rm + 4 → Rm

0100mmmm00100111

3—

Description: Stores the source operand into control registers SR, GBR, or VBR.
Note: No interrupts are accepted between this instruction and the next instruction. Address
errors are accepted.
Operation:
LDCSR(long m)/* LDC Rm,SR */{SR=R[m]&0x000003F3;
PC+=2;}LDCGBR(long m)/* LDC Rm,GBR */{GBR=R[m];PC+=2;}LDCVBR(long m)/* LDC Rm,VBR */{VBR=R[m];PC+=2;}HITACHI 101

LDCMSR(long m)/* LDC.L @Rm+,SR */{SR=Read_Long(R[m])&0x000003F3;
R[m]+=4;
PC+=2;}LDCMGBR(long m)/* LDC.L @Rm+,GBR */{GBR=Read_Long(R[m]);R[m]+=4;
PC+=2;}LDCMVBR(long m)/* LDC.L @Rm+,VBR */{VBR=Read_Long(R[m]);R[m]+=4;
PC+=2;}

Examples:
LDC

LDC.L

R0,SR

@R15+,GBR

102 HITACHI

Before execution

R0 = H'FFFFFFFF, SR = H'00000000

After execution

SR = H'000003F3

Before execution

R15 = H'10000000

After execution

R15 = H'10000004, GBR = @H'10000000

6.28

LDS (Load to System Register): System Control Instruction

Class: Interrupt disabled instruction
FormatAbstract

Code

State

T Bit

LDS

Rm,MACH

Rm → MACH

0100mmmm00001010

1

—

LDS

Rm,MACL

Rm → MACL

0100mmmm00011010

1

—

LDS

Rm,PR

Rm → PR

0100mmmm00101010

1—(Rm) → MACH, Rm + 4 → Rm

0100mmmm00000110

1—(Rm) → MACL, Rm + 4 → Rm

0100mmmm00010110

1—(Rm) → PR, Rm + 4 → Rm

0100mmmm00100110

1

—

LDS.L
@Rm+,MAC
H
LDS.L@Rm+,MAC
L
LDS.L@Rm+,PR

Description: Stores the source operand into the system registers MACH, MACL, or PR.
Note: No interrupts are accepted between this instruction and the next instruction. Address
errors are accepted.
For the SH-1 CPU, the lower 10 bits are stored in MACH. For the SH-2 CPU, 32 bits are
stored in MACH.
Operation:LDSMACH(long m)/* LDS Rm,MACH */{MACH=R[m];if ((MACH&0x00000200)==0) MACH&=0x000003FF;
else MACH|=0xFFFFFC00;

For SH-1 CPU (these 2 lines
not needed for SH-2 CPU)

PC+=2;}LDSMACL(long m)/* LDS Rm,MACL */{MACL=R[m];PC+=2;}HITACHI 103

LDSPR(long m)/* LDS Rm,PR */{
PR=R[m];PC+=2;}LDSMMACH(long m)/* LDS.L @Rm+,MACH */{MACH=Read_Long(R[m]);if ((MACH&0x00000200)==0) MACH&=0x000003FF;
else MACH|=0xFFFFFC00;

For SH-1 CPU (these 2 lines
not needed for SH-2 CPU)

R[m]+=4;
PC+=2;}LDSMMACL(long m)/* LDS.L @Rm+,MACL */{MACL=Read_Long(R[m]);R[m]+=4;
PC+=2;}LDSMPR(long m)/* LDS.L @Rm+,PR */{PR=Read_Long(R[m]);R[m]+=4;
PC+=2;}

Examples:
LDS

R0,PR

LDS.L

@R15+,MACL

104 HITACHI

Before execution
After execution
Before execution
After execution

R0 = H'12345678, PR = H'00000000
PR = H'12345678
R15 = H'10000000
R15 = H'10000004, MACL = @H'10000000

6.29

MAC.L (Multiply and Accumulate Long): Arithmetic Instruction(SH-2 CPU)

Format
MAC.L

Abstract@Rm+,@Rn+ Signed operation, (Rn) × (Rm)
+ MAC → MAC

Code

State

T Bit

0000nnnnmmmm1111

3/(2 to4)—

Description: Signed-multiplies 32-bit operands obtained using the contents of generalregisters Rm and Rn as addresses. The 64-bit result is added to contents of the MAC register,and the final result is stored in the MAC register. Every time an operand is read, they
increment Rm and Rn by four.
When the S bit is cleared to 0, the 64-bit result is stored in the coupled MACH and MACL
registers. When bit S is set to 1, addition to the MAC register is a saturation operation at the
48th bit starting from the LSB. For the saturation operation, only the lower 48 bits of the
MACL registers are enabled and the result is limited to a range of H'FFFF800000000000(minimum) to H'00007FFFFFFFFFFF (maximum).
Operation:
MACL(long m,long n) /* MAC.L @Rm+,@Rn+*/{unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
unsigned long temp0,templ,temp2,temp3;
long tempm,tempn,fnLmL;

tempn=(long)Read_Long(R[n]);R[n]+=4;
tempm=(long)Read_Long(R[m]);R[m]+=4;

if ((long)(tempn^tempm)<0) fnLmL=-1;
else fnLmL=0;
if (tempn<0) tempn=0-tempn;
if (tempm<0) tempm=0-tempm;

temp1=(unsigned long)tempn;
temp2=(unsigned long)tempm;

HITACHI 105

RnL=temp1&0x0000FFFF;
RnH=(temp1>>16)&0x0000FFFF;
RmL=temp2&0x0000FFFF;
RmH=(temp2>>16)&0x0000FFFF;

temp0=RmL*RnL;
temp1=RmH*RnL;
temp2=RmL*RnH;
temp3=RmH*RnH;

Res2=0;Res1=temp1+temp2;
if (Res1<temp1) Res2+=0x00010000;

temp1=(Res1<<16)&0xFFFF0000;
Res0=temp0+temp1;
if (Res0<temp0) Res2++;

Res2=Res2+((Res1>>16)&0x0000FFFF)+temp3;

if(fnLm<0){
Res2=~Res2;
if (Res0==0) Res2++;else Res0=(~Res0)+1;}
if(S==1){
Res0=MACL+Res0;
if (MACL>Res0) Res2++;
Res2+=(MACH&0x0000FFFF);

if(((long)Res2<0)&&(Res2<0xFFFF8000)){
Res2=0x00008000;
Res0=0x00000000;}
if(((long)Res2>0)&&(Res2>0x00007FFF)){
Res2=0x00007FFF;
Res0=0xFFFFFFFF;};

106 HITACHIMACH=Res2;
MACL=Res0;}
else {
Res0=MACL+Res0;
if (MACL>Res0) Res2++;
Res2+=MACH

MACH=Res2;
MACL=Res0;}
PC+=2;}

Example:MOVA

TBLM,R0

MOV

R0,R1

MOVA

TBLN,R0

CLRMAC
MAC.L

Table address
Table address
MAC register initialization@R0+,@R1+

MAC.L@R0+,@R1+

STS

MACL,R0Store result into R0...............

TBLM

TBLN

.align2.data.lH'1234ABCD.data.lH'5678EF01.data.lH'0123ABCD.data.lH'4567DEF0

HITACHI 107

6.30

MAC (Multiply and Accumulate): Arithmetic Instruction (SH-1
CPU)

Format
MAC.W@Rm+,@Rn

Abstract

Code

State

T Bit

With signed, (Rn) × (Rm) +MAC → MAC

0100nnnnmmmm1111

3/(2)

—

+

Description: Multiplies 16-bit operands obtained using the contents of general registers Rm
and Rn as addresses. The 32-bit result is added to contents of the MAC register, and the final
result is stored in the MAC register. Every time an operand is read, they increment Rm and
Rn by two.
When the S bit is cleared to 0, the 42-bit result is stored in the coupled MACH and MACL
registers. Bit 9 data is transferred to the upper 22 bits (bits 31 to 10) of the MACH register.
When the S bit is set to 1, addition to the MAC register is a saturation operation. For thesaturation operation, only the MACL register is enabled and the result is limited to a range ofH'80000000 (minimum) to H'7FFFFFFF (maximum).
If an overflow occurs, the LSB of the MACH register is set to 1. The result is stored in the
MACL register, and the result is limited to a value between H'80000000 (minimum) for
overflows in the negative direction and H'7FFFFFFF (maximum) for overflows in the positive
direction.
Note: The normal number of cycles for execution is 3; however, this instruction can be
executed in two cycles according to the succeeding instruction.

108 HITACHI6.31

MAC.W (Multiply and Accumulate Word): Arithmetic Instruction

Format
MAC.W
MAC

Abstract@Rm+,@Rn+ Signed operation,@Rm+,@Rn+ (Rn) × (Rm) + MAC → MAC

Code

State

T Bit

0100nnnnmmmm1111

3/(2)

—

Description: Signed-multiplies 16-bit operands obtained using the contents of generalregisters Rm and Rn as addresses. The 32-bit result is added to contents of the MAC register,and the final result is stored in the MAC register. Every time an operand is read, they
increment Rm and Rn by two.
When the S bit is cleared to 0, the operation is 16 × 16 + 64 → 64-bit multiply andaccumulate and the 64-bit result is stored in the coupled MACH and MACL registers.
When the S bit is set to 1, the operation is 16 × 16 + 32 → 32-bit multiply and accumulate
and addition to the MAC register is a saturation operation. For the saturation operation, only
the MACL register is enabled and the result is limited to a range of H'80000000 (minimum)
to H'7FFFFFFF (maximum).
If an overflow occurs, the LSB of the MACH register is set to 1. The result is stored in the
MACL register, and the result is limited to a value between H'80000000 (minimum) for
overflows in the negative direction and H'7FFFFFFF (maximum) for overflows in the positive
direction.
Note: When the S bit is 0, the SH-2 CPU performs a 16 × 16 + 64 → 64 bit multiply andaccumulate operation and the SH-1 CPU performs a 16 × 16 + 42 → 42 bit multiply andaccumulate operation.
Operation:
MACW(long m,long n) /* MAC.W @Rm+,@Rn+*/{long tempm,tempn,dest,src,ans;
unsigned long templ;
tempn=(long)Read_Word(R[n]);R[n]+=2;
tempm=(long)Read_Word(R[m]);R[m]+=2;
templ=MACL;
tempm=((long)(short)tempn*(long)(short)tempm);

HITACHI 109

if ((long)MACL>=0) dest=0;
else dest=1;
if ((long)tempm>=0 {src=0;
tempn=0;}
else {
src=1;
tempn=0xFFFFFFFF;}
src+=dest;
MACL+=tempm;
if ((long)MACL>=0) ans=0;
else ans=1;
ans+=dest;
if (S==1) {if (ans==1) {if (src==0 || src==2)
MACH|=0x00000001;

For SH-1 CPU (these 2
lines
not needed for SH-2 CPU)if (src==0) MACL=0x7FFFFFFF;
if (src==2) MACL=0x80000000;}}
else {
MACH+=tempn;
if (templ>MACL) MACH+=1;
if ((MACH&0x00000200)==0)
MACH&=0x000003FF;
else MACH|=0xFFFFFC00;}
PC+=2;}

110 HITACHIFor SH-1 CPU (these 3
lines
not needed for SH-2 CPU)Example:
MOVA

TBLM,R0

MOV

R0,R1

MOVA

TBLN,R0

CLRMAC
MAC.W

Table address
Table address
MAC register initialization@R0+,@R1+

MAC.W@R0+,@R1+

STS

MACL,R0Store result into R0...............

TBLM

TBLN

.align2.data.w

H'1234.data.w

H'5678.data.w

H'0123.data.w

H'4567HITACHI 111

6.32

MOV (Move Data): Data Transfer Instruction

FormatAbstract

Code

State

T Bit

MOV

Rm,Rn

Rm → Rn

0110nnnnmmmm0011

1

—

MOV.B

Rm,@RnRm → (Rn)0010nnnnmmmm0000

1

—

MOV.W

Rm,@RnRm → (Rn)0010nnnnmmmm0001

1

—

MOV.L

Rm,@RnRm → (Rn)0010nnnnmmmm0010

1

—

MOV.B

@Rm,Rn(Rm) → sign extension → Rn

0110nnnnmmmm0000

1

—

MOV.W

@Rm,Rn(Rm) → sign extension → Rn

0110nnnnmmmm0001

1

—

MOV.L

@Rm,Rn(Rm) → Rn

0110nnnnmmmm0010

1

—

MOV.B

Rm,@–Rn

Rn – 1 → Rn, Rm → (Rn)0010nnnnmmmm0100

1

—

MOV.W

Rm,@–Rn

Rn – 2 → Rn, Rm → (Rn)0010nnnnmmmm0101

1

—

MOV.L

Rm,@–Rn

Rn – 4 → Rn, Rm → (Rn)0010nnnnmmmm0110

1

—

MOV.B

@Rm+,Rn(Rm) → sign extension → Rn,
Rm + 1 → Rm

0110nnnnmmmm0100

1

—

MOV.W

@Rm+,Rn(Rm) → sign extension → Rn,
Rm + 2 → Rm

0110nnnnmmmm0101

1

—

MOV.L

@Rm+,Rn(Rm) → Rn, Rm + 4 → Rm

0110nnnnmmmm0110

1

—

MOV.B

Rm,@(R0,Rn) Rm → (R0 + Rn)

0000nnnnmmmm0100

1

—

MOV.W

Rm,@(R0,Rn) Rm → (R0 + Rn)

0000nnnnmmmm0101

1

—

MOV.L

Rm,@(R0,Rn) Rm → (R0 + Rn)

0000nnnnmmmm0110

1

—

MOV.B

@(R0,Rm),Rn (R0 + Rm) → sign extension→ Rn

0000nnnnmmmm1100

1—0000nnnnmmmm1101@(R0,Rm),Rn (R0 + Rm) → sign extension
→ Rn

1

—

MOV.W

0000nnnnmmmm1110

1

—

MOV.L

@(R0,Rm),Rn (R0 + Rm) → Rn

Description: Transfers the source operand to the destination. When the operand is stored inmemory, the transferred data can be a byte, word, or longword. When the source operand is inmemory, loaded data from memory is stored in a register after it is sign-extended to alongword.
Operation:
MOV(long m,long n){R[n]=R[m];PC+=2;}

112 HITACHI/* MOV Rm,Rn */MOVBS(long m,long n)/* MOV.B Rm,@Rn */{Write_Byte(R[n],R[m]);PC+=2;}
MOVWS(long m,long n)/* MOV.W Rm,@Rn */{Write_Word(R[n],R[m]);PC+=2;}MOVLS(long m,long n)/* MOV.L Rm,@Rn */{Write_Long(R[n],R[m]);PC+=2;}
MOVBL(long m,long n)/* MOV.B @Rm,Rn */{R[n]=(long)Read_Byte(R[m]);if ((R[n]&0x80)==0) R[n]&0x000000FF;
else R[n]|=0xFFFFFF00;
PC+=2;}MOVWL(long m,long n)/* MOV.W @Rm,Rn */{R[n]=(long)Read_Word(R[m]);if ((R[n]&0x8000)==0) R[n]&0x0000FFFF;
else R[n]|=0xFFFF0000;
PC+=2;}MOVLL(long m,long n)/* MOV.L @Rm,Rn */{R[n]=Read_Long(R[m]);PC+=2;}HITACHI 113

MOVBM(long m,long n)/* MOV.B Rm,@–Rn */{Write_Byte(R[n]–1,R[m]);R[n]–=1;
PC+=2;}
MOVWM(long m,long n)/* MOV.W Rm,@–Rn */{Write_Word(R[n]–2,R[m]);R[n]–=2;
PC+=2;}MOVLM(long m,long n)/* MOV.L Rm,@–Rn */{Write_Long(R[n]–4,R[m]);R[n]–=4;
PC+=2;}MOVBP(long m,long n) /* MOV.B @Rm+,Rn */{R[n]=(long)Read_Byte(R[m]);if ((R[n]&0x80)==0) R[n]&0x000000FF;
else R[n]|=0xFFFFFF00;
if (n!=m) R[m]+=1;
PC+=2;}
MOVWP(long m,long n)/* MOV.W @Rm+,Rn */{R[n]=(long)Read_Word(R[m]);if ((R[n]&0x8000)==0) R[n]&0x0000FFFF;
else R[n]|=0xFFFF0000;
if (n!=m) R[m]+=2;
PC+=2;}

114 HITACHIMOVLP(long m,long n)/* MOV.L @Rm+,Rn */{R[n]=Read_Long(R[m]);if (n!=m) R[m]+=4;
PC+=2;}MOVBS0(long m,long n)/* MOV.B Rm,@(R0,Rn) */{Write_Byte(R[n]+R[0],R[m]);PC+=2;}
MOVWS0(long m,long n)/* MOV.W Rm,@(R0,Rn) */{Write_Word(R[n]+R[0],R[m]);PC+=2;}MOVLS0(long m,long n)/* MOV.L Rm,@(R0,Rn) */{Write_Long(R[n]+R[0],R[m]);PC+=2;}
MOVBL0(long m,long n)/* MOV.B @(R0,Rm),Rn */{R[n]=(long)Read_Byte(R[m]+R[0]);if ((R[n]&0x80)==0) R[n]&0x000000FF;
else R[n]|=0xFFFFFF00;
PC+=2;}MOVWL0(long m,long n)/* MOV.W @(R0,Rm),Rn */{R[n]=(long)Read_Word(R[m]+R[0]);if ((R[n]&0x8000)==0) R[n]&0x0000FFFF;
else R[n]|=0xFFFF0000;
PC+=2;}HITACHI 115

MOVLL0(long m,long n)/* MOV.L @(R0,Rm),Rn */{R[n]=Read_Long(R[m]+R[0]);PC+=2;}

Example:
MOV

R0,R1

Before execution R0 = H'FFFFFFFF, R1 = H'00000000
After execution
R1 = H'FFFFFFFF

MOV.W

R0,@R1

Before execution R0 = H'FFFF7F80
After execution@R1 = H'7F80

MOV.B@R0,R1

Before execution @R0 = H'80, R1 = H'00000000
After execution
R1 = H'FFFFFF80

MOV.W

R0,@–R1

Before execution R0 = H'AAAAAAAA, R1 = H'FFFF7F80
After execution
R1 = H'FFFF7F7E, @R1 = H'AAAA

MOV.L@R0+,R1

Before execution R0 = H'12345670
After execution
R0 = H'12345674, R1 = @H'12345670

MOV.B

R1,@(R0,R2) Before execution R2 = H'00000004, R0 = H'10000000

After execution
MOV.W

R1 = @H'10000004@(R0,R2),R1 Before execution R2 = H'00000004, R0 = H'10000000

After execution

116 HITACHI

R1 = @H'10000004

6.33

MOV (Move Immediate Data): Data Transfer Instruction

FormatAbstract

Code1110nnnniiiiiiii 1—1001nnnndddddddd 1—1101nnnndddddddd 1—

MOV#imm,Rn

imm → sign extension →
Rn

MOV.W

@(disp,PC),Rn(disp × 2 + PC) → signextension → Rn

MOV.L@(disp,PC),Rn(disp × 4 + PC) → Rn

State

T Bit

Description: Stores immediate data, which has been sign-extended to a longword, into
general register Rn.
If the data is a word or longword, table data stored in the address specified by PC +displacement is accessed. If the data is a word, the 8-bit displacement is zero-extended anddoubled. Consequently, the relative interval from the table is up to PC + 510 bytes. The PC
points to the starting address of the second instruction after this MOV instruction. If the data
is a longword, the 8-bit displacement is zero-extended and quadrupled. Consequently, therelative interval from the table is up to PC + 1020 bytes. The PC points to the starting addressof the second instruction after this MOV instruction, but the lowest two bits of the PC are
corrected to B’00.
Note: The end address of the program area (module) or the second address after an
unconditional branch instruction are suitable for the start address of the table. If suitable tableassignment is impossible (for example, if there are no unconditional branch instructions
within the area specified by PC + 510 bytes or PC + 1020 bytes), the BRA instruction must
be used to jump past the table. When this MOV instruction is placed immediately after adelayed branch instruction, the PC points to an address specified by (the starting address ofthe branch destination) + 2.
Operation:
MOVI(long i,long n)/* MOV #imm,Rn */{if ((i&0x80)==0) R[n]=(0x000000FF & (long)i);
else R[n]=(0xFFFFFF00 | (long)i);PC+=2;}MOVWI(long d,long n)/* MOV.W @(disp,PC),Rn */{long disp;

HITACHI 117

disp=(0x000000FF & (long)d);R[n]=(long)Read_Word(PC+(disp<<1));
if ((R[n]&0x8000)==0) R[n]&=0x0000FFFF;
else R[n]|=0xFFFF0000;
PC+=2;}MOVLI(long d,long n)/* MOV.L @(disp,PC),Rn */{long disp;

disp=(0x000000FF & (long)d);R[n]=Read_Long((PC&0xFFFFFFFC)+(disp<<2));
PC+=2;}

Example:Address1000

MOV#H'80,R1

1002

MOV.W

IMM,R21004

ADD#–1,R0

1006

TST

R0,R0

R1 = H'FFFFFF80
R2 = H'FFFF9ABC, IMM means @(H'08,PC)← PC location used for address calculation for

the MOV.W instruction
1008

MOVT

R13

100A

BRA

NEXT

100C

MOV.L

@(4,PC),R3

100E IMM.data.w

H'9ABC

1010.data.w

H'12341012 NEXT

JMP

@R3

1014

CMP/EQ#0,R0.align4.data.lH'12345678

1018

118 HITACHI

Delayed branch instruction
R3 = H'12345678

Branch destination of the BRA instruction← PC location used for address calculation for
the MOV.L instruction

6.34

MOV (Move Peripheral Data): Data Transfer Instruction

FormatAbstract

Code

State

T Bit

MOV.B

@(disp,GBR),R0(disp + GBR) → signextension → R0

11000100dddddddd

1

—

MOV.W

@(disp,GBR),R0(disp × 2 + GBR) →sign extension → R0

11000101dddddddd

1

—

MOV.L

@(disp,GBR),R0(disp × 4+ GBR) → R0

11000110dddddddd

1

—

MOV.B

R0,@(disp,GBR)

R0 → (disp + GBR)

11000000dddddddd

1

—

MOV.W

R0,@(disp,GBR)

11000001dddddddd

1

—

MOV.L

R0,@(disp,GBR)

R0 → (disp × 2 +GBR)11000010dddddddd

1—

R0 → (disp × 4 +GBR)

Description: Transfers the source operand to the destination. This instruction is suitable foraccessing data in the peripheral module area. The data can be a byte, word, or longword, but
the register is fixed to R0.
A peripheral module base address is set to the GBR. When the peripheral module data is abyte, the 8-bit displacement is zero-extended. Consequently, an address within +255 bytes
can be specified. When the peripheral module data is a word, the 8-bit displacement is zeroextended and doubled. Consequently, an address within +510 bytes can be specified. Whenthe peripheral module data is a longword, the 8-bit displacement is zero-extended and isquadrupled. Consequently, an address within +1020 bytes can be specified. If thedisplacement is too short to reach the memory operand, the above @(R0,Rn) mode must be
used after the GBR data is transferred to a general register. When the source operand is inmemory, the loaded data is stored in the register after it is sign-extended to a longword.
Note: The destination register of a data load is always R0. R0 cannot be accessed by the next
instruction until the load instruction is finished. Changing the instruction order shown in figure
6.1 will give better results.
MOV.B @(12, GBR), R0

MOV.B @(12, GBR), R0AND#80, R0ADD#20, R1

ADD#20, R1

AND#80, R0

Figure 6.1 Using R0 after MOV

HITACHI 119

Operation:
MOVBLG(long d)/* MOV.B @(disp,GBR),R0 */{long disp;

disp=(0x000000FF & (long)d);R[0]=(long)Read_Byte(GBR+disp);
if ((R[0]&0x80)==0) R[0]&=0x000000FF;
else R[0]|=0xFFFFFF00;
PC+=2;}MOVWLG(long d)/* MOV.W @(disp,GBR),R0 */{long disp;

disp=(0x000000FF & (long)d);R[0]=(long)Read_Word(GBR+(disp<<1));
if ((R[0]&0x8000)==0) R[0]&=0x0000FFFF;
else R[0]|=0xFFFF0000;
PC+=2;}MOVLLG(long d)/* MOV.L @(disp,GBR),R0 */{long disp;

disp=(0x000000FF & (long)d);R[0]=Read_Long(GBR+(disp<<2));
PC+=2;}MOVBSG(long d){long disp;

120 HITACHI/* MOV.B R0,@(disp,GBR) */disp=(0x000000FF & (long)d);Write_Byte(GBR+disp,R[0]);PC+=2;}
MOVWSG(long d)/* MOV.W R0,@(disp,GBR) */{long disp;

disp=(0x000000FF & (long)d);Write_Word(GBR+(disp<<1),R[0]);PC+=2;}MOVLSG(long d)/* MOV.L R0,@(disp,GBR) */{long disp;

disp=(0x000000FF & (long)d);Write_Long(GBR+(disp<<2),R[0]);PC+=2;}

Examples:
MOV.L@(2,GBR),R0

Before execution
After execution@(GBR + 8) = H'12345670
R0 = @H'12345670

MOV.B

R0,@(1,GBR)

Before execution
After execution

R0 = H'FFFF7F80@(GBR + 1) = H'FFFF7F80

HITACHI 121

6.35

MOV (Move Structure Data): Data Transfer Instruction

FormatAbstract

Code

State

T Bit

R0 → (disp + Rn)

10000000nnnndddd

1

—

MOV.B

R0,@(disp,Rn)

MOV.W

R0,@(disp,Rn)

R0 → (disp × 2 + Rn)

10000001nnnndddd

1

—

MOV.L

Rm,@(disp,Rn)

Rm → (disp × 4 + Rn)

0001nnnnmmmmdddd

1

—

MOV.B

@(disp,Rm),R0(disp + Rm) → signextension → R0

10000100mmmmdddd

1

—

MOV.W

@(disp,Rm),R0(disp × 2 + Rm) → signextension → R0

10000101mmmmdddd

1

—

MOV.L

@(disp,Rm),Rn(disp × 4 + Rm) → Rn

0101nnnnmmmmdddd

1—

Description: Transfers the source operand to the destination. This instruction is suitable foraccessing data in a structure or a stack. The data can be a byte, word, or longword, but whena byte or word is selected, only the R0 register is fixed. When the data is a byte, the 4-bit
displacement is zero-extend. Consequently, an address within +15 bytes can be specified.
When the data is a word, the 4-bit displacement is zero-extended and doubled. Consequently,
an address within +30 bytes can be specified. When the data is a longword, the 4-bit
displacement is zero-extended and quadrupled. Consequently, an address within +60 bytes
can be specified. If the displacement is too short to reach the memory operand, theaforementioned @(R0,Rn) mode must be used. When the source operand is in memory, theloaded data is stored in the register after it is sign-extended to a longword.
Note: When byte or word data is loaded, the destination register is always R0. R0 cannot be
accessed by the next instruction until the load instruction is finished. Changing the instruction
order in figure 6.2 will give better results.
MOV.B @(2, R1), R0

MOV.B @(2, R1), R0AND#80, R0ADD#20, R1

ADD#20, R1

AND#80, R0

Figure 6.2 Using R0 after MOV

122 HITACHIOperation:
MOVBS4(long d,long n)/* MOV.B R0,@(disp,Rn) */{long disp;

disp=(0x0000000F & (long)d);Write_Byte(R[n]+disp,R[0]);PC+=2;}
MOVWS4(long d,long n)/* MOV.W R0,@(disp,Rn) */{long disp;

disp=(0x0000000F & (long)d);Wr ite_Word(R[n]+(disp<<1),R[0]);PC+=2;}MOVLS4(long m,long d,long n)/* MOV.L Rm,@(disp,Rn) */{long disp;

disp=(0x0000000F & (long)d);Write_Long(R[n]+(disp<<2),R[m]);PC+=2;}
MOVBL4(long m,long d)/* MOV.B @(disp,Rm),R0 */{long disp;

disp=(0x0000000F & (long)d);R[0]=Read_Byte(R[m]+disp);
if ((R[0]&0x80)==0) R[0]&=0x000000FF;
else R[0]|=0xFFFFFF00;
PC+=2;}HITACHI 123

MOVWL4(long m,long d)/* MOV.W @(disp,Rm),R0 */{long disp;

disp=(0x0000000F & (long)d);R[0]=Read_Word(R[m]+(disp<<1));
if ((R[0]&0x8000)==0) R[0]&=0x0000FFFF;
else R[0]|=0xFFFF0000;
PC+=2;}MOVLL4(long m,long d,long n)/* MOV.L @(disp,Rm),Rn */{long disp;

disp=(0x0000000F & (long)d);R[n]=Read_Long(R[m]+(disp<<2));
PC+=2;}

Examples:
MOV.L@(2,R0),R1

Before execution @(R0 + 8) = H'12345670
After execution R1 = @H'12345670

MOV.L

R0,@(H'F,R1)

Before execution R0 = H'FFFF7F80
After execution @(R1 + 60) = H'FFFF7F80

124 HITACHI6.36

MOVA (Move Effective Address): Data Transfer Instruction

FormatMOVA@(disp,PC),R0

Abstract

Code

State

T Bit

disp × 4 + PC → R0

11000111dddddddd

1—

Description: Stores the effective address of the source operand into general register R0. The
8-bit displacement is zero-extended and quadrupled. Consequently, the relative interval fromthe operand is PC + 1020 bytes. The PC points to the starting address of the second
instruction after this MOVA instruction, but the lowest two bits of the PC are corrected to
B’00.
Note: If this instruction is placed immediately after a delayed branch instruction, the PC must
point to an address specified by (the starting address of the branch destination) + 2.
Operation:
MOVA(long d) /* MOVA @(disp,PC),R0 */{long disp;

disp=(0x000000FF & (long)d);R[0]=(PC&0xFFFFFFFC)+(disp<<2);
PC+=2;}

Example:Address.org

H'10061006

MOVA

STR,R0

1008

MOV.B

@R0,R1

100A

ADD

R4,R5

.align4.sdata“XYZP12”

100C

STR:

Address of STR → R0
R1 = “X”← PC location after correcting
the lowest two bits
← Original PC location for address calculation for
the MOVA instruction...............
2002

BRA

TRGET

2004

MOVA

@(0,PC),R0

2006

NOP

Delayed branch instruction
Address of TRGET + 2 → R0

HITACHI 125

6.37

MOVT (Move T Bit): Data Transfer Instruction

FormatMOVT

Rn

Abstract

Code

State

T Bit

T → Rn

0000nnnn00101001

1—

Description: Stores the T bit value into general register Rn. When T = 1, 1 is stored in Rn,
and when T = 0, 0 is stored in Rn.
Operation:
MOVT(long n) /* MOVT Rn */{R[n]=(0x00000001 & SR);
PC+=2;}

Example:
XOR

R2,R2

CMP/PZ R2
MOVT

R0

CLRT
MOVT

R1

126 HITACHI

R2 = 0T=1
R0 = 1T=0
R1 = 0

6.38

MUL.L (Multiply Long): Arithmetic Instruction (SH-2 CPU)

Format
MUL.L

Rm,Rn

Abstract

Code

State

T Bit

Rn × Rm → MACL

0000nnnnmmmm0111

2 to 4—

Description: Performs 32-bit multiplication of the contents of general registers Rn and Rm,
and stores the lower 32 bits of the result in the MACL register. The MACH register data does
not change.
Operation:
MULL(long m,long n) /* MUL.L Rm,Rn */{MACL=R[n]*R[m];PC+=2;}

Example:MUL.L R0,R1

STS

Before execution
After execution
MACL,R0R0 = H'FFFFFFFE, R1 = H'00005555
MACL = H'FFFF5556
Operation result

HITACHI 127

6.39

MULS.W (Multiply as Signed Word): Arithmetic Instruction

FormatAbstract

Code

State

T Bit

MULS.W Rm,Rn
MULS
Rm,Rn

Signed operation, Rn × Rm →MACL0010nnnnmmmm1111

1 to 3—

Description: Performs 16-bit multiplication of the contents of general registers Rn and Rm,
and stores the 32-bit result in the MACL register. The operation is signed and the MACH
register data does not change.
Operation:
MULS(long m,long n) /* MULS Rm,Rn */{MACL=((long)(short)R[n]*(long)(short)R[m]);PC+=2;}

Example:MULS R0,R1

STS

128 HITACHI

Before execution
After execution
MACL,R0R0 = H'FFFFFFFE, R1 = H'00005555
MACL = H'FFFF5556
Operation result

6.40

MULU.W (Multiply as Unsigned Word): Arithmetic Instruction

FormatAbstract

Code

State

T Bit

MULU.W Rm,Rn
MULU
Rm,Rn

Unsigned, Rn × Rm → MAC

0010nnnnmmmm1110

1 to 3—

Description: Performs 16-bit multiplication of the contents of general registers Rn and Rm,
and stores the 32-bit result in the MACL register. The operation is unsigned and the MACH
register data does not change.
Operation:
MULU(long m,long n) /* MULU Rm,Rn */{MACL=((unsigned long)(unsigned short)R[n]*(unsigned long)(unsigned short)R[m]);PC+=2;}

Example:
MULU

R0,R1

B efore execution
After execution

STS MACL,R0

R0 = H'00000002, R1 = H'FFFFAAAA
MACL = H'00015554

Operation result

HITACHI 129

6.41

NEG (Negate): Arithmetic Instruction

Format
NEG

Rm,Rn

Abstract

Code

State

T Bit

0 – Rm → Rn

0110nnnnmmmm1011

1—

Description: Takes the two’s complement of data in general register Rm, and stores theresult in Rn. This effectively subtracts Rm data from 0, and stores the result in Rn.
Operation:
NEG(long m,long n)/* NEG Rm,Rn */{R[n]=0-R[m];PC+=2;}

Example:
NEG

R0,R1

130 HITACHI

Before execution
After execution

R0 = H'00000001
R1 = H'FFFFFFFF

6.42

NEGC (Negate with Carry): Arithmetic Instruction

Format
NEGC

Rm,Rn

Abstract

Code

State

T Bit

0 – Rm – T → Rn, Borrow → T

0110nnnnmmmm1010

1

Borrow

Description: Subtracts general register Rm data and the T bit from 0, and stores the result in
Rn. If a borrow is generated, T bit changes accordingly. This instruction is used for inverting
the sign of a value that has more than 32 bits.
Operation:
NEGC(long m,long n) /* NEGC Rm,Rn */{unsigned long temp;

temp=0-R[m];R[n]=temp-T;
if (0<temp)

T=1;

else T=0;
if (temp<R[n])T=1;

PC+=2;}

Examples:
CLRT
NEGC

R1,R1

NEGC

R0,R0

Sign inversion of R1 and R0 (64 bits)
Before execution R1 = H'00000001, T = 0
After execution
R1 = H'FFFFFFFF, T = 1
Before execution R0 = H'00000000, T = 1
After execution
R0 = H'FFFFFFFF, T = 1

HITACHI 131

6.43

NOP (No Operation): System Control Instruction

FormatAbstract

Code

State

T Bit

NOP

No operation

0000000000001001

1—

Description: Increments the PC to execute the next instruction.
Operation:
NOP()/* NOP */{PC+=2;}

Example:NOP

Executes in one cycle

132 HITACHI6.44

NOT (NOT—Logical Complement): Logic Operation Instruction

FormatAbstract

Code

State

T Bit

NOT Rm,Rn~Rm → Rn

0110nnnnmmmm0111

1—

Description: Takes the one’s complement of general register Rm data, and stores the resultin Rn. This effectively inverts each bit of Rm data and stores the result in Rn.
Operation:
NOT(long m,long n)/* NOT Rm,Rn */{R[n]=~R[m];PC+=2;}

Example:
NOT

R0,R1

Before execution R0 = H'AAAAAAAA
After execution R1 = H'55555555

HITACHI 133

6.45

OR (OR Logical) Logic Operation Instruction

FormatAbstract

Code

State

T Bit

OR

Rm,Rn

Rn | Rm → Rn

0010nnnnmmmm1011

1

—

OR

#imm,R0

R0 | imm → R0

11001011iiiiiiii

1—

11001111iiiiiiii

3—#imm,@(R0,GB(R0 + GBR) | imm → (R0 +
GBR)

OR.B
R)

Description: Logically ORs the contents of general registers Rn and Rm, and stores theresult in Rn. The contents of general register R0 can also be ORed with zero-extended 8-bit
immediate data, or 8-bit memory data accessed by using indirect indexed GBR addressing
can be ORed with 8-bit immediate data.
Operation:
OR(long m,long n)/* OR Rm,Rn */{R[n]|=R[m];PC+=2;}
ORI(long i)/* OR #imm,R0 */{R[0]|=(0x000000FF & (long)i);PC+=2;}
ORM(long i)/* OR.B #imm,@(R0,GBR) */{long temp;

temp=(long)Read_Byte(GBR+R[0]);temp|=(0x000000FF & (long)i);
Write_Byte(GBR+R[0],temp);
PC+=2;}

134 HITACHIExamples:
OR

R0,R1

Before execution
R0 = H'AAAA5555, R1 = H'55550000
After execution R1 = H'FFFF5555

OR#H'F0,R0

Before execution
R0 = H'00000008
After execution R0 = H'000000F8

OR.B#H'50,@(R0,GBR)

Before execution@(R0,GBR) = H'A5
After execution @(R0,GBR) = H'F5

HITACHI 135

6.46

ROTCL (Rotate with Carry Left): Shift Instruction

FormatROTCL

Rn

Abstract

Code

State

T Bit

T ← Rn ← T

0100nnnn00100100

1

MSB

Description: Rotates the contents of general register Rn and the T bit to the left by one bit,and stores the result in Rn. The bit that is shifted out of the operand is transferred to the T bit(figure 6.3).
MSB
T
ROTCL

Figure 6.3 Rotate with Carry Left
Operation:
ROTCL(long n) /* ROTCL Rn */{long temp;

if ((R[n]&0x80000000)==0) temp=0;
else temp=1;
R[n]<<=1;
if (T==1) R[n]|=0x00000001;
else R[n]&=0xFFFFFFFE;
if (temp==1) T=1;
else T=0;
PC+=2;}

Example:ROTCL

R0

136 HITACHI

Before execution
After execution

R0 = H'80000000, T = 0
R0 = H'00000000, T = 1

LSB

6.47

ROTCR (Rotate with Carry Right): Shift Instruction

Format
ROTCR

Rn

Abstract

Code

State

T Bit

T → Rn → T

0100nnnn00100101

1

LSB

Description: Rotates the contents of general register Rn and the T bit to the right by one bit,and stores the result in Rn. The bit that is shifted out of the operand is transferred to the T bit(figure 6.4).
MSB

LSB
T

ROTCR

Figure 6.4 Rotate with Carry Right
Operation:
ROTCR(long n) /* ROTCR Rn */{long temp;

if ((R[n]&0x00000001)==0) temp=0;
else temp=1;
R[n]>>=1;
if (T==1) R[n]|=0x80000000;
else R[n]&=0x7FFFFFFF;
if (temp==1) T=1;
else T=0;
PC+=2;}

Examples:
ROTCR

R0

Before execution
After execution

R0 = H'00000001, T = 1
R0 = H'80000000, T = 1

HITACHI 137

6.48

ROTL (Rotate Left): Shift Instruction

Format
ROTL

Rn

Abstract

Code

State

T Bit

T ← Rn ← MSB

0100nnnn00000100

1

MSB

Description: Rotates the contents of general register Rn to the left by one bit, and stores theresult in Rn (figure 6.5). The bit that is shifted out of the operand is transferred to the T bit.
MSB
ROTL

T

Figure 6.5 Rotate Left
Operation:
ROTL(long n) /* ROTL Rn */{if ((R[n]&0x80000000)==0) T=0;
else T=1;
R[n]<<=1;
if (T==1) R[n]|=0x00000001;
else R[n]&=0xFFFFFFFE;
PC+=2;}

Examples:ROTL

R0

138 HITACHI

Before execution
After execution

R0 = H'80000000, T = 0
R0 = H'00000001, T = 1

LSB

6.49

ROTR (Rotate Right): Shift Instruction

Format
ROTR

Rn

Abstract

Code

State

T Bit

LSB → Rn → T

0100nnnn00000101

1

LSB

Description: Rotates the contents of general register Rn to the right by one bit, and stores theresult in Rn (figure 6.6). The bit that is shifted out of the operand is transferred to the T bit.
MSB

LSB
T

ROTR

Figure 6.6 Rotate Right
Operation:
ROTR(long n) /* ROTR Rn */{if ((R[n]&0x00000001)==0) T=0;
else T=1;
R[n]>>=1;
if (T==1) R[n]|=0x80000000;
else R[n]&=0x7FFFFFFF;
PC+=2;}

Examples:
ROTR

R0

Before execution
After execution

R0 = H'00000001, T = 0
R0 = H'80000000, T = 1

HITACHI 139

6.50

RTE (Return from Exception): System Control Instruction

Class: Delayed branch instruction
FormatAbstract

Code

State

T Bit

RTE

Stack area → PC/SR

0000000000101011

4

LSB

Description: Returns from an interrupt routine. The PC and SR values are restored from thestack, and the program continues from the address specified by the restored PC value.
Note: Since this is a delayed branch instruction, the instruction after this RTE is executed
before branching. No address errors and interrupts are accepted between this instruction andthe next instruction. If the next instruction is a branch instruction, it is acknowledged as anillegal slot instruction.
Operation:
RTE()/* RTE */{unsigned l ong temp;

temp=PC;
PC=Read_Long(R[15])+4;
R[15]+=4;
SR=Read_Long(R[15])&0x000003F3;
R[15]+=4;
Delay_Slot(temp+2);}

Example:RTE
ADD #8,R14

Returns to the original routine
Executes ADD before branching

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by thedelay slot instruction, the branch will still be made using the value of the registerprior to the change as the branch destination address.

140 HITACHI6.51

RTS (Return from Subroutine): Branch Instruction

Class: Delayed branch instruction
FormatAbstract

Code

State

T Bit

RTS

PR → PC

0000000000001011

2—

Description: Returns from a subroutine procedure. The PC values are restored from the PR,
and the program continues from the address specified by the restored PC value. This
instruction is used to return to the program from a subroutine program called by a BSR or JSR
instruction.
Note: Since this is a delayed branch instruction, the instruction after this RTS is executed
before branching. No address errors and interrupts are accepted between this instruction andthe next instruction. If the next instruction is a branch instruction, it is acknowledged as anillegal slot instruction.
Operation:
RTS() /* RTS */{unsigned long temp;
temp=PC;
PC=PR+4;
Delay_Slot(temp+2);}

Example:
MOV.L
JSR
NOP
ADD

TABLE,R3@R3
R0,R1.............
TABLE: .data.l TRGET.............
TRGET: MOV
R1,R0
RTS
MOV

R3 = Address of TRGET
Branches to TRGET
Executes NOP before JSR← Return address for when the subroutine procedure iscompleted (PR data)
Jump table← Procedure entrance
PR data → PC

#12,R0Executes MOV before branching

Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order ofdelayed branch instruction, then delay slot instruction. For example, even if theregister in which the branch destination address has been loaded is changed by the

HITACHI 141

delay slot instruction, the branch will still be made using the value of the registerprior to the change as the branch destination address.

142 HITACHI6.52

SETT (Set T Bit): System Control Instruction

FormatAbstract

Code

State

T Bit

SETT

1→T

0000000000011000

1

1

Description: Sets the T bit to 1.
Operation:
SETT() /* SETT */{T=1;
PC+=2;}

Example:SETT

Before execution T = 0
After execution
T=1

HITACHI 143

6.53

SHAL (Shift Arithmetic Left): Shift Instruction

Format
SHAL

Rn

Abstract

Code

State

T Bit

T ← Rn ← 0

0100nnnn00100000

1MSB

Description: Arithmetically shifts the contents of general register Rn to the left by one bit,and stores the result in Rn. The bit that is shifted out of the operand is transferred to the T bit(figure 6.7).
MSB
SHAL

LSB

T

0

Figure 6.7

Shift Arithmetic Left

Operation:
SHAL(long n) /* SHAL Rn (Same as SHLL) */{if ((R[n]&0x80000000)==0) T=0;
else T=1;
R[n]<<=1;
PC+=2;}

Example:SHAL

R0

144 HITACHI

Before execution
After execution

R0 = H'80000001, T = 0
R0 = H'00000002, T = 1

6.54

SHAR (Shift Arithmetic Right): Shift Instruction

FormatSHAR

Rn

Abstract

Code

State

T Bit

MSB → Rn → T

0100nnnn00100001

1

LSB

Description: Arithmetically shifts the contents of general register Rn to the right by one bit,and stores the result in Rn. The bit that is shifted out of the operand is transferred to the T bit(figure 6.8).
MSB

LSB
T

SHAR

Figure 6.8

Shift Arithmetic Right

Operation:
SHAR(long n) /* SHAR Rn */{long temp;

if ((R[n]&0x00000001)==0) T=0;
else T=1;
if ((R[n]&0x80000000)==0) temp=0;
else temp=1;
R[n]>>=1;
if (temp==1) R[n]|=0x80000000;
else R[n]&=0x7FFFFFFF;
PC+=2;}

Example:SHAR

R0

Before execution
After execution

R0 = H'80000001, T = 0
R0 = H'C0000000, T = 1

HITACHI 145

6.55

SHLL (Shift Logical Left): Shift Instruction

FormatSHLL

Rn

Abstract

Code

State

T Bit

T ← Rn ← 0

0100nnnn00000000

1MSB

Description: Logically shifts the contents of general register Rn to the left by one bit, andstores the result in Rn. The bit that is shifted out of the operand is transferred to the T bit(figure 6.9).
MSB
SHLL

LSB

T

0

Figure 6.9

Shift Logical Left

Operation:
SHLL(long n) /* SHLL Rn (Same as SHAL) */{if ((R[n]&0x80000000)==0) T=0;
else T=1;
R[n]<<=1;
PC+=2;}

Examples:SHLL

R0

146 HITACHI

Before execution
After execution

R0 = H'80000001, T = 0
R0 = H'00000002, T = 1

6.56

SHLLn (Shift Logical Left n Bits): Shift Instruction

FormatAbstract

Code

State

T Bit

SHLL2

Rn

Rn << 2 → Rn

0100nnnn00001000

1

—

SHLL8

Rn

Rn << 8 → Rn

0100nnnn00011000

1—

SHLL16 Rn

Rn << 16 → Rn

0100nnnn00101000

1—

Description: Logically shifts the contents of general register Rn to the left by 2, 8, or 16 bits,
and stores the result in Rn. Bits that are shifted out of the operand are not stored (figure 6.10).
MSB

LSB

SHLL2
0

MSB

LSB

SHLL8
0

MSB

LSB

SHLL160

Figure 6.10

Shift Logical Left n Bits

Operation:
SHLL2(long n) /* SHLL2 Rn */{R[n]<<=2;
PC+=2;}HITACHI 147

SHLL8(long n) /* SHLL8 Rn */{R[n]<<=8;
PC+=2;}SHLL16(long n)/* SHLL16 Rn */{R[n]<<=16;
PC+=2;}

Examples:
SHLL2

R0

Before execution
After execution

R0 = H'12345678
R0 = H'48D159E0

SHLL8

R0

Before execution
After execution

R0 = H'12345678
R0 = H'34567800

SHLL16 R0

Before execution
After execution

R0 = H'12345678
R0 = H'56780000

148 HITACHI6.57

SHLR (Shift Logical Right): Shift Instruction

FormatSHLR

Rn

Abstract

Code

State

T Bit

0 → Rn → T

0100nnnn00000001

1

LSB

Description: Logically shifts the contents of general register Rn to the right by one bit, andstores the result in Rn. The bit that is shifted out of the operand is transferred to the T bit(figure 6.11).
MSB
SHLR

LSB

0

Figure 6.11

T

Shift Logical Right

Operation:
SHLR(long n) /* SHLR Rn */{if ((R[n]&0x00000001)==0) T=0;
else T=1;
R[n]>>=1;
R[n]&=0x7FFFFFFF;
PC+=2;}

Examples
SHLR

R0

Before execution
After execution

R0 = H'80000001, T = 0
R0 = H'40000000, T = 1

HITACHI 149

6.58

SHLRn (Shift Logical Right n Bits): Shift Instruction

FormatAbstract

Code

State

T Bit

SHLR2

Rn

Rn>>2 → Rn

0100nnnn00001001

1

—

SHLR8

Rn

Rn>>8 → Rn

0100nnnn00011001

1—

SHLR16 Rn

Rn>>16 → Rn

0100nnnn00101001

1—

Description: Logically shifts the contents of general register Rn to the right by 2, 8, or 16
bits, and stores the result in Rn. Bits that are shifted out of the operand are not stored(figure 6.12).
MSB

LSB

MSB

LSB

MSB

LSB

SHLR2
0

SHLR8
0

SHLR160

Figure 6.12
Operation:
SHLR2(long n) /* SHLR2 Rn */{R[n]>>=2;
R[n]&=0x3FFFFFFF;
PC+=2;}

150 HITACHI

Shift Logical Right n BitsSHLR8(long n) /* SHLR8 Rn */{R[n]>>=8;
R[n]&=0x00FFFFFF;
PC+=2;}SHLR16(long n)/* SHLR16 Rn */{R[n]>>=16;
R[n]&=0x0000FFFF;
PC+=2;}

Examples:
SHLR2

SHLR8

SHLR16R0

R0

R0

Before execution

R0 = H'12345678

After execution

R0 = H'048D159E

Before execution

R0 = H'12345678

After execution

R0 = H'00123456

Before execution

R0 = H'12345678

After execution

R0 = H'00001234

HITACHI 151

6.59

SLEEP (Sleep): System Control Instruction

FormatAbstract

Code

State

T Bit

SLEEP

Sleep

0000000000011011

3—

Description: Sets the CPU into power-down mode. In power-down mode, instruction
execution stops, but the CPU module state is maintained, and the CPU waits for an interrupt
request. If an interrupt is requested, the CPU exits the power-down mode and begins
exception processing.
Note: The number of cycles given is for the transition to sleep mode.
Operation:
SLEEP()/* SLEEP */{PC-=2;
Wait_for_exception;}

Example:SLEEPTransits power-down mode

152 HITACHI6.60

STC (Store Control Register): System Control Instruction

Class: Interrupt disabled instruction
FormatAbstract

Code

State

T Bit

STC

SR,Rn

SR → Rn

0000nnnn00000010

1

—

STC

GBR,Rn

GBR → Rn

0000nnnn00010010

1

—

STC

VBR,Rn

VBR → Rn

0000nnnn00100010

1

—

STC.L

SR,@-Rn

Rn – 4 → Rn, SR → (Rn)

0100nnnn00000011

2

—

STC.L

GBR,@-Rn

Rn – 4 → Rn, GBR → (Rn)

0100nnnn00010011

2

—

STC.L

VBR,@-Rn

Rn – 4 → Rn, VBR → (Rn)

0100nnnn00100011

2—

Description: Stores control registers SR, GBR, or VBR data into a specified destination.
Note: No interrupts are accepted between this instruction and the next instruction. Address
errors are accepted.
Operation:
STCSR(long n)/* STC SR,Rn */{R[n]=SR;
PC+=2;}STCGBR(long n)/* STC GBR,Rn */{R[n]=GBR;
PC+=2;}STCVBR(long n)/* STC VBR,Rn */{R[n]=VBR;
PC+=2;}HITACHI 153

STCMSR(long n)/* STC.L SR,@-Rn */{R[n]-=4;
Write_Long(R[n],SR);
PC+=2;}STCMGBR(long n)/* STC.L GBR,@-Rn */{R[n]-=4;
Write_Long(R[n],GBR);
PC+=2;}STCMVBR(long n)/* STC.L VBR,@-Rn */{R[n]-=4;
Write_Long(R[n],VBR);
PC+=2;}

Examples:Before execution
After execution
STC.L GBR,@-R15 Before execution
After execution
STC

SR,R0

154 HITACHI

R0 = H'FFFFFFFF, SR = H'00000000
R0 = H'00000000
R15 = H'10000004
R15 = H'10000000, @R15 = GBR

6.61

STS (Store System Register): System Control Instruction

Class: Interrupt disabled instruction
FormatAbstract

Code

State

T Bit

STS

MACH,Rn

MACH → Rn

0000nnnn00001010

1

—

STS

MACL,Rn

MACL → Rn

0000nnnn00011010

1

—

STS

PR,Rn

PR → Rn

0000nnnn00101010

1

—

STS.L

MACH,@–Rn

Rn – 4 → Rn, MACH → (Rn)

0100nnnn00000010

1

—

STS.L

MACL,@–Rn

Rn – 4 → Rn, MACL → (Rn)

0100nnnn00010010

1

—

STS.L

PR,@–Rn

Rn – 4 → Rn, PR → (Rn)

0100nnnn00100010

1—

Description: Stores system registers MACH, MACL and PR data into a specified destination.
Note: No interrupts are accepted between this instruction and the next instruction. Address
errors are accepted.
If the system register is MACH in the SH-1 series, the value of bit 9 is transferred to andstored in the higher 22 bits (bits 31 to 10) of the destination. With the SH-2 series, the 32 bitsof MACH are stored directly.
Operation:
STSMACH(long n)/* STS MACH,Rn */{R[n]=MACH;
if ((R[n]&0x00000200)==0)

For SH-1 CPU (these 2 lines not

R[n]&=0x000003FF;

needed for SH-2 CPU)else R[n]|=0xFFFFFC00;
PC+=2;}STSMACL(long n)/* STS MACL,Rn */{R[n]=MACL;
PC+=2;}HITACHI 155

STSPR(long n)/* STS PR,Rn */{R[n]=PR;
PC+=2;}
STSMMACH(long n) /* STS.L MACH,@–Rn */{R[n]–=4;

if ((MACH&0x00000200)==0)

For SH-1 CPU

Write_Long(R[n],MACH&0x000003FF);
else Write_Long(R[n],MACH|0xFFFFFC00)
Write_Long(R[n], MACH);

For SH-2 CPU

PC+=2;}
STSMMACL(long n) /* STS.L MACL,@–Rn */{R[n]–=4;
Write_Long(R[n],MACL);
PC+=2;}
STSMPR(long n)/* STS.L PR,@–Rn */{R[n]–=4;
Write_Long(R[n],PR);
PC+=2;}

Example:STS

MACH,R0

Before execution
After execution

R0 = H'FFFFFFFF, MACH = H'00000000
R0 = H'00000000

STS.L

PR,@–R15

Before execution
After execution

R15 = H'10000004
R15 = H'10000000, @R15 = PR

156 HITACHI6.62

SUB (Subtract Binary): Arithmetic Instruction

FormatSUB

Rm,Rn

Abstract

Code

State

T Bit

Rn – Rm → Rn

0011nnnnmmmm1000

1—

Description: Subtracts general register Rm data from Rn data, and stores the result in Rn. To
subtract immediate data, use ADD #imm,Rn.
Operation:
SUB(long m,long n)/* SUB Rm,Rn */{R[n]-=R[m];PC+=2;}

Example:
SUB

R0,R1

Before execution
After execution

R0 = H'00000001, R1 = H'80000000
R1 = H'7FFFFFFFHITACHI 157

6.63

SUBC (Subtract with Carry): Arithmetic Instruction

FormatSUBC

Rm,Rn

Abstract

Code

State

T Bit

Rn – Rm– T → Rn, Borrow →T

0011nnnnmmmm1010

1

Borrow

Description: Subtracts Rm data and the T bit value from general register Rn, and stores theresult in Rn. The T bit changes according to the result. This instruction is used for subtractionof data that has more than 32 bits.
Operation:
SUBC(long m,long n) /* SUBC Rm,Rn */{unsigned long tmp0,tmp1;

tmp1=R[n]-R[m];tmp0=R[n];R[n]=tmp1-T;
if (tmp0<tmp1) T=1;
else T=0;
if (tmp1<R[n]) T=1;
PC+=2;}

Examples:
CLRT
SUBC

R3,R1

SUBC

R2,R0

158 HITACHI

R0:R1(64 bits) – R2:R3(64 bits) = R0:R1(64 bits)
Before execution
T = 0, R1 = H'00000000, R3 = H'00000001
After execution
T = 1, R1 = H'FFFFFFFF
Before execution
T = 1, R0 = H'00000000, R2 = H'00000000
After execution
T = 1, R0 = H'FFFFFFFF

6.64

SUBV (Subtract with V Flag Underflow Check): Arithmetic
Instruction

FormatSUBV

Abstract
Rm,Rn

Code

Rn – Rm → Rn, Underflow → T 0011nnnnmmmm1011

State

T Bit

1

Underflow

Description: Subtracts Rm data from general register Rn data, and stores the result in Rn. If
an underflow occurs, the T bit is set to 1.
Operation:
SUBV(long m,long n) /* SUBV Rm,Rn */{long dest,src,ans;if ((long)R[n]>=0) dest=0;
else dest=1;
if ((long)R[m]>=0) src=0;
else src=1;
src+=dest;
R[n]-=R[m];if ((long)R[n]>=0) ans=0;
else ans=1;
ans+=dest;if (src==1) {if (ans==1) T=1;
else T=0;}
else T=0;
PC+=2;}

Examples:
SUBV

R0,R1

Before execution
After execution

R0 = H'00000002, R1 = H'80000001
R1 = H'7FFFFFFF, T = 1

SUBV

R2,R3

Before execution
After execution

R2 = H'FFFFFFFE, R3 = H'7FFFFFFE
R3 = H'80000000, T = 1

HITACHI 159

6.65

SWAP (Swap Register Halves): Data Transfer Instruction

FormatAbstract

Code

State

T Bit

SWAP.B Rm,Rn

Rm → Swap upper and lower
halves of lower 2 bytes → Rn

0110nnnnmmmm1000

1—

SWAP.W Rm,Rn

Rm → Swap upper and lower
word → Rn

0110nnnnmmmm1001

1—

Description: Swaps the upper and lower bytes of the general register Rm data, and stores theresult in Rn. If a byte is specified, bits 0 to 7 of Rm are swapped for bits 8 to 15. The upper 16
bits of Rm are transferred to the upper 16 bits of Rn. If a word is specified, bits 0 to 15 of Rm
are swapped for bits 16 to 31.
Operation:
SWAPB(long m,long n) /* SWAP.B Rm,Rn */{unsigned long temp0,temp1;
temp0=R[m]&0xffff0000;
temp1=(R[m]&0x000000ff)<<8;
R[n]=(R[m]>>8)&0x000000ff;
R[n]=R[n]|temp1|temp0;
PC+=2;}
SWAPW(long m,long n) /* SWAP.W Rm,Rn */{unsigned long temp;
temp=(R[m]>>16)&0x0000FFFF;
R[n]=R[m]<<16;
R[n]|=temp;
PC+=2;}

ExamplesSWAP.B R0,R1

Before execution
After execution

R0 = H'12345678
R1 = H'12347856

SWAP.W R0,R1

Before execution
After execution

R0 = H'12345678
R1 = H'56781234

160 HITACHI6.66

TAS (Test and Set): Logic Operation Instruction

FormatTAS.B@Rn

Abstract

Code

State

When (Rn) is 0, 1 → T, 1 → MSB of(Rn)

0100nnnn00011011 4

T Bit
Test
results

Description: Reads byte data from the address specified by general register Rn, and sets the
T bit to 1 if the data is 0, or clears the T bit to 0 if the data is not 0. Then, data bit 7 is set to
1, and the data is written to the address specified by Rn. During this operation, the bus is notreleased.
Operation:
TAS(long n)/* TAS.B @Rn */{long temp;

temp=(long)Read_Byte(R[n]); /* Bus Lock enable */if (temp==0) T=1;
else T=0;
temp|=0x00000080;
Write_Byte(R[n],temp);/* Bus Lock disable */PC+=2;}

Example:
_LOOP

TAS.B

@R7

BF

_LOOP

R7 = 1000
Loops until data in address 1000 is 0

HITACHI 161

6.67

TRAPA (Trap Always): System Control Instruction

Format
TRAPA#imm

Abstract

Code

State

T Bit

PC/SR → Stack area, (imm × 4 +VBR) → PC

11000011iiiiiiii

8—

Description: Starts the trap exception processing. The PC and SR values are stored on thestack, and the program branches to an address specified by the vector. The vector is amemory address obtained by zero-extending the 8-bit immediate data and then quadrupling it.
The PC points the starting address of the next instruction. TRAPA and RTE are both used forsystem calls.
Operation:
TRAPA(long i) /* TRAPA #imm */{long imm;

imm=(0x000000FF & i);R[15]-=4;
Write_Long(R[15],SR);
R[15]-=4;
Write_Long(R[15],PC–2);
PC=Read_Long(VBR+(imm<<2))+4;}

Example:Address
VBR+H'80.data.l

10000000..........
TRAPA

#H'20

TST

#0,R0

Branches to an address specified by data in address
VBR + H'80
← Return address from the trap routine (stacked PC
value)...........
..........
100000000

XOR

100000002

RTE

100000004

NOP

162 HITACHI

R0,R0← Trap routine entrance

Returns to the TST instruction
Executes NOP before RTE

6.68

TST (Test Logical): Logic Operation Instruction

FormatAbstract

Code

State

T Bit

TST

Rm,Rn

Rn & Rm, when result is
0, 1 → T

0010nnnnmmmm1000

1

Test
results

TST#imm,R0

R0 & imm, when result is
0, 1 → T

11001000iiiiiiii

1

Test
results(R0 + GBR) & imm, when 11001100iiiiiiii
result is 0, 1 → T

3

Test
results

TST.B#imm,@(R0,GBR)

Description: Logically ANDs the contents of general registers Rn and Rm, and sets the T bit
to 1 if the result is 0 or clears the T bit to 0 if the result is not 0. The Rn data does notchange. The contents of general register R0 can also be ANDed with zero-extended 8-bit
immediate data, or the contents of 8-bit memory accessed by indirect indexed GBR
addressing can be ANDed with 8-bit immediate data. The R0 and memory data do notchange.
Operation:
TST(long m,long n)/* TST Rm,Rn */{if ((R[n]&R[m])==0) T=1;
else T=0;
PC+=2;}TSTI(long i) /* TEST #imm,R0 */{long temp;

temp=R[0]&(0x000000FF & (long)i);if (temp==0) T=1;
else T=0;
PC+=2;}TSTM(long i) /* TST.B #imm,@(R0,GBR) */{long temp;

HITACHI 163

temp=(long)Read_Byte(GBR+R[0]);temp&=(0x000000FF & (long)i);if (temp==0) T=1;
else T=0;
PC+=2;}

Examples:
TST

TST

TST.B

R0,R0

#H'80,R0

Before execution

R0 = H'00000000

After execution

T=1

Before execution

R0 = H'FFFFFF7F

After execution

T=1#H'A5,@(R0,GBR) Before execution

After execution

164 HITACHI@(R0,GBR) = H'A5
T=0

6.69

XOR (Exclusive OR Logical): Logic Operation Instruction

FormatAbstract

Code

State

T Bit

XOR

Rm,Rn

Rn ^ Rm → Rn

0010nnnnmmmm1010

1

—

XOR

#imm,R0

R0 ^ imm → R0

11001010iiiiiiii

1

—

XOR.B

#imm,@(R0,GBR) (R0 + GBR) ^ imm → (R0+ GBR)

11001110iiiiiiii

3—

Description: Exclusive ORs the contents of general registers Rn and Rm, and stores theresult in Rn. The contents of general register R0 can also be exclusive ORed with zeroextended 8-bit immediate data, or 8-bit memory accessed by indirect indexed GBR
addressing can be exclusive ORed with 8-bit immediate data.
Operation:
XOR(long m,long n)/* XOR Rm,Rn */{R[n]^=R[m];PC+=2;}XORI(long i) /* XOR #imm,R0 */{R[0]^=(0x000000FF & (long)i);PC+=2;}XORM(long i) /* XOR.B #imm,@(R0,GBR) */{long temp;

temp=(long)Read_Byte(GBR+R[0]);temp^=(0x000000FF & (long)i);
Write_Byte(GBR+R[0],temp);
PC+=2;}HITACHI 165

Examples:
XOR

R0,R1

Before execution R0 = H'AAAAAAAA, R1 = H'55555555
After execution R1 = H'FFFFFFFF

XOR#H'F0,R0

Before execution R0 = H'FFFFFFFF
After execution R0 = H'FFFFFF0F

XOR.B #H'A5,@(R0,GBR)

Before execution @(R0,GBR) = H'A5
After execution @(R0,GBR) = H'00

166 HITACHI6.70

XTRCT (Extract): Data Transfer Instruction

Format
XTRCT

Rm,Rn

Abstract

Code

State

T Bit

Center 32 bits of Rm and Rn →Rn

0010nnnnmmmm1101

1—

Description: Extracts the middle 32 bits from the 64 bits of general registers Rm and Rn, andstores the 32 bits in Rn (figure 6.13).
MSB

LSB

MSB

Rm

LSB
Rn

Rn

Figure 6.13

Extract

Operation:
XTRCT(long m,long n)/* XTRCT Rm,Rn */{unsigned long temp;

temp=(R[m]<<16)&0xFFFF0000;
R[n]=(R[n]>>16)&0x0000FFFF;
R[n]|=temp;
PC+=2;}

Example:
XTRCT

R0,R1

Before execution
After execution

R0 = H'01234567, R1 = H'89ABCDEF
R1 = H'456789AB

HITACHI 167

Section 7 Pipeline Operation
This section describes the operation of the pipelines for each instruction. This information isprovided to allow calculation of the required number of CPU instruction execution states(system clock cycles).

7.1

Basic Configuration of Pipelines

Pipelines are composed of the following five stages:• IF (Instruction fetch) Fetches an instruction from the memory in which the program isstored.
• ID (Instruction decode)
Decodes the instruction fetched.
• EX (Instruction execution)
Performs data operations and address calculations
according to the results of decoding.
• MA (Memory access)Accesses data in memory. Generated by instructions that involve
memory access, with some exceptions.
• WB (Write back)
Returns the results of the memory access (data) to a register.
Generated by instructions that involve memory loads, with some exceptions.
As shown in figure 7.1, these stages flow with the execution of the instructions and thereby
constitute a pipeline. At a given instant, five instructions are being executed simultaneously.
All instructions have at least 3 stages: IF, ID, and EX. Most, but not all, have stages MA and
WB as well. The way the pipeline flows also varies with the type of instruction. The basic
pipeline flow is as shown in figure 7.1; some pipelines differ, however, because of contention
between IF and MA. In figure 7.1, the period in which a single stage is operating is called aslot.
: SlotInstruction 1

IF

Instruction 2
Instruction 3

ID

EX

MA WB

IF

ID

EX

MA WB

IF

ID

EX

MA

WB

IF

ID

EX

MA WB

IF

ID

EX

MA WB

IF

ID

EX

Instruction 4
Instruction 5
Instruction 6

Instruction
stream

MA WB

Time

Figure 7.1

168 HITACHI

Basic Structure of Pipeline Flow

7.2

Slot and Pipeline Flow

The time period in which a single stage operates is called a slot. Slots must follow the rules
described below.
7.2.1

Instruction Execution

Each stage (IF, ID, EX, MA, and WB) of an instruction must be executed in one slot. Two or
more stages cannot be executed within one slot (figure 7.2), with exception of WB and MA.
Since WB is executed immediately after MA, however, some instructions may execute MA
and WB within the same slot.
X
Instruction 1: SlotIF

Instruction 2
Note:

ID

EX

IF

ID

EX

MA WB

ID and EX of instruction 1 are being executed in the same slot.

Figure 7.2
7.2.2

MA WB

Impossible Pipeline Flow 1

Slot Sharing

A maximum of one stage from another instruction may be set per slot, and that stage must be
different from the stage of the first instruction. Identical stages from two different instructions
may never be executed within the same slot (figure 7.3).
X: SlotInstruction 1

IF

ID

EX

MA WB

Instruction 2

IF

ID

EX

MA WB

IF

ID

EX

MA

WB

Instruction 4

IF

ID

EX

MA WB

Instruction 5

IF

ID

EX

MA WB

Instruction 3

Note:

Same stage of another instruction is being executed in same slot.

Figure 7.3

Impossible Pipeline Flow 2

HITACHI 169

7.2.3

Slot Length

The number of states (system clock cycles) S for the execution of one slot is calculated withthe following conditions:• S = (the cycles of the stage with the highest number of cycles of all instruction stages
contained in the slot)
This means that the instruction with the longest stage stalls others with shorter stages.
• The number of execution cycles for each stage:
 IF
The number of memory access cycles for instruction fetch
 ID
Always one cycle
 EX
Always one cycle
 MA
The number of memory access cycles for data access WB
Always one cycle
As an example, figure 7.4 shows the flow of a pipeline in which the IF (memory access for
instruction fetch) of instructions 1 and 2 are two cycles, the MA (memory access for data
access) of instruction 1 is three cycles and all others are one cycle. The dashes indicate theinstruction is being stalled.

(2)
Instruction 1
Instruction 2

IF

(2)
IF

(3)

(1)

ID

—

EX

MA

MA MA

WB

IF

IF

ID

EX

—

MA

Figure 7.4

170 HITACHI

(1)

—

(1)
WB

Slots Requiring Multiple Cycles: SlotNumber ofcycles7.3

Number of Instruction Execution States

The number of instruction execution states is counted as the interval between execution of
EX stages. The number of states between the start of the EX stage for instruction 1 and thestart of the EX stage for the following instruction (instruction 2) is the execution time for
instruction 1.
For example, in a pipeline flow like that shown in figure 7.5, the EX stage interval between
instructions 1 and 2 is five cycles, so the execution time for instruction 1 is five cycles. Since
the interval between EX stages for instructions 2 and 3 is one state, the execution time of
instruction 2 is one state.
If a program ends with instruction 3, the execution time for instruction 3 should be calculated
as the interval between the EX stage of instruction 3 and the EX stage of a hypothetical
instruction 4, using an MOV Rm, Rn that follows instruction 3. (In the case of figure 7.5, theexecution time of instruction 3 would thus be one cycle.) In this example, the MA of
instruction 1 and the IF of instruction 4 are in contention. For operation during the contention
between the MA and IF, see section 7.4, Contention Between Instruction Fetch (IF) andMemory Access (MA). The execution time between instructions 1 and 3 in figure 7.5 is sevenstates (5 + 1 + 1).
: Slot(2)
Instruction 1

IF

(2)
IF

Instruction 2

(1)

(1)

ID

—

EX

—

MA

MA

MA

WB

IF

IF

ID

—

—

—

—

EX

IF

IF

—

—

—

ID

EX

MA

IF

ID

EX )

Instruction 3(Instruction 4 : MOV Rm, Rn

Figure 7.5

(4)

(2)

How Instruction Execution States Are Counted

HITACHI 171

7.4

Contention Between Instruction Fetch (IF) and Memory Access
(MA)

7.4.1

Basic Operation When IF and MA are in Contention

The IF and MA stages both access memory, so they cannot operate simultaneously. When the
IF and MA stages both try to access memory within the same slot, the slot splits as shown infigure 7.6. When there is a WB, it is executed immediately after the MA ends.
A

B

C

D

E

F

G
: SlotInstruction 1

IF

Instruction 2

ID

EX

MA WB

IF

ID

EX

MA

IF

ID

EX

IF

ID

EX

IF

ID

Instruction 3
Instruction 4
Instruction 5

MA of instruction 1 and IF of instruction 4contend at D

WB

MA of instruction 2 and IF of instruction 5contend at E
EX

When MA and IF are in contention, the following occurs:

A

B

C

D

E

F

IF

ID

EX

MA WB

IF

ID

—

EX

MA

WB

IF

—

ID

—

EX

IF

—

ID

EX

IF

ID

G
: SlotInstruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5

Figure 7.6

Split at D
Split at E

EX

Operation When IF and MA Are in Contention

The slots in which MA and IF contend are split. MA is given priority to execute in the firsthalf (when there is a WB, it immediately follows the MA), and the EX, ID, and IF are
executed simultaneously in the latter half. For example, in figure 7.6 the MA of instruction 1
is executed in slot D while the EX of instruction 2, the ID of instruction 3 and IF of
instruction 4 are executed simultaneously thereafter. In slot E, the MA of instruction 2 isgiven priority and the EX of instruction 3, the ID of instruction 4 and the IF of instruction 5
executed thereafter.
The number of states for a slot in which MA and IF are in contention is the sum of thenumber of memory access cycles for the MA and the number of memory access cycles for theIF.

172 HITACHI

7.4.2The Relationship Between IF and the Location of Instructions in On-Chip
ROM/RAM or On-Chip Memory

When the instruction is located in the on-chip memory (ROM or RAM) or on-chip cache of
the SH microcomputer, the SH microcomputer accesses the on-chip memory in 32-bit units.
The SH microcomputer instructions are all fixed at 16 bits, so basically 2 instructions can be
fetched in a single IF stage access.
If an instruction is located on a longword boundary, an IF can get two instructions at each
instruction fetch. The IF of the next instruction does not generate a bus cycle to fetch an
instruction from memory. Since the next instruction IF also fetches two instructions, theinstruction IFs after that do not generate a bus cycle either.
This means that IFs of instructions that are located so they start from the longword boundaries
within instructions located in on-chip memory (the position when the bottom two bits of the
instruction address are 00 is A1 = 0 and A0 = 0) also fetch two instructions. The IF of thenext instruction does not generate a bus cycle. IFs that do not generate bus cycles are written
in lower case as ‘if’. These ‘if’s always take one state.
When branching results in a fetch from an instruction located so it starts from the wordboundaries (the position when the bottom two bits of the instruction address are 10 is A1 = 1,
A0 = 0), the bus cycle of the IF fetches only the specified instruction more than one of said
instructions. The IF of the next instruction thus generates a bus cycle, and fetches two
instructions. Figure 7.7 illustrates these operations.

HITACHI 173

32 bits: SlotInstruc- Instruc- ... Instruction 1
tion 1tion 2
Instruction 2...
Instruction 3
Instruc- Instruction 3

IF

ID

EX

if

ID

EX

IF

ID

EX

if

ID

EX

IF

ID

EX

if

ID

tion 4

Instruction 4...
Instruction 5
Instruc- Instruction 5tion 6
Instruction 6(On-chip memory
or on-chip cache)

IF
if

EX

: Bus cycle generated: No bus cycle

Fetching from an instruction (instruction 1) located on a longword boundary: SlotInstruc... Instruction 2tion 2IF... Instruction 3
Instruc- Instruction 3tion 4
Instruc- Instruction 5tion 6

Instruction 4... Instruction 5
Instruction 6
IF
if

ID

EX

IF

ID

EX

if

ID

EX

IF

ID

EX

if

ID

EX

: Bus cycle generated: No bus cycle

Fetching from an instruction (instruction 2) located on a word boundary

Figure 7.7
7.4.3

Relationship Between IF and Location of Instructions in On-Chip Memory

Relationship Between Position of Instructions Located in On-Chip ROM/RAMor On-Chip Memory and Contention Between IF and MA

When an instruction is located in on-chip memory (ROM/RAM) or on-chip cache, there are
instruction fetch stages (‘if’ written in lower case) that do not generate bus cycles as
explained in section 7.4.2 above. When an if is in contention with an MA, the slot will not
split, as it does when an IF and an MA are in contention, because ifs and MAs can be
executed simultaneously. Such slots execute in the number of states the MA requires formemory access, as illustrated in figure 7.8.
When programming, avoid contention of MA and IF whenever possible and pair MAs with ifs
to increase the instruction execution speed. Instructions that have 4 (5)-stage pipelines of IF,
ID, EX, MA, (WB) prevent stalls when they start from the longword boundaries in on-chip

174 HITACHImemory (the position when the bottom 2 bits of instruction address are 00 is A1 = 0 and A0 =0) because the MA of the instruction falls in the same slot as ifs that follow.
A

B

ID

EX MA

WB

if

ID

EX

MA

WB

IF

ID

—

EX

if

—

ID

EX

IF

ID

EX

if

ID

32 bits
Instruc- Instruc- ... Instruction 1
tion 1tion 2
Instruction 2
Instruc- Instruc- ... Instruction 3tion 3tion 4
Instruction 4... Instruction 5
Instruc- Instruction 5tion 6(On-chip memory
or on-chip cache)IF: SlotInstruction 6
IF: Splits

if: Does not split

EX

MA in slot A is in contention with an if, so no split occurs.
MA in slot B is in contention with an IF, so it splits.

Figure 7.8

7.5

Relationship Between the Location of Instructions in On-Chip Memory andContention Between IF and MA

Effects of Memory Load Instructions on Pipelines

Instructions that involve loading from memory return data to the destination register during
the WB stage that comes at the end of the pipeline. The WB stage of such a load instruction(load instruction 1) will thus come after the EX stage of the instruction that immediately
follows it (instruction 2).
When instruction 2 uses the same destination register as load instruction 1, the contents ofthat register will not be ready, so any slot containing the MA of instruction 1 and EX of
instruction 2 will split. The destination register of load instruction 1 is the same as thedestination (not the source) of instruction 2, so it splits.
When the destination of load instruction 1 is the status register (SR) and the flag in it isfetched by instruction 2 (as ADDC does), a split occurs. No split occurs, however, in thefollowing cases:• When instruction 2 is a load instruction and its destination is the same as that of load
instruction 1.
• When instruction 2 is Mac @Rm+, @Rn+, and the destination of load instruction 1 are
the same.
The number of states in the slot generated by the split is the number of MA cycles plus thenumber of IF (or if) cycles, as illustrated in figure 7.9. This means the execution speed will

HITACHI 175

be lowered if the instruction that will use the results of the load instruction is placed
immediately after the load instruction. The instruction that uses the result of the load
instruction will not slow down the program if placed one or more instructions after the load
instruction.
: SlotLoad instruction 1 (MOV.W @R0, R1)
Instruction 2 (ADD R1, R2)
Instruction 3
Instruction 4

Figure 7.9

7.6

IF

ID

EX

MA WB

IF

ID

—

EX

IF

—

ID

EX

.....

IF

ID

.....

Effects of Memory Load Instructions on the Pipeline

Programming Guide

To improve instruction execution speed, consider the following when programming:• To prevent contention between MA and IF, locate instructions that have MA stages sothey start from the longword boundaries of on-chip memory (the position when the bottom
two bits of the instruction address are 00 is A1 = 0 and A0 = 0) wherever possible.
• The instruction that immediately follows an instruction that loads from memory should not
use the same destination register as the load instruction.
• Locate instructions that use the multiplier nonconsecutively. Also locate nonconsecutively
an access to the MACH or MACL register for fetching the results from the multiplier andan instruction that uses the multiplier.

176 HITACHI

7.7

Operation of Instruction Pipelines

This section describes the operation of the instruction pipelines. By combining these with therules described so far, the way pipelines flow in a program and the number of instruction
execution states can be calculated.
In the following figures, “Instruction A” refers to the instruction being described. When “IF”
is written in the instruction fetch stage, it may refer to either “IF” or “if”. When there iscontention between IF and MA, the slot will split, but the manner of the split is notdescribed in the tables, with a few exceptions. When a slot has split, see section 7.4,
Contention Between Instruction Fetch (IF) and Memory Access (MA). Base your response on
the rules for pipeline operation given there.
Table 7.1 lists the format for number of instruction stages and execution states:
Table 7.1

Format for the Number of Stages and Execution States for Instructions

Type

Category

Stage

State

Functional
types

Instructions arecategorizedbased onoperations

Numberofstagesin an
instruction

Number Contention that
occursofexecutionstateswhennocontention
occursTable 7.2

Number of Instruction Stages and Execution States

Type

Category

Stage

State

Contention

Instruction

Datatransfer
instructions

Registerregistertransfer
instructions

3

1

—

MOV

#imm,Rn

MOV

Rm,Rn

MOVA

@(disp,PC),R0

MOVT

Rn

Contention

Instruction
Corresponding instructions
represented by mnemonic

SWAP.B Rm,Rn
SWAP.W Rm,Rn
XTRCT

Rm,Rn

HITACHI 177

Table 7.2

Number of Instruction Stages and Execution States (cont)Type

Category

Stage

State

Contention

Instruction

Datatransfer
instructions(cont)

Memoryload
instructions

5

1• Contention
occurs if the
instruction
placedimmediately
after this one
uses the same
destination
register

MOV.W@(disp,PC),Rn

MOV.L@(disp,PC),Rn

MOV.B@Rm,RnMOV.W@Rm,RnMOV.L@Rm,RnMOV.B@Rm+,Rn

MOV.W@Rm+,Rn• MA contends
with IF

MOV.L@Rm+,Rn

MOV.B@(disp,Rm),R0

MOV.W@(disp,Rm),R0

MOV.L@(disp,Rm),Rn

MOV.B@(R0,Rm),Rn

MOV.W@(R0,Rm),Rn

MOV.L@(R0,Rm),Rn

MOV.B@(disp,GBR),R0

MOV.W@(disp,GBR),R0

MOV.L@(disp,GBR),R0

MOV.B

Rm,@RnMOV.W

Rm,@RnMOV.L

Rm,@RnMOV.B

Rm,@–Rn

MOV.W

Rm,@–Rn

MOV.L

Rm,@–Rn

MOV.B

R0,@(disp,Rn)

MOV.W

R0,@(disp,Rn)

MOV.L

Rm,@(disp,Rn)

MOV.B

Rm,@(R0,Rn)

MOV.W

Rm,@(R0,Rn)

MOV.L

Rm,@(R0,Rn)

MOV.B

R0,@(disp,GBR)

MOV.W

R0,@(disp,GBR)

MOV.L

R0,@(disp,GBR)

Memorystore
instructions

178 HITACHI

4

1• MA contends
with IFTable 7.2

Number of Instruction Stages and Execution States (cont)Type

Category

Stage

State

Contention

Instruction

Arithmetic
instructions
betweenregisters(except
multiplication
instructions)

3

1

—

ADD

Rm,Rn

ADD

#imm,Rn

ADDC

Rm,Rn

ADDV

Rm,Rn

Arithmetic
instructions

CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ Rn
CMP/PL Rn
CMP/STR Rm,Rn
DIV1

Rm,Rn

DIV0S

Rm,Rn

DIV0U
DT

Rn*3

EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
NEG

Rm,Rn

NEGC

Rm,Rn

SUB

Rm,Rn

SUBC

Rm,Rn

SUBV

Rm,Rn

Notes 1. In the SH-2 CPU, multiply/accumulate instructions are 7 stage s, multiply instructions 6
stages; in the SH-1 CPU, multiply/accumulate instructions are 8 stages, multiply
instructions 7 stages
2. The normal minimum number of execution states (The number in parentheses is thenumber of states when there is contention with preceding/following instructions)
3. SH-2 CPU instructions

HITACHI 179

Table 7.2

Number of Instruction Stages and Execution States (cont)Type

Category

Arithmetic
instructions(cont)

Multiply/
7/8*1
accumulate
instructions

Stage

State

Contention

Instruction

3/(2)*2• Multiplier contention
occurs when an
instruction that uses
the multiplier follows
a MAC instruction

MAC.W@Rm+,@Rn+

MAC.L@Rm+,@Rn+* 3• MA contends with IF
Doublelength
multiply/
accumulate
instruction(SH-2 CPUonly)

9

3/(2 to4)* 2• Multiplier contention
occurs when an
instruction that uses
the multiplier follows
a MAC instruction• MA contends with IF

Multiplic6/7*1
ation
instructions

1 to 3*2• Multiplier contention
occurs when an
instruc-tion that uses
the multiplier follows
a MUL instruction

MULS.W Rm,Rn
MULU.W Rm,Rn• MA contends with IF
Doublelength
multiply/
accumulate
instruction(SH-2 CPU
only)
Logic
operation
instructions

93
Registerregister
logic
operation
instructions

2 to 4*2• Multiplier contention
occurs when an
instruction that uses
the multiplier follows
a MAC instruction• MA contends with IF

1—

DMULS.L
Rm,Rn*3
DMULU.L
Rm,Rn*3
MUL.L

Rm,Rn*3

AND

Rm,Rn

AND

#imm,R0

NOT

Rm,Rn

OR

Rm,Rn

OR

#imm,R0

TST

Rm,Rn

TST

#imm,R0

XOR

Rm,Rn

XOR

#imm,R0

Notes 1. In the SH-2 CPU, multiply/accumulate instructions are 7 stages, multiply instructions 6
stages; in the SH-1 CPU, multiply/accumulate instructions are 8 stages, multiply
instructions 7 stages
2. The normal minimum number of execution states (The number in parentheses is thenumber of cycles when there is contention with following instructions)
3. SH-2 CPU instructions

180 HITACHITable 7.2

Number of Instruction Stages and Execution States (cont)Type

Category

Stage State

Contention

Instruction

Logic
operation
instructions(cont)

Memory logic
operations
instructions

6• MA contends
with IF

AND.B#imm,@(R0,GBR)

OR.B#imm,@(R0,GBR)

TST.B#imm,@(R0,GBR)

XOR.B#imm,@(R0,GBR)

Shift
instructions

3

TAS instruction

64• MA contends
with IF

TAS.B

@Rn

Shift
instructions

3

1

—

ROTL

Rn

ROTR

Rn

ROTCL

Rn

ROTCR

Rn

SHAL

Rn

SHAR

Rn

SHLL

Rn

SHLR

Rn

SHLL2

Rn

SHLR2

Rn

SHLL8

Rn

SHLR8

Rn

SHLL16 Rn
SHLR16 Rn
Branchinstructions

Conditional
branchinstructions

3

Delayedconditional
branchinstructions(SH-2 CPU
only)

3

Uncondi tional
branchinstructions

3

3/1*4

2/1*4

2

—

—

—

BF

label

BT

label

BF/S

label*3

BT/Slabel*3

BRA

label

BRAF

Rm*3

BSR

label

BSRF

Rm*3

JMP

@Rm

JSR

@Rm

RTS
Notes 3. SH-2 CPU instruction
4. One state when there is no branch

HITACHI 181

Table 7.2

Number of Instruction Stages and Execution States (cont)Type

Category

Stage

State

Contention

Instruction

Systemcontrol
instructions

Systemcontrol ALU
instructions

3

1

—

CLRT
LDC

Rm,SR

LDC

Rm,GBRLDC

Rm,VBR

LDS

Rm,PR

NOP
SETT

LDC.L
instruction

5

3

STC

SR,Rn

STC

GBR,RnSTC

VBR,Rn

STS

PR,Rn

LDC.L
• Contention
occurs when an
LDC.L
instruction that
LDC.L
uses the same
destination
register is placed
immediately after
this instruction@Rm+,SR@Rm+,GBR@Rm+,VBR• MA contends
with IF
STC.L
instructions

LDS.L
instructions
(PR)

4

5

2

1

• MA contends
with IF• Contention
occurs when an
instruction thatuses the same
destination
register is placed
immediately after
this instruction

STC.L

SR,@–Rn

STC.L

GBR,@–Rn

STC.L

VBR,@–Rn

LDS.L@Rm+,PR

STS.L

PR,@–Rn• MA contends
with IF
STS.L
instruction(PR)

182 HITACHI

4

1• MA contends
with IFTable 7.2

Number of Instruction Stages and Execution States (cont)Type

Category

Stage

State

Contention

Instruction

Systemcontrol
instructions(cont)

Register →MAC
transfer
instruction

4

1• Contention
occurs withmultiplier

CLRMAC

Memory →MACtransfer
instructions

4

MAC →
registertransfer
instruction

5• MA contends
with IF1• Contention
occurs withmultiplier

LDS

Rm,MACH

LDS

Rm,MACL

LDS.L@Rm+,MACH

LDS.L@Rm+,MACL

STS

MACH,RnSTS

MACL,Rn

STS.L

MACH,@–Rn

STS.L

MACL,@–Rn• MA contends
with IF1• Contention
occurs withmultiplier• Contention
occurs when an
instruction thatuses the same
destination
register is placed
immediately after
this instruction• MA contends
with IFMAC →memorytransfer
instruction

4

RTE
instruction

5

4

—

RTE

TRAP
instruction

9

8

—

TRAPA

SLEEP
instruction

3

3

—

SLEEP

1

• Contention
occurs withmultiplier• MA contends
with IF#imm

HITACHI 183

7.7.1

Data Transfer Instructions

Register-Register Transfer Instructions: Include the following instruction types:
•
•
•
•
•
•
•

MOV
MOV
MOVA
MOVT
SWAP.B
SWAP.W
XTRCT#imm, Rn
Rm, Rn@(disp, PC), R0
Rn
Rm, RnRm, RnRm, Rn: SlotInstruction A
Next instruction
Third instruction......

Figure 7.10

IF

ID

EX

IF

ID

EX ......

IFID

EX ......

Register-Register Transfer Instruction Pipeline

Operation: The pipeline ends after three stages: IF, ID, and EX. Data is transferred in the EX
stage via the ALU.
Memory Load Instructions: Include the following instruction types:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B

184 HITACHI@(disp, PC), Rn@(disp, PC), Rn@Rm, Rn@Rm, Rn@Rm, Rn@Rm+, Rn
@Rm+, Rn
@Rm+, Rn@(disp, Rm), R0@(disp, Rm), R0@(disp, Rm), Rn@(R0, Rm), Rn@(R0, Rm), Rn@(R0, Rm), Rn@(disp, GBR), R0

• MOV.W• MOV.L@(disp, GBR), R0@(disp, GBR), R0: SlotInstruction A

IF

Next instruction
Third instruction......

Figure 7.11

ID

EX MB

IF

ID

EX

WB
.....

IF

ID

EX

.....

Memory Load Instruction Pipeline

Operation: The pipeline has five stages: IF, ID, EX, MA, and WB (figure 7.11). If an
instruction that uses the same destination register as this instruction is placed immediately
after it, contention will occur. (See Section 7.5, Effects of Memory Load Instructions on
Pipelines.)
Memory Store Instructions: Include the following instruction types:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L

Rm, @Rn
Rm, @Rn
Rm, @Rn
Rm, @–Rn
Rm, @–Rn
Rm, @–Rn
R0, @(disp, Rn)
R0, @(disp, Rn)
Rm, @(disp, Rn)
Rm, @(R0, Rn)
Rm, @(R0, Rn)
Rm, @(R0, Rn)
R0, @(disp, GBR)
R0, @(disp, GBR)
R0, @(disp, GBR)HITACHI 185

: Slot
Instruction A
Next instruction
Third instruction......

Figure 7.12

IF

ID

EX MA

IF

ID

EX

.....

IF

ID

EX

.....

Memory Store Instruction Pipeline

Operation: The pipeline has four stages: IF, ID, EX, and MA (figure 7.12). Data is not
returned to the register so there is no WB stage.
7.7.2

Arithmetic Instructions

Arithmetic Instructions between Registers (Except Multiplication Instructions): Include
the following instruction types:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

ADDRm, Rn
ADD#imm, Rn
ADDC
Rm, RnADDVRm, Rn
CMP/EQ#imm, R0
CMP/EQRm, Rn
CMP/HSRm, RnCMP/GERm, Rn
CMP/HIRm, RnCMP/GTRm, Rn
CMP/PZRn
CMP/PLRn
CMP/STR Rm, Rn
DIV1
Rm, RnDIV0S
Rm, Rn
DIV0U
DT Rn(SH-2 CPU only)
EXTS.BRm, RnEXTS.WRm, Rn
EXTU.BRm, Rn
EXTU.WRm, RnNEG Rm, Rn
NEGC
Rm, Rn186 HITACHI• SUB Rm, Rn• SUBCRm, Rn• SUBVRm, Rn: SlotInstruction A
Next instruction
Third instruction......

Figure 7.13

IF

ID

EX

IF

ID

EX

.....

IF

ID

EX

.....

Pipeline for Arithmetic Instructions between Registers Except
Multiplication Instructions

Operation: The pipeline has three stages: IF, ID, and EX (figure 8.13). The data operation iscompleted in the EX stage via the ALU.

HITACHI 187

Multiply/Accumulate Instruction (SH-1 CPU): Includes the following instruction type:• MAC.W@Rm+, @Rn+
: Slot
MAC.W
Next instruction
Third instruction......

Figure 7.14

IF

ID

EX

MA MA mm mm mm

IF

—

ID

EX

MA WB

IF

ID

EX

MA

WB

Multiply/Accumulate Instruction Pipeline

Operation: The pipeline has eight stages: IF, ID, EX, MA, MA, mm, mm, and mm (figure8.14). The second MA reads the memory and accesses the multiplier. The mm indicates thatthe multiplier is operating. The mm operates for three cycles after the final MA ends,
regardless of slot. The ID of the instruction after the MAC.W instruction is stalled for one slot.
The two MAs of the MAC.W instruction, when they contend with IF, split the slots as
described in section 7.4, Contention Between Instruction Fetch (IF) and Memory Access(MA).
When an instruction that does not use the multiplier follows the MAC.W instruction, the
MAC.W instruction may be considered to be five-stage pipeline instructions of IF, ID, EX,
MA, and MA. In such cases, the ID of the next instruction simply stalls one slot andthereafter the pipeline operates normally. When an instruction that uses the multiplier comes
after the MAC.W instruction, contention occurs with the multiplier, so operation is not asnormal. This occurs in the following cases:
1.
2.
3.
4.
5.
6.

When a MAC.W instruction is located immediately after another MAC.W instruction
When a MULS.W instruction is located immediately after a MAC.W instruction
When an STS (register) instruction is located immediately after a MAC.W instruction
When an STS.L (memory) instruction is located immediately after a MAC.W instruction
When an LDS (register) instruction is located immediately after a MAC.W instruction
When an LDS.L (memory) instruction is located immediately after a MAC.W instruction

188 HITACHI1. When a MAC.W instruction is located immediately after another MAC.W instruction
When the second MA of a MAC.W instruction contends with an mm generated by apreceding multiplier-type instruction, the bus cycle of that MA is extended until the mmends (the M—A shown in the dotted line box below) and that extended MA occupies one
slot.
If one or more instruction not related to the multiplier is located between the MAC.W
instructions, multiplier contention between MAC instructions does not cause stalls (figure7.15).
: Slot
IF

MAC.W
MAC.W

ID

EX

MA MA mm mm mm

IF

—

ID

EX

MA

M——A

IF

—

ID

EX

Third instruction......

mm mm mm
MA .....

—: Slot
MAC.W

IF

Other instruction

ID

EX

MA MA mm mm mm

IF

—

ID

EX

MA WB

IF

ID

EX

MAC.W
......

Figure 7.15MA

MA mm mm mm .....

Unrelated Instructions between MAC.W Instructions

Sometimes consecutive MAC.Ws may not have multiplier contention even when MA andIF contention causes misalignment of instruction execution. Figure 7.16 illustrates a caseof this type. This figure assumes MA and IF contention.
: Slot
MAC.W
MAC.W

if

ID

EX MA MA mm mm mm

IF

—

MAC.W
MAC.W
.....

Figure 7.16

ID

EX MA

—

MA mm mm mm

if

—

—

ID

EX MA M——A mm mm mm

IF

—

ID

EX

— MA M——A mm .....

Consecutive MAC.Ws without Misalignment

HITACHI 189

When the second MA of the MAC.W instruction is extended until the mm ends,
contention between MA and IF will split the slot, as usual. Figure 7.17 illustrates a case ofthis type. This figure assumes MA and IF contention.
: Slot
MAC.W IFID EX MA —

MAC.W

if

Other instruction——

ID EX MA M——A mm mm mm
IF — ID — — EX MA .....
if

Other instruction
Other instruction......

——

ID

EX .....

IF

Figure 7.17

190 HITACHI

MA mm mm mm

MA and IF Contention

2. When a MULS.W instructions is located immediately after a MAC.W instruction
A MULS.W instruction has an MA stage for accessing the multiplier. When the MA of the
MULS.W instruction contends with an operating MAC instruction multiplier (mm), theMA is extended until the mm ends (the M—A shown in the dotted line box in figure 7.18)
to create a single slot. When two or more instructions not related to the multiplier comebetween the MAC.W and MULS.W instructions, MAC.W and MULS.W contention does
not cause stalling. When the MULS.W MA and IF contend, the slot is split.
: Slot
MAC.W

IF

MULS.WID

EX MA MA mm mm mm

IF—

Other instruction......

ID

EX

M————A

IF

ID

EX

—

mm mm mm
— MA .....

: Slot
MAC.W

IF

Other instruction

ID

EX MA MA mm mm mm

IF—

MULS.W

ID

EX

IF

ID

EX

IF

ID

Other instruction......

M——A mm mm mm
EX — MA .....

: Slot
MAC.W
Other instruction
Other instruction
MULS.W
Other instruction......

Figure 7.18

IFID

EX MA MA mm mm mm

IF

—

ID

EX MA WB

IF

ID

EX MA WB

IF

ID
IF

EX MA mm mm mm
ID EX MA .....

MULS.W Instruction Immediately After a MAC.W Instruction

HITACHI 191

3. When an STS (register) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are stored in a general-purpose register using an
STS instruction, an MA stage for accessing the multiplier is added to the STS instruction,
as described later. When the MA of the STS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.19) to create a single slot. The MA of the STS contends with the IF.
Figure 7.19 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.W

IF

STS

ID

EX MA

—

if

—

—

ID

MA mm mm mm
EX M————A WB

IF

ID

—

—

—

EX MA

if

—

—

—

ID EX

Other instruction
Other instruction

IF ID

Other instruction......

EX .....

: Slot
MAC.W
STS
Other instruction
Other instruction
Other instruction......

Figure 7.19

192 HITACHI

if

ID

EX MA MA mm mm mm

IF

—

ID

—

EX

M——A WB

if

—

ID

EX

IF

ID

—

EX

if

—

ID

EX .....

STS (Register) Instruction Immediately After a MAC.W Instruction

4. When an STS.L (memory) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are stored in memory using an STS instruction, an
MA stage for accessing the multiplier and writing to memory is added to the STS
instruction, as described later. When the MA of the STS instruction contends with theoperating multiplier (mm), the MA is extended until one state after the mm ends (theM—A shown in the dotted line box in figure 7.20) to create a single slot. The MA of the
STS contends with the IF. Figure 7.20 illustrates how this occurs, assuming MA and IF
contention.
: Slot
MAC.W

IF

STS.L

ID

EX MA —

if——

Other instruction

MA mm mm mm
M——————A

ID

EX

IF

ID

—

—

if

—

—

Other instruction

WB

—

—

EX MA

—

—

ID EX
IF ID EX ......

Other instruction......
: Slot
MAC.W
STS.L
Other instruction
Other instruction
Other instructionif

ID

EX MA MA mm mm mm

IF

—

ID

—

EX

M————A

if

—

ID

EX

IF

ID

—

—

EX

if

—

—

ID

EX .....

......

Figure 7.20

STS.L (Memory) Instruction Immediately After a MAC.W Instruction

HITACHI 193

5. When an LDS (register) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are loaded from a general-purpose register using an
LDS instruction, an MA stage for accessing the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.21) to create a single slot. The MA of this LDS contends with IF.
Figure 7.21 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.W

IF

LDS

ID

EX MA —

MA mm mm mm

if

—

ID

EX

M————A

IF

ID

—

—

—

EX MA

if

—

—

—

ID EX

—

Other instruction
Other instruction

IF ID EX .....

Other instruction......

: SlotMAC.W
LDS
Other instruction
Other instruction
Other instruction......

Figure 7.21

194 HITACHI

if

ID

EX MA MA mm mm mm

IF

—

ID

—

EX

M——A

if

—

ID

EX

IF

ID

—

EX

if

—

ID

EX .....

LDS (Register) Instruction Immediately After a MAC.W Instruction

6. When an LDS.L (memory) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are loaded from memory using an LDS instruction,
an MA stage for accessing the memory and the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.22) to create a single slot. The MA of the LDS contends with IF.
Figure 7.22 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.W

IF

LDS.L

ID

EX MA — MA mm mm mm

if

—

—

Other instruction

ID

EX

M————A

IF

ID

—

—

—

EX MA

if

—

—

—

ID EX

Other instruction

IF ID EX .....

Other instruction......

: Slot
MAC.W
LDS.L
Other instruction
Other instruction
Other instruction......

Figure 7.22

if

ID

EX MA MA mm mm mm

if

—

ID

—

EX

M——A

if

—

ID

EX

IF

ID

—

EX MA

if

—

ID

EX .....

LDS.L (Memory) Instruction Immediately After a MAC.W Instruction

HITACHI 195

Multiply/Accumulate Instruction (SH-2 CPU): Includes the following instruction type:• MAC.W@Rm+, @Rn+
: Slot
MAC.W
Next instruction
Third instruction......

Figure 7.23

IFID

EX MA MA mm mm

IF

—

ID

EX MA WB

IF

ID

EX MA WB

Multiply/Accumulate Instruction Pipeline

Operation: The pipeline has seven stages: IF, ID, EX, MA, MA, mm and mm (figure 7.23).
The second MA reads the memory and accesses the multiplier. The mm indicates that themultiplier is operating. The mm operates for two cycles after the final MA ends, regardless ofslot. The ID of the instruction after the MAC.W instruction is stalled for one slot. The two
MAs of the MAC.W instruction, when they contend with IF, split the slots as described in
Section 7.4, Contention Between Instruction Fetch (IF) and Memory Access (MA).
When an instruction that does not use the multiplier follows the MAC.W instruction, the
MAC.W instruction may be considered to be a five-stage pipeline instructions of IF, ID, EX,
MA, and MA. In such cases, the ID of the next instruction simply stalls one slot andthereafter the pipeline operates normally. When an instruction that uses the multiplier comes
after the MAC.W instruction, contention occurs with the multiplier, so operation is not asnormal. This occurs in the following cases:
1. When a MAC.W instruction is located immediately after another MAC.W instruction
2. When a MAC.L instruction is located immediately after a MAC.W instruction
3. When a MULS.W instruction is located immediately after a MAC.W instruction
4. When a DMULS.L instruction is located immediately after a MAC.W instruction
5. When an STS (register) instruction is located immediately after a MAC.W instruction
6. When an STS.L (memory) instruction is located immediately after a MAC.W instruction
7. When an LDS (register) instruction is located immediately after a MAC.W instruction
8. When an LDS.L (memory) instruction is located immediately after a MAC.W instruction

196 HITACHI1. When a MAC.W instruction is located immediately after another MAC.W instruction
The second MA of a MAC.W instruction does not contend with an mm generated by apreceding multiplication instruction.
: Slot
MAC.W

IF

MAC.W

ID

EX

MA MA mm mm

IF

—

ID

EX

MA

IF

—

ID

Third instruction......

Figure 7.24

MA mm mm
EX MA ....

MAC.W Instruction That Immediately Follows Another MAC.W
instruction

Sometimes consecutive MAC.Ws may have misalignment of instruction execution caused
by MA and IF contention. Figure 7.25 illustrates a case of this type. This figure assumes
MA and IF contention.
: Slot
MAC.W
MAC.W

if

ID EX MA MA mm mm
IF— ID EX MA — MA mm mm
if

MAC.W
MAC.W
......

——ID EX MA MA mm mm
IF

Figure 7.25—

ID EX MA MA mm ....

Consecutive MAC.Ws with Misalignment

HITACHI 197

When the second MA of the MAC.W instruction contends with IF, the slot will split asusual. Figure 7.26 illustrates a case of this type. This figure assumes MA and IF
contention.
: Slot
MAC.W

IF

MAC.W

ID

EX MA —

MA mm mm

if

—

ID

EX

MA MA mm mm

IF

—

ID

—

EX MA

....

if

—

ID

....

—

Other instruction
Other instruction
Other instruction......

EX

IF

Figure 7.26

MA and IF Contention

2. When a MAC.L instruction is located immediately after a MAC.W instruction
The second MA of a MAC.W instruction does not contend with an mm generated by apreceding multiplication instruction (figure 7.27).
: Slot
MAC.W
MAC.L
Third instruction......

Figure 7.27

198 HITACHI

IF

ID

EX

MA MA mm mm

IF

—

ID

EX

MA

IF

—

ID

MA mm mm mm mm
EX MA ....

MAC.L Instructions Immediately After a MAC.W Instruction

3. When a MULS.W instruction is located immediately after a MAC.W instruction
MULS.W instructions have an MA stage for accessing the multiplier. When the MA of the
MULS.W instruction contends with an operating MAC.W instruction multiplier (mm), theMA is extended until the mm ends (the M—A shown in the dotted line box in figure 7.28)
to create a single slot. When one or more instructions not related to the multiplier comebetween the MAC.W and MULS.W instructions, MAC.W and MULS.W contention does
not cause stalling. There is no MULS.W MA contention while the MAC.W instruction
multiplier is operating (mm). When the MULS.W MA and IF contend, the slot is split.
: Slot
MAC.W

IF

MULS.WID

EX MA MA mm mm

IF—

Other instruction......

ID

EX

IF

ID

M——A mm mm
EX — MA ....

: Slot
MAC.W

IF

Other instruction

ID

EX MA MA mm mm

IF—

MULS.W

ID

EX

IF

ID

Other instruction......

Figure 7.28

IF

EX MA mm mm
ID EX MA ....

MULS.W Instruction Immediately After a MAC.W Instruction

4. When a DMULS.L instruction is located immediately after a MAC.W instruction
DMULS.L instructions have an MA stage for accessing the multiplier, but there is no
DMULS.L MA contention while the MAC.W instruction multiplier is operating (mm).
When the DMULS.L MA and IF contend, the slot is split (figure 7.29).
: Slot
MAC.W
DMULS.L
Other instruction......

Figure 7.29

IFID

EX MA MA mm mm

IF

—

ID
IF

EX MA MA mm mm mm mm— ID EX MA ....

DMULS.L Instructions Immediately After a MAC.W Instruction

HITACHI 199

5. When an STS (register) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are stored in a general-purpose register using an
STS instruction, an MA stage for accessing the multiplier is added to the STS instruction,
as described later. When the MA of the STS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.30) to create a single slot. The MA of the STS contends with the IF.
Figure 7.30 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.W IFID

EX MA —

MA mm mm

STS

if

—

ID

EX

M——A WB

IF

ID

—

—

EX MA

if

—

—

ID
IF

—

Other instruction
Other instruction
Other instruction......

EX
ID EX ....

: Slot
MAC.W ifID

EX MA MA mm mm

STS

IF

—

Other instruction
Other instruction
Other instruction......

Figure 7.30

200 HITACHIID—

EX MA WB

if

—

ID EX
IF

ID
if

EX MA
ID EX

....

STS (Register) Instruction Immediately After a MAC.W Instruction

6. When an STS.L (memory) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are stored in memory using an STS instruction, an
MA stage for accessing the memory and the multiplier and writing to memory is added to
the STS instruction, as described later. Figure 7.31 illustrates how this occurs, assuming
MA and IF contention.
: Slot
MAC.W IFID EX MA — MA mm mm

STS.L

if

—

—

Other instruction

ID

EX

M——A

IF

ID

—

—

EX MA

if

—

—

ID
IF

Other instruction
Other instruction......

EX
ID EX

....

: Slot
MAC.W if

ID EX MA MA mm mm

STS.L

IF

Other instruction
Other instruction
Other instruction......

Figure 7.31

—

ID

—

EX MA

if

—

ID

EX

IF

ID
if

EX
ID EX

....

STS.L (Memory) Instruction Immediately After a MAC.W Instruction

HITACHI 201

7. When an LDS (register) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are loaded from a general-purpose register using an
LDS instruction, an MA stage for accessing the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.32) to create a single slot. The MA of this LDS contends with IF.
Figure 7.32 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.W IFID

EX MA — MA mm mm

LDS

if

—

—

Other instruction

ID

EX M——A

IF

ID

—

—

EX MA

if

—

—

ID
IF

Other instruction
Other instruction......

EX
ID EX

....

: Slot
MAC.W ifID

EX MA MA mm mm

LDS

IF

—

Other instruction
Other instruction
Other instruction......

Figure 7.32

202 HITACHI

ID

—

EX MA

if

—

ID EX
IF

ID
if

EX
ID EX ....

LDS (Register) Instruction Immediately After a MAC.W Instruction

8. When an LDS.L (memory) instruction is located immediately after a MAC.W instruction
When the contents of a MAC register are loaded from memory using an LDS instruction,
an MA stage for accessing the multiplier is added to the LDS instruction, as describedlater. When the MA of the LDS instruction contends with the operating multiplier (mm),the MA is extended until the mm ends (the M—A shown in the dotted line box in figure7.33) to create a single slot. The MA of the LDS contends with IF. Figure 7.33 illustrates
how this occurs, assuming MA and IF contention.
: Slot
MAC.W IF

ID

EX MA

—

MA mm mm

LDS.L

if

—

ID

EX

M——A

IF

ID

—

—

EX

if

—

—

ID
IF

—

Other instruction
Other instruction
Other instruction......

EX
ID EX

....

: Slot
MAC.W ifID

EX MA MA mm mm

LDS.L

IF

—

Other instruction
Other instruction
Other instruction......

Figure 7.33

ID

—

EX MA

if

—

ID EX
IF

ID
if

EX
ID EX

....

LDS.L (Memory) Instruction Immediately After a MAC.W Instruction

HITACHI 203

Double-Length Multiply/Accumulate Instruction (SH-2 CPU): Includes the following
instruction type:• MAC.L@Rm+, @Rn+ (SH-2 CPU only): Slot
MAC.L
Next instruction
Third instruction......

Figure 7.34

IFID

EX MA MA mm mm mm mm

IF

—

ID

EX MA

WB

IF

ID

MA WB

EX

Multiply/Accumulate Instruction Pipeline

Operation: The pipeline has nine stages: IF, ID, EX, MA, MA, mm, mm, mm, and mm(figure 7.34). The second MA reads the memory and accesses the multiplier. The mm
indicates that the multiplier is operating. The mm operates for four cycles after the final MA
ends, regardless of a slot. The ID of the instruction after the MAC.L instruction is stalled forone slot. The two MAs of the MAC.L instruction, when they contend with IF, split the slots as
described in Section 7.4, Contention Between Instruction Fetch (IF) and Memory Access(MA).
When an instruction that does not use the multiplier follows the MAC.L instruction, the
MAC.L instruction may be considered to be five-stage pipeline instructions of IF, ID, EX,
MA, and MA. In such cases, the ID of the next instruction simply stalls one slot andthereafter the pipeline operates normally. When an instruction that uses the multiplier comes
after the MAC.L instruction, contention occurs with the multiplier, so operation is not asnormal. This occurs in the following cases:
1. When a MAC.L instruction is located immediately after another MAC.L instruction
2. When a MAC.W instruction is located immediately after a MAC.L instruction
3. When a DMULS.L instruction is located immediately after a MAC.L instruction
4. When a MULS.W instruction is located immediately after a MAC.L instruction
5. When an STS (register) instruction is located immediately after a MAC.L instruction
6. When an STS.L (memory) instruction is located immediately after a MAC.L instruction
7. When an LDS (register) instruction is located immediately after a MAC.L instruction
8. When an LDS.L (memory) instruction is located immediately after a MAC.L instruction

204 HITACHI1. When a MAC.L instruction is located immediately after another MAC.L instruction
When the second MA of the MAC.L instruction contends with the mm produced by theprevious multiplication instruction, the MA bus cycle is extended until the mm ends (theM—A shown in the dotted line box in figure 7.35) to create a single slot. When two or
more instructions that do not use the multiplier occur between two MAC.L instructions,the stall caused by multiplier contention between MAC.L instructions is eliminated.
: Slot
MAC.L

IF

MAC.L

ID

EX MA MA mm mm mm mm

IF—

Third instruction......

ID

EX MA

IF

—

ID

M————A mm mm mm mm
EX — — MA ......

: Slot
MAC.L

IF

Other instruction

ID

EX MA MA mm mm mm mm

IF—

ID EX MA WB
IFOther instruction
MAC.L......

Figure 7.35

ID

EX MA WB

IF

ID

EX MA MA mm mm mm mm

MAC.L Instruction Immediately After Another MAC.L Instruction

Sometimes consecutive MAC.Ls may have less multiplier contention even when there is
misalignment of instruction execution caused by MA and IF contention. Figure 7.36
illustrates a case of this type, assuming MA and IF contention.
: Slot
MAC.L
MAC.L
MAC.L

if

ID

EX MA MA mm mm mm mm

IF

—

ID

EX MA —

M——A mm mm mm mm

if

—

EX
—

MAC.L
......

Figure 7.36

—

ID
IF

—
—

MA M————A mm mm mm mm
ID EX — — MA

Consecutive MAC.Ls with Misalignment

HITACHI 205

When the second MA of the MAC.L instruction is extended to the end of the mm,contention between the MA and IF will split the slot in the usual way. Figure 7.37
illustrates a case of this type, assuming MA and IF contention.
: Slot
MAC.L
MAC.L
Other intructionIF

ID

EX MA —

MA mm mm mm mm

if

—

ID

EX MA

M————A mm mm mm mm

IF

—

—
—

—

Other intruction

ID
if

—
—

—
—

Other intruction......

Figure 7.37

206 HITACHI

MA and IF Contention

EX
ID
IF

2. When a MAC.W instruction is located immediately after a MAC.L instruction
When the second MA of the MAC.W instruction contends with the mm produced by theprevious multiplication instruction, the MA bus cycle is extended until the mm ends (theM—A shown in the dotted line box in figure 7.38) to create a single slot. When two or
more instructions that do not use the multiplier occur between the MAC.L and MAC.W
instructions, the stall caused by multiplier contention between MAC.L instructions iseliminated.
: Slot
MAC.L

IF

MAC.W

ID

EX MA MA mm mm mm mm

IF

—

ID
IF

Third instruction......

EX MA MA————A mm mm— ID EX — — MA ......

: Slot
MAC.L
Other instruction
Other instruction
MAC.W......

Figure 7.38

IFID

EX MA MA mm mm mm mm

IF—

ID EX MA WB
IFID

EX MA WB

IF

ID

EX MA MA mm mm

MAC.W Instruction Immediately After a MAC.L Instruction

HITACHI 207

3. When a DMULS.L instruction is located immediately after a MAC.L instruction
DMULS.L instructions have an MA stage for accessing the multiplier. When the second
MA of the DMULS.L instruction contends with an operating MAC.L instruction multiplier(mm), the MA is extended until the mm ends (the M—A shown in the dotted line box infigure 7.39) to create a single slot. When two or more instructions not related to themultiplier come between the MAC.L and DMULS.L instructions, MAC.L and DMULS.L
contention does not cause stalling. When the DMULS.L MA and IF contend, the slot is
split.
: Slot
MAC.L

IF

DMULS.LID

EX MA MA mm mm mm mm

IF—

Other instruction......

ID

EX MA

IF

—

ID

M————A mm mm mm mm— — EX MA ......

: Slot
MAC.L

IF

Other instruction

ID

EX MA MA mm mm mm mm

IF

—

ID EX
IF

DMULS.LID
IF

Other instruction......

EX MA M——A mm mm mm mm— ID — EX MA ......

: Slot
MAC.L
Other instruction
Other instruction
DMULS.L
Other instruction......

IF

ID

EX MA MA mm mm mm mm

IF

—

ID EX

MA WB

IF

ID

EX MA WB

IF

ID
IF

EX MA MA mm mm mm mm— ID EX MA ......

Figure 7.39 DMULS.L Instruction Immediately After a MAC.L Instruction

208 HITACHI

4. When a MULS.W instruction is located immediately after a MAC.L instruction
MULS.W instructions have an MA stage for accessing the multiplier. When the MA of the
MULS.W instruction contends with an operating MAC.L instruction multiplier (mm), theMA is extended until the mm ends (the M—A shown in the dotted line box in figure 7.40)
to create a single slot. When three or more instructions not related to the multiplier comebetween the MAC.L and MULS.W instructions, MAC.L and MULS.W contention does notcause stalling. When the MULS.W MA and IF contend, the slot is split.
: Slot
MAC.L

IF

MULS.WID

EX MA MA mm mm mm mm mm

IF—

Other instruction......

mm mm— MA ......

ID

EX MA

M——————A

IF

—

EX

ID

—

—

: Slot
MAC.L

IF

Other instruction

ID

EX MA MA mm mm mm mm

IF

—

ID EX
IF

MULS.W
Other instruction......

ID

EX

IF

ID

M————A mm mm
EX — — MA ......

: Slot
MAC.L

IF

Other instruction

ID

EX MA MA mm mm mm mm

IF—

ID EX MA WB
IFOther instruction
MULS.WID

EX MA WB

IF

ID

EX

IF

ID

Other instruction......

M——A mm mm— MA ......

EX: Slot
MAC.L
Other instruction
Other instruction
Other instruction
MULS.W
Other instruction......

Figure 7.40

IFID

EX MA MA mm mm mm mm

IF

—

ID EX

MA WB

IF

ID

EX MA WB

IF

ID

EX MA WB

IF

ID
IF

EX MA mm mm
ID EX MA ......

MULS.W Instruction Immediately After a MAC.L Instruction

HITACHI 209

5. When an STS (register) instruction is located immediately after a MAC.L instruction
When the contents of a MAC register are stored in a general-purpose register using an
STS instruction, an MA stage for accessing the multiplier is added to the STS instruction,
as described later. When the MA of the STS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.41) to create a single slot. The MA of the STS contends with the IF.
Figure 7.41 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.L

IF

STS

ID

EX MA —

if

—

—

IF

Other instruction

MA mm mm mm mm

ID EX M———————A WB

Other instruction

ID

—

—

—

—

EX MA

if

—

—

—

—

ID EX
IF ID EX ......

Other instruction......

: Slot
MAC.L
STS
Other instruction
Other instruction
Other instruction......

Figure 7.41

210 HITACHI

if

ID

EX MA MA mm mm mm mm

IF

—

ID

—

EX

M————A

WB

if

—

ID

EX

IF

ID

—

—

EX

if

—

—

ID

EX ......

STS (Register) Instruction Immediately After a MAC.L Instruction

6. When an STS.L (memory) instruction is located immediately after a MAC.L instruction
When the contents of a MAC register are stored in memory using an STS instruction, an
MA stage for accessing the multiplier and writing to memory is added to the STS
instruction, as described later. The MA of the STS contends with the IF. Figure 7.42
illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.L IFID EX MA — MA mm mm mm mm

STS.L

if

— —

ID EX M———————AIF

Other instruction
Other instruction

ID

—

—

—

—

EX MA

if

—

—

—

—

ID EX
IF

Other instruction......

ID EX ......

: Slot
MAC.L
STS.L
Other instruction
Other instruction
Other instruction......

Figure 7.42

if

ID EX MA MA mm mm mm mm
IF

—

ID

—

EX M————A

if

—

ID EX
IF

ID

—

—

EX

if

—

—

ID EX ......

STS.L (Memory) Instruction Immediately After a MAC.L Instruction

HITACHI 211

7. When an LDS (register) instruction is located immediately after a MAC.L instruction
When the contents of a MAC register are loaded from a general-purpose register using an
LDS instruction, an MA stage for accessing the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.43) to create a single slot. The MA of this LDS contends with IF.
Figure 7.43 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.L

IF

ID
if

LDS

EX MA — MA mm mm mm mm— — ID EX M—————–—AIF

Other instruction
Other instruction

ID

—

—

—

— EX MA

if

—

—

—

—

Other instruction......

IDEX

IF

ID EX ......

: SlotMAC.L
LDS
Other instruction
Other instruction
Other instruction......

Figure 7.43

212 HITACHI

if

ID

EX MA MA mm mm mm mm

IF

—

ID

—

EX

M————A

if

—

ID

EX

IF

ID

—

—

EX

if

—

—

ID

EX ......

LDS (Register) Instruction Immediately After a MAC.L Instruction

8. When an LDS.L (memory) instruction is located immediately after a MAC.L instruction
When the contents of a MAC register are loaded from memory using an LDS instruction,
an MA stage for accessing the memory and the memory and the multiplier is added to the
LDS instruction, as described later. When the MA of the LDS instruction contends withthe operating multiplier (mm), the MA is extended until the mm ends (the M—A shownin the dotted line box in figure 7.44) to create a single slot. The MA of the LDS contends
with IF. Figure 7.44 illustrates how this occurs, assuming MA and IF contention.
: Slot
MAC.L

IF

ID
if

LDS.L

EX MA — MA mm mm mm mm— — ID EX M—————–—AIF

Other instruction
Other instruction

ID

—

—

—

— EX MA

if

—

—

—

—

Other instruction......

IDEX

IF

ID EX ......

: Slot
MAC.L
LDS.L
Other instruction
Other instruction
Other instruction......

Figure 7.44

if

ID

EX MA MA mm mm mm mm

IF

—

ID

—

EX

M————A

if

—

ID

EX

IF

ID

—

—

EX

if

—

—

ID

EX ......

LDS.L (Memory) Instruction Immediately After a MAC.L Instruction

HITACHI 213

Multiplication Instructions (SH-1 CPU): Include the following instruction types:• MULS.W• MULU.W

Rm, RnRm, Rn: Slot
MULS.W
Next instruction
Third instruction......

Figure 7.45

IFID

EX MA mm mm mm

IF

ID

EX MA WB

IF

ID

EX MA WB

Multiplication Instruction Pipeline

Operation: The pipeline has seven stages: IF, ID, EX, MA, mm, mm, and mm (figure 8.45).
The MA accesses the multiplier. The mm indicates that the multiplier is operating. The mm
operates for three cycles after the MA ends, regardless of a slot. The MA of the MULS.W
instruction, when it contends with IF, splits the slot as described in Section 7.4, Contention
Between Instruction Fetch (IF) and Memory Access (MA).
When an instruction that does not use the multiplier comes after the MULS.W instruction, the
MULS.W instruction may be considered to be four-stage pipeline instructions of IF, ID, EX,
and MA. In such cases, it operates like a normal pipeline. When an instruction that uses themultiplier comes after the MULS.W instruction, however, contention occurs with themultiplier, so operation is not as normal. This occurs in the following cases:
1. When a MAC.W instruction is located immediately after a MULS.W instruction
2. When a MULS.W instruction is located immediately after another MULS.W instruction
3. When an STS (register) instruction is located immediately after a MULS.W instruction
4. When an STS.L (memory) instruction is located immediately after a MULS.W instruction
5. When an LDS (register) instruction is located immediately after a MULS.W instruction
6. When an LDS.L (memory) instruction is located immediately after a MULS.W instruction

214 HITACHI1. When a MAC.W instruction is located immediately after a MULS.W instruction
When the second MA of a MAC.W instruction contends with the mm generated by apreceding multiplication instruction, the bus cycle of that MA is extended until the mmends (the M—A shown in the dotted line box below) and that extended MA occupies one
slot.
If one or more instructions not related to the multiplier comes between the MULS.W and
MAC.W instructions, multiplier contention between the MULS.W and MAC.W
instructions does not cause stalls (figure 7.46).
: Slot
MULS.W

IF

MAC.W

ID

EX MA mm mm mm

IF

ID

Third instruction......

IF

EX MA M——A mm mm mm— ID EX — MA .....

: Slot
MULS.W
Other instruction
MAC.W......

Figure 7.46

IFID

EX MA mm mm mm

IF

ID

EX MA WB

IF

ID

EX MA MA mm mm mm .....

MAC.W Instruction Immediately After a MULS.W Instruction

HITACHI 215

2. When a MULS.W instruction is located immediately after another MULS.W instruction
MULS.W instructions have an MA stage for accessing the multiplier. When the MA of the
MULS.W instruction contends with the operating multiplier (mm) of another MULS.W
instruction, the MA is extended until the mm ends (the M—A shown in the dotted line
box in figure 7.47) to create a single slot. When two or more instructions not related to themultiplier are located between the two MULS.W instructions, contention between the
MULS.Ws does not cause stalling. When the MULS.W MA and IF contend, the slot is
split.
: Slot
MULS.WIF

MULS.WID

EX MA mm mm mm

IF

ID

EX

IF

ID

Other instruction......

M————A mm mm mm
EX — — MA .....

: Slot
MULS.W

IF

Other instruction

ID

EX MA mm mm mm

IF

ID

EX

IF

ID

EX

IF

ID

MULS.W
Other instruction......

M——A mm mm mm
EX — MA .....

: Slot
MULS.W
Other instruction
Other instruction
MULS.W
Other instruction......

Figure 7.47

216 HITACHIIFID

EX MA mm mm mm

IF

ID

EX MA WB

IF

ID

EX MA WB

IF

ID
IF

EX MA mm mm mm
ID EX MA ......

MULS.W Instruction Immediately After Another MULS.W Instruction

When the MA of the MULS.W instruction is extended until the mm ends, contention
between MA and IF will split the slot, as is normal. Figure 7.48 illustrates a case of thistype, assuming MA and IF contention.
: Slot
MULS.W
MULS.W
Other instruction
Other instruction
Other instruction......

Figure 7.48

IFID

EX MA mm mm mm

if

ID

EX

IF

ID

—

if

—

M————A mm mm mm— — EX MA .....
—

—

ID
IF

EX .....
ID .....

MULS.W Instruction Immediately After Another MULS.W Instruction(IF and MA Contention)

HITACHI 217

3. When an STS (register) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are stored in a general-purpose register using an
STS instruction, an MA stage for accessing the multiplier is added to the STS instruction,
as described later. When the MA of the STS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.49) to create a single slot. The MA of the STS contends with the IF.
Figure 7.49 illustrates how this occurs, assuming MA and IF contention.
: Slot
MULS.W

IF

STS

ID

EX MA mm mm mm

if

ID

EX

IF

ID

—

—

—

EX MA

if

—

—

—

ID

EX

IF

ID

Other instruction
Other instruction

M————A WB

Other instruction......

EX .....

: Slot
MULS.W
STS
Other instruction
Other instruction
Other instruction......

Figure 7.49

218 HITACHI

if

ID

EX MA mm mm mm

IF

ID

—

EX

M——A WB

if

—

ID

EX

IF

ID

—

EX

if

—

ID

EX .....

STS (Register) Instruction Immediately After a MULS.W Instruction

4. When an STS.L (memory) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are loaded from memory using an STS instruction,
an MA stage for accessing the multiplier and writing to memory is added to the STS
instruction, as described later. When the MA of the STS instruction contends with theoperating multiplier (mm), the MA is extended until one cycle after the mm ends (theM—A shown in the dotted line box in figure 7.50) to create a single slot. The MA of the
STS contends with the IF. Figure 7.50 illustrates how this occurs, assuming MA and IF
contention.
: Slot
MULS.W IF
STS.L
Other instruction
Other instruction
Other instruction......

ID EX MA mm mm mm
if ID EX M————AIF ID — — — EX MA
if — — — ID EX
IF ID EX .....

MULS.W if
STS.L
Other instruction
Other instruction
Other instruction......

ID EX MA mm mm mm
IF ID — EX M——A
if — ID EX
IF ID — EX
if — ID EX .....

: SlotFigure 7.50

STS.L (Memory) Instruction Immediately After a MULS.W Instruction

HITACHI 219

5. When an LDS (register) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are loaded from a general-purpose register using an
LDS instruction, an MA stage for accessing the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box below) to create a single slot. The MA of this LDS contends with IF. Figure 7.51
illustrates how this occurs, assuming MA and IF contention.
: Slot
MULS.W

IF

LDS

ID

EX MA mm mm mm

if

ID

EX

IF

ID

—

—

—

EX MA

if

—

—

—

ID

EX

IF

ID

Other instruction
Other instruction

M————A

Other instruction......

EX .....

: Slot
MULS.WLDSOther instruction
Other instruction
Other instruction......

Figure 7.51

220 HITACHI

if

ID

EX MA mm mm mm

IF

ID

—

EX

M——A

if

—

ID

EX

IF

ID

—

EX

if

—

ID

EX .....

LDS (Register) Instruction Immediately After a MULS.W Instruction

6. When an LDS.L (memory) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are loaded from memory using an LDS instruction,
an MA stage for accessing the memory and the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.52) to create a single slot. The MA of the LDS contends with IF.
Figure 7.52 illustrates how this occurs, assuming MA and IF contention.
: Slot
MULS.W

IF

LDS.L

ID

EX MA mm mm mm

if

ID

EX

IF

ID

—

—

—

EX MA

if

—

—

—

ID

EX

IF

ID

Other instruction
Other instruction

M————A

Other instruction......

EX .....

: Slot
MULS.W
LDS.L
Other instruction
Other instruction
Other instruction......

Figure 7.52

if

ID

EX MA mm mm mm

IF

ID

—

EX

M——A

if

—

ID

EX

IF

ID

—

EX

if

—

ID

EX .....

LDS.L (Memory) Instruction Immediately After a MULS.W Instruction

HITACHI 221

Multiplication Instructions (SH-2 CPU): Include the following instruction types:• MULS.W• MULU.W

Rm, RnRm, Rn: Slot
MULS.WIF

Next instruction
Third instruction.....

Figure 7.53

ID

EX

MA mm mm

IF

ID

EX

MA

WB

IF

ID

EX

MA

WB

Multiplication Instruction Pipeline

Operation: The pipeline has six stages: IF, ID, EX, MA, mm, and mm (figure 8.53). The MA
accesses the multiplier. The mm indicates that the multiplier is operating. The mm operates
for two cycles after the MA ends, regardless of the slot. The MA of the MULS.W instruction,
when it contends with IF, splits the slot as described in Section 7.4, Contention Between
Instruction Fetch (IF) and Memory Access (MA).
When an instruction that does not use the multiplier comes after the MULS.W instruction, the
MULS.W instruction may be considered to be four-stage pipeline instructions of IF, ID, EX,
and MA. In such cases, it operates like a normal pipeline. When an instruction that uses themultiplier is located after the MULS.W instruction, however, contention occurs with themultiplier, so operation is not as normal. This occurs in the following cases:
1. When a MAC.W instruction is located immediately after a MULS.W instruction
2. When a MAC.L instruction is located immediately after a MULS.W instruction
3. When a MULS.W instruction is located immediately after another MULS.W instruction
4. When a DMULS.L instruction is located immediately after a MULS.W instruction
5. When an STS (register) instruction is located immediately after a MULS.W instruction
6. When an STS.L (memory) instruction is located immediately after a MULS.W instruction
7. When an LDS (register) instruction is located immediately after a MULS.W instruction
8. When an LDS.L (memory) instruction is located immediately after a MULS.W instruction

222 HITACHI1. When a MAC.W instruction is located immediately after a MULS.W instruction
The second MA of a MAC.W instruction does not contend with the mm generated by apreceding multiplication instruction.
: Slot
MULS.W

IF

MAC.W

ID

EX MA mm mm

IF

ID
IF

Third instruction......

Figure 7.54

EX MA MA mm mm— ID EX MA ......

MAC.W Instruction Immediately After a MULS.W Instruction

2. When a MAC.L instruction is located immediately after a MULS.W instruction
The second MA of a MAC.W instruction does not contend with the mm generated by apreceding multiplication instruction.
: Slot
MULS.W
MAC.L
Third instruction......

Figure 7.55

IFID

EX MA mm mm

IF

ID
IF

EX MA MA mm mm mm mm— ID EX MA ......

MAC.L Instruction Immediately After a MULS.W Instruction

HITACHI 223

3. When a MULS.W instruction is located immediately after another MULS.W instruction
MULS.W instructions have an MA stage for accessing the multiplier. When the MA of the
MULS.W instruction contends with the operating multiplier (mm) of another MULS.W
instruction, the MA is extended until the mm ends (the M—A shown in the dotted line
box in figure 7.56) to create a single slot. When one or more instructions not related to themultiplier is located between the two MULS.W instructions, contention between the
MULS.Ws does not cause stalling. When the MULS.W MA and IF contend, the slot is
split.
: Slot
MULS.WIF

MULS.WID

EX MA mm mm

IF

ID

EX M——AIF

ID

Other instruction......

EX

—

mm mm
MA ......

: Slot
MULS.W

IF

Other instruction

ID

EX MA mm mm

IF

ID

EX

IF

ID

EX MA

IF

ID

MULS.W
Other instruction......

Figure 7.56

EX

mm mm
MA ......

MULS.W Instruction Immediately After Another MULS.W Instruction

When the MA of the MULS.W instruction is extended until the mm ends, contention
between the MA and IF will split the slot in the usual way. Figure 7.57 illustrates a caseof this type, assuming MA and IF contention.
: Slot
MULS.W
MULS.W
Other instruction
Other instruction
Other instruction......

Figure 7.57

224 HITACHI

IF

ID
if

EX MA mm mm
ID

EX M——A

mm mm

IF

ID

—

—

if

—

—

EX MA ......
ID EX ......
IF

ID......

MULS.W Instruction Immediately After Another MULS.W Instruction(IF and MA contention)

4. When a DMULS.L instruction is located immediately after a MULS.W instruction
Though the second MA in the DMULS.L instruction makes an access to the multiplier, it
does not contend with the operating multiplier (mm) generated by the MULS.W
instruction.
: Slot
MULS.WDMULS.L
Other instruction......

Figure 7.58

IFID

EX MA mm mm

IF

ID
IF

EX MA MA mm mm mm mm— ID EX MA ......

DMULS.L Instruction Immediately After a MULS.W Instruction

HITACHI 225

5. When an STS (register) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are stored in a general-purpose register using an
STS instruction, an MA stage for accessing the multiplier is added to the STS instruction,
as described later. When the MA of the STS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.59) to create a single slot. The MA of the STS contends with the IF.
Figure 7.59 illustrates how this occurs, assuming MA and IF contention.
: Slot
MULS.W

IF

STS

ID

EX MA mm mm

if

ID

EX M——A

WB

IF

ID

—

—

EX MA

if

—

—

ID

EX

IF

ID

Other instruction
Other instruction
Other instruction......

EX ......

: Slot
MULS.W
STS
Other instruction
Other instruction
Other instruction......

Figure 7.59

226 HITACHI

if

ID

EX MA mm mm

IF

ID

—

EX MA

if

—

ID

EX

IF

ID

EX

if

ID EX

WB

......

STS (Register) Instruction Immediately After a MULS.W Instruction

6. When an STS.L (memory) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are stored in memory using an STS instruction, an
MA stage for accessing the multiplier and writing to memory is added to the STS
instruction, as described later. The MA of the STS contends with the IF. Figure 7.60
illustrates how this occurs, assuming MA and IF contention.
: Slot
MULS.W

IF

ID
if

STS.L
Other instruction

EX MA mm mm
ID

EX M———A

IF

ID

—

—

EX MA

if

—

—

ID

EX

IF

ID

Other instruction
Other instruction......

EX ......

: Slot
MULS.W
STS.L
Other instruction
Other instruction
Other instruction......

Figure 7.60

ifID

EX MA mm mm

IF

ID

—

EX MA

if

—

ID

EX

IF

ID

EX

if

ID

EX ......

STS.L (Memory) Instruction Immediately After a MULS.W Instruction

HITACHI 227

7. When an LDS (register) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are loaded from a general-purpose register using an
LDS instruction, an MA stage for accessing the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box below) to create a single slot. The MA of this LDS contends with IF. The
following figures illustrates how this occurs, assuming MA and IF contention.
: Slot
MULS.W

IF

LDS

ID

EX MA mm mm

if

ID

EX M——A

IF

ID

—

—

EX MA

if

—

—

ID

EX

IF

ID

Other instruction
Other instruction
Other instruction......

EX ......

: Slot
MULS.WLDSOther instruction
Other instruction
Other instruction......

Figure 7.61

228 HITACHI

if

ID

EX MA mm mm

IF

ID

—

EX MA

if

—

ID

EX

IF

ID

EX

if

ID

EX ......

LDS (Register) Instruction Immediately After a MULS.W Instruction

8. When an LDS.L (memory) instruction is located immediately after a MULS.W instruction
When the contents of a MAC register are loaded from memory using an LDS instruction,
an MA stage for accessing the multiplier is added to the LDS instruction, as describedlater. When the MA of the LDS instruction contends with the operating multiplier (mm),the MA is extended until the mm ends (the M—A shown in the dotted line box in figure7.62) to create a single slot. The MA of the LDS contends with IF. Figure 7.62 illustrates
how this occurs, assuming MA and IF contention.
: Slot
MULS.W

IF

LDS.L

ID

EX MA mm mm

if

ID

EX M——A

IF

ID

—

—

EX MA

if

—

—

ID

EX

IF

ID

Other instruction
Other instruction
Other instruction......

EX ......

: Slot
MULS.W

if

LDS.L

ID

EX MA mm mm

IF

ID

—

EX MA

if

—

ID

EX

IF

ID

EX

if

ID

Other instruction
Other instruction
Other instruction......

Figure 7.62

EX ......

LDS.L (Memory) Instruction Immediately After a MULS.W Instruction

Double-Length Multiplication Instructions (SH-2 CPU): Include the following instruction
types:• DMULS.L• DMULU.L• MUL.LRm, Rn (SH-2 CPU only)
Rm, Rn (SH-2 CPU only)
Rm, Rn (SH-2 CPU only): SlotDMULS.L

Next instructionIF

ID

EX MA MA mm mm mm mm

IF—

Third instruction......

Figure 7.63

ID

EX MA WB

IF

ID

EX MA WB

Multiplication Instruction Pipeline

HITACHI 229

The pipeline has nine stages: IF, ID, EX, MA, MA, mm, mm, mm, and mm (figure 7.63). The
MA accesses the multiplier. The mm indicates that the multiplier is operating. The mm
operates for four cycles after the MA ends, regardless of a slot. The ID of the instruction
following the DMULS.L instruction is stalled for 1 slot (see the description of themultiply/accumulate instruction). The two MA stages of the DMULS.L instruction, when they
contend with IF, split the slot as described in section 7.4, Contention Between Instruction
Fetch (IF) and Memory Access (MA).
When an instruction that does not use the multiplier comes after the DMULS.L instruction,
the DMULS.L instruction may be considered to be a five-stage pipeline instruction of IF, ID,
EX, MA, and MA. In such cases, it operates like a normal pipeline. When an instruction thatuses the multiplier comes after the DMULS.L instruction, however, contention occurs withthe multiplier, so operation is not as normal. This occurs in the following cases:
1. When a MAC.L instruction is located immediately after a DMULS.L instruction
2. When a MAC.W instruction is located immediately after a DMULS.L instruction
3. When a DMULS.L instruction is located immediately after another DMULS.L instruction
4. When a MULS.W instruction is located immediately after a DMULS.L instruction
5. When an STS (register) instruction is located immediately after a DMULS.L instruction
6. When an STS.L (memory) instruction is located immediately after a DMULS.L instruction
7. When an LDS (register) instruction is located immediately after a DMULS.L instruction
8. When an LDS.L (memory) instruction is located immediately after a DMULS.L
instruction
1. When a MAC.L instruction is located immediately after a DMULS.L instruction
When the second MA of a MAC.L instruction contends with the mm generated by apreceding multiplication instruction, the bus cycle of that MA is extended until the mmends (the M—A shown in the dotted line box below) and that extended MA occupies one
slot.
If two or more instructions not related to the multiplier are located between the DMULS.Land MAC.L instructions, multiplier contention between the DMULS.L and MAC.L
instructions does not cause stalls (figure 7.64).

230 HITACHI

: Slot
DMULS.L

IF

MAC.L

ID

EX MA MA mm mm mm mm

IF—

Third instruction......

ID

EX MA

M————A

IF

—

EX

ID

—

—

mm mm mm mm
MA ......

: SlotDMULS.LIF

Other instruction

ID

EX MA MA mm mm mm mm

IF—

Other instruction

ID

EX MA WB

IF

ID

EX

MA WB

IF

ID

EX

MAC.L

MA MA

mm mm mm mm......

Figure 7.64

MAC.L Instruction Immediately After a DMULS.L Instruction

2. When a MAC.W instruction is located immediately after a DMULS.L instruction
When the second MA of a MAC.W instruction contends with the mm generated by apreceding multiplication instruction, the bus cycle of that MA is extended until the mmends (the M—A shown in the dotted line box below) and that extended MA occupies one
slot.
If two or more instructions not related to the multiplier are located between the DMULS.Land MAC.W instructions, multiplier contention between the DMULS.L and MAC.W
instructions does not cause stalls (figure 7.65).
: SlotDMULS.L

IF

MAC.W

ID

EX MA MA mm mm mm mm

IF—

Third instruction......

ID

EX MA

M————A

IF

—

EX

ID

—

—

mm mm
MA ......

: SlotDMULS.L
Other instruction
Other instruction
MAC.W

IF

ID

EX MA MA mm mm mm mm

IF

—

ID

EX MA WB

IF

ID

EX

MA WB

IF

ID

EX MA

MA mm mm......

Figure 7.65

MAC.W Instruction Immediately After a DMULS.L Instruction

HITACHI 231

3. When a DMULS.L instruction is located immediately after another DMULS.L instruction
DMULS.L instructions have an MA stage for accessing the multiplier. When the MA of
the DMULS.L instruction contends with the operating multiplier (mm) of another
DMULS.L instruction, the MA is extended until the mm ends (the M—A shown in thedotted line box in figure 7.66) to create a single slot. When two or more instructions not
related to the multiplier are located between two DMULS.L instructions, contention
between the DMULS.Ls does not cause stalling. When the DMULS.L MA and IF contend,
the slot is split.
: SlotDMULS.LIFDMULS.LID

EX MA MA mm mm mm mm

IF—

Other instruction......

ID

EX MA

M————A

IF

—

EX

ID

—

—

mm mm mm mm
MA ......

: SlotDMULS.LIF

Other instruction

ID

EX MA MA mm mm mm mm

IF—

DMULS.L

ID

EX

IF

ID

EX

MA M——AIF—

ID

Other instruction......

EX—mm mm mm mm
MA ......

: SlotDMULS.L
Other instruction
Other instruction
DMULS.L
Other instruction......

Figure 7.66

232 HITACHIIFID

EX MA MA mm mm mm mm

IF

—

ID

EX MA WB

IF

ID

EX

MA WB

IF

ID

EX MA MA mm mm mm mm— ID EX MA ......

IFDMULS.L Instruction Immediately After Another DMULS.L Instruction

When the MA of the DMULS.L instruction is extended until the mm ends, contention
between the MA and IF will split the slot in the usual way. Figure 7.67 illustrates a caseof this type, assuming MA and IF contention.
: SlotDMULS.LIFDMULS.LID

EX MA MA —mm mm mm mm

if—

MA M—————Amm mm mm mm

ID
if

EX
ID EX ......
IF ID ......

EX—

Other instruction

ID
IF

Other instruction

—
—

—
—

Other instruction......

Figure 7.67——

DMULS.L Instruction Immediately After Another DMULS.L Instruction(IF and MA Contention)

4. When a MULS.W instruction is located immediately after a DMULS.L instruction
MULS.W instructions have an MA stage for accessing the multiplier. When the MA of the
MULS.W instruction contends with the operating multiplier (mm) of a DMULS.L
instruction, the MA is extended until the mm ends (the M—A shown in the dotted line
box in figure 7.68) to create a single slot. When three or more instructions not related tothe multiplier are located between the DMULS.L instruction and the MULS.W instruction,
contention between the DMULS.L and MULS.W does not cause stalling. When the
MULS.W MA and IF contend, the slot is split..
: SlotDMULS.LIF

MULS.WID

EX MA MA mm mm mm mm

IF—

Other instruction......

ID

EX M———————A

IF

ID

EX

—

—

—

mm mm
MA ......

: SlotDMULS.L
Other instruction
Other instruction
Other instruction
MULS.W
Other instruction......

Figure 7.68

IFID

EX MA MA mm mm mm mm

IF

—

ID

EX MA WB

IF

ID
IF

EX
ID

MA WB
EX MA WB

IF

ID
IF

EX MA MA mm mm
ID EX MA ......

MULS.W Instruction Immediately After a DMULS.L Instruction

When the MA of the DMULS.L instruction is extended until the mm ends, contention
between the MA and IF will split the slot in the usual way. Figure 7.69 illustrates a caseof this type, assuming MA and IF contention.

HITACHI 233

: Slot
DMULS.LIF

MULS.WID
if

EX MA — MA mm mm mm mm— — ID EX M———————A mm mm
IF

Other instruction
Other instruction

ID
if

—
—

—
—

—
—

—
—

Other instruction......

Figure 7.69

EX MA ......
ID EX ......
IF ID ......

MULS.W Instruction Immediately After a DMULS.L Instruction (IF and
MA Contention)

5. When an STS (register) instruction is located immediately after a DMULS.L instruction
When the contents of a MAC register are stored in a general-purpose register using an
STS instruction, an MA stage for accessing the multiplier is added to the STS instruction,
as described later. When the MA of the STS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.70) to create a single slot. The MA of the STS contends with the IF.
Figure 7.70 illustrates how this occurs, assuming MA and IF contention.
: SlotDMULS.L IF ID EX MA — MA mm mm mm mm
STS

if

—

—

Other instruction

ID EX M——————A WBIFOther instruction
Other instruction......

ID —

—

—

— EX

if

—

—

—

—

ID EX
IF ID EX....

: SlotDMULS.L if
STS
Other instruction
Other instruction
Other instruction......

Figure 7.70

234 HITACHIID EX MA MA mm mm mm mm
IF

— ID
if

— EX M————A WB— ID EXIF

ID
if— — EX— — ID EX ....

STS (Register) Instruction Immediately After a DMULS.L Instruction

6. When an STS.L (memory) instruction is located immediately after a DMULS.L instruction
When the contents of a MAC register are stored in memory using an STS instruction, an
MA stage for accessing the multiplier and writing to memory is added to the STS
instruction, as described later. The MA of the STS contends with the IF. Figure 7.71
illustrates how this occurs, assuming MA and IF contention.
: SlotDMULS.L IF ID EX MA — MA mm mm mm mm
STS.L

if

— —

Other instruction

ID EX M——————AIF

Other instruction
Other instruction......

ID ———— EX MA

if

—

—

—

—

ID EX
IF ID EX....

: SlotDMULS.L if
STS.L
Other instruction
Other instruction
Other instruction......

Figure 7.71

ID EX MA MA mm mm mm mm
IF

— ID
if

— EX M—————A— ID EXIF

ID
if— — EX— — ID EX ....

STS.L (Memory) Instruction Immediately After a DMULS.L Instruction

7. When an LDS (register) instruction is located immediately after a DMULS.L instruction
When the contents of a MAC register are loaded from a general-purpose register using an
LDS instruction, an MA stage for accessing the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box below) to create a single slot. The MA of this LDS contends with IF. The
following figure illustrates how this occurs, assuming MA and IF contention.

HITACHI 235

: Slot
DMULS.L IF ID EX MA — MA mm mm mm mm
LDS

if

— —

Other instruction

ID EX M——————AIF

Other instruction
Other instruction......

ID ———— EX MAif——— ID EXIF ID EX—....

: SlotDMULS.L if
LDS
Other instruction
Other instruction
Other instruction......

Figure 7.72

ID EX MA MA mm mm mm mm
IF

— ID
if

— EX M————A— ID EXIF

ID
if— — EX— — ID EX ....

LDS (Register) Instruction Immediately After a DMULS.L Instruction

8. When an LDS.L (memory) instruction is located immediately after a DMULS.L
instruction
When the contents of a MAC register are loaded from memory using an LDS instruction,
an MA stage for accessing the memory and the multiplier is added to the LDS instruction,
as described later. When the MA of the LDS instruction contends with the operating
multiplier (mm), the MA is extended until the mm ends (the M—A shown in the dottedline box in figure 7.73) to create a single slot. The MA of the LDS contends with IF.
Figure 7.73 illustrates how this occurs, assuming MA and IF contention.

236 HITACHI

: Slot
DMULS.L IF ID EX MA — MA mm mm mm mm
LDS.L

if

—

— ID EX M——————A

Other instruction

IF

ID —

—

—

— EX MA

if

—

—

—

Other instruction
Other instruction......

—ID EX
IF ID EX....

: SlotDMULS.L if

ID EX MA MA mm mm mm mm
IF

LDS.L

— ID
if

Other instruction

7.7.3— ID EXIF

Other instruction
Other instruction......

Figure 7.73

— EX M————AID
if— — EX— — ID EX ....

LDS.L (Memory) Instruction Immediately After a DMULS.L Instruction

Logic Operation Instructions

Register-Register Logic Operation Instructions: Include the following instruction types:
•
•
•
•
•
•
•
•
•

ANDRm, Rn
AND#imm, R0
NOT Rm, Rn
OR Rm, Rn
OR #imm, R0
TST Rm, Rn
TST #imm, R0
XOR Rm, Rn
XOR#imm, R0: SlotInstruction A
Next instruction
Third instruction......

Figure 7.74

IF

ID

EX

IF

ID

EX

.....

IF

ID

EX

.....

Register-Register Logic Operation Instruction Pipeline

HITACHI 237

Operation: The pipeline has three stages: IF, ID, and EX (figure 8.74). The data operation iscompleted in the EX stage via the ALU.
Memory Logic Operation Instructions: Include the following instruction types:
•
•
•
•

AND.B
OR.B
TST.B
XOR.B

#imm, @(R0, GBR)
#imm, @(R0, GBR)
#imm, @(R0, GBR)
#imm, @(R0, GBR)
: SlotInstruction A

IF

Next instruction

ID

EX

MA

EX

MA

IF

—

—

ID

EX

.....

IF

ID

EX

Third instruction......

Figure 7.75.....

Memory Logic Operation Instruction Pipeline

Operation: Operation: The pipeline has six stages: IF, ID, EX, MA, EX, and MA (figure7.75). The ID of the next instruction stalls for 2 slots. The MAs of these instructions contend
with IF.
TAS Instruction: Includes the following instruction type:• TAS.B@Rn: SlotInstruction A
Next instruction

IF

ID

EX

MA

EX

MA

IF

—

—

—

ID

EX

.....

IF

ID

EX

Third instruction......

Figure 7.76.....

TAS Instruction Pipeline

Operation: The pipeline has six stages: IF, ID, EX, MA, EX, and MA (figure 7.76). The IDof the next instruction stalls for 3 slots. The MA of the TAS instruction contends with IF.
7.7.4

Shift Instructions

Shift Instructions: Include the following instruction types:• ROTL238 HITACHI

Rn

•
•
•
•
•
•
•
•
•
•
•
•
•

ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLR
SHLL2
SHLR2
SHLL8
SHLR8
SHLL16
SHLR16

Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rn
: SlotInstruction A

IF

Next instruction

ID

EX

IF

ID

EX

.....

IF

ID

EX

Third instruction......

Figure 7.77.....

Shift Instruction Pipeline

Operation: The pipeline has three stages: IF, ID, and EX (figure 7.77). The data operation iscompleted in the EX stage via the ALU.
7.7.5

Branch Instructions

Conditional Branch Instructions: Include the following instruction types:• BF label• BT label
Operation: The pipeline has three stages: IF, ID, and EX. Condition verification is performedin the ID stage. Conditional branch instructions are not delayed branch.

HITACHI 239

1. When condition is satisfied
The branch destination address is calculated in the EX stage. The two instructions after
the conditional branch instruction (instruction A) are fetched but discarded. The branch
destination instruction begins its fetch from the slot following the slot which has the EX
stage of instruction A (figure 7.78).
: SlotInstruction A

IF

Next instruction

ID

EX

IF

—

(Fetched but discarded)

Third instruction

IF—

Branch destination......

—

IF(Fetched but discarded)
EX .....

ID
IF

ID

EX

.....

......

Figure 7.78

Branch Instruction When Condition is Satisfied

2. When condition is not satisfied
If it is determined that conditions are not satisfied at the ID stage, the EX stage proceeds
without doing anything. The next instruction also executes a fetch (figure 7.79).
: SlotInstruction A
Next instruction
Third instruction......

IF

ID

EX

IF

ID

EX

.....

IF

ID

EX

.....

IF

ID

EX

.....

......

Figure 7.79 Branch Instruction When Condition is Not Satisfied
Note: SH-2 always fetches instructions with a long word. Therefore, "1. When condition issatisfied", 2 instructions are overrun when fetched, if that address is at the boundary of
the 4n address.
Delayed Conditional Branch Instructions (SH-2 CPU): Include the following instruction
types:• BF/S• BT/S

label
label

(SH-2 CPU only)(SH-2 CPU only)

Operation: The pipeline has three stages: IF, ID, and EX. Condition verification is performedin the ID stage.

240 HITACHI1. When condition is satisfied
The branch destination address is calculated in the EX stage. The instruction after theconditional branch instruction (instruction A) is fetched and executed, but the instruction
after that is fetched and discarded. The branch destination instruction begins its fetch fromthe slot following the slot which has the EX stage of instruction A (figure 7.80).
: SlotInstruction A

IF

Next instruction

ID

EX

IF

—

ID

IF

—

Third instruction

IF

Branch destination......

Figure 7.80

EX

MA WB

(Fetched but discarded)
EX .....

ID
IF

ID

EX

.....

Branch Instruction When Condition is Satisfied

2. When condition is not satisfied
If it is determined that conditions are not satisfied at the ID stage, the EX stage proceeds
without doing anything. The next instruction also executes a fetch (figure 7.81).
: SlotInstruction A
Next instruction
Third instruction......

IF

ID

EX

IF

ID

EX

.....

IF

ID

EX

.....

IF

ID

EX

.....

......

Figure 7.81

Branch Instruction When Condition is Not Satisfied

Note: SH-2 always fetches instructions with a long word. Therefore, "1. When condition issatisfied", 2 instructions are overrun when fetched, if that address is at the boundary of
the 4n address.
Unconditional Branch Instructions: Include the following instruction types:
•
•
•
•
•
•
•

BRA label
BRAF
BSR label
BSRF
JMP @Rm
JSR @Rm
RTS

Rm(SH-2 CPU only)

Rm(SH-2 CPU only)

HITACHI 241

: Slot
Instruction A
Delay slot

IF

ID

EX

IF

—

Branch destination......

ID

EX

IF

ID

MA WB
EX .....

IF

ID

EX

.....

......

Figure 7.82

Unconditional Branch Instruction Pipeline

Operation: The pipeline has three stages: IF, ID, and EX (figure 7.82). Unconditional branch
instructions are delayed branch. The branch destination address is calculated in the EX stage.
The instruction following the unconditional branch instruction (instruction A), that is, thedelay slot instruction is fetched and not discarded as the conditional branch instructions are,but is then executed. Note that the ID slot of the delay slot instruction does stall for one
cycle. The branch destination instruction starts its fetch from the slot after the slot that has
the EX stage of instruction A.
7.7.6

System Control Instructions

System Control ALU Instructions: Include the following instruction types:
•
•
•
•
•
•
•
•
•
•
•

CLRT
LDC Rm, SR
LDC Rm, GBR
LDC Rm, VBR
LDS Rm, PR
NOP
SETT
STC SR, Rn
STC GBR, Rn
STC VBR, Rn
STS PR, Rn

242 HITACHI

: Slot
Instruction A

IF

Next instruction

ID

EX

IF

ID

EX

.....

IF

ID

EX

Third instruction......

Figure 7.83.....

System Control ALU Instruction Pipeline

Operation: The pipeline has three stages: IF, ID, and EX (figure 7.83). The data operation iscompleted in the EX stage via the ALU.
LDC.L Instructions: Include the following instruction types:• LDC.L• LDC.L• LDC.L@Rm+, SR
@Rm+, GBR
@Rm+, VBR
: SlotInstruction A

IF

Next instruction

ID

EX

MA

EX

IF

—

—

ID

EX

.....

IF

ID

EX

Third instruction......

Figure 7.84.....

LDC.L Instruction Pipeline

Operation: The pipeline has five stages: IF, ID, EX, MA, and EX (figure 7.84). The ID of thefollowing instruction is stalled for two slots.
STC.L Instructions: Include the following instruction types:• STC.L• STC.L• STC.LSR, @–Rn
GBR, @–Rn
VBR, @–Rn: SlotInstruction A
Next instruction

IF

ID

EX

MA

IF

—

ID

EX

.....

IF

ID

EX

Third instruction......

Figure 7.85.....

STC.L Instruction Pipeline

HITACHI 243

Operation: The pipeline has four stages: IF, ID, EX, and MA (figure 7.85). The ID of thenext instruction is stalled for one slot.
LDS.L Instruction (PR): Includes the following instruction type:• LDS.L@Rm+, PR
: SlotInstruction A

IF

Next instruction

ID

EX

IF

ID

MA WB
EX .....

IFID

Third instruction......

Figure 7.86

EX

.....

LDS.L Instruction (PR) Pipeline

Operation: The pipeline has five stages: IF, ID, EX, MA, and WB (figure 7.86). It is thesame as an ordinary load instruction.
STS.L Instruction (PR): Includes the following instruction type:• STS.LPR, @–Rn: SlotInstruction A

IF

Next instruction
Third instruction......

Figure 7.87

ID

EX

MA

IF

ID

EX

.....

IF

ID

EX

.....

STS.L Instruction (PR) Pipeline

Operation: The pipeline has four stages: IF, ID, EX, and MA (figure 7.87). It is the same as
an ordinary store instruction.
Register → MAC Transfer Instructions: Include the following instruction types:• CLRMAC• LDS Rm, MACH
• LDS Rm, MACL

244 HITACHI

: Slot
Instruction A

IF

Next instruction

ID

EX

MA

IF

ID

EX

.....

IF

ID

EX

Third instruction......

Figure 7.88.....

Register → MAC Transfer Instruction Pipeline

Operation: The pipeline has four stages: IF, ID, EX, and MA (figure 7.88). The MA is astage for accessing the multiplier. The MA contends with the IF. This makes it the same asordinary store instructions. Since the multiplier contends with the MA, see the section for the
SOP instruction, multiply instruction, and double precision multiply instruction.
Memory → MAC Transfer Instructions: Include the following instruction types:• LDS.L• LDS.L@Rm+, MACH
@Rm+, MACL
: SlotInstruction A
Next instruction
Third instruction......

Figure 7.89

IF

ID

EX

MA

IF

ID

EX

.....

IF

ID

EX

.....

Memory → MAC Transfer Instruction Pipeline

Operation: The pipeline has four stages: IF, ID, EX, and MA (figure 7.89). The MA contends
with the IF. The MA is a stage for memory access and multiplier access. This makes it thesame as ordinary load instructions. Since the multiplier contends with the MA, see thesection for the SOP instruction, multiply instruction, and double precision multiply
instruction.
MAC → Register Transfer Instructions: Include the following instruction types:• STS MACH, Rn• STS MACL, Rn

HITACHI 245

: Slot
Instruction A

IF

Next instruction

ID
IF

Third instruction......

ID

MA WB
EX .....

IF

ID

EX

EX

.....

Figure 7.90 MAC → Register Transfer Instruction Pipeline
Operation: The pipeline has five stages: IF, ID, EX, MA, and WB (figure 7.90). The MA is astage for accessing the multiplier. The MA contends with the IF. This makes it the same asordinary load instructions. Since the multiplier contends with the MA, see the section for the
SOP instruction, multiply instruction, and double precision multiply instruction.
MAC → Memory Transfer Instructions: Include the following instruction types:• STS.L• STS.L

MACH, @–Rn
MACL, @–Rn
: SlotInstruction A
Next instruction
Third instruction......

Figure 7.91

IF

ID

EX

MA

IF

ID

EX

.....

IF

ID

EX

.....

MAC → Memory Transfer Instruction Pipeline

Operation: The pipeline has four stages: IF, ID, EX, and MA (figure 7.91). The MA is astage for accessing the memory and the multiplier. The MA contends with IF. This makes it
the same as ordinary store instructions. Since the multiplier contends with the MA, see thesection for the SOP instruction, multiply instruction, and double precision multiply
instruction.
RTE Instruction: Includes the following instruction type:• RTE

246 HITACHI

: Slot
RTE

IF

Delay slot

ID

EX

MA

MA

IF

—

—

—

Branch destination......

Figure 7.92

ID

EX

.....

IF

ID

EX

.....

RTE Instruction Pipeline

The pipeline has five stages: IF, ID, EX, MA, and MA (figure 7.92). The MAs contend with
the IF. The RTE is a delayed branch instruction. The ID of the delay slot instruction is stalled
for 3 slots. The IF of the branch destination instruction starts from the slot following the MAof the RTE.
TRAP Instruction: Includes the following instruction type:• TRAPA#imm: SlotTRAPA

Next instruction
Third instruction

IF

ID

EX EX MA MA MA EX EX

IFIF

Branch destination......

IF

Figure 7.93

ID

EX .....

IFID

EX .....

TRAP Instruction Pipeline

The pipeline has nine stages: IF, ID, EX, EX, MA, MA, MA, EX, and EX (figure 7.93). The
MAs contend with the IF. The TRAP is not a delayed branch instruction. The two instructions
after the TRAP instruction are fetched, but they are discarded without being executed. The IFof the branch destination instruction starts from the slot of the EX in the ninth stage of the
TRAP instruction.
SLEEP Instruction: Includes the following instruction type:• SLEEPHITACHI 247

: Slot
IF

SLEEP

ID

Next instruction......

EX

IF

Figure 7.94

SLEEP Instruction Pipeline

Operation: The pipeline has three stages: IF, ID and EX (figure 7.94). It is issued until the IFof the next instruction. After the SLEEP instruction is executed, the CPU enters sleep modeor standby mode.
7.7.7

Exception Processing

Interrupt Exception Processing: Includes the following instruction type:• Interrupt exception processing: SlotInterrupt
Next instruction

IF

ID

EX EX MA MA EX MA EX EX

IF

Branch destination......

Figure 7.95

IF

ID
IF

EX .....
ID .....

Interrupt Exception Processing Pipeline

Operation: The interrupt is received during the ID stage of the instruction and everything
after the ID stage is replaced by the interrupt exception processing sequence. The pipeline
has ten stages: IF, ID, EX, EX, MA, MA, EX, MA, EX, and EX (figure 7.95). Interrupt
exception processing is not a delayed branch. In interrupt exception processing, an overrun
fetch (IF) occurs. In branch destination instructions, the IF starts from the slot that has the
final EX in the interrupt exception processing.
Interrupt sources are external interrupt request pins such as NMI, user breaks, and on-chip
peripheral module interrupts.

248 HITACHIAddress Error Exception Processing: Includes the following instruction type:• Address error exception processing: SlotInterrupt

IF

Next instruction

ID

EX EX MA MA EX MA EX EX

IF

Branch destination......

IF

ID
IF

Figure 7.96

EX .....
ID .....

Address Error Exception Processing Pipeline

Operation: The address error is received during the ID stage of the instruction and everything
after the ID stage is replaced by the address error exception processing sequence. The
pipeline has ten stages: IF, ID, EX, EX, MA, MA, EX, MA, EX, and EX (figure 7.96).
Address error exception processing is not a delayed branch. In address error exception
processing, an overrun fetch (IF) occurs. In branch destination instructions, the IF starts fromthe slot that has the final EX in the address error exception processing.
Address errors are caused by instruction fetches and by data reads or writes. For details of theerror cause, refer to the appropriate hardware manual.
Illegal Instruction Exception Processing: Includes the following instruction type:• Illegal instruction exception processing: SlotIllegal instruction

IF

Next instruction(Third instruction
Branch destination......

Figure 7.97

ID

EX EX MA MA MA EX EX

IF
IF)
IF

ID
IF

EX .....
ID .....

Illegal Instruction Exception Processing Pipeline

Operation: The illegal instruction is received during the ID stage of the instruction andeverything after the ID stage is replaced by the illegal instruction exception processing
sequence. The pipeline has nine stages: IF, ID, EX, EX, MA, MA, MA, EX, and EX (figure7.97). Illegal instruction exception processing is not a delayed branch. In illegal instruction
exception processing, an overrun fetch (IF) occurs. Whether there is an IF only in the next
instruction or in the one after that as well depends on the instruction that was to be executed.

HITACHI 249

In branch destination instructions, the IF starts from the slot that has the final EX in theillegal instruction exception processing.
Illegal instruction exception processing is caused by ordinary illegal instructions and byillegal slot instructions. When undefined code placed somewhere other than the slot directly
after the delayed branch instruction (called the delay slot) is decoded, ordinary illegal
instruction exception processing occurs. When undefined code placed in the delay slot is
decoded or when an instruction placed in the delay slot to rewrite the program counter isdecoded, an illegal slot instruction exception handling occurs.

250 HITACHIAppendix A Instruction Code
See “6. Instruction Descriptions” for details.

A.1

Instruction Set by Addressing Mode

Table A.1 lists instruction codes and execution states by addressing modes.

HITACHI 251

Table A.1 Instruction Set by Addressing Mode
Types
Addressing Mode

Category

Sample Instruction

SH-2

SH-1

No operand

—

NOP

8

8

Direct register addressing

Destination operand only

MOVT

Rn

18

17

Source and destination
operand

ADD

Rm,Rn

34

31

Load and store with control
register or system register

LDC

Rm,SR

12

12

STS

MACH,Rn

Source operand only

JMP

@Rm

2

2

Destination operand only

TAS.B

@Rn

1

1

Data transfer with direct
register addressing

MOV.L

Rm,@Rn6

6Multiply/accumulate
operation

MAC.W@Rm+,@Rn+

2

1

Data transfer from direct
register addressing

MOV.L@Rm+,Rn

3

3

Load to control register orsystem register

LDC.L@Rm+,SR6

6

Data transfer from direct
register addressing

MOV.L

Rm,@–Rn

3

3Store from control register orsystem register

STC.L

SR,@–Rn

6

6

Indirect register addressing
with displacement

Data transfer with direct
register addressing

MOV.L

Rm,@(disp,Rn)

6

6

Indirect indexed register
addressing

Data transfer with direct
register addressing

MOV.L

Rm,@(R0,Rn)

6

6

Indirect GBR addressing
with displacement

Data transfer with direct
register addressing

MOV.L

R,@(disp,GBR)

6

6

Indirect indexed GBR
addressing

Immediate data transfer

AND.B#imm,@(R0,GBR)

4

4

PC relative addressing withdisplacement

Data transfer to direct
register addressing

MOV.L@(disp,PC),Rn

3

3

PC relative addressing withRm

Branch instruction

BRAF

Rm

2

0

PC relative addressing

Branch instruction

BRA

label

6

4

Immediate addressing

Arithmetic logical operations
with direct register
addressing

ADD#imm,Rn

7

7

Specify exception processing
vector

TRAPA

#imm

1

1

142

133

Indirect register
addressing

Post increment indirect
register addressing

Pre decrement indirect
register addressing

Total:

252 HITACHIA.1.1No OperandTable A.2 No OperandInstruction

Code

Operation

State

T Bit

CLRT

0000000000001000

0→T

1

0

CLRMAC

0000000000101000

0 → MACH, MACL

1

—

DIV0U

0000000000011001

0 → M/Q/T

1

0

NOP

0000000000001001

No operation

1

—

RTE

0000000000101011

Delayed branch, Stack area
→ PC/SR

4

LSB

RTS

0000000000001011

Delayed branch, PR → PC

2

—

SETT

0000000000011000

1→T

1

1

SLEEP

0000000000011011

Sleep

3

—

HITACHI 253

A.1.2

Direct Register Addressing

Table A.3 Destination Operand Only
Instruction

Code

Operation

State

T Bit

CMP/PL Rn

0100nnnn00010101

Rn > 0, 1 → T

1Comparison result

CMP/PZ Rn

0100nnnn00010001

Rn ≥ 0, 1 → T

1Comparison result

DT

Rn*

0100nnnn00010000

Rn – 1 → Rn
When Rn is 0, 1 → T,
when Rn is nonzero,
0→T

1Comparison result

MOVT

Rn

0000nnnn00101001

T → Rn

1

—

ROTL

Rn

0100nnnn00000100

T ← Rn ← MSB

1

MSB

ROTR

Rn

0100nnnn00000101

LSB → Rn → T

1

LSB

ROTCL

Rn

0100nnnn00100100

T ← Rn ← T

1

MSB

ROTCR

Rn

0100nnnn00100101

T → Rn → T

1

LSB

SHAL

Rn

0100nnnn00100000

T ← Rn ← 0

1

MSB

SHAR

Rn

0100nnnn00100001

MSB → Rn → T

1

LSB

SHLL

Rn

0100nnnn00000000

T ← Rn ← 0

1

MSB

SHLR

Rn

0100nnnn00000001

0 → Rn → T

1

LSB

SHLL2

Rn

0100nnnn00001000

Rn<<2 → Rn

1

—

SHLR2

Rn

0100nnnn00001001

Rn>>2 → Rn

1

—

SHLL8

Rn

0100nnnn00011000

Rn<<8 → Rn

1

—

SHLR8

Rn

0100nnnn00011001

Rn>>8 → Rn

1—

SHLL16 Rn

0100nnnn00101000

Rn<<16 → Rn

1—

SHLR16 Rn

0100nnnn00101001

Rn>>16 → Rn

1—

Note: SH-2 CPU instruction

Table A.4 Source and Destination OperandInstruction

Code

Operation

State

T Bit

ADD

Rm,Rn

0011nnnnmmmm1100

Rn + Rm → Rn

1

—

ADDC

Rm,Rn

0011nnnnmmmm1110

Rn + Rm + T → Rn,
carry → T

1

Carry

ADDV

Rm,Rn

0011nnnnmmmm1111

Rn + Rm → Rn,
overflow → T

1

Overflow

AND

Rm,Rn

0010nnnnmmmm1001

Rn & Rm → Rn

1—

254 HITACHITable A.4 Source and Destination Operand (cont)
Instruction

Code

Operation

State

T Bit

CMP/EQ Rm,Rn

0011nnnnmmmm0000

When Rn = Rm, 1 → T

1Comparison
result

CMP/HS Rm,Rn

0011nnnnmmmm0010

When unsigned and Rn 1
≥ Rm, 1 → T

Comparison
result

CMP/GE Rm,Rn

0011nnnnmmmm0011

When signed and Rn ≥Rm, 1 → T

1

Comparison
result

CMP/HI Rm,Rn

0011nnnnmmmm0110

When unsigned and Rn 1
> Rm, 1 → T

Comparison
result

CMP/GT Rm,Rn

0011nnnnmmmm0111

When signed and Rn >Rm, 1 → T

1

Comparison
result

CMP/STR
Rm,Rn

0010nnnnmmmm1100

When a byte in Rn
equals bytes in Rm, 1→T

1

Comparison
result

DIV1

Rm,Rn

0011nnnnmmmm0100

1-step division (Rn ÷Rm)1

Calculation
result

DIV0S

Rm,Rn

0010nnnnmmmm0111

MSB of Rn → Q, MSB
of Rm → M, M ^ Q →T

1

Calculation
resultDMULS.L
Rm,Rn*20011nnnnmmmm1101

Signed, Rn × Rm →MACH, MACL

2 to 4*1—

DMULU.L
Rm,Rn*20011nnnnmmmm0101

Unsigned, Rn × Rm →MACH, MACL

2 to 4*1—

EXTS.B Rm,Rn

0110nnnnmmmm1110

Sign – extends Rmfrom byte → Rn

1—

EXTS.W Rm,Rn

0110nnnnmmmm1111

Sign – extends Rmfrom word → Rn

1—

EXTU.B Rm,Rn

0110nnnnmmmm1100

Zero – extends Rmfrom byte → Rn

1—

EXTU.W Rm,Rn

0110nnnnmmmm1101

Zero – extends Rmfrom word → Rn

1

—

MOV

0110nnnnmmmm0011

Rm → Rn

1—

0000nnnnmmmm0111

Rn × Rm → MACL

2 to 4*1—

MULS.W Rm,Rn

0010nnnnmmmm1111

Signed, Rn × Rm →MAC

1 to 3*1—

MULU.W Rm,Rn

0010nnnnmmmm1110

Unsigned, Rn × Rm →MAC

1 to 3*1

—

NEG

Rm,Rn

0110nnnnmmmm1011

0 – Rm → Rn

1

—

NEGC

Rm,Rn

0110nnnnmmmm1010

0 – Rm – T → Rn,
Borrow → T

1

Borrow

Notes:

1. The normal minimum number of execution states
2. SH-2 CPU instruction

MUL.L

Rm,Rn
Rm,Rn*2

HITACHI 255

Table A.4 Source and Destination Operand (cont)
Instruction

Code

Operation

State

T Bit

NOT

Rm,Rn

0110nnnnmmmm0111~Rm → Rn

1

—

OR

Rm,Rn

0010nnnnmmmm1011

Rn | Rm → Rn

1

—

SUB

Rm,Rn

0011nnnnmmmm1000

Rn – Rm → Rn

1

—

SUBC

Rm,Rn

0011nnnnmmmm1010

Rn – Rm – T → Rn,
Borrow → T

1

Borrow

SUBV

Rm,Rn

0011nnnnmmmm1011

Rn – Rm → Rn,
Underflow → T

1

Underflow

SWAP.B Rm,Rn

0110nnnnmmmm1000

Rm → Swap upper andlower halves of lower 2
bytes → Rn

1—

SWAP.W Rm,Rn

0110nnnnmmmm1001

Rm → Swap upper andlower word → Rn

1

—

TST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm, when result is
0, 1 → T

1

Test results

XOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm → Rn

1

—

XTRCT

Rm,Rn

0010nnnnmmmm1101

Center 32 bits of Rm
and Rn → Rn

1—

Table A.5 Load and Store with Control Register or System Register
Instruction

Code

Operation

State

T Bit

LDC

Rm,SR

0100mmmm00001110

Rm → SR

1

LSB

LDC

Rm,GBR

0100mmmm00011110

Rm → GBR

1

—

LDC

Rm,VBR

0100mmmm00101110

Rm → VBR

1

—

LDS

Rm,MACH

0100mmmm00001010

Rm → MACH

1

—

LDS

Rm,MACL

0100mmmm00011010

Rm → MACL

1

—

LDS

Rm,PR

0100mmmm00101010

Rm → PR

1

—

STC

SR,Rn

0000nnnn00000010

SR → Rn

1—

STC

GBR,Rn

0000nnnn00010010

GBR → Rn

1

—

STC

VBR,Rn

0000nnnn00100010

VBR → Rn

1

—

STS

MACH,Rn

0000nnnn00001010

MACH → Rn

1

—

STS

MACL,Rn

0000nnnn00011010

MACL → Rn

1

—

STS

PR,Rn

0000nnnn00101010

PR → Rn1—

256 HITACHIA.1.3

Indirect Register Addressing

Table A.6 Destination Operand Only
Instruction

Code

Operation

State

T Bit

JMP

@Rm

0100mmmm00101011

Delayed branch, Rm → PC

2

—

JSR

@Rm

0100mmmm00001011

Delayed branch, PC → PR,
Rm → PC

2

—

TAS.B

@Rn

0100nnnn00011011

When (Rn) is 0, 1 → T, 1 →MSB of (Rn)4

Test results

Table A.7 Data Transfer with Direct Register Addressing
Instruction

Code

Operation

State

T Bit

MOV.B

Rm,@Rn0010nnnnmmmm0000

Rm → (Rn)

1

—

MOV.W

Rm,@Rn0010nnnnmmmm0001

Rm → (Rn)

1

—

MOV.L

Rm,@Rn0010nnnnmmmm0010

Rm → (Rn)

1

—

MOV.B

@Rm,Rn0110nnnnmmmm0000(Rm) → sign extension → Rn

1

—

MOV.W

@Rm,Rn0110nnnnmmmm0001(Rm) → sign extension → Rn

1

—

MOV.L

@Rm,Rn0110nnnnmmmm0010(Rm) → Rn

1

—

A.1.4

Post Increment Indirect Register Addressing

Operation

State

T
Bit

Table A.8 Multiply/Accumulate Operation
Instruction

Code

MAC.L

@Rm+,@Rn+* 2 0000nnnnmmmm1111

Signed, (Rn) × (Rm) + MAC→ MAC

3/(2to 4)*1

—

MAC.W

@Rm+,@Rn+

Signed, (Rn) × (Rm) + MAC→ MAC

3/(2)*1—

Notes:

1. The normal minimum number of execution states (The number in parentheses is thenumber of states when there is contention with preceding/following instructions).
2. SH-2 CPU instruction

0100nnnnmmmm1111

HITACHI 257

Table A.9 Data Transfer from Direct Register Addressing
Instruction

Code

Operation

State

T Bit

MOV.B

@Rm+,Rn

0110nnnnmmmm0100(Rm) → sign extension →Rn, Rm + 1 → Rm

1

—

MOV.W

@Rm+,Rn

0110nnnnmmmm0101(Rm) → sign extension →Rn, Rm + 2 → Rm

1

—

MOV.L

@Rm+,Rn

0110nnnnmmmm0110(Rm) → Rn, Rm + 4 → Rm

1—

Table A.10 Load to Control Register or System Register
Instruction

Code

Operation

State

T Bit

LDC.L

@Rm+,SR

0100mmmm00000111(Rm) → SR, Rm + 4 → Rm

3

LSB

LDC.L

@Rm+,GBR

0100mmmm00010111(Rm) → GBR, Rm + 4 → Rm

3

—

LDC.L

@Rm+,VBR

0100mmmm00100111(Rm) → VBR, Rm + 4 → Rm

3

—

LDS.L

@Rm+,MACH 0100mmmm00000110(Rm) → MACH, Rm + 4 → Rm

1

—

LDS.L

@Rm+,MACL 0100mmmm00010110(Rm) → MACL, Rm + 4 → Rm

1

—

LDS.L

@Rm+,PR(Rm) → PR, Rm + 4 → Rm

1

—

A.1.5

Pre Decrement Indirect Register Addressing

0100mmmm00100110

Table A.11 Data Transfer from Direct Register Addressing
Instruction

Code

Operation

State

T Bit

MOV.B

Rm,@–Rn

0010nnnnmmmm0100

Rn – 1 → Rn, Rm → (Rn)

1

—

MOV.W

Rm,@–Rn

0010nnnnmmmm0101

Rn – 2 → Rn, Rm → (Rn)

1

—

MOV.L

Rm,@–Rn

0010nnnnmmmm0110

Rn – 4 → Rn, Rm → (Rn)1—

258 HITACHITable A.12 Store from Control Register or System Register
Instruction

Code

Operation

State

T Bit

STC.L

SR,@-Rn

0100nnnn00000011

Rn – 4 → Rn, SR → (Rn)

2

—

STC.L

GBR,@-Rn

0100nnnn00010011

Rn – 4 → Rn, GBR → (Rn)

2

—

STC.L

VBR,@-Rn

0100nnnn00100011

Rn – 4 → Rn, VBR → (Rn)

2

—

STS.L

MACH,@–Rn

0100nnnn00000010

Rn – 4 → Rn, MACH → (Rn) 1

—

STS.L

MACL,@–Rn

0100nnnn00010010

Rn – 4 → Rn, MACL → (Rn)

1

—

STS.L

PR,@–Rn

0100nnnn00100010

Rn – 4 → Rn, PR → (Rn)

1

—

A.1.6

Indirect Register Addressing with Displacement

Table A.13 Indirect Register Addressing with Displacement
Instruction

Code

Operation

State

T Bit

MOV.B

R0,@(disp,Rn)

10000000nnnndddd

R0 → (disp + Rn)

1

—

MOV.W

R0,@(disp,Rn)

10000001nnnndddd

R0 → (disp × 2 + Rn)

1

—

MOV.L

Rm,@(disp,Rn)

0001nnnnmmmmdddd

Rm → (disp × 4 + Rn)

1

—

MOV.B

@(disp,Rm),R0

10000100mmmmdddd(disp + Rm) → signextension → R0

1

—

MOV.W

@(disp,Rm),R0

10000101mmmmdddd(disp × 2 + Rm) →sign extension → R0

1

—

MOV.L

@(disp,Rm),Rn

0101nnnnmmmmdddd(disp × 4 + Rm) → Rn

1

—

A.1.7

Indirect Indexed Register Addressing

Table A.14 Indirect Indexed Register Addressing
Instruction

Code

Operation

State

T Bit

MOV.B

Rm,@(R0,Rn)

0000nnnnmmmm0100

Rm → (R0 + Rn)

1

—

MOV.W

Rm,@(R0,Rn)

0000nnnnmmmm0101

Rm → (R0 + Rn)

1

—

MOV.L

Rm,@(R0,Rn)

0000nnnnmmmm0110

Rm → (R0 + Rn)

1

—

MOV.B

@(R0,Rm),Rn

0000nnnnmmmm1100(R0 + Rm) → signextension → Rn

1

—

MOV.W

@(R0,Rm),Rn

0000nnnnmmmm1101(R0 + Rm) → signextension → Rn

1

—

MOV.L

@(R0,Rm),Rn

0000nnnnmmmm1110(R0 + Rm) → Rn

1—

HITACHI 259

A.1.8Indirect GBR Addressing with Displacement

Table A.15 Indirect GBR Addressing with Displacement
Instruction

Code

Operation

State

T Bit

MOV.B

R0,@(disp,GBR)

11000000dddddddd

R0 → (disp + GBR)

1

—

MOV.W

R0,@(disp,GBR)

11000001dddddddd

R0 → (disp × 2 +
GBR)

1

—

MOV.L

R0,@(disp,GBR)

11000010dddddddd

R0 → (disp × 4 +
GBR)

1

—

MOV.B

@(disp,GBR),R0

11000100dddddddd(disp + GBR) → signextension → R0

1

—

MOV.W

@(disp,GBR),R0

11000101dddddddd(disp × 2 + GBR) →sign extension → R0

1

—

MOV.L

@(disp,GBR),R0

11000110dddddddd(disp × 4 + GBR) →
R0

1

—

A.1.9

Indirect Indexed GBR Addressing

State

T Bit

Table A.16 Indirect Indexed GBR Addressing
Instruction

Code

Operation

AND.B#imm,@(R0,GBR) 11001101iiiiiiii(R0 + GBR) & imm → (R0 3+ GBR)—

OR.B#imm,@(R0,GBR) 11001111iiiiiiii(R0 + GBR) | imm → (R0+ GBR)—

TST.B#imm,@(R0,GBR) 11001100iiiiiiii(R0 + GBR) & imm, when 3
result is 0, 1 → T

Test
results

XOR.B#imm,@(R0,GBR) 11001110iiiiiiii(R0 + GBR) ^ imm → (R0+ GBR)

3—

A.1.10PC Relative Addressing with Displacement

3

Table A.17 PC Relative Addressing with Displacement
Instruction

Code

Operation

State

T Bit

MOV.W

@(disp,PC),Rn

1001nnnndddddddd(disp × 2 + PC) → signextension → Rn

1

—

MOV.L

@(disp,PC),Rn

1101nnnndddddddd(disp × 4 + PC) → Rn

1

—

MOVA

@(disp,PC),R0

11000111dddddddd

disp × 4 + PC → R0

1—

260 HITACHIA.1.11PC Relative Addressing with Rm

Table A.18 PC Relative Addressing with Rm
Instruction

Code

Operation

State

T Bit

BRAF

Rm*2

0000mmmm00100011

Delayed branch, Rm + PC → PC

2

—

BSRF

Rm*2

0000mmmm00000011

Delayed branch, PC → PR, Rm + PC 2
→ PC—

Notes:

2. SH-2 CPU instruction

A.1.12PC Relative Addressing

Table A.19 PC Relative Addressing
Instruction

Code

Operation

State

T Bit

BF

label

10001011dddddddd

When T = 0, disp × 2 + PC → PC;
When T = 1, nop

3/1*3

—

BF/S

label*2

10001111dddddddd

When T = 0, disp × 2 + PC → PC;
When T = 1, nop

2/1*3

—

BT

label

10001001dddddddd

When T = 1, disp × 2+ PC → PC;
When T = 0, nop

3/1*3

—

BT/S

label*2

10001101dddddddd

When T = 1, disp × 2 + PC → PC;
When T = 0, nop

2/1*3

—

BRA

label

1010dddddddddddd

Delayed branch, disp × 2 + PC →
PC

2

—

BSR

label

1011dddddddddddd

Delayed branch, PC → PR, disp × 2
2 + PC → PC—

Notes: 2. SH-2 CPU instruction
3. One state when it does not branch

HITACHI 261

A.1.13

Immediate

Table A.20 Arithmetic Logical Operation with Direct Register Addressing
Instruction

Code

Operation

State

T Bit

ADD

#imm,Rn

0111nnnniiiiiiii

Rn + imm → Rn

1

—

AND

#imm,R0

11001001iiiiiiii

R0 & imm → R0

1—

CMP/EQ #imm,R0

10001000iiiiiiii

When R0 = imm, 1 → T

1Comparison result

MOV#imm,Rn

1110nnnniiiiiiii

imm → sign extension → Rn 1—

OR

#imm,R0

11001011iiiiiiii

R0 | imm → R0

1

—

TST

#imm,R0

11001000iiiiiiii

R0 & imm, when result is 0,
1→T1

Test results

XOR#imm,R0

11001010iiiiiiii

R0 ^ imm → R0

1—

Table A.21 Specify Exception Processing Vector
Instruction

Code

Operation

State

T Bit

TRAPA

#imm

11000011iiiiiiii

PC/SR → Stack area, (imm × 4 +VBR) → PC

8

—

A.2

Instruction Sets by Instruction Format

Tables A.22 to A.48 list instruction codes and execution states by instruction formats.

262 HITACHITable A.22 Instruction Sets by Format
Types
FormatCategory

Sample Instruction

0

—

NOP

Direct register addressing

MOVT

n

SH-2 SH-1
8

8

Rn

18

17

Direct register addressing (store with control STSor system registers)

MACH,Rn

6

6

Indirect register addressing

TAS.B

@Rn

1

1

Pre decrement indirect register addressing

STC.L

SR,@–Rn

6

6

Direct register addressing (load with control LDC
or system registers)

Rm,SR

6

6

PC relative addressing with Rn

BRAF

Rm

2

0

Direct register addressing

JMP

@Rm

2

2

Post increment indirect register addressing

LDC.L@Rm+,SR6

6

Direct register addressing

ADD

Rm,Rn

34

31

Indirect register addressing

MOV.L

Rm,@Rn6

6

Post increment indirect register addressing(multiply/accumulate operation)

MAC.W@Rm+,@Rn+

2

1

Post increment indirect register addressing

MOV.L@Rm+,Rn

3

3

Pre decrement indirect register addressing

MOV.L

Rm,@–Rn

3

3

Indirect indexed register addressing

MOV.L

Rm,@(R0,Rn)

6

6

md

Indirect register addressing withdisplacement

MOV.B@(disp,Rm),R0

2

2

nd4

Indirect register addressing withdisplacement

MOV.B

R0,@(disp,Rn)

2

2

nmd

Indirect register addressing withdisplacement

MOV.L

Rm,@(disp,Rn)

2

2

d

Indirect GBR addressing with displacement MOV.L

R0,@(disp,GBR)

6

6

Indirect PC addressing with displacement

MOVA@(disp,PC),R0

1

1

PC relative addressing

BF

label

4

2

d12

PC relative addressing

BRA

label

2

2

nd8

PC relative addressing with displacement

MOV.L@(disp,PC),Rn

2

2

Indirect indexed GBR addressing

AND.B

m

nm

i

ni

#imm,@(R0,GBR)

4

4

Immediate addressing (arithmetic and logical AND
operations with direct register)#imm,R05

5

Immediate addressing (specify exception
processing vector)

TRAPA

#imm

1

1

Immediate addressing (direct register
arithmetic operations and data transfers )ADD#imm,Rn

2

2

142

133

Total:HITACHI 263

A.2.10 FormatTable A.23 0 Format
Instruction

Code

Operation

State

T Bit

CLRT

0000000000001000

0→T

1

0

CLRMAC

0000000000101000

0 → MACH, MACL

1

—

DIV0U

0000000000011001

0 → M/Q/T

1

0

NOP

0000000000001001

No operation

1

—

RTE

0000000000101011

Delayed branching, stackarea → PC/SR

4

LSB

RTS

0000000000001011

Delayed branching, PR →
PC

2

—

SETT

0000000000011000

1→T

1

1

Sleep

3* 4

—

SLEEP

0000000000011011

Notes: 4. This is the number of states until a transition is made to the Sleep state.

264 HITACHIA.2.2n FormatTable A.24 Direct Register Addressing
Instruction

Code

Operation

State

T Bit

CMP/PL Rn

0100nnnn00010101

Rn > 0, 1 → T

1Comparison result

CMP/PZ Rn

0100nnnn00010001

Rn ≥ 0, 1 → T

1Comparison result

DT

Rn*2

0100nnnn00010000

Rn - 1 → Rn;
If Rn is 0, 1 → T, if Rn
is nonzero, 0 → T

1Comparison result

MOVT

Rn

0000nnnn00101001

T → Rn

1

—

ROTL

Rn

0100nnnn00000100

T ← Rn ← MSB

1

MSB

ROTR

Rn

0100nnnn00000101

LSB → Rn → T

1

LSB

ROTCL

Rn

0100nnnn00100100

T ← Rn ← T

1

MSB

ROTCR

Rn

0100nnnn00100101

T → Rn → T

1

LSB

SHAL

Rn

0100nnnn00100000

T ← Rn ← 0

1

MSB

SHAR

Rn

0100nnnn00100001

MSB → Rn → T

1

LSB

SHLL

Rn

0100nnnn00000000

T ← Rn ← 0

1

MSB

SHLR

Rn

0100nnnn00000001

0 → Rn → T

1

LSB

SHLL2

Rn

0100nnnn00001000

Rn<<2 → Rn

1

—

SHLR2

Rn

0100nnnn00001001

Rn>>2 → Rn

1

—

SHLL8

Rn

0100nnnn00011000

Rn<<8 → Rn

1

—

SHLR8

Rn

0100nnnn00011001

Rn>>8 → Rn

1—

SHLL16 Rn

0100nnnn00101000

Rn<<16 → Rn

1—

SHLR16 Rn

0100nnnn00101001

Rn>>16 → Rn

1—

Notes:

2. SH-2 CPU instruction.

Table A.25 Direct Register Addressing (Store with Control and System Registers)
Instruction

Code

Operation

State

T Bit

STC

SR,Rn

0000nnnn00000010

SR → Rn

1—

STC

GBR,Rn

0000nnnn00010010

GBR → Rn

1

—

STC

VBR,Rn

0000nnnn00100010

VBR → Rn

1

—

STS

MACH,Rn

0000nnnn00001010

MACH → Rn

1

—

STS

MACL,Rn

0000nnnn00011010

MACL → Rn

1

—

STS

PR,Rn

0000nnnn00101010

PR → Rn

1—

HITACHI 265

Table A.26 Indirect Register Addressing
Instruction

Code

Operation

State

T Bit

TAS.B

0100nnnn00011011

When (Rn) is 0, 1 → T, 1 →MSB of (Rn)4

Test results@Rn

Table A.27 Pre Decrement Indirect Register
Instruction

Code

Operation

State

T Bit

STC.L

SR,@-Rn

0100nnnn00000011

Rn – 4 → Rn, SR → (Rn)

2

—

STC.L

GBR,@-Rn

0100nnnn00010011

Rn – 4 → Rn, GBR → (Rn)

2

—

STC.L

VBR,@-Rn

0100nnnn00100011

Rn – 4 → Rn, VBR → (Rn)

2

—

STS.L

MACH,@–Rn

0100nnnn00000010

Rn – 4 → Rn, MACH → (Rn) 1

—

STS.L

MACL,@–Rn

0100nnnn00010010

Rn – 4 → Rn, MACL → (Rn)

1

—

STS.L

PR,@–Rn

0100nnnn00100010

Rn – 4 → Rn, PR → (Rn)1—

266 HITACHIA.2.3m FormatTable A.28 Direct Register Addressing (Load with Control and System Registers)
Instruction

Code

Operation

State

T Bit

LDC

Rm,SR

0100mmmm00001110

Rm → SR

1

LSB

LDC

Rm,GBR

0100mmmm00011110

Rm → GBR

1

—

LDC

Rm,VBR

0100mmmm00101110

Rm → VBR

1

—

LDS

Rm,MACH

0100mmmm00001010

Rm → MACH

1

—

LDS

Rm,MACL

0100mmmm00011010

Rm → MACL

1

—

LDS

Rm,PR

0100mmmm00101010

Rm → PR

1—

Table A.29 Indirect Register
Instruction

Code

Operation

State

T Bit

JMP

@Rm

0100mmmm00101011

Delayed branch, Rm → PC

2

—

JSR

@Rm

0100mmmm00001011

Delayed branch, PC → PR,
Rm → PC

2—

Table A.30 Post Increment Indirect Register
Instruction

Code

Operation

State

T Bit

LDC.L

@Rm+,SR

0100mmmm00000111(Rm) → SR, Rm + 4 → Rm

3

LSB

LDC.L

@Rm+,GBR

0100mmmm00010111(Rm) → GBR, Rm + 4 → Rm

3

—

LDC.L

@Rm+,VBR

0100mmmm00100111(Rm) → VBR, Rm + 4 → Rm

3—

0100mmmm00000110(Rm) → MACH, Rm + 4 → Rm

1—

0100mmmm00010110(Rm) → MACL, Rm + 4 → Rm

1—

0100mmmm00100110(Rm) → PR, Rm + 4 → Rm

1

—

LDS.L
@Rm+,MAC
H
LDS.L@Rm+,MAC
L
LDS.L@Rm+,PR

HITACHI 267

Table A.31 PC Relative Addressing with Rm
Instruction

Code

Operation

State

T Bit

BRAF

Rm*2

0000mmmm00100011

Delayed branch, Rm + PC → PC

2

—

BSRF

Rm*2

0000mmmm00000011

Delayed branch, PC → PR, Rm + PC 2
→ PC—

Notes:

2. SH-2 CPU instruction

268 HITACHIA.2.4nm Format

Table A.32 Direct Register Addressing
Instruction

Code

Operation

State

T Bit

ADD

Rm,Rn

0011nnnnmmmm1100

Rn + Rm → Rn

1

—

ADDC

Rm,Rn

0011nnnnmmmm1110

Rn + Rm + T → Rn, carry
→T

1

Carry

ADDV

Rm,Rn

0011nnnnmmmm1111

Rn + Rm → Rn, overflow→T

1

Overflow

AND

Rm,Rn

0010nnnnmmmm1001

Rn & Rm → Rn

1—

CMP/EQ Rm,Rn

0011nnnnmmmm0000

When Rn = Rm, 1 → T

1Comparison
result

CMP/HS Rm,Rn

0011nnnnmmmm0010

When unsigned and Rn ≥Rm, 1 → T

1

Comparison
result

CMP/GE Rm,Rn

0011nnnnmmmm0011

When signed and Rn ≥Rm, 1 → T

1

Comparison
result

CMP/HI Rm,Rn

0011nnnnmmmm0110

When unsigned and Rn >Rm, 1 → T

1

Comparison
result

CMP/GT Rm,Rn

0011nnnnmmmm0111

When signed and Rn >Rm, 1 → T

1

Comparison
result

CMP/STR
Rm,Rn

0010nnnnmmmm1100

When a byte in Rn equals
a byte in Rm, 1 → T

1Comparison
result

DIV1

Rm,Rn

0011nnnnmmmm0100

1-step division (Rn ÷ Rm)

1

Calculation
result

DIV0S

Rm,Rn

0010nnnnmmmm0111

MSB of Rn → Q, MSB of 1
Rm → M, M ^ Q → T

Calculation
resultDMULS.L
Rm,Rn*20011nnnnmmmm1101

Signed, Rn x Rm →MACH, MACL

2 to
4* 1

—

DMULU.L
Rm,Rn*20011nnnnmmmm0101

Unsigned, Rn x Rm →MACH, MACL

2 to
4* 1

—

EXTS.B Rm,Rn

0110nnnnmmmm1110

Sign-extends Rm frombyte → Rn

1—

EXTS.W Rm,Rn

0110nnnnmmmm1111

Sign-extends Rm fromword → Rn

1—

EXTU.B Rm,Rn

0110nnnnmmmm1100

Zero-extends Rm frombyte → Rn

1—

EXTU.W Rm,Rn

0110nnnnmmmm1101

Zero-extends Rm fromword → Rn

1

—

MOV

Rm,Rn

0110nnnnmmmm0011

Rm → Rn

1—

Notes:

1. The normal minimum number of execution states
2. SH-2 CPU instruction

HITACHI 269

Table A.32 Direct Register Addressing (cont)
Instruction

Code

Operation

State

T Bit

0000nnnnmmmm0111

Rn × Rm → MACL

2 to 4*1—0010nnnnmmmm1111

Signed, Rn × Rm → MAC

1 to 3*1—

MULU.W Rm,Rn

0010nnnnmmmm1110

Unsigned, Rn × Rm →MAC

1 to 3*1

—

NEG

Rm,Rn

0110nnnnmmmm1011

0 – Rm → Rn

1

—

NEGC

Rm,Rn

0110nnnnmmmm1010

0 – Rm – T → Rn, borrow→T1

Borrow

NOT

Rm,Rn

0110nnnnmmmm0111~Rm → Rn

1

—

OR

Rm,Rn

0010nnnnmmmm1011

Rn | Rm → Rn

1

—

SUB

Rm,Rn

0011nnnnmmmm1000

Rn – Rm → Rn

1

—

SUBC

Rm,Rn

0011nnnnmmmm1010

Rn – Rm – T → Rn,borrow → T

1

Borrow

SUBV

Rm,Rn

0011nnnnmmmm1011

Rn – Rm → Rn, underflow→T

1

Underflow

SWAP.B Rm,Rn

0110nnnnmmmm1000

Rm → Swap upper andlower halves of lower 2
bytes → Rn

1—

SWAP.W Rm,Rn

0110nnnnmmmm1001

Rm → Swap upper andlower word → Rn

1

—

TST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm, when result is
0, 1 → T

1

Test results

XOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm → Rn

1

—

XTRCT

Rm,Rn

0010nnnnmmmm1101

Center 32 bits of Rm and
Rn → Rn

1

—

MUL.L

Rm,Rn*2

MULS.W Rm,RnNotes: 1. The normal minimum number of execution cycles.
2. SH-2 CPU instructions

270 HITACHITable A.33 Indirect Register Addressing
Instruction

Code

Operation

State

T Bit

MOV.B

Rm,@Rn0010nnnnmmmm0000

Rm → (Rn)

1

—

MOV.W

Rm,@Rn0010nnnnmmmm0001

Rm → (Rn)

1

—

MOV.L

Rm,@Rn0010nnnnmmmm0010

Rm → (Rn)

1

—

MOV.B

@Rm,Rn0110nnnnmmmm0000(Rm) → sign extension → Rn 1

—

MOV.W

@Rm,Rn0110nnnnmmmm0001(Rm) → sign extension → Rn 1

—

MOV.L

@Rm,Rn0110nnnnmmmm0010(Rm) → Rn—

1

Table A.34 Post Increment Indirect Register (Multiply/Accumulate Operation)
Instruction

Code

Operation

State

T Bit

MAC.L

@Rm+,@Rn+* 20000nnnnmmmm1111

Signed, (Rn) × (Rm) +MAC → MAC

3/(2 to
4)* 1

—

MAC.W

@Rm+,@Rn+

0100nnnnmmmm1111

Signed, (Rn) × (Rm) +MAC → MAC

3/(2)*1—

Notes: 1. The normal minimum number of execution cycles.(The number in parentheses in thenumber of cycles when there is contention with preceding/following instructions).
2. SH-2 CPU instruction.

Table A.35 Post Increment Indirect Register
Instruction

Code

Operation

State

T Bit

MOV.B

@Rm+,Rn

0110nnnnmmmm0100(Rm) → sign extension →Rn, Rm + 1 → Rm

1

—

MOV.W

@Rm+,Rn

0110nnnnmmmm0101(Rm) → sign extension →Rn, Rm + 2 → Rm

1

—

MOV.L

@Rm+,Rn

0110nnnnmmmm0110(Rm) → Rn, Rm + 4 → Rm

1—

Table A.36 Pre Decrement Indirect Register
Instruction

Code

Operation

State

T Bit

MOV.B

Rm,@–Rn

0010nnnnmmmm0100

Rn – 1 → Rn, Rm → (Rn)

1

—

MOV.W

Rm,@–Rn

0010nnnnmmmm0101

Rn – 2 → Rn, Rm → (Rn)

1

—

MOV.L

Rm,@–Rn

0010nnnnmmmm0110

Rn – 4 → Rn, Rm → (Rn)

1—

HITACHI 271

Table A.37 Indirect Indexed Register
Instruction

Code

Operation

Cycles T Bit

MOV.B

Rm,@(R0,Rn)

0000nnnnmmmm0100

Rm → (R0 + Rn)

1

—

MOV.W

Rm,@(R0,Rn)

0000nnnnmmmm0101

Rm → (R0 + Rn)

1

—

MOV.L

Rm,@(R0,Rn)

0000nnnnmmmm0110

Rm → (R0 + Rn)

1

—

MOV.B

@(R0,Rm),Rn

0000nnnnmmmm1100(R0 + Rm) → signextension → Rn

1

—

MOV.W

@(R0,Rm),Rn

0000nnnnmmmm1101(R0 + Rm) → signextension → Rn

1

—

MOV.L

@(R0,Rm),Rn

0000nnnnmmmm1110(R0 + Rm) → Rn

1

—

A.2.5

md Format

Table A.38 md Format
Instruction

Code

Operation

State

T Bit

MOV.B

@(disp,Rm),R0

10000100mmmmdddd(disp + Rm) → signextension → R0

1

—

MOV.W

@(disp,Rm),R0

10000101mmmmdddd(disp × 2 + Rm) →sign extension →
R0

1

—

A.2.6

nd4 Format

Table A.39 nd4 Format
Instruction

Code

Operation

State

T Bit

MOV.B

R0,@(disp,Rn)

10000000nnnndddd

R0 → (disp + Rn)

1

—

MOV.W

R0,@(disp,Rn)

10000001nnnndddd

R0 → (disp × 2+ Rn)

1

—

A.2.7

nmd Format

Instruction

Code

Operation

State

T Bit

MOV.L

Rm,@(disp,Rn)

0001nnnnmmmmdddd

Rm → (disp × 4 + Rn)

1

—

MOV.L

@(disp,Rm),Rn

0101nnnnmmmmdddd(disp × 4+ Rm) → Rn

1—

Table A.40 nmd Format

272 HITACHIA.2.8d FormatTable A.41 Indirect GBR with Displacement
Instruction

Code

Operation

State

T Bit

MOV.B

R0,@(disp,GBR)

11000000ddddddddR0 → (disp + GBR)

1

—

MOV.W

R0,@(disp,GBR)

11000001ddddddddR0 → (disp × 2 +
GBR)

1

—

MOV.L

R0,@(disp,GBR)

11000010ddddddddR0 → (disp × 4 +
GBR)

1

—

MOV.B

@(disp,GBR),R0

11000100dddddddd(disp + GBR) → signextension → R0

1

—

MOV.W

@(disp,GBR),R0

11000101dddddddd(disp × 2 + GBR) →sign extension → R0

1

—

MOV.L

@(disp,GBR),R0

11000110dddddddd(disp × 4 + GBR) →
R0

1

—

Table A.42 PC Relative with Displacement
Instruction

Code

Operation

State

T Bit

MOVA

11000111dddddddd

disp × 4 + PC → R0

1—@(disp,PC),R0

Table A.43 PC Relative Addressing
Instruction
BF

label

BF/S

Code

Operation

State

T Bit

10001011dddddddd

When T = 0, disp × 2 + PC → PC;
When T = 1, nop

3/1*3

—

10001111dddddddd

When T = 0, disp × 2 + PC → PC;
When T = 1, nop

2/1*3

—

10001001dddddddd

When T = 1, disp × 2 + PC → PC;
When T = 0, nop

3/1*3

—

10001101dddddddd

When T = 1, disp × 2 + PC → PC;
When T = 0, nop

2/1*3

—

label
*2
BT

label

BT/S
label
*2

Notes: 2. SH-2 CPU instruction
3. One state when it does not branch

HITACHI 273

A.2.9d12 Format

Table A.44 d12 Format
Instruction

Code

Operation

State

T Bit

BRA

1010dddddddddddd

Delayed branch, disp × 2+ PC → PC

2—1011dddddddddddd

Delayed branching, PC → PR, disp ×
2 + PC → PC

2

—

labe
l
BSR
labe
l

A.2.10

nd8 Format

Table A.45 nd8 Format
Instruction

Code

Operation

State

T Bit

MOV.W

@(disp,PC),Rn

1001nnnndddddddd(disp × 2 + PC) → signextension → Rn

1

—

MOV.L

@(disp,PC),Rn

1101nnnndddddddd(disp × 4 + PC) → Rn

1—

A.2.11i FormatTable A.46 Indirect Indexed GBR Addressing
Instruction

Code

Operation

State

T Bit

AND.B

11001101iiiiiiii(R0 + GBR) & imm →(R0 + GBR)

3—

11001111iiiiiiii(R0 + GBR) | imm → (R0 3+ GBR)—#imm,@(R0,GBR)

OR.B#imm,@(R0,GBR)
TST.B#imm,@(R0,GBR)

11001100iiiiiiii(R0 + GBR) & imm,
when result is 0, 1 → T

3

Test
results

XOR.B#imm,@(R0,GBR)

11001110iiiiiiii(R0 + GBR) ^ imm →(R0 + GBR)

3—274 HITACHITable A.47 Immediate Addressing (Arithmetic Logical Operation with Direct Register)
Instruction

Code

Operation

State

T Bit

AND

#imm,R0

11001001iiiiiiii

R0 & imm → R0

1—

CMP/EQ #imm,R0

10001000iiiiiiii

When R0 = imm, 1 → T 1

Comparison
resultsOR#imm,R0

11001011iiiiiiii

R0 | imm → R0

1

—

TST

#imm,R0

11001000iiiiiiii

R0 & imm, when result
is 0, 1 → T

1Test results

XOR#imm,R0

11001010iiiiiiii

R0 ^ imm → R0

1—

Table A.48 Immediate Addressing (Specify Exception Processing Vector)
Instruction

Code

Operation

State

T Bit

TRAPA

#imm

11000011iiiiiiii

PC/SR → Stack area, (imm × 4 +VBR) → PC

8—

A.2.12ni Format

Table A.49 ni Format
Instruction

Code

Operation

State

T Bit

ADD

0111nnnniiiiiiii

Rn + imm → Rn

1—1110nnnniiiiiiii

imm → sign extension → Rn

1—

#imm,Rn
MOV#imm,RnHITACHI 275

A.3

Instruction Set in Order by Instruction Code

Table A.50 lists instruction codes and execution states in order by instruction code.
Table A.50 Instruction Set by Instruction CodeInstruction

Code

Operation

State

T Bit

CLRT

0000000000001000

0→T

1

0

NOP

0000000000001001

No operation

1

—

RTS

0000000000001011

Delayed branch, PR
→ PC

2

—

SETT

0000000000011000

1→T

1

1

DIV0U

0000000000011001

0 → M/Q/T

1

0276 HITACHITable A.50 Instruction Set by Instruction Code (cont)
Instruction

Code

Operation

State

T Bit

SLEEP

0000000000011011

Sleep

3

—

CLRMAC

0000000000101000

0 → MACH, MACL

1

—

RTE

0000000000101011

Delayed branch, stackarea → PC/SR

4

LSB

STC

SR,Rn

0000nnnn00000010

SR → Rn

1

—

BSRF

Rm*2

0000mmmm00000011

Delayed branch, PC→ PR, Rm + PC → PC

2

—

STS

MACH,Rn

0000nnnn00001010

MACH → Rn

1

—

STC

GBR,Rn

0000nnnn00010010

GBR → Rn

1

—

STS

MACL,Rn

0000nnnn00011010

MACL → Rn

1

—

STC

VBR,Rn

0000nnnn00100010

VBR → Rn

1

—

BRAF

Rm*2

0000mmmm00100011

Delayed branch, Rm +PC → PC

2

—

MOVT

Rn

0000nnnn00101001

T → Rn

1

—

STS

PR,Rn

0000nnnn00101010

PR → Rn

1

—

MOV.B

Rm,@(R0,Rn)

0000nnnnmmmm0100

Rm → (R0 + Rn)

1

—

MOV.W

Rm,@(R0,Rn)

0000nnnnmmmm0101

Rm → (R0 + Rn)

1

—

MOV.L

Rm,@(R0,Rn)

0000nnnnmmmm0110

Rm → (R0 + Rn)

1

—

MUL.L

Rm,Rn*20000nnnnmmmm0111

Rn x Rm → MACL

2
(to 4)* 1

—

MOV.B

@(R0,Rm),Rn

0000nnnnmmmm1100(R0 + Rm) → signextension → Rn

1

—

MOV.W

@(R0,Rm),Rn

0000nnnnmmmm1101(R0 + Rm) → signextension → Rn

1

—

MOV.L

@(R0,Rm),Rn

0000nnnnmmmm1110(R0 + Rm) → Rn

1

—

MAC.L

@Rm+,@Rn+* 20000nnnnmmmm1111

Signed, (Rn) x (Rm) +MAC → MAC

3/ (2to 4)* 1—

MOV.L

Rm,@(disp,Rn)

0001nnnnmmmmdddd

Rm → (disp × 4 + Rn)

1

—

MOV.B

Rm,@Rn0010nnnnmmmm0000

Rm → (Rn)

1

—

MOV.W

Rm,@Rn0010nnnnmmmm0001

Rm → (Rn)1—

Notes: 1. The normal minimum number of execution states (The number in parentheses is thenumber of states when there is contention with preceding/following instructions)
2. SH-2 CPU instruction

HITACHI 277

Table A.50 Instruction Set by Instruction Code (cont)
Instruction

Code

Operation

State

T Bit

MOV.L

Rm,@Rn0010nnnnmmmm0010

Rm → (Rn)

1

—

MOV.B

Rm,@-Rn

0010nnnnmmmm0100

Rn – 1 → Rn, Rm →
(Rn)

1

—

MOV.W

Rm,@–Rn

0010nnnnmmmm0101

Rn – 2 → Rn, Rm →
(Rn)

1

—

MOV.L

Rm,@–Rn

0010nnnnmmmm0110

Rn – 4 → Rn, Rm →
(Rn)

1

—

DIV0S

Rm,Rn

0010nnnnmmmm0111

MSB of Rn → Q,
MSB of Rm → M, M ^Q→ T1

Calculation
resultTST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm, when result
is 0, 1 → T

1Test results

AND

Rm,Rn

0010nnnnmmmm1001

Rn & Rm → Rn

1

—

XOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm → Rn

1

—

OR

Rm,Rn

0010nnnnmmmm1011

Rn | Rm → Rn

1—

CMP/STR
Rm,Rn

0010nnnnmmmm1100

When a byte in Rn
equals a byte in Rm, 1→T

1

Comparison
result

XTRCT

Rm,Rn

0010nnnnmmmm1101

Center 32 bits of Rm
and Rn → Rn

1—

MULU.W Rm,Rn

0010nnnnmmmm1110

Unsigned, Rn × Rm → 1 to 3*1
MAC—

MULS.W Rm,Rn

0010nnnnmmmm1111

Signed, Rn × Rm →MAC—

CMP/EQ Rm,Rn

0011nnnnmmmm0000

When Rn = Rm, 1 → T 1

Comparison
result

CMP/HS Rm,Rn

0011nnnnmmmm0010

When unsigned andRn ≥ Rm, 1 → T

1Comparison
result

CMP/GE Rm,Rn

0011nnnnmmmm0011

When signed and Rn≥ Rm, 1 → T

1Comparison
resultDIV10011nnnnmmmm0100

1-step division (Rn ÷Rm)1

Calculation
result0011nnnnmmmm0101

Unsigned, Rn x Rm →MACH, MACL

2 to 4*1—

Rm,Rn

DMULU.L
Rm,Rn*2

Notes: 1. The normal minimum number of execution states
2. SH-2 CPU instruction

278 HITACHI

1 to 3*1

Table A.50 Instruction Set by Instruction Code (cont)
Instruction

Code

Operation

State

T Bit

CMP/HI Rm,Rn

0011nnnnmmmm0110

When unsigned
and Rn > Rm, 1→T

1

Comparison
result

CMP/GT Rm,Rn

0011nnnnmmmm0111

When signed and
Rn > Rm, 1 → T

1Comparison
resultSUB

Rm,Rn

0011nnnnmmmm1000

Rn – Rm → Rn

1

—

SUBC

Rm,Rn

0011nnnnmmmm1010

Rn – Rm – T →Rn, borrow → T

1

Borrow

SUBV

Rm,Rn

0011nnnnmmmm1011

Rn – Rm → Rn,
underflow → T

1

Underflow

ADD

Rm,Rn

0011nnnnmmmm1100

Rm + Rn → Rn

1—0011nnnnmmmm1101

Signed, Rn x Rm
→ MACH, MACL

2 to 4*1—

DMULS.L

Rm,Rn*2

ADDC

Rm,Rn

0011nnnnmmmm1110

Rn + Rm + T →Rn, carry → T

1

Carry

ADDV

Rm,Rn

0011nnnnmmmm1111

Rn + Rm → Rn,
overflow → T

1

OverflowSHLL

Rn

0100nnnn00000000

T ← Rn ← 0

1

MSB

SHLR

Rn

0100nnnn00000001

0 → Rn → T

1

LSB

STS.L

MACH,@–Rn

0100nnnn00000010

Rn – 4 → Rn,
MACH → (Rn)

1

—

STC.L

SR,@-Rn

0100nnnn00000011

Rn – 4 → Rn, SR→ (Rn)

2

—

ROTL

Rn

0100nnnn00000100

T ← Rn ← MSB

1

MSB

ROTR

Rn

0100nnnn00000101

LSB → Rn → T

1

LSB

LDS.L

@Rm+,MACH

0100mmmm00000110(Rm) → MACH,
Rm + 4 → Rm

1

—

LDC.L

@Rm+,SR

0100mmmm00000111(Rm) → SR, Rm + 3
4 → Rm

LSB

SHLL2

Rn

0100nnnn00001000

Rn<<2 → Rn

1

—

SHLR2

Rn

0100nnnn00001001

Rn>>2 → Rn

1

—

LDS

Rm,MACH

0100mmmm00001010

Rm → MACH

1—

Notes: 1. The normal minimum number of execution states
2. SH-2 CPU instruction

HITACHI 279

Table A.50 Instruction Set by Instruction Code (cont)
Instruction

Code

Operation

State

T Bit

JSR

@Rm

0100mmmm00001011

Delayed branch, PC→ PR, Rm → PC

2

—

LDC

Rm,SR

0100mmmm00001110

Rm → SR

1

LSB

DT

Rn*2

0100nnnn00010000

Rn - 1 → Rn; if Rn is0, 1 → T, if Rn is
nonzero, 0 → T

1Comparison
result

CMP/PZ Rn

0100nnnn00010001

Rn ≥ 0, 1 → T

1Comparison
resultSTS.L

MACL,@–Rn

0100nnnn00010010

Rn – 4 → Rn, MACL
→ (Rn)

1

—

STC.L

GBR,@-Rn

0100nnnn00010011

Rn – 4 → Rn, GBR →
(Rn)

2

—

CMP/PL Rn

0100nnnn00010101

Rn > 0, 1 → T

1Comparison
resultLDS.L@Rm+,MACL

0100mmmm00010110(Rm) → MACL, Rm +4 → Rm

1

—

LDC.L

@Rm+,GBR

0100mmmm00010111(Rm) → GBR, Rm + 4
→ Rm

3

—

SHLL8

Rn

0100nnnn00011000

Rn<<8 → Rn

1

—

SHLR8

Rn

0100nnnn00011001

Rn>>8 → Rn

1

—

LDS

Rm,MACL

0100mmmm00011010

Rm → MACL

1

—

TAS.B

@Rn

0100nnnn00011011

When (Rn) is 0, 1 →T, 1 → MSB of (Rn)4

Test results

LDC

Rm,GBR

0100mmmm00011110

Rm → GBR

1

—

SHAL

Rn

0100nnnn00100000

T ← Rn ← 0

1

MSB

SHAR

Rn

0100nnnn00100001

MSB → Rn → T

1

LSB

STS.L

PR,@–Rn

0100nnnn00100010

Rn – 4 → Rn, PR →
(Rn)

1

—

STC.L

VBR,@-Rn

0100nnnn00100011

Rn – 4 → Rn, VBR →
(Rn)

2

—

ROTCL

Rn

0100nnnn00100100

T ← Rn ← T

1

MSB

ROTCR

Rn

0100nnnn00100101

T → Rn → T

1

LSB

LDS.L

@Rm+,PR

0100mmmm00100110(Rm) → PR, Rm + 4 →
Rm

1

—

LDC.L

@Rm+,VBR

0100mmmm00100111(Rm) → VBR, Rm + 4
→ Rm

3

—

Notes:

2. SH-2 CPU instruction

280 HITACHITable A.50 Instruction Set by Instruction Code (cont)
Instruction

Code

Operation

State

T Bit

SHLL16 R n

0100nnnn00101000

Rn<<16 → Rn

1—

SHLR16 R n

0100nnnn00101001

Rn>>16 → Rn

1

—

LDS

Rm,PR

0100mmmm00101010

Rm → PR

1

—

JMP

@Rm

0100mmmm00101011

Delayed branch, Rm
→ PC

2

—

LDC

Rm,VBR

0100mmmm00101110

Rm → VBR

1

—
—

MAC.W

@Rm+,@Rn+

0100nnnnmmmm1111

Signed, (Rn) × (Rm)
+ MAC → MAC

3/(2)*1

MOV.L@(disp,Rm),Rn

0101nnnnmmmmdddd(disp + Rm) → Rn

1

—

MOV.B

@Rm,Rn0110nnnnmmmm0000(Rm) → signextension → Rn

1

—

MOV.W

@Rm,Rn0110nnnnmmmm0001(Rm) → signextension → Rn

1

—

MOV.L

@Rm,Rn0110nnnnmmmm0010(Rm) → Rn

1

—

MOV

Rm,Rn

0110nnnnmmmm0011

Rm → Rn

1

—

MOV.B

@Rm+,Rn

0110nnnnmmmm0100(Rm) → signextension → Rn, Rm+ 1 → Rm

1

—

MOV.W

@Rm+,Rn

0110nnnnmmmm0101(Rm) → signextension → Rn, Rm+ 2 → Rm

1

—

MOV.L

@Rm+,Rn

0110nnnnmmmm0110(Rm) → Rn, Rm + 4
→ Rm

1

—

NOT

Rm,Rn

0110nnnnmmmm0111~Rm → Rn

1—

SWAP.B Rm,Rn

0110nnnnmmmm1000

Rm → Swap upperand lower halves oflower 2 bytes → Rn

1—

SWAP.W Rm,Rn

0110nnnnmmmm1001

Rm → Swap upperand lower word →
Rn

1

—

NEGC

Rm,Rn

0110nnnnmmmm1010

0 – Rm – T → Rn,borrow → T

1

Borrow

NEG

Rm,Rn

0110nnnnmmmm1011

0 – Rm → Rn

1—

Notes: 1

The normal minimum number of execution states (The number in parentheses is thenumber in contention with preceding/following instructions)

HITACHI 281

Table A.50 Instruction Set by Instruction Code (cont)
Instruction

Code

Operation

State

EXTU.B Rm,Rn

0110nnnnmmmm1100

Zero-extends Rmfrom byte → Rn

1—

EXTU.W Rm,Rn

0110nnnnmmmm1101

Zero-extends Rmfrom word → Rn

1—

EXTS.B Rm,Rn

0110nnnnmmmm1110

Sign-extends Rmfrom byte → Rn

1—

EXTS.W Rm,Rn

0110nnnnmmmm1111

Sign-extends Rmfrom word → Rn

1

—

ADD

#imm,Rn

0111nnnniiiiiiii

Rn + imm → Rn

1

—

MOV.B

R0,@(disp,Rn)

10000000nnnndddd

R0 → (disp + Rn)

1

—

MOV.W

R0,@(disp,Rn)

10000001nnnndddd

R0 → (disp × 2 +
Rn)

1

—

MOV.B

@(disp,Rm),R0

10000100mmmmdddd(disp + Rm) → signextension → R0

1

—

MOV.W

@(disp,Rm),R0

10000101mmmmdddd(disp × 2 + Rm) →sign extension →
R0

1

—

CMP/EQ #imm,R0

10001000iiiiiiii

When R0 = imm, 1→T

1Comparison results

BT

label

10001001dddddddd

When T = 1, disp ×
2 + PC → PC;
When T = 0, nop.

3/1*3

—

BT/S

label*

10001101dddddddd

When T = 1, disp ×
2 + PC → PC;
When T = 1, nop.

2/1*3

—

BF

label

10001011dddddddd

When T = 0, disp ×
2 + PC → PC;
When T = 0, nop

3/1*3

—

BF/S

label*

10001111dddddddd

When T = 0, disp ×
2 + PC → PC;
When T = 1, nop

2/1*3

—

MOV.W

@(disp,PC),Rn

1001nnnndddddddd(disp × 2 + PC) →sign extension →
Rn

1

—

BRA

label

1010dddddddddddd

Delayed branch,disp × 2 + PC →
PC

2

—

Notes: 2. SH-2 CPU instruction
3. One state when it does not branch

282 HITACHIT Bit

Table A.50 Instruction Set by Instruction Code (cont)
Instruction

Code

BSR

label

MOV.B

Operation

State

T Bit

1011dddddddddddd Delayed branch, PC →PR, disp × 2 + PC → PC

2—

R0,@(disp,GBR)

11000000dddddddd R0 → (disp + GBR)

1

—

MOV.W

R0,@(disp,GBR)

11000001dddddddd R0 → (disp × 2 + GBR)

1

—

MOV.L

R0,@(disp,GBR)

11000010dddddddd R0 → (disp × 4 + GBR)

1

—

TRAPA

#imm

11000011iiiiiiii PC/SR → Stack area,(imm × 4 + VBR) → PC

8

—

MOV.B

@(disp,GBR),R0

11000100dddddddd (disp + GBR) → signextension → R0

1

—

MOV.W

@(disp,GBR),R0

11000101dddddddd (disp × 2 + GBR) → signextension → R0

1

—

MOV.L

@(disp,GBR),R0

11000110dddddddd (disp × 4 + GBR) → R0

1

—

MOVA

@(disp,PC),R0

11000111dddddddd disp × 4 + PC → R0

1

—

TST

#imm,R0

11001000iiiiiiii R0 & imm, when result is
0, 1 → T1

Test
resultsAND#imm,R0

11001001iiiiiiii R0 & imm → R0

1

—

XOR

#imm,R0

11001010iiiiiiii R0 ^ imm → R0

1

—

OR

#imm,R0

11001011iiiiiiii R0 | imm → R0

1

—

TST.B

#imm,@(R0,GBR)

11001100iiiiiiii (R0 + GBR) & imm, whenresult is 0, 1 → T

3

Test
results

AND.B#imm,@(R0,GBR)

11001101iiiiiiii (R0 + GBR) & imm → (R0+ GBR)

3

—

XOR.B

#imm,@(R0,GBR)

11001110iiiiiiii (R0 + GBR) ^ imm → (R0+ GBR)

3—

OR.B#imm,@(R0,GBR)

11001111iiiiiiii (R0 + GBR) | imm → (R0 + 3
GBR)

—

MOV.L

@(disp,PC),Rn

1101nnnndddddddd (disp × 4 + PC) → Rn

1

—

MOV

#imm,Rn

1110nnnniiiiiiii imm → sign extension →
Rn

1

—

HITACHI 283

A.4

Operation Code Map

Table A.51 is an operation code map.
Table A.51 Operation Code Map
Instruction CodeMSB

Fx: 0000
LSB MD: 00

Fx: 0001

Fx: 0010

Fx: 0011–1111

MD: 01

MD: 10

MD: 110000 Rn

Fx

0000

0000 Rn

Fx

0001

0000 Rn

Fx

0010 STC

SR,Rn* STC

0000 Rm

Fx

0011 BSRF

Rm*

0000 Rn

Rm

01MD MOV.B
Rm,@(R0,Rn)

MOV.W
Rm,@(R0,Rn)

MOV.L
Rm,@(R0,Rn)

0000 0000 Fx

1000 CLRTSETT

CLRMAC

0000 0000 Fx

1001 NOP

DIV0U

0000 0000 Fx

1010

0000 0000 Fx

1011 RTS

0000 Rn

Fx

1000

0000 Rn

Fx

1001

0000 Rn

Fx

1010 STS MACH,Rn

0000 Rn

Fx

1011

0000 Rn

Fx

11MD MOV.B@(R0,Rm),Rn

0001 RnRm

disp0010 Rn

Rm

00MD MOV.B

0010 Rn

Rm

01MD MOV.B
Rm,@-Rn

MOV.W
Rm,@-Rn

MOV.L
Rm,@-Rn

0010 Rn

Rm

10MD TST

AND

Rm,Rn

XOR

0010 Rn

Rm

11MD CMP/STR
Rm,Rn

XTRCT

Rm,Rn

MULU.W Rm,Rn MULS.W Rm,Rn

0011 Rn

Rm

00MD CMP/EQ Rm,Rn

0011 Rn

Rm

01MD DIV1

Rm,Rn

0011 Rn

Rm

10MD SUB

Rm,Rn

0011 Rn

Rm

11MD ADD

Rm,Rn

0100 Rn

Fx

0000 SHLL

Rn

284 HITACHI

MOV.L

GBR,Rn STC
BRAF

SLEEP

VBR,RnRm*
MUL.L
Rm,Rn*

RTE

MOVT

Rn

STS MACL,Rn

STS

PR,Rn

MOV.W
@(R0,Rm),Rn

MOV.L@(R0,Rm),Rn

MAC.L@Rm+,@Rn+*

Rm,@(disp:4,Rn)
Rm,@Rn MOV.W

Rm,Rn

Rm,@Rn MOV.L

Rm,@RnDIV0S

Rm,Rn O R

Rm,Rn
Rm,Rn

CMP/HS Rm,Rn CMP/GE Rm,Rn
DMULU.L
Rm,Rn*

CMP/HI Rm,Rn CMP/GT Rm,Rn
SUBC

Rm,Rn SUBVRm,Rn

DMULS.L
Rm,Rn*ADDC

Rm,Rn ADDV

Rm,Rn

DT

SHAL

Rn

Rn*

HITACHI 285

Table A.51 Operation Code Map (cont)
Instruction CodeMSB

Fx: 0000
LSB MD: 00

Fx: 0001

Fx: 0010

Fx: 0011–1111

MD: 01

MD: 10

MD: 110100 Rn

Fx

0001 SHLR

Rn

CMP/PZ Rn

SHAR0100 Rn

Fx

0010 STS.L
MACH,@–Rn

STS.L
MACL,@–Rn

STS.L
PR,@–Rn

0100 Rn

Fx

0011 STC.L
SR,@–Rn

STC.L
GBR,@–Rn

STC.L
VBR,@–Rn

0100 Rn

Fx

0100 ROTL

Rn

0100 Rn

Fx

0101 ROTR

Rn

0100 Rm

Fx

0100 Rm

Rn

ROTCL

Rn

CMP/PL Rn

ROTCR

Rn

0110 LDS.L@Rm+,MACH

LDS.L@Rm+,MACL

LDS.L@Rm+,PR

Fx

0111 LDC.L@Rm+,SR

LDC.L@Rm+,GBR

LDC.L@Rm+,VBR

0100 Rn

Fx

1000 SHLL2

Rn

SHLL8

Rn

SHLL16 Rn

0100 Rn

Fx

1001 SHLR2

Rn

SHLR8

Rn

SHLR16 Rn

0100 Rm

Fx

1010 LDS

0100 Rm/
Rn

Fx

1011 JSR

0100 Rm

Fx

1100

0100 Rm

Fx

1101

0100 Rn

Fx

0100 Rn

Rm,MACH LDS

Rm,MACL LDS

Rm,PR
@Rm

@Rm

TAS.B

@Rn

1110 LDC

Rm,SR

LDC

Rm,GBR LDC

Rm

1111 MAC.W@Rm+,@Rn+

0101 RnRm

disp@(disp:4,Rm),Rn

0110 Rn

Rm

00MD MOV.B

Rm,Rn

MOV.W

@Rm,Rn MOV.L@Rm,Rn MOV

Rm,Rn

0110 Rn

Rm

01MD MOV.B

Rm+,Rn MOV.W@Rm+,Rn MOV.L@Rm+,Rn NOT

Rm,Rn

0110 Rn

Rm

10MD SWAP.B
Rm,Rn

SWAP.W
Rm,Rn

NEGC

Rm,Rn

Rm,Rn

0110 Rn

Rm

11MD EXTU.B Rm,Rn

EXTU.W Rm,Rn

EXTS.B Rm,Rn

0111 Rn

imm

MOV.L

ADD

disp

MOV.B R0,@(disp:4,Rn)

MOV.W R0,@(disp:4,Rn)

1000 01MD Rm

disp

MOV.B
@(disp:4,
Rm),R0

MOV.W@(disp:4,
Rm),R0

imm/disp

CMP/EQ#imm:8,R0BT

286 HITACHIRm,VBR

NEG

EXTS.W Rm,Rn#imm:8,Rn

1000 00MD Rn

1000 10MD

JMP

label:8

BF

label:8

Table A.51 Operation Code Map (cont)
Instruction CodeMSB

Fx: 0000
LSB MD: 00

1000 11MD

imm/disp

1001 Rndisp

Fx: 0001

Fx: 0010

Fx: 0011–1111

MD: 01

MD: 10

MD: 11

BT/Slabel:8*

BF/Slabel:8*

MOV.W @(disp:8,PC),Rn

1010

disp

BRA

label:12

1011

disp

BSR

label:121100 00MD

imm/disp

MOV.B R0,@(disp:8,
GBR)

MOV.W R0,@(disp:8,
GBR)

MOV.L R0,@(disp:8,
GBR)

TRAPA

1100 01MD

disp

MOV.B
@(disp:8,
GBR),R0

MOV.W@(disp:8,
GBR),R0

MOV.L@(disp:8,
GBR),R0

MOVA@(disp:8,
PC),R01100 10MD

imm

TST#imm:8,R0

AND#imm:8,R0

XOR#imm:8,R0

OR#imm:8,R0

1100 11MD

imm

TST.B
#imm:8,@(R0,GBR)

AND.B#imm:8,@(R0,GBR)

XOR.B#imm:8,@(R0,GBR)

OR.B#imm:8,@(R0,GBR)

1101 Rn

disp

MOV.L

@(disp:8,PC),R0

1110 Rn

imm

MOV#imm:8,Rn

1111
Note:

#imm:8...
SH-2 CPU instructions

HITACHI 287

Appendix B

Pipeline Operation and Contention

The SH-1 and SH-2 CPU is designed so that basic instructions are executed in one state. Two
or more states are required for instructions when, for example, the branch destination address
is changed by a branch instruction or when the number of states is increased by contention
between MA and IF. Table B.1 gives the number of execution states and stages for different
types of contention and their instructions. Instructions without contention and instructions that
require 2 or more cycles even without contention are also shown.
Instructions experience contention in the following ways:• Operations and transfers between registers are executed in one state with no contention.
• No contention occurs, but the instruction still requires 2 or more cycles.
• Contention occurs, increasing the number of execution states. Contention combinations
are as follows: MA contends with IF
 MA contends with IF and sometimes with memory loads as well
 MA contends with IF and sometimes with the multiplier as well
 MA contends with IF and sometimes with memory loads and sometimes with themultiplier288 HITACHITable B.1

Instructions and Their Contention Patterns

Contention

State

Stage

Instruction

None

1

3

Transfer between registers
Operation between registers (except
multiplication instruction)
Logical operation between registers
Shift instruction
System control ALU instruction

2

3

Unconditional branch

3/1*3

3

Conditional branch

3

3

SLEEP instruction

4

5

RTE instruction

89

TRAP instruction

1

4

Memory store instruction and STS.L
instruction (PR)2

4

STC.L instruction

3

6

Memory logic operations

4

6

TAS instruction

MA contends with IF andsometimes with memory loads as
well

1

5

Memory load instructions and LDS.L
instruction (PR)35

LDC.L instruction

MA contends with IF andsometimes with the multiplier as
well

1

4

Register to MAC transfer instruction,
memory to MAC transfer instruction and
MAC to memory transfer instruction

1 to 3*2

6/7*1

Multiplication instruction

3/(2)*2

7/8*1

Multiply/accumulate instruction

3/(2 to4)* 2

9

Double-length multiply/accumulate
instruction (SH-2 only)

2 to 4*2

9

Double-length multiplication instruction(SH-2 only)

5

MAC to register transfer instruction

MA contends with IF

MA contends with IF and1sometimes with memory loads
and sometimes with the multiplierNotes: 1. With the SH-2 CPU, multiply/accumulate instructions are 7 stages and multiplication
instructions are 6 stages, while with the SH-1 CPU, multiply/accumulate instructionsare 8 stages and multiplication instructions are 7 stages.
2. The normal minimum number of execution states (The number in parentheses is thenumber in contention with preceding/following instructions).
3. One stage when it does not branch.

HITACHI 289