When using this document, keep the following in mind:ntialGeneral Notice

1. This document is confidential. By accepting this document you acknowledge that you are boundby the terms set forth in the non-disclosure and confidentiality agreement signed separately and /inthe possession of SEGA. If you have not signed such a non-disclosure agreement, please contact
SEGA immediately and return this document to SEGA.

de2. This document may include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new versions of the
document. SEGA may make improvements and/or changes in the product(s) and/or the
program(s) described in this document at any time.

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3. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without SEGA’S written permission. Request for copies of this document and for technicalinformation about SEGA products must be made to your authorized SEGA Technical Services
representative.

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4. No license is granted by implication or otherwise under any patents, copyrights, trademarks, orother intellectual property rights of SEGA Enterprises, Ltd., SEGA of America, Inc., or any third
party.
5. Software, circuitry, and other examples described herein are meant merely to indicate the characteristics and performance of SEGA’s products. SEGA assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples
describe herein.

GA

6. It is possible that this document may contain reference to, or information about, SEGA products(development hardware/software) or services that are not provided in countries other than Japan.
Such references/information must not be construed to mean that SEGA intends to provide such
SEGA products or services in countries other than Japan. Any reference of a SEGA licensed product/program in this document is not intended to state or simply that you can use only SEGA’slicensed products/programs. Any functionally equivalent hardware/software can be used instead.
7. SEGA will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s equipment, or programs according to this document.

SE

NOTE: A reader's comment/correction form is provided with thisdocument. Please address comments to :(6/27/95- 002)

SEGA of America, Inc., Developer Technical Support (att. Evelyn Merritt)
150 Shoreline Drive, Redwood City, CA 94065
SEGA may use or distribute whatever information you supply in any way
it believes appropriate without incurring any obligation to you.

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TM

SCU
User's Manual
Third version
Doc. # ST-97-R5-072694© 1994 SEGA. All Rights Reserved.

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READER CORRECTION/COMMENT SHEETKeep us updated!
If you should come across any incorrect or outdated information while reading through the attacheddocument, or come up with any questions or comments, please let us know so that we can make therequired changes in subsequent revisions. Simply fill out all information below and return this form to
the Developer Technical Support Manager at the address below. Please make more copies of this form if
more space is needed. Thank you.
General Information:

Phone

Document number
Document namedeYour Name

Date

ST-97-R5-072694
SCU User's ManualCorrections:
Correction

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pg. #

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Chpt.

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Questions/comments:

Fax:

Where to send your corrections:(415) 802-3963
Attn: Manager,
Developer Technical Support

Mail:

SEGA OF AMERICA
Attn: Manager,
Developer Technical Support
275 Shoreline Dr. Ste 500
Redwood City, CA 94065

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REFERENCES

KenKyusha New Japanese-English Dictionary
1974 Edition

2.

Nelson’s Japanese-English Character Dictionary
2nd revised version

3.

Microsoft Computer Dictionary

4.

Japanese-English Computer Terms Dictionary
Nichigai Associates
4th version

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1.

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In translating/creating this document, certain technical words and/or phrases were interpretedwith the assistance of the technical literature listed below.

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Version History
April 7, 1994
• New draft

Version 2:

May 31, 1994
• Revisions according to April 28, 1994 meeting

Version 3:

July 15, 1994
• Revisions requested on June 30 and July 11, 1994

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Version 1:

IntroductionntialThis manual explains functions of the system controller and how they are used. The system
controller transfers data rapidly and smoothly by means of the bus controls.
Explanation of Terms
The following terms are used in this manual.

System Control Unit. The SCU contains the CPU I/F, A-Bus IF, B-BUS I/F, andsmoothly effects data transfers between several processors connected throughtheir respective I/F and bus. It also internally houses the DMA controller,
interrupt controller, and DSP, and makes possible rapid DMA control, interrupt
control, and processing of operations.

Main CPU

Uses a RISC type CPU SH2 that controls the overall system. SH2 contains 32-bit
internal and external buses.

VDP1

Video Display Processor 1. Functions include character and line painting, color
indication, Gouraud Shading color operations, screen output coordinate indication, and frame buffer display control.

VDP2

Video Display Processor 2. Functions include scrolling the screen up/down/
left/right, rotating the screen, determining priority order of multiple screens, anda priority function that controls the image process of color operations and color
offset.

SCSPAcronym for Saturn Custom Sound Processor. This is a sound source LSI for
multi-functional games that combines a PCM sound source and sound used forthe DSP.

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SCU

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System Manager and Peripheral Control. Has the functions of managing system
resets, control of interfacing with output devices (control pads, mouse, etc.), time
display by a real time clock, and battery backup.

Data

A bit is the smallest unit for expressing 1 or 0. 8 bits is a byte. 16 bits (or 2 bytes)
is a word. 32 bits (or 4 bytes) is a 9 long word.

A_Bus

Bus that connects external devices such as a ROM cassette or CD.

B_Bus

Bus that connects VDP1, VDP2, and SCSP.

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SMPC

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Manual Notations

ntialThis manual contains the following notations.

Represented by “B” at the end as in 100B. However, “B” may be omitted
for 1 bit.

Hexadecimal

Represented by H at the end as in 00H and FFH.

Unit

1 KByte is 1,024 bytes. 1 Mbit is 1,048,576 bits.

MSB, LSB

The configuration of byte and word shows at the left the high order bit(MSB, most significant bit), and atthe right the low order bit (LSB, leastsignificant bit).

Undefined Bit

A bit not defined by an instruction word is represented by “—”(R)

Represents read only data.

(W)

Represents write only data.

(R/W)

Represents data that can be read and written.

++

Shows increments. For example, when the CT0 register is incremented, it
is shown as CT0++.

x=2-0This indicates that 3 types exist, 2,1, and 0. For example, DxR26-0[x=2-0]
in the read address in section 3.2 “DMA Control Register” means that
D2R26-0, D1R26-0, and D0R26-0 exist. Similarly, D2R26-0 indicates that
D2R26 ~ D2R0 exist.

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Binary

iii

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CONTENTSINTRODUCTION

Explanation of Terms .............................................................................. (i)Manual Notations .................................................................................. (iii)

List of Figures ................................................................................ (vii)

List of Tables .................................................................................... (x)de

CHAPTER 1 OVERVIEW .......................................................................... 1
1.1 SCU Overview ........................................................................ 2
System Diagram ............................................................................. 2
Block Diagram ................................................................................ 3nfi

1.2 SCU Mapping ......................................................................... 4
Operation of Cache Hit ................................................................... 5

1.3 SCU Register Map ................................................................. 7
Level 2-0DMA Set Register ........................................................... 8DMA Forced-Stop Register ........................................................... 8Co

DMA Status Register ......................................................................9DSP Program Control Port ............................................................ 9
DSP Program RAM Data Port ..................................................... 10
DSP Data RAM Address Port ...................................................... 10
DSP Data RAM Data Port ............................................................ 10
Timer 0 Compare Register ........................................................... 11GA

Timer 1 Set Data Register ............................................................ 11
Timer 1 Mode Register ................................................................. 11Interrupt Mask Register ................................................................ 12Interrupt Status Register ...............................................................12
A-Bus Interrupt Acknowledge Register ........................................ 12
A-Bus Set Register ....................................................................... 13SE

A-Bus Refresh Register ................................................................ 13
SCU SDRAM Select Register ...................................................... 14
SCU Version Register ................................................................... 14iv

CHAPTER 2 OPERATION ............................................................... 15
2.1 DMA Transfer ....................................................................... 16nti
alBasic Operation of DMA ...............................................................16

DMA Mode.................................................................................... 18
Example of a Specific Use ............................................................ 21

2.2 Interrupt Control .................................................................. 27
Blanking Interrupt ......................................................................... 29

Timer Interrupt .............................................................................. 30
DSP-End Interrupt ........................................................................ 33

deSound-Request Interrupt .............................................................. 33
SMPC Interrupt ............................................................................. 33

PAD Interrupt ................................................................................ 33
DMA End Interrupt ........................................................................ 33
DMA-Illegal Interrupt ..................................................................... 33

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Sprite Draw End Interrupt .............................................................33

2.3 DSP ....................................................................................... 34
DSP Control from the Main CPU ................................................. 34

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CHAPTER 3 REGISTERS ............................................................... 39
3.1 Register List ......................................................................... 40
3.2 DMA Control Registers ....................................................... 41
Level 2-0 DMA Set Register ........................................................ 41
DMA Mode, Address Update, Start Factor Select Register ......... 46
DMA Force-Stop Register ............................................................ 47
DMA Status Register ....................................................................47

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3.3 DSP Control Ports ............................................................... 51
DSP Program Control Port .......................................................... 51
DSP Program RAM Data Port ..................................................... 53
DSP Data RAM Address Port ...................................................... 53
DSP Data RAM Data Port ............................................................ 54

3.4 Timer Registers ................................................................... 55

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Timer 0 Compare Register .......................................................... 55
Timer 1 Set Data Register ............................................................ 55
Timer 1 Mode Register ................................................................. 56v

3.5 Interrupt Control Registers ..................................................... 57ntialInterrupt Mask Register ................................................................ 57
Interrupt Status Register ...............................................................58

3.6 A-Bus Control Registers .......................................................... 61

A-Bus Interrupt Acknowledge Register ........................................ 61
A-Bus Set Register ...................................................................... 62

A-Bus Refresh Register ................................................................ 72

3.7 SCU Control Registers .............................................................. 73
SCU SDRAM Select Register ...................................................... 73

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SCU Version Register ................................................................... 73

CHAPTER 4 DSP CONTROL .......................................................... 75
4.1 DSP Internal BLOCK MAP .................................................. 76
4.2 List of Commands ..................................................................... 80

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4.3 Operand Execution Methods .............................................. 85
Jump Command Execution ......................................................... 85
Loop Command Execution .......................................................... 86
DMA Command Execution .......................................................... 87

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End Command Execution .............................................................88

4.4 Special Process Execution ..................................................... 89
Loading a Program by the DMA Command ................................. 89
Repeating One Command ............................................................ 89
Executing a Subroutine Program ................................................. 90

4.5 More About Commands ............................................................ 91

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Operation Commands .................................................................. 91
Load Immediate Command ....................................................... 120
DMA Command .......................................................................... 132
Jump Commands ....................................................................... 141
Loop Bottom Commands ............................................................ 153

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END Command .......................................................................... 156

vi

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List of Figures(Chapter 1 Overview)

Figure 1.1 Diagram of System .................................................................................... 2
Figure 1.2 Block Diagram ........................................................................................... 3

Figure 1.3 SCU Mapping (Cache_address) ............................................................. 4

Figure 1.4 Explanation of Cache Hit Operation ........................................................ 5
Figure 1.5 SCU Mapping (Cache_through_address) ................................................. 6
Figure 1.6 SCU Register Map .................................................................................... 7

deFigure 1.7 Level 2-0 DMA Set Register Map ............................................................. 8
Figure 1.8 DMA Force-Stop Register Map .................................................................8
Figure 1.9 DMA Status Register Map ......................................................................... 9
Figure 1.10 DSP Program Control Port Map ............................................................. 9

Figure 1.11 DSP Program RAM Data Port Map ....................................................... 10

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Figure 1.12 DSP Data RAM Address Port Map ....................................................... 10
Figure 1.13 DSP Data RAM Data Port Map .............................................................10
Figure 1.14 Timer 0 Compare Register Map ............................................................ 11
Figure 1.15 Timer 1 Set Data Register Map ............................................................. 11

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Figure 1.16 Timer 1 Mode Register Map .................................................................. 11
Figure 1.17 Interrupt Mask Register Map ................................................................. 12
Figure 1.18 Interrupt Status Register Map ................................................................ 12
Figure 1.19 A-Bus Interrupt Acknowledge Map ....................................................... 12
Figure 1.20 A-Bus Set Register Map.................................................................. 13

Figure 1.21 A-Bus Refresh Register Map ................................................................. 13
Figure 1.22 SCU SDRAM Select Register Map ....................................................... 14

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Figure 1.23 SCU Version Register Map .................................................................. 14(Chapter 2 Operation)

Figure 2.1 DMA Transfer Basic Operation ................................................................ 16
Figure 2.2 DMA Transferable Area when Activacted from the Main CPU ................ 17
Figure 2.3 DMA Transferable Area when Activacted from the DSP ......................... 17

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Figure 2.4 Direct Mode DMA Transfer Operation .................................................... 18
Figure 2.5 Indirect Mode DMA Transfer Flow .......................................................... 19
Figure 2.6 Indirect Mode DMA Transfer Operation Details ...................................... 20
Figure 2.7 Differences in DMA Operations according to the Address Update Bit .... 22vii

Figure 2.8 Example of Data Write ............................................................................ 23ntialFigure 2.9 Work RAM Area Contents ...................................................................... 24
Figure 2.10 DMA Transfer by Setting Address Add Value ........................................ 26
Figure 2.11 Blanking Interrupt .................................................................................... 29
Figure 2.12 Timer 0 Interrupt Process (compare register = when 19 is set) ........... 30

Figure 2.13 Timer 1 Interrupt Process (In sync with Timer 0) .................................. 31
Figure 2.14 Timer 1 Interrupt Process (not in sync with Timer 0) ............................ 32
Figure 2.15 DSP Program Load Step 1 ....................................................................34
Figure 2.16 DSP Program Load Step 2 ....................................................................35

deFigure 2.17 DSP Program Load Step 3 ....................................................................35

Figure 2.18 DSP Data Access Step 1 ....................................................................... 36
Figure 2.19 DSP Data Access Step 2 ...................................................................... 37
Figure 2.20 DSP Data Access Step 3 ...................................................................... 37
Figure 2.21 DSP Program Execution Start Control from CPU ................................. 38

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Figure 2.22 DSP Program Forced Stop Control from CPU ...................................... 38(Chapter 3 Registers)

Figure 3.1 Level 2-0 Read Address (Register: D0R, D1R, D2R) ........................... 41

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Figure 3.2 Level 2-0 Write Address (Register: D0W, D1W, D2W) ......................... 41
Figure 3.3 Level 0 Transfer Byte Number (Register: D0C) .................................... 42
Figure 3.4 Level 2-1 Transfer Byte Number (Register: D1C, D2C) ........................ 42
Figure 3.5 Level 2-0 Address Add Value (Register: D0AD, D1AD, D2AD) ............. 42
Figure 3.6 Communication Units between the SCU and Processor ........................ 44
Figure 3.7 Specific Example of Transfer between the SCU and Processor ............. 44
Figure 3.8 Write Address Add Value Indication ........................................................ 45

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Figure 3.9 Level 2-0 DMA Authorization Bit (Register: D0EN, D1EN, D2EN) ....... 45
Figure 3.10 Level 2-0 DMA Mode, Address Update, Start Up Factor
Select Register (Register: D0MP, D1MP, D2MP) ................................ 46

Figure 3.11 DMA Force-Stop Register (Register: DSTP) ...................................... 47
Figure 3.12 High and Low Level DMA Operation .................................................... 48

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Figure 3.13 DMA Status Register (Register: DSTA) .............................................. 48

viii

Figure 3.14 DSP Program Control Port (Register: PPAF) ..................................... 51ntialFigure 3.15 DSP Program RAM Data Port (Register: PPD) ................................... 53
Figure 3.16 DSP Data RAM Address Port (Register: PDA) .................................... 53
Figure 3.17 DSP Data RAM Data Port (Register: PDD) ........................................ 54
Figure 3.18 Time 0 Compare Register(Register: T0C) ....................................... 55

Figure 3.19 Timer 1 Set Data Register (Register: T1S) ......................................... 55

Figure 3.20 Timer 1 Mode Register (Register: T1MD) ........................................... 56
Figure 3.21 Interrupt Mask Register (Register: IMS) ............................................. 57

Figure 3.22 Interrupt Status Register (Register: IST) ........................................... 58

deFigure 3.23 A-Bus Interrupt Acknowledge Register (Register: AIAK) ...................... 61

Figure 3.24 A-Bus Set [CS0, 1 Space] (Register: ASR0) ........................................ 62
Figure 3.25 A-Bus Set [CS2, Dummy Space] (Register: ASR1) ............................. 62
Figure 3.26 Result of Previous Read Process ......................................................... 63
Figure 3.27 Timing when Setting the Pre-Charge Insert Bit after Write ................... 63

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Figure 3.28 Timing when Setting the Pre-Charge Insert Bit after Read .................. 64
Figure 3.29 Differences in Timing by Setting External Wait Effective Bit ................. 64
Figure 3.30 A-Bus Refresh Register (Register: AREF) .......................................... 72
Figure 3.31 SCU SDRAM Select Bit (Register: RSEL) .......................................... 73

Chapter 4 DSP Control)Co

Figure 3.32 SCU Version Register (Register: VER) ................................................ 73

Figure 4.1 DSP Internal Block Map ........................................................................... 77
Figure 4.2 Jump Command Execution ..................................................................... 85
Figure 4.3 Loop Program Execution ......................................................................... 86
Figure 4.4 Subroutine Program Execution ................................................................ 91

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Figure 4.5 Operation Command Format ................................................................... 92
Figure 4.6 Load Immediate Command Format 1 (Unconditional Transfer) ........... 120
Figure 4.7 Load Immediate Command Format 2 (Conditional Transfer) ............... 120
Figure 4.8 DMA Command Format 1...................................................................... 132
Figure 4.9 DMA Command Format 2...................................................................... 132
Figure 4.10 Jump Command Format ...................................................................... 141

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Figure 4.11 Loop Bottom Command Format ......................................................... 153
Figure 4.12 End Command Format ........................................................................ 156

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List of Tables(Chapter 2 Operation)

Table 2.1 Interrupt Factors ................................................................. 27

Table 2.2 Interrupt Factor General Names ........................................ 28(Chapter 3 Registers)

Table 3.1 Register List ....................................................................... 40

Table 3.2 Read Address Add Value ................................................... 43

deTable 3.3 Write Address Add Value ................................................... 43
Table 3.4 Starting Factors .................................................................. 46
Table 3.5 RAM Page Select ...............................................................53
Table 3.6 Timer 1 Occurrence Selection Contents ............................ 56
Table 3.7 Timer Operation Contents ................................................. 56

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Table 3.8 Interrupt Status Bit Contents ............................................. 59
Table 3.9 A-Bus Interrupt Acknowledge Contents .............................. 61
Table 3.10 CS0 Space Burst Cycle Set Values .................................. 65
Table 3.11 CS0 Space Normal Cycle Set Values ............................... 65

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Table 3.12 CS0 Space Burst Length Set Values ................................ 65
Table 3.13 CS0 Space Bus Size Set Values ...................................... 66
Table 3.14 CS1 Space Burst Cycle Set Values .................................. 67
Table 3.15 CS1 Space Normal Cycle Set Values ............................... 67
Table 3.16 CS1 Space Burst Length Set Values ................................ 68
Table 3.17 CS1 Space Bus Size Set Values ...................................... 68
Table 3.18 CS2 Space Burst Cycle Set Values .................................. 69

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Table 3.19 CS2 Space Bus Size Set Values ...................................... 70
Table 3.20 Dummy Space Burst Cycle Set Values ............................. 71
Table 3.21 Dummy Space Normal Cycle Set Values ......................... 71
Table 3.22 Dummy Space Burst Length Set Values ........................... 71
Table 3.23 Dummy Space Bus Size Set Values ................................. 72

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Table 3.24 A-Bus Refresh Wait Number ............................................. 72

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(Chapter 4 DSP Control)ntialTable 4.1 List of Commands (1) ........................................................ 80
Table 4.2 List of Commands (2) ........................................................ 81
Table 4.3 List of Commands (3) ........................................................ 82
Table 4.4 List of Commands (4) ........................................................ 83

Table 4.5 Descriptions of Constants .................................................. 84

Table 4.6 Features of Data Transfer from D0 Bus to DSP ................ 87

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Table 4.7 Features of Data Transfer from DSP to D0 Bus ................ 88

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CHAPTER 1 OVERVIEW

Chapter 1 ContentsSCU Overview ......................................................................2

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1.1

System Diagram ..................................................2
Block Diagram .....................................................3
1.2

SCU Mapping .......................................................................4
Operation of Cache Hit ......................................5
SCU Register Map................................................................ 7

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1.3

Level 2-0DMA Set Register ................................8DMA Forced-Stop Register ................................8DMA Status Register ..........................................9Co

DSP Program Control Port ................................9DSP Program RAM Data Port .........................10
DSP Data RAM Address Port ..........................10
DSP Data RAM Data Port ................................10
Timer 0 Compare Register ............................... 11
Timer 1 Set Data Register ................................. 11Interrupt Mask Register ...................................12
Interrupt Status Register ..................................12
A-Bus Interrupt Acknowledge Register ........12
A-Bus Set Register .............................................13
A-Bus Refresh Register .....................................13
SCU SDRAM Select Register ...........................14
SCU Version Register ........................................14SE

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Timer 1 Mode Register ..................................... 11

SCU User's Manual

1

1.1

SCU Overview

ntial

The SCU (System Control Unit) contains a CPU I/F, A-Bus I/F, and B-Bus I/F. It
smoothly interfaces multiple processors connected through their respective I/Fs andbuses. Also contained inside are the DMA controller, interrupt controller, and DSP.

deThe DMA controller controls the internal level 2-0 as well as DSP total 4 channel
DMA transfer, and allows the free transfer of data between the CPU, A-Bus, and BBus. Using the CPU-Bus, the CPU can access the work area while executing the
DMA of the A-Bus and B-Bus. The DSP region must be used in data transfer requestfrom the DSP. For instance, DMA transfer with the A-Bus and B-Bus not using the
DSP region cannot request that data be transfered from the DSP.
The interrupt controller includes interrupts from the A-Bus, B-Bus, and System
Manager, and controls all interrupts within the SCU. It also supports interrupt bytimers and can produce interrupts that are in sync with the screen.

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DSP can handle processes that cannot be handled by the main CPU when its load
has been exceeded. DSP operates at half the frequency of the main CPU. As a result,
one step takes about 70 nsec.

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System Diagram
A diagram of the system is shown in Figure 1.1. The Work RAM-H, Work RAM-L,
Backup RAM, IPL ROM, and SMPC are connected to the CPU-Bus. The CPU-Bus
controls the system reset signal and control pad. The medium that supplies the CDor cartridge software is an external system connected to the A-Bus. VDP1, VDP2,
and SCSP are connected to the B-Bus and control picture and sound.

A-Bus

Main
CPU

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INT Signal

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WORK WORK BACKUP
RAM-H RAM-L
RAM

2

SCU

CPU-Bus

IPL
ROM

SMPC

Figure 1.1 Diagram of System

B-Bus

VDP1

VDP2

SCSP

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Block Diagram
A block diagram of the SCU is shown in Figure 1.2. As previously mentioned, theCPU interface, A-Bus, and B-Bus interfaces, and the DMA controller, interrupt controller, and DSP are contained in the SCU. All interfaces and controllers are connected by buses, making transfer of data possible.

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The CPU I/F and A-Bus I/F connections are through two buses. The upper bus isconnected through the register. The lower bus is a connection used in transferringdata. Therefore, DMA transfer is done using the lower bus.

SCU
Main CPU

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INT

TIMER

CPU
I/F

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CPU-Bus

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DSP

SCU User's Manual

DMA

A-Bus
I/F

A-Bus

B-Bus
I/F

B-Bus

Figure 1.2 Block Diagram

3

SCU Mapping

Figure 1.3 shows the mapping operation.

00000000 H

ROM Access Region

512 Kbyte

00080000 H
00100000 H

SMPC Region

128 byte

00100080 H
00180000 H

Backup-RAM Region

64 Kbyte

00190000 H
00300000 H
01000000 H

External Area 1 Region
Work-RAM-L Region
MINIT Region

01000004 H
01800000 H
01800004 H

SINIT Region

02000000 H

05000000 H
05800000 H

4 byte32 Mbyte
16 Mbyte

A-Bus Dummy Region

8 MbyteA-Bus CS2 Region

1 MbyteCo

1 Mbyteabout 1 Mbyte

VDP 1 Region

192 Kbyte

VDP 1 Region

24 byteVDP 2 Region

512 Kbyte

VDP 2 Region

4 KbyteGA

Sound Region

VDP 2 Region
VDP 2 Region
05FC0000 H

288 byte

05FE0000 H
05FE00D0 H

SCU Register Region

208 byte

06000000 H
06100000 H
07FFFFFF H

SCU Register
Region Region
Work RAM-H

1 MbyteSE

Indicates areas that can't be accessed

Figure 1.3 SCU Mapping (Cache_address)

4

4 byteA-Bus CS1 Region

05900000 H
05A00000 H
05B00EE4 H
05C00000 H
05CC0000 H
05D00000 H
05D00018 H
05E00000 H
05E80000 H
05F00000 H
05F01000 H
05F80000 H
05F80120 H

1 Mbytenfi

A-Bus CS0 Region
04000000 H

~
~

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00200000 H

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1.2

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Operation of Cache Hit
If a hit is made to the cache during access to an area that is rewritable by non-CPU
devices such as the work RAM of an I/O port, an external device, or a SCU register,a value different from the actual value could be returned. When this happens, thecache-through area must be accessed.
Figure 1.4 explains cache hit operations, and Figure 1.5 shows cach-through operations.

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Cache

A Device

Reads address 5C00000 H.
Data is FFFFFFFF H

B Device

CPU can write data to cache

SCU

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CPU

Write from device A to B (DMA)
Cache
CPU

A Device

Cache does not change.

B Device

Address 5C00000H clears to 0

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SCU

Accesses cache address area
Cache

A Device

Accesses cache-through area
Cache
SCU

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SCU
CPU

B DeviceCPU

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Address 5C00000H is read again.
Data FFFFFFFF H inside cache
becomes valid.

SCU User's Manual

A Device
B Device

Reads again from device B without
accessing the cache. Data is 0.
Address is 25C00000H.

arrow indicates the flow of data

Figure 1.4 Explanation of Cache Hit Operation

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ROM Access Region

512 Kbyte

20100000 H

SMPC Region

128 byte

20100080 H
20180000 H

Backup-RAM Region

64 Kbyte

20190000 H
20200000 H
20300000 H
21000000 H~~

External Area 1 Region
Work-RAM-L Region

1 MbyteMINIT Region

4 byte21800004 H

SINIT Region

22000000 H
A-Bus CS0

25000000 H
25800000 H

A-Bus CS1

A-Bus CS2

1 Mbyte1 MbyteSound Region

about 1 Mbyte

VDP 1 Region

192 Kbyte

VDP 1 Region

24 byteVDP 2 Region

512 Kbyte

VDP 2 Region

4 KbyteVDP 2 Region
VDP 2 Region
05FC0000 H

288 byte

SCU Register Region

208 byte

SCU Register
Region Region
Work RAM-H

1 MbyteGA

26000000 H
26100000 H
27FFFFFF H

8 MbyteCo

25FE0000 H
25FE00D0 H

16 Mbyte

A-Bus Dummy

25900000 H
25A00000 H
25B00EE4 H
25C00000 H
25CC0000 H
25D00000 H
25D00018 H
25E00000 H
25E80000 H
25F00000 H
25F01000 H
25F80000 H
25F80120 H

32 Mbyte

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24000000 H

4 bytede21000004 H
21800000 H

ntial20000000 H
20080000 H

Indicates areas that can't be accessedSE

Figure 1.5 SCU Mapping (Cache_through_address)

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1.3

SCU Register Map

25FE0000 H
Level 0 DMA Set Register
25FE0020 H

deLevel 1 DMA Set Register
25FE0040 H

25FE0070 H

32 byte32 byteLevel 2 DMA Set Register

32 byteDMA Forced Stop

16 bytenfi

25FE0060 H

ntialFigure 1.6 shows a map of the SCU register. The SCU register is assigned to thehighest address in the SCU mapping region and, as shown in Figure 1.3, maintains a
208 byte area. Next, a map of each register region is shown.

16 byte25FE0080 H
25FE0084 H
25FE0088 H
25FE008C H
25FE0090 H
25FE0094 H
25FE0098 H
25FE009C H
25FE00A0 H
25FE00A4 H
25FE00A8 H
25FE00AC H
25FE00B0 H

DSP Program Control PortDSP Program RAM DataPort
DSP Data RAM Address PortDSP Data RAM DataPort
Timer 0 Compare Register
Timer 1 Set Data Register
Timer 1 Mode Register
Free
Interrupt Mask Register
Interrupt Status Register
A-Bus Interrupt Acknowledge
Free

4 byte4 byte4 byte4 byte4 byte4 byte4 byte4 byte4 byte4 byte4 byte4 byteA-Bus Set Register

8 byte25FE00B8 H
25FE00BC H

A-Bus Refresh Register

4 byteGA

Co

DMA Status Register

Free

SE

25FE00C4 H SCU SDRAM Select Register
25FE00C8 H SCU Version Register
25FE00CC H
Free
25FE00CF H

SCU User's Manual

8 byte4 byte4 byte4 byteFigure 1.6 SCU Register Map

7

31

24

16

nti
al

Level 2-0 DMA Set Register
Figure 1.7 is a map of the Level 2-0 DMA set register. Parameters required for DMA
transfer are stored in this register. There are three DMA levels (from level 0 to level2), as there are in the SCU register map (Figure 1.6). As a result, the addresses in
Figure 1.7 are shown as relative addresses.
8

00 H
04 H

Read Address (in bytes)

08 H
0C H

Transfer byte number (in bytes)

0

(R/W)

Write Address (in bytes)

(R/W)
(R/W)

10 H
14 H
18 H

3
5

6

7

(W)

4 (W)

8

(W)

nfi

1C H

2

de

1

Co

Inside graphic:
1. Read address add value 5. DMA mode bit (=0:Direct Mode / =1:Indirect Mode)
2. Write address add value
6. Read address update bit (=0:Save / =1:Revise)
3. DMA enable bit (=0:Disable / =1:Enable) 7. Write address update bit (=0:Save / =1:Update )4. DMA starting bit
8. DMA start factor select bit
Figure 1.7 Level 2-0 DMA Set Register Map

GA

DMA Force-Stop Register
Figure 1.8 is a map of the DMA force-stop register. This register has a bit that forces
the DMA operation to stop. However, if the DMA is forced to stop, it can no longer
be used. This register should not be used except for debugging.
31

25FE0060 H

Inside graphic:
1. DMA force-stop bit (=1:DMA force-stop)SE

Figure 1.8 DMA Force-Stop Register Map

8

0

1 (W)

31

24

25FE007C H

16
1 2 3

4 5

nti
al

DMA Status Register
Figure 1.9 is a map of the DMA status register. This register shows level 2-0 condition
status.
8

6 7

0

8 9

1011

1213 (R)deInside graphic:
1. DMA DSP-Bus access flag (=0: no access /=1:access)2. DMA B-Bus access flag (=0: no access / =1:access) 8. Level 1 DMA standby (=0:stop/=1:standby)
3. DMA A-Bus access flag (=0: no access / =1:access) 9. Level 1 DMA in operation (=0:stop/=1:operate)
4. Level 1 DMA interrupt(=0:stop/=1:interrupt)
10. Level 0 DMA stand by (=0:stop/=1:standby)
5. Level 0 DMA interrupt(=0:stop/=1:interrupt)
11. Level 0 DMA in operation (=0:stop/=1:operate)
6. Level 2 DMA standby (=0:stop/=1:standby)
12. DSP side DMA in stand by (=0:stop/=1:standby)
7. Level 2 DMA in operation (=0:stop/=1:operate)
13. DSP side DMA in operation (=0:stop/=1:operate)
Figure 1.9 DMA Status Register Map

25FE0080 H

26 24

16 15

Co

31

nfi

DSP Program Control Port
Figure 1.10 is a map of the DSP program control port. This is the DSP control register.
It stores both the DSP operation start address and end address.

12

3 4 5 6 7 8 91011

70Prog RAM address (R/W)

GA

Inside graphic:
1. EX = cancels pause briefly (=0: no execute/=1:execute) 7. Overflow flag
2. EX = executes pause briefly (=0: no execute/=1:execute) 8. Program end interrupt flag
3. D0 bus use DMA transfer execution flag
4. Sine flag
9. Program step execute control bit (=0:no execute/=1:execute)
5. Zero flag
10. Program execute control (=0:stop/=1:execute)
6. Carry flag
11. Program counter load authorization (=0:no execute/=1:execute)SE

Figure 1.10 DSP Program Control Port Map

SCU User's Manual

9

nti
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DSP Program RAM Data Port
Figure 1.11 is a map of the DSP program RAM data port. This port is used as ago-between when transferring program data from the CPU to the DSP.
310

05FE0084 H(W)

Program RAM Data
Figure 1.11 DSP Program RAM Data Port Mapde

DSP Data RAM Address Port
Figure 1.12 is a map of the DSP data RAM address port. This port indicates the data
RAM address while accessing the data RAM inside DSP from the CPU.
31

7

05FE0088 H

0

Data RAM Address (W)nfi

Figure 1.12 DSP Data RAM Address Port Map

31

05FE008C H

Co

DSP Data RAM Data Port
Figure 1.13 is a map of the DSP data RAM data port. The content of the address
shown by the DSP data RAM address port is stored. Data written from the CPU isstored in the DSP data RAM and data read from the CPU can fetch RAM data inside
the DSP.
Data RAM Data

SE

GA

Figure 1.13 DSP Data RAM Data Port Map

10

0
(R/W)

nti
al

Timer 0 Compare Register
Figure 1.14 is the map of the timer 0 compare register. Timer 0 gets in sync with VBlank-IN interrupt (See 2.2 Interrupt Control) and causes interrupt to occur. The operation is explained in section 2.2 and the register contents are explained in chapter 3.
31

905FE0090 H

0(W)Counter Value

Figure 1.14 Timer 0 Compare Register Map

deTimer 1 Set Data Register
Figure 1.15 is the map timer 1 set data register. Timer 1 is data-set by H-Blank-IN interrupt (See 2.2 Interrupt Control) and decremented by 7 MHz cycles. Interrupt occurs
when data is 0. The operation is explained in section 2.2 and the register contents are
explained in chapter 3.
31

8

nfi

05FE0094 H

0
Set Data(W)

Figure 1.15 Timer 1 Set Data Register Map

31

05FE0098 H

CoTimer 1 Mode Register
Figure 1.16 is a map of the timer 1 mode register. This register indicates the timing bywhich Time 1 is generated. The operation is explained in section 2.2 and the register
contents are explained in chapter 3.

GA

Inside graphic:
1. Timer 1 mode bit
2. Time operation enable bit

8

0
2 (W)

=0:occurs at each line
=1:occurs only for lines designated by timer 0=0: Timer operation OFF=1 : Timer operation ON

SE

Figure 1.16 Timer 1 Mode Register Map

SCU User's Manual

11

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Interrupt Mask Register
Figure 1.17 shows the map of the interrupt mask register. When this bit is 0, interrupt
is not masked and occurs as needed. When the bit is 1, interrupt will not occur because it is masked. Chapter 3 has more information about bit 0 (inside graphic, no. 15)
to bit 13 (inside graphic, no. 2).
0

15

05FE00A0 H

1

2 3 4 5 6 7 8 9 10 1112131415 (W)deInside graphic:
1. A-Bus interrupt mask bit
2~15 Interrupt mask bit
Figure 1.17 Interrupt Mask Register Map

nfi

Interrupt Status Register
Figure 1.18 shows the map of the interrupt status register. Because this register is able
to read and write, when reading it shows that interrupt won’t occur when bit data is 0,
and will occur when bit data is 1. When writing, interrupt is reset if 0 is written, andmaintains the current interrupt status when 1 is written. See chapter 3 for details
about this register.

Co

31

05FE00A4 H 1 2 3 4 5 6 7 8 9 10 1112131415 1601718192021222324252627282930 (R/W)

Inside graphic:
1~30 Interrupt status bit

GA

Figure 1.18 Interrupt Status Register Map

A-Bus Interrupt Acknowledge Register
Figure 1.19 shows a map of the A-Bus interrupt acknowledge. This is a read/write bitthat has different meanings when reading vs. when writing. See chapter 3 for details.
31

SE

25FE00A8 H

0
1 (R/W)

Inside graphic:
1. READ: A-Bus interrupt acknowledge significant bit (=0:insignificant / =1:significant)
WRITE: A-Bus interrupt acknowledge significant bit (=0:insignificant / =1:significant)Figure 1.19 A-Bus Interrupt Acknowledge Register Map

12

nti
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A-Bus Set Register
Figure 1.20 shows the map of the A-Bus set register. Each pre-read significant bit,precharge insertion bit, and external wait significant bit is insignificant at 0 andsignificant at 1. See chapter 3 for more information.
0

31

25FE00B0 H 1 2 3 4 5 6 7 8 9 10 1112 1314

1516171819 20 212223242526272829

30 (W)

25FE00B4 H 31323334

3738394041424344 454647484950 51

52 (W)

3536

31. CS2 space, pre-read significant bit
32. CS2 space, precharge insertion bit after write
33. CS2 space, precharge insertion bit after read
34. CS2 space, external wait significant bit
35~36. CS2 space, burst length set bit
37. Bus size set bit (0=16 bit 1=8 bit)
38. Spare space, pre-read significant bit
39. Spare space, precharge insertion after write
40. Spare space, precharge insertion after read
41. Spare space, external wait significant bit
42~45. Spare space, burst cycle wait no. set bit
46~49. Spare space, normal cycle wait no. set bit
50~51. Spare space, burst length set bit
52. Spare space, bus size set bit (0=16bit 1=8bit)

Co

nfi

de

Inside graphic:
1. CS0 space, pre-read significant bit
2. CS0 space, precharge insertion bit after write
3. CS0 space, precharge insertion bit after read
4. CS0 space, external wait significant bit
5~8. CS0 space, burst cycle wait no. set
9~12. CS0 space, single cycle wait no. set
13~14. CS0 space, burst length set
15. CS0 space, bus size set bit (0=16bit 1=8bit)
16. CS1 space, pre-read significant bit
17. CS1 space, precharge insertion bit after write
18. CS1 space, precharge insertion bit after read
19. CS1 space, external wait significant bit
20~23. CS1 space, burst cycle wait no. set
24~27. CS1 space, normal cycle wait no. set
28~29. CS1 space, burst length set bit
30. CS1 space, bus size set bit (0=16bit 1=8bit)

Figure 1.20 A-Bus Set Register Map

GA

A-Bus Refresh Register
Figure 1.21 shows the map of the A-Bus refresh register. This register performs thesettings for A-Bus refresh.
31

25FE00B8 H

4

0

1 2 3 4 5 (W)SE

Inside graphic:
1. A-Bus refresh output significant bit (=0:insignificant / =1:significant)2~5. A-Bus refresh wait number set bit

SCU User's Manual

Figure 1.21 A-Bus Refresh Register Map

13

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SCU SDRAM Select Register
Figure 1.22 shows the map of the SCU SDRAM select register.
0

25FE00C4 H

1 (R/W)

Inside graphic:
1. Work-SDRAM select bit (=0:2 Mbit x2 / =1:4 Mbit x 2)

deFigure 1.22 SCU SDRAM Select Register Map

SCU Version Register
Figure 1.23 shows the map of the SCU version register.
31

nfi

25FE00C8 H

Inside graphic:
1~4. Version number‘

SE

GA

Co

Figure 1.23 SCU Version Register Map

140

1 2 3 4 (R)

nti
al

CHAPTER 2 OPERATION
Chapter 2 Contents

2.1

DMA Transfer .......................................................................................16

Basic Operation of DMA ...........................................................16de

DMA Mode .................................................................................18

Example of A Specific Use ........................................................21
2.2

Interrupt Control ..................................................................................27
Blanking Interrupt ......................................................................29
Timer Interrupt ...........................................................................30

nfi

DSP-End Interrupt .....................................................................33
Sound-Request Interrupt ...........................................................33
SMPC Interrupt ..........................................................................33
PAD Interrupt .............................................................................33Co

DMA End Interrupt ...................................................................33
DMA-Illegal Interrupt ...............................................................33
Sprite Draw End Interrupt ........................................................33

2.3

DSP .......................................................................................................34SEGA

DSP Control from the Main CPU .............................................34

SCU User's Manual

15

2.1

DMA Transfer

ntialBasic Operation of DMA
Figure 2.1 shows basic DMA operation. This DMA is basically long word accessthrough the DMA controller buffer, but if the start address and end address are notin long word boundaries, reads and writes are made in byte units, and DMA transfer
can be executed.

Source

3H
4H
5H
6H
7H
8H
9H

1st byte

2nd byte

3rd byte

3rd byte

4th byte

4th byte

5th byte

5th byte

4D H
4EH
4F H

8th byte

8th byte

9th byte

9th byte

~

~

~

7H
8H
9H
AH
BH
CH
DH
EH

1st byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
7th byte
8th byte
9th byte~~

75th byte

50H

75th byte

76th byte

76th byte

51H

76th byte

77th byte

77th byte

78th byte

78th byte

79th byte

79th byte

80th byte

80th byte

Access in long word units

Figure 2.1 DMA Transfer Basic Operation

16

6H

75th byteSE

50H

7th byteGA

4C H

6th byte

7th byte~
4BH

1st byte

2nd byte

6th byte

Destination

write

nfi

2H

Buffer

read

Co

1H

de

Figure 2.1 is an example of DMA transfer from transfer source address 1H - 50H totransfer destination address 6H - 55H. However, since the long word boundary inthe transfer source is 4H, 1H - 3H is read in byte units. Since the long word boundary in the transfer destination is 8H, the first 2 bytes of read data are written to 6H 7H in byte units. Moreover, the transfer source end address is 50H, but since thelong word boundary is up to 4FH, the data in 50H is read in byte units. On the other
hand, since the transfer destination end address is 55H but the long word boundary
is up to 53H, the last two bytes read are written to 54H - 55H in byte units.

52H
53H
54H
55H
Access in bytes

77th byte
78th byte
79th byte
80th bytentialThere are two methods of activating the SCU’s DMA transfer control.
1) activate DMA from the Main CPU2) activate DMA from the DSP

Figure 2.2 shows the DMA transferable area when activated from the main CPU.
Figure 2.3 shows the DMA transferable area when activated from the DSP.

B-Bus Connection
Processor

nfi

A-Bus Connection
ProcessordeWork RAM-H Area

Figure 2.2 DMA Transferable Area when activated from the Main CPU

Co

DSP Area

Work RAM-H Area

B-Bus Connection
Processor

GA

A-Bus Connection
Processor

SE

Figure 2.3 DMA Transferable Area when activated from the DSPSCU User's Manual

17

nti
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DMA Mode
The SCU DMA mode has the following two modes:
1) Direct Mode
2) Indirect Mode
Direct ModeDMA Set Register
Read Address
Write Address

nfiTransfer Byte NumberdeData is transferred only in byte numbers shown as transfer byte numbers directly
using address values of separate level DMA set registers, and from the address
memory shown by the read address register to the address memory shown by thewritten address register. One transfer is implemented per start up, then DMA ends.
Figure 2.4 shows the DMA transfer operation of the direct mode.

Address Add ValueDMA Authorization Bit

Co

Mode, Update, SelectTransfer Source
Read
Address

GA

.
.
.
.

Transfer Destination
Write
Address

DMA Transfer

SE

Figure 2.4 Direct Mode DMA Transfer Operation Map

18

.
.
.
.

Indirect Mode

Indirect Mode DMA

de

nti
al

The indirect mode implements DMA transfer by indirectly using the DMA set register at a level different from the Direct mode mentioned earlier. The address value
and byte number stored by the Direct mode in the set register are stored in theindirect mode temporary buffer by the Indirect mode, and DMA transfer is repeateduntil the end code is detected. Thus, the Indirect mode can implement more than
one DMA transfer when activated once. Figure 2.5 shows the execution flow ofIndirect mode DMA.

nfi

Parameters used for transfer are
copied in a temporary bufferN

Co

End Code Exists

Y

DMA Transfer

GA

DMA Transfer

SE

End

SCU User's Manual

Figure 2.5 Indirect Mode DMA Transfer Flow

19

The indirect mode address is incremented in 4 byte units.

ntialWhen the Indirect mode is activated, parameters of a 3 long word segment from theaddress first written in the write address register (DxW) is read and stored in a
temporary buffer. Next, the actual DMA is executed using the parameters. On
completion of DMA, the address parameters of DxW+CH are read and similarly
executed. This operation is repeated until the end code is detected.

Execute Address Storage Buffer

DMA Set Register
Address

Write Address
Address Add Value(DxW)First Read AddressFirst Write Address

Mode, Update, SelectFirst Transfer Byte Number
Second Read Address(DxW+CH)

Second Write Address

Second Transfer Byte Number

nfi

Write AddressdeDMA Authorization Bit(DxW+C(N-1)H)End Code~~Co

nth Write Address
nth Transfer Byte Number

Temporary Buffer
Read Address

Write Address

GA

Transfer Byte Number
Transfer Destination

Transfer Source

1st DMA Transfer

Write
Address 1

Read
Address 2

2nd DMA Transfer

Write
Address 2

Read
Address 3

3rd DMA Transfer

Write
Address 3

SE

Read
Address 1

End of DMA Transfer

Figure 2.6 Indirect Mode DMA Transfer Operation Details

20

Example of a Specific Use
Direct Mode

4)

5)

6)

7)

de

3)

nfi

2)

Write the read address (200000H) to the read address register D0R. (Loads theaddress that is read to address 25EF0000H from the CPU.)
Write the write address (6000000H) to the write address register D0W. (Loads
the address that is written to address 25EF0004H from the CPU.)
Write the transfer byte number (400H) to transfer byte number register D0C.
(Loads the transfer byte number from the CPU to address 25EF0008H.)
Write the address add value (101H) to address add value register D0AD.
(Loads the address add value from the CPU to address 25EF000CH. Details of
the address add value are listed in the address add value of this section. The
address add value indicated in the normal DMA is 101H. )The DMA mode is 0, and the address update bit and DMA start factor are set as
necessary and written to mode/address/update/DMA start factor register
D0MD. For example, when address update is handled as the save mode and
V-Blank-IN is handled as the start factor, 0 is written to D0MD. (Loads 0 in
address 25EF0014H from the CPU.)Set 1 in the DMA enable bit. When the start factor set by step 5) occurs, DMA
is activated and 1 Kbyte of data is transferred by level 0 from address 2000000H(A-Bus area) to address 6000000H (work RAM).
After DMA has ended, DMA is activated each time the start factor set in step 5)
occurs. The operation at that time changes according to the values of the readaddress update bit (D0RUP) and write address update bit (D0WUP). Figure 2.7
shows DMA operation changes by the address update bit.

Co

1)

nti
al

A 1 Kbyte transfer can be thought of as level 0 DMA from address 2000000H (A-Busarea) to address 6000000H (work RAM). DMA (direct mode) can be executed when
operating in accordance with the following procedures.

SE

GA

Steps 1) to 5) do not have to be done in the same order. (When the start factor is set
in the DMA starting bit, DMA starts each time the DMA operation bit is set to 1 by
the CPU.)SCU User's Manual21

When D0RUP=0 and D0WUP=0
6000000 H

20003FF H

60003FF H

nti
al2000000 H

When D0RUP=0 and D0WUP=1
2000000 H

6000000 H

6000400 H

de20003FF H

When D0RUP=1 and D0WUP=0

6000000 H

nfi

2000000 H

60003FF H

Co

2000400 H

When D0RUP=1 and D0WUP=1
2000000 H

GA

2000400 H

First DMA transfer

6000000 H

6000400 H

Second DMA transfer

Figure 2.7 Differences in DMA Operations according to the Address update Bit

SEWhen the read address update bit is 0, the same address is referred to (read to) boththe first and second time. When the read address update bit is 1, the second readstarts after the address following the first read.
When the write address update bit is 0, write is executed to the same address forboth the first and second time. When the write address update bit is 1, the second
write starts after the address following the first write.

22

Indirect Modential

The Indirect mode is used when executing DMA transfer more than once by starting
once. The Indirect mode is not set in a register as is the Direct mode, but uses amethod of executing DMA by accessing the register through RAM. For example,
consider a case in which three DMA transfers are to be continuously (consecutively)
executed at level 0 through work RAM area (6000000H).
(a) 20HByte DMA transfer from 4000000H to 5C00000H(b) 10HByte DMA transfer from 5E00000H to 6080000H(c) 15HByte DMA transfer from 5A00000H to 6081000H
DMA (Indirect mode) can be executed if operated in accord with the following steps.

600000CH

Co

6000018H

4 00 0 00 0 H
5 C0 0 00 0 H
2 0H
5 E00 0 00 H
6 08 0 00 0 H
1 0H
5 A00 0 00 H
6 08 1 00 0 H
8 00 0 00 1 5H

nfi

6000000Hde1) As shown in Figure 2.8, data is written in long word units from the work RAM
area (6000000H).

6000024H

Figure 2.8 Example of Data Write

GA2) DMA parameter source address (6000000H) is written to the write address
register (D0W).
3) The address add value (101H) is loaded to the address add value register D0AD.
(The address add value is written from the CPU to address 25FE000CH.) Information on the address add value is described in the address add value of thissection. The address add value indicates 101H in normal DMA.

SE4) The DMA mode is 1 and the address update bit and DMA start factor are set as
required and written to mode/address/update /DMA start factor register D0MP.
For example, when address update is handled as the retain mode and V-BlankIN is handled as the start factor, 1000000H is written to D0MD. (Loads 1000000H
in address 25FE0014H from the CPU.)SCU User's Manual

23

nti
al

5) “1” is set in the DMA enable bit, DMA is activated when the start factor set bystep 4) occurs. DMA transfer (a) to (c) is executed in order until the DMA end
code is detected. The DMA end code is the end notification code of the DMA
indirect mode that exists only in the work RAM area. DMA transfer continues aslong as “1” of this bit remains undetected.
Steps 1) to 4) do not need to be done in the same order. The read address register(D0R), transfer byte number register (D0C), and address add value register (D0AD),
which must be set in the Direct mode, do not need to be set in the Indirect mode.

deWhen the DMA transfers listed below are registered in memory, DMA transfer isrestarted after the above process ends. Restart can be done only by repeating theoperation in step (4) above.
(d) 30HByte DMA transfer from 5000000H to 6100000H.
(e) 25HByte DMA transfer from 5100000H to 6200000H.

600000CH

6000018H

GA

6000024H

4 00 0 00 0 H
5 C0 0 00 0 H
2 0H
5 E00 0 00 H
6 08 0 00 0 H
1 0H
5 A00 0 00 H
6 08 1 00 0 H
8 00 0 00 1 5H
5 00 0 00 0 H
6 09 0 00 0 H
3 0H
5 10 0 00 0 H
6 0A0 0 00 H
8 00 0 00 2 5H

Co

6000000Hnfi

The contents from the work RAM area 6000000H are shown below in Figure 2.9.
DMA starts each time the start factor set by (5) occurs.

6000030H

600003CHSE

Figure 2.9 Work RAM Area Contents

24

nti
al

The operation at restart differs depending on whether the DMA mode is in savemode or update mode. Recognition of the save/update mode of the Indirect mode
is performed and judged by the write address update bit.
• For Save mode (write address update bit = 0), after one DMA transfer iscompleted, because the address accessing the parameters is saved at 6000000H,(a) ~ (c) DMA transfer is re-implemented.
• For update mode (write address update bit = 1), after one DMA transfer iscompleted, because the address accessing the parameters is updated at 6000024H,(d) ~ (e) DMA transfer is implemented.
Address Add Value

nfi

de

DMA normally accesses continuous areas, but by setting the address add value, theaddresses of fixed intervals can be accessed. This function is effective when changing part of continuously arranged parameters like the VDP1 command table. An
example is 32 blocks as one 20H byte table from address 5C00000H, among which
the parameters of each 8 byte block are rewritten one time. Change parameters thathave 40H bytes from address 6000000H are set by the following steps and the transfer
process is implemented when transferring via level 0 of DMA.

SE

GA

Co

1) Write the read address 6000000H to read address register D0R.
2) Write the write address 5C00008H to write address register D0W.
3) Write transfer byte number 40H to transfer byte number register D0C.
4) Write the address add value 105H to address add value register D0AD. Here, thelow 3 bits (5=101B) updates the address for each 20H.
5) Set the DMA mode to 0 and set the address update bit and DMA start factor as
required. Write to the mode/address /update/DMA start factor register D0MD.
For example, 0 is written to D0MD when V-Blank-IN is the starting factor andaddress update is in a retain mode.

SCU User's Manual

25

nti
al

6) Set the DMA enable bit to 1. DMA is activated when the starting factor set instep 5) occurs and the slanted line area in Figure 2.10 is rewritten once.

16 bit

5C00000 H
5C00008 H

Table 1

5C00020 H
5C00028 H

deTable 25C00030 H

nfi

5C003E0H
5C003E8H

Co

Table 32

Figure 2.10 DMA Transfer by Setting Address Add ValueSE

GA

Steps 1) through 5) do not have to be in the same order.

26

2.2

Interrupt Control

Table 2.1 Interrupt Factors

V-Blank-IN
V-Blank-OUT
H-Blank-IN
Timer 0Timer 1DSP EndSound Request
System Manager
PAD Interrupt
Level-2 DMA End
Level-1 DMA End
Level-0 DMA End
DMA-illegal
Sprite Draw End--External Interrupt 00
External Interrupt 01
External Interrupt 02
External Interrupt 03
External Interrupt 04
External Interrupt 05
External Interrupt 06
External Interrupt 07
External Interrupt 08
External Interrupt 09
External Interrupt 10External Interrupt 11External Interrupt 12External Interrupt 13External Interrupt 14External Interrupt 15

VDP2
VDP2
VDP2
SCU
SCU
SCU
SCSP
SM
PAD
A-Bus
A-Bus
A-Bus
SCU
VDP1

Vector Number

Level

Vector 40
Vector 41
Vector 42
Vector 43
Vector 44
Vector 45
Vector 46
Vector 47
Vector 48
Vector 49
Vector 4A
Vector 4B
Vector 4C
Vector 4D

Level F
Level E
Level D
Level C
Level B
Level A
Level 9Level 8
Level 8
Level 6
Level 6
Level 5
Level 3
Level 2Vector 50
Vector 51
Vector 52
Vector 53
Vector 54
Vector 55
Vector 56
Vector 57
Vector 58
Vector 59
Vector 5A
Vector 5B
Vector 5C
Vector 5D
Vector 5E
Vector 5F

Level 7
Level 7
Level 7
Level 7
Level 4
Level 4
Level 4
Level 4
Level 1
Level 1
Level 1
Level 1
Level 1
Level 1
Level 1
Level 1nfi

deInterrupt Source

A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus
A-Bus

SE

GA

bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
bit 11
bit 12
bit 13
bit 14
bit 15
bit 16bit 17
bit 18bit 19bit 20
bit 21
bit 22
bit 23
bit 24bit 25bit 26bit 27
bit 28bit 29bit 30
bit 31

Interrupt Factors

Co

Bit
Allocationnti
alTable 2.1 shows the bit allocation of interrupt factors. Bit allocation shows the interrupt register status. Level 1 is the lowest interrupt level and level F is the highest.
Details are given below for each interrupt factor.

SCU User's Manual27

Table 2.2 Interrupt Factor General Names
General Namesntial

Table 2.2 shows by what general names the interrupt factors are called. Later descriptions are based on the general name.

Specific Names

Timer Interrupt

H-Blank-IN
Timer 0DMA End Interrupt

Timer 1
Level 2-DMA End Interrupt
Level 1-DMA End Interrupt

deBlanking Interrupt

V-Blank-IN
V-Blank-OUT

SE

GA

Co

nfi

Level 0-DMA End Interrupt

28

nti
al

Blanking Interrupt
There are three types of blanking interrupt, V-Blank-IN, V-Blank-OUT, and H-BlankIN. Figure 2.11 details blanking interrupt. Blanking interrupt is synchronous to thedisplay, and notifies the user whether a drawing is at the beginning or end.

Display Direction

H-Blank-IN

de

V-Blank-OUT

Co

nfi

Display Screen

GA

V-Blank-IN

Non-Display Area

Figure 2.11 Blanking Interrupt

V-Blank-IN

Indicates the end of a display, after which nothing will be displayed on the screen
even when attempting to display data.
V-Blank-OUT

SE

V-Blank-OUT indicates the beginning of a display. Although a display may be about
to begin, how long before interrupt occurs must be taken into consideration since ittakes time (an interval) for the actual display to materialize. V-Blank-OUT also
clears Time 0 data.

SCU User's Manual29H-Blank-IN

ntialH-Blank-IN indicates the draw end of one line. Timer 0 data is incremented by thistiming.
Timer Interrupt
Time interrupt includes Timer 0 and Timer 1. Time interrupt is synchronous withthe blanking interrupt mentioned earlier and can cause interrupt to occur at dots
(points) on the screen.
Timer 0nfi

deValues are cleared by V-Blank-OUT interrupt reception and counted by
H-Blank-IN interrupt reception . Timer 0 interrupt occurs when values compared to
the Timer 0 compare register (see register details) are the same. Figure 2.12 shows
the Timer 0 occurrence process.

Display Direction
Timer 0 Clear
Timer 0 Increment(In
Sync
with V-Blank-IN)(In Sync with V-Blank-OUT)

Co

Display Screen

SE

GA

Timer 0 Interrupt
Occurence

30

Timer 0 =0Timer 0 =10

Timer 0 =19(Same value ascompare register)

Non-Display Area

Figure 2.12 Timer 0 Interrupt Occurrence Process(compare register = example when set to 19)

Timer 1

de

nti
al

Data of the Timer 1 data set register (see register details) is set by Timer 1 with HBlank-In interrupt receiving. Count down is done at a frequency (1 dot painting) of
7 MHz or about 1/4 the system clock. When the value of Timer 1 becomes 0, interrupt of Timer 1 occurs. Interrupt can also be made to occur at 1 point by combining
it with Timer 0 according to the Timer 1 mode register value (see register details),
and interrupt can be caused to occur at each line independently of Timer 0. Figure
2.13 shows the process up to when Timer 1 interrupt is caused to occur in sync with
Timer 0.

Display Direction

Timer 1 Data Set(each line)

nfi

Display Screen

Timer 1 Register = 0

CoTimer 1 Register = 1

Timer 1 Interrupt Occurence

Timer 0occurence

7 MHz

Non-Display AreaGA

V-Blank-IN
Timer 1 Decrement

SE

Figure 2.13 Timer 1 Interrupt Process (In sync with Timer 0)

SCU User's Manual

31

nti
al

Figure 2.14 shows the process up to when Timer 1 is caused to occur out of sync with
Timer 0. There is no change when operationally in sync but a judgment is made foreach line and interrupt made to occur.

Display Direction

Timer 1 Data Set(each line)deDisplay Screen

7 MHz

Non-Display Area

Co

V-Blank-IN
Timer 1 Decrement

nfi

Timer 1 Interrupt
occurs at each
line

SE

GA

Figure 2.14 Timer 1 Interrupt Process (out of sync with Timer 0)

32

nti
al

DSP-End Interrupt
The program execution control flag (see section 3.3, E flag of the Program Control Port)of the program control port (see section 3.3, Program Control Port) is set by the DSP
ENDI command (see section 4.5, “Command” ENDI command) and gives notice when
the program has ended. By this, the main CPU can retrieve the results calculated by
the DSP.
Sound-Request Interrupt
This interrupt occurs from the SCSP. For example, to display the volume level meteron the screen when a CD (Compact Disk) is connected, interrupt from SCSP is used
and reported to the main.

de

SMPC Interrupt
Detailed information about interrupt that occurs from SMPC is listed in the SMPC
User’s Manual.

nfi

PAD Interrupt
The occurrence of this interrupt depends on the action of the user. PAD is given as
one example but other items, such as a mouse, may be connected.
DMA End Interrupt
Divided by level, this interrupt notifies the user when DMA transfer has ended.
There are three DMA levels from level 2 to level 0.

Co

DMA-Illegal Interrupt
Notifies user that DMA cannot be executed by interrupt when executing DMA thatcannot be done using certain parameters.

SEGA

Sprite Draw End Interrupt
Notifies user via VDP1 that draw has ended.

SCU User's Manual

33

2.3

DSP

nti
al

DSP Control from the Main CPU
This allows control of the DSP from the main CPU. DSP items that can be controlledfrom the CPU include:
1) Load DSP program2) Access DSP data
3) Begin DSP program execution4) Forced stop of DSP program
Load DSP Program

nfi

de

There are two methods in which the DSP program is loaded: by using the DSPDMA command, and by writing directly to the DSP program RAM area from themain CPU. Program data can be loaded if controlled from the main CPU in theorder shown below.
1) Set the program control port bits 16 and 17 to 0.
2) Write the transfer start address to the program RAM address of the same port.
If DSP is not stopped, it cannot be loaded.
3) Write sequence program data in long word units to the program RAM data port.
Figures 2.15 to 2.17 show each step of control from the CPU.

Co

Program Control Port
bit 17

bit 16

Step executecontrol bit

Program executecontrol bit

0

0

GA

bit 31

STEP 1

Stops Program Execute

SE

Figure 2.15 DSP Program Load Step 1

34

bit 0

bit 31

bit 7

nti
al

Program Control Portbit 0

Program RAM Address

Program Transfer
Begin Addressde

STEP 2

Recognizes the Transfer Source Address

Program RAM Data Port
bit 31

nfi

Figure 2.16 DSP Program Load Step 2

bit 0

Co

Program RAM Data Port

Data

GA

STEP 3Loads Program

Program transfer
address counts up 1.

SE

Figure 2.17 DSP Program Load Step 3

SCU User's Manual

35

DSP Data Accessntial

In order to access DSP data, the DMA command of DSP can be used, but there is also
a method that accesses the DSP data RAM area from the main CPU. Data can beaccessed if controlled from the CPU in the following sequence.
1) Set the program control port bit 16 and bit 17 to 0.
2) Write the access start address to the data RAM address port.
If DSP is not stopped, it cannot be set.
3) Sequence data is accessed in long-word units through the data RAM data port.

Program Control Port
bit 31

bit 17

Program executecontrol bitCo0

bit 16

nfi

Step executecontrol bitdeControl methods from the CPU for each step are shown from Figure 2.18 to
Figure 2.20.

0

STEP 1

Stops Program Execute

SE

GA

Figure 2.18 DSP Data Access Step 1

36

bit 0

bit 31

bit 7

nti
al

Data RAM Address Portbit 0

Program RAM Address

Data Access Start Addressde

STEP 2

Recognizes the Access Start Addressnfi

Figure 2.19 DSP Data Access Step 2

Data RAM Data Port
bit 31

bit 0

Co

Data RAM Data Port

Data

GA

STEP 3

Read / Write data

Data access address
counts up 1.

SE

Figure 2.20 DSP Data Access Step 3

SCU User's Manual37

DSP Program Execute Start

Program Control Portb16
Program executecontrol bit

1

b0

de

b31

nti
al

Execution of the DSP program is begun by writing of the program control port 1 tobit 16 (see Figure 2.21). When the write is recognized, DSP begins execution fromthe address stored in the program RAM address of the program control port. The
execution start address must be set before writing “1” to bit 16 of the program control port.

nfi

Figure 2.21 DSP Program Execution Start Control from CPU

DSP Program Forced Stop

Program Control Portb16
Program executecontrol bit

GA

b31

Co

In contrast to execution start, DSP program execution forced stop is done by writing
the program control port 0 to bit 16 of the program control port. Figure 2.22 shows
the forced stop control.

0SE

Figure 2.22 DSP Program Forced Stop Control from CPU

38

b0

nti
al

CHAPTER 3 REGISTERS

Chapter 3 Contents

Register List......................................................................................................... 40

3.2

DMA Control Registers .................................................................................... 41

de

3.1

Level 2-0 DMA Set Register ............................................................. 41
DMA Enable Register ....................................................................... 45
DMA Mode, Address Update, Start Factor Select Register ........ 46
DMA Forced Stop Register .............................................................. 47

3.3

nfi

DMA Status Register ........................................................................ 47
DSP Control Ports .............................................................................................. 51
DSP Program Control Port .............................................................. 51
DSP Program RAM Data Port ......................................................... 53

Co

DSP Data RAM Address Port .......................................................... 53
DSP Data RAM Data Port ................................................................ 54

3.4

Timer Registers ................................................................................................... 55
Timer 0 Compare Register ............................................................... 55
Timer 1 Set Data Register ................................................................. 55
Timer 1 Mode Register ..................................................................... 56

Interrupt Control Registers .............................................................................. 57

GA

3.5

3.6

SE

3.7

SCU User's Manual

Interrupt Mask Register ................................................................... 57
Interrupt Status Register .................................................................. 58

A-Bus Control Registers ................................................................................... 61
A-Bus Interrupt Acknowledge Register ........................................ 61
A-Bus Set Register ............................................................................. 62
A-Bus Refresh Register .................................................................... 72

SCU Control Registers ...................................................................................... 73
SCU SDRAM Select Register ........................................................... 73
SCU Version Register ........................................................................ 73

39

3.1

Register List

Table 3.1 Register List

DSP Control Ports

Timer Registers

End Address

Size

Level 0-DMA Set Register 25FE0000H

25FE0017H

24 byteLevel 1-DMA Set Register

25FE0020H

25FE0037H

24 byteLevel 2-DMA Set Register

25FE0040H

25FE0057H

24 byteDMA Force-End Register

25FE0060H

25FE0063H

4 byteDMA Status Register

25FE007CH

25FE007FH

4 byteDSP Program Control Port 25FE0080H
DSP Program RAM Data
25FE0084H
Port
DSP Data RAM Address
25FE0088H
Port

25FE0083H

4 byte25FE0087H

4 byte25FE008BH

4 byteDSP RAM Data Port

25FE008CH

25FE008FH

4 byteTimer 0 Compare Register 25FE0090H

25FE0093H

4 byteTimer 1 Set Data Register 25FE0094H

25FE0097H

4 byteTimer 1 Mode Register

25FE0098H

25FE009BH

4 bytede

DMA Control Registers

Lead Address

nfi

Register Name

Co

Type

nti
al

A list of SCU registers is given in Table 3.1. Headings are divided for each register
type and each register is explained.

Interrupt Control

Interrupt Mask Register

25FE00A0H

25FE00A3H

4 byteRegisters

Interrupt Status Register

25FE00A4H

25FE00A7H

4 byteA-Bus Control Registers A-Bus Interrupt Acknowledge 25FE00A8H

25FE00ABH

4 byte25FE00B0H

25FE00B7H

8 byteA-Bus Refresh Register

25FE00B8H

25FE00BBH

4 byteSCU SDRAM Select Register

25FE00C4H

25FE00C7H

4 byte25FE00C8H

25FE00CBH

4 byteGA

SCU Control Registers

A-Bus Set RegisterSE

SCU Version Register

40

DMA Control Registers

nti
al

3.2

Level 2-0 DMA Set Register
There are three DMA levels, beginning at the highest priority level of 2 to the lowest
priority level of 0. These are explained below.
• Read Address
Figure 3.1 is the read address register. The DMA mode includes a direct mode
and an indirect mode. The value of the meaning changes for each mode.
b24 b23b31

1 2 3 4 5

b16 b15b8 b7
b0
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

de

25FE0000 (Level 0)
25FE0020 (Level 1)
25FE0040 (Level 2)

Figure 3.1 Level 2-0 Read Address (Register: D0R, D1R, D2R) Initail value undefined
Read Address (1~27 [bit 26 ~ 0] in Figure 3.1)
DxR 26-0[x=2-0] (R/W) DMA level 2-0 Read address bit 26-0

nfi

When in the Direct mode, values being stored are transfer source addresses.
However, this has no meaning when in the Indirect mode. The register ofthat level prohibits writing while DMA is operating. All address values are
expressed in bytes.

25FE0004 (Level 0)
25FE0024 (Level 1)
25FE0044 (Level 2)

b31

Co

• Write Address
The write address register is shown in Figure 3.2. The DMA mode includes a
direct mode and indirect mode; the value of the meaning changes with eachmode.
b24 b23

1

2

3

4

5

6

7 8

b16 b15b8 b7
b0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Figure 3.2 Level 2-0 Write Address (Register: D0W, D1W, D2W) Initial value undefinedGA

Write Address (1~27 [bit 26 ~ 0] in Figure 3.2)
DxW 26-0[x=2-0] (R/W) DMA level 2-0 Write address bit 26-0

SE

When in the Direct mode, the value being stored is the transfer source address. However, when in the Indirect mode, the address of the location where
the transfer source address of DMA transfer is executed the first time isstored. The register of that level prohibits writing while DMA is operating.
All address values are expressed in bytes.

SCU User's Manual

41

•

b31

b24 b23

25FE0008

ntialTransfer Byte Number
Stores the byte number to be transferred by DMA. Figure 3.3 shows the level 0transfer byte number. Figure 3.4 shows the level 2-1 transfer byte number.

b16 b15b8 b7
b0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Figure 3.3 Level 0 Transfer Byte Number (Register: D0C) Initial value undefined
Level 0 transfer byte number (1~20 [bit 19 ~ 0] in Figure 3.3)
D0C 19-0 (R/W) DMA level 0 Count bit 19-0

b31

de

Stores the DMA transfer byte number to be operated at level 0. The registerof that level prohibits writing while DMA is operating. This register can be
set to up to 1 MByte.
b24 b23b16 b15

25FE0028 (Level 1)
25FE0048 (Level 2)

b8 b7
b0
1 2 3 4 5 6 7 8 9 10 11 12

nfi

Figure 3.4 Level 2-1 Transfer Byte Number (Register: D1C, D2C) Initial value undefined
Level 2-1 transfer byte number (1~12 [bit 11 ~ 0] in Figure 3.4)
DxC 11-0[x=2-1] (R/W) DMA level 2-1 Count bit 11-0•

CoStores the DMA transfer byte number to be operated at level 1 or 2. The
register of that level prohibits writing while DMA is operating. This registercan be set to a maximum of 4 Kbytes.

Add Value Register
Figure 3.5 shows the add value register.

25FE000C (Level 0)
25FE002C (Level 1)
25FE004C (Level 2)b31

b24 b23b16 b15

b8 b7
1

b0
2 3 4

SE

GA

Figure 3.5 Level 2-0 Address Add Value (Register: D0AD, D1AD, D2AD) Initial value 00000101H

42

Read Address Add Value (1 [bit 8] in Figure 3.5)
DxRA[x=2-0] (W) DMA level 2-0 Read address Addition data bit

Table 3.2 Read Address Add Value
DxRA (X=2-0)

Description

Nothing is added
4 Bytes are added

de

0
1

nti
al

Designates the add byte number of the read address. Table 3.2 shows theread address add value. Since this is effective only for the CS2 space of the ABus, everything else should set 1B. The register of that level prohibits writing
while DMA is operating.

nfi

Write Address Add Value (2~4 [bit 2~0] in Figure 3.5)
DxWA3-0[x=2-0] (W) DMA level 2-0 Write address Addition data bit 3-0

Co

Designates the add byte number of the write address. Table 3.3 shows thewrite address add value. This value is always effective when writing data to
the B-Bus, but is effective only for 000B or 010B data when writing to the CS2
space of the A-Bus. Data should be set to 010B when writing anywhere except
to A-Bus or B-Bus. The register of that level prohibits writing while DMA isoperating.

Table 3.3 Write Address Add Value
DxWA (X=2-0)

Nothing is added
2 Bytes are added
4 Bytes are added
8 Bytes are added
16 Bytes are added
32 Bytes are added
64 Bytes are added
128 Bytes are added

SE

GA

000 B
001 B
010 B
011 B
100 B
101 B
110 B
111 B

Description

SCU User's Manual

43

de

nti
al

There are provisions (as in Figure 3.6) for the write address add value. As shown in
Figure 3.6, communication between the SCU and B-Bus is in 32-bit units, but in 16bit units between the B-Bus and processor. Thus, when transferring A ~ D data fromthe SCU to the processor, as shown in Figure 3.7, the SCU can transfer A ~ D to the
B-Bus at one time but the B-Bus can only transfer to the processor after dividing A ~B and C ~ D. From this, the difference between address 2 and address 1 can be
written and indicated as the address add value since the write address add value of
B-Bus is 2 byte units, as shown in Figure 3.8.

SCU

B-Bus

16

nfi

32

VDP1

VDP2

Co

SCSP

Figure 3.6 Communication Units Between the SCU and Processor

A

B

B

GA

SCU

A

C
D

SE

32 bits of A~D isoutput once

B-Bus

C
D

Processor
SCSP
VDP1
VDP2

A~B, C~D are divided
into 2 and output

Figure 3.7 Specific Example of Transfer Between the SCU and Processor

44

SCU Transfer B-Bus Transfer
Units
Units

nti
al

Transfer
SourceAddress 1

Transfer
DestinationdeAddress 2

nfi

Address 2 - Address 1 canbe indicated by "Write
Address Add Value"

Figure 3.8 Write Address Add Value Indication

25FE0010 (Level 0)
25FE0030 (Level 1)
25FE0050 (Level 2)b24 b23b16 b15b8 b7
1

Level 2-0 DMA Enable Bit (Register: D0EN, D1EN, D2EN) Initial Value 00000000H

GA

Figure 3.9

b31

Co

DMA Enable Register
This register enable execution of DMA. The register of that level prohibits writing
while DMA is operating. Figure 3.9 shows the format of this register.

DMA Enable Bit (1 [bit 8] in Figure 3.9)
DxEN[x=2-0] (W) DMA level 2-0 ENable bit

This bit enables DMA to be executed. This flag is set to 1 when DMA isenabled. Other required data must be set in advance since DMA begins after
the flag is set.

SE

DMA Starting Bit (2 [bit 0] in Figure 3.9)
DxGO[x=2-0] (W) DMA level 2-0 GO bit

This bit starts execution of DMA. The starting factor bit is significant only
when 111B, and when DMA is started, this bit is set to 1. DMA starts one time
per set.

SCU User's Manual45

25FE0014 (Level 0)
25FE0034 (Level 1)
25FE0054 (Level 2)b31

Figure 3.10

b24 b231

b16 b152nti
al

DMA Mode, Address Update, Start Factor Select Register
This register designates the DMA mode (direct or indirect), address update (save or
update set value), and selection of the start factor. Registers of that level prohibit
writing while DMA is operating. Figure 3.10 shows the register.
b8 b7
3

4

5

b0
6

Level 2-0 DMA Mode, Address Update, Start Factor Select

DMA Mode Bit (1 [bit 24] in Figure 3.10)
DxMOD[x=2-0] (W) DMA level 2-0 MODe bitdeRegister (Register : D0MD, D1MD, D2MD) Initial Value 00000007H

Decides the DMA mode. “0” shows the direct mode, and “1” shows theindirect mode.
Read Address Update Bit (2 [bit 16] in Figure 3.10)
DxRUP[x=2-0] (W) DMA level 2-0 Read update UP bit

nfi

This bit decides whether to save or update the value at the time it is set forread address. 0 means save and 1 means update. See “Example of a SpecificUse” in section 2.1 “DMA Transfer” for more information on how to operate it.
Write Address Update Bit (3 [bit 8] in Figure 3.10)(DxWUP[x=2-0] (W) DMA level 2-0 Write update UP bit

CoThis bit decides whether to save or update the value at the time it is set for
write address. “0” means save and “1” means update. See “Example of A
Specific Use” in section 2.1 “DMA Transfer” for more information on how to
operate it.
DMA Starting Factor Select Bit (4~6 [bit 2~0] in Figure 3.10)
DxFT2-0[x=2-0] (W) DMA level 2-0 starting FacTor bit 2-0

GA

DMA sets the DMA enable bit and starts by receiving an outside signal selected by the starting factor select bit. When the starting factor bit is 111B,
DMA starts by setting the DMA starting bit.
Table 3.4 Starting Factors

Starting Factor Bits (x=2-0)

DxFT1
0
0
1
1
0
0
1
1

SE

DxFT2
0
0
0
0
1
1
1
1

46

DXFT0
0
1
0
1
0
1
0
1

Starting Factors

V-BLANK-IN signal receive and enable bit setting
V-BLANK-OUT signal receive and enable bit setting
H-BLANK-IN signal receive and enable bit setting
Timer 0 signal receive and enable bit setting
Timer 1 signal receive and enable bit setting
Sound Req signal receive and enable bit setting
Sprite draw end signal receive and enable bit setting
Enable bit setting and DMA starting factor bit setting

b31

b24 b23b16 b15

25FE0060

Figure 3.11

nti
al

DMA Forced Stop Register
This is a bit in DMA control which causes DMA forced stops. This register is positioned at address 05FE0060H (32 bit area) within the SCU. Its operation is shown by
the map below.

b8 b7

b0

DMA Force-Stop Register (Register: DSTP) Initial Value 00000000Hde

DMA Force-Stop bit (1 [bit 0] in Figure 3.11)
DSTOP (W) DMA STOP control bit
DSTOP=1 : Stops DMA while in operation.

nfi

DMA Status Register• Access, Interruption, Stand by, Operation Registers
This register shows the DMA bus access indication and the DMA condition foreach level. The four DMA conditions are interrupt, standby, operation, andstop. Explained first are the high level and low level DMA operational relation
ships.

Co

When high level DMA is operating, as shown in Figure 3.15, and launching
low level DMA currently interrupted, the operation will not occur at the time
when the low level DMA is launched (it will not be in operation). It will wait fora period of time and then go into operation mode. This period is called Standby(or Wait period), and this condition always exists prior to the DMA operation.
Low level DMA operates after high level DMA is completed.

SE

GA

When starting high level DMA while low level DMA is operating, operation
will not begin at the moment that high level DMA is started but will begin tooperate after temporarily being on standby. At this time, low level DMA isinterrupted and cannot start until high level DMA has stopped (operation ends).

SCU User's Manual

47

1

nti
al

When Low Level DMA starts while High Level DMA is operating
Start
Low Level DMA

stoppedon standby

High Level DMA

in operationin operation

stoppeddeWhen High Level DMA starts while Low Level DMA is operating
Start
High Level DMA

stoppedLow Level DMA

in operation

stoppedin operation

stoppedinterrupted

in operationnfi

on standby

Figure 3.12 High Level DMA Operation

Co

A 0 bit during interrupt or operation confirms that the DMA operation is stopped.
Figure 3.13 shows access, interrupt, stand by, and operation registers.
b31

b24 b23

25FE007C

1

2

3

4

b16 b15
5

6

7

8

b8 b7
9

10 11

b0
12 13

Figure 3.13 DMA Status Register (Register: DSTA) Initial Value 00000000HGADMA DSP Bus Access Flag (1 [bit 22] in Figure 3.13)
DACSD (R) DMA ACceSs DSP-Bus

Shows whether the DSP bus is being accessed during DMA. 1 means accessing. 0 means not accessing.
DMA B Bus Access Flag (2 [bit 21] in Figure 3.13)
DACSB (R) DMA ACceSs B-Bus

SE

Shows whether the B bus is being accessed during DMA. 1 means accessing.
0 means not accessing.
DMA A Bus Access Flag (3 [bit 20] in Figure 3.13)
DACSA (R) DMA ACceSs A-Bus

Shows whether the A bus is being accessed during DMA. 1 means accessing.
0 means not accessing.

48

nti
al

Level-1 DMA Interrupt Flag (4 [bit 17] in Figure 3.13)
D1BK (R) DMA level 1 BacK ground flag

Shows Level-1 DMA transfer execution is interrupted by the effect of highlevel DMA. A 1 shows that it is currently being interrupted. A 0 shows thatlevel 1 DMA is not interrupted.
Level-0 DMA Interrupt Flag (5 [bit 16] in Figure 3.13)
D0BK (R) DMA level 0 BacK ground flagdeShows Level-0 DMA transfers execution is interrupted by the effect of highlevel DMA. A 1 shows that it is currently being interrupted. A 0 shows thatlevel 0 DMA is not interrupted.
Level-2 DMA Stand by Flag (6 [bit 13] in Figure 3.13)
D2WT (R) DMA level 2 WaiT flag

nfi

Level-2 DMA transfer execution is currently shown in on standby (in wait
condition). A 1 shows the current standby condition. A 0 shows that level 2
DMA is not on standby.
Level-2 DMA Operation Flag (7 [bit 12] in Figure 3.13)
D2MV (R) DMA level 2 MoVe flag

Co

Level-2 DMA transfer execution is currently shown in operation. A 1 showsthat it is currently in operation. A 0 shows level 2 DMA is not in operation.
Also, when both D2WT and D2MV are 0, it shows that level 2 DMA is
stopped.
Level-1 DMA Stand by Flag (8 [bit 19] in Figure 3.13)
D1WT (R) DMA level 1 WaiT flag

Level-1 DMA transfer execution is currently shown on standby. A 1 shows
the current standby condition. A 0 shows that level 1 DMA is not on standby.
Level-1 DMA Operation Flag (9 [bit 8] in Figure 3.13)
D1MV (R) DMA level 1 MoVe flag

GA

Level-1 DMA transfer execution is currently shown in operation. A 1 showsthat it is currently in operation. A 0 shows level 1 DMA is not in operation.
Also, when D1WT, D1MV, D1BK are all 0, it shows that level 1 DMA is
stopped.

Level-0 DMA Stand by Flag (10 [bit 5] in Figure 3.13)
D0WT (R) DMA level 0 WaiT flag

SE

Level-0 DMA transfer execution is shown to be currently on standby. A 1
shows the current standby condition. A 0 shows level 0 DMA is not on
standby.

SCU User's Manual49Level-0 DMA Operation Flag (11 [bit 4] in Figure 3.13)
D0MV (R) DMA level 0 MoVe flagntialLevel-0 DMA transfer execution is shown to be currently in operation. A 1
shows that it is currently in operation. A 0 shows that level 0 DMA is not in
operation. Also, when all D0WT, D0MV, D0BK are 0 it indicates that level 0
DMA is stopped.
DSP DMA Stand by Flag (12 [bit 1] in Figure 3.13)
DDWT (R) DMA DSP WaiT flag

DSP DMA Operation Flag (13 [bit 0] in Figure 3.13)
DDMV (R) DMA DSP MoVe flagdeDMA transfer execution of the DSP statement is shown to be currently on
standby. A 1 shows the current standby condition. A 0 shows that DSP issue
DMA is not on standby.

SE

GA

Co

nfi

DMA transfer execution of the DSP statement is shown to be currently inoperation. A 1 shows that it is currently in operation. A 0 shows that DSP
issue DMA is not in operation. Also, when DDWT, DDMV, D0BK are all 0, it
shows that DSP DMA is stopped.

50

3.3 DSP Control Ports

b31
1 2

25FE080b24 b23
3 4 5

b16 b156 7 8 9 10 11nti
al

DSP Program Control PortThe DSP program control port is shown in Figure 3.14.

b8 b7
b0
12 13 14 15 16 17 18 19

Figure 3.14 DSP Program Control Port (Register: PPAF) Initial Value 00000000H

de

Execute Pause Reset Flag (1 [bit 26] in Figure 3.14)
PR (W) execute Pause Reset flag

When the program execute control flag (see below) is 1, the program pause isreset if 1 is written to the flag and execution begins. The condition does notchange when it does not pause or when the program execute flag is 0.

nfi

Execute Pause Flag (2 [bit 25] in Figure 3.14)
EP (W) Execute Pause flag

When the program execute control flag (see below) is 1, the executing program pauses if 1 is written to the flag. This condition does not change when
it pauses or when the program execute flag is 0.

Co

D0-Bus DMA Execution Flag (3 [bit 23] in Figure 3.14)
T0 (R) Transfer 0This flag becomes 1 when executing DMA using the D0-Bus.
Sine Flag (4 [bit 22] in Figure 3.14)
S (R) Sign flag

This flag becomes 1 when the operation result is negative.
Zero Flag (5 [bit 21] in Figure 3.14)
Z (R) Zero flag

GA

This flag becomes 1 when the operation result is 0.

Carry Flag (6 [bit 20] in Figure 3.14)
C (R) Carry flag

This flag becomes 1 when carry occurs in the operation result.

Overflow Flag (7 [bit 19] in Figure 3.14)
V (R) oVerflow flag

SE

This flag becomes 1 when the operation results causes overflow (orunderflow). This flag is reset by the read out.

SCU User's Manual51

Program End Interrupt Flag (8 [bit 18] in Figure 3.14)
E (R) End flag

Step Execute Control BIt (9 [bit 17] in Figure 3.14)
ES (W) Execute Step control bit

ntialThis flag becomes 1 and causes program end interrupt to occur when the
program ended by the ENDI command is detected. This flag is reset by theread out.

The program executes 1 step if a 1 is written while the program is stopped(when the program execute control flag is 0). Invalid while executing.
Program Execute Control Flag (10 [bit 16] in Figure 3.14)
EX (R/W) program EXecute control flagdeControls execution of program. Execution begins by writing 1 and stops by
writing 0. When this flag is read out, it can be determined whether execution
is in progress (1) or is stopped (0).
Program Counter Transfer Enable Bit (11 [bit 15] in Figure 3.14)
LE (W) Load Enable bit

Co

nfi

This bit decides whether or not the program RAM address (see below) is to beloaded to the program counter. The program RAM address is loaded to theprogram counter if 1 is written to the bit. The address can not be loaded
when the program is being executed (when the program execute control flagis 1).
Program RAM Address (12~19 [bit 7~0] in Figure 3.14)
P7-0 (R/W) Program RAM address bit 7-0

SEGAStores the address of the program RAM. Also, is able to set the begin address
and read the stop address.

52

b31
25FE0084 1

2

3 4

5

6

7

nti
al

DSP Program RAM Data Port
Details of the DSP program RAM data port are shown in Figure 3.15. Data is loaded
into the program RAM by writing data stored in the program RAM area from the CPU.
After loading, the program RAM address of the program control port counts up 1.
However, write is prohibited while the program is being executed (when program
execute control flag is 1). This port is write only.
b24 b23b16 b15b8 b7
b0
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

deFigure 3.15 DSP Program RAM Data Port (Register: PPD) Initial Value Undefinedb31

b24 b23

25FE0088

nfi

DSP Data RAM Address PortThe DSP data RAM address port is shown in Figure 3.16. This sets the data RAM address to be accessed. However, write is prohibited while the program is being executed(when program execute control flag is 1).
b16 b15

b8 b7
1 2

3 4 5

b0
6 7 8

Co

Figure 3.16 DSP Data RAM Address Port (Register: PDA) Initial Value 00000000H
Data RAM Select Bit (1~2 [bit 7~6] in Figure 3.16)
RA7-6 (W) RAM select bit bit 7-6

Shows the page of the read RAM data. Table 3.5 shows the RAM page selection.
Table 3.5 RAM Page SelectBit

Select RAM Page

RA6

0
0
1
1

0
1
0
1

GA

RA7

Selects RAM0
Selects RAM1
Selects RAM2
Selects RAM3

Data RAM Address (3~8 [bit 5~0] in Figure 3.16)
RA5-0 (W) RAM address bit 5-0

SE

Indicates the read data RAM address.

SCU User's Manual

53

b31
25FE008C 1

2

3 4

5

6

7

nti
al

DSP Data RAM Data Port
Details of the DSP data RAM data port are shown in Figure 3.17. The data RAM
data is accessed from this port. The data RAM address of the DSP data RAM address port increases by 1 when accessed. However, access is prohibited while theprogram is being executed (when program execute control flag is 1). This port canread and write.

b24 b23b16 b15b8 b7
b0
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

SE

GA

Co

nfi

de

Figure 3.17 DSP Data RAM Data Port (Register: PDD) Initial Value Undefined54

3.4 Timer Registers

b31

b24 b23b16 b15

25FE0090

ntialTimer 0 Compare Register
The Timer 0 compare register is shown in Figure 3.18. (Timer 0 is a counter that
increases on receiving an H-Blank-IN signal, and that is cleared by a V-Blank-END
signal.)b8 b7
1 2 3 4 5b0
6 7 8 9 10

Timer 0 Compare Data (1~1
0 [bit 9~0] in Figure 3.18)
TOC9-0 (W) Timer 0 Compare data bit 9-0

deFigure 3.18 Timer 0 Compare Register (Register: T0C) Initial Value Undefined

nfi

When the value of Timer 0 is equal to the value of this register, timer 0 interrupt will occur.

b31
25FE0094

Co

Timer 1 Set Data Register
The Timer 1 set data register is shown in Figure 3.19. (Timer 1 sets the data of thisregister by the H-Blank-IN signal receive, automatically counts down by 7 MHz, andwhen the Timer 1 value is 0, executes interrupt.)
b24 b23b16 b15b8 b7
1 2 3 4

5

6

7

8

Figure 3.19 Timer 1 Set Data Register (Register: T1S) Initial Value UndefinedGA

Timer 1 Set Data (1~9 [bit 8~0] in Figure 3.19)
T1S8-0 (W) Timer 1 Set data bit 8-0

SE

Sets the value that is set in Timer 1.

SCU User's Manual

55

b0
9

b31

b24 b23ntialTimer 1 Mode Register
Details of the Timer 1 mode register are shown in Figure 3.20. How occurrence ofTime is set is decided by this register.
b16 b15b8 b7
1

25FE0098

Figure 3.20 Timer 1 Mode Register (Register: T1MD) Initial Value 00000000H

Timer 1 Mode Bit (1 [bit 8] in Figure 3.20)
T1MD (W) Timer 1 MoDe bit

Table 3.6 Timer 1 Occurrence Selection
T1MD

Occurrence Selection

Interrupt occurs at each line
Occurs only at lines indicated by Timer 0

nfi

0
1

de

This bit specifies the occurrence of Timer 1. Table 3.6 shows what happens
when it occurs.

Timer Enable Bit (2 [bit 0] in Figure 3.20)
TENB (W) Timer ENaBle bit

CoThis bit turns the timer operation ON/OFF. Operation details are shown in
Table 3.7.
Table 3.7 Timer Operation Contents
TENB

Timer Operation

Timer operation off

1

Timer operation on

SE

GA

0

56

b0
2

3.5 Interrupt Control Registers

b31

b24 b23b16 b15
1

25FE00A0

nti
alInterrupt Mask Register
The interrupt register is shown in Figure 3.21. It does not mask interrupt when thevalue of this register is 0, and masks interrupt when it is 1.

2

3 4

5

6

b8 b7
b0
7 8 9 10 11 12 13 14 15

Figure 3.21 Interrupt Mask Register (Register: IMS) Initial Value 0000BFFFH

deA-Bus Interrupt Mask Bit (1 [bit 15] in Figure 3.21)
IMS15 (W) Interrupt MaSk bit bit 15

Indicates whether to mask the A-Bus interrupt.

Sprite Draw End Interrupt Mask Bit (2 [bit 13] in Figure 3.21)
IMS13 (W) Interrupt MaSk bit bit 13

nfi

Indicates whether to mask the sprite draw end interrupt.
DMA Illegal Interrupt Mask Bit (3 [bit 12] in Figure 3.21)
IMS12 (W) Interrupt MaSk bit bit 12

Indicates whether to mask the DMA illegal interrupt.

Co

Level-0-DMA End Interrupt Mask Bit (4 [bit 11] in Figure 3.21)
IMS11 (W) Interrupt MaSk bit bit 11

Indicates whether to mask the level-0-DMA end interrupt.
Level-1-DMA End Interrupt Mask Bit (5 [bit 10] in Figure 3.21)
IMS10 (W) Interrupt MaSk bit bit 10

Indicates whether to mask the level-1-DMA end interrupt.
Level-2-DMA End Interrupt Mask Bit (6 [bit 9] in Figure 3.21)
IMS9 (W) Interrupt MaSk bit bit 9

GA

Indicates whether to mask the level-2-DMA end interrupt.

PAD Interrupt Mask Bit (7 [bit 8] in Figure 3.21)
IMS8 (W) Interrupt MaSk bit bit 8

Indicates whether to mask the interrupt from PAD.

System Manager Interrupt Mask Bit (8 [bit 7] in Figure 3.21)
IMS7 (W) Interrupt MaSk bit bit 7

SE

Indicates whether to mask the interrupt from the system manager.

Sound Request Interrupt Mask Bit (9 [bit 6] in Figure 3.21)
IMS6 (W) Interrupt MaSk bit bit 6

Indicates whether to mask the sound request interrupt.

SCU User's Manual57

DSP End Interrupt Mask Bit (10 [bit 5] in Figure 3.21)
IMS5 (W) Interrupt MaSk bit bit bit 5

Timer 1 Interrupt Mask Bit (11 [bit 4] in Figure 3.21)
IMS4 (W) Interrupt MaSk bit bit 4

Indicates whether to mask the Timer 1 interrupt.
Timer 0 Interrupt Mask Bit (12 [bit 3] in Figure 3.21)
IMS3 (W) Interrupt MaSk bit bit 3

Indicates whether to mask the Timer 0 interrupt.

deH-Blank-IN Interrupt Mask Bit (13 [bit 2] in Figure 3.21)
IMS2 (W) Interrupt MaSk bit bit 2

nti
alIndicates whether to mask the DSP end interrupt.

Indicates whether to mask the H-Blank-IN interrupt.
V-Blank-OUT Interrupt Mask Bit (14 [bit 1] in Figure 3.21)
IMS1 (W) Interrupt MaSk bit bit 1

nfi

Indicates whether to mask the V-Blank-OUT interrupt.
V-Blank-IN Interrupt Mask Bit (15 [bit 0] in Figure 3.21)
IMS0 (W) Interrupt MaSk bit bit 0

Interrupt Status RegisterCo

Indicates whether to mask the V-Blank-IN interrupt.

Figure 3.22 shows the interrupt status register.

b31
25FE00A4 1

2

3 4

6

7

b24 b23b16 b158 9 10 11 12 13 14 15 16

b8 b7
b0
17 18 19 20 21 22 23 24 25 26 27 28 29 30

Interrupt Status Register (Register: IST) Initial Value 00000000H

GA

Figure 3.22

5SE

These status registers are all read/write registers; the read and write meanings are asshown in Table 3.8.

58

Table 3.8 Interrupt Status Bit Contents
StatusResultRead

01

Interrupt does not occur
Interrupt does occur

Write

0
1

Resets interrupt
Maintains current interrupt statusntialAccessExternal Interrupt Status Bit (1~16 [bit 31-16] in Figure 3.22)
IST31-16 (R/W) Interrupt STatus bit bit 31-16

deShows the status of 16 external interrupts from external interrupt 15 (1 inFigure 3.25) to external interrupt 0 (16 in Figure 3.25).
Sprite Draw End Interrupt Status Bit (17 [bit 13] in Figure 3.22)
IST13 (R/W) Interrupt STatus bit bit 13

Shows interrupt status of sprite draw end.

nfi

DMA Illegal Interrupt Status Bit (18 [bit 12] in Figure 3.22)
IST12 (R/W) Interrupt STatus bit bit 12

Shows interrupt status of DMA illegal.

Level-0-DMA End Interrupt Status Bit (19 [bit 11] in Figure 3.22)
IST11 (R/W) Interrupt STatus bit bit 11

Co

Shows interrupt status of level-0-DMA end.

Level-1-DMA End Interrupt Status Bit (20 [bit 10] in Figure 3.22)
IST10 (R/W) Interrupt STatus bit bit 10

Shows interrupt status of level-1-DMA end.
Level-2-DMA End Interrupt Status Bit (21 [bit 9] in Figure 3.22)
IST9 (R/W) Interrupt STatus bit bit 9

Shows interrupt status of level-2-DMA end.

GA

PAD Interrupt Status Bit (22 [bit 8] in Figure 3.22)
IST8 (R/W) Interrupt STatus bit bit 8

Shows status of interrupt from PAD.

System Manager Interrupt Status Bit (23 [bit 7] in Figure 3.22)
IST7 (R/W) Interrupt STatus register bit bit 7

Shows status of interrupt from the system manager.

SE

Sound Request Interrupt Status Bit (24 [bit 6] in Figure 3.22)
IST6 (R/W) Interrupt STatus bit bit 6

Shows status of sound request interrupt.

SCU User's Manual59

Shows status of DSP end interrupt.
Timer 1 Interrupt Status Bit (26 [bit 4] in Figure 3.22)
IST4 (R/W) Interrupt STatus bit bit 4

Shows status of Timer 1 interrupt.
Timer 0 Interrupt Status Bit (27 [bit 3] in Figure 3.22)
IST3 (R/W) Interrupt STatus bit bit 3

Shows status of Timer 0 interrupt.

Shows status of H-Blank-IN interrupt.

deH-Blank-IN Interrupt Status Bit (28 [bit 2] in Figure 3.22)
IST2 (R/W) Interrupt STatus register bit bit 2ntial

DSP End Interrupt Status Bit (25 [bit 5] in Figure 3.22)
IST5 (R/W) Interrupt STatus bit bit 5

V-Blank-OUT Interrupt Status Bit (29 [bit 1] in Figure 3.22)
IST1 (R/W) Interrupt STatus bit bit 1

nfi

Shows status of V-Blank-OUT interrupt.

V-Blank-IN Interrupt Status Bit (30 [bit 0] in Figure 3.22)
IST0 (R/W) Interrupt STatus bit bit 0

SE

GA

Co

Shows status of V-Blank-IN interrupt.

60

3.6 A-Bus Control Registers

b31

b24 b23b16 b15

25FE00A8

nti
alA-Bus Interrupt Acknowledge Register
Figure 3.23 shows the A-Bus interrupt acknowledge register.

b8 b7

b0
1

Figure 3.23 A-Bus Interrupt Acknowledge Register (Register: AIACK) Initial Value 00000000H
A-Bus Interrupt Acknowledge (1 [bit 0] in Figure 3.23)
AIACK (R/W) A-Bus Interrupt ACKnowledge

nfi

de

This shows the effectiveness or ineffectiveness of interrupts from the devices
that exist on the A-Bus. This bit can read and write. The meaning of the bit isshown in Table 3.9. If interrupt is requested, the A-Bus interrupt acknowledge
cycle occurs, the interrupt classification data (16 bit) is fetched, and by meansof its contents, the current interrupt condition can be acknowledged. If thiscycle occurs, and since the AIACK bit must be 0 and the A-Bus interrupt becomes ineffective, the AIACK bit must be reset to receive interrupt from the
A-Bus.
Table 3.9 A-Bus Interrupt Acknowledge Contents
StatusRead0Invalid A-Bus interrupt

1

Valid A-Bus interrupt

0Invalid A-Bus interrupt

1

Valid A-Bus interrupt

SE

GA

Write

Contents

Co

AccessSCU User's Manual

61

nti
al

A-Bus Set Register
There are a total of four types of spaces arranged as spaces connected to the A-Bus,chip select 0 ~ 2 (hereafter referred to as CS) which includes three types of spacesthat are output and one type of dummy space that CS does not output.
The register relating to the A-Bus is determined by the connecting devices andtherefore must be set to include all devices. Make sure that there is no excessivechange in the value after it has been set.
CS0, CS1, and CS2 Dummy Space A-Bus Set Registers

b31
25FE00B0 1

2

3 4 5

b24 b236 7 8 9 10 11 12 13 14

deFigure 3.24 shows the CS0 and CS1 spaces, and Figure 3.25 shows the CS2 spaces
and dummy spaces of the A-Bus set register.
b16 b15b8 b7
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

b0
30

b31
25FE00B4 1

b24 b23
2

3 4

5

6

nfi

Figure 3.24 A-Bus Set Register [CS0, CS1 Spaces] (Register: ASR0) Initial Value 00000000H

b16 b15b8 b7
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Co

Figure 3.25 A-Bus Set Register [CS2, Dummy Spaces] (Register: ASR1) Initial Value 00000000H

CS0 Space Previous Read Bit (1 [bit 31] in Figure 3.24)
A0PRD (W) A-Bus CS0 Previous ReaD bit

SEGAThis bit decides whether the data previous read process of CS0 space iseffective or not. The time period from when access begins until data output
is reduced by the previous data read process. This is effective only for datathat is stored in the address following the accessed data; other addresses do
not change with normal access. A 1 shows it is effective, 0 shows it is noteffective. Figure 3.26 shows the result when the previous read is effective.

62

b0
22

CPU RDA

B

A-Bus RD
A-Bus DATA

A

B
A

C

C

E

F

E

F

D

B

C

E

de

Collects the next address
data in advance (preread)* The clock in the figure is
the SCU internal clock

Decreases loss time from beginningof access until data is output

Result of Previous Read Process

nfi

Figure 3.26

E

D

C
B

A

CPU DATA

nti
al

CLK

Pre-charge Insert Bit After CS0 Space Write (2 [bit 30] in Figure 3.24)
A0WPC (W) A-Bus CS0 after Write Pre-Charge insert bit

Co

After data is written in the CS0 space, 1 clock no-process condition can beinserted. This is the bit that decides whether the process is effective or ineffective: 1 shows it is effective; 0 shows it is ineffective. This bit does notaffect the operation after CS0 space read. The operation when this bit
has been set is shown in Figure 3.27.
CLK
ARD
AWR

GA

After Read1 clock

After Write
2 clock

After Write
2 clock

After Read1 clock*The clock in the figure is the SCU internal clock

Figure 3.27 Timing when Setting the Pre-Charge Insert Bit after Write

Pre-charge Insert Bit After CS0 Space Read (3 [bit 29] in Figure 3.24)
A0RPC (W) A-Bus CS0 Previous ReaD bit

SE

After CS0 space data is read, 1 clock no-process condition can be inserted.
This is the bit that decides whether the process is effective or ineffective: 1
shows it is effective; 0 shows it is ineffective. This bit does not affect theoperation after CS0 space write. The operation when this bit has been set isshown in Figure 3.28. Depending on the type of device, this bit is set because
a fixed period is required after CS is set to High until the next CS is set toLow. This is true for write as well.

SCU User's Manual

63

ARD
AWR

After Read2 clock

After Write
1 clock

After Write
1 clock

nti
al

CLK

After Read2 clock* Clock in the figure is the SCU internal clock

Figure 3.28 Timing when Setting the Pre-Charge Insert Bit after ReaddeCSO External Wait effective Bit (4 [bit 28] in Figure 3.24)
A0EWT (W) A-Bus CS0 External WaiT effective bit

nfi

Wait can be inserted by force by the external signal when accessing the CS0
space via the A-Bus. Whether the process will be effective or not is decided
by this bit. A 1 shows that the process is effective, 0 shows that the process isineffective. When the process is effective, wait will continue as long as theexternal wait signal is “Low” at the time of the SCU wait sampling. Figure3.29 shows the difference in timing charts when external wait is effective or
ineffective.
CLK

Co

CPU RD
A-Bus RD
AWAIT
DATA

GA

Timing when External Wait
is Ineffective

Timing when External Wait
is Effective* Clock in the figure is the SCU internal clock

Figure 3.29 Differences in Timing by Setting External Wait Effective Bit
CS0 Space Burst Cycle Wait Number Set Bit (5~8 [bit 27~24] in Figure 3.24)
A0BW3-0 (W) A-Bus CS0 Burst cycle Wait bit 3-0

SE

In the CS0 space, the wait number is set for 1 cycle while a burst access isbeing performed. Table 3.10 shows the set values.

64Table 3.10 CS0 Space Burst Cycle Set Values
Bit
A0BW2

A0BW1

A0BW0

0
0
:
1
1

0
0
:
1
1

0
0
:
1
1

0
1
:
0
1

nti
al

Wait Number

A0BW3

No wait (wait does not sample)
1-cycle wait
14-cycle wait
15-cycle wait

CS0 Normal Cycle Wait Number Set Bit (9~12 [bit 23~20] in Figure 3.24)
A0NW3-0 (W) A-Bus CS0 Normal cycle Wait bit 3-0

de

In the CS0 space, the wait number is set for 1 cycle during normal access.
Table 3.11 shows the set values.
Table 3.11 CS0 Space Normal Cycle Set Values
Bit

Wait Number

A0NW2

A0NW1

A0NW0

0
0
:
1
1

0
0
:
1
1

0
0
:
1
1

0
1
:
0
1

No wait (does not sample waits)
1 cycle wait

nfi

A0NW3

Co

14 cycle wait
15 cycle wait

CS0 Burst Length Set Bit (13~14 [bit 19~18] in Figure 3.24)
A0LN1-0 (W) A-Bus CS0 burst LeNgth bit 1-0

In the CS0 space, the length (boundary) to be accessed is designated during
burst access. Table 3.12 shows the length set values.
Table 3.12 CS0 Space Burst Length Set Values
Bit

Access Values

A0LN0
0
1
0
1

No burst access
4 address burst access
256 address burst accessNo boundary

SE

GA

A0LN1
0
0
1
1

SCU User's Manual

65

nti
al

CS0 Space Bus Size Set Bit (15 [bit 16] in Figure 3.24)
A0SZ (W) A-Bus CS0 bus SiZe bit

Sets the A-Bus size in the CS0 space. Table 3.13 shows the set values.
Table 3.13 CS0 Space Bus Set Values
A0SZ

0
1

Bus Size Settings

Indicates 16 bit bus
Indicates 8 bit bus

CS1 Space Previous Read Effective Bit (16 [bit 15] in Figure 3.24)
A1PRD (W) A-Bus CS1 Previous ReaD bit

nfi

de

This bit decides whether the data previous read process of CS1 space is effective or not. The data previous read processes reduces the time from accessstart until data output. This is effective only for data that is stored in addressthat follows the accessed data. Other addresses do not change with normal
addresses. A 1 shows it is effective, a 0 shows it is not effective. See Figure
3.26 for the result when previous read is effective.
Pre-charge Insert Bit After CS1 Space Write (17 [bit 14] in Figure 3.24)
A1WPC (W) A-Bus CS1 after Write Pre-Charge insert bit

Co

Non-process conditions of 1 clock can be inserted after writing data to CS1
space. This is the bit that decides whether the process is effective or ineffective. A 1 shows it is effective, a 0 shows it is ineffective. This bit has no effecton the operation after read. Figure 3.26 shows the operation when this bit
has been set.
Pre-charge Insert Bit After CS1 Space Read (18 [bit 13] in Figure 3.24)
A1RPC (W) A-Bus CS1 Read Pre-Charge insert bitSEGA

One clock worth of non-process condition can be inserted after reading data
to CS1 space. This is the bit that decides whether the process is effective or
ineffective. A 1 shows it is effective, a 0 shows it is ineffective. This bit has
no effect on the operation after write. Figure 3.28 shows the operation when
this bit has been set.

66

CS1 Space External Wait Effective Bit (19 [bit 12] in Figure 3.24)
A1EWT (W) A-Bus CS1 External WaiT effective bitntialWait can be entered by force by an external signal when accessing the CS1
space via the A-Bus; however, whether the process will be effective or not isdecided by this bit. A 1 shows that the process is effective, a 0 shows that theprocess is ineffective. When the process is effective, wait will continue aslong as the external signal is “Low.” Figure 3.29 shows differences intiming charts when external wait is effective vs. ineffective.
CS1 space Burst Cycle Wait Number Set Bit (20~23 [bit 11~8] in Figure 3.24)
A1BW3-0 (W) A-Bus CS1 Burst cycle WaiT bit 3-0

In the CS1 space, the wait number is set for 1 cycle while a burst access isperformed. Table 3.14 shows the set values.

Bit

de

Table 3.14 CS1 Space Burst Cycle Set Values

Wait Number

A1BW2

A1BW1

A1BW0

0
0
:
1
1

0
0
:
1
1

0
0
:
1
1

0
1
:
0
1

No wait (Does not sample wait)
1 cycle wait

nfi

A1BW3

14 cycle wait
15 cycle wait

CS1 Normal Cycle Wait Number Set Bit (24~27 [bit 7~4] in Figure 3.24)
A1NW3-0 (W) A-Bus CS1 Normal cycle Wait bit 3-0

Co

In the CS1 space, the wait number is set for 1 cycle during a normal access.
Table 3.15 shows the set values.
Table 3.15 CS1 Space Normal Cycle Set Values
Bit

A1NW2

0
0
:
1
1

0
0
:
1
1

A1NW1

A1NW0

0
0
:
1
1

0
1
:
0
1

No wait (Does not sample wait)
1 cycle wait
14 cycle wait
15 cycle wait

SE

GA

A1NW3

Wait Number

SCU User's Manual

67

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CS1 space Burst Length Bit (28~29 [bit 3~2] in Figure 3.24)
A1LN1-0 (W) A-Bus CS1 burst LeNgth bit 1-0

The access length (boundary) is indicated while burst accessing in CS1 space.
Table 3.16 shows length values.
Table 3.16 CS1 Space Burst Length Set Values
Bit

Access Settings

A1LN1

A1LN0

0
0
1
1

0
1
0
1

CS1 space Bus Size Set Bit (30 [bit 0] in Figure 3.24)
A1SZ (W) A-Bus CS1 bus SiZe bitdeNo burst access
4 Address burst access
256 Address burst accessNo boundary

Table 3.17 CS1 Space Bus Size Set Values
A1SZ

0
1

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Sets the A-Bus bus size in the CS1 space. Table 3.17 shows the set values.

Bus Size Settings

Indicates 16-bit bus
Indicates 8-bit bus

Co

CS2 Space Previous Read Effective Bit (1 [bit 31] in Figure 3.25)
A2PRD (W) A-Bus CS2 Previous ReaD bit

SEGAThis bit decides whether the data in the previous read process of CS2 iseffective or not. The data previous read process reduces the time fromaccess start until data output. This is effective only for data that is stored in
the address that follows the accessed data. Other addresses do not changewith normal addresses. A 1 shows it is effective, a 0 shows it is not effective.
See Figure 3.25 for the effect when previous read is effective.

68Pre-charge Insert Bit After Writing CS2 Space (2 [bit 30] in Figure 3.25)
A2WPC (W) A-Bus CS2 after Write Pre-Charge insert bitntial

A no-process condition of 1 clock can be inserted after writing data to CS2.
This is the bit that decides whether the process is effective or ineffective. A
1 shows it is effective, a 0 shows it is ineffective. This bit has no effect on theoperation after read. Figure 3.27 shows the operation when this bit has beenset.
Pre-charge Insert Bit After Reading CS2 Space (3 [bit 29] in Figure 3.25)
A2RPC (W) A-Bus CS2 Read Pre-Charge insert bitdeA no-process condition of 1 clock can be inserted after reading data to CS2.
This is the bit that decides whether the process is effective or ineffective. A
1 shows it is effective, a 0 shows it is ineffective.This bit does not affect theoperation after write. Figure 3.28 shows the operation when this bit has
been set.
CS2 Space External Wait Effective Bit (4 [bit 28] in Figure 3.25)
A2EWT (W) A-Bus CS2 External Wait effective bit

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Wait can be entered by force by an external signal when accessing the CS2
space via the A-Bus. Whether the process will be effective or not is decided bythis bit. A 1 shows that the process is effective, a 0 shows that the process isineffective. When the process is effective, wait will continue as long as theexternal signal is “Low.” Figure 3.29 shows differences in timing charts
when external wait is effective vs. ineffective.
CS2 Space Burst Length Bit (5~6 [bit 19~18] in Figure 3.25)
A2LN1-0 (W) A-Bus CS2 burst LeNgth bit 1-0

Co

The access length (boundary) is indicated while burst accessing in CS2.
Table 3.18 shows the length settings.
Table 3.18 CS2 Space Burst Length Set Values
Bit

Access Settings

A2LN0

0
0
1
1

0
1
0
1

GA

A2LN1

No burst access
4 Address burst access
256 Address burst accessNo border

CS2 Bus Size Set Bit (7 [bit 16] in Figure 3.25)
A2SZ (W) A-Bus CS2 bus SiZe bit

SE

Sets the A-Bus bus size in the CS2 space. Table 3.19 shows the set values.

SCU User's Manual69

Table 3.19 CS2 Space Bus Size Set Values
A2SZ

Bus Size Settings

Indicates 16-bit bus
Indicates 8-bit bus

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0
1

Dummy Space Previous Read Effective Bit (8 [bit 15] in Figure 3.25)
A3PRD (W) A-Bus CS3 Previous ReaD bitdeThis bit decides whether the data previous read process of dummy space iseffective or not. The data previous read process reduces the time from accessstart until data output. This is effective only for data that is stored in addressthat follows the accessed data. Other addresses do not change with normal
addresses. A 1 shows it is effective, a 0 shows it is not effective. See Figure
3.26 for the result when previous read is effective.
After Pre-charge Insert Bit Dummy Space Write (9 [bit 14] in Figure 3.25)
A3WPC (W) A-Bus CS3 after Write Pre-Charge insert bit

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Non-process conditions of 1 clock can be inserted after writing data todummy space. This is the bit that decides whether the process is effective or
ineffective. A 1 shows it is effective, a 0 shows it is ineffective. This bit hasno
effect on the operation after read. Figure 3.27 shows the operation when
this bit has been set.
After Pre-charge Insert Bit Dummy Space Read (10 [bit 13] in Figure 3.25)
A3RPC (W) A-Bus CS3 Read Pre-Charge insert bit

Co

Non-process conditions of 1 clock can be inserted after reading data todummy space. This is the bit that decides whether the process is effective or
ineffective. A 1 shows it is effective, a 0 shows it is ineffective. This bit does
not affect the operation after write. Figure 3.28 shows the operation when
this bit has been set.
Dummy Space External Wait Effective Bit (11 [bit 12] in Figure 3.25)
A3EWT (W) A-Bus CS3 External WaiT effective bit

GA

Wait can be entered by force by an external signal when accessing thedummy space via the A-Bus. Whether the process will be effective or not isdecided by this bit. A 1 shows that the process is effective, a 0 shows that theprocess is ineffective. When the process is effective, wait will continue aslong as the external signal is “Low.” Figure 3.29 shows differences intiming charts for when external wait is effective vs. when it is ineffective.
Dummy Space Burst Cycle Wait Number Set Bit (12~15 [bit 11~8] in Figure 3.25)
A3BW3-0 (W) A-Bus CS3 Burst cycle Wait bit 3-0

SE

In dummy space, the wait number is set for 1 cycle while a burst access isperformed. Table 3.20 shows the set values.

70Table 3.20

Dummy Space Burst Cycle Set Values
Bit
A3BW2

A3BW1

A3BW0

0
0
:
1
1

0
0
:
1
1

0
0
:
1
1

0
1
:
0
1

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Wait Number

A3BW3

No wait (wait not sampled)
1 cycle wait
14 cycle wait
15 cycle wait

Dummy Space Normal Cycle Wait Number Bit (16~19 [bit 7~4] in Figure 3.25)
A-Bus CS 3 Normal cycle Wait bit 3-0
A3NW3-0 (W)deIn the dummy space, the wait number is set for 1 cycle during normal
accessing. Table 3.21 shows the set values.
Table 3.21

Dummy Space Normal Cycle Set Values
Bit
Wait Number

A3NW3

A3NW2

A3NW1

A3NW0

0
0
:
1
1

0
0
:
1
1

0
0
:
1
1

0
1
:
0
1

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No wait (wait not sampled)
1 cycle wait
14 cycle wait
15 cycle wait

Co

Dummy Space Burst Length Set Bit (20~21 [bit 3~2] in Figure 3.25)
A3LN1-0 (W)A-Bus CS 3 burst Le Ngth bit 1-0

In the dummy space, the length (boundary) to be accessed is designatedduring burst access. Table 3.22 shows the length set values.
Table 3.22
A3LN1

Dummy Space Burst Length Set Values
Bit
Access Settings
A3LN0

0
1
0
1

No burst access
4 address burst access
256 address burst accessNo boundary

SE

GA

0
0
1
1

SCU User's Manual71Dummy Space Bus Size Set Bit (22 [bit 0] in Figure 3.25)
A3SZ (W) A-Bus CS3 bus SiZe bit

nti
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Table 3.23 Dummy Space Bus Size Set Values
A3SZ

Bus Size Settings

0
1

Indicates 16 bit bus
Indicates 8 bit bus

b31

b24 b23b16 b15

25FE00B8

de

A-Bus Refresh Register
Figure 3.30 shows the A-Bus refresh register.

b8 b7

1

2

3

4

b0
5

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Figure 3.30 A-Bus Refresh Register (Register: AREF) Initial Value 00000000H

A-Bus Refresh Output Effective Bit (1 [bit 4] in Figure 3.30)
ARFEN (W) A-Bus ReFresh ENable bit

Makes effective the refresh cycle output of A-Bus. A 1 indicates it is effective,a 0 indicates it is not effective.

Co

A-Bus Refresh Wait Number Set Bit (2~5 [bit 3~0] in Figure 3.30)
ARWT3-0 (W) A-Bus Refresh WaiT bit 3-0

Sets the A-Bus refresh cycle wait number. Table 3.24 shows the details.
Table 3.24 A-Bus Refresh Wait Number
Bit

Wait Number

ARWT2

ARWT1

0
0
:
1
1

0
0
:
1
1

0
0
:
1
1

SE
72

ARWT0

0
1
:
0
1

GA

ARWT3

No wait1 cycle wait
14 cycle wait
15 cycle wait

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3.7 SCU Control Registers
SCU SDRAM Select Register
The SCU has a register that designates the SDRAM configuration. The SDRAM
select register is shown in Figure 3.31. This register is at address 25FE00C4H within
the SCU.
b31

b24 b23b16 b15

25FE00C4

b8 b7

b0
1

de

Figure 3.31 SCU SDRAM Select Bit (Register: RSEL) Initial Value 00000000H
SD-RAM Select Bit (1 [bit 0] in Figure 3.31)
RSEL (R/W) RAM SELect bit

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RSEL=0 indicates 2 Mbit X 2
RSEL=1 indicates 4 Mbit X 2

SCU Version Register
SCU has a register showing the chip version. This register is at the address
25FE00C8H within the SCU. The version register is shown in Figure 3.32.
b24 b23Co

b31
25FE00C8

b16 b15

b8 b7
1

2

3

Figure 3.32 SCU Version Register (Register: VER) Initial Value 00000000H
Version Number (1~4 [bit 3~0] in Figure 3.32)
VER 3-0 (R) VERsion number bit 3~0

SEGA

Shows the SCU chip version. Because there are 4 bits, this supports version
0~15 chips.

SCU User's Manual

73

b0
4

SE

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(This page is blank in the original Japanese document.)

74

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CHAPTER 4 DSP CONTROL

Chapter 4 Contents

DSP Internal BLOCK MAP ................................................................76

4.2

List of Commands ................................................................................80

4.3

Operand Execution Methods .............................................................85

de

4.1

Jump Command Execution ...............................................85
Loop Program Execution ..................................................86
DMA Command Execution ..............................................87

4.4

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End Command Execution .................................................88
Special Process Execution ...................................................................89
Loading a Program by the DMA Command ..................89
Repeating One Command .................................................89

4.5

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Executing a SubRoutine Program .....................................90
More About Commands .....................................................................91
Operation Commands ........................................................91
Load Immediate Command ............................................120
DMA Command ................................................................132
Jump Commands ..............................................................141

END Command .................................................................156

SE

GA

Loop Bottom Commands .................................................153

SCU User's Manual

75

4.1

DSP Internal BLOCK MAP

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Figure 4.1 (on the next page) is an internal block map of the DSP.

76

SCU User's Manual

77

GA

D0
D1
X
Y

48

RD

SHIFT L16

48

A

WD

RD

A (64 word X 32 bit)

MD2

CT3(6)WD

PROGRAM RAM(256 wordX32bit)

read
data

F
E
T
C
H

RA(8)

Instruction
decoder

TOP(12)

Imm

RD

WA0

DS[31-0]

D0[31-0]

DSPexternalregister

RA0

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DSP
PC(8) LEEX ES EP PR E V C Z S T0
Write address
data

MD3
A (64 word X 32 bit)deTOP(8)nfi

CT2(6)

ACH(16) ACL(32)Q

B

PL(32)WD

P47-0

PH(16)

CT1(6)Co

MD1

A (64 word X 32 bit)

ALU

Y

X

RD

MULTIPLIER

RY(32)

RX(32)

CT0(6)WD

A (64 word X 32 bit)

MDO

Figure 4.1 Block Map Inside DSPSEThis arithmetic unit is able to output up to 48 bits. Normal calculations are executed at 32 bits. Only product sum operations become
48-bit operations.

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• ALU

• MULTIPLIERThis multiplier outputs a low-order 48 bit from among the 64 bit
results obtained by 32 bit X 32 bit. The calculation results are in 48 bit
data; the high-order 16 bit is stored in PH and the low order 32 bit isstored in PL (see below).
This is an 8 bit register that stores the lead address. The jumpcommand and subroutine execution process store the lead address inthis register and execute the process.

• LOP (W)This is a 12 bit register that stores the loop counter. The number ofloops is set by the process of repeating 1 command.

• CT0-3 (W)This is a 6 bit register that stores the access address of data RAM0-3.

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• TOP (W)Co

• MDO-3 (R/W)
This is a 32 bit unit data port that stores the data of data
RAM0-3. There are 64 data ports in each data RAM.
This is the address that stores the register for accessing the data
RAM. This register is 8 bit. The RAM designation number (0-3) isstored by a high-order 2 bit. The RAM access address is stored by a
low-order 6 bit.

• RX (W)This is the 32 bit X-bus connection register that stores the multiplierinput data.

• RY (W)This is the 32 bit Y-bus connection register that stores the multiplierinput data.
This register stores the high-order 16 bit within the 48 bit multiplieroutput data. There is also an input data storage register that stores
the high-order 16 bit within ALU arithmetic unit input data B (48bit).

SE• PH (W)GA• RA (W)• PL (W)78This register stores the low-order 32 bit within the 48 bit of multiplieroutput data. There is also an input data storage register that storesthe low-order 32 bit within ALU arithmetic unit input data B (48bit).

This register stores the high-order 16 bit within 48 bit data showing
the ALU calulation results. There is also an imput data storage
register that stores the high-order 16 bit within ALU arithmetic unit
input data A(48bit).

• ACL (W)This register stores the low-order 32 bit within the 48 bit data
showing the ALU calulation results. There is also an imput data
storage register that stores the low-order 32 bit within ALU arithmetic
unit input data A(48bit).

• D0 BusThis is a 32 bit data bus for external access. It operates at 28 MHz.
It is used in accessing the main CPU.

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• ACH (W)

• X-Bus, Y-Bus

This is a 32 bit data bus for aquiring arithmetic unit input data. It
operates at 14 MHz.
This is a 32 bit external address register used in external → DSP DMA
transfer. Since it takes a 4 byte unit value, the external address should
be shifted right 2 bits.

• WAO (W)This is a 32 bit external address register used in DSP → external DMA
transfer. Since it takes a 4 byte unit value, the external address should
be shifted right 2 bits.

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• RAO (W)SCU User's Manual79List of Commands

A list of commands used by DSP is given in Tables 4.1 to 4.4.
Table 4.1 List of Commands (1)Command

Overview of Operation

Operation Commands
ALU Control
NOP

No operation

AND

Takes the AND operation of [ACL] and [PL].

OR
XOR
ADD

Takes the OR operation of [ACL] and [PL].

SUB
AD2
SR
RR

Subtracts [PL] from [ACL].

SL

Shifts [ACL] left 1 bit, stores 0 in LSB of [ACL], stores MSB
in carry flag.
Rotates [ACL] left 1 bit, stores MSB in carry flag.

Adds [ACL] and [PL].

Adds [ACH][ACL] and [PH][PL].

Shifts [ACL] right 1 bit, stores LSB in carry flag

Rotates [ACL] right 1 bit, stores LSB in carry flag

RL
RL8

Rotates [ACL] left 8 bits, stores b24 in carry flag.

X-Bus Control NOP
MOV [s], X
MOV MUL, P
MOV [s], P

No operation

Y-Bus Control NOP
MOV [s], Y
CLR A
MOV ALU, A

No operation

Transfers data from data RAM to [RX]

[MULTIPLIER] data is transfered to [PH] [PL]Co

MOV [s], A
D1-Bus Control NOPdeTakes the exclusive OR of [ACL] and [PL].

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Type

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4.2

Transfers data from data RAM to [RY]
Clears to 0 [ACH] and [ACL]Transfers [ALU] data to [ACH][ACL]Transfers data from data RAM to [ACL]
No operation

SImm (short immediate) data is stored in a register or a data
RAM designated by [d].
Data is transfered to the RAM designated by [s] or data RAM
designated by [d] from the register.
Stores Imm (immediate) data in register or in data RAM
designated by [d]GA

MOV SImm, [d]Transfers data from data RAM to [PL]

MOV [s], [d]Load Immediate
MVI Imm , [d]Commands
MVI Imm , [d] , Z When Z (zero flag) of the program control port is 1, Imm

SE(immediate) data is stored in register or in data RAM
designated by [d]MVI Imm , [d] , NZWhen Z (zero flag) of the program control port is 0, Imm(immediate) data is stored in register or in data RAM
designated by [d]80Table 4.2 List of Commands (2)Command

Overview of Operation

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Type

When S (sine flag) of the program control port is 1, Imm(immediate) data is stored in register or in data RAM
designated by [d]MVI Imm , [d] , NS When S (sine flag) of the program control port is 0, Imm(immediate) data is stored in register or in data RAM
designated by [d]MVI Imm , [d] , C When C (carry flag) of the program control port is 1, Imm(immediate) data is stored in register or in data RAM
designated by [d]MVI Imm , [d] , NC When C (carry flag) of the program control port is 0, Imm(immediate) data is stored in register or in data RAM
designated by [d]MVI Imm , [d] , T0 When T0 (flag while executing D0 bus DMA) of the program
control port is 1, Imm (immediate) data is stored in register orin data RAM designated by [d]MVI Imm , [d] , NT0 When T0 (flag while executing D0 bus DMA) of the program
control port is 0, Imm (immediate) data is stored in register orin data RAM designated by [d]MVI Imm , [d] , ZS When either S (sine flag) or Z (zero flag) of the program
control port is 1, Imm (immediate) data is stored in register orin data RAM designated by [d]MVI Imm , [d] , NZSWhen both S (sine flag) and Z (zero flag) of the program
control port are 0, Imm (immediate) data is stored in registeror in data RAM designated by [d]DMA D0, [RAM],
SImm (short immediate) data is set in the transfer wordSImm
number counter ([TN0]) as the transfer counter, andtransfers data to the RAM area designated by [RAM] fromoutside using D0-Bus. Transfer begin address ([RA0]) andtransfer word number counter ([TN0]) are updated to thevalue when transfer ends.
DMA [RAM], D0,
SImm (short immediate) data is set in the transfer wordSImm
number counter ([TN0]) as the transfer counter, andtransfers data from the RAM area designated by [RAM] using
D0-Bus to the outside. Transfer begin address ([WA0]) andtransfer word number counter ([TN0]) are updated to thevalue when transfer ends.

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DMA Commands

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Load Immediate
MVI Imm , [d] , S
commands

SCU User's Manual81Table 4.3 List of Commands (3)Command

Overview of Operation

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Type

Sets data within the data RAM designated by [s] as thetransfer counter to the transfer word number counter([TN0]), and transfers data to the RAM area designatedby [RAM] from outside using D0-Bus. Transfer begin
address ([RA0]) and transfer word number counter([TN0]) are updated to the value when transfer ends.
DMA [RAM], D0, [s]Sets data within the data RAM designated by [s] as thetransfer counter to the transfer word number counter([TN0]), and transfers data to the outside from the RAM
area designated by [RAM] using D0-Bus. Transfer begin
address ([WA0]) and transfer word number counter([TN0]) are updated to the value at the time that transfer
ends.
DMAH D0, [RAM], SImm SImm (short immediate) data is set in the transfer word
number counter ([TN0]) as the transfer counter, andtransfers data to the RAM area designated by [RAM] fromoutside using D0-Bus. Transfer begin address ([RA0])
and transfer word number counter ([TN0]) keep the value
when transfer begins.
DMAH [RAM], D0, SImm SImm (short immediate) data is set as the transfer
counter in the transfer word number counter ([TN0]), andtransfers data from the RAM area designated by [RAM] to
the outside using D0-Bus. Transfer begin address([WA0]) and transfer word number counter ([TN0]) keep
the value at the time that transfer ends.
DMAH D0, [RAM], [s]Sets data within the data RAM designated by [s] as thetransfer counter to the transfer word number counter([TN0]), and transfers data to the RAM area designatedby [RAM] from outside using D0-Bus. Transfer begin
address ([RA0]) and transfer word number counter([TN0]) keep the value at the time that transfer begins.
DMAH [RAM], D0, [s]Sets data within the data RAM designated by [s] as thetransfer counter to the transfer word number counter([TN0]) , and transfers data to the outside from the RAM
area designated by [RAM] using D0-Bus. Transfer begin
address ([WA0]) and transfer word number counter([TN0]) keep the value at the time that transfer begins.
Moves to the address shown by Imm (immediate)
JUMP Commands JMP Imm
Moves to the address shown by Imm (immediate) when
JMP Z, Imm
the Z (zero flag) of the program control port is 1.
Moves to the address shown by Imm (immediate) when
JMP NZ, Imm
the Z (zero flag) of the program control port is 0.

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DMA Commands DMA D0, [RAM], [s]82Table 4.4 List of Commands (4)Command

Overview of Processing

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Type

When S (sine flag) of the program control port is 1, moves toaddress displayed by Imm (immediate)
JMP NS, Imm When S (sine flag) of the program control port is 0, moves toaddress displayed by Imm (immediate)
When C (carry flag) of the program control port is 1, moves to
JMP C, Immaddress displayed by Imm (immediate)
JMP NC, Imm When C (carry flag) of the program control port is 0, moves toaddress displayed by Imm (immediate)
When T0 (flag while executing D0 Bus DMA) of the program
JMP T0, Imm
control port is 1, moves to address displayed by Imm(immediate)
JMP NT0, Imm When T0 (flag while executing D0 Bus DMA) of the program
control port is 0, moves to address displayed by Imm(immediate)
JMP ZS, Imm When either Z (zero flag) or S (sine flag) of the program control
port is 1, moves to address displayed by Imm (immediate)
JMP NZS, Imm When either Z (zero flag) or S (sine flag) of the program control
port is 0, moves to address displayed by Imm (immediate)
When loop counter ([LOP]) is any number but 0, the top address
BTM
register ([TOP]) is stored in the program counter and the loop
counter ([LOP]) is decremented. No operation is done when 0.
When loop counter ([LOP]) is any number but 0, the program
LPS
counter stops, the next command is executed, loop counter([LOP]) is decremented. This is repeated until the loop counter
is 0.
Program stops and EX (program execute control flag) of the
END
program control port is reset.
Program stops and EX (program execute control flag) of the
ENDI
program control port is reset, and E (program end interrupt flag)is set.

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END Commands

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LOOP BOTTOM
Commandsde

JUMP Commands JMP S, Imm

SCU User's Manual83•

Table 4.5 Descriptions of Constants
Notation

Description

ExamplePlace a "%" before numbers
Place nothing before nor after numbers
Place a "$" before numbers%0010, %1111
2, 10, 16, 32$05, $0A, $FF

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BinaryDigitalHexadecimalntialDescription of Constants
Follow the notation in Table 4.5.

84

4.3

Operand Execution Methodntial

DSP controls and executes registers as shown for the following commands.

deJump Command Execution
Jump command execution is attained by storing the jump destination address (Immediate Data) in the program RAM address of the program control port. But you
should be aware that commands that are pre-fetched will be executed. The conditional JUMP command examines the condition of the program control port flag, andthen, if the conditions are met, stores the jump destination address in the program
RAM address of the program control port. See the section on Jump commands
under 4.5 “Commands” for the command format. Figure 4.2 is a flowchart of theJump command execution.

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Jump
CommandN

Co

Any
Conditions?
Y

N

Conditions
Satisfied ?
YGAStores Jump destination addressin program RAM address ofprogram control port

SE

Executes pre-fetched commands

SCU User's Manual

END

Figure 4.2 Jump Command Execution

85

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Loop Program Execution
Execution of programs between the address designated by the top address register([TOP]) and the BTM command of the DSP (see Loop Bottom command under 4.5“Command” ) are repeated only the number of times indicated by the loop counter.
Thus, in order to realize this process, it must be executed after setting values in the
top address register and loop counter. Values can be set by the DSP load immediate
command (see section on Load Immediate Command under 4.5 “Command”). Execution flow of the Loop program is shown in Figure 4.3.

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LOOP

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Sets the top addressof the Loop program

Sets number of Loops

Y

Loop End ?
([LOP]=0)Execute command

N

GA

Y

N

Co

BTM
Command ?

Decrement
number of Loops

Stores the Loop program top
address in the program control port

Execute Pre-Fetch Commands

Execute Pre-Fetch Commands

SE

END

Figure 4.3 Loop Program Execution

861) Data transfer from the D0-Bus to the DSP.
2) Data transfer from the DSP to the D0-Bus.

ntial

DMA Command Execution
This sets the DMA controller register from the DSP and explains the actual processof DMA transfer. The DMA command is divided into the two types, shown below,
depending on the transfer direction (read / write).

de• Data transfer from D0-Bus to DSP
DSP data RAM transfer begin address and external memory transfer begin
address are set in registers ([CT0-3] and [RA0]), and transfer is begun by the
DMA command. The command formats up to the DMA command are shown
below. See 4.5 “Commands” for more information.
SImm , [CT0]; Sets DSP data RAM0 transfer begin address

MVI

Imm , [RA0]; Sets external memory transfer begin address

DMA

D0 , [MD0] , SImm

; Begins DMA transfer using the D0 Bus

nfi

MOV

Co

Table 4.6 is a collection of the features of DMA transfer. Because DMA transfer is
executed by 1 long word units, setting of the transfer word number (SImm of the
DMA command mentioned above) must be done in long word units.

Table 4.6 Features of Data Transfer from D0 Bus to DSP
ItemFlag Set
Start and End

T0 flag of the program control port is set
Follows the data ready signal from outside. Transfer is done by this signal in 1
long word units. DMA transfer is ended by the end signal from outside, andthe program control port T0 flag is reset by this timing.
Each time 1 long word is transfered, 1 is added to the DSP data RAM transfer
address ([CT0-3]), and the external memory transfer address ([RA0]) is added
according to the address add number.
If the DMA command Hold bit (see item 4.5 "Commands" DMA command
section) is set to 1, the transfer word number ([TN0]) and external memorytransfer address ([RA0]) keep the transfer begin values.

GA

Address Update

FeatureSE

Hold Status

SCU User's Manual

87

•

nti
al

Data transfer from DSP to D0-Bus
The DSP data RAM transfer begin address and external memory begin address
are set in registers ([CT0-3]) and (WA0]), and transfer is begun by the DMA
command. The command formats up to the DMA command are shown below.
See item 4.5 for more information.
MOV
MVI

SImm , [CT0]Imm , [WA0]; Sets DSP data RAM0 transfer begin address; Sets external memory transfer begin address

DMA[MD0] , D0, SImm

; Begins DMA transfer using the D0 Bus

Table 4.7 Features of Data Transfer from DSP to D0 Bus
FeatureFlag Set
Start and End

Hold Status

T0 flag of the program control part is set

Obeys the data ready signal from outside. Transfer is done by thissignal in 1 long word units. DMA transfer is ended by the end signal
from outside, and the program control port T0 flag is reset by thistiming.
Each time 1 long word is transfered, 1 is added to the DSP data RAM
transfer address ([CT0-3]), and the external memory transfer address([WA0]) is added according to the address add number.
If the DMA command Hold bit (see item 4.5 "Commands" DMA
command section) is set to 1, the transfer word number ([TN0]) andexternal memory transfer address ([WA0]) keep the transfer begin
values.

Co

Address Change

nfi

Item

de

Table 4.7 is a collection of the features of DMA transfer. Because DMA transfer is
executed in single long word units, setting of the transfer word number (SImm of
the DMA command mentioned above) must be done in long word units.

SEGA

END Command Execution
When the END command is recognized, the program control port program RAM
address add process is stopped and the program execution control bit (EX flag) is
reset. Execution of the DSP program is stopped accordingly. But data transfer by
the DMA command continues ignoring this END command until the transfer iscompleted. The value of the program address when the program termintes stops at
the address that follows the address stored in END command.

88Special Process Execution

DSP can execute the following special processes.
1) Loading a Program by the DMA command2) Repeating One Command3) Execution of subroutine program

nti
al

4.4

Imm , [RA0]; Sets external memory transfer begin address

DMA D0 , [PRG], SImm

; Sets transfer word number, begins transfer

MVI; Sets program execution start address

Imm , [PC] , SImm

nfi

MVI

de

Loading a Program by the DMA command
Loading from the CPU was explained earlier as one method of loading a program(see section 2.3), but a program can be loaded in the DSP program RAM by using the
DSP DMA command as well. Loading a program is done in the following formats.

MVI
LPS

Imm , [LOP]; Sets number of repetitions; Repeat execution comand; This command is repeatedly executed

SE

GA

###

Co

Repeating One Command
The format for repeating 1 command is shown below. The 1 command repeat execution command (see LPS command in section 4.5 “Command” under the part on Loop
Bottom) repeat the following commands. The repeat number executes one time
more than the set value.

SCU User's Manual

89

nti
al

Executing a SubRoutine Program
There are no special commands (mnemonic) in the DSP program for executing
subroutines. By combining the Load Immediate command to the [PC] with the Loop
Bottom command, subroutines are created in the form shown in Figure 4.4.

Main

de

Subroutine
Program

ProgramChild

Designates
execution 1 time

MOV Imm , [PC]Sets subroutine
program start address

NOP

Caution:Executed 2 times

nfi

MOV $01 , [LOP]

Programwithin subroutine

Jumps after execution

END

Co

Program

BTM
Execute pre-fetchedcommand of next stepGA

Return to start addressSE

Figure 4.4 Subroutine Program Execution

90

4.5

More About CommandsntialOperation Commands
Operation commands use each X, Y, and D1 bus as well as an arithmetic logic unit
(ALU). Operation commands can be classified into the following four control types.
1) ALU control command2) X-Bus control command3) Y-Bus control command4) D1-Bus control command

31 30 29

26 25

20 19

14 13

Y-Bus Control

0

D1-Bus Control

nfi

0 0 ALU Control X-Bus Controlde

The operation command format is as shown in Figure 4.5.

Figure 4.5 Operation Command Format

SE

GA

Co

Operation commands can execute these four types of commands concurrently.
Mnemonics should list the ALU control command to the far left. Other requiredcommands should be listed and separated by a space or tab.

SCU User's Manual

91

•

SE

GA

Co

nfi

de

nti
al

ALU Control Command
ALU control commands operate using the ALU. The following pages show more
about ALU control commands.

92

ALU No Operation
No ALU command process

Label

NOP

Instruction Code

0

Co

nfi

b31
26
0 0 0 0 0 0

deOperation
Description

nti
al

NOP

No change

GA

Flag

SE

Comments

SCU User's Manual

93

AND

AND Operation
Takes the AND operation of [ACL] and [PL] logical product.

Label

AND

Instruction Code

Co

nfi

b31
26
0 0 0 0 01

de

nti
al

Operation
Description

S ; 1 when operation result is negative, otherwise it is 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; is 0.

GA

Flag

SE

Comments

94

0

OR

OR Operation
Takes the OR operation of [ACL] and [PL] logical sum.

Label

OR

Instruction Code

0

Co

nfi

b31
26
0 0 0 01 0

de

nti
al

Operation
Description

S ; 1 when operation result is negative, otherwise it is 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; is 0.

GA

Flag

SE

Comments

SCU User's Manual

95

XOR

Exclusive OR Operation
Takes the exclusive OR operation of [ACL] and [PL].

Label

XOR

Instruction Code

Co

nfi

b31
26
0 0 0 01 1

de

nti
al

Operation
Description

S ; 1 when operation result is negative, otherwise it is 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; this is 0.

GA

Flag

SE

Comments

960Addition
ADDS [ACL] and [PL].

Label

ADD

Instruction Code

0

Co

nfi

b31
26
0 0 01 0 0

deOperation
Description

nti
al

ADD

S ; 1 when operation result is negative, otherwise it is 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; 1 when carry occurs as a result of the operation, otherwise it is 0.
V ; 1 when there is overflow (exceeds 48 bits)opeation result,
otherwise it is 0.

GA

Flag

SE

Comments

SCU User's Manual97Subtraction
Subtracts [PL] from [ACL].

Label

SUB

Instruction Code

0

Co

nfi

b31
26
0 0 01 01

deOperation
Description

nti
al

SUB

S ; 1 when operation result is negative, otherwise it is 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; 1 when carry occurs as a result of the operation, otherwise it is 0.
V ; 1 when there is underflow in the opeation result,otherwise it is 0.

GA

Flag

SE

Comments98Addition
Adds [ACH][ACL] and [PH][PL].

Label

AD2

Instruction Code

0

Co

nfi

b31
26
0 0 01 1 0

deOperation
Description

nti
al

AD2

S ; 1 when operation result is negative, otherwise it is 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; 1 when carry occurs as a result of the operation, otherwise it is 0.
V ; 1 when there is overflow (exceeds 48 bits)operation result,
otherwise it is 0.

GA

Flag

SE

Comments

SCU User's Manual99

Right Shift 1 Bit

Operation
Description

nti
al

SR

Shifts the value of [ACL] right 1 bit, and the value of bit 0 is stored in C
flag.
MSB

LSB

b31 b30 b29

b2

b1

b0

C

Label

Instruction Code

0

Co

nfi

b31
26
0 01 0 0 0deSRS ; 1 when operation result MSB is 1,0 when 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; 1 when the value of b0 of input data is 1, 0 when 0.
ACL ; Shifts 1 bit to the right, most significant bit (b31) does not change

GA

Flag

SE

Comments

100

Right Rotate 1 Bit

Operation
Description

Rotates the [ACL] value right 1 bit.

MSB

nti
al

RR

LSB

b31 b30 b29

b0

C

Label

Instruction Code

0

Co

nfi

b31
26
0 01 0 01

deRR

S ; 1 when operation result MSB is 1,0 when 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; 1 when the value of b0 of input data is 1, 0 when 0.
ACL ; Shifts 1 bit to the right, least significant bit (b0) moves to the mostsignificant bit (b31).

GA

Flag

SE

Comments

SCU User's Manual101Left Shift 1 Bit

Operation
Description

nti
al

SL

Shifts the [ACL] value left 1 bit.

MSB

LSB

0

b31 b30 b29
C

Label

Instruction Code

Co

nfi

b31
26
0 01 01 0

deSL

S ; 1 when operation result MSB is 1,0 when 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; 1 when the value of b31 of input data is 1, 0 when 0.
ACL ; Shifts 1 bit to the left; least significant bit (b0) is 0.

GA

Flag

SE

Comments

1020Left Rotate 1 Bit

Operation
Description

Rotates the [ACL] value left 1 bit.
MSB

LSB

b31 b30 b29
C

Label

b0

0

Co

nfi

b31
26
0 01 01 1

deRL

Instruction Code

nti
al

RL

S ; 1 when operation result MSB is 1,0 when 0.
Z ; 1 when operation result is 0, otherwise it is 0.
C ; 1 when the value of b31of input data is 1, 0 when 0.
ACL ; Shifts 1 bit to the left, most significant bit (b31) moves to the leastsignificant bit (b0).

GA

Flag

SE

Comments

SCU User's Manual

103

RL8

Left Rotate 8 Bits

Operation
DescriptionntialRotates the [ACL] value left 8 bits.
MSB

LSB

b31 b30 b29

b0

C

Label

Instruction Code

Co

nfi

b31
26
0 01 1 1 1

de

RL8

S ; 1 when operation result MSB is 1,0 when 0.
Z ; 1 when operation result is 0, other wise 0.
C ; 1 when the value of b24of input data is 1, 0 when 0.
ACL ; Rotates 8bits to the left.

GA

Flag

SE

Comments

1040

X-Bus Control Commands
X-Bus control commands transfer data using the X-Bus to the RX register
and PH, PL registers. The following pages show more about X-Bus control
commands.

SE

GA

Co

nfi

de

nti
al

•

SCU User's Manual105

X-Bus No Operation
No X-Bus control process

Label

NOP

Instruction Code
25 23
0 0 0

Co

nfi

b31
0 0

de

Operation
Description

nti
al

NOP

Flag

GA

No change

SE

Comments

1060Operation
DescriptionntialTransfer (Memory →[RX])MOV [s],X

Data is transfered to [RX] from the data RAM address displayed by[CTx(x=0~3)].

[CTx]

[RX]

32bit

Label

de

MOV [Source RAM],X

Source RAM = MO ~ M3 *,MC0 ~ MC3 *Instruction Code25
20
1 0 0x x x

nfi

b31
0 0

Bit Data
bit 21 bit 20

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Co

bit 220

Process Selections

0 DATA RAM0
1 DATA RAM1
0 DATA RAM2
1 DATA RAM30 DATA RAM0
1 DATA RAM1
0 DATA RAM2
1 DATA RAM3

[RX]
[RX]
[RX]
[RX]
[RX] ,CT0++[RX] ,CT1++[RX] ,CT2++[RX] ,CT3++* RX ; becomes data selected by multiple choice.
CTx(x=0 ~ 3) ; incremented as long as b22 = 1. No change when b220.

Comments* [Mx(x=0 ~ 3)] designates DATA RAMx(x=0~3).
[MCx(x=0 ~ 3)] designates DATA RAMx(x=0~3) and after transfer,increments [CTx(x=0~3).

SE

GA

Flag

SCU User's Manual107

MOV MUL,P

The high order 16 bit of the MULTIPLIER data 48 bit is transfered to[PH], and the low order 32 bit is transferred to [PL]
MULTIPLIER
16bit

32bit

[PH]
Label

[PL]

25
0 1 0

20

Co

nfi

b31
0 0

de

MOV MUL,P

Instruction CodeSE

Comments

108

PH ; becomes MULTIPLIER high order 16 bit data
PL ; becomes the MULTIPLIER low order 32 bit data

GA

Flag

→[Pn])

nti
alOperation
Description

Transfer (MULTIPLIER

0Operation
DescriptionntialTransfer (Memory →[PL])

MOV [s],P

Data is transfered to [PL] from the data RAM address displayed by[CTx(x=0~3)]. The value of [PH] is changed by the [PL] signextension.

[CTx]

[PL]

32bit

Label

de

MOV [Source RAM],P

Source RAM = MO ~ M3,MC0 ~ MC3 *Instruction Code25
20
0 1 1x x x

nfi

b31
0 0

Bit Data
bit 21 bit 20

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Process Selections

0 DATA RAM0
1 DATA RAM1
0 DATA RAM2
1 DATA RAM30 DATA RAM0
1 DATA RAM1
0 DATA RAM2
1 DATA RAM3

[PL]
[PL ]
[PL]
[PL]
[PL] ,CT0++[PL] ,CT1++[PL] ,CT2++[PL] ,CT3++

GA

Co

bit 220

PL ; becomes data selected by multiple choice.
PH ; changed by [PL] sign extension.
CTx(x=0~3) ; incremented when b22 = 1. No change when b22 = 0.

Comments* [Mx(x=0 ~ 3)] designates DATA RAMx(x=0~3).
[MCx(x=0 ~ 3)] designates DATA RAMx(x=0~3) and after transfer
increments [CTx(x=0~3).

SE

Flag

SCU User's Manual

109

GA

Co

nfi

de

nti
al

Y-Bus Control Commands
Y-Bus control commands transfer data using the Y-Bus to the RY register
and ACH, ACL registers. The following pages shows more about Y-Bus
control commands.

SE

•

110

Y-Bus No Operation
No Y-Bus control process

Label

NOP

de

Operation
Description

nti
al

NOP

Instruction Code

19 17
0 0 0

0

Co

nfi

b31
0 0

No change

GA

Flag

SE

Comments

SCU User's Manual111

Operation
DescriptionntialTransfer (Memory →[RY])

MOV [s],Y

Data is transfered to [RY] from the data RAM address displayed by[CTx(x=0~3)].

[CTx]

[RY]

32bit

Label

de

MOV [Source RAM],Y
Source RAM = MO ~ M3,MC0 ~ MC3 *Instruction Code19
14
1 0 0x x x

Bit Data
bit16 bit15 bit 14
0
0
1
1
0
0
1
1

Process Selections

0 DATA RAM0
1 DATA RAM1
0 DATA RAM2
1 DATA RAM30 DATA RAM0
1 DATA RAM00 DATA RAM0
1 DATA RAM0

Flag

GA

Co

0
0
0
0
1
1
1
1

SE

Comments

112

0

nfi

b31
0 0

[RY]
[RY ]
[RY]
[RY]
[RY] ,CT0++[RY] ,CT1++[RY] ,CT2++[RY] ,CT3++

RY ; becomes data selected by multiple choice.
CTx(x=0~3) ; incremented when b16 = 1. No change when b16 = 0.

* [Mx(x=0 ~ 3)] designates DATA RAMx(x=0~3).
[MCx(x=0 ~ 3)] designates DATA RAMx(x=0~3) and after transfer
increments [CTx(x=0~3).

0 Clear

nti
al

CLR A

0 clears the [ACH] and [ACL] values.

Label

CLR A

de

Operation
Description

Instruction Code

19
0 0 1

14

0

Co

nfi

b31
0 0

ACH ; becomes 0
ACL ; becomes 0

GA

Flag

SE

Comments

SCU User's Manual113

Operation
Description

Transfers the value of the [ALU] high order 16 bit to [ACH] and thevalue of the [ALU] low order 32 bit to [ACL].
ALU

Label

nti
al

Transfer ([ALU] →[ACH][ACL])

MOV ALU,A

16bit

32bit

[ACH]

[ACL]

Instruction Code
19
0 1 0

14

Co

nfi

b31
0 0

de

MOV ALU,A

ACH ; becomes ALU high order 16 bit data
ACL ; becomes ALU low order 32 bit data

GA

Flag

SE

Comments

114

0Operation
DescriptionntialTransfer (Memory →[ACL])

MOV [s],A

Data is transfered to [ACL] from the data RAM address displayed by[CTx(x=0~3)]. The value of [ACH] is changed by the sign extension of[ACL].

[CTx]

[ACL]

32bit

Label

de

MOV [Source RAM],A

Source RAM = MO ~ M3,MC0 ~ MC3 *Instruction Code19
14
0 1 1x x x

nfi

b31
0 0

Bit Data
bit16 bit15 bit 14
0
0
1
1
0
0
1
1

Process Selections

0DATA RAM01DATA RAM10DATA RAM2
1DATA RAM30DATA RAM01DATA RAM10DATA RAM2
1DATA RAM3

[ACL]
[ACL]
[ACL]
[ACL]
[ACL] ,CT0++[ACL] ,CT1++[ACL] ,CT2++[ACL] ,CT3++

GA

Co

0
0
0
0
1
1
1
1

0

ACL ; becomes data selected by multiple choice.
ACH ; is changed by the sign extension of [ACL]
CTx(x=0~3) ; incremented when b16 = 1. No change when b16 = 0.

Comments* [Mx(x=0 ~ 3)] designates DATA RAMx(x=0~3).
[MCx(x=0 ~ 3)] designates DATA RAMx(x=0~3) and after transfer
increments [CTx(x=0~3).

SE

Flag

SCU User's Manual

115

GA

Co

nfi

de

nti
al

D1-Bus Control Commands
D1-Bus control commands control the exchange of data between memory
connected to the D1-Bus. The following pages shows more about D1-Bus
control commands.

SE

•

116

D1-Bus No Operation
No D1-Bus control process

Label

NOP

de

Operation
Description

nti
al

NOP

Instruction Code
b31
0 0

0

Co

nfi

13
0 0

No change

GA

Flag

SE

Comments

SCU User's Manual117

Operation
DescriptionntialTransfer (SImm →[destination])

MOV SImm,[d]SImm data is transfered to the RAM or register designated by[destination]. SImm data is signed 8 bit data.

[destination]

Short Immediate Data

D31 - 7 ← b7
D6-0 ← b6-0
Label

de

MOV SImm,[Destination]
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,TOP,CT0 ~ CT3

Instruction Code
b31
0 0

13
8 7
0 1x x x x0

nfi

SImm Data

Bit Data
bit11 bit10 bit 9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused
[LOP]
[TOP]
[CT0]
[CT1]
[CT2]
[CT3]

Flag

GA

Co

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

[d] Selections

bit 8

SE

Comments

118

Area selected by [d] selection ; becomes Imm data

* [MCx(x=0 ~ 3)] designates DATA RAMx(x=0~3) and, after transfer,increments [CTx(x=0~3).

Transfer ([source]→[destination])ntialMOV [s],[d]RAM data or register data designated by [source] is transfered to the
RAM or register designated by [destination].

Label

MOV [Source], [Destination]
Source = M0 ~ M3 *,MC0 ~ MC3 *,ALH,ALL
Destination = MC0 ~ MC3,RX,PL,RA0,WA0,LOP,TOP,CT0 ~ CT3deOperation
Description

Instruction Code13
8
1 1x x x x

nfi

b31
0 0

Bit Data[d] Selections

Bit Data

bit 3 bit 2

bit 1

bit 0

[s] Selections

DATA RAM0 ,CT0++

0

0

0

0

DATA RAM0001

DATA RAM10DATA RAM1 ,CT1++DATA RAM2 ,CT2++

0
0

0

1

0

DATA RAM2

1

1

DATA RAM3 ,CT3++

0

0

1

1

DATA RAM3

1

0

0

[RX]

0

1

0

0

DATA RAM0,CT0++

0

1

0

1

[PL]

0

1

0

1

DATA RAM1,CT1++

0

1

1

0

[RA0]

0

1

1

0

DATA RAM2,CT2++

0

1

1

1

[WA0]

0

1

1

1

DATA RAM3,CT3++

10

0

0unused1

0

0

0

no field

1

0

0

1

unused1

0

0

1[ALU LOW]

1

0

1

0

[LOP]

1

0

1

0

[ALU HIGH]

1

0

1

1

[TOP]

1

1

0

0

[CT0]

1

1

0

1

[CT1]

GA

bit11 bit10 bit 9 bit 8

30x x x x

1

1

1

0

[CT2]

1

1

1

1

[CT3]

0

0

0

0

0

0

0

0

0

0

0

1

1

Co

0

Area selected by [d] selection is data of an area selected by [s] selectio

Comments* [Mx(x=0 ~ 3)] designates DATA RAM x(x=0~3)[MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

SE

Flag

SCU User's Manual11931 30 29

26 25 24ntialLoad Immediate Command
The load immediate command transfers immediate data to the storage destination.
Unconditional transfer follows the format in Figure 4.6. Conditional transfer follows
the format in Figure 4.7. Details are on the following pages.
0

Storage
1 0 Destination
0

Immediate data

31 30 29

26 25 24

Storage
1 0 Destination
1

19 18
StatusdeFigure 4.6 Load Immediate Command Format 1 (Unconditional Transfer)

Immediate data

SE

GA

Co

nfi

Figure 4.7 Load Immediate Command Format 2 (Conditional Transfer)

120

0MVI Imm,[d]→[destination])ntialUnconditional Transfer (ImmImm data is unconditional and is transfered to the RAM or register
designated by [destination].
Imm data is signed 25 bit data.

Label

MVI Imm,[Destination]
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PCdeOperation
Description

Instruction Codeb31
24
1 0x x x x 00nfi

Imm Data

Bit Data
bit11 bit10 bit 9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

GA

Co

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

bit 8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused[TOP] ,[PC]Area selected by [d] multiple choice ; becomes Imm data

Comments* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

SE

Flag

SCU User's Manual

121

MVI Imm,[d]Z→[destination])nti
alConditional Transfer (Z=1 then Imm

When the Z flag is 1, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used as execution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],Z
Destination RAM = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PC

Instruction Codeb31
18
1 0x x x x 1 1 0 0 0 0 1

deOperation
Description0

Imm Data

nfi

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused

Flag

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

SE

Comments

122[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

MVI =Imm,[d]NZ→[destination])nti
alConditional Transfer (Z=0 then Imm

When the Z flag is 0, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used as execution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],NZ
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PCdeOperation
Description

Instruction Codeb31
18
1 0x x x x 1 1 0 0 0 0 1

0Imm Data

nfi

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

Comments* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer ,increments [CTx(x=0~3).

SE

Flag

SCU User's Manual123

MVI Imm,[d]S→[destination])nti
alConditional Transfer (S=1 then Imm

When the S flag is 1, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used asexecution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Th
address next after this command will be executed twice, once before
the subroutine and once after.

Label

MVI Imm,[Destination],S
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PC

Instruction Codeb31
18
1 0x x x x 1 1 0 0 0 1 0deOperation
Description0

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused

Flag

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

nfi

Imm Data

SE

Comments

124[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

MVI Imm,[d]NS→[destination])nti
alConditional Transfer (S=0 then Imm

When the S flag is 0, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used asexecution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],NS
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PCdeOperation
Description

Instruction Codeb31
18
1 0x x x x 1 1 0 0 0 1 00Imm Data

nfi

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

Comments* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

SE

Flag

SCU User's Manual

125

MVI Imm,[d]C→[destination])nti
alConditional Transfer (C=1 then Imm

When the C flag is 1, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used asexecution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],C
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PC

Instruction Codeb31
18
1 0x x x x 1 1 0 0 1 0 0

deOperation
Description0

Imm Data

nfi

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused

Flag

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

SE

Comments

126[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

MVI Imm,[d]NC→[destination])nti
alConditional Transfer (C=0 then Imm

When the C flag is 0, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used asexecution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],NC
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PCdeOperation
Description

Instruction Codeb31
18
1 0x x x x 1 1 0 0 1 0 0

0

Imm Data

nfi

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

Comments* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

SE

Flag

SCU User's Manual127

MVI Imm,[d],T0

Conditional Transfer (T0=1 then Imm→[destination])

When the T0 flag is 1, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used asexecution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],T0
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PC

Instruction Codeb31
18
1 0x x x x 1 1 0 1 0 0 0

de

nti
al

Operation
Description0

Imm Data

nfi

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused

Flag

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

SE

Comments

128[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

MVI Imm,[d]NT0→[destination])nti
alConditional Transfer (T0=0 then Imm

When the T0 flag is 0, Imm data is transfered to the RAM or register
designated by [destination]. Imm data is signed 19 bit data.
Can be used asexecution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],NT0
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PCdeOperation
Description

Instruction Codeb31
18
1 0x x x x 1 0 0 1 0 0 00nfi

Imm Data

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

Comments* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

SE

Flag

SCU User's Manual

129

MVI Imm,[d]ZS

→

nti
al

Conditional Transfer (Z=1 or S=1 then Imm[destination])

When the Z flag or S flag is 1, Imm data is transfered to the RAM orregister designated by [destination]. Imm data is signed 19 bit data.
Can be used asexecution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],ZS
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PC

Instruction Codeb31
18
1 0x x x x 1 1 0 0 0 1 1

deOperation
Description0

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

Flag

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

nfi

Imm Data

SE

Comments

130

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

MVI Imm,[d]NZS→ [destination])nti
alConditional Transfer (Z=0=S then Imm

When the Z flag or S flag are both 0, Imm data is transfered to the RA
or register designated by [destination]. Imm data is signed 19 bit data
Can be used as execution of the subroutine program (see instruction
code**) by sending Imm data (subtroutine begin dress) to the PC andsaving the PC (jump address after subroutine ends) value to TOP. Be
aware that the address next after this command will be executed twice
once before the subroutine and once after.

Label

MVI Imm,[Destination],NZS
Destination = MC0 ~ MC3 *,RX,PL,RA0,WA0,LOP,PCdeOperation
Description

Instruction Codeb31
18
1 0x x x x 1 0 0 0 0 1 1

0nfi

Imm Data

Bit Data
bit28 bit27 bit26
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1

GA

Co

bit29
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

[d] Selections

DATA RAM0 ,CT0++DATA RAM1 ,CT1++DATA RAM2 ,CT2++DATA RAM3 ,CT3++

[RX]
[PL]
[RA0]
[WA0]
unusedunused[LOP]
unused[PC] →
unusedunusedunused[TOP] ,[PC]Area selected by [d] selection ; becomes Imm data

Comments* [MCx(x=0 ~ 3)] designates DATA RAM x(x=0~3) and, after transfer,increments [CTx(x=0~3).

SE

Flag

SCU User's Manual131

18 17Add
Mode

1 1 0 0015 14 13 12 11 10 8 7

H 0 dirRAM

Immediate datade31 30 29 28 27

ntial

DMA Command
DMA commands transfer data of an external and DSP internal RAM through anexternal bus. There are two methods, one of which is setting the transfer word
number directly by Imm data, and the other is setting the internal RAM transfer
word number by designating the number of the internal data RAM. The first
method is shown in Figure 4.8 and the second method is shown in Figure 4.9.
Details of the command are shown on the pages that follow.

Figure 4.8 DMA Command Format 1

31 30 29 28 27

18 17

15 14 13 12 11 10 8 7

Add
Mode

H 1 dirRAMnfi

1 1 0 0

SE

GA

Co

Figure 4.9 DMA Command Format 2

132

3 2

0

SOURCE

→ RAM)DMA Transfer (D0[31-0]ntial

DMA D0,[RAM],SImm
Operation
Description

D0[31-0] data is transfered to RAM . The external address registerand transfer word number register are updated (added) according to
the address add number. The transfer word number register is a
register for storing the transfer word number in long word units. This
word number is either 0 or transfer ends when forced to end.

Label

DMA D0,[Destination],CounterdeDestination = M0 ~ M3 *Instruction Codeb31
28
1 1 0 0nfi

Co

Bit Data
Add Mode Selections
bit17 bit16 bit15000Address Add 0100
Address Add 1010
Address Add 2110
Address Add 4001
Address Add 8101
Address Add 16011
Address Add 32111
Address Add 64

SImm Data

Bit Data
bit9 bit8
0
0
1
1

0
1
0
1

Selections
DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3

T0 ; becomes 1.

GA

Flag

0

7
17 15
x x x 0 0 0 0 0x x

SE

Comments

SCU User's Manual* [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3).
**When the END signal informing you that transfer end from outside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command andbecomes DMA0~DMA64.
Add number is1 when address add number designation is omitted.
The transfer source address is set in advance to RA0 and the transfer
destination RAM address is set in advance to CTx.

133

DMA [RAM],D0,SImm→ D0[31-0])ntial

DMA Transfer (RAMOperation
Description

RAM data is transfered to D0[31-0]. The external address register andtransfer word number register are updated (added) according to theaddress add number. Only add numbers 0 and 1 are valid for the A
Bus and the write unit is 32bit. All add numbers (0 - 64) are valid for
the B-Bus. Write unit is16bit; 32bit data is divided in half and written atintervals of16X (0-64). The transfer word number register is a registerfor storing the transfer word number in long word units. This word
number is either 0 or transfer ends when forced to end.

Label

DMA [Source],D0,Counter

Instruction Codeb31
1 1 0 0de

Source = Mo ~ M3 *717 15x x x 0 0 1 0 0x x

0nfi

SImm Data

Flag

0
0
1
1

0
1
0
1

Selections
DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3

GA

T0 ; becomes 1.

SE

Comments134

Bit Data
bit9 bit8Co

Bit Data
Add Mode Selections
bit17 bit16 bit15000Address Add 0100
Address Add 1010
Address Add 2110
Address Add 4001
Address Add 8101
Address Add 16011
Address Add 32111
Address Add 64* [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3).
**When the END signal informing you that transfer end from outside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command andbecomes DMA0~DMA64.
Add number is 1 when address add number designation is omitted.
The transfer source RAM address is set in advance to CTx and thetransfer destination address is set in advance to WA0.

DMA D0,[RAM],[s]→ RAM )ntial

DMA Transfer (D0[31-0]

Operation
Description[s] data designated by bit0~2 is treated as a transfer counter, and only
numbers displayed transfer D0[31-0] data to the RAM. External
address register and transfer word number register are updated(added) according to the address add number. The transfer word
number register stores transfer word numbers in long word units. This
word number becomes 0 or transfer ends when forced to end.

Label

DMA D0,[Destination],[Counter]deCounter = M0 ~ M3 *,MC0~MC3*
Destination = M0~M3 *,PRG *Instruction
Code

Valid only for A-Bus
Address add is 32bit units.

b31
28
1 1 0 0nfi

bit 15 Add Mode Selections
Address Add 001
Address Add 1

RAM Selections

Co

Bit Data
bit 10 bit9 bit8
0
0
0
1
0
0
0
0
1
1
0
1
1
0
0

7

0 0x 0 1 0 0x x x

DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3
PROGRAM RAM

bit 2
0
0
0
0
1
1
1
1

Bit Data
bit1 bit 0
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
x x x

[s] Selections
DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3
DATA RAM 0,CT0++DATA RAM 1,CT1++DATA RAM 2,CT2++DATA RAM 3,CT3++

T0 ; becomes 1. **CTx(x0~3) ; incremented when b2=1. When b2=0, there is no change

Comments* [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3). MCx(x=0~3) selects
DATA RAM x(x=0~3), and after transfer increments CTx(x0~3).
PRG selects program RAM.
**When the END signal informing you that transfer end from outside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command an
becomes DMA0~DMA1.
Add number is 1 when address add number designation is omitted.
The transfer source address is set in advance to RA0 and the transfer
destination RAM address is set in advance to CTx.

SE

GA

Flag

SCU User's Manual135

DMA Transfer (RAM

→ D0[31-0]

)

nti
al

DMA [RAM],D0,[s][s] data designated by bit0~2 is treated as a transfer counter, and only
numbers displayed transfer RAM data to DO[31-0] data. External
address register and transfer word number register are updated(added) according to the address add number. The transfer word
number register stores transfer word numbers in long word units. But
only add numbers 0 and 1 are valid for A-Bus, and write units are 32
bits. For B-Bus, all add numbers (0-64) are valid. Write units are 16 bit;
32 bit data is divided in half and written at intervals of 16bitX (0-64). Th
transfer word number register stores transfer words in long word units.
This word number becomes 0 or transfer ends when forced to end.

Label

DMA D0,[Destination],[Counter]
Counter = M0 ~ M3 *,MC0~MC3*
Source = M0~M3 *,PR*
Bit Data
Add Mode Selections
bit17 bit16 bit15000Address Add 0100
Address Add 1010
Address Add 2110
Address Add 400
Address Add 8110
Address Add 16101
Address Add 32111
Address Add 64
1

Bit Data[s] Selections
bit 2 bit1 bit 0
DATA RAM 0
0
0
0
1
0
0
DATA RAM 10
10
DATA RAM 21
1
0
DATA RAM 3001
DATA RAM 0,CT0++101DATA RAM 1,CT1++011DATA RAM 2,CT2++1
1
1DATA RAM 3,CT3++b31
1 1 0 0Co

nfi

Instruction
Code

de

Operation
Description

7
17x x x 0 1 1 0 0x x

Flag

GA

Bit Data
bit9 bit8

SE

Comments

136

0
0
1
1

0
1
0
1

0
x x x

RAM Selections
DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3

T0 ; becomes 1. **CTx(x=0~3) ; incremented when b2=1. No changes when b2=0.
* [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3). MCx(x=0~3) selects
DATA RAM x(x=0~3), and after transfer increments CTx(x0~3).
**When the END signal informing you that transfer end from outside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command an
becomes DMA0~DMA64.
Add number is 1 when address add number designation is omitted.
The transfer source RAM address is set in advance to CTx and thetransfer destination address is set in advance to WA0.

DMA Transfer (D0[31-0]→ RAM) by HOLD Statusnti
al

DMAH D0,[RAM],SImm
Operation
Description

D0[31-0] data is transfered to the RAM. External address register andtransfer word number register save the value at the time transfer
begins. The transfer word number register stores the transfer word
number in long word units. This word number becomes 0 or becomes
the transfer end when forced to end.

Label

DMAH D0,[Destination],[Counter]deDestination = M0~M3 *,PR*

Instruction Codeb31
28
1 1 0 017 15
7
0 0x 0 1 0 0x x x

Bit Data
bit 10 bit9 bit8
0
0
0
1
0
0
0
1
0
1
1
0
1
0
0

nfi

bit 15 Add Mode Selections
Address Add 001
Address Add 1

Flag

RAM Selections
DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3
PROGRAM RAM

T0 ; becomes 1.*** [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3).
PR selects PROGRAM RAM**When the END signal informing you that transfer end from outside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command an
becomes DMAH0~DMAH1.
Add number is 1 when address add number designation is omitted.
The transfer source address is set in advance to RA0 and the transfer
destination RAM address is set in advance to CTx.

SE

GA

Comments

SImm Data

Co

Valid only for A-Bus
Address add is 32 bit unit.

0
x x x

SCU User's Manual137

DMA Transfer (RAM

→ D0[31-0]) by HOLD Statusnti
al

DMAH [RAM],D0,SImm
Operation
Description

RAM data is transfered to D0[31-0]. The external address register andtransfer word number register save the value when transfer starts.
The transfer word number register is a register for storing the transfer
word number in long word units. This word number is either 0 ortransfer ends when forced to end.

Label

DMA H [Source],D0,Counter

Instruction Codeb31
1 1 0 0de

Source = Mo ~ M3 *717 15x x x 1 0 1 0 0x x

0SImm Data

Bit Data
bit9 bit8

nfi

Bit Data
Add Mode Selections
bit17 bit16 bit15000Address Add 0100
Address Add 1010
Address Add 2110
Address Add 4001
Address Add 8101
Address Add 16011
Address Add 32111
Address Add 64

0
1
0
1

DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3

Co

Flag

GA

T0 ; becomes 1.**SE

Comments

138

0
0
1
1

Selections* [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3).
**When the END signal informing you that transfer end fromoutside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command andbecomes DMAH0~DMAH64.
Add number is 1 when address add number designation is omitted.
The transfer source RAM address is set in advance to CTx and thetransfer destination address is set in advance to WA0.

DMAH D0,[RAM],[s]→ RAM ) by HOLD Statusntial

DMA Transfer (D0[31-0]

Operation
Description[s] data designated by bit0~2 is treated as transfer counter, and only
numbers displayed transfer RAM data to D0(31-0) data. External
address register and transfer word number register save the value,
when starting transfer, to the address add number. The transfer word
number register stores transfer word numbers in long word units. This
word number becomes 0 or transfer ends when forced to end.

Label

DMA H D0,[Destination],[Counter]deCounter = M0 ~ M3 *,MC0~MC3*
Destination = M0~M3 *,PR*

Instruction
Code

Valid only for A-Bus
Address add is 32bit units.

nfi

bit 15 Add Mode Selections
Address Add 001
Address Add 1b31
28
1 1 0 0Co

Bit Data
bit 10 bit9 bit8
0
0
0
1
0
0
0
0
1
1
0
1
1
0
0

7

0 0x 1 1 0 0x x x

RAM Selections

DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3

0
0
0
0
1
1
1
1

Bit Data
bit1 bit 0
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

[s] Selections
DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3
DATA RAM 0,CT0++DATA RAM 1,CT1++DATA RAM 2,CT2++DATA RAM 3,CT3++GAPROGRAM RAM

bit 2

0
x x x

T0 ; becomes 1. **CTx(x0~3) ; incremented when b2=1. When b2=0, there is no change

Comments* [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3). MCx(x=0~3) selects
DATA RAM x(x=0~3), and after transfer increments CTx(x0~3).
**When the END signal informing you that transfer end from outside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command an
becomes DMAH0~DMAH1.
Add number is 1 when address add number designation is omitted.
The transfer source address is set in advance to RA0 and the transfer
destination RAM address is set in advance to CTx.

SE

Flag

SCU User's Manual139

DMA Transfer (RAM

→ D0[31-0]) by HOLD Statusntial

DMA [RAM],D0,[s]Operation
Description[s] data designated by bit0~2 is treated as transfer counter, and only
numbers displayed transfer RAM data to D0[31-0] data. External
address register and transfer word number register save the value
when starting transfer. The transfer word number register storestransfer words in long word units. This word number becomes 0 ortransfer ends when forced to end.

Label

DMAH [Source],DO,[Counter]

Bit Data
Add Mode
bit17 bit16 bit15 Selections
00
Address Add 0010
Address Add 1001
Address Add 2011
Address Add 40
Address Add 8001
Address Add 16101
Address Add 32
011
Address Add 64
1
1
1

Bit Data[s] Selections
bit 2 bit1 bit 0
Data RAM 0
0
0
0
1
0
0
Data RAM 10
10
Data RAM 21
1
0
Data RAM 3001
Data RAM 0 ,CT0++1
01Data RAM 1 ,CT1++011Data RAM 2 ,CT2++1
11
Data RAM 3 ,CT3++

Co

nfi

Instruction
Code

de

Counter = M0 ~ M3 *,MC0~MC3*
Source = M0~M3 *,PR*b31
1 1 0 07
17x x x 1 1 1 0 0x x

Flag

GA

Bit Data
bit9 bit8

SE

Comments

140

0
0
1
1

0
1
0
1

0
x x x

RAM Selections
DATA RAM 0
DATA RAM 1
DATA RAM 2
DATA RAM 3

T0 ; becomes 1. **CTx(x=0~3) ; incremented when b2=1. No changes when b2=0.
* [MCx(x=0 ~ 3)] selects DATA RAM x(x=0~3). MCx(x=0~3) selects
DATA RAM x(x=0~3), and after transfer increments CTx(x0~3).
**When the END signal informing you that transfer end from outside
has been entered, T0; becomes 0.
Designating address-add adds an add number after the command andbecomes DMAH0~DMAH64.
Add number is 1 when address add number designation is omitted.
The transfer source RAM address is set in advance to CTx and thetransfer destination address is set in advance to WA0.

31 30 29 28 27 26 25 24

1 1 0 1nti
alJUMP Commands
Jump commands are realized by storing immediate data in the program counter.
Figure 4.10 shows the Jump command format. Details of the command are shown in
the next few pages.
19 18

8 7

Status0

Immediate

SE

GA

Co

nfi

de

Figure 4.10 Jump Command Format

SCU User's Manual141Unconditional Jump
Jumps according to address data (Imm).

Label

JMP [address]

Instruction Codeb31
1 1 0 125
19
0 0 0 0 0 0 0

deOperation
Descriptionntial

JMP Imm

7

Co

nfi

Imm Data

Flag

GA

No change

SE

Comments

1420Conditional Jump (Z = 1)ntial

JMP Z, Imm

When the Z flag is 1, jump is in accordance with address data (Imm).

Label

JMP Z,[address]

Instruction Code25
19
1 1 0 0 0 0 1

70

Imm Data

Co

nfi

b31
1 1 0 1deOperation
Description

No change

GA

Flag

SE

Comments

SCU User's Manual143

Conditional Jump (Z=0)

nti
al

JMP NZ,Imm

When the Z flag is 0, jump is in accordance with address data (Imm).

Label

JMP NZ,[address]

Instruction Codeb31
1 1 0 125
19
1 0 0 0 0 0 1

deOperation
Description

7

Co

nfi

Imm Data

Flag

GA

No change

SE

Comments

1440Conditional Jump (S=1)

nti
al

JMP S,Imm

When the S flag is 1, jump is in accordance with address data (Imm).

Label

JMP S,[address]

Instruction Code25
19
1 1 0 0 0 1 0

70

Imm Data

Co

nfi

b31
1 1 0 1deOperation
Description

No change

GA

Flag

SE

Comments

SCU User's Manual145

Conditional Jump (Z=0)

nti
al

JMP NS,Imm

When the S flag is 0, jump is in accordance with address data (Imm).

Label

JMP NS,[address]

Instruction Codeb31
1 1 0 125
19
1 0 0 0 0 1 0deOperation
Description

7

Co

nfi

Imm Data

Flag

GA

No change

SE

Comments

1460Conditional Jump (C=1)

ntial

JMP C,Imm

When the C flag is 1, jump is in accordance with address data (Imm).

Label

JMP C,[address]

Instruction Code25
19
1 1 0 0 1 0 0

70

Imm Data

Co

nfi

b31
1 1 0 1deOperation
Description

No change

GA

Flag

SE

Comments

SCU User's Manual147

Conditional Jump (C=0)

ntial

JMP NC,Imm

When the C flag is 0, jump is in accordance with address data (Imm).

Label

JMP NC,[address]

Instruction Codeb31
1 1 0 125
19
1 0 0 0 1 0 0

deOperation
Description

7

Co

nfi

Imm Data

Flag

GA

No change

SE

Comments

1480Conditional Jump (T0=1)

ntial

JMP T0,Imm

When the T0 flag is 1, jump is in accordance with address data (Imm).

Label

JMP T0,[address]

Instruction Code25
19
1 1 0 1 0 0 0

70

Imm Data

Co

nfi

b31
1 1 0 1deOperation
Description

No change

GA

Flag

SE

Comments

SCU User's Manual149

Conditional Jump (T0=0)

nti
al

JMP NT0,Imm

When the T0 flag is 0, jump is in accordance with address data (Imm).

Label

JMP NT0,[address]

Instruction Codeb31
1 1 0 125
19
1 0 01 0 0 0

deOperation
Description

7

Co

nfi

Imm Data

Flag

GA

No change

SE

Comments

1500Conditional Jump (Z=1 or S=1)nti
al

JMP ZS,Imm

When the Z flag or S flag is 1, jump is in accordance with address data(Imm).

Label

JMP ZS,[address]

Instruction Code25
19
1 1 0 0 0 1 1

7

0

Imm Data

Co

nfi

b31
1 1 0 1deOperation
Description

No change

GA

Flag

SE

Comments

SCU User's Manual151

Conditional Jump (Z=S=0)nti
al

JMP NZS,Imm

When the Z flag and S flag are 0, jump is in accordnce with address d(Imm).

Label

JMP NZS,[address]

Instruction Codeb31
1 1 0 125
19
1 0 0 0 0 1 1

deOperation
Description

7

Co

nfi

Imm Data

No change

GA

Flag

SE

Comments

152

0

nti
al

LOOP BOTTOM Commands
Loop Bottom commands repeat one to several steps of a program. Figure 4.11 shows
the Jump command format. Details of the command are shown in the next few
pages.
31 30 29 28 27

0

1 1 1 0 MOD

SE

GA

Co

nfi

de

Figure 4.11 Loop Bottom Command Format

SCU User's Manual

153

BTM

Repeat Process Criterion
There is no repeat when the [LOP] flag is 0. Otherwise the program
counter returns to [TOP].
Does nothing when the [LOP] flag is 0; otherwise, it returns the
program counter to [TOP].

Label

BTM

Instruction Code

Co

nfi

b31 29 27
1 1 1 0 0

de

nti
al

Operation
Description

LOP ; decremented when LOP≠ 0. Ends when LOP=0.

GA

Flag

SE

Comments

1540

1 Step Repeat

nti
al

LPS

Repeats next 1 step until the [LOP] register is 0.

Label

LPS

Instruction Code

0

Co

nfi

b31 29 27
1 1 1 0 1

deOperation
Description

LOP ; decremented when LOP≠ 0. Ends when LOP=0.

GA

Flag

After the process ends, PC executes LOP+1 time then ends.

SE

Comments

SCU User's Manual15531 30 29 28 27

ntial

END Command
The END command stops the program currently being executed. Figure 4.12 shows
the END command format. Details of the command are shown in the next two
pages.
0

1 1 1 1 IE

SE

GA

Co

nfi

de

Figure 4.12 END Command Format

156

STOP
Stops the program.

Label

END

Instruction Code

0

Co

nfi

b31 29 27
1 1 1 1 0

deOperation
Description

nti
al

END

EX ; is0.

GA

Flag

SE

Comments

SCU User's Manual157

Program End

nti
al

ENDI

Stops the program, and sets the E flag (program end interrupt flag).

Label

ENDI

Instruction Code

Co

nfi

b31 29 27
1 1 1 1 1

deOperation
Description

E ; is 1
EX ; is0.

GA

Flag

SE

Comments

158

0

APPENDIX

SE

GA

Co

nfi

de

nti
al

This appendix contains a list of SCU register address maps.

SCU User's Manual

159

160
D1MOD

D1W22

D2MOD

D2W26 D2W25 D2W24 D2W23

D0WUP

D1W8

D1W7

D2W21 D2W20 D2W19

D1BK D0BK

D2RUP

D2W18 D2W17 D2W16

D2WT D2MV

D1W2

D1W1

D2W8

D2W6

D2W4

D2W3

D2W2

D2R4 D2R3 D2R2

D2W1

D2W0

D2R1 D2R0

D1FT0

D1WT D1MV

D0WT D0MV

nti
al

D2FT2

DSTOP

D2FT0

DOWT DOMV

D2FT1

D2GO

D2EN
D2WUP

D2WA2 D2WA1 D2WA0

D2C5 D2C4 D2C3 D2C2 D2C1` D2C0

D2W5

D1FT1

D2RA

D2C7 D2C6

D2W7

D1FT2

D1GO
D1WUP

D1EN

D1C0

D1W0

D1R0

D1WA2 D1WA1 D1WA0

D2R5

D1W3

D1C4 D1C3 D1C2 D1C1

D1W4

D1R4 D1R3 D1R2 D1R1

D0FT2 D0FT1 D0FT0

D1RA

D2C11 D2C10 D2C9 D2C8

D2W11 D2W10 D2W9

de
D2W15 D2W14 D2W13 D2W12

D2W5

D1C6 D1C5

D1W6

D1R6 D1R5

D2R19 D2R18 D2R17 D2R16 D2R15 D2R14 D2R13 D2R12 D2R11 D2R10 D2R9
D2R8 D2R7 D2R6

D1RUP

D1W10 D1W9

D1C11 D1C10 D1C9 D1C8 D1C7

D1W17 D1W16 D1W15 D1W14 D1W13 D1W12 D1W11

nfi

D1W21 D1W20 D1W19 D1W18

DACS0 DACSB DACSA

D2W22

D0RUP

D1R18 D1R17 D1R16 D1R15 D1R14 D1R13 D1R12 D1R11 D1R10 D1R9
D1R8 D1R7

Co

D1W25 D1W24 D1W23

D2R26 D2R25 D2R24 D2R23 D2R22 D2R21 D2R20

D1W26

D0W0

D0GO

D0W1

D0R1 D0R0

D0EN

D0W2

D0WA2 D0WA1 D0WA0

D0W3

D0C7 D0C6 D0C5 D0C4 D0C3 D0C2 D0C1 D0C0

D0W4

D0C8

D0W5

D0R5 D0R4 D0R3 D0R2

D0RA

D0W6

D0R6

D0C19 D0C18 D0C17 D0C16 D0C15 D0C14 D0C13 D0C12 D0C11 D0C10 D0C9

D0W7

D0W8

D0W15 D0W14 D0W13 D0W12
D0W11 D0W10 D0W9

D0W17 D0W16

D0R19 D0R18 D0R17 D0R16 D0R15 D0R14 D0R13 D0R12 D0R11 D0R10 D0R9 D0R8 D0R7

D0W23 D0W22 D0W21 D0W20 D0W19 D0W18

D1R26 D1R25 D1R24 D1R23 D1R22 D1R21 D1R20 D1R19

D0MOD

GA

SE
D0W26 D0W25 D0W24

D0R26 D0R25 D0R24 D0R23 D0R22 D0R21 D0R20

Register names are shown in parenthesis.

SCU User's Manual

161

25FE00CC(—)

25FE00C8(VER)

25FE00C4(RSEL)

25FE00C0(—)

25FE00BC(AIAK)

EP
9
Z

C
V

Co

T0
E
EX

LE

A2LN1 A2LN0

A0WPC A0RPC A0EWT A0BW3 A0BW2 A0BW1 A0BW0
A0NW3 A0NW2 A0NW1 A0NW0 A0LN1 A0LN0

T198
T1MD

IMS13 IMS12 IMS11 IMS10 IMS9 IMS8

RD6

RA6

PD6

RD5

RA5

PD5

P5

RD4

RA4

PD4

P4

RA2

PD2

P2

RD3 RD2

RA3

PD3

P3

PD0

P0

RD1

RD0

RA1 RA0

PD1

P1

IST5 IST4

A3SZ

A1SZ

AIACK

IST0

VER3 VER2 VER1 VER0RSEL

ARFEN ARWT3 ARWT2 ARWT1 ARWT0A2SZ A3PRO A3WPC A3RPC A3EW1 A3BW3 A3BW2 A3BW1 A3BW0 A3NW3 A3NW2 A3NW1 A3NW0 A3LN1 A3LN0

A1LN1 A1LN0

IST3 IST2 IST1

nti
al

IST6

IMS7 IMS6 IMS5 IMS4 IMS3 IMS2 IMS1 IMS0

TENB

T197 T196 T195 T194 T193 T192 T191 T190

IST13 IST12 IST11 IST10 IST9 IST8 IST7

de

RD7

RA7

PD7

P6

A0SZ A1PRO A1WPC A1RPC A1EW1 A1BW3 A1BW2 A1BW1 A1BW0 A1NW3 A1NW2 A1NW1 A1NW0

IMS15

nfi

IST31 IST30 IST29 IST28 IST27 IST26 IST25 IST24 IST23 IST22 IST21 IST20 IST19 IST18 IST17 IST16

RD8

PD8

P7

T0C9 T0C8 T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0

RD15 RD14 RD13 RD12 RD11 RD10 RD9

PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9E8RD31 RD30 RD29 RD28 RD27 RD26 RD25 RD24 RD23 RD22 RD21 RD20 RD19 RD18 RD17 RD16

25FE00B4(ASR1) A2PRO A2WPC A2RPC A2EWT

25FE00B8(AREF)

PR

GA

PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18

25FE00B0(ASR0) A0PRO

25FE00AC(—)

25FE00A8(—)

25FE00A4(IST)

25FE00A0(IMS)

25FE009C(—)

25FE0098(T1MD)

25FE0094(T1S)

25FE0090(T0C)

25FE008C(PDD)

25FE0088(PDA)

25FE0084(PPD)

25FE0080(PPAF)SEARFENARWT3-0
A0BW3-0
A0EWT
A0LN1-0
A0PRD
A0RPC
A0NW3-0
A0SZ
A0WPC
A1BW3-0
A1EWT
A1LN1-0
A1NW3-0
A1PRD
A1RPC
A1SZ
A1WPC
A2EWT
A2LN1-0
A2PRD
A2RPC
A2SZ
A2WPC
A3BW3-0
A3EWT
A3LN1-0
A3NW3-0
A3PRD
A3RPC
A3SZ
A3WPC
C
DACSA
DACSB
DACSD
DDMV
DDWT
DSTOP
D0BK
D0C19-0
D0EN

25FE00B8H
25FE00B8H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B0H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE00B4H
25FE0080H
25FE007CH
25FE007CH
25FE007CH
25FE007CH
25FE007CH
25FE0060H
25FE007CH
25FE0008H
25FE0010H

43-0
27 - 2428
19 - 1831
29
23 - 20
16
30
11 - 8
12
3-2
7-4
15
13
0
14
28
19 - 1831
29
16
30
11 - 8
12
3-2
7-4
15
13
0
14
20
20
21
22
0
1
0
16
19 - 08

A-Bus interrupt acknowledge output valid bit(=0: invalid / =1: valid)
A-Bus refresh output valid bit(=0: invalid/=1: valid)
A-Bus refresh wait number
CS0 space, burst cycle wait number set bit
CS0 space, external wait effective bit (=0: invalid/=1: valid)CS0 space, burst length set bit
CS0 space, previous read effective bit (=0: invalid/=1: valid)CS0 space, pre-charge insert bit after readCS0 space, normal cycle wait number set bit
CS0 space, bus size set bit
CS0 space, pre-charge insert bit after write
CS1 space, burst cycle wait number set bit
CS1 space, external wait effctive bit (=0: invalid/=1: valid)
CS1 space, burst length set bit
CS1 space, normal cycle wait number set bit
CS1 space, previous read effective bit (=0: invalid/=1: valid)
CS1 space, pre-charge insert bit after readCS1 space, bus size set bit
CS1 space, pre-charge insert bit after write
CS2 space, external wait effctive bit (=0: invalid/=1: valid)CS2 space, burst length set bit
CS2 space, previous read effective bit (=0: invalid/=1: valid)CS2 space, pre-charge insert bit after readCS2 space, bus size set bit
CS2 space, pre-charge insert bit after write
Dummy space, burst cycle wait number set bit
Dummy space, external wait effctive bit (=0: invalid/=1: valid)
Dummy space, burst length set bit
Dummy space, normal cycle wait number set bit
Dummy space, previous read effective bit (=0: invalid/=1: valid)
Dummy space, pre-charge insert bit after read
Dummy space, bus size set bit
Dummy space, pre-charge insert bit after write
DSP program control port, Carry flag
DMA A-Bus Access Flag (=0: no access/=1: access)
DMA B-Bus Access Flag (=0: no access/=1: access)DMA DSP-Bus Access Flag (=0: no access/=1: access)
DSP side DMA operate flag (=0: stop/=1: operate)
DSP side DMA standby flag (=0: stop/=1: standby)
DMA force-stop bit (=0: DMA operable/=1: DMA force stop)
DMA level 0 interrupt flag (=0: stop/=1: interrupt)
DMA level 0 transfer byte number
DMA level 0 enable bit (=0: Disable/=1: Enable)

Co

0

GA

SE
162

Description

nti
al

Bit

de

Address
25FE00A8H

nfi

Acronym
AIACK

D0GO
D0MOD
D0MV
D0RA

25FE0010H
25FE0014H
25FE007CH
25FE000CH

0
24
4
8

D0RUP
D0R26-0
D0WA2-0

25FE0014H
25FE0000H
25FE000CH

16
26 - 0
2-0

D0WT
D0WUP
D0W26-0
D1BK
D1C11-0
D1EN
D1FT2-0

25FE007CH
25FE0014H
25FE0004H
25FE007CH
25FE0028H
25FE0030H
25FE0034H

58
26 - 017
11 - 0
8
2-0

D1GO
D1MOD
D1MV
D1RA

25FE0030H
25FE0034H
25FE007CH
25FE002CH

0
24
8
8

D1RUP
D1R26-0

25FE0034H
25FE0020H

16
26 - 0Description
DMA level 0 starting factor selection bit=000B: V-Blank-IN receive and enable bit set=001B: V-Blank-OUT receive and enable bit set=010B: H-Blank-IN receive and enable bit set=011B: Timer 0 receive and enable bit set=100B: Timer 1 receive and enable bit set=101B: Sound Req receive and enable bit set=110B: Sprite draw end and enable bit set=111B: DMA start bit set and enable bit set

nti
al

Bit
2-0

DMA level 0 start bit (=0: stop =1: start)
DMA level 0 mode bit (=0: direct mode/=1: indirect mode)
DMA level 0 operating flag (=0: stop/=1: start)
DMA level 0 read address add value(=0: no add/=1: adds 4 byte)
DMA level 0 read address update bit
DMA level 0 read address
DMA level 0 write address add value=000B: no addition=001B: adds 2 bytes=010B: adds 4 bytes=011B: adds 8 bytes=100B: adds 16 bytes=101B: adds 32 bytes=110B: adds 64 bytes=111B: adds 128 bytes
DMA level 0 standby flag (=0: stop/=1: standby)
DMA level 0 write address update bit
DMA level 0 write address
DMA level 1 interrupt flag (=0: stop/=1: interrupt)
DMA level 1 transfer byte number
DMA level 1 enable bit (=0: Disable/=1: Enable)
DMA level 1 starting factor selection bit=000B: V-Blank-IN receive and enable bit set=001B: V-Blank-OUT receive and enable bit set=010B: H-Blank-IN receive and enable bit set=011B: Timer 0 receive and enable bit set=100B: Timer 1 receive and enable bit set=101B: Sound Req receive and enable bit set=110B: Sprite draw end and enable bit set=111B: DMA start bit set and enable bit set
DMA level 1 start bit (=0: stop/=1: start)
DMA level 1 mode bit (=0: direct mode/=1: indirect mode)
DMA level 1 operating flag (=0: stop/=1: start)
DMA level 1 read address add value(=0: no add/=1: adds 4 bytes)
DMA level 1 read address update bit
DMA level 1 read addressdeAddress
25FE0014H

SE

GA

Co

nfi

Acronym
D0FT2-0

SCU User's Manual163

25FE007CH
25FE0034H
25FE0024H
25FE0048H
25FE0050H
25FE0054H

98
26 - 0
11 - 0
8
2-0

D2G0
D2MOD
D2MV
D2RA

25FE0050H
25FE0054H
25FE007CH
25FE004CH

0
24
12
8

D2RUP
D2R26-0
D2WA2-0

25FE0054H
25FE0040H
25FE004CH

16
26 - 0
2-0

D2WT
D2WUP
D2W26-0
E
EP

25FE007CH
25FE0054H
25FE0044H
25FE0080H
25FE0080H

13
8
26 - 0
18
25

GA

SE
164

DMA level 1 write address add value=000B:does not add=001B: adds 2 bytes=010B: adds 4 bytes=011B: adds 8 bytes=100B: adds 16 bytes=101B: adds 32 bytes=110B: adds 64 bytes=111B: adds 128 bytes
DMA level 1 standby flag (=0: stop/=1: standby)
DMA level 1 write address update bit
DMA level 1 write address
DMA level 2 transfer byte number
DMA level 2 enable bit (=0: Disable/=1: Enable)
DMA level 2 starting factor selection bits
=000B: V-Blank-IN receive and enable bit set=001B: V-Blank-OUT receive and enable bit set=010B: H-Blank-IN receive and enable bit set=011B: Timer 0 recieve and enable bit set=100B: Timer 1 recieve and enable bit set=101B: Sound Req receive and enable bit set=110B: Sprite draw end and enable bit set=111B: DMA start bit set and enable bit set
DMA level 2 start bit (=0: stop/=1: operation)
DMA level 2 mode bit (=0: direct mode/=1: indirect mode)
DMA level 2 operation flag (=0: stop/=1: operation)
DMA level 2 read address add value(=0: no add/=1: adds 4 bytes)
DMA level 2 read address update bit
DMA level 2 read address
DMA level 2 write address add value=000B: no addition=001B: adds 2 bytes=010B: adds 4 bytes=011B: adds 8 bytes=100B: adds 16 bytes=101B: adds 32 bytes=110B: adds 64 bytes=111B: adds 128 bytes
DMA level 2 standby flag (=0: stop/=1: standby)
DMA level 2 write address update bit
DMA level 2 write address
DSP Program control port, Program end interrupt flag
DSP Program control port, Temporary stop execution flag during
program execution(=0: don't execute / =1: execute)

nti
al

D1WT
D1WUP
D1W26-0
D2C11-0
D2EN
D2FT2-0

Description

de

Bit
2-0

nfi

Address
25FE002CH

Co

AcronymD1WA2-0

EX

25FE0080H

16

IMS0
IMS1
IMS2
IMS3
IMS4
IMS5
IMS6
IMS7
IMS8
IMS9
IMS10
IMS11
IMS12
IMS13
IMS15
IST0
IST1
IST2
IST3

25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A0H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H

0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
0
1
2
3

IST4
IST5
IST6
IST7
IST8
IST9
IST10
IST11
IST12
IST13
IST31-16
LE

25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE00A4H
25FE0080H

4
5
6
7
8
9
10
11
12
13
31-16
15

PD31-0PR

25FE0084H
25FE0080H

31 - 026

DSP Program Control Port, Program Step Execution Control Bit(=0: don't execute / =1: execute)
DSP Program Control Port, Program Execution Control Bit(=0: don't execute / =1: execute)
V-Blank-IN Interrupt Mask Bit
V-Blank-OUT Interrupt Mask Bit
H-Blank-IN Interrupt Mask Bit
Timer 0 Interrupt Mask Bit
Timer 1 Interrupt Mask Bit
DSP End Interrupt Mask Bit
Sound Request Interrupt Mask Bit
SMPC Interrupt Mask Bit
PAD Interrupt Mask Bit
Level 2-DMA End Interrupt Mask Bit
Level 1-DMA End Interrupt Mask Bit
Level 0-DMA End Interrupt Mask Bit
DMA Illegal Interrupt Mask Bit
Sprite Draw End Interrupt Mask Bit
A-Bus Interrupt Mask Bit
V-Blank-IN Interrupt Status Bit
V-Blank-OUT Interrupt Status Bit
H-Blank-IN Interrupt Status Bit
Timer 0 Interrupt Status BitTimer 1 Interrupt Status Bit
DSP End Interrupt Status Bit
Sound request Interrupt Status Bit
SMPC Interrupt Status Bit
PAD Interrupt Status Bit
Level 2-DMA End Interrupt Status Bit
Level 1-DMA End Interrupt Status Bit
Level 0-DMA End Interrupt Status Bit
DMA Illegal Interrupt Status Bit
Sprite Draw End Interrupt Status Bit
Outside Interrupt 15-0 Status Bit
DSP Program Control Port, Program Counter Load Enable Bit (=0:no execute/=1: execute)
DSP Program RAM Data PortDSP Program Control Port, Pause Cancel Flag while program is
executing (=0: no execute/=1: execute)
DSP Program RAM Address
DSP Data RAM Address
DSP Data RAM Data PortSDRAM Selection Bit (=0: 2 Mbit x 2 / =1: 4 Mbit x 2)
DSP Program Control Port, Sine Flag

Co

GA
25FE0080H
25FE0088H
25FE008CH
25FE00C4H
25FE0080H

7-0
7-0
31 - 0
0
22

SE

P7-0
RA7-0
RD31-0RSELS

Description

nti
al

Bit
17

de

Address
25FE0080H

nfi

AcronymES

SCU User's Manual

165

0
23
9-0
8

T1S8-0V
VER3-0Z

25FE0094H
25FE0080H
25FE00C8H
25FE0080H

8-0
19
3-0
21

Timer Enable Bit (=0: OFF / =1: ON)
DSP Program Control Port, D0 Bus Use DMA Execute Flag
Timer 0 Compare Data
Timer 1 ModeBit=0: occurs at each line
=1: occurs only at lines indicated by Timer 0
Timer 1 Set Data
DSP Program Control Port, Overflow FlagSCU Chip Version Number
DSP Program Control Port, Zero Flagnti
al

25FE0098H
25FE0080H
25FE0090H
25FE0098H

SE

GA

Co

nfi

de

TENB
T0
T0C9-0T1MD

166

INDEXnti
alNumbers within ( ) shows the page of the “First” heading.

Numeric

1 command Repeat Execution...................................................................................... 89

Alphabetic

A-Bus ................................................................................................................................ ii

A-Bus Control Register ................................................................................................. 61
A-Bus Interrupt Acknowledge .................................................................................... 61

A-Bus Interrupt Acknowledge Register ..................................................................... 61deA-Bus Interrupt Acknowledge Map ........................................................................... 14
A-Bus Refresh Register ........................................................................................... 13, 71
A-Bus Refresh Register Map ........................................................................................ 13
A-Bus Refresh Wait Number ........................................................................................ 71
A-Bus Set Register (CS0, 1 spaces) .............................................................................. 62

nfi

A-Bus Set Register (CS2 and dummy spaces) ........................................................... 62
A-Bus Set Register Map ................................................................................................ 13
Access, Interrupt, Standby, Operation Registers ....................................................... 47
B-Bus ............................................................................................................................... (ii)
Blanking Interrupt ......................................................................................................... 29

Co

Block Diagram .................................................................................................................. 3
Commands ...................................................................................................................... 91
Commands (1), List of ................................................................................................... 80
Commands (2), List of ................................................................................................... 81
Commands (3), List of ................................................................................................... 82
Commands (4), List of ................................................................................................... 83
Constants, Description of ............................................................................................. 90

GA

CS0 Space Burst Cycle Set Value ................................................................................. 65
CS0 Space Burst Length Set Value ............................................................................... 65
CS0 Space Bus Size Set Value ....................................................................................... 66
CS0 Space Single Cycle Set Value ................................................................................ 65
CS0, 1 Space A-Bus Set Set Register ............................................................................ 62
CS1 Space Burst Cycle Set Value ................................................................................. 67
CS1 Space Burst Length Set Value ............................................................................... 68

SE

CS1 Space Bus Size Set Value ....................................................................................... 68
CS1 Space Single Cycle Set Value ................................................................................ 67
CS2 Space Burst Cycle Value ........................................................................................ 68
CS2 Space Bus Size Set Value ....................................................................................... 70

SCU User's Manual

167

Data .................................................................................................................................... ii
Data Write Example (Indirect Mode) .......................................................................... 23ntialDifference in DMA operation by Address Renewal Bit ........................................... 22
Difference in Timing by Setting External Wait Effective Bit .................................... 64

Direct Mode DMA Transfer Operation ...................................................................... 18
DMA Enable Register .................................................................................................... 45
DMA Command Execution .......................................................................................... 87

DMA Command Format 1 ......................................................................................... 132
DMA Command Format 2 ......................................................................................... 132

DMA Control Register .................................................................................................. 41de

DMA End Interrupt ....................................................................................................... 33
DMA Force-Stop Register ............................................................................................. 47

DMA Force-Stop Register Map...................................................................................... 8
DMA Illegal Interrupt ................................................................................................... 33
DMA Mode ..................................................................................................................... 18

DMA Mode, Address Renewal, Start Factor Select Register ................................... 46

nfi

DMA Status Register ............................................................................................... 47, 48

DMA Status Register Map .............................................................................................. 9
DMA Transfer (Basic Operation) ................................................................................. 16
DMA Transfer Execution by Address Add Value Set ............................................... 26
DMA Transferable Area when Started from DSP ..................................................... 17Co

DMA Transferable Area when Started from Main CPU .......................................... 17
DMA Write Address while Stopped ........................................................................... 46
DSP .................................................................................................................................. 34
DSP Control Port............................................................................................................ 51
DSP Data RAM Address Port ................................................................................ 10, 53
DSP Data RAM Address Port Map ............................................................................. 10
DSP Data RAM Data Port ............................................................................................. 54

GA

DSP Data RAM Data Port Map ................................................................................... 10
DSP End Interrupt ......................................................................................................... 33
DSP Program Control Port ............................................................................................. 9
DSP Program Load Step 1 ............................................................................................ 34
DSP Program Load Step 2 ............................................................................................ 35
DSP Program Load Step 3 ............................................................................................ 35
DSP Program RAM Data Port ................................................................................ 10, 53

SE

DSP Program RAM Data Port Map ............................................................................ 10
Dummy Space Burst Cycle Set Value ......................................................................... 71
Dummy Space Burst Length Set Value ....................................................................... 71
Dummy Space Bus Size Set Value ............................................................................... 72
Dummy Space Single Cycle Set Value ........................................................................ 71

168

Example of transfer between SCU and Processor ..................................................... 44
Features of Data Transfer to DSP from D0 Bus ................................................... 87, 88ntialHigh/Low Level DMA Operation .............................................................................. 48

Indirect Mode DMA Transfer ...................................................................................... 20
Indirect Mode DMA Transfer Flow ............................................................................. 19
Interrupt Control Register ............................................................................................ 57
Interrupt Factor .............................................................................................................. 27

Interrupt Factor, General Names ................................................................................. 28
Interrupt Mask Register ................................................................................................ 57

Interrupt Mask Register Map ....................................................................................... 12deInterrupt Status Register ............................................................................................... 58
Interrupt Status Register Contents .............................................................................. 59
Interrupt Status Register Map ..................................................................................... 12

Jump Command Execution .......................................................................................... 85
Jump Command Format ............................................................................................. 141
Level 0 Transfer Byte Number ..................................................................................... 42

nfi

Level 2-0 Address Add Value ....................................................................................... 42
Level 2-0 DMA Authorization Bit ............................................................................... 45
Level 2-0 DMA Mode, Address Renewal, Start Factor Select Register .................. 46
Level 2-0 DMA Set Register Map .................................................................................. 8
Level 2-0 Read Address ................................................................................................ 41

Co

Level 2-0 Write Address ................................................................................................ 41
Level 2-1 Transfer Byte Number .................................................................................. 42
Load Immediate Command Format 1 (unconditional transfer) ........................... 120
Load Immediate Command Format 2 (conditional transfer) ................................ 120
Loop Bottom Command Format ............................................................................... 153
Loop Program Execution .............................................................................................. 86
Main CPU .......................................................................................................................... iGA

Operand Execution Method ......................................................................................... 85
Operation Command Format ...................................................................................... 91
Operation when Cache Hit ............................................................................................. 5
PAD Interrupt ................................................................................................................. 33
RAM Page Select ............................................................................................................ 53
Read Address Add Value .............................................................................................. 43
Registers, List of ............................................................................................................. 40

SE

Results of Previous Read Process ................................................................................ 63

SCU User's Manual169

SCSP .................................................................................................................................... i
SCU ..................................................................................................................................... intial

SCU Control Register .................................................................................................... 73
SCU Mapping (Cache_address)..................................................................................... 4

SCU Mapping (Cache_through_address) .................................................................... 6
SCU Overview ................................................................................................................. 2

SCU SDRAM Select Register Map .............................................................................. 14
SCU SDRAM Select Bit ................................................................................................. 73

SCU Version Register Map ........................................................................................... 14
SCU Version Register .................................................................................................... 73

de

SMPC ................................................................................................................................. ii

SMPC Interrupt .............................................................................................................. 33

Sound Request Interrupt .............................................................................................. 33
Special Process Execution ............................................................................................. 89
Sprite Draw End Interrupt ........................................................................................... 33

Start Factor ...................................................................................................................... 46

nfi

Subroutine Program Execution .................................................................................... 90
System Configuration ..................................................................................................... 2

Timer 0 Compare Register ...................................................................................... 11, 55
Timer 0 Compare Register Map ................................................................................... 11
Timer 0 Interrupt Degree of Occurrence .................................................................... 30

Co

Timer 1 Interrupt Degree of Occurrence .................................................................... 31
Timer 1 Mode Register ............................................................................................ 11, 56
Timer 1 Mode Register Map ......................................................................................... 11
Timer 1 Occurrence Select Content ............................................................................. 56
Timer 1 Set Data Register ....................................................................................... 11, 55
Timer 1 Set Data Register Map .................................................................................... 11
Timer Operation Contents ............................................................................................ 56

GA

Timer Register ................................................................................................................ 55
Timing when setting pre-charge insert bit after Read .............................................. 63
Timing when setting pre-charge insert bit after Write ............................................. 63
Timing when Writing CS2 Burst Cycle ....................................................................... 65
VDP1 ................................................................................................................................... i
VDP2 ................................................................................................................................... i
Work RAM Area Contents ............................................................................................ 24

SE

Write Address Add Value ............................................................................................. 43
Write Address Add Value Indication .......................................................................... 45

170

SE

GA

Co

nfi

de

nti
al

(This page is blank in the original Japanese document.)

SCU User's Manual

171

CommandsntialNOP (ALU Operation) .................................................................................................. 93
AND ................................................................................................................................. 94

OR .................................................................................................................................... 95

XOR .................................................................................................................................. 96
ADD ................................................................................................................................. 97
SUB .................................................................................................................................. 98

AD2 .................................................................................................................................. 99
SR ................................................................................................................................... 100

deRR ................................................................................................................................... 101
SL .................................................................................................................................... 102
RL ................................................................................................................................... 103
RL8 ................................................................................................................................. 104

NOP (X-Bus Operation) .............................................................................................. 106
MOV [s] , X ................................................................................................................... 107

nfi

MOV MUL , p ............................................................................................................... 108

MOV [s] , P.................................................................................................................... 109
NOP (Y-Bus Control) ...................................................................................................111
MOV [s] , Y ................................................................................................................... 112
CLR A ........................................................................................................................... 113

Co

MOV ALU , A ............................................................................................................... 114
MOV [s] , A ................................................................................................................... 115
NOP (D1-Bus No Operation) .................................................................................... 117
MOV SImm , [d] ........................................................................................................... 118
MOV [s] , [d] ................................................................................................................. 119
MVI Imm , [d] ............................................................................................................... 121
MVI [d] , Imm , Z ......................................................................................................... 122

GA

MVI Imm , [d] , NZ ...................................................................................................... 123
MVI Imm , [d] , S ......................................................................................................... 124
MVI Imm , [d] , NS ...................................................................................................... 125
MVI Imm , [d] , C ......................................................................................................... 126
MVI Imm , [d] , NC ..................................................................................................... 127
MVI Imm , [d] , T0 ....................................................................................................... 128
MVI Imm , [d] , NT0 .................................................................................................... 129

SE

MVI Imm , [d] , ZS ....................................................................................................... 130
MVI Imm , [d] , NZS ................................................................................................... 131

172

DMA D0 , [RAM] , SImm .......................................................................................... 133
DMA [RAM] , D0 , SImm .......................................................................................... 134ntialDMA , D0 , [RAM] , [s] .............................................................................................. 135
DMA [RAM] , D0 , [s] ................................................................................................ 136
DMAH , D0 , [RAM] , SImm ..................................................................................... 137
DMAH [RAM] , D0 , SImm ....................................................................................... 138

DMAH D0 , [RAM] , [s] ............................................................................................. 139
DMAH [RAM] , D0 , [s] ............................................................................................. 140
JMP Imm ...................................................................................................................... 142

JMP Z , Imm................................................................................................................. 143

de

JMP NZ , Imm ............................................................................................................. 144

JMP S , Imm ................................................................................................................. 145
JMP NS , Imm .............................................................................................................. 146
JMP C , Imm ................................................................................................................ 147
JMP NC , mm .............................................................................................................. 148
JMP T0 , Imm ............................................................................................................... 149

nfi

JMP NT0 , Imm ........................................................................................................... 150
JMP ZS , Imm .............................................................................................................. 151
JMP NZS , Imm ........................................................................................................... 152
BTM ............................................................................................................................... 154
LPS ................................................................................................................................. 155

Co

END ............................................................................................................................... 157

SE

GA

ENDI ........................................................................................................................ 33, 158

SCU User's Manual173