CXD5602 User Manual

CXD5602 User Manual－1/1293－CXD5602 User ManualContents
Contents .................................................................................................................................................................... 2
Figure Contents........................................................................................................................................................ 7
Table Contents ....................................................................................................................................................... 14
1

Introduction ................................................................................................................................................... 40
1.1

Introduction ............................................................................................................................................. 40

1.2

Notation ................................................................................................................................................... 40

1.2.1
2

CXD5602 Outline ........................................................................................................................................... 42
2.1

Introduction ............................................................................................................................................. 42

2.2

Features.................................................................................................................................................... 42

2.3

Block Diagram ......................................................................................................................................... 45

2.4

Architecture Overview............................................................................................................................. 46

2.5

CPU Processor ......................................................................................................................................... 47

2.5.1

Application Processor ...................................................................................................................... 47

2.5.2

System and I/O Processor ................................................................................................................ 47

2.6

Memory Mapping .................................................................................................................................... 49

2.6.1

Memory Map of Each Block ........................................................................................................... 50

2.6.2

Main Memory .................................................................................................................................. 51

2.6.3

System Memory ............................................................................................................................... 52

2.6.4

Backup Memory .............................................................................................................................. 52

2.7

Clock and Reset ....................................................................................................................................... 52

2.7.1

Overview ......................................................................................................................................... 52

2.7.2

Clock Architecture ........................................................................................................................... 55

2.8

3

Notation of numerical value ............................................................................................................ 40

Power Management ................................................................................................................................. 57

2.8.1

Overview ......................................................................................................................................... 57

2.8.2

Power Domain ................................................................................................................................. 57

2.8.3

Power Supply States ........................................................................................................................ 60

Function Details ............................................................................................................................................. 62
3.1

I/O Configuration..................................................................................................................................... 62

3.1.1

Outline ............................................................................................................................................. 62

3.1.2

Function List .................................................................................................................................... 62

3.1.3

Switching between HOST I/F Select Function and SWD Function ................................................ 63

3.1.4

Pin Multiplexer ................................................................................................................................ 64

3.2

General Purpose Input/Output (GPIO) .................................................................................................... 95

3.2.1

Outlines and Features ...................................................................................................................... 95－2/1293－CXD5602 User Manual

3.2.2

Function List .................................................................................................................................... 95

3.2.3

Function Specification Outlines....................................................................................................... 96

3.2.4

Detailed Function and Control Specification ................................................................................... 98

3.3

Interrupt ................................................................................................................................................. 121

3.3.1

Overview and Features .................................................................................................................. 121

3.3.2

Register Descriptions ..................................................................................................................... 122

3.4

PMU (Power Management Unit) ........................................................................................................... 125

3.4.1

Features and Overview .................................................................................................................. 125

3.4.2

Register List ................................................................................................................................... 135

3.4.3

Register Descriptions ..................................................................................................................... 137

3.4.4

Power Supply Control Flow .......................................................................................................... 149

3.4.5

Power Supply Control Example .................................................................................................... 163

3.5

Clock and Reset (Clock Reset Generator) ............................................................................................. 167

3.5.1

Overview ....................................................................................................................................... 167

3.5.2

Clock Scheme for CRG ................................................................................................................. 167

3.5.3

Analog Circuits .............................................................................................................................. 169

3.5.4

Clock Setting Confirmation ........................................................................................................... 172

3.5.5

Power Domain Reset ..................................................................................................................... 175

3.5.6

Reset by WDT ............................................................................................................................... 176

3.6

RTC ....................................................................................................................................................... 179

3.6.1

Outlines and Features .................................................................................................................... 179

3.6.2

Clock Input .................................................................................................................................... 180

3.6.3

Function List .................................................................................................................................. 181

3.6.4

Function Block Diagrams .............................................................................................................. 181

3.6.5

Detailed Function and Control Specification ................................................................................. 184

3.7

I2C ......................................................................................................................................................... 222

3.7.1

Overview ....................................................................................................................................... 222

3.7.2

Features .......................................................................................................................................... 225

3.7.3

Functional description.................................................................................................................... 226

3.7.4

List of Registers ............................................................................................................................. 250

3.8

DMAC ................................................................................................................................................... 278

3.8.1

Overview and Features .................................................................................................................. 278

3.8.2

Function Descriptions .................................................................................................................... 278

3.8.3

SDMAC ......................................................................................................................................... 280

3.8.4

HDMAC ........................................................................................................................................ 283

3.8.5

SYDMAC ...................................................................................................................................... 285

3.8.6

SYSUBDMAC .............................................................................................................................. 286

3.8.7

ADMAC ........................................................................................................................................ 287

3.8.8

IDMAC .......................................................................................................................................... 289－3/1293－CXD5602 User Manual

3.9

SCU (Sensor Control Unit) .................................................................................................................... 301

3.9.1

SCU Overview and Features.......................................................................................................... 301

3.9.2

SCU Block Diagram ...................................................................................................................... 303

3.9.3

Memory Map ................................................................................................................................. 304

3.9.4

Clock Control................................................................................................................................. 307

3.9.5

Power Supply Control.................................................................................................................... 313

3.9.6

Interrupt ......................................................................................................................................... 313

3.9.7

MATH_PROC processing ............................................................................................................. 318

3.9.8

FIFO............................................................................................................................................... 328

3.9.9

Sequencers ..................................................................................................................................... 334

3.9.10

DMA .............................................................................................................................................. 356

3.9.11

PWM .............................................................................................................................................. 358

3.9.12SCU Register Details ..................................................................................................................... 369

3.9.13SCU Control Sequence .................................................................................................................. 870

3.9.14

Error Handling ............................................................................................................................... 914

3.9.15

Restrictions .................................................................................................................................... 915

3.10

SPI ......................................................................................................................................................... 930

3.10.1

Overview and Features .................................................................................................................. 930

3.10.2

SPI0 ............................................................................................................................................... 932

3.10.3

SPI3 ............................................................................................................................................... 933

3.10.4

SPI4 ............................................................................................................................................... 934

3.10.5SPI5 ............................................................................................................................................... 936

3.10.6

List of Registers ............................................................................................................................. 937

3.11

UART .................................................................................................................................................... 949

3.11.1

Overview and Features .................................................................................................................. 949

3.11.2

UART1 .......................................................................................................................................... 950

3.11.3

UART2 .......................................................................................................................................... 952

3.11.4

List of Registers ............................................................................................................................. 953

3.12

GNSS ..................................................................................................................................................... 965

3.13

APP ........................................................................................................................................................ 967

3.13.1

Function Overview ........................................................................................................................ 967

3.13.2

Power Supply Control.................................................................................................................... 970

3.13.3Clock Reset Control ....................................................................................................................... 971

3.13.4

Description of APP_DSP Function................................................................................................ 982

3.14

SYSIOP Clock and Reset Control ....................................................................................................... 1007

3.14.1

Function Overiew ........................................................................................................................ 1007

3.14.2

Power Supply Control.................................................................................................................. 1010

3.14.3Clock and Reset Control .............................................................................................................. 1011

3.15

Audio Codec ........................................................................................................................................ 1029

－4/1293－CXD5602 User Manual

3.15.1

Audio Codec Overview and Features .......................................................................................... 1029

3.15.2

Audio Codec Block Diagram ....................................................................................................... 1030

3.15.3Clock Supply ............................................................................................................................... 1035

3.15.4Standalone Operation (without the CXD5247)............................................................................ 1035

3.15.5External Interfaces ....................................................................................................................... 1036

3.15.6

Details of Audio Codec Control Registers................................................................................... 1038

3.15.7

Status Register ............................................................................................................................. 1083

3.15.8Interrupt Flag ............................................................................................................................... 1087

3.15.9

Audio Codec Control Register List ............................................................................................. 1090

3.15.10Control Sequence ..................................................................................................................... 1106

3.16

SDIO .................................................................................................................................................... 1112

3.17

eMMC.................................................................................................................................................. 1112

3.18

USB ..................................................................................................................................................... 1112

3.18.1

Overview ..................................................................................................................................... 1113

3.18.2

Configuration Parameters ............................................................................................................ 1118

3.18.3

Theory of Operation .................................................................................................................... 1124

3.18.4DMA Mode.................................................................................................................................. 1124

3.18.5

Slave-Only Mode ......................................................................................................................... 1128

3.18.6

Control and Status Registers ........................................................................................................ 1131

3.18.7

Slave-Only Operation .................................................................................................................. 1172

3.18.8DMA Operation ........................................................................................................................... 1181

3.18.9Application Bus Protocol (Slave-Only Mode) ............................................................................. 1201

3.18.10

Application Bus Protocol (DMA Mode).................................................................................. 1203

3.18.11

Software Implementation Guidelines ...................................................................................... 1205

3.18.12

USB Programming................................................................................................................... 1211

3.18.13Multiple RxFIFO Controllers .................................................................................................. 1233

3.19

CIS I/F ................................................................................................................................................. 1238

3.20

2D Graphics ......................................................................................................................................... 1238

3.21

ADC ..................................................................................................................................................... 1239

3.21.1ADC Overview ............................................................................................................................ 1239

3.21.2ADC Block Diagram ................................................................................................................... 1240

3.21.3

Memory Map ............................................................................................................................... 1240

3.21.4

Power Supply Control.................................................................................................................. 1241

3.21.5Clock Control............................................................................................................................... 1242

3.21.6

Reset Control ............................................................................................................................... 1245

3.21.7

Interrupt ....................................................................................................................................... 1245

3.21.8

FIFO writing Process ................................................................................................................... 1245

3.21.9Gain Control ................................................................................................................................ 1246

3.21.10

Performance Estimation........................................................................................................... 1248

－5/1293－CXD5602 User Manual

43.21.11

Synchronization Function with PWM ..................................................................................... 1249

3.21.12ADC Control Register Details ................................................................................................. 1249

3.21.13ADC Control Sequence ........................................................................................................... 1285

3.21.14

Restrictions .............................................................................................................................. 1285

3.21.15

Error Handling ......................................................................................................................... 1286

Appendix..................................................................................................................................................... 1287
4.1

Words and Terms ................................................................................................................................. 1287

4.1.1
4.2

Words and Terms Used in This User Manual .............................................................................. 1287

Reference ............................................................................................................................................. 1289

Revision History................................................................................................................................................. 1290

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Figure Contents
Figure Block Diagram-1 CXD5602 Block Diagram ............................................................................................... 45
Figure Memory Mapping-2 Memory Map of the SYSIOP, GNSS, and APP ......................................................... 49
Figure Clock and Reset-3 Clock Diagram ............................................................................................................... 56
Figure Power Management-4 Power Domain Layers .............................................................................................. 57
Figure Power Management-5 CXD5602 Power Domain ........................................................................................ 58
Figure Power Management-6 Changes of Power Supply States ............................................................................. 61
Figure I/O Configuration-7 Switching between HOST I/F Function and SWD Function....................................... 63
Figure I/O Configuration-8 Visualized Function inside IOCELL Controlled by IOCELL Control Register ......... 75
Figure I/O Configuration-9 Examples of Assigning Roles to the Pin (P1r_02) ...................................................... 79
Figure I/O Configuration-10 PMIC_INT Signal Routes (MODE=1)...................................................................... 81
Figure I/O Configuration-11 PMIC_INT Signal Routes (MODE=2 Open Drain) .................................................. 82
Figure I/O Configuration-12 RTC_IRQ_OUT Signal Routes (MODE=2 Open Drain).......................................... 83
Figure I/O Configuration-13 SDIO CLK Input Schematic...................................................................................... 91
Figure I/O Configuration-14 SDIO WP/CD Input Control Register Schematic...................................................... 92
Figure General Purpose Input/Output (GPIO)-15 GPIO Overview Block Diagram ............................................... 96
Figure General Purpose Input/Output (GPIO)-16 Diagram of GPIO Event Detect Block ...................................... 97
Figure General Purpose Input/Output (GPIO)-17 Output Signal Route in the I/O Function Controlled by GPIO
Parameter ........................................................................................................................................................... 100
Figure General Purpose Input/Output (GPIO)-18 Input Signal Route in the I/O Function Controlled by GPIO
Parameter ........................................................................................................................................................... 101
Figure General Purpose Input/Output (GPIO)-19 GPIO Pin Selection ................................................................. 102
Figure General Purpose Input/Output (GPIO)-20 External Interrupt Selection .................................................... 106
Figure General Purpose Input/Output (GPIO)-21 Event Detection Control.......................................................... 109
Figure General Purpose Input/Output (GPIO)-22 Event Detection Timing Diagram ........................................... 112
Figure General Purpose Input/Output (GPIO)-23 Connection Diagram of Event Detection and SYSCPU or DSP........................................................................................................................................................................... 117
Figure General Purpose Input/Output (GPIO)-24 Time Interval for a Signal to be able to Detect an Event Again(PMU_WAKE_TRIG_NOISECUTEN0:0) ....................................................................................................... 120
Figure Interrupt-25 Interrupt Connection Diagram ............................................................................................... 121
Figure PMU (Power Management Unit)-26 PMU and the Power Domain Layers ............................................... 125
Figure PMU (Power Management Unit)-27 Individual Power Supply Control within the Power Domains ......... 127
Figure PMU (Power Management Unit)-28 Power Supply Control within the Power Domain (PWD_APP Main
Memory) ............................................................................................................................................................ 128
Figure PMU (Power Management Unit)-29 Changes of Power Supply States ..................................................... 130
Figure PMU (Power Management Unit)-30 Overall Block Diagram of the PMU ................................................ 133－7/1293－CXD5602 User Manual

Figure PMU (Power Management Unit)-31 PMU Clock System ......................................................................... 134
Figure PMU (Power Management Unit)-32 Sleep/Wakeup Control Flow of the Application Processor ............. 166
Figure Clock and Reset (Clock Reset Generator)-33 CRG Control Area within Overall Clock Scheme ............. 168
Figure Clock and Reset (Clock Reset Generator)-34 CRG Clock Scheme ........................................................... 168
Figure RTC-35 RTC0/1 Power Supply Framework .............................................................................................. 179
Figure RTC-36 Clock Resources of RTC .............................................................................................................. 181
Figure RTC-37 RTC Block Diagram .................................................................................................................... 182
Figure RTC-38 RTC (Time Update) Block Diagram ............................................................................................ 183
Figure I2C-39 I2C0/I2C1 Clock and Reset System............................................................................................... 223
Figure I2C-40 I2C2 Clock and Reset System ........................................................................................................ 224
Figure I2C-41 Master/Slave and Transmitter/Receiver Relationships .................................................................. 227
Figure I2C-42 Data transfer on the I2C Bus .......................................................................................................... 228
Figure I2C-43 START and STOP Condition ........................................................................................................ 229
Figure I2C-44 7-bit Address Format ..................................................................................................................... 230
Figure I2C-45 10-bit Address Format ................................................................................................................... 230
Figure I2C-46 Master-Transmitter Protocol .......................................................................................................... 231
Figure I2C-47 Master-Receiver Protocol .............................................................................................................. 231
Figure I2C-48 START BYTE Transfer ................................................................................................................. 232
Figure I2C-49 IC_DATA_CMD Register if IC_EMPTYFIFO_HOLD_MASTER_EN = 0 ................................ 233
Figure I2C-50 Master Transmitter Tx FIFO Becomes Empty if IC_EMPTYFIFO_HOLD_MASTER_EN=0 ... 233
Figure I2C-51 Master Receiver Tx FIFO Becomes Empty if IC_EMPTYFIFO_HOLD_MASTER_EN=0 ........ 234
Figure I2C-52 IC_DATA_CMD Register if IC_EMPTYFIFO_HOLD_MASTER_EN = 1 ................................ 234
Figure

I2C-53MasterTransmitter

Tx

FIFO

Empties/STOP

Generation

if

IC_EMPTYFIFO_HOLD_MASTER_EN=1 .................................................................................................... 235
Figure

I2C-54MasterReceiverTx

FIFO

Empties/STOP

Generation

if

IC_EMPTYFIFO_HOLD_MASTER_EN=1 .................................................................................................... 235
Figure

I2C-55MasterTransmitter

Restart

Bit

of

IC_DATA_CMD

is

set

(IC_EMPTYFIFO_HOLD_MASTER_EN=1) .................................................................................................. 236
Figure

I2C-56MasterReceiverRestart

Bit

of

IC_DATA_CMD

is

set

(IC_EMPTYFIFO_HOLD_MASTER_EN=1) .................................................................................................. 236
Figure

I2C-57

MasterTransmitter

Stop

Bit

of

IC_DATA_CMD

Set/Tx

FIFO

Not

Empty

(IC_EMPTYFIFO_HOLD_MASTER_EN=1) .................................................................................................. 236
Figure I2C-58 Master Transmitter First Byte Loaded into Tx FIFO Allowed to Empty, Restart Bit Set(IC_EMPTYFIFO_HOLD_MASTER_EN=1) .................................................................................................. 237
Figure

I2C-59MasterReceiver

Stop

Bit

of

IC_DATA_CMD

Set/Tx

FIFO

Not

Empty

(IC_EMPTYFIFO_HOLD_MASTER_EN=1) .................................................................................................. 237
Figure I2C-60 Master Receiver First Command Loaded After Tx FIFO Allowed to Empty, Restart Bit Set(IC_EMPTYFIFO_HOLD_MASTER_EN=1) .................................................................................................. 237
Figure I2C-61 Multiple Master Arbitration ........................................................................................................... 238－8/1293－CXD5602 User Manual

Figure I2C-62 Multi-Master Clock Synchronization............................................................................................. 239
Figure I2C-63 Spike Suppression Example ........................................................................................................... 242
Figure I2C-64 Impact of SCL Rise Time and Fall Time on Generated SCL ........................................................ 244
Figure I2C-65 IC_SDA_HOLD Register .............................................................................................................. 247
Figure I2C-66 IC_SDA_RX_HOLD >= 3 ............................................................................................................ 248
Figure I2C-67 IC_SDA_RX_HOLD = 2 ............................................................................................................... 248
Figure I2C-68 DW_apb_i2c Master Implementing tHD; DAT with IC_SDA_HOLD = 3................................... 249
Figure DMAC-69 SDMAC Overview of Added Functions .................................................................................. 280
Figure DMAC-70 SDMAC Clock and Reset System............................................................................................ 282
Figure DMAC-71 HDMAC Overview of Added Functions ................................................................................. 283
Figure DMAC-72 HDMAC Clock and Reset System ........................................................................................... 284
Figure DMAC-73 SYDMAC Clock and Reset System ......................................................................................... 285
Figure DMAC-74 SYSUBDMAC Clock and Reset System ................................................................................. 287
Figure DMAC-75 ADMAC Clock and Reset System ........................................................................................... 288
Figure DMAC-76 IDMAC Function Block Diagram............................................................................................ 289
Figure DMAC-77 IDMAC Clock and Reset System ............................................................................................ 300
Figure SCU (Sensor Control Unit)-78 Block Function Overview......................................................................... 303
Figure SCU (Sensor Control Unit)-79 Memory Mapping from the Upper CPUs; the CPU in the SYSIOP and the
CPU in the GNSS; (hereinafter in the Chapter on SCU, referred as “upper CPUs”) ........................................ 304
Figure SCU (Sensor Control Unit)-80 Memory Mapping within the SCU as seen from the Upper CPUs ........... 305
Figure SCU (Sensor Control Unit)-81 Memory Mapping as seen from the Internal Sequencer ........................... 306
Figure SCU (Sensor Control Unit)-82 Memory Mapping as seen from the HOSTIFC ........................................ 306
Figure SCU (Sensor Control Unit)-83 Clock System ............................................................................................ 309
Figure SCU (Sensor Control Unit)-84 Interrupt Connections ............................................................................... 314
Figure SCU (Sensor Control Unit)-85 Decimation Partition Data Path ................................................................ 319
Figure SCU (Sensor Control Unit)-86 Normal Sensor Partition Data Path ........................................................... 319
Figure SCU (Sensor Control Unit)-87 Preprocessing Data Flow .......................................................................... 320
Figure SCU (Sensor Control Unit)-88 Decimation Processing Data Flow............................................................ 321
Figure SCU (Sensor Control Unit)-89 Data Flow within the Math Function ........................................................ 322
Figure SCU (Sensor Control Unit)-90 2 2nd Order IIR Filter Combinations ....................................................... 323
Figure SCU (Sensor Control Unit)-91 2nd Order IIR Filter Internal Data Flow ................................................... 324
Figure SCU (Sensor Control Unit)-92 Normalization Processing Data Flow ....................................................... 324
Figure SCU (Sensor Control Unit)-93 Excess Detection Operation (by a Comparator and an Excess Detector) . 325
Figure SCU (Sensor Control Unit)-94 Excess Detection Operation (Two-step Cascade Connection) ................. 326
Figure SCU (Sensor Control Unit)-95 FIFO Block Diagram ................................................................................ 334
Figure SCU (Sensor Control Unit)-96 Sequencer Overall Image.......................................................................... 336
Figure SCU (Sensor Control Unit)-97 Sequencer Process Flow (Example) ......................................................... 336
Figure SCU (Sensor Control Unit)-98 Overall Data Flow (excluding Data Duplication Function)...................... 337
Figure SCU (Sensor Control Unit)-99 Startup Control ......................................................................................... 338－9/1293－CXD5602 User Manual

Figure SCU (Sensor Control Unit)-100 External Bus Transaction Generation ..................................................... 339
Figure SCU (Sensor Control Unit)-101 External Data Capture ............................................................................ 340
Figure SCU (Sensor Control Unit)-102 Sensor Data Flow when Capturing External Data .................................. 341
Figure SCU (Sensor Control Unit)-103 Data Normalization (Example) ............................................................... 342
Figure SCU (Sensor Control Unit)-104 Data Stacked in the FIFO (Image) .......................................................... 343
Figure SCU (Sensor Control Unit)-105 Sequencer Data Flow .............................................................................. 350
Figure SCU (Sensor Control Unit)-106 Sequencer Completed ............................................................................. 352
Figure SCU (Sensor Control Unit)-107 Sequencer Suspended ............................................................................. 352
Figure SCU (Sensor Control Unit)-108 MATH_PROC Parameter Change (Example) ........................................ 353
Figure SCU (Sensor Control Unit)-109 Error Notification (Example).................................................................. 355
Figure SCU (Sensor Control Unit)-110 DMA Handshake Signal Connections .................................................... 357
Figure SCU (Sensor Control Unit)-111 PWM Output Mode using ADC Timing as a Reference ........................ 361
Figure SCU (Sensor Control Unit)-112 ADC Data Capture Mode using the PWM Output Timing as a Reference........................................................................................................................................................................... 364
Figure SCU (Sensor Control Unit)-113 Processing Block Overview.................................................................... 412
Figure SCU (Sensor Control Unit)-114 Filter Overview ....................................................................................... 414
Figure SCU (Sensor Control Unit)-115 Excess Detection Overview .................................................................... 450
Figure SCU (Sensor Control Unit)-116 I2C Master Control (Example) ............................................................... 918
Figure SCU (Sensor Control Unit)-117 Basic Startup Timing .............................................................................. 919
Figure SCU (Sensor Control Unit)-118 Delay at Start (Example) ........................................................................ 919
Figure SCU (Sensor Control Unit)-119 Time Stamp Fluctuation by the Presence/Absence of HPADC Execution........................................................................................................................................................................... 924
Figure SCU (Sensor Control Unit)-120 Counter Basic Operation ........................................................................ 925
Figure SCU (Sensor Control Unit)-121 1 One-to-One Connection (Example) ..................................................... 926
Figure SCU (Sensor Control Unit)-122 One-to-N Connection (Example)............................................................ 927
Figure SPI-123 SPI0 Clock and Reset System ...................................................................................................... 933
Figure SPI-124 SPI3 Clock and Reset System ...................................................................................................... 934
Figure SPI-125 SPI4 Clock and Reset System ...................................................................................................... 935
Figure SPI-126 SPI5 Clock and Reset System ...................................................................................................... 936
Figure SPI-127 Mode0, single transfer .................................................................................................................. 939
Figure SPI-128 Mode0, continuous transfer .......................................................................................................... 939
Figure SPI-129 Mode1, single and continuous transfers ....................................................................................... 940
Figure SPI-130 Mode2, single transfer .................................................................................................................. 941
Figure SPI-131 Mode2, continuous transfer .......................................................................................................... 941
Figure SPI-132 Mode3, single and continuous transfers ....................................................................................... 942
Figure UART-133 UART1 Clock and Reset System ............................................................................................ 951
Figure UART-134 UART2 Clock and Reset System ............................................................................................ 952
Figure APP-135 Application Domain Clock System ............................................................................................ 972
Figure APP-136 Application Domain Reset System ............................................................................................. 973－10/1293－

CXD5602 User Manual

Figure APP-137 APP_DSP Block Diagram .......................................................................................................... 983
Figure APP-138 WDTRES Connection ................................................................................................................ 990
Figure APP-139 Address Map ............................................................................................................................... 994
Figure APP-140 Input-Output Addresses of Address Converter ........................................................................... 995
Figure APP-141 Address Conversion Operation Scheme ..................................................................................... 996
Figure APP-142 Example of Address Conversion: Conversion of Bit Assignment for ADSP0 ........................... 999
Figure APP-143 Example of Address Conversion: Conversion Address Map for ADSP0 and ADSP1 ............... 999
Figure APP-144 Success Case 1 of Exclusive Access......................................................................................... 1001
Figure APP-145 Success Case 2 of Exclusive Access......................................................................................... 1001
Figure APP-146 Failure Case 1 of Exclusive Access .......................................................................................... 1002
Figure APP-147 Failure Case 2 of Exclusive Access .......................................................................................... 1002
Figure APP-148 Failure Case 3 of Exclusive Access .......................................................................................... 1002
Figure SYSIOP Clock and Reset Control-149 SYSIOP Clock Configuration Diagram ..................................... 1012
Figure SYSIOP Clock and Reset Control-150 SYSIOP Reset Configuration Diagram ...................................... 1026
Figure 3.15-1 Audio Codec Block Diagram ........................................................................................................ 1030
Figure 3.15-2 I2S Signal Path .............................................................................................................................. 1031
Figure 3.15-3 Mic Signal Path ............................................................................................................................. 1032
Figure 3.15-4 SP Signal Path ............................................................................................................................... 1034
Figure 3.15-5 Serializer Timing Chart................................................................................................................. 1035
Figure 3.15-6 I2S Format 24bit ........................................................................................................................... 1036
Figure 3.15-7 Left Justified 24bit ........................................................................................................................ 1037
Figure 3.15-8 CXD5247 Interface (SP) (MIC) .................................................................................................... 1037
Figure 3.15-9 DMIC Timing ............................................................................................................................... 1038
Figure 3.15-10 Internal Signal Selector Overview Diagram ............................................................................... 1040
Figure 3.15-11 Characterstics of the Band Limiting Filter (HI_RES_MODE:1'b1, SRC{1,2}:2'b10) ............... 1053
Figure 3.15-12 Characterstics of the Band Limiting Filter (HI_RES_MODE:1'b1, SRC{1,2}:2'b01) ............... 1054
Figure 3.15-13 Volume Control Overview Diagram ........................................................................................... 1055
Figure 3.15-14 Example of ALC_TARGET Control (ALC_KNEE:7'h00) ........................................................ 1056
Figure 3.15-15 Example of ALC_KNEE Control (ALC_TARGET:6'h00) ........................................................ 1057
Figure 3.15-16 The HP Output Signal in Normal Mode (fs = 48 kHz) with ALC function OFF and Input Signal
Level: -6 dB/-26 dB ......................................................................................................................................... 1059
Figure 3.15-17 The HP Output Signal in Normal Mode (fs = 48 kHz) with ALC function ON,
SPC_ALC_RELEASE = 0x000100, ALC_ALG = 1'b0, and Input Signal Level -6 dB/-26 dB ..................... 1059
Figure 3.15-18 The HP Output Signal in Normal Mode (fs = 48 kHz) with SPC function ON,
SPC_ALC_ATTACK = 0x000100, and Input Signal Level -6 dB/-26 dB...................................................... 1060
Figure 3.15-19 AWEIGHT Filter Characteristics (Hi-Res Mode) ...................................................................... 1061
Figure 3.15-20 AWEIGHT Filter Chracteristics (Normal Mode) ....................................................................... 1061
Figure 3.15-21 Order of Processing DEQ, ALC, and Clear Stereo (HI_RES_MODE:1'b1, ALC_REC:1'b0) ... 1062
Figure 3.15-22 Order of Processing DEQ, ALC, and Clear Stereo－11/1293－(HI_RES_MODE:1'b1, ALC_REC:1'b1) 1062

CXD5602 User Manual

Figure 3.15-23 Order of Processing DEQ, ALC, and Clear Stereo (HI_RES_MODE:1'b0, ALC_REC:1'b0) ... 1062
Figure 3.15-24 Order of Processing DEQ, ALC, and Clear Stereo (HI_RES_MODE:1'b0, ALC_REC:1'b1) ... 1063
Figure 3.15-25 Order of Processing DEQ, SPC, and Clear Stereo ...................................................................... 1063
Figure 3.15-26 Decimation Filter Peripheral Overview ...................................................................................... 1064
Figure 3.15-27 Characteristics of 1/2-band Decimation Filter ............................................................................ 1065
Figure 3.15-28 Characteristics of 1/4-band Decimation Filter ............................................................................ 1066
Figure 3.15-29 Characteristics of 1/8-band Decimation Filter ............................................................................ 1066
Figure 3.15-30 BUS MASTER(MIC) Block ....................................................................................................... 1071
Figure 3.15-31 Bit Configuration by Transfer Mode (when writing to the SRAM)............................................ 1072
Figure 3.15-32 BUS MASTER (I2S0/I2S1) Block ............................................................................................. 1072
Figure 3.15-33 Bit Configuration by Transfer Mode (when writing to the SRAM)............................................ 1073
Figure 3.15-34 Bit Configuration by Transfer Mode (when reading from the SRAM) ...................................... 1073
Figure 3.15-35 Mic Signal Upload Flow (Example) ........................................................................................... 1108
Figure 3.15-36 I2S0 Signal Upload Flow (Example) .......................................................................................... 1109
Figure USB-37 UDC-AHB Subsystem Architecture .......................................................................................... 1114
Figure USB-38 Clock Boundary ......................................................................................................................... 1117
Figure USB-39 IN Transaction Flow in DMA Mode .......................................................................................... 1125
Figure USB-40 OUT Transaction Flow in DMA Mode (Without Thresholding) ............................................... 1127
Figure USB-41 IN Transaction Flow in Slave-Only Mode ................................................................................. 1129
Figure USB-42 OUT Transaction Flow in Slave-Only Mode ............................................................................. 1130
Figure USB-43 Memory Map (Processor Viewpoint) ......................................................................................... 1166
Figure USB-44 UDC-AHB Subsystem Architecture .......................................................................................... 1173
Figure USB-45 External RAM Write/Read Transfer .......................................................................................... 1177
Figure USB-46 FIFO Confirm Mechanism ......................................................................................................... 1177
Figure USB-47 RxFIFO Implementation ............................................................................................................ 1179
Figure USB-48 Descriptor Memory Structure..................................................................................................... 1182
Figure USB-49 SETUP Data Memory Structure ................................................................................................. 1183
Figure USB-50 OUT Data Memory Structure ..................................................................................................... 1184
Figure USB-51 IN Data Memory Structure ......................................................................................................... 1186
Figure USB-52 Control/Bulk-IN Transaction in Packet-Per-Buffer With Descriptor Update Mode .................. 1192
Figure USB-53 Control/Bulk-IN Transaction in Packet-Per-Buffer Without Descriptor Update Mode ............. 1193
Figure USB-54 OUT Transaction in Packet-Per-Buffer Mode With Descriptor Update .................................... 1194
Figure USB-55 OUT Transaction in Packet-Per-Buffer Mode Without Descriptor Update ............................... 1195
Figure USB-56 DMA Processing OUT Packets in Buffer Fill Mode.................................................................. 1196
Figure USB-57 DMA Processing OUT Packets in Packet-Per-Buffer With Descriptor Update Mode With
Threshold Enabled ........................................................................................................................................... 1198
Figure USB-58 Byte Ordering (Endianness) Conversion .................................................................................... 1199
Figure USB-59 OUT Transaction Flow in DMA Mode Without Thresholding Enabled .................................... 1235
Figure USB-60 OUT Transaction Flow in DMA Mode With Thresholding Enabled ......................................... 1236

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Figure USB-61 OUT Transaction Flow in Slave-Only Mode ............................................................................. 1237
Figure ADC-62 Block Diagram ADCIF module and around ADC macro circuits ............................................. 1240
Figure ADC-63 Memory Map inside the ADCIF ................................................................................................ 1241
Figure ADC-64 Schematic Diagram of the Clock Control .................................................................................. 1243
Figure ADC-65 Data Flow of the ADC ............................................................................................................... 1245
Figure ADC-66 HPADC Gain Control Overview ............................................................................................... 1247

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Table Contents
Table Notation-1 Notation of Numerical Value ...................................................................................................... 40
Table Memory Mapping-2 Memory Mapping of the SYSIOP Block (SYS Window) ............................................ 50
Table Memory Mapping-3 Memory Mapping of the APP Block (APP Window) .................................................. 51
Table Power Management-4 Power Supply States .................................................................................................. 60
Table I/O Configuration-5 Function List ................................................................................................................. 62
Table I/O Configuration-6 HOST I/F Decided in Accordance with Pin SYSTEM{0,1} ........................................ 63
Table I/O Configuration-7 List of Registers for Controlling Pin Multiplexer ......................................................... 64
Table I/O Configuration-8 List of Registers for Controlling IOCELL .................................................................... 64
Table I/O Configuration-9 List of Registers for AUDIO and SDIO Control .......................................................... 67
Table I/O Configuration-10 Overview of Registers for Selecting a Role of the I/O Pins Belonging to SYS Group............................................................................................................................................................................. 68
Table I/O Configuration-11 Table of Role Selection for I/O Pins Belonging to SYS Group.................................. 69
Table I/O Configuration-12 Overview of Registers for Selecting a Role of the I/O Pins Belonging to APP Group............................................................................................................................................................................. 71
Table I/O Configuration-13 Table of Role Selection for the I/O Pins Belonging to APP Group ............................ 72
Table I/O Configuration-14 Overview of Registers to Select Function of IOCELL ............................................... 74
Table I/O Configuration-15 Correspondence Table of IOCELL Control Registers and Controllable I/O Pins ...... 76
Table I/O Configuration-16 Overview of Registers for Selecting Output Function of I2S ..................................... 77
Table I/O Configuration-17 Overview of Register for Selecting PDM_CLK Output Function .............................. 77
Table I/O Configuration-18 Overview of Registers for Selecting Input Value to SDIO......................................... 78
Table General Purpose Input/Output (GPIO)-19 Function List............................................................................... 95
Table General Purpose Input/Output (GPIO)-20 GPIO Control Register ............................................................... 98
Table General Purpose Input/Output (GPIO)-21 Correspondence of GPIO Control Registers to I/O Pins ............ 99
Table General Purpose Input/Output (GPIO)-22 IO Pin Selection (SYS Group) ................................................. 103
Table General Purpose Input/Output (GPIO)-23 Correspondence of I/O Pins to Setting Values (SYS Group) ... 104
Table General Purpose Input/Output (GPIO)-24 I/O Pin Selection (APP Group) ................................................ 104
Table General Purpose Input/Output (GPIO)-25 Correspondence of I/O Pins to Setting Values (APP Group) ... 105
Table General Purpose Input/Output (GPIO)-26 External Interrupt Selection...................................................... 107
Table General Purpose Input/Output (GPIO)-27 I/O Pins That Can be Used for Event Detection ....................... 110
Table General Purpose Input/Output (GPIO)-28 Event Detection Setting for I/O Pins ........................................ 112
Table General Purpose Input/Output (GPIO)-29 Status of Event Detection ......................................................... 115
Table General Purpose Input/Output (GPIO)-30 Registers to Clear the Status of the Event Detections .............. 116
Table General Purpose Input/Output (GPIO)-31 Time Interval for a Signal to be Able to Detect an Event Again(1*) ....................................................................................................................................................................... 119－14/1293－

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Table Interrupt-32 List of Interrupt Registers of Application Processor ............................................................... 122
Table Interrupt-33 Interrupt Factor Registers of Application Processor ............................................................... 122
Table PMU (Power Management Unit)-34 Power Supply States.......................................................................... 129
Table PMU (Power Management Unit)-35 The Setting of the Power Supply in “Reset” State and After Changing
to “Normal” State............................................................................................................................................... 130
Table PMU (Power Management Unit)-36 PMU Register List ............................................................................ 135
Table PMU (Power Management Unit)-37 Power Supply Control Settings (Power Domain) ............................. 137
Table PMU (Power Management Unit)-38 Power Supply Status (Power Domain) .............................................. 138
Table PMU (Power Management Unit)-39 Power Supply Control Settings (SRAM) .......................................... 139
Table PMU (Power Management Unit)-40 Power Supply Status (SRAM) .......................................................... 141
Table PMU (Power Management Unit)-41 Power Supply Control Settings (Analog Circuit) .............................. 143
Table PMU (Power Management Unit)-42 Power Supply Status (Analog Circuit) .............................................. 144
Table PMU (Power Management Unit)-43 Power Supply Control Request ......................................................... 145
Table PMU (Power Management Unit)-44 Interrupt............................................................................................. 145
Table PMU (Power Management Unit)-45 Power Supply Setting Check............................................................. 146
Table PMU (Power Management Unit)-46 Power Supply Setting Check Items ................................................... 147
Table PMU (Power Management Unit)-47 Power Supply Control Setting Values............................................... 149
Table PMU (Power Management Unit)-48 Parameter Setting for Each Mode ..................................................... 155
Table PMU (Power Management Unit)-49 Current Adjustment Setting .............................................................. 156
Table PMU (Power Management Unit)-50 SYSPLL Division Ratio Setting........................................................ 158
Table Clock and Reset (Clock Reset Generator)-51 RCOSC Block Status Registers ........................................... 169
Table Clock and Reset (Clock Reset Generator)-52 XOSC Block Status Register ............................................... 170
Table Clock and Reset (Clock Reset Generator)-53 SYSPLL Frequency Confirmation ...................................... 171
Table Clock and Reset (Clock Reset Generator)-54 SYSPLL Block Status Registers ......................................... 171
Table Clock and Reset (Clock Reset Generator)-55 Clock Switching Status Registers........................................ 172
Table Clock and Reset (Clock Reset Generator)-56 Clock Enable Status Registers ............................................. 174
Table Clock and Reset (Clock Reset Generator)-57 Power Domain and the Reset Control Registers ................. 175
Table Clock and Reset (Clock Reset Generator)-58 Reset Registers of the Power Domain ................................. 176
Table Clock and Reset (Clock Reset Generator)-59 WDT Reset Control Registers ............................................. 177
Table RTC-60Clock Resource of RTC.................................................................................................................. 180
Table RTC-61 Clock Enable of RTC .................................................................................................................... 180
Table RTC-62 Function List.................................................................................................................................. 181
Table RTC-63 Register List of Counter Value Write Control System .................................................................. 184
Table RTC-64 Register List of Time Counter Value Read Control System ......................................................... 184
Table RTC-65 Register List of Alarm Control System ......................................................................................... 185
Table RTC-66 Register List of Time Update Confirming System ........................................................................ 186
Table RTC-67 List of External Alarm Output and Time Synchronization Register ............................................. 186
Table RTC-68 Alarm Occurrence Condition......................................................................................................... 206
Table RTC-69 Examples of Setting Synchronizing Internal RTC with External RTC Synchronization Setting .. 218－15/1293－

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Table I2C-70 I2C List............................................................................................................................................ 222
Table I2C-71 XOSC (26 MHz), High Performance Mode .................................................................................... 225
Table I2C-72 XOSC (26 MHz), Low Power Mode............................................................................................... 225
Table I2C-73 IC_CON .......................................................................................................................................... 252
Table I2C-74 IC_TAR ........................................................................................................................................... 254
Table I2C-75 IC_SAR ........................................................................................................................................... 254
Table I2C-76 IC_HS_MADDR ............................................................................................................................. 254
Table I2C-77 IC_DATA_CMD ............................................................................................................................. 255
Table I2C-78 IC_SS_SCL_HCNT ........................................................................................................................ 256
Table I2C-79 IC_SS_SCL_LCNT ......................................................................................................................... 256
Table I2C-80 IC_FS_SCL_HCNT ........................................................................................................................ 257
Table I2C-81 IC_FS_SCL_LCNT ......................................................................................................................... 257
Table I2C-82 IC_HS_SCL_HCNT........................................................................................................................ 258
Table I2C-83 IC_HS_SCL_LCNT ........................................................................................................................ 258
Table I2C-84 IC_INTR_STAT.............................................................................................................................. 259
Table I2C-85 IC_INTR_MASK ............................................................................................................................ 259
Table I2C-86 IC_RAW_INTR_STAT .................................................................................................................. 260
Table I2C-87 IC_RX_TL ...................................................................................................................................... 262
Table I2C-88 IC_TX_TL....................................................................................................................................... 262
Table I2C-89 IC_CLR_INTR ................................................................................................................................ 263
Table I2C-90 IC_CLR_RX_UNDER .................................................................................................................... 263
Table I2C-91 IC_CLR_RX_OVER ....................................................................................................................... 263
Table I2C-92 IC_CLR_TX_OVER ....................................................................................................................... 263
Table I2C-93 IC_CLR_RD_REQ.......................................................................................................................... 264
Table I2C-94 IC_CLR_TX_ABRT ....................................................................................................................... 264
Table I2C-95 IC_CLR_RX_DONE ...................................................................................................................... 264
Table I2C-96 IC_CLR_ACTIVITY ...................................................................................................................... 264
Table I2C-97 IC_CLR_STOP_DET...................................................................................................................... 265
Table I2C-98 IC_CLR_START_DET ................................................................................................................... 265
Table I2C-99 IC_CLR_GEN_CALL .................................................................................................................... 265
Table I2C-100 IC_ENABLE ................................................................................................................................. 265
Table I2C-101 IC_STATUS .................................................................................................................................. 267
Table I2C-102 IC_TXFLR .................................................................................................................................... 268
Table I2C-103 IC_RXFLR .................................................................................................................................... 268
Table I2C-104 IC_SDA_HOLD ............................................................................................................................ 269
Table I2C-105 IC_TX_ABRT_SOURCE ............................................................................................................. 269
Table I2C-106 IC_SLV_DATA_NACK_ONLY .................................................................................................. 271
Table I2C-107 IC_DMA_CR ................................................................................................................................ 271
Table I2C-108 IC_DMA_TDLR ........................................................................................................................... 271－16/1293－

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Table I2C-109 IC_DMA_RDLR ........................................................................................................................... 272
Table I2C-110 IC_SDA_SETUP ........................................................................................................................... 272
Table I2C-111 IC_ACK_GENERAL_CALL ....................................................................................................... 273
Table I2C-112 IC_ENABLE_STATUS ................................................................................................................ 273
Table I2C-113 IC_FS_SPKLEN ........................................................................................................................... 274
Table I2C-114 IC_HS_SPKLEN ........................................................................................................................... 275
Table I2C-115 IC_CLR_RESTART_DET ............................................................................................................ 275
Table I2C-116 IC_COMP_PARAM_1 ................................................................................................................. 275
Table I2C-117 IC_COMP_VERSION .................................................................................................................. 276
Table I2C-118 IC_COMP_TYPE.......................................................................................................................... 276
Table DMAC-119 DMA Request Bit Assignment ................................................................................................ 279
Table DMAC-120 SDMAC Control Register List ................................................................................................ 281
Table DMAC-121 SDMAC Added Registers ....................................................................................................... 282
Table DMAC-122 HDMAC Control Register List ............................................................................................... 284
Table DMAC-123 SYDMAC Control Register List ............................................................................................. 285
Table DMAC-124 SYSUBDMAC Control Register List ..................................................................................... 286
Table DMAC-125 ADMAC Control Register List ............................................................................................... 287
Table SCU (Sensor Control Unit)-126 Clock Summary ....................................................................................... 307
Table SCU (Sensor Control Unit)-127 Input Clock Source Selection................................................................... 308
Table SCU (Sensor Control Unit)-128 Control of each Clock .............................................................................. 310
Table SCU (Sensor Control Unit)-129 Clock Control Registers ........................................................................... 310
Table SCU (Sensor Control Unit)-130

Clock Control from the Internal Sequencers......................................... 311

Table SCU (Sensor Control Unit)-131 Clock Control from CPU ......................................................................... 312
Table SCU (Sensor Control Unit)-132 Power Supply Control Registers .............................................................. 313
Table SCU (Sensor Control Unit)-133 Interrupt Number ..................................................................................... 313
Table SCU (Sensor Control Unit)-134 Information Interrupts .............................................................................. 315
Table SCU (Sensor Control Unit)-135 System Error Interrupts ............................................................................ 316
Table SCU (Sensor Control Unit)-136 Interrupts for the Sequencers ................................................................... 317
Table SCU (Sensor Control Unit)-137 Internal Sequencer Interrupts ................................................................... 317
Table SCU (Sensor Control Unit)-138 Partition Name and Writing Port/Readout* Port ...................................... 329
Table SCU (Sensor Control Unit)-139 Writing Port and Readout Port Addresses ............................................... 330
Table SCU (Sensor Control Unit)-140 Parameters of Sequencer Resources ........................................................ 345
Table SCU (Sensor Control Unit)-141 Parameters of ADC Resources................................................................. 346
Table SCU (Sensor Control Unit)-142 Parameters of FIFO Resources ................................................................ 346
Table SCU (Sensor Control Unit)-143 Parameters of I2C Resources ................................................................... 349
Table SCU (Sensor Control Unit)-144 Parameters of SPI Resources ................................................................... 349
Table SCU (Sensor Control Unit)-145 DMA Handshake Signals and Connection Destination DMAC ch IDs ... 357
Table SCU (Sensor Control Unit)-146 PWM Maximum and Minimum Setting Range ....................................... 360
Table SCU (Sensor Control Unit)-147 Reference ADC Channel Selection .......................................................... 362－17/1293－

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Table SCU (Sensor Control Unit)-148 ADC Channels and PWM Assignment .................................................... 365
Table SCU (Sensor Control Unit)-149 Settings for Synchronization between PWMs ......................................... 366
Table SCU (Sensor Control Unit)-150 Setting of PWM Channels to be Combined ............................................. 368
Table SCU (Sensor Control Unit)-151 SCU Internal Memory.............................................................................. 369
Table SCU (Sensor Control Unit)-152 SCU Register List .................................................................................... 369
Table SCU (Sensor Control Unit)-153 .................................................................................................................. 378
Table SCU (Sensor Control Unit)-154 .................................................................................................................. 379
Table SCU (Sensor Control Unit)-155 .................................................................................................................. 380
Table SCU (Sensor Control Unit)-156 .................................................................................................................. 381
Table SCU (Sensor Control Unit)-157 .................................................................................................................. 384
Table SCU (Sensor Control Unit)-158 .................................................................................................................. 385
Table SCU (Sensor Control Unit)-159 .................................................................................................................. 387
Table SCU (Sensor Control Unit)-160 .................................................................................................................. 388
Table SCU (Sensor Control Unit)-161 .................................................................................................................. 389
Table SCU (Sensor Control Unit)-162 .................................................................................................................. 390
Table SCU (Sensor Control Unit)-163 .................................................................................................................. 392
Table SCU (Sensor Control Unit)-164 .................................................................................................................. 393
Table SCU (Sensor Control Unit)-165 .................................................................................................................. 394
Table SCU (Sensor Control Unit)-166 .................................................................................................................. 395
Table SCU (Sensor Control Unit)-167 .................................................................................................................. 396
Table SCU (Sensor Control Unit)-168 .................................................................................................................. 397
Table SCU (Sensor Control Unit)-169 .................................................................................................................. 398
Table SCU (Sensor Control Unit)-170 .................................................................................................................. 399
Table SCU (Sensor Control Unit)-171 .................................................................................................................. 400
Table SCU (Sensor Control Unit)-172 .................................................................................................................. 401
Table SCU (Sensor Control Unit)-173 .................................................................................................................. 403
Table SCU (Sensor Control Unit)-174 .................................................................................................................. 405
Table SCU (Sensor Control Unit)-175 .................................................................................................................. 406
Table SCU (Sensor Control Unit)-176 .................................................................................................................. 406
Table SCU (Sensor Control Unit)-177 .................................................................................................................. 407
Table SCU (Sensor Control Unit)-178 .................................................................................................................. 409
Table SCU (Sensor Control Unit)-179 .................................................................................................................. 411
Table SCU (Sensor Control Unit)-180 .................................................................................................................. 412
Table SCU (Sensor Control Unit)-181 .................................................................................................................. 413
Table SCU (Sensor Control Unit)-182 .................................................................................................................. 413
Table SCU (Sensor Control Unit)-183 .................................................................................................................. 414
Table SCU (Sensor Control Unit)-184 .................................................................................................................. 415
Table SCU (Sensor Control Unit)-185 .................................................................................................................. 415
Table SCU (Sensor Control Unit)-186 .................................................................................................................. 416－18/1293－

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Table SCU (Sensor Control Unit)-187 .................................................................................................................. 416
Table SCU (Sensor Control Unit)-188 .................................................................................................................. 417
Table SCU (Sensor Control Unit)-189 .................................................................................................................. 417
Table SCU (Sensor Control Unit)-190 .................................................................................................................. 418
Table SCU (Sensor Control Unit)-191 .................................................................................................................. 418
Table SCU (Sensor Control Unit)-192 .................................................................................................................. 419
Table SCU (Sensor Control Unit)-193 .................................................................................................................. 419
Table SCU (Sensor Control Unit)-194 .................................................................................................................. 420
Table SCU (Sensor Control Unit)-195 .................................................................................................................. 421
Table SCU (Sensor Control Unit)-196 .................................................................................................................. 421
Table SCU (Sensor Control Unit)-197 .................................................................................................................. 422
Table SCU (Sensor Control Unit)-198 .................................................................................................................. 422
Table SCU (Sensor Control Unit)-199 .................................................................................................................. 423
Table SCU (Sensor Control Unit)-200 .................................................................................................................. 423
Table SCU (Sensor Control Unit)-201 .................................................................................................................. 424
Table SCU (Sensor Control Unit)-202 .................................................................................................................. 424
Table SCU (Sensor Control Unit)-203 .................................................................................................................. 425
Table SCU (Sensor Control Unit)-204 .................................................................................................................. 425
Table SCU (Sensor Control Unit)-205 .................................................................................................................. 426
Table SCU (Sensor Control Unit)-206 .................................................................................................................. 427
Table SCU (Sensor Control Unit)-207 .................................................................................................................. 427
Table SCU (Sensor Control Unit)-208 .................................................................................................................. 428
Table SCU (Sensor Control Unit)-209 .................................................................................................................. 428
Table SCU (Sensor Control Unit)-210 .................................................................................................................. 429
Table SCU (Sensor Control Unit)-211 .................................................................................................................. 429
Table SCU (Sensor Control Unit)-212 .................................................................................................................. 430
Table SCU (Sensor Control Unit)-213 .................................................................................................................. 430
Table SCU (Sensor Control Unit)-214 .................................................................................................................. 431
Table SCU (Sensor Control Unit)-215 .................................................................................................................. 431
Table SCU (Sensor Control Unit)-216 .................................................................................................................. 432
Table SCU (Sensor Control Unit)-217 .................................................................................................................. 433
Table SCU (Sensor Control Unit)-218 .................................................................................................................. 433
Table SCU (Sensor Control Unit)-219 .................................................................................................................. 434
Table SCU (Sensor Control Unit)-220 .................................................................................................................. 434
Table SCU (Sensor Control Unit)-221 .................................................................................................................. 435
Table SCU (Sensor Control Unit)-222 .................................................................................................................. 435
Table SCU (Sensor Control Unit)-223 .................................................................................................................. 436
Table SCU (Sensor Control Unit)-224 .................................................................................................................. 436
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Table SCU (Sensor Control Unit)-226 .................................................................................................................. 437
Table SCU (Sensor Control Unit)-227 .................................................................................................................. 438
Table SCU (Sensor Control Unit)-228 .................................................................................................................. 439
Table SCU (Sensor Control Unit)-229 .................................................................................................................. 439
Table SCU (Sensor Control Unit)-230 .................................................................................................................. 440
Table SCU (Sensor Control Unit)-231 .................................................................................................................. 440
Table SCU (Sensor Control Unit)-232 .................................................................................................................. 441
Table SCU (Sensor Control Unit)-233 .................................................................................................................. 441
Table SCU (Sensor Control Unit)-234 .................................................................................................................. 442
Table SCU (Sensor Control Unit)-235 .................................................................................................................. 442
Table SCU (Sensor Control Unit)-236 .................................................................................................................. 443
Table SCU (Sensor Control Unit)-237 .................................................................................................................. 443
Table SCU (Sensor Control Unit)-238 .................................................................................................................. 444
Table SCU (Sensor Control Unit)-239 .................................................................................................................. 445
Table SCU (Sensor Control Unit)-240 .................................................................................................................. 445
Table SCU (Sensor Control Unit)-241 .................................................................................................................. 446
Table SCU (Sensor Control Unit)-242 .................................................................................................................. 446
Table SCU (Sensor Control Unit)-243 .................................................................................................................. 447
Table SCU (Sensor Control Unit)-244 .................................................................................................................. 447
Table SCU (Sensor Control Unit)-245 .................................................................................................................. 448
Table SCU (Sensor Control Unit)-246 .................................................................................................................. 448
Table SCU (Sensor Control Unit)-247 .................................................................................................................. 449
Table SCU (Sensor Control Unit)-248 .................................................................................................................. 449
Table SCU (Sensor Control Unit)-249 .................................................................................................................. 450
Table SCU (Sensor Control Unit)-250 .................................................................................................................. 451
Table SCU (Sensor Control Unit)-251 .................................................................................................................. 451
Table SCU (Sensor Control Unit)-252 .................................................................................................................. 452
Table SCU (Sensor Control Unit)-253 .................................................................................................................. 453
Table SCU (Sensor Control Unit)-254 .................................................................................................................. 454
Table SCU (Sensor Control Unit)-255 .................................................................................................................. 454
Table SCU (Sensor Control Unit)-256 .................................................................................................................. 455
Table SCU (Sensor Control Unit)-257 .................................................................................................................. 456
Table SCU (Sensor Control Unit)-258 .................................................................................................................. 457
Table SCU (Sensor Control Unit)-259 .................................................................................................................. 457
Table SCU (Sensor Control Unit)-260 .................................................................................................................. 458
Table SCU (Sensor Control Unit)-261 .................................................................................................................. 459
Table SCU (Sensor Control Unit)-262 .................................................................................................................. 459
Table SCU (Sensor Control Unit)-263 .................................................................................................................. 460
Table SCU (Sensor Control Unit)-264 .................................................................................................................. 461－20/1293－

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Table SCU (Sensor Control Unit)-265 .................................................................................................................. 461
Table SCU (Sensor Control Unit)-266 .................................................................................................................. 462
Table SCU (Sensor Control Unit)-267 .................................................................................................................. 462
Table SCU (Sensor Control Unit)-268 .................................................................................................................. 463
Table SCU (Sensor Control Unit)-269 .................................................................................................................. 463
Table SCU (Sensor Control Unit)-270 .................................................................................................................. 464
Table SCU (Sensor Control Unit)-271 .................................................................................................................. 464
Table SCU (Sensor Control Unit)-272 .................................................................................................................. 465
Table SCU (Sensor Control Unit)-273 .................................................................................................................. 465
Table SCU (Sensor Control Unit)-274 .................................................................................................................. 466
Table SCU (Sensor Control Unit)-275 .................................................................................................................. 466
Table SCU (Sensor Control Unit)-276 .................................................................................................................. 467
Table SCU (Sensor Control Unit)-277 .................................................................................................................. 468
Table SCU (Sensor Control Unit)-278 .................................................................................................................. 470
Table SCU (Sensor Control Unit)-279 .................................................................................................................. 472
Table SCU (Sensor Control Unit)-280 .................................................................................................................. 474
Table SCU (Sensor Control Unit)-281 .................................................................................................................. 476
Table SCU (Sensor Control Unit)-282 .................................................................................................................. 478
Table SCU (Sensor Control Unit)-283 .................................................................................................................. 480
Table SCU (Sensor Control Unit)-284 .................................................................................................................. 482
Table SCU (Sensor Control Unit)-285 .................................................................................................................. 484
Table SCU (Sensor Control Unit)-286 .................................................................................................................. 485
Table SCU (Sensor Control Unit)-287 .................................................................................................................. 487
Table SCU (Sensor Control Unit)-288 .................................................................................................................. 489
Table SCU (Sensor Control Unit)-289 .................................................................................................................. 490
Table SCU (Sensor Control Unit)-290 .................................................................................................................. 491
Table SCU (Sensor Control Unit)-291 .................................................................................................................. 492
Table SCU (Sensor Control Unit)-292 .................................................................................................................. 493
Table SCU (Sensor Control Unit)-293 .................................................................................................................. 494
Table SCU (Sensor Control Unit)-294 .................................................................................................................. 496
Table SCU (Sensor Control Unit)-295 .................................................................................................................. 498
Table SCU (Sensor Control Unit)-296 .................................................................................................................. 500
Table SCU (Sensor Control Unit)-297 .................................................................................................................. 502
Table SCU (Sensor Control Unit)-298 .................................................................................................................. 504
Table SCU (Sensor Control Unit)-299 .................................................................................................................. 504
Table SCU (Sensor Control Unit)-300 .................................................................................................................. 505
Table SCU (Sensor Control Unit)-301 .................................................................................................................. 506
Table SCU (Sensor Control Unit)-302 .................................................................................................................. 507
Table SCU (Sensor Control Unit)-303 .................................................................................................................. 508－21/1293－

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Table SCU (Sensor Control Unit)-304 .................................................................................................................. 509
Table SCU (Sensor Control Unit)-305 .................................................................................................................. 510
Table SCU (Sensor Control Unit)-306 .................................................................................................................. 511
Table SCU (Sensor Control Unit)-307 .................................................................................................................. 512
Table SCU (Sensor Control Unit)-308 .................................................................................................................. 513
Table SCU (Sensor Control Unit)-309 .................................................................................................................. 513
Table SCU (Sensor Control Unit)-310 .................................................................................................................. 514
Table SCU (Sensor Control Unit)-311 .................................................................................................................. 515
Table SCU (Sensor Control Unit)-312 .................................................................................................................. 515
Table SCU (Sensor Control Unit)-313 .................................................................................................................. 516
Table SCU (Sensor Control Unit)-314 .................................................................................................................. 517
Table SCU (Sensor Control Unit)-315 .................................................................................................................. 517
Table SCU (Sensor Control Unit)-316 .................................................................................................................. 518
Table SCU (Sensor Control Unit)-317 .................................................................................................................. 519
Table SCU (Sensor Control Unit)-318 .................................................................................................................. 520
Table SCU (Sensor Control Unit)-319 .................................................................................................................. 521
Table SCU (Sensor Control Unit)-320 .................................................................................................................. 522
Table SCU (Sensor Control Unit)-321 .................................................................................................................. 523
Table SCU (Sensor Control Unit)-322 .................................................................................................................. 524
Table SCU (Sensor Control Unit)-323 .................................................................................................................. 525
Table SCU (Sensor Control Unit)-324 .................................................................................................................. 526
Table SCU (Sensor Control Unit)-325 .................................................................................................................. 527
Table SCU (Sensor Control Unit)-326 .................................................................................................................. 528
Table SCU (Sensor Control Unit)-327 .................................................................................................................. 529
Table SCU (Sensor Control Unit)-328 .................................................................................................................. 530
Table SCU (Sensor Control Unit)-329 .................................................................................................................. 531
Table SCU (Sensor Control Unit)-330 .................................................................................................................. 532
Table SCU (Sensor Control Unit)-331 .................................................................................................................. 533
Table SCU (Sensor Control Unit)-332 .................................................................................................................. 534
Table SCU (Sensor Control Unit)-333 .................................................................................................................. 535
Table SCU (Sensor Control Unit)-334 .................................................................................................................. 536
Table SCU (Sensor Control Unit)-335 .................................................................................................................. 537
Table SCU (Sensor Control Unit)-336 .................................................................................................................. 538
Table SCU (Sensor Control Unit)-337 .................................................................................................................. 539
Table SCU (Sensor Control Unit)-338 .................................................................................................................. 540
Table SCU (Sensor Control Unit)-339 .................................................................................................................. 540
Table SCU (Sensor Control Unit)-340 .................................................................................................................. 541
Table SCU (Sensor Control Unit)-341 .................................................................................................................. 541
Table SCU (Sensor Control Unit)-342 .................................................................................................................. 542－22/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-343 .................................................................................................................. 542
Table SCU (Sensor Control Unit)-344 .................................................................................................................. 543
Table SCU (Sensor Control Unit)-345 .................................................................................................................. 543
Table SCU (Sensor Control Unit)-346 .................................................................................................................. 544
Table SCU (Sensor Control Unit)-347 .................................................................................................................. 545
Table SCU (Sensor Control Unit)-348 .................................................................................................................. 546
Table SCU (Sensor Control Unit)-349 .................................................................................................................. 546
Table SCU (Sensor Control Unit)-350 .................................................................................................................. 547
Table SCU (Sensor Control Unit)-351 .................................................................................................................. 548
Table SCU (Sensor Control Unit)-352 .................................................................................................................. 549
Table SCU (Sensor Control Unit)-353 .................................................................................................................. 550
Table SCU (Sensor Control Unit)-354 .................................................................................................................. 550
Table SCU (Sensor Control Unit)-355 .................................................................................................................. 551
Table SCU (Sensor Control Unit)-356 .................................................................................................................. 551
Table SCU (Sensor Control Unit)-357 .................................................................................................................. 552
Table SCU (Sensor Control Unit)-358 .................................................................................................................. 553
Table SCU (Sensor Control Unit)-359 .................................................................................................................. 554
Table SCU (Sensor Control Unit)-360 .................................................................................................................. 554
Table SCU (Sensor Control Unit)-361 .................................................................................................................. 555
Table SCU (Sensor Control Unit)-362 .................................................................................................................. 556
Table SCU (Sensor Control Unit)-363 .................................................................................................................. 558
Table SCU (Sensor Control Unit)-364 .................................................................................................................. 559
Table SCU (Sensor Control Unit)-365 .................................................................................................................. 560
Table SCU (Sensor Control Unit)-366 .................................................................................................................. 561
Table SCU (Sensor Control Unit)-367 .................................................................................................................. 562
Table SCU (Sensor Control Unit)-368 .................................................................................................................. 563
Table SCU (Sensor Control Unit)-369 .................................................................................................................. 563
Table SCU (Sensor Control Unit)-370 .................................................................................................................. 564
Table SCU (Sensor Control Unit)-371 .................................................................................................................. 565
Table SCU (Sensor Control Unit)-372 .................................................................................................................. 565
Table SCU (Sensor Control Unit)-373 SCU_FIFO_REG Register List................................................................ 566
Table SCU (Sensor Control Unit)-374 .................................................................................................................. 576
Table SCU (Sensor Control Unit)-375 .................................................................................................................. 577
Table SCU (Sensor Control Unit)-376 .................................................................................................................. 578
Table SCU (Sensor Control Unit)-377 .................................................................................................................. 579
Table SCU (Sensor Control Unit)-378 .................................................................................................................. 579
Table SCU (Sensor Control Unit)-379 .................................................................................................................. 580
Table SCU (Sensor Control Unit)-380 .................................................................................................................. 581
Table SCU (Sensor Control Unit)-381 .................................................................................................................. 582－23/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-382 .................................................................................................................. 583
Table SCU (Sensor Control Unit)-383 .................................................................................................................. 583
Table SCU (Sensor Control Unit)-384 .................................................................................................................. 584
Table SCU (Sensor Control Unit)-385 .................................................................................................................. 585
Table SCU (Sensor Control Unit)-386 .................................................................................................................. 586
Table SCU (Sensor Control Unit)-387 .................................................................................................................. 587
Table SCU (Sensor Control Unit)-388 .................................................................................................................. 587
Table SCU (Sensor Control Unit)-389 .................................................................................................................. 588
Table SCU (Sensor Control Unit)-390 .................................................................................................................. 589
Table SCU (Sensor Control Unit)-391 .................................................................................................................. 590
Table SCU (Sensor Control Unit)-392 .................................................................................................................. 591
Table SCU (Sensor Control Unit)-393 .................................................................................................................. 591
Table SCU (Sensor Control Unit)-394 .................................................................................................................. 592
Table SCU (Sensor Control Unit)-395 .................................................................................................................. 593
Table SCU (Sensor Control Unit)-396 .................................................................................................................. 594
Table SCU (Sensor Control Unit)-397 .................................................................................................................. 595
Table SCU (Sensor Control Unit)-398 .................................................................................................................. 595
Table SCU (Sensor Control Unit)-399 .................................................................................................................. 596
Table SCU (Sensor Control Unit)-400 .................................................................................................................. 597
Table SCU (Sensor Control Unit)-401 .................................................................................................................. 598
Table SCU (Sensor Control Unit)-402 .................................................................................................................. 599
Table SCU (Sensor Control Unit)-403 .................................................................................................................. 599
Table SCU (Sensor Control Unit)-404 .................................................................................................................. 600
Table SCU (Sensor Control Unit)-405 .................................................................................................................. 601
Table SCU (Sensor Control Unit)-406 .................................................................................................................. 602
Table SCU (Sensor Control Unit)-407 .................................................................................................................. 603
Table SCU (Sensor Control Unit)-408 .................................................................................................................. 603
Table SCU (Sensor Control Unit)-409 .................................................................................................................. 604
Table SCU (Sensor Control Unit)-410 .................................................................................................................. 605
Table SCU (Sensor Control Unit)-411 .................................................................................................................. 606
Table SCU (Sensor Control Unit)-412 .................................................................................................................. 607
Table SCU (Sensor Control Unit)-413 .................................................................................................................. 607
Table SCU (Sensor Control Unit)-414 .................................................................................................................. 608
Table SCU (Sensor Control Unit)-415 .................................................................................................................. 609
Table SCU (Sensor Control Unit)-416 .................................................................................................................. 610
Table SCU (Sensor Control Unit)-417 .................................................................................................................. 611
Table SCU (Sensor Control Unit)-418 .................................................................................................................. 611
Table SCU (Sensor Control Unit)-419 .................................................................................................................. 612
Table SCU (Sensor Control Unit)-420 .................................................................................................................. 613－24/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-421 .................................................................................................................. 614
Table SCU (Sensor Control Unit)-422 .................................................................................................................. 615
Table SCU (Sensor Control Unit)-423 .................................................................................................................. 615
Table SCU (Sensor Control Unit)-424 .................................................................................................................. 616
Table SCU (Sensor Control Unit)-425 .................................................................................................................. 617
Table SCU (Sensor Control Unit)-426 .................................................................................................................. 618
Table SCU (Sensor Control Unit)-427 .................................................................................................................. 619
Table SCU (Sensor Control Unit)-428 .................................................................................................................. 619
Table SCU (Sensor Control Unit)-429 .................................................................................................................. 620
Table SCU (Sensor Control Unit)-430 .................................................................................................................. 621
Table SCU (Sensor Control Unit)-431 .................................................................................................................. 622
Table SCU (Sensor Control Unit)-432 .................................................................................................................. 623
Table SCU (Sensor Control Unit)-433 .................................................................................................................. 623
Table SCU (Sensor Control Unit)-434 .................................................................................................................. 624
Table SCU (Sensor Control Unit)-435 .................................................................................................................. 625
Table SCU (Sensor Control Unit)-436 .................................................................................................................. 626
Table SCU (Sensor Control Unit)-437 .................................................................................................................. 627
Table SCU (Sensor Control Unit)-438 .................................................................................................................. 627
Table SCU (Sensor Control Unit)-439 .................................................................................................................. 628
Table SCU (Sensor Control Unit)-440 .................................................................................................................. 629
Table SCU (Sensor Control Unit)-441 .................................................................................................................. 630
Table SCU (Sensor Control Unit)-442 .................................................................................................................. 631
Table SCU (Sensor Control Unit)-443 .................................................................................................................. 631
Table SCU (Sensor Control Unit)-444 .................................................................................................................. 632
Table SCU (Sensor Control Unit)-445 .................................................................................................................. 633
Table SCU (Sensor Control Unit)-446 .................................................................................................................. 634
Table SCU (Sensor Control Unit)-447 .................................................................................................................. 635
Table SCU (Sensor Control Unit)-448 .................................................................................................................. 635
Table SCU (Sensor Control Unit)-449 .................................................................................................................. 636
Table SCU (Sensor Control Unit)-450 .................................................................................................................. 637
Table SCU (Sensor Control Unit)-451 .................................................................................................................. 638
Table SCU (Sensor Control Unit)-452 .................................................................................................................. 639
Table SCU (Sensor Control Unit)-453 .................................................................................................................. 639
Table SCU (Sensor Control Unit)-454 .................................................................................................................. 640
Table SCU (Sensor Control Unit)-455 .................................................................................................................. 641
Table SCU (Sensor Control Unit)-456 .................................................................................................................. 642
Table SCU (Sensor Control Unit)-457 .................................................................................................................. 643
Table SCU (Sensor Control Unit)-458 .................................................................................................................. 643
Table SCU (Sensor Control Unit)-459 .................................................................................................................. 644－25/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-460 .................................................................................................................. 644
Table SCU (Sensor Control Unit)-461 .................................................................................................................. 645
Table SCU (Sensor Control Unit)-462 .................................................................................................................. 646
Table SCU (Sensor Control Unit)-463 .................................................................................................................. 647
Table SCU (Sensor Control Unit)-464 .................................................................................................................. 648
Table SCU (Sensor Control Unit)-465 .................................................................................................................. 648
Table SCU (Sensor Control Unit)-466 .................................................................................................................. 649
Table SCU (Sensor Control Unit)-467 .................................................................................................................. 649
Table SCU (Sensor Control Unit)-468 .................................................................................................................. 650
Table SCU (Sensor Control Unit)-469 .................................................................................................................. 651
Table SCU (Sensor Control Unit)-470 .................................................................................................................. 652
Table SCU (Sensor Control Unit)-471 .................................................................................................................. 653
Table SCU (Sensor Control Unit)-472 .................................................................................................................. 653
Table SCU (Sensor Control Unit)-473 .................................................................................................................. 654
Table SCU (Sensor Control Unit)-474 .................................................................................................................. 654
Table SCU (Sensor Control Unit)-475 .................................................................................................................. 655
Table SCU (Sensor Control Unit)-476 .................................................................................................................. 656
Table SCU (Sensor Control Unit)-477 .................................................................................................................. 657
Table SCU (Sensor Control Unit)-478 .................................................................................................................. 658
Table SCU (Sensor Control Unit)-479 .................................................................................................................. 658
Table SCU (Sensor Control Unit)-480 .................................................................................................................. 659
Table SCU (Sensor Control Unit)-481 .................................................................................................................. 659
Table SCU (Sensor Control Unit)-482 .................................................................................................................. 660
Table SCU (Sensor Control Unit)-483 .................................................................................................................. 661
Table SCU (Sensor Control Unit)-484 .................................................................................................................. 662
Table SCU (Sensor Control Unit)-485 .................................................................................................................. 663
Table SCU (Sensor Control Unit)-486 .................................................................................................................. 663
Table SCU (Sensor Control Unit)-487 .................................................................................................................. 664
Table SCU (Sensor Control Unit)-488 .................................................................................................................. 664
Table SCU (Sensor Control Unit)-489 .................................................................................................................. 665
Table SCU (Sensor Control Unit)-490 .................................................................................................................. 666
Table SCU (Sensor Control Unit)-491 .................................................................................................................. 667
Table SCU (Sensor Control Unit)-492 .................................................................................................................. 668
Table SCU (Sensor Control Unit)-493 .................................................................................................................. 668
Table SCU (Sensor Control Unit)-494 .................................................................................................................. 669
Table SCU (Sensor Control Unit)-495 .................................................................................................................. 669
Table SCU (Sensor Control Unit)-496 .................................................................................................................. 670
Table SCU (Sensor Control Unit)-497 .................................................................................................................. 671
Table SCU (Sensor Control Unit)-498 .................................................................................................................. 672－26/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-499 .................................................................................................................. 673
Table SCU (Sensor Control Unit)-500 .................................................................................................................. 673
Table SCU (Sensor Control Unit)-501 .................................................................................................................. 674
Table SCU (Sensor Control Unit)-502 .................................................................................................................. 674
Table SCU (Sensor Control Unit)-503 .................................................................................................................. 675
Table SCU (Sensor Control Unit)-504 .................................................................................................................. 676
Table SCU (Sensor Control Unit)-505 .................................................................................................................. 677
Table SCU (Sensor Control Unit)-506 .................................................................................................................. 678
Table SCU (Sensor Control Unit)-507 .................................................................................................................. 678
Table SCU (Sensor Control Unit)-508 .................................................................................................................. 679
Table SCU (Sensor Control Unit)-509 .................................................................................................................. 679
Table SCU (Sensor Control Unit)-510 .................................................................................................................. 680
Table SCU (Sensor Control Unit)-511 .................................................................................................................. 681
Table SCU (Sensor Control Unit)-512 .................................................................................................................. 682
Table SCU (Sensor Control Unit)-513 .................................................................................................................. 683
Table SCU (Sensor Control Unit)-514 .................................................................................................................. 683
Table SCU (Sensor Control Unit)-515 .................................................................................................................. 684
Table SCU (Sensor Control Unit)-516 .................................................................................................................. 684
Table SCU (Sensor Control Unit)-517 .................................................................................................................. 685
Table SCU (Sensor Control Unit)-518 .................................................................................................................. 686
Table SCU (Sensor Control Unit)-519 .................................................................................................................. 687
Table SCU (Sensor Control Unit)-520 .................................................................................................................. 688
Table SCU (Sensor Control Unit)-521 .................................................................................................................. 688
Table SCU (Sensor Control Unit)-522 .................................................................................................................. 689
Table SCU (Sensor Control Unit)-523 .................................................................................................................. 689
Table SCU (Sensor Control Unit)-524 .................................................................................................................. 690
Table SCU (Sensor Control Unit)-525 .................................................................................................................. 691
Table SCU (Sensor Control Unit)-526 .................................................................................................................. 692
Table SCU (Sensor Control Unit)-527 .................................................................................................................. 693
Table SCU (Sensor Control Unit)-528 .................................................................................................................. 694
Table SCU (Sensor Control Unit)-529 .................................................................................................................. 694
Table SCU (Sensor Control Unit)-530 .................................................................................................................. 695
Table SCU (Sensor Control Unit)-531 .................................................................................................................. 696
Table SCU (Sensor Control Unit)-532 .................................................................................................................. 697
Table SCU (Sensor Control Unit)-533 .................................................................................................................. 698
Table SCU (Sensor Control Unit)-534 .................................................................................................................. 699
Table SCU (Sensor Control Unit)-535 .................................................................................................................. 699
Table SCU (Sensor Control Unit)-536 .................................................................................................................. 700
Table SCU (Sensor Control Unit)-537 .................................................................................................................. 701－27/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-538 .................................................................................................................. 702
Table SCU (Sensor Control Unit)-539 .................................................................................................................. 703
Table SCU (Sensor Control Unit)-540 .................................................................................................................. 704
Table SCU (Sensor Control Unit)-541 .................................................................................................................. 704
Table SCU (Sensor Control Unit)-542 .................................................................................................................. 705
Table SCU (Sensor Control Unit)-543 .................................................................................................................. 706
Table SCU (Sensor Control Unit)-544 .................................................................................................................. 707
Table SCU (Sensor Control Unit)-545 .................................................................................................................. 708
Table SCU (Sensor Control Unit)-546 .................................................................................................................. 709
Table SCU (Sensor Control Unit)-547 .................................................................................................................. 709
Table SCU (Sensor Control Unit)-548 .................................................................................................................. 710
Table SCU (Sensor Control Unit)-549 .................................................................................................................. 711
Table SCU (Sensor Control Unit)-550 .................................................................................................................. 712
Table SCU (Sensor Control Unit)-551 .................................................................................................................. 713
Table SCU (Sensor Control Unit)-552 .................................................................................................................. 714
Table SCU (Sensor Control Unit)-553 .................................................................................................................. 714
Table SCU (Sensor Control Unit)-554 .................................................................................................................. 715
Table SCU (Sensor Control Unit)-555 .................................................................................................................. 716
Table SCU (Sensor Control Unit)-556 .................................................................................................................. 717
Table SCU (Sensor Control Unit)-557 .................................................................................................................. 718
Table SCU (Sensor Control Unit)-558 .................................................................................................................. 719
Table SCU (Sensor Control Unit)-559 .................................................................................................................. 719
Table SCU (Sensor Control Unit)-560 .................................................................................................................. 720
Table SCU (Sensor Control Unit)-561 .................................................................................................................. 721
Table SCU (Sensor Control Unit)-562 .................................................................................................................. 722
Table SCU (Sensor Control Unit)-563 .................................................................................................................. 723
Table SCU (Sensor Control Unit)-564 .................................................................................................................. 724
Table SCU (Sensor Control Unit)-565 .................................................................................................................. 724
Table SCU (Sensor Control Unit)-566 .................................................................................................................. 725
Table SCU (Sensor Control Unit)-567 .................................................................................................................. 726
Table SCU (Sensor Control Unit)-568 .................................................................................................................. 727
Table SCU (Sensor Control Unit)-569 .................................................................................................................. 728
Table SCU (Sensor Control Unit)-570 .................................................................................................................. 729
Table SCU (Sensor Control Unit)-571 .................................................................................................................. 729
Table SCU (Sensor Control Unit)-572 .................................................................................................................. 730
Table SCU (Sensor Control Unit)-573 .................................................................................................................. 731
Table SCU (Sensor Control Unit)-574 .................................................................................................................. 732
Table SCU (Sensor Control Unit)-575 .................................................................................................................. 733
Table SCU (Sensor Control Unit)-576 .................................................................................................................. 734－28/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-577 .................................................................................................................. 734
Table SCU (Sensor Control Unit)-578 .................................................................................................................. 735
Table SCU (Sensor Control Unit)-579 .................................................................................................................. 736
Table SCU (Sensor Control Unit)-580 .................................................................................................................. 737
Table SCU (Sensor Control Unit)-581 .................................................................................................................. 738
Table SCU (Sensor Control Unit)-582 .................................................................................................................. 739
Table SCU (Sensor Control Unit)-583 .................................................................................................................. 739
Table SCU (Sensor Control Unit)-584 .................................................................................................................. 740
Table SCU (Sensor Control Unit)-585 .................................................................................................................. 741
Table SCU (Sensor Control Unit)-586 .................................................................................................................. 742
Table SCU (Sensor Control Unit)-587 .................................................................................................................. 743
Table SCU (Sensor Control Unit)-588 .................................................................................................................. 744
Table SCU (Sensor Control Unit)-589 .................................................................................................................. 744
Table SCU (Sensor Control Unit)-590 .................................................................................................................. 745
Table SCU (Sensor Control Unit)-591 .................................................................................................................. 746
Table SCU (Sensor Control Unit)-592 .................................................................................................................. 747
Table SCU (Sensor Control Unit)-593 .................................................................................................................. 748
Table SCU (Sensor Control Unit)-594 .................................................................................................................. 749
Table SCU (Sensor Control Unit)-595 .................................................................................................................. 749
Table SCU (Sensor Control Unit)-596 .................................................................................................................. 750
Table SCU (Sensor Control Unit)-597 .................................................................................................................. 751
Table SCU (Sensor Control Unit)-598 .................................................................................................................. 752
Table SCU (Sensor Control Unit)-599 .................................................................................................................. 753
Table SCU (Sensor Control Unit)-600 .................................................................................................................. 754
Table SCU (Sensor Control Unit)-601 .................................................................................................................. 754
Table SCU (Sensor Control Unit)-602 .................................................................................................................. 755
Table SCU (Sensor Control Unit)-603 .................................................................................................................. 756
Table SCU (Sensor Control Unit)-604 .................................................................................................................. 757
Table SCU (Sensor Control Unit)-605 .................................................................................................................. 758
Table SCU (Sensor Control Unit)-606 .................................................................................................................. 759
Table SCU (Sensor Control Unit)-607 .................................................................................................................. 759
Table SCU (Sensor Control Unit)-608 .................................................................................................................. 760
Table SCU (Sensor Control Unit)-609 .................................................................................................................. 761
Table SCU (Sensor Control Unit)-610 .................................................................................................................. 762
Table SCU (Sensor Control Unit)-611 .................................................................................................................. 763
Table SCU (Sensor Control Unit)-612 .................................................................................................................. 764
Table SCU (Sensor Control Unit)-613 .................................................................................................................. 764
Table SCU (Sensor Control Unit)-614 .................................................................................................................. 765
Table SCU (Sensor Control Unit)-615 .................................................................................................................. 766－29/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-616 .................................................................................................................. 767
Table SCU (Sensor Control Unit)-617 .................................................................................................................. 768
Table SCU (Sensor Control Unit)-618 .................................................................................................................. 769
Table SCU (Sensor Control Unit)-619 .................................................................................................................. 769
Table SCU (Sensor Control Unit)-620 .................................................................................................................. 770
Table SCU (Sensor Control Unit)-621 .................................................................................................................. 771
Table SCU (Sensor Control Unit)-622 .................................................................................................................. 772
Table SCU (Sensor Control Unit)-623 .................................................................................................................. 773
Table SCU (Sensor Control Unit)-624 .................................................................................................................. 774
Table SCU (Sensor Control Unit)-625 .................................................................................................................. 774
Table SCU (Sensor Control Unit)-626 .................................................................................................................. 775
Table SCU (Sensor Control Unit)-627 .................................................................................................................. 776
Table SCU (Sensor Control Unit)-628 .................................................................................................................. 777
Table SCU (Sensor Control Unit)-629 .................................................................................................................. 778
Table SCU (Sensor Control Unit)-630 .................................................................................................................. 779
Table SCU (Sensor Control Unit)-631 .................................................................................................................. 779
Table SCU (Sensor Control Unit)-632 .................................................................................................................. 780
Table SCU (Sensor Control Unit)-633 .................................................................................................................. 781
Table SCU (Sensor Control Unit)-634 .................................................................................................................. 782
Table SCU (Sensor Control Unit)-635 .................................................................................................................. 783
Table SCU (Sensor Control Unit)-636 .................................................................................................................. 784
Table SCU (Sensor Control Unit)-637 .................................................................................................................. 784
Table SCU (Sensor Control Unit)-638 .................................................................................................................. 785
Table SCU (Sensor Control Unit)-639 .................................................................................................................. 786
Table SCU (Sensor Control Unit)-640 .................................................................................................................. 787
Table SCU (Sensor Control Unit)-641 .................................................................................................................. 788
Table SCU (Sensor Control Unit)-642 .................................................................................................................. 789
Table SCU (Sensor Control Unit)-643 .................................................................................................................. 789
Table SCU (Sensor Control Unit)-644 .................................................................................................................. 790
Table SCU (Sensor Control Unit)-645 .................................................................................................................. 791
Table SCU (Sensor Control Unit)-646 .................................................................................................................. 792
Table SCU (Sensor Control Unit)-647 .................................................................................................................. 793
Table SCU (Sensor Control Unit)-648 .................................................................................................................. 794
Table SCU (Sensor Control Unit)-649 .................................................................................................................. 794
Table SCU (Sensor Control Unit)-650 .................................................................................................................. 795
Table SCU (Sensor Control Unit)-651 .................................................................................................................. 796
Table SCU (Sensor Control Unit)-652 .................................................................................................................. 797
Table SCU (Sensor Control Unit)-653 .................................................................................................................. 798
Table SCU (Sensor Control Unit)-654 .................................................................................................................. 799－30/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-655 .................................................................................................................. 799
Table SCU (Sensor Control Unit)-656 .................................................................................................................. 800
Table SCU (Sensor Control Unit)-657 .................................................................................................................. 801
Table SCU (Sensor Control Unit)-658 .................................................................................................................. 802
Table SCU (Sensor Control Unit)-659 .................................................................................................................. 803
Table SCU (Sensor Control Unit)-660 .................................................................................................................. 804
Table SCU (Sensor Control Unit)-661 .................................................................................................................. 804
Table SCU (Sensor Control Unit)-662 .................................................................................................................. 805
Table SCU (Sensor Control Unit)-663 .................................................................................................................. 806
Table SCU (Sensor Control Unit)-664 .................................................................................................................. 807
Table SCU (Sensor Control Unit)-665 .................................................................................................................. 808
Table SCU (Sensor Control Unit)-666 .................................................................................................................. 809
Table SCU (Sensor Control Unit)-667 .................................................................................................................. 809
Table SCU (Sensor Control Unit)-668 .................................................................................................................. 810
Table SCU (Sensor Control Unit)-669 .................................................................................................................. 811
Table SCU (Sensor Control Unit)-670 .................................................................................................................. 812
Table SCU (Sensor Control Unit)-671 .................................................................................................................. 813
Table SCU (Sensor Control Unit)-672 .................................................................................................................. 814
Table SCU (Sensor Control Unit)-673 .................................................................................................................. 814
Table SCU (Sensor Control Unit)-674 .................................................................................................................. 815
Table SCU (Sensor Control Unit)-675 .................................................................................................................. 816
Table SCU (Sensor Control Unit)-676 .................................................................................................................. 817
Table SCU (Sensor Control Unit)-677 .................................................................................................................. 818
Table SCU (Sensor Control Unit)-678 .................................................................................................................. 819
Table SCU (Sensor Control Unit)-679 .................................................................................................................. 819
Table SCU (Sensor Control Unit)-680 .................................................................................................................. 820
Table SCU (Sensor Control Unit)-681 .................................................................................................................. 821
Table SCU (Sensor Control Unit)-682 .................................................................................................................. 822
Table SCU (Sensor Control Unit)-683 .................................................................................................................. 823
Table SCU (Sensor Control Unit)-684 .................................................................................................................. 824
Table SCU (Sensor Control Unit)-685 .................................................................................................................. 824
Table SCU (Sensor Control Unit)-686 .................................................................................................................. 825
Table SCU (Sensor Control Unit)-687 .................................................................................................................. 826
Table SCU (Sensor Control Unit)-688 .................................................................................................................. 827
Table SCU (Sensor Control Unit)-689 .................................................................................................................. 828
Table SCU (Sensor Control Unit)-690 .................................................................................................................. 829
Table SCU (Sensor Control Unit)-691 .................................................................................................................. 829
Table SCU (Sensor Control Unit)-692 .................................................................................................................. 830
Table SCU (Sensor Control Unit)-693 .................................................................................................................. 831－31/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-694 .................................................................................................................. 832
Table SCU (Sensor Control Unit)-695 .................................................................................................................. 833
Table SCU (Sensor Control Unit)-696 .................................................................................................................. 834
Table SCU (Sensor Control Unit)-697 .................................................................................................................. 834
Table SCU (Sensor Control Unit)-698 .................................................................................................................. 835
Table SCU (Sensor Control Unit)-699 .................................................................................................................. 836
Table SCU (Sensor Control Unit)-700 .................................................................................................................. 837
Table SCU (Sensor Control Unit)-701 .................................................................................................................. 838
Table SCU (Sensor Control Unit)-702 .................................................................................................................. 839
Table SCU (Sensor Control Unit)-703 .................................................................................................................. 839
Table SCU (Sensor Control Unit)-704 .................................................................................................................. 840
Table SCU (Sensor Control Unit)-705 .................................................................................................................. 841
Table SCU (Sensor Control Unit)-706 .................................................................................................................. 842
Table SCU (Sensor Control Unit)-707 .................................................................................................................. 843
Table SCU (Sensor Control Unit)-708 .................................................................................................................. 844
Table SCU (Sensor Control Unit)-709 .................................................................................................................. 844
Table SCU (Sensor Control Unit)-710 .................................................................................................................. 845
Table SCU (Sensor Control Unit)-711 .................................................................................................................. 846
Table SCU (Sensor Control Unit)-712 .................................................................................................................. 847
Table SCU (Sensor Control Unit)-713 .................................................................................................................. 848
Table SCU (Sensor Control Unit)-714 .................................................................................................................. 849
Table SCU (Sensor Control Unit)-715 .................................................................................................................. 849
Table SCU (Sensor Control Unit)-716 .................................................................................................................. 850
Table SCU (Sensor Control Unit)-717 .................................................................................................................. 851
Table SCU (Sensor Control Unit)-718 .................................................................................................................. 852
Table SCU (Sensor Control Unit)-719 .................................................................................................................. 853
Table SCU (Sensor Control Unit)-720 .................................................................................................................. 854
Table SCU (Sensor Control Unit)-721 .................................................................................................................. 854
Table SCU (Sensor Control Unit)-722 .................................................................................................................. 855
Table SCU (Sensor Control Unit)-723 .................................................................................................................. 856
Table SCU (Sensor Control Unit)-724 .................................................................................................................. 857
Table SCU (Sensor Control Unit)-725 .................................................................................................................. 858
Table SCU (Sensor Control Unit)-726 SCU_RAM Parameters ............................................................................ 859
Table SCU (Sensor Control Unit)-727 .................................................................................................................. 860
Table SCU (Sensor Control Unit)-728 .................................................................................................................. 860
Table SCU (Sensor Control Unit)-729 .................................................................................................................. 860
Table SCU (Sensor Control Unit)-730 .................................................................................................................. 861
Table SCU (Sensor Control Unit)-731 .................................................................................................................. 861
Table SCU (Sensor Control Unit)-732 .................................................................................................................. 862－32/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-733 .................................................................................................................. 862
Table SCU (Sensor Control Unit)-734) ................................................................................................................. 863
Table SCU (Sensor Control Unit)-735 Sequencer Instruction Formats ................................................................ 863
Table SCU (Sensor Control Unit)-736 .................................................................................................................. 864
Table SCU (Sensor Control Unit)-737 FIFO_IDs and the FIFOs linked to FIFO_ID .......................................... 865
Table SCU (Sensor Control Unit)-738 .................................................................................................................. 865
Table SCU (Sensor Control Unit)-739 .................................................................................................................. 866
Table SCU (Sensor Control Unit)-740 .................................................................................................................. 867
Table SCU (Sensor Control Unit)-741 .................................................................................................................. 867
Table SCU (Sensor Control Unit)-742 .................................................................................................................. 868
Table SCU (Sensor Control Unit)-743 .................................................................................................................. 869
Table SCU (Sensor Control Unit)-744

Power Supply Control Power ON ......................................................... 873

Table SCU (Sensor Control Unit)-745 Main Reset Control .................................................................................. 876
Table SCU (Sensor Control Unit)-746 Sub Reset Control .................................................................................... 876
Table SCU (Sensor Control Unit)-747 AD Conversion Settings .......................................................................... 878
Table SCU (Sensor Control Unit)-748 Startup Settings ........................................................................................ 878
Table SCU (Sensor Control Unit)-749 Output Disable Settings ........................................................................... 881
Table SCU (Sensor Control Unit)-750 Sequencer Startup Settings ...................................................................... 882
Table SCU (Sensor Control Unit)-751 SPI Direct Control from CPU during Sequencer Operation .................... 889
Table SCU (Sensor Control Unit)-752 I2C0 Direct Control from CPU during Sequencer Operation .................. 889
Table SCU (Sensor Control Unit)-753 I2C1 Direct Control from CPU during Sequencer Operation .................. 889
Table SCU (Sensor Control Unit)-754 LPADC Operation Initial Settings ........................................................... 891
Table SCU (Sensor Control Unit)-755 HPADC0 Operation Initial Settings......................................................... 892
Table SCU (Sensor Control Unit)-756 HPADC1 Operation Initial Settings......................................................... 892
Table SCU (Sensor Control Unit)-757 FIFO Writing Side Initial Settings ........................................................... 894
Table SCU (Sensor Control Unit)-758 FIFO Readout Side Initial Settings .......................................................... 898
Table SCU (Sensor Control Unit)-759 FIFO Write Processing ............................................................................ 902
Table SCU (Sensor Control Unit)-760 FIFO Readout Processing ........................................................................ 904
Table SCU (Sensor Control Unit)-761 Transition Process to FIFO (8 KByte) Retention..................................... 912
Table SCU (Sensor Control Unit)-762 Transition Process to FIFO (8 KByte) All ON ........................................ 913
Table SCU (Sensor Control Unit)-763 Transition Process to FIFO (8 KByte) ALL OFF .................................... 913
Table SCU (Sensor Control Unit)-764 Transition Process to FIFO (32 KByte) Retention................................... 913
Table SCU (Sensor Control Unit)-765 Transition Process to FIFO (8 KByte) All ON ........................................ 913
Table SCU (Sensor Control Unit)-766 Transition Process to FIFO (8 KByte) ALL OFF .................................... 913
Table SCU (Sensor Control Unit)-767 Errors and their Handling......................................................................... 914
Table SCU (Sensor Control Unit)-768 Conversion to 2’s Complement Format (e.g. four bit width) ................... 916
Table SCU (Sensor Control Unit)-769 MATH_PROC Registers that cannot be Dynamically Changed ............. 916
Table SCU (Sensor Control Unit)-770 Approximate Execution Times of Tasks .................................................. 923
Table SCU (Sensor Control Unit)-771 Time Stamp Fluctuation Estimated Values .............................................. 923－33/1293－

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Table SCU (Sensor Control Unit)-772 Write FIFO Initialization (excluding virtual partition) ............................ 927
Table SCU (Sensor Control Unit)-773 Read FIFO Initialization .......................................................................... 928
Table SPI-774 SPI List .......................................................................................................................................... 931
Table SPI-775 XOSC (26 MHz), High Performance Mode .................................................................................. 931
Table SPI-776 XOSC (26 MHz), Low Power Mode ............................................................................................. 932
Table SPI-777 SSPCR0 Register ........................................................................................................................... 938
Table SPI-778 SSPCR1 Register ........................................................................................................................... 943
Table SPI-779 SSPDR Register............................................................................................................................. 944
Table SPI-780 SSPSR Register ............................................................................................................................. 945
Table SPI-781 SSPCPSR Register ........................................................................................................................ 945
Table SPI-782 SSPIMSC Register ........................................................................................................................ 946
Table SPI-783 SSPRIS Register ............................................................................................................................ 946
Table SPI-784 SSPMIS Register ........................................................................................................................... 947
Table SPI-785 SSICR Register .............................................................................................................................. 947
Table SPI-786 SSPIDMACR Register .................................................................................................................. 947
Table SPI-787 CS_MODE Register ...................................................................................................................... 948
Table SPI-788 SSP_CS Register ........................................................................................................................... 948
Table SPI-789 SLAVE_TYPE Register ................................................................................................................ 948
Table UART-790 UART List ................................................................................................................................ 949
Table UART-791 XOSC (26 MHz), High Performance Mode ............................................................................. 950
Table UART-792 XOSC (26 MHz), Low Power Mode ........................................................................................ 950
Table UART-793 UARTDR Register ................................................................................................................... 954
Table UART-794 UARTRSR/UARTECR Register.............................................................................................. 955
Table UART-795 UARTFR Register .................................................................................................................... 955
Table UART-796 UARTILPR Register ................................................................................................................ 956
Table UART-797 UARTIBRD Register ............................................................................................................... 957
Table UART-798 UARTFBRD Register .............................................................................................................. 957
Table UART-799 UARTLCR_H Register ............................................................................................................ 957
Table UART-800 UARTCR Register ................................................................................................................... 959
Table UART-801 UARTIFLS Register................................................................................................................. 960
Table UART-802 UARTIMSC Register ............................................................................................................... 961
Table UART-803 UARTRIS Register................................................................................................................... 962
Table UART-804 UARTMIS Register .................................................................................................................. 963
Table UART-805 UARTICR Register .................................................................................................................. 963
Table UART-806 UARTDMACR Register .......................................................................................................... 964
Table APP-807 XOSC (26 MHz), High Performance Mode ................................................................................ 971
Table APP-808 XOSC (26 MHz), Low Power Mode ........................................................................................... 971
Table APP-809Clock Division Ratio Setting Registers......................................................................................... 974
Table APP-810 Clock Switching Registers ........................................................................................................... 974－34/1293－

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Table APP-811 Clock Enable Registers ................................................................................................................ 975
Table APP-812 Clock Reset Generator Registers ................................................................................................. 976
Table APP-813 APP SRAM Tile Clock Gating Registers .................................................................................... 980
Table APP-814 Reset Control Registers................................................................................................................ 982
Table APP-815 APP_DSP Function List............................................................................................................... 984
Table APP-816 APP_DSP Register List ............................................................................................................... 985
Table APP-817 Cortex®-M4 processor with FPU Function List ........................................................................... 987
Table APP-818 Register List ................................................................................................................................. 988
Table APP-819 Processor List ............................................................................................................................... 988
Table APP-820 WDTRES Register List ................................................................................................................ 991
Table APP-821 SLEEPING Signal Register List .................................................................................................. 991
Table APP-822 Debug Function List .................................................................................................................... 992
Table APP-823 Address Conversion Registers ..................................................................................................... 997
Table APP-824 Exclusive Access Register ......................................................................................................... 1000
Table SYSIOP Clock and Reset Control-825 XOSC (26 MHz), High Performance Mode ................................ 1012
Table SYSIOP Clock and Reset Control-826 XOSC (26 MHz), Low Power Mode ........................................... 1013
Table SYSIOP Clock and Reset Control-827 Clock Switching Status Registers ................................................ 1014
Table SYSIOP Clock and Reset Control-828 System and I/O Processor Frequency Division Setting ............... 1016
Table SYSIOP Clock and Reset Control-829 AHB Clock Frequency Division Setting ..................................... 1016
Table SYSIOP Clock and Reset Control-830 APB Clock Frequency Division Setting ...................................... 1016
Table SYSIOP Clock and Reset Control-831 Frequency Division Setting of Clock for the SPI Flash Controller......................................................................................................................................................................... 1017
Table SYSIOP Clock and Reset Control-832 Frequency Division Setting Status Registers............................... 1018
Table SYSIOP Clock and Reset Control-833 Clock Enable Status Registers ..................................................... 1022
Table SYSIOP Clock and Reset Control-834 Reset Control Registers ............................................................... 1027
Table 3.15-1

Function Limitations upon Standalone Use ............................................................................. 1035

Table 3.15-2 I2S Interface Specifications............................................................................................................ 1036
Table 3.15-3 Audio Codec Address Map ............................................................................................................ 1038
Table 3.15-4 Clock Supply Settings .................................................................................................................... 1039
Table 3.15-5 Mic Mode Settings ......................................................................................................................... 1043
Table 3.15-6 BCK Support Range by SRC1 (I2S slave mode) ........................................................................... 1050
Table 3.15-7 BCK Output Frequency by SRC1 (I2S master mode) .................................................................... 1050
Table 3.15-8 Bandwidth limitation by BLF (HI_RES_MODE:1'b1) .................................................................. 1052
Table 3.15-9 Bandwidth limitation by BLF (HI_RES_MODE:1'b0) .................................................................. 1052
Table 3.15-10 Settings by Input and Output Rate ............................................................................................... 1066
Table 3.15-11 Settings According to the Transfer Mode .................................................................................... 1068
Table 3.15-12 Transfer Channel Settings ............................................................................................................ 1075
Table 3.15-13 I2S0, I2S1 Line BUS ERROR Detection Settings ....................................................................... 1083
Table 3.15-14 Signal Processing Interrupt Status Registers (offset 0x1160) ...................................................... 1087

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Table 3.15-15 Signal Processing Interrupt Clear Registers (offset 0x115C) ....................................................... 1087
Table 3.15-16 Signal Processing Interrupt Mask Registers (offset 0x1158) ....................................................... 1088
Table 3.15-17 AHB I/F Interrupt Status Registers (offset 0x1140) ..................................................................... 1088
Table 3.15-18 AHB I/F Interrupt Status Registers (offset 0x1144) ..................................................................... 1088
Table 3.15-19 AHB I/F Interrupt Status Registers (offset 0x1148) ..................................................................... 1089
Table 3.15-20 AHB I/F Interrupt Mask Registers (offset 0x114C) ..................................................................... 1090
Table 3.15-21 AHB I/F Interrupt Mask Registers (offset 0x1150)...................................................................... 1090
Table 3.15-22 AHB I/F Interrupt Mask Registers (offset 0x1154)...................................................................... 1090
Table 3.15-23 System Control Register List ....................................................................................................... 1091
Table 3.15-24 Codec DSP Control Register List ................................................................................................. 1092
Table 3.15-25 Codec DSP Control Register List ................................................................................................. 1094
Table 3.15-26 Codec DSP Control Register List ................................................................................................. 1095
Table 3.15-27 Codec DSP Control Register List ................................................................................................. 1096
Table 3.15-28 DNC, S-Master Control Register List .......................................................................................... 1097
Table 3.15-29 CXD5247 I/F Control Register List ............................................................................................. 1098
Table 3.15-30 Decimation Filter Control Register List ....................................................................................... 1099
Table 3.15-31 DEQ Control Register List ........................................................................................................... 1099
Table 3.15-32 SRAM Register List ..................................................................................................................... 1099
Table 3.15-33 AHB I/F MIC Control Register List............................................................................................. 1100
Table 3.15-34 AHB I/F I2S0 (UP) Control Register List .................................................................................... 1101
Table 3.15-35 AHB I/F I2S1 (UP) Control Register List .................................................................................... 1101
Table 3.15-36 AHB I/F I2S0 (DOWN) Control Register List............................................................................. 1102
Table 3.15-37 AHB I/F I2S1 (DOWN) Control Register List............................................................................. 1102
Table 3.15-38 AHB I/F Other Control Register List ........................................................................................... 1103
Table 3.15-39 AHB I/F Interrupt Control Register List ...................................................................................... 1103
Table 3.15-40 Signal Processing Interrupt Control Register List ........................................................................ 1105
Table USB-41 Basic Configuration Parameters .................................................................................................. 1118
Table USB-42 UDC-AHB Subsystem Configuration Parameters....................................................................... 1119
Table USB-43 UDC-AHB Subsystem Configuration Parameters (Continued) .................................................. 1120
Table USB-878 UDC-AHB Subsystem Configuration Parameters (Continued) ................................................ 1121
Table USB-879 UDC-AHB Subsystem Configuration Parameters (Continued) ................................................ 1122
Table USB-880 UDC-AHB Subsystem Configuration Parameters (Continued) ................................................ 1123
Table USB-881 Device Configuration Register .................................................................................................. 1132
Table USB-882 Device Configuration Register (Continued) .............................................................................. 1133
Table USB-883 Device Configuration Register (Continued) .............................................................................. 1134
Table USB-884 Device Configuration Register (Continued) .............................................................................. 1135
Table USB-885 Device Configuration Register (Continued) .............................................................................. 1136
Table USB-886 Device Configuration Register (Continued) .............................................................................. 1137
Table USB-887 Device Control Register ............................................................................................................ 1138

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Table USB-888 Device Control Register (Continued) ........................................................................................ 1139
Table USB-889 Device Control Register (Continued) ........................................................................................ 1140
Table USB-890 Device Status Register ............................................................................................................... 1141
Table USB-891 Device Status Register (Continued)........................................................................................... 1142
Table USB-892 Device Status Register (Continued)........................................................................................... 1143
Table USB-893 Device Interrupt Register........................................................................................................... 1144
Table USB-894 Device Interrupt Register (Continued) ...................................................................................... 1145
Table USB-895 Device Interrupt Register (Continued) ...................................................................................... 1146
Table USB-896 Device Interrupt Mask Register ................................................................................................. 1147
Table USB-897 Endpoint Interrupt Register ....................................................................................................... 1148
Table USB-898 Endpoint Interrupt Register ....................................................................................................... 1148
Table USB-899 Endpoint Interrupt Mask Register ............................................................................................. 1149
Table USB-900 Endpoint Control Register ......................................................................................................... 1150
Table USB-901 Endpoint Control Register (Continued) ..................................................................................... 1151
Table USB-68 Endpoint Control Register (Continued) ....................................................................................... 1152
Table USB-903 Endpoint Control Register (Continued) ..................................................................................... 1153
Table USB-904 Endpoint Control Register (Continued) ..................................................................................... 1154
Table USB-905 Endpoint Control Register (Continued) ..................................................................................... 1155
Table USB-906 Endpoint Status Register ........................................................................................................... 1156
Table USB-907 Endpoint Status Register (Continued) ....................................................................................... 1157
Table USB-908 Endpoint Status Register (Continued) ....................................................................................... 1158
Table USB-909 Endpoint Status Register (Continued) ....................................................................................... 1159
Table USB-910 Buffer Size/Frame Number Register ......................................................................................... 1160
Table USB-911 Buffer Size/Frame Number Register (Continued) ..................................................................... 1161
Table USB-912 Endpoint Buffer Size OUT/Maximum Packet Size Register..................................................... 1161
Table USB-913 Endpoint Buffer Size OUT/Maximum Packet Size Register (Continued) ................................ 1162
Table USB-914 Endpoint SETUP Buffer Pointer Register ................................................................................. 1162
Table USB-915 Endpoint Data Descriptor Pointer Register ............................................................................... 1162
Table USB-916 CSR Memory Map .................................................................................................................... 1163
Table USB-917 CSR Memory Map (Continued) ................................................................................................ 1164
Table USB-918 CSR Memory Map (Continued) ................................................................................................ 1165
Table USB-919 Handshake Response Options During a Control Command’s Status-OUT Stage ..................... 1167
Table USB-920 Handshake Response Options During a Control Command’s Status-OUT Stage (Continued). 1168
Table USB-921 UDCVCI Endpoint Register ...................................................................................................... 1169
Table USB-922 UDC20 Endpoint Register ......................................................................................................... 1170
Table USB-923 Release Number Register .......................................................................................................... 1171
Table USB-924 SETUP Data Memory Structure Values .................................................................................... 1183
Table USB-925 OUT Data Memory Structure Values ........................................................................................ 1185
Table USB-926 IN Data Memory Structure Values ............................................................................................ 1186

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Table USB-927 IN Data Memory Structure Values ............................................................................................ 1187
Table USB-928 HBURST Generation................................................................................................................. 1189
Table ADC-929 Sampling Rate Range Supported by the LPADC ..................................................................... 1239
Table ADC-930 Sampling Rate Range Supported by the HPADC ..................................................................... 1240
Table ADC-931 Power Supply Information ........................................................................................................ 1241
Table ADC-932 Clock Summary ........................................................................................................................ 1242
Table ADC-933 Clock Control Register List ...................................................................................................... 1243
Table ADC-934 Input Clock Selection ................................................................................................................ 1244
Table ADC-935 Main Reset Control ................................................................................................................... 1245
Table ADC-936 Gain Control of the HPADC ..................................................................................................... 1246
Table ADC-937 ADC Sampling Frequency Estimation ...................................................................................... 1248
Table ADC-938 ADC Sensor Sampling Frequency Estimation .......................................................................... 1249
Table ADC-939 SCU_ADCIF_REG Register List ............................................................................................. 1250
Table ADC-940 ................................................................................................................................................... 1251
Table ADC-941 ................................................................................................................................................... 1252
Table ADC-942 ................................................................................................................................................... 1253
Table ADC-943 ................................................................................................................................................... 1254
Table ADC-944 ................................................................................................................................................... 1255
Table ADC-945 ................................................................................................................................................... 1256
Table ADC-946 ................................................................................................................................................... 1258
Table ADC-947 ................................................................................................................................................... 1260
Table ADC-948 ................................................................................................................................................... 1262
Table ADC-949 ................................................................................................................................................... 1263
Table ADC-950 ................................................................................................................................................... 1264
Table ADC-951 ................................................................................................................................................... 1265
Table ADC-952 ................................................................................................................................................... 1266
Table ADC-953 ................................................................................................................................................... 1267
Table ADC-954 ................................................................................................................................................... 1268
Table ADC-955 ................................................................................................................................................... 1271
Table ADC-956 ................................................................................................................................................... 1272
Table ADC-957 ................................................................................................................................................... 1273
Table ADC-958 ................................................................................................................................................... 1274
Table ADC-959 ................................................................................................................................................... 1275
Table ADC-960 ................................................................................................................................................... 1276
Table ADC-961 ................................................................................................................................................... 1277
Table ADC-962 ................................................................................................................................................... 1280
Table ADC-963 ................................................................................................................................................... 1281
Table ADC-964 ................................................................................................................................................... 1283
Table ADC-965 ................................................................................................................................................... 1284

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Table ADC-966 ................................................................................................................................................... 1284
Table Words and Terms-967 Words and Terms Used in This User Manual ....................................................... 1287

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CXD5602 User Manual

1 Introduction
1.1

Introduction

This manual is intended for CXD5602 users.

1.2

Notation

1.2.1

Notation of numerical value

The table below shows notation of numerical values used in this document.
Table Notation-1 Notation of Numerical Value
Base

Notation

ExampleBase 16

adds prefixed "0x"0x2A

or, adds prefixed "<bit width>'h"

8’h2ABase 10describes numerical value only

256

Base 2

adds prefixed "<bit width>'b"

4'b1010

Numerical numbers are noted in the format shown below when the status of the signal (signed/unsigned) and theposition of the decimal point should be indicated.


[sign][bit number of integer part].[bit number of decimal part]In the [sign], U or S is described. U represents unsigned, and S, signed.
When the sign is U, bit number of integer part plus bit number of decimal part equals the total bit
number.



When the sign is S, 1(sign bit) plus bit number of integer part plus bit number of decimal part equals thetotal bit number.

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The notation examples are as follows.


5-bit unsigned signal with integer number is noted as U5.0.



5-bit unsigned signal with decimal point [1].[0] position is noted as U4.1.



5-bit unsigned signal with decimal point [-1].[-2] position is noted as U6.-1.



5-bit signed signal with integer number is noted as S4.0.



5-bit signed signal with decimal point [1].[0] position is noted as S3.1.

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2 CXD5602 Outline
2.1

Introduction

CXD5602GF/GG is a 32 bit RISC low power microprocessor solution for wearable applications. It is based on theArm® Cortex®-M4 processor with FPU 32 bit RISC and It integrates Arm® Cortex®-M0+ 32 bit RISC specificallyfor the system controller (power management, clock, reset) and I/O processor. It incorporates embedded 1.5
MByte of SRAM, 64 KByte of backup SRAM, and 256 KByte of I/O processor SRAM.
The Arm® Cortex®-M4 processor with FPU and Arm® Cortex®-M0+ are power-gated by the Power Management
Unit, respectively, that is, the CPUs are powered off by internal power switches. Processor SRAMs are able toretain data, and it’s possible to restart processors quickly.
To provide optimized hardware performance for sensor fusion and audio processing services, the device integrates
ultra-low power GNSS Domain, Audio Codec Domain and Sensor Domain. Integrated Audio Codec Domain
supports digital noise cancelling and digital equalizer. Sensor Domain provides the specialized engine for sensor
processing.
Eliminating the need for a discrete sensor hub, these features enable various sensor applications (activity
recognition, voice recognition, etc.) low power audio applications such as music playback (MP3 decode,
Bluetooth A2DP, etc.) and hands-free communication (Bluetooth HFP).

2.2

Features

The features of CXD5602GF/GG are:


Application ProcessorArm® Cortex®-M4 processor with FPU 32 bit RISC
Operating frequency up to 156 MHz



1.5 MByte Application MemoryApplication Multi-layer Bus
32 bit Multi-layer bus architecture
Application Domain for Arm® Cortex®-M4 processor with FPU 32 bit RISC, Audio Codec,
Connectivity, Storage and Image Block

Audio Codec
Digital Equalizer (DEQ)
Two I2S Interfaces supported
Unique Audio Data Format (Pulse Density Modulation) between CXD5602GF/GG and CXD5247GF



8 bit parallel Camera Interface supported

2D Graphics Acceleration－42/1293－

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BitBLT, Rotate, Scaling, BlenderConnectivity/Storage Interface
On-chip USB2.0 Device supported
eMMC 4.41 for eMMC Device
SD3.0 Host Controller interface
SPI and SDIO support for external Wi-Fi transceivers
UART support for external Bluetooth transceivers
Quad SPI-FLASH Interface

Display Interface
SPI Interface up to 40.96 Mbps
8/16/24/32 bpp LCD or E-Ink recommend up to QVGA resolution

System and I/O Processor (SYSCPU)
Arm® Cortex®-M0+ 32 bit RISC
Operating frequency up to 100 MHz at 1.0 V
256 KByte SRAM
128 KByte ROM for secure booting

System and IOP Domain multi-layer bus
32 bit Multi-layer bus architecture
SYSIOP for Arm® Cortex®-M0+ 32 bit RISC, PMU, GNSS, Sensor engine, HostIF, Configurable IO

Power management
I2C and GPIO interface connections to Power Management IC (assuming CXD5247GF)
power on reset
power gate control



Clock and Reset management
X'tal, RTC, RCOSC, PLL

64 KByte Backup SRAM



Timer
RTC
A general-purpose 32 bit timer each Processor Unit

Host Interface
I2C, SPI or UART interface
1 KByte Host communication MemorySensor engine
SPI and Two I2C Interfaces
40 KByte Sensory Data FIFO
Pre-processing unit for sensor fusion
Up to Four PWMs

ADCsFour channel 10 bit low power ADC－43/1293－

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Two channels 10 bit high performance ADC
Multi-GNSS ControllerArm® Cortex®-M4 processor with FPU 32 bit RISC
Operating frequency up to 98.208 MHz
64 KByte ROM
640 KByte SRAM
CORDIC engine for GNSS support

Multi-GNSS receiver
GPS (L1 C/A)
GLONASS (L1OF)
QZSS (L1 C/A, L1 SAIF)SBAS (L1 C/A)
WAAS, EGNOS, MSAS
BeiDou (B1)
Galileo (E1 CBOC)

Configurable I/O
I2C/SPI/GPIO Interfaces



Debug
Serial wire debug (SWD), Embedded Trace Macrocell
UART supported－44/1293－

CXD5602 User Manual

2.3

Block Diagram

Figure Block Diagram-1 CXD5602 Block Diagram－45/1293－

CXD5602 User Manual

2.4

Architecture Overview

The CXD5602 has one Arm® Cortex®-M0 and seven Arm® Cortex®-M4 (includes FPU) inside. Each CPU isconnected each other through multi-layer AHB matrixes and bus bridges separately. Arm® Cortex®-M0 is inside
the SYSIOP. One Arm® Cortex®-M4 is prepared for the GNSS only, and the remainder six Arm® Cortex®-M4 for
the APP.
The CXD5602 has a bus architecture using the Bus Matrix so that eight CPUs and the other bus masters can
independently access to each slave, not affected by any bus traffic.
By Round-robin arbitration inside the Bus Matrix, bus master need not to wait for a long time to access to slaveeven if access competition occurs.
As Figure Block Diagram-1 shows, each bus in the APP/SYSIOP/GNSS is independent.
In addition, between the SYSIOP and the GNSS, and between the SYSIOP and the APP, each peripheral isconnected to the bus bridge.

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2.5

CPU Processor

2.5.1

Application Processor

The application processor integrates six Cortex®-M4 processors with FPU to meet the requirements of wearable
devices, which demand operation in low power and performance-optimized consumer applications with the ability
to scale in speed up to 156.0 MHz, the Arm® Cortex®-M4 processor with FPU.
The key features include:Arm® Cortex®-M4 processor
ISA Support: Thumb/Thumb-2 technology
DSP Extension: Single cycle 16/32 bit MAC, Single cycle dual 16 bit MAC, 8/16 bit SIMD arithmetic,
Hardware Divide (2-12 Cycles)
Floating Point Unit: Single precision floating point unit, IEEE 754 compliantProcessor system peripherals
Programmable Interrupts Controller
128 channel peripheral Interrupt support for each processorTimers
AMBA® Design Kit (ADK) SP804
Two-channel supported
One Timer module for each processor (Total: Six Timers)
Watchdog Timer
AMBA® Design Kit (ADK) SP805
One channel for each processor (Total: Six Watchdog Timers)

2.5.2

System and I/O Processor

The I/O processor integrates Cortex®-M0+ to meet the requirements of wearable devices, which demand operation
in low power and performance-optimized consumer applications with the ability to scale in speed from 32 MHz to
100 MHz, the Arm® Cortex®-M0 Processor.
The key features are:Arm® Cortex®-M0+ processor

ISA Support: Thumb Thumb-2 subset

System and I/O Processor Memory

ROM: 128 KByte



SRAM: 256 KByte

Boot ModesAt startup, the BOOT_MODE pin is used to select one of Two boot options
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CXD5602 User Manual

Boot from embedded ROM


It is used to download the program to either SPI-Flash memory or eMMC via one of the available
interfaces (USB device, Configurable I/O<UART>, or the Host Interface<SPI, UART, and I2C>).



Processor system peripheralsInter-processor communication unit
communication FIFO (Tx, Rx) support
16 binary semaphores support

Programmable Interrupts Controller
One channel software Generated Interrupt for each processor
128 channel shared peripheral Interrupts for the application processors

Timers
AMBA® Design Kit (ADK) SP804
Two channel supported

Watchdog Timer
AMBA® Design Kit (ADK) SP805
One channel supported for each application processor－48/1293－

CXD5602 User Manual

2.6

Memory Mapping

Overview of Memory Map Configuration
Memory map is made up of three types of views. The “SYS View” can be referred from System and I/O Processor,
the “GNSS View” can be referred from the GNSS DSP, and the “APP View” can be referred from Application
Processor. The SYS Window, the GNSS Window, and the APP Window are defined so that each of them can beaccessed to the same address from its own processor.
The SYS Window defines addresses of the master device and the slave device inside the SYSIOP and the SCU.
The GNSS Window defines addresses of the master device and the slave device inside the GNSS, the APPWindow, inside the APP, as well.
Figure Memory Mapping-2 shows memory map configuration.
SYS View

GNSS View

APP View

Data
on SPI-FlashData
on SPI-FlashData
on SPI-FlashAPP Window

APP Window

APP Window

GNSS Window

GNSS Window

GNSS Window

SYS Window

SYS Window

SYS Window

0x8FFFFFFF

0x80000000

0x0FFFFFFF
0x0C000000
0x08000000
0x04000000
0x00000000

Figure Memory Mapping-2 Memory Map of the SYSIOP, GNSS, and APP－49/1293－

CXD5602 User Manual

2.6.1

Memory Map of Each Block

For detailed address information of the SYSIOP block, the GNSS block, and each functional block, refer to thecontent of each functional block.
Table Memory Mapping-2 Memory Mapping of the SYSIOP Block (SYS Window)
Category
ROM
Reserved
Top Peripheral

Reserved
SPI Flash Controller
Reserved
DM AC

ReservedSCU

HOSTIFC

CONFIGIO

Reserved
Backup SRAM
Reserved
SYSCPU Local

Pheripheral Name
ROM (128KB)
Reserved
PM U, CRG, GPIO, I/O Config
I2C4
FREQDISC
RTC0

Start Address

End Address

0x04000000
0x04020000
0x04100000
0x04106000
0x04107000
0x04108000

0x0401FFFF
0x040FFFFF
0x04105FFF
0x04106FFF
0x04107FFF
0x04108FFF

Size(4k bytes unit）
128K
896K
24K
4K
4K
4K

RTC1

0x04109000

0x04109FFF

4K

Reserved
SPI Flash Controller(REG)
Reserved
SDM ACHDM ACSYDM AC
SYSUBDM AC
Reserved
FIFO Control
FIFO(40K)
SPI3
I2C0
I2C1
HPADC, LPADC
Reserved
Sensor Engine
SCU Register
Reserved
SPI2
I2C3
SRAM (1KB)
Reserved
SEQ
Reserved
UART0
I2C2
SPI0
UART1
Reserved
SRAM (64KB)
Reserved
System and I/O Processor

0x0410B000
0x04110000
0x04111000
0x04120000
0x04121000
0x04122000
0x04123000
0x04124000
0x04180000
0x04183000
0x0418D000
0x0418D400
0x0418D800
0x0418DC00
0x0418E000
0x04190000
0x04195000
0x04196000
0x041A0000
0x041A0400
0x041A0800
0x041A0C00
0x041A1000
0x041A4000
0x041A9000
0x041AA000
0x041AB000
0x041AC000
0x041AD000
0x04400000
0x04410000
0x05000000

0x0410FFFF
0x04110FFF
0x0411FFFF
0x04120FFF
0x04121FFF
0x04122FFF
0x04123FFF
0x0417FFFF
0x04182FFF
0x0418CFFF
0x0418D3FF
0x0418D7FF
0x0418DBFF
0x0418DFFF
0x0418FFFF
0x04194FFF
0x04195FFF
0x0419FFFF
0x041A03FF
0x041A07FF
0x041A0BFF
0x041A0FFF
0x041A3FFF
0x041A8FFF
0x041A9FFF
0x041AAFFF
0x041ABFFF
0x041ACFFF
0x043FFFFF
0x0440FFFF
0x04FFFFFF
0x07FFFFFF

20K
4K
60K
4K
4K
4K
4K
368K
12K
40K
1K
1K
1K
1K
8K
20K
4K
40K
1K
1K
1K
1K
12K
20K
4K
4K
4K
4K
2.3M
64K
11.9M
48M

－50/1293－

CXD5602 User Manual

Table Memory Mapping-3 Memory Mapping of the APP Block (APP Window)
Category
Reserved
SRAM
Reserved
APP Local
Reserved
DM A
Reserved
Imaging/2D

Reserved
Storage/Connectivity

Reserved
Audio Codec
Reserved

2.6.2

Pheripheral Name
Reserved
SRAM (1.5M B)
Reserved
CRG and Application Processor
Reserved
ADM AC
ReservedCIS I/F
2D Graphics
IDM AC
UART2
SPI4
SPI5
ReservedUSB
eM M C
SDIO
Reserved
AUDIO DSP, I2S, PDM
Reserved

Start Address

End Address

0x0C000000
0x0D000000
0x0D180000
0x0E000000
0x0E014000
0x0E020000
0x0E021000
0x0E100000
0x0E101000
0x0E102000
0x0E103000
0x0E103400
0x0E103C00
0x0E105000
0x0E200000
0x0E201000
0x0E202000
0x0E203000
0x0E300000
0x0E305000

0x0CFFFFFF
0x0D17FFFF
0x0DFFFFFF
0x0E013FFF
0x0E01FFFF
0x0E020FFF
0x0E0FFFFF
0x0E100FFF
0x0E101FFF
0x0E102FFF
0x0E1033FF
0x0E103BFF
0x0E104FFF
0x0E1FFFFF
0x0E200FFF
0x0E201FFF
0x0E202FFF
0x0E2FFFFF
0x0E304FFF
0x0FFFFFFF

Size(4k bytes unit）
16M
1.5M
14M
80M
48K
4K
892K
4K
4K
4K
1K
1K
5K
1004K
4K
4K
4K
1012K
20K
28M

Main Memory

There is 1.5 MByte SRAM in total which is connected to AHB of the Application Processor.
The SRAM is made up of 128 KByte Logic Tiles. Each of them has the AHB I/F individually.
In addition, the Logic Tile is the unit for the SRAM access protection function.
You can use protection feature that keeps masters with specific Master ID from accessing specific SRAM Logic
Tiles. The protection feature can be controlled via buses.
Power domain of Main Memory is PWD_APP. When PWD_APP is turned off, this memory cannot be used.
Power on/off can be controlled suitably by power switch inside SRAM for each 128 KByte Logic Tile. There are
two operation modes for SRAM power-off; they can be set by system control registers.
Retention modeA mode in which only the power supply of SRAM memory array is ON, and the power supply of theperipheral circuitry is turned OFF. In Retention mode, the SRAM cannot be accessed, but the data
within the SRAM is retained. By turning on (ON mode) the power supply of peripheral circuitry of the
SRAM once again, the data within the SRAM can be accessed. Retention mode enables reduction of theleakage power and recovery of high speed of peripheral circuitry for SRAMs that are temporarily not
used.



Shutdown modeA mode that turns OFF both the power supply of the SRAM memory array and peripheral circuitry.
This mode consumes less power than the Retention mode, but the data in the SRAM is not retained.

－51/1293－

CXD5602 User Manual

2.6.3

System Memory

There is 256 KByte SRAM in total which is connected to the AHB of the System and I/O Processor.
The SRAM block is made up of four 64K Byte Logic Tiles. One tile of the four is divided into four sub Logic
Tiles of: 8 KByte, 8 KByte, 16 KByte, and 32 KByte.
Each Logic Tile has the AHB I/F individually. The application program can access data from each Logic Tile via
local AHB. In addition, the Logic Tile is the unit for the SRAM access protection function. You can use
protection feature that keeps masters with specific Master ID from accessing specific SRAM Logic Tiles. The
protection feature can be controlled via buses. You can assign only Arm® Cortex®-M0+ of SYSCPU as masterthat can control the protection feature. Shortly after the POR, all masters can access all Logic Tiles.
Power domain is PWD_CORE. When PWD_CORE is turned OFF, this memory cannot be used. Each sub area
tile is allocated to serial addresses; therefore, each sub Logic Tile can be turned ON/OFF individually. There are
two operation modes for the SRAM power-off: Retention mode and Shutdown mode. They can be set by system
control registers.

2.6.4

Backup Memory

There is 64 KByte SRAM in total which is connected to the AHB in System and IOP Domain for backup.
You can use protection feature that keeps masters with specific Master ID from accessing specific SRAM Logic
Tiles. The protection feature can be controlled via buses.
Power domain belongs to PWD_PMU area. You can use protection feature that keeps masters with specific
Master ID from accessing specific SRAM Logic Tiles. The protection feature can be controlled via buses. Power
ON/OFF can be controlled by registers. There are two operation modes for the SRAM power-off: Retention modeand Shutdown mode. They can be set by system control registers.

2.7

Clock and Reset

2.7.1

Overview

The clock architecture inside the CXD5602 enables circuit blocks to select a variety of clock sources. It can
support wide range of application with optimized power consumption, from low speed sensing operation with low
power consumption, to high speed application processing using multi-core processor.
The CXD5602 has five types of usable clock sources and is made up of main five clock domains in accordance－52/1293－

CXD5602 User Manualwith functional blocks. A variety of processors can dynamically select multiple usable clock source, and use mostsuitable clock frequency optimized for the operating conditions by using divider circuit architecture.
The functions of clock and reset of the CXD5602 are described below.


Clock Source
The CXD5602 has following clocks.


RTC Clock:is 32.768 kHz real time clock input from outside chipis assumed to be input as the RTC clock from external the RTC oscillator or the PMIC containing
the RTC oscillator

can be used as clock for the RTC counter circuit incorporated in the chip, as system clock inoperation with low power, and as clock of sensing circuit in operation with low power such as the
SCU, as well.



RCOSC (RC Oscillator) Clock:

is 8.192 MHz incorporated ring oscillator

becomes 8.192 MHz by being calibrated with RTC clock

incorporates POR system

XOSC (X'tal Oscillator) Clock:

X'tal 26MHz



can be used as CPU operation clock, in addition, can be supplied to SYSPLL and RFPLL as
reference clock

SYSPLL Clock:

incorporates low power PLL which realizes high CPU operation frequency without any input ofhigh speed clock from outside.

Following frequencies can be selected as SYSPLL clock according to the combination of suitable
X'tal frequency variation and the division ratio of the PLL.



Under high speed oscillation setting: 195.000 MHz



Under usual speed oscillation setting: 156.000 MHz

RFPLL Clock (Clock generated in PWD_GNSS):is provided from the PLL (RFPLL) included in the PWD_GNSS for the RF block

Following frequencies can be selected as RFPLL clock according to the suitable X'tal frequency
variation.



GPS/Beidou mode: 196.416 MHz

Reset Source
The following reset functions are prepared for whole chip reset.
Power On reset (POR) issued from the external PMICThe POR issued from the POR circuit incorporated in the RCOSC

The above POR can be enabled or disabled with external input.

－53/1293－

CXD5602 User Manual

System reset from Watchdog Timer (WDT)

It is a whole chip reset controlled by the WDT of the SYSCPU.

You can enable/disable whole chip reset controlled by the WDT with register setting.

－54/1293－

CXD5602 User Manual

2.7.2

Clock Architecture

The figure below shows CX5602 clock diagram. The CXD5602 has main five clock domains according tofunctional blocks. Clock can be selected in accordance with the operating conditions of each functional block.


Always OnApplication DomainThe RTC clock and the RCOSC clock can be selected.
The Application Processor can change the frequency dynamically with the frequency divider.

System and IOP Domain

Four clock sources: the SYSPLL, the XOSC, the RCOSC, and the RTC can be selected, and can beswitched dynamically in accordance with the use case.

Sensor Domain
The System and I/O Processor can change the frequency dynamically with the frequency divider.
Three clock sources: the RTC, XOSC, and RCOSC can be selected.

GNSS DomainThe clock selected by the System and I/O Processor in the System and IOP Domain is distributed
to the GNSS DSP. Frequency division ratio can be set independently.



The clock generated by either the SYSPLL or the RFPLL is distributed to the baseband signal
processing block. Operational constraints depend on which PLL is selected. For details, refer to
Chapter of the GNSS.

－55/1293－

CXD5602 User Manual

Application Domain
Divider

163MHz(High performance mode)/ 40MHz(Low Power mode)

Application
Processor
APP Bus
Peripheral

AHB

Divider
Divider

CIS I/F
USB
49.104MHz

Divider

SDIO
2D Graphics

49.104MHz

Divider

eMMC

Divider

AUDIO

MCLK

24.576kHz

Divider

100MHz(High performance mode)/ 32MHz(Low Power mode)

System and IOP Domain
System and I/OProcessor

AHB

Divider

SYSIOP Bus
Peripheral

APB

Divider

Debug
Divider

Sensor Domain

163.68MHz
196.416MHz

GNSS Domain

SYSPLL

Divider
Max199.2MHz

XOSC

RF

XTAL

Divider
Divider

26MHz

RCOSC

100MHz(High performance mode)/ 32MHz(Low Power mode)

66.4MHz(RFPLL)/65.472MHz(SYSPLL)
16.6MHz(RFPLL)/16.368MHz(SYSPLL)GNSS DSPBB
ITP

Always On≒8.192MHz

32KHz / 8.192MHz

1/250

Divider

32KHz

RTC Clock32.768kHz

Figure Clock and Reset-3 Clock Diagram－56/1293－

PMU
RTC

CXD5602 User Manual

2.8Power Management

2.8.1

Overview

The CXD5602 has a large power domain, which is divided into 11 domains. It performs ON control of necessaryfunctions only, while performing OFF control of the unnecessary ones, thereby reducing the power consumption.
Additionally, the SRAM or analog circuits such as the ADC within the power supply domains enable individual
power supply control.
Power supply control is implemented by setting on the Power Management Unit (referred as “PMU” hereinafter).
You can check with the PMU about the present power state.

2.8.2

Power Domain

The 11 power domains comprise a layer structure as shown in Figure Power Management-4. The lower-layer
power domains cannot be turned ON when the upper-layer power domains are OFF. Furthermore, PWD_GNSS
can be turned ON only when both PWD_GNSS_ITP and PWD_SYSIOP are ON.

VDD_COREPMU

PWD_PMU

Always ON

PWD_SCU

Sensor
DomainPWD_SCU
Power switch

PWD_COREPWD_CORE
Power switch

PWD_SYSIOP_SUB

PWD_SYSIOP_SUB
Power switch

System and IOP
DomainPWD_SYSIOPPWD_SYSIOPPower switch

PWD_APPPWD_APPPower switch

PWD_APP_DSP

PWD_APP_DSP
Power switch

PWD_APP_SUB

PWD_APP_SUB
Power switch

PWD_APP_AUD

PWD_APP_AUD
Power switch

PWD_GNSS_ITP

PWD_GNSS_ITP
Power switch

PWD_GNSSPWD_GNSSPower switch

Figure Power Management-4 Power Domain Layers－57/1293－

Application
DomainGNSS
DomainCXD5602 User Manual

PWD_PMU
Application Domain

Imaging / 2D

APP

PWD_APP_DSP

ADMAC

2D
Graphics

Crypto
(AES)

CIS
I/F

Application Processor(Cortex-M4 x 6)

S
P
I
4

S
P
I
5

Storage/Connectivity

U
A
R
T
2

eMMC

IDMAC

PWD_APP_SUB
APB

USB

SDIO

AHB

AHB to
AHB

Sync

32b Multi-Layer AHB

32b Multi-Layer AHB
Audio Codec

SRAM(1.5MB)PWD_APP_AUD
Audio
DSP

Async

PWD_APP
System and IOP Domain

PWD_COREPWD_SYSIOP
debugger I/F

PWD_GNSS

System andI/O Processor(Cortex-M0+)

GNSS DSP(Cortex-M4)

FREQDISC

32b Multi-Layer AHB
SRAM

Sync
Up/Down

Sync
Up/Down

SYDMAC

BB

SDMAC

Sync

I2C4
RTC0

HOSTIFC
Async

ITP

IOCTRLGPIO
INTCTLe-fuseBackUpSRAM(64KB)

32b Multi-Layer AHB

GNSS Reciever
RF

HDMAC

PWD_SYSIOP_SUB

Async

APB

ROM

(128KB)SPI Flash
Controller

SYSUB
DMAC

Crypto(Clefia)

S
P
I
0

I
2
C
2

APB
U
A
R
T
1

S
P
I
2

I
2
C
3

U Sequencer
A
R
SRAM
T
(1KB)
0

Async
Sync

32b Multi-Layer AHB(256KB)

RTC1

Async

(64KB)PMU

APB

32b Multi-Layer AHB
ROM

RCOSC
XOSC
SysPLL

ITM

GNSS

SRAM
(640KB)

Power Management,
Clock,Reset
CRG
RTC Clock

SYSIOP

GNSS Domain

Sensor Domain
SCU

APB

PWD_SCUL H S I I P
P P
P 2 2 WA A
M
D D I C C ×
C C 3 0 1 4

FIFO Sensor
Engine(40KB)

Figure Power Management-5 CXD5602 Power Domain
The following describes the functions of each power domain.
Application Domain

PWD_APPAll components of Application Domain

Including 1.5 MByte SRAM in Application memory and Application Multi-layer Bus

PWD_APP_DSPApplication processors

DSP block



ADMAC

PWD_APP_SUB




I2S0
I2S1
PDM

Connectivity, Storage I/F and Camera, Display Interface in Application Domain

PWD_APP_AUD－58/1293－

CXD5602 User Manual

Audio Codec

System and IOP Domain

PWD_SYSIOP

System and IOP Domain

Excluding 256 KByte SRAM in System and I/O Processor Memory

PWD_SYSIOP_SUB
Configurable I/O (I2C, SPI, UART) Interface

SPI-FLASH Interface



128 KByte ROM in System and I/O Processor Memory

Crypto Engine in System and IOP Domain

SYSUB-DMAC

PWD_COREAll components of System and IOP Domain and GNSS Domain

Including 256 KByte SRAM in System and I/O Processor MemoryIncluding 640 KByte SRAM in GNSS MemoryIncluding ALIVE I/O (I2C, GPIO)



Including GNSS-RF

Including Key generation in System and IOP Domain



ALIVE I2C

GNSS Domain

PWD_GNSS

Components of GNSS Domain

Excluding RF and 640 KByte SRAM in GNSS Memory

PWD_GNSS_ITP

ITP Block in GNSS Domain

Sensor Domain

PWD_SCUComponents of sensor engine

Including LP-ADC, HP-ADC

Always ON


PWD_PMU

All components of VDD supplied logic, SRAM, ROM and analog

Including Clock, reset and Power Management Domain and BackUp SRAM



Including XOSC, SYSPLLALIVE GPIO

－59/1293－

CXD5602 User Manual

2.8.3

Power Supply States

The following describes the main power supply states.
Table Power Management-4 Power Supply States
Power supply state

Description

1

Power Off

Both the CXD5602 (referred to as “the LSI” hereinafter) and the CXD5247 are OFF.

2

Deep Sleep

The LSI is OFF and the CXD5247 is ON.
In this state, the RTC of the CXD5247 is counting, and time information can be obtained
from the CXD5247 after the LSI is started.

3

Reset

In this state, the LSI and the CXD5247 are both ON, and the LSI is being reset.

4

NormalThe LSI and the CXD5247 are both ON, and the System Control (PWD_SYSIOP) turns
ON, enabling power supply control of each Domain.

The state begins from “Power OFF,” and after the CXD5247 starts, power is supplied to the LSI and a reset isenabled, changing the state to “Reset.” After releasing the reset of the LSI, the System Control of the System and
IOP Domain is automatically started, and the state enters to “Normal.” In the “Normal” state, the power supply
control of each feature’s Domain can be controlled.
By issuing the Deep Sleep command to the CXD5247, the state changes to “Deep Sleep”. When events of the
CXD5247 occur, such as the timer or interrupts, the state changes to “Reset” and then to “Normal.”－60/1293－

CXD5602 User ManualState: Power OFF
CXD5247
OFF(PMIC)CXD5602
OFF
System and Application GNSSIOP Domain Domain
DomainOFF
OFF
OFF

Sensor
DomainOFF

State: Normal (Domain ON)(Transition to each state is possible.)

CXD5602
ON

System andApplication
IOP Domain ON Domain ON

State: ResetCXD5247
ON(PMIC)CXD5602
ON
System and Application GNSSIOP Domain Domain
DomainOFF
OFF
OFF

CXD5602
ON

Sensor
DomainOFF

System andApplication
IOP Domain ON Domain OFF

CXD5602
ON
System and Application GNSSIOP Domain Domain
DomainON
OFF
OFF

System andApplication
IOP Domain ON Domain OFF

Sensor
DomainOFF(PMIC)

GNSS
Domain OFF

CXD5602
ON

System andApplication
IOP Domain ON Domain ON

GNSS
Domain OFF

CXD5602
ON

State: Deep Sleep
CXD5247
ON

GNSS
Domain ON

CXD5602
ON

State: Normal(PMIC)

GNSS
Domain ON

CXD5602
ON

System andApplication
IOP Domain ON Domain ON

CXD5247
ON

GNSS
Domain OFF

CXD5602
OFF
System and Application GNSSIOP Domain Domain
DomainOFF
OFF
OFF

System andApplication
IOP Domain ON Domain OFF

Sensor
DomainOFF－61/1293－

CXD5602
ON

System andApplication
IOP Domain ON Domain ON

Figure Power Management-6 Changes of Power Supply States

GNSS
Domain ON

GNSS
Domain ON

Sensor
Domain OFF

Sensor
Domain OFF

Sensor
Domain OFF

Sensor
Domain ON

Sensor
Domain ON

Sensor
Domain ON

Sensor
Domain ON

CXD5602 User Manual

3 Function Details
3.1

I/O Configuration

3.1.1

OutlineI/O Configuration switches between HOST I/F select function and Serial Wire Debug (SWD) function, andcontrols Pin Multiplexer.

3.1.2

Function List

Table I/O Configuration-5 shows I/O Configuration function list.
Table I/O Configuration-5 Function List
No

Function Name

Description

1

Switching between HOST I/F selectThis function decides communication tools. After it decides a HOST I/F, it switches

function and SWD function

SYSTEM0/1 pin to use as SWD.

Pin Multiplexer

To a pin, Pin Multiplexer can assign a role selecting from up to four options.

2

Multiple roles cannot be played at a time.

－62/1293－

CXD5602 User Manual

3.1.3

Switching between HOST I/F Select Function and SWD

FunctionOnce clock is provided to this block after Power-on Reset (POR) release, values of pin SYSTEM0 and pin
SYSTEM1 are held inside. A HOST I/F is selected from I2C, SPI, or UART in accordance with the held values.
Then, pin SYSTEM0 and pin SYSTEM1 are switched to SWD function.
Figure I/O Configuration-7 shows switching between HOST I/F Select function and SWD function.

CXD5602
Host I/F
select signal

0

Debugger

1

SYSTEM0 (in)SYSTEM1 (in)0

Hold
SYSTEM0,1

1

SWD
control

Hold SYSTEM0,1

HOSTIFC
I2C
UART

Delay

SPI

POR

LL
HL
LH

SYSTEM0,1
switched to SWD control
CXD5602
Host I/F
select signal

0

Debugger

1

SYSTEM0 (in)SYSTEM1 (in/out)

Switched to
SWD control

Delay

0

Hold
SYSTEM0,1

1

SWD
control

Select Host I/F

HOSTIFC
I2C
UART
SPI

POR

LL
HL
LH

Figure I/O Configuration-7 Switching between HOST I/F Function and SWD Function
Table I/O Configuration-6 shows HOST I/F decided in accordance with the held values of pin SYSTEM0 and pin
SYSTEM1 after POR release.
Table I/O Configuration-6 HOST I/F Decided in Accordance with Pin SYSTEM{0,1}
Pin name

SYSTEM0=L

SYSTEM0=H

SYSTEM0=L

SYSTEM0=H

SYSTEM1=L

SYSTEM1=L

SYSTEM1=H

SYSTEM1=H

P00_00I2C3_BCKUART0_TXD

SPI2_CSX-

P00_01

I2C3_BDTUART0_RXD

SPI2_SCK-

P01_00--

SPI2_MOSI-

P01_01--

SPI2_MISO-－63/1293－

CXD5602 User Manual

3.1.4

Pin Multiplexer

To each pin of this LSI, Pin Multiplexer can assign a role selecting from up to four options. Multiple roles cannot
be played at a time. Not only General Purpose Input/Output (GPIO) mode controlled by register, but alsoInter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver Transmitter(UART), Pulse Width Modulation (PWM), Secure Digital Input/Output (SDIO), Embedded Multi Media Card
(EMMC), or AUDIO can be selected.

3.1.4.1 List of Registers
Table I/O Configuration-7 shows list of registers for controlling Pin Multiplexer. Table I/O Configuration-8 showslist of registers that control Input/Output and Pull up/down of IOCELL. And Table I/O Configuration-9 shows listof registers for AUDIO Output Enable Control, and for input value setting on IP (SDIO) when SDIO function is
not used.
Table I/O Configuration-7 List of Registers for Controlling Pin Multiplexer
Address

Register Name

AttribFunction

Initial Value

ute
0x041007C0IOCSYS_IOMD0

RW

selects pin function (System)

0x00000000

0x041007C4IOCSYS_IOMD1

RW

selects pin function (System)

0x00000000

0x041014A0

IOCAPP_IOMD

RW

selects pin function (Application)

0x00000000

Table I/O Configuration-8 List of Registers for Controlling IOCELL
Address

Register Name

AttribFunction

Initial Value

ute
0x04100800

IO_RTC_CLK_IN

RWIOCELLsettingfor

pin

0x00010100

RTC_CLK_IN
0x04100804

IO_I2C4_BCK

RW

IOCELL setting for pin P10_00

0x01010100

0x04100808

IO_I2C4_BDT

RW

IOCELL setting for pin P10_01

0x01010100

0x0410080C

IO_PMIC_INTRWIOCELL setting for pin P11_00

0x01010100

0x04100810

IO_RTC_IRQ_OUT

RWIOCELL setting for pin P12_00

0x01010100

0x04100814

IO_AP_CLK

RW

IOCELL setting for pin P13_00

0x01010100

0x04100818

IO_GNSS_1PPS_OUT

RW

IOCELL setting for pin P14_00

0x01010100

0x0410081C

ReservedRO

Reserved

0x00000000|
0x04100840－64/1293－

CXD5602 User Manual

0x04100844

IO_SPI0_CS_X

RW

IOCELL setting for pin P16_00

0x01010100

0x04100848

IO_SPI0_SCK

RWIOCELL setting for pin P16_01

0x01010100

0x0410084C

IO_SPI0_MOSIRWIOCELL setting for pin P17_00

0x01010100

0x04100850

IO_SPI0_MISO

RWIOCELL setting for pin P17_01

0x01010100

0x04100854

IO_SPI1_CS_X

RW

IOCELL setting for pin P18_00

0x00010100

0x04100858

IO_SPI1_SCK

RW

IOCELL setting for pin P18_01

0x00010100

0x0410085C

IO_SPI1_IO0

RW

IOCELL setting for pin P18_02

0x00010100

0x04100860

IO_SPI1_IO1RW

IOCELL setting for pin P18_03

0x00010100

0x04100864

IO_SPI1_IO2

RW

IOCELL setting for pin P19_00

0x00010100

0x04100868

IO_SPI1_IO3

RW

IOCELL setting for pin P19_01

0x00010100

0x0410086C

IO_SPI2_CS_X

RW

IOCELL setting for pin P00_00

0x01010100

0x04100870

IO_SPI2_SCK

RW

IOCELL setting for pin P00_01

0x01010100

0x04100874

IO_SPI2_MOSIRWIOCELL setting for pin P01_00

0x01010100

0x04100878

IO_SPI2_MISO

RWIOCELL setting for pin P01_01

0x01010100

0x0410088C

IO_HIF_IRQ_OUT

RWIOCELL setting for pin P02_00

0x01010100

0x04100880

IO_HIF_GPIO0RW

IOCELL setting for pin P03_00

0x01010100

0x04100884

Reserved

R0

Reserved

0x00000000

0x04100894

IO_SEN_IRQ_IN

RW

IOCELL setting for pin P1e_00

0x01010100

0x04100898

IO_SPI3_CS0_X

RW

IOCELL setting for pin P1f_00

0x01010100

0x0410089C

IO_SPI3_CS1_X

RW

IOCELL setting for pin P1g_00

0x01010100

0x041008A0

IO_SPI3_CS2_X

RW

IOCELL setting for pin P1h_00

0x01010100

0x041008A4

IO_SPI3_SCK

RW

IOCELL setting for pin P1i_00

0x01010100

0x041008A8

IO_SPI3_MOSIRWIOCELL setting for pin P1i_01

0x01010100

0x041008AC

IO_SPI3_MISO

RWIOCELL setting for pin P1i_02

0x01010100

0x041008B0

IO_I2C0_BCK

RW

IOCELL setting for pin P1j_00

0x01010100

0x041008B4

IO_I2C0_BDT

RW

IOCELL setting for pin P1j_01

0x01010100

0x041008B8

IO_PWM0

RW

IOCELL setting for pin P1r_00

0x01010100

0x041008BC

IO_PWM1

RW

IOCELL setting for pin P1r_01

0x01010100

0x041008C0

IO_PWM2

RW

IOCELL setting for pin P1r_02

0x01010100

0x041008C4

IO_PWM3

RW

IOCELL setting for pin P1r_03

0x01010100

0x041008C8

ReservedRO

Reserved

0x00000000

0x041008D4

IO_DBG_SWOCLKRWIOCELL setting for pin SWOCLK

0x00010100

0x041008D8

IO_DBG_SWO

RW

IOCELL setting for pin SWO

0x01010100

0x041008E0

IO_IS_CLK

RW

IOCELL setting for pin P1m_00

0x01010100|
0x04100890|
0x041008D0－65/1293－

CXD5602 User Manual

0x041008E4

IO_IS_VSYNC

RW

IOCELL setting for pin P1m_01

0x01010100

0x041008E8

IO_IS_HSYNC

RWIOCELL setting for pin P1m_02

0x01010100

0x041008EC

IO_IS_DATA0RWIOCELL setting for pin P1m_03

0x01010100

0x041008F0

IO_IS_DATA1RWIOCELL setting for pin P1m_04

0x01010100

0x041008F4

IO_IS_DATA2RWIOCELL setting for pin P1m_05

0x01010100

0x041008F8

IO_IS_DATA3RWIOCELL setting for pin P1m_06

0x01010100

0x041008FC

IO_IS_DATA4RWIOCELL setting for pin P1m_07

0x01010100

0x04100900

IO_IS_DATA5RWIOCELL setting for pin P1m_08

0x01010100

0x04100904

IO_IS_DATA6RWIOCELL setting for pin P1m_09

0x01010100

0x04100908

IO_IS_DATA7RWIOCELL setting for pin P1m_10

0x01010100

0x0410090C

IO_UART2_TXD

RW

IOCELL setting for pin P1n_00

0x01010100

0x04100910

IO_UART2_RXD

RW

IOCELL setting for pin P1n_01

0x01010100

0x04100914

IO_UART2_CTS

RW

IOCELL setting for pin P1n_02

0x01010100

0x04100918

IO_UART2_RTS

RW

IOCELL setting for pin P1n_03

0x01010100

0x0410091C

IO_SPI4_CS_X

RW

IOCELL setting for pin P1o_00

0x01010100

0x04100920

IO_SPI4_SCK

RW

IOCELL setting for pin P1o_01

0x01010100

0x04100924

IO_SPI4_MOSIRWIOCELL setting for pin P1o_02

0x01010100

0x04100928

IO_SPI4_MISO

RWIOCELL setting for pin P1o_03

0x01010100

0x0410092C

IO_EMMC_CLK

RWIOCELL setting for pin P1p_00

0x01010100

0x04100930

IO_EMMC_CMD

RWIOCELL setting for pin P1p_01

0x01010100

0x04100934

IO_EMMC_DATA0RWIOCELL setting for pin P1p_02

0x01010100

0x04100938

IO_EMMC_DATA1RWIOCELL setting for pin P1p_03

0x01010100

0x0410093C

IO_EMMC_DATA2RWIOCELL setting for pin P1q_00

0x01010100

0x04100940

IO_EMMC_DATA3RWIOCELL setting for pin P1q_01

0x01010100

0x04100944

IO_SDIO_CLK

RWIOCELL setting for pin P1r_00

0x01010100

0x04100948

IO_SDIO_CMD

RWIOCELL setting for pin P1r_01

0x01010100

0x0410094C

IO_SDIO_DATA0RWIOCELL setting for pin P1r_02

0x01010100

0x04100950

IO_SDIO_DATA1RWIOCELL setting for pin P1r_03

0x01010100

0x04100954

IO_SDIO_DATA2RWIOCELL setting for pin P1r_04

0x01010100

0x04100958

IO_SDIO_DATA3RWIOCELL setting for pin P1r_05

0x01010100

0x0410095C

IO_SDIO_CD

RW

IOCELL setting for pin P1s_00

0x01010100

0x04100960

IO_SDIO_WP

RW

IOCELL setting for pin P1s_01

0x01010100

0x04100964

IO_SDIO_CMDDIR

RW

IOCELL setting for pin P1t_00

0x01010100

0x04100968

IO_SDIO_DIR0

RW

IOCELL setting for pin P1t_01

0x01010100

0x0410096C

IO_SDIO_DIR1_3

RW

IOCELL setting for pin P1t_02

0x01010100

0x04100970

IO_SDIO_CLKI

RW

IOCELL setting for pin P1u_00

0x01010100－66/1293－

CXD5602 User Manual

0x04100974

IO_I2S0_BCK

RW

IOCELL setting for pin P1v_00

0x01010100

0x04100978

IO_I2S0_LRCKRWIOCELL setting for pin P1v_01

0x01010100

0x0410097C

IO_I2S0_DATA_IN

RW

IOCELL setting for pin P1v_02

0x01010100

0x04100980

IO_I2S0_DATA_OUT

RWIOCELL setting for pin P1v_03

0x01010100

0x04100984

IO_I2S1_BCK

RW

IOCELL setting for pin P1w_00

0x01010100

0x04100988

IO_I2S1_LRCKRWIOCELL setting for pin P1w_01

0x01010100

0x0410098C

IO_I2S1_DATA_IN

RW

IOCELL setting for pin P1w_02

0x01010100

0x04100990

IO_I2S1_DATA_OUT

RWIOCELL setting for pin P1w_03

0x01010100

0x04100994

IO_MCLK

RW

IOCELL setting for pin P1x_00

0x01010100

0x04100998

IO_PDM_CLK

RW

IOCELL setting for pin P1y_00

0x01010100

0x0410099C

IO_PDM_IN

RW

IOCELL setting for pin P1y_01

0x01010100

0x041009A0

IO_PDM_OUT

RW

IOCELL setting for pin P1y_02

0x01010100

0x041009A4

IO_USB_VBUSINTRWIOCELL setting for pin P1z_00

0x01010100

Table I/O Configuration-9 List of Registers for AUDIO and SDIO Control
Address

Register Name

AttribFunction

Initial Value

ute
0x04101470

AUDIO_IF_SEL

RW

PDM_CLK output signal selection

0x00000000

0x04101474

IOOEN_APP

RW

I2S output control

0x00000033

0x04101478

IOFIX_APP

RW

input value setting on IP (SDIO)

0x00000003

when SDIO is not used

－67/1293－

CXD5602 User Manual

3.1.4.2 Register Descriptions
3.1.4.2.1

Registers for selecting a role of the I/O pins belonging to SYS group

Table I/O Configuration-10 shows registers for selecting a role of the I/O pins belonging to SYS group. Setting
examples are explained in “3.1.4.3 Function Details”.
Table I/O Configuration-10 Overview of Registers for Selecting a Role of the I/O Pins Belonging to SYS Group
Address

0x041007C00x041007C4

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

IOCSYS_

Reserved-[31:28]

-

For

IOMD0

HIFEXT

RW[27:26]0IOCSYS_IOMOD1,0, refer to Table

HIFIRQ

RW[25:24]0

I/O Configuration-11.

SPI2B

RW

[23:22]

0

SPI2A

RW

[21:20]

0

SPI1B

RW

[19:18]

0

SPI1A

RW

[17:16]

0

SPI0B

RW

[15:14]

0

SPI0A

RW

[13:12]0

Reserved-[11:10]-

GNSS_1PPS_OUT

RW

[9:8]

0

AP_CLK

RW

[7:6]

0

RTC_IRQ_OUT

RW

[5:4]

0

PMIC_INT

RW

[3:2]

0

I2C4

RW

[1:0]

0

IOCSYS_

Reserved-[31:24]

-

IOMD1

PWMB

RW

[23:22]

0

PWMA

RW

[21:20]

0

I2C0

RW

[19:18]

0

SPI3

RW

[17:16]0

SPI3_CS2_X

RW[15:14]0

SPI3_CS1_X

RW[13:12]0

SPI3_CS0_X

RW[11:10]0

SEN_IRQ_IN

RW

[9:8]

0

Reserved

-

[7:0]

-

Value

－68/1293－pinfunctionsselectedbyCXD5602 User Manual

Table I/O Configuration-11 shows pin functions selected by IOCSYS_IOMD0 and IOSYS_IOMD1.
Table I/O Configuration-11 Table of Role Selection for I/O Pins Belonging to SYS Group
Pin

Register

Register Setting value

Name

Name

0

1

2

3

P10_00IOCSYS_IOMD0.I2C4GPIO

I2C_BCK

GPIO

GPIO

GPIO

I2C_BDT

GPIO

GPIO

GPIO

PMIC_INT

RTC_IRQ_OUT

GPIO

P10_01
P11_00IOCSYS_IOMD0.PMIC_INT(Open Drain)with PMIC_INT(Open Drain)
P12_00IOCSYS_IOMD0.RTC_IRQ_OUT

GPIO

RTC_IRQ_OUT

RTC_IRQ_OUTGPIO(Open Drain)
P13_00IOCSYS_IOMD0.AP_CLK

GPIO

AP_CLKPMU_WDT

PMU_WDT(Open Drain)

P14_00IOCSYS_IOMD0.GNSS_1PPS_OUT

GPIO

GNSS_1PPS_O

CPU_WDT(Open Drain)

UT
P16_00IOCSYS_IOMD0.SPI0A

CPU_WDTGPIO

UART1_TXD

SPI0_CS_X

ReservedGPIO

UART1_RXD

SPI0_SCK

Reserved

GPIO

I2C2_BCKSPI0_MOSI

Reserved

GPIO

I2C2_BDTSPI0_MISO

Reserved

GPIO

SPI1_CS_X

SPI0_CS_X

Reserved

P18_01GPIO

SPI1_SCKSPI0_SCK

Reserved

P18_02GPIO

SPI0_IO0

SPI0_MOSI

Reserved

P18_03GPIO

SPI0_IO1

SPI0_MISO

Reserved

GPIO

SPI1_IO2

GPIO

Reserved

GPIO

SPI1_IO3GPIO

Reserved

GPIO

SPI2_CS_X

UART0_TXD

I2C3_BCKGPIOSPI2_SCKUART0_RXD

I2C3_BDTGPIO

SPI2_MOSIUART0_CTS

GPIO

GPIO

SPI2_MISO

UART0_RTS

GPIO

GPIO

HIF_IRQ_OUT

HIF_IRQ_OUT

GNSS_1PPS_OU(Open Drain)T

P16_01
P17_00IOCSYS_IOMD0.SPI0B

P17_01
P18_00

P19_00IOCSYS_IOMD0.SPI1AIOCSYS_IOMD0.SPI1B

P19_01
P00_00IOCSYS_IOMD0.SPI2A

P00_01
P01_00IOCSYS_IOMD0.SPI2B

P01_01
P02_00IOCSYS_IOMD0.HIFIRQ

P03_00IOCSYS_IOMD0.HIFEXT

GPIO

GPIO

GPIO

GPS_EXTLD

P1e_00IOCSYS_IOMD1.SEN_IRQ_IN

GPIO

SEN_IRQ_IN

Reserved

Reserved

P1f_00IOCSYS_IOMD1.SPI3_CS0_X

GPIO

SPI3_CS0_X

Reserved

Reserved

P1g_00IOCSYS_IOMD1.SPI3_CS1_X

GPIO

SPI3_CS1_X

Reserved

Reserved

P1h_00IOCSYS_IOMD1.SPI3_CS2_X

GPIO

SPI3_CS2_X

Reserved

Reserved－69/1293－

CXD5602 User ManualP1i_00IOCSYS_IOMD1.SPI3GPIO

SPI3_SCK

Reserved

Reserved

P1i_01GPIO

SPI3_MOSI

Reserved

Reserved

P1i_02GPIO

SPI3_MISO

Reserved

Reserved

GPIO

I2C0_BCK

Reserved

Reserved

GPIO

I2C0_BDT

Reserved

Reserved

GPIO

PWM0

Reserved

Reserved

GPIO

PWM1

GPIO

Reserved

GPIO

PWM2

I2C1_BCK

Reserved

GPIO

PWM3

I2C1_BDT

Reserved

P1j_00IOCSYS_IOMD1.I2C0

P1j_01P1k_00IOCSYS_IOMD1.PWMA

P1k_01P1l_00P1l_01IOCSYS_IOMD1.PWMB－70/1293－

CXD5602 User Manual

3.1.4.2.2

Register for selecting a role of the I/O pins belonging to APP group

Table I/O Configuration-12 shows registers for selecting a role of the I/O pins belonging to APP group. Setting
examples are explained in “3.1.4.3 Function Details”.
Table I/O Configuration-12 Overview of Registers for Selecting a Role of the I/O Pins Belonging to APP Group
Address

0x041014A0

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

IOCAPP_

Reserved-[31:28]-For pin functions selected by IOCAPP_IOMD,

IOMD

USBVBUSRW[27:26]0refer to Table I/O Configuration-13.

PDM

RW

[25:24]

0

MCLK

RW

[23:22]

0

I2S1

RW

[21:20]

0

I2S0

RW

[19:18]

0

SDIOD

RW

[17:16]

0

SDIOC

RW

[15:14]

0

SDIOB

RW

[13:12]

0

SDIOA

RW

[11:10]

0

EMMCB

RW

[9:8]

0

EMMCA

RW

[7:6]

1

SPI4

RW

[5:4]

0

UART2

RW

[3:2]

0

IS

RW

[1:0]

0

Value

－71/1293－

CXD5602 User Manual

Table I/O Configuration-13 shows pin functions selected by IOCAPP_IOMD.
Table I/O Configuration-13 Table of Role Selection for the I/O Pins Belonging to APP GroupPin Name

Register Name

Register Setting value
0

1

2

3

GPIO

IS_CLK

GPIO

GPIO

P1m_01GPIO

IS_VSYNC

GPIO

GPIO

P1m_02GPIO

IS_HSYNC

GPIO

GPIO

P1m_03GPIO

IS_DATA0

GPIO

GPIO

P1m_04GPIO

IS_DATA1

GPIO

GPIO

P1m_05GPIO

IS_DATA2

GPIO

GPIO

P1m_06GPIO

IS_DATA3

GPIO

GPIO

P1m_07GPIO

IS_DATA4

GPIO

GPIO

P1m_08GPIO

IS_DATA5

GPIO

GPIO

P1m_09GPIO

IS_DATA6

GPIO

GPIO

P1m_10GPIO

IS_DATA7

GPIO

GPIO

GPIO

UART2_TXD

Reserved

GPIO

P1n_01GPIO

UART2_RXD

Reserved

GPIO

P1n_02GPIO

UART2_CTS

Reserved

GPIO

P1n_03GPIO

UART2_RTS

Reserved

GPIO

GPIO

SPI4_CS_X

Reserved

GPIO

P1o_01GPIO

SPI4_SCK

Reserved

GPIO

P1o_02GPIO

SPI4_MOSI

Reserved

GPIO

P1o_03GPIO

SPI4_MISO

Reserved

GPIO

GPIO

EMMC_CLK

SPI5_SCK

GPIO

P1p_01GPIO

EMMC_CMD

SPI5_CS_X

GPIO

P1p_02GPIO

EMMC_DATA0SPI5_MOSI

GPIO

P1p_03GPIO

EMMC_DATA1

SPI5_MISO

GPIO

GPIO

EMMC_DATA2

Reserved

GPIO

GPIO

EMMC_DATA3

Reserved

GPIO

GPIO

SDIO_CLK

SPI5_SCK

GPIO

P1r_01GPIO

SDIO_CMD

SPI5_CS_X

GPIO

P1r_02GPIO

SDIO_DATA0SPI5_MOSI

GPIO

P1r_03GPIO

SDIO_DATA1

SPI5_MISO

GPIO

P1r_04GPIO

SDIO_DATA2

GPIO

GPIO

P1r_05GPIO

SDIO_DATA3

GPIO

GPIO

GPIO

SDIO_CD

GPIO

GPIO

GPIO

SDIO_WP

GPIO

GPIO

P1m_00P1n_00P1o_00P1p_00P1q_00IOCAPP_IOMD.IS

IOCAPP_IOMD.UART2

IOCAPP_IOMD.SPI4

IOCAPP_IOMD.EMMCA

IOCAPP_IOMD.EMMCB

P1q_01P1r_00P1s_00P1s_01

IOCAPP_IOMD.SDIOA

IOCAPP_IOMD.SDIOB－72/1293－

CXD5602 User ManualP1t_00IOCAPP_IOMD.SDIOC

GPIO

SDIO_CMDDIR

GPIO

GPIO

P1t_01GPIO

SDIO_DIR0

GPIO

GPIO

P1t_02GPIO

SDIO_DIR1_3

GPIO

GPIO

P1u_00IOCAPP_IOMD.SDIODGPIO

SDIO_CLKI

GPIO

GPIO

P1v_00IOCAPP_IOMD.I2S0

GPIO

I2S0_BCK

Reserved

GPIO

P1v_01GPIO

I2S0_LRCK

Reserved

GPIO

P1v_02GPIO

I2S0_DATA_IN

Reserved

GPIO

P1v_03GPIO

I2S0_DATA_OUT

Reserved

GPIO

GPIO

I2S1_BCK

Reserved

GPIO

P1w_01GPIO

I2S1_LRCK

Reserved

GPIO

P1w_02GPIO

I2S1_DATA_IN

Reserved

GPIO

P1w_03GPIO

I2S1_DATA_OUT

Reserved

GPIO

P1w_00IOCAPP_IOMD.I2S1

P1x_00IOCAPP_IOMD.MCLK

GPIO

MCLK

Reserved

GPIO

P1y_00IOCAPP_IOMD.PDM

GPIO

PDM_CLK

Reserved

GPIO

P1y_01GPIO

PDM_IN

GPIO

GPIO

P1y_02GPIO

PDM_OUT

GPIO

GPIO

GPIO

USB_VBUSINT

GPIO

Reserved

P1z_00IOCAPP_IOMD.USBVBUS－73/1293－

CXD5602 User Manual

3.1.4.2.3

IOCELL Control Register

These registers set IOCELL of each I/O pin. Table I/O Configuration-14 shows overview of registers. Figure I/O
Configuration-8 shows a visualized function inside IOCELL controlled by the parameter that is set by IOCELL
control register. And Table I/O Configuration-15Table I/O Configuration-15 Correspondence Table of IOCELL
Control Registers and Controllable I/O Pinsshows correspondence table of registers and I/O pins.
Table I/O Configuration-14 Overview of Registers to Select Function of IOCELL
Address

0x04100800|

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

IO_*

Reserved-[31:25]

-

-

(1*)

LOWEMI

RW

[24]

1

Output Current Control 0: 4mA(Max64MHz), 1:

Value

0x041009A4

2mA(Max32MHz)
Reserved-[23:17]

-

-

PDN

RW

[16]

1

Pulldown Control 0: Pulldown, 1: Normal

Reserved-[15:9]

-

-

PUN

RW

[8]

1

Pullup Control 0: Pullup, 1: Normal

Reserved

-

[7:1]

-

-

ENZI

RW

[0]

0

Input Enable Control 0: Input Disable, 1: Input Enable(1*)：For pin names corresponding to registers, refer to Table I/O Configuration-15.

The following IOCELL control registers are different from those listed above.
IO_DBG_SWO_CLK.ENZI is reserved.



O_DBG_SWO.ENZI is reserved.



IO_RTC_CLK_IN.LOWEMI is reserved.



The initial value of IO_SPI1_CS_X.LOWEMI is “0”.



The initial value of IO_SPI1_SCK.LOWEMI is “0”.



The initial value of IO_SPI1_IO0.LOWEMI is “0”.



The initial value of IO_SPI1_IO1.LOWEMI is “0”.



The initial value of IO_SPI1_IO2.LOWEMI is “0”.



The initial value of IO_SPI1_IO3.LOWEMI is “0”.



The initial value of IO_DBG_SWOCLK.LOWEMI is “0”.

－74/1293－

CXD5602 User Manual

IO_Configration

2
Pull upState

IO PinIOCELL.LOWEMIIOCELL.PDN
IOCELL.PUP
GPIO Regs
Output Enable
IOCSYS{0,1}.*
IOCAPP.*
Alternate Function
OutputPull Dn
State

GPIO Regs
Alternate Function
Input
IOCELL.ENZIFigure I/O Configuration-8 Visualized Function inside IOCELL Controlled by IOCELL Control Register－75/1293－

CXD5602 User Manual

Table I/O Configuration-15 Correspondence Table of IOCELL Control Registers and Controllable I/O Pins
Register Name

Pin Name

Register Name

Pin Name

Register Name

Pin Name

IO_I2C4_BCK

P10_00

IO_I2C0_BCK

P1j_00

IO_EMMC_DATA2

P1q_00

IO_I2C4_BDT

P10_01

IO_I2C0_BDT

P1j_01

IO_EMMC_DATA3

P1q_01

IO_PMIC_INT

P11_00IO_PWM0

P1k_00

IO_SDIO_CLK

P1r_00

IO_RTC_IRQ_OUT

P12_00IO_PWM1

P1k_01

IO_SDIO_CMD

P1r_01

IO_AP_CLK

P13_00IO_PWM2

P1l_00

IO_SDIO_DATA0

P1r_02

IO_GNSS_1PPS_OUT

P14_00IO_PWM3

P1l_01

IO_SDIO_DATA1

P1r_03

IO_SPI0_CS_X

P16_00

IO_IS_CLK

P1m_00

IO_SDIO_DATA2

P1r_04

IO_SPI0_SCK

P16_01

IO_IS_VSYNC

P1m_01

IO_SDIO_DATA3

P1r_05IO_SPI0_MOSI

P17_00

IO_IS_HSYNC

P1m_02

IO_SDIO_CD

P1s_00

IO_SPI0_MISO

P17_01

IO_IS_DATA0

P1m_03

IO_SDIO_WP

P1s_01

IO_SPI1_CS_X

P18_00

IO_IS_DATA1

P1m_04

IO_SDIO_CMDDIR

P1t_00

IO_SPI1_SCK

P18_01

IO_IS_DATA2

P1m_05

IO_SDIO_DIR0

P1t_01

IO_SPI1_IO0

P18_02

IO_IS_DATA3

P1m_06

IO_SDIO_DIR1_3

P1t_02

IO_SPI1_IO1

P18_03

IO_IS_DATA4

P1m_07

IO_SDIO_CLKI

P1u_00

IO_SPI1_IO2

P19_00

IO_IS_DATA5

P1m_08IO_I2S0_BCK

P1v_00

IO_SPI1_IO3

P19_01

IO_IS_DATA6

P1m_09IO_I2S0_LRCK

P1v_01

IO_SPI2_CS_X

P00_00

IO_IS_DATA7

P1m_10

IO_I2S0_DATA_IN

P1v_02

IO_SPI2_SCK

P00_01

IO_UART2_TXD

P1n_00

IO_I2S0_DATA_OU

P1v_03T
IO_SPI2_MOSI

P01_00IO_UART2_RXD

P1n_01

IO_I2S1_BCK

P1w_00

IO_SPI2_MISO

P01_01

IO_UART2_CTS

P1n_02

IO_I2S1_LRCK

P1w_01

IO_HIF_IRQ_OUT

P02_00IO_UART2_RTS

P1n_03

IO_I2S1_DATA_IN

P1w_02

IO_HIF_GPIO0

P03_00

IO_SPI4_CS_X

P1o_00

IO_I2S1_DATA_OU

P1w_03T
IO_SEN_IRQ_IN

P1e_00

IO_SPI4_SCK

P1o_01

IO_MCLK

P1x_00

IO_SPI3_CS0_X

P1f_00

IO_SPI4_MOSI

P1o_02

IO_PDM_CLK

P1y_00

IO_SPI3_CS1_X

P1g_00

IO_SPI4_MISO

P1o_03

IO_PDM_IN

P1y_01

IO_SPI3_CS2_X

P1h_00

IO_EMMC_CLK

P1p_00

IO_PDM_OUT

P1y_02

IO_SPI3_SCK

P1i_00

IO_EMMC_CMD

P1p_01

IO_USB_VBUSINT

P1z_00

IO_SPI3_MOSI

P1i_01

IO_EMMC_DATA

P1p_02--P1p_03--0
IO_SPI3_MISO

P1i_02

IO_EMMC_DATA
1－76/1293－

CXD5602 User Manual

3.1.4.2.4

I2S Output Control Register

This register performs Output Enable setting when pin P1v_{00,01} and pin P1w_{00,01} are used as I2S I/F.
I2S is operated in master mode or slave mode. When you use I2S in master mode, set it Output Enable to use
P1v_{00,01} and pin P1w_{00,01} as output pin. When you use it in slave mode, set it Output Disable to usethem as input pin.
Table I/O Configuration-16 Overview of Registers for Selecting Output Function of I2S
Address

0x04101474

Register

Bit Field

Name

Name

IOOEN_APPReserved-[31:8]--

I2S1_LRCK

RW

[5]

1

0: Output Enable, 1: Output Disable

I2S1_BCK

RW

[4]

1

0: Output Enable, 1: Output Disable

Reserved

-

[3:2]

-

-

I2S0_LRCK

RW

[1]

1

0: Output Enable, 1: Output Disable

I2S0_BCK

RW

[0]

1

0: Output Enable, 1: Output Disable

3.1.4.2.5

Type

Bit

InitialDescription

Value

PDM_CLK Selection Register

This register selects output signals when pin P1y_00 is used as PDM_CLK output.
Table I/O Configuration-17 Overview of Register for Selecting PDM_CLK Output Function
Address

0x04101470

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

AUDIO_IF_

Reserved-[31:5]--SEL

PDM_CLK_S

RW

[4]

0

selects PDM_CLK output

Value

0: selects OFS_CLK

EL

1: selects MCK_DMIC
Reserved

-

[3:0]

-

－77/1293－-

CXD5602 User Manual

3.1.4.2.6

SDIO Input Control Register

This register sets input values to IP (SDIO) inside the LSI when pin P1s_{00,01} is not used as SDIO function(when GPIO mode is selected). For function details, refer to “3.1.4.3.31 SDIO.”
Table I/O Configuration-18 Overview of Registers for Selecting Input Value to SDIO
Address

0x04101478

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

IOFIX_APPReserved-[31:2]--SDIO_WP

RW

[1]

1

input value to SDIO_WP when SDIO function isValue

not used
SDIO_CD

RW

[0]

1

input value to SDIO_CD when SDIO function is
not used

3.1.4.3 Function Details
To each pin, Pin Multiplexer can assign a role selecting from up to four options. Multiple roles cannot be played
at a time. You can assign roles by setting IOCSYS_IMOD0, 1, IOCAPP_IMOD and IO_*.
Figure I/O Configuration-9 shows pin P1r_02 as examples of assigning roles. Pin P1r_02 can be assigned one rolefrom three options of GPIO, SDIO_DATA0, and SPI5_MOSI.

－78/1293－

CXD5602 User Manual

Select GPIO(inout)

Select SDIO_DATA0(inout)
2

IO Configuration

IOCAPP_IMOD.SDIOA=0
GPIO

0

2

IO Configuration

IOCAPP_IMOD.SDIOA=1
GPIO

00 1 2 30 1 2 3
0
1
2
3

0
1
2
3

SDIO

SPI5

1
2
3

SDIO

SPI5

1
2
3

IO_SDIO_DATA0.ENZIIO_SDIO_DATA0.ENZI

Select SPI5_MOSI(output)
2

IO Configuration

IOCAPP_IMOD.SDIOA=2
GPIO

00 1 2 3
0
1
2
3

1
2
3

SDIO

SPI5

IO_SDIO_DATA0.ENZIFigure I/O Configuration-9 Examples of Assigning Roles to the Pin (P1r_02)－79/1293－

CXD5602 User Manual

3.1.4.3.1

I2C4

The following are settings that pin P10_{00,01} is assigned I2C (for PMIC) role.
IO_I2C_BCK.ENZI=1



IO_I2C_BDT.ENZI=1IOCSYS_IOMD0.I2C4=1

3.1.4.3.2

PMIC_INT

The following are settings that pin P11_00 is assigned PMIC_INT role.


IO_PMIC_INT.ENZI=1IOCSYS_IOMD0.PMIC_INT=1

Note:
Before receiving PMIC_INT, by using the register of RTC{0,1}, set External Alarm Output Select Signal toExternal Interrupt (RTC{0,1}_RTC_CTL.SYNC_SEL=2). Figure I/O Configuration-10 shows the signal routes.

－80/1293－

CXD5602 User Manual

IO Configuration
1

2

IOCSYS_IMOD0.PMIC_INT
GP_PMIC_INT.DIR
select PMIC_INT

0 1 2 30
1
2
3

P11_0000GP_PMIC_INT.OUT

RTC0OExtAlarm
PMIC_INT
ExternalAlerm2
ExternalAlerm1
ExternalAlerm0

RTC1
OExtAlarm

1
2
3

PMIC_INT
ExternalAlerm2
ExternalAlerm1
ExternalAlerm0

IO_PMIC_INT.ENZIInterrupt to CPU(PMIC_INT)

OPEN

2

1

GP_PMIC_INT.IN

IOCSYS_IMOD0.RTC_IRQ_OUT
GP_RTC_IRQ_OUT.DIR

0 1 2 3

P12_000
1
2
3

GP_RTC_IRQ_OUT.OUT
0

GP_RTC_IRQ_OUT.IN
1
2
3

OPEN
OPEN
OPEN
IO_RTC_IRQ_OUT.ENZIFigure I/O Configuration-10 PMIC_INT Signal Routes (MODE=1)－81/1293－

CXD5602 User Manual

3.1.4.3.3

PMIC_INT with RTC_IRQ_OUT (Open Drain)

In this mode, the pin P11_00 is used bidirectionally as RTC_IRQ_OUT output role, and as PMIC_INT (for RTC
synchronization) input role. By using pins of both CXD5602 and PMIC connected to CXD5602 as Open Drain,
the above two roles can be compatible without any dynamic I/O control.
The following are settings that pin P11_00 is used as PMIC_INT input and RTC_IRQ_OUT output.


IO_PMIC_INT.ENZI=1IOCSYS_IOMD0.PMIC_INT=2

Note:
Before receiving PMIC_INT, by using the register of RTC{0,1}, set External Alarm Output Select Signal toExternal Interrupt (RTC{0,1}_RTC_CTL.SYNC_SEL=2). Figure I/O Configuration-11 shows the signal routes.
Besides, when you want to use PMIC_INT as CPU interrupt, select pin P11_00 using GPIO External Interrupt
selection (Section 3.2.4.3 GPIO External Interrupt) function.

Set nagative logic

IO Configuration
1

2

IOCSYS_IMOD0.PMIC_INT
GP_PMIC_INT.DIR
selectExternalAlerm2

0 1 2 30
1
2
3

P11_0000GP_PMIC_INT.OUT

RTC0OExtAlarm
PMIC_INT
ExternalAlerm2
ExternalAlerm1
ExternalAlerm0

RTC1
OExtAlarm

1
2
3

PMIC_INT
ExternalAlerm2
ExternalAlerm1
ExternalAlerm0

IO_PMIC_INT.ENZIInterrupt to CPU(PMIC_INT)

OPEN

2

1

GP_PMIC_INT.IN

IOCSYS_IMOD0.RTC_IRQ_OUT
GP_RTC_IRQ_OUT.DIR

0 1 2 3

P12_000
1
2
3

GP_RTC_IRQ_OUT.OUT
0

GP_RTC_IRQ_OUT.IN
1
2
3

OPEN
OPEN
OPEN
IO_RTC_IRQ_OUT.ENZIFigure I/O Configuration-11 PMIC_INT Signal Routes (MODE=2 Open Drain)－82/1293－

CXD5602 User Manual

3.1.4.3.4

RTC_IRQ_OUT

The following is a setting that pin P12_00 is assigned RTC_IRQ_OUT role.


IOCSYS_IOMD0.RTC_IRQ_OUT=1

3.1.4.3.5

RTC_IRQ_OUT(Open Drain)

The following is a setting that pin P12_00 is assigned RTC_IRQ_OUT role (Open Drain). The pin becomes tooperate as Open Drain. By using the register of RTC0, set the External Alarm Output Select Signal to negative
logic (RTC0_RTC_CTL.EXTALM_POL=1).


IOCSYS_IOMD0.RTC_IRQ_OUT=2
Set nagative logic

IO Configuration
1

2

IOCSYS_IMOD0.PMIC_INT
GP_PMIC_INT.DIR

0 1 2 30
1
2
3

P11_0000GP_PMIC_INT.OUT

RTC0OExtAlarm
PMIC_INT
ExternalAlerm2
ExternalAlerm2
ExternalAlerm2

RTC1
OExtAlarm

1
2
3

PMIC_INT
ExternalAlerm2
ExternalAlerm1
ExternalAlerm0

IO_PMIC_INT.ENZIInterrupt to CPU(PMIC_INT)

OPEN

2

1

GP_PMIC_INT.IN

IOCSYS_IMOD0.RTC_IRQ_OUT
GP_RTC_IRQ_OUT.DIR

0 1 2 3

P12_000
1
2
3

GP_RTC_IRQ_OUT.OUT
0

GP_RTC_IRQ_OUT.IN
1
2
3

OPEN
OPEN
OPEN
IO_RTC_IRQ_OUT.ENZIFigure I/O Configuration-12 RTC_IRQ_OUT Signal Routes (MODE=2 Open Drain)－83/1293－

CXD5602 User Manual

3.1.4.3.6

AP_CLKThe following are settings that pin P13_00 is assigned AP_CLK role.


IO_AP_CLK.ENZI=1IOCSYS_IOMD0.AP_CLK=1

3.1.4.3.7

PMU_WDTThe following is a setting that pin P13_00 is assigned PMU_WDT role.


IOCSYS_IOMD0.AP_CLK=2

3.1.4.3.8

PMU_WDT (Open Drain)

The following is a setting that pin P13_00 is assigned PMU_WDT (Open Drain) role. The pin becomes to operate
as Open Drain and outputs in negative logic.
IOCSYS_IOMD0.AP_CLK=3



3.1.4.3.9

GNSS_1PPS_OUT

The following is a setting that pin P14_00 is assigned GNSS_1PPS_OUT role.


IOCSYS_IOMD0.GNSS_1PPS_OUT=1

The following is a setting that pin P02_00 is assigned GNSS_1PPS_OUT role.


IOCSYS_IOMD1.HIFIRQ=3

3.1.4.3.10

CPU_WDTThe following is a setting that pin P14_00 is assigned CPU_WDT role.


IOCSYS_IOMD0.GNSS_1PPS_OUT=2

3.1.4.3.11

CPU_WDT (Open Drain)

The following is a setting that pin P14_00 is assigned CPU_WDT (Open Drain) role. The pin becomes to operate
as Open Drain and outputs in negative logic.


IOCSYS_IOMD0.GNSS_1PPS_OUT=3－84/1293－

CXD5602 User Manual

3.1.4.3.12

UART1

The following are settings that pin P16_{00,01} are assigned UART role.


IO_SPI0_SCK.ENZI=1IOCSYS_IOMD0.SPI0A=1

3.1.4.3.13

I2C2

The following are settings that pin P17_{00,01} are assigned I2C role.


IO_SPI0_MOSI.ENZI=1



IO_SPI0_MISO.ENZI=1IOCSYS_IOMD0.SPI0B=1

3.1.4.3.14

SPI0

The following are settings that pin P16_{00,01} and P17_{00,01} are assigned SPI role.


IO_SPI0_MISO.ENZI=1IOCSYS_IOMD0.SPI0A=2



IOCSYS_IOMD0.SPI0B=2

A function for pin P16_{00,01} are selected by IOCSYS_IOMD0.SPI0A.
A function for pin P17_{00,01} are selected by IOCSYS_IOMD0.SPI0B.
The following are settings that pin P18_{00,01,02,03} are assigned SPI role.


IO_SPI1_IO1.ENZI=1IOCSYS_IOMD0.SPI1A=2

Note: SPI0 must not be assigned to both of the two pins.

3.1.4.3.15

SPI1

The following are settings that pin P18_{00,01,02,03} and pin P19_{00,01} are assigned SPI (for accessing Flashmemory) role.


IO_SPI1_IO0.ENZI=1



IO_SPI1_IO1.ENZI=1



IO_SPI1_IO2.ENZI=1



IO_SPI1_IO3.ENZI=1IOCSYS_IOMD0.SPI1A=1

IOCSYS_IOMD0.SPI1B=1－85/1293－

CXD5602 User Manual

3.1.4.3.16

SPI2

If the pin SYSTEM0 is Low and the pin SYSTEM1 is High when POR is released, pin P00_{00,01} and pin
P01_{00,01} are assigned SPI role automatically. For this reason, usually SPI2 role cannot be set by registers.
The following are settings to release roles assigned automatically by pin SYSTEM0 and pin SYSTEM1, and to
newly assign pin P00_{00,01} and pin P01_{00,01} SPI role for debugging.


DBG_HOSTIF_SEL.LATCH_OFF=1



IO_SPI2_CS_X.ENZI=1



IO_SPI2_SCK.ENZI=1



IO_SPI2_MOSI.ENZI=1IOCSYS_IOMD0.SPI2A=1



IOCSYS_IOMD0.SPI2B=1

3.1.4.3.17

UART0

If the pin SYSTEM0 is High and the pin SYSTEM1 is Low when POR is released, pin P00_{00,01} are assigned
UART role automatically. For this reason, usually UART0 role cannot be set by registers.
The following is a setting that pin P01_{00,01} are used as URAT0_CTS or UART0_RTS.


IOCSYS_IOMD0.SPI2B=2

The following are settings to release roles assigned automatically by pin SYSTEM0 and pin SYSTEM1, and to
newly assign pin P00_{00,01} and pin P01_{00,01} UART role for debugging.


DBG_HOSTIF_SEL.LATCH_OFF=1



IO_SPI2_SCK.ENZI=1 (RXD input)

IO_SPI2_MOSI.ENZI=1 (CTS input)



IOCSYS_IOMD0.SPI2A=2



IOCSYS_IOMD0.SPI2B=2－86/1293－

CXD5602 User Manual

3.1.4.3.18

I2C3

If the pin SYSTEM0 is Low and the pin SYSTEM1 is Low when POR is released, pin P00_{00,01} are assigned
I2C role automatically. For this reason, usually I2C3 role cannot be set by registers.
The following are settings to release roles assigned automatically by pin SYSTEM0 and pin SYSTEM1, and to
newly assign pin P00_{00,01} I2C role for debugging.


DBG_HOSTIF_SEL.LATCH_OFF=1



IO_SPI2_CS_X.ENZI=1



IO_SPI2_SCK.ENZI=1IOCSYS_IOMD0.SPI2A=3

3.1.4.3.19

HIF_IRQ_OUT

The following is a setting that pin P02_00 is assigned HIF_IRQ_OUT role.


IOCSYS_IOMD0.HIFIRQ=1

3.1.4.3.20

HIF_IRQ_OUT (Open Drain)

The following is a setting that pin P02_00 is assigned HIF_IRQ_OUT role. The pin becomes to operate as Open
Drain and outputs in negative logic.


IOCSYS_IOMD0.HIFIRQ=2

3.1.4.3.21

GPS_EXTLDThe following are settings that pin P03_00 is assigned GPS_EXTLD role.


IO_HIF_GPIO0.ENZI=1IOCSYS_IOMD0.HIFEXT=3

3.1.4.3.22

SEN_IRQ_IN

The following are settings that pin P1e_00 is assigned SEN_IRQ_IN role.


IO_SEN_IRQ_IN.ENZI=1IOCSYS_IOMD1.SEN_IRQ_IN=1－87/1293－

CXD5602 User Manual

3.1.4.3.23

SPI3

The following are settings that pin P1f_00, pin P1g_00, pin P1h_00, and pin P1i_{00,01,02} are assigned SPI
role.


IO_SPI3_MISO.ENZI=1IOCSYS_IOMD1.SPI3_CS0_X=1



IOCSYS_IOMD1.SPI3_CS1_X=1



IOCSYS_IOMD1.SPI3_CS2_X=1



IOCSYS_IOMD1.SPI3=1

3.1.4.3.24

I2C0

The following are settings that pin P1j_{00,01} is assigned I2C role.
IO_I2C0_BCK.ENZI=1



IO_I2C0_BDT.ENZI=1IOCSYS_IOMD1.I2C0=1

3.1.4.3.25

I2C1

The following are settings that pin P1l_{00,01} are assigned I2C role.


IO_PWM2.ENZI=1



IO_PWM3.ENZI=1IOCSYS_IOMD1.PWMB=2

3.1.4.3.26

PWM

The following are settings that pin P1k_{00,01} and pin P1l_{00,01} are assigned PWM role.


IOCSYS_IOMD1.PWMA=1



IOCSYS_IOMD1.PWMB=1－88/1293－

CXD5602 User Manual

3.1.4.3.27

Image Sensor

The following are settings that pin P1m_{00,01,02,03,04,05,06,07,08,09,10} are assigned Image Sensor role.


IO_IS_CLK.ENZI=1



IO_IS_VSYNC.ENZI=1



IO_IS_HSYNC.ENZI=1



IO_IS_DATA{0~7}.ENZI=1



IOCAPP_IOMD.IS=1

3.1.4.3.28

UART2(APP_UART)The following are settings that pin P1n_{00,01,02,03} are assigned UART role.


IO_UART2_RXD.ENZI=1



IO_UART2_CTS.ENZI=1



IOCAPP_IOMD.UART2=1

3.1.4.3.29

SPI4(APP_SPI)The following are settings that pin P1o_{00,01,02,03} are assigned SPI role.


IO_SPI4_MISO.ENZI=1



IOCAPP_IOMD.SPI4=1

3.1.4.3.30

EMMC

The following are settings that pin P1p{00,01,02,03} and pin P1q_{00,01} are assigned EMMC role.


IO_EMMC_CMD.ENZI=1



IO_EMMC_DATA{0~3}.ENZI=1



IOCAPP_IOMD.EMMCA=1



IOCAPP_IOMD.EMMCB=1－89/1293－

CXD5602 User Manual

3.1.4.3.31

SDIO

The following are settings that pin P1r_{00,01,02,03,04,05}, pin P1s{00,01}, pin P1t_{00,01,02}, and pin P1u_00
are assigned SDIO role.


IO_SIDO_CLK.ENZI=1



IO_SIDO_CMD.ENZI=1



IO_SIDO_DATA{0~3}.ENZI=1



IO_SIDO_CD.ENZI=1



IO_SIDO_WP.ENZI=1



IO_SIDO_CLKI.ENZI=1



IOCAPP_IOMD.SDIOA=1



IOCAPP_IOMD.SDIOB=1



IOCAPP_IOMD.SDIOC=1



IOCAPP_IOMD.SDIOD=1

Figure I/O Configuration-13 shows connecting diagram of SDIO input clock.
SDIO IP uses either clock turned inside IOCELL or clock turned outside the LSI.

－90/1293－

CXD5602 User Manual

IO Configuration
0 0

2

IOCAPP_IMOD.SDIOA
GP_SDIO_CLK.DIR

0 1 2 3
GP_SDIO_CLK.OUT
SDIO_CLK
SPI5_SCK0
1
2
3

P1r_00

GP_SDIO_CLK.IN
12
3

SDIO_CLK
SPI5_SCKOPEN
IO_SDIO_CLK.ENZI
2

1

IOCAPP_IMOD.SDIOD
GP_SDIO_CLKI.DIR

0 1 2 3

P1u_000
1
2
3

GP_SDIO_CLKI.OUT
0

GP_SDIO_CLKI.IN
1
2
3

SDIO_CLKI
OPEN
OPEN
IO_SDIO_CLKI.ENZIFigure I/O Configuration-13 SDIO CLK Input Schematic－91/1293－SDIO

CXD5602 User Manual

While pin P1s_00 and pin P1s_01 are assigned GPIO role, CD/WP signal of internal IP (SDIO) can be set byusing IOFIX_APP. Figure I/O Configuration-14 shows connecting diagram of CD/WP signal to SDIO IP.

IO Configuration
1

2

IOCAPP_IMOD.SDIOB
GP_SDIO_CD.DIR

0 1 2 3
GP_SDIO_CD.OUT

0
1
2
3

P1s_000

When IOCAPP_IOMD.SDIOB = 1,
Connect from P1s_00 to SDIO_CD
When IOCAPP_IOMD.SDIOB = 0,
Connect from IOCFIX_APP.SDIO_CD to SDIO_CD[0]

GP_SDIO_CD.IN
1
2

OPEN

3

OPEN

1
0

SDIO_CDIOCFIX_APP.SDIO_CD
IO_SDIO_CD.ENZI

1

SDIO

GP_SDIO_WP.DIR

0 1 2 3

P1s_01

GP_SDIO_WP.OUT

0
1
2
3

0

[0]
GP_SDIO_WP.IN
1
2

OPEN

3

OPEN

1
0

SDIO_WPIOCFIX_APP.SDIO_WP
IO_SDIO_WP.ENZIFigure I/O Configuration-14 SDIO WP/CD Input Control Register Schematic

3.1.4.3.32

I2S0

When you use a pin as I2S role, you need to select I2S role by using IOCAPP_IOMD, as well as decide in whichmode I2S role should be played, master or slave. According to the decision, you need to set IOOEN_APP
adequately.
The following are settings that pin P1v_{00,01,02,03} are used as the I2S master.
IO_I2S0_BCK.ENZI=0 (Input Disable)

IO_I2S0_LRCK.ENZI=0 (Input Disable)

IO_I2S0_DATA_IN.ENZI=1(Input Enable)



IOCAPP_IOMD.I2S0=1



IO_IOOEN_APP.I2S0_BCK=0 (Output Enable)

IO_IOOEN_APP.I2S0_LRCK=0 (Output Enable)－92/1293－

CXD5602 User Manual

The following are settings that pin P1v_{00,01,02,03} are used as the I2S slave.
IO_IOOEN_APP.I2S0_BCK=1 (Output Disable)

IO_IOOEN_APP.I2S0_LRCK=1 (Output Disable)

IO_I2S0_BCK.ENZI=1 (Input Enable)

IO_I2S0_LRCK.ENZI=1 (Input Enable)

IO_I2S0_DATA_IN.ENZI=1 (Input Enable)



IOCAPP_IOMD.I2S0=1

3.1.4.3.33

I2S1

When you use a pin as I2S role, you need to select I2S role by using IOCAPP_IOMD, as well as decide in whichmode I2S role should be played, master or slave. According to the decision, you need to set IOOEN_APP
adequately.
The following are settings that pin P1w_{00,01,02,03} are assigned the I2S master.
IO_I2S1_BCK.ENZI=0 (Input Disable)

IO_I2S1_LRCK.ENZI=0 (Input Disable)

IO_I2S1_DATA_IN.ENZI=1(Input Enable)



IOCAPP_IOMD.I2S1=1



IO_IOOEN_APP.I2S1_BCK=0 (Output Enable)

IO_IOOEN_APP.I2S1_LRCK=0 (Output Enable)

The following are settings that pin P1w_{00,01,02,03} are assigned the I2S slave.
IO_IOOEN_APP.I2S1_BCK=1 (Output Disable)

IO_IOOEN_APP.I2S1_LRCK=1 (Output Disable)

IO_I2S1_BCK.ENZI=1 (Input Enable)

IO_I2S1_LRCK.ENZI=1 (Input Enable)

IO_I2S1_DATA_IN.ENZI=1 (Input Enable)



IOCAPP_IOMD.I2S1=1

3.1.4.3.34

MCLK

The following are settings that pin P1x_00 is assigned Master Clock (MCLK) role.


IO_MCLK.ENZI=1 (Input Enable)



IOCAPP_IOMD.MCLK=1

3.1.4.3.35

PDM

The following are settings that pin P1y_{00,01,02} are assigned PDM_OUT role (OFS_CLK output).

－93/1293－

CXD5602 User Manual

IO_PDM_IN.ENZI=1 (Input Enable)



AUDIO_IF_SEL.PDM_CLK_SEL=0

IOCAPP_IOMD.PDM=1

The following are settings that pin P1y_{00,01,02} are assigned PDM_OUT role (MCK_DMIC output).


IO_PDM_IN.ENZI=1 (Input Enable)



AUDIO_IF_SEL.PDM_CLK_SEL=1



IOCAPP_IOMD.PDM=1

3.1.4.3.36

USB_VBUSINT

The following are settings that pin P1z_00 is assigned USB_VBUSINT input role.


IO_USB_VBUSINT.ENZI=1(Input Enable)



IOCAPP_IOMD.USBVBUS=1

3.1.4.3.37

SPI5

The following are settings that pin P1p_{00,01,02,03} are assigned SPI role.


IO_EMMC_DATA1.ENZI=1(Input Enable)



IOCAPP_IOMD.EMMCA=2

The following are settings that pin P1r_{00,01,02,03} are assigned SPI role. In this setting, pin P1r_{04,05} canbe used as GPIO role.


IO_SDIO_DATA1.ENZI=1(Input Enable)



IOCAPP_IOMD.SDIOA=2


Note: SPI5 must not be assigned to both of the two pins.

－94/1293－

CXD5602 User Manual

3.2

General Purpose Input/Output (GPIO)

3.2.1

Outlines and Features

In the chapter of GPIO, GPIO control, detection control, and pin selection for interrupt are explained.

3.2.2

Function List
Table General Purpose Input/Output (GPIO)-19 Function List

No

Function Name

Description

1

GPIO Control

controls I/O pins to switch between input and output

2

I/O Pin Selection

selects I/O pins used for interrupts

3

External

Interrupt

selects an interrupt option for outputting to SYSCPU and DSP

Detection

controls “Event Detection” that can be selected as an option described in the No. 3

Option4

Event
Control

above－95/1293－

CXD5602 User Manual

3.2.3

Function Specification Outlines

3.2.3.1 Function Block Diagrams
Figure General Purpose Input/Output (GPIO)-15 shows entire functions of GPIO and Figure General Purpose
Input/Output (GPIO)-16 shows Event Detect block inside GPIO function.

I/O Function

Pull-up/Pull-down

Pull up/down, LOWEMIPin Output Enable
Pin Output

2

IO PinPull up
State
Pull Dn
State

Output(Mode1)
Output(Mode2)
Output(Mode3)

Pin Input
Input(Mode1)
Input(Mode2)
Input(Mode3)

GPIO Control

I/O Configuration

Alternate Function Output

GPIO Status
Alternate Function Input

Event
DetectPin Input Enable

Input Enable

Figure General Purpose Input/Output (GPIO)-15 GPIO Overview Block Diagram－96/1293－

Wakeup factor(to PMU)
Interrupt(to CPU/DSP)CXD5602 User Manual

Event Detect

CRG
SCU

4

RTC0

4

Wakeup factor(to PMU)GNSSInternal signal detection

SYSIOP_SUB

0
14HI F_DETECT_I2C_SLAVE

14
Pos edge

Pulse

20

S et
C lr

1

INT_PMIC_I2CM

PMU

16

External signal detection
20

0

64 to 1......

Chattering removal

1

USB_VBUS

Instant High

Pulse

Instant Low

Pulse

Level HighLevel

Level Low

Level

Pos edge

Pulse

Neg edge

Pulse

Pos/Neg edge

Pulse

or

PMIC_INT

001

EXDEVICE[11:0]
USBVBUSUSBVBUSN
HVDD
PMIC_INT

0
1
2
3
4

2
3

S et
C lr

4
5
6

PMU_WAKE_TRIGx

PMU_WAKE_TRIG_ENx
PMU_WAKE_TRIGx_RAW

PMU_WAKE_TRIG_CPUINTSELx

HIF_SPI_CS_X
HIF_SCL_LOW

PMU_WAKE_TRIGx_CLR

HIF_UART_RXD

PMU_WAKE_TRIG_INTDETx

SEN_INTHVDD_DETPMU_WAKE_TRIG_NOISECUTENx

from I/O

External
signal selectFigure General Purpose Input/Output (GPIO)-16 Diagram of GPIO Event Detect Block－97/1293－

Interrupt(to CPU/DSP)CXD5602 User Manual

3.2.4

Detailed Function and Control Specification

3.2.4.1 GPIO Control
GPIO Control can be performed when I/O pins are set as GPIO mode. The GPIO mode can be set by using Pin
Multiplexer register IOCSYS_IOMD{0,1} or IOCAPP_IOMD{0,1}. For details for setting GPIO mode, refer to
Section 3.1.4 (Pin Multiplexer). Table General Purpose Input/Output (GPIO)-20 shows GPIO control registers.
Table General Purpose Input/Output (GPIO)-20 GPIO Control Register
Address

0x04102000|

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

GP_*

ReservedRO[31:17]

0

Reserved

(1*)

DIR

RW

[16]

1

OutputEnable control in GPIO mode

Value

0x04102188

0: OutputEnable, 1: OutputDisable
ReservedRO[15:9]

0Reserved

OUT

RW

[8]

0

OutputData control in GPIO mode

Reserved

RO

[7:1]

0

Reserved

IN

RO

[0]

0

I/O pin value(1*): A register is prepared for each I/O pin. For correspondence of I/O pins to registers, refer to Table

General Purpose

Input/Output (GPIO)-21.


GP_*.DIR: Control of OutputEnable
Set the register OutputEnable when you use GPIO as output, set it OutputDisable when you use GPIO as
input.



GP_*.IN: Confirmation of I/O pin value
By setting IO_*.ENZI = 1 (refer to 3.1 in the chapter of IO Configuration), the I/O pin value can be read. The
value can be read not only under GPIO output control, but also under other than GPIO controls.



GP_*.OUT: Control of OutputData
0/1 is output to an I/O pin according to the control register setting.

－98/1293－

CXD5602 User Manual

Table General Purpose Input/Output (GPIO)-21 Correspondence of GPIO Control Registers to I/O Pins
Register Name

Pin Name

Register Name

Pin Name

Register Name

Pin Name

GP_I2C4_BCK

P10_00

GP_I2C0_BCK

P1j_00GP_EMMC_DATA2

P1q_00

GP_I2C4_BDT

P10_01

GP_I2C0_BDT

P1j_01

GP_EMMC_DATA3

P1q_01

GP_PMIC_INT

P11_00

GP_PWM0

P1k_00

GP_SDIO_CLK

P1r_00

GP_RTC_IRQ_OUT

P12_00

GP_PWM1

P1k_01

GP_SDIO_CMD

P1r_01

GP_AP_CLK

P13_00

GP_PWM2

P1l_00

GP_SDIO_DATA0

P1r_02

GP_GNSS_1PPS_OUT

P14_00

GP_PWM3

P1l_01

GP_SDIO_DATA1

P1r_03

GP_SPI0_CS_X

P16_00GP_IS_CLK

P1m_00

GP_SDIO_DATA2

P1r_04

GP_SPI0_SCK

P16_01

GP_IS_VSYNC

P1m_01

GP_SDIO_DATA3

P1r_05

GP_SPI0_MOSI

P17_00GP_IS_HSYNC

P1m_02

GP_SDIO_CD

P1s_00

GP_SPI0_MISO

P17_01

GP_IS_DATA0

P1m_03

GP_SDIO_WP

P1s_01

GP_SPI1_CS_X

P18_00GP_IS_DATA1

P1m_04

GP_SDIO_CMDDIR

P1t_00

GP_SPI1_SCK

P18_01

GP_IS_DATA2

P1m_05

GP_SDIO_DIR0

P1t_01

GP_SPI1_IO0

P18_02

GP_IS_DATA3

P1m_06

GP_SDIO_DIR1_3

P1t_02

GP_SPI1_IO1

P18_03

GP_IS_DATA4

P1m_07

GP_SDIO_CLKI

P1u_00

GP_SPI1_IO2

P19_00GP_IS_DATA5

P1m_08GP_I2S0_BCK

P1v_00

GP_SPI1_IO3

P19_01

GP_IS_DATA6

P1m_09GP_I2S0_LRCK

P1v_01

GP_SPI2_CS_X

P00_00GP_IS_DATA7

P1m_10

GP_I2S0_DATA_IN

P1v_02

GP_SPI2_SCK

P00_01

GP_UART2_TXD

P1n_00

GP_I2S0_DATA_OU

P1v_03T
GP_SPI2_MOSI

P01_00GP_UART2_RXD

P1n_01

GP_I2S1_BCK

P1w_00

GP_SPI2_MISO

P01_01

GP_UART2_CTS

P1n_02

GP_I2S1_LRCK

P1w_01

GP_HIF_IRQ_OUT

P02_00GP_UART2_RTS

P1n_03

GP_I2S1_DATA_IN

P1w_02

GP_HIF_GPIO0

P03_00

GP_SPI4_CS_X

P1o_00

GP_I2S1_DATA_OU

P1w_03

T
GP_SEN_IRQ_IN

P1e_00

GP_SPI4_SCK

P1o_01

GP_MCLK

P1x_00

GP_SPI3_CS0_X

P1f_00

GP_SPI4_MOSI

P1o_02

GP_PDM_CLK

P1y_00

GP_SPI3_CS1_X

P1g_00

GP_SPI4_MISO

P1o_03

GP_PDM_IN

P1y_01

GP_SPI3_CS2_X

P1h_00GP_EMMC_CLK

P1p_00

GP_PDM_OUT

P1y_02

GP_SPI3_SCK

P1i_00GP_EMMC_CMD

P1p_01

GP_USB_VBUSINT

P1z_00

GP_SPI3_MOSI

P1i_01

GP_EMMC_DATA

P1p_02--P1p_03--0
GP_SPI3_MISO

P1i_02

GP_EMMC_DATA1－99/1293－

CXD5602 User Manual

GPIO Output Control
0/1 can be output to an I/O pin according to the control register setting. The status that a control register value isdirectly output to an I/O pin is called GPIO Output Control.
Settings in GPIO Output Control are described below.


GP_*.DIR = 0 (OutputEnable)

{IOCSYS/IOCAPP}_IOMD{0/1}.* = 0

GP_*.OUT = any value

Figure General Purpose Input/Output (GPIO)-17 shows a visualized function controlled by GPIO parameter that is
set by GPIO output control register.

I/O Function

Pull-up/Pull-down

Pin Output Enable

GP_*.DIR=0

Pin Output

GP_*.OUT

2

IO PinPull up
State
Pull Dn
State

Pull up/down, LOWEMI

Output(Mode1)
Output(Mode2)
Output(Mode3)

Pin Input
Input(Mode1)
Input(Mode2)
Input(Mode3)

GPIO Control

I/O Configuration

Alternate Function Output

GPIO Status
Alternate Function Input

Event
DetectPin Input Enable

Wakeup factor(to PMU)
Interrupt(to CPU/DSP)

Input Enable

Figure General Purpose Input/Output (GPIO)-17 Output Signal Route in the I/O Function Controlled by GPIO
Parameter
For example, the settings that pin P10_00 is assigned GPIO output control function are described below.


GP_I2C4_BCK.DIR = 0 (OutputDisable)



IOCSYS_IOMD0.I2C4 = 0



GP_I2C4_BCK.OUT = (1/0)－100/1293－

CXD5602 User Manual

GPIO Input Control
Values that are input to I/O pins can be read out as the status registers. As for the inputs, the status registers can beread out without any special settings. This function is called “input control” in contrast to output control but
actually the “input control” does not control input. The input control is particularly called GPIO input control
when it is used as GPIO.
Settings in GPIO input control are described below.


IO_*.ENZI = 1 (InputEnable)



GP_*.DIR = 1 (OutputDisable)



IOCSYS_IOMD{0,1}.* = 0 (SYS Group) or IOCAPP_IOMD{0,1}.* = 0 (APP Group)Confirm the input value by reading GP_*.IN.

Figure General Purpose Input/Output (GPIO)-18 shows a visualized function controlled by GPIO parameter that is
set by GPIO input control register.

I/O Function

Pull-up/Pull-down

Pin Output Enable

Pull up/down, LOWEMI
GP_*.DIR=1
GPIO Control

Pin Output

I/O Configuration

2

IO PinPull up
State
Pull Dn
State

Output(Mode1)
Output(Mode2)
Output(Mode3)

Pin Input

Alternate Function Output

GP_*.IN

Input(Mode1)
Input(Mode2)
Input(Mode3)

GPIO Status
Alternate Function Input

IO_*.ENZI=1
Pin Input Enable

Event
DetectWakeup factor(to PMU)
Interrupt(to CPU/DSP)

Input Enable

Figure General Purpose Input/Output (GPIO)-18 Input Signal Route in the I/O Function Controlled by GPIO
Parameter
For example, the settings that pin P10_00 is assigned GPIO input control function are described below.


IO_I2C4_BCK.ENZI = 1 (InputEnable)



GP_I2C4_BCK.DIR = 1 (OutputDisable)



IOCSYS_IOMD0.I2C4 = 0

Confirm the input value by reading GP_I2C4_BCK.IN.

－101/1293－

CXD5602 User Manual

3.2.4.2 I/O Pin Selection
In the chapter of I/O Pin Selection, how to select pins used as external interrupts is explained. I/O pins used asinterrupts are classified into two groups: SYS group and APP group. You can select six pins each from both SYS
group and APP group. Table General Purpose Input/Output (GPIO)-23 shows I/O pins belonging to SYS group,
and Table General Purpose Input/Output (GPIO)-25 shows I/O pins belonging to APP group. Figure General
Purpose Input/Output (GPIO)-19 shows the function in the Event Detect Block, which is explained in this section.

Event Detect

CRG
SCU

4

RTC0

4

Wakeup factor(to PMU)GNSSInternal signal detection

SYSIOP_SUB

0
14HI F_DETECT_I2C_SLAVE

14
Pos edge

Pulse

20

S et
C lr

1

INT_PMIC_I2CM

PMU

16

External signal detection
20

External
signal select064 to 1......

Chattering removal

1

USB_VBUS

Pulse

Instant Low

Pulse

Level HighLevel

Level Low

Level

Pos edge

Pulse

Neg edge

Pulse

Pos/Neg edge

Pulse

or

PMIC_INT

001

EXDEVICE[11:0]
USBVBUSUSBVBUSN
HVDD
PMIC_INT

0
1
2
3
4

2
3

S et
C lr

4
5
6

Figure General Purpose Input/Output (GPIO)-19 GPIO Pin Selection－102/1293－

PMU_WAKE_TRIGx

PMU_WAKE_TRIG_ENx
PMU_WAKE_TRIGx_RAW

PMU_WAKE_TRIG_CPUINTSELx

HIF_SPI_CS_X
HIF_SCL_LOW

PMU_WAKE_TRIGx_CLR

HVDD_DETHIF_UART_RXD

PMU_WAKE_TRIG_INTDETx

SEN_INTPMU_WAKE_TRIG_NOISECUTENx

from I/O

Instant HighInterrupt(to CPU/DSP)CXD5602 User Manual

Table General Purpose Input/Output (GPIO)-22 and Table General Purpose Input/Output (GPIO)-24 show
registers that select I/O pins, Table General Purpose Input/Output (GPIO)-23 and Table General Purpose
Input/Output (GPIO)-25 show selectable I/O pins. Initial value of a register is set as 63. In this case, no I/O pin is
selected and an input value to the circuit for detecting interrupts or events is tied to “0”.
As for the selected external interrupt I/O pin, the Input Enable needs to be valid by setting 1 on the register
IO_*.ENZI.
Table General Purpose Input/Output (GPIO)-22 IO Pin Selection (SYS Group)
Address

0x041007B00x041007B4

Register

Bit Field

Name

Name

IOCSYS_INTSEL0

ReservedRO[31:30]0Reserved

SEL3

RW[29:24]63

assigns an I/O pin to an external signal (SYSGPI3)

ReservedRO[23:22]0

Reserved

SEL2

RW[21:16]63

assigns an I/O pin to an external signal (SYSGPI2)

ReservedRO[15:14]0Reserved

SEL1

RW[13:8]

63

assigns an I/O pin to an external signal (SYSGPI1)

Reserved

RO

[7:6]

0

Reserved

SEL0

RW

[5:0]

63

assigns an I/O pin to an external signal (SYSGPI0)

ReservedRO[31:14]0Reserved

SEL5

RW[13:8]

63

assigns an I/O pin to an external signal (SYSGPI5)

Reserved

RO

[7:6]

0

Reserved

SEL4

RW

[5:0]

63

assigns an I/O pin to an external signal (SYSGPI4)IOCSYS_INTSEL1

Type

Bit

InitialDescription

Value－103/1293－

CXD5602 User Manual

Table General Purpose Input/Output (GPIO)-23 Correspondence of I/O Pins to Setting Values (SYS Group)
Selected

Pin

Setting

Selected

Name

Value

P10_00Pin

Setting

Selected

Name

Value

0

P16_00

P10_01

1

P11_00Pin

Setting

Selected

Pin

Setting

Name

Value

Name

Value

16

－

32

P1l_01

48

P16_01

17

－

33

－

49

2

P17_00

18

－

34

－

50

P12_00

3

P17_01

19

－

35

－

51

P13_00

4

P18_0020

P1e_00

36－

52

P14_00

5

P18_0121

P1f_00

37

－

53

－

6

P18_0222

P1g_00

38

－

54

－

7

P18_0323

P1h_00

39

－

55

－

8

P19_0024

P1i_00

40

－

56

－

9

P19_0125

P1i_01

41

－

57

－

10

P00_0026

P1i_02

42

－

58

－

11

P00_0127

P1j_00

43

－

59

－

12

P01_0028

P1j_01

44

－

60

－

13

P01_0129

P1k_00

45

－

61

－

14

P02_0030

P1k_01

46

－

62

－

15

P03_0031

P1l_0047－(default)

63

Table General Purpose Input/Output (GPIO)-24 I/O Pin Selection (APP Group)
Address

0x04101490

0x04101494

Register

Bit Field

Name

Name

IOCAPP_INTSEL0

ReservedRO[31:30]0Reserved

SEL3

RW[29:24]63

assigns an I/O pin to an external signal (APPGPI3)

ReservedRO[23:22]0

Reserved

SEL2

RW[21:16]63

assigns an I/O pin to an external signal (APPGPI2)

ReservedRO[15:14]0Reserved

SEL1

RW[13:8]

63

assigns an I/O pin to an external signal (APPGPI1)

Reserved

RO

[7:6]

0

Reserved

SEL0

RW

[5:0]

63

assigns an I/O pin to an external signal (APPGPI0)

ReservedRO[31:14]0Reserved

SEL5

RW[13:8]

63

assigns an I/O pin to an external signal (APPGPI5)

Reserved

RO

[7:6]

0

Reserved

SEL4

RW

[5:0]

63

assigns an I/O pin to an external signal (APPGPI4)

IOCAPP_INTSEL1

Type

Bit

InitialDescription

Value－104/1293－

CXD5602 User Manual

Table General Purpose Input/Output (GPIO)-25 Correspondence of I/O Pins to Setting Values (APP Group)
Selected

Pin

Setting

Selected

Name

Value

P1m_00Pin

Setting

Selected

Name

Value

0

P1o_01P1m_01

1

P1m_02

Setting

Selected

Name

Value

Name

Value

16

P1s_0132

P1y_0248

P1o_02

17

P1t_0033

P1z_0049

2

P1o_0318

P1t_0134－

50

P1m_03

3

P1p_00

19

P1t_0235－

51

P1m_04

4

P1p_0120

P1u_0036－52

P1m_05

5

P1p_0221

P1v_0037－53

P1m_06

6

P1p_0322

P1v_0138－

54

P1m_07

7

P1q_0023

P1v_0239－

55

P1m_088

P1q_0124

P1v_0340－

56

P1m_099

P1r_0025

P1w_0041－

57

P1m_10

10

P1r_0126

P1w_01

42－

58

P1n_00

11

P1r_0227

P1w_0243－

59

P1n_0112

P1r_0328

P1w_0344－

60

P1n_0213

P1r_0429

P1x_0045－

61

P1n_03

14

P1r_0530

P1y_0046－

62

P1o_0015

P1s_0031

P1y_0147－(default)

63－105/1293－

Pin

Pin

SettingCXD5602 User Manual

3.2.4.3 External Interrupt
Selected I/O pins described in the section 3.2.4.2 and some other pins (refer to Table General Purpose
Input/Output (GPIO)-27) can be communicated to SYSCPU and DSP as external interrupts with no changes.
Besides, not only I/O pins’ values themselves can be communicated to SYSCPU and DSP, but information that an
event has been detected (refer to 3.2.4.4) can be as well.
Figure General Purpose Input/Output (GPIO)-20 shows the function in the Event Detect Block, which is explainedin this section.
Output Selection

0: The value of the I/O pin is communicated as an interrupt signal with no changes.



1: The inverted value of the I/O pin is communicated as an interrupt signal.



2: The result of the event detection is communicated as an interrupt signal with no changes.



3: When an event is detected, the register is asserted and communicated as a latched interrupt signal.



4-7: The output value is tied to “0”.

Event Detect

CRG
SCU

4

RTC0

4

Wakeup factor(to PMU)GNSSInternal signal detection

SYSIOP_SUB

0
14HI F_DETECT_I2C_SLAVE

14
Pos edge

Pulse

20

S et
C lr

1

INT_PMIC_I2CM

PMU

16

External signal detection
20

External
signal select064 to 1......

Chattering removal

1

USB_VBUS

Pulse

Instant Low

Pulse

Level HighLevel

Level Low

Level

Pos edge

Pulse

Neg edge

Pulse

Pos/Neg edge

Pulse

or

PMIC_INT

001

EXDEVICE[11:0]
USBVBUSUSBVBUSN
HVDD
PMIC_INT

0
1
2
3
4

2
3

S et
C lr

4
5
6

PMU_WAKE_TRIGx

PMU_WAKE_TRIG_ENx
PMU_WAKE_TRIGx_RAW

PMU_WAKE_TRIG_CPUINTSELx

HIF_SPI_CS_X
HIF_SCL_LOW

PMU_WAKE_TRIGx_CLR

HVDD_DETHIF_UART_RXD

PMU_WAKE_TRIG_INTDETx

SEN_INTPMU_WAKE_TRIG_NOISECUTENx

from I/O

Instant High

Figure General Purpose Input/Output (GPIO)-20 External Interrupt Selection－106/1293－

Interrupt(to CPU/DSP)CXD5602 User Manual

Table General Purpose Input/Output (GPIO)-26 shows control registers for processing external interrupt signals.
Table General Purpose Input/Output (GPIO)-26 External Interrupt Selection
Address

0x04100468

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

PMU_WAKE_TRIG_

Reserved

RO

[31]

0

Reserved

CPUINTSEL0SYSGPI3

RW[30:28]0Interrupt options for outputting to

Value

SYSCPU and DSP
0: value of I/O pin
1: inverted value of I/O pin
2: result of the event detection
3: If the status is changed to “event
not detected”, the former status “event
detected” is latched.
4-7: The output value is tied to “0”.
Reserved

RO

[27]

0

Reserved

SYSGPI2

RW[26:24]0Refer to SYSGPI3

Reserved

RO

[23]

0

Reserved

SYSGPI1

RW[22:20]0Refer to SYSGPI3

Reserved

RO

[19]

0

Reserved

SYSGPI0

RW[18:16]0Refer to SYSGPI3

Reserved

RO

[15]

0

Reserved

HVDD_DET

RW[14:12]0Refer to SYSGPI3

Reserved

RO

[11]

0

Reserved

HIF_UART_R

RW[10:8]

0

Refer to SYSGPI3

Reserved

RO

[7]

0

Reserved

HIF_SPI_CS_X

RW

[6:4]

0

Refer to SYSGPI3

Reserved

RO

[3]

0

Reserved

HIF_SCL_LO

RW

[2:0]

0

Refer to SYSGPI3

XD

W
0x0410046C

PMU_WAKE_TRIG_

Reserved

RO

[31]

0

Reserved

CPUINTSEL1

APPGPI5

RW[30:28]0Refer to SYSGPI3

Reserved

RO

[27]

0

Reserved

APPGPI4

RW[26:24]0Refer to SYSGPI3

Reserved

RO

[23]

0

Reserved

APPGPI3

RW[22:20]0Refer to SYSGPI3

Reserved

RO

[19]

0

Reserved－107/1293－

CXD5602 User Manual

0x04100470

APPGPI2

RW[18:16]0Refer to SYSGPI3

Reserved

RO

[15]

0

Reserved

APPGPI1

RW[14:12]0Refer to SYSGPI3

Reserved

RO

[11]

0

Reserved

APPGPI0

RW[10:8]

0

Refer to SYSGPI3

Reserved

RO

[7]

0

Reserved

SYSGPI5

RW

[6:4]

0

Refer to SYSGPI3

Reserved

RO

[3]

0

Reserved

SYSGPI4

RW

[2:0]

0

Refer to SYSGPI3

PMU_WAKE_TRIG_

ReservedRO[31:15]0Reserved

CPUINTSEL2

USB_VBUS

RW[14:12]0Refer to SYSGPI3

Reserved

RO

[11]

0

Reserved

USB_VBUS_X

RW[10:8]

0

Refer to SYSGPI3

Reserved

RO

[7]

0

Reserved

PMIC_INT

RW

[6:4]

0

Refer to SYSGPI3

Reserved

RO

[3]

0

Reserved

SEN_INT

RW

[2:0]

0

Refer to SYSGPI3－108/1293－

CXD5602 User Manual

3.2.4.4 Event Detection Control
Event detection asserts when it detects that a signal meets conditions set for detection. It keeps the status until thecontrol register clears the status. Event Detection Control can perform edge detection, level detection, and instantdetection of external signals from I/O pins. Detected events can be used as interrupts.
Figure General Purpose Input/Output (GPIO)-21 shows the function in the Event Detect Block, which is explainedin this section.

Event Detect

CRG
SCU

4

RTC0

4

Wakeup factor(to PMU)GNSSInternal signal detection

SYSIOP_SUB

0
14HI F_DETECT_I2C_SLAVE

14
Pos edge

Pulse

20

S et
C lr

1

INT_PMIC_I2CM

PMU

16

External signal detection
20

External
signal select064 to 1......

Chattering removal

1

USB_VBUS

Pulse

Instant Low

Pulse

Level HighLevel

Level Low

Level

Pos edge

Pulse

Neg edge

Pulse

Pos/Neg edge

Pulse

or

PMIC_INT

001

EXDEVICE[11:0]
USBVBUSUSBVBUSN
HVDD
PMIC_INT

0
1
2
3
4

2
3

S et
C lr

4
5
6

PMU_WAKE_TRIGx

PMU_WAKE_TRIG_ENx
PMU_WAKE_TRIGx_RAW

PMU_WAKE_TRIG_CPUINTSELx

HIF_SPI_CS_X
HIF_SCL_LOW

PMU_WAKE_TRIGx_CLR

HVDD_DETHIF_UART_RXD

PMU_WAKE_TRIG_INTDETx

SEN_INTPMU_WAKE_TRIG_NOISECUTENx

from I/O

Instant High

Figure General Purpose Input/Output (GPIO)-21 Event Detection Control－109/1293－

Interrupt(to CPU/DSP)CXD5602 User Manual

Table General Purpose Input/Output (GPIO)-27 shows I/O pins that can be used for event detection. As for I/O
pins that can be used for interrupt (refer to 3.2.4.2), bit-field names of interrupt factor registers are described in the“Interrupt Factor” field of the table. For interrupt factors, refer to Chapter 3.3 (interrupt).
Table General Purpose Input/Output (GPIO)-27 I/O Pins That Can be Used for Event Detection
Pin Name

Bit Field Name of Event
Detection Register

P1z_00

USB_VBUS

I/O Pin Description

Interrupt Factor

detects connection or disconnection of USB (in positive

USBVBUS（1*）

logic)
Both positive and negative logics are prepared to detect bothconnection and disconnection of USB.
P1z_00

USB_VBUS_X

detects connection or disconnection of USB (in negative

USBVBUSN

logic)
P11_00

PMIC_INT

detects interrupts that are output from CXD5247

PMIC_INT

basically connects alarm interrupts of CXD5247
P1e_00

SEN_INT

detects interrupts (SEN_IRQ_IN) that are output from-sensors
Interrupts from external sensor devices connected to SCU are
assumed.
refer

to

APPGPI5

I/O pin selected by IOCAPP_INTSEL1.SEL5

EXDEVICE[11]Table

APPGPI4

I/O pin selected by IOCAPP_INTSEL1.SEL4

EXDEVICE[10]GeneralAPPGPI3

I/O pin selected by IOCAPP_INTSEL0.SEL3

EXDEVICE[9]PurposeAPPGPI2

I/O pin selected by IOCAPP_INTSEL0.SEL2

EXDEVICE[8]Input/Out

APPGPI1

I/O pin selected by IOCAPP_INTSEL0.SEL1

EXDEVICE[7]put

APPGPI0

I/O pin selected by IOCAPP_INTSEL0.SEL0

EXDEVICE[6]SYSGPI5

I/O pin selected by IOCSYS_INTSEL1.SEL5

EXDEVICE[5]Table

SYSGPI4

I/O pin selected by IOCSYS_INTSEL1.SEL4

EXDEVICE[4]GeneralSYSGPI3

I/O pin selected by IOCSYS_INTSEL0.SEL3

EXDEVICE[3]PurposeSYSGPI2

I/O pin selected by IOCSYS_INTSEL0.SEL2

EXDEVICE[2]Input/Out

SYSGPI1

I/O pin selected by IOCSYS_INTSEL0.SEL1

EXDEVICE[1]put

SYSGPI0

I/O pin selected by IOCSYS_INTSEL0.SEL1

EXDEVICE[0]-HVDD_DET

detects status change of IO power supply of HOST I/F

HVDD

P00_01

HIF_UART_RXD

detects UART0_RXD = L-(GPIO)-2
5
refer

to

(GPIO)-2
3－110/1293－

CXD5602 User Manual

detects UART communication from external HOST devices
when HOST I/F is UART
P00_00

HIF_SPI_CS_X

detects SPI2_CS_X = L-

detects SPI communications from external HOST when
HOST I/F is SPI
P00_00

HIF_SCL_LOW

detects I2C3_BCK = L-

detects I2C communications from external HOST devices
when HOST I/F is I2C（1*）

Applicable Registers

PMU_WAKE_TRIG_NOISECUTEN0

PMU_WAKE_TRIG_INTDET0

PMU_WAKE_TRIG_INTDET1

PMU_WAKE_TRIG_INTDET2

PMU_WAKE_TRIG_EN0



PMU_WAKE_TRIG0_RAW



PMU_WAKE_TRIG0

PMU_WAKE_TRIG0_CLR

3.2.4.4.1

How to Detect Events (External Signal)

There are seven ways of detecting events by an external signal from I/O pin. You can select one from them byusing a register for each I/O pin.
Selection of the way of detecting events (PMU_WAKE_TRIG_INTDET*)(0) Instant High Detection(1) Instant Low Detection(2) Level High Detection(3) Level Low Detection(4) Rising Edge Detection(5) Falling Edge Detection(6) Both Edge Detection(7) Both Edge Detection (This function removes information of event detection that is made when CXD5602 is
reset and then the reset is released while the status of the I/O pin is High. That is because the input value of the
I/O pin is not actually changed.)
When you select (6), right after the reset is released when the status of the I/O pin is High, an event is detected.
If you want to eliminate this determination, use (7).
When you select (2) to (7), if you set debounce function (PMU_WAKE_TRIG_NOISECUTEN0) as effective,
you can remove signal changes of two cycles of RTC Clock or less.

－111/1293－

CXD5602 User Manual

Figure General Purpose Input/Output (GPIO)-22 shows event detection timings of (0) to (5) of the above sevenways.
RTC Clock
External Signal(0) Instant High(1) Instant Low
Always Event det ect(2) Level High
(3) Level Low(4) Pos edge(5) Neg edge
(2) Level High(Noise Cut)
(3) Level Low(Noise Cut)
(4) Pos edge(Noise Cut)
(5) Neg edge(Noise Cut)

Two consecutive samplingof External Signal

Event detect
Sampling

Figure General Purpose Input/Output (GPIO)-22 Event Detection Timing Diagram
Table General Purpose Input/Output (GPIO)-28 shows registers for setting Event Detection of I/O pins.
Table General Purpose Input/Output (GPIO)-28 Event Detection Setting for I/O Pins
Address

0x04100464

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

PMU_WAKE_TRIG_

USB_VBUS

RW

[31]

0

Debounce

NOISECUTEN0

USB_VBUS_X

RW

[30]

0

1: eliminates noise

PMIC_INT

RW

[29]

0

0: does not eliminate noise

SEN_INT

RW

[28]

0

APPGPI5

RW

[27]

0

APPGPI4

RW

[26]

0

APPGPI3

RW

[25]

0

APPGPI2

RW

[24]

0

APPGPI1

RW

[23]

0

APPGPI0

RW

[22]

0

SYSGPI5

RW

[21]

0

SYSGPI4

RW

[20]

0

Value

－112/1293－

CXD5602 User Manual

0x04100474

SYSGPI3

RW

[19]

0

SYSGPI2

RW

[18]

0

SYSGPI1

RW

[17]

0

SYSGPI0

RW

[16]

0

HVDD_DET

RW

[15]

0

HIF_UART_RXD

RW

[14]

0

HIF_SPI_CS_X

RW

[13]

0

HIF_SCL_LOW

RW

[12]

0

ReservedRO[11:0]

0Reserved

PMU_WAKE_TRIG_

Reserved

RO

[31]

0

Reserved

INTDET0

SYSGPI3

RW[30:28]0

Selection of the way of detecting
events0: Instant H,
1: Instant L,
2: Level H,
3: Level L,
4: Rising edge,
5: Falling edge,
6: Both Edges,
7:

Both

Edges

(removes

response at the start-up)

0x04100478

Reserved

RO

[27]

0

Reserved

SYSGPI2

RW[26:24]0refer to SYSGPI3

Reserved

RO

[23]

0

Reserved

SYSGPI1

RW[22:20]0refer to SYSGPI3

Reserved

RO

[19]

0

Reserved

SYSGPI0

RW[18:16]0refer to SYSGPI3

Reserved

RO

[15]

0

Reserved

HVDD_DET

RW[14:12]0refer to SYSGPI3

Reserved

RO

[11]

0

Reserved

HIF_UART_RXD

RW[10:8]

0refer to SYSGPI3

Reserved

RO

[7]

0

Reserved

HIF_SPI_CS_X

RW

[6:4]

0

refer to SYSGPI3

Reserved

RO

[3]

0

Reserved

HIF_SCL_LOW

RW

[2:0]

0

refer to SYSGPI3

PMU_WAKE_TRIG_

Reserved

RW

[31]

0

Reserved

INTDET1

APPGPI5

RW[30:28]0refer to SYSGPI3

Reserved

RO

[27]

0

Reserved－113/1293－

theCXD5602 User Manual

0x0410047C

APPGPI4

RW[26:24]0refer to SYSGPI3

Reserved

RO

[23]

0

Reserved

APPGPI3

RW[22:20]0refer to SYSGPI3

Reserved

RO

[19]

0

Reserved

APPGPI2

RW[18:16]0refer to SYSGPI3

Reserved

RO

[15]

0

Reserved

APPGPI1

RW[14:12]0refer to SYSGPI3

Reserved

RO

[11]

0

Reserved

APPGPI0

RW[10:8]

0refer to SYSGPI3

Reserved

RO

[7]

0

Reserved

SYSGPI5

RW

[6:4]

0

refer to SYSGPI3

Reserved

RO

[3]

0

Reserved

SYSGPI4

RW

[2:0]

0

refer to SYSGPI3

PMU_WAKE_TRIG_

ReservedRO[31:15]0Reserved

INTDET2

USB_VBUS

RW[14:12]0refer to SYSGPI3

Reserved

RO

[11]

0

Reserved

USB_VBUS_X

RW[10:8]

0refer to SYSGPI3

Reserved

RO

[7]

0

Reserved

PMIC_INT

RW

[6:4]

0

refer to SYSGPI3

Reserved

RO

[3]

0

Reserved

SEN_INT

RW

[2:0]

0

refer to SYSGPI3－114/1293－

CXD5602 User Manual

3.2.4.4.2

Status of Event Detection

When an event is detected, a status register for event detection becomes High and keeps the status even if theevent ends. Table General Purpose Input/Output (GPIO)-29 shows status registers for event detection.
Table General Purpose Input/Output (GPIO)-29 Status of Event Detection
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04103440

PMU_WAKE_TRIG0

USB_VBUS

RO

[31]

0

Status of Event Detection

USB_VBUS_X

RO

[30]

0

1: event is detected

PMIC_INT

RO

[29]

0

0: event is not detected

SEN_INT

RO

[28]

0

APPGPI5

RO

[27]

0

APPGPI4

RO

[26]

0

APPGPI3

RO

[25]

0

APPGPI2

RO

[24]

0

APPGPI1

RO

[23]

0

APPGPI0

RO

[22]

0

SYSGPI5

RO

[21]

0

SYSGPI4

RO

[20]

0

SYSGPI3

RO

[19]

0

SYSGPI2

RO

[18]

0

SYSGPI1

RO

[17]

0

SYSGPI0

RO

[16]

0

HVDD_DET

RO

[15]

0

HIF_UART_RXD

RO

[14]

0

HIF_SPI_CS_X

RO

[13]

0

HIF_SCL_LOW

RO

[12]

0

HIF_DETECT_I2C_SLAVE

RO

[11]

0

INT_SYSIOPSUB

RO

[10]

0

INT_GNSS

RO

[9]

0

PMU_RTCALMERR

RO

[8]

0

PMU_RTCALM2

RO

[7]

0

PMU_RTCALM1

RO

[6]

0

PMU_RTCALM0

RO

[5]

0

SCU_INT3

RO

[4]

0

SCU_INT2

RO

[3]

0

－115/1293－

CXD5602 User Manual

0x04103444

PMU_WAKE_TRIG1

SCU_INT1

RO

[2]

0

SCU_INT0

RO

[1]

0

CRG_INT

RO

[0]

0

ReservedRO[31:2]

0Reserved

INT_PMIC_I2CM

RO

[1]

0

Status of Event Detection

UNEXP_PMU

RO

[0]

0

1: event is detected
0: event is not detected

3.2.4.4.3

Clear of Event Detection

Held statuses of Event Detection can be cleared by registers. If you write “1” on the register, clearing process will
begin. When the process is completed, the value returns to “0” automatically. You need not write “0”.
Table General Purpose Input/Output (GPIO)-30 shows registers to clear the status of the Event Detections.
Table General Purpose Input/Output (GPIO)-30 Registers to Clear the Status of the Event Detections
Address

0x04103430

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

PMU_WAKE_TRIG0_CLR

USB_VBUS

RW

[31]

0

Held

USB_VBUS_X

RW

[30]

0

Event Detection can

PMIC_INT

RW

[29]

0

be

SEN_INT

RW

[28]

0

writing “1”.

APPGPI5

RW

[27]

0

APPGPI4

RW

[26]

0

APPGPI3

RW

[25]

0

APPGPI2

RW

[24]

0

APPGPI1

RW

[23]

0

APPGPI0

RW

[22]

0

SYSGPI5

RW

[21]

0

SYSGPI4

RW

[20]

0

SYSGPI3

RW

[19]

0

SYSGPI2

RW

[18]

0

SYSGPI1

RW

[17]

0

SYSGPI0

RW

[16]

0

HVDD_DET

RW

[15]

0

HIF_UART_RXD

RW

[14]

0

HIF_SPI_CS_X

RW

[13]

0

HIF_SCL_LOW

RW

[12]

0

HIF_DETECT_I2C_SLAVE

RW

[11]

0

Value

－116/1293－

statuses

clearedofbyCXD5602 User Manual

PMU_WAKE_TRIG1_CLR

0x04103434

INT_SYSIOPSUB

RW

[10]

0

INT_GNSS

RW

[9]

0

PMU_RTCALMERR

RW

[8]

0

PMU_RTCALM2

RW

[7]

0

PMU_RTCALM1

RW

[6]

0

PMU_RTCALM0

RW

[5]

0

SCU_INT3

RW

[4]

0

SCU_INT2

RW

[3]

0

SCU_INT1

RW

[2]

0

SCU_INT0

RW

[1]

0

CRG_INT

RW

[0]

0

ReservedRO[31:2]

0Reserved

INT_PMIC_I2CM

RW

[1]

0

The status can be

UNEXP_PMU

RW

[0]

0

cleared by writing“1”.

3.2.4.4.4

Flow of Controlling Event Detection when used as Interrupt

When you use the results of event detection as interrupts (refer to 3.2.4.4.1), for setting Event Detection andclearing the status register, follow the flow shown below. Figure General Purpose Input/Output (GPIO)-23 showsa connection diagram of event detection function and SYSCPU or DSP.
Intterupt detect
Event Detect

External
signal selectNoise Cut On/Off
064 to 1......

Chattering removal

1

USB_VBUS

Instant High

Pulse

Instant Low

Pulse

Level HighLevel

Level Low

Level

Pos edge

Pulse

Neg edge

Pulse

Pos/Neg edge

Pulse

or

PMIC_INT

0

0

1

0
1
2
3
4

Event detect latch

2
3

INT_IRQ0.*

20

CPU/DSPEXDEVICE[11:0]
USBVBUSUSBVBUSN
HVDD
PMIC_INT
INT_EN0.*

External signal detection

External signal

from I/O

16

Interrupt(to CPU/DSP)

Intterupt mask

S et
C lr

4

Event detect clear

5
6

PMU_WAKE_TRIGx

PMU_WAKE_TRIG_ENx
PMU_WAKE_TRIGx_RAW

PMU_WAKE_TRIG_CPUINTSELx

PMU_WAKE_TRIGx_CLR

HIF_SPI_CS_X
HIF_SCL_LOW

PMU_WAKE_TRIG_INTDETx

HIF_UART_RXD

PMU_WAKE_TRIG_NOISECUTENx

SEN_INTHVDD_DET

Figure General Purpose Input/Output (GPIO)-23 Connection Diagram of Event Detection and SYSCPU or DSP
Flow of Setting Event Detection
For example, the flow of setting Event Detection as an interrupt (EXDEVICE[0]) is described below. For masking－117/1293－

CXD5602 User Manualinterrupts INT_EN*, refer to 3.3.2 (Chapter of Interrupt).
1. Mask an interrupt.
INT_EN0.EXDEVICE[0] = 0
2. Set the Event Detection (Pin Multiplexer, I/O pin selection, and way of detecting events).
3. Clear status register of Event Detection (to avoid errors caused by the result of the previous event
detection).
PMU_WAKE_TRIG0_CLR.SYSGPI0 = 1
4. Wait for the completion of clearing the status register of Event Detection.
Confirm that PMU_WAKE_TRIG0_CLR.SYSGPI0 = 0.
5. Cancel interrupt masking.
INT_EN0.EXDEVICE = 1
Flow of Clearing Event Detection
For example, the flow of clearing an interrupt (EXDEVICE[0]) is described below.
1. Detect an event detection as an interrupt.
2. Mask an interrupt.
INT_EN0.EXDEVICE[0] = 0
3. Clear the status register of Event Detection.
PMU_WAKE_TRIG0_CLR.SYSGPI0 = 1
4. Wait for the completion of clearing the status register of Event Detection.
Confirm that PMU_WAKE_TRIG0_CLR.SYSGPI0 equals 0.
5. Cancel interrupt masking (only when you want to detect an interrupt again)
INT_EN0.EXDEVICE[0] = 1
Restriction on Clearing Events
Clearing process to clear a held event is performed when 1 is set on any bit of PMU_WAKE_TRIG0_CLR. You
cannot start a new clearing while the former one is still in process. That is, if you set 1 on other bit of
PMU_WAKE_TRIG0_CLR while the former clearing is still in process, you must wait for the new clearing until
the former one ends. However, if you set 1 on multiple bits at a time, multiple clearing processing can be
performed in parallel.
For example, if you set 1 on PMU_WAKE_TRIG0_CLR and then set 2 or 3 on it, clearing processing of
SCU_INT0 cannot start until clearing process of CRG_INT ends.
If you set 3 on PMU_WAKE_TRIG0_CLR, clearing processing of both CRG_INT and SCU_INT0 can be
performed in parallel.
Time Interval for a Signal to be Able to Detect an Event Again
Once a signal from I/O pin (external signal) is received to detect an event, the same one from I/O pin will ignore
further events until the detected event is cleared. Table General Purpose Input/Output (GPIO)-31 shows timeintervals from event detection to the next event detection through the flow of clearing the result of event detection.

－118/1293－

CXD5602 User Manual

Figure General Purpose Input/Output (GPIO)-24 shows the timing diagram.
(A) in the table means the time from when an external signal is asserted to when an event detection is held. The
time depends on debounce setting. (B) means the time from when the clearing of event detection is executed towhen the clearing is completed.
Table General Purpose Input/Output (GPIO)-31 Time Interval for a Signal to be Able to Detect an Event Again
(1*)

Way

of

detecting

Debounce

eventsPMU_WAKE_TRI

PMU_WAKE_TRI

G_INTDET*

G_NOISECUTEN(A) Time of Detecting an(B) Time of Clearing(A) + (B)

Event

Event Detection

Time Interval between Event(Cycle of RTC Clock)(Cycle of RTC Clock)

Detections again(Cycle of RTC Clock)

0
0,

1:

Instant

Don't care

2~3

7~8

10 ~ 11

0: No

2~3

7~8

10 ~ 11

1: Yes4~5

7~8

12 ~ 13(constantly without

Detection

elimination)
4 - 7: Edge Detection(1*) The time intervals in the table are those which are assumed when the following conditions are met.

After an interrupt is detected, SYSCPU or DSP instantly masks the interrupt and clears the event.



The clock frequency of one of SYSCPU or DSP that performs the processing described in the above
condition must be adequately higher than that of RTC Clock. This restriction does not apply to the otherthat does not perform the processing.

When you execute the clearing of the event detection of (B), no clearing of other event detection is inprocess.
(If you start a new clearing process when the former clearing of event detection is still in process, thelatter process must wait until the present process is completed. For this reason, the period of (B)extends.)－119/1293－

CXD5602 User Manual

RTC Clock

Event
Detectable

Event Undetectable(from event detect to event detect clear done)

Event
Detectable

External Signal
Event detect(A)2~3 Cycle(B)7~8 Cycle

Event detect latch
Intterupt
INT_IRQ0.*

Intterupt mask
INT_EN0.*

Event detect clear
PMU_WAKE_TRIG0_CLR.*CPU

PMU_WAKE_TRIG0_RAW

2.mask enable & 3.clear
1.intterupt detect

5.mask disable
4.wait clear

Figure General Purpose Input/Output (GPIO)-24 Time Interval for a Signal to be able to Detect an Event Again(PMU_WAKE_TRIG_NOISECUTEN0:0)－120/1293－

CXD5602 User Manual

3.3

Interrupt

3.3.1

Overview and Features

The LSI has individual interrupt controllers for the SYSIOP, GNSS, and APP.
The 128 bit interrupt factors are connected to the CPUs of each SYSIOP, GNSS, and APP.
Interrupt requests are divided into two main categories: one is internal interrupt generated from each CPU core or
Peripheral, and another is external interrupt from I/O.
As external interrupts, signals from I/O can be used without any change, and results of event detection by GPIO
can be used as well.

Interrupt factor(I/O, SYSIOP, GNSS, APP)

System and I/O Processor
semapho re

WDTINT
WDTRESWDTRESOUT

Cause3[31:16]
Cause3[15:14]
Cause3[13]Cause3[9:8]
Cause1[19:17]

NMI

Cause1[20]Cause1[21]Cause1[22]Cause1[23]Cause1[24]to 32bit

128

EN Reg

GNSS DSP

Cortex-M0+
PID0

MASK

FIFO
SW INT
DEBUG
TIMER
WDT

Interrupt input Register

32

IRQ

Interrupt input Register
Cause3[31:16]
Cause3[15:14]

WDTINT
WDTRES

Cause3[13]Cause3[9:8]
Cause1[19:17]

Cortex-M4
PID1

MASK

SW INT
DEBUG
TIMER
WDT

Cause1[20]Cause1[21]NMI

Cause1[4]128

EN RegApplication Processor

IRQ

Interrupt
input
RegisterInterrupt
input
RegisterInterrupt
inputInterrupt
inputRegister
RegisterInterrupt
Interruptinput
inputRegister
RegisterCause3[31:16]
Cause3[15:14]
Cause3[0]WDTINT
WDTRES

Cause2[13:12]
Cause3[3:1]

Cortex-M4
PIDn(n:2-7)

MASK

DEBUG
TIMER
WDT

Cause3[4]Cause3[5]NMI
EN RegFigure Interrupt-25 Interrupt Connection Diagram－121/1293－

128

IRQ

System Reset(to CRG)CXD5602 User Manual

Interrupt request from Wathdog Timer, WDTINT (bit[20]) is connected to IRQ of Processor 0, and reset signal
from Watchdog Timer, WDTRES (bit[21]) is connected to Non-Maskable Interrupt (NMI) of Processor 0 (PID0in Figure Interrupt-25).
WDTRES (bit[23]) of GNSS and WDTRES (bit[23]) of APP are ORed with WDTINT(bit[20]), and the result isprovided to NMI of Processor 0. In the meantime, WDTRESOUT (bit[22]) is not connected to IRQ or NMI ofProcessor 0, but connected to System Reset of CRG, therefore, System Reset can be performed regardless of thestatus of Processor 0.

3.3.2

Register Descriptions

3.3.2.1 Interrupt Registers of Application Processor
Table Interrupt-32 shows list of interrupt registers of Application Processor.
Table Interrupt-32 List of Interrupt Registers of Application Processor
Address

RegisterType

InitialDescription

0xE0045000

INT_CAUSE0

RO-Interrupt factor

0xE0045004

INT_CAUSE1

RO-

indicates the status of the interrupt

0xE0045008

INT_CAUSE2

RO-

The initial value of the register depends on that of connected block.

0xE004500C

INT_CAUSE3

RO-

0xE0045010

INT_EN0RW

0x00000000

Interrupt enable

0xE0045014

INT_EN1

RW

0x00000000

When bit value is “1”, interrupt is requested to processor (enabled),

0xE0045018

INT_EN2

RW

0x00000000

and when bit value is “0”, interrupt is not requested (disabled).

0xE004501C

INT_EN3

RW

0x00000000

0xE0045020

INT_INV0RW

0x00000000

Inverted polarity

0xE0045024

INT_INV1

RW

0x00000000

Writing “1” enables to invert the polarity of the interrupt of the

0xE0045028

INT_INV2

RW

0x00000000

corresponding bit.

0xE004502C

INT_INV3

RW

0x00000000

0xE0045030

INT_IRQ0RO

0x00000000

Interruption request

0xE0045034

INT_IRQ1

RO

0x00000000

means ANDed value between interrupt factor (INT_CAUSE) and

0xE0045038

INT_IRQ2

RO

0x00000000

interrupt enable (INT_EN), and indicates the status of signal

0xE004503C

INT_IRQ3

RO

0x00000000

actually provided to processor

Table Interrupt-33 Interrupt Factor Registers of Application Processor
Address

Register

Bit Field

Type

Bit

InitialDescription

0xE0045000

INT_CAUSE0EXDEVICE

RO[31:20]-Interrupt request from external device (fromGPIO)－122/1293－

CXD5602 User Manual

SCU

RO

[19:16]-

Interrupt request from SCU

HOSTIFCRO[15:13]-

Interrupt request from Host I/F

UART

RO

[12]

-

Interrupt request from UART0

UARTDBG

RO

[11]

-

Interrupt request from UART1

RTC_INT

RO

[10]

-

ORed value between the following:- Interrupt request from RTC1_Misc- Interrupt request from RTC0_Misc

RTC1A2

RO[9]-

Interrupt request from RTC1 OAlarm2

RTC1A1

RO[8]-

Interrupt request from RTC1 OAlarm0

RTC1A0RO[7]-

Interrupt request from RTC1 OAlarm0

RTC0A2

RO[6]-

Interrupt request from RTC0 OAlarm2

RTC0A1

RO[5]-

Interrupt request from RTC0 OAlarm1

RTC0A0RO[4]-Interrupt request from RTC0 OAlarm0

Reserved

RO

[3]

-

Reserved

HVDD

RO

[2]

-

Interrupt request from VDD_IO_HOST
status

CRG

RO

[1]

-

Interrupt request from CRG

PMU

RO

[0]

-

Interrupt request from PMU

0xE0045004

INT_CAUSE1

SDMAC

RO

[31:0]-

Interrupt request from SDMAC

0xE0045008

INT_CAUSE2

SPH

RO

[31:16]-

Interrupt request from semaphore regarding
communication between CPUs

FIFOFROM

RO

[15]

-

Interrupt request from receive FIFO
regarding communication between CPUs

FIFOTO

RO

[14]

-

Interrupt request from transmit FIFO
regarding communication between CPUs

DEBUG

RO

[13:12]-

Interrupt request from debug block (APP)I2CMCOM

RO

[11]

-

Interrupt request from I2C2SPIMCOM

RO

[10]

-

Interrupt request from SPI0USBVBUSN

RO

[9]

-

Inverted polarity of interrupt request fromexternal device (USB_VBUSINT)USBVBUS

RO

[8]

-

Interrupt

requestfromexternal(USB_VBUSINT)

0xE004500C

INT_CAUSE3

CRYPTO_CLEFIA

RO

[7:6]

-

Interrupt request from Crypto (Clefia)

SYSUBDMAC

RO

[5:4]

-

Interrupt request from SYSUBDMACSYDMAC

RO

[3:2]

-

Interrupt request from SYDMAC

HDMAC

RO

[1:0]

-

Interrupt request from HDMAC

PMIC_INT

RO

[31]

-

Interrupt request from external device(PMIC)－123/1293－

deviceCXD5602 User Manual

SFC

RO

[30]

-

Interrupt request from SPI Flash controller

GNSSOR

RO

[29]

-

ORed value of GNSS Receiver interrupts

Reserved

RO

[28]

-

Reserved

CRYPTO_AES_MS

RO[27:26]-

Interrupt request from Crypto (AES)BusMaster

T
CRYPTO_AES_CO

RO[25:24]-

Interrupt request from Crypto (AES) AES

ADMAC

RO

[23:22]-

Interrupt request from ADMACPERUSBRO[21:20]-Interrupt request from USB

PERSDIF

RO

[19]

-

Interrupt request from SDIOPEREMMC

RO

[18]

-

Interrupt request from eMMC

IMGSSP

RO

[17]

-

Interrupt request from SPI4IMGVSYNC

RO

[16]

-

Interrupt request from Imaging vsync

IMGUART

RO

[15]

-

Interrupt request from UART2IMGDMAC

RO

[14]

-

Interrupt request from IDMACIMGWSSP

RO

[13]

-

Interrupt request from SPI5IMGCIS

RO

[12]

-

Interrupt request from CIS I/F

IMGROT

RO

[11]

-

Interrupt request from Imaging rotation

IMG2D

RO

[10]

-

Interrupt request from 2D Graphics

AUDCODEC

RO

[9]

-

Interrupt request from AudioDSP

AUDI2S1

RO

[8]

-

Interrupt request from I2S1

AUDI2S0

RO

[7]

-

Interrupt request from I2S0

AUDMIC

RO[6]-

Interrupt request from PDM

WDTRES

RO[5]-

Interrupt request from Watchdog RES (APP)

WDTINT

RO[4]-

Interrupt request from Watchdog Timer

RE

(APP)
TIMER

RO

[3:1]

-

Interrupt request from TIMER (APP)

SWINT

RO

[0]

-

Software interrupt request (APP)－124/1293－

CXD5602 User Manual

3.4

PMU (Power Management Unit)

3.4.1

Features and Overview

The Power Management Unit (referred to as “PMU” hereinafter) is the block that performs overall power supply
control of the CXD5602.
The CXD5602 has a large power domain, which is divided into 11 domains. It performs ON control of necessary
power domains only, while performing OFF control of the unnecessary ones, thereby reducing the power
consumption.
The 11 power domains comprise a layer structure as shown in Figure PMU (Power Management Unit)-26. The
lower-layer power domains cannot be turned ON when the upper-layer power supplies are OFF. Furthermore,
PWD_GNSS can be turned ON only when both PWD_GNSS_ITP and PWD_SYSIOP are ON.

VDD_COREPMU

PWD_PMU

Always ON

PWD_SCU

Sensor
DomainPWD_SCU
Power switch

PWD_COREPWD_CORE
Power switch

PWD_SYSIOP_SUB

PWD_SYSIOP_SUB
Power switch

System and IOP
DomainPWD_SYSIOPPWD_SYSIOPPower switch

PWD_APPPWD_APPPower switch

PWD_APP_DSP

PWD_APP_DSP
Power switch

PWD_APP_SUB

PWD_APP_SUB
Power switch

PWD_APP_AUD

PWD_APP_AUD
Power switch

PWD_GNSS_ITP

PWD_GNSS_ITP
Power switch

PWD_GNSSPWD_GNSSPower switch

Figure PMU (Power Management Unit)-26 PMU and the Power Domain Layers－125/1293－

Application
DomainGNSS
DomainCXD5602 User Manual

3.4.1.1 Individual Power Supply Control within the Power Domains
The SRAM or analog circuits such as the ADC within the power domains enable individual power supply control.

－126/1293－

CXD5602 User Manual

VDD_COREPWD_PMU

SRAM (Backup SRAM
SRAM (Backup SRAM
RCOSC
XOSC
SYSPLLPWD_SCU

8 KB
SRAM (FIFO
SRAM (FIFO 32 KB
SRAM (Sequencer RAM
ADC (HPADCADC (LPADCPWD_CORE

SRAM (SYSIOP Tile
SRAM (〃SRAM (〃SRAM (〃SRAM (SYSIOP Tile
SRAM (SYSIOP Tile
SRAM (SYSIOP Tile
SRAM (GNSS DSP Tile
SRAM (〃SRAM (GNSS DSP Tile
SRAM (GNSS DSP Tile
SRAM (GNSS DSP Tile
SRAM (GNSS DSP Tile
SRAM (GNSS DSP Tile
SRAM (GNSS DSP Tile

PWD_SYSIOP_SUB
PWD_SYSIOP32KB )
32KB )

Always ON

)
)
)
)
)

#0
〃
〃
〃
#1
#2
#3
#0
〃
#1
#2
#3
#4,5
#6,7
#8,9

Sensor
Domain

8 KB)
8 KB)
16 KB)
32 KB)
64 KB)
64 KB)
64 KB)
16 KB)
48 KB)
64 KB)
64 KB)
64 KB)
128 KB)128 KB)128 KB)

SRAM (HOSTIFC 1KB
SRAM (HOSTIFC Sequencer RAM

PWD_APPSRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile
SRAM (Application Processor Tile

PWD_APP_DSP

System and IOP
Domain

)
)

#0
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
#11

128 KB)128 KB)128 KB)128 KB)128 KB)128 KB)128 KB)128 KB)128 KB)128 KB)128 KB)128 KB)

Application
DomainPWD_APP_SUB
PWD_APP_AUD
PWD_GNSS_ITP
PWD_GNSSSRAM (GNSS BB
SRAM (GNSS BB
SRAM (GNSS BB
SRAM (GNSS BB
SRAM (GNSS BB
SRAM (GNSS BB
RF
(LNA
RF
(MIX
RF
(IF
RF
(ADC
RF
(LO
RF
(PLL

#0
#1
#2
#3
#4
#5

)
)
)
)
)
)
)
)
)
)
)
)

GNSS
DomainFigure PMU (Power Management Unit)-27 Individual Power Supply Control within the Power Domains－127/1293－

CXD5602 User Manual

Using the PWD_APP of Figure PMU (Power Management Unit)-27 as an example, Figure PMU (PowerManagement Unit)-28 explains how individual power supply control is performed within the power domains. The
PWD_APP has a total of 1.5 Mbytes of SRAM as main memory for the Application Processor. It comprises 12
logic tiles in 128 Kbyte units, and each one can control the power supply individually. The power supply of themain memory’s upper layer is PWD_APP. When PWD_APP is ON, the main memory for the Application
Processor can be turned ON.

supply power toPWD_SYSIOPPWD_SYSIOPPWD_APPPMUPWD_APPPower switch
Application
Processor<Tile #0>

Supply Power to
SRAM Array

SRAM Array
Power switch
SRAM Peripheral
Power switch

Tile #0 (128KB)

SRAM

Array
Peripheral
Supply Power to
SRAM Peripheral

Tile #1 (128KB)

SRAM
Application
Processor<Tile #1>

for Application
Processor

SRAM Array
Power switch

for Application
Processor

Array
Peripheral

SRAM Peripheral
Power switch

Application
Processor
SRAM(total 1.5MB)

Tile #11 (128KB)

SRAM
Application
Processor<Tile #11>

SRAM Array
Power switch

for Application
Processor

Array
Peripheral

SRAM Peripheral
Power switch

Figure PMU (Power Management Unit)-28 Power Supply Control within the Power Domain (PWD_APP Main
Memory)There are three modes for power supply control of the SRAMs.


On mode

The power supply of the SRAM memory array and peripheral circuitry are ON, and R/W access to the
SRAM is possible.

Retention modeA mode in which only the power supply of the SRAM memory array is ON, and the power supply of theperipheral circuitry is turned OFF. In Retention mode, the SRAM cannot be accessed, but the data
within the SRAM is retained. By turning on (ON mode) the power supply of the peripheral circuitry of－128/1293－

CXD5602 User Manual

the SRAM once again, the data within the SRAM can be accessed. Retention mode enables reduction of
the leakage power and recovery of high speed of peripheral circuitry for SRAMs that are temporarily
not used.
ShutDown modeA mode that turns OFF both the power supplies of the SRAM memory array and peripheral circuitry.
This mode consumes less power than the Retention mode, but the data in the SRAM is not retained.

3.4.1.2 Power Supply States
The following describes the main power supply states.
Table PMU (Power Management Unit)-34 Power Supply States
Power supply states

Description

1

Power Off

Both the CXD5602 (referred to as “the LSI” hereinafter) and the CXD5247 are OFF.

2

Deep Sleep

The LSI is OFF and the CXD5247 is ON.
In this state, the RTC of the CXD5247 is counting, and time information can be obtained
from the CXD5247 after the LSI is started.

3

Reset

In this state, the LSI and CXD5247 are both ON, and the LSI is being reset.

4

NormalThe LSI and CXD5247 are both ON, and the System Control (PWD_SYSIOP) turns ON,
enabling power supply control of each Domain.

The state begins from “Power OFF,” and after the CXD5247 starts, power is supplied to the LSI and a reset isenabled, changing the state to “Reset.” After releasing the reset of the LSI, the System Control of the System and
IOP Domain is automatically started, and the state enters “Normal.” In the “Normal” state, the power supply
control of each feature’s Domain can be controlled. By issuing the Deep Sleep command to the CXD5247, thestate changes to “Deep Sleep.” When events of the CXD5247 occur, such as the timer or interrupts, the statechanges to “Reset” and then to “Normal.”－129/1293－

CXD5602 User ManualState: Power OFF
CXD5247OFF

CXD5602
OFF
System and Application GNSSIOP Domain Domain
DomainOFF
OFF
OFF(PMIC)

Sensor
DomainOFF

CXD5247ON

CXD5602
ON
System and Application GNSSIOP Domain Domain
DomainOFF
OFF
OFF(PMIC)

Sensor
DomainOFF

State: Normal(PMIC)CXD5602
ON
System and Application GNSSIOP Domain Domain
DomainON
OFF
OFF

Sensor
DomainOFF

State: Deep Sleep
CXD5247
ON(PMIC)(Transition to each state is possible.)

System and
IOP Domain
ON

State: ResetCXD5247
ON

State: Normal (Domain ON)

CXD5602
OFF
System and Application GNSSIOP Domain Domain
DomainOFF
OFF
OFF

Sensor
DomainOFF

CXD5602
ON

Application
Domain ON

CXD5602
ON

System and
IOP Domain
ON

Application
Domain OFF

System and
IOP Domain
ON

Application
Domain ON

System and
IOP Domain
ON

Application
Domain OFF

System and
IOP Domain
ON

GNSS
Domain OFF

GNSS
Domain ON

CXD5602
ON

GNSS
Domain ON

CXD5602
ON

GNSS
Domain OFF

CXD5602
ON

Application
Domain ON

GNSS
Domain OFF

CXD5602
ON

System and
IOP Domain
ON

Application
Domain OFF

System and
IOP Domain
ON

Application
Domain ON

GNSS
Domain ON

CXD5602
ON

GNSS
Domain ON

Sensor
Domain OFF

Sensor
Domain OFF

Sensor
Domain OFF

Sensor
Domain ON

Sensor
Domain ON

Sensor
Domain ON

Sensor
Domain ON

Figure PMU (Power Management Unit)-29 Changes of Power Supply States
Details of the Power Supply Settings of the Power Supply States
The following table shows the relation between “Reset” states of the power supply, and the setting of the power
supply immediately after the state changes from “Reset” to “Normal” state.
Table PMU (Power Management Unit)-35 The Setting of the Power Supply in “Reset” State and After Changing
to “Normal” State
Domain namePower name“Reset” state

Immediately

after

changing from “Reset” to“Normal” state
Always ON

Sensor Domain

PWD_PMU

ON

ON

SRAM (Backup SRAM 32 KByte)

ON

ON

SRAM (Backup SRAM 32 KByte)

ON

ON

RCOSC

ON

ON

XOSC

OFF

OFF

SYSPLLOFF

OFF

PWD_SCU

OFF

OFF

SRAM (FIFO 32 KByte)

OFF

OFF

SRAM (FIFO 8 KByte)

OFF

OFF

SRAM (Sequencer RAM)

OFF

OFF

－130/1293－

CXD5602 User Manual

System and IOP
DomainApplication
DomainADC (HPADC)

OFF

OFF

ADC (LPADC)

OFF

OFF

OFF

ON

SRAM (SYSIOP Tile #0 8 KByte)

OFF

ON

SRAM (SYSIOP Tile #0 8 KByte)

OFF

ON

SRAM (SYSIOP Tile #0 16 KByte)

OFF

ON

SRAM (SYSIOP Tile #0 32 KByte)

OFF

ON

SRAM (SYSIOP Tile #1 64 KByte)

OFF

ON

SRAM (SYSIOP Tile #2 64 KByte)

OFF

ON

SRAM (SYSIOP Tile #3 64 KByte)

OFF

ON

SRAM (GNSS DSP Tile #0 16 KByte)

OFF

ON

SRAM (GNSS DSP Tile #0 48 KByte)

OFF

ON

SRAM (GNSS DSP Tile #1 64 KByte)

OFF

ON

SRAM (GNSS DSP Tile #2 64 KByte)

OFF

ON

SRAM (GNSS DSP Tile #3 64 KByte)

OFF

ON

SRAM (GNSS DSP Tile #4,5 128 KByte)

OFF

ON

SRAM (GNSS DSP Tile #6,7 128 KByte)

OFF

ON

SRAM (GNSS DSP Tile #8,9 128 KByte)

OFF

ON

PWD_SYSIOP_SUB

OFF

ON

PWD_SYSIOP

OFF

ON

SRAM (HOSTIFC 1KByte)

OFF

ON

SRAM (HOSTIFC Sequencer RAM)

OFF

ON

OFF

OFF

SRAM (Application Processor Tile #0 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #1 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #2 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #3 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #4 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #5 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #6 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #7 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #8 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #9 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #10 128 KByte)

OFF

OFF

SRAM (Application Processor Tile #11 128 KByte)

OFF

OFF

PWD_APP_DSP

OFF

OFF

PWD_APP_SUB

OFF

OFF

PWD_APP_AUD

OFF

OFF

PWD_COREPWD_APP－131/1293－

CXD5602 User Manual

GNSS Domain

PWD_GNSS_ITP

OFF

OFF

PWD_GNSS

OFF

OFF

SRAM (GNSS BB#0)

OFF

OFF

SRAM (GNSS BB#1)

OFF

OFF

SRAM (GNSS BB#2)

OFF

OFF

SRAM (GNSS BB#3)

OFF

OFF

SRAM (GNSS BB#4)

OFF

OFF

SRAM (GNSS BB#5)

OFF

OFF

RF (LNA)OFF

OFF

RF (MIX)OFF

OFF

RF (IF)OFF

OFF

RF (ADC)OFF

OFF

RF (LO)OFFOFF

RF (PLL)

OFF

OFF

3.4.1.3 Block Diagram
Figure PMU (Power Management Unit)-30 shows the block diagram of the PMU, which is mainly comprised ofthree blocks.


AHB IF
This is the control register of the PMU. After setting the power supply control of the power domain,
analog circuit, and SRAM, setting the power supply control request PMU_PW_CTL starts the power
supply control. The status of the power switch can be confirmed by reading the control register.



Check Register Value
In response to the power supply control request, this checks whether or not there are errors in the power
supply control register settings (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL). Power supply
control is executed only when the register settings are correct, and not performed when they areincorrect. For example, when a power supply of the upper layer (PWD_APP) is OFF, and a power
supply of the lower layer (PWD_APP_DSP) receives a setting request to turn it ON, this is judged as anincorrect setting and power supply control is not performed.

Power Control Sequencer
This sequencer identifies the upper and lower layers of the power supply and automatically controls theorder of the power supply switch control. When the power supply is controlled from OFF to ON, theoperation begins from the power supply in the upper layer. Conversely, when the power supply iscontrolled from ON to OFF, the operation begins from the power supply in the lower layer. In this way,using only 1 power supply control request, power supply control of the power supply in the upper layer(PWD_APP) and power supply control of the power supply in the lower layer (PWD_APP_DSP) can bedone together. For example, when issuing a power supply control request to turn ON both the upper－132/1293－

CXD5602 User Manual

layer and lower layer, the Power Control Sequencer first turns ON the power supply of the upper layer(PWD_APP) and then turns ON the power supply of the lower layer (PWD_APP_DSP). The CPU canrecognize the completion of power supply control by the interrupt.

Turn ON from upper power supply(PWD_SYSIOP first)

AHB IFPWD_CTL
Power supply*_RAMMODE_SEL
setting
ANA_PW_CTL

CheckRegister Value
CheckPower Control Sequencer
OFF→ONPower control
requestPMU_PW_CTL

Correct?

Yes

No
PSW_CHECKCheck result details

PWD_SYSIOPPWD_SYSIOPPower switch

OFF

ON

ON

OFF

PWD_CORE

ON→OFFOFF ON

OFF

supply power toPWD_COREOFFOFF

PWD_APPPWD_APPPower switch

PWD_APP_DSP

PWD_APP_DSP
Power switch

PowerControl
Start

PowerControl
Done

Turn OFF from lower power supply(PWD_APP_DSP first)

PWD_CTL_STAT*_RAMMODE_SEL_STAT
ANA_PW_CTL_STAT
PMU_INT_MASK.NOGO_CTRL

INT

to NVICPMU_INT_MASK.DONE

Figure PMU (Power Management Unit)-30 Overall Block Diagram of the PMU

3.4.1.4 Clock and Reset
Clock
Figure PMU (Power Management Unit)-31 shows a system diagram of the PMU’s clock.


AHB IF
Operates using the ck_ahb_gear clock which is synchronized with the System and I/O Processor.

Check Register Value, Power Control Sequencer
Operates using the RCOSC or RTC_CLK_IN. When power is supplied, the RCOSC turns ON and theinitial value of the control register (RORTC_STAT_CLK_SEL2) selects RCOSC as the operation clock of
the PMU. Before turning OFF the power switch of the RCOSC, make sure to switch the operation clockof the PMU to the RTC_CLK_IN.

－133/1293－

CXD5602 User Manual

Supply Power to
RCOSC
Initial Value: ON

PMU
ck_ahb_gear

RCOSC

0

Divider
1/250

AHB IFPMU Clock

Check
Register
Value

Power
ControlSequencer

1
0

RTC Clo ck

1

RTC_CLK_IN(32.768kHz)CKSEL_ROOT.PMU_STAT_CLK_SEL4[1]CKSEL_ROOT.RORTC_STAT_CLK_SEL2

Initial Value: 0

Figure PMU (Power Management Unit)-31 PMU Clock System
Reset
The PMU is reset by full reset of the CXD5602 (external reset (RST_X) or RCOSC POR or WDT reset), byautomatic release. Reset cannot be applied to the PMU alone.

－134/1293－

CXD5602 User Manual

3.4.2

Register List

Table PMU (Power Management Unit)-36 shows a list of registers related to each feature of the PMU.
Table PMU (Power Management Unit)-36 PMU Register List
Address

Register NameType

Description

Initial Value

0x04100000

PWD_CTL

RWPower supply control setting (Power domain)

0x00000000

0x04100004

ANA_PW_CTL

RWPower supply control setting (Analog circuit)

0x00000001

0x04100008

ANA_EN_CTL

RW

XOSC control setting

0x0F1901F7

0x04100010

SYSCPU_RAMMODE_SEL

RWPower supply control setting

0x00003FFF(SRAM for System and I/O Processor)
0x04100014

ReservedRO

Reserved

0x00000000

0x04100018

TOP_SCU_RAMMODE_SEL

RWPower supply control setting (SRAM for SCU)

0x000F0000

0x0410001C

HOSTIFC_RAMMODE_SEL

RWPower supply control setting (SRAM for HOSTIFC)

0x0000000F

0x04100020

Reserved

RW

Reserved-

0x04100030

PMU_PW_CTL

WOPower supply control request

0x00000000

0x04100040

PMU_INT_STAT

ROInterrupt status

0x00000000

0x04100044

PMU_RAW_INT_STAT

RO

Pre-masked interrupt status

0x00000000

0x04100048

PMU_INT_CLR

WOInterrupt clear

0x00000000

0x0410004C

PMU_INT_MASKRWInterrupt mask

0x00000F10

0x04100070

Reserved

RW

Reserved-

0x04100200

PWD_STATROPower supply status (Power domain)

0x00000000

0x04100204

ReservedRO

Reserved

0x00000000

0x04100208

ANA_PW_STAT

RO

Power supply status (Analog circuit)

0x00000000

0x0410020C

SYSCPU_RAMMODE_STAT

RO

Power supply status

0x00003FFF|
0x0410002C|
0x04100104(SRAM for System and I/O Processor)
0x04100214

TOP_SCU_RAMMODE_STAT

RO

Power supply status (SRAM for SCU)

0x00000F00

0x04100218

HOSTIFC_RAMMODE_STAT

RO

Power supply status (SRAM for HOSTIFC)

0x00000000

0x0410021C

PMU_HW_STAT

RO

Power supply control status

0x3F3F0000

0x04100400

ReservedRO

Reserved-

GNSSDSP_RAMMODE_SEL

RWPower supply setting (SRAM for GNSS DSP)

0x0000FFFF|
0x04100450
0x04100C00－135/1293－

CXD5602 User Manual

0x04100C40

GNSSDSP_RAMMODE_STAT

RO

Power supply status (SRAM for GNSS DSP)

0x0000FFFF

0x04103000

PSW_CHECKROPower supply setting check

0x00000000

0x04103004

Reserved

RW

Reserved-

0x04103C00

GNSS_RAMMODE_SEL

RWPower supply setting (SRAM for GNSS)

0x00000000

0x04103C30

GNSS_RAMMODE_STAT

RO

Power supply status (SRAM for GNSS)

0x00000000

0x04104400

APPDSP_RAMMODE_SEL0

RWPower supply setting

0x00000000|
0x04103034(SRAM0 for Application Processor)
0x04104404

APPDSP_RAMMODE_SEL1

RWPower supply setting

0x00000000(SRAM1 for Application Processor)
0x04104420

APPDSP_RAMMODE_STAT0

RO

Power supply status

0x00000000(SRAM0 for Application Processor)
0x04104424

APPDSP_RAMMODE_STAT1

ROPower supply status(SRAM1 for Application Processor)－136/1293－

0x00000000

CXD5602 User Manual

3.4.3

Register Descriptions

3.4.3.1 Register Settings
Within the power supply control register (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL), there is a Write
Enable for each power supply. Power supply control is enabled only for power supplies with Write Enable set to“1”, allowing the control of the desired power supply without performing read-modify-write.
When making the settings for power supply control, make sure to use Word access to simultaneously performwrite operations to the bits of Write Enable and each power supply’s setting (ON/OFF). Do not use Byte or half
word access.

3.4.3.2 Power Supply Control (Power Domain)
Table PMU (Power Management Unit)-37 and Table PMU (Power Management Unit)-38 show the registers
related to power supply control of the power domains. For the control method, refer to the control flow describedin Section 3.4.4.1.
Table PMU (Power Management Unit)-37 Power Supply Control Settings (Power Domain)
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100000

PWD_CTL

WEN

RO

[31]

0

Reserved

WO

[30]

0

Write Enable (PWD_APP_AUD)

WO

[29]

0

Write Enable (PWD_GNSS)

WO

[28]

0

Write Enable (PWD_GNSS_ITP)

RO

[27]

0

Reserved

WO

[26]

0

Write Enable (PWD_APP_SUB)

WO

[25]

0

Write Enable (PWD_APP_DSP)

WO

[24]

0

Write Enable (PWD_APP)

RO

[23]

0

Reserved

WO

[22]

0

Write Enable (PWD_SYSIOP_SUB)

WO

[21]

0

Write Enable (PWD_SYSIOP)

WO

[20]

0

Write Enable (PWD_CORE)RO[19:17]

0

Reserved

WO

[16]

0

Write Enable (PWD_SCU)

Reserved

RO

[15]

0

Reserved

PWD_APP_AUD

RW

[14]

0

Power supply control setting

PWD_GNSS

RW

[13]

0

1: ON, 0: OFF

PWD_GNSS_ITP

RW

[12]

0

－137/1293－

CXD5602 User Manual

Reserved

RO

[11]

0

Reserved

PWD_APP_SUB

RW

[10]

0

Power supply control setting

PWD_APP_DSP

RW

[9]

0

1: ON, 0: OFF

PWD_APP

RW

[8]

0

Reserved

RO

[7]

0

Reserved

PWD_SYSIOP_SU

RW

[6]

1

Power supply control setting
1: ON, 0: OFF

B
PWD_SYSIOP

RW

[5]

1

PWD_CORE

RW

[4]

1

Reserved

RO

[3:1]

0

Reserved

PWD_SCU

RW

[0]

0

Power supply control setting
1: ON, 0: OFFNote:
The power supplies that are controlled are only the ones to which “1” has been written to their corresponding
Write Enables.
Table PMU (Power Management Unit)-38 Power Supply Status (Power Domain)
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100200

PWD_STAT

ReservedRO[31:15]0Reserved

PWD_APP_AUD

RO

[14]

0

Power supply status

PWD_GNSS

RO

[13]

0

1: ON, 0: OFF

PWD_GNSS_ITP

RO

[12]

0

Reserved

RO

[11]

0

Reserved

PWD_APP_SUB

RO

[10]

0

Power supply status

PWD_APP_DSP

RO

[9]

0

1: ON, 0: OFF

PWD_APP

RO

[8]

0

Reserved

RO

[7]

0

Reserved

PWD_SYSIOP_SUB

RO

[6]

0

Power supply statusPWD_SYSIOP

RO

[5]

0

1: ON, 0: OFF

PWD_CORE

RO

[4]

0

Reserved

RO

[3:1]

PWD_SCU

RO[0]

Reserved
0Power supply status
1: ON, 0: OFF－138/1293－

CXD5602 User Manual

3.4.3.3 Power Supply Control (SRAM)
Table PMU (Power Management Unit)-39 and Table PMU (Power Management Unit)-40 show the registers
related to power supply control of the SRAM. For the power supply control method, refer to the control flow
described in Section 3.4.4.1.
Table PMU (Power Management Unit)-39 Power Supply Control Settings (SRAM)
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100010

0x04100018

SYSCPU_RAMM

Reserved

RO

[31]

0

Reserved

ODE_SEL

WEN

WO

[30]

0

Write Enable (RAM3_64KB)

[29]

0

Write Enable (RAM2_64KB)

[28]

0

Write Enable (RAM1_64KB)

[27]

0

Write Enable (RAM0_32KB)

[26]

0

Write Enable (RAM0_16KB)

[25]

0

Write Enable (RAM0_8KB_1)

[24]

0

Write Enable (RAM0_8KB_0)

ReservedRO[23:14]0Reserved

RAM3_64KB

RW[13:12]2'b11

Power supply control settings

RAM2_64KB

RW[11:10]

2'b11

2'b11: On mode

RAM1_64KB

RW

[9:8]

2'b11

2'b01: Retention mode

RAM0_32KB

RW

[7:6]

2'b11

2'b00: ShutDown mode

RAM0_16KB

RW

[5:4]

2'b11

2'b10: Prohibited setting

RAM0_8KB_1

RW

[3:2]

2'b11

RAM0_8KB_0

RW

[1:0]

2'b11

TOP_SCU_RAM

ReservedRO[31:20]0Reserved

MODE_SEL

WEN

WO

[25]

0

Write Enable (BKMEM_MODESEL1)

WO

[24]

0

Write Enable (BKMEM_MODESEL0)

ReservedRO[23:20]0Reserved

BKRAM_MODES

RW[19:18]2'b11

Power supply control settings
2'b11: On mode

EL1
BKRAM_MODES

RW[17:16]

2'b11

2'b01: Retention mode
2'b00: ShutDown modeEL0

2'b10: Prohibited setting
ReservedRO[15:13]0Reserved

WEN

WO

[12]

0

Write Enable (SCUSEQ)

ReservedRO[11:10]0Reserved

WEN

WO

[9]

0

Write Enable (SCU_FIFO1)[8]

0

Write Enable (SCU_FIFO0)－139/1293－

CXD5602 User Manual

Reserved

RO

[7:6]

0

Reserved

SCUSEQ

RW

[5:4]

2'b00

Power supply control settings

SCU_FIFO1

RW

[3:2]

2'b00

2'b11: On mode

SCU_FIFO0

RW

[1:0]

2'b00

2'b01: Retention mode
2'b00: ShutDown mode
2'b10: Prohibited setting

0x0410001C

HOSTIFC_RAM

ReservedRO[31:4]

0Reserved

MODE_SEL

WEN

WO

[25]

0

Write Enable (SEQ)

[24]

0

Write Enable (RAM_1KB)

ReservedRO[23:4]

0Reserved

SEQ

RW

[3:2]

2'b11

Power supply control settings

RAM_1KB

RW

[1:0]

2'b11

2'b11: On mode

RCOSC

RW

[0]

0

2'b01: Retention mode
2'b00: ShutDown mode
2'b10: Prohibited setting

0x04100C00

GNSSDSP_RAM

WEN

WO

MODE_SEL

0x04104424

[31]

0

Write Enable (RAM89_128KB)

[30]

0

Write Enable (RAM67_128KB)

[29]

0

Write Enable (RAM45_128KB)

[28]

0

Write Enable (RAM3_64KB)

[27]

0

Write Enable (RAM2_64KB)

[26]

0

Write Enable (RAM1_64KB)

[25]

0

Write Enable (RAM0_48KB)

[24]

0

Write Enable (RAM0_16KB)

ReservedRO[23:16]

0Reserved

RAM89_128KB

RW[15:14]

2'b11

Power supply control settings

RAM67_128KB

RW[13:12]

2'b11

2'b11: On mode

RAM45_128KB

RW[11:10]

2'b11

2'b01: Retention mode

RAM3_64KB

RW

[9:8]

2'b11

2'b00: ShutDown mode

RAM2_64KB

RW

[7:6]

2'b11

2'b10: Prohibited setting

RAM1_64KB

RW

[5:4]

2'b11

RAM0_48KB

RW

[3:2]

2'b11

RAM0_16KB

RW

[1:0]

2'b11

APPDSP_RAMM

ReservedRO[31:30]0Reserved

ODE_SEL0

WEN

WO

[29]

0

Write Enable (RAM5)

[28]

0

Write Enable (RAM4)

[27]

0

Write Enable (RAM3)

[26]

0

Write Enable (RAM2)

[25]

0

Write Enable (RAM1)－140/1293－

CXD5602 User Manual

0x04104424

[24]

0

Write Enable (RAM0)

ReservedRO[23:12]0

Reserved

RAM5

RW[11:10]

2'b00

Power supply control settings

RAM4

RW

[9:8]

2'b00

2'b11: On mode

RAM3

RW

[7:6]

2'b00

2'b01: Retention mode

RAM2

RW

[5:4]

2'b00

2'b00: ShutDown mode

RAM1

RW

[3:2]

2'b00

2'b10: Prohibited setting

RAM0

RW

[1:0]

2'b00

APPDSP_RAMM

ReservedRO[31:30]0Reserved

ODE_SEL1

WEN

WO

[29]

0

Write Enable (RAMB)

[28]

0

Write Enable (RAMA)

[27]

0

Write Enable (RAM9)

[26]

0

Write Enable (RAM8)

[25]

0

Write Enable (RAM7)

[24]

0

Write Enable (RAM6)

ReservedRO[23:12]0

Reserved

RAMB

RW[11:10]

2'b00

Power supply control settings

RAMA

RW

[9:8]

2'b00

2'b11: On mode

RAM9

RW

[7:6]

2'b00

2'b01: Retention mode

RAM8

RW

[5:4]

2'b00

2'b00: ShutDown mode

RAM7

RW

[3:2]

2'b00

2'b10: Prohibited setting

RAM6

RW

[1:0]

2'b00

Table PMU (Power Management Unit)-40 Power Supply Status (SRAM)
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x0410020C

0x04100214

SYSCPU_RAMM

ReservedRO[31:14]0Reserved

ODE_STAT

RAM3_64KB

RO[13:12]2'b11

Power supply control settings

RAM2_64KB

RO[11:10]

2'b11

2'b11: On mode

RAM1_64KB

RO

[9:8]

2'b11

2'b01: Retention mode

RAM0_32KB

RO

[7:6]

2'b11

2'b00: ShutDown mode

RAM0_16KB

RO

[5:4]

2'b11

2'b10: Prohibited setting

RAM0_8KB_1

RO

[3:2]

2'b11

RAM0_8KB_0

RO

[1:0]

2'b11

TOP_SCU_RAM

ReservedRO[31:20]0Reserved

MODE_STATBKRAM1

RO[19:18]2'b11

Power supply status－141/1293－

CXD5602 User Manual

BKRAM0RO[17:16]

2'b11

2'b11: On mode
2'b01: Retention mode
2'b00: ShutDown mode
2'b10: Prohibited setting

ReservedRO[15:6]

0Reserved

SCUSEQ

RO

[5:4]

2'b00

Power supply status

SCU_FIFO1

RO

[3:2]

2'b00

2'b11: On mode

SCU_FIFO0

RO

[1:0]

2'b00

2'b01: Retention mode
2'b00: ShutDown mode
2'b10: Prohibited setting

0x04100218

HOSTIFC_RAM

ReservedRO[31:4]

0Reserved

MODE_STAT

SEQ

RO

[3:2]

2'b00

Power supply status

RAM_1KB

RO

[1:0]

2'b00

2'b11: On mode
2'b01: Retention mode
2'b00: ShutDown mode
2'b10: Prohibited status

0x04100C40

0x04104420

0x04104424

GNSSDSP_RAM

ReservedRO[31:16]

0Reserved

MODE_STAT

RAM89_128KB

RO[15:14]

2'b11

Power supply status

RAM67_128KB

RO[13:12]

2'b11

2'b11: On mode

RAM45_128KB

RO[11:10]

2'b11

2'b01: Retention mode

RAM3_64KB

RO

[9:8]

2'b11

2'b00: ShutDown mode

RAM2_64KB

RO

[7:6]

2'b11

2'b10: Prohibited setting

RAM1_64KB

RO

[5:4]

2'b11

RAM0_48KB

RO

[3:2]

2'b11

RAM0_16KB

RO

[1:0]

2'b11

APPDSP_RAMM

ReservedRO[31:12]0

Reserved

ODE_STAT0

RAM5

RO

[11:10]

2'b00

Power supply status

RAM4

RO

[9:8]

2'b00

2'b11: On mode

RAM3

RO

[7:6]

2'b00

2'b01: Retention mode

RAM2

RO

[5:4]

2'b00

2'b00: ShutDown mode

RAM1

RO

[3:2]

2'b00

2'b10: Prohibited setting

RAM0

RO

[1:0]

2'b00

APPDSP_RAMM

ReservedRO[31:12]0

Reserved

ODE_STAT1

RAMB

RO

[11:10]

2'b00

Power supply status

RAMA

RO

[9:8]

2'b00

2'b11: On mode

RAM9

RO

[7:6]

2'b00

2'b01: Retention mode

RAM8

RO

[5:4]

2'b00

2'b00: ShutDown mode

RAM7

RO

[3:2]

2'b00

2'b10: Prohibited setting－142/1293－

CXD5602 User Manual

RAM6

RO

[1:0]

2'b00

3.4.3.4 Power Supply Control (Analog Circuit)
Table PMU (Power Management Unit)-41 and Table PMU (Power Management Unit)-42 show the registers
related to power supply control of the analog circuit. For the power supply control method, refer to the control
flow described from Section 3.4.4.1.2 to Section 3.4.4.1.7.
Table PMU (Power Management Unit)-41 Power Supply Control Settings (Analog Circuit)
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100004

ANA_PW_CTL

WEN

RO

[31:30]0Reserved

WO

[29]

0

Write Enable (LPADC)

WO

[28]

0

Write Enable (HPADC)

RO[27:26]

0Reserved

WO

[25]

0

Write Enable (RF_PLL)

WO

[24]

0

Write Enable (RF_LO)

WO

[23]

0

Write Enable (RF_ADC)

WO

[22]

0

Write Enable (RF_IF)

WO

[21]

0

Write Enable (RF_MIX)

WO

[20]

0

Write Enable (RF_LNA)

RO

[19]

0

Reserved

WO

[18]

0

Write Enable (SYSPLL)

WO

[17]

0

Write Enable (XOSC)

WO

[16]

0

Write Enable (RCOSC)

ReservedRO[15:14]0Reserved

LPADC

RW

[13]

0

Power supply control setting

HPADC

RW

[12]

0

1: ON, 0: OFF

ReservedRO[11:10]0Reserved

RF_PLLRW[9]0Power supply control setting

RF_LO

RW

[8]

0

1: ON, 0: OFF

RF_ADC

RW

[7]

0

RF_IF

RW

[6]

0

RF_MIX

RW[5]0

RF_LNARW[4]0

Reserved

RO

[3]

0

Reserved

SYSPLLRW[2]

0Power supply control setting

XOSC

RW

[1]

0

1: ON, 0: OFF

RCOSC

RW

[0]

0

－143/1293－

CXD5602 User Manual

0x04100008

ANA_EN_CTL

ReservedRO[31:26]

0Reserved

ON_XO_OSC_EN_

RW

[25]

1

XOSC oscillator Enable

RW

[24]

1

ReservedRO[23:21]

0

Reserved

ON_XO_OSCOUT

RW

[20]

1

XOSC oscillator output Enable

RW

[19]

1

RW

[18]

0

RW

[17]

0

ReservedRO[16:0]

0x1F7

Reserved

Reserved

RW[31:24]0Reserved

SET
OFF_XO_OSC_EN_CLR_EN_SET
OFF_XO_OSCOU
T_EN_CLR
ON_XO_EXT_EN_

XOSC external clock operation Enable

SET
OFF_XO_EXT_EN_CLR

0x04100584

XOSC_CTRL2(Do not change the initial value)
IXO_LV_I_VAL3

RW[23:16]0

Oscillator current adjustment

IXO_LV_I_VAL1

RW[15:8]

0

Oscillator current adjustment

Reserved

RW

[7:0]

0

Reserved(Do not change the initial value)

Table PMU (Power Management Unit)-42 Power Supply Status (Analog Circuit)
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100208

ANA_PW_STAT

ReservedRO[31:14]0Reserved

LPADC

RO

[13]

0

Power supply status

HPADC

RO

[12]

0

1: ON, 0: OFF

ReservedRO[11:10]0Reserved

RF_PLLRO[9]0

Power supply status

RF_LO

RO

[8]

0

1: ON, 0: OFF

RF_ADC

RO

[7]

0

RF_IF

RO

[6]

0

RF_MIX

RO[5]

0

RF_LNARO[4]

0

Reserved

RO

[3]

0

Reserved

SYSPLLRO[2]

0

Power supply status

XOSC

RO

[1]

0

1: ON, 0: OFF－144/1293－

CXD5602 User Manual

RCOSC

RO

[0]

0

3.4.3.5 Power Supply Control Request
Table PMU (Power Management Unit)-43 shows the power supply control request registers. By writing “1” toPMU_PW_CTL.POWER_CTRL_ON, power supply control starts according to the value of the power supply
control setting register (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL).
Table PMU (Power Management Unit)-43 Power Supply Control Request
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100030

PMU_PW_CTL

ReservedRO[31:1]

0Reserved

POWER_CTRL_O

WO

[0]

0

Power supply control request
1: Power supply control executionN
0x0410021C

PMU_HW_STAT

ReservedRO[31:1]-

Reserved

POWER_CTRL_ST

RO

[0]

0

Power supply control status
1: Power supply is being controlled

AT

0: Power supply is not yet controlled

3.4.3.6 Interrupt
The PMU has two types of interrupts, each of which allows the control of status read, clear, and mask. The twointerrupts (PMU_INT_STAT[1:0]) are ORed and sent to the CPU/DSP as INT_CAUSE0.PMU. For details, refer
to Section 3.3.2. The following describes the details of the two interrupts. Table PMU (Power Management
Unit)-44 shows a register list of the interrupts.
Interrupt


DONE: Completion of power supply control

When power supply control is completed, this changes to “1”.
NOGO_CTRL: Error in power supply setting

When a power supply control request is made with an incorrect setting of the power supply control
register (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL), this changes to “1”. At this time, thepower supply control is not performed. The reason for the error can be checked by PSW_CHECK. For
details, refer to Section 3.4.3.7.
Table PMU (Power Management Unit)-44 Interrupt
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100040

PMU_INT_STAT

ReservedRO[31:2]-

Reserved

NOGO_CTRL

RO

[1]

0

Interrupt request－145/1293－

CXD5602 User Manual

DONE

RO

[0]

0

Indicates the status after the interrupt
factor is masked by the interrupt mask
register.

0x04100044

PMU_RAW_INT

ReservedRO[31:2]-

Reserved_STAT

NOGO_CTRL

RO

[1]

0

Interrupt factor

DONE

RO

[0]

0

1: Interrupt exists
0: No interrupt

0x04100048

PMU_INT_CLR

Reserved

WO[31:2]

0Reserved
The API may change the value. Perform
read-modify-write when writing values
to NOGO_CTRL and DONE.

0x0410004C

PMU_INT_MAS

NOGO_CTRL

WO

[1]

0

Interrupt clear

DONE

WO

[0]

0

1: Clear

Reserved

RW[31:2]

30'h

Reserved

3C4

The API may change the value. PerformK

read-modify-write when writing values
to NOGO_CTRL and DONE.
NOGO_CTRL

RW

[1]

0

Interrupt mask

DONE

RW

[0]

0

Processor notification setting of theinterrupt factor
0: Notify
1: Do not notify

3.4.3.7 Power Supply Setting Check
During a power supply control request, the PMU checks whether or not there is an incorrect setting in the power
supply setting. When there is an incorrect setting, the corresponding bit within the PSW_CHECK becomes “1”and power supply control is not performed.
Table PMU (Power Management Unit)-45 shows the registers of PSW_CHECK. Table PMU (Power Management
Unit)-46 shows the content checked by PSW_CHECK.
Table PMU (Power Management Unit)-45 Power Supply Setting Check
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04103000

PSW_CHECK

STATE

RO

[31:0]

0

Incorrect setting
1: Incorrect setting exists
0: No incorrect setting－146/1293－

CXD5602 User Manual

Table PMU (Power Management Unit)-46 Power Supply Setting Check Items
PSW_CHECK
Bit

Category

Content checked

Power supply“RCOSC power supply and PMU clock source check”

control

When turning OFF the RCOSC, make sure to change the operation clock of the PMU from

（1*）

[31]

RCOSC to RTC_CLK_IN beforehand.
When changing the operation clock of the PMU to RCOSC, turn ON the RCOSC beforehand.

You want to set the operation clock of the PMU to a clock other than RCOSC
Refer to Section 3.4.4.1.2 for the RCOSC OFF control flow.

You want to turn ON the RCOSC
Refer to Section 3.4.4.1.2 for the RCOSC ON control flow.

[21]

GNSS

“Power supply setting check (Power domain and SRAM) of GNSS Domain”
When PWD_GNSS is ON, turn ON at least one of the SRAMs for GNSS DSP.
When turning OFF all SRAMs for GNSS DSP, make sure to turn OFF PWD_GNSS too.

To turn ON the PWD_GNSS and SRAM for GNSSDP:PWD_CTL=0x20002000
GNSSDSP_RAMMODE_SEL=0xFF00FFFF & SRAM for GNSS DSP power supply
settingTo turn OFF the PWD_GNSS and SRAM for GNSSDP:PWD_CTL=0x20000000
GNSSDSP_RAMMODE_SEL=0xFF000000[18]“Power supply setting check (RF and XOSC) of the GNSS Domain”
When turning ON the RF, also turn ON the XOSC.
When turning OFF the XOSC, also turn OFF the RF.



To turn ON the XOSC and RF:
ANA_PW_CTL=0x00020002 | (0x03F03F0 & RF power supply setting)To turn OFF the XOSC and RF:
ANA_PW_CTL=0x03F20000[17]“Power supply setting check (Power domain) of the GNSS Domain”
When turning ON the PWD_GNSS, also turn ON the PWD_GNSS_ITP.
When turning OFF the PWD_GNSS_ITP, also turn OFF the PWD_GNSS.



To turn ON the PWD_GNSS and PWD_GNSS_ITP:PWD_CTL=0x30003000



To turn OFF the PWD_GNSS and PWD_GNSS_ITP:PWD_CTL=0x30000000－147/1293－

CXD5602 User Manual[16]“Power supply setting check (RF and SRAM) of the GNSS Domain”
When turning ON the SRAM for GNSS or RF, also turn ON the PWD_GNSS.
When turning OFF the PWD_GNSS, also turn OFF the SRAM for GNSS and RF.



To turn ON the PWD_GNSS and SRAM for GNSS, RF:
PWD_CTL=0x30003000
ANA_PW_CTL=0x00020002 | (0x03F03F0 & RF power supply setting)
GNSS_RAMMODE_SEL=0x3F000FFF

To turn OFF the PWD_GNSS and SRAM for GNSS, RF:
PWD_CTL=0x20000000
GNSS_RAMMODE_SEL=0x3F000000
ANA_PW_CTL=0x03F00000

[12]

SCU

“Power supply setting check of the Sensor Domain”
When turning ON the SRAM for SCU, HPADC, or LPADC, also turn ON the PWD_SCU.
When turning OFF the PWD_SCU, also turn OFF the SRAM for SCU, HPADC, and LPADC.



To turn ON the PWD_SCU, SRAM for SCU, HPADC, and LPADC:
PWD_CTL=0x00010001
ANA_PW_CTL=0x30003000 & (HPADC and LPADC power supply setting)
TOP_SCU_RAMMODE_SEL=0x0000133F & SRAM for SCU power supply settingTo turn OFF the PWD_SCU, SRAM for SCU, HPADC, and LPADC:
PWD_CTL=0x00010001
ANA_PW_CTL=0x30000000
TOP_SCU_RAMMODE_SEL=0x00001300

[9]

CPU

“Power supply setting check of the Application Domain”
When turning ON power supply layers lower than the PWD_APP, also turn ON the PWD_APP.
When turning OFF the PWD_APP, also turn OFF the power supply layers lower than the
PWD_APP.
Note:
The layers lower than PWD_APP are as follows:
PWD_APP_AUD, PWD_APP_SUB, PWD_APP_DSP, SRAM for Application Processor

To turn ON the power supply layers lower than the PWD_APP:
PWD_CTL=0x01000100 | (0x46004600 & PWD_APP_(AUD/SUB/DSP) power supply
setting)
APPDSP_RAMMODE_SEL0=0x3F000FFF
APPDSP_RAMMODE_SEL1=0x3F000FFF

To turn OFF the PWD_APP:
PWD_CTL=0x47000000
APPDSP_RAMMODE_SEL0=0x3F000000
APPDSP_RAMMODE_SEL1=0x3F000000[4]

Analog circuit“Power supply setting check of the XOSC and SYSPLL”－148/1293－

CXD5602 User Manual

When turning ON the SYSPLL, also turn ON the XOSC.
When turning OFF the XOSC, also turn OFF the SYSPLL.



To turn ON the XOSC ON, SYSPLL:
ANA_PW_CTL=0x00060006



To turn OFF the XOSC OFF, SYSPLL:
ANA_PW_CTL=0x00060000（1*）

The Bits not listed are Reserved.

3.4.4

Power Supply Control Flow

3.4.4.1 Basic Flow of Power Supply Control
The following describes the basic flow of power supply control. Make sure to control the power domain and
SRAM in accordance with the basic flow of power supply control. In the case of Analog circuits, individual
settings are required for each analog circuit before and after the basic flow of power supply control. For details on
the control flow including individual settings, refer to Section 3.4.4.1.2 through Section 3.4.4.1.7.
1. Power supply control On/Off (/Retention) settings
PWD_CTL=0x40004000 (Example: PWD_APP_AUD=ON)
Refer to Table PMU (Power Management Unit)-47 and make the register settings of the desired power
supply. For the setting restrictions, refer to the power supply control restrictions. For an actual example
of power supply control, refer to Section 3.4.5.1.
Table PMU (Power Management Unit)-47 Power Supply Control Setting Values
DomainPower nameRegister name

Off Control

On Control

Retention

Setting

Setting

Control

Value

Value

Setting Value

－

－

－

－

TOP_SCU_RAMMODE_SEL

0x01000000

0x01030000

0x01010000

TOP_SCU_RAMMODE_SEL

0x02000000

0x020C0000

0x02040000

RCOSC

ANA_PW_CTL

0x00010000

0x00010001

－

XOSC

ANA_PW_CTL

0x00020000

0x00020002－

SYSPLL

ANA_PW_CTL

0x00040000

0x00040004－

PWD_CTL

0x00010000

0x00010001－

TOP_SCU_RAMMODE_SEL

0x00000100

0x00000103

0x00000101

name

AlwaysON

PWD_PMU
SRAM(Backup SRAM 32 KByte)
SRAM(Backup SRAM 32 KByte)

SensorPWD_SCU

DomainSRAM(FIFO 8 KByte)－149/1293－

CXD5602 User Manual

TOP_SCU_RAMMODE_SEL

0x00000200

0x0000020C

0x00000204

TOP_SCU_RAMMODE_SEL

0x00001000

0x00001030

0x00001010

ADC (HPADC)

ANA_PW_CTL

0x10000000

0x10001000－

ADC (LPADC)

ANA_PW_CTL

0x20000000

0x20002000－

PWD_CTL

0x00100000

0x00100010－

SYSCPU_RAMMODE_SEL

0x01000000

0x01000003

0x01000001

SYSCPU_RAMMODE_SEL

0x02000000

0x0200000C

0x02000004

SYSCPU_RAMMODE_SEL

0x04000000

0x04000030

0x04000010

SYSCPU_RAMMODE_SEL

0x08000000

0x080000C00x08000040

SYSCPU_RAMMODE_SEL

0x10000000

0x10000300

0x10000100

SYSCPU_RAMMODE_SEL

0x20000000

0x20000C00

0x20000400

SYSCPU_RAMMODE_SEL

0x40000000

0x40003000

0x40001000

GNSSDSP_RAMMODE_SEL

0x01000000

0x01000003

0x01000001

GNSSDSP_RAMMODE_SEL

0x02000000

0x0200000C

0x02000004

GNSSDSP_RAMMODE_SEL

0x04000000

0x04000030

0x04000010

GNSSDSP_RAMMODE_SEL

0x08000000

0x080000C00x08000040

GNSSDSP_RAMMODE_SEL

0x10000000

0x10000300

0x10000100

GNSSDSP_RAMMODE_SEL

0x20000000

0x20000C00

0x20000400

SRAM(FIFO 32 KByte)
SRAM(Sequencer RAM)

SystemPWD_CORE

and IOP

SRAM

Domain(SYSIOP Tile #0 8 KByte)
SRAM(SYSIOP Tile #0 8 KByte)
SRAM(SYSIOP Tile #0 16 KByte)
SRAM(SYSIOP Tile #0 32 KByte)
SRAM(SYSIOP Tile #1 64 KByte)
SRAM(SYSIOP Tile #2 64 KByte)
SRAM(SYSIOP Tile #3 64 KByte)
SRAM
(GNSS

DSP

Tile

#0

16

KByte)
SRAM
(GNSS

DSP

Tile

#0

48

KByte)SRAM(GNSS DSP Tile #1 64KByte)
SRAM
(GNSS

DSP

Tile

#2

64

KByte)
SRAM
(GNSS

DSP

Tile

#3

64

KByte)SRAM (GNSS DSP Tile #4,5
128 KByte)－150/1293－

CXD5602 User Manual

GNSSDSP_RAMMODE_SEL

0x40000000

0x40003000

0x40001000

GNSSDSP_RAMMODE_SEL

0x80000000

0x8000C000

0x80004000

PWD_SYSIOP_SUB

PWD_CTL

0x00400000

0x00400040－

PWD_SYSIOPPWD_CTL

0x00200000

0x00200020－

SRAM (HOSTIFC 1 KByte)

HOSTIFC_RAMMODE_SEL

0x01000000

0x01000003

0x01000001

SRAM

HOSTIFC_RAMMODE_SEL

0x02000000

0x0200000C

0x02000004

PWD_CTL

0x01000000

0x01000100－

APPDSP_RAMMODE_SEL0

0x01000000

0x01000003

0x01000001

APPDSP_RAMMODE_SEL0

0x02000000

0x0200000C

0x02000004

APPDSP_RAMMODE_SEL0

0x04000000

0x04000030

0x04000010

APPDSP_RAMMODE_SEL0

0x08000000

0x080000C00x08000040

APPDSP_RAMMODE_SEL0

0x10000000

0x10000300

0x10000100

APPDSP_RAMMODE_SEL0

0x20000000

0x20000C00

0x20000400

APPDSP_RAMMODE_SEL1

0x01000000

0x01000003

0x01000001

APPDSP_RAMMODE_SEL1

0x02000000

0x0200000C

0x02000004

APPDSP_RAMMODE_SEL1

0x04000000

0x04000030

0x04000010

APPDSP_RAMMODE_SEL1

0x08000000

0x080000C00x08000040

APPDSP_RAMMODE_SEL1

0x10000000

0x10000300

0x10000100

APPDSP_RAMMODE_SEL1

0x20000000

0x20000C00

0x20000400

PWD_APP_DSP

PWD_CTL

0x02000000

0x02000200－

PWD_APP_SUB

PWD_CTL

0x04000000

0x04000400－

PWD_APP_AUD

PWD_CTL

0x40000000

0x40004000－

SRAM(GNSS DSP Tile #6,7 128
KByte)SRAM (GNSS DSP Tile #8,9
128KByte)(HOSTIFC Sequencer RAM)
Applicati

PWD_APPon

SRAM (Application Processor

DomainTile #0 128 KByte)
SRAM (Application Processor
Tile #1 128 KByte)
SRAM (Application Processor
Tile #2 128 KByte)
SRAM (Application Processor
Tile #3 128 KByte)
SRAM (Application Processor
Tile #4 128 KByte)
SRAM (Application Processor
Tile #5 128 KByte)
SRAM (Application Processor
Tile #6 128 KByte)
SRAM (Application Processor
Tile #7 128 KByte)
SRAM (Application Processor
Tile #8 128 KByte)
SRAM (Application Processor
Tile #9 128 KByte)
SRAM (Application Processor
Tile #10 128 KByte)
SRAM (Application Processor
Tile #11 128 KByte)－151/1293－

CXD5602 User Manual

GNSS

PWD_GNSS_ITP

PWD_CTL

0x10000000

0x10001000－

DomainPWD_GNSSPWD_CTL

0x20000000

0x20002000－

SRAM (GNSS BB#0)

GNSS_RAMMODE_SEL

0x01000000

0x01000003

0x01000001

SRAM (GNSS BB#1)

GNSS_RAMMODE_SEL

0x02000000

0x0200000C

0x02000004

SRAM (GNSS BB#2)

GNSS_RAMMODE_SEL

0x04000000

0x04000030

0x04000010

SRAM (GNSS BB#3)

GNSS_RAMMODE_SEL

0x08000000

0x080000C00x08000040

SRAM (GNSS BB#4)

GNSS_RAMMODE_SEL

0x10000000

0x10000300

0x10000100

SRAM (GNSS BB#5)

GNSS_RAMMODE_SEL

0x20000000

0x20000C00

0x20000400

RF (LNA)

ANA_PW_CTL

0x00100000

0x00100010－

RF (MIX)

ANA_PW_CTL

0x00200000

0x00200020－

RF (IF)

ANA_PW_CTL

0x00400000

0x00400040－

RF (ADC)

ANA_PW_CTL

0x00800000

0x00800080－

RF (LO)

ANA_PW_CTL

0x01000000

0x01000100－

RF (PLL)

ANA_PW_CTL

0x02000000

0x02000200－

2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. Power supply control execution
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
In the case of PMU_INT_STAT.STAT[1]=1, refer to Section 3.4.3.7.
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. Clock and reset control
Perform proper clock and reset control according to each power domain, SRAM, and Analog circuit.
Power Supply Control Restrictions
When power domains such as the SRAM are turned ON, make sure to turn ON all SRAMs in those power
domains. The following describes an example of the power supply control setting.
In the case of turning ON the PWD_APP (SRAM (Application Processor Tile #0-11) ON)

PWD_CTL=0x01000100 (PWD_APP=ON)

APPDSP_RAMMODE_SEL0=0x3F000FFF (SRAM (Application Processor Tile #0-5) =ON)

APPDSP_RAMMODE_SEL1=0x3F000FFF (SRAM (Application Processor Tile #6-11) =ON)

In the case of turning ON the PWD_GNSS (SRAM (GNSS BB#0-5) ON)

PWD_CTL=0x20002000 (PWD_GNSS=ON)－152/1293－

CXD5602 User Manual

GNSS_RAMMODE_SEL=0x3F000FFF (SRAM (GNSS BB#0-5) =ON)

－153/1293－

CXD5602 User Manual

3.4.4.1.2

RCOSC

OFF => ON Control Flow
The following describes the flow to turn ON the power supply of the RCOSC.
1. RCOSC power supply ON setting
ANA_PW_CTL=32'h00010001
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. RCOSC power supply ON control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. Clock control
Control the supply/stop of the clock in accordance with the function block or Analog circuit you use.


When supplying the clock

RCOSC_CTRL1.IRO_LV_SENSCLK_XEN=0 (for HPADC)



RCOSC_CTRL1.IRO_LV_LOGICLK_XEN=0 (for each function block)

When stopping the clock

RCOSC_CTRL1.IRO_LV_SENSCLK_XEN=1 (for HPADC)



RCOSC_CTRL1.IRO_LV_LOGICLK_XEN=1 (for each function block)ON => OFF Control Flow
The following describes the flow to turn OFF the power supply of the RCOSC. As a precondition, when there is a
block using the RCOSC such as the PMU, use the API to switch the clock source to one other than the RCOSC
before turning OFF the RCOSC. The clock of the PMU can be confirmed by
CKSEL_ROOT.RORTC_STAT_CLK_SEL2.
The following describes the flow.
1. RCOSC power supply OFF setting
ANA_PW_CTL=32'h00010000
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. RCOSC power supply OFF control－154/1293－

CXD5602 User Manual

PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11

3.4.4.1.3

XOSC

OFF => ON Control Flow
The following describes the flow to turn ON the power supply of the XOSC.
1. XOSC parameter setting
Refer to Table PMU (Power Management Unit)-48 for the settings of ANA_EN_CTL.
The XOSC has two operation modes as shown below, in which the register parameters vary according to
the mode.
Internal oscillation mode (system configuration that uses crystal oscillation)
Supported frequencies: 26 MHz

External clock mode (system configuration that uses TCXO)
Supported frequencies: 26 MHz
Table PMU (Power Management Unit)-48 Parameter Setting for Each Mode
Register Name

Internal Oscillation

External Clock Mode

Mode
ANA_EN_CTL.ON_XO_OSC_EN_SET

0

1

ANA_EN_CTL.OFF_XO_OSC_EN_CLR

0

1

ANA_EN_CTL.ON_XO_OSCOUT_EN_SET

0

1

ANA_EN_CTL.OFF_XO_OSCOUT_EN_CLR

0

1

ANA_EN_CTL.ON_XO_EXT_EN_SET

10

ANA_EN_CTL.OFF_XO_EXT_EN_CLR

10

2. XOSC current adjustment settingIn the case of internal oscillation mode
Refer

to

Table

PMU

(PowerManagement

Unit)-49

forthesettingsofManagement

Unit)-49

forthesettings

of

XOSC_CTRL2.IXO_LV_I_VAL1.
Refer

to

Table

PMU

(Power

XOSC_CTRL2.IXO_LV_I_VAL3.


In the case of external clock mode
XOSC_CTRL2.IXO_LV_I_VAL1=8'h00
XOSC_CTRL2.IXO_LV_I_VAL3=8'h00－155/1293－

CXD5602 User Manual

3. The setting value of current adjustment is different for each frequency of the XOSC.
Table PMU (Power Management Unit)-49 shows the assumed combination of the crystal oscillator,
damping resistor, and the oscillation circuit setting.
Table PMU (Power Management Unit)-49 Current Adjustment Setting
FrequeCrystal oscillator

Damping

Oscillation Circuit Setting

ncy

Model

Resistor

Before oscillation

After

[MHz]

NumberRd[Ω]XOSC_CTRL2.IXO_L

change

V_I_VAL1

XOSC_CTRL2.IXO_L

CL[pF]

current

setting

V_I_VAL3
19.2

DSR211ATH

7

0

30

30

26

(KDS)

8

0

60

40

26

TAS-2016B

8

0

60

40

32.768

(TEW)

4

0

20

20

5.2

0

90

70

52

4. XOSC power supply ON control
ANA_PW_CTL=32'h00020002
5. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
6. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
7. Power supply control execution
PMU_PW_CTL.POWER_CTRL_ON=1
8. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
9. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
10. Clock control
Control the supply/stop of the clock in accordance with the function block or Analog circuit you use.
In the case of supplying the clock

XOSC_CTRL.IXO_LV_LOCLK_EN=1 (for GNSS)

XOSC_CTRL.IXO_LV_PLLCLK_EN=1 (for SYSPLL)

XOSC_CTRL.IXO_LV_SENCLK_EN=1 (for HPADC)

XOSC_CTRL.IXO_LV_LOGICLK_EN=1 (for each function block)In the case of stopping the clock

OSC_CTRL.IXO_LV_LOCLK_EN=0 (for GNSS)

XOSC_CTRL.IXO_LV_PLLCLK_EN=0 (for SYSPLL)

XOSC_CTRL.IXO_LV_SENCLK_EN=0 (for HPADC)－156/1293－

CXD5602 User Manual

XOSC_CTRL.IXO_LV_LOGICLK_EN=0 (for each function block)ON => OFF Control Flow
The following describes the flow to turn OFF the power supply of the XOSC. As a precondition, make sure thatthe power supply of the SYSPLL is turned OFF during this operation.
1. XOSC power supply OFF setting
ANA_PW_CTL=32'h00020000
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. XOSC power supply OFF control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11－157/1293－

CXD5602 User Manual

3.4.4.1.4

SYSPLLOFF => ON Control Flow
The following describes the flow to turn ON the power supply of the SYSPLL. As a precondition, perform thecontrol with the power supply of the XOSC turned ON, and the clock supplied to the SYSPLL(XOSC_CTRL.IXO_LV_PLLCLK_EN=1).
1. SYSPLL division ratio setting
Refer

to

Table

PMU

(PowerManagement

Unit)-50

forthesettingsofManagement

Unit)-50

forthesettings

of

SYS_PLL_CTRL2.ISP_LV_SELRCDIV.
Refer

to

Table

PMU

(Power

SYS_PLL_CTRL2.ISP_LV_SELFBDIV.
The frequency of the SYSPLL is determined by the frequency of the XOSC and register value. The
following describes the division ratio settings of the SYSPLL.
Table PMU (Power Management Unit)-50 SYSPLL Division Ratio Setting
XOSC

SYS_PLL_CTRL2.ISP_L

SYS_PLL_CTRL2.ISP_L

SYSPLL

Frequency

V_SELRCDIV[1:0]

V_SELFBDIV[2:0]Frequency[MHz]
16.36819.2

2632.736

52

[MHz]
0

0

163.6801

196.421

2

144.000

0

192.001

1

156.001

2

195.001

0163.681

1

196.423

1

156.003

2

195.002. SYSPLL power supply ON setting
ANA_PW_CTL=32'h00040004
3. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
4. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
5. SYSPLL power supply ON control
PMU_PW_CTL.POWER_CTRL_ON=1－158/1293－

CXD5602 User Manual

6. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
7. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
8. Clock control
Control the supply/stop of the clock in accordance with the function block or Analog circuit you use.
In the case of supplying the clock

SYS_PLL_CTRL1.ISP_LV_ENDSPCLK=1 (for each function block)

SYS_PLL_CTRL1.ISP_LV_ENGPADCCLK=1 (for GNSS)

In the case of stopping the clock

SYS_PLL_CTRL1.ISP_LV_ENDSPCLK=1 (for each function block)

SYS_PLL_CTRL1.ISP_LV_ENGPADCCLK=1 (for GNSS)

ON => OFF Control Flow
The following describes the flow to turn OFF the power supply of the SYSPLL.
1. SYSPLL power supply OFF setting
ANA_PW_CTL=32'h00040000
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. SYSPLL power supply OFF control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11

3.4.4.1.5

HPADC

OFF => ON Control Flow
The following describes the flow to turn ON the power supply of the HPADC. The PWD_SCU must be turned
ON for this operation.
1. HPADC initial setting
Turn ON either the XOSC or the RCOSC according to the operation mode of the HPADC.
For details, refer to Section xxx.
2. HPADC power supply ON setting
ANA_PW_CTL=32'h10001000
3. Interrupt clear－159/1293－

CXD5602 User Manual

PMU_INT_CLR.CLR[1:0]=2'b11
4. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
5. HPADC power supply ON control
PMU_PW_CTL.POWER_CTRL_ON=1
6. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
7. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
8. Reset release
SWRESET_SCU.XRST_SCU_HPADC=1
9. Clock control
For details, refer to Section xxx.
ON => OFF Control Flow
The following describes the flow to turn OFF the power supply of the HPADC.
1. HPADC power supply OFF setting
ANA_PW_CTL=32'h10000000
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. HPADC power supply OFF control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. HPADC reset enable
SWRESET_SCU.XRST_SCU_HPADC=0
8. HPADC clock stop
For details, refer to Section xxx.

－160/1293－

CXD5602 User Manual

3.4.4.1.6

LPADC

OFF => ON Control Flow
The following describes the flow to turn ON the power supply of the LPADC. The PWD_SCU must be turned ON
for this operation.
1. LPADC power supply ON setting
ANA_PW_CTL=32'h20002000
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. LPADC power supply ON control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. LPADC reset release
SWRESET_SCU.XRST_SCU_LPADC=1
8. Clock control
For details, refer to Section xxx.
ON => OFF Control Flow
The following describes the flow for turning OFF the power supply of the LPADC.
1. LPADC power supply OFF setting
ANA_PW_CTL=32'h20000000
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. LPADC power supply OFF control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. LPADC reset application
SWRESET_SCU.XRST_SCU_LPADC=0－161/1293－

CXD5602 User Manual

8. LPADC clock stop
For details, refer to Section xxx.

3.4.4.1.7

RF

OFF => ON Control Flow
The following describes the flow to turn ON the power supply of the RF (LNA, MIX, IF, ADC, LO, PLL). The
XOSC, PWD_GNSS_ITP, and PWD_GNSS must be turned ON for this operation.
1. RF power supply ON setting
ANA_PW_CTL=32'h03F003F0
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. RF power supply ON control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. Clock control
For details, refer to Section 3.12.
ON => OFF Control Flow
The following describes the flow to turn OFF the power supply of the RF (LNA, MIX, IF, ADC, LO, PLL).
1. RF power supply OFF setting
ANA_PW_CTL=32'h03F00000
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. RF power supply OFF control
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. RF clock stop
For details, refer to Section 3.12.

－162/1293－

CXD5602 User Manual

3.4.5

Power Supply Control Example

3.4.5.1 Actual Example of Power Supply Control
By ORing the power supply control setting (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL) of each power
supply, you can control multiple power supplies together by a single power supply control request(PMU_PW_CTL.POWER_CTRL_ON). The PMU recognizes the upper layer and lower layer of the power
supplies and automatically controls the order of the power supply switch control. When controlling the power
supply from OFF to ON, the control is started from the power supplies in the upper layer. Conversely, whencontrolling the power supply from ON to OFF, the control is started from the lower layer. The following describes
an example of power supply control.
Power supplies to control


PWD_APP (OFF=>ON)

PWD_APP_AUD (OFF=>ON)

PWD_SCU (ON=>OFF)

SRAM (Application Processor Tile #4) (OFF=>ON)

Power supply control flow
1. Power supply control setting
PWD_CTL=0x41014100
OR the following power supply control settings


PWD_CTL=0x01000100 (PWD_APP=ON)

PWD_CTL=0x40004000 (PWD_APP_AUD=ON)

PWD_CTL=0x00010000 (PWD_SCU=ON)

APPDSP_RAMMODE_SEL0=0x3F000FFF
Note:
Due to the power supply control restrictions, turn ON all SRAMs of the PWD_APP layer.
OR the following power supply control settings

APPDSP_RAMMODE_SEL0=0x01000003 (SRAM (Application Processor Tile #0) =ON)

APPDSP_RAMMODE_SEL0=0x0200000C (SRAM (Application Processor Tile #1) =ON)

APPDSP_RAMMODE_SEL0=0x04000030 (SRAM (Application Processor Tile #2) =ON)

APPDSP_RAMMODE_SEL0=0x080000C0 (SRAM (Application Processor Tile #3) =ON)

APPDSP_RAMMODE_SEL0=0x10000300 (SRAM (Application Processor Tile #4) =ON)

APPDSP_RAMMODE_SEL0=0x20000C00 (SRAM (Application Processor Tile #5) =ON)

APPDSP_RAMMODE_SEL1=0x3F000FFF
OR the following power supply control settings

APPDSP_RAMMODE_SEL1=0x01000003 (SRAM (Application Processor Tile #6) =ON)

－163/1293－

CXD5602 User Manual

APPDSP_RAMMODE_SEL1=0x0200000C (SRAM (Application Processor Tile #7) =ON)

APPDSP_RAMMODE_SEL1=0x04000030 (SRAM (Application Processor Tile #8) =ON)

APPDSP_RAMMODE_SEL1=0x080000C0 (SRAM (Application Processor Tile #9) =ON)

APPDSP_RAMMODE_SEL1=0x10000300 (SRAM (Application Processor Tile #10) =ON)

APPDSP_RAMMODE_SEL1=0x20000C00 (SRAM (Application Processor Tile #11) =ON)

2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask setting
PMU_INT_MASK.MSK[1:0]=2'b00
4. Power supply control execution
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. Clock and reset control
Perform proper clock and reset control according to each power domain, SRAM, and Analog circuits.
8. Turn OFF all SRAMs other than the power supply control setting SRAM (Application Processor Tile #4)
APPDSP_RAMMODE_SEL0=0x2F00CFF (SRAM (Application Processor Tile #0-3, 5) =OFF)
APPDSP_RAMMODE_SEL1=0x3F000000 (SRAM (Application Processor Tile #6-11) =OFF)
9. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
10. Interrupt mask setting
PMU_INT_MASK.MSK[1:0]=2'b00
11. Power supply control execution
PMU_PW_CTL.POWER_CTRL_ON=1
12. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
13. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11

3.4.5.2 Application Processor Sleep/Wakeup Control
In this document, the term Sleep refers to cases when any of the power domains of the CXD5602 turn OFF, orwhen the DSP belonging to that power domain is not operating. On the other hand, Wakeup refers to cases when
they turn ON, or when the DSP belonging to that power domain starts operating. Since the Application Processorof the PWD_APP_DSP cannot perform Sleep/Wakeup of its own power domain (PWD_APP_DSP),
Sleep/Wakeup is performed from the System and I/O Processor instead.
The following describes an overview and the control flow of Sleep/Wakeup of the PWD_APP_DSP. Also, Figure－164/1293－

CXD5602 User Manual

PMU (Power Management Unit)-32 shows the control flow diagram.
Control Overview


Sleep control
The Application Processor requests Sleep (PWD_APP_DSP "OFF”) control to the System and I/O Processor.
After the Application Processor has made this request, it enters WFI state. The System and I/O Processor
then confirms that the Application Processor has entered WFI state, and performs OFF control of the
PWD_APP_DSP.

Wakeup control
Wakeup occurs as a result of an interrupt to the Application Processor. However, the Application Processor
is in Sleep, and cannot receive the interrupt nor perform ON control of the PWD_APP_DSP. Therefore,
during Sleep, the System and I/O Processor receives the interrupt instead, and performs ON control of the
PWD_APP_DSP.

Sleep (PWD_APP_DSP=OFF) Control Flow

Control of Application Processor side
Since Sleep control is not performed during the operation of the Application Processor, the interrupt ismasked and the Application Processor enters WFI state.
1. Mask all interrupts made to the Application Processor.
INT_EN*=0
For details on the interrupt mask INT_EN*, refer to Section 3.3.2.
2. Request Sleep (PWD_APP_DSP “OFF”) control to the System and I/O Processor.
3. Issue WFI command.

Control of System and I/O Processor side (reference)
The OFF request of the PWD_APP_DSP is received from the Application Processor, and the control starts.
1. The WFI monitor register (DSP_SLEEPING) of the Application Processor is polled, and the change to
WFI state is confirmed.
2. The PWD_APP_DSP is turned OFF (Refer to Section 3.4.4.1 for Basic flow of power supply control).
3. Cancel the interrupt mask of receiving the interrupt on the Application Processor’s behalf.
The following is the setting for using SYDMAC[0] as the Wakeup trigger.
INT_EN3.SYDMAC[0]=1

Wakeup (PWD_APP_DSP=ON) Control Flow
Wakeup starts when the interrupt is received. As an example, the following describes the flow when Wakeup is
performed using the interrupt INT_CAUSE3.SYMAC[0] as the trigger.
Control of the System and I/O Processor side
1. Confirm INT_CAUSE3.SYMAC[0]=1
2. Interrupt mask
INT_EN3.SYDMAC[0]=0－165/1293－

CXD5602 User Manual

3. Turn ON the PWD_APP_DSP (Refer to Section 3.4.4.1 Basic flow of power supply control)
Control of Application Processor side (reference)Starts when the System and I/O Processor turns ON the power supply of the PWD_APP_DSP
1. Interrupt mask cancel
INT_EN2.SYDMAC[0]=1
2. Detect interrupt INT_CAUSE2.SYDMAC[0] and clear
Sleep sequence

Wakeup sequence

User Control
EnableDisableWFI start

PWD_APP_DSP ON

System andI/O Processor

Power control
by proxyPMU

PWD_APP_DSP OFF

power offSleep
setting

interrupt
handling

PWD_APP_DSP ON

Detect & power control
by proxy

WFI reg
Polling

wakeup sett ing

Off request

API and HWControl(reference)

wakeup sett ing

Interrupt
clear

WFI

Sleep setting

Application
Processor

power onfor Application processor

Power off
sequence

On request

Interrupt Mask

Off request

Power onsequence

Interrupt

Figure PMU (Power Management Unit)-32 Sleep/Wakeup Control Flow of the Application Processor－166/1293－

CXD5602 User Manual

3.5

Clock and Reset (Clock Reset Generator)

3.5.1

Overview

The Clock Reset Generator (CRG) is the block that controls the clock and reset of the overall CXD5602.
For the clock sources, there are XOSC and RCOSC, SYSPLL, RTC Clock, and RF. The RTC Clock is supplied
from the outside of the CXD5602.
Clock control includes clock switching, clock supply, and clock stop. Reset control includes reset enable, reset
release, and reset enable using the WDT.
Since clock control and reset control are performed using the API, this Section describes the information for
confirming the statuses of the clock and reset.

3.5.2

Clock Scheme for CRG

Figure Clock and Reset (Clock Reset Generator)-33 shows the overall clock scheme for the CRG, while Figure
Clock and Reset (Clock Reset Generator)-34 shows the details. In Figure Clock and Reset (Clock Reset
Generator)-34, the registers indicated as ANA (number), SEL (number), and CG (number) are explained in theregister descriptions provided in the CRG Section. For descriptions on CKDIV_CPU_DSP_BUS.CK_M0,
CKDIV_CPU_DSP_BUS.CK_AHB, and CKDIV_CPU_DSP_BUS.CK_APB, refer to Section 3.14.3.

－167/1293－

CXD5602 User Manual

Application Domain
Divider

163MHz(High performance mode)/ 40MHz(Low Power mode)

Divider

Application
Processor
APP Bus
Peripheral

AHB

Divider
Divider

CIS I/F
USB
49.104MHz

Divider

SDIO
2D Graphics

49.104MHz

Divider

eMMC

Divider

AUDIO

MCLK

24.576kHz

Divider

System and IOP Domain

100MHz(High performance mode)/ 32MHz(Low Power mode)

Divider

System and I/OProcessor

AHB

Divider

SYSIOP Bus
Peripheral

APB

Divider

Debug
Divider

Sensor Domain

163.68MHz
196.416MHz

GNSS Domain

SYSPLL

Divider
Max199.2MHz

XOSC

ITP

Always On≒8.192MHz

RCOSC

BB

16.6MHz(RFPLL)/16.368MHz(SYSPLL)Divider

26MHz

GNSS DSP

66.4MHz(RFPLL)/65.472MHz(SYSPLL)Divider

RF

XTAL

100MHz(High performance mode)/ 32MHz(Low Power mode)

32KHz / 8.192MHz

1/250

Divider

PMU

32KHz

RTC

RTC Clock32.768kHz

Figure Clock and Reset (Clock Reset Generator)-33 CRG Control Area within Overall Clock Scheme
System and IOP
Fabric(Refer to SYSIOP)
ck_rf_pll_1

0
1
2
3

ck_cpu_bus

1/M

ck_cpu_bus_gear_1

SEL(4)SYSPLL macro
Clock for Logic

ANA(7)XOSC macro
Clock for SYSPLL

CK
GATE

Clock for Logic

CK
GATE

ANA(4)

ANA(2)

XTAL

16.368MHz
19.2MHz
26MHz
32.736MHz
52MHz

Clock for RF
xo_pllclk

CK_RF_ADC

1/2
1/3
1/4
1/5

CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
CKDIV_CPU_DSP_BUS.CK_APB

0
1
2
3

0
1

1/M

ck_ahb_gear

CG(2)

1/M

CK_XOSCXO_LV_LOCLK

CK
GATE

CK_RF_REF

Clock for Logic

CK
GATE

ANA(1)
ANA(0)

RTC Clock(32.768kHz)

CK
GATE

PCLK

Crypto(Clefia)
HCLK

ck_apb_gear

SEL(2)(Refer to GNSS)RCOSC macro
CKGATE

CK_PWD_RAM(Refer to SCU)

Reserved

Clock for HPADC

BackUp SRAM

CK
GATE

SEL(1)CKGATE

ANA(5)CKGATESYSPLL(Refer to SCU)XOSCClock for HPADC

ANA(3)

ANA(6)

CK
GATE

CG(3)

0
1
2
3

Always On
CG(1)

I2C4
I2CCLK
PCLK

RegisterSEL(6)
ro_senclk

CK
GATE

CG(0)

CK
GATE

CK_RTC_APB(Refer to SCU)

RCOSC

1/250

RCRTC
Reserved
Reserved

0
1
2
3

ck_rtc_pre01

ck_sel_ro_rtc

SEL(3)SEL(5)

Figure Clock and Reset (Clock Reset Generator)-34 CRG Clock Scheme－168/1293－

PMU

CK_PMUCXD5602 User Manual

3.5.3

Analog Circuits

The CRG has three analog circuits (RCOSC block, XOSC block, and SYSPLL block). The following shows thesetting confirmation registers of each analog circuit. Some of them are RW registers, but use them as RO registers.
For descriptions of the RF block, refer to Section 3.12.

3.5.3.1 RCOSC Block Setting Confirmation
The RCOSC is an internal ring oscillator that operates at 8.192 MHz. In initial state, the oscillation frequency ishigher than 8.192 MHz, but by using the calibration process of the API, it can be adjusted to 8.192 MHz.

3.5.3.1.1

Register Descriptions

Table Clock and Reset (Clock Reset Generator)-51 shows the control registers related to the RCOSC block.
Table Clock and Reset (Clock Reset Generator)-51 RCOSC Block Status Registers
Address

0x04100590

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

RCOSC_

Reserved

RW[31:15]0Reserved

CTRL1

IRO_LV_SENSCLK_

RW

[14]

1

Indicated as ANA(1) in Figure Clock and

Value

Reset (Clock Reset Generator)-34

XEN

Clock Enable for HPADC
0: Enable, 1: Disable
IRO_LV_LOGICLK_

RW

[13]

0

Indicated as ANA(0) in Figure Clock andReset (Clock Reset Generator)-34

XEN

Clock Enable for each function block
0: Enable, 1: Disable
Reserved

RW[12:0]

1

Reserved

3.5.3.2 XOSC Block Setting Confirmation
The XOSC operates at the following 5 frequencies. The selectable frequencies are different between internal
oscillation and external clock input mode.
Frequency
26 MHz

ModeInternal oscillation mode (system configuration using crystal oscillation)*Supported frequencies: 26 MHz

External clock input mode (system configuration using TCXO)－169/1293－

CXD5602 User Manual*Supported frequencies: 26 MHz
The XOSC can be used as the processor’s operation clock and is also supplied as the reference clock to the
SYSPLL and RF.

3.5.3.2.1

Register Descriptions

Table Clock and Reset (Clock Reset Generator)-52 shows the control registers related to the XOSC block.
Table Clock and Reset (Clock Reset Generator)-52 XOSC Block Status Register
Address

0x04100580

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

XOSC_C

Reserved

RW[31:20]0ReservedTRL

IXO_LV_LOCLK_E

RW

[19]

0

Indicated as ANA(5) in Figure Clock and

Value

Reset (Clock Reset Generator)-34

N

Clock Enable for GNSS
0: Clock supplied, 1: Clock stopped
IXO_LV_PLLCLK_E

RW

[18]

0

Indicated as ANA(4) in Figure Clock andReset (Clock Reset Generator)-34

N

Clock Enable for SYSPLL block
0: Clock supplied, 1: Clock stopped
IXO_LV_SENCLK_

RW

[17]

0

Indicated as ANA(3) in Figure Clock andReset (Clock Reset Generator)-34

EN

Clock Enable for HPADC
0: Clock supplied, 1: Clock stopped
IXO_LV_LOGICLK_

RW

[16]

0

Indicated as ANA(2) in Figure Clock andReset (Clock Reset Generator)-34

EN

Clock Enable for each function block
0: Clock supplied, 1: Clock stopped
Reserved

RW[15:0]－170/1293－

0ReservedCXD5602 User Manual

3.5.3.3 SYSPLL Block Setting Confirmation
The frequencies of SYSPLL can be confirmed by the XOSC frequency and division ratio setting register as shownin Table Clock and Reset (Clock Reset Generator)-53.
Table Clock and Reset (Clock Reset Generator)-53 SYSPLL Frequency Confirmation
XOSC

SYS_PLL_CTRL2.ISP_L

SYS_PLL_CTRL2.ISP_L

SYSPLL

Frequency

V_SELRCDIV[1:0]

V_SELFBDIV[2:0]Frequency[MHz]
16.36819.2

2632.73652

3.5.3.3.1

[MHz]
0

0

163.6801

196.421

2

144.000

0

192.001

1

156.001

2

195.001

0163.681

1

196.423

1

156.003

2

195.00Register Descriptions

Table Clock and Reset (Clock Reset Generator)-54 shows the control registers related to the SYSPLL block.
Table Clock and Reset (Clock Reset Generator)-54 SYSPLL Block Status Registers
Address

0x04100588

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

SYS_PLL

Reserved

RW[31:4]

0Reserved_CTRL1

ISP_LV_ENDSPCLK

RW

[3]

0

Indicated as ANA(7) in Figure Clock and

Value

Reset (Clock Reset Generator)-34
Clock Enable for each function block
0: Clock supplied, 1: Clock stopped
Reserved

RW

[2]

0

Reserved

ISP_LV_ENGPADC

RW

[1]

0

Indicated as ANA(6) in Figure Clock andReset (Clock Reset Generator)-34

CLK

Clock Enable for GNSS
0: Clock supplied, 1: Clock stopped

0x0410058C

SYS_PLL

Reserved

RW

[0]

0

Reserved

ISP_LV_SELRCDIV

RW[31:30]0

RCDIV frequency division ratio switching－171/1293－

CXD5602 User Manual_CTRL2

3.5.4

ISP_LV_SELFBDIV

RW[29:27]3'b001FBDIV frequency division ratio switchingReserved

RW[26:0]

0Reserved

Clock Setting Confirmation

3.5.4.1 Register Descriptions
The following describes the status confirmation registers of the clock switching and the clock Enable. Some ofthem are RW registers, but use them as RO registers.

3.5.4.1.1

Clock Switching

Table Clock and Reset (Clock Reset Generator)-55 shows the status registers of clock switching.
Table Clock and Reset (Clock Reset Generator)-55 Clock Switching Status Registers
Address

0x041004C4

Register

Bit Field

Name

Name

CKSEL_PMU_STAT_CLK_S

ROOT

EL4

Type

Bit

InitialDescription

Value
RO

[31:30]0

Indicated as SEL(5) in Figure Clock andReset (Clock Reset Generator)-34
PMU’s clock source switching status
2'b00: RCRTC (frequency of dividing the
RCOSC by 250)
2'b01: Reserved
2'b10: RTC Clock2'b11: Reserved

Reserved

RW[29:24]0Reserved

STAT_CLK_SEL4

RO[23:22]0

Indicated as SEL(4) in Figure Clock andReset (Clock Reset Generator)-34
Clock source switching status for System andI/O Processor/AHB/APB
2'b00: RCOSC
2'b01: SYSPLL
2'b10: XOSC
2'b11: RTC ClockReserved

RW[21:14]－172/1293－

0ReservedCXD5602 User Manual

RORTC_STAT_CLK

RO

[13]

0

Indicated as SEL(3) in Figure Clock andReset (Clock Reset Generator)-34_SEL2

Clock source switching status for power
supply control
0: RCOSC
1: RTC ClockReserved

RW

[12]

0

Reserved

RFPLL1_STAT_CLK

RO[11:10]0

Indicated as SEL(2) in Figure Clock andReset (Clock Reset Generator)-34_SEL4

SYSPLL frequency division switching status
2'b00: No frequency division
2'b01: divided by 2 (Duty H:L=1:1)
2'b10: divided by 3 (Duty H:L=2:1)
2'b11: divided by 4 (Duty H:L=1:1) ordivided by 5 (Duty H:L=3:2)
Reserved

RW

[9:3]

0

Reserved

CPU_PLL_DIV5

RW

[2]

0

Indicated as SEL(1) in Figure Clock andReset (Clock Reset Generator)-34
Either SYSPLL4 or 5 frequency divisionswitching status
0: divided by 4
1: divided by 5

0x041004C8

Reserved

RW

[1:0]

0

Reserved

CKSEL_P

ReservedRO[31:2]

0Reserved

MU

SEL_RTC_PCLK

RW

[1:0]

0

Indicated as SEL(6) in Figure Clock andReset (Clock Reset Generator)-34
I2C4 clock source switching status
2'b00: ck_apb_gear
2'b01: RTC Clock2'b10: RCOSC
2'b11: Prohibited setting－173/1293－

CXD5602 User Manual

3.5.4.1.2

Clock Enable

Table Clock and Reset (Clock Reset Generator)-56 shows the status registers of clock Enable (clock
supplied/clock stopped).
Table Clock and Reset (Clock Reset Generator)-56 Clock Enable Status Registers
Address

0x041004C0

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

PMU_CO

ReservedRO[31:4]

0Reserved

RE_CKE

BKMEM

RW

[3]

1

Indicated as CG(3) in Figure Clock and

Value

Reset (Clock Reset Generator)-34

N

Clock Enable for BackUpSRAM
1: Clock supplied
0: Clock stopped
HCLK_KAKI

RW

[2]

0

Indicated as CG(2) in Figure Clock andReset (Clock Reset Generator)-34
Clock Enable for Crypto (Clefia)
RTC_PCLK

RW

[1]

1

Indicated as CG(1) in Figure Clock andReset (Clock Reset Generator)-34
Clock Enable for I2C4
PMU_RTC_PCLK

RW

[0]

1

Indicated as CG(0) in Figure Clock andReset (Clock Reset Generator)-34
Clock Enable for I2C4 register IF－174/1293－

CXD5602 User Manual

3.5.5Power Domain Reset

The reset of each power domain can be controlled by the registers excluding some domains.
When releasing a reset, first perform ON control of the corresponding power domain, and then release the reset.
To enable a reset, first perform OFF control of the corresponding power domain, and then enable the reset.
Table Clock and Reset (Clock Reset Generator)-57 shows the relation between each power domain and the reset
control registers.
Table Clock and Reset (Clock Reset Generator)-57 Power Domain and the Reset Control Registers
Power Domain

Register

PWD_PMUNone

PWD_CORE

Reset is automatically released at start up

PWD_SYSIOPPWD_SYSIOP_SUB

PWD_RESET0.PWD_SYSIOP_SUB

PWD_SCUPWD_RESET0.PWD_SCU

PWD_APPPWD_RESET0.PWD_APP

PWD_APP_DSP

Enables/releases reset of domain layers lower than

PWD_APP_SUB

the PWD_APP

PWD_APP_AUD
PWD_GNSS_ITP

PWD_RESET0.PWD_GNSS_ITP

PWD_GNSSPWD_RESET0.PWD_GNSS－175/1293－

CXD5602 User Manual

3.5.5.1 Register Descriptions
Table Clock and Reset (Clock Reset Generator)-58 shows the reset registers of the power domain. There is a
Write Enable for each reset control bit, and reset control is performed for only the power domain to which “1” hasbeen written to the Write Enable.
Table Clock and Reset (Clock Reset Generator)-58 Reset Registers of the Power Domain
Address

0x04100060

Register

Bit Field

Name

Name

PWD_RE

WEN

SET0

Type

Bit

InitialDescription

Value
RO

[31:30]0Reserved

WO

[29]

0

Write Enable (PWD_GNSS)

[28]

0

Write Enable (PWD_GNSS_ITP)[27:25]0Reserved[24]

0

Write Enable (PWD_APP)

[23]

0

Reserved[22]0

Write Enable (PWD_SYSIOP_SUB)[21:17]

0

Reserved[16]

0

Write Enable (PWD_SCU)

ReservedRO[15:14]0Reserved

PWD_GNSS

RW

[13]

0

Reset of PWD_GNSS power domain
0: Reset is performed
1: Reset release

3.5.6

PWD_GNSS_ITP

RW

[12]

0

Reset of PWD_GNSS_ITP power domain.

ReservedRO[11:9]

0Reserved

PWD_APP

RW

[8]

0

Reset of PWD_APP power domain

Reserved

RO

[7]

0

Reserved

PWD_SYSIOP_SUB

RW

[6]

1

Reset of PWD_SYSIOP_SUB power domain

Reserved

RO

[5:1]

0

Reserved

PWD_SCU

RW

[0]

0

Reset of PWD_SCU power domain

Reset by WDT

3.5.6.1 Function Details
By detecting the asserting of the WDT within the System and I/O Processor, a reset is automatically issued to eachblock of the CXD5602. However, reset by the WDT is not performed for the following registers or SRAM. (Resetis performed only during POR).

－176/1293－

CXD5602 User ManualRegister: RAMMODE.LS (0x041006E4)

Register: BOOT_CAUSE.RAW_WDT_REBOOT (0x04100484)



SRAM: BackUpRAM
Note:
In the case of accessing the BackUpRAM after reset by WDT, clear the WDT factor register.

The WDT asserting flag of the System and I/O Processor is stored in the
BOOT_CAUSE.RAW_WDT_REBOOT.
To clear the flag, write “1” to the BOOT_CAUSE.CLR_WDT_REBOOT.
Reset by WDT can be made valid/invalid by the WDT_SRST_EN.EN.

3.5.6.2 Register Descriptions
Table Clock and Reset (Clock Reset Generator)-59 shows the control registers of reset by WDT.
Table Clock and Reset (Clock Reset Generator)-59 WDT Reset Control Registers
Address

0x04100640

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

WDT_SR

ReservedRO[31:1]

0Reserved

ST_EN

EN

RW

[0]

0

System reset by WDT valid/invalid

Value

0: Invalid
1: Valid
0x04100484

BOOT_C

ReservedRO[31:1]

0Reserved

AUSE

CLR_WDT_REBOO

WO

[5]

0

WDT asserting flag clear
1: ClearT

BOOT_CAUSE.CAUSE.RAW_WDT_REB
OOT to “0”
CLR_INITIAL_BOO

WO

[4]

0

Boot flag clear
1: ClearT

BOOT_CAUSE.CAUSE.RAW_INITIAL_
BOOT to “0”Reserved

RO

[3:2]

0

Reserved

RAW_WDT_REBOO

RO

[1]

0

WDT asserting flag
1: Reset enable occurred by WDT asserting.

T－177/1293－

CXD5602 User Manual

RAW_INITIAL_BO

RO

[0]

1

Boot flag
1: Boot by POR or WDT

OTWhen booted by POR
RAW_WDT_REBOOT =0
RAW_INITIAL.BOOT =1
When booted from WDT
RAW_WDT_REBOOT =1
RAW_INITIAL.BOOT =1－178/1293－

CXD5602 User Manual

3.6

RTC

3.6.1

Outlines and Features

Real Time Clock (RTC) continues counting time up with 32.768 kHz clock frequency. RTC is made up of 15-bit
PreCounter that generates one second interval, and 32-bit PostCounter that counts time every second. When TimeCounter meets Alarm-set time, RTC outputs an Alarm. The Alarm can be used for CPU interrupt.
Two RTC systems are embedded in this LSI.
List of RTC


RTC0 (power supply domain: PWD_PMU)

RTC1 (power supply domain: PWD_SYSIOP)

RTC0 is supplied with VDD_CORE of CXD5602, and after the reset release, it continues counting time. On theother hand, RTC1 counts time only when PWD_SYSIOP is powered on. When the PWD_SYSIOP power supply
is turned off, the Time Counter returns to “0”. As for power on/off setting of RTC0 and RTC1, refer to Chapter
3.4.
VDD_CORE

RTC0
PWD_COREPWD_SYSIOP
RTC1Figure RTC-35 RTC0/1 Power Supply Framework
Time Synchronization
In this manual, copying Time Counter values between RTCs is referred to as Time Synchronization. RTC0 and
RTC1 can mutually synchronize Time Counter values. Time Counter values of a RTC IC outside CXD5602,
typically the CXD5247 PMIC, can be synchronized to RTC0 or RTC1.

－179/1293－

CXD5602 User Manual

3.6.2

Clock Input

The clock source of the RTC is selected from either a real time clock (32.768 kHz) provided by an RTC IC
outside CXD5602 or real time clock from an internal clock (about 32 kHz) divided from the RCOSC. Initial value
after the reset release is “0” (see Table 3.6-1). When you use RCOSC, you must calibrate it to 8.192 MHz byusing API, and then use it for the RTC.
Table RTC-60Clock Resource of RTC
Clock Selection

Explanation

CKSEL_ROOT.
PMU_STAT_CLK_SEL4[1]0

Clock resource is RCOSC.
The RCOSC is calibrated to 8.192 MHz for use.
Frequency is about 32 kHz.
(initial value after the reset release of CXD5602)

1

Clock resource is real time clock provided from RTC_CLK_IN
terminal.
Frequency is 32.768 kHz

RTC Clock, which is connected to RTC1 and APB IF (RTC0/1 register control) block, can be provided or stopped
providing by Clock Enable. Provide RTC1 and register with RTC Clock before controlling them.
Table RTC-61 Clock Enable of RTC
Clock Enable

Explanation

SYSIOP_CKEN.SYSIOP_RTC
0

stops RTC Clock1

provides with RTC Clock(initial value after the reset release of CXD5602)－180/1293－

CXD5602 User Manual

RCOSC

Divider
1/250

0Calibration
required to 8MHz

RTC Clock

RTC0

1

PWD_CORE

RTC_CLK_IN(32.768kHz)PWD_SYSIOPCKSEL_ROOT.PMU_STAT_CLK_SEL4[1]

CK
GA TE

RTC1

SYSIOP_CKEN.SYSIOP_RTC
CK_APBAPB IF

Figure RTC-36 Clock Resources of RTC

3.6.3

Function List

Table RTC-62 shows list of functions that this block holds.
Table RTC-62 Function List
No

Function Name

Description

1

RTC Counter Update/Synchronization

updates internal RTC counter in variety of conditions

2

Alarm Output

outputs Alarm Flag at the prescribed time

3.6.4

Function Block Diagrams

Figure RTC-37 is a block diagram that shows functional specification of this block. There are one Time Counterand three Alarm Timers. Registers are set via APB IF block. APB IF block is operated by PWD_SYSIOP power
supply. RTC0 can select one Alarm from three Alarms, and output it from CXD5602 RTC_IRQ_OUT terminal.
Update function of Time Counter (Time Update) is shown in the block diagram on the next page.

－181/1293－

CXD5602 User Manual

Time Update

APB IFTime Counter

SetTime

Pre

Post

A

AlarmTime2
Pre

A＝B

B

Post

A

AlarmTime1

SetAlarm

Pre

A＝B

B

Post

A

Pre

A

AlarmFlag1

RTCx_Alarm1

A

Alarm

SetAlarm
Control

to NVICPMU

ErrorFlag0

A>B

B

RTCx_Misc

Control
Register0Time
Update Done

3
2
1
0

RTCx_ExtAlmCtrlSel
RTCx_ExtAlmCtrlPol
RTCx_CLKNEGEDGE_EN
operate with PWD_SYSIOP power supply

RTCx_Alarm0

AlarmFlag0

A＝B

B

Post

RTCx_Alarm2

ErrorFlag1

A>B

B

AlarmTime0

AlarmFlag2010

RTCx_ExtAlm

1

to IO(only RTC0)
RTC Time sync.

RTC0: operate always (Powered in always)
RTC1: operate with PWD_SYSIOP power supply

Figure RTC-37 RTC Block Diagram
As for Time Counter, there are two ways of updating and synchronizing time separately. By using Interrupt, you
can check whether the Time Counter has been completely updated or not.


How to set Time Counter
1. You can set the designated Time Counter value
2. You can adjust the current Time CounterHow to set Time Synchronization
3. You can set another RTC Time Counter value inside CXD5602.
4. At the timing of asserting either External Alarm Flag (Interrupt from PMIC_INT) or Alarm from RTC
inside CXD5602 (RTCx_ExtAlm), you can set the designated Time Counter value.

－182/1293－

CXD5602 User Manual

1,4
2from Other RTC Counter

Time Counter{Post, Pre}

to Other RTC Counter3

Update TypeAPB IF
WrRegPostCnt
WrRegPreCnt
OffsetVal

1:Register
2:Offset
3:RTC Sync

WrRegReq
OffsetReq
RtcSyncReq
WrIntCtrl

4:External Sync

UpdateFlag

Time Counter
update done

CntUpdateEn
WrIntCtrl.Edge

PMIC_INT

RTC0_ExtAlm
RTC1_ExtAlm

0
1
2
3

RTCx_ExtIntCtrlSel
RTCx_CLKNEGEDGE_EN

01

DetectEdge

Figure RTC-38 RTC (Time Update) Block Diagram

3.6.4.1 Address Map
RTC0 and RTC1 have each Base Address and register for synchronization setting. Addresses are as follows.


RTC00x04108000 Base Address
0x04100730 Time Synchronization setting

RTC1
0x04109000 Base Address
0x41030470 Time Synchronization setting－183/1293－

CXD5602 User Manual

3.6.5

Detailed Function and Control Specification

3.6.5.1 List of Registers
Table RTC-63 Register List of Counter Value Write Control System
OffsetRegister Name

Attribute

Function

Initial Value

0x00

WrRegPostCnt

RW

Time Counter value (PostCounter)

0x00000000

0x04

WrRegPreCnt

RW

Time Counter value (PreCounter)

0x00000000

0x08

WrRegReq

RW

Request for setting of Time Counter value

0x00000000

0x0C

ReservedRO

Reserved

0x00000000

0x10

ReservedRO

Reserved

0x00000000

0x14

ReservedRO

Reserved

0x00000000

0x18

WrIntCtrl

RW

Request for waiting for External Alarm Flag

0x00000000

Edge Detection Control of External Alarm Flag
0x1C

WrIntClr

RW

External Synchronization

0x00000000

Cancel of Request for waiting for External Alarm Flag
0x20

OffsetVal

RW

Correction value of Time Counter (PreCounter)

0x00000000

0x24

OffsetReq

RW

Correction request for Time Counter (PreCounter)

0x00000000

0x28

RtcSyncReq

RW

Synchronization request to other RTC (synchronizing one

0x00000000

RTC’s time with another RTC’s time)
0x2C

ReservedRO

Reserved

0x00000000

Table RTC-64 Register List of Time Counter Value Read Control System
OffsetRegister Name

Attribute

Function

Initial Value

0x30

RdReq

RW

Read Request for PostCounter and PreCounter

0x00000000

0x34

RdPostCnt

RO

PostCounter Read Value at Read Request

0x00000000

0x38

RdPreCnt

RO

PreCounter Read Value at Read Request

0x00000000

0x3C

ReservedRO

Reserved

0x00000000

0x40

RtPostCnt

RO

PostCounter Read Value when RtPostCnt Register was

0x00000000

read
0x44

RtPreCnt

RO

PreCounter Read Value when RtPostCnt Register was

0x00000000

read
0x48

ReservedRO

Reserved

0x00000000

0x4C

ReservedRO

Reserved

0x00000000－184/1293－

CXD5602 User Manual

Table RTC-65 Register List of Alarm Control System
OffsetRegister name

Attribute

Function

Initial Value

0x50

SetAlmPostCnt0

RW

Comparison Value of PostCounter for Alarm0

0xFFFFFFFF

0x54

SetAlmPreCnt0

RW

Comparison Value of PostCounter for Alarm0 and Status

0x00007FFF

The status of some bits is RO.
0x58

SetAlmPostCnt1

RW

Comparison Value of PostCounter for Alarm1

0xFFFFFFFF

0x5C

SetAlmPreCnt1

RW

Comparison Value of PreCounter for Alarm1 and Status

0x00007FFF

The status of some bits is RO.
0x60

SetAlmPostCnt2

RW

Comparison Value of PostCounter for Alarm2

0xFFFFFFFF

0x64

SetAlmPreCnt2

RW

Comparison Value of PostCounter for Alarm2 and Status

0x00007FFF

The status of some bits is RO.
0x68

ReservedRO

Reserved

0x00000000

0x6C

ReservedRO

Reserved

0x00000000

0x70

AlmClrWO

Clear of Normal Alarm Flag and Error Alarm Flag

0x00000000

0x74

AlmOutEn0

RW

Enable Signal Control and Status of O(Err)Alarm0, Read

0x00000000

Value of DbgAlmOutEn0(Enable Signal Value for Alarm0 currently used by RTC)
The status of some bits is RO.
0x78

AlmOutEn1

RW

Enable Signal Control and Status of O(Err)Alarm1, Read

0x00000000

Value of DbgAlmOutEn1(Enable Signal Value for Alarm1 currently used by RTC)
The status of some bits is RO.
0x7C

AlmOutEn2

RW

Enable Signal Control and Status of O(Err)Alarm2, Read

0x00000000

Value of DbgAlmOutEn2(Enable Signal Value for Alarm2 currently used by RTC)
The status of some bits is RO.
0x80

AlmFlgRO

Normal Alarm Flag and Error Alarm Flag

0x00000000

0x84

ReservedRO

Reserved

0x00000000

0x88

ReservedRO

Reserved

0x00000000

0x8C

ReservedRO

Reserved

0x00000000

0x90

DbgSetAlmPostCnt0

RO

Read Value of DbgSetAlmCnt0[46:15]

0xFFFFFFFF(Comparison Value of PostCounter for Alarm0 currently
used by RTC)
0x94

DbgSetAlmPreCnt0

RO

Read Value of DbgSetAlmCnt0[14:0]

0x00007FFF(Comparison Value of PreCounter for Alarm0 currently usedby RTC)
0x98

DbgSetAlmPostCnt1

RO

Read Value of DbgSetAlmCnt1[46:15]－185/1293－

0xFFFFFFFF

CXD5602 User Manual(Comparison Value of PostCounter for Alarm1 currently
used by RTC)
0x9C

DbgSetAlmPreCnt1

RO

Read Value of DbgSetAlmCnt1[14:0]

0x00007FFF(Comparison Value of PreCounter for Alarm1 currently usedby RTC)
0xA0

DbgSetAlmPostCnt2

RO

Read Value of DbgSetAlmCnt2[46:15]

0xFFFFFFFF(Comparison Value of PostCounter for Alarm2 currently
used by RTC)
0xA4

DbgSetAlmPreCnt2

RO

Read Value of DbgSetAlmCnt2[14:0]

0x00007FFF(Comparison Value of PreCounter for Alarm2 currently usedby RTC)
0xA8

ReservedRO

Reserved

0x00000000

0xAC

ReservedRO

Reserved

0x00000000

Table RTC-66 Register List of Time Update Confirming System
OffsetRegister Name

Attribute

Function

Initial Value

0xB0

CntUpdateClr

WO

Clear of interrupt notifying update completion of RTC

0x00000000

Counter
0xB4

CntUpdateEn

RW

Enable Signal Control of interrupt notifying update

0x00000000

completion of RTC Counter
0xB8

CntUpdateFlg

RO

Interrupt flag notifying update completion of RTC Counter

0x00000000

0xBC

ReservedRO

Reserved

0x00000000

0xC0

DiffSignBit

RO

Sign bit of difference value between one RTC Counter and

0x00000000

other RTC Counter
0xC4

DiffPostCnt

RO

Read Value of difference value [46:15] between one RTC

0x00000000

Counter and other RTC Counter
0xC8

DiffPreCnt

RO

Read Value of difference value [14:0] between one RTC

0x00000000

Counter and other RTC Counter
0xCC

ReservedRO

Reserved

0x00000000

Table RTC-67 List of External Alarm Output and Time Synchronization Register
Absolute

Register Name

Attribute

Function

Initial Value

RTC0_RTC_CTL

RW

List of RTC0 external alarm output and time

0x00000000

Address
0x04100730

synchronization register0x41030470

RTC1_RTC_CTL

RW

List of RTC1 external alarm output and timesynchronization register－186/1293－

0x00000000

CXD5602 User Manual

3.6.5.2 Register Descriptions
By turning off the PWD_SYSIOP power supply, all register values of RTC1 (from 0x04109000 to 0x041090C8)
return to initial values. However, no register values of RTC0 (from 0x04108000 to 0x041080C8) return to initialvalues. When tuning on the PWD_SYSIOP power supply again, alarm information set in the RTC0 can be read.
The following are registers that do not return to initial values.


AlmOutEn(0/1/2).Dbg



AlmOutEn(0/1).ErrDbg



DbgSetAlmPostCnt(0/1/2).Dbg

DbgSetAlmPreCnt(0/1/2).Dbg



AlmFlg.Flg(0/1/2)



AlmFlg.ErrFlg(0/1)

WrRegPostCnt(0x00)

3.6.5.2.1
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Post
RW

15
Post
RW



bit[31:0] : Post[31:0] (PostCounter Write Value)
This is a value reflected on PostCounter of RTC when Write Request (WrRegReq) is issued, or when RTC
receives an interrupt (External Alarm Flag) from PMIC_INT.

－187/1293－

CXD5602 User Manual

WrRegPreCnt(0x04)

3.6.5.2.2
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15
Rese
rved
-



14
Pre
RW

bit[14:0] : Pre[14:0] (PreCounter Write Value)
This is a value reflected on PreCounter of RTC when Write Request (WrRegReq) is issued, or when RTC
receives External Alarm Flag.

WrRegReq(0x08)

3.6.5.2.3
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15

14

Busy

ReservedA-

RW

When you write “1” on WrRegReq.BusyA, this register issues a write request. After the write request is issued,
WrRegPostCnt values and WrRegPreCnt values are reflected on RTC Counter values. (Of RTC Counter 47 bits,
WrRegPostCnt values are reflected on higher 32 bits, and WrRegPreCnt values are reflected on lower 15 bits.)
This register is cleared to “0” after executing the request and becomes possible to issue a request again.
(OffsetReq.BusyA and RdReq.BusyA indicate similar status.)

bit[0] : BusyA (Write Request)



BusyA

Description of Functions

0

Writing 0: You cannot write “0”.

1

Writing 1: issues Write Request－188/1293－

CXD5602 User Manual

When WrReg(Post/Pre)Cnt value is reflected to (Post/Pre)Counter and Write Request
becomes possible to be issued again, this register is cleared to “0” automatically.

WrIntCtrl(0x18)

3.6.5.2.4
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

Edge

Reserved

Busy

-

RW

-

RW

Reserved
-

15



14

bit[0] : Busy (Request for waiting for External Alarm Flag)
When you write “1” on Busy, the internal RTC comes into the status of waiting for External Alarm Flag.
When the internal RTC detects the edge of the External Alarm Flag during this waiting status,
WrIntPostCnt value and WrIntPreCnt value are reflected on PostCounter and PreCounter separately, andthe internal RTC is synchronized with the external RTC.
You can cancel Request for waiting for External Alarm Flag by writing “1” on WrIntClr register.
Busy

Description of Functions

0

Writing 0: You cannot write “0”.

1

Writing 1: makes internal RTC come into the status of waiting for the External Alarm
Flag. When the internal RTC detects the External Alarm Flag during this waiting status
and WrInt(Post/Pre)Cnt value is reflected on (Post/Pre)Counter, this register iscleared to “0” automatically.

bit[8] : Edge (Positive/Negative Edge Detection of the External Alarm Flag)



Edge

Description of Functions

0

Writing 0: detects rising edges of the External Alarm Flag and synchronizes theinternal RTC with the external RTC.

1

Writing 1: detects falling edges of the External Alarm Flag and synchronizes theinternal RTC with the external RTC.

－189/1293－

CXD5602 User Manual

WrIntClr(0x1C)

3.6.5.2.5
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved-

15

14

Reserved

Busy

-

RW



bit[0] : Busy (Cancel of waiting for External Alarm Flag)
When you write “1” on Busy, this register cancels Request for waiting for External Alarm Flag
(WrIntCtrl.Busy is cleared to “0”).
Busy

Description of Functions

0

Writing 0: You cannot write “0”.

1

Writing 1: cancels a Request for waiting for External Alarm Flag. When it is canceled,this register is cleared to “0” automatically.

OffsetVal(0x20)

3.6.5.2.6
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved-

15

14

Reserved

Offset-RW

bit[7:0] : Offset[7:0] (Correction value of RTC Counter value)
This register adds Offset value to RTC PreCounter. The Offset range is from -64 to 63.
Set the register value with two’s complements. When carry or borrow to PostCounter occurs, this register
updates PostCounter.

－190/1293－

CXD5602 User Manual

OffsetReq(0x24)

3.6.5.2.7
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15

14

Busy

Reserved

A

-



RW

bit[0] : BusyA (Correction request for RTC Counter value)
This register issues a correction request for RTC Counter value. After issuing the request, it adds OffsetVal
value to RTC Counter.
BusyA

Description of Functions

0

Writing 0: You cannot write “0”.

1

Writing 1: issues a correction request for RTC. After correcting RTC Counter, thisregister is cleared to “0” when the same request becomes possible to be issued again.

－191/1293－

CXD5602 User Manual

RtcSyncReq(0x28)

3.6.5.2.8
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved-

15

14

Reserved

Req

-

RW



bit[0] : Req (Synchronization request with other RTC Counter)
When you write “1”, this register issues a synchronization request. After issuing the request, this register
makes one RTC import the other internal RTC counter value to its own value, and makes it synchronize withthe other RTC. (Example: When this register issues a synchronization request to RTC0, RTC0 imports
RTC1’s RTC Counter value and is synchronized with RTC1.)
Req

Description of Functions

0

Writing 0: You cannot write “0”.

1

Writing 1: issues a synchronization request with the other RTC Counter. Aftercompleting the synchronization, this register is cleared to “0” automatically when thesame request becomes possible to be issued again.

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CXD5602 User Manual

RdReq(0x30)

3.6.5.2.9
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15

14

Busy

ReservedA-

RW

 bit[0] : BusyA (Read Request)
When you write “1”, this register issues a Read Request. Once the Read Request is issued, RTC Counter value
at the time when it is issued can be read from RdPostCnt and RdPreCnt.
BusyA

Description of Functions

0

Writing 0: You cannot write “0”.

1

Writing 1: issues a Read Request. After reflecting values on RdPostCnt and
RdPreCnt, this register is cleared to “0” automatically when the same request
becomes possible to be issued again.

RdPostCnt(0x34)

3.6.5.2.10
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Post
RO

15
Post
RO

 bit[31:0] : Post[31:0] (PostCounter value at the time of Read Request )By reading this register, you can see the PostCounter value at the point of time when the read request wasissued.

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CXD5602 User Manual

RdPreCnt(0x38)

3.6.5.2.11
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15
Rese
rved
-



14
Pre
RO

bit[14:0] : Pre[14:0] (PreCounter value at the time of Read Request)
By reading this register, you can see the PreCounter value at the point of time when the read request wasissued.

－194/1293－

CXD5602 User Manual

RtPostCnt(0x40)

3.6.5.2.12
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Post
RO

15
Post
RO



bit[31:0] : Post[31:0] (PostCounter value when RtPostCnt was read)
The following are differences from Rd(Post/Pre)Cnt.



There is no need to issue a Read Request (RdReq).



After you write “1” on RdReq, there is no restriction to wait for RdReq to become 0.

Restriction on the use of this registerAS for Rt(Post/Pre)Cnt, read RtPostCnt before reading RtPreCnt.



If relation between CK_APB and CK_RTC (RTC Clock (32.768kHz)) is “frequency of CK_APB <frequency of CK_RTC ×10”, do not read Rt(Post/Pre)Cnt. The value cannot be guaranteed.

RtPreCnt(0x44)

3.6.5.2.13
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15
Rese
rved
-



14
Pre
RO

bit[14:0] : Pre[14:0] (PreCounter value when PostCounter was read)
By reading this register, you can see the PreCounter value at the point of time when you read RtPostCnt.

－195/1293－

CXD5602 User Manual

SetAlmPostCnt0(0x50)

3.6.5.2.14
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Post
RW

15
Post
RW



bit[31:0] : Post[31:0] (Comparison Value of PostCounter for AlmFlg.Flg0 and AlmFlg.ErrFlg0)
This register sets Operation time (PostCounter) of Alarm0.
This register compares SetAlm(Post/Pre)Cnt0 with RTC Counter (PostCounter and PreCounter) by using
absolute value, and generates Normal Alarm0 or Error Alarm0.
Normal Alarm0 or Error Alarm0 is generated when the RTC Counter value meets the following conditions.


Normal Alarm: is generated if value written on SetAlm(Post/Pre){0,1} matches RTC Counter value

Error Alarm: is generated if written value is smaller than RTC Counter value when SetAlmPre{0,1} isset

Restriction on the use of this register
AS for SetAlm(Post/Pre)Cnt{0,1,2}, write values on SetAlmPostCnt{0,1,2} before writing values on
SetAlmPreCnt{0,1,2}.

－196/1293－

CXD5602 User Manual

SetAlmPreCnt0(0x54)

3.6.5.2.15
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Reserved

Busy

-

RO

15
Rese
rved
-



14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Pre
RW

bit[14:0] : Pre[14:0] (Comparison value of PreCounter for AlmFlg.Flg0 and AlmFlg.ErrFlg0)
This register sets operation time (PreCounter) of Alarm0.
It takes time to reflect a new Alarm Operation time. During reflecting, do not update the Alarm Operation
time. You can check whether it is in the process of reflecting by using Busy.



bit[16] : Busy (SetAlmPreCnt0 Write Busy status)
This register indicates how far SetAlm(Post/Pre)Cnt0 register is reflected.
When

Busy

indicates

“1”,

the

registerisreflecting

Alarm

Operationtime(meansthat

SetAlm(Post/Pre)Cnt0 must not be updated). Once the reflection is completed, Busy becomes “0”automatically.
Busy

Description of Functions

0

Reading 0: Alarm Operation time is not set or reflected completely.

1

Reading 1: Alarm Operation time is being reflected. SetAlm(Post/Pre)Cnt0 must not
be written.

－197/1293－

CXD5602 User Manual

SetAlmPostCnt1(0x58)

3.6.5.2.16
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Post
RW

15
Post
RW



bit[31:0] : Post[31:0] (Comparison Value of PostCounter for AlmFlg.Flg1 and AlmFlg.ErrFlg1)
This register sets Operation time (PostCounter) of Alarm1.
This register compares SetAlm（Post/Pre）Cnt1 with RTC Counter (PostCounter and PreCounter) by using
absolute value, and generates Normal Alarm1 or Error Alarm1.

SetAlmPreCnt1(0x5C)

3.6.5.2.17
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Reserved

Busy

-

RO

15
Rese
rved
-



14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Pre
RW

bit[31:0] :Pre[14:0] (Comparison Value of PreCounter for AlmFlg.Flg1 and AlmFlg.ErrFlg1)
This register sets Operation Time (PreCounter) of the Alarm1.
It takes time to reflect a new Alarm Operation time. During reflecting, do not update the Alarm Operation
time. You can check whether it is in the process of reflecting by using Busy.



bit[16] : Busy (SetAlmPreCnt1 Write Busy status)
When

Busy

indicates

“1”,

the

registerisreflecting

Alarm

Operationtime(meansthat

SetAlm(Post/Pre)Cnt1 must not be updated). Once the reflection is completed, Busy becomes “0”automatically.
Busy

Description of Functions

0

Reading 0: Alarm Operation time is not set or reflected completely.

－198/1293－

CXD5602 User Manual

Reading 1: Alarm Operation time is being reflected. SetAlm(Post/Pre)Cnt1 must not

1

be written.

SetAlmPostCnt2(0x60)

3.6.5.2.18
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Post
RW

15
Post
RW



bit[31:0] : Post[31:0] (Comparison Value of PostCounter for AlmFlg.Flg2)
This register sets Operation time (PostCounter) of Alarm2.
The function of Alarm2 is different from that of Alarm0 and Alarm1.
AlmFlg.Flg2 is asserted when time passes to the value set on SetAlm(Post/Pre)Cnt2, starting from the time
written on SetAlmPreCnt2.

SetAlmPreCnt2(0x64)

3.6.5.2.19
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Reserved

Busy

-

RO

15
Rese
rved
-

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Pre
RW

bit[31:0] : Pre[14:0] (Comparison Value of PostCounter for AlmFlg.Flg2)
This register sets Operation Time (PreCounter) of Alarm2.
It takes time to reflect a new Alarm Operation time. During reflecting, do not update the Alarm Operation
time. You can check whether it is in the process of reflecting by using Busy.


bit[16] : Busy (SetAlmPreCnt2 Write Busy status)
When

Busy

indicates

“1”,

the

registerisreflecting－199/1293－

Alarm

Operationtime(meansthat

CXD5602 User Manual

SetAlm(Post/Pre)Cnt2 must not be updated). Once the reflection is completed, Busy becomes “0”automatically.
Busy

Description of Functions

0

Reading 0: Alarm Operation time is not set or reflected completely.

1

Reading 1: Alarm Operation time is being reflected. SetAlm(Post/Pre)Cnt2 must not
be written.

AlmClr(0x70)

3.6.5.2.20
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Err

Err

Flg1

Flg0

WO

WO

2

1

0

Reserved

Flg2

Flg1

Flg0

-

WO

WO

WO

Reserved
-

15

14

13

12

11

10

9

8

7

6

5

4

3

When an Alarm occurs, an Alarm Interrupt is asserted (set). When a Clear Register is written, the Alarm Interrupt
can be deasserted (reset) instantly.


bit[0] : Flg0 (Clear of Normal Alarm Flag0)
When you write “1” on AlmClr.Flg0, Normal Alarm0 Interrupt is deasserted, and Normal Alarm
Flag0 is cleared.
Flg0

Description of Functions

0

Writing 0: invalid

1

Writing 1: deasserts Normal Alarm Flag0
When Normal Alarm Flag0 is deasserted, this register is cleared to “0” automatically.



bit[1] : Flg1 (Clear of Normal Alarm Flag1)
Flg1

Description of Functions

0

Writing 0: invalid

1

Writing 1: deasserts Normal Alarm Flag1
When Normal Alarm Flag1 is deasserted, this register is cleared to “0” automatically.



bit[1] : Flg1 (Clear of Alarm Flag2)
Flg2

Description of Functions－200/1293－

CXD5602 User Manual0

Writing 0: invalid

1

Writing 1: deasserts Normal Alarm Flag2
When Normal Alarm Flag2 is deasserted, this register is cleared to “0” automatically.



bit[16] : ErrFlg0 (Clear of Error Alarm Flag0)
When you write “1” on AlmClr.Flg0, Error Alarm0 Interrupt is deasserted, and Error Alarm Flag0 iscleared.
ErrFlg0

Description of Functions

0

Writing 0: invalid

1

Writing 1: deasserts Interrupt of Error Alarm Flag0
When Error Alarm Flag0 is deasserted, this register is cleared to “0” automatically.



bit[17] : ErrFlg1 (Clear of Error Alarm Flag1)
ErrFlg1

Description of Functions

0

Writing 0: invalid

1

Writing 1: deasserts Interrupt of Error Alarm Flag1
When Error Alarm Flag1 is deasserted, this register is cleared to “0” automatically.

AlmOutEn0(0x74)

3.6.5.2.21
31
Err
Dbg

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Err

Reserved

RO

-

15

14

Dbg
RO

16

En
RW

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

Busy

Reserved

En

-

RO

-

RW

bit[0] : En (Enable Signal for Normal Alarm0 Interrupt)
This register does the settings for notifying processor of Normal Alarm Flag0.
It takes time to reflect the settings. During reflecting, do not update the settings. You can check whether it isin the process of reflecting by using Busy.
En

Description of Functions

0

Writing 0: disables an interrupt request to processor.
Even if conditions are met, interrupt will be deasserted.

1

Writing 1: enables an interrupt request to processor.

－201/1293－

CXD5602 User Manual

If conditions are met, interrupt will be asserted.

If 1'b0 is set on En, an interrupt request is disabled. However, status register AlmFlg.Flg0 transitions to 1'b1 if conditions are met.


bit[8] : Busy (Write Busy Status)
This register indicates how far AlmOutEn0 register is reflected.
When Busy indicates “1”, the register is reflecting Enable Signal (means that AlmOutEn0 must not be
updated). Once the reflection is completed, Busy becomes “0” automatically.



Busy

Description of Functions

0

Reading 0: AlmOutEn0 is not set or reflected completely.

1

Reading 1: AlmOutEn0 is being reflected. AlmOutEn0 must not be written.

bit[15] : Dbg (Enable Signal Value for current Normal Alarm0 Interrupt)
This register is used for debugging. By reading this register, you can see Enable Signal value for the Normal
Alarm0 Interrupt that is currently used in RTC. By using this register, you can check whether the set value
has been normally reflected on AlmOutEn0.En or not.



bit[16] : ErrEn (Enable Signal for Error Alarm0 Interrupt)
This register does the settings for notifying processor of Error Alarm Flag0.
ErrEn

Description of Functions

0

Writing 0: disables an interrupt request to processor.
Even if conditions are met, interrupt will be deasserted.

1

Writing 1: enables an interrupt request to processor.
If conditions are met, interrupt will be asserted.

If 1'b0 is set on ErrEn, an interrupt request is disabled. However, status register AlmFlg.ErrFlg0 transitions to 1'b1 if conditions
are met.



bit[31] : ErrDbg (Enable Signal Value for current Error Alarm0 Interrupt)
This register is used for debugging. By reading this register, you can see Enable Signal value for the Error
Alarm0 Interrupt that is currently used in RTC. By using this register, you can check whether the set value
has been normally reflected on AlmOutEn0.ErrEn or not.

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CXD5602 User Manual

AlmOutEn1(0x78)

3.6.5.2.22
31
Err
Dbg

30

28

27

26

25

24

23

22

21

20

19

18

17

-

15

14

Dbg
RO

16
Err

Reserved

RO



29

En
RW

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

Busy

Reserved

En

-

RO

-

RW

bit[0] : En (Enable Signal for Normal Alarm1 Interrupt)
This register does the settings for notifying processor of Normal Alarm Flag1.
It takes time to reflect the settings. During reflecting, do not update the settings. You can check whether it isin the process of reflecting by using Busy.
En

Description of Functions

0

Writing 0: disables an interrupt request to processor.
Even if conditions are met, interrupt will be deasserted.

1

Writing 1: enables an interrupt request to processor.
If conditions are met, interrupt will be asserted.

If 1'b0 is set on En, an interrupt request is disabled. However, status register AlmFlg.Flg1 transitions to 1'b1 if conditions are met.


bit[8] : Busy (Write Busy Status)
This register indicates how far AlmOutEn1register is reflected.
When Busy indicates “1”, the register is reflecting Enable Signal (means that AlmOutEn1 must not be
updated). Once the reflection is completed, Busy becomes “0” automatically.



Busy

Description of Functions

0

Reading 0: AlmOutEn1 is not set or reflected completely.

1

Reading 1: AlmOutEn1 is being reflected. AlmOutEn1 must not be written.

bit[15] : Dbg (Enable Signal Value for current Normal Alarm1 Interrupt)
This register is used for debugging. By reading this register, you can see Enable Signal value for the Normal
Alarm1 Interrupt that is currently used in RTC. By using this register, you can check whether the set value
has been normally reflected on AlmOutEn1.En or not.



bit[16] : ErrEn (Enable Signal for Error Alarm1 Interrupt)
This register does the settings for notifying processor of Error Alarm Flag1.

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CXD5602 User Manual

ErrEn

Description of Functions

0

Writing 0: disables an interrupt request to processor.
Even if conditions are met, interrupt will be deasserted.

1

Writing 1: enables an interrupt request to processor.
If conditions are met, interrupt will be asserted.

If 1'b0 is set on ErrEn, an interrupt request is disabled. However, status register AlmFlg.ErrFlg1 transitions to 1'b1 if conditions
are met.



bit[31] : ErrDbg (Current Enable Signal Value)
This register is used for debugging. By reading this register, you can see Enable Signal value for the Error
Alarm1 Interrupt that is currently used in RTC. By using this register, you can check whether the set value
has been normally reflected on AlmOutEn1.ErrEn or not.

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CXD5602 User Manual

AlmOutEn2(0x7C)

3.6.5.2.23
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15

14

Dbg

Reserved

Busy

Reserved

En

RO

-

RO

-

RW



bit[0] : En (Enable Signal for Normal Alarm2 Interrupt)
This register does the settings for notifying processor of Normal Alarm Flag2.
It takes time to reflect the settings. During reflecting, do not update the settings. You can check whether it isin the process of reflecting by using Busy.
En

Description of Functions

0

Writing 0: disables an interrupt request to processor.
Even if conditions are met, interrupt will be deasserted.

1

Writing 1: enables an interrupt request to processor.
If conditions are met, interrupt will be asserted.

If 1'b0 is set on En, an interrupt request is disabled. However, status register AlmFlg.Flg2 transitions to 1'b1 if conditions are met.


bit[8] : Busy (Write Busy Status)
This register indicates how far AlmOutEn2 register is reflected.
When Busy indicates “1”, the register is reflecting Enable Signal (means that AlmOutEn2 must not be
updated). Once the reflection is completed, Busy becomes “0” automatically.



Busy

Description of Functions

0

Reading 0: AlmOutEn2 is not set or reflected completely.

1

Reading 1: AlmOutEn2 is being reflected. AlmOutEn2 must not be written.

bit[15] : Dbg (Enable Signal Value for current Normal Alarm2 Interrupt)
This register is used for debugging. By reading this register, you can see Enable Signal value for the Normal
Alarm2 Interrupt that is currently used in RTC. By using this register, you can check whether the set value
has been normally reflected on AlmOutEn2.En or not.

－205/1293－

CXD5602 User Manual

AlmFlg(0x80)

3.6.5.2.24
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Err

Err

Flg1

Flg0

RO

RO

2

1

0

Reserved

Flg2

Flg1

Flg0

-

RO

RO

RO

Reserved
-

15

14

13

12

11

10

9

8

7

6

5

4

3

By reading this register, you can see Normal Alarm and Error Alarm Flag (Alarm Interrupt value before
controlling registers Enabled or Disabled by using AlmOutEn). When the conditions are as described in the Table
RTC-68 below, an Alarm occurs. When the Alarm is asserted, AlmFlg becomes “1”. If you want to clear AlmFlg
to “0”, write “1” on AlmClr.
Table RTC-68 Alarm Occurrence Condition
Register

Alarm Occurrence Condition

Flg0

when set value of Alarm0 matches RTC Counter value

Flg1

when set value of Alarm1 matches RTC Counter value

Flg2

when time passes to the set value of Alarm2, based on the RTC Counter value at the time of being written on
SetAlmPreCnt2

ErrFlg0

when set value of Alarm0 at the time of being written on SetAlmPreCnt0 is smaller than RTC Counter value

ErrFlg1

when set value of Alarm1 at the time of being written on SetAlmPreCnt1 is smaller than RTC Counter value

Note:
RTC Counter={PostCounter[31:0], PreCounter[14:0] }Set value of Alarm{0,1,2}= {SetAlmPostCnt{0,1,2} [31:0], SetAlmPreCnt{0,1,2} [14:0] }

bit[0] : Flg0 (Normal Alarm Flag0)
Flg0

Description of Functions

0

Normal Alarm0 Interrupt is deasserted.

1

Normal Alarm0 Interrupt is asserted.

bit[1] : Flg1 (Normal Alarm Flag1)
Flg1

Description of Functions

0

Normal Alarm1 Interrupt is deasserted.

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CXD5602 User Manual

1







Normal Alarm1 Interrupt is asserted.

bit[2] : Flg2 (Normal Alarm Flag2)
Flg2

Description of Functions

0

Normal Alarm2 Interrupt is deasserted.

1

Normal Alarm2 Interrupt is asserted.

bit[0] : ErrFlg0 (Error Alarm Flag0)
Flg0

Description of Functions

0

Error Alarm0 Interrupt is deasserted.

1

Error Alarm0 Interrupt is asserted.

bit[1] : ErrFlg1 (Error Alarm Flag1)
Flg1

Description of Functions

0

Error Alarm1 Interrupt is deasserted.

1

Error Alarm1 Interrupt is asserted.

DbgSetAlmPostCnt0(0x90)

3.6.5.2.25
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Dbg
RW

15
Dbg
RW

bit[31:0] : Dbg[31:0] (Current SetAlmPostCnt0 value)This register is used for debugging. By reading this register, you can see SetAlmPostCnt0 value that iscurrently used in RTC. By using this register, you can check whether the set value has been normallyreflected on SetAlmPostCnt0 or not.

DbgSetAlmPreCnt0(0x94)

3.6.5.2.26
31

30

29

28

27

26

25

24

23

22

Reserved-－207/1293－

21

20

19

18

17

16

CXD5602 User Manual

15
Rese
rved
-



14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Dbg
RW

bit[14:0] : Dbg[14:0] (Current SetAlmPreCnt0 value)
This register is used for debugging. By reading this register, you can see SetAlmPreCnt0 Value that iscurrently used in RTC. By using this register, you can check whether the set value has been normallyreflected on SetAlmPreCnt0 or not.

DbgSetAlmPostCnt1(0x98)

3.6.5.2.27
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Dbg
RW

15
Dbg
RW



bit[31:0] : Dbg[31:0] (Current SetAlmPostCnt1 value)
This register is used for debugging. By reading this register, you can see SetAlmPostCnt1 value that iscurrently used in RTC. By using this register, you can check whether the set value has been normallyreflected on SetAlmPostCnt1 or not.

DbgSetAlmPreCnt1(0x9C)

3.6.5.2.28
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15
Rese
rved
-



14
Dbg
RW

bit[14:0] : Dbg[14:0] (Current SetAlmPreCnt1 value)
This register is used for debugging. By reading this register, you can see SetAlmPreCnt1 value that is－208/1293－

CXD5602 User Manualcurrently used in RTC. By using this register, you can check whether the set value has been normallyreflected on SetAlmPreCnt1 or not.

DbgSetAlmPostCnt2(0xA0)

3.6.5.2.29
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Dbg
RW

15
Dbg
RW



bit[31:0] : Dbg[31:0] (Current SetAlmPostCnt2 value)
This register is used for debugging. By reading this register, you can see comparison value of PostCounterfor Alarm2 that is currently used in RTC. (means current SetAlmPostCnt2 plus RTC Counter value at thetime when SetAlmPreCnt2 was written).
By using this register, you can check whether the set value has been normally reflected on SetAlmPostCnt2
or not.

DbgSetAlmPreCnt2(0xA4)

3.6.5.2.30
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15
Rese
rved
-



14
Pre
RW

bit[14:0] : Dbg[14:0] (Current SetAlmPreCnt2 Value)
This register is used for debugging. By reading this register, you can see comparison value of PostCounterfor Alarm2 that is currently used in RTC. (means current SetAlmPreCnt2 plus RTC Counter value at thetime when SetAlmPreCnt2 was written)
By using this register, you can check whether the set value has been normally reflected on SetAlmPreCnt2
or not.

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CXD5602 User Manual

CntUpdateClr(0xB0)

3.6.5.2.31
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved-

15

14

Reserved

Flg

-

WO

When RTC Counter has been updated completely, the interrupt flag notifying that RTC Counter has been updated
is asserted (set). If Clear Register is written, the interrupt flag can be deasserted (reset) instantly.
As for conditions that the interrupt flag notifying that RTC Counter has been updated is asserted, refer to
CntUpdateFlg(0xB8)


bit[0] : Flg (Clear of the interrupt flag notifying that RTC Counter has been updated)
When you write “1” on CntUpdateClr.Flg, the interrupt flag notifying that RTC Counter has been updated
is deasserted and cleared to “0”.
Flg

Description of Functions

0

Writing 0: invalid

1

Writing 1: deasserts interrupt flag notifying that RTC Counter has been updated

CntUpdateEn(0xB4)

3.6.5.2.32
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved-

15

14

Reserved

En

-

RW



bit[0] : En (Enable Signal for the interrupt flag notifying that RTC Counter has been updated)
This register does the settings for notifying processor that RTC Counter has been updated.
En

Description of Functions

0

Writing 0: disables an interrupt request to processor.

1

Writing 1: enables an interrupt request to processor.

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CXD5602 User Manual

CntUpdateFlg(0xB8)

3.6.5.2.33
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved-

15

14

Reserved

Flg

-

RO

By reading this register, you can see the interrupt flag notifying that RTC Counter has been updated (Interrupt
value before being controlled Enabled or Disabled by CntUpdateEn). If RTC Counter is updated under thefollowing conditions, CntUpdateFlg becomes “1”. If you want to clear CntUpdateFlg to “0”, write “1” on
CntUpdateClr.


Update of RTC Counter valueSynchronization of external RTC

Synchronization between internal RTCs



Correction of RTC Counter value－211/1293－

CXD5602 User Manual

DiffSignBit(0xC0)

3.6.5.2.34
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved-

15

14

Reserved

Val

-

RO



bit[0] : Val (sign bit of difference value from other RTC Counter)
By reading this register, you can see sign when difference (means one RTC Counter (47 bits) minus other
RTC Counter (47 bits)) is calculated.
Val

Description of Functions

0

Positive

1

Negative

Restriction on the use of this register

Check the interrupt flag notifying that RTC Counter has been updated (CntUpdateFlg(0xB8)) before
reading DiffSignBit, DiffPostCnt, and DiffPretCnt.

DiffPostCnt(0xC4)

3.6.5.2.35
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Val
RW

15
Val
RW



bit[31:0] : Val[31:0] (Difference from other RTC Counter value)
By reading this register, you can see higher 32 bits of the difference (47 bits) (means one RTC Counter (47bits) minus other RTC Counter (47 bits)).

－212/1293－

CXD5602 User Manual

DiffPreCnt (0xC8)

3.6.5.2.36
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15
Rese
rved
-



14
Val
RW

bit[14:0] : Val[14:0] (Difference from other RTC Counter value)
By reading this register, you can see lower 15 bits of the difference (47 bits) (means one RTC Counter (47bits) minus other RTC Counter (47 bits)).

RTC0_RTC_CTL (0x04100730)

3.6.5.2.37
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15

14

CLK

EXT

NEG
Reserved

EDG

Reserved

SYNC_SEL

Reserved

E_E



RW

M_P

Reserved

EXTALM_S
EL

OL

N
-

AL

-

RW

-

RW

-

RW

bit[1:0] : EXTALM_SEL [1:0] (External Alarm Output Select Signal)
This register selects one AlarmFlag from AlarmFlag0, AlarmFlag1, and AlarmFlag2 as an Alarm output
outside (RTC0_ExtAlm).
EXTALM_SEL

Description of Functions

0

AlarmFlag0(AlmFlg,Flg0) is used as an External Output Alarm (RTC0_ExtAlm).

1

AlarmFlag1(AlmFlg,Flg1) is used as an External Output Alarm (RTC0_ExtAlm).

2

AlarmFlag2(AlmFlg,Flg2) is used as an External Output Alarm (RTC0_ExtAlm).

3

0 is output as an External Output Alarm (RTC0_ExtAlm). (When EXTALM_POL indicates “0”)－213/1293－

CXD5602 User Manual

EXTALM_SEL

Description of Functions
1 is output as an External Output Alarm (RTC0_ExtAlm). (When EXTALM_POL indicates “1”)

bit[4] : EXTALM_POL (External Alarm Output Select Signal)
This register sets signal logic (positive logic or negative logic) of External Output Alarm.



EXTALM_POL

Description of Functions

0

outputs an External Output Alarm (RTC0_ExtAlm) signal in positive logic

1

outputs an External Output Alarm (RTC0_ExtAlm) signal in negative logic

bit[9:8] : SYNC_SEL [1:0] (External Alarm Output Select Signal)
This register selects one Alarm used as a trigger of Time Synchronization.
EXTALM_SEL

Description of Functions

0

RTC0_ExtAlm is used as a trigger of Time Synchronization.

1

RTC1_ExtAlm is used as a trigger of Time Synchronization.

2

When IOCSYS_IOMD0.PMIC_INT indicates 2, this alarm is used. For details, refer to Chapter
3.1.4.3.2.

3

When IOCSYS_IOMD0.PMIC_INT indicates 3, this alarm is used. For details, refer to Chapter
3.1.4.3.3.

bit[12] : CLKNEGEDGE_EN (Inverted Clock Setting)

By using this register, External Output Alarm and Time Synchronization Trigger Signal are set whether
to synchronize at the falling edge of the clock.
EXTALM_POL

Description of Functions

0

External Output Alarm and Time Synchronization are performed at the rising edge of the clock.
External Output Alarm and Time Synchronization Trigger Signal synchronize to usual clock.

1

External Output Alarm and Time Synchronization are performed at the falling edge of the clock.
External Output Alarm and Time Synchronization Trigger Signal synchronize to inverted clock(falling edge of the usual clock).

－214/1293－

CXD5602 User Manual

RTC1_RTC_CTL (0x04100730)

3.6.5.2.38
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved
-

15

14

CLK

EXT

NEG
Reserved

EDG

Reserved

SYNC_SEL

Reserved

E_E



RW

M_P

Reserved

EXTALM_S
EL

OL

N
-

AL

-

RW

-

RW

-

RW

bit[1:0] : EXTALM_SEL [1:0] (External Alarm Output Select Signal)
This register selects one AlarmFlag from AlarmFlag0, AlarmFlag1, and AlarmFlag2 as an Alarm output
outside (RTC1_ExtAlm).
EXTALM_SEL

Description of Functions

0

AlarmFlag0 is used as an External Output Alarm (RTC1_ExtAlm).

1

AlarmFlag1 is used as an External Output Alarm (RTC1_ExtAlm).

2

AlarmFlag2 is used as an External Output Alarm (RTC1_ExtAlm).

3

0 is output as an External Output Alarm (RTC0_ExtAlm).
(When EXTALM_POL indicates “0”)1 is output as an External Output Alarm (RTC0_ExtAlm).
(When EXTALM_POL indicates “1”)

bit[4] : EXTALM_POL (External Alarm Output Select Signal)
This register sets signal logic (positive logic or negative logic) of External Output Alarm.



EXTALM_POL

Description of Functions

0

outputs an External Output Alarm (RTC1_ExtAlm) signal using positive logic

1

outputs an External Output Alarm (RTC1_ExtAlm) signal using negative logic

bit[9:8] : SYNC_SEL [1:0] (External Alarm Output Select Signal)
This register selects one Alarm used as a trigger of Time Synchronization.
EXTALM_SEL

Description of Functions

0

RTC0_ExtAlm is used as a trigger of Time Synchronization.

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CXD5602 User Manual

EXTALM_SEL

Description of Functions

1

RTC1_ExtAlm is used as a trigger of Time Synchronization.

2

This alarm is used when IOCSYS_IOMD0.PMIC_INT indicates 2. For details, refer to Chapter
3.1.4.3.2.

3This alarm is used when IOCSYS_IOMD0.PMIC_INT indicates 3. For details, refer to Chapter
3.1.4.3.3.



bit[12] : CLKNEGEDGE_EN (Inverted Clock Setting)
By using this register, External Output Alarm and Time Synchronization Trigger Signal are set whether tosynchronize at the falling edge of the clock.
EXTALM_POL

Description of Functions

0

External Output Alarm and Time Synchronization are performed at the rising edgeof the clock.
External Output Alarm and Time Synchronization Trigger Signal synchronize tousual clock (rising edge of the clock).

1

External Output Alarm and Time Synchronization are performed at the falling edgeof the clock.
External Output Alarm and Time Synchronization Trigger Signal synchronize to
inverted clock (falling edge of the usual clock).

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CXD5602 User Manual

3.6.5.3 Control Flow
3.6.5.3.1

Update of RTC Counter Value

This function is used when you reflect values, which are set by registers, on RTC Counter value(PostCounter[31:0], PreCounter[14:0]). The sequence is as follows.
1. On WrRegPostCnt register, write a value that you want to reflect on PostCounter.
2. On WrRegPreCnt register, write a value that you want to reflect on PreCounter.
3. Write “1” on WrRegReq.BusyA register.
You can check whether RTC Counter value has been updated in the following two ways.


performing polling to WrRegReq.BusyA until it returns to “0”receiving interrupt request CntUpdateFlg which means that RTC Counter has been updated

3.6.5.3.2

Correction of RTC Counter Value

This function is used to correct RTC Counter values. You can set corrected RTC Counter values by providing
current RTC Counter value with relative values. The sequence is as follows.
1. Write a correction value on OffsetVal register.
Correction values must be written with two’s complements.
2. Write “1” on OffsetReq.BusyA register.
You can check whether RTC Counter value has been corrected in the following two ways.


performing polling to OffsetReq.BusyA until it returns to “0”.



receiving interrupt request CntUpdateFlg which means that RTC Counter has been updated－217/1293－

CXD5602 User Manual

3.6.5.3.3

Synchronization of External RTC

Synchronization of External RTC is a function that sets time of RTC inside CXD5602 by receiving interrupts
from outside including PMIC (PMIC_INT).
Synchronizing CXD5602 with CXD5247
The sequence when CXD5602 (hereinafter called the LSI) is synchronized with CXD5247 (hereinafter called thePMIC) is described below. As frequency and synchronizing timing depend on connected PMIC setting, adjust thetime to synchronize in accordance with PMIC.
1. PMU confirms RTC Counter value of PMIC.
2. Set the time when PMIC outputs External Alarm Flag (Interrupt from PMIC_INT).
For example, when the time that you want to synchronize is Y[46:0], set Y[46:6]-1 as the time that External
Alarm Flag is output.
(Y must be future time value compared with the RTC Counter value that was confirmed in 1 above.)
3. On WrReg(Post/Pre)Cnt register, write the time Y[46:0]+0x3+Δ that synchronizes with internal RTC.Δ is adifference between the LSI and the PMIC. For details, refer to chapter “Difference Calculation between
CXD5602 and CXD5247”.
When Δ is 0x0, calculate the formula replacing the Δ with 0x40. When the synchronization is performed
between internal RTCs, calculate the formula replacing the Δ with 0x40 at all times.
The following are examples of setting synchronizing internal RTC with external RTC.
Table RTC-69 Examples of Setting Synchronizing Internal RTC with External RTC Synchronization Setting
DesiredTime

OutputTime

ofDifference Δ between

RTC Synchronization Time SettingforExternal Alarm Flag

the LSI and PMIC

for the LSI

Synchronization

Y[46:6]-1

0x00 ~ 0x3F

(WrReg(Post/Pre)Cnt)

Y[46:0]
0x100

0x140

Y[46:0]+0x03+ Δ
0x3

0x4

0x00

0x143 ( = 0x100 + 0x03 + 0x40 )

0x01

0x104 ( = 0x100 + 0x03 + 0x01 )0x02

0x105 ( = 0x100 + 0x03 + 0x02 )

…

…

0x3E

0x141 ( = 0x100 + 0x03 + 0x3E )

0x3F

0x142 ( = 0x100 + 0x03 + 0x3F )0x00

0x183 ( = 0x140 + 0x03 + 0x40 )

0x01

0x144 ( = 0x140 + 0x03 + 0x01 )0x02

0x145 ( = 0x140 + 0x03 + 0x02 )

…

…

0x3E

0x181 ( = 0x140 + 0x03 + 0x3E )0x3F

0x182 ( = 0x140 + 0x03 + 0x3F )－218/1293－

CXD5602 User Manual

4. Write “1” on WrIntCtrl.Busy register.
Receiving PMIC External Alarm from PMIC_INT, synchronization between RTC in the PMIC and RTC in
the CXD5602 will be completed on the time (Y[46:6]-1) designated in 2 above. Once synchronization has
been completed, WrIntCtrl.Busy becomes “0”.
WrRegPostCnt value is reflected on PostCounter, and WrRegPreCnt value is reflected on PreCounter.
By using interrupt CntUpdateFlg notifying that RTC Counter has been updated, you can check whether thesynchronization has been completed or not.
5. Clear PMIC External Alarm Flag.
Synchronizing CXD5247 with CXD5602
The following is the synchronization sequence when CXD5602 (hereinafter called LSI) is combined withCXD5247 (hereinafter called PMIC).
1. Read RTC Counter value of the LSI by using Rt(Post/Pre)Cnt.
Set the time when Interrupt is output to PMIC by using RTCx_ExtAlm (hereinafter called External Output
Alarm).
For alarm time setting, refer to “Alarm Output Setting”, and for Output Selection of External Output Alarm,refer to “RTC0_RTC_CTL (0x04100730).”
If you want to synchronize the value of CXD5602 with CXD5247 when the value of{PostCounter[31:0],PreCounter[14:0]} has reached X[46:0], the time to output External Output Alarm to
CXD5247 will be set as follows:For

example,when

EXTALM_SEL

is

set

as

2,

the

setting

value

of{SetAlmPostCnt2[31:0],SetAlmPreCnt2[14:0]} will be upper 41 bits = X[46:6]-1, and lower 6 bits = 0x3F.
X must be future time value compared with RTC Counter value read out in 1 above.
Note:
The followings are settings of External Output Alarm synchronized with X[46:0]=0xFFFC00

Time to output
Time to output: [46:6]=X[46:6]-1=0x3FFF-0x1=0x3FFE

Time to output: [5:0]= 0x3F

Setting of time to output External Output Alarm (when Normal Alarm0 is used)

SetAlmPostCnt0[31:0]= Time to output [46:15]=0x1F



SetAlmPreCnt0[14:0]= Time to output [14:0]=0x7FBF

2. On PMIC, set the time X[46:6]+3 , which the PMIC is synchronized with the RTC of the LSI.
At the set time described in 2 above, RTC inside the LSI outputs External Alarm Flag to PMIC, andsynchronization of PMIC with the LSI is completed.

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CXD5602 User Manual

Difference Calculation between CXD5602 and CXD5247
RTC of CXD5602 operates at 32.7 kHz clock frequency. Meanwhile, RTC of CXD5247 operates at 512 Hz clock
frequency. For this reason, there might be time difference between the PMIC and the LSI when CXD5247(hereinafter called PMIC) is synchronized with CXD5602 (hereinafter called LSI). Accordingly, calculate thedifference Δ in advance. Then, set the time for the synchronization taking into account it. How to calculate thedifference Δ is shown below.
1. Set the time that External Alarm Flag is output from PMIC to the LSI using the offset time.
PMIC will output External Alarm Flag to the LSI at the set time.
2. Right after receiving External Alarm Flag, the LSI reads RTC Counter value inside RTC by using
Rt(Post/Pre)Cnt.
3. Hold the lower 6 bits of RtPreCnt as difference Δ between PMIC and the LSI.
Hold difference Δ in Flash Memories or the like before getting into Deep Sleep mode.
4. Clear the PMIC External Alarm Flag.

3.6.5.3.4

Synchronization Between Internal RTCs

This function is used when synchronization of time counter value is performed between RTC0 and RTC1. When asynchronization request is issued to one RTC, it takes in the RTC Counter value of another RTC and gets
synchronized with another RTC.
When you synchronize RTC0 with RTC Counter value of RTC1, write “1” on RtcSyncReq of RTC0.
When you synchronize RTC1 with RTC Counter value of RTC0, write “1” on RtcSyncReq of RTC1.
You can check whether synchronization has been completed in the following two ways.


polling to WrRegReq of one RTC, which wrote 1 on RtcSyncReq register, and confirming that it
returns to “0”receiving interrupt request CntUpdateFlg which means that RTC has been updated

3.6.5.3.5

Alarm Output SettingThis function is used to set time for Alarm Output. The sequence is as follows taking Alarm0 as an example.
When you want to use Alarm1, read each register in the sequence replacing Flg0/En0/Cnt0 part with
Flg1/En1/Cnt1. Likewise, when you want to use Alarm2, read each register in the sequence replacing
Flg0/En0/Cnt0 part with Flg2/En2/Cnt2.
When you set Alarm output time (first time)
1. Write “1” on AlmClr.Flg0 and AlmClr.ErrFlg0 registers.
Clear Normal and Error Alarm Flags to “0”.
2. Write “1” on AlmOutEn0.En and AlmOutEn0.ErrEn registers at the same time.
Enable O(Err)Alarm0 to be output.

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3. On SetAlmPostCnt0 register, write the time that you want to output an Alarm.
Make sure to write SetAlmPostCnt0 before SetAlmPreCnt0.
4. On SetAlmPreCnt0 register, write the time that you want to output an Alarm.
An Alarm is output at the time set in 3 and 4 above.
You can check whether an Alarm has been output in the following two ways.



performing polling to AlmFlg.Flg0 until it returns to “0”receiving Alarm interrupt request

When you output an Alarm again
1. Write “1” on AlmClr.Flg0 and AlmClr.ErrFlg0 registers.
Clear Normal and Error Alarm Flags to “0”.
2. On SetAlmPostCnt0 register, write the time that you want to output an Alarm.
3. On SetAlmPreCnt0 register, write the time that you want to output an Alarm.

When you do not use Alarm anymore after outputting an Alarm
1. Write “0” on AlmOutEn0.En and AlmOutEn0.ErrEn registers.
Disable O(Err)Alarm0 to be output.
2. Write “1” on AlmClr.Flg0 and AlmClr.ErrFlg0 registers.
Clear Normal and Error Alarm Flags to “0”.

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3.7

I2C

3.7.1

Overview

I2C is a commonly used 2-wire (SCL and SDA) interface that can be used to connect devices for lower-speed datatransfer. The CXD5602 has 5 independent channels. This chapter mainly describes I2C0, I2C1 and I2C2, which
can be directly controlled for the user by the i2c driver. On the other hand, I2C3 and I2C4 are controlled by each
dedicated driver.
Table I2C-70 I2C List
I2C
channel
I2C0

Base Address

Power Domain

Description

0x0418d400

MasterSlave
MasterPWD_SCU

I2C1

0x0418d800

MasterPWD_SCU

I2C2

0x041aa000

MasterPWD_SYSIOP_SUB

I2C3

0x041a0400

Slave

PWD_SYSIOP

I2C4

0x04106000

MasterPWD_CORE

This is a general channel. It is controlled by the i2c or scu
driver.
This is a general channel It is controlled by the i2c or scu
driver.
This is a dedicated channel to communicate with the camera
interface. It is controlled by the i2c driver.
This is a dedicated channel to communicate with the hostmicrocontroller. It is controlled by the hostif driver.
This is a dedicated channel to communicate with the PMIC
like CXD5247. It is controlled by the pmic driver.

3.7.1.1 I2C0, I2C1The I2C0 and I2C1 are the I2C masters and support Standard and Fast Mode. In addition to direct control from the
System and I/O Processor, they can be controlled using the sequencer of the SCU, in which the use of thesequencer can reduce the load on the System and I/O Processor. Control from the System and I/O Processor andcontrol from the sequencer are exclusive and cannot be performed simultaneously. For information on thesequencer, refer to the chapter of the SCU.

3.7.1.1.1

Clock and Reset

Figure I2C-39 shows the clock and reset system of the I2C0 and I2C1.
Before accessing the I2C0 or I2C1 registers, make sure to set SCU_CKEN.SCU=1'b1.

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RCOSC
RTC_CLK_IN(32.768kHz)

1/250

0
1

CKSEL_SCU.SEL_SCU_32K

Reserved

0123

ck_scu_pre

CK
GATE

I2C0

I2CCLKPCLK

PRESETn

XOSC

1/2
1/3
1/4

0
1
2
3

CK
GATE

CKSEL_SCU.SEL_SCU_XTALSCU_CKEN.SCU_I2C0
Control by sequencer

CKSEL_SCU.SEL_SCU

I2C1

I2CCLKPCLK

PRESETn

SCU_CKEN.SCU_I2C1
Control by sequencer
PWD_RESET0.PWD_SCU
SWRESET_SCU.XRST_SCU_I2C0
SWRESET_SCU.XRST_SCU_I2C1

Figure I2C-39 I2C0/I2C1 Clock and Reset System
The I2C0 and I2C1 are integrated within the SCU, and clock control is possible by the System and I/O Processor
or sequencer of the SCU. For clock gating control of the I2CCLK, there is control using the register and control
using the sequencer, and the clock is supplied when either is in the supply setting.
The clock source can be selected from: the RCOSC; the clock generated by dividing the XOSC; the RCOSC
divided by 250; or the RTC.

3.7.1.1.2

Clock Supply Start

The following describes the method to start clock supply to the I2C0 and I2C1.
1. Clock supply start (internal circuit initialization)
SCU_CKEN.SCU_I2C0 = 1'b1
SCU_CKEN.SCU_I2C1 = 1'b1
2. Clock stop
SCU_CKEN.SCU_I2C0 = 1'b0
SCU_CKEN.SCU_I2C1 = 1'b0
3. Reset cancel
SWRESET_SCU.XRST_SCU_I2C0 = 1'b1
SWRESET_SCU.XRST_SCU_I2C1 = 1'b1
4. Clock supply start
SCU_CKEN.SCU_I2C0 = 1'b1
SCU_CKEN.SCU_I2C1 = 1'b1

3.7.1.1.3

Clock Supply Stop

The following describes the method to stop clock supply to the I2C0 and I2C1.
1. Clock stop

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SCU_CKEN.SCU_I2C0 = 1'b0
SCU_CKEN.SCU_I2C1 = 1'b0

3.7.1.2 I2C2The I2C2 is the I2C master and supports Standard and Fast Mode.

3.7.1.2.1

Clock and Reset

Figure I2C-40 shows the clock and reset system of the I2C2.
When accessing the I2C2 register, supply the clock to the AHB/APB Bus Bridge.

RCOSC

ck_rf_pll_1

RTC_CLK_IN(32.768kHz)XOSC

SYSPLLck_cpu_bus

1/M

ck_co m_gear

CK
GATE

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

I2C2

I2CCLKPCLK

PRESETn

0
1

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4

CKDIV_COM.CK_COM
SYSIOP_SUB_CKEN.I2CM_SUBSYSIOP_SUB_CKEN.COM_BRG

CK
GATE

1/M

1/M

ck_ahb_gear

CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_BRG_COMIF
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
SWRESET_BUS.XRST_I2CM_SUB

Figure I2C-40 I2C2 Clock and Reset System

3.7.1.2.2

Clock Supply Start

The following describes the method to start clock supply to the I2C2.
1. Clock supply start of the AHB/APB Bus Bridge.
SYSIOP_SUB_CKEN.COM_BRG = 1'b1
SYSIOP_SUB_CKEN.AHB_BRG_COMIF = 1'b1
2. Clock supply start (internal circuit initialization).
SYSIOP_SUB_CKEN.I2CM_SUB = 1'b1
3. Clock stop
SYSIOP_SUB_CKEN.I2CM_SUB = 1'b0
4. Reset release
SWRESET_BUS.XRST_I2CM_SUB = 1'b1

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CK
GATE

AHB/APB
BusBridge

CXD5602 User Manual

5. Clock supply start
SYSIOP_SUB_CKEN.I2CM_SUB = 1'b1

3.7.1.2.3

Clock Supply Stop

The following describes the method to stop the clock supply to the I2C2.
1. Clock stop
SYSIOP_SUB_CKEN.I2CM_SUB = 1'b0

3.7.1.3 Transfer Rate
The maximum transfer rate of the I2C is determined by the combination of the clock selected as the clock source(SYSPLL, XOSC, RCOSC, or RTC), the X'tal Oscillator clock, and the voltage mode (High Performancemode/Low Power mode). The following table describes each combination and their maximum transfer rates.
The transfer rate also varies with the external load capacity. Here, the values are shown under an ideal state.
Table I2C-71 XOSC (26 MHz), High Performance Mode
Clock source
frequency
M Hz
SYSIOP (ck_ahb_gear,ck_com_gear) M Hz
I2C2 BCKkbps
I2C4 BCKkbps
SCU (ck_scu_pre)
M Hz
I2C0,I2C1 BCKkbps

SYSPLL
195.000
156.000
48.75039.000
400
400
400
400
-

XOSC
26.00026.000400
400
13.000
400

RCOSC
8.192
8.192
356
356
8.192
356

RTC
0.032768
0.032768
1.424696
1.424696
0.032768
1.424696

RCOSC
8.192
8.192
356
356
8.192
356

RTC
0.032768
0.032768
1.424696
1.424696
0.032768
1.424696

Table I2C-72 XOSC (26 MHz), Low Power Mode
Clock source
frequency
M Hz
SYSIOP (ck_ahb_gear,ck_com_gear) M Hz
I2C2 BCKkbps
I2C4 BCKkbps
SCU (ck_scu_pre)
M Hz
I2C0,I2C1 BCK
kbps

3.7.2

SYSPLL
195.000
156.000
32.50031.200
400
400
400
400
-

XOSC
26.00026.000400
400
13.000400

Features

Each I2C controllers is based on a configuration of Synopsys DW_apb_i2c IP. I2C has the following features:■ Two-wire I2C serial interface I2C consists of a serial data line (SDA) and a serial clock (SCL)■ Standard mode (0 to 100 Kb/s) or Fast mode (≦400 Kb/s)－225/1293－

CXD5602 User Manual■ Fast mode plus and high-speed mode are not supported■ Clock synchronization■ Master I2C operation■ Slave I2C operation is not supported.
■ 7- or 10-bit addressing■ 7- or 10-bit combined format transfers■ Bulk transmit mode
■ Ignores CBUS addresses (an older ancestor of I2C that used to share the I2C bus)
■ Transmit and receive buffers■ Interrupt or polled-mode operation■ Handles Bit and Byte waiting at all bus speeds■ Simple software interface consistent with DesignWare APB peripherals■ Component parameters for configurable software driver support■ DMA handshaking interface compatible with the DW_ahb_dmac handshaking interface■ Programmable SDA hold time
The DW_apb_i2c requires external hardware components as support in order to be compliant in an I2C system.
The descriptions are detailed later in this document.

3.7.3

Functional description

3.7.3.1 I2C Terminology
3.7.3.1.1

I2C Bus Terms

The following terms relate to how the role of the I2C device and how it interacts with other I2C devices on thebus.
■ Transmitter – the device that sends data to the bus. A transmitter can either be a device that initiates the datatransmission to the bus (a master-transmitter) or responds to a request from the master to send data to the bus (aslave-transmitter).
■ Receiver – the device that receives data from the bus. A receiver can either be a device that receives data on
its own request (a master-receiver) or in response to a request from the master (a slave-receiver).
■ Master - the component that initializes a transfer (START command), generates the clock (SCL) signal andterminates the transfer (STOP command). A master can be either a transmitter or a receiver.
■ Slave – the device addressed by the master. A slave can be either receiver or transmitter.

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Master

SDA

Transmitter

SCL

MasterSDA

Receiver

SCL

Slave
ReceiverSlave
Transmitter

Figure I2C-41 Master/Slave and Transmitter/Receiver Relationships■ Multi-master – the ability for more than one master to co-exist on the bus at the same time without collision
or data loss.
■ Arbitration – the predefined procedure that authorizes only one master at a time to take control of the bus.
For more information about this behavior, refer to “Multiple Master Arbitration”.
■ Synchronization – the predefined procedure that synchronizes the clock signals provided by two or moremasters. For more information about this feature, refer to “Clock Synchronization”.
■ SDA – data signal line (Serial DAta)■ SCL – clock signal line (Serial CLock)3.7.3.1.2

Bus Transfer Terms

The following terms are specific to data transfers that occur to/from the I2C bus.
■ START (RESTART) – data transfer begins with a START or RESTART condition. The level of the SDA
data line changes from high to low, while the SCL clock line remains high. When this occurs, the bus becomesbusy. START and RESTART conditions are functionally identical.
■ STOP – data transfer is terminated by a STOP condition. This occurs when the level on the SDA data line
passes from the low state to the high state, while the SCL clock line remains high. When the data transfer has
been terminated, the bus is free or idle once again. The bus stays busy if a RESTART is generated instead of a
STOP condition.

3.7.3.2 I2C Behavior
The master is responsible for generating the clock and controlling the transfer of data. The slave is responsible for
either transmitting or receiving data to/from the master. The acknowledgement of data is sent by the device that isreceiving data, which can be either a master or a slave. As mentioned previously, the I2C protocol also allows
multiple masters to reside on the I2C bus and uses an arbitration procedure to determine bus ownership.
Each slave has a unique address that is determined by the system designer. When a master wants to communicate
with a slave, the master transmits a START/RESTART condition that is then followed by the slave’s address anda control bit (R/W) to determine if the master wants to transmit data or receive data from the slave. The slave thensends an acknowledge (ACK) pulse after the address.

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If the master (master-transmitter) is writing to the slave (slave-receiver), the receiver gets one byte of data. Thistransaction continues until the master terminates the transmission with a STOP condition. If the master is readingfrom a slave (master-receiver), the slave transmits (slave-transmitter) a byte of data to the master, and the masterthen acknowledges the transaction with the ACK pulse. This transaction continues until the master terminates thetransmission by not acknowledging (NACK) the transaction after the last byte is received, and then the masterissues a STOP condition or addresses another slave after issuing a RESTART condition. This behavior is
illustrated in Figure I2C-42.

P or R
SDA
SCL

MSB

S or R

1

LSB
2

7

START orRESTART
Condition

8

ACK

ACK

from slavefrom receiver

9

Byte Complete
Interrupt within
Slave

1

2

3-8

R or P

9

SCL held low
while servicing
interrupts

STOP ANDRESTART
Condition

Figure I2C-42 Data transfer on the I2C Bus
The DW_apb_i2c is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while
the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain or
open-collector to perform wire-AND functions on the bus. The maximum number of devices on the bus is limited
by only the maximum capacitance specification of 400 pF. Data is transmitted in byte packages.
The I2C protocols implemented in DW_apb_i2c are described in more details in “I2C Protocols”.

3.7.3.2.1

START and STOP Generation

When operating as an I2C master, putting data into the transmit FIFO causes the DW_apb_i2c to generate a
START condition on the I2C bus. If the IC_EMPTYFIFO_HOLD_MASTER_EN parameteris set to 0, allowing
the transmit FIFO to empty causes the DW_apb_i2c to generate a STOP condition on the I2C bus. If
IC_EMPTYFIFO_HOLD_MASTER_EN is set to 1, then writing a 1 to IC_DATA_CMD[9] causes theDW_apb_i2c to generate a STOP condition on the I2C bus; a STOP condition is not issued if this bit is not set,even if the transmit FIFO is empty.

3.7.3.2.2

Combined Formats

The DW_apb_i2c supports mixed read and write combined format transactions in both 7-bit and 10-bit addressing
modes.
The DW_apb_i2c does not support mixed address and mixed address format—that is, a 7-bit address transaction
followed by a 10-bit address transaction or vice versa—combined format transactions.

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To initiate combined format transfers, IC_CON.IC_RESTART_EN should be set to 1. With this value set andoperating as a master, when the DW_apb_i2c completes an I2C transfer, it checks the transmit FIFO and executes
the next transfer. If the direction of this transfer differs from the previous transfer, the combined format is used toissue the transfer. If the transmit FIFO is empty when the current I2C transfer completes—depending on the valueof IC_EMPTYFIFO_HOLD_MASTER_EN:■ Either a STOP is issued or,■ IC_DATA_CMD[9] is checked and:❑ If set to 1, a STOP bit is issued.
❑ If set to 0, the SCL is held low until the next command is written to the transmit FIFO.
For more details, refer to “Tx FIFO Management and START, STOP and RESTART Generation”.

3.7.3.3 I2C Protocols
The DW_apb_i2c has the protocols discussed in this section.

3.7.3.3.1

START and STOP Conditions

When the bus is idle, both the SCL and SDA signals are pulled high through external pull-up resistors on the bus.
When the master wants to start a transmission on the bus, the master issues a START condition. This is defined to
be a high-to-low transition of the SDA signal while SCL is 1. When the master wants to terminate thetransmission, the master issues a STOP condition. This is defined to be a low-to-high transition of the SDA line
while SCL is 1. Figure I2C-43 shows the timing of the START and STOP conditions. When data is beingtransmitted on the bus, the SDA line must be stable when SCL is 1.
SDA
SCL

S
Start
Condition

P
Change of Data
AllowedData line Stable
Data Valid

Change of Data
AllowedStop
Condition

Figure I2C-43 START and STOP Condition

3.7.3.3.2

Addressing Slave Protocol

There are two address formats: the 7-bit address format and the 10-bit address format.
7-bit Address Format
During the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave address and the LSB bit(bit 0) is the R/W bit as shown in Figure I2C-44. When bit 0 (R/W) is set to 0, the master writes to the slave.
When bit 0 (R/W) is set to 1, the master reads from the slave.

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LSB

MSB

S

A6

A5

A4

A3

A1

A2

A0 R/W ACK
sent by slave

Slave Address

START condition

Read/Write Pulse
Acknowledge

Figure I2C-44 7-bit Address Format
10-bit Address Format
During 10-bit addressing, two bytes are transferred to set the 10-bit address. The transfer of the first byte contains
the following bit definition. The first five bits (bits 7:3) notify the slaves that this is a 10-bit transfer followed by
the next two bits (bits 2:1), which set the slaves address bits 9:8, and the LSB bit (bit 0) is the R/W bit. The
second byte transferred sets bits 7:0 of the slave address. Figure I2C-45 shows the 10-bit address format.

Read/Write Pulse
AcknowledgeS‘1’ ‘1’ ‘1’ ‘1’ ‘0’

START condition

A9

A8 R/W ACK

A7

A6

Acknowledge

A5

A4

A3

A2

sent by slave

Reserved for 10-bit Address

A1

A0

ACK
sent by slave

Figure I2C-45 10-bit Address Format
Slave Address

R/W BitDescription

0000 000

0General Call Address. DW_apb_i2c places the data in the receive buffer andissues a General Call interrupt.

0000 000

1START byte. For more details, refer to “START BYTE Transfer Protocol”.

0000 001

X

CBUS address. DW_apb_i2c ignores these accesses.

0000 010

X

Reserved.

0000 011

X

Reserved.

0000 1XX

X

High-speed master code.

1111 1XXX

Reserved.

1111 0XXX

10-bit slave addressing

DW_apb_i2c does not restrict you from using these reserved addresses. However, if you use these reserved
addresses, you may run into incompatibilities with other I2C components.

3.7.3.3.3

Transmitting and Receiving Protocol

The master can initiate data transmission and reception to/from the bus, acting as either a master-transmitter ormaster-receiver. A slave responds to requests from the master to either transmit data or receive data to/from thebus, acting as either a slave-transmitter or slave-receiver, respectively.

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Master-Transmitter and Slave-Receiver
All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer. After the
master sends the address and R/W bit or the master transmits a byte of data to the slave, the slave-receiver must
respond with the acknowledge signal (ACK). When a slave-receiver does not respond with an ACK pulse, themaster aborts the transfer by issuing a STOP condition. The slave must leave the SDA line high so that the mastercan abort the transfer.
If the master-transmitter is transmitting data as shown in Figure I2C-46, then the slave-receiver responds to themaster-transmitter with an acknowledge pulse after every byte of data is received.
For 7-bit Address
S

Slave Address

For 10-bit Address
S

R/W
‘0’
write

Slave Address R/WFirst 7 bits ‘0’‘11110xxx’ write

A

DATA

A

DATA

A/A

P

A

Slave Address
Second Byte

A

DATA

A/A

P

A = Acknowledge (SDA low)
A = No Acknowledge (SDA high)S = START Condition
P = STOP Condition

From Master to Slave
From Slave to MasterFigure I2C-46 Master-Transmitter Protocol
Master-Receiver and Slave-Transmitter
If the master is receiving data as shown in Figure I2C-47, then the master responds to the slave-transmitter with an
acknowledge pulse after a byte of data has been received, except for the last byte. This is the way themaster-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes the SDA
line after detecting the No Acknowledge (NACK) so that the master can issue a STOP condition.
For 7-bit Address
S

Slave Address

For 10-bit Address
S

R/W
‘1’
read

Slave Address R/WFirst 7 bits ‘0’‘11110xxx’ write

A

DATA

A

A

Slave Address
Second Byte

A

From Master to Slave
From Slave to Master

DATA

Sr

A

P

Slave Address R/WFirst 7 bits ‘1’‘11110xxx’ readA = Acknowledge (SDA low)
A = No Acknowledge (SDA high)S = START ConditionSr = RESTART Condition
P = STOP Condition

Figure I2C-47 Master-Receiver Protocol－231/1293－

A

DATA

A

P

CXD5602 User Manual

When a master does not want to relinquish the bus with a STOP condition, the master can issue a RESTART
condition. This is identical to a START condition except it occurs after the ACK pulse. Operating in master mode,
the DW_apb_i2c can then communicate with the same slave using a transfer of a different direction. For a
description of the combined format transactions that the DW_apb_i2c supports, refer to “Combined Formats”.
The DW_apb_i2c must be completely disabled—if I2C_DYNAMIC_TAR_UPDATE = 0—or inactive on theserial port—if I2C_DYNAMIC_TAR_UPDATE = 1—before the target slave address register (IC_TAR) can be
reprogrammed.

3.7.3.3.4

START BYTE Transfer Protocol

The START BYTE transfer protocol is set up for systems that do not have an on-board dedicated I2C hardware
module. When the DW_apb_i2c is addressed as a slave, it always samples the I2C bus at the highest speed
supported so that it never requires a START BYTE transfer. However, when DW_apb_i2c is a master, it supports
the generation of START BYTE transfers at the beginning of every transfer in case a slave device requires it.
This protocol consists of seven zeros being transmitted followed by a 1, as illustrated in Figure I2C-48. This
allows the processor that is polling the bus to under-sample the address phase until 0 is detected. Once themicrocontroller detects a 0, it switches from the under the sampling rate to the correct rate of the master.
dummy
acknowledge

SDA(HIGH)

SCL

S

1

2

7

8

start byte 00000001

9

Sr

ACK

Figure I2C-48 START BYTE Transfer
The START BYTE procedure is as follows:
1. Master generates a START condition.
2. Master transmits the START byte (0000 0001).
3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format used on thebus)
4. No slave sets the ACK signal to 0.
5. Master generates a RESTART (R) condition.
A hardware receiver does not respond to the START BYTE because it is a reserved address and resets after the
RESTART condition is generated.

3.7.3.4 Tx FIFO Management and START, STOP and RESTART Generation
When operating as a master, the DW_apb_i2c component supports two modes of Tx FIFO management. You use
the IC_EMPTYFIFO_HOLD_MASTER_EN parameter to select between these two modes:－232/1293－

CXD5602 User Manual■ IC_EMPTYFIFO_HOLD_MASTER_EN equals 0, illustrated in Figure I2C-49■ IC_EMPTYFIFO_HOLD_MASTER_EN equals 1, illustrated in Figure I2C-52

3.7.3.4.1

Tx FIFO Management When IC_EMPTYFIFO_HOLD_MASTER_EN = 0

When the value of IC_EMPTYFIFO_HOLD_MASTER_EN is 0, the component generates a STOP
on the bus whenever the Tx FIFO becomes empty. If RESTART generation capability is enabled,
the component generates a RESTART when the direction of the transfer in the Tx FIFO commands
changes from Read to Write or vice-versa; if RESTART is not enabled, a STOP followed by a
START is generated in this situation.
Figure I2C-49 shows the bits in the IC_DATA_CMD register if IC_EMPTYFIFO_HOLD_MASTER_EN = 0.

IC_DATA_CMD

CMD
8

DATA
7

0

DATA – Read/Write field; data retrieved from slave is read from this field;
data to be sent to slave is written to this field.
CMD – Write-only field; this bit determines whether transfer to be carried out
is Read (CMD=1) or Write (CMD=0).
Figure I2C-49 IC_DATA_CMD Register if IC_EMPTYFIFO_HOLD_MASTER_EN = 0
Figure I2C-50 shows a timing diagram that illustrates the behavior of the DW_apb_i2c when Tx FIFO becomes
empty while operating as a master transmitter when IC_EMPTYFIFO_HOLD_MASTER_EN=0.

S
SDA

P
A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack

SCL
FIFO_EMPTY
Tx FIFO loaded with data
(write data in this example)

Data availability triggers
START condition on bus

Last byte popped
from Tx FIFO

Empty Tx FIFO triggers
STOP condition on bus

Figure I2C-50 Master Transmitter Tx FIFO Becomes Empty if IC_EMPTYFIFO_HOLD_MASTER_EN=0
Figure I2C-51 shows a timing diagram that illustrates the behavior of the DW_apb_i2c when Tx FIFO becomes
empty while operating as a master receiver when IC_EMPTYFIFO_HOLD_MASTER_EN=0.

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S
SDA

P
A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Nak

SCL
FIFO_EMPTY
Command availability triggers
START condition on bus
Tx FIFO loaded with data(read operation in this example)

Last command popped
from Tx FIFO

Empty Tx FIFO triggers
STOP condition on bus

Figure I2C-51 Master Receiver Tx FIFO Becomes Empty if IC_EMPTYFIFO_HOLD_MASTER_EN=0

3.7.3.4.2

Tx FIFO Management When IC_EMPTYFIFO_HOLD_MASTER_EN = 1

When the value of IC_EMPTYFIFO_HOLD_MASTER_EN is 1, the component does not generate a STOP if theTx FIFO becomes empty; in this situation the component holds the SCL line low, stalling the bus until a newentry is available in the Tx FIFO. A STOP condition is generated only when the user specifically requests it bysetting bit 9 (Stop bit) of the command written to IC_DATA_CMD register.
Figure I2C-52 shows the bits in the IC_DATA_CMD register if IC_EMPTYFIFO_HOLD_MASTER_EN = 1.

IC_DATA_CMD

Restart

Stop

CMD

10

9

8

DATA
7

0

DATA – Read/Write field; data retrieved from slave is read from this field;
data to be sent to slave is written to this field.
CMD – Write-only field; this bit determines whether transfer to be carried out
is Read (CMD=1) or Write (CMD=0).
Stop – Write-only field; this bit determines whether STOP is generated after
data byte is sent or received
Restart – Write-only field; this bit determines whether RESTART (or STOP
followed by START in case of restart capability is not enabled)is generated before data byte is sent or received

Figure I2C-52 IC_DATA_CMD Register if IC_EMPTYFIFO_HOLD_MASTER_EN = 1
Figure I2C-53 illustrates the behavior of the DW_apb_i2c when the Tx FIFO becomes empty while operating as amaster transmitter, as well as showing the generation of a STOP condition when
IC_EMPTYFIFO_HOLD_MASTER_EN=1.

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S
SDA

P
A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack

D7 D6 D5 D4 D3 D2 D1 D0 Ack

SCL
FIFO_EMPTY
Data availability triggers
START condition on bus
Tx FIFO loaded with data
Last byte popped(write data in this example)
from Tx FIFO with STOP bit not set

Tx FIFO loadedwith new data

Because STOP bit was not set on last bytes
popped from Tx FIFO, Master holds SCL low

Last byte popped from Tx
FIFO with STOP bit set

STOP bit enabled triggers
STOP condition on bus

Master releases SCL line andresumes transmission because
new data became available

Figure I2C-53 Master Transmitter Tx FIFO Empties/STOP Generation if
IC_EMPTYFIFO_HOLD_MASTER_EN=1
Figure I2C-54 illustrates the behavior of the DW_apb_i2c when the Tx FIFO becomes empty while operating as amaster receiver, as well as showing the generation of a STOP condition when
IC_EMPTYFIFO_HOLD_MASTER_EN=1.
S
SDA

P
A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack

Ack D7 D6 D5 D4 D3 D2 D1 D0 Nak

SCL
FIFO_EMPTY
Command availability triggers
START condition on bus
Tx FIFO loaded with command
Last command popped(read operation in this example)
from Tx FIFO with STOP bit not set

Tx FIFO loadedwith new command
Last command popped from
Because STOP bit was not set on last commands Tx FIFO with STOP bit set
popped from Tx FIFO, Master holds SCL low

STOP bit enabled triggers
STOP condition on bus

Master releases SCL line andresumes transmission because
new command became available

Figure I2C-54 Master Receiver Tx FIFO Empties/STOP Generation if
IC_EMPTYFIFO_HOLD_MASTER_EN=1
Figure I2C-55 and Figure I2C-56 illustrate configurations where the user can control the generation of RESTART
conditions on the I2C bus. If bit 10 (Restart) of the IC_DATA_CMD register is set and the restart capability isenabled (IC_RESTART_EN=1), a RESTART is generated before the data byte is written to or read from the slave.
If the restart capability is not enabled a STOP followed by a START is generated in place of the RESTART.
Figure I2C-55 illustrates this situation during operation as a master transmitter.

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S
SDA

Sr
A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6

A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack

SCL
FIFO_EMPTY
Tx FIFO loaded with data
(write data in this example)

Data availability triggers
START condition on bus
Next byte in TxFIFO
has RESTART bit set

Because next byte on Tx FIFO has been taggedwith RESTART bit, Master issues
RESTART and initiates new transmission

Figure I2C-55 Master Transmitter Restart Bit of IC_DATA_CMD is set(IC_EMPTYFIFO_HOLD_MASTER_EN=1)
Figure I2C-56 illustrates the same situation, but during operation as a master receiver.
S
SDA

Sr
A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6

A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Nak

SCL
FIFO_EMPTY
Command availability triggers
START condition on bus
Tx FIFO loaded with command(write data in this example)
Next command in Tx FIFO
has RESTART bit set

Master issues NOT ACK
as required before RESTART
when operating as receiver

Because next command on Tx FIFO has beentagged with RESTART bit, Master issues
RESTART and initiates new transmission

Figure I2C-56 Master Receiver Restart Bit of IC_DATA_CMD is set(IC_EMPTYFIFO_HOLD_MASTER_EN=1)
Figure I2C-57 illustrates operation as a master transmitter where the Stop bit of the IC_DATA_CMD register is
set and the Tx FIFO is not empty (IC_EMPTYFIFO_HOLD_MASTER_EN=1).
S
SDA

P S
A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6

A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack

SCL
FIFO_EMPTY
Data availability triggers
START condition on bus
Tx FIFO loaded with data
One byte (not last one) is popped(write data in this example)
from Tx FIFO with STOP bit set

Because more data is available in Tx FIFO,
a new transmission is immediately initiated(provided master is granted access to bus)

Because STOP bit was set on last byte popped
from Tx FIFO, Master generates STOP condition

Figure I2C-57 Master Transmitter Stop Bit of IC_DATA_CMD Set/Tx FIFO Not Empty(IC_EMPTYFIFO_HOLD_MASTER_EN=1)
Figure I2C-58 illustrates operation as a master transmitter where the first byte loaded into the Tx FIFO is allowed
to go empty with the Restart bit set (IC_EMPTYFIFO_HOLD_MASTER_EN=1).

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S
SDA

Sr
A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6

A6 A5 A4 A3 A2 A1 A0 W Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack

SCL
FIFO_EMPTY
Data availability triggers
START condition on bus
Tx FIFO loaded
Tx FIFO loaded with data
Last byte popped
with new data
(write data in this example)
from Tx FIFO with STOP bit not set
Because STOP bit was not set on last commands
popped from Tx FIFO, Master holds SCL low

Master issues RESTART
and initiates new transmission

Figure I2C-58 Master Transmitter First Byte Loaded into Tx FIFO Allowed to Empty, Restart Bit Set(IC_EMPTYFIFO_HOLD_MASTER_EN=1)
Figure I2C-59 illustrates operation as a master receiver where the Stop bit of the IC_DATA_CMD register is set
and the Tx FIFO is not empty (IC_EMPTYFIFO_HOLD_MASTER_EN=1).
S
SDA

P S
A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6

A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Nak

SCL
FIFO_EMPTY
Command availability triggers
START condition on bus
Tx FIFO loaded with command
One command (not last one)(write data in this example)
is popped from Tx FIFO with
STOP bit set

Because STOP bit wasset on last command
popped from Tx FIFO,
Master generates
STOP condition

Because more command are available
in TX FIFO, a new transmission isimmediately initiated (provided masteris granted access to bus)

Figure I2C-59 Master Receiver Stop Bit of IC_DATA_CMD Set/Tx FIFO Not Empty(IC_EMPTYFIFO_HOLD_MASTER_EN=1)
Figure I2C-60 illustrates operation as a master receiver where the first command loaded after the Tx FIFO isallowed to empty and the Restart bit is set (IC_EMPTYFIFO_HOLD_MASTER_EN=1).
S
SDA

Sr
A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0

A6 A5 A4 A3 A2 A1 A0 R Ack D7 D6

Nak

SCL
FIFO_EMPTY
Command availability triggers
START condition on bus
Tx FIFO loaded with command
Last command popped(write data in this example)
from Tx FIFO with
STOP bit not set

Master issues RESTART andinitiate new transmission

Because STOP bit was
not set on last command
popped from Tx FIFO,
Master holds SCL low
Tx FIFO loadedwith new command

Master issues NOT ACK as
required before RESTART
when operating as receiver
Next command loaded into
Tx FIFO has RESTART bit set

Figure I2C-60 Master Receiver First Command Loaded After Tx FIFO Allowed to Empty, Restart Bit Set(IC_EMPTYFIFO_HOLD_MASTER_EN=1)－237/1293－

CXD5602 User Manual

3.7.3.5 Multiple Master Arbitration
The DW_apb_i2c bus protocol allows multiple masters to reside on the same bus. If there are two masters on thesame I²C-bus, there is an arbitration procedure if both try to take control of the bus at the same time by generating
a START condition at the same time. Once a master (for example, a microcontroller) has control of the bus, noother master can take control until the first master sends a STOP condition and places the bus in an idle state.
Arbitration takes place on the SDA line, while the SCL line is 1. The master, which transmits a 1 while the othermaster transmits 0, loses arbitration and turns off its data output stage. The master that lost arbitration cancontinue to generate clocks until the end of the byte transfer. If both masters are addressing the same slave device,
the arbitration could go into the data phase.
Upon detecting that it has lost arbitration to another master, the DW_apb_i2c will stop generating SCL(ic_clk_oe).
Figure I2C-61 illustrates the timing of when two masters are arbitrating on the bus.
DATA1

MSB

‘1’

DATA1 loses arbitration

matching data
MSB

DATA2

‘0’
SDA mirrors DATA2

SDA

MSB

SCL
SDA lines up
with DATA1START condition

Figure I2C-61 Multiple Master Arbitration

For high-speed mode, the arbitration cannot go into the data phase because each master is programmed with aunique high-speed master code. This 8-bitcode is defined by the system designer and is set by writing to the High
Speed Master Mode Code Address Register, IC_HS_MADDR. Because the codes are unique, only one master can
win arbitration, which occurs by the end of the transmission of the high-speed master code.
Control of the bus is determined by address or master code and data sent by competing masters, so there is nocentral master nor any order of priority on the bus. Arbitration is not allowed between the following conditions:■ A RESTART condition and a data bit－238/1293－

CXD5602 User Manual■ A STOP condition and a data bit■ A RESTART condition and a STOP condition

3.7.3.6 Clock Synchronization
When two or more masters try to transfer information on the bus at the same time, they must
arbitrate and synchronize the SCL clock. All masters generate their own clock to transfer messages.
Data is valid only during the high period of SCL clock. Clock synchronization is performed using
the wired-AND connection to the SCL signal. When the master transitions the SCL clock to 0, themaster starts counting the low time of the SCL clock and transitions the SCL clock signal to 1 at the
beginning of the next clock period. However, if another master is holding the SCL line to 0, thenthe master goes into a HIGH wait state until the SCL clock line transitions to 1.
All masters then count off their high time, and the master with the shortest high time transitions
the SCL line to 0. The masters then counts out their low time and the one with the longest low timeforces the other master into a HIGH wait state. Therefore, a synchronized SCL clock is generated,which is illustrated in Figure I2C-62. Optionally, slaves may hold the SCL line low to slow down thetiming on the I2C bus.
Wait State
Start counting HIGH period
CLKA
CLKB
SCL
SCL transitions HIGH
when all CLKs are in HIGH state

SCL LOW transition
Resets all CLKs to start
counting their LOW periods

Figure I2C-62 Multi-Master Clock Synchronization

3.7.3.7 Master Mode Operation
This section discusses master mode procedures.

3.7.3.7.1

Initial Configuration

The initial configuration procedure for Master Mode Operation depends on the configuration parameter
I2C_DYNAMIC_TAR_UPDATE. When set to “Yes” (1), the target address and address format can be changed
dynamically without having to disable DW_apb_i2c. This parameter only applies to when DW_apb_i2c is acting
as a master because the slave requires the component to be disabled before any changes can be made to the－239/1293－

CXD5602 User Manualaddress. For more information about how this parameter affects the IC_TAR register.
The procedures are very similar and are only different with regard to where the IC_10BITADDR_MASTER bit isset (either bit 4 of IC_CON register or bit 12 of IC_TAR register).

To use the DW_apb_i2c as a master when the I2C_DYNAMIC_TAR_UPDATE configuration parameter is set to“Yes” (1), perform the following steps:
1. Disable the DW_apb_i2c by writing 0 to bit 0 of the IC_ENABLE register.
2. Write to the IC_CON register to set the maximum speed mode supported for slave operation (bits 2:1) and to
specify whether the DW_apb_i2c starts its transfers in 7/10 bit addressing mode when the device is a slave(bit 3).
3. Write to the IC_TAR register the address of the I2C device to be addressed. It also indicates whether aGeneral Call or a START BYTE command is going to be performed by I2C. The desired speed of theDW_apb_i2c master-initiated transfers, either 7-bit or 10-bit addressing, is controlled by the
IC_10BITADDR_MASTER bit field (bit 12).
4. Only applicable for high-speed mode transfers. Write to the IC_HS_MADDR register the desired master codefor the DW_apb_i2c. The master code is programmer-defined.
5. Enable the DW_apb_i2c by writing a 1 to bit 0 of the IC_ENABLE register.
6. Now write the transfer direction and data to be sent to the IC_DATA_CMD register. If the IC_DATA_CMD
register is written before the DW_apb_i2c is enabled, the data and commands are lost as the buffers are kept
cleared when DW_apb_i2c is not enabled.

3.7.3.7.2

Dynamic IC_TAR or IC_10BITADDR_MASTER Update

The DW_apb_i2c supports dynamic updating of the IC_TAR (bits 9:0) and IC_10BITADDR_MASTER (bit 12)
bit fields of the IC_TAR register. In order to perform a dynamic update of the IC_TAR register, theI2C_DYNAMIC_TAR_UPDATE configuration parameter must be set to Yes (1). You can dynamically write to
the IC_TAR register provided the software ensures that there are no other commands in the Tx FIFO that use theexisting TAR address. If the software does not ensure this, then IC_TAR should be re-programmed only if thefollowing conditions are met:
DW_apb_i2c is not enabled (IC_ENABLE[0]=0);
OR
DW_apb_i2c is enabled (IC_ENABLE[0]=1); AND
DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0); AND
DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1); AND
there are NO entries in the Tx FIFO (IC_STATUS[2]=1);
You can change the TAR address dynamically without losing the bus, only if the following conditions are met.
DW_apb_i2c is enabled (IC_ENABLE[0]=1); AND
IC_EMPTYFIFO_HOLD_MASTER_EN configuration parameter is set to 1; AND－240/1293－

CXD5602 User Manual

DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1); AND
there are NO entries in the Tx FIFO and the master is in HOLD state (IC_INTR_STAT[13]=1);

3.7.3.7.3

Master Transmit and Master Receive

The DW_apb_i2c supports switching back and forth between reading and writing dynamically. To transmit data,
write the data to be written to the lower byte of the I2C Rx/Tx Data Buffer and Command Register(IC_DATA_CMD). The CMD bit [8] should be written to 0 for I2C write operations. Subsequently, a readcommand may be issued by writing “don’t cares” to the lower byte of the IC_DATA_CMD register, and a 1
should be written to the CMD bit. The DW_apb_i2c master continues to initiate transfers as long as there arecommands present in the transmit FIFO. If the transmit FIFO becomes empty - depending on the value of
IC_EMPTYFIFO_HOLD_MASTER_EN, the master either inserts a STOP condition after completing the current
transfers, or it checks to see if IC_DATA_CMD[9] is set to 1.
■ If set to 1, it issues a STOP condition after completing the current transfer.
■ If set to 0, it holds SCL low until next command is written to the transmit FIFO.
For more details, refer to “Tx FIFO Management and START, STOP and RESTART Generation”.

3.7.3.7.4

Disabling DW_apb_i2c

The register IC_ENABLE_STATUS is added to allow software to unambiguously determine when the hardware
has completely shutdown in response to bit 0 of the IC_ENABLE register being set from 1 to 0. Only one register
is required to be monitored, as opposed to monitoring two registers (IC_STATUS and IC_RAW_INTR_STAT)
which is a requirement for DW_apb_i2c versions 1.05a or earlier.
1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling period for the highest I2C transfer speed
used in the system and supported by DW_apb_i2c. For example, if the highest I2C transfer mode is 400 kb/s,
then this ti2c_poll is 25us.
2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any repeated polling operation
exceeds this maximum value, an error is reported.
3. Execute a blocking thread/process/function that prevents any further I2C master transactions to be started bysoftware, but allows any pending transfers to be completed.
4. The variable POLL_COUNT is initialized to zero.
5. Set bit 0 of the IC_ENABLE register to 0.
6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment POLL_COUNT by one. If
POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant error code.
7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the previous step. Otherwise, exit
with a relevant success code.

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3.7.3.7.5

Aborting I2C Transfers

The ABORT control bit of the IC_ENABLE register allows the software to relinquish the I2C bus before
completing the issued transfer commands from the Tx FIFO. In response to an ABORT request, the controller
issues the STOP condition over the I2C bus, followed by Tx FIFO flush. Aborting the transfer is allowed only inmaster mode of operation.
1. Stop filling the Tx FIFO (IC_DATA_CMD) with new commands.
2. When operating in DMA mode, disable the transmit DMA by setting TDMAE to 0.
3. Set bit 1 of the IC_ENABLE register (ABORT) to 1.
4. Wait for the M_TX_ABRT interrupt.
5. Read the IC_TX_ABRT_SOURCE register to identify the source as ABRT_USER_ABRT.

3.7.3.8 Spike Suppression
The DW_apb_i2c contains programmable spike suppression logic that match requirements imposed by the I2C
Bus Specification for SS/FS (tSP, Table 4) and HS (tSP, Table 6) modes.
This logic is based on counters that monitor the input signals (SCL and SDA), checking if they remain stable for apredetermined amount of ic_clk cycles before they are sampled internally. There is one separate counter for eachsignal (SCL and SDA). The number of ic_clk cycles can be programmed by the user and should be calculated
taking into account the frequency of ic_clk and the relevant spike length specification.
Each counter is started whenever its input signal changes its value. Depending on the behavior of the input signal,
one of the following scenarios occurs:■ The input signal remains unchanged until the counter reaches its count limit value. When this happens, theinternal version of the signal is updated with the input value, and the counter is reset and stopped. The counteris not restarted until a new change on the input signal is detected.
■ The input signal changes again before the counter reaches its count limit value. When this happens, thecounter is reset and stopped, but the internal version of the signal is not updated. The counter remains stopped
until a new change on the input signal is detected.
The timing diagram in Figure I2C-63 illustrates the behavior described above.

ic_clkSCL
Spike length counter

0

1

2

3

0

1

2

3

Internal filtered SCL
Figure I2C-63 Spike Suppression Example－242/1293－

4

5

0

CXD5602 User Manual

The count limit value used in this example is 5 and was calculated for a 10 ns ic_clk period and for SS/FS
operation (50 ns spike suppression).

The I2C Bus Specification calls for different maximum spike lengths according to the operating mode—50 ns for
SS and FS; 10 ns for HS—so two registers are required to store the values needed for each case:■ Register IC_FS_SPKLEN holds the maximum spike length for SS and FS modes■ Register IC_HS_SPKLEN holds the maximum spike value for HS mode.

These registers are 8 bits wide and accessible through the APB interface for read and write purposes; however,they can be written to only when the DW_apb_i2c is disabled. The minimum value that can be programmed into
these registers is 1; attempting to program a value smaller than 1 results in the value 1 being written.
The default value for these registers is automatically calculated in coreConsultant based on the value of ic_clk
period, but this value can be overridden by the user when configuring the component.

3.7.3.9 IC_CLK Frequency Configuration
When the DW_apb_i2c is configured as a master, the *CNT registers must be set before any I2C bus transaction
can take place in order to ensure proper I/O timing. The *CNT registers are:
■ IC_SS_SCL_HCNT■ IC_SS_SCL_LCNT■ IC_FS_SCL_HCNT■ IC_FS_SCL_LCNT■ IC_HS_SCL_HCNT■ IC_HS_SCL_LCNT

3.7.3.9.1

Minimum High and Low Counts

When the DW_apb_i2c operates as an I2C master, in both transmit and receive transfers:■ IC_SS_SCL_LCNT and IC_FS_SCL_LCNT register values must be larger than IC_FS_SPKLEN + 7.
■ IC_SS_SCL_HCNT and IC_FS_SCL_HCNT register values must be larger than IC_FS_SPKLEN + 5.
■ If the component is programmed to support HS, IC_HS_SCL_LCNT register value must be larger than
IC_HS_SPKLEN + 7.
■ If the component is programmed to support HS, IC_HS_SCL_HCNT register value must be larger than
IC_HS_SPKLEN + 5.

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Details regarding the DW_apb_i2c high and low counts are as follows:■ The minimum value of IC_*_SPKLEN + 7 for the *_LCNT registers is due to the time required for theDW_apb_i2c to drive SDA after a negative edge of SCL.
■ The minimum value of IC_*_SPKLEN + 5 for the *_HCNT registers is due to the time required for theDW_apb_i2c to sample SDA during the high period of SCL.
■ The DW_apb_i2c adds one cycle to the programmed *_LCNT value in order to generate the low period of the
SCL clock; this is due to the counting logic for SCL low counting to (*_LCNT + 1).
■ The DW_apb_i2c adds IC_*_SPKLEN + 7 cycles to the programmed *_HCNT value in order to generate thehigh period of the SCL clock; this is due to the following factors:❑ The counting logic for SCL high counts to (*_HCNT+1).
❑ The digital filtering applied to the SCL line incurs a delay of SPKLEN + 2 ic_clk cycles, where SPKLEN is:■ IC_FS_SPKLEN if the component is operating in SS or FS■ IC_HS_SPKLEN if the component is operating in HS.
This filtering includes metastability removal and the programmable spike suppression on SDA and SCL edges.
❑ Whenever SCL is driven 1 to 0 by the DW_apb_i2c—that is, completing the SCL high time—an internal
logic latency of three ic_clk cycles is incurred. Consequently, the minimum SCL low time of which theDW_apb_i2c is capable is nine (9) ic_clk periods (7 + 1 + 1), while the minimum SCL high time is thirteen (13)ic_clk periods (6 + 1 + 3 + 3).

ic_clkic_clk_in_a/SCL
HCNT+IC_*_SPKLEN+7
SCL
rise time

SCL
fall time

LCNT+1SCL
rise time

SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_fall_time
SCL_Low_time = [(LCNT + 1) * ic_clk] – SCL_fall_time + SCL_rise_time

Figure I2C-64 Impact of SCL Rise Time and Fall Time on Generated SCL－244/1293－

CXD5602 User Manual

3.7.3.9.2

Minimum IC_CLK Frequency

This section describes the minimum ic_clk frequencies that the DW_apb_i2c supports for each speed mode, andthe associated high and low count values. In Slave mode, IC_SDA_HOLD (Thd;dat) and IC_SDA_SETUP(Tsu:dat) need to be programmed to satisfy the I2C protocol timing requirements.
The following examples are for the case where IC_FS_SPKLEN and IC_HS_SPKLEN are programmed to 2.
Standard Mode and Fasst Mode
This section details how to derive a minimum ic_clk value for standard and fast modes of the DW_apb_i2c.
Although the following method shows how to do fast mode calculations, you can also use the same method inorder to do calculations for standard mode and fast mode plus.
Given conditions and calculations for the minimum DW_apb_i2c ic_clk value in fast mode:
Derived equations:■ Fast mode has data rate of 400kb/s; implies SCL period of 1/400khz = 2.5us■ Minimum hcnt value of 14 as a seed value; IC_HCNT_FS = 14
■ Protocol minimum SCL high and low times:❑ MIN_SCL_LOWtime_FS = 1300ns❑ MIN_SCL_HIGHtime_FS = 600ns
Derived equations:

Combined, the previous equations produce the following:

Solving for IC_LCNT_FS:

The previous equation gives:
These calculations produce IC_LCNT_FS = 16 and IC_HCNT_FS = 14, giving an ic_clk value of:－245/1293－

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Testing these results shows that protocol requirements are satisfied.

A following lists the minimum ic_clk values for all modes with high and low count values.
Speed

IC_CLKfreq

Minimum

SCL Low

SCL

SCL

SCL

SCL

SCL

Mode

(MHz)

Value of

Time

Low

Low

High

High

High

IC_*_SPKLEN

IC_CLKs

Program

Time

Time

Program

Time

in

Value

in

IC_CLKs

Value

SS

2.7

1

13

12

4.7us

14

6

5.2us

FS

12.0

1

16

15

1.33us14

6

1.16usCalculating High and Low Counts
The calculations below show how to calculate SCL high and low counts for each speed mode in the DW_apb_i2c.
For the calculations to work, the ic_clk frequencies used must not be less than the minimum ic_clk frequencies
specified in above table.
The DW_apb_i2c coreConsultant GUI can automatically calculate SCL high and low count values. By specifying
an integer ic_clk period value in nanoseconds for the IC_CLK_PERIOD parameter, SCL high and low countvalues are automatically calculated for each speed mode. The ic_clk period must not specify a clock of a lower
frequency than required for all supported speed modes. It is possible that the automatically calculated values may
result in a baud rate higher than the maximum rate specified by the protocol. If this happens, either the low or highcount values can be scaled up to reduce the baud rate.
The equation to calculate the proper number of ic_clk signals required for setting the proper SCL clocks high andlow times is as follows:
IC_xCNT = (ROUNDUP(MIN_SCL_xxxtime * OSCFREQ, 0))
ROUNDUP is an explicit Excel function call that is used to convert a real number to its equivalent integer
number.
MIN_SCL_HIGHtime = Minimum High Period
MIN_SCL_HIGHtime = 4000 ns for 100 kbps
600 ns for 400 kbps
MIN_SCL_LOWtime = Minimum Low Period
MIN_SCL_LOWtime = 4700 ns for 100 kbps
1300 ns for 400 kbps
OSCFREQ = ic_clk Clock Frequency (Hz).
For example:
OSCFREQ = 100 MHz－246/1293－

CXD5602 User Manual

I2Cmode = fast, 400 kbit/s
MIN_SCL_HIGHtime = 600 ns
MIN_SCL_LOWtime = 1300 ns
IC_xCNT = (ROUNDUP(MIN_SCL_HIGH/LOWtime * OSCFREQ, 0))
IC_HCNT = (ROUNDUP(600 ns * 100 MHz, 0))
IC_HCNTSCL PERIOD = 60
IC_LCNT = (ROUNDUP(1300 ns * 100 MHz, 0))
IC_LCNTSCL PERIOD = 130
Actual MIN_SCL_HIGHtime = 60 * (1/100 MHz) = 600 ns
Actual MIN_SCL_LOWtime = 130 * (1/100 MHz) = 1300 ns

3.7.3.10

SDA Hold TimeThe I2C protocol specification requires 300ns of hold time on the SDA signal (tHD;DAT) in standard mode andfast mode, and a hold time long enough to bridge the undefined part between logic 1 and logic 0 of the fallingedge of SCL in high speed mode and fast mode plus.
Board delays on the SCL and SDA signals can mean that the hold-time requirement is met at the I2C master, but
not at the I2C slave (or vice-versa). As each application encounters differing board delays, the DW_apb_i2c
contains a software programmable register (IC_SDA_HOLD) to enable dynamic adjustment of the SDA
hold-time.
The bits [15:0] are used to control the hold time of SDA during transmit in both slave and master mode (after SCL
goes from HIGH to LOW).
The bits [23:16] are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver (in either
master or slave mode).

31:24 23:16

15:0

Reserved
IC_SDA_RX_HOLD
IC_SDA_TX_HOLD

Figure I2C-65 IC_SDA_HOLD Register
If different SDA hold times are required for different speed modes, the IC_SDA_HOLD register must be
reprogrammed when the speed mode is being changed. The IC_SDA_HOLD register can be programmed only
when the DW_apb_i2c is disabled (IC_ENABLE[0] = 0).
The reset value of the IC_SDA_HOLD register can be set via the coreConsultant parameter
IC_DEFAULT_SDA_HOLD

3.7.3.10.1

SDA Hold Timings in Receiver

When DW_apb_i2c acts as a receiver, according to the I2C protocol, the device should internally－247/1293－

CXD5602 User Manualhold the SDA line to bridge undefined gap between logic 1 and logic 0 of SCL.
IC_SDA_RX_HOLD can be used to alter the internal hold time which DW_apb_i2c applies to theincoming SDA line. Each value in the IC_SDA_RX_HOLD register represents a unit of one ic_clk
period. The minimum value of IC_SDA_RX_HOLD is 0. This hold time is applicable only when
SCL is HIGH. The receiver does not extend the SDA after SCL goes LOW internally.
Figure I2C-66 shows the DW_apb_i2c as receiver with IC_SDA_RX_HOLD programmed to greaterthan or equal to 3.

ic_clkscl_int(Internal SCL after filter logic)
sda_post_spk_suppression(Internal signal after filter logic)
sda_int(SDA signal after filter and hold)
IC_SDA_RX_HOLD >= 3

Figure I2C-66 IC_SDA_RX_HOLD >= 3
If IC_SDA_RX_HOLD is greater than 3, DW_apb_i2c does not hold SDA beyond 3 ic_clk cycles, because SCL
goes LOW internally.
Figure I2C-67 shows the DW_apb_i2c as receiver with IC_SDA_RX_HOLD programmed to 2.

ic_clkscl_int(Internal SCL after filter logic)
sda_post_spk_suppression(Internal signal after filter logic)
sda_int(SDA signal after filter and hold)
IC_SDA_RX_HOLD = 2
Figure I2C-67 IC_SDA_RX_HOLD = 2

Speed Mode

Maximum IC_SDA_RX_HOLD Value

Standard Mode

IC_SS_SCL_HCNT - IC_FS_SPKLEN - 3－248/1293－

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Fast Mode

3.7.3.10.2

IC_FS_SCL_HCNT – IC_FS_SPKLEN - 3

SDA Hold Timings in Transmitter

The IC_SDA_TX_HOLD register can be used to alter the timing of the generated SDA (ic_data_oe) signal by the
DW_apb_i2c. Each value in the IC_SDA_TX_HOLD register represents a unit of one ic_clk period.
When the DW_apb_i2c is operating in Master Mode, the minimum tHD:DAT timing is one ic_clk period.
Therefore even when IC_SDA_TX_HOLD has a value of zero, the DW_apb_i2c will drive SDA (ic_data_oe) one
ic_clk cycle after driving SCL (ic_clk_oe) to logic 0. For all other values of IC_SDA_TX_HOLD, the following
is true:■ Drive on SDA (ic_data_oe) occurs IC_SDA_TX_HOLD ic_clk cycles after driving SCL (ic_clk_oe) to logic 0
When the DW_apb_i2c is operating in Slave Mode, the minimum tHD:DAT timing is SPKLEN + 7 ic_clk periods,
where SPKLEN is:■ IC_FS_SPKLEN if the component is operating in standard mode, fast mode, or fast mode plus
■ IC_HS_SPKLEN if the component is operating in high speed modeThis delay allows for synchronization and spike suppression on the SCL (ic_clk_in_a) sample. Therefore, evenwhen IC_SDA_TX_HOLD has a value less than SPKLEN + 7, the DW_apb_i2c drives SDA (ic_data_oe)
SPKLEN + 7 ic_clk cycles after SCL (ic_clk_in) has transitioned to logic 0. For all other values of
IC_SDA_TX_HOLD, the following is true:■ Drive on SDA (ic_data_oe) occurs IC_SDA_TX_HOLD ic_clk cycles after SCL (ic_clk_in_a) has transitioned
to logic 0.
Figure I2C-68 shows the tHD:DAT timing generated by the DW_apb_i2c operating in Master Modewhen IC_SDA_TX_HOLD = 3.
ic_clkic_data_oe
ic_clk_oe
IC_SDA_TX_HOLD = 3

Figure I2C-68 DW_apb_i2c Master Implementing tHD; DAT with IC_SDA_HOLD = 3

3.7.3.11

DMA Controller Interface

The DW_apb_i2c has an optional built-in DMA capability that can be selected at configuration time; it has a
handshaking interface to a DMA Controller to request and control transfers. The APB bus is used to perform thedata transfer to or from the DMA. While the DW_apb_i2c DMA operation is designed in a generic way to fit any－249/1293－

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DMA controller as easily as possible, it is designed to work seamlessly, and best used, with the DesignWare
DMA Controller, the DW_ahb_dmac. The settings of the DW_ahb_dmac that are relevant to the operation of theDW_apb_i2c are discussed here, mainly bit fields in the DW_ahb_dmac channel control register, CTLx, where x
is the channel number.
The relevant DMA settings are discussed in the following sections.

3.7.3.11.1

Enabling the DMA Controller Interface

To enable the DMA Controller interface on the DW_apb_i2c, you must write the DMA Control Register(IC_DMA_CR). Writing a one into the TDMAE bit field of IC_DMA_CR register enables the DW_apb_i2ctransmit handshaking interface. Writing a one into the RDMAE bit field of the IC_DMA_CR register enables theDW_apb_i2c receive handshaking interface.
For example, where the transfer count programmed into the DMA Controller is four. The DMA transfer consistsof a series of four single transactions. If the DW_apb_i2c makes a transmit request to this channel, a single data
item is written to the DW_apb_i2c TX FIFO. Similarly, if the DW_apb_i2c makes a receive request to thischannel, a single data item is read from the DW_apb_i2c RX FIFO. Four separate requests must be made to thisDMA channel before all four data items are written or read.

3.7.3.11.2

Watermark Levels

In DW_apb_i2c the registers for setting watermarks to allow DMA bursts do not need be set to anything otherthan their reset value. Specifically, IC_DMA_TDLR and IC_DMA_RDLR can be left at reset values of zero. Thisis because only single transfers are needed due to the low bandwidth of I2C relative to system bandwidth, and also
the DMA controller normally has highest priority on the system bus so will generally complete very quickly.

3.7.3.11.3

Overview of Operation

The DMA Controller is programmed with the number of data items (transfer count) that are to be transmitted or
received by DW_apb_i2c. The transfer is broken into single transfers on the bus, each initiated by a request fromthe DW_apb_i2c.

3.7.4

List of Registers

3.7.4.1 Register Map
OffsetName

Description

0x0000

IC_CONI2C Control Register

0x0004

IC_TARI2C Target Address Register－250/1293－

CXD5602 User Manual

0x0008IC_SARI2C Slave Address Register

0x000c

IC_HS_MADDR

I2C High Speed Master Mode Code Address Register0x0010

IC_DATA_CMD

I2C Rx/Tx Data Buffer and Command Register0x0014

IC_SS_SCL_HCNT

Standard Speed I2C Clock SCL High Count Register0x0018

IC_SS_SCL_LCNTStandard Speed I2C Clock SCL Low Count Register0x001cIC_FS_SCL_HCNTFast Mode I2C Clock SCL High Count Register

0x0020

IC_FS_SCL_LCNTFast Mode I2C Clock SCL Low Count Register

0x0024

IC_HS_SCL_HCNTHigh Speed I2C Clock SCL High Count Register

0x0028

IC_HS_SCL_LCNTHigh Speed I2C Clock SCL Low Count Register

0x002c

IC_INTR_STAT

I2C Interrupt Status Register

0x0030

IC_INTR_MASKI2C Interrupt Mask Register

0x0034

IC_RAW_INTR_STAT

I2C Raw Interrupt Status Register

0x0038

IC_RX_TL

I2C Receive FIFO Threshold Register

0x003cIC_TX_TL

I2C Transmit FIFO Threshold Register

0x0040

IC_CLR_INTR

Clear Combined and Individual Interrupt Register

0x0044

IC_CLR_RX_UNDER

Clear RX_UNDER Interrupt Register

0x0048IC_CLR_RX_OVER

Clear RX_OVER Interrupt Register

0x004cIC_CLR_TX_OVER

Clear TX_OVER Interrupt Register

0x0050

IC_CLR_RD_REQ

Clear RD_REQ Interrupt Register

0x0054

IC_CLR_TX_ABRT

Clear TX_ABRT Interrupt Register

0x0058IC_CLR_RX_DONE

Clear RX_DONE Interrupt Register

0x005cIC_CLR_ACTIVITY

Clear ACTIVITY Interrupt Register

0x0060

IC_CLR_STOP_DET

Clear STOP_DET Interrupt Register

0x0064

IC_CLR_START_DET

Clear START_DET Interrupt Register

0x0068IC_CLR_GEN_CALL

Clear GEN_CALL Interrupt Register

0x006c

IC_ENABLE

I2C ENABLE Register0x0070

IC_STATUS

I2C STATUS Register0x0074

IC_TXFLRI2C Transmit FIFO Level Register0x0078

IC_RXFLRI2C Receive FIFO Level Register0x007c

IC_SDA_HOLD

I2C SDA Hold Time Length Register

0x0080

IC_TX_ABRT_SOURCEI2C Transmit Abort Source Register

0x0084

IC_SLV_DATA_NACK_ONLY

Generate Slave Data NACK Register

0x0088IC_DMA_CRDMA Control Register

0x008c

IC_DMA_TDLRDMA Transmit Data Level Register

0x0090

IC_DMA_RDLRDMA Receive Data Level Register

0x0094

IC_SDA_SETUPI2C SDA Setup Register

0x0098

IC_ACK_GENERAL_CALL

I2C ACK General Call Regisster

0x009c

IC_ENABLE_STATUS

I2C Enable Status Register－251/1293－

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0x00a0

IC_FS_SPKLEN

I2C SS and FS Spike Suppression Limit Register

0x00a4

IC_HS_SPKLEN

I2C HS Spike Suppression Limit Register

0x00a8IC_CLR_RESTART_DET

Clear RESTART_DET Interrupt Register

0x00f4

IC_COMP_PARAM_1

Component Parameter Register 1

0x00f8

IC_COMP_VERSIONI2C Component Version Register

0x00fc

IC_COMP_TYPE

I2C Component Type Register

3.7.4.2 Registers and Field Descriptions
3.7.4.2.1

IC_CON (0x0000)

Description: I2C Control Register.
This register can be written only when the DW_apb_i2c is disabled, which corresponds to IC_ENABLE[0] being
set to 0. Writes at other times have no effect.
Table I2C-73 IC_CON
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:11]-

Reserved

STOP_DET_IF_M
ASTER_ACTIVE

R/W[10:10]0

RX_FIFO_FULL_
HLD_CTRL

R/W

[9:9]

0

TX_EMPTY_CTR
L

R/W

[8:8]

0

In Master mode
■ 0: Issues the STOP_DET irrespective of whether the master is active■ 1: Issues the STOP_DET interrupt only when the master is active
This bit controls whether DW_apb_i2c should hold the bus when the Rx
FIFO is physically full to its RX_BUFFER_DEPTH.
■ 0: Overflow when RX_FIFO is full
■ 1: Hold bus when RX_FIFO is fullThis bit controls the generation of the TX_EMPTY interrupt, as described in
the IC_RAW_INTR_STAT register.
■ 0: Default behaviour of TX_EMPTY interrupt■ 1: Controlled generation of TX_EMPTY interrupt

STOP_DET_IFAD
DRESSED

R/W

[7:7]

0

This register bit value is not applicable in the master mode.

IC_SLAVE_DISA
BLE

R/W

[6:6]

1

This bit controls whether I2C has its slave disabled, which means once thepresetn signal is applied, then this bit is set and the slave is disabled.
If this bit is set (slave is disabled), DW_apb_i2c functions only as a masterand does not perform any action that requires a slave.
■ 0 – slave is enabled■ 1 – slave is disabled
NOTE: Software should ensure that if this bit is written with ‘0,’ then bit 0
should also be written with a ‘0’.

－252/1293－

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IC_RESTART_EN

R/W

[5:5]

1

Determines whether RESTART conditions may be sent when acting as amaster. Some older slaves do not support handling RESTART conditions;however, RESTART conditions are used in several DW_apb_i2c operations.
■ 0: Master restart disable■ 1: Master restart enable
When the RESTART is disabled, the DW_apb_i2c master is incapable ofperforming the following functions:■ Sending a START BYTE
■ Performing any high-speed mode operation■ Performing direction changes in combined format mode
■ Performing a read operation with a 10-bit address
By replacing RESTART condition followed by a STOP and a subsequent
START condition, split operations are broken down into multiple
DW_apb_i2c transfers. If the above operations are performed, it will result insetting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.

IC_10BIT_ADDR_MASTER

R

[4:4]

1

This bit is read-only, and the function of this bit is handled by bit 12 of
IC_TAR register.
■ 0: Master 7-bit addressing■ 1: Master 10-bit addressing

IC_10BITADDR_S
LAVE

R/W

[3:3]

0

This register bit value is not applicable in the master mode.

SPEED

R/W

[2:1]

2

These bits control at which speed the DW_apb_i2c operates; its setting isrelevant only if one is operating the DW_apb_i2c in master mode. Hardware
protects against illegal values being programmed by software. This registershould be programmed only with a value in the range of 1 to
IC_MAX_SPEED_MODE; otherwise, hardware updates this register with thevalue of IC_MAX_SPEED_MODE.
■ 1: standard mode (0 to 100 Kb/s)■ 2: fast mode (≤ 400 Kb/s) or fast mode plus (≤ 1000 Kb/s)■ 3: high speed mode (≤ 3.4 Mb/s)

MASTER_MODE

R/W

[0:0]

1

This bit controls whether the DW_apb_i2c master is enabled.
■ 0: master disabled■ 1: master enabled
NOTE: Software should ensure that if this bit is written with ‘1,’ then bit 6
should also be written with a ‘1’.

3.7.4.2.2

IC_TAR (0x0004)

Description: I2C Target Address Register.
To write to IC_TAR succeed when one of the following conditions are true:■ DW_apb_i2c is NOT enabled (IC_ENABLE[0] is set to 0); or■ DW_apb_i2c is enabled (IC_ENABLE[0]=1); AND
DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0); AND
DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1); AND
there are NO entries in the Tx FIFO (IC_STATUS[2]=1)－253/1293－

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Table I2C-74 IC_TAR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:13]-

Reserved

IC_10BITADDR_MASTER

R/W[12:12]

1This bit controls whether the DW_apb_i2c starts its transfers in 7 or 10-bit
addressing mode when acting as a master.
■ 0: 7-bit addressing■ 1: 10-bit addressing

SPECIAL

R/W[11:11]0This bit indicates whether software performs a General Call or START BYTE
command.
■ 0: ignore bit 10 GC_OR_START and use IC_TAR normally■ 1: perform special I2C command as specified in GC_OR_START bit

GC_OR_START

R/W[10:10]0

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Callor START byte command is to be performed by the DW_apb_i2c.
■ 0: General Call Address – after issuing a General Call, only writes may be
performed. Attempting to issue a read command results in setting bit 6(TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c
remains in General Call mode until the SPECIAL bit value (bit 11) iscleared.
■ 1: START BYTEIC_TAR

R/W

[9:0]

0x55

This is the target address for any master transaction. When transmitting a
General Call, these bits are ignored. To generate a START BYTE, the CPU
needs to write only once into these bits.
If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs areshared between master and slave, so full loopback is not feasible. Only one
direction loopback mode is supported (simplex), not duplex. A master cannot
transmit to itself; it can transmit to only a slave.

3.7.4.2.3

IC_SAR (0x0008)

Description: I2C Slave Address Register.
Table I2C-75 IC_SAR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:10]-Reserved

IC_SAR

R/W

[9:0]

0x55

This register bit value is not applicable in the master mode.

3.7.4.2.4

IC_HS_MADDR (0x000c)

Description: I2C High Speed Master Mode Code Address Register.
Table I2C-76 IC_HS_MADDR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:3]-

Reserved－254/1293－

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IC_HS_MAR

R/W

[2:0]

0

This bit field holds the value of the I2C HS mode master code. HS-mode
master codes are reserved 8-bit codes (00001xxx) that are not used for slave
addressing or other purposes. Each master has its unique master code; up to
eight highspeed mode masters can be present on the same I2C bus system.
Valid values are from 0 to 7. This register goes away and becomes read-only
returning 0’s if the IC_MAX_SPEED_MODE configuration parameter is set
to either Standard (1) or Fast (2).
This register can be written only when the I2C interface is disabled, whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect.

3.7.4.2.5

IC_DATA_CMD (0x0010)

Description: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling
the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
Table I2C-77 IC_DATA_CMD
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:12]-

Reserved

FIRST_DATA_BY
TE

R[11:11]0

Indicates the first data byte received after the address phase for receive
transfer in Master receiver or Slave receiver mode.
Dependencies: This Register bit value is applicable only when
FIRST_DATA_BYTE_STATUS=1.

RESTARTW[10:10]0This bit controls whether a RESTART is issued before the byte is sent or
received.
■ 0: If IC_RESTART_EN is 1, a RESTART is issued only if the transfer
direction is changing from the previous command; if IC_RESTART_EN
is 0, a STOP followed by a START is issued instead.
■ 1: If IC_RESTART_EN is 1, a RESTART is issued before the data issent/received (according to the value of CMD), regardless of whether or
not the transfer direction is changing from the previous command; if
IC_RESTART_EN is 0, a STOP followed by a START is issued instead.

STOP

W

[9:9]

0

This bit controls whether a STOP is issued after the byte is sent or received.
■ 0: STOP is not issued after this byte, regardless of whether or not the Tx
FIFO is empty. If the Tx FIFO is not empty, the master continues thecurrent transfer by sending/receiving data bytes according to the valueof the CMD bit. If the Tx FIFO is empty, the master holds the SCL
line low and stalls the bus until a new command is available in the Tx
FIFO.
■ 1: STOP is issued after this byte, regardless of whether or not the Tx
FIFO is empty. If the Tx FIFO is not empty, the master immediately
tries to start a new transfer by issuing a START and arbitrating for thebus.

－255/1293－

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CMD

W

[8:8]

0

This bit controls whether a read or a write is performed. This bit does notcontrol the direction when the DW_apb_i2c acts as a slave. It controls only
the direction when it acts as a master.
■ 0 = Write■ 1 = Read
When a command is entered in the TX FIFO, this bit distinguishes the write
and read commands. In slave-receiver mode, this bit is a “don’t care”
because writes to this register are not required. In slave-transmitter mode, a“0” indicates that the data in IC_DATA_CMD is to be transmitted.
When programming this bit, you should remember the following: attempting
to perform a read operation after a General Call command has been sent
results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT
register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared.
If a “1” is written to this bit after receiving a RD_REQ interrupt, then a
TX_ABRT interrupt occurs.

DAT

R/W

[7:0]

0

This register contains the data to be transmitted or received on the I2C bus. If
you are writing to this register and want to perform a read, bits 7:0 (DAT) are
ignored by the DW_apb_i2c. However, when you read this register, these bits
return the value of data received on the DW_apb_i2c interface.

3.7.4.2.6

IC_SS_SCL_HCNT (0x0014)

Description: Standard Speed I2C Clock SCL High Count Register.
Table I2C-78 IC_SS_SCL_HCNTBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:16]-

Reserved

IC_SS_SCL_HCNT

R/W[15:0]

0x190

This register must be set before any I2C bus transaction can take place toensure proper I/O timing. This register sets the SCL clock high-period countfor standard speed. For more information, refer to “IC_CLK Frequency
Configuration”.
This register can be written only when the I2C interface is disabled whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect.
The minimum valid value is 6; hardware prevents values less than this being
written, and if attempted results in 6 being set.
NOTE: This register must not be programmed to a value higher than 65525,
because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition
when this counter reaches a value of IC_SS_SCL_HCNT + 10.

3.7.4.2.7

IC_SS_SCL_LCNT (0x0018)

Description: Standard Speed I2C Clock SCL Low Count Register.
Table I2C-79 IC_SS_SCL_LCNTBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:16]-

Reserved－256/1293－

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IC_SS_SCL_LCNT

R/W[15:0]

0x1d6

This register must be set before any I2C bus transaction can take place toensure proper I/O timing. This register sets the SCL clock low period countfor standard speed. For more information, refer to “IC_CLK Frequency
Configuration”.
This register can be written only when the I2C interface is disabled whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect.
The minimum valid value is 8; hardware prevents values less than this being
written, and if attempted, results in 8 being set. For designs with

3.7.4.2.8

IC_FS_SCL_HCNT (0x001c)

Description: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register.
Table I2C-80 IC_FS_SCL_HCNTBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:16]-

Reserved

IC_FS_SCL_HCNT

R/W[15:0]

0x3c

This register must be set before any I2C bus transaction can take place toensure proper I/O timing. This register sets the SCL clock high-period countfor fast mode or fast mode plus. It is used in high-speed mode to send theMaster Code and START BYTE or General CALL. For more information,refer to “IC_CLK Frequency Configuration”.
This register goes away and becomes read-only returning 0s if
IC_MAX_SPEED_MODE = standard. This register can be written only whenthe I2C interface is disabled, which corresponds to IC_ENABLE[0] being set
to 0. Writes at other times have no effect.
The minimum valid value is 6; hardware prevents values less than this being
written, and if attempted results in 6 being set.

3.7.4.2.9

IC_FS_SCL_LCNT (0x0020)

Description: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register.
Table I2C-81 IC_FS_SCL_LCNTBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:16]-

Reserved

IC_FS_SCL_LCNT

R/W[15:0]

0x82

This register must be set before any I2C bus transaction can take place toensure proper I/O timing. This register sets the SCL clock low period countfor fast mode or fast mode plus. It is used in high-speed mode to send theMaster Code and START BYTE or General CALL. For more information,refer to “IC_CLK Frequency Configuration”.
This register goes away and becomes read-only returning 0s if
IC_MAX_SPEED_MODE = standard.
This register can be written only when the I2C interface is disabled, whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect.
The minimum valid value is 8; hardware prevents values less than this being
written, and if attempted results in 8 being set.

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3.7.4.2.10

IC_HS_SCL_HCNT (0x0024)

Description: High Speed I2C Clock SCL High Count Register.
Table I2C-82 IC_HS_SCL_HCNTBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:16]-

Reserved

IC_HS_SCL_HCN
T

R/W[15:0]

0x6

This register must be set before any I2C bus transaction can take place toensure proper I/O timing. This register sets the SCL clock high period countfor high speed. For more information, refer to “IC_CLK Frequency
Configuration”.
The SCL High time depends on the loading of the bus. For 100pF loading, the
SCL High time is 60ns; for 400pF loading, the SCL High time is 120ns.
This register goes away and becomes read-only returning 0s if
IC_MAX_SPEED_MODE != high.
This register can be written only when the I2C interface is disabled, whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect.
The minimum valid value is 6; hardware prevents values less than this being
written, and if attempted results in 6 being set.

3.7.4.2.11

IC_HS_SCL_LCNT (0x0028)

Description: High Speed I2C Clock SCL Low Count Register.
Table I2C-83 IC_HS_SCL_LCNTBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:16]-

Reserved

IC_HS_SCL_LCN
T

R/W[15:0]

0x10

This register must be set before any I2C bus transaction can take place toensure proper I/O timing. This register sets the SCL clock low period countfor high speed. For more information, refer to “IC_CLK Frequency
Configuration”.
The SCL low time depends on the loading of the bus. For 100pF loading, the
SCL low time is 160ns; for 400pF loading, the SCL low time is 320ns.
This register goes away and becomes read-only returning 0s if
IC_MAX_SPEED_MODE != high.
This register can be written only when the I2C interface is disabled, whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect.
The minimum valid value is 8; hardware prevents values less than this being
written, and if attempted results in 8 being set.

3.7.4.2.12

IC_INTR_STAT (0x002c)

Description: I2C Interrupt Status Register. Each bit in this register has a corresponding mask bit in the－258/1293－

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IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked
raw versions of these bits are available in the IC_RAW_INTR_STAT register.
Table I2C-84 IC_INTR_STAT
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:14]-

Reserved

R_MST_ON_HOLD
R_RESTART_DET

R[13:13]0R[12:12]0

R_GEN_CALL

R[11:11]0

See IC_RAW_INTR_STAT for a detailed description of
R_MST_ON_HOLD bit.
See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET
bit.
See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.

R_START_DET

R[10:10]0

See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.

R_STOP_DET

R

[9:9]

0

See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.

R_ACTIVITY

R

[8:8]

0

See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.

R_RX_DONE

R

[7:7]

0

See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.

R_TX_ABRT

R

[6:6]

0

See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.

R_RD_REQ

R

[5:5]

0

See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.

R_TX_EMPTY

R

[4:4]

0

See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.

R_TX_OVER

R

[3:3]

0

See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.

R_RX_FULL

R

[2:2]

0

See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.

R_RX_OVER

R

[1:1]

0

See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.

R_RX_UNDER

R

[0:0]

0

See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.

3.7.4.2.13

IC_INTR_MASK (0x0030)

Description: I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register
is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.
Table I2C-85 IC_INTR_MASKBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:14]-

Reserved

M_MST_ON_HOL
D

R/W[13:13]0This bit masks the R_MST_ON_HOLD interrupt bit in the
IC_RAW_INTR_STAT register.

M_RESTART_DE
T

R/W[12:12]0This bit masks the R_RESTART_DET interrupt status bit in the
IC_RAW_INTR_STAT register.

M_GEN_CALL

R/W[11:11]

1

See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.

M_START_DET

R/W[10:10]0

See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.

M_STOP_DET

R/W

[9:9]

0

See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.

M_ACTIVITY

R/W

[8:8]

0

See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.

M_RX_DONE

R/W

[7:7]

1

See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.

M_TX_ABRT

R/W

[6:6]

1

See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.

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M_RD_REQ

R/W

[5:5]

1

See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.

M_TX_EMPTY

R/W

[4:4]

1

See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.

M_TX_OVER

R/W

[3:3]

1

See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.

M_RX_FULL

R/W

[2:2]

1

See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.

M_RX_OVER

R/W

[1:1]

1

See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.

M_RX_UNDER

R/W

[0:0]

1

See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.

3.7.4.2.14

IC_RAW_INTR_STAT (0x0034)

Description: I2C Raw Interrupt Status Register. These bits are not masked so they always show the true status of
the DW_apb_i2c.
Table I2C-86 IC_RAW_INTR_STAT
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:14]-

Reserved

MST_ON_HOLD

R[13:13]0

Indicates whether a master is holding the bus and the Tx FIFO is empty.

RESTART_DET

R[12:12]0This register bit value is not applicable in the master mode.
Indicates whether a RESTART condition has occurred on the I2C interface
when DW_apb_i2c is operating in slave mode and the slave is the addressedslave.

GEN_CALLR[11:11]0

Set only when a General Call address is received, and it is acknowledged. It
stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores thereceived data in the Rx buffer.

START_DETR[10:10]0

Indicates whether a START or RESTART condition has occurred on the I2C
interface regardless of whether DW_apb_i2c is operating in slave or master
mode.

STOP_DET

R

[9:9]

0

Indicates whether a STOP condition has occurred on the I2C interface
regardless of whether DW_apb_i2c is operating in slave or master mode.
In Master Mode:■ If IC_CON[10]=1’b1 (STOP_DET_IF_MASTER_ACTIVE), the
STOP_DET interrupt is issued only if the master is active.
■ If IC_CON[10]=1’b0 (STOP_DET_IFADDRESSED), the STOP_DET
interrupt is issued irrespective of whether the master is active.

ACTIVITY

R

[8:8]

0

This bit captures DW_apb_i2c activity and stays set until it is cleared. There
are four ways to clear it:■ Disabling the DW_apb_i2c■ Reading the IC_CLR_ACTIVITY register■ Reading the IC_CLR_INTR register■ System reset
Once this bit is set, it stays set unless one of the four methods is used to clear
it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
indicating that there was activity on the bus.

RX_DONE

R

[7:7]

0

This register bit value is not applicable in the master mode.
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if
the master does not acknowledge a transmitted byte. This occurs on the lastbyte of the transmission, indicating that the transmission is done.

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TX_ABRT

R

[6:6]

0

This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete
the intended actions on the contents of the transmit FIFO. This situation canoccur both as an I2C master or an I2C slave and is referred to as a “transmit
abort”.
When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates thereason why the transmit abort takes places.
NOTE: The DW_apb_i2c flushes/resets/empties only the TX_FIFO whenever
there is a transmit abort caused by any of the events tracked by the
IC_TX_ABRT_SOURCE register. The Tx FIFO remains in this flushedstate until the register IC_CLR_TX_ABRT is read. Once this read is
performed, the Tx FIFO is then ready to accept more data bytes from the
APB interface.

RD_REQ

R

[5:5]

0

This register bit value is not applicable in the master mode.
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C
master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds
the I2C bus in a wait state (SCL=0) until this interrupt is serviced, whichmeans that the slave has been addressed by a remote master that is asking fordata to be transferred. The processor must respond to this interrupt and thenwrite the requested data to the IC_DATA_CMD register. This bit is set to 0
just after the processor reads the IC_CLR_RD_REQ register.

TX_EMPTY

R

[4:4]

0

The behavior of the TX_EMPTY interrupt status differs based on the
TX_EMPTY_CTRL selection in the IC_CON register.
■ When TX_EMPTY_CTRL = 0:This bit is set to 1 when the transmit buffer is at or below the thresholdvalue set in the IC_TX_TL register.
■ When TX_EMPTY_CTRL = 1:
This bit is set to 1 when the transmit buffer is at or below the thresholdvalue set in the IC_TX_TL register and the transmission of theaddress/data from the internal shift register for the most recently popped
command is completed.
It is automatically cleared by hardware when the buffer level goes above thethreshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed andheld in reset. There the TX FIFO looks like it has no data within it, so this bit
is set to 1, provided there is activity in the master or slave state machines.
When there is no longer any activity, then with ic_en=0, this bit is set to 0.

TX_OVER

R

[3:3]

0

Set during transmit if the transmit buffer is filled to
IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C
command by writing to the IC_DATA_CMD register. When the module isdisabled, this bit keeps its level until the master or slave state machines go
into idle, and when ic_en goes to 0, this interrupt is cleared.

RX_FULL

R

[2:2]

0

Set when the receive buffer reaches or goes above the RX_TL threshold in
the IC_RX_TL register. It is automatically cleared by hardware when buffer
level goes below the threshold. If the module is disabled(IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the
RX FIFO is not full. So this bit is cleared once IC_ENABLE[0] is set to 0,
regardless of the activity that continues.

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RX_OVER

R

[1:1]

0

Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH andan additional byte is received from an external I2C device. The DW_apb_i2c
acknowledges this, but any data bytes received after the FIFO is full are lost.
If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until themaster or slave state machines go into idle, and when ic_en goes to 0, thisinterrupt is cleared.
NOTE: If the bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL)
is programmed to HIGH, then the RX_OVER interrupt never occurs,
because the Rx FIFO never overflows.

RX_UNDER

R

[0:0]

0

3.7.4.2.15

IC_RX_TL (0x0038)

Set if the processor attempts to read the receive buffer when it is empty byreading from the IC_DATA_CMD register. If the module is disabled(IC_ENABLE[0]=0), this bit keeps its level until the master or slave statemachines go into idle, and when ic_en goes to 0, this interrupt is cleared.

Description: I2C Receive FIFO Threshold Register.
Table I2C-87 IC_RX_TL
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:8]-

Reserved

RX_TL

R/W

[7:0]

0

Receive FIFO Threshold Level
Controls the level of entries (or above) that triggers the RX_FULL interrupt(bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with theadditional restriction that hardware does not allow this value to be set to avalue larger than the depth of the buffer. If an attempt is made to do that, theactual value set will be the maximum depth of the buffer.
A value of 0 sets the threshold for 1 entry, and a value of 255 sets thethreshold for 256 entries.

3.7.4.2.16

IC_TX_TL (0x003c)

Description: I2C Transmit FIFO Threshold Register.
Table I2C-88 IC_TX_TL
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:8]-

Reserved

TX_TL

R/W

[7:0]

0

Transmit FIFO Threshold Level
Controls the level of entries (or below) that trigger the TX_EMPTY interrupt(bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with theadditional restriction that it may not be set to value larger than the depth of
the buffer. If an attempt is made to do that, the actual value set will be themaximum depth of the buffer.
A value of 0 sets the threshold for 0 entries, and a value of 255 sets thethreshold for 255 entries.

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3.7.4.2.17

IC_CLR_INTR (0x0040)

Description: Clear Combined and Individual Interrupt Register.
Table I2C-89 IC_CLR_INTR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_INTR

R

[0:0]

0

Read this register to clear the combined interrupt, all individual interrupts,
and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware
clearable interrupts but software clearable interrupts. Refer to Bit 9 of the
IC_TX_ABRT_SOURCE register for an exception to clearing
IC_TX_ABRT_SOURCE.

3.7.4.2.18

IC_CLR_RX_UNDER (0x0044)

Description: Clear RX_UNDER Interrupt Register.
Table I2C-90 IC_CLR_RX_UNDER
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_RX_UNDER

R

[0:0]

0

Read this register to clear the RX_UNDER interrupt (bit 0) of the
IC_RAW_INTR_STAT register.

3.7.4.2.19

IC_CLR_RX_OVER (0x0048)

Description: Clear RX_OVER Interrupt Register.
Table I2C-91 IC_CLR_RX_OVER
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_RX_OVER

R

[0:0]

0

Read this register to clear the RX_OVER interrupt (bit 1) of the
IC_RAW_INTR_STAT register.

3.7.4.2.20

IC_CLR_TX_OVER (0x004c)

Description: Clear TX_OVER Interrupt Register.
Table I2C-92 IC_CLR_TX_OVER
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_TX_OVER

R

[0:0]

0

Read this register to clear the TX_OVER interrupt (bit 3) of the
IC_RAW_INTR_STAT register.

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3.7.4.2.21

IC_CLR_RD_REQ (0x0050)

Description: Clear RD_REQ Interrupt Register.
Table I2C-93 IC_CLR_RD_REQ
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_RD_REQ

R

[0:0]

0

Read this register to clear the RD_REQ interrupt (bit 5) of the
IC_RAW_INTR_STAT register.

3.7.4.2.22

IC_CLR_TX_ABRT (0x0054)

Description: Clear TX_ABRT Interrupt Register.
Table I2C-94 IC_CLR_TX_ABRTBit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_TX_ABRT

R

[0:0]

0

Read this register to clear the TX_ABRT interrupt (bit 6) of the
IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register.
This also releases the Tx FIFO from the flushed/reset state, allowing morewrites to the Tx FIFO. Refer to bit 9 of the IC_TX_ABRT_SOURCE register
for an exception to clearing IC_TX_ABRT_SOURCE.

3.7.4.2.23

IC_CLR_RX_DONE (0x0058)

Description: Clear RX_DONE Interrupt Register.
Table I2C-95 IC_CLR_RX_DONE
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_RX_DONE

R

[0:0]

0

Read this register to clear the RX_DONE interrupt (bit 7) of the
IC_RAW_INTR_STAT register.

3.7.4.2.24

IC_CLR_ACTIVITY (0x005c)

Description: Clear ACTIVITY Interrupt Register.
Table I2C-96 IC_CLR_ACTIVITY
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

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CLR_ACTIVITY

R

[0:0]

0

Reading this register clears the ACTIVITY interrupt if the I2C is not active
anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt
bit continues to be set. It is automatically cleared by hardware if the module isdisabled and if there is no further activity on the bus. The value read from thisregister to get status of the ACTIVITY interrupt (bit 8) of the
IC_RAW_INTR_STAT register.

3.7.4.2.25

IC_CLR_STOP_DET (0x0060)

Description: Clear STOP_DET Interrupt Register.
Table I2C-97 IC_CLR_STOP_DET
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_STOP_DET

R

[0:0]

0

Read this register to clear the STOP_DET interrupt (bit 9) of the
IC_RAW_INTR_STAT register.

3.7.4.2.26

IC_CLR_START_DET (0x0064)

Description: Clear START_DET Interrupt Register.
Table I2C-98 IC_CLR_START_DET
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_START_DET

R

[0:0]

0

Read this register to clear the START_DET interrupt (bit 10) of the
IC_RAW_INTR_STAT register.

3.7.4.2.27

IC_CLR_GEN_CALL (0x0068)

Description: Clear GEN_CALL Interrupt Register.
Table I2C-99 IC_CLR_GEN_CALL
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_GEN_CALL

R

[0:0]

0

Read this register to clear the GEN_CALL interrupt (bit 11) of
IC_RAW_INTR_STAT register.

3.7.4.2.28

IC_ENABLE (0x006c)

Description: I2C Enable Register.
Table I2C-100 IC_ENABLE
Bit Field

Type

Bit

InitialDescription－265/1293－

CXD5602 User Manual

Reserved

N/A[31:3]-

Reserved

TX_CMD_BLOCK

R/W

[2:2]

0

In Master mode
■ 0: The transmission of data starts on I2C bus automatically, as soon as thefirst data is available in the Tx FIFO.
■ 1: Blocks the transmission of data on I2C bus even if Tx FIFO has data totransmit.

ABORT

R/W

[1:1]

0

Note: To block the execution of Master commands, set the
TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]=1) andthe master is in the Idle state (IC_STATUS[5] == 0). Any further commands
put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset.
When set, the controller initiates the transfer abort.
■ 0: ABORT not initiated or ABORT done
■ 1: ABORT operation in progress

ENABLE

R/W

[0:0]

0

The software can abort the I2C transfer in master mode by setting this bit.
The software can set this bit only when ENABLE is already set; otherwise,
the controller ignores any write to ABORT bit. The software cannot clear the
ABORT bit once set. In response to an ABORT, the controller issues a STOP
and flushes the Tx FIFO after completing the current transfer, then sets the
TX_ABORT interrupt after the abort operation. The ABORT bit is cleared
automatically after the abort operation. For a detailed description on how toabort I2C transfers, refer to “Aborting I2C Transfers” on page 57.
Controls whether the DW_apb_i2c is enabled.
■ 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state)■ 1: Enables DW_apb_i2c
Software can disable DW_apb_i2c while it is active. However, it is importantthat care be taken to ensure that DW_apb_i2c is disabled properly. A
recommended procedure is described in “Disabling DW_apb_i2c”. When
DW_apb_i2c is disabled, the following occurs:■ The TX FIFO and RX FIFO get flushed.
■ Status bits in the IC_INTR_STAT register, are still active until
DW_apb_i2c goes into IDLE state.
If the module is transmitting, it stops as well as deletes the contents of thetransmit buffer after the current transfer is complete. If the module isreceiving, the DW_apb_i2c stops the current transfer at the end of the current
byte and does not acknowledge the transfer. In systems with asynchronous
pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1),there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For adetailed description on how to disable DW_apb_i2c, refer to “IC_CLK
Frequency Configuration”.

3.7.4.2.29

IC_STATUS (0x0070)

Description: I2C Status Register. This is a read-only register used to indicate the current transfer status and FIFO
status. The status register may be read at any time. None of the bits in this register request an interrupt.
When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register:■ Bits 1 and 2 are set to 1
■ Bits 3 to 10 are set to 0
When the master or slave state machines goes to idle and ic_en=0:■ Bits 5 and 6 are set to 0－266/1293－

CXD5602 User Manual

Table I2C-101 IC_STATUS
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:11]-

Reserved

SLV_HOLD_RX_F
IFO_FULL

R[10:10]0

SLV_HOLD_TX_F
IFO_EMPTY

R

[9:9]

0

MST_HOLD_RX_
FIFO_FULL

R

[8:8]

0

This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Fulland an additional byte being received.
Dependencies: This Register bit value is applicable only when
IC_STAT_FOR_CLK_STRETCH=1.
This bit indicates the BUS Hold in Slave mode for the Read request when the
Tx FIFO is empty. The Bus is in hold until the Tx FIFO has data to Transmit
for the read request.
Dependencies: This Register bit value is applicable only when
IC_STAT_FOR_CLK_STRETCH=1.
This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full andadditional byte has been received.
Dependencies: This Register bit value is applicable only when

MST_HOLD_TX_
FIFO_EMPTY

R

[7:7]

0

IC_STAT_FOR_CLK_STRETCH=1
The DW_apb_i2c master stalls the write transfer when Tx FIFO is empty, andthe last byte does not have the Stop bit set.
This bit indicates the BUS hold when the master holds the bus because of theTx FIFO being empty, and the the previous transferred command does nothave the Stop bit set.
Dependencies: This Register bit value is applicable only when

SLV_ACTIVITY

R

[6:6]

0

IC_STAT_FOR_CLK_STRETCH=1
Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is
not in the IDLE state, this bit is set.
■ 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not
Active■ 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is
ActiveMST_ACTIVITY

R

[5:5]

0

Master FSM Activity Status. When the Master Finite State Machine (FSM) is
not in the IDLE state, this bit is set.
■ 0: Master FSM is in IDLE state so the Master part ofDW_apb_i2c is not Active■ 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is
Active

RFF

R

[4:4]

0

NOTE: IC_STATUS[0]—that is, ACTIVITY bit—is the OR of
SLV_ACTIVITY and MST_ACTIVITY bits
Receive FIFO Completely Full. When the receive FIFO is completely full,
this bit is set. When the receive FIFO contains one or more empty location,
this bit is cleared.
■ 0: Receive FIFO is not full
■ 1: Receive FIFO is full

RFNE

R

[3:3]

0

Receive FIFO Not Empty. This bit is set when the receive FIFO contains one
or more entries; it is cleared when the receive FIFO is empty.
■ 0: Receive FIFO is empty■ 1: Receive FIFO is not empty－267/1293－

CXD5602 User Manual

TFE

R

[2:2]

0

Transmit FIFO Completely Empty. When the transmit FIFO is completely
empty, this bit is set. When it contains one or more valid entries, this bit iscleared. This bit field does not request an interrupt.
■ 0: Transmit FIFO is not empty■ 1: Transmit FIFO is empty

TFNF

R

[1:1]

0

Transmit FIFO Not Full. Set when the transmit FIFO contains one or more
empty locations and is cleared when the FIFO is full.
■ 0: Transmit FIFO is full
■ 1: Transmit FIFO is not full

ACTIVITY

R

[0:0]

0

I2C Activity Status

3.7.4.2.30

IC_TXFLR (0x0074)

Description: I2C Transmit FIFO Level Register. This register contains the number of valid data entries in thetransmit FIFO buffer. It is cleared whenever:■ The I2C is disabled■ There is a transmit abort—that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register■ The slave bulk transmit mode is aborted
The register increments whenever data is placed into the transmit FIFO and decrements when data is taken fromthe transmit FIFO.
Table I2C-102 IC_TXFLR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:6]-

Reserved

TXFLR

R

[5:0]

0

Transmit FIFO Level. Contains the number of valid data entries in thetransmit FIFO.

3.7.4.2.31

IC_RXFLR (0x0078)

Description: I2C Receive FIFO Level Register. This register contains the number of valid data entries in thereceive FIFO buffer. It is cleared whenever:■ The I2C is disabled■ Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE
The register increments whenever data is placed into the receive FIFO and decrements when data is taken fromthe receive FIFO.
Table I2C-103 IC_RXFLR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:6]-

Reserved

RXFLR

R

[5:0]

0

Receive FIFO Level. Contains the number of valid data entries in the receive
FIFO.

－268/1293－

CXD5602 User Manual

3.7.4.2.32

IC_SDA_HOLD (0x007c)

Description: I2C SDA Hold Time Length Register. The bits [15:0] of this register are used to control the holdtime of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
The bits [23:16] of this register rare used to extend the SDA transition (if any) whenever SCL is HIGH in thereceiver in either master or slave mode.
Writes to this register succeed only when IC_ENABLE[0]=0.
The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be
greater than the minimum hold time in each mode —one cycle in master mode, seven cycles in slave mode —forthe value to be implemented.
The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the durationof the low part of scl. Therefore, the programmed value cannot be larger than N_SCL_LOW-2, where
N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.
Table I2C-104 IC_SDA_HOLD
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:24]-

Reserved

IC_SDA_RX_HOL
D
IC_SDA_TX_HOL
D

R/W[23:16]

R/W[15:0]

3.7.4.2.33

IC_TX_ABRT_SOURCE (0x0080)

Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c
acts as a reciever. Reset value: IC_DEFAULT_SDA_HOLD
Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c
acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD

Description: I2C Transmit Abort Source Register. This register has 32 bits that indicate the source of the
TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the
IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first;
RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the
GC_OR_START bit must be cleared (IC_TAR[10]).
Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner asother bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear
this bit, Bit 9 clears for one cycle and is then re-asserted.
Table I2C-105 IC_TX_ABRT_SOURCEBit Field

Type

Bit

InitialDescription

TX_FLUSH_CNT

R[31:23]-0Reserved

N/A[22:17]-This field indicates the number of Tx FIFO data commands that are flushed
due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.
Reserved

ABRT_USER_AB
RT

R[16:16]0This is a master-mode-only bit. Master has detected the transfer abort(IC_ENABLE[1]).

－269/1293－

CXD5602 User Manual

ABRT_SLVRD_IN
TX

R[15:15]0

1: When the processor side responds to a slave mode request for data to betransmitted to a remote master and user writes a 1 in CMD (bit 8) of
IC_DATA_CMD register.
■ 1: Slave lost the bus while transmitting data to a remote master.
IC_TX_ABRT_SOURCE[12] is set at the same time. NOTE: Even though
the slave never “owns” the bus, something could go wrong on the bus. This isa fail safe check. For instance, during a data transmission at the low-to-hightransition of SCL, if what is on the data bus is not what is supposed to betransmitted, then DW_apb_i2c no longer own the bus.
1: Slave has received a read command and some data exists in the TX FIFO
so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set,
then the slave transmitter has lost arbitration.
1: User tries to initiate a Master operation with the Master mode disabled.

ABRT_SLV_ARB
LOST

R[14:14]0

ABRT_SLVFLUS
H_TXFIFORRB_LOSTR[13:13]0R[12:12]0

ABRT_MASTER_DISABRT_10B_RD_N
ORSTRT
ABRT_SBYTE_N
ORSTRT

R[11:11]0R[10:10]

0

R

[9:9]

0

ABRT_HS_NORS
TRT
ABRT_SBYTE_A
CKDETABRT_HS_ACKD
ET
ABRT_GCALL_R
EAD

R

[8:8]

0

R

[7:7]

0

R

[6:6]

0

R

[5:5]

0

ABRT_GCALL_N
OACK
ABRT_TXDATA_
NOACK

R

[4:4]

0

R

[3:3]

0

ABRT_10ADDR2_NOACK
ABRT_10ADDR1_NOACK
ABRT_7B_ADDR_
NOACK

R

[2:2]

0

R

[1:1]

0

R

[0:0]

0

3.7.4.2.34

IC_SLV_DATA_NACK_ONLY (0x0084)

1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and themaster sends a read command in 10-bit addressing mode.
To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed
first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be
cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared(IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed,
then this bit can be cleared in the same manner as other bits in this register. If
the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting
to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The
restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user istrying to send a START Byte.
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and theuser is trying to use the master to transfer data in High Speed mode.
1: Master has sent a START Byte and the START Byte was acknowledged(wrong behavior).
1: Master is in High Speed mode and the High Speed Master code was
acknowledged (wrong behavior).
■ 1: DW_apb_i2c in master mode sent a General Call but the user
programmed the byte following the General Call to be a read from the bus(IC_DATA_CMD[9] is set to 1).
1: DW_apb_i2c in master mode sent a General Call and no slave on the bus
acknowledged the General Call.
1: This is a master-mode only bit. Master has received an acknowledgement
for the address, but when it sent data byte(s) following the address, it did notreceive an acknowledge from the remote slave(s).
1: Master is in 10-bit address mode and the second address byte of the 10-bit
address was not acknowledged by any slave.
1: Master is in 10-bit address mode and the first 10-bit address byte was not
acknowledged by any slave.
1: Master is in 7-bit addressing mode and the address sent was not
acknowledged by any slave.

Description: Generate Slave Data NACK Register. The register is used to generate a NACK for the data part of atransfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the
IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist
and writing to the register’s address has no effect.

－270/1293－

CXD5602 User Manual

A write can occur on this register if both of the following conditions are met:
■ DW_apb_i2c is disabled (IC_ENABLE[0] = 0)
■ Slave part is inactive (IC_STATUS[6] = 0)

Table I2C-106 IC_SLV_DATA_NACK_ONLY
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

NACK

R/W

[0:0]

0

Generate NACK. This NACK generation only occurs when DW_apb_i2c is aslave-receiver. If this register is set to a value of 1, it can only generate a
NACK after a data byte is received; hence, the data transfer is aborted, andthe data received is not pushed to the receive buffer. When the register is set
to a value of 0, it generates NACK/ACK, depending on normal criteria.
■ 0 = generate NACK/ACK normally■ 1 = generate NACK after data byte received

3.7.4.2.35

IC_DMA_CR (0x0088)

Description: DMA Control Register.
This register is only valid when DW_apb_i2c is configured with a set of DMA Controller interface signals(IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation, this register does not exist andwriting to the register’s address has no effect and reading from this register address will return zero. The register
is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This canbe programmed regardless of the state of IC_ENABLE.
Table I2C-107 IC_DMA_CR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:2]-

Reserved

TDMAE

R/W

[1:1]

0

RDMAE

R/W

[0:0]

0

Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA
channel.
■ 0 = Transmit DMA disabled■ 1 = Transmit DMA enabled
Receive DMA Enable. This bit enables/disables the receive FIFO DMA
channel.
■ 0 = Receive DMA disabled■ 1 = Receive DMA enabled

3.7.4.2.36

IC_DMA_TDLR (0x008c)

Description: DMA Transmit Data Level Register. This register is only valid when the DW_apb_i2c is configured
with a set of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA
operation, this register does not exist; writing to its address has no effect; reading from its address returns zero.
Table I2C-108 IC_DMA_TDLR－271/1293－

CXD5602 User Manual

Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:5]-

Reserved

DMATDL

R/W

[4:0]

0

Transmit Data Level. This bit field controls the level at which a DMA request
is made by the transmit logic. It is equal to the watermark level; that is, thedma_tx_req signal is generated when the number of valid data entries in thetransmit FIFO is equal to or below this field value, and TDMAE = 1.

3.7.4.2.37

IC_DMA_RDLR (0x0090)

Description: I2C Receive Data Level Register. This register is only valid when DW_apb_i2c is configured with aset of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation, thisregister does not exist; writing to its address has no effect; reading from its address returns zero.
Table I2C-109 IC_DMA_RDLR
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:5]-

Reserved

DMARDL

R/W

[4:0]

0

Receive Data Level. This bit field controls the level at which a DMA request
is made by the receive logic. The watermark level = DMARDL+1; that is,
dma_rx_req is generated when the number of valid data entries in the receive
FIFO is equal to or more than this field value + 1, and RDMAE = 1. For
instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or moredata entries are present in the receive FIFO.

3.7.4.2.38

IC_SDA_SETUP (0x0094)

Description: I2C SDA Setup Register. This register controls the amount of time delay (in terms of number of
ic_clk clock periods) introduced in the rising edge of SCL—relative to SDA changing—by holding SCL low
when DW_apb_i2c services a read request while operating as a slave-transmitter. The relevant I2C requirement is
tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal
to or greater than 2.
Writes to this register succeed only when IC_ENABLE[0] = 0.
Table I2C-110 IC_SDA_SETUP
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:8]-

Reserved

SDA_SETUP

R/W

[7:0]

0x64

SDA Setup. It is recommended that if the required delay is 1000ns, then foran ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to avalue of 11. IC_SDA_SETUP must be programmed with a minimum value of2.

3.7.4.2.39

IC_ACK_GENERAL_CALL (0x0098)

Description: I2C ACK General Call Register. The register controls whether DW_apb_i2c responds with an ACK
or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is－272/1293－

CXD5602 User Manualin the slave mode.
Table I2C-111 IC_ACK_GENERAL_CALL
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

ACK_GEN_CALL

R/W

[0:0]

1

This register bit value is not applicable in the master mode.
ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (byasserting ic_data_oe) when it receives a General Call. When set to 0, theDW_apb_i2c does not generate General Call interrupts.

3.7.4.2.40

IC_ENABLE_STATUS (0x009c)

Description: I2C Enable Status Register. The register is used to report the DW_apb_i2c hardware status when
IC_ENABLE[0] is set from 1 to 0; that is, when DW_apb_i2c is disabled.
If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as ‘0’.
When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling theDW_apb_i2c depends on I2C bus activities.
Table I2C-112 IC_ENABLE_STATUS
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:3]-

Reserved

SLV_RX_DATA_L
OST

R

[2:2]

0

Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has
been aborted with at least one data byte received from an I2C transfer due tosetting IC_ENABLE[0] from 1 to 0. When read as 1, DW_apb_i2c is deemed
to have been actively engaged in an aborted I2C transfer (with matching
address) and the data phase of the I2C transfer has been entered, even thougha data byte has been responded with a NACK.
NOTE: If the remote I2C master terminates the transfer with a STOP
condition before the DW_apb_i2c has a chance to NACK a transfer, and
IC_ENABLE [0] has been set to 0, then this bit is also set to 1. When read as
0, DW_apb_i2c is deemed to have been disabled without being actively
involved in the data phase of a Slave- Receiver transfer.
NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.

－273/1293－

CXD5602 User Manual

SLV_DISABLED_
WHILE_BUSY

R

[1:1]

0

Slave Disabled While Busy (Transmit, Receive). This bit indicates if apotential or active Slave operation has been aborted due to setting bit 0 of the
IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to
bit 0 of IC_ENABLE while: (a) DW_apb_i2c is receiving the address byte of
the Slave-Transmitter operation from a remote master; OR, (b) address anddata bytes of the Slave-Receiver operation from a remote master. When readas 1, DW_apb_i2c is deemed to have forced a NACK during any part of an
I2C transfer, irrespective of whether the I2C address matches the slave
address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed
before bit 0 of IC_ENABLE is set to 0, but has not taken effect.
NOTE: If the remote I2C master terminates the transfer with a STOP
condition before the DW_apb_i2c has a chance to NACK a transfer, and bit 0of IC_ENABLE has been set to 0, then this bit will also be set to 1. Whenread as 0, DW_apb_i2c is deemed to have been disabled when there is master
activity, or when the I2C bus is idle.
NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
ic_en Status. This bit always reflects the value driven on the output port
ic_en. ■ When read as 1, DW_apb_i2c is deemed to be in an enabled state. ■When read as 0, DW_apb_i2c is deemed completely inactive. NOTE: The
CPU can safely read this bit anytime. When this bit is read as 0, the CPU cansafely read SLV_RX_DATA_LOST (bit 2) and
SLV_DISABLED_WHILE_BUSY (bit 1).

IC_EN

R

[0:0]

0

3.7.4.2.41

IC_FS_SPKLEN (0x00a0)

Description: I2C SS and FS Spike Suppression Limit Register. This register is used to store the duration,measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when thecomponent is operating in standard mode, fast mode, or fast mode plus. The relevant I2C requirement is tSP(Table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
Table I2C-113 IC_FS_SPKLEN
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:8]-

Reserved

IC_FS_SPKLEN

R/W

[7:0]

0x1

This register must be set before any I2C bus transaction can take place toensure stable operation. This register sets the duration, measured in ic_clk
cycles, of the longest spike in the SCL or SDA lines that are filtered out by
the spike suppression logic; for more information, refer to “SpikeSuppression”.
This register can be written only when the I2C interface is disabled, whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect.
The minimum valid value is 1; hardware prevents values less than this being
written, and if attempted, results in 1 being set.

3.7.4.2.42

IC_HS_SPKLEN (0x00a4)

Description: I2C HS Spike Suppression Limit Register.
This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the
spike suppression logic when the component is operating in HS mode. The relevant I2C requirement is tSP (Table－274/1293－

CXD5602 User Manual

6) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1 and is
implemented only if the component is configured to support HS mode; that is, if the IC_MAX_SPEED_MODE
parameter is set to 3.
Table I2C-114 IC_HS_SPKLEN
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:8]-

Reserved

IC_HS_SPKLEN

R/W

[7:0]

0

This register must be set before any I2C bus transaction can take place toensure stable operation. This register sets the duration, measured in ic_clk
cycles, of the longest spike in the SCL or SDA lines that are filtered out by
the spike suppression logic; for more information, refer to “SpikeSuppression”.
This register can be written only when the I2C interface is disabled, whichcorresponds to IC_ENABLE[0] being set to 0. Writes at other times have noeffect. The minimum valid value is 1; hardware prevents values less than thisbeing written, and if attempted, results in 1 being set. This register isimplemented only if the component is configured to support HS mode; that is,if the IC_MAX_SPEED_MODE parameter is set to 3.

3.7.4.2.43

IC_CLR_RESTART_DET (0x00a8)

Description: Clear RESTART_DET Interrupt Register.
Table I2C-115 IC_CLR_RESTART_DET
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:1]-

Reserved

CLR_RESTART_D
ET

R

[0:0]

0

This register bit value is not applicable in the master mode.
Read this register to clear the RESTART_DET interrupt (bit 12) of the
IC_RAW_INTR_STAT register.

3.7.4.2.44

IC_COMP_PARAM_1 (0x00f4)

Description: Component Parameter Register 1.
Table I2C-116 IC_COMP_PARAM_1
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[31:24]-

Reserved

TX_BUFFER_DEP
TH

R[23:16]0x31

This is the configuration value of IC_TX_BUFFER_DEPTH.
■ 0x00 = Reserved■ 0x01 = 2■ 0x02 = 3…
■ 0xFF = 256－275/1293－

CXD5602 User Manual

RX_BUFFER_DEP
TH

R[15:8]

0x31

This is the configuration value of IC_RX_BUFFER_DEPTH.
■ 0x00 = Reserved■ 0x01 = 2■ 0x02 = 3…
■ 0xFF = 256

ADD_ENCODED_PARAMS

R

[7:7]

1

This is the IC_ADD_ENCODED_PARAMS parameter.
Reading 1 in this bit means that the capability of reading these encodedparameters via software has been included. Otherwise, the entire register is 0
regardless of the setting of any other parameters that are encoded in the bits.
■ 0: False

HAS_DMA

R[6:6]■ 1: True
This is the IC_HAS_DMA parameter.

1■ 0: False
INTR_IO

R[5:5]■ 1: True
This is the IC_INTR_IO parameter.

0■ 0: Individual■ 1: Combined
This is the IC_HC_COUNT_VALUES parameter.
■ 0: False

HC_COUNT_VAL
UES

R

[4:4]

0

MAX_SPEED_MO
DE

R

[3:2]

0x2

APB_DATA_WID
TH

R

[1:0]

0x2

3.7.4.2.45

IC_COMP_VERSION (0x00f8)■ 1: True
This is the IC_MAX_SPEED_MODE parameter.
■ 0x0 = Reserved■ 0x1 = Standard■ 0x2 = Fast
■ 0x3 = HighThis is the APB_DATA_WIDTH parameter.
■ 0x0 = 8 bits
■ 0x1 = 16 bits
■ 0x2 = 32 bits
■ 0x3 = Reserved

Description: I2C Component Version Register.
Table I2C-117 IC_COMP_VERSION
Bit Field

Type

Bit

InitialDescription

IC_COMP_VERSI
ON

R[31:0]

0x3132312a

Component version value.

3.7.4.2.46

IC_COMP_TYPE (0x00fc)

Description: I2C Component Type Register.
Table I2C-118 IC_COMP_TYPE
Bit Field

Type

Bit

InitialDescription－276/1293－

CXD5602 User Manual

IC_COMP_TYPE

R[31:0]

0x44570140

Designware Component Type number = 0x44_57_01_40. This
assigned unique hex value is constant and is derived from the two
ASCII letters “DW” followed by a 16-bit unsigned number.

－277/1293－

CXD5602 User Manual

3.8

DMAC

3.8.1

Overview and Features

List of DMACs


SDMAC (Power domain: PWD_SYSIOP)The SDMAC is for the Sensor and performs DMA transfer between the SCU and each SRAMHDMAC (Power domain: PWD_SYSIOP)
The HDMAC is for the HOSTIFC and performs DMA transfer between the HOSTIFC and each SRAMSYDMAC (Power domain: PWD_SYSIOP)The SYDMAC is for the System and performs DMA transfer between each SRAMSYSUBDMAC (Power domain: PWD_SYSIOP_SUB)The SYSUBDMAC is for the System and performs DMA transfer of each SRAM, and data store andload to/from the FLASHADMAC (Power domain: PWD_APP_DSP)
The ADMAC is for the Application processor and performs DMA transfer between each SRAMIDMAC (Power domain: PWD_APP_SUB)
The IDMAC performs DMA transfer of the Display and Wi-Fi data

3.8.2


Function Descriptions

SDMAC
The PrimeCell® µDMA Controller (PL230) from ARM Limited is equipped. There are 32 channels of DMA
channels. For details, refer to the PrimeCell® µDMA Controller (PL230) Technical Reference Manual.
This Controller adds a feature to notify the CPU of independent interrrupts of each DMA channel.



HDMAC, SYDMAC, SYSUBDMAC, ADMAC
The PrimeCell® Single Master DMA Controller (PL081) from ARM Limited is equipped. For details, refer tothe PrimeCell® Single Master DMA Controller (PL081) Technical Reference Manual.
This Controller adds a feature to notify the CPU of independent interrrupts of each DMA channel.



IDMAC
The functions have been modified based on the PrimeCell® DMA Controller (PL080) from ARM Limited.

－278/1293－

CXD5602 User Manual

Table DMAC-119 shows the DMA request bit assignment for Memory-to-peripheral transfer andPeripheral-to-memory transfer of each DMAC. The ADMAC supports Memory-to-memory transfer only.
Table DMAC-119 DMA Request Bit Assignment
Request Bit

SDMAC

HDMAC

SYDMACSYSUBDMAC

ADMAC

IDMAC

[0]

SPI3 TX

I2C3 TX

Reserved

Reserved

Reserved

UART2 TX

[1]

SPI3 RXI2C3 RX

Reserved

Reserved

Reserved

UART2 RX[2]

I2C0 TXSPI2 TX

Reserved

I2C2 TX

Reserved

SPI4 TX[3]

I2C0 RXSPI2 RX

Reserved

I2C2 RX

Reserved

SPI4 RX[4]

I2C1 TXHOSTIFC

Reserved

UART1 TX

Reserved

SPI5 TX[5]

I2C1 RXUART0 TX

Reserved

UART1 RX

Reserved

SPI5 RX[6]

LPADC0

UART0 RX

Reserved

SPI0 TX

Reserved

Reserved[7]

LPADC1

Reserved

Reserved

SPI0 RX

Reserved

Reserved[8]

LPADC2

Reserved

Reserved

Reserved

Reserved

Reserved[9]

LPADC3

Reserved

Reserved

Reserved

Reserved

Reserved[10]

HPADC0Reserved

Reserved

Reserved

Reserved

Reserved[11]

HPADC1

Reserved

Reserved

Reserved

Reserved

Reserved[12]

SCU FIFO RX(1)Reserved

Reserved

Reserved

Reserved

Reserved[13]

SCU FIFO RX(2)Reserved

Reserved

Reserved

Reserved

Reserved[14]

SCU FIFO RX(3)Reserved

Reserved

Reserved

Reserved

Reserved[15]

SCU FIFO RX(4)Reserved

Reserved

Reserved

Reserved

Reserved[16]

SCU FIFO RX(5)

-

-

-

-

-

[17]

SCU FIFO RX(6)

-

-

-

-

-

[18]

SCU FIFO RX(7)

-

-

-

-

-

[19]

SCU FIFO RX(8)

-

-

-

-

-

[20]

SCU FIFO RX(9)

-

-

-

-

-

[21]

SCU FIFO RX(10)

-

-

-

-

-

[22]

SCU FIFO RX(11)

-

-

-

-

-

[23]

SCU FIFO RX(12)

-

-

-

-

-

[24]

SCU FIFO RX(13)

-

-

-

-

-

[25]

SCU FIFO RX(14)

-

-

-

-

-

－279/1293－

CXD5602 User Manual

3.8.3

SDMAC

Adds a feature to notify the CPU of independent interrupts or each DMA channel to the PrimeCell® µDMA
Controller (PL230).


The interrupt signal is changed from pulse to levelThe interrupt factor register (dma_done, dma_err) is added.

Figure DMAC-69 shows an overview of the independent interrupt signals of each DMA channel.

SDMAC

dma_done(pulse)slave_error(pulse)Interrupt Clear

Additional logic
32

32

set
clear

(level)set
clear

to CPU Interrupt

SDMAC(PL230)Interrupt Status
RegisterFigure DMAC-69 SDMAC Overview of Added Functions－280/1293－

CXD5602 User Manual

3.8.3.1 Register List
Table DMAC-120 shows the registers that control the SDMAC.
Table DMAC-120 SDMAC Control Register List
Address

Register NameType

Description

initialValue

PrimeCell® µDMA Controller (PL230) register-

0x04120050

dma_done

RW

Notifies DMA transfer completion of each DMA channel

0x0

0x04120054

dma_err

RW

Notifies AHB error occurrence of each DMA channel

0x0

0x04120058

ReservedRO

Reserved

0x0

0x04120000|
0x0412004C|
0x04120DFC
0x04120E00

PrimeCell® µDMA Controller (PL230) register|
0x04120FFC－281/1293－-

CXD5602 User Manual

3.8.3.2 Register Descriptions
Table DMAC-121 shows descriptions of the registers added to the SDMAC.
Table DMAC-121 SDMAC Added Registers
Address

Register Name

0x04120050

dma_doneBit Field
Name
dma_done

Initial

Type

Bit

RW

[31:0]

Value
0x0

Description
DMA channel number of DMA transfer completion
Read as:0: DMA transfer not completed
1: DMA transfer completed
Write as:0: No effect
1: Set dma_done LOW

0x04120054

dma_err

dma_err

RW[31:0]0x0

DMA channel number of AHB error occurrence
Read as:0: AHB no error occurred
1: AHB error occurred
Write as:0: No effect
1: Set dma_err LOW

3.8.3.3 Clock and Reset
Figure DMAC-70 shows the clock and reset system diagram of the SDMAC.
Reset of the SDMAC is automatically released when the PWD_SYSIOP power domain is turned ON.
RCOSC
ck_rf_pll_1

RTC_CLK_IN(32.768kHz)SYSPLL

XOSC

ck_cpu_bus

1/M

1/M

ck_ahb_gear

CK
GATE

Auto(PWD_SYSIOP Power Domain ON)

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

0
1

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_CKEN.AHB_DMAC0

Figure DMAC-70 SDMAC Clock and Reset System－282/1293－

SDMAC
HCLK

HRESETnCXD5602 User Manual

3.8.3.4 Clock Supply Start and Stop
3.8.3.4.1

Clock Supply Start

Perform the following control to start supplying the HCLK clock of the SDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP power domain is turned ON.
2.

Clock supply start
SYSIOP_CKEN.AHB_DMAC0=1'b1

3.8.3.4.2

Clock Supply Stop

Perform the following control to stop supplying the HCLK clock of the SDMAC.
1. Clock supply stop
SYSIOP_CKEN.AHB_DMAC0=1'b0

3.8.4

HDMAC

Adds a feature to notify the CPU of independent interrupts of each DMA channel to the PrimeCell® Single Master
DMA Controller (PL081). Figure DMAC-71 shows an overview of the added functions.
HDMAC(PL081)
Conventional logic
INTERR

Not used

INTTC

INTR

Chennel0

Additional logic
DMACINTR0IntTCCh0

Chennel1

IntErrCh1

DMACINTR1

IntTCCh1

to CPU Interrupt

IntErrCh0

Figure DMAC-71 HDMAC Overview of Added Functions－283/1293－

CXD5602 User Manual

3.8.4.1 Register List
Table DMAC-122 shows the registers that control the HDMAC.
Table DMAC-122 HDMAC Control Register List
Address

Register NameType

Description

initialValue

0x04121000

PrimeCell® Single Master DMA Controller (PL081) register-|
0x04121FFC

3.8.4.2 Clock and Reset
Figure DMAC-72 shows the clock and reset system diagram of the HDMAC.
Reset of the HDMAC is automatically released when the PWD_SYSIOP power domain is turned ON.
RCOSC
ck_rf_pll_1

RTC_CLK_IN(32.768kHz)SYSPLL

XOSC

ck_cpu_bus

1/M

1/M

ck_ahb_gear

CK
GATE

Auto(PWD_SYSIOP Power Domain ON)

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

0
1

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_CKEN.AHB_DMAC1

Figure DMAC-72 HDMAC Clock and Reset System

3.8.4.3 Clock Supply Start and Stop
3.8.4.3.1

Clock Supply Start

Perform the following control to start supplying the HCLK clock of the HDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP power domain is turned ON.
2. Clock supply start
SYSIOP_CKEN.AHB_DMAC1=1'b1－284/1293－

HDMAC
HCLK

HRESETnCXD5602 User Manual

3.8.4.3.2

Clock Supply Stop

Perform the following control to stop supplying the HCLK clock of the HDMAC.
1. Clock supply stop
SYSIOP_CKEN.AHB_DMAC1=1'b0

3.8.5

SYDMAC

3.8.5.1 Register List
Table DMAC-123 shows the registers that control the SYDMAC.
Table DMAC-123 SYDMAC Control Register List
Address

Register NameType

Description

initialValue

0x04122000

PrimeCell® Single Master DMA Controller (PL081) register-|
0x04122FFC

3.8.5.2 Clock and Reset
Figure DMAC-73 shows the clock and reset system diagram of the SYDMAC.
Reset of the SYDMAC is automatically released when the PWD_SYSIOP power domain is turned ON.
RCOSC
ck_rf_pll_1

RTC_CLK_IN(32.768kHz)SYSPLL

XOSC

ck_cpu_bus

1/M

1/M

ck_ahb_gear

CK
GATE

Auto(PWD_SYSIOP Power Domain ON)

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

0
1

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_CKEN.AHB_DMAC2

Figure DMAC-73 SYDMAC Clock and Reset System－285/1293－

SYDMACHCLKHRESETnCXD5602 User Manual

3.8.5.3 Clock Supply Start and Stop
3.8.5.3.1

Clock Supply Start

Perform the following control to start supplying the HCLK clock of the SYDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP power domain is turned ON.
2. Clock supply start
SYSIOP_CKEN.AHB_DMAC2=1'b1

3.8.5.3.2

Clock Supply Stop

Perform the following control to stop supplying the HCLK clock of the SYDMAC.
1. Clock supply stop
SYSIOP_CKEN.AHB_DMAC2=1'b0

3.8.6

SYSUBDMAC

3.8.6.1 Register List
Table DMAC-124 shows the registers that control the SYSUBDMAC.
Table DMAC-124 SYSUBDMAC Control Register List
Address

Register NameType

Description

initialValue

0x04123000

PrimeCell® Single Master DMA Controller (PL081) register-|
0x04123FFC

3.8.6.2 Clock and Reset
Figure DMAC-74 shows the clock and reset system diagram of the SYSUBDMAC.
Reset of the SYSUBDMAC is automatically released when the PWD_SYSIOP_SUB power domain is turned ON.

－286/1293－

CXD5602 User Manual

RCOSC
ck_rf_pll_1

RTC_CLK_IN(32.768kHz)SYSPLL

XOSC

ck_cpu_bus

1/M

1/M

ck_ahb_gear

SYSUBDMAC

CK
GATE

HCLK

Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

HRESETn

0
1

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_DMAC3

Figure DMAC-74 SYSUBDMAC Clock and Reset System

3.8.6.3 Clock Supply Start and Stop
3.8.6.3.1

Clock Supply Start

Perform the following control to start supplying the HCLK clock of the SYSUBDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP_SUB power domain is turned ON.
2. Clock supply start
SYSIOP_SUB_CKEN.AHB_DMAC3=1'b1

3.8.6.3.2

Clock Supply Stop
1. Clock supply stop
SYSIOP_SUB_CKEN.AHB_DMAC3=1'b0

3.8.7

ADMAC

3.8.7.1 Register List
Table DMAC-125 shows the registers that control the ADMAC.
Table DMAC-125 ADMAC Control Register List
Address

Register NameType

Description

initialValue

0x0E020000

PrimeCell® Single Master DMA Controller (PL081) register|
0x0E020FFF－287/1293－-

CXD5602 User Manual

3.8.7.2 Clock and Reset
Figure DMAC-75 shows the clock and reset system diagram of the ADMAC.
RCOSC
XOSC

RTC_CLK_IN(32.768kHz)SYSPLL

CK
GATE

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

CK_APP

N/M
GEAR_AHB.gear_m_ahb
GEAR_AHB.gear_n_ahb
CK
GATE

CK_GATE_AHB.ck_gate_dmac
RESET.xrs_dsp_gen

01

APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP

HRESETnCKGATE

CK_GATE_AHB.ck_gate_img
RESET.xrs_img

PWD_RESET0.PWD_APP

RST_APP_X

3.8.7.3 Clock Supply Start and Stop
Clock Supply Start

Perform the following control to start supplying the HCLK clock of the ADMAC.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_dsp_gen=1'b1
2. Supply the CK_APP (Refer to APP (Chapter 3.13))
3. AHB bus clock supply and division ratio setting
GEAR_AHB.gear_m_ahb= (arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb= (arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_dmac=1'b1

3.8.7.3.2

Clock Supply Stop

Perform the following control to stop supplying the HCLK clock of the ADMAC.
1. AHB bus clock stop
CK_GATE_AHB.ck_gate_dmac=1'b0－288/1293－

IDMAC
HCLK
HRESETn

Figure DMAC-75 ADMAC Clock and Reset System

3.8.7.3.1

ADMAC
HCLK

CXD5602 User Manual

3.8.8

IDMAC

The functions of the IDMAC have been modified based on the PrimeCell® DMA Controller (PL080) from ARM
Limited.
Features of the IDMAC

There are five DMA channels, each of which supports unidirectional transfer.



Accepts transfer requests from IMG_SSP and IMG_UART

Enables single data transfer and burst data transfer. In the case of burst data transfer, the size can be set by
the program

Enables Scatter/Gather transfer by use of the linked list.

Each channel has an independent 16 byte FIFO built in.

Supports only little endianDMACSREQ[15:0]
DMACBREQ[15:0]
DMACLSREQ[15:0]
DMACLBREQ[15:0]
DMACCLR[15:0]
DMACTC[15:0]

DMACINTR
HADDR[11:2]
HWDATA[31:0]
HWRITEHSELHTRANS[1:0]
HSIZE[2:0]
HBURST[2:0]
HREADYIN
HRDATA[31:0]
HRESP[1:0]
HREADYOUT

Channel0
RequestAnd
Response

Channel1
Channel2

Interrupt
RequestInternal
Arbiter

Channel5
Channel6
Channel7

Bus
InterfaceBus
RequestChannel3
Channel4

AHB
Slave
InterfaceAHB Master 1

AHB Master 2

Internal
Arbiter

Bus
InterfaceBus
RequestUnimplemented

Figure DMAC-76 IDMAC Function Block Diagram－289/1293－

HADDRM1[31:0]
HWRITEM1
HSIZEM1[2:0]
HPROTM1[3:0]
HLOCKM1HTRANSM1[1:0]
HBURSTM1[2:0]
HWDATAM1[31:0]
HRDATAM1[31:0]
HRESPM1[1:0]
HREADYINM1
HBUSREQM1
HGRANTM1
HADDRM2[31:0]
HWRITEM2
HSIZEM2[2:0]
HPROTM2[3:0]
HLOCKM2HTRANSM2[1:0]
HBURSTM2[2:0]
HWDATAM2[31:0]
HRDATAM2[31:0]
HRESPM2[1:0]
HREADYINM2
HBUSREQM2
HGRANTM2

CXD5602 User Manual

3.8.8.1 Register List
Table DMAC-8 shows the registers that control the IDMAC.
Table DMAC-8 IDMAC Control Register List
Address

Register NameType

Description

initialValue

0x04123000

DMACIntStatus

RO

Interrupt Status Register

00x04123004

DMACIntTCStatus

RO

Interrupt Terminal Count Status Register

00x04123008

DMACIntTCClr

W

Interrupt Terminal Count Clear Register-

0x0412300C

DMACIntErrorStatus

RO

Interrupt Error Status Register

00x04123010

DMACIntErrClr

W

Interrupt Error Clear Register-

0x04123014

DMACRawIntTCStatusRO

Raw Interrupt Terminal Count Status Register

00x04123018

DMACRawIntErrorStat

RO

Raw Error Interrupt Status Register

0us0x0412301C

DMAEnbldChns

RO

Enabled channel register

00x04123020

DMACSoftBReq

RW

Software burst request register

00x04123024

DMACSoftSReq

RW

Software single request register

00x04123028

DMACSoftLBReq

RW

Software last burst request register

00x0412302C

DMACSoftLSReq

RW

Software last single request register

00x04123030

DMACConfiguration

RW

Configuration register

0x04000x04123034

DMACSync

RW

Synchronization register

0xFFFF0x04123038

DMACSReqMask

RW

Single Request Mask register

0xFFFF0x04123100

DMACSrcAddr_n

RW

Channel source address registers

0

RW

Channel destination address registers

0

RW

Channel linked list item register

0

RW

Extended Channel Control register

0

RW

Channel Configuration register

0

RW

Channel Default Link List Item registers

0

ReservedRO

Reserved

0

DMACITCR

RW

Test Control Register0(n=0-3,step=0x20)
0x04123104

DMACDestAddr_n(n=0-3,step=0x20)

0x04123108

DMACLLI_n(n=0-3,step=0x20)

0x0412310C

DMACExtControl_n(n=0-3,step=0x20)

0x04123110

DMACConfiguration_n(n=0-3,step=0x20)

0x04123114

DMACDefLLI_n(n=0-3,step=0x20)

0x04123180|
0x041234FC
0x04123500－290/1293－

CXD5602 User Manual

0x04123504

DMACITOP1

RW

Integration Test Output Register 1

00x04123508

DMACITOP2

RW

Integration Test Output Register 2

00x0412350C

DMACITOP3

RW

Integration Test Output Register 3

00x04123510

ReservedRO

Reserved

00x04123800

DMACAUX0RWDMAC Auxury Register 000x04123804

DMACAUX1RWDMAC Auxury Register 1

00x04123808

DMACAUX2RWDMAC Auxury Register 2

00x0412380C

DMACAUX3RW

DMAC Auxury Register 3

0|0x041237FC

3.8.8.2 Register Descriptions
Table DMAC-9 shows the descriptions of the registers of the IDMAC.
Table DMAC-9 IDMAC Control Register Descriptions
Address

Register Name

0x04123000

DMACIntStatus

0x04123004

Bit Field

Initial

Type

Bit

-

RO

[31:0]

0Same as PL080

DMACIntTCStatus-RO[31:0]

0Same as PL080

0x04123008

DMACIntTCClr-

W[31:0]-

Same as PL080

0x0412300C

DMACIntErrorStatus-RO[31:0]

0Same as PL080

0x04123010

DMACIntErrClr-

W[31:0]-

Same as PL080

0x04123014

DMACRawIntTCStatus-RO[31:0]

0Same as PL080

0x04123018

DMACRawIntErrorSta-

RO[31:0]

0Same as PL080

Name

Value

Descriptiontus
0x0412301C

DMAEnbldChns-

RO[31:0]

0Same as PL080

0x04123020

DMACSoftBReq-

RW[31:0]

0Same as PL080

0x04123024

DMACSoftSReq-

RW[31:0]

0Same as PL080

0x04123028

DMACSoftLBReq-

RW[31:0]

0Same as PL080

0x0412302C

DMACSoftLSReq-

RW[31:0]

0Same as PL080

0x04123030

DMACConfiguration

ReservedRO[31:16]

0Reserved

FSIZE

RO

[15:14]2'b00

Can read out the FIFO size of the DMAC.

Sets the operation mode

Takes the following values depending onof the DMA controller

the configuration of the DMAC.
0: 16 byte
1: 32 byte
2: 64 byte
3: 128 byte

－291/1293－

CXD5602 User Manual

ARB

RO

[13]

1'b0

When the arbiter within the DMAC
schedules the transfers (for multiple
transferrequests),theschemethat

determines the priority can be read out.
Takes the following values depending on
the configuration of the DMAC.
0: Fixed-priority
1: Round-robin
TR

RO

[12]

1'b0

Can read out whether or not there is a
DMA external trigger function. Takes thefollowingvaluesdependingontheconfiguration of the DMAC.
0: Operates without external trigger
1: Waits for external trigger
DLLI

RO

[11]

1'b1

Can read out whether or not there is a
DefLLI function of the DMAC. Takes thefollowingvaluesdependingontheconfiguration of the DMAC.
0: Disables the DefLLI function
1: Enables the DefLLI function
TS

RO

[10]

1'b1

Can read out whether the Channel Control
register mapping of the DMAC isTransferSize

expandedmappingorDefault mapping. Takes the following
values depending on the configuration of
the DMAC.
0: The Channel Control register mappingis Default mapping
1: The Channel Control register mappingis TransferSize expanded mapping
Reserved

RO

[9:3]

0

Reserved

M2

RW

[2]

1'b0

Same as PL080

M1

RW

[1]

1'b0

E

RW

[0]

1'b0

Same as PL080

0x04123034

DMACSync-

RW[31:0]

0Same as PL080

0x04123038

DMACSReqMask

ReservedRO[31:16]

0Reserved－292/1293－

CXD5602 User Manual

DMACSR

RW[15:0]

0

EQMASK

Masks the input of the DMA data transfer
request input terminal DMASREQ[15:0].
When masked, only DMABREQ[15:0]
becomes valid.

0: DMASREQ input is masked
1: DMASREQ input is valid
Note that the setting of this registerchanges the handshake method between
the DMAC and Peripherals and should be
used with care. When single data transfer
requests are disabled, only burst requests
can be accepted.
0x04123100

0x04123104

0x04123108

DMACSrcAddr_n

SRCADD(n=0-3,step=0x20)

R

DMACDestAddr_n

DESTADD(n=0-3,step=0x20)

R

DMACLLI_n

RW[31:0]

0Same as PL080

RW[31:0]

0Same as PL080-

RW[31:0]

0Same as PL080

I

RW

[31]

1'b0

When

(n=0-3,step=0x20)
0x0412310C

DMACExtControl_n(n=0-3,step=0x20)(TransferSize expanded mapping)
The

Indicates

theinformation

DMACConfiguration.TS=1

enablebitforterminal

countcontrolinterrupt, which controls whether theeachcurrent LLI is expected to trigger theofchannel’s transfer size,

terminal count interrupt.

burst size, transfer datawidth, etc. during the

DI

RW

[30]

1'b0

When

DMACConfiguration.TS=1

DMA data transfer. This

(TransferSize expanded mapping)register

Controls whether or not to increment the

must

be

set

before the corresponding

destination address.

DMA channel is enabled.

0: No increment
1: Increments each time a transfer occurs

When

Scatter/Gathertransferisperformed,

it

SI

RW

[29]

being
will

1'b0

When

DMACConfiguration.TS=1(TransferSize expanded mapping)beControls whether or not to increment the

automatically updated tosource address.

the0: No increment

value

of

the

corresponding linked list.

1: Increments each time a transfer occurs－293/1293－

CXD5602 User Manual

The

ChannelControl

D

RW

[28]

1'b0

DMACConfiguration.TS=1

Whenregister mapping changes(TransferSize expanded mapping)according to the TS value

Indicates the AHB master channel usedoffor the destination data transfer.

the

DMACConfiguration

0: Selects AHB master 1 for theregister.

destination data transfer.
1: Selects AHB master 2 for thedestination data transfer.
S

RW

[27]

1'b0

DMACConfiguration.TS=1

When(TransferSize expanded mapping)
Indicates the AHB master channel used
for the source data transfer.
0: Selects AHB master 1 for the source
data transfer.
1: Selects AHB master 2 for the source
data transfer.
DWIDTH

RW[26:25]0

DMACConfiguration.TS=1

When(TransferSize expanded mapping)
Indicates the transfer data size of thedestination bus.
0: byte transfer
1: halfword transfer
2: word transfer
3: Reserved
SWIDTH

RW[24:23]0

DMACConfiguration.TS=1

When(TransferSize expanded mapping)
Indicates the transfer data size of thesource bus.
0: byte transfer
1: halfword transfer
2: word transfer
3: Reserved
The data sizes of the source side and thedestination side do not have to be the
same.

The

hardwareautomatically

performs the packing and unpacking of
the data when required.

－294/1293－

CXD5602 User Manual

DSIZE

RW

[22:21]0

When

DMACConfiguration.TS=1(TransferSize expanded mapping)
Indicates the burst size of the destination
data transfer. Make sure to set this value
to the burst size of the destination
peripheral or to the memory boundary size
if the memory is the destination.
The burst size sets the amount of data to
be transferred when the DMACxBREQ
signal becomes active at the destination
peripheral. The amount of data actuallytransferred

can

be

calculatedbymultiplying this burst size by the DWidth.
0: 1 Burst
1: 4 Burst
2: 8 Burst
3: 16 Burst
SSIZE

RW

[20:19]0

When

DMACConfiguration.TS=1(TransferSize expanded mapping)
Indicates the burst size of the source datatransfer. Make sure to set this value to theburst size of the source peripheral or tothe memory boundary size if the memoryis the source.
The burst size sets the amount of data to
be transferred when the DMACxBREQ
signal becomes active at the source
peripheral. The amount of data actuallytransferred

can

be

calculatedbymultiplying this burst size and the
SWidth.
0:1 Burst
1:4 Burst
2:8 Burst
3:16 Burst－295/1293－

CXD5602 User Manual

TRANSFE

RW[18:0]

0

RSIZE

When

DMACConfiguration.TS=1(TransferSize expanded mapping)
When the DMA controller is the flow
controller, the amount of data transfer tobe performed is written to this register.
Values can be written from 0 to 524287.
The actual number of bytes of transferreddata is equal to the product of multiplying
this by the data width set in the
aforementioned SWidth bit.
When read out, the completed amount oftransfer is indicated.
When the DMA controller is not the flow
controller, this value becomes invalid.

0x04123110

DMACConfiguration_n

TRIGGER(n=0-3,step=0x20)

PERPHER(when waiting for external trigger)

AL

This is the selection bit for external

RW[31:28]0

When

DMACConfiguration.TR=1

For various settings of thetrigger Peripheral. When the external

DMA

trigger function is disabled, this bit ischannels.

Thisregister does not change

invalid.

by update of the LLIWhen DMACConfiguration.TR=0 (whenitem.

operating without external trigger)
Becomes Reserved. When writing, set to“0”, when reading, mask it.
TEN

RW

[27]

0

When

DMACConfiguration.TR=1(when waiting for external trigger)
This is the external trigger function enable
bit.
0: External trigger function is disabled
1: External trigger function is enabled
When

DMACConfiguration.TR=0(when operating without external trigger
function)
Becomes Reserved. When writing, set to“0”, when reading, mask it.
Reserved

RO[26]－296/1293－

0ReservedCXD5602 User Manual

DESTME

RW

[25]

0

MBURST

Sets access of the AHB port, which is set
as the memory access of the Destinationside, so that it always conforms to theburst length set by DBSize. This is used toraise the efficiency of memory access.
However, since the FIFO size is 16/32/64
byte, 4/8/16 burst is the largest number ofbursts in word size.
Be cautious with the DBSize setting of the
Channel Control register.

SRCMEM

RW

[24]

0

BURST

Sets access of the AHB port, which is set
as the memory access of the Source side,
so that it always conforms to the burst
length set by SBSize. This is used to raise
the efficiency of memory access.
However, since the FIFO size is 16/32/64
bytes, 4/8/16 burst is the largest numberof bursts in word size.
Be cautious with the SBSize setting of the
Channel Control register.

ReservedRO[23:19]0Reserved

HALT

RW

[18]

0

Same as PL080

ACTIVE

RW

[17]

0

Same as PL080

LOCK

RW

[16]

0

When this bit is set, locked transfer(HLOCK=H) is performed.

ITC

RW

[15]

0

Same as PL080

IE

RW

[14]

0

Same as PL080

FLOWCNRW[13:11]0Same as PL080

Reserved

RO

[10]

0

Reserved

DESTPERI

RW

[9:6]

0

Same as PL080

Reserved

RO

[5]

0

Reserved

SRCPERIP

RW

[4:1]

0

Same as PL080

RW

[0]

0

Same as PL080

TRL

PHERAL

HERAL
E－297/1293－

CXD5602 User Manual

0x04123114

DMACDefLLI_n

DEFLLI

RW[31:2]

0(n=0-3,step=0x20)

The address that points to the Default
Linked List Item. When transfer starts
with the DefLLI function enabled, the LLI

The register for settingof the address that DefLLI points to is

the DefLLI. Does notread before starting data transfer, andperform

following

automatic

the

updateof

SrcAddr,update.

DestAddr, LLI, and Control, the transfer

Whenstarts.

DMACConfiguration.D

DEFLE

RW

[1]

0

Selects enable/disable of the DefLLI

LLI=1 (DefLLI function

function.

exists),0: Disabled

thisregisterexists.
When

1: Enabled
DEFLM

RW

[0]

0

Sets the AHB bus master channel thatDMACConfiguration.D

becomes active when the DefLLI is

LLI=0 (DefLLI function

loaded.

does not exist), all bits

0: Selects AHB master 1

become Reserved.

1: Selects AHB master 2

When writing, set to “0”,when reading, mask it.
0x04123500

DMACITCR-

RW[31:0]

0Same as PL080

0x04123504

DMACITOP1-

RW[31:0]

0Same as PL080

0x04123508

DMACITOP2-

RW[31:0]

0Same as PL080

0x0412350C

DMACITOP3-

RW[31:0]

0Same as PL080

0x04123800

DMACAUX0

AUX_0

RW

[31:0]

0

Any data can be set

0x04123804

DMACAUX1

AUX_1

RW

[31:0]

0

Any data can be set

0x04123808

DMACAUX2

AUX_2

RW

[31:0]

0

Any data can be set

0x0412380C

DMACAUX3

AUX_3

RW

[31:0]

0

Any data can be set－298/1293－

CXD5602 User Manual

Important Points to Note

About locked transfer
Locked transfer is not supported. Do not set the corresponding function registers.



DMACConfiguration
Make sure to set the M1, M2 bits to little endian. Setting them to big endian is prohibited.

DMACSync
Use it with the synchronization logic enabled.

DMACSreqMask
Use it with Input enable (Default).

Transfer using DefLLI function
In the case of writing to the DMACConfiguration_n while the DMAC channel is transferring data, set the
DMACDefLLI_n.DefLE to “0” beforehand regardless of the bit to be set. Violation of this restriction can
result in unexpected operation of the DMAC.



About the Src/Dest address
For 32bit (Word), 16bit (HalfWord) access, the addresses must be aligned. Make sure to follow the
restrictions of each channel’s SrcAddr, DstAddr, and Swidth, Dwidt.

1.

If Swidth=Word, SrcAddr[1:0]=2'b00

2.

If Swidth=HalfWord, SrcAddr[0]=1'b0

3.

If Dwidth=Word, DstAddr[1:0]=2'b00

4.

If Dwidth=HalfWord, DstAddr[0]=1'b0

About Transfersize
When the Dwidth is larger than the Swidth in each DMAC channel, depending on the TransferSize, broken
numbers may occur against the data width, and the transfer cannot be completed and the data will be lost.
Transfer completion interrupts will not be issued either. Make sure to follow the below restrictions regardlessof the flow control of the DMAC.

1.

If Swidth=Byte, Dwidth=HalfWord, the TransferSize must be a multiple of two.

2.

If Swidth=Byte, Dwidth=Word, the TransferSize must be a multiple of four.

3.

If Swidth=HalfWord, Dwidth=Word, the TransferSize must be a multiple of two.

About the master port setting
When accessing an address area outside the IMG block, use the AHB1 port. When accessing the internal
peripheral area, use the AHB2 port. Be cautious with the settings of related function registers.

－299/1293－

CXD5602 User Manual

3.8.8.3 Clock and Reset
Figure DMAC-77 shows the clock and reset system diagram of the IDMAC.
RCOSC
XOSC

RTC_CLK_IN(32.768kHz)SYSPLL

CK
GATE

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

CK_APP

N/M
GEAR_AHB.gear_m_ahb
GEAR_AHB.gear_n_ahb
CK
GATE

CK_GATE_AHB.ck_gate_dmac
RESET.xrs_dsp_gen

01

APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP

HRESETnCKGATE

CK_GATE_AHB.ck_gate_img
RESET.xrs_img

PWD_RESET0.PWD_APP

RST_APP_X

3.8.8.4 Clock Supply Start and Stop
Clock Supply Start

Perform the following control to start supplying the HCLK clock of the IDMAC.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_img=1'b1
2. Supply the CK_APP (Refer to APP (Chapter 3.13))
3. AHB bus clock supply and division ratio setting
GEAR_AHB.gear_m_ahb= (arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb= (arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_dmac=1'b1

3.8.8.4.2

Clock Supply Stop

Perform the following control to stop supplying the HCLK clock of the IDMAC.
1. AHB bus clock stop
CK_GATE_AHB.ck_gate_img=1'b0－300/1293－

IDMAC
HCLK
HRESETn

Figure DMAC-77 IDMAC Clock and Reset System

3.8.8.4.1

ADMAC
HCLK

CXD5602 User Manual

3.9

SCU (Sensor Control Unit)

3.9.1

SCU Overview and Features

The Sensor Control Unit (referred to as “SCU” hereinafter) is the block that provides control of capturing output
data from the external sensor information.
It offers the following features.
(1) Sensor Interface Function
Analog Input (High Performance ADC) x 2 channels
Successive approximation ADC, 10 bit resolution, 32 kS/s maximum sampling rate
Analog Input (Low Power ADC) x 4 channels
Successive approximation ADC, 10 bit resolution, 32 kS/s maximum sampling rate (when operating one
channel)SPI (master) x 1 channel
Uses the PrimeCell Synchronous Serial Port (PL022) from ARM Limited; supports a maximum transfer
frequency of 6.5 MHz
Allows the use of three Slave Selection signals (CS)I2C (master) x 2 channels
Fast Mode support (Maximum 393.9 kbps)
For details on each sensor interface, refer to the Chapters of each function.
(2) Sequencer Functions for capturing sensor data
The Sequencer performs the following sequence of processes.
Using the designated time intervals as a trigger, it intermittently captures the sensor data from the sensor I/F.
Performs arithmetic processing (MATH_PROC) to the sensor data and stores the results in the FIFO within the
SCU.
When storing the calculation results in the FIFO, it adds time stamp information of the time the data was captured.
When the sequencer within the SCU is not used, the CPU can directly control the SPI, I2C, and ADC.
The CPU Block (Ultra Small & Ultra Low Power CPU) is customized as a System for APB Peripheral control
Contains 8 KByte (32bit x 2048words) of SRAM for commands of the internal sequencer and 2 KByte (32bit x
512words) of SRAM for data.
(3) FIFO Functions for Storing Sensor Data
The FIFO has 27 partitions, which are classified into four types.


Decimation Partitions(4 per each set) x 2 sets

Normal Sensor Partitions

x8



Virtual Sensor Partitions

x 10－301/1293－

CXD5602 User Manual

Random Access Partitions x 1
Each partition is assigned to regions divided within an SRAM having 40 KByte (32bit x 2048words + 32bit x

8192 words) space.
Power supply control of the FIFO SRAM can be performed from the PMU (Power Supply Control Unit) outside
the SCU.
A time stamp is attached to each data of the FIFO.
The FIFO data can be read out from the CPU, or from an external host via the HOSTIFC.
In accordance with the data size of the FIFO, handshake is performed with the DMAC outside the SCU, allowing
DMA transfer to be performed.
In accordance with the data size of the FIFO, an interrupt signal can be output.
(4) MATH_PROC functions for arithmetic processing of the sensor data
The following arithmetic processing can be executed in a programmable fashion.
Unsigned data/signed data conversion

Gain multiplication by each vector element

Offset addition by each vector element



Decimation

Multiplication processing with clipping

2nd order IIR filterNormalization Processing

Excess Detection (Event)(5) PWM function that is capable of external output

The SCU has eight channels of timers for the Pulse Width Modulation (PWM). Up to four of these channels canbe output to the external terminals for LED brightness adjustment as the PWM. Timers that are not used as PWMs
can be used as timers for the SCU clock reference.
The start timing can be synchronized between each channel of the timers.
The LPADC/HPADC can receive the conversion timing from the timers.
The signal output from the external terminal can be combined by AND or OR logic of the eight channels of output
signals.

－302/1293－

CXD5602 User Manual

3.9.2

SCU Block DiagramCXD5602

ASYNC

ASYNC
PWD_SCUSCU_LOGICMUX

SCU_REGHOSTIFCSEQUENCER
MATH_PROC

MUX

Arbiter

Arbiter

MUX

SPI

I2C0

I2C1

ADCIF
SCU_FIFO

PWM

SEL
LPADC

HPADC
SCU_ANALOG

Figure SCU (Sensor Control Unit)-78 Block Function Overview－303/1293－

CXD5602 User Manual

3.9.3

Memory Map

Figure SCU (Sensor Control Unit)-79 shows the MemoryMap as seen from the SYSCPU.
0x003F_FFFF
0x001D_3000
0x001D_2FFF
0x001D_1000
0x001D_0FFF
0x001D_0000
0x001C_FFFF
0x001A_D000
0x001A_CFFF
0x001A_C000
0x001A_BFFF
0x001A_B000
0x001A_AFFF
0x001A_A000
0x001A_9FFF
0x001A_9000
0x001A_8FFF
0x001A_4000
0x001A_3FFF
0x001A_0000
0x0019_FFFF
0x0018_0000
0x0017_FFFF
0x0012_4000
0x0012_3FFF
0x0012_0000
0x0011_FFFF
0x0011_1000
0x0011_0FFF
0x0011_0000
0x0010_FFFF
0x0010_C000
0x0010_BFFF

Reserved(2.1M)
SAKE(8K)
KAKI(4K)

UART(4K)
0x9000_0000
0x8FFF_FFFF

SPIM(4K)
I2CM(4K)
HostUART(4K)
Reserved(20K)
HOSTIFC(16K)
SCU(128K)

0x0012_3FFF
0x0012_3000
0x0012_2FFF
0x0012_2000
0x0012_1FFF
0x0012_1000
0x0012_0FFF
0x0012_0000

SYSUBDMAC(4K)

DMAC(16K)
Reserved(60K)
SPIFLASHIF(4K)
Reserved(16K)
TOP_Peri(48K)

0x0002_0000
0x0001_FFFF

Reserved(896K)
ROM(128K)

0x8000_0000
0x7FFF_FFFF

SYDMAC(4K)
HDMAC(4K)
SDMAC(4K)

0x1000_0000
0x0FFF_FFFF

0x0C00_0000
0x0BFF_FFFF

Reserved(368K)

0x0010_0000
0x000F_FFFF

0x0000_0000

0xFFFF_FFFF

Reserved(140K)

0x0010_BFFF
0x0010_B000
0x0010_AFFF
0x0010_A000
0x0010_9FFF
0x0010_9000
0x0010_8FFF
0x0010_8000
0x0010_7FFF
0x0010_7000
0x0010_6FFF
0x0010_6000
0x0010_5FFF
0x0010_3000
0x0010_2FFF
0x0010_0000

TDC(4K)
Reserved(4K)
RTCREG#1(4K)
RTCREG#0(4K)
FREQDISC(4K)
PMU_SUB(4K)
TOPREG_SUB(12K)
TOPREG(12K)

0x0800_0000
0x07FF_FFFF

0x0400_0000
0x03FF_FFFF

0x0100_0000
0x00FF_FFFF

0x0041_0000
0x0040_FFFF
0x0040_0000

Reserved(1792M)SPIFLASHIF(256M)

Reserved(1792M)

APP
(64M)
GNSS
(64M)
Mirror(64M)
SYS_CPU_Local(48M)

Reserved(11.9M)
BKUPSRAM(64K)

Figure SCU (Sensor Control Unit)-79 Memory Mapping from the Upper CPUs; the CPU in the SYSIOP and the
CPU in the GNSS; (hereinafter in the Chapter on SCU, referred as “upper CPUs”)
Figure SCU (Sensor Control Unit)-80 shows the Memory Map within the SCU as seen by the upper CPUs.

－304/1293－

CXD5602 User Manual

Figure SCU (Sensor Control Unit)-80 Memory Mapping within the SCU as seen from the Upper CPUs
The Reserved area within this Figure is writing-invalid (no error response) and “0” read during readout (noerror response).
The data storage region including the FIFO RAM (32 KByte) and FIFO RAM (8 KByte) is 40 KByte. Refer to
Section 3.9.8 for details.
The FIFO (4 KByte) is the port for data writing and readout. Refer to Table SCU (Sensor Control Unit)-139 fordetails.
The FIFO REG (8 KByte) handles controls around the FIFO. Refer to Section 3.9.12.10 for details.
The SCU_REG (4 KByte) is the control register. Refer to Section 3.9.12.3 for details.
The DRAM (2 KByte) is used as the SCU_RAM. Refer to Section 3.9.12.11 for details.
The IRAM (8 KByte) is used as the SEQ_IRAM. This stores the control firmware of the internal sequencer.
Figure SCU (Sensor Control Unit)-81 shows the Memory Map as seen from the internal sequencer of the SCU.

－305/1293－

CXD5602 User Manual

The Reserved area within this Figure is
writing-invalid (no error response) and “0”read during readout (no error response).

Figure SCU (Sensor Control Unit)-81 Memory Mapping as seen from the Internal Sequencer
Figure SCU (Sensor Control Unit)-82 shows the Memory Mapping as seen from the SCU window of the
HOSTIFC.

The Reserved area within this Figure is
writing-invalid (no error response) and “0”read during readout (no error response).

Figure SCU (Sensor Control Unit)-82 Memory Mapping as seen from the HOSTIFC－306/1293－

CXD5602 User Manual

3.9.4

Clock Control

3.9.4.1 Clock Summary
Table SCU (Sensor Control Unit)-126 Clock Summary
Clock Name

Maximum Frequency

Maximum Frequency

Usage(High Performance mode)(Low Power mode)

CK_SCU_SCU

13MHz

13MHz

SCU Main

CK_SCU_SCU_SC

13MHz

13MHz

SCU Main CPU control only

CK_SCU_SCU_SPI

13MHz

13MHz

For SPICK_SCU_SCU_I2C0

13MHz

13MHz

For I2C0

CK_SCU_SCU_I2C1

13MHz

13MHz

For I2C1

CK_SCU_SCU_SEQ

13MHz

13MHz

For SCU internal sequencer

CK_SCU_XOSC

13MHz

13MHz

For HPADC(1*)

CK_SCU_RC8M

8MHz

8MHz

For HPADC(1*)

CK_SCU_U32KL

32kHz

32kHz

For LPADC(1*)

CK_SCU_U32KH

32kHz

32kHz

For HPADC(1*)

CK_SCU_32K

32kHz

32kHz

For PWM

CK_SCU_BRG_HCLK

13MHz

13MHz

For AHB BUS

1* For details on the clocks for the HPADC and LPADC, refer to the Chapter on ADC (3.21).

3.9.4.2 Logic System (High Speed) Clocks


CK_SCU_SCU

CK_SCU_SCU_SC

CK_SCU_SPI (for SPI)CK_SCU_I2C0 (for I2C0)

CK_SCU_I2C1 (for I2C1)

CK_SCU_SEQ (for SEQ)

CK_SCU_BRG_HCLKThe above Logic System (High Speed) Clocks all have the same operating frequency (they are synchronized)

but their control conditions for clock enabler are different.
The Logic System (High Speed) Clocks are generated from one of the below clock sources at CRG (Clock andReset Generator) outside the SCU.

－307/1293－

CXD5602 User Manual

RCOSC (standard operating frequency of 8.13 MHz)



XOSC



CK_SCU_32K (RTC clock or RCOSC divided by 250)
For the XOSC, frequency divisions of 1, 2, 3, or 4 can be selected by the CRG. However, since the maximum

operating frequency of the SCU is 13 MHz, you will need to select the appropriate frequency division inaccordance with the crystal oscillator that is connected from outside. Use the API to select these clock sources, the
XOSC frequency division, and the source for the CK_SCU_32K.

3.9.4.3 Logic System (Low Speed) Clock
CK_SCU_32K
The Logic System (Low Speed) Clocks operate at around 32.768 kHz and are generated from one of the below
clock sources.


RTC (32.768 kHz)RCOSC divided by 250
Use the API to select these clock sources.

3.9.4.4 HPADC Clock and LPADC ClockFor details on the HPADC clock and LPADC clock, refer to the Chapter on ADC (3.21) clock control.

3.9.4.5 Clock Control Summary
The following table summarizes the selection of input clocks. For details on the LPADC and HPADC clocks,
refer to the Chapter on ADC (3.21).
Table SCU (Sensor Control Unit)-127 Input Clock Source Selection
Clock Source Selector (*)

Frequency

Clock Source Selector (*)

Clock Port Name

Description

CK_SCU_SCU

Main clock

Division
Circuit (*)
・RTC

None

・

・RCRTC (RCOSC divided(directly

operatingby 250)connected)

8.192 MHz)

RCOSC

(standardfrequency

of・XOSC (after selecting toCan be controlled from the
SCU and HOSTIFCCK_SCU_SCU_SC

Main clock

divide by 1, 2, 3, or 4)

Cannot be controlled from・ The clock selected bythe

Selector 1(supplied to the ADCIF and

SCU

INTC)

－308/1293－

or

HOSTIFCCXD5602 User Manual

CK_SCU_SPIFor SPICK_SCU_I2C0

For I2C0

CK_SCU_I2C1

For I2C1

CK_SCU_SEQ

For sequencer

CK_SCU_BRG_H

For AHB bridge

CLK
Directly connected from

CK_SCU_32K

For PWM timer

Selector 1* The Clock Source Selector and frequency division circuit can be controlled from the TOPREG.

Figure SCU (Sensor Control Unit)-83 shows the clock system. The CK_SCU_32K shown in the Figure is used
for the LPADC and HPADC within the SCU.
RCRTC
RCOSC
8.192MHzSCU_CKEN[5]

0

1/250

1

RTC

CKSEL_SCU.SEL_SCU_32K
XOSC"configure unavailable"

CK_SCU_32K

CG

CK_SCU_SCU

(1)
(2)

2

CKSEL_SCU.SCU_XTALCG

SCU_CKEN[0]
0
1

DIV

SCU

SCU_CKEN[8]3CKSEL_SCU.SEL_SCU

SCU_CKEN[3]CK_SCU_BRG_HCLKCG

CK_SCU_SCU_SC

CG

CK_SCU_SCU_SPICG

CK_SCU_SCU_SEQCG

CK_SCU_SCU_I2C1

CG

CK_SCU_SCU_I2C0(2)
SCU_CKEN[4](2)
SCU_CKEN[2](2)SCU_CKEN[1](1) control signal from the HOSTIFC sequencer(2) control signal from the SCU sequencer(2)

Figure SCU (Sensor Control Unit)-83 Clock System
As shown in Figure SCU (Sensor Control Unit)-83, the clock signal provided to CK_SCU_SCU is controlled
by the signal that is made by ORing SCU_CKEN[0]: the signal from the upper layer, the signal (1) from theinternal sequencer of the HOSTIFC, and the signal (2) from the internal sequencer of the SCU. The clock signal－309/1293－

CXD5602 User Manual

provided to CK_SCU_SCU_SPI, CK_SCU_SCU_I2C1, and CK_SCU_SCU_I2C0 are controlled by the signalthat is made by ORing dedicated bit in the SCU_CKEN: the signal from the upper layer, and the signal (2) fromthe internal sequencer of the SCU. Note that each control signal from the internal sequencer that is input to eachclock’s control is independent.
The clock signal provided to CK_SCU_SCU_SEQ is controlled by the signal that is made by ANDing
SCU_CKEN[4]: the signal from the upper layer, and the signal (2) from the internal sequencer of the SCU.
As this described, the clocks within the SCU are divided into several domains, and clock control is possible fromthe SYSCPU, DSP, internal sequencer of the HOSTIFC, or the internal sequencer of the SCU. In the case ofcontrolling from multiple CPUs/internal sequencers, OR control is used.
Table SCU (Sensor Control Unit)-128 Control of each ClockSCU Clock NameControl

fromtheControl

fromInternal

Control from Internal Sequencer ofUpper CPU

Sequencer of SCU

HOSTIFC

CK_SCU_SCU

possiblepossiblepossible

CK_SCU_SCU_SC

possible－－

CK_SCU_SCU_SPI

possiblepossible－

CK_SCU_SCU_I2C0

possiblepossible－

CK_SCU_SCU_I2C1

possiblepossible－

CK_SCU_SCU_SEQ

possiblepossible－

The clocks are controlled using the following registers.
Table SCU (Sensor Control Unit)-129 Clock Control Registers
Controlled

Block Name

Register Name

offsetRemarksCPU

TOPREGSCU_CKEN

0x071cTOPREG Control Region

HOSTIFC

HOS_SEQ_REG

HOS_SCU_POWER

0x0010HOSTIFC Register Internal Sequencer Control

from:RegionSCU

SCU_SEQ_REG

SCU_ISOP_POWER

0x0044－310/1293－

SCU Register Internal Sequencer Control Region

CXD5602 User Manual

3.9.4.6 Clock Control from Internal Sequencers
To reduce power consumption, the firmware of the internal sequencers attempts to stop as many as clocks as
possible during Sleep. Also, since SPI, I2C0, and I2C1 are master devices, each of their clocks are controlled by
the internal sequencers so they operate only during data transfer (Table SCU (Sensor Control Unit)-130). The
CK_SCU_32K and CK_SCU_SCU_SC clocks are required for operation of the internal sequencers but since they
are not controlled by the internal sequencers, they must be turned ON from the CPU for operation of the SCU.
Table SCU (Sensor Control Unit)-130SCU Clock Name

During Internal Sequencer

Clock Control from the Internal Sequencers
During Internal Sequencer Active

Sleep
CK_SCU_SCU

OFF

ON

CK_SCU_SCU_SC

Not controlled

CK_SCU_SCU_SPI

OFF

ON only during SPI transfer, OFF all other times

CK_SCU_SCU_I2C0

OFFON only during I2C0 transfer, OFF all other times

CK_SCU_SCU_I2C1

OFF

ON only during I2C1 transfer, OFF all other times

CK_SCU_SCU_SEQ

OFF

ON

CK_SCU_32K

Not controlled

3.9.4.7 Clock Control from CPU
When viewed from the SYSCPU, the ON/OFF control of the internal sequencer clocks change automaticallyduring the operation of the internal sequencers. During the operation of the internal sequencers, ON/OFF
switching of the internal sequencer clocks cannot be controlled by the SYSCPU, and is automatically performed.
The CPU must supply the clocks so that the ON/OFF control of internal sequencer clocks can be properly
performed (Table SCU (Sensor Control Unit)-131).

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CK_SCU_SCU_SEQ (Internal Sequencer itself and Resource)

CK_SCU_XOSC (SYSCPU Resource)

CK_SCU_RC8M (SYSCPU Resource)

CK_SCU_U32KL (SYSCPU Resource)

CK_SCU_U32KH (SYSCPU Resource)

CK_SCU_32K (SYSCPU Resource)

clock

clock

clock

clock

OFF

OFF

OFF

OFF

OFF

OFF

W

clock

clock

clock

clock

clock

OFF

OFF

OFF

OFF

OFF

C

C

C

C

clock

CK_SCU_SCU_I2C0 (SYSCPU/Internal Sequencer Resource

clock

CK_SCU_SCU_SPI (SYSCPU/Internal Sequencer Resource

clock

CK_SCU_SCU_SC (SYSCPU Resource)C

CK_SCU_SCU (SYSCPU/Internal Sequencer Resource

Operation requested from

CK_SCU_SCU_I2C1 (SYSCPU/Internal Sequencer Resource

Table SCU (Sensor Control Unit)-131 Clock Control from CPU

clock

clock

C

C

ON

OFF

clock

clock

clock

clock

clock

ON

OFF

OFF

OFF

OFF

ADC is used (Internal

clock

clock

clock

clock

clock

clock

Sequencer is not used)

ON

ON

OFF

OFF

OFF

OFF

PWM is used (Internal

clock

clock

clock

clock

clock

clock

Sequencer is not used)

ON

OFF

OFF

OFF

OFF

OFF

When Internal Sequencer

clock

clock

clock

clock

clock

clock

is used

OFF

ON

OFF

OFF

OFF

ON

CPU

SCU

Internal

RegisterAccess(incl. FIFO)
RAM Access (1*)

OFF
C

C

C

C

clock
ON

C

C

C

C

clock
ON

C: When using the corresponding resource, the clock must be turned ON.
W: Inhibition of automatic ON/OFF of clock (SCU_REG register: by HPADC0_ACCESS_INHIBIT_REQ)
1* In addition to this method, access to the SCU_RAM is possible by turning ON the CK_SCU_SCU_SEQ clock

during the assertion of an internal sequencer reset because the clock is supplied.
For information on CK_SCU_XOSC, CK_SCU_RC8M, CK_SCU_U32KL, and CK_SCU_U32KH, also referto the ADC (3.21) Chapter.
When multiple operations coincide, the corresponding clock must be turned ON from the CPU even when one
clock is “clock ON”.

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3.9.5

Power Supply Control

The SCU module belongs to a power domain called PWD_SCU.
Within the PWD_SCU, there are power supply control module regions (listed below) as separate power domains.
Refer to the PMU Chapter (3.4) for details on the ON/OFF control registers of these power domains.
Table SCU (Sensor Control Unit)-132 Power Supply Control Registers
Power Supply Control Target

Control Register Name

LPADC

ANA_PW_CTL

HPADC

ANA_PW_CTL

FIFO SRAM (8KByte)

SCU_RAMMODE_SEL

FIFO SRAM (32KByte)

SCU_RAMMODE_SEL

Internal Sequencer SRAM (Instruction, Data)

SCU_RAMMODE_SEL

3.9.6

Interrupt

3.9.6.1 Overview
The SCU has four lines of interrupts, which connect to the SYSCPU and DSP.
For details, refer to the Chapter on Interrupt (3.3).
The following shows the relation with the interrupt number.
Table SCU (Sensor Control Unit)-133 Interrupt Number
SCU Interrupt Name

Description

INT0

SPI interrupt

INT1

I2C0 interrupt

INT2

I2C1 interrupt

INT3

Event Interrupt

3.9.6.2 Interrupt Details
The interrupts that occur within the SCU are connected to the CPU in the SYSIOP and the CPU in the GNSS;(hereinafter referred as “upper CPUs” in the Chapter on SCU), and also notified to the internal sequencer of the
SCU.
The interrupts to the upper CPUs are integrated into four interrupts at the INT_SEL module, and then output.
The interrupts from the SPI, I2C0, and I2C1 are output separately from the other interrupts.
Other interrupts such as LPADC, HPADC, PWM, and FIFO are ORed within the INT_SEL and combined into

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one signal that is output as INT3.
An interrupt mask can be separately set for each of the interrupt factors, and the statuses before and after themasks are applied can be read out.
The Edge interrupt factor can be cleared. In addition, depending on the interrupt factor, Level/Edge selection ispossible.
Figure SCU (Sensor Control Unit)-84 shows the connections of the INT_SEL.

PWD_SCUSCU_REG

Configuration
Data(ex. EN,CLR,etc.)
SCU_INT_SEL

SPI
I2C0
I2C1
SCU_ADCIF4

SCU_FIFOSCU_SEQ_CTRL
SCU_PWM 0～7

Figure SCU (Sensor Control Unit)-84 Interrupt Connections－314/1293－

M0/M4 CPUCXD5602 User Manual

Table SCU (Sensor Control Unit)-134 and Table SCU (Sensor Control Unit)-135 show the interrupt factors thatare ORed within the SCU.
Table SCU (Sensor Control Unit)-134 Information Interrupts
Interrupt Name

NumberDescription

Edge/Level

LPADC_ALMO

4 (n = 0, ...,The data amount stored in the FIFO for the “n” th channel of the LPADC

Selecta

ST_FULLn3) *within the ADCIF has reached the Watermark

ble

HPADCn_ALM

2 (n = 1, 2)

The data amount stored in the FIFO for the “n” th channel of the HPADC

Selectawithin the ADCIF has reached the Watermark

ble

Rise Event of the Math Function n within the MATH_PROCEdge

The data amount stored in the FIFO partition D0_Rn has reached the

Selecta

Watermarkble

The data amount stored in the FIFO partition D1_Rn has reached the

Selecta

Watermarkble

OST_FULL
MATH_EVENT

3 (n = 0, 1,

n_R

2)

D0_Rn_C_ALM

2 (n = 1, 2)

OST_FULL
D1_Rn_C_ALM

2 (n = 1, 2)

OST_FULL
Nn_R1_C_ALM

8 (n = 0, ...,The data amount stored in the FIFO partition Nn_R1 has reached the

Selecta

OST_FULL

7)

Watermarkble

Dn_R3_CH_AL

2 (n = 0, 1)

The data amount stored in the FIFO partition Dn_R3 has reached the

Selecta

WatermarkbleInterrupt n from the internal sequencer

Selecta

MOST_FULL
ISOPn

4 (n = 0, ...
3)

MATH_EVENT

3 (n = 0, 1,

n_F

2)

PWMn_INVALI

8 (n = 0, ...,

D_VALUE

7)

ble
Fall Event of Math Function n within the MATH_PROC

Edge

PWMn timer mode interrupt

Edge

Note: As for the name of the interrupt for LPADC ch.0, the n is not “0” but is left blank.

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Table SCU (Sensor Control Unit)-135 System Error Interrupts
Interrupt Name

NumberDescription

Edge/
Level

LPADC_OVE

4(nR_RUNn0, ..., 3) *=overflowed

HPADCn_OV

2 (n = 1, 2)

The FIFO for the “n” th channel of the HPADC within the ADCIF has

ER_RUNADCIF_REA

The FIFO for the “n” th channel of the LPADC within the ADCIF has

Edge

Edge

overflowed
1

An abnormal readout from the FIFO within the ADCIF has occurredEdge

2 (n = 1, 2)

The FIFO partition D0_Rn has overflowedLevel

2 (n = 1, 2)

The FIFO partition D1_Rn has overflowed

Level

Nn_R1_C_OV8=The FIFO partition Nn_R1 has overflowed

Level

ER_RUN

0, ..., 7)

Dn_R3_CH_O

2 (n = 0, 1)

The FIFO partition Dn_R3 has overflowed

Level

LPADC_UND

4

The FIFO for the “n” th channel of the LPADC within the ADCIF was empty

Edge

ER_RUNn

0, ..., 3) *but readout

HPADCn_UN

2 (n = 1, 2)

The FIFO for the “n” th channel of the HPADC within the ADCIF was empty

D_ERR
D0_Rn_C_OV
ER_RUN
D1_Rn_C_OV
ER_RUN(nVER_RUN(n=

DER_RUN
D0_Rn_C_UN

Edge

but readout
2 (n = 1, 2)

The FIFO partition D0_Rn was empty but readoutLevel

2 (n = 1, 2)

The FIFO partition D1_Rn was empty but readout

Level

Nn_R1_C_UN

8=

The FIFO partition Nn_R1 was empty but readout

Level

DER_RUN0, ..., 7)

Dn_R3_CH_U

2 (n = 0, 1)

The FIFO partition Dn_R3 was empty but readout

Level

REQ_BEFOR

10=

The execution of SEQn wasn’t in time by the next execution opportunity

Level

E_FINISHn

0, ..., 9)

EXE_ERRn

10=

An error occurred when executing SEQn

Level

DER_RUN
D1_Rn_C_UN
DER_RUN(nNDER_RUN(n(n0, ..., 9)

Note: As for the name of the interrupt for LPADC ch.0, the n is not “0” but is left blank.
For the internal sequencers, interrupt signals separate from the those for the upper CPU are connected.

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Table SCU (Sensor Control Unit)-136 shows the interrupt factors received by the sequencers.
Table SCU (Sensor Control Unit)-136 Interrupts for the Sequencers
Interrupt Name

NumberDescription

EXE_REQ_STTn

10 (n = 0, ..., 9)

Execution request to SEQn

APB_ACCESS_INHI

1

Access to the APB was prohibited by the upper CPU

1

The FIFO for the data received via the I2C0 has the specified number of data

1

The FIFO for the data sent via the I2C0 is empty but a STOP command has not

BIT
I2C0_RX_ALMOST_
FULL
I2C0_MASTER_ON_
HOLD

been issued

I2C0_ACTIVE

1

The operation of the I2C0 is Active

I2C1_RX_ALMOST_

1

The FIFO for the data received via the I2C1 has the specified number of data

1

The FIFO for the data sent via the I2C1 is empty but a STOP command has not

FULL
I2C1_MASTER_ON_
HOLD

been issued

I2C1_ACTIVE

1

The operation of the I2C1 is Active

LPADCn_NOT_EMP

4 (n = 0, ..., 3)

The FIFO for the “n” th channel of the LPADC has one or more data

2 (n = 0, 1)

The FIFO for the “n” th channel of the HPADC has one or more data

1

Indicates whether or not writing is possible to the MATH_PROC

1

Indicates whether or not readout is possible from the MATH_PROC

FIFO0_ALL_ON_STT

1

Indicates that the power supply status of the FIFO SRAM (8 KByte) is All On

FIFO1_ALL_ON_STT

1

Indicates that the power supply status of the FIFO SRAM (32 KByte) is All

TY
HPADCn_NOT_EMP
TY
MATH_PROC_WRIT
E_DATA_READY
MATH_PROC_READ_DATA_READYOn
TIMER_INTn

3 (n = 0, ..., 2)

Timer mode interrupt (selectable from eight lines) of PWMm (m = 0, ..., 7)

The firmware of the SCU internal sequencer notifies the CPU of the following interrupts.
Table SCU (Sensor Control Unit)-137 Internal Sequencer Interrupts
Interrupt Name

Description

iSoP0

Data was output to the Output Region 0 of the one-shot sequencer

iSoP1

Data was output to the Output Region 1 of the one-shot sequencer

iSoP2

Data was output to the Output Region 2 of the one-shot sequencer

iSoP3

A complete interrupt or suspend interrupt occurred(Synchronous communication control interrupt between the SCU and CPU)

EXE_ERR

An error occurred during execution of the sequencer－317/1293－

CXD5602 User Manual

REQ_BEFORE_FINISH

3.9.7

This process was not in time by the next startup of the sequencer. A timeout error.

MATH_PROC processing

The MATH_PROC processing performs programmable arithmetic processing to the data captured by thesensors.
When using MATH_PROC processing, make sure that the data type is “Calculation Operable Sample Type”.
Calculation Operable Sample Type refers to one of the following data types.
Calculation Operable Sample Type・16-bit 1 axis: 1 sample = {x} format(2 Byte)・16-bit 2 axis: 1 sample = {x,y} format(4 Byte)・16-bit 3 axis: 1 sample = {x,y,z} format(6 Byte)The following processes can be handled.
Preprocessing (For details, see Section 3.9.7.1)
・Unsigned data/signed data conversion
・Gain multiplication by vector element
・Offset addition by vector element
Decimation Processing (For details, see Section 3.9.7.2)
・Decimation
・Multiplication processing with clipping
Math Function Processing (For details, refer to Section 3.9.7.3)
・2nd order IIR filters
・Normalization processing
・Excess detection (Event)In the MATH_PROC processing, a total of 10 lines of executable data paths can be used by combining theabove calculations. There are two types of data paths according to the differences in what they process.
Decimation Partition Data Path

… x two linesNormal Sensor Partition Data Path … x eight lines
Figure SCU (Sensor Control Unit)-85 and Figure SCU (Sensor Control Unit)-86 show the structures of eachdata path.

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CXD5602 User ManualDR

Math function

Decim
0-1

DR

Math function

Decim
0-2

DR

Math function

Decim
0-3

DR

Math function

Pre

Figure SCU (Sensor Control Unit)-85 Decimation Partition Data Path
・Preprocessing can be performed to the 1, 2, or 3 axis data of the signed 16 bit.
・The data after preprocessing can be sent through three lines of Decimeters and one bypass path.
・Afterwards, Dynamic Range adjustment can be applied separately to the four lines of data.
・And then, the Math Function can be assigned.

Math function

Pre

Figure SCU (Sensor Control Unit)-86 Normal Sensor Partition Data Path
・Preprocessing can be performed to the 1, 2, or 3 axis data of the signed 16bit.
・Afterwards, the Math Function can be assigned.
The Math Function processing can be inserted in up to three paths among the total of 16 paths in the
MATH_PROC (four paths per Decimation Partition Data Path x two lines, 1 path per Normal Sensor Partition
Data Path x eight lines). In the Decimation Partition Data Path example in Figure SCU (Sensor Control Unit)-85,
the Math Function is inserted only in the Decim 0-3 lines, and the Dynamic Range adjustment (DR) output isdirectly connected to the direct connection/Decim 0-1/Decim 0-2 lines.

3.9.7.1 Preprocessing
The following functions can be executed for all MATH_PROC paths according to the values set in the registers.
(1) Signed data/unsigned data conversion(2) Offset addition(3) Gain multiplication
These processes are called Preprocessing and the data flow is shown in Figure SCU (Sensor Control Unit)-87.

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CXD5602 User Manual

X

round
and
clip

bin
two

Y

unsigned_to_signed
OffsetGain

Figure SCU (Sensor Control Unit)-87 Preprocessing Data Flow
As for offset addition and gain multiplication, when the data is multiple-axis (2 axis/3 axis), settings can bemade independently for each X, Y, and Z axis.

3.9.7.2 Decimation Processing

In the MATH_PROC processing, up to two lines of decimation filters (two-stage CIC filter) can be used, which
can be applied to the sensor data captured by the SEQ0 sequencer and SEQ1 sequencer.
The decimation path has four output paths per each input, and 1/(2^n) decimation can be selected for three ofthem depending on the settings. A two-stage CIC filter process is applied for the decimation processing.
For the three target paths of decimation, the results of decimation, the input signal in its original form, or thesetting for 0-fixed output can be selected.
Also, after the decimation processing, multiplying by 2n times with clipping is performed. In this process, acommon multiplying by 2n times coefficient is used for the X, Y, and Z axes.
Figure SCU (Sensor Control Unit)-88 shows the data flow of the decimation and multiplication processing withclipping.

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Level
Adj

wrap

wrap

FF

FF

1/2N0
wrap

FF

FF

wrap

bit
Shift

clip

wrap

bit
Shift

clip

wrap

bit
Shift

clip

FF

1/2N1
wrap

FF

FF

Level
Adj

FF

1/2N2
wrap

FF

Level
Adj

FF

Level
Adj

FF

Figure SCU (Sensor Control Unit)-88 Decimation Processing Data Flow

3.9.7.3 Math Function Processing
3.9.7.3.1

2nd Order IIR Filter

The Math Function is a function block comprised of 2nd order IIR Filters, normalization processing, and excess
detection.
Of the 16 paths for writing to the FIFO within the MATH_PROC, up to three can be independently inserted inarbitrary paths.
Within the Math Function, there are the two following data paths.
(1) Path that outputs to the FIFO
(2) Path that is input to the excess detection after the normalization processing
Figure SCU (Sensor Control Unit)-89 shows the overall data path within the Math Function.

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CXD5602 User Manual

1

2

5

3

6

Norm.

4

7

2nd order
IIR

8

Excess
Detector

2nd order
IIR

Figure SCU (Sensor Control Unit)-89 Data Flow within the Math Function
The path on the top is output to the FIFO and the path on the bottom is used for excess detection.
Also, at blocks 1 through 8 in Figure SCU (Sensor Control Unit)-89, two 2nd order IIR filters can be inserted atarbitrary points by setting the registers.
Figure SCU (Sensor Control Unit)-90 shows the combination of data paths when 2nd order IIR filters areinserted.

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CXD5602 User Manual

4'b0001

4'b1000
2nd order
IIR

2nd order
IIR

Excess
DetectorNorm.

4'b0010Norm.

2nd order
IIR

2nd order
IIR

Excess
Detector

2nd order
IIR

Excess
Detector

4'b1001
2nd order
IIR

Norm.

2nd order
IIR

2nd order
IIR

Excess
DetectorNorm.

4'b1010

4'b0011
2nd order
IIR

2nd order
IIR

2nd order
IIR

Norm.

Excess
DetectorNorm.

2nd order
IIR

Excess
Detector

2nd order
IIR

Excess
Detector

4'b1100

4'b0100

2nd order
IIR

2nd order
IIR

Norm.

Excess
Detector

4'b0101

2nd order
IIR

Norm.

else
2nd order
IIR

2nd order
IIR

Norm.

Excess
Detector

Norm.

Excess
Detector

4'b0110
2nd order
IIR

2nd order
IIR

Norm.

Excess
Detector

Figure SCU (Sensor Control Unit)-90 2 2nd Order IIR Filter Combinations
The 2nd order IIR Filters allows settings of five multiplication coefficients, the input, and the amount of bit
shift of the output.
Figure SCU (Sensor Control Unit)-89 shows the internal data flow of the 2nd order IIR filters.

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CXD5602 User Manual

EN
bit
shift

C0

S1

Z-1

C1

Z-1

round
and
clip

bit
shift

round

clip

Y

S2

・・・

X

SEL

C2
round

Z-1

C3

・・・

round

Z-1

C4

round

round

Figure SCU (Sensor Control Unit)-91 2nd Order IIR Filter Internal Data Flow

3.9.7.3.2

Normalization Processing

The normalization processing performs simplified conversion of multiple axis (2 axis/3 axis) data to single axis
values.
The square sum of each axis becomes a circle when the two axes have the same values, and becomes a spherewhen the three axes have the same value. However, in normalization processing, the values are calculated as
approximates to a rectangular octagon when converting from two axes.


1st order The absolute value of the input is output as-is
Output = |x|

2nd order
Output = 123/128 x Max(|x|,|y|) + 51/128 x Min(|x|,|y|)

3rd order
L1 = 120/128 x Max(|x|,|y|) + 49/128 x Min(|x|,|y|)Output = Max(L1,|z|) + 44/128 x Min(L1,|z|)Figure SCU (Sensor Control Unit)-92 shows the data flow of normalization processing.

formatconvert

123

120
x
y

abs

Max(x,y)abs

Min(x,y)

round
and
clip

formatconvertMax(L1,z)
bit
shift

Min(L1,z)51zformatconvert

round
and
clip

44

49
abs

Figure SCU (Sensor Control Unit)-92 Normalization Processing Data Flow－324/1293－

CXD5602 User Manual

3.9.7.3.3

Excess Detection

The Excess Detection function performs excess detection to the value converted to 1 axis at the normalization
processing and then outputs an interrupt to the upper module. Also, the result of this conversion can be used forwriting control to the FIFO.
There are two thresholds in the internal comparator. The comparator determines whether the target input value
is bigger than top threshold or smaller than bottom threshold or not. Next to the comparator, two circuits areconnected in two-step cascade connection. They detect whether the “true” result of the comparator’sdetermination occurs for the specified number of times in series. The output from the second circuit becomes to be
the determination. By using registers, you can delay the interrupt occurrence which is output in response to thedetermination.
The occurrence of the two interrupts: Rise interrupt which indicates the transition from Low to High, and Fallinterrupt which indicates the transition from High to Low, can be selected independently.
Figure SCU (Sensor Control Unit)-93 shows an example of the input value’s change with time and theoperation of the excess detection.
dummy
UTHRESHUCOUNTLCOUNT

LTHRESH

Statusover
under
UTHRE LTHRES
SH
H

over
UTHRESHDELAY_SAMPLEInterrupt

Figure SCU (Sensor Control Unit)-93 Excess Detection Operation (by a Comparator and an Excess Detector)
The Excess Detection function of the MATH_PROC actually has a different interrupt output from the above
Figure because the excess detection is operated with two-step cascade connection.
Figure SCU (Sensor Control Unit)-94 shows the operation of excess detection in two-step cascade connection.

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dummy
UCOUNT0

UTHRESHUCOUNT1

Upper
status in

LTHRESHUpper
status in

Lowerstatus in

LCOUNT0

Lower
status in

Upper
DetectUpper
DetectUpper
DetectLower
DetectLower
DetectLower
DetectData Input
UTHRESH
LTHRESH

check the continuity of the status
No.1
Status(Upper,Lower)

Comparator

Status(Upper,Lower)LCOUNT1

check the continuity of the status
No.2
Status(Upper,Lower)UCOUNT0
LCOUNT0
UCOUNT1LCOUNT1

Interrupt Signal
Generator

RISE_INT_EN

interrupt

FALL_INT_EN
DELAY_SAMPLE_R
DELAY_SAMPLE_F

Figure SCU (Sensor Control Unit)-94 Excess Detection Operation (Two-step Cascade Connection)
In the two-step cascade connection, the first step of detection is called “Status Continuity Determination 0” andthe second step is called “Continuity Determination 1”.
The following explains the details of interrupt occurrence conditions using Rise interrupt as an example.
Precondition:
UCOUNT0… Number of status continuity of the top threshold of the status continuity determination 0

LCOUNT0… Number of status continuity of the bottom threshold of the status continuity determination

0
UCOUNT1… Number of status continuity of the top threshold of the status continuity determination 1

DELAY_SAMPLE_R … Delay of Rise interrupt occurrenceWhen UCOUNT0==0, a Rise interrupt occurs regardless of the UCOUNT1/DELAY_SAMPLE_R setting
value.



When UCOUNT0 ≥ 1 and UCOUNT1==0 and DELAY_SAMPLE_R==0, a Rise interrupt occurs
immediately after the detection results of continuous match detection 0 changes to upper.
E.g.: When UCOUNT0=2/UCOUNT1=0/DELAY_SMAPLE_R=0, a Rise interrupt occurs when Upper data
is input two samples in a row.

When UCOUNT0 ≥ 1 and UCOUNT1 ≥ 1 and DELAY_SAMPLE_R==0, a Rise interrupt occurs when thedetection results of continuous match detection 0 changes to Upper, and the results of continuous matchdetection 0 remain in upper state for UCOUNT1-1 samples.

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E.g.: When UCOUNT0==2/UCOUNT1==4/DELAY_SMAPLE_R==0
A Rise interrupt occurs when Upper data is input two samples in a row, and Upper data continues for threesamples after.
When Upper data is input two samples in a row, and Lower data continues for LCOUNT0 times or more
within three samples, the UCOUNT conditions are not referenced and the continuous match count of
UCOUNT1 returns to its initial value.
The startup condition of the counter which counts delay time is set as shown below.
((UCOUNT0 ≥ 1 and UCOUNT1==0 and the results of status continuity determination 0 is“Upper”) or (UCOUNT0 ≥ 1 and UCOUNT1 ≥ 1 and the results of status continuity
determination 1 is “Upper”))When DELAY_SAMPLE_R ≥ 1
When the startup condition of the counter written above is satisfied, the DELAY_SAMPLE_R counter turns
to operation state, and regardless of the input data, a Rise interrupt occurs after the DELAY_SAMPLE_R
sample, and the DELAY_SAMPLE_R counter enters a stop state.
E.g.: When UCOUNT0=2/UCOUNT1=0/DELAY_SMAPLE_R=7 and the detection result is Lower for two
consecutive times, a Rise interrupt occurs after seven sample times regardless of the detection result that
follows.
E.g.: When UCOUNT0=2/UCOUNT1=4/DELAY_SAMPLE_R=2 and the detection result is Upper for two
consecutive times, “Status Continuity Determination 0” is Upper and this state is held four times (after statuschanges to "Upper", the detection result is Upper for three consecutive times), a Rise interrupt occurs after
two sample times regardless of the detection result that follows.
After Upper data is input two samples in a row, and the Lower data continues for LCOUNT0 times or more
within three samples, the UCOUNT conditions are not referenced and the count of the status continuity
determination of UCOUNT1 returns to its initial value.


Delay counter startup triggers that occur during the counter operation of DELAY_SAMPLE_R are
ignored.

The Fall interrupt operates in the same way (the settings are exchanged between UCOUNT<-->LCOUNT, thedetection results of the Upper part are re-read as Lower, and DELAY_SAMPLE_R is re-read as
DELAY_SAMPLE_L).
[Caution] Do not enter a negative value for the excess detection. The detection result will be incorrect.

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3.9.7.4 FIFO Writing
The following FIFO writing conditions can be set in conjunction with the interrupts generated by the excess
detection function of the Math Function.


Stop writing by generating Rise/Fall interrupt
・Performs writing to the FIFO until an interrupt occurs, and after the interrupt, writes to the FIFO until a
specified number of samples.
・Writing is stopped from the specified number of samples +1 until the FIFO writing control interrupt iscleared.

Start writing by generating Rise/Fall interrupt
・Writing to the FIFO is not performed until an interrupt is generated, and writing starts from when theinterrupt is generated.

Writing continues regardless of the generation of Rise/Fall interrupts

Writing is stopped regardless of the Rise/Fall interrupts

3.9.8

FIFO

3.9.8.1 Overview
The FIFO operation is such that the values written to the writing ports of the two SRAMs (8 KByte＋32 Kbyteeach) can be readout from the readout ports in the same order. The SRAMs are divided into regions called“Partitions”, where each one can be used as FIFO. Up to 27 partitions can be used.

3.9.8.2 FIFO Writing Data Types
The data unit that can be written to the FIFO is defined as a “Sample”.
Each Sample must use one of the “data types” listed below.
(1) Calculation Operable Sample Type
16-bit 1 axis: 1 Sample = {x} format(2 Byte/Sample)

16-bit 2 axis: 1 Sample = {x,y} format(4 Byte/Sample)

16-bit 3 axis: 1 Sample = {x,y,z} format(6 Byte/Sample)(2) Calculation Inoperable Sample Type
24-bit : 1 Sample format(3 Byte/Sample)

32-bit : 1 Sample format(4 Byte/Sample)

48-bit : 1 Sample format(6 Byte/Sample)

64-bit : 1 Sample format(8 Byte/Sample)

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128-bit :1 Sample format(16 Byte/Sample)

3.9.8.3 Partition
The SRAM for the FIFO has up to 27 partitions.
The partitions are classified as follows:(1) Decimation Partitions…

x 4 partitions x 2 sets (Total: 8 partitions)(2) Normal Sensor Partitions …

x 8 partitions(3) Virtual Sensor Partitions …

x 10 partitions(4) Random Access Partitions … x 1 partition
The region of each partition is allocated by specifying an arbitrary address size from the 40 Kbytes of SRAM. The
allocation must be done under the following conditions.


The partition regions must not overlapEach partition size must be equal to or larger than the value 1 and must be an integral multiple of the Sample
size.



The writing port and readout port must have a one-to-one relation, and the readout ports that are not usedmust be set to disable.

When performing power supply control of the SRAM, the partition region must not be set across the 8
Kbytes and 32 Kbytes of the two SRAMs.
The number of each partition’s writing ports/readout ports depends on the type of the partition. For clarification,

Table SCU (Sensor Control Unit)-138 shows the mnemonics for each partition name and by each writing
port/readout port.
Table SCU (Sensor Control Unit)-138 Partition Name and Writing Port/Readout* Port
Partition TypePartition

Write

Read0

Read1

Read2

Read3

D0_W0_S

D0_R0_H

D0_R1_C

D0_R2_C

D0_R3_CH

D1_R0_H

D1_R1_C

D1_R2_C

D1_R3_CH

Name
Decimation Partition

D0

D0_W1_S
D0_W2_S
D0_W3_S
D1

D1_W0_S
D1_W1_S
D1_W2_S
D1_W3_S

NormalPartition

Sensor

N0

N0_W_S

N0_R0_H

N0_R1_C

Not Available

Not Available

N1

N1_W_S

N1_R0_H

N1_R1_C

Not Available

Not Available

N2

N2_W_S

N2_R0_H

N2_R1_C

Not Available

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RandomAccessN3

N3_W_S

N3_R0_H

N3_R1_C

Not Available

Not Available

N4

N4_W_S

N4_R0_H

N4_R1_C

Not Available

Not Available

N5

N5_W_S

N5_R0_H

N5_R1_C

Not Available

Not Available

N6

N6_W_S

N6_R0_H

N6_R1_C

Not Available

Not Available

N7

N7_W_S

N7_R0_H

N7_R1_C

Not Available

Not Available

V0

V0_W_C

V0_R_H

Not Available

Not Available

Not Available

V1

V1_W_C

V1_R_H

Not Available

Not Available

Not Available

V2

V2_W_C

V2_R_H

Not Available

Not Available

Not Available

V3

V3_W_C

V3_R_H

Not Available

Not Available

Not Available

V4

V4_W_C

V4_R_H

Not Available

Not Available

Not Available

V5

V5_W_C

V5_R_H

Not Available

Not Available

Not Available

V6

V6_W_C

V6_R_H

Not Available

Not Available

Not Available

V7

V7_W_C

V7_R_H

Not Available

Not Available

Not Available

V8

V8_W_C

V8_R_H

Not Available

Not Available

Not Available

V9

V9_W_C

V9_R_H

Not Available

Not Available

Not Available

R0

R0_W_CH

R0_R_CH

Not Available

Not Available

Not Available

Partition

The one to two character suffix of the mnemonic describes the access privileges for the given writing
port/readout port as follows:・"S"For partitions that can be written to from the SCU・"C"For partitions that can be written to/readout from the CPU・"H"For partitions that can be readout from the Host

・"CH" For partitions that can be written to/readout from by selecting the CPU or Host
Table SCU (Sensor Control Unit)-139 shows the addresses of each partition’s readout ports and writing ports.
Table SCU (Sensor Control Unit)-139 Writing Port and Readout Port Addresses
WritingPort

WritingPort

Readout

Port

Readout

Port

Readout

Port

Readout

Address

Mnemonic

Address

Mnemonic

Address

Mnemonic

0x2000

D0_W0_S

0x2100D0_R1_C

0x2160V0_R_H

0x2004

D0_W1_S

0x2104

D0_R2_C

0x2164

V1_R_H

0x2008

D0_W2_S

0x2108

D1_R1_C

0x2168V2_R_H

0x200C

D0_W3_S

0x210C

D1_R2_C

0x216C

V3_R_H

0x2010

D1_W0_S

0x2110N0_R1_C

0x2170

V4_R_H

0x2014

D1_W1_S

0x2114

N1_R1_C

0x2174

V5_R_H

0x2018

D1_W2_S

0x2118N2_R1_C

0x2178V6_R_H

0x201C

D1_W3_S

0x211C

N3_R1_C

0x217C

V7_R_H

0x2020N0_W_S

0x2120

N4_R1_C

0x2180

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0x2024

N1_W_S

0x2124

N5_R1_C

0x2028N2_W_S

0x2128N6_R1_C

0x202C

N3_W_S

0x212C

N7_R1_C

0x2030

N4_W_S

0x2130D0_R3_CH

0x2034

N5_W_S

0x2134

D1_R3_CH

0x2038

N6_W_S

0x2138

D0_R0_H

0x203C

N7_W_S

0x213C

D1_R1_H

0x2040V0_W_C0x2140N0_R0_H

0x2044

V1_W_C0x2144

N1_R0_H

0x2048

V2_W_C0x2148N2_R0_H

0x204C

V3_W_C0x214C

N3_R0_H

0x2050

V4_W_C

0x2150

N4_R0_H

0x2054

V5_W_C

0x2154

N5_R0_H

0x2058

V6_W_C

0x2158N6_R0_H

0x205C

V7_W_C

0x215C

N7_R0_H

0x2060

V8_W_C0x2064

V9_W_C

0x2184

V9_R_HAmong the FIFO access space (Addresses 0x2000 to 0x2FFF), the addresses not shown in Table SCU (Sensor
Control Unit)-139 are Reserved and are writing-invalid (no error response) and 0 read during readout (no error
response).
Since the Random Access partition has a non-FIFO structure, it does not have physical writing ports or physicalreadout ports.

3.9.8.4 Decimation Partition
The Decimation partition stores the data that was decimation-processed by the MATH_PROC. There are two
sets of Decimation partitions, each of which is comprised of four sub-partitions.
Within each sub-partition of the Decimation partition, data can be stored as either Calculation Operable Sample
Type or Calculation Inoperable Sample Type but when performing decimation or arithmetic processing,
Calculation Operable Sample Type must be used.
The Decimation partition can only be written from the internal sequencer of the SCU, and writing from the
CPU or Host is prohibited. The four sub-partitions within a certain Decimation partition stores sample data thatdiffers in terms of decimation rate based on the same sample data.
The Decimation partition has four different readout ports per partition, each to which one of the four
sub-partitions can be assigned according to the setting.

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CXD5602 User ManualCPU dedicated readout portx2

Host dedicated readout portx1

CPU or Host readout port

x1

[Caution] The writing port and readout port must have a one-to-one relation. In the reset initial state, all readout
ports are connected to the same readout port Dn_W0_S (n=0,1). Therefore, be sure to make the proper settings.

3.9.8.5 Virtual Sensor Partition
The Virtual Sensor partition allows the storage of arbitrary data (Virtual Sensor data) and there are 10 of thesepartitions. This partition can store data as either Calculation Operable Sample Type or Calculation Inoperable
Sample Type.
Writing to the Virtual Sensor partition is only possible from the CPU. Writing from the Host is prohibited.
The Virtual Sensor partitions have only one readout port for the Host per partition.

3.9.8.6 Random Access Partition
The Random Access partition can be used for data communication between the Host and CPU, and only one of
27 partitions can be set as the Random Access partition. The Random Access partition has a non-FIFO structure,and data can be randomly written and readout to/from the CPU or Host.
Reading/Writing access is possible be selecting an arbitrary address from the 40 Kbytes of the SRAM. However,caution is required so that the data of other partitions is not corrupted by exceeding the region secured for theRandom Access partition.
The Random Access partition is used as a buffer region for communication between the Host and CPU.

3.9.8.7 Partition Common Specifications (other than the Random Access Partition)
When writing a value to the FIFO write register (Writing Port), the value is stacked in the FIFO.
The behavior when writing data during FIFO Full can be selected from the following:(1) Data writing failed, and older data is stored(2) The oldest data is overwritten
For readout, there are either one or multiple readout ports depending on the type of the partition.
When reading out from the FIFO readout register (Readout Port), the oldest data corresponding to that port can bereadout.
Each readout port has the following functions.
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Valid data amount can be readout separately

Watermark Level (Almost Full) can be set separately

Interrupts/DMA transfer requests such as the following can be generated separately
When the valid data amount becomes equal to or higher than the Watermark, an interrupt is asserted,
and when it falls below the Watermark, an interrupt is negated.

When the valid data amount becomes equal to or higher than the Watermark, DMA_BREQ isasserted, and when 1 or larger, DMA_SREQ is asserted.

When the DMA_CLR from the DMAC becomes “1”, the DMA_BREQ and DMA_SREQ are once
negated, and the DMA_BREQ and DMA_SREQ are asserted again in accordance with the valid
data amount.



FIFO Clear (setting is enforced as valid data amount = 0) can be performed separately

Equips a separate time stamp readout registerFrom the time stamp readout register, the value that corresponds to the below readable data can be obtained.



The time stamp value is calculated from the following formula:“the time stamp that corresponds to the latest value - (valid data amount -1) x data capture interval”

3.9.8.8 Time Stamp
Each partition excluding the Random Access partition has time stamp information.
Time stamps are count values of 47 bits that are incremented at 32.768 kHz intervals. The upper 32 bits indicate“integer part of second” while the lower 15 bits are values of “second after the decimal point”.

3.9.8.8.1

Time Stamp Value Handling at the Writing Side

The partition to which data is written from the SCU (internal sequencer) is directly connected to the time stamp
information supplied from the other block, and the writing side time stamp information is updated according to thedata writing timing.
The partition to which data is written from the CPU has the following registers which can be set from the CPU.


Reference time stamp value

Writing time interval value
The CPU first writes the reference time stamp value and writing time interval value. Then, each time the CPU

writes data to the FIFO, the writing time interval value is cumulatively added to the reference time stamp value.
The cumulatively added time stamp value can be read out as the register value by the CPU.
Time stamp generation logic when reading out
Within the FIFO, the time stamp values of each datum are not stored together in the FIFO, instead, the writingside (latest) time stamp values and the writing time interval values are stored.
The readout side time stamps are values calculated during readout by the following equation.

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Writing side (= latest) time stamp – (valid data samples – 1) x writing time interval

3.9.8.9 FIFO Block Diagram

SCU_FIFODMA
HandShake

FIFO_REG

MUX

Timestamp

DecorderRAM I/F

SRAM

Figure SCU (Sensor Control Unit)-95 FIFO Block Diagram

3.9.8.10

FIFO Points of Attention

The partition regions must not overlap.

The partition size must be 1 or larger, and must be an integral multiple of the sample size.

The writing port and readout port must have a one-to-one relation, and the readout ports that are notused must be disabled.

When performing power supply control of the SRAM, do not set the partition region across the 8
Kbyte and 32 KByte SRAMs.



When performing a Clear to the FIFO writing port, also make sure to perform a Clear to thecorresponding readout port.

When changing FIFO_ENABLE from Disable to Enable, make sure to perform a Clear to the FIFO
readout port.



3.9.9

Do not set the WATER_MARK register to “0”.

Sequencers

The sequencers intermittently capture sensor data from the external sensors connected to the SPI, I2C or analog
input using the specified time intervals as triggers.

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Data Transfer Function

Reads the data from the I2C/SPI and transfers it to the FIFO
・Data can be transferred periodically according to the interrupt from the SCU_CTRL.



In accordance with the process request from the CPU, data can be read from the I2C/SPI (only one time) andtransferred to the FIFO (One-shot Operation)
・Completion of the transfer is notified when the transfer completes.

Reads data from the ADCIF (data to which AD conversion is applied at the AD converter) and transfers it to
the FIFO (AD data transfer)



MATH_PROC processing can be performed before the data is transferred to the FIFO.
・Inputs data to the MATH_PROC and takes out the results and writes to the FIFO
・Judges whether or not to write to the FIFO according to the event output from the MATH_PROC
Data Duplication Function

The ID of Write FIFO to which the data output from each sequencer is written is already specified. However,this function allows the output to be duplicated to one other Write FIFO.
Data Processing FunctionWhen the data is sent to the MATH_PROC, a maximum data size of 6 Bytes can be Byte Swapped or Left
Bit Shifted in units of 2 Btyes before input to the MATH_PROC.
Note: Since the data processing within the MATH_PROC is performed by the hardware other than thesequencer, the internal sequencer is not involved.
Other Functions

SCU-CPU Synchronization Function
・When one cycle of the sequencer operation is completed, an interrupt notification is sent to the CPU(suspend interrupt)
After sending the suspend interrupt, if the CPU cannot clear the suspend interrupt request by the next time
the MATH_PROC starts up, an error flag within the SCU_RAM is asserted, and the error is notified to theCPU.
・When the sequencer’s periodic startup has been completed and a separate startup request is not sent fromthe CPU, an interrupt notification is sent to the CPU (complete interrupt).
The following shows the five main operations of the sequencer in the order they are executed.

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Among these processes, the Startup control is fully implemented in the hardware while the other operations are
implemented in the software of the sequencer controller.
There are 10 independent sequencers within the sequencer, each to which separate startup control and sensor
polling settings are possible.
Figure SCU (Sensor Control Unit)-96 shows the overall processes of the sequencers.

SPI MasterI2C Master 0

LPADC

I2C Master 1

HPADC0HPADC1SEQUENCER
10 instruction groupassertion of
Trigger SingalorInterrupt
signalGenerate signal
about request
for Startup

3 instruction grouprequestConfiguration
to sequencer

completion
noticeConfiguration
Data

SCU_REGData
formattingandControl
FIFO

Read
Sensor
Data

MATH_PROCSCU_FIFO

Configuration
Data

Data formatting

Writing to FIFO
Setting

10 configuration
data set

10 configuration
data set

16 configuration
data set

Figure SCU (Sensor Control Unit)-96 Sequencer Overall Image
Figure SCU (Sensor Control Unit)-97 shows an example of the process. The SEQ ID0 operates periodicallyaccording to the timer, and the data from the I2C is captured. The SEQ ID1 starts up by a certain trigger andcaptures the data of the LPADC FIFO.
Periodic Access by timer
some kind of trigger

SEQ
ID0

startupconfig.

startupconfig.

SEQ
ID1

HW
Resource

Sequencer
Statusgenerate thefetch the
MATH_PROC
bus transactions external data processing

startupconfig.

fetch theexternal data

generate thefetch the
MATH_PROC
bus transactions external data processing

Write
FIFO

Write
FIFO

LPADC
FIFO

I2C BUS Access

IDLE

Write
FIFO

BUSY

I2C BUS Access

IDLE

BUSY

IDLE

Figure SCU (Sensor Control Unit)-97 Sequencer Process Flow (Example)
The 10 sequencer requests startup independently. However, afterwards, the sequences are processed one at atime in order because each process of the external bus transaction generation, external data capture,
MATH_PROC processing, and FIFO writing are executed by the sequencer software.
The normal (excluding the duplication function) data flow is shown below.

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SCU_RAM

Sequencer
SEQ0

I2C0

I2C1

SCU_RAMSEQ1
SCU_RAMSEQ2

LPADC0/1/2/3
ADCIF

SCU_RAM

D0_W0_S

D0_R0_H

D0_W1_S

D0_R1_C

D0_W2_S

D0_R2_C

D0_W3_S

D0_R3_CH

D1_W0_S

D1_R0_H

D1_W1_S

D1_R1_C

D1_W2_S

D1_R2_C

D1_W3_S

D1_R3_CH

N0_W_S

N0_R0_H

N1_W_S

N1_R0_H

N2_W_S

N2_R0_H

N0_R1_C

SEQ3

HPADC0/1
SCU_RAMSEQ4
SCU_RAM

N1_R1_C
N2_R1_C
N3_W_S

N3_R0_H

N4_W_S

N4_R0_H

N5_W_S

N5_R0_H

SEQ5

N3_R1_C
SCU_RAMSEQ6
SCU_RAM
SEQ7

N4_R1_C
N5_R1_C
N6_W_S

N6_R0_H

N7_W_S

N7_R0_H

N6_R1_C
SCU_RAM

N7_R1_C

SEQ8
SCU_RAM
SEQ9
From SEQ0-9

MATH_PROCSCU_RAMCPUCPU or HOST

V0_W_C

V0_R_H

V1_W_C

V1_R_H

V2_W_C

V2_R_H

V3_W_C

V3_R_H

V4_W_C

V4_R_H

V5_W_C

V5_R_H

V6_W_C

V6_R_H

V7_W_C

V7_R_H

V8_W_C

V8_R_H

V9_W_C

V9_R_H

R0_W_CH

R0_R_CH

Figure SCU (Sensor Control Unit)-98 Overall Data Flow (excluding Data Duplication Function)－337/1293－

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3.9.9.1 Startup Control
SPI MasterI2C Master 0

HPADC0LPADC

I2C Master 1

HPADC1SEQUENCER
10 instruction groupassertion of
Trigger SingalorInterrupt
signalGenerate signal
about request
for Startup

3 instruction grouprequestConfiguration
to sequencer

completion
noticeConfiguration
Data

SCU_REG

Read
SensorData

Data
formattingandControl
FIFO

MATH_PROCSCU_FIFO

Configuration
Data

Data formatting

Writing to FIFO
Setting

10 configuration
data set

10 configuration
data set

16 configuration
data set

Figure SCU (Sensor Control Unit)-99 Startup Control
A startup request occurs for each SEQ_ID under any of the following conditions.


A certain cycle by the timer

A certain cycle by the timer after receiving an external interrupt as the trigger

One operation using an external interrupt as the trigger

One operation using the register writing operation as the trigger, which is from the CPU
The startup intervals by the timer can be selected using the frequency division value of the Pre Divider that

determines the startup maximum frequency.
The operating frequency of each sequencer can be selected by the frequency of the 2nd power of the frequency
divided by the Pre Divider.
When the sequencer is started up by the startup request, the process is branched into each physical interface
shown below according to the setting value that is set on the SCU_RAM and hands over the external bus
transaction process.


SPI



I2C0



I2C1
When either LPADC or HPADC is selected as the physical interface, it does not branch into the external bus

transaction generation process, and the sequencer control program moves to external data capture process.

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3.9.9.2 External Bus Transaction Generation
SPI MasterI2C Master 0

I2C Master 1

LPADC

HPADC0HPADC1SEQUENCER
10 instruction groupassertion of
Trigger SingalorInterrupt
signalGenerate signal
about request
for Startup

3 instruction grouprequestConfiguration
to sequencer

completion
noticeConfiguration
Data

SCU_REG

Read
SensorData

Data
formattingandControl
FIFO

MATH_PROCSCU_FIFO

Configuration
Data

Data formatting

Writing to FIFO
Setting

10 configuration
data set

10 configuration
data set

16 configuration
data set

Figure SCU (Sensor Control Unit)-100 External Bus Transaction Generation
At the External Bus Transaction Generation process, the bus transaction can be controlled for each physicalinterface according to the setting value written on the SCU_RAM.
The SPI and I2C (I2C0, I2C1) access sequencers can be issued by combining the below sequence commands.


TX_RX command・In the case of SPI, the selected data is output from the MOSI terminal and up to 8 Bytes of data aresimultaneously captured from the MISO terminal.
・In the case of IC2, the selected data is either output to the I2C bus, or up to 8 Bytes of data are captured
from the I2C bus. The slave address (and R/W selected) is also output as data handled by the TX_RX
command.
・In the case of continuous transfers, the TX_RX command can be executed continuously for multiple times.
You can freely select whether to turn OFF the CS in the case of SPI, or send a Stop Condition in the case of
I2C.

WAIT command
・Waits for the specified time
These commands are interpreted by the internal sequencer, converted to the APB access processing of the SPI

or I2C, to perform the actual data transfer processing.

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3.9.9.3 External Data Capture
SPI MasterI2C Master 0

I2C Master 1

LPADC

HPADC0HPADC1SEQUENCER
10 instruction groupassertion of
Trigger SingalorInterrupt
signalGenerate signal
about request
for Startup

3 instruction grouprequestConfiguration
to sequencer

completion
noticeConfiguration
Data

SCU_REGData
formattingandControl
FIFO

Read
Sensor
Data

MATH_PROCSCU_FIFO

Configuration
Data

Data formatting

Writing to FIFO
Setting

10 configuration
data set

10 configuration
data set

16 configuration
data set

Figure SCU (Sensor Control Unit)-101 External Data Capture
At the External Data Capture processing, the data from each sensor connected to each physical interface isreadout, and the data is written to the FIFO via the MATH_PROC processing, or directly from the sensor to the
FIFO.
Regardless of writing the data via the MATH_PROC or directly from the sensor to the FIFO, the data type must
be one of the following “Calculation Operable Sample Types” or “Calculation Inoperable Sample Types”. Other
data types cannot be handled.
Also, when the data is written via the MATH_PROC processing, the data type of the sensor readout data (the data
handed to the MATH_PROC) must be the Calculation Operable Sample Type.


Calculation Operable Sample Types
・16-bit 1 axis: 1 Sample = {x} format(2 Byte/Sample)

・16-bit 2 axis: 1 Sample = {x,y} format(4 Byte/Sample)

・16-bit 3 axis: 1 Sample = {x,y,z} format (6 Byte/Sample)


Calculation Inoperable Sample Types
・24-bit: 1 Sample format(3 Byte/Sample)

・32-bit: 1 Sample format(4 Byte/Sample)

・48-bit: 1Ssample format(6 Byte/Sample)

・64-bit: 1 Sample format(8 Byte/Sample)

・96-bit: 1 Sample format(12 Byte/Sample)

・128-bit: 1 Sample format(16 Byte/Sample)

From the SPI/I2C sensors, up to 16 Bytes of data can be readout in one process.
Data readout from the LPADC is treated as MSB-aligned 16 bit data.
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selected, the data is treated as 16 bit 2 axis data. When non-vector mode is selected, the data is treated as
MSB-aligned 16 bit data for each channel. In the case of vector mode, the data readout from HPADC0 is allocatedto the LSB side ({x}) and the data readout from HPADC1 is allocated to the MSB side ({y}).
You can select whether or not to apply the MATH_PROC processing by the MATH_PROC setting.
Figure SCU (Sensor Control Unit)-102 shows the flow of the sensor data when capturing the external data.

SPI/I2C Read Out Buffer
0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15
LastlyRead
DataFirstlyRead
Data

Calculation Operable Sample Type
XH

XL

YH

X

YL
Y

LSB MSB

MSB

ZH

ZL
Z

LSB

LSB

MATH_PROC

Calculation Operable Sample Type
XH

XL

YH

X
MSB

YL

ZH

Y
LSB MSB

ZL
Z

LSB

LSB

FIFO

Figure SCU (Sensor Control Unit)-102 Sensor Data Flow when Capturing External Data
When the data captured by the SPI, I2C, LPADC, or HPADC is sent through the MATH_PROC, take out amaximum of 6 Bytes of continuous data from the selected capture start position, then perform Byte Swap and left
shift in units of 2 Bytes (see Section 3.9.12.11.6), and perform the data normalization processing. Figure SCU(Sensor Control Unit)-103 shows an example of data normalization of transferring data 2 Bytes at a time from a
12 bit data sensor.

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input data format(ex.12bit)
EndianStuffing

data[0][11:4]MSB justified[3:0]

LSB MSBMSB[3:0]

MSB justified

MSB

MSB

LSB

MSB

LSB MSB

LSB MSB[11:4]

LSB[11:4]
LSB

MSB

LSB

MSB

LSB MSB

LSB

MSB

LSB

[3:0]
LSB MSB[11:4]LSB[3:0]
LSB MSB[11:4]

[7:0]

[3:0]
LSB MSBMSB[3:0]
LSB MSB[11:8]
MSB[11:4]
LSB[7:0][11:8]
LSB[11:8][7:0]

LSB justified[3:0]
LSB MSB

MSB[11:4]LSB MSB

MSB

LittleLSB[7:0][11:8]LSB justified[11:4]LSB MSB

MSB

Big

MATH_WRITE_BYTE_SWAPT:0

data[1]LSB[3:0]
LSB MSB

LSB

MATH_WRITE_BYTE_SWAPT:1
MATH_WRITE_SHIFT_SIZE:4

Figure SCU (Sensor Control Unit)-103 Data Normalization (Example)
When the data is not passed through the MATH_PROC, the offset and writing length can be selected for a
maximum of 16 Bytes of data that was captured by the SPI, I2C, LPADC, or HPADC.
The data ultimately written to the FIFO, when not passed through the MATH_PROC, is written in the readout
order from the sensor.
When passed through the MATH_PROC, you can select from 16 bits or 8 bits for each element (bits per axis).
(OUTPUT_8BIT of Section 3.9.12.11.11.)
When 16 bits is selected for each element, writing is performed in the X,Y,Z order from the LSB side byte.
When 8 bits is selected for each element, the MSB side 8 bits of each X,Y, and Z are written in X,Y,Z order.
Figure SCU (Sensor Control Unit)-104 shows how the data is ultimately stacked in the FIFO.

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Calculation Inoperable Sample Type01Firstly
Read
Data

2

3

4

5

Calculation Operable Sample Type
XL

XH

7

6

8

9

10

11

13

12

14

MSB

15

Z

Y
LSB MSB

ZL

ZH

YL

YH

X

LSB

LSB

Lastly
Read
Data
FIFO

FIFO

15
14
13
12

SCU_RAM
SEQ_OUT_FORMAT11

OUTPUT_8BIT:1

OUTPUT_8BIT:0

ZH

ZH

YH

ZL

XH

YH
YL

10

XH

9

XL

8
8bit x n

7

8bit x 2 x n

6
5
4
3
2
1
0

Max 16Bytein the read orderFigure SCU (Sensor Control Unit)-104 Data Stacked in the FIFO (Image)

3.9.9.4 Connectable Sequencers
3.9.9.4.1

I2C

The I2C0 and I2C1 can be connected to any sequencer from SEQ0 to SEQ9.
See Section 3.9.9.8 for the data flow.
The I2C execution command must be set beforehand in the parameter SEQ_INSTRUCTION_n (n is the
instruction number, n = 0, ..., 127) within the SCU_RAM. At each sequencer, set this instruction number in theparameter SEQ_PROPERTY_n.INST_OFST (n is the sequencer number, n = 0, ..., 9) within the SCU_RAM.
For the I2C macro, set the fastest baud rate calculated from the frequency of the SCU clock, and when readingout 6 Bytes from the 3 axis sensor, use the total of approximately 2,200 clock cycles for the I2C transfer. Also,－343/1293－

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when intentionally inserting a STOP command, an overhead of approximately 570 cycles (when RCOSC is 8.192
MHz) occurs due to resending the slave address.

3.9.9.4.2

SPI

The SPI can be connected to the any sequencer from SEQ0 to SEQ9.
For the data flow, refer to Section 3.9.9.8.
The execution command must be set beforehand in the parameter SEQ_INSTRUCTION_n (n is the instruction
number, n = 0, ..., 127) within the SCU_RAM. At each sequencer, set this instruction number in the parameter
SEQ_PROPERTY_n.INST_OFST (n is the sequencer number, n = 0, ..., 9) within the SCU_RAM.

3.9.9.4.3

ADC

When reading out data from the ADC, the resources of the sequencers are not used. However, the sequencers
using the same FIFO numbers cannot be used, because the FIFO connected to the sequencers are occupied when
the readout data is written. However, One-shot Operation using the sequencer number assigned for ADC readout
is possible.
The LPADC can connect to the following FIFOs.


D0_W0_S



D1_W0_Sfrom N0_W_S to N7_W_S

The LPADC can also connect to the following FIFOs via the MATH_PROC.


D0_W1_S



D0_W2_S



D0_W3_S

D1_W1_S

D1_W2_S

D1_W3_SThe HPADC can connect to the following FIFOs.
from N0_W_S to N7_W_S

For the ADC data flow, refer to the Chapter on ADC (3.21).

3.9.9.5 One-shot Sequence
A total of three channels of One-shot Sequencer is equipped.
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operation of writing the transfer data to the SEQ_RAM_OUT_n_READ_DATA_m (n is the One-shot Sequencer
number n = 0, …, 2, m is the Byte offset of the data readout m = 0, …, 3, refer to Table SCU (Sensor Control
Unit)-726) within the SCU_RAM is called “One-shot Operation” and the block that executes this is called the“One-shot Sequencer”. The One-shot Sequencer can only be selected on the SPI or I2C.
The data cannot be passed through the MATH_PROC in One-shot Operation.
Since the One-shot Operation does not use the Write FIFO, the ADC can be assigned to the same sequencer
number and used at the same time.
The execution command must be set beforehand in the parameter SEQ_INSTRUCTION_n (n is the instruction
number, n = 0, ..., 127) within the SCU_RAM. After this, set the SEQ_MODEn (n = 0, …, 9) to “2” or “3”, then
set the START_INTERVALn (n = 0, …, 9) to 0xA, and finally, write “1” to the sequencer number bit that
corresponds to the SINGLE_EXE register. This will start the operation. When One-shot Operation is completed,
an iSoP0/1/2 interrupt is notified in accordance with the writing region of the SCU_RAM.

3.9.9.6 Sequencer Settings
The following table shows each resource with its registers and SCU_RAM parameters. For the power suppliesof the overall SCU and control of clocks, make the appropriate settings separately.
Table SCU (Sensor Control Unit)-140 Parameters of Sequencer Resources
Sub-resources

Item

Parameter

Descriptions

Sequencer

SCU_REGSTART_CTRL_COMMON

Section 3.9.12.3.5

START_MODE*

Section 3.9.12.3.6 and 3.9.12.3.7

START_INTERVAL*

Section 3.9.12.3.8, 3.9.12.3.9, and 3.9.12.3.10

START_PHASE*

Section

3.9.12.3.11,

3.9.12.3.12,

3.9.12.3.14, and 3.9.12.3.15
SEQ_ENABLE_ALL

Section 3.9.12.3.3

HPADC0_ACCESS_INHIBIT_REQ

address 0x00195024 bit[4]HPADC1_ACCESS_INHIBIT_REQ

address 0x00195024 bit[5]LPADC_ACCESS_INHIBIT_REQ

address 0x00195024 bit[3]Section

TOPREGSCU_RAM

MATH_PROCSCU_REG

3.9.12.3.4

TOP_SCU_RAMMODE_STAT

address 0x0214

SCU_CKEN

address 0x071C

SEQ_SRC_SEL.*

Section 3.9.12.11.4

SEQ_PROPERTY.*

Section 3.9.12.11.5

SEQ_OUT_FORMAT.*

Section 3.9.12.11.6

SEQ_RAM_OUT*

Section 3.9.12.11.13

OFST_GAIN_EN

Section 3.9.12.3.20－345/1293－

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FIFO

ADC

UNSIGNED_TO_SIGNED

Section 3.9.12.3.21

DEC_CLR

Section 3.9.12.3.22

MATHFUNC_CLR

Section 3.9.12.3.23

DECIMATION_PARAM*

Section 3.9.12.3.25 and 3.9.12.3.26

MATHFUNC_SEL

Section 3.9.12.3.27

MATHFUNC_POS*

Section 3.9.12.3.28, 3.9.12.3.29, and 3.9.12.3.30

MATHFUNC_PARAM_*

Section 3.9.12.3.31 to 3.9.12.3.96

EVENT_PARAM0_THRESH

Section 3.9.12.3.97

EVENT_PARAM0_COUNT*

Section 3.9.12.3.98, 3.9.12.3.99, and 3.9.12.3.100

EVENT_PARAM1_THRESH

Section 3.9.12.3.101

EVENT_PARAM1_COUNT*

Section 3.9.12.3.102, 3.9.12.3.103, and 3.9.12.3.104

EVENT_PARAM2_THRESH

Section 3.9.12.3.105

EVENT_PARAM2_COUNT*

Section 3.9.12.3.106, 3.9.12.3.107, and 3.9.12.3.108

SCU_RAM

SEQ_MATH_PROC_OFST_GAIN

Section 3.9.12.11.7

SCU_RAM

FIFO_WRITE_EVENT_CTRL.*

Section 3.9.12.11.11

FIFO_SRAM_POWER_CTRL.*

Section 3.9.12.11.12

ADC_PROPERTY.*

Section 3.9.12.11.9

HPADC0_ENABLE

Section 3.9.12.11.9

HPADC1_ENABLE

Section3.9.12.11.9

LPADC_ENABLE

Section 3.9.12.11.9

ADC_MATH_PROC_OFST_GAIN.*

Section 3.9.12.11.10

SCU_RAM

Table SCU (Sensor Control Unit)-141 Parameters of ADC Resources
Sub-resource

Item

Parameter

Descriptions

LPADC

ADCIF_REG

LPADC_A*

Refer to the Chapter on ADC (3.21).

LPADC_D*
HPADC

ADCIF_REG

HPADC0_A*
HPADC0_D*
HPADC1_A*
HPADC1_D*

Table SCU (Sensor Control Unit)-142 Parameters of FIFO Resources
Sub-resource

Item

Parameter

Descriptions

FIFO

FIFO_REG

D0_W0_S_CTRL*

Section 3.9.12.10.1 and 3.9.12.10.2

D0_W1_S_CTRL*

Section 3.9.12.10.6 and 3.9.12.10.7

D0_W2_S_CTRL*

Section 3.9.12.10.11 and 3.9.12.10.12

D0_W3_S_CTRL*

Section 3.9.12.10.16 and 3.9.12.10.17

D1_W0_S_CTRL*

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D1_W1_S_CTRL*

Section 3.9.12.10.26 and 3.9.12.10.27

D1_W2_S_CTRL*

Section 3.9.12.10.31, and 3.9.12.10.32

D1_W3_S_CTRL*

Section 3.9.12.10.36 and 3.9.12.10.37

N0_W_S_CTRL*

Section 3.9.12.10.41 and 3.9.12.10.42

N1_W_S_CTRL*

Section 3.9.12.10.46 and 3.9.12.10.47

N2_W_S_CTRL*

Section 3.9.12.10.51 and 3.9.12.10.52

N3_W_S_CTRL*

Section 3.9.12.10.56 and 3.9.12.10.57

N4_W_S_CTRL*

Section 3.9.12.10.61 and 3.9.12.10.62

N5_W_S_CTRL*

Section 3.9.12.10.66 and 3.9.12.10.67

N6_W_S_CTRL*

Section 3.9.12.10.71 and 3.9.12.10.72

N7_W_S_CTRL*

Section 3.9.12.10.76 and 3.9.12.10.77

V0_W_C_CTRL*

Section 3.9.12.10.81 and 3.9.12.10.82

V1_W_C_CTRL*

Section 3.9.12.10.88 and 3.9.12.10.89

V2_W_C_CTRL*

Section 3.9.12.10.95 and 3.9.12.10.96

V3_W_C_CTRL*

Section 3.9.12.10.102 and 3.9.12.10.103

V4_W_C_CTRL*

Section 3.9.12.10.109 and 3.9.12.10.110

V5_W_C_CTRL*

Section 3.9.12.10.116 and 3.9.12.10.117

V6_W_C_CTRL*

Section 3.9.12.10.123 and 3.9.12.10.124

V7_W_C_CTRL*

Section 3.9.12.10.130 and 3.9.12.10.131

V8_W_C_CTRL*

Section 3.9.12.10.137 and 3.9.12.10.138

V9_W_C_CTRL*

Section 3.9.12.10.144 and 3.9.12.10.145

V0_W_C_TIMESTAMP_SET*

Section 3.9.12.10.86 and 3.9.12.10.87

V1_W_C_TIMESTAMP_SET*

Section 3.9.12.10.93 and 3.9.12.10.94

V2_W_C_TIMESTAMP_SET*

Section 3.9.12.10.100 and 3.9.12.10.101

V3_W_C_TIMESTAMP_SET*

Section 3.9.12.10.107 and 3.9.12.10.108

V4_W_C_TIMESTAMP_SET*

Section 3.9.12.10.114 and 3.9.12.10.115

V5_W_C_TIMESTAMP_SET*

Section 3.9.12.10.121 and 3.9.12.10.122

V6_W_C_TIMESTAMP_SET*

Section 3.9.12.10.128 and 3.9.12.10.129

V7_W_C_TIMESTAMP_SET*

Section 3.9.12.10.135 and 3.9.12.10.136

V8_W_C_TIMESTAMP_SET*

Section 3.9.12.10.142 and 3.9.12.10.143

V9_W_C_TIMESTAMP_SET*

Section 3.9.12.10.149 and 3.9.12.10.150

V0_W_C_STATUS

Section 3.9.12.10.83

V1_W_C_STATUS

Section 3.9.12.10.90

V2_W_C_STATUS

Section 3.9.12.10.97

V3_W_C_STATUS

Section 3.9.12.10.104

V4_W_C_STATUS

Section 3.9.12.10.111

V5_W_C_STATUS

Section 3.9.12.10.118

V6_W_C_STATUS

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SCU_REG

V7_W_C_STATUS

Section 3.9.12.10.132

V8_W_C_STATUS

Section 3.9.12.10.139

V9_W_C_STATUS

Section 3.9.12.10.146

D0_R1_C_ALMOST_FULL

Section 3.9.12.3.125

D0_R2_C_ALMOST_FULL
D1_R1_C_ALMOST_FULL
D1_R2_C_ALMOST_FULL
N0_R1_C_ALMOST_FULL
N1_R1_C_ALMOST_FULL
N2_R1_C_ALMOST_FULL
N3_R1_C_ALMOST_FULL
N4_R1_C_ALMOST_FULL
N5_R1_C_ALMOST_FULL
N6_R1_C_ALMOST_FULL
N7_R1_C_ALMOST_FULL
D0_R3_CH_ALMOST_FULL
D1_R3_CH_ALMOST_FULL
D0_R1_C_OVER_RUN

Section 3.9.12.3.131

D0_R2_C_OVER_RUN
D1_R1_C_OVER_RUN
D1_R2_C_OVER_RUN
N0_R1_C_OVER_RUN
N1_R1_C_OVER_RUN
N2_R1_C_OVER_RUN
N3_R1_C_OVER_RUN
N4_R1_C_OVER_RUN
N5_R1_C_OVER_RUN
N6_R1_C_OVER_RUN
N7_R1_C_OVER_RUN
D0_R3_CH_OVER_RUN
D1_R3_CH_OVER_RUN
D0_R1_C_UNDER_RUN
D0_R2_C_UNDER_RUN
D1_R1_C_UNDER_RUN
D1_R2_C_UNDER_RUN
N0_R1_C_UNDER_RUN
N1_R1_C_UNDER_RUN
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N3_R1_C_UNDER_RUN
N4_R1_C_UNDER_RUN
N5_R1_C_UNDER_RUN
N6_R1_C_UNDER_RUN
N7_R1_C_UNDER_RUN
D0_R3_CH_UNDER_RUN
D1_R3_CH_UNDER_RUN

Table SCU (Sensor Control Unit)-143 Parameters of I2C Resources
Sub-resource

Item

Parameter

Descriptions

I2C

I2C_REG-----

Refer to the I2C (3.7) Chapter for information including the Parameters.

Table SCU (Sensor Control Unit)-144 Parameters of SPI Resources
Sub-resource

Item

Parameter

DescriptionsSPI

SPI_REG-----

Refer to the SPI (3.10) Chapter for information including the Parameters.

3.9.9.7 Sequencer Priority
The sequencers are executed in the following priority.
SEQ0 (highest) > SEQ1 > SEQ2 > SEQ3 > SEQ4 > SEQ5 > SEQ6 > SEQ7 > SEQ8 > SEQ9 (lowest)
The data capture sequence with higher sampling frequencies must be assigned to sequencers with higher
priority. This is because sequencers with higher sampling frequencies require higher precision for time stamps.
Since an execution flag check is performed for each sequencer number after a task is executed, sequencers withlower priority may be executed earlier depending on the execution order of the task.
Also, when a sequence with higher priority interrupts during periodic execution of a low priority sequencer, thelower priority sequencer is executed in the next main loop, causing a shift in the time stamp.
Also, multiple sequencers are not executed in the main loop at one time, since priority must be given in a uniform
way to other processes such as the ADC.

3.9.9.8 Data Flow
There are 10 channels of sequencers built into the SCU. Each sequencer can be assigned to I2C/SPI transfers.
The following shows the data flow of the sequencers.

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I2C0
I2C1

MATH_PROC

SPI

Sequencer
Processing

FIFO

Figure SCU (Sensor Control Unit)-105 Sequencer Data Flow
Within the main loop, when a task of the I2C is called up for example, the I2C task will be executed as long as
the sequencer number assigned to the I2C task is active.

3.9.9.9 MATH_PROC Processing
The SCU internal sequencer writes data to the MATH_PROC when there is a request from the MATH_PROC.
Then, when the data is output from the MATH_PROC, the processing takes place in accordance with the internalsetting.
The presence of a request is judged by reading out the MATH_PROC_EXE register within the
SCU_MATH_PROC_REG by the internal sequencer.
The requests from the MATH_PROC occur under the following conditions. These are all controlled from thesettings of the CPU.


SEQ0 or SEQ1 (decimation filter is used)
When any of the following conditions are “true”(1) Any of the OFST_GAIN_EN* in the OFST_GAIN_EN{0x5070} of the MATHID within the SCU_REG
is set to ”1”(2) Any from among MATHF_EN0, MAYHF_EN1, and MATHF_EN2 in the MATHFUNC_SEL{0x508c}of the MATHID within the SCU_REG is set(3) Any from among N1, N2, and N3 in the DECIMATION_PARAM0/1{0x5084/0x5088} of the MATHID
within the SCU_REG is set to 9 or lower



SEQ2 to SEQ9 (Normal partition)
When one of the two conditions is “true”(1) Any of the OFST_GAIN_EN* in the OFST_GAIN_EN{0x5070} of the MATHID within the SCU_REG
is set to “1”(2) Any from among MATHF_EN0, MAYHF_EN1, and MATHF_EN2 in the MATHFUNC_SEL{0x508c}of the MATHID setting within the SCU_REG is set
When FIFO writing happens because of the event, the internal sequencer writes to the FIFO with the highest

priority.

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3.9.9.10

Data Duplication Function

By writing the COPY_ID as the copy destination and the COPY_ENALBE to the SCU_FIFO_COPY_INFO_n(n is sequencer number, 0 to 9) within SCU_RAM, the data is duplicated to the specified Write FIFO.
The atomicity of the 3 axis data does not corrupt even when the duplication destination FIFO is dynamicallyswitched during operation of the corresponding sequencer. (part of X, Y, Z is not lost at the duplication
destination)

3.9.9.11

Interrupt Notification

The internal sequencers notify the CPU of interrupts. For details, refer to Table SCU (Sensor Control
Unit)-136.

3.9.9.12

SCU-CPU Synchronous Communication

With some exceptions, the firmware parameters of the SCU internal sequencer and the SCU hardware
parameters can only be re-written when their corresponding functions are not operating. (Refer to Section 3.9.12
for information on which registers can be written or not during operation of functions.) For the parameters within
the SCU_RAM, refer to Section 3.9.12.11.
For the CPU to recognize whether the operation of a sequencer has completely finished or whether theoperation has been suspended during intermittent operations of data capture from sensors, etc., the completion orsuspension of the operation must be notified to the CPU. The SCU-CPU Synchronous Communication Systemnotifies this by use of an interrupt.
The following defines the meanings of “suspension” and “completion” of the operation.
“Operation Completed” refers to cases when either the operation of a sequencer or ADC completes, and thenext operation does not start until a startup request is received from the CPU (Figure SCU (Sensor Control
Unit)-106).

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sequencer completed
one processing
SEQ0
Processing

SEQ

START_CTRL

interrupt

Suspend request

CPU

Figure SCU (Sensor Control Unit)-106 Sequencer Completed“Operation suspended” refers to cases when one sequencer completes the processing of one main loop andwaits for the next startup request (Figure SCU (Sensor Control Unit)-107).
Sequencer suspended

one processing

SEQ

START_CTRL

sequencer
status issuspended

SEQ0
Processing

interrupt

SEQ0
Processing

SEQ0
Processing

interrupt

Figure SCU (Sensor Control Unit)-107 Sequencer Suspended

3.9.9.12.1

Completion Judgement

The following events notify the CPU of the completion of operations.


The ADC has been completed

One of the SEQ0 to SEQ9 has been completed
The CPU requests the completion of operations to each sequencer.

Multiple complete requests are not issued simultaneously, therefore, each judgement of sequencers SEQ0 to SEQ9
is not needed. Judgement conditions to the complete request can be set as “judging whether (OR judgement) oneof the sequencers or ADC processing has been completed”.
In completion judgement, there is no need to judge whether the main loop was operating before. (state－352/1293－

CXD5602 User Manualtransition does not have to be checked). The judgement is “true” if the corresponding sequencer or ADC has been
completed in accordance with the CPU request.

3.9.9.12.2

Suspension Judgement

The following event notifies the suspension of operations.


SEQ0 to 9 has completed one main loop’s worth of processing and the operation has suspended.
This function is for changing settings (mainly the Decimator’s dynamic connection) from the CPU during thesuspension state of the MATH_PROC (when the data that was input to the MATH_PROC is output, and theinternal sequencer is transferred to the FIFO). The following describes an example of changing setting of
MATH_PROC by using this suspension judgement.

CPU can change the configurationof MATH_PROC in this period.

(4)(1) (2) (3)

CPU

SEQ

Processing

Processing

Processing

Process
ing

Processing

MATH_PROCSTART_CTRL(5)(6)

interrupt

interrupt

HPADC0_ACCESS_INHIBIT_REQ
HPADC1_ACCESS_INHIBIT_REQ
SYNCHRO_CPU2iSoP

1

Figure SCU (Sensor Control Unit)-108 MATH_PROC Parameter Change (Example)
In the above Figure, the CPU performs the following controls.
(1) Sets HPADC0_ACCESS_INHIBIT_REQ to “1” (release and inhibition of SCU SLEEP).
(2) Completes the sequencer within the SCU_RAM and sets the suspend request sequencer number(SYNCHRO_CPU2iSoP, refer to Section 3.9.12.11.14.)(3) Sets the HPADC1_ACCESS_INHIBIT_REQ to “1” (suspend interrupt request), clears the interrupt factor,－353/1293－

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disables the IRQ3 interrupt mask, and waits for an interrupt.
(4) Clears the interrupt factor, sets the IRQ3 interrupt mask, and sets HPADC1_ACCESS_INHIBIT_REQ to “0”.
(5) Checks that the error flag (SCU_RAM internal parameter SYNCHRO_iSoP2CPU (refer to Section 3.9.12.11))
is not “1”.
(If the value is “1”, there is an error. Performs readout twice, and after checking, clears to “0”.)(6) Sets HPADC0_ACCESS_INHIBIT_REQ to “0” (SLEEP enable)
The setting changes of MATH_PROC can be made when the MATH_PROC calculation finishes after
controlling the above (1) to (3).
The suspension judgement is performed separately for each sequencer. (If it is decided that OR judgment can bedone at the loop-end in the same way as suspension judgment, for example, when the process of a sequencer otherthan the sequencer of suspension judgement takes time, the suspend notification to the CPU shortens, meaning
there is less time for the CPU to make setting changes.)
Also, suspend interrupt cannot be used in the ADC.

3.9.9.12.3

Interrupt Requests and Notification

By setting the SYNCHRO_CPU2iSoP parameter on the SCU_RAM, the sequencers which issue sequencer
complete/suspend request interrupts can be selected. The interrupt requests are controlled from the
SEQ_ACCESS_INHIBIT_REQ register (refer to Section 3.9.12.3.4) within the SCU_REG.
However, regarding the LPADC_ACCESS_INHIBIT_REQ, the conventional INHIBIT request function(related operations do not function during INHIBIT requests) of the LPADC has been removed from the register.
When you need to use the LPADC not being under the CPU’s control, set LPADC0_ENABLE of the
ADC_PROPERTY parameter within the SCU_RAM to “0”. In the same way, the conventional INHIBIT request
function has been removed from the HPADC0_ACCESS_INHIBIT_REQ and
HPADC1_ACCESS_INHIBIT_REQ registers. When you need to use the HPADC0 not being under the CPU’s
control, set HPADC0_ENABLE of the ADC_PROPERTY parameter within the SCU_RAM to “0” since the ADC
readout from the firmware controlling the sequencer must be suspended.
When you need to use the HPADC1 not being under the CPU’s control, set HPADC1_ENABLE to “0”.
For the control items of HPADC0_ACCESS_INHIBIT_REQ, refer to Section 3.9.9.13.
The firmware of the SCU internal sequencer performs an interrupt notification to the CPU when thecorresponding completion or suspension judgement turns to “true”. It uses an iSoP3 interrupt. (Refer to Section
3.9.6 for details on interrupt numbers from the internal sequencers.)
For the procedure on interrupt notification requests, refer to SYNCHRO_CPU2iSoP (Section 3.9.12.11.14).

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3.9.9.12.4

Error Notification

Error detection is performed when a suspend interrupt request is issued, and an error flag is set to the parameter(SYNCHRO_iSoP2CPU (refer to Section 3.9.12.11)) within the SCU_RAM when an error occurs.
The conditions for error detection are as follows:(1) A suspend interrupt request is not cancelled(2) The MATH_PROC of the sequencer corresponding to the suspend interrupt request has started
When an error is detected, there are cases when the sampled data is not written to the FIFO.
The sequencer complete interrupt requests and suspend interrupt requests from the CPU are performed for eachsource, and the next request is performed after confirming the interrupt from the SCU.
The setting of the MATH_PROC cannot be re-written until the MATH_PROC is executed with the given
settings at least once.

CPU

SEQ

Processing

Processing

Processing

Processing

Processing

Processing

MATH_PROCSTART_CTRL(4) (5)(6)(1) (2)(3)Process
ing
interrupt

interrupt

HPADC0_ACCESS_INHIBIT_REQ
HPADC1_ACCESS_INHIBIT_REQ
1

SYNCHRO_CPU2iSoP
SYNCHRO_iSoP2CPU

Figure SCU (Sensor Control Unit)-109 Error Notification (Example)
The controls of (1) to (6) in the above Figure are the same as Figure SCU (Sensor Control Unit)-108. During
the control of (4), the MATH_PROC started, causing the SYNCHRO_iSoP2CPU to be set to “1”. Note that thetransition of the SYNCHRO_iSoP2CPU from “1” to “0” must be controlled by the CPU. When the sequencer
detects an error, it sets the SYNCHRO_iSoP2CPU to “1”, but does not set it back to “0”.

3.9.9.13

SLEEP

When the internal sequencer has nothing to process, it automatically enters SLEEP. Sequencers in SLEEP will－355/1293－

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WAKEUP when the sequencer conditions are met. It is also possible to inhibit sequencers from entering SLEEP.
The following shows the conditions of SLEEP, WAKEUP, and SLEEP inhibition.
SLEEP Conditions
The internal sequencer enters SLEEP when it satisfies all conditions below.
(1) A sequencer execution request has not been received(2) The FIFO of the ADC in operation is "NOT_EMPTY" (Readout entirely)(3) A suspend interrupt or complete interrupt request is not in progress
WAKEUP Conditions
The internal sequencer Wakes up when it satisfies the condition below.
(1) An interrupt raised from the VIC
When you need to Wake up a sequencer from the outside of the SCU, set the HPADC0_ACCESS_INHIBIT_REQ(refer to Section 3.9.12.3.4) register to “1”. Note that the sequencer will not automatically enter SLEEP unless you
set the HPADC0_ACCESS_INHIBIT_REQ register back to “0”.
SLEEP Inhibition
SLEEP can be inhibited by setting the HPADC0_ACCESS_INHIBIT_REQ register within the SCU_REG to“1”.

3.9.9.14

Manual Mode

The SCU assumes the reduction of CPU load using the sequencers, but you can also choose not to use
sequencers. In such case, the CPU will set all (accessible) control registers as appropriate to realize each function(Manual Mode).
When controlling the SCU in Manual Mode, do not change the reset (XRST_SCU_ISOP) setting of the internalsequencer setting from “1'b0”.
For the FIFO within the SCU, use the virtual sensor partition.

3.9.10DMA

The DMA handshake signal is synchronized at the DMA_SEL block within the SCU.
There are 26 sets of signal lines, each which comprises two lines of output from the SCU and one line of input tothe SCU.
The destination DMAC is placed outside the SCU, to which all 26 sets of signals are connected.
Figure SCU (Sensor Control Unit)-110 shows the connection of the DMA handshake signals.

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Figure SCU (Sensor Control Unit)-110 DMA Handshake Signal Connections
Table SCU (Sensor Control Unit)-145 shows the relation between the DMA request factors within the SCU andthe 26 sets of handshake signals.
Table SCU (Sensor Control Unit)-145 DMA Handshake Signals and Connection Destination DMAC ch IDs
DMA Request Factor

Connection

DMA Request Factor

Connection

Destination

Destination

DMAC ch ID

DMAC ch ID

SPI (M) Tx

ch0

FIFO Rx (D0_R1_C)

ch12

SPI (M) Rx

ch1

FIFO Rx (D0_R2_C)

ch13

I2C0 (M) Tx

ch2

FIFO Rx (D0_R3_CH)

ch14

I2C0 (M) Rx

ch3

FIFO Rx (D1_R1_C)

ch15

I2C1 (M) Tx

ch4

FIFO Rx (D1_R2_C)

ch16

I2C1 (M) Rx

ch5

FIFO Rx (D1_R3_CH)

ch17

LPADC (Ch.0)

ch6

FIFO Rx (N0_R1_C)

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LPADC (Ch.1)

ch7

FIFO Rx (N1_R1_C)

ch19

LPADC (Ch.2)

ch8

FIFO Rx (N2_R1_C)

ch20

LPADC (Ch.3)

ch9

FIFO Rx (N3_R1_C)

ch21

HPADC (Ch.0)

ch10

FIFO Rx (N4_R1_C)

ch22

HPADC (Ch.1)

ch11

FIFO Rx (N5_R1_C)

ch23

FIFO Rx (N6_R1_C)

ch24

FIFO Rx (N7_R1_C)

ch25

3.9.11
3.9.11.1

PWM
PWM Overview

The PWM repeats the output of High/Low at the specified cycle and the specified duty.
There are eight channels of the PWM, each which has the following functions.


Operating Frequency, Number of Channels
・Operates (when prescaler is 1/1) by the SCU clock (max. 13 MHz), total of eight channels equipped
・Up to four external output terminals (selected from internal PWM 8ch or combined for output)
・Each channel equips a prescaler (1/1 to 1/256)
・The PWM has a 15 bit resolution (1/32768 to 32767/32768), the cycle and output H width are freely
selectable within this range

Function for synchronization with ADC
・The PWM can be output using the data fix signal of any ADC channel as a reference
・ADC data can be captured after a specified duration from the rising edge of the PWM output

Synchronization function between PWM channels
・The PWM output can be synchronized between arbitrary PWM channels (including phase adjustment)Combining function of external output signals
・Multiple channels can be arbitrarily selected and combined by OR or AND for each output terminal (total
of 4)



Timer function
・Can be used as a general-purpose timer when not used as a PWM, allowing readout of count values
・Can output interrupts to both the SCU internal sequencer and upper CPUs
・Interrupt is reflected in "INT_ENABLE_ERR_0"

3.9.11.2

PWM Control

The basic settings for the PWM channels n (n = 0, ..., 7) are made using the following registers.
Also refer to information after Section 3.9.12.3.154.

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PWMn_PARAM register

PWMn_CYCLE field… sets the cycle

PWMn_PARAM register

PWMn_THRESH field… sets the duty (L width)

PWMn_EN register

PWMn_EN field… selects the permission of operation

PWMn_EN registerPWM_SELLn field[2:0]… selects the ADC channel used as thereference

PWMn_EN registerPWM_SELLn field[5:3]… selects the PWM used as the reference

PWMn_UPDATE register

PWMn_UPDATE field… reflects the setting update*

PWM_PASEn register

PWM_DELAYn field… selects the number of clocks for phaseadjustment
PWM_PASExx register

PWM_CNTENn field[15:8] … sets the capture start position (from 3 to255)


PWM_PASExx register

PWM_CNTENn field[7:4]… sets the number of captures (from 1 to

PWM_CNTENn field[3:0]… sets the frequency division of the

PWM_SEL_DISm field… selects the PWM channels used for

PWM_SEL_INVm field… selects whether or not to invert the PWM

PWM_SELm field… “0” selects AND combining/“1” selects

15)


PWM_PASEn registerprescaler

PWM_FUCN2 register
combining

PWM_FUNCSEL0 registerpolarity

PWM_FUNC4 register
OR combining

Note: The PWMn_UPDATE must be written in any of the following cases.
When the PWM_CYCLE value is changedTo synchronize with other PWMs



To synchronize with the ADC
The following table shows the maximum and minimum setting range of the output for representative clock

settings.

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Table SCU (Sensor Control Unit)-146 PWM Maximum and Minimum Setting Range
SCU Frequency

Prescaler Setting

Output Variable Range (Setting Example)(representative

Maximum

example)(Duty 50%)

13 MHz8.192 MHz32.768 kHz

3.9.11.2.1

Frequency

Longest Cycle

Pulse Width Accuracy

1/1

6.5 MHz (154 ns)

396.7 Hz (2.521 ms)

76.9 ns/step

1/128

50.7 kHz (19692 ns)

3.099 Hz (322.6 ms)

9846 ns/step

1/1

4.096 MHz (244 ns)

250 Hz (4 ms)

122 ns/step

1/128

32 kHz (31250 ns)

1.953 Hz (512 ms)

15625 ns/step

1/1

16.384 kHz (61 μs)

1 Hz (1 s)

30.5 μs/step

1/128

128 Hz (7812.5 μs)

0.0078 Hz (128 s)

3906.25 μs/step

PWM Cycle Calculation Formula

PWM cycle = UPWM_CYCLE/(SCU_CLK >> PWM_CNTENn)
When prescaler is set to 1/1 (PWM_CNTENn == 0)
UPWM_CYCLE = PWMn_CYCLE + 1
Restriction: PWMn_CYCLE > 0
When prescaler is set to 1/2 or higher (PWM_CNTENn >= 1)
UPWM_CYCLE = PWMn_CYCLE
Restriction: PWMn_CYCLE > 1

3.9.11.2.2

PWM Output Duty (High time/cycle) Calculation Formula

DUTY=1-(UPWM_THRESH/(UPWM_CYCLE))
When prescaler is set to 1/1 (PWM_CNTENn == 0)
UPWM_CYCLE = PWMn_CYCLE + 1
UPWM_THRESH = PWMn_THRESH
Restriction: PWMn_CYCLE>0, PWMn_CYCLE ≥ PWMn_THRESH
When prescaler is set to 1/2 or higher (PWM_CNTENn >= 1)
UPWM_CYCLE = PWMn_CYCLE << PWM_CNTENn
UPWM_THRESH = (PWMn_THRESH << PWM_CNTENn) -1
Restriction: PWMn_CYCLE > 1, PWMn_THRESH > 1, PWMn_CYCLE ≥ PWMn_THRESH

3.9.11.2.3
Special Settings (Fixed Output)

Setting to make PWM Output fixed status (control by each PWM)
fixed to High Level
PWMn_CYCLE“1” or higher－360/1293－

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Set PWMn_THRESH to “0” and select ENABLE + UPDATE
fixed to Low Level
Set ENABLE to “0”Setting to make PMW Output fixed status (control at PWM combining point)
Paste to H
Set PWM_SEL_INVn to “0x1” and PWM_SEL_DISn to “0x1”Paste to L
Set PWM_SEL_INVn to “0x0” and PWM_SEL_DISn to “0x1”

3.9.11.3

Function for Synchronization with ADC (PWM to ADC)

This mode performs output of the PWM using the valid signal for the ADC output (synchronization signal)
from the ADC (LPADC/HPADC) as a reference. The following is an overview.

Start Phase is adjusted when the 1st AD_EN
rising after updating register setting
AD_EN

Internal
TriangularsignalPWM startphase iscontrollable

PWM output
PWM period iscontrollable
A/D Sampling
TimingFigure SCU (Sensor Control Unit)-111 PWM Output Mode using ADC Timing as a Reference
When setting the PWM channel n (n = 0, ..., 7), set the following registers in addition to the basic operation
settings.


PWMn_EN registerPWM_SELLn field[2:0] … selects the ADC channel used as the reference
PWM_SELLn field[5:3]･･･fixed to “0”

PWM_PASEn register
PWM_DELAYn field… selects the number of clocks for phase adjustment－361/1293－

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Enable control of this synchronization function is controlled by the PWMn_EN field of the PWMn_EN registerand synchronization operation starts by using the Writing to the PWMn_UPDATE register as a trigger.
The following is an example of the settings.
[1]PWM start setting (first time)
PWM0_PARAM = 0x00070007
PWM_PASE0 = 0x00000001
PWM0_EN = 0x0000000x (selection of ADC synchronization source | 0x1[EN])PWM0_UPDATE = 0x00000001[2]ADC sampling start
Executes ADC sampling of the SensorDriver[3]PWM suspend setting
PWM0_EN = 0x00000000
PWM0_UPDATE = 0x00000001[4]ADC sampling suspension
Suspends by HPADC0_A1 LV_ADC0_EN /HPADC1_A1 LV_ADC1_EN/ LPADC_A0 LV_ADC_EN
Note: The data strobe signal connected to the PWM cannot be controlled by the HPADC0_D2.DECIFIFO_EN/
HPADC1_D2.DECI FIFO_EN/ LPADC_D2 FIFO_EN.
The ADC channels used as the reference can be selected as follows.
Table SCU (Sensor Control Unit)-147 Reference ADC Channel Selection
PWM_SELLn[2:0]

AD Selection

0

Does not synchronize with ADC (free run mode)

1

Synchronizes with HPADC02

Synchronizes with HPADC1

3

Reserved

4, 5, 6, and 7

Synchronizes with LPADC0, LPADC1, LPADC2 and LPADC3

3.9.11.3.1

Phase Difference Calculation Formula

When prescaler is set to 1/1
Phase difference (number of SCU_CLOCK) = PWM_DELAYn + 1
When prescaler is set to 1/2 or higher
Phase difference (number of SCU_CLOCK) = PWM_DELAYn x (2^PWM_CNTENn) - α
Range which α may take
The maximum shift width of the Phase difference shift is determined by the prescaler setting value.
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α maximum value = (2^PWM_CNTENn) - 1(1/2 --> 1[clk], 1/4 --> 3[clk], …, 1/256 --> 255[clk])
Note: This shift occurs randomly and cannot be controlled.

3.9.11.3.2
ADC-PWM Synchronization Settings Procedure (when you do not want tosuspend ADC)
[1]ADC Sampling Start
ADC_EN ON[2]PWM Start Settings (for 2nd time on) PWM0_PARAM = 0x00070007
PWM_PASE0 = 0x00000001(must be 1 or larger)

PWM0_EN = 0x0000000x(Selection of ADC synchronization source | 0x1[EN])PWM0_UPDATE = 0x00000001[3]PWM suspend settings
PWM0_EN = 0x00000000
PWM0_UPDATE = 0x00000001[4]ADC Sampling Start (same as [2])ADC_EN ON[5]PWM Start Settings (from 2nd time on)
PWM_PASE0 = 0x0000ffff
PWM0_PARAM = 0x00070007
PWM0_EN = 0x0000000x (Selection of ADC synchronization source | 0x1[EN])PWM0_UPDATE = 0x00000001
PWM_PASE0 = 0x00000001

3.9.11.4

Function for Synchronization with ADC (ADC to PWM)

Using the rising edge of the PWM output as a reference timing, this mode controls the timing that the ADC datais captured within the SCU.

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PWM output
Data Enable
HPADC output(Channel 0)
HPADC output(Channel 1)
Capture timing iscontrollable

FIFO Write
Timing

The number of
capture data is
controllable

Figure SCU (Sensor Control Unit)-112 ADC Data Capture Mode using the PWM Output Timing as a Reference
When setting the PWM channel n (n = 0, ..., 7), set the following registers in addition to the basic operation
settings.


PWM_PASExx register
PWM_CNTENn field[15:8] … sets the capture start position (3 to 255)

PWM_PASExx register
PWM_CNTENn field[7:4]… sets the number of captures (1 to 15)


PWMn_EN registerPWM_SELLn field [2:0] … selects the ADC channel used as the reference
PWM_SELLn field [5:3]･･･fixed to “0”Enable control of this synchronization function is controlled by the PWMn_EN field of the PWMn_EN registerand synchronization operation starts by using the Writing to the PWMn_UPDATE register as a trigger.
The following is an example of the basic settings.
[1]Setting of the PWM to which data capture timing of the ADC is synchronized
HPADC0_D1 DECI_RATIO2 /HPADC1_D1 DECI_RATIO2/LPADC_D0
DECI_RATIO2/LPADC_D1 DECI_RATIO2/LPADC_D2 DECI_RATIO2/LPADC_D3 DECI_RATIO2[2] Setting the number of data captured by the ADC
PWM_PASExx PWM_CNTENn [15:8] and [7:4] must not be “0”[3]The Synchronization ADC is set
PWMn_EN PWM_SELLn

Synchronization ADC channel setting[4]The PWM starts
PWMxx_EN/PWMcxx_UPDATE is executed
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the ADC side.
Table SCU (Sensor Control Unit)-148 ADC Channels and PWM Assignment
Register Name

Field Name

Target ADC

LPADC_D1[20:12]

DECI _RATIO2LPADC0

LPADC_D4[20:12]

DECI _RATIO2LPADC1LPADC_D5[20:12]

DECI _RATIO2LPADC2LPADC_D6[20:12]

DECI _RATIO2LPADC3

HPADC_D0_D1[20:12]

DECI _RATIO2

HPADC0HPADC_D1_D1[20:12]

DECI _RATIO2

HPADC1The synchronization function becomes valid when bit 8 of each register’s DECI _RATIO2 is set to “1”. The
PWM channel of each synchronization target is selected by bit0 to 7, and by setting each one to “1”, thesynchronization signals PWM0 to 7 become valid.

3.9.11.5

Synchronization Function between PWM Channels

This mode synchronizes the timing between any PWM channels. It is also possible to operate multiple PWMs
in a chain sequence. When setting the PWM channel n (n = 0, ..., 7), set the following registers in addition to thebasic operation settings.


PWMn_EN registerPWM_SELLn field [5:3] … sets channel (m) of the PWM you want to synchronize

PWM_PASEn register
PWM_DELAYn field… selects the number of clocks for phase adjustment

After making the settings, perform the additional setting on the PWM channel m which you want tosynchronize. That is to say, write “1” on the PWMm_UPDATE field of the PWMm_EN register. By thisadditional setting, the PWM channel n synchronizes with the PWM channel m. The following is an example
setting of synchronizing channel 0 with channel 1.
<Example of Procedures>[1] Ch0 set
PWM0_PARAM= 0x00070007

PWM_PASE0= 0x00000001

PWM0_EN= 0x00000011

PWM0_UPDATE = 0x00000001[2]Ch1 set
PWM1_PARAM= 0x00040007

PWM_PASE1= 0x00000000

PWM1_EN= 0x00000001

PWM1_UPDATE = 0x00000001 (Ch1＆Ch0 output start)－365/1293－

CXD5602 User Manual[3] Ch0 suspend
PWM0_EN= 0x00000010

PWM0_UPDATE = 0x00000001[4] Ch1 suspend
PWM1_EN= 0x00000000

PWM1_UPDATE = 0x00000001[5] Ch0 suspend and then process
PWM_PASE0[15:0] ＝ 0xffff[6] PWM another setting (if you want)
The settings for the PWM you want to synchronize can be selected as follows:
Table SCU (Sensor Control Unit)-149 Settings for Synchronization between PWMs
PWM_SE

PWM0

PWM1

PWM2

PWM3

PMW4

PMW5

PWM6

PWM7

No

No

No

No

No

No

No

No

Synchroni

Synchroni

Synchroni

Synchroni

Synchroni

Synchroni

Synchroni

Synchroni

zationzationzationzationzationzationzationzation

1

PWM1

PWM0

PWM0

PWM0

PWM0

PWM0

PWM0

PWM0

2

PWM2

PWM2

PWM1

PWM1

PWM1

PWM1

PWM1

PWM1

3

PWM3

PWM3

PWM3

PWM2

PWM2

PWM2

PWM2

PWM2

4

PWM4

PWM4

PWM4

PWM4

PWM3

PWM3

PWM3

PWM3

5

PWM5

PWM5

PWM5

PWM5

PWM5

PWM4

PWM4

PWM4

6

PWM6

PWM6

PWM6

PWM6

PWM6

PWM6

PWM5

PWM5

7

PWM7

PWM7

PWM7

PWM7

PWM7

PWM7

PWM7

PWM6

LLn[5:3]0

3.9.11.5.1

PWM Output Phase Calculation Formula

When prescaler is set to 1/1
Phase difference (number of SCU_CLOCK) = PWM_DELAYn + 1
When prescaler is set to 1/2 or higher
Phase difference (number of SCU_CLOCK) = PWM_DELAYn x (2^PWM_CNTENn) - α
Range which α may take
The maximum shift width of the Phase difference shift α is determined by the prescaler setting.
α minimum value = 0
α maximum value = (2^PWM_CNTENn) - 1
For the prescaler 1/2 setting, this is 1[clk]. For the prescaler 1/4 setting, it is 3[clk], and then, at the 1/256
setting, it is 255[clk].
Note: This shift occurs randomly and cannot be controlled.

－366/1293－

CXD5602 User Manual

3.9.11.5.2

PWM Output Synchronization Initialization Procedures

Note 1: Do not set PWM_PASEn[15:0] to “0xffff” nor “0x0000”.
Note 2: “0xffff” is a setting for clear, and actual phase setting is not permitted.
[1]PWM suspend setting
PWM0_EN = 0x00000000
PWM0_UPDATE = 0x00000001[2]Phase Setting
PWM_PASEn[15:0] = 0xffff[3]PWM another setting (if you want)

3.9.11.6

External Output Signal Combining Function

By combining the internal PWM signal, the waveform output from the external PWM terminal can be
combined. AND or OR can be used for the combining.
Setting example:
Terminal PWM0ch = PWM0 & PWM1 & PWM2 & PWM3 & PWM4 & PWM5 & PWM6 & PWM7
Terminal PWM1ch = PWM0 | PWM1 | PWM2 | PWM3 | PWM4 | PWM5 | PWM6 | PWM7When setting the output terminal PWMm (m = 0, ..., 3), set the following registers in addition to the basic
operation settings.


PWM_FUCN2 registerPWM_SEL_DISm field… selects the PWM channel used for the combining

PWM_FUNCSEL0 registerPWM_SEL_INVm field … selects whether or not to invert the PWM polarity



PWM_FUNC4 registerPWM_SELm field… “0” selects AND combining/“1” selects OR combining－367/1293－

CXD5602 User Manual

The setting of the PWM channel used for combining can be selected as follows:
Table SCU (Sensor Control Unit)-150 Setting of PWM Channels to be Combined
PWM_SEL_DISm[7:0]

PWM0 Terminal

PWM1 Terminal

PWM2 Terminal

PWM3 Terminal

bit 0

PWM0

PWM1

PWM2

PWM3

bit 1

PWM1

PWM0

PWM0

PWM0

bit 2

PWM2

PWM2

PWM1

PWM1

bit 3

PWM3

PWM3

PWM3

PWM2

bit 4

PWM4

PWM4

PWM4

PWM4

bit 5

PWM5

PWM5

PWM5

PWM5

bit 6

PWM6

PWM6

PWM6

PWM6

bit 7

PWM7

PWM7

PWM7

PWM7

PWM_SEL_INVm[7:0]Regarding the PWM_SEL_DISm, when bit0 is “0”, the corresponding PWM becomes valid, when “1”, thecorresponding PWM becomes invalid.
Regarding bit 1 to bit 7, when they are “1”, the corresponding PWM becomes valid, when “0”, the corresponding
PWM becomes invalid. In either case, the PWM channels that were made invalid are treated as “1” output.
Regarding the PWM_SEL_INVm, the PWM channels corresponding to each bit are inverted by “1”.
When performing OR combining by the PWM_SELm field setting, disable the channels that are not used by
PWM_SEL_DISm and then also make an invert setting for PWM_SEL_INVm (input “0” at the OR combining
stage).
Note that at the reset initial state, these registers are All 0 and the output terminal PWMm (m = 0, ..., 3) is in astate that the internal PWMm can be output without being combined and inverted.

3.9.11.7

PWM_TIMER

Channels that are not used as the PWM function can be used as general-purpose timers. The settings are thesame as PWM.
Also, interrupts can be generated at the timing of each falling edge of the PWM output (PWM cycle).
Note that for the internal sequencer, a total of three signals are generated by ORing arbitrarily selected eightchannels and provided as interrupt signals.
For the upper CPU, each of eight channels of PMW timer interrupt is output via the INT_SEL module. Please also
refer to Section 3.9.6.2.

－368/1293－

CXD5602 User Manual

3.9.12SCU Register Details

3.9.12.1

Address Offset

The following shows 32 bit address offset from the CPU. Add the following address to the offsets in the table tocalculate the address from the CPU.
Offset: 0x00190000 (Mirror: 0x04190000)

3.9.12.2

SCU_REG Internal Memory List
Table SCU (Sensor Control Unit)-151 SCU Internal Memory

OffsetAddressName

Size (bits)

Description

SEQ_IRAM32

Inst Ram Array(Transaction Port)
0x0000 .. 0x3FFC

Internal

Sequencer

Instruction

Ram

Array
0x4000 .. 0x4FFC

3.9.12.3

SEQ_DRAM(SCU_RAM)

32

Internal Sequencer Data Ram Array

SCU_REG Register List

Note: Some offset addresses are listed irregularly. Be careful when you set address by calculating with the SW.
The Reserved regions are secured in the 0x50AC to 0x50AF, and 0x50C0 to 0x50CF offset addresses shown in
the following list.
Table SCU (Sensor Control Unit)-152 SCU Register List
OffsetName

Type

AddressSize

Description

Reset Value

Monitors SCL/SDA/internal status of

0x00000000(bit)(Transaction
Port)
0x5018

I2C0

RO

32

the IP for I2C00x501C

I2C1

RO

32

Monitors SCL/SDA/internal status of

0x00000000

the IP for I2C1
0x5020

SEQ_ENABLE_ALL

RW

32

Permission/prohibition

setting

for

operations of whole sequencers can becollectively controlled
0: operation is prohibited
1: operation is permitted－369/1293－

0x00000000

CXD5602 User Manual

When the bit is “0”, the operation of all
sequencers is suspended.
When the bit is “1”, the operation ofeach sequencer is performed according
to the permission of each sequencer.
0x5024

SEQ_ACCESS_INHIBIT

RW

320x00000000

0x5028START_CTRL_COMMON

RW

320x0000FF00

0x502CSTART_MODE0RW

320x00000000

0x5030START_MODE1

RW

32

0: Operation suspended

0x00000000

1: A certain cycle startup by the timer
2: One startup after the externalinterrupt occurrence
3: A certain cycle startup by the timer
after the external interrupt occurrence
0x5034

START_INTERVAL3_0

RW

32

0x00000000

0x5038START_INTERVAL7_4

RW

32

0x00000000

0x503CSTART_INTERVAL9_8

RW

32

0x00000000

0x5040START_PHASE1_0

RW

32

0x00000000

0x5044

START_PHASE3_2

RW

32

0x00000000

0x5048START_PHASE5_4

RW

32

0x00000000

0x504CSTART_PHASE7_6

RW

32

0x00000000

0x5050START_PHASE9_8

RW

32

0x00000000

0x5054SINGLE_EXE

RW

32

0x00000000

0x5058START_CTRL_STT0

RO

320x00000000

0x505CSTART_CTRL_STT1

RO

32

0x00000000

0x5060DEBUG_CTRL

RW

320x00000000

0x5070

OFST_GAIN_EN

RW

32

0x00000000

0x5074

UNSIGNED_TO_SIGNED

RW

320x00000000

0x5078

DEC_CLR

WO

320x00000000

0x507C

MATHFUNC_CLR

WO

320x00000000

0x5080EVENT_STT

WO

320x00000000

0x5084

DECIMATION_PARAM0RW

320x00000000

0x5088DECIMATION_PARAM1

RW

320x00000000

0x508C

MATHFUNC_SEL

RW

32

0: D0_W0_S
1: D0_W1_S
2: D0_W2_S
3: D0_W3_S
4: D1_W0_S－370/1293－

0x00000000

CXD5602 User Manual

5: D1_W1_S
6: D1_W2_S
7: D1_W3_S
8: N0_W_S
9: N1_W_S
10: N2_W_S
11: N3_W_S
12: N4_W_S
13: N5_W_S
14: N6_W_S
15: N7_W_S
0x5090

MATHFUNC_POS0

RW

32

0x00000000

0x5094

MATHFUNC_POS1

RW

32

0x00000000

0x5098MATHFUNC_POS2

RW

32

0x00000000

0x50A0

MATHFUNC_PARAM_0_0

RW

32

0x00000000

0x50A4

MATHFUNC_PARAM_C0_0_

RW

32

0x00000000

RW

32

0x00000000

0_MSB
0x50A8MATHFUNC_PARAM_C0_0_
0_LSB

0x50AC toReserved

Reserved

0x50AF
0x50B0

MATHFUNC_PARAM_C1_0_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

0_MSB
0x50B4

MATHFUNC_PARAM_C1_0_
0_LSB

0x50B8MATHFUNC_PARAM_C2_0_
0_MSB

0x50BC

MATHFUNC_PARAM_C2_0_
0_LSB

0x50C0 toReserved

Reserved

0x50CF
0x50D0

MATHFUNC_PARAM_C3_0_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

0_MSB
0x50D4

MATHFUNC_PARAM_C3_0_
0_LSB

0x50D8MATHFUNC_PARAM_C4_0_
0_MSB

0x50DC

MATHFUNC_PARAM_C4_0_－371/1293－

CXD5602 User Manual

0_LSB
0x50E0

MATHFUNC_PARAM_0_1

RW

32

0x00000000

0x50E4

MATHFUNC_PARAM_C0_0_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

1_MSB
0x50E8MATHFUNC_PARAM_C0_0_
1_LSB

0x50EC

MATHFUNC_PARAM_C1_0_
1_MSB

0x50F0

MATHFUNC_PARAM_C1_0_
1_LSB

0x50F4

MATHFUNC_PARAM_C2_0_
1_MSB

0x50F8MATHFUNC_PARAM_C2_0_
1_LSB

0x50FC

MATHFUNC_PARAM_C3_0_
1_MSB

0x5100

MATHFUNC_PARAM_C3_0_
1_LSB

0x5104

MATHFUNC_PARAM_C4_0_
1_MSB

0x5108MATHFUNC_PARAM_C4_0_
1_LSB

0x510C

MATHFUNC_PARAM_1_0

RW

32

0x00000000

0x5110

MATHFUNC_PARAM_C0_1_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

0_MSB
0x5114

MATHFUNC_PARAM_C0_1_
0_LSB

0x5118MATHFUNC_PARAM_C1_1_
0_MSB

0x511C

MATHFUNC_PARAM_C1_1_
0_LSB

0x5120

MATHFUNC_PARAM_C2_1_
0_MSB

0x5124

MATHFUNC_PARAM_C2_1_
0_LSB

0x5128MATHFUNC_PARAM_C3_1_
0_MSB

0x512C

MATHFUNC_PARAM_C3_1_－372/1293－

CXD5602 User Manual

0_LSB
0x5130

MATHFUNC_PARAM_C4_1_

RW

32

0x00000000

RW

32

0x00000000

0_MSB
0x5134

MATHFUNC_PARAM_C4_1_
0_LSB

0x5138MATHFUNC_PARAM_1_1

RW

32

0x00000000

0x513C

MATHFUNC_PARAM_C0_1_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

1_MSB
0x5140

MATHFUNC_PARAM_C0_1_
1_LSB

0x5144

MATHFUNC_PARAM_C1_1_
1_MSB

0x5148MATHFUNC_PARAM_C1_1_
1_LSB

0x514C

MATHFUNC_PARAM_C2_1_
1_MSB

0x5150

MATHFUNC_PARAM_C2_1_
1_LSB

0x5154

MATHFUNC_PARAM_C3_1_
1_MSB

0x5158MATHFUNC_PARAM_C3_1_
1_LSB

0x515C

MATHFUNC_PARAM_C4_1_
1_MSB

0x5160

MATHFUNC_PARAM_C4_1_
1_LSB

0x5164

MATHFUNC_PARAM_2_0

RW

32

0x00000000

0x5168MATHFUNC_PARAM_C0_2_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

0_MSB
0x516C

MATHFUNC_PARAM_C0_2_
0_LSB

0x5170

MATHFUNC_PARAM_C1_2_
0_MSB

0x5174

MATHFUNC_PARAM_C1_2_
0_LSB

0x5178MATHFUNC_PARAM_C2_2_
0_MSB

0x517C

MATHFUNC_PARAM_C2_2_－373/1293－

CXD5602 User Manual

0_LSB
0x5180

MATHFUNC_PARAM_C3_2_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

0_MSB
0x5184

MATHFUNC_PARAM_C3_2_
0_LSB

0x5188MATHFUNC_PARAM_C4_2_
0_MSB

0x518C

MATHFUNC_PARAM_C4_2_
0_LSB

0x5190

MATHFUNC_PARAM_2_1

RW

32

0x00000000

0x5194

MATHFUNC_PARAM_C0_2_

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

1_MSB
0x5198MATHFUNC_PARAM_C0_2_
1_LSB

0x519C

MATHFUNC_PARAM_C1_2_
1_MSB

0x51A0

MATHFUNC_PARAM_C1_2_
1_LSB

0x51A4

MATHFUNC_PARAM_C2_2_
1_MSB

0x51A8MATHFUNC_PARAM_C2_2_
1_LSB

0x51AC

MATHFUNC_PARAM_C3_2_
1_MSB

0x51B0

MATHFUNC_PARAM_C3_2_
1_LSB

0x51B4

MATHFUNC_PARAM_C4_2_
1_MSB

0x51B8MATHFUNC_PARAM_C4_2_
1_LSB

0x51BCEVENT_PARAM0_THRESH

RW

320x00000000

0x51C0EVENT_PARAM0_COUNT0RW

320x00000000

0x51C4EVENT_PARAM0_COUNT1RW

320x00000000

0x51C8EVENT_PARAM0_COUNT2RW

320x00000000

0x51CCEVENT_PARAM1_THRESH

RW

320x00000000

0x51D0EVENT_PARAM1_COUNT0RW

320x00000000

0x51D4EVENT_PARAM1_COUNT1RW

320x00000000

0x51D8EVENT_PARAM1_COUNT2RW

320x00000000－374/1293－

CXD5602 User Manual

0x51DCEVENT_PARAM2_THRESH

RW

320x00000000

0x51E0EVENT_PARAM2_COUNT0RW

320x00000000

0x51E4EVENT_PARAM2_COUNT1RW

320x00000000

0x51E8EVENT_PARAM2_COUNT2RW

320x00000000

0x51ECEVENT_PARAM0_DELAY_S

RW

32

0x00000000

RW

32

0x00000000

RW

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RO

32

0x00000000

RW

32

0x00000000

AMPLE
0x51F0EVENT_PARAM1_DELAY_S
AMPLE

0x51F4EVENT_PARAM2_DELAY_S
AMPLE

0x5200EVENT_TIMESTAMP0_R_M
SB

0x5204EVENT_TIMESTAMP0_R_LS
B

0x5208EVENT_TIMESTAMP1_R_M
SB0x520CEVENT_TIMESTAMP1_R_LS
B

0x5210EVENT_TIMESTAMP2_R_M
SB

0x5214EVENT_TIMESTAMP2_R_LS
B

0x5218EVENT_TIMESTAMP0_F_M
SB

0x521CEVENT_TIMESTAMP0_F_LS
B

0x5220EVENT_TIMESTAMP1_F_M
SB0x5224EVENT_TIMESTAMP1_F_LS
B

0x5228EVENT_TIMESTAMP2_F_M
SB0x522CEVENT_TIMESTAMP2_F_LS
B

0x5230

FIFO_WRITE_CTRL

0x5300Reserved

0x5400INT_ENABLE_MAIN

RW

320x00000000

0x5404

INT_DISABLE_MAIN

RW

320x00000000

Reserved－375/1293－

CXD5602 User Manual

0x5408

INT_CLEAR_MAIN

WO

320x00000000

0x540CLEVEL_SEL_MAIN

RW

320x00000000

0x5410

INT_RAW_STT_MAIN

RO

320x00000000

0x5414

INT_MASKED_STT_MAIN

RO

320x00000000

0x5420INT_ENABLE_ERR_0

RW

32

0x00000000

0x5424

INT_DISABLE_ERR_0

RW

32

0x00000000

0x5428

INT_CLEAR_ERR_0

WO

320x00000000

0x542CINT_RAW_STT_ERR_0

RO

320x00000000

0x5430

INT_MASKED_STT_ERR_0

RO

320x00000000

0x5440INT_ENABLE_ERR_1

RW

32

0x00000000

0x5444

INT_DISABLE_ERR_1

RW

32

0x00000000

0x5448

INT_CLEAR_ERR_1

WO

320x00000000

0x544CINT_RAW_STT_ERR_1

RO

32

0x00000000

0x5450

INT_MASKED_STT_ERR_1

RO

32

0x00000000

0x5460INT_ENABLE_ERR_2

RW

32

0x00000000

0x5464

INT_DISABLE_ERR_2

RW

32

0x00000000

0x5468

INT_CLEAR_ERR_2

WO

320x00000000

0x546CINT_RAW_STT_ERR_2

RO

320x00000000

0x5470

INT_MASKED_STT_ERR_2

RO

320x00000000

0x5500

RAM_TEST

RW

320x00000000

0x5510

SCU_POWER

RO

32

Clock status controlled by the SCU

0x00000000

internal sequencer
0: CK_SCU
1: CK_SCU_SPI
2: CK_SCU_I2C0
3: CK_SCU_I2C1
0x5520INT_ENABLE_MAIN_AD

RW

32

0x00000000

0x5524

INT_DISABLE_MAIN_AD

RW

32

0x00000000

0x5528

INT_CLEAR_MAIN_AD

WO

320x00000000

0x552CLEVEL_SEL_MAIN_AD

RW

32

0x00000000

0x5530

INT_RAW_STT_MAIN_AD

RO

32

0x00000000

0x5534

INT_MASKED_STT_MAIN_

RO

320x00000000

RW

32

AD
0x5600PWM0_PARAM

PWM00x00000000

Pulse period/width setting
0x5604

PWM0_EN

RW

32

0x00000000

0x5608

PWM0_UPDATE

RW

320x00000000

0x560C

PWM1_PARAM

RW

32

PWM1

－376/1293－

0x00000000

CXD5602 User Manual

Pulse period/width setting
0x5610

PWM1_EN

RW

32

0x00000000

0x5614

PWM1_UPDATE

RW

320x00000000

0x5618PWM2_PARAM

RW

320x00000000

0x561C

PWM2_EN

RW

32

0x00000000

0x5620PWM2_UPDATE

RW

320x00000000

0x5624

PWM3_PARAM

RW

320x00000000

0x5628PWM3_EN

RW

32

0x00000000

0x562C

PWM3_UPDATE

RW

320x00000000

0x5630PWM_PASE0RW

320x00000000

0x5634

PWM_PASE1

RW

320x00000000

0x5638PWM_PASE2

RW

320x00000000

0x563CPWM_PASE3

RW

320x00000000

0x5640

PWM4_PARM

RW

320x00000000

0x5644PWM4_EN

RW

32

0x00000000

0x5648PWM4_UPDATE

RW

320x00000000

0x564C

PWM5_PARAM

RW

320x00000000

0x5650

PWM5_EN

RW

32

0x00000000

0x5654

PWM5_UPDATE

RW

320x00000000

0x5658

PWM6_PARAM

RW

320x00000000

0x565C

PWM6_EN

RW

32

0x00000000

0x5660

PWM6_UPDATE

RW

320x00000000

0x5664

PWM7_PARAM

RW

320x00000000

0x5668

PWM7_EN

RW

32

0x00000000

0x566C

PWM7_UPDATE

RW

320x00000000

0x5670PWM_PASE4

RW

320x00000000

0x5674

PWM_PASE5RW

320x00000000

0x5678PWM_PASE6

RW

320x00000000

0x567CPWM_PASE7

RW

320x00000000

0x5680PWM_TIMER01

RO

320x00000000

0x5684

PWM_TIMER23RO

320x00000000

0x5688

PWM_TIMER45RO

320x00000000

0x568CPWM_TIMER67RO

320x00000000

0x5690PWM_FUNCSEL0

RW

320x00000000

0x5694

PWM_FUNC1

RW

320x00000000

0x5698PWM_FUCN2

RW

320x00000000

0x569CPWM_FUNC3RW

320x00000000

0x56A0PWM_FUNC4RW

320x00000000－377/1293－

CXD5602 User Manual

0x56A4POWER_EN

3.9.12.3.1

RW

32

0x0000FFFF{0x5018} I2C0 Details
Table SCU (Sensor Control Unit)-153
Register Type: RO (read only)

Local Address: 0x5018

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..13

Reserved

RO

0x00000

Reserved

12..8

FSM

RO

0x00

7..2

Reserved

RO

0x00

1

SDA

RO

0x0

0

SCL

RO

0x0

SCL

FSM

SDA

Reserved

The internal status of the IP for I2C0 can bemonitored.
Reserved
Input status of the signal in the SDA of the IP
for I2C0 can be monitored.
Input status of the signal in the SCL of the IP
for I2C0 can be monitored.

－378/1293－

CXD5602 User Manual

3.9.12.3.2{0x501C} I2C1 Details
Table SCU (Sensor Control Unit)-154
Register Type: RO (read only)

Local Address: 0x501C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..13

Reserved

RO

0x00000

Reserved

12..8

FSM

RO

0x00

7..2

Reserved

RO

0x00

1

SDA

RO

0x0

0

SCL

RO

0x0

SCL

FSM

SDA

Reserved

The internal status of the IP for I2C1 can bemonitored.
Reserved
Input status of the signal in the SDA of the IP
for I2C1 can be monitored.
Input status of the signal in the SCL of the IP
for I2C1can be monitored.

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CXD5602 User Manual

3.9.12.3.3{0x5020} SEQ_ENABLE_ALL Details

Permission/prohibition setting for operations of whole sequencers can be collectively controlled
0: operation is prohibited
1: operation is permitted
When the bit is “0”, the operation of all sequencers is suspended.
When the bit is “1”, the operation of each sequencer is performed according to the permission of each sequence.
Table SCU (Sensor Control Unit)-155
Register Type: RW (read/write)

Local Address: 0x5020

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..2

ReservedRO

Reserved

0x00000000

ENABLE_ALL_SEQ

ENABLE_READY

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Indicates that the sequence operation is ready.
1

ENABLE_READY

RO

0x0

Write “1” on ENABLE_ALL_SEQ after thebit becomes “1”.
Permission/prohibition setting for operations

0

ENABLE_ALL_SEQ RW

0x0

of whole sequencers can be collectively
controlled－380/1293－

CXD5602 User Manual

3.9.12.3.4{0x5024} SEQ_ACCESS_INHIBIT Details
Table SCU (Sensor Control Unit)-156
Register Type: RW (read/write)

Local Address: 0x5024

Reset Value: 0x00000000

Bits

Name

31..20 Reserved
19
18
17
16
15
14
13
12
11

LPADC_ACCESS_I
NHIBIT_ACK3
LPADC_ACCESS_I
NHIBIT_ACK2
LPADC_ACCESS_I
NHIBIT_ACK1
LPADC_ACCESS_I
NHIBIT_REQ3
LPADC_ACCESS_I
NHIBIT_REQ2
LPADC_ACCESS_I
NHIBIT_REQ1
HPADC1_ACCESS_INHIBIT_ACK
HPADC0_ACCESS_INHIBIT_ACK
LPADC_ACCESS_I
NHIBIT_ACK

Type

Reset
Value

Description

RO

0x000 Reserved

RO

0x0

-

RO

0x0

-

RO

0x0

-

RW

0x0

RW

0x0

RW

0x0

-

RO

0x0

-

RO

0x0

-

RO

0x0

-

－381/1293－

SPI_ACCESS_INHIBIT_REQ

HPADC1_ACCESS_INHIBIT_REQ
HPADC0_ACCESS_INHIBIT_REQ
LPADC_ACCESS_INHIBIT_REQ
I2C1_ACCESS_INHIBIT_REQ
I2C0_ACCESS_INHIBIT_REQ

Reserved

Reserved

LPADC_ACCESS_INHIBIT_ACK3
LPADC_ACCESS_INHIBIT_ACK2
LPADC_ACCESS_INHIBIT_ACK1
LPADC_ACCESS_INHIBIT_REQ3
LPADC_ACCESS_INHIBIT_REQ2
LPADC_ACCESS_INHIBIT_REQ1
HPADC1_ACCESS_INHIBIT_ACK
HPADC0_ACCESS_INHIBIT_ACK
LPADC_ACCESS_INHIBIT_ACK
I2C1_ACCESS_INHIBIT_ACK
I2C0_ACCESS_INHIBIT_ACK
SPI_ACCESS_INHIBIT_ACK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

After “I2C1_ACCESS_INHIBIT_REQ==1” is detected, if
10

I2C1_ACCESS_INH
IBIT_ACK

you stop the I2C1 slave access, the sequencer sets “1” onRO

0x0

this bit.
You must read or write on the register for I2C1 slave after
the bit becomes “1”.
After “I2C0_ACCESS_INHIBIT_REQ==1” is detected, if

9

I2C0_ACCESS_INH
IBIT_ACK

you stop the I2C0 slave access, the sequencer sets “1” onRO

0x0

this bit.
You must read or write on the register for I2C0 slave after
the bit becomes “1”.
After “SPI_ACCESS_INHIBIT_REQ==1” is detected, if

8

SPI_ACCESS_INHI
BIT_ACK

you stop the SPI slave access, the sequencer sets “1” on this
RO

0x0

bit.
You must read or write on the register for the SPI slave after
the bit becomes “1”.

7..6ReservedRO

0x0

Reserved
When the sequencer is requested to be suspended
Suspend interrupt is requested and canceled to the internal

5

HPADC1_ACCESS_INHIBIT_REQ

RW

0x0

sequencer.
“1” is set when the sequencer is requested to be suspended.
“0” is set in the interrupt context.
Refer to Section 3.9.9.12.3
When the sequencer is requested to be completed orsuspended
Release and inhibition of the SLEEP for the internal

4

HPADC0_ACCESS_INHIBIT_REQ

RW

0x0

sequencer is performed.
“1” is set when the sequencer is requested to becompleted/suspended.
“0” is set after the request is done.
Refer to Section 3.9.9.13.
When the sequencer is requested to be completed
Complete interrupt is requested and canceled to the internal

3

LPADC_ACCESS_I
NHIBIT_REQ

RW

0x0

sequencer.
“1” is set when the sequencer is requested to be completed.
“0” is set in the interrupt context.
Refer to Section 3.9.9.12.3.

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CXD5602 User Manual

When the CPU directly accesses I2C1, “1” is set on this bit.
2

I2C1_ACCESS_INH
IBIT_REQ

SEQ_CTRL holds the access to I2C1 while the bit is “1”.
RW

0x0

Note that if this bit is set “1” for longer time than thesequencer’s access cycle using I2C1 from SEQ_CTRL, thebit of EXE_ERR_STT will become “1”.
When the CPU directly accesses I2C0, “1” is set on this bit.

1

I2C0_ACCESS_INH
IBIT_REQ

SEQ_CTRL holds the access to I2C0 while the bit is “1”.
RW

0x0

Note that if this bit is set “1” for longer time than thesequencer’s access cycle using I2C0 from SEQ_CTRL, thebit of EXE_ERR_STT will become “1”.
When the CPU directly accesses SPI, “1” is set on this bit.

0

SPI_ACCESS_INHI
BIT_REQ

SEQ_CTRL holds the access to SPI while the bit is “1”.
RW

0x0

Note that if this bit is set “1” for longer time than thesequencer’s access cycle using SPI from SEQ_CTRL, the bitof EXE_ERR_STT will become “1”.

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CXD5602 User Manual

3.9.12.3.5{0x5028} START_CTRL_COMMON Details
Table SCU (Sensor Control Unit)-157
Register Type: RW (read/write)

Local Address: 0x5028

Reset Value: 0x0000FF00

Reserved

PRE_DIVIDER

Bits

Name

Type

31..16

Reserved

RO

Reset
Value
0x0000

EXT_INT_POL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Description
Reserved
Maximum frequency setting for starting data capturingcommon to all sequencers
32.768

kHz/(PRE_DIVIDER+1)

is

the

maximum

frequency for data capturing common to all sequencers.
15..8

PRE_DIVIDER

RW

0xFF

For example, if you have a sensor which must sample at
maximum 1 kHz, the frequency is 32.768/ (31 + 1) =1024, and the value of PRE_DIVIDER is 31. For thesensor’s maximum sampling ability, refer to the Chapterof ADC (3.21).

7..1

Reserved

RO

0x00

Reserved
Polarity setting for the external interrupt input signal

0

EXT_INT_POL

RW

0x0

0: rising edge of the interrupt signal
1: falling edge of the interrupt signal－384/1293－

CXD5602 User Manual

3.9.12.3.6{0x502C} START_MODE0 Details
Table SCU (Sensor Control Unit)-158
Register Type: RW (read/write)

Local Address: 0x502C

Reset Value: 0x00000000

Bits

Name

Type Reset Value Description

31..10Reserved

RO

0x000000START_ENABLE9 RW

0x0

permission/prohibition

theReserved
This

9

START_ENABLE0

Reserved

START_ENABLE9
START_ENABLE8
START_ENABLE7
START_ENABLE6
START_ENABLE5
START_ENABLE4
START_ENABLE3
START_ENABLE2
START_ENABLE1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

designatesof

Sequencer 9’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

8

START_ENABLE8 RW

0x0

designates

permission/prohibition

of

the

Sequencer 8’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

7

START_ENABLE7 RW

0x0

designates

permission/prohibition

of

the

Sequencer 7’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

6

START_ENABLE6 RW

0x0

designates

permission/prohibition

of

the

Sequencer 6’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

5

START_ENABLE5 RW

0x0

designates

permission/prohibition

of

the

Sequencer 5’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.

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This
4

START_ENABLE4 RW

0x0

designates

permission/prohibition

of

the

Sequencer 4’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

3

START_ENABLE3 RW

0x0

designates

permission/prohibition

of

the

Sequencer 3’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

2

START_ENABLE2 RW

0x0

designates

permission/prohibition

of

the

Sequencer 2’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

1

START_ENABLE1 RW

0x0

designates

permission/prohibition

of

the

Sequencer 1’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.
This

0

START_ENABLE0 RW

0x0

designates

permission/prohibition

of

the

Sequencer 0’s operation. Even if the operation ispermitted, when ENABLE_ALL is prohibited, theoperation will not start.

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CXD5602 User Manual

3.9.12.3.7{0x5030} START_MODE1 Details
Table SCU (Sensor Control Unit)-159
Register Type: RW (read/write)

Local Address: 0x5030

Reset Value: 0x00000000

Bits

Name

Type

31..20Reserved

RO

Reset
Value

START_MODE0

START_MODE1

START_MODE2

START_MODE3

START_MODE4

START_MODE5

START_MODE6

START_MODE7

Reserved

START_MODE8

START_MODE931 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description

0x000 Reserved
This designates the Sequencer 9’s starting mode.
0: Operation suspended

19..18START_MODE9 RW

0x0

1: A certain cycle startup by the timer
2: One startup after the external interrupt occurrence
3: after the external interrupt occurrence

17..16

START_MODE8 RW

0x0

15..14

START_MODE7 RW

0x0

13..12

START_MODE6 RW

0x0

11..10START_MODE5 RW

0x0

9..8

START_MODE4 RW

0x0

7..6

START_MODE3 RW

0x0

5..4

START_MODE2 RW

0x0

3..2

START_MODE1 RW

0x0

1..0

START_MODE0 RW

0x0This designates the Sequencer 8’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 7’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 6’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 5’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 4’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 3’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 2’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 1’s starting mode.
For the control specifications, refer to START_MODE9.
This designates the Sequencer 0’s starting mode.
For the control specifications, refer to START_MODE9.

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CXD5602 User Manual

3.9.12.3.8{0x5034} START_INTERVAL3_0 Details
Table SCU (Sensor Control Unit)-160
Register Type: RW (read/write)

Local Address: 0x5034

Reset Value: 0x00000000

Bits

Name

31..28 Reserved

Type
RO

Reset
Value
0x0

Reserved

Reserved

START_INTERVAL0

Reserved

START_INTERVAL1

START_INTERVAL2

Reserved

START_INTERVAL3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
This designates Sequencer 3’s timer operating frequency division
value.
When SEQ_MODE is “0” or “1”, the set value is referred.

27..24

START_INTERVAL3RW

0x0

32.768

kHz/(PRE_DIVIDER+1)/(2^START_INTERVAL3)

is

Sequencer 3’s operating frequency division value.
The value range that can be set to SEQ_INTERVAL3 is from 0 to 9.
When using a One-shot Sequencer corresponding to the register, 0xA
must be set.

23..20 Reserved

RO

0x0

Reserved
This designates Sequencer 2’s timer operating frequency division
value.

19..16

START_INTERVAL2

RW

0x0

When SEQ_MODE is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the rangeof values that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

15..12 Reserved

RO

0x0

Reserved
This designates Sequencer 1’s timer operating frequency division
value.

11..8

START_INTERVAL1

RW

0x0

When SEQ_MODE1 is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the rangeof values that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

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7..4

ReservedRO

0x0

Reserved
This designates Sequencer 0’s timer operating frequency division
value.

3..0

START_INTERVAL0

RW

When SEQ_MODE0 is “0” or “1”, this set value is referred.

0x0

As for the calculating formula of the operating frequency, the rangeof values that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

3.9.12.3.9{0x5038} START_INTERVAL7_4 Details
Table SCU (Sensor Control Unit)-161
Register Type: RW (read/write)

Local Address: 0x5038

Reset Value: 0x00000000

Bits

Name

31..28 Reserved

Type
RO

Reset
Value
0x0

Reserved

START_INTERVAL4

Reserved

START_INTERVAL5

Reserved

START_INTERVAL6

Reserved

START_INTERVAL7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
This designates Sequencer 7’s timer operating frequency division
value.

27..24

START_INTERVAL7

RW

0x0

When SEQ_MODE7 is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the range ofvalues that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

23..20 Reserved

RO

0x0

Reserved
This designates Sequencer 6’s timer operating frequency division
value.

19..16

START_INTERVAL6

RW

0x0

When SEQ_MODE6 is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the range ofvalues that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

15..12 Reserved

RO

0x0

Reserved－389/1293－

CXD5602 User ManualThis designates Sequencer 5’s timer operating frequency division
value.
11..8

START_INTERVAL5

RW

0x0

When SEQ_MODE5 is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the range ofvalues that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

7..4

ReservedRO

0x0

Reserved
This designates Sequencer 4’s timer operating frequency division
value.

3..0

START_INTERVAL4

RW

0x0

When SEQ_MODE4 is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the range ofvalues that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

3.9.12.3.10{0x503C} START_INTERVAL9_8 Details
Table SCU (Sensor Control Unit)-162
Register Type: RW (read/write)

Local Address: 0x503C

Reset Value: 0x00000000

Reserved

Bits

Name

31..12 Reserved

Type
RO

Reset
Value

Reserved

START_INTERVAL8START_INTERVAL9

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description

0x00000 Reserved
This designates Sequencer 9’s timer operating frequency division
value.

START_I
11..8

NTERVA RW

0x0

L9

When SEQ_MODE9 is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the rangeof values that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

7..4

ReservedRO

0x0

Reserved－390/1293－

CXD5602 User ManualThis designates Sequencer 8’s timer operating frequency division
value.

START_I
3..0

NTERVA RW
L80x0

When SEQ_MODE8 is “0” or “1”, this set value is referred.
As for the calculating formula of the operating frequency, the rangeof values that can be set, and set values when using the One-shot
Sequencer, refer to START_INTERVAL3.

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3.9.12.3.11{0x5040} START_PHASE1_0 Details
Table SCU (Sensor Control Unit)-163
Register Type: RW (read/write)

Local Address: 0x5040

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

Bits

START_PHASE1

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

Reserved

START_PHASE0

Description
Reserved
This designates Sequencer 1’s timer startup phase.
When SEQ_MODE1 is “0” or “1”, this set value is referred.

24..16 START_PHASE1

RW

0x000 When the value of the internal counter SEQ_INTERVAL1
corresponds to SEQ_PHASE1, a request to start sequencer
operation occurs.

15..9

Reserved

RO

0x00

Reserved
This designates Sequencer 0’s timer startup phase.
When SEQ_MODE0 is “0” or “1”, this set value is referred.

8..0

START_PHASE0

RW0x000 When the value of the internal counter SEQ_INTERVAL0
corresponds to SEQ_PHASE0, a request to start sequencer
operation occurs.

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3.9.12.3.12{0x5044} START_PHASE3_2 Details
Table SCU (Sensor Control Unit)-164
Register Type: RW (read/write)

Local Address: 0x5044

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

START_PHASE3

Bits

Type

Name

31..25 Reserved

RO

Reset
Value
0x00

Reserved

START_PHASE2

Description
Reserved
This designates Sequencer 3’s timer startup phase.

24..16

START_PH
ASE3

When SEQ_MODE3 is “0” or “1”, this set value is referred.
RW

0x000 When the value of the internal counter SEQ_INTERVAL3
corresponds to SEQ_PHASE3, a request to start sequencer
operation occurs.

15..9

Reserved

RO

0x00

Reserved
This designates Sequencer 2’s timer startup phase.

8..0

START_PH
ASE2

When SEQ_MODE2 is “0” or “1”, this set value is referred.
RW

0x000 When the value of the internal counter SEQ_INTERVAL2
corresponds to SEQ_PHASE2, a request to start sequencer
operation occurs.

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3.9.12.3.13{0x5048} START_PHASE5_4 Details
Table SCU (Sensor Control Unit)-165
Register Type: RW (read/write)

Local Address: 0x5048

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

START_PHASE5

Bits

Type

Name

31..25 Reserved

RO

Reset
Value
0x00

Reserved

START_PHASE4

Description
Reserved
This designates Sequencer 5’s timer startup phase.

24..16

START_PH
ASE5

When SEQ_MODE5 is “0” or “1”, this set value is referred.
RW

0x000 When the value of the internal counter SEQ_INTERVAL5
corresponds to SEQ_PHASE5, a request to start sequencer
operation occurs.

15..9

Reserved

RO

0x00

Reserved
This designates Sequencer 4’s timer startup phase.

8..0

START_PH
ASE4

When SEQ_MODE4 is “0” or “1”, this set value is referred.
RW

0x000 When the value of the internal counter SEQ_INTERVAL4
corresponds to SEQ_PHASE4, a request to start sequencer
operation occurs.

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3.9.12.3.14{0x504C} START_PHASE7_6 Details
Table SCU (Sensor Control Unit)-166
Register Type: RW (read/write)

Local Address: 0x504C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

START_PHASE7

Bits

Type

Name

31..25 Reserved

RO

Reset
Value
0x00

Reserved

START_PHASE6

Description
Reserved
This designates Sequencer 7’s timer startup phase.

24..16

START_PH
ASE7

When SEQ_MODE7 is “0” or “1”, this set value is referred.
RW

0x000 When the value of the internal counter SEQ_INTERVAL7
corresponds to SEQ_PHASE7, a request to start sequencer operation
occurs.

15..9Reserved

RO

0x00

Reserved
This designates Sequencer 6’s timer startup phase.

8..0

START_PH
ASE6

When SEQ_MODE1 is “0” or “1”, this set value is referred.
RW

0x000 When the value of the internal counter SEQ_INTERVAL6
corresponds to SEQ_PHASE6, a request to start sequencer operation
occurs.

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3.9.12.3.15{0x5050} START_PHASE9_8 Details
Table SCU (Sensor Control Unit)-167
Register Type: RW (read/write)

Local Address: 0x5050

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

Bits

Name

31..25 Reserved

START_PHASE9

Type
RO

Reset
Value
0x00

Reserved

START_PHASE8

Description
Reserved
This designates Sequencer 9’s timer startup phase.

24..16

START_P
HASE9

When SEQ_MODE9 is “0” or “1”, this set value is referred.
RW

0x000

When the value of the internal counter SEQ_INTERVAL9
corresponds to SEQ_PHASE9, a request to start sequencer operation
occurs.

15..9Reserved

RO

0x00

Reserved
This designates Sequencer 8’s timer startup phase.

8..0

START_P
HASE8

When SEQ_MODE8 is “0” or “1”, this set value is referred.
RW

0x000

When the value of the internal counter SEQ_INTERVAL8
corresponds to SEQ_PHASE8, a request to start sequencer operation
occurs.

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3.9.12.3.16{0x5054} SINGLE_EXE Details
Table SCU (Sensor Control Unit)-168
Register Type: RW (read/write)

Local Address: 0x5054

Reset Value: 0x00000000

Bits

Name

31..10 Reserved

REQ9
REQ8
REQ7
REQ6
REQ5
REQ4
REQ3
REQ2
REQ1

Reserved

Type
RO

Reset
Value
0x000000

REQ031 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
By writing “1”, Sequencer 9’s execution request is issued only once.

9

REQ9

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE9 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 8’s execution request is issued only once.

8

REQ8

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE8 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 7’s execution request is issued only once.

7

REQ7

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE7 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 6’s execution request is issued only once.

6

REQ6

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE6 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 5’s execution request is issued only once.

5

REQ5

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE5 is “2” or “3”, this set value is referred.

－397/1293－

CXD5602 User Manual

By writing “1”, Sequencer 4’s execution request is issued only once.
4

REQ4

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE4 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 3’s execution request is issued only once.

3

REQ3

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE3 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 2’s execution request is issued only once.

2

REQ2

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE2 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 1’s execution request is issued only once.

1

REQ1

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE1 is “2” or “3”, this set value is referred.
By writing “1”, Sequencer 0’s execution request is issued only once.

0

REQ0

WO

0x0

When the corresponding START_ENABLE bit is “0”, this register is
not active.
When SEQ_MODE0 is “2” or “3”, this set value is referred.

3.9.12.3.17{0x5058} START_CTRL_STT0 Details
Table SCU (Sensor Control Unit)-169
Register Type: RO (read only)

Local Address: 0x5058

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME_STAMP_MSB
Bits

Name

Type Reset Value

Description
The time stamp value at the time of being read out can beread out.

31..0

TIME_STAM
P_MSB

Note that the value can be changed when reading out theRO

0x00000000

TIME_STAMP_LSB.

Therefore,

read

out

TIME_STAMP_MSB and TIME_STAMP_LSB, and do thesame again to confirm that the second values are notchanged from the first.

－398/1293－

CXD5602 User Manual

3.9.12.3.18{0x505C} START_CTRL_STT1 Details
Table SCU (Sensor Control Unit)-170
Register Type: RO (read only)

Local Address: 0x505C

Reset Value: 0x00000000

Reserved

Bits

EXE_REQ_STT

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIME_STAMP_LSB

Description
Reserved
This indicates the request status of the sequencers.
1: request issued or request in processing
bit 16: Sequencer 0
bit 17: Sequencer 1
bit 18: Sequencer 2

25..16 EXE_REQ_STT

RO

0x000

bit 19: Sequencer 3
bit 20: Sequencer 4
bit 21: Sequencer 5
bit 22: Sequencer 6
bit 23: Sequencer 7
bit 24: Sequencer 8
bit 25: Sequencer 915

ReservedRO

0x0

Reserved
The execution request value at the time of being read out canbe read out.

14..0

TIME_STAMP_LS
B

Note that the value can be changed when reading out theRO

0x0000 TIME_STAMP_MSB.

Therefore,

read

out

TIME_STAMP_MSB and TIME_STAMP_LSB, and do thesame again to confirm that the second values are not changed
from the first.

－399/1293－

CXD5602 User Manual

3.9.12.3.19{0x5060} DEBUG_CTRL Details
Table SCU (Sensor Control Unit)-171
Register Type: RW (read/write)

Local Address: 0x5060

Reset Value: 0x00000000

DONE_REQ

ReservedReset

MONSEL

Reserved

Bits

Name

Type

31

EXT_INT_REQ

WO

0x0

30..26 Reserved

RO

0x00

25..16 DONE_REQ

WO

0x000

15..12 Reserved

RO

0x0

Reserved

11..8

MONSEL

RW

0x0

Selecting monitor output signals

7..2

Reserved

RO

0x00

Reserved

1

EXT_INT_REQ_DBG_EN RW

0x0

This enables EXE_INT_REQ.

0

DONE_REQ_DBG_EN

0x0

This enables DONE_REQ.

RW

DONE_REQ_DBG_EN

Reserved

EXT_INT_REQ_DBG_EN

EXT_INT_REQ

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description

Value

This forces an external interrupt to occur from theCPU.
Reserved
This forces an execution completed to occur from theCPU.

－400/1293－

CXD5602 User Manual

3.9.12.3.20{0x5070} OFST_GAIN_EN Details
Table SCU (Sensor Control Unit)-172
Register Type: RW (read/write)

Local Address: 0x5070

Reset Value: 0x00000000

Bits

Name

31..16 Reserved
15

14

13

12

11

10

9

OFST_GAIN_
EN15
OFST_GAIN_EN14
OFST_GAIN_EN13
OFST_GAIN_EN12
OFST_GAIN_EN11
OFST_GAIN_EN10
OFST_GAIN_
EN9

Type
RO

Reset
Value
0x0000

OFST_GAIN_EN0

Reserved

OFST_GAIN_EN4

Reserved

Reserved

OFST_GAIN_EN15
OFST_GAIN_EN14
OFST_GAIN_EN13
OFST_GAIN_EN12
OFST_GAIN_EN11
OFST_GAIN_EN10
OFST_GAIN_EN9
OFST_GAIN_EN8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 9.
If “0” is designated, the value of OFST_GAIN9 is ignored.
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 8.
If “0” is designated, the value of OFST_GAIN8 is ignored.
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 7.
If “0” is designated, the value of OFST_GAIN7 is ignored.
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 6.
If “0” is designated, the value of OFST_GAIN6 is ignored.
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 5.
If “0” is designated, the value of OFST_GAIN5 is ignored.
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 4.
If “0” is designated, the value of OFST_GAIN4 is ignored.
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 3.
If “0” is designated, the value of OFST_GAIN3 is ignored.

－401/1293－

CXD5602 User Manual

8
7..5
4
3..1
0

OFST_GAIN_
EN8Reserved
OFST_GAIN_
EN4Reserved
OFST_GAIN_
EN0

Designate “1” to perform offset addition processing and gain
RW

0x0

multiplication processing for MATH_PROC of Sequencer 2.
If “0” is designated, the value of OFST_GAIN2 is ignored.

RO

0x0

Reserved
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 1.
If “0” is designated, the value of OFST_GAIN1 is ignored.

RO

0x0

Reserved
Designate “1” to perform offset addition processing and gain

RW

0x0

multiplication processing for MATH_PROC of Sequencer 0.
If “0” is designated, the value of OFST_GAIN0 is ignored.

－402/1293－

CXD5602 User Manual

3.9.12.3.21{0x5074} UNSIGNED_TO_SIGNED Details
Table SCU (Sensor Control Unit)-173
Register Type: RW (read/write)

Local Address: 0x5074

Reset Value: 0x00000000

Bits

Name

31..16 Reserved

Type
RO

Reset
Value
0x0000UNSIGNED_TO_SIGNED0

Reserved

UNSIGNED_TO_SIGNED4

Reserved

Reserved

UNSIGNED_TO_SIGNED15
UNSIGNED_TO_SIGNED14UNSIGNED_TO_SIGNED13
UNSIGNED_TO_SIGNED12UNSIGNED_TO_SIGNED11UNSIGNED_TO_SIGNED10UNSIGNED_TO_SIGNED9UNSIGNED_TO_SIGNED8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
When “1” is designated, before performing offset addition
processing and gain multiplication processing of Sequencer 9,
the input data format must be regarded as offset binary and

15

UNSIGNED_TO_SIGNED15

RW

0x0

converted into two’s complement format. The offset binary
format’s offset is [(maximum value of input value binary +1)/2.
When “0” is designated, code conversion is not performed.

14
13
12
11
10
9

UNSIGNED_TO_SIGNED14
UNSIGNED_TO_SIGNED13
UNSIGNED_TO_SIGNED12UNSIGNED_TO_SIGNED11
UNSIGNED_TO_SIGNED10
UNSIGNED_TO_SIGNED9

RW

0x0

RW

0x0

RW

0x0

RW

0x0

RW

0x0

RW

0x0

This controls processing of Sequencer 8.
As for specifications, refer to UNSIGNED_TO_SIGNED15.
This controls processing of Sequencer 7.
As for specifications, refer to UNSIGNED_TO_SIGNED15.
This controls processing of Sequencer 6.
As for specifications, refer to UNSIGNED_TO_SIGNED15.
This controls processing of Sequencer 5.
As for specifications, refer to UNSIGNED_TO_SIGNED15.
This controls processing of Sequencer 4.
As for specifications, refer to UNSIGNED_TO_SIGNED15.
This controls processing of Sequencer 3.
As for specifications, refer to UNSIGNED_TO_SIGNED15－403/1293－

CXD5602 User Manual

8
7..5
4
3..1
0

UNSIGNED_TO_SIGNED8
Reserved
UNSIGNED_TO_SIGNED4
Reserved
UNSIGNED_TO_SIGNED0

RW

0x0

RO

0x0

RW

0x0

RO

0x0

RW

0x0

This controls processing of Sequencer 2.
As for specifications, refer to UNSIGNED_TO_SIGNED15.
Reserved
This controls processing of Sequencer 1.
As for specifications, refer to UNSIGNED_TO_SIGNED15.
Reserved
This controls processing of Sequencer 0.
As for specifications, refer to UNSIGNED_TO_SIGNED15.

－404/1293－

CXD5602 User Manual

3.9.12.3.22{0x5078} DEC_CLR Details
Table SCU (Sensor Control Unit)-174
Register Type: WO (write only)

Local Address: 0x5078

Reset Value: 0x00000000

Bits

Reset

Name

Type

31..8 Reserved

WO

0x000000 Reserved7

DEC1_N2_CLR

WO

0x0

6

DEC1_N1_CLR

WO

0x0

5

DEC1_N0_CLR

WO

0x0

4

DEC1_COMMON_CLR

WO

0x0

3

DEC0_N2_CLR

WO

0x0

2

DEC0_N1_CLR

WO

0x0

1

DEC0_N0_CLR

WO

0x0

0

DEC0_COMMON_CLR

WO

0x0

Value

DEC0_COMMON_CLR

Reserved

DEC1_N2_CLR
DEC1_N1_CLR
DEC1_N0_CLR
DEC1_COMMON_CLR
DEC0_N2_CLR
DEC0_N1_CLR
DEC0_N0_CLR

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reset

(to

FF

in

the

(to

FF

in

the

(to

FF

in

the

(to

FF

in

the

(to

FF

in

the

(to

FF

in

the

Description

DEC1

synchronous

differentiating circuit for N2)
DEC1

synchronous

reset

differentiating circuit for N1)
DEC1

synchronous

reset

differentiating circuit for N0)
DEC1 synchronous reset
DEC0synchronous

reset

differentiating circuit for N2)
DEC0synchronous

reset

differentiating circuit for N1)
DEC0

synchronous

reset

differentiating circuit for N0)
DEC0 synchronous reset (to FF in the integrating
circuit)－405/1293－

CXD5602 User Manual

3.9.12.3.23{0x507C} MATHFUNC_CLR Details
Table SCU (Sensor Control Unit)-175
Register Type: WO (write only)

Local Address: 0x507C

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..3

Reserved

WO

0x00000000

Reserved

2

MATHFUNC2_CLR WO

0x0

MATHFUNC2 synchronous reset

1

MATHFUNC1_CLR WO

0x0

MATHFUNC1 synchronous reset0

MATHFUNC0_CLR WO

0x0

MATHFUNC0 synchronous reset

3.9.12.3.24

MATHFUNC0_CLR

MATHFUNC2_CLR
MATHFUNC1_CLR

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0{0x5080} EVENT_STT Details
Table SCU (Sensor Control Unit)-176
Register Type: WO (write only)

Local Address: 0x5080

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

CLR

Bits

Name

Type Reset Value

Description

31..3

Reserved

WO

0x00000000

Reserved

2..0

CLR

WO

0x0

Clear of the internal status for the event
detection－406/1293－

CXD5602 User Manual

3.9.12.3.25{0x5084} DECIMATION_PARAM0 Details
Table SCU (Sensor Control Unit)-177
Register Type: RW (read/write)

Local Address: 0x5084

Reset Value: 0x00000000

3130

FORCE_THROU
GH3
Reserved

Type

Value
0x0

RO

0x0

LEVEL_ADJ_0

N1
Reserved

LEVEL_ADJ_1

N2

Reset

RW

FORCE_THROUGH1Reserved

Name

LEVEL_ADJ_2

LEVEL_ADJ_3

Bits

N3

FORCE_THROUGH2Reserved

FORCE_THROUGH3
Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Description
When “1” is set, input data is forced to output directly regardlessof the N3 value.
Reserved
Level adjust value setting with clipping for D0_W3_S.
0: once29..28 LEVEL_ADJ_3 RW

0x0

1: twice
2: four times
3: eight times
Decimation ratio for D0_W3_S.

27..24 N3

RW

0x0

0 to 9: Frequency is divided by 1/(2^n) using n as a designatedvalue.
10 to 15: Decimation is not performed, and data are not output.

23

FORCE_THROU

RW

0x0

RO

0x0

21..20 LEVEL_ADJ_2 RW

0x0

19..16 N2

RW

0x0

RW

0x0

RO

0x0

22

15
14

GH2
Reserved

FORCE_THROU
GH1
Reserved

When “1” is set, input data is forced to output directly regardlessof the N2 value.
Reserved
Level adjust value setting with clipping for D0_W2_S.
As for specifications, refer to LEVEL_ADJ_3.
Decimation ratio for D0_W3_S.
As for specifications, refer to N3.
When “1” is set, input data is forced to output directly regardlessof the N1 value.
Reserved－407/1293－

CXD5602 User Manual

13..12 LEVEL_ADJ_1 RW

0x0

11..8

N1

RW

0x0

7..6

Reserved

RO

0x0

5..4

LEVEL_ADJ_0 RW

0x0

3..0

Reserved

0x0

RO

Level adjust value setting with clipping for D1_W1_S.
As for specifications, refer to LEVEL_ADJ_3.
Decimation ratio for D0_W1_S.
As for specifications, refer to N3.
Reserved
Level adjust value setting with clipping for D0_W0_S.
As for specifications, refer to LEVEL_ADJ_3.
Reserved－408/1293－

CXD5602 User Manual

3.9.12.3.26{0x5088} DECIMATION_PARAM1 Details
Table SCU (Sensor Control Unit)-178
Register Type: RW (read/write)

Local Address: 0x5088

Reset Value: 0x00000000

3130

FORCE_THROUG
H7Reserved

Type

Value
0x0

RO

0x0

LEVEL_ADJ_4

N5
Reserved

LEVEL_ADJ_5

N6

Reset

RW

FORCE_THROUGH5
Reserved

Name

LEVEL_ADJ_6

LEVEL_ADJ_7

Bits

N7

FORCE_THROUGH6
Reserved

FORCE_THROUGH7
Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Description
When “1” is set, input data is forced to output directly
regardless of the N7 value.
Reserved
Level adjust value setting with clipping for D1_W3_S.
0: once29..28 LEVEL_ADJ_7

RW

0x0

1: twice
2: four times
3: eight times
Decimation ratio for D1_W3_S.
0 to 9: Frequency is divided by 1/(2^n) using n as a designated27..24 N7

RW

0x0

value.
10 to 15: Decimation is not performed, and data are not
output.

23

FORCE_THROUG

RW

0x0

Reserved

RO

0x021..20 LEVEL_ADJ_6

RW

0x0

19..16 N6

RW

0x0

RW

0x0

22

15

H6

FORCE_THROUG
H5When “1” is set, input data is forced to output directly
regardless of the N6 value.
Reserved
Level adjust value setting with clipping for D1_W2_S.
As for specifications, refer to LEVEL_ADJ_7.
Decimation ratio for D0_W2_S.
As for specifications, refer to N7.
When “1” is set, input data is forced to output directly
regardless of the N5 value.

－409/1293－

CXD5602 User Manual

14

Reserved

RO

0x0

13..12 LEVEL_ADJ_5

RW

0x0

11..8

N5

RW

0x0

7..6

Reserved

RO

0x0

5..4

LEVEL_ADJ_4

RW

0x0

3..0

ReservedRO

0x0

Reserved
Level adjust value setting with clipping for D1_W1_S.
As for specifications, refer to LEVEL_ADJ_7.
Decimation ratio for D1_W1_S.
As for specifications, refer to N7.
Reserved
Level adjust value setting with clipping for D1_W0_S.
As for specifications, refer to LEVEL_ADJ_7.
Reserved－410/1293－

CXD5602 User Manual

3.9.12.3.27{0x508C} MATHFUNC_SEL Details

0: D0_W0_S

8: N0_W_S

1: D0_W1_S

9: N1_W_S

2: D0_W2_S

10: N2_W_S

3: D0_W3_S

11: N3_W_S

4: D1_W0_S

12: N4_W_S

5: D1_W1_S

13: N5_W_S

6: D1_W2_S

14: N6_W_S

7: D1_W3_S

15: N7_W_S
Table SCU (Sensor Control Unit)-179
Register Type: RW (read/write)

Local Address: 0x508C

Reset Value: 0x00000000

MATHF_EN0

WID1

Reserved

WID2

MATHF_EN1

Reserved

Reserved

MATHF_EN2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WID0

Bits

Name

Type Reset Value

Description

31..21

Reserved

RO

0x000

Reserved

20

MATHF_EN2

RW

0x0

Operation permission of Math Function 2

19..16

WID2

RW

0x0

15..13

ReservedRO

0x0

Reserved

12

MATHF_EN1

RW

0x0

Operation permission of Math Function 1

11..8

WID1

RW

0x0

7..5

ReservedRO

0x0

Reserved

4

MATHF_EN0

RW

0x0

Operation permission of Math Function 0

3..0

WID0

RW

0x0

FIFO Partition ID setting value allocated toMath Function 2: 0 to 15

FIFO Partition ID setting value allocated toMath Function 1: 0 to 15

FIFO Partition ID setting value allocated toMath Function 0: 0 to 15－411/1293－

CXD5602 User Manual

3.9.12.3.28{0x5090} MATHFUNC_POS0 Details

1

2

5

3

4

Norm.

6

7

2nd order
IIR

8

Excess
Detector

2nd order
IIR

Figure SCU (Sensor Control Unit)-113 Processing Block Overview
In Figure SCU (Sensor Control Unit)-113, we call insertion IIR on the left side “IIR0”, insertion IIR on theright side “IIR1”.
The positions where IIRs are inserted are as follows:
4’b0001:{(1), (2)}4’b0011:{(1), (3)}4’b0101:{(1), (5)}4’b1001:{(1), (7)}4’b0010:{(3), (4)}4’b0110:{(3), (5)}4’b1010:{(3), (7)}4’b0100:{(5), (6)}4’b1100:{(5), (7)}4’b1001:{(7), (8)}Table SCU (Sensor Control Unit)-180
Register Type: RW (read/write)

Local Address: 0x5090

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Bits

POS_0
Name

Type Reset Value

Description－412/1293－

CXD5602 User Manual

31..4

Reserved

RO

0x0000000

3..0

POS_0

RW

0x0

3.9.12.3.29

Reserved
This designates the position where the IIR of
Math Function 0 is inserted.

{0x5094} MATHFUNC_POS1 Details

As for the positions where the IIRs are inserted, refer to Section 3.9.12.3.28 {0x5090} MATHFUNC_POS0.
Table SCU (Sensor Control Unit)-181
Register Type: RW (read/write)

Local Address: 0x5094

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

POS_1

Bits

Name

Type Reset Value

Description

31..4

Reserved

RO

0x0000000

Reserved

3..0

POS_1

RW

0x0

3.9.12.3.30

This designates the position where the IIR of
Math Function 1 is inserted.

{0x5098} MATHFUNC_POS2 Details

As for the positions where the IIRs are inserted, refer to Section 3.9.12.3.28 {0x5090} MATHFUNC_POS0.
Table SCU (Sensor Control Unit)-182
Register Type: RW (read/write)

Local Address: 0x5098

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

POS_2

Bits

Name

Type Reset Value

Description

31..4

Reserved

RO

0x0000000

Reserved

3..0

POS_2

RW

0x0

This designates the position where the IIR of
Math Function 2 is inserted.

－413/1293－

CXD5602 User Manual

3.9.12.3.31{0x50A0} MATHFUNC_PARAM_0_0 Details
REG
C0

X

bit
Expand

Clip

REG
S1

Z-1

REG
C1

±3bit shift

Round
and
Clip

Round

REG
S2

REG
C2

±3bit shift
Round

Round

Z-1

REG
C3

REG
C4

Round

Round

Figure SCU (Sensor Control Unit)-114 Filter Overview
Table SCU (Sensor Control Unit)-183
Register Type: RW (read/write)

Local Address: 0x50A0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

S2

Bits

Name

Type Reset Value

Description

31..11

ReservedRO

Reserved

0x000000Reserved

S1

The IIR parameter for Math Function 0
10..8

S2

RW

0x0

±3 bit shift at IIR0 outlet port
Changing the setting value is prohibited during
operation.

7..3

Reserved

RO

0x00

Reserved
The IIR parameter for Math Function 0

2..0

S1

RW

0x0

±3 bit shift at IIR0 outlet port
Changing the setting value is prohibited during
operation.

－414/1293－YCXD5602 User Manual

3.9.12.3.32{0x50A4} MATHFUNC_PARAM_C0_0_0_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-184
Register Type: RW (read/write)

Local Address: 0x50A4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C0

31..0

C0

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.33{0x50A8} MATHFUNC_PARAM_C0_0_0_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-185
Register Type: RW (read/write)

Local Address: 0x50A8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C0

31..30C0RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－415/1293－

CXD5602 User Manual

3.9.12.3.34{0x50B0} MATHFUNC_PARAM_C1_0_0_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-186
Register Type: RW (read/write)

Local Address: 0x50B0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C1

31..0

C1

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.35{0x50B4} MATHFUNC_PARAM_C1_0_0_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-187
Register Type: RW (read/write)

Local Address: 0x50B4Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C1

31..30C1

RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－416/1293－

CXD5602 User Manual

3.9.12.3.36{0x50B8} MATHFUNC_PARAM_C2_0_0_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-188
Register Type: RW (read/write)

Local Address: 0x50B8Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C2

31..0

C2

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.37{0x50BC} MATHFUNC_PARAM_C2_0_0_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-189
Register Type: RW (read/write)

Local Address: 0x50BC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C2

31..30C2

RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－417/1293－

CXD5602 User Manual

3.9.12.3.38{0x50D0} MATHFUNC_PARAM_C3_0_0_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-190
Register Type: RW (read/write)

Local Address: 0x50D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C3

31..0

C3

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.39{0x50D4} MATHFUNC_PARAM_C3_0_0_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-191
Register Type: RW (read/write)

Local Address: 0x50D4Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C3

31..30C3RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－418/1293－

CXD5602 User Manual

3.9.12.3.40{0x50D8} MATHFUNC_PARAM_C4_0_0_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-192
Register Type: RW (read/write)

Local Address: 0x50D8Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C4

31..0

C4

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.41{0x50DC} MATHFUNC_PARAM_C4_0_0_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-193
Register Type: RW (read/write)

Local Address: 0x50DC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C4

31..30C4RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－419/1293－

CXD5602 User Manual

3.9.12.3.42{0x50E0} MATHFUNC_PARAM_0_1 Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-194
Register Type: RW (read/write)

Local Address: 0x50E0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

S2

Bits

Name

Type Reset Value

Description

31..11

ReservedRO

Reserved

0x000000Reserved

S1

The IIR parameter for Math Function 0
10..8

S2

RW

0x0

±3 bit shift at IIR1 outlet port
Changing the setting value is prohibited during
operation.

7..3

Reserved

RO

0x00

Reserved
The IIR parameter for Math Function 0

2..0

S1

RW

0x0

±3 bit shift at IIR1 outlet port
Changing the setting value is prohibited during
operation.

－420/1293－

CXD5602 User Manual

3.9.12.3.43{0x50E4} MATHFUNC_PARAM_C0_0_1_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-195
Register Type: RW (read/write)

Local Address: 0x50E4Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C0

31..0

C0

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.44{0x50E8} MATHFUNC_PARAM_C0_0_1_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-196
Register Type: RW (read/write)

Local Address: 0x50E8Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C0

31..30C0RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－421/1293－

CXD5602 User Manual

3.9.12.3.45{0x50EC} MATHFUNC_PARAM_C1_0_1_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-197
Register Type: RW (read/write)

Local Address: 0x50EC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C1

31..0

C1

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.46{0x50F0} MATHFUNC_PARAM_C1_0_1_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-198
Register Type: RW (read/write)

Local Address: 0x50F0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C1

31..30C1

RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－422/1293－

CXD5602 User Manual

3.9.12.3.47{0x50F4} MATHFUNC_PARAM_C2_0_1_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-199
Register Type: RW (read/write)

Local Address: 0x50F4Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C2

31..0

C2

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.48{0x50F8} MATHFUNC_PARAM_C2_0_1_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-200
Register Type: RW (read/write)

Local Address: 0x50F8Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C2

31..30C2

RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－423/1293－

CXD5602 User Manual

3.9.12.3.49{0x50FC} MATHFUNC_PARAM_C3_0_1_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-201
Register Type: RW (read/write)

Local Address: 0x50FC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C3

31..0

C3

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.50{0x5100} MATHFUNC_PARAM_C3_0_1_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-202
Register Type: RW (read/write)

Local Address: 0x5100

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C3

31..30C3RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－424/1293－

CXD5602 User Manual

3.9.12.3.51{0x5104} MATHFUNC_PARAM_C4_0_1_MSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-203
Register Type: RW (read/write)

Local Address: 0x5104

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C4

31..0

C4

RW

0x00000000

Coefficient value format: (s2.31)
Changing the setting value is prohibited during
operation.

3.9.12.3.52{0x5108} MATHFUNC_PARAM_C4_0_1_LSB Details

The IIR Parameter for Math Function 0
Table SCU (Sensor Control Unit)-204
Register Type: RW (read/write)

Local Address: 0x5108

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Reserved
Name

Type Reset Value

Description
Coefficient setting for IIR0 REG: C4

31..30C4RW

Coefficient value format: (s2.31)

0x0Changing the setting value is prohibited during
operation.

29..0

Reserved

RO

0x00000000

Reserved－425/1293－

CXD5602 User Manual

3.9.12.3.53{0x510C} MATHFUNC_PARAM_1_0 Details

The IIR Parameter for Math Function 1
Refer to {0x50A0} MATHFUNC_PARAM_0_0 Details
Table SCU (Sensor Control Unit)-205
Register Type: RW (read/write)

Local Address: 0x510C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

S2

Bits

Name

Type Reset Value

Description

31..11

Reserved

RO

0x000000Reserved

10..8

S2

RW

0x0

7..3

Reserved

RO

0x00

2..0

S1

RW

0x0

Reserved－426/1293－

Reserved

S1

CXD5602 User Manual

3.9.12.3.54{0x5110} MATHFUNC_PARAM_C0_1_0_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50A4} MATHFUNC_PARAM_C0_0_0_MSB Details
Table SCU (Sensor Control Unit)-206
Register Type: RW (read/write)

Local Address: 0x5110

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Name

Type Reset Value

31..0

C0

RW

3.9.12.3.55

Description

0x00000000{0x5114} MATHFUNC_PARAM_C0_1_0_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x50A8} MATHFUNC_PARAM_C0_0_0_LSB Details
Table SCU (Sensor Control Unit)-207
Register Type: RW (read/write)

Local Address: 0x5114

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0

Reserved

Bits

Name

Type Reset Value

31..30

C0

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－427/1293－

CXD5602 User Manual

3.9.12.3.56{0x5118} MATHFUNC_PARAM_C1_1_0_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50B0} MATHFUNC_PARAM_C1_0_0_MSB Details
Table SCU (Sensor Control Unit)-208
Register Type: RW (read/write)

Local Address: 0x5118

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Name

Type Reset Value

31..0

C1

RW

3.9.12.3.57

Description

0x00000000{0x511C} MATHFUNC_PARAM_C1_1_0_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x50B4} MATHFUNC_PARAM_C1_0_0_LSB Details
Table SCU (Sensor Control Unit)-209
Register Type: RW (read/write)

Local Address: 0x511C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1

Reserved

Bits

Name

Type Reset Value

31..30

C1

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－428/1293－

CXD5602 User Manual

3.9.12.3.58{0x5120} MATHFUNC_PARAM_C2_1_0_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50B8} MATHFUNC_PARAM_C2_0_0_MSB Details
Table SCU (Sensor Control Unit)-210
Register Type: RW (read/write)

Local Address: 0x5120

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Name

Type Reset Value

31..0

C2

RW

3.9.12.3.59

Description

0x00000000{0x5124} MATHFUNC_PARAM_C2_1_0_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x50BC} MATHFUNC_PARAM_C2_0_0_LSB Details
Table SCU (Sensor Control Unit)-211
Register Type: RW (read/write)

Local Address: 0x5124

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2

Reserved

Bits

Name

Type Reset Value

31..30

C2

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－429/1293－

CXD5602 User Manual

3.9.12.3.60{0x5128} MATHFUNC_PARAM_C3_1_0_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50D0} MATHFUNC_PARAM_C3_0_0_MSB Details
Table SCU (Sensor Control Unit)-212
Register Type: RW (read/write)

Local Address: 0x5128

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Name

Type Reset Value

31..0

C3

RW

3.9.12.3.61

Description

0x00000000{0x512C} MATHFUNC_PARAM_C3_1_0_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x50D4} MATHFUNC_PARAM_C3_0_0_LSB Details
Table SCU (Sensor Control Unit)-213
Register Type: RW (read/write)

Local Address: 0x512C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3Reserved

Bits

Name

Type Reset Value

31..30

C3

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－430/1293－

CXD5602 User Manual

3.9.12.3.62{0x5130} MATHFUNC_PARAM_C4_1_0_MSB Details

The IIR Parameter for Math Function 1
Refer

to

{0x50D8}

MATHFUNC_PARAM_C4_0_0_MSB

Details{0x50D8}

MATHFUNC_PARAM_C4_0_0_MSB Details
Table SCU (Sensor Control Unit)-214
Register Type: RW (read/write)

Local Address: 0x5130

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Name

Type Reset Value

31..0

C4

RW

3.9.12.3.63

Description

0x00000000{0x5134} MATHFUNC_PARAM_C4_1_0_LSB Details

The IIR Parameter for Math Function 1
Refer{0x50DC}to

MATHFUNC_PARAM_C4_0_0_LSB

Details_{0x50DC}_MATHFUNC_PARAM_C4_0_0_LSB_
Table SCU (Sensor Control Unit)-215
Register Type: RW (read/write)

Local Address: 0x5134

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4

Reserved

Bits

Name

Type Reset Value

31..30

C4

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－431/1293－

CXD5602 User Manual

3.9.12.3.64{0x5138} MATHFUNC_PARAM_1_1 Details

The IIR Parameter for Math Function 1
Refer to {0x50E0} MATHFUNC_PARAM_0_1 Details
Table SCU (Sensor Control Unit)-216
Register Type: RW (read/write)

Local Address: 0x5138

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

S2

Bits

Name

Type Reset Value

Description

31..11

Reserved

RO

0x000000Reserved

10..8

S2

RW

0x0

7..3

Reserved

RO

0x00

2..0

S1

RW

0x0

Reserved－432/1293－

Reserved

S1

CXD5602 User Manual

3.9.12.3.65{0x513C} MATHFUNC_PARAM_C0_1_1_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50E4} MATHFUNC_PARAM_C0_0_1_MSB Details
Table SCU (Sensor Control Unit)-217
Register Type: RW (read/write)

Local Address: 0x513C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Name

Type Reset Value

31..0

C0

RW

3.9.12.3.66

Description

0x00000000{0x5140} MATHFUNC_PARAM_C0_1_1_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x50E8} MATHFUNC_PARAM_C0_0_1_LSB Details
Table SCU (Sensor Control Unit)-218
Register Type: RW (read/write)

Local Address: 0x5140

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0

Reserved

Bits

Name

Type Reset Value

31..30

C0

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－433/1293－

CXD5602 User Manual

3.9.12.3.67{0x5144} MATHFUNC_PARAM_C1_1_1_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50EC} MATHFUNC_PARAM_C1_0_1_MSB Details
Table SCU (Sensor Control Unit)-219
Register Type: RW (read/write)

Local Address: 0x5144

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Name

Type Reset Value

31..0

C1

RW

3.9.12.3.68

Description

0x00000000{0x5148} MATHFUNC_PARAM_C1_1_1_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x50F0} MATHFUNC_PARAM_C1_0_1_LSB Details
Table SCU (Sensor Control Unit)-220
Register Type: RW (read/write)

Local Address: 0x5148

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1

Reserved

Bits

Name

Type Reset Value

31..30

C1

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－434/1293－

CXD5602 User Manual

3.9.12.3.69{0x514C} MATHFUNC_PARAM_C2_1_1_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50F4} MATHFUNC_PARAM_C2_0_1_MSB Details
Table SCU (Sensor Control Unit)-221
Register Type: RW (read/write)

Local Address: 0x514C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Name

Type Reset Value

31..0

C2

RW

3.9.12.3.70

Description

0x00000000{0x5150} MATHFUNC_PARAM_C2_1_1_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x50F8} MATHFUNC_PARAM_C2_0_1_LSB Details
Table SCU (Sensor Control Unit)-222
Register Type: RW (read/write)

Local Address: 0x5150

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2

Reserved

Bits

Name

Type Reset Value

31..30

C2

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－435/1293－

CXD5602 User Manual

3.9.12.3.71{0x5154} MATHFUNC_PARAM_C3_1_1_MSB Details

The IIR Parameter for Math Function 1
Refer{0x50FC}

to

MATHFUNC_PARAM_C3_0_1_MSB

Details_{0x50FC}_MATHFUNC_PARAM_C3_0_1_MSB_
Table SCU (Sensor Control Unit)-223
Register Type: RW (read/write)

Local Address: 0x5154

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Name

Type Reset Value

31..0

C3

RW

3.9.12.3.72

Description

0x00000000{0x5158} MATHFUNC_PARAM_C3_1_1_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x5100} MATHFUNC_PARAM_C3_0_1_LSB Details
Table SCU (Sensor Control Unit)-224
Register Type: RW (read/write)

Local Address: 0x5158

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3Reserved

Bits

Name

Type Reset Value

31..30

C3

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－436/1293－

CXD5602 User Manual

3.9.12.3.73{0x515C} MATHFUNC_PARAM_C4_1_1_MSB Details

The IIR Parameter for Math Function 1
Refer to {0x50FC} MATHFUNC_PARAM_C3_0_1_MSB Details
Table SCU (Sensor Control Unit)-225
Register Type: RW (read/write)

Local Address: 0x515C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Name

Type Reset Value

31..0

C4

RW

3.9.12.3.74

Description

0x00000000{0x5160} MATHFUNC_PARAM_C4_1_1_LSB Details

The IIR Parameter for Math Function 1
Refer to {0x5100} MATHFUNC_PARAM_C3_0_1_LSB Details
Table SCU (Sensor Control Unit)-226
Register Type: RW (read/write)

Local Address: 0x5160

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4

Reserved

Bits

Name

Type Reset Value

31..30

C4

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－437/1293－

CXD5602 User Manual

3.9.12.3.75{0x5164} MATHFUNC_PARAM_2_0 Details

The IIR Parameter for Math Function 2
Refer to {0x50A0} MATHFUNC_PARAM_0_0 Details
Table SCU (Sensor Control Unit)-227
Register Type: RW (read/write)

Local Address: 0x5164

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

S2

Bits

Name

Type Reset Value

Description

31..11

Reserved

RO

0x000000Reserved

10..8

S2

RW

0x0

7..3

Reserved

RO

0x00

2..0

S1

RW

0x0

Reserved－438/1293－

Reserved

S1

CXD5602 User Manual

3.9.12.3.76{0x5168} MATHFUNC_PARAM_C0_2_0_MSB Details

The IIR Parameter for Math Function 2
Refer to {0x50A4} MATHFUNC_PARAM_C0_0_0_MSB Details
Table SCU (Sensor Control Unit)-228
Register Type: RW (read/write)

Local Address: 0x5168

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Name

Type Reset Value

31..0

C0

RW

3.9.12.3.77

Description

0x00000000{0x516C} MATHFUNC_PARAM_C0_2_0_LSB Details

The IIR Parameter for Math Function 2
Refer{0x50A8}

to

MATHFUNC_PARAM_C0_0_0_LSB

Details_{0x50A8}_MATHFUNC_PARAM_C0_0_0_LSB_
Table SCU (Sensor Control Unit)-229
Register Type: RW (read/write)

Local Address: 0x516C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0

Reserved

Bits

Name

Type Reset Value

31..30

C0

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－439/1293－

CXD5602 User Manual

3.9.12.3.78{0x5170} MATHFUNC_PARAM_C1_2_0_MSB Details

The IIR Parameter for Math Function 2
Refer{0x50B0}to

MATHFUNC_PARAM_C1_0_0_MSB

Details_{0x50B0}_MATHFUNC_PARAM_C1_0_0_MSB_
Table SCU (Sensor Control Unit)-230
Register Type: RW (read/write)

Local Address: 0x5170

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Name

Type Reset Value

31..0

C1

RW

3.9.12.3.79

Description

0x00000000{0x5174} MATHFUNC_PARAM_C1_2_0_LSB Details

The IIR Parameter for Math Function 2
Refer to {0x50B4} MATHFUNC_PARAM_C1_0_0_LSB Details
Table SCU (Sensor Control Unit)-231
Register Type: RW (read/write)

Local Address: 0x5174

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1

Reserved

Bits

Name

Type Reset Value

31..30

C1

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－440/1293－

CXD5602 User Manual

3.9.12.3.80{0x5178} MATHFUNC_PARAM_C2_2_0_MSB Details

The IIR Parameter for Math Function 2
Refer to{0x50B8} MATHFUNC_PARAM_C2_0_0_MSB Details
Table SCU (Sensor Control Unit)-232
Register Type: RW (read/write)

Local Address: 0x5178

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Name

Type Reset Value

31..0

C2

RW

3.9.12.3.81

Description

0x00000000{0x517C} MATHFUNC_PARAM_C2_2_0_LSB Details

The IIR Parameter for Math Function 2
Refer to {0x50BC} MATHFUNC_PARAM_C2_0_0_LSB Details
Table SCU (Sensor Control Unit)-233
Register Type: RW (read/write)

Local Address: 0x517C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2

Reserved

Bits

Name

Type Reset Value

31..30

C2

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－441/1293－

CXD5602 User Manual

3.9.12.3.82{0x5180} MATHFUNC_PARAM_C3_2_0_MSB Details

The IIR Parameter for Math Function 2
Refer to {0x50D0} MATHFUNC_PARAM_C3_0_0_MSB Details
Table SCU (Sensor Control Unit)-234
Register Type: RW (read/write)

Local Address: 0x5180

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Name

Type Reset Value

31..0

C3

RW

3.9.12.3.83

Description

0x00000000{0x5184} MATHFUNC_PARAM_C3_2_0_LSB Details

The IIR Parameter for Math Function 2
Refer to {0x50D4} MATHFUNC_PARAM_C3_0_0_LSB Details
Table SCU (Sensor Control Unit)-235
Register Type: RW (read/write)

Local Address: 0x5184

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3Reserved

Bits

Name

Type Reset Value

31..30

C3

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－442/1293－

CXD5602 User Manual

3.9.12.3.84{0x5188} MATHFUNC_PARAM_C4_2_0_MSB Details

The IIR Parameter for Math Function 2
Refer to {0x50D8} MATHFUNC_PARAM_C4_0_0_MSB Details
Table SCU (Sensor Control Unit)-236
Register Type: RW (read/write)

Local Address: 0x5188

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Name

Type Reset Value

31..0

C4

RW

3.9.12.3.85

Description

0x00000000{0x518C} MATHFUNC_PARAM_C4_2_0_LSB Details

The IIR Parameter for Math Function 2
Refer to {0x50DC} MATHFUNC_PARAM_C4_0_0_LSB Details
Table SCU (Sensor Control Unit)-237
Register Type: RW (read/write)

Local Address: 0x518C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4

Reserved

Bits

Name

Type Reset Value

31..30

C4

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－443/1293－

CXD5602 User Manual

3.9.12.3.86{0x5190} MATHFUNC_PARAM_2_1 Details

The IIR Parameter for Math Function 2
Table SCU (Sensor Control Unit)-238
Register Type: RW (read/write)

Local Address: 0x5190

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

S2

Bits

Name

Type Reset Value

Description

31..11

Reserved

RO

0x000000Reserved

10..8

S2

RW

0x0

7..3

Reserved

RO

0x00

2..0

S1

RW

0x0

Reserved－444/1293－

Reserved

S1

CXD5602 User Manual

3.9.12.3.87{0x5194} MATHFUNC_PARAM_C0_2_1_MSB Details

The IIR Parameter for Math Function 2
Refer to {0x50E4} MATHFUNC_PARAM_C0_0_1_MSB Details
Table SCU (Sensor Control Unit)-239
Register Type: RW (read/write)

Local Address: 0x5194

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0
Bits

Name

Type Reset Value

31..0

C0

RW

3.9.12.3.88

Description

0x00000000{0x5198} MATHFUNC_PARAM_C0_2_1_LSB Details

The IIR Parameter for Math Function 2
Refer{0x50E8}

to

MATHFUNC_PARAM_C0_0_1_LSB

Details_{0x50E8}_MATHFUNC_PARAM_C0_0_1_LSB_
Table SCU (Sensor Control Unit)-240
Register Type: RW (read/write)

Local Address: 0x5198

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C0

Reserved

Bits

Name

Type Reset Value

31..30

C0

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－445/1293－

CXD5602 User Manual

3.9.12.3.89{0x519C} MATHFUNC_PARAM_C1_2_1_MSB Details

The IIR Parameter for Math Function 2
Refer{0x50EC}to

MATHFUNC_PARAM_C1_0_1_MSB

Details_{0x50EC}_MATHFUNC_PARAM_C1_0_1_MSB_
Table SCU (Sensor Control Unit)-241
Register Type: RW (read/write)

Local Address: 0x519C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1
Bits

Name

Type Reset Value

31..0

C1

RW

3.9.12.3.90

Description

0x00000000{0x51A0} MATHFUNC_PARAM_C1_2_1_LSB Details

The IIR Parameter for Math Function 2
Refer{0x50F0}to

MATHFUNC_PARAM_C1_0_1_LSB

Details_{0x50F0}_MATHFUNC_PARAM_C1_0_1_LSB_
Table SCU (Sensor Control Unit)-242
Register Type: RW (read/write)

Local Address: 0x51A0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C1

Reserved

Bits

Name

Type Reset Value

31..30

C1

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－446/1293－

CXD5602 User Manual

3.9.12.3.91{0x51A4} MATHFUNC_PARAM_C2_2_1_MSB Details

The IIR Parameter for Math Function 2
Refer

to

{0x50F4}

MATHFUNC_PARAM_C2_0_1_MSB

Details_{0x50F4}_MATHFUNC_PARAM_C2_0_1_MSB_
Table SCU (Sensor Control Unit)-243
Register Type: RW (read/write)

Local Address: 0x51A4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2
Bits

Name

Type Reset Value

31..0

C2

RW

3.9.12.3.92

Description

0x00000000{0x51A8} MATHFUNC_PARAM_C2_2_1_LSB Details

The IIR Parameter for Math Function 2
Refer to{0x50F8} MATHFUNC_PARAM_C2_0_1_LSB Details
Table SCU (Sensor Control Unit)-244
Register Type: RW (read/write)

Local Address: 0x51A8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2

Reserved

Bits

Name

Type Reset Value

31..30

C2

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－447/1293－

CXD5602 User Manual

3.9.12.3.93{0x51AC} MATHFUNC_PARAM_C3_2_1_MSB Details

The IIR Parameter for Math Function 2
Refer{0x50FC}

to

MATHFUNC_PARAM_C3_0_1_MSB

Details_{0x50FC}_MATHFUNC_PARAM_C3_0_1_MSB_
Table SCU (Sensor Control Unit)-245
Register Type: RW (read/write)

Local Address: 0x51AC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3
Bits

Name

Type Reset Value

31..0

C3

RW

3.9.12.3.94

Description

0x00000000{0x51B0} MATHFUNC_PARAM_C3_2_1_LSB Details

The IIR Parameter for Math Function 2
Refer

MATHFUNC_PARAM_C3_0_1_LSB

to{0x5100}

Details_{0x5100}_MATHFUNC_PARAM_C3_0_1_LSB_
Table SCU (Sensor Control Unit)-246
Register Type: RW (read/write)

Local Address: 0x51B0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3Reserved

Bits

Name

Type Reset Value

31..30

C3

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－448/1293－

CXD5602 User Manual

3.9.12.3.95{0x51B4} MATHFUNC_PARAM_C4_2_1_MSB Details

The IIR Parameter for Math Function 2
Refer{0x50FC}

to

MATHFUNC_PARAM_C3_0_1_MSB

Details_{0x50FC}_MATHFUNC_PARAM_C3_0_1_MSB_
Table SCU (Sensor Control Unit)-247
Register Type: RW (read/write)

Local Address: 0x51B4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4
Bits

Name

Type Reset Value

31..0

C4

RW

3.9.12.3.96

Description

0x00000000{0x51B8} MATHFUNC_PARAM_C4_2_1_LSB Details

The IIR Parameter for Math Function 2
Refer to {0x5108} MATHFUNC_PARAM_C4_0_1_LSB Details
Table SCU (Sensor Control Unit)-248
Register Type: RW (read/write)

Local Address: 0x51B8Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4

Reserved

Bits

Name

Type Reset Value

31..30

C4

RW

0x0

29..0

Reserved

RO

0x00000000

Description
Reserved－449/1293－

CXD5602 User Manual

3.9.12.3.97{0x51BC} EVENT_PARAM0_THRESH Details

status(upper, lower)

EVENT_PARAMX_THRESH: UTHRESH

Threshold Level (top)(unsigned 16bit)

EVENT_PARAMX_THRESH: LTHRESH

Threshold Level (bottom)(unsigned 16bit)

Continuous Match Detection 1

Continuous Match Detection 0

Comparator
input Data
(unsigned 16bit)

status(upper, lower)

2

Number of status continuity(unsigned 16bit)
Number of status continuity(unsigned 16bit)

status(upper, lower)

2

Number of status continuity(unsigned 16bit)
Number of status continuity(unsigned 16bit)

EVENT_PARAMX_COUNT0: UCOUNTEVENT_PARAMX_COUNT0: LCOUNTEVENT_PARAMX_COUNT1: UCOUNTEVENT_PARAMX_COUNT1: LCOUNTInterrupt Singal Generator
Interrupt

statusEVENT_PARAMX_COUNT2:
RISE_INT_EN

Rise interrupt enable

EVENT_PARAMX_COUNT2:
FALL_INT_EN
EVENT_PARAMX_COUNT2:
DELAY_SAMPLE_R

Fall interrupt enable
Rise interrupt delay time
(unsigned 16bit)
Fall interrupt delay time
(unsigned 16bit)

EVENT_PARAMX_COUNT2:
DELAY_SAMPLE_F

Figure SCU (Sensor Control Unit)-115 Excess Detection Overview
Excess detection for Math Function 0
Table SCU (Sensor Control Unit)-249
Register Type: RW (read/write)

Local Address: 0x51BC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTHRESHUTHRESH

Bits

Name

Type Reset Value

Description

31..16

LTHRESH

RW

0x0000

Reference value for excess detection (bottom)

15..0

UTHRESH

RW

0x0000

Reference value for excess detection (top)－450/1293－

2

CXD5602 User Manual

3.9.12.3.98{0x51C0} EVENT_PARAM0_COUNT0 Details

Excess detection for Math Function 0
Table SCU (Sensor Control Unit)-250
Register Type: RW (read/write)

Local Address: 0x51C0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCOUNT

Bits

Name

UCOUNT

Type

Reset
Value

31..16 LCOUNT

RW

0x000015..0RW

0x0000UCOUNT

3.9.12.3.99

Description
Designates how many times the input value exceeds the top
threshold before the event ignition
Designates how many times the input value exceeds the bottom
threshold before the event ignition{0x51C4} EVENT_PARAM0_COUNT1 Details

Excess detection for Math Function 0
Table SCU (Sensor Control Unit)-251
Register Type: RW (read/write)

Local Address: 0x51C4Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCOUNT

Bits

Name

UCOUNT

Type

Reset
Value

31..16 LCOUNT

RW

0x000015..0RW

0x0000UCOUNT

Description
Designates how many times the input value exceeds the top
threshold before the event ignition
Designates how many times the input value exceeds the bottom
threshold before the event ignition－451/1293－

CXD5602 User Manual

3.9.12.3.100{0x51C8} EVENT_PARAM0_COUNT2 Details

Excess detection for Math Function 0
Table SCU (Sensor Control Unit)-252
Register Type: RW (read/write)

Local Address: 0x51C8Reset Value: 0x00000000

Reserved

Bits

Name

31..9 Reserved

Reserved

RISE_INT_EN

FALL_INT_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Type Reset Value Description
RO

0x000000Reserved
Interrupt occurrence permission in the case that the status

8

FALL_INT_EN RW

0x0

has changed from “determined serially that the input values
are bigger than the top threshold” to “determined seriallythat the input values are smaller than the bottom threshold”.

7..1

Reserved

RO

0x00

Reserved
Interrupt occurrence permission in the case that the status
has changed from “determined serially that the input values

0

RISE_INT_EN

RW

0x0

are smaller than the bottom threshold” to “determined
serially that the input values are bigger than the top
threshold”.

－452/1293－

CXD5602 User Manual

3.9.12.3.101{0x51CC} EVENT_PARAM1_THRESH Details

Excess detection for Math Function 1
Table SCU (Sensor Control Unit)-253
Register Type: RW (read/write)

Local Address: 0x51CC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTHRESHUTHRESH

Bits

Name

Type Reset Value

Description

31..16

LTHRESH

RW

0x0000

Reference value for excess detection (bottom)

15..0

UTHRESH

RW

0x0000

Reference value for excess detection (top)－453/1293－

CXD5602 User Manual

3.9.12.3.102{0x51D0} EVENT_PARAM1_COUNT0 Details

Excess detection for Math Function 1
Table SCU (Sensor Control Unit)-254
Register Type: RW (read/write)

Local Address: 0x51D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCOUNT

Bits

Name

UCOUNT

Type

Reset
Value

31..16 LCOUNT RW

0x000015..0

0x0000UCOUNT RW

3.9.12.3.103

Description
Designates how many times the input value exceeds the top threshold
before the event ignition
Designates how many times the input value exceeds the bottom
threshold before the event ignition{0x51D4} EVENT_PARAM1_COUNT1 Details

Excess detection for Math Function 1
Table SCU (Sensor Control Unit)-255
Register Type: RW (read/write)

Local Address: 0x51D4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCOUNT

Bits

Name

UCOUNT

Type

Reset
Value

31..16 LCOUNT RW

0x000015..0

0x0000UCOUNT RW

Description
Designates how many times the input value exceeds the top threshold
before the event ignition
Designates how many times the input value exceeds the bottom
threshold before the event ignition－454/1293－

CXD5602 User Manual

3.9.12.3.104{0x51D8} EVENT_PARAM1_COUNT2 Details

Excess detection for Math Function 1
Table SCU (Sensor Control Unit)-256
Register Type: RW (read/write)

Local Address: 0x51D8

Reset Value: 0x00000000

Reserved

Bits

Name

Type

31..9 Reserved

RO

Reset
Value

Reserved

RISE_INT_EN

FALL_INT_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description

0x000000 ReservedInterrupt occurrence permission in the case that the status has

8

FALL_INT_EN RW

0x0changed from “determined serially that the input values arebigger than the top threshold” to “determined serially that the
input values are smaller than the bottom threshold”.

7..1

Reserved

RO

0x00

Reserved
Interrupt occurrence permission in the case that the status has

0

RISE_INT_EN

RW

0x0

changed from “determined serially that the input values are
smaller than the bottom threshold” to “determined serially thatthe input values are bigger than the top threshold”.

－455/1293－

CXD5602 User Manual

3.9.12.3.105{0x51DC} EVENT_PARAM2_THRESH Details

Excess detection for Math Function 2
Table SCU (Sensor Control Unit)-257
Register Type: RW (read/write)

Local Address: 0x51DC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTHRESHUTHRESH

Bits

Name

Type Reset Value

Description

31..16

LTHRESH

RW

0x0000Bottom threshold

15..0

UTHRESH

RW

0x0000Top threshold－456/1293－

CXD5602 User Manual

3.9.12.3.106{0x51E0} EVENT_PARAM2_COUNT0 Details

Excess detection for Math Function 2
Table SCU (Sensor Control Unit)-258
Register Type: RW (read/write)

Local Address: 0x51E0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCOUNT

Bits

Name

UCOUNT

Type

Reset
Value

31..16 LCOUNT RW

0x000015..0

0x0000UCOUNT RW

3.9.12.3.107

Description
Designates how many times the input value exceeds the top threshold
before the event ignition
Designates how many times the input value exceeds the bottom
threshold before the event ignition{0x51E4} EVENT_PARAM2_COUNT1 Details

Excess detection for Math Function 2
Table SCU (Sensor Control Unit)-259
Register Type: RW (read/write)

Local Address: 0x51E4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCOUNT

Bits

Name

UCOUNT

Type

Reset
Value

31..16 LCOUNT RW

0x000015..0

0x0000UCOUNT RW

Description
Designates how many times the input value exceeds the top threshold
before the event ignition
Designates how many times the input value exceeds the bottom
threshold before the event ignition－457/1293－

CXD5602 User Manual

3.9.12.3.108{0x51E8} EVENT_PARAM2_COUNT2 Details

Excess detection for Math Function 2
Table SCU (Sensor Control Unit)-260
Register Type: RW (read/write)

Local Address: 0x51E8Reset Value: 0x00000000

Reserved

Bits

Name

Type

31..9 Reserved

RO

Reset
Value

Reserved

RISE_INT_EN

FALL_INT_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description

0x000000 ReservedInterrupt occurrence permission in the case that the status has

8

FALL_INT_EN RW

0x0changed from “determined serially that the input values arebigger than the top threshold” to “determined serially that the
input values are smaller than the bottom threshold”.

7..1

Reserved

RO

0x00

Reserved
Interrupt occurrence permission in the case that the status has

0

RISE_INT_EN

RW

0x0

changed from “determined serially that the input values are
smaller than the bottom threshold” to “determined serially thatthe input values are bigger than the top threshold”.

－458/1293－

CXD5602 User Manual

3.9.12.3.109{0x51EC} EVENT_PARAM0_DELAY_SAMPLE Details
Table SCU (Sensor Control Unit)-261
Register Type: RW (read/write)

Local Address: 0x51EC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELAY_SAMPLE_F
Bits

Name

DELAY_SAMPLE_R
Type Reset Value Description
After the conditions of the event ignition is31..16 DELAY_SAMPLE_F

RW

0x0000fulfilled, this register designates how many
samples must be taken before the event ignition.
After the conditions of the event ignition is

15..0

DELAY_SAMPLE_R

RW

0x0000fulfilled, this register designates how many
samples must be taken before the event ignition.

3.9.12.3.110{0x51F0} EVENT_PARAM1_DELAY_SAMPLE Details
Table SCU (Sensor Control Unit)-262
Register Type: RW (read/write)

Local Address: 0x51F0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELAY_SAMPLE_F
Bits

Name

DELAY_SAMPLE_R
Type Reset Value Description
After the conditions of the event ignition is fulfilled,

31..16 DELAY_SAMPLE_F RW

0x0000this register designates how many samples must be
taken before the event ignition.
After the conditions of the event ignition is fulfilled,

15..0

DELAY_SAMPLE_R RW

0x0000this register designates how many samples must be
taken before the event ignition.

－459/1293－

CXD5602 User Manual

3.9.12.3.111{0x51F4} EVENT_PARAM2_DELAY_SAMPLE Details
Table SCU (Sensor Control Unit)-263
Register Type: RW (read/write)

Local Address: 0x51F4Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELAY_SAMPLE_F
Bits

Name

DELAY_SAMPLE_R
Type Reset Value Description
After the conditions of the event ignition is fulfilled,

31..16 DELAY_SAMPLE_F RW

0x0000this register designates how many samples must be
taken before the event ignition.
After the conditions of the event ignition is fulfilled,

15..0

DELAY_SAMPLE_R RW

0x0000this register designates how many samples must be
taken before the event ignition.

－460/1293－

CXD5602 User Manual

3.9.12.3.112{0x5200} EVENT_TIMESTAMP0_R_MSB Details
Table SCU (Sensor Control Unit)-264
Register Type: RO (read only)

Local Address: 0x5200

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMESTAMP
Bits

Name

Type Reset Value

31..0

TIMESTAMP

RO

3.9.12.3.113

0x00000000

Description
Time stamp value (integer part of second) atthe EVENT0 occurrence{0x5204} EVENT_TIMESTAMP0_R_LSB Details
Table SCU (Sensor Control Unit)-265
Register Type: RO (read only)

Local Address: 0x5204

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

TIMESTAMP

Bits

Name

Type Reset Value

Description

31..15Reserved

RO

0x00000

Reserved

14..0

TIMESTAMP

RO

0x0000Time stamp value (second after the decimal
point) at the EVENT0 occurrence－461/1293－

CXD5602 User Manual

3.9.12.3.114{0x5208} EVENT_TIMESTAMP1_R_MSB Details
Table SCU (Sensor Control Unit)-266
Register Type: RO (read only)

Local Address: 0x5208

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMESTAMP
Bits

Name

Type Reset Value

31..0

TIMESTAMP

RO

3.9.12.3.115

0x00000000

Description
Time stamp value (integer part of second) atthe EVENT1 occurrence{0x520C} EVENT_TIMESTAMP1_R_LSB Details
Table SCU (Sensor Control Unit)-267
Register Type: RO (read only)

Local Address: 0x520C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

TIMESTAMP

Bits

Name

Type Reset Value

Description

31..15Reserved

RO

0x00000

Reserved

14..0

TIMESTAMP

RO

0x0000Time stamp value (second after the decimal
point at the EVENT1 occurrence－462/1293－

CXD5602 User Manual

3.9.12.3.116{0x5210} EVENT_TIMESTAMP2_R_MSB Details
Table SCU (Sensor Control Unit)-268
Register Type: RO (read only)

Local Address: 0x5210

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMESTAMP
Bits

Name

Type Reset Value

31..0

TIMESTAMP

RO

3.9.12.3.117

0x00000000

Description
Time stamp value (integer part of second) atthe EVENT2 occurrence{0x5214} EVENT_TIMESTAMP2_R_LSB Details
Table SCU (Sensor Control Unit)-269
Register Type: RO (read only)

Local Address: 0x5214

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

TIMESTAMP

Bits

Name

Type Reset Value

Description

31..15Reserved

RO

0x00000

Reserved

14..0

TIMESTAMP

RO

0x0000Time stamp value (second after the decimal
point) at the EVENT2 occurrence－463/1293－

CXD5602 User Manual

3.9.12.3.118{0x5218} EVENT_TIMESTAMP0_F_MSB Details
Table SCU (Sensor Control Unit)-270
Register Type: RO (read only)

Local Address: 0x5218

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMESTAMP
Bits

Name

Type Reset Value

31..0

TIMESTAMP

RO

3.9.12.3.1190x00000000

Description
Time stamp value (integer part of second) atthe EVENT0 occurrence{0x521C} EVENT_TIMESTAMP0_F_LSB Details
Table SCU (Sensor Control Unit)-271
Register Type: RO (read only)

Local Address: 0x521C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

TIMESTAMP

Bits

Name

Type Reset Value

Description

31..15Reserved

RO

0x00000

Reserved

14..0

TIMESTAMP

RO

0x0000Time stamp value (second after the decimal
point) at the EVENT0 occurrence－464/1293－

CXD5602 User Manual

3.9.12.3.120{0x5220} EVENT_TIMESTAMP1_F_MSB Details
Table SCU (Sensor Control Unit)-272
Register Type: RO (read only)

Local Address: 0x5220

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMESTAMP
Bits

Name

Type Reset Value

31..0

TIMESTAMP

RO

3.9.12.3.1210x00000000

Description
Time stamp value (integer part of second) atthe EVENT1 occurrence{0x5224} EVENT_TIMESTAMP1_F_LSB Details
Table SCU (Sensor Control Unit)-273
Register Type: RO (read only)

Local Address: 0x5224

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

TIMESTAMP

Bits

Name

Type Reset Value

Description

31..15Reserved

RO

0x00000

Reserved

14..0

TIMESTAMP

RO

0x0000Time stamp value (second after the decimal
point) at the EVENT1 occurrence－465/1293－

CXD5602 User Manual

3.9.12.3.122{0x5228} EVENT_TIMESTAMP2_F_MSB Details
Table SCU (Sensor Control Unit)-274
Register Type: RO (read only)

Local Address: 0x5228

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMESTAMP
Bits

Name

Type Reset Value

31..0

TIMESTAMP

RO

3.9.12.3.123

0x00000000

Description
Time stamp value (integer part of second) atthe EVENT2 occurrence{0x522C} EVENT_TIMESTAMP2_F_LSB Details
Table SCU (Sensor Control Unit)-275
Register Type: RO (read only)

Local Address: 0x522C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

TIMESTAMP

Bits

Name

Type Reset Value

Description

31..15Reserved

RO

0x00000

Reserved

14..0

TIMESTAMP

RO

0x0000Time stamp value (second after the decimal
point) at the EVENT2 occurrence－466/1293－

CXD5602 User Manual

3.9.12.3.124{0x5230} FIFO_WRITE_CTRL Details
Table SCU (Sensor Control Unit)-276
Register Type: RW (read/write)

Local Address: 0x5230

Reset Value: 0x00000000

Reserved

Bits

Name

Type

Reset Value

Description

31..6 Reserved

RO

0x0000000

Reserved

5

EVENT2_F

RW

0x0

4

EVENT1_F

RW

0x0

3

EVENT0_F

RW

0x0

2

EVENT2_R

RW

0x0

1

EVENT1_R

RW

0x0
The status of MATH_EVENT.

0EVENT0_R

RW

0x0

It is referred when writing data to the FIFO.
It can be cleared by writing “1”.

－467/1293－

EVENT0_R

EVENT2_F
EVENT1_F
EVENT0_F
EVENT2_R
EVENT1_R

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.3.125{0x5400} INT_ENABLE_MAIN Details
Table SCU (Sensor Control Unit)-277
Register Type: RW (read/write)

Local Address: 0x5400

Reset Value: 0x00000000

Reset

Bits

Name

Type

31

Reserved

RO

0x0

30

MATH_EVENT2_F

RW

0x0

29

MATH_EVENT1_F

RW

0x0

28

MATH_EVENT0_F

RW

0x0

27

ISOP3

RW

0x0

26

ISOP2

RW

0x0

25

ISOP1

RW

0x0

24

ISOP0

RW

0x0

23

Reserved

RO

0x0

22

D1_R3_CH_ALMOST_FULL RW

0x0

21

D0_R3_CH_ALMOST_FULL RW

0x0

20

N7_R1_C_ALMOST_FULL

RW

0x0

19

N6_R1_C_ALMOST_FULL

RW

0x0

18

N5_R1_C_ALMOST_FULL

RW

0x0

17

N4_R1_C_ALMOST_FULL

RW

0x0

16

N3_R1_C_ALMOST_FULL

RW

0x0

15

N2_R1_C_ALMOST_FULL

RW

0x0

14

N1_R1_C_ALMOST_FULL

RW

0x0

13

N0_R1_C_ALMOST_FULL

RW

0x0

12

D1_R2_C_ALMOST_FULL

RW

0x0

Value

Description
Reserved

Reserved－468/1293－

SPI

Reserved
MATH_EVENT2_F
MATH_EVENT1_F
MATH_EVENT0_F
ISOP3
ISOP2
ISOP1
ISOP0
Reserved
D1_R3_CH_ALMOST_FULL
D0_R3_CH_ALMOST_FULL
N7_R1_C_ALMOST_FULL
N6_R1_C_ALMOST_FULL
N5_R1_C_ALMOST_FULL
N4_R1_C_ALMOST_FULL
N3_R1_C_ALMOST_FULL
N2_R1_C_ALMOST_FULL
N1_R1_C_ALMOST_FULL
N0_R1_C_ALMOST_FULL
D1_R2_C_ALMOST_FULL
D1_R1_C_ALMOST_FULL
D0_R2_C_ALMOST_FULL
D0_R1_C_ALMOST_FULL
MATH_EVENT2_R
MATH_EVENT1_R
MATH_EVENT0_R
HPADC1_ALMOST_FULL
HPADC0_ALMOST_FULL
LPADC_ALMOST_FULL
I2C1
I2C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

11

D1_R1_C_ALMOST_FULL

RW

0x0

10

D0_R2_C_ALMOST_FULL

RW

0x0

9

D0_R1_C_ALMOST_FULL

RW

0x0

8

MATH_EVENT2_R

RW

0x0

7

MATH_EVENT1_R

RW

0x0

6

MATH_EVENT0_R

RW

0x0

5

HPADC1_ALMOST_FULL

RW

0x0

4

HPADC0_ALMOST_FULL

RW

0x0

3

LPADC_ALMOST_FULL

RW

0x0

2

I2C1

RW

0x0

1

I2C0

RW

0x0
Interrupt permission for the SPI or Math Function

0

SPI

RW

0x0

Event 0.
The interrupt is permitted by writing “1”.
Writing “0” cannot prohibit the interrupt.

－469/1293－

CXD5602 User Manual

3.9.12.3.126{0x5404} INT_DISABLE_MAIN Details
Table SCU (Sensor Control Unit)-278
Register Type: RW (read/write)

Local Address: 0x5404

Reset Value: 0x00000000

Reset

Bits

Name

Type

31

Reserved

RO

0x0

30

MATH_EVENT2_F

RW

0x0

29

MATH_EVENT1_F

RW

0x0

28

MATH_EVENT0_F

RW

0x0

27

ISOP3

RW

0x0

26

ISOP2

RW

0x0

25

ISOP1

RW

0x0

24

ISOP0

RW

0x0

23

Reserved

RO

0x0

22

D1_R3_CH_ALMOST_FULL RW

0x0

21

D0_R3_CH_ALMOST_FULL RW

0x0

20

N7_R1_C_ALMOST_FULL

RW

0x0

19

N6_R1_C_ALMOST_FULL

RW

0x0

18

N5_R1_C_ALMOST_FULL

RW

0x0

17

N4_R1_C_ALMOST_FULL

RW

0x0

16

N3_R1_C_ALMOST_FULL

RW

0x0

15

N2_R1_C_ALMOST_FULL

RW

0x0

14

N1_R1_C_ALMOST_FULL

RW

0x0

13

N0_R1_C_ALMOST_FULL

RW

0x0

12

D1_R2_C_ALMOST_FULL

RW

0x0

Value

Description
Reserved

Reserved－470/1293－

SPI

Reserved
MATH_EVENT2_F
MATH_EVENT1_F
MATH_EVENT0_F
ISOP3
ISOP2
ISOP1
ISOP0
Reserved
D1_R3_CH_ALMOST_FULL
D0_R3_CH_ALMOST_FULL
N7_R1_C_ALMOST_FULL
N6_R1_C_ALMOST_FULL
N5_R1_C_ALMOST_FULL
N4_R1_C_ALMOST_FULL
N3_R1_C_ALMOST_FULL
N2_R1_C_ALMOST_FULL
N1_R1_C_ALMOST_FULL
N0_R1_C_ALMOST_FULL
D1_R2_C_ALMOST_FULL
D1_R1_C_ALMOST_FULL
D0_R2_C_ALMOST_FULL
D0_R1_C_ALMOST_FULL
MATH_EVENT2_R
MATH_EVENT1_R
MATH_EVENT0_R
HPADC1_ALMOST_FULL
HPADC0_ALMOST_FULL
LPADC_ALMOST_FULL
I2C1
I2C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

11

D1_R1_C_ALMOST_FULL

RW

0x0

10

D0_R2_C_ALMOST_FULL

RW

0x0

9

D0_R1_C_ALMOST_FULL

RW

0x0

8

MATH_EVENT2_R

RW

0x0

7

MATH_EVENT1_R

RW

0x0

6

MATH_EVENT0_R

RW

0x0

5

HPADC1_ALMOST_FULL

RW

0x0

4

HPADC0_ALMOST_FULL

RW

0x0

3

LPADC_ALMOST_FULL

RW

0x0

2

I2C1

RW

0x0

1

I2C0

RW

0x0
Interrupt prohibition for the SPI.

0

SPI

RW

0x0

The interrupt is prohibited by writing “1”.
Writing “0” cannot permit the interrupt.

－471/1293－

CXD5602 User Manual

3.9.12.3.127{0x5408} INT_CLEAR_MAIN Details
Table SCU (Sensor Control Unit)-279
Register Type: WO (write only)

Local Address: 0x5408

Reset Value: 0x00000000

Bits

Name

Type Reset Value Description

31

Reserved

WO

0x0

30

MATH_EVENT2_F

WO

0x0

29

MATH_EVENT1_F

WO

0x0

28

MATH_EVENT0_F

WO

0x0

27

ISOP3

WO

0x0

26

ISOP2

WO

0x0

25

ISOP1

WO

0x0

24

ISOP0

WO

0x0

23

Reserved

WO

0x0

22

D1_R3_CH_ALMOST_FULL WO

0x0

21

D0_R3_CH_ALMOST_FULL WO

0x0

20

N7_R1_C_ALMOST_FULL

WO

0x0

19

N6_R1_C_ALMOST_FULL

WO

0x0

18

N5_R1_C_ALMOST_FULL

WO

0x0

17

N4_R1_C_ALMOST_FULL

WO

0x0

16

N3_R1_C_ALMOST_FULL

WO

0x0

15

N2_R1_C_ALMOST_FULL

WO

0x0

14

N1_R1_C_ALMOST_FULL

WO

0x0

13

N0_R1_C_ALMOST_FULL

WO

0x0

12

D1_R2_C_ALMOST_FULL

WO

0x0

11

D1_R1_C_ALMOST_FULL

WO

0x0

Reserved

Reserved－472/1293－

Reserved

Reserved
MATH_EVENT2_F
MATH_EVENT1_F
MATH_EVENT0_F
ISOP3
ISOP2
ISOP1
ISOP0
Reserved
D1_R3_CH_ALMOST_FULL
D0_R3_CH_ALMOST_FULL
N7_R1_C_ALMOST_FULL
N6_R1_C_ALMOST_FULL
N5_R1_C_ALMOST_FULL
N4_R1_C_ALMOST_FULL
N3_R1_C_ALMOST_FULL
N2_R1_C_ALMOST_FULL
N1_R1_C_ALMOST_FULL
N0_R1_C_ALMOST_FULL
D1_R2_C_ALMOST_FULL
D1_R1_C_ALMOST_FULL
D0_R2_C_ALMOST_FULL
D0_R1_C_ALMOST_FULL
MATH_EVENT2_R
MATH_EVENT1_R
MATH_EVENT0_R
HPADC1_ALMOST_FULL
HPADC0_ALMOST_FULL
LPADC_ALMOST_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

10

D0_R2_C_ALMOST_FULL

WO

0x0

9

D0_R1_C_ALMOST_FULL

WO

0x0

8

MATH_EVENT2_R

WO

0x0

7

MATH_EVENT1_R

WO

0x0

6

MATH_EVENT0_R

WO

0x0

5

HPADC1_ALMOST_FULL

WO

0x0

4

HPADC0_ALMOST_FULL

WO

0x0

3

LPADC_ALMOST_FULL

WO

0x0

2..0

Reserved

WO

0x0

Reserved－473/1293－

CXD5602 User Manual

3.9.12.3.128{0x540C} LEVEL_SEL_MAIN Details
Table SCU (Sensor Control Unit)-280
Register Type: RW (read/write)

Local Address: 0x540C

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..28 Reserved

RO

0x0

27

ISOP3

RW

0x0

26

ISOP2

RW

0x0

25

ISOP1

RW

0x0

24

ISOP0

RW

0x0

23

Reserved

RO

0x0

22

D1_R3_CH_ALMOST_FULL RW

0x0

21

D0_R3_CH_ALMOST_FULL RW

0x0

20

N7_R1_C_ALMOST_FULL

RW

0x0

19

N6_R1_C_ALMOST_FULL

RW

0x0

18

N5_R1_C_ALMOST_FULL

RW

0x0

17

N4_R1_C_ALMOST_FULL

RW

0x0

16

N3_R1_C_ALMOST_FULL

RW

0x0

15

N2_R1_C_ALMOST_FULL

RW

0x0

14

N1_R1_C_ALMOST_FULL

RW

0x0

13

N0_R1_C_ALMOST_FULL

RW

0x0

12

D1_R2_C_ALMOST_FULL

RW

0x0

11

D1_R1_C_ALMOST_FULL

RW

0x0

10

D0_R2_C_ALMOST_FULL

RW

0x0

9

D0_R1_C_ALMOST_FULL

RW

0x0

Description
Reserved

Reserved－474/1293－

Reserved

HPADC1_ALMOST_FULL
HPADC0_ALMOST_FULL
LPADC_ALMOST_FULL

Reserved

Reserved

ISOP3
ISOP2
ISOP1
ISOP0
Reserved
D1_R3_CH_ALMOST_FULL
D0_R3_CH_ALMOST_FULL
N7_R1_C_ALMOST_FULL
N6_R1_C_ALMOST_FULL
N5_R1_C_ALMOST_FULL
N4_R1_C_ALMOST_FULL
N3_R1_C_ALMOST_FULL
N2_R1_C_ALMOST_FULL
N1_R1_C_ALMOST_FULL
N0_R1_C_ALMOST_FULL
D1_R2_C_ALMOST_FULL
D1_R1_C_ALMOST_FULL
D0_R2_C_ALMOST_FULL
D0_R1_C_ALMOST_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

8..6

Reserved

RO

0x0

5

HPADC1_ALMOST_FULL

RW

0x0

4

HPADC0_ALMOST_FULL

RW

0x0

Reserved

Set “1” when you want to use interrupt
3

LPADC_ALMOST_FULL

RW

0x0

LPADC_ALMOST_FULL as a level interrupt.
Set “0” when you use the interrupt as an edge
detection.

2..0

ReservedRO

0x0

Reserved－475/1293－

CXD5602 User Manual

3.9.12.3.129{0x5410} INT_RAW_STT_MAIN Details
Table SCU (Sensor Control Unit)-281
Register Type: RO (read only)

Local Address: 0x5410

Reset Value: 0x00000000

Bits

Name

Type Reset Value Description

31

Reserved

RO

0x0

30

MATH_EVENT2_F

RO

0x0

29

MATH_EVENT1_F

RO

0x0

28

MATH_EVENT0_F

RO

0x0

27

ISOP3

RO

0x0

26

ISOP2

RO

0x0

25

ISOP1

RO

0x0

24

ISOP0

RO

0x0

23

Reserved

RO

0x0

22

D1_R3_CH_ALMOST_FULL RO

0x0

21

D0_R3_CH_ALMOST_FULL RO

0x0

20

N7_R1_C_ALMOST_FULL

RO

0x0

19

N6_R1_C_ALMOST_FULL

RO

0x0

18

N5_R1_C_ALMOST_FULL

RO

0x0

17

N4_R1_C_ALMOST_FULL

RO

0x0

16

N3_R1_C_ALMOST_FULL

RO

0x0

15

N2_R1_C_ALMOST_FULL

RO

0x0

14

N1_R1_C_ALMOST_FULL

RO

0x0

13

N0_R1_C_ALMOST_FULL

RO

0x0

12

D1_R2_C_ALMOST_FULL

RO

0x0

11

D1_R1_C_ALMOST_FULL

RO

0x0

Reserved

Reserved－476/1293－

SPI

Reserved
MATH_EVENT2_F
MATH_EVENT1_F
MATH_EVENT0_F
ISOP3
ISOP2
ISOP1
ISOP0
Reserved
D1_R3_CH_ALMOST_FULL
D0_R3_CH_ALMOST_FULL
N7_R1_C_ALMOST_FULL
N6_R1_C_ALMOST_FULL
N5_R1_C_ALMOST_FULL
N4_R1_C_ALMOST_FULL
N3_R1_C_ALMOST_FULL
N2_R1_C_ALMOST_FULL
N1_R1_C_ALMOST_FULL
N0_R1_C_ALMOST_FULL
D1_R2_C_ALMOST_FULL
D1_R1_C_ALMOST_FULL
D0_R2_C_ALMOST_FULL
D0_R1_C_ALMOST_FULL
MATH_EVENT2_R
MATH_EVENT1_R
MATH_EVENT0_R
HPADC1_ALMOST_FULL
HPADC0_ALMOST_FULL
LPADC_ALMOST_FULL
I2C1
I2C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

10

D0_R2_C_ALMOST_FULL

RO

0x0

9

D0_R1_C_ALMOST_FULL

RO

0x0

8

MATH_EVENT2_R

RO

0x0

7

MATH_EVENT1_R

RO

0x0

6

MATH_EVENT0_R

RO

0x0

5

HPADC1_ALMOST_FULL

RO

0x0

4

HPADC0_ALMOST_FULL

RO

0x0

3

LPADC_ALMOST_FULL

RO

0x0

2

I2C1

RO

0x0

1

I2C0

RO

0x0

0

SPI

RO

0x0

The interrupt status of the SPI or Math
Function Event 0 before masking－477/1293－

CXD5602 User Manual

3.9.12.3.130{0x5414} INT_MASKED_STT_MAIN Details
Table SCU (Sensor Control Unit)-282
Register Type: RO (read only)

Local Address: 0x5414

Reset Value: 0x00000000

Bits

Name

Type Reset Value Description

31

ALL_ORED_ERR

RO

0x0

30

MATH_EVENT2_F

RO

0x0

29

MATH_EVENT1_F

RO

0x0

28

MATH_EVENT0_F

RO

0x0

27

ISOP3

RO

0x0

26

ISOP2

RO

0x0

25

ISOP1

RO

0x0

24

ISOP0

RO

0x0

23

Reserved

RO

0x0

22

D1_R3_CH_ALMOST_FULL RO

0x0

21

D0_R3_CH_ALMOST_FULL RO

0x0

20

N7_R1_C_ALMOST_FULL

RO

0x0

19

N6_R1_C_ALMOST_FULL

RO

0x0

18

N5_R1_C_ALMOST_FULL

RO

0x0

17

N4_R1_C_ALMOST_FULL

RO

0x0

16

N3_R1_C_ALMOST_FULL

RO

0x0

15

N2_R1_C_ALMOST_FULL

RO

0x0

14

N1_R1_C_ALMOST_FULL

RO

0x0

13

N0_R1_C_ALMOST_FULL

RO

0x0

12

D1_R2_C_ALMOST_FULL

RO

0x0

11

D1_R1_C_ALMOST_FULL

RO

0x0

Reserved－478/1293－

SPI

ALL_ORED_ERR
MATH_EVENT2_F
MATH_EVENT1_F
MATH_EVENT0_F
ISOP3
ISOP2
ISOP1
ISOP0
Reserved
D1_R3_CH_ALMOST_FULL
D0_R3_CH_ALMOST_FULL
N7_R1_C_ALMOST_FULL
N6_R1_C_ALMOST_FULL
N5_R1_C_ALMOST_FULL
N4_R1_C_ALMOST_FULL
N3_R1_C_ALMOST_FULL
N2_R1_C_ALMOST_FULL
N1_R1_C_ALMOST_FULL
N0_R1_C_ALMOST_FULL
D1_R2_C_ALMOST_FULL
D1_R1_C_ALMOST_FULL
D0_R2_C_ALMOST_FULL
D0_R1_C_ALMOST_FULL
MATH_EVENT2_R
MATH_EVENT1_R
MATH_EVENT0_R
HPADC1_ALMOST_FULL
HPADC0_ALMOST_FULL
LPADC_ALMOST_FULL
I2C1
I2C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

10

D0_R2_C_ALMOST_FULL

RO

0x0

9

D0_R1_C_ALMOST_FULL

RO

0x0

8

MATH_EVENT2_R

RO

0x0

7

MATH_EVENT1_R

RO

0x0

6

MATH_EVENT0_R

RO

0x0

5

HPADC1_ALMOST_FULL

RO

0x0

4

HPADC0_ALMOST_FULL

RO

0x0

3

LPADC_ALMOST_FULL

RO

0x0

2

I2C1

RO

0x0

1

I2C0

RO

0x0

0

SPI

RO

0x0

The interrupt status of the SPI or Math
Function Event 0 after masking－479/1293－

CXD5602 User Manual

3.9.12.3.131{0x5420} INT_ENABLE_ERR_0 Details
Table SCU (Sensor Control Unit)-283
Register Type: RW (read/write)

Local Address: 0x5420

Reset Value: 0x00000000

Bits

Name

Type Reset Value Description

31

Reserved

RO

0x0

30

PWM7_INVALID_VALUE RW

0x0

29

PWM6_INVALID_VALUE RW

0x0

28

PWM5_INVALID_VALUE RW

0x0

27

PWM4_INVALID_VALUE RW

0x0

26

PWM3_INVALID_VALUE RW

0x0

25

PWM2_INVALID_VALUE RW

0x0

24

PWM1_INVALID_VALUE RW

0x0

23

PWM0_INVALID_VALUE RW

0x0

22

D1_R3_CH_OVER_RUN

RW

0x0

21

D0_R3_CH_OVER_RUN

RW

0x0

20

N7_R1_C_OVER_RUN

RW

0x0

19

N6_R1_C_OVER_RUN

RW

0x0

18

N5_R1_C_OVER_RUN

RW

0x0

17

N4_R1_C_OVER_RUN

RW

0x0

16

N3_R1_C_OVER_RUN

RW

0x0

15

N2_R1_C_OVER_RUN

RW

0x0

14

N1_R1_C_OVER_RUN

RW

0x0

13

N0_R1_C_OVER_RUN

RW

0x0

12

D1_R2_C_OVER_RUN

RW

0x0

LPADC_OVER_RUN1

ADCIF_READ_ERR
HPADC1_OVER_RUN
HPADC0_OVER_RUN
LPADC_OVER_RUN
LPADC_OVER_RUN3
LPADC_OVER_RUN2

Reserved

Reserved
PWM7_INVALID_VALUE
PWM6_INVALID_VALUE
PWM5_INVALID_VALUE
PWM4_INVALID_VALUE
PWM3_INVALID_VALUE
PWM2_INVALID_VALUE
PWM1_INVALID_VALUE
PWM0_INVALID_VALUE
D1_R3_CH_OVER_RUN
D0_R3_CH_OVER_RUN
N7_R1_C_OVER_RUN
N6_R1_C_OVER_RUN
N5_R1_C_OVER_RUN
N4_R1_C_OVER_RUN
N3_R1_C_OVER_RUN
N2_R1_C_OVER_RUN
N1_R1_C_OVER_RUN
N0_R1_C_OVER_RUN
D1_R2_C_OVER_RUN
D1_R1_C_OVER_RUN
D0_R2_C_OVER_RUN
D0_R1_C_OVER_RUN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Interrupt permission to detect outlier setting(CYCLE < THRESH) to PWM1Interrupt permission to detect outlier setting(CYCLE < THRESH) to PWM0－480/1293－

CXD5602 User Manual

11

D1_R1_C_OVER_RUN

RW

0x0

10

D0_R2_C_OVER_RUN

RW

0x0

9

D0_R1_C_OVER_RUN

RW

0x0

8..7

Reserved

RO

0x0

6

ADCIF_READ_ERR

RW

0x0

5

HPADC1_OVER_RUN

RW

0x0

4

HPADC0_OVER_RUN

RW

0x0

3

LPADC_OVER_RUN

RW

0x0

2

LPADC_OVER_RUN3

RW

0x0

1

LPADC_OVER_RUN2

RW

0x0

0

LPADC_OVER_RUN1

RW

0x0

Reserved－481/1293－

CXD5602 User Manual

3.9.12.3.132{0x5424} INT_DISABLE_ERR_0 Details
Table SCU (Sensor Control Unit)-284
Register Type: RW (read/write)

Local Address: 0x5424

Reset Value: 0x00000000

Bits

Name

Type Reset Value Description

31

Reserved

RO

0x0

30

PWM7_INVALID_VALUE RW

0x0

29

PWM6_INVALID_VALUE RW

0x0

28

PWM5_INVALID_VALUE RW

0x0

27

PWM4_INVALID_VALUE RW

0x0

26

PWM3_INVALID_VALUE RW

0x0

25

PWM2_INVALID_VALUE RW

0x0

24

PWM1_INVALID_VALUE RW

0x0

23

PWM0_INVALID_VALUE RW

0x0

22

D1_R3_CH_OVER_RUN

RW

0x0

21

D0_R3_CH_OVER_RUN

RW

0x0

20

N7_R1_C_OVER_RUN

RW

0x0

19

N6_R1_C_OVER_RUN

RW

0x0

18

N5_R1_C_OVER_RUN

RW

0x0

17

N4_R1_C_OVER_RUN

RW

0x0

16

N3_R1_C_OVER_RUN

RW

0x0

15

N2_R1_C_OVER_RUN

RW

0x0

14

N1_R1_C_OVER_RUN

RW

0x0

13

N0_R1_C_OVER_RUN

RW

0x0

12

D1_R2_C_OVER_RUN

RW

0x0

LPADC_OVER_RUN1

ADCIF_READ_ERR
HPADC1_OVER_RUN
HPADC0_OVER_RUN
LPADC_OVER_RUN
LPADC_OVER_RUN3
LPADC_OVER_RUN2

Reserved

Reserved
PWM7_INVALID_VALUE
PWM6_INVALID_VALUE
PWM5_INVALID_VALUE
PWM4_INVALID_VALUE
PWM3_INVALID_VALUE
PWM2_INVALID_VALUE
PWM1_INVALID_VALUE
PWM0_INVALID_VALUE
D1_R3_CH_OVER_RUN
D0_R3_CH_OVER_RUN
N7_R1_C_OVER_RUN
N6_R1_C_OVER_RUN
N5_R1_C_OVER_RUN
N4_R1_C_OVER_RUN
N3_R1_C_OVER_RUN
N2_R1_C_OVER_RUN
N1_R1_C_OVER_RUN
N0_R1_C_OVER_RUN
D1_R2_C_OVER_RUN
D1_R1_C_OVER_RUN
D0_R2_C_OVER_RUN
D0_R1_C_OVER_RUN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Interrupt permission to detect outlier setting(CYCLE < THRESH) to PWM1Interrupt permission to detect outlier setting(CYCLE < THRESH) to PWM0－482/1293－

CXD5602 User Manual

11

D1_R1_C_OVER_RUN

RW

0x0

10

D0_R2_C_OVER_RUN

RW

0x0

9

D0_R1_C_OVER_RUN

RW

0x0

8..7

Reserved

RO

0x0

6

ADCIF_READ_ERR

RW

0x0

5

HPADC1_OVER_RUN

RW

0x0

4

HPADC0_OVER_RUN

RW

0x0

3

LPADC_OVER_RUN

RW

0x0

2

LPADC_OVER_RUN3

RW

0x0

1

LPADC_OVER_RUN2

RW

0x0

0

LPADC_OVER_RUN1

RW

0x0

Reserved

Interrupt permission of overrun error (write
occurrence at FIFO Full) for LPADC－483/1293－

CXD5602 User Manual

3.9.12.3.133{0x5428} INT_CLEAR_ERR_0 Details
Table SCU (Sensor Control Unit)-285
Register Type: WO (write only)

Local Address: 0x5428

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value Description

31

Reserved

WO

0x0

30

PWM7_INVALID_VALUE WO

0x0

29

PWM6_INVALID_VALUE WO

0x0

28

PWM5_INVALID_VALUE WO

0x0

27

PWM4_INVALID_VALUE WO

0x0

26

PWM3_INVALID_VALUE WO

0x0

25

PWM2_INVALID_VALUE WO

0x0

24

PWM1_INVALID_VALUE WO

0x0

23

PWM0_INVALID_VALUE WO

0x0

LPADC_OVER_RUN1

ADCIF_READ_ERR
HPADC1_OVER_RUN
HPADC0_OVER_RUN
LPADC_OVER_RUN
LPADC_OVER_RUN3
LPADC_OVER_RUN2

Reserved
PWM7_INVALID_VALUE
PWM6_INVALID_VALUE
PWM5_INVALID_VALUE
PWM4_INVALID_VALUE
PWM3_INVALID_VALUE
PWM2_INVALID_VALUE
PWM1_INVALID_VALUE
PWM0_INVALID_VALUE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Interrupt clear of detecting outlier setting(CYCLE < THRESH) to PWM1Interrupt clear of detecting outlier setting(CYCLE < THRESH) to PWM0

22..7 Reserved

WO

0x00006

ADCIF_READ_ERR

WO

0x0

5

HPADC1_OVER_RUN

WO

0x0

4

HPADC0_OVER_RUN

WO

0x0

3

LPADC_OVER_RUN

WO

0x0

2

LPADC_OVER_RUN3

WO

0x0

1

LPADC_OVER_RUN2

WO

0x0

0

LPADC_OVER_RUN1

WO

0x0

Reserved－484/1293－

CXD5602 User Manual

3.9.12.3.134{0x542C} INT_RAW_STT_ERR_0 Details
Table SCU (Sensor Control Unit)-286
Register Type: RO (read only)

Local Address: 0x542C

Reset Value: 0x00000000

Bits

Name

Type Reset Value Description

31

Reserved

RO

0x0

30

PWM7_INVALID_VALUE RO

0x0

29

PWM6_INVALID_VALUE RO

0x0

28

PWM5_INVALID_VALUE RO

0x0

27

PWM4_INVALID_VALUE RO

0x0

26

PWM3_INVALID_VALUE RO

0x0

25

PWM2_INVALID_VALUE RO

0x0

24

PWM1_INVALID_VALUE RO

0x0

23

PWM0_INVALID_VALUE RO

0x0

22

D1_R3_CH_OVER_RUN

RO

0x0

21

D0_R3_CH_OVER_RUN

RO

0x0

20

N7_R1_C_OVER_RUN

RO

0x0

19

N6_R1_C_OVER_RUN

RO

0x0

18

N5_R1_C_OVER_RUN

RO

0x0

17

N4_R1_C_OVER_RUN

RO

0x0

16

N3_R1_C_OVER_RUN

RO

0x0

15

N2_R1_C_OVER_RUN

RO

0x0

14

N1_R1_C_OVER_RUN

RO

0x0

13

N0_R1_C_OVER_RUN

RO

0x0

12

D1_R2_C_OVER_RUN

RO

0x0

11

D1_R1_C_OVER_RUN

RO

0x0

10

D0_R2_C_OVER_RUN

RO

0x0

Reserved－485/1293－

LPADC_OVER_RUN1

ADCIF_READ_ERR
HPADC1_OVER_RUN
HPADC0_OVER_RUN
LPADC_OVER_RUN
LPADC_OVER_RUN3
LPADC_OVER_RUN2

Reserved

Reserved
PWM7_INVALID_VALUE
PWM6_INVALID_VALUE
PWM5_INVALID_VALUE
PWM4_INVALID_VALUE
PWM3_INVALID_VALUE
PWM2_INVALID_VALUE
PWM1_INVALID_VALUE
PWM0_INVALID_VALUE
D1_R3_CH_OVER_RUN
D0_R3_CH_OVER_RUN
N7_R1_C_OVER_RUN
N6_R1_C_OVER_RUN
N5_R1_C_OVER_RUN
N4_R1_C_OVER_RUN
N3_R1_C_OVER_RUN
N2_R1_C_OVER_RUN
N1_R1_C_OVER_RUN
N0_R1_C_OVER_RUN
D1_R2_C_OVER_RUN
D1_R1_C_OVER_RUN
D0_R2_C_OVER_RUN
D0_R1_C_OVER_RUN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

9

D0_R1_C_OVER_RUN

RO

0x0

8..7

Reserved

RO

0x0

6

ADCIF_READ_ERR

RO

0x0

5

HPADC1_OVER_RUN

RO

0x0

4

HPADC0_OVER_RUN

RO

0x0

3

LPADC_OVER_RUN

RO

0x0

2

LPADC_OVER_RUN3

RO

0x0

1

LPADC_OVER_RUN2

RO

0x0

0

LPADC_OVER_RUN1

RO

0x0

Reserved－486/1293－

CXD5602 User Manual

3.9.12.3.135{0x5430} INT_MASKED_STT_ERR_0 Details
Table SCU (Sensor Control Unit)-287
Register Type: RO (read only)

Local Address: 0x5430

Bits

Name

Type

Reset Value

Description

31

ReservedRO

0x0

Reserved

30

PWM7_INVALID_VALUE

RO

0x0

29

PWM6_INVALID_VALUE

RO

0x0

28

PWM5_INVALID_VALUE

RO

0x0

27

PWM4_INVALID_VALUE

RO

0x0

26

PWM3_INVALID_VALUE

RO

0x0

25

PWM2_INVALID_VALUE

RO

0x0

24

PWM1_INVALID_VALUE

RO

0x0

23

PWM0_INVALID_VALUE

RO

0x0

22

D1_R3_CH_OVER_RUN

RO

0x0

21

D0_R3_CH_OVER_RUN

RO

0x0

20

N7_R1_C_OVER_RUN

RO

0x0

19

N6_R1_C_OVER_RUN

RO

0x0

18

N5_R1_C_OVER_RUN

RO

0x0

17

N4_R1_C_OVER_RUN

RO

0x0

16

N3_R1_C_OVER_RUN

RO

0x0

15

N2_R1_C_OVER_RUN

RO

0x0

14

N1_R1_C_OVER_RUN

RO

0x0

13

N0_R1_C_OVER_RUN

RO

0x0

12

D1_R2_C_OVER_RUN

RO

0x0

11

D1_R1_C_OVER_RUN

RO

0x0

10

D0_R2_C_OVER_RUN

RO

0x0

－487/1293－

5

4

3

2

1

0

HPADC0_OVER_RUN

LPADC_OVER_RUN

LPADC_OVER_RUN3

LPADC_OVER_RUN2

LPADC_OVER_RUN1

7 6

ADCIF_READ_ERR

8Reserved

D0_R1_C_OVER_RUN

D0_R2_C_OVER_RUN

D1_R1_C_OVER_RUN

D1_R2_C_OVER_RUN

N0_R1_C_OVER_RUN

N1_R1_C_OVER_RUN

N2_R1_C_OVER_RUN

N3_R1_C_OVER_RUN

N4_R1_C_OVER_RUN

N5_R1_C_OVER_RUN

N6_R1_C_OVER_RUN

N7_R1_C_OVER_RUN

D0_R3_CH_OVER_RUN

D1_R3_CH_OVER_RUN

PWM0_INVALID_VALUE

PWM1_INVALID_VALUE

PWM2_INVALID_VALUE

PWM3_INVALID_VALUE

PWM4_INVALID_VALUE

PWM5_INVALID_VALUE

PWM6_INVALID_VALUE

PWM7_INVALID_VALUE

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

HPADC1_OVER_RUN

Reset Value: 0x00000000

CXD5602 User Manual

9

D0_R1_C_OVER_RUN

RO

0x0

8..7

Reserved

RO

0x0

6

ADCIF_READ_ERR

RO

0x0

5

HPADC1_OVER_RUN

RO

0x0

4

HPADC0_OVER_RUN

RO

0x0

3

LPADC_OVER_RUN

RO

0x0

2

LPADC_OVER_RUN3

RO

0x0

1

LPADC_OVER_RUN2

RO

0x0

0

LPADC_OVER_RUN1

RO

0x0

Reserved－488/1293－

CXD5602 User Manual

3.9.12.3.136{0x5440} INT_ENABLE_ERR_1 Details
Table SCU (Sensor Control Unit)-288
Register Type: RW (read/write)

Local Address: 0x5440

Bits

Name

Type

Reset Value

Description

31..23

Reserved

RO

0x000

Reserved

22

D1_R3_CH_UNDER_RUN RW

0x0

21

D0_R3_CH_UNDER_RUN RW

0x0

20

N7_R1_C_UNDER_RUN

RW

0x0

19

N6_R1_C_UNDER_RUN

RW

0x0

18

N5_R1_C_UNDER_RUN

RW

0x0

17

N4_R1_C_UNDER_RUN

RW

0x0

16

N3_R1_C_UNDER_RUN

RW

0x0

15

N2_R1_C_UNDER_RUN

RW

0x0

14

N1_R1_C_UNDER_RUN

RW

0x0

13

N0_R1_C_UNDER_RUN

RW

0x0

12

D1_R2_C_UNDER_RUN

RW

0x0

11

D1_R1_C_UNDER_RUN

RW

0x0

10

D0_R2_C_UNDER_RUN

RW

0x0

9

D0_R1_C_UNDER_RUN

RW

0x0

8..6

Reserved

RO

0x0

5

HPADC1_UNDER_RUN

RW

0x0

4

HPADC0_UNDER_RUN

RW

0x0

3

LPADC_UNDER_RUN

RW

0x0

2

LPADC_UNDER_RUN3

RW

0x0

1

LPADC_UNDER_RUN2

RW

0x0

0

LPADC_UNDER_RUN1

RW

0x0

Reserved－489/1293－

7 6

5

4

3

2

1

0

HPADC0_UNDER_RUN

LPADC_UNDER_RUN

LPADC_UNDER_RUN3

LPADC_UNDER_RUN2

LPADC_UNDER_RUN1

8

HPADC1_UNDER_RUN

D0_R1_C_UNDER_RUN

D0_R2_C_UNDER_RUN

D1_R1_C_UNDER_RUN

D1_R2_C_UNDER_RUN

N0_R1_C_UNDER_RUN

N1_R1_C_UNDER_RUN

N2_R1_C_UNDER_RUN

N3_R1_C_UNDER_RUN

N4_R1_C_UNDER_RUN

N5_R1_C_UNDER_RUN

N6_R1_C_UNDER_RUN

N7_R1_C_UNDER_RUN

Reserved

D0_R3_CH_UNDER_RUN

D1_R3_CH_UNDER_RUN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9Reserved

Reset Value: 0x00000000

CXD5602 User Manual

3.9.12.3.137{0x5444} INT_DISABLE_ERR_1 Details
Table SCU (Sensor Control Unit)-289
Register Type: RW (read/write)

Local Address: 0x5444

Reset Value: 0x00000000

Bits

Name

31..23 Reserved

Type Reset Value Description
RO

0x000

22

D1_R3_CH_UNDER_RUN RW

0x0

21

D0_R3_CH_UNDER_RUN RW

0x0

20

N7_R1_C_UNDER_RUN

RW

0x0

19

N6_R1_C_UNDER_RUN

RW

0x0

18

N5_R1_C_UNDER_RUN

RW

0x0

17

N4_R1_C_UNDER_RUN

RW

0x0

16

N3_R1_C_UNDER_RUN

RW

0x0

15

N2_R1_C_UNDER_RUN

RW

0x0

14

N1_R1_C_UNDER_RUN

RW

0x0

13

N0_R1_C_UNDER_RUN

RW

0x0

12

D1_R2_C_UNDER_RUN

RW

0x0

11

D1_R1_C_UNDER_RUN

RW

0x0

10

D0_R2_C_UNDER_RUN

RW

0x0

9

D0_R1_C_UNDER_RUN

RW

0x0

8..6

Reserved

RO

0x0

5

HPADC1_UNDER_RUN

RW

0x0

4

HPADC0_UNDER_RUN

RW

0x0

3

LPADC_UNDER_RUN

RW

0x0

2

LPADC_UNDER_RUN3

RW

0x0

1

LPADC_UNDER_RUN2

RW

0x0

0

LPADC_UNDER_RUN1

RW

0x0

Reserved

Reserved－490/1293－

LPADC_UNDER_RUN1

HPADC1_UNDER_RUN
HPADC0_UNDER_RUN
LPADC_UNDER_RUN
LPADC_UNDER_RUN3
LPADC_UNDER_RUN2

Reserved

Reserved

D1_R3_CH_UNDER_RUN
D0_R3_CH_UNDER_RUN
N7_R1_C_UNDER_RUN
N6_R1_C_UNDER_RUN
N5_R1_C_UNDER_RUN
N4_R1_C_UNDER_RUN
N3_R1_C_UNDER_RUN
N2_R1_C_UNDER_RUN
N1_R1_C_UNDER_RUN
N0_R1_C_UNDER_RUN
D1_R2_C_UNDER_RUN
D1_R1_C_UNDER_RUN
D0_R2_C_UNDER_RUN
D0_R1_C_UNDER_RUN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.3.138{0x5448} INT_CLEAR_ERR_1 Details
Table SCU (Sensor Control Unit)-290
Register Type: WO (write only)

Local Address: 0x5448

Reset Value: 0x00000000

Reserved

Bits

Name

Type

Reset Value Description

31..6

Reserved

WO

0x0000000

5HPADC1_UNDER_RUN

WO

0x0

4

HPADC0_UNDER_RUN

WO

0x0

3

LPADC_UNDER_RUN

WO

0x0

2

LPADC_UNDER_RUN3

WO

0x0

1

LPADC_UNDER_RUN2

WO

0x0

0

LPADC_UNDER_RUN1

WO

0x0

Reserved－491/1293－

LPADC_UNDER_RUN1

HPADC1_UNDER_RUN
HPADC0_UNDER_RUN
LPADC_UNDER_RUN
LPADC_UNDER_RUN3
LPADC_UNDER_RUN2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.3.139{0x544C} INT_RAW_STT_ERR_1 Details
Table SCU (Sensor Control Unit)-291
Register Type: RO (read only)

Local Address: 0x544C

Bits

Name

Type

Reset Value

Description

31..23

Reserved

RO

0x000

Reserved

22

D1_R3_CH_UNDER_RUN RO

0x0

21

D0_R3_CH_UNDER_RUN RO

0x0

20

N7_R1_C_UNDER_RUN

RO

0x0

19

N6_R1_C_UNDER_RUN

RO

0x0

18

N5_R1_C_UNDER_RUN

RO

0x0

17

N4_R1_C_UNDER_RUN

RO

0x0

16

N3_R1_C_UNDER_RUN

RO

0x0

15

N2_R1_C_UNDER_RUN

RO

0x0

14

N1_R1_C_UNDER_RUN

RO

0x0

13

N0_R1_C_UNDER_RUN

RO

0x0

12

D1_R2_C_UNDER_RUN

RO

0x0

11

D1_R1_C_UNDER_RUN

RO

0x0

10

D0_R2_C_UNDER_RUN

RO

0x0

9

D0_R1_C_UNDER_RUN

RO

0x0

8..6

Reserved

RO

0x0

5

HPADC1_UNDER_RUN

RO

0x0

4

HPADC0_UNDER_RUN

RO

0x0

3

LPADC_UNDER_RUN

RO

0x0

2

LPADC_UNDER_RUN3

RO

0x0

1

LPADC_UNDER_RUN2

RO

0x0

0

LPADC_UNDER_RUN1

RO

0x0

Reserved－492/1293－

7 6

5

4

3

2

1

0

HPADC0_UNDER_RUN

LPADC_UNDER_RUN

LPADC_UNDER_RUN3

LPADC_UNDER_RUN2

LPADC_UNDER_RUN1

8

HPADC1_UNDER_RUN

D0_R1_C_UNDER_RUN

D0_R2_C_UNDER_RUN

D1_R1_C_UNDER_RUN

D1_R2_C_UNDER_RUN

N0_R1_C_UNDER_RUN

N1_R1_C_UNDER_RUN

N2_R1_C_UNDER_RUN

N3_R1_C_UNDER_RUN

N4_R1_C_UNDER_RUN

N5_R1_C_UNDER_RUN

N6_R1_C_UNDER_RUN

N7_R1_C_UNDER_RUN

Reserved

D0_R3_CH_UNDER_RUN

D1_R3_CH_UNDER_RUN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9Reserved

Reset Value: 0x00000000

CXD5602 User Manual

3.9.12.3.140{0x5450} INT_MASKED_STT_ERR_1 Details
Table SCU (Sensor Control Unit)-292
Register Type: RO (read only)

Local Address: 0x5450

Reset Value: 0x00000000

Bits

Name

31..23 Reserved

Type

Reset Value Description

RO

0x000

22

D1_R3_CH_UNDER_RUN RO

0x0

21

D0_R3_CH_UNDER_RUN RO

0x0

20

N7_R1_C_UNDER_RUN RO

0x0

19

N6_R1_C_UNDER_RUN RO

0x0

18

N5_R1_C_UNDER_RUN RO

0x0

17

N4_R1_C_UNDER_RUN RO

0x0

16

N3_R1_C_UNDER_RUN RO

0x0

15

N2_R1_C_UNDER_RUN RO

0x0

14

N1_R1_C_UNDER_RUN RO

0x0

13

N0_R1_C_UNDER_RUN RO

0x0

12

D1_R2_C_UNDER_RUN RO

0x0

11

D1_R1_C_UNDER_RUN RO

0x0

10

D0_R2_C_UNDER_RUN RO

0x0

9

D0_R1_C_UNDER_RUN RO

0x0

8..6

Reserved

RO

0x0

5

HPADC1_UNDER_RUN

RO

0x0

4

HPADC0_UNDER_RUN

RO

0x0

3

LPADC_UNDER_RUN

RO

0x0

2

LPADC_UNDER_RUN3

RO

0x0

1

LPADC_UNDER_RUN2

RO

0x0

0

LPADC_UNDER_RUN1

RO

0x0

Reserved

Reserved－493/1293－

LPADC_UNDER_RUN1

HPADC1_UNDER_RUN
HPADC0_UNDER_RUN
LPADC_UNDER_RUN
LPADC_UNDER_RUN3
LPADC_UNDER_RUN2

Reserved

Reserved

D1_R3_CH_UNDER_RUN
D0_R3_CH_UNDER_RUN
N7_R1_C_UNDER_RUN
N6_R1_C_UNDER_RUN
N5_R1_C_UNDER_RUN
N4_R1_C_UNDER_RUN
N3_R1_C_UNDER_RUN
N2_R1_C_UNDER_RUN
N1_R1_C_UNDER_RUN
N0_R1_C_UNDER_RUN
D1_R2_C_UNDER_RUN
D1_R1_C_UNDER_RUN
D0_R2_C_UNDER_RUN
D0_R1_C_UNDER_RUN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.3.141{0x5460} INT_ENABLE_ERR_2 Details
Table SCU (Sensor Control Unit)-293
Register Type: RW (read/write)

Local Address: 0x5460

Reset Value: 0x00000000

Bits

Name

Type

Reset Value Description

31..26 Reserved

RO

0x00

25

EXE_ERR9

RW

0x0

24

EXE_ERR8

RW

0x0

23

EXE_ERR7

RW

0x0

22

EXE_ERR6

RW

0x0

21

EXE_ERR5

RW

0x0

20

EXE_ERR4

RW

0x0

19

EXE_ERR3

RW

0x0

18

EXE_ERR2

RW

0x0

17

EXE_ERR1

RW

0x0

REQ_BEFORE_FINISH0

Reserved
EXE_ERR9
EXE_ERR8
EXE_ERR7
EXE_ERR6
EXE_ERR5
EXE_ERR4
EXE_ERR3
EXE_ERR2
EXE_ERR1
EXE_ERR0

Reserved

REQ_BEFORE_FINISH9
REQ_BEFORE_FINISH8
REQ_BEFORE_FINISH7
REQ_BEFORE_FINISH6
REQ_BEFORE_FINISH5
REQ_BEFORE_FINISH4
REQ_BEFORE_FINISH3
REQ_BEFORE_FINISH2
REQ_BEFORE_FINISH1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Permission of interrupt for not completing the16

EXE_ERR0

RW

0x0

sequencer’s

process

executing Sequencer 0
15..10 Reserved

RO

0x00

9

REQ_BEFORE_FINISH9 RW

0x08

REQ_BEFORE_FINISH8 RW

0x0

7

REQ_BEFORE_FINISH7 RW

0x0

6

REQ_BEFORE_FINISH6 RW

0x0

5

REQ_BEFORE_FINISH5 RW

0x0

4

REQ_BEFORE_FINISH4 RW

0x0

3

REQ_BEFORE_FINISH3 RW

0x02

REQ_BEFORE_FINISH2 RW

0x0

Reserved－494/1293－

successfullywhen

CXD5602 User Manual

1

REQ_BEFORE_FINISH1 RW

0x00

REQ_BEFORE_FINISH0 RW

0x0

Permission of interrupt for requesting the next
operation before completion (Sequencer 0)－495/1293－

CXD5602 User Manual

3.9.12.3.142{0x5464} INT_DISABLE_ERR_2 Details
Table SCU (Sensor Control Unit)-294
Register Type: RW (read/write)

Local Address: 0x5464

Reset Value: 0x00000000

Bits

Name

Type Reset Value

Description

31..26 Reserved

RO

0x00

Reserved

25

EXE_ERR9

RW

0x0

24

EXE_ERR8

RW

0x0

23

EXE_ERR7

RW

0x0

22

EXE_ERR6

RW

0x0

21

EXE_ERR5

RW

0x0

20

EXE_ERR4

RW

0x0

19

EXE_ERR3

RW

0x0

18

EXE_ERR2

RW

0x0

17

EXE_ERR1

RW

0x0

REQ_BEFORE_FINISH0

Reserved
EXE_ERR9
EXE_ERR8
EXE_ERR7
EXE_ERR6
EXE_ERR5
EXE_ERR4
EXE_ERR3
EXE_ERR2
EXE_ERR1
EXE_ERR0

Reserved

REQ_BEFORE_FINISH9
REQ_BEFORE_FINISH8
REQ_BEFORE_FINISH7
REQ_BEFORE_FINISH6
REQ_BEFORE_FINISH5
REQ_BEFORE_FINISH4
REQ_BEFORE_FINISH3
REQ_BEFORE_FINISH2
REQ_BEFORE_FINISH1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Permission of interrupt for not completing the16

EXE_ERR0

RW

0x0

sequencer’s

process

executing Sequencer 0
15..10 Reserved

RO

0x00

9

REQ_BEFORE_FINISH9 RW

0x08

REQ_BEFORE_FINISH8 RW

0x0

7

REQ_BEFORE_FINISH7 RW

0x0

6

REQ_BEFORE_FINISH6 RW

0x0

5

REQ_BEFORE_FINISH5 RW

0x0

4

REQ_BEFORE_FINISH4 RW

0x0

3

REQ_BEFORE_FINISH3 RW

0x02

REQ_BEFORE_FINISH2 RW

0x0

Reserved－496/1293－

successfullywhen

CXD5602 User Manual

1

REQ_BEFORE_FINISH1 RW

0x00

REQ_BEFORE_FINISH0 RW

0x0

Permission of interrupt for requesting the next
operation before completion (Sequencer 0)－497/1293－

CXD5602 User Manual

3.9.12.3.143{0x5468} INT_CLEAR_ERR_2 Details
Table SCU (Sensor Control Unit)-295
Register Type: WO (write only)

Local Address: 0x5468

Reset Value: 0x00000000

Bits

Name

Type Reset Value

Description

31..26 Reserved

WO

0x00

Reserved

25

EXE_ERR9

WO

0x0

24

EXE_ERR8

WO

0x0

23

EXE_ERR7

WO

0x0

22

EXE_ERR6

WO

0x0

21

EXE_ERR5

WO

0x0

20

EXE_ERR4

WO

0x0

19

EXE_ERR3

WO

0x0

18

EXE_ERR2

WO

0x0

17

EXE_ERR1

WO

0x0

REQ_BEFORE_FINISH0

Reserved
EXE_ERR9
EXE_ERR8
EXE_ERR7
EXE_ERR6
EXE_ERR5
EXE_ERR4
EXE_ERR3
EXE_ERR2
EXE_ERR1
EXE_ERR0

Reserved

REQ_BEFORE_FINISH9
REQ_BEFORE_FINISH8
REQ_BEFORE_FINISH7
REQ_BEFORE_FINISH6
REQ_BEFORE_FINISH5
REQ_BEFORE_FINISH4
REQ_BEFORE_FINISH3
REQ_BEFORE_FINISH2
REQ_BEFORE_FINISH1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Clear of interrupt for not completing the16

EXE_ERR0

WO

0x0

sequencer’s

process

executing Sequencer 0
15..10 Reserved

WO

0x00

9

REQ_BEFORE_FINISH9 WO

0x0

8

REQ_BEFORE_FINISH8 WO

0x0

7

REQ_BEFORE_FINISH7 WO

0x0

6

REQ_BEFORE_FINISH6 WO

0x0

5

REQ_BEFORE_FINISH5 WO

0x0

4

REQ_BEFORE_FINISH4 WO

0x0

3

REQ_BEFORE_FINISH3 WO

0x0

2

REQ_BEFORE_FINISH2 WO

0x0

Reserved－498/1293－

successfullywhen

CXD5602 User Manual

1

REQ_BEFORE_FINISH1 WO

0x00

REQ_BEFORE_FINISH0 WO

0x0

Clear of interrupt for requesting the next
operation before completion (Sequencer 0)－499/1293－

CXD5602 User Manual

3.9.12.3.144{0x546C} INT_RAW_STT_ERR_2 Details
Table SCU (Sensor Control Unit)-296
Register Type: RO (read only)

Local Address: 0x546C

Reset Value: 0x00000000

Bits

Name

Type

Reset Value

Description

31..26 Reserved

RO

0x00

Reserved

25

EXE_ERR9

RO

0x0

24

EXE_ERR8

RO

0x0

23

EXE_ERR7

RO

0x0

22

EXE_ERR6

RO

0x0

21

EXE_ERR5

RO

0x0

20

EXE_ERR4

RO

0x0

19

EXE_ERR3

RO

0x0

18

EXE_ERR2

RO

0x0

17

EXE_ERR1

RO

0x0

REQ_BEFORE_FINISH0

Reserved
EXE_ERR9
EXE_ERR8
EXE_ERR7
EXE_ERR6
EXE_ERR5
EXE_ERR4
EXE_ERR3
EXE_ERR2
EXE_ERR1
EXE_ERR0

Reserved

REQ_BEFORE_FINISH9
REQ_BEFORE_FINISH8
REQ_BEFORE_FINISH7
REQ_BEFORE_FINISH6
REQ_BEFORE_FINISH5
REQ_BEFORE_FINISH4
REQ_BEFORE_FINISH3
REQ_BEFORE_FINISH2
REQ_BEFORE_FINISH1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Status of interrupt for not completing the16

EXE_ERR0

RO

0x0

sequencer’s

process

successfully

executing Sequencer 0 (before masking)15..10 Reserved

RO

0x00

9

REQ_BEFORE_FINISH9 RO

0x0

8

REQ_BEFORE_FINISH8 RO

0x0

7

REQ_BEFORE_FINISH7 RO

0x0

6

REQ_BEFORE_FINISH6 RO

0x0

5

REQ_BEFORE_FINISH5 RO

0x0

4

REQ_BEFORE_FINISH4 RO

0x0

3

REQ_BEFORE_FINISH3 RO

0x0

2

REQ_BEFORE_FINISH2 RO

0x0

Reserved－500/1293－

when

CXD5602 User Manual

1

REQ_BEFORE_FINISH1 RO

0x0
Interrupt status for requesting the next

0

REQ_BEFORE_FINISH0 RO

0x0

operation before completion (Sequencer 0,
before masking)－501/1293－

CXD5602 User Manual

3.9.12.3.145{0x5470} INT_MASKED_STT_ERR_2 Details
Table SCU (Sensor Control Unit)-297
Register Type: RO (read only)

Local Address: 0x5470

Reset Value: 0x00000000

Bits

Name

Type Reset Value

Description

31..26 Reserved

RO

0x00

Reserved

25

EXE_ERR9

RO

0x0

24

EXE_ERR8

RO

0x0

23

EXE_ERR7

RO

0x0

22

EXE_ERR6

RO

0x0

21

EXE_ERR5

RO

0x0

20

EXE_ERR4

RO

0x0

19

EXE_ERR3

RO

0x0

18

EXE_ERR2

RO

0x0

17

EXE_ERR1

RO

0x0

REQ_BEFORE_FINISH0

Reserved
EXE_ERR9
EXE_ERR8
EXE_ERR7
EXE_ERR6
EXE_ERR5
EXE_ERR4
EXE_ERR3
EXE_ERR2
EXE_ERR1
EXE_ERR0

Reserved

REQ_BEFORE_FINISH9
REQ_BEFORE_FINISH8
REQ_BEFORE_FINISH7
REQ_BEFORE_FINISH6
REQ_BEFORE_FINISH5
REQ_BEFORE_FINISH4
REQ_BEFORE_FINISH3
REQ_BEFORE_FINISH2
REQ_BEFORE_FINISH1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Status of interrupt for not completing the16

EXE_ERR0

RO

0x0

sequencer’s

process

successfully

executing Sequencer 0 (after masking)15..10 Reserved

RO

0x00

9

REQ_BEFORE_FINISH9 RO

0x0

8

REQ_BEFORE_FINISH8 RO

0x0

7

REQ_BEFORE_FINISH7 RO

0x0

6

REQ_BEFORE_FINISH6 RO

0x0

5

REQ_BEFORE_FINISH5 RO

0x0

4

REQ_BEFORE_FINISH4 RO

0x0

3

REQ_BEFORE_FINISH3 RO

0x0

2

REQ_BEFORE_FINISH2 RO

0x0

Reserved－502/1293－

when

CXD5602 User Manual

1

REQ_BEFORE_FINISH1 RO

0x0
Interrupt status for requesting the next

0

REQ_BEFORE_FINISH0 RO

0x0

operation before completion (Sequencer 0,
after masking)－503/1293－

CXD5602 User Manual

3.9.12.3.146{0x5500} RAM_TEST Details
Table SCU (Sensor Control Unit)-298
Register Type: RW (read/write)

Local Address: 0x5500

Reset Value: 0x00000000

Bits

Name

Type Reset Value

Description

31..9

Reserved

RO

0x000000Reserved

8..7

ICGOVERRIDE

RW

0x0

6..5

WM

RW

0x0

4..2

RM

RW

0x0

1

EN_STANDBY

RW

0x0

0

EN_IG

RW

0x0

3.9.12.3.147

WM RM

EN_IG

Reserved

EN_STANDBYICGOVERRIDE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

write timing margin common to all RAMs in
the SCU
read timing margin common to all RAMs in
the SCU
standby enable common to all RAMs in the
SCU
InputGate enable common to all RAMs in the
SCU{0x5510} SCU_POWER Details

Clock Control under Internal Sequencer’s control
0: CK_SCU 1: CK_SCU_SPI 2: CK_SCU_I2C0 3: CK_SCU_I2C1
Table SCU (Sensor Control Unit)-299
Register Type: RO (read only)

Local Address: 0x5510

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

CLK_EN

Bits

Name

Type Reset Value

Description

31..4

Reserved

RO

0x0000000

Reserved

3..0

CLK_ENRO

0x0－504/1293－

CXD5602 User Manual

3.9.12.3.148{0x5520} INT_ENABLE_MAIN_AD Details
Table SCU (Sensor Control Unit)-300
Register Type: RW (read/write)

Local Address: 0x5520

Reset Value: 0x00000000

Reserved

Bits

Name

31..3 Reserved

LPADC_ALMOST_FULL1LPADC_ALMOST_FULL3LPADC_ALMOST_FULL2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Type Reset Value Description
RO

0x00000000 Reserved

2

LPADC_ALMOST_FULL3 RW

0x01

LPADC_ALMOST_FULL2 RW

0x0
Interrupt permission for the SPI or Math0

LPADC_ALMOST_FULL1 RW

0x0

Function Event 0.
The interrupt is permitted by writing “1”.
Writing “0” cannot prohibit the interrupt.

－505/1293－

CXD5602 User Manual

3.9.12.3.149{0x5524} INT_DISABLE_MAIN_AD Details
Table SCU (Sensor Control Unit)-301
Register Type: RW (read/write)

Local Address: 0x5524

Reset Value: 0x00000000

Reserved

Bits

Name

31..3 Reserved

Type Reset Value Description
RO

0x00000000 Reserved

2

LPADC_ALMOST_FULL3 RW

0x01

LPADC_ALMOST_FULL2 RW

0x0
Interrupt prohibition for the SPI.

0LPADC_ALMOST_FULL1 RW

0x0

The interrupt is prohibited by writing “1”.
Writing “0” cannot permit the interrupt.

－506/1293－

LPADC_ALMOST_FULL1LPADC_ALMOST_FULL3LPADC_ALMOST_FULL2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.3.150{0x5528} INT_CLEAR_MAIN_AD Details
Table SCU (Sensor Control Unit)-302
Register Type: WO (write only)

Local Address: 0x5528

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value Description

31..3

Reserved

WO

2

LPADC_ALMOST_FULL3 WO

0x0

1

LPADC_ALMOST_FULL2 WO

0x0

LPADC_ALMOST_FULL1LPADC_ALMOST_FULL3LPADC_ALMOST_FULL2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x00000000 ReservedInterrupt clear of Math Function Event 0.
0

LPADC_ALMOST_FULL1 WO

0x0

When the SPI is selected, the interrupt iscleared by the register of the SPI Slave.

－507/1293－

CXD5602 User Manual

3.9.12.3.151{0x552C} LEVEL_SEL_MAIN_AD Details
Table SCU (Sensor Control Unit)-303
Register Type: RW (read/write)

Local Address: 0x552C

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..3

ReservedRO

Reserved

2

LPADC_ALMOST_FULL3 RW

0x01

LPADC_ALMOST_FULL2 RW

0x00

LPADC_ALMOST_FULL1 RW

0x0

0x00000000－508/1293－

LPADC_ALMOST_FULL1LPADC_ALMOST_FULL3LPADC_ALMOST_FULL2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.3.152{0x5530} INT_RAW_STT_MAIN_AD Details
Table SCU (Sensor Control Unit)-304
Register Type: RO (read only)

Local Address: 0x5530

Reset Value: 0x00000000

Reserved

Bits

Name

31..3 Reserved

LPADC_ALMOST_FULL1LPADC_ALMOST_FULL3LPADC_ALMOST_FULL2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Type Reset Value Description
RO

0x00000000 Reserved

2

LPADC_ALMOST_FULL3 RO

0x0

1

LPADC_ALMOST_FULL2 RO

0x00

LPADC_ALMOST_FULL1 RO

0x0

Interrupt status of the SPI or Math Function
Event 0 before masking－509/1293－

CXD5602 User Manual

3.9.12.3.153{0x5534} INT_MASKED_STT_MAIN_AD Details
Table SCU (Sensor Control Unit)-305
Register Type: RO (read only)

Local Address: 0x5534

Reset Value: 0x00000000

Reserved

Bits

Name

Type

Reset Value Description

31..3 Reserved

RO

0x00000000 Reserved

2

LPADC_ALMOST_FULL3 RO

0x0

1

LPADC_ALMOST_FULL2 RO

0x00

LPADC_ALMOST_FULL1 RO

0x0

LPADC_ALMOST_FULL1LPADC_ALMOST_FULL3LPADC_ALMOST_FULL2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Interrupt status of the SPI or Math Function
Event 0 after masking－510/1293－

CXD5602 User Manual

3.9.12.3.154{0x5600} PWM0_PARAM Details
Table SCU (Sensor Control Unit)-306
Register Type: RW (read/write)

Local Address: 0x5600

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM0_THRESH

PWM0_CYCLE

Bits

Name

Type Reset Value

Description

31..16

PWM0_THRESH

RW

0x0000

Sets the duty of PWM0 output

15..0

PWM0_CYCLE

RW

0x0000

Sets the cycle of PWM0 output

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and as for the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－511/1293－

CXD5602 User Manual

3.9.12.3.155{0x5604} PWM0_EN Details

100: LPADC0 101: LPADC1 110: LPADC2 111: LPADC3
Table SCU (Sensor Control Unit)-307
Register Type: RW (read/write)

Local Address: 0x5604

Reset Value: 0x00000000

Reserved

PWM_SELL0

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM0_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM0 is
synchronized with

7..1

PWM_SELL0

RW

0x00

0x0:

is not synchronized with ADs

0x1:

is synchronized with HPADC00x2:

is synchronized with HPADC1

0x3:

is synchronized with LPADC in

operation
0x4:

is synchronized with LPADC0

0x5:

is synchronized with LPADC1

0x6:

is synchronized with LPADC2

0x7:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM0
is synchronized with
Controls the permission/stop of the PWM’s0

PWM0_EN

RW

0x0

operation.
The operation is permitted by writing “1”.
The operation is suspended by writing “0”.

－512/1293－

CXD5602 User Manual

3.9.12.3.156{0x5608} PWM0_UPDATE Details
Table SCU (Sensor Control Unit)-308
Register Type: RW (read/write)

Local Address: 0x5608

Reset Value: 0x00000000

PWM0_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM0_UPDATE

WO

0x0

3.9.12.3.157

Reflects a set value in PWM0’s operation by
writing “1” on this register.

{0x560C} PWM1_PARAM Details
Table SCU (Sensor Control Unit)-309
Register Type: RW (read/write)

Local Address: 0x560C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM1_THRESH

PWM1_CYCLE

Bits

Name

Type Reset Value

Description

31..16

PWM1_THRESH

RW

0x0000

Sets the duty of PWM1 output

15..0

PWM1_CYCLE

RW

0x0000

Sets the output cycle of PWM1

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and as for the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－513/1293－

CXD5602 User Manual

3.9.12.3.158{0x5610} PWM1_EN Details
Table SCU (Sensor Control Unit)-310
Register Type: RW (read/write)

Local Address: 0x5610

Reset Value: 0x00000000

Reserved

PWM_SELL1

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM1_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM1 issynchronized with

7..1

PWM_SELL1

RW

0x00

0x0:

is not synchronized with ADs

0x1:

is synchronized with HPADC00x2:

is synchronized with HPADC1

0x3:

is synchronized with LPADC in

operation
0x4:

is synchronized with LPADC0

0x5:

is synchronized with LPADC1

0x6:

is synchronized with LPADC2

0x7:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM1
is synchronized with
Controls the permission/stop of the PWM’s
0

PWM1_EN

RW

0x0

operation.
The operation is permitted by writing “1”.
The operation is suspended by writing “0”.

－514/1293－

CXD5602 User Manual

3.9.12.3.159{0x5614} PWM1_UPDATE Details
Table SCU (Sensor Control Unit)-311
Register Type: RW (read/write)

Local Address: 0x5614

Reset Value: 0x00000000

PWM1_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM1_UPDATE

WO

0x0

3.9.12.3.160

Reflects a set value in PWM1’s operation by
writing “1” on this register.

{0x5618} PWM2_PARAM Details
Table SCU (Sensor Control Unit)-312
Register Type: RW (read/write)

Local Address: 0x5618

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM2_THRESH

PWM2_CYCLE

Bits

Name

Type Reset Value

Description

31..16

PWM2_THRESH

RW

0x0000

Sets the duty of PWM2 output

15..0

PWM2_CYCLE

RW

0x0000

Sets the output cycle of PWM2

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－515/1293－

CXD5602 User Manual

3.9.12.3.161{0x561C} PWM2_EN Details
Table SCU (Sensor Control Unit)-313
Register Type: RW (read/write)

Local Address: 0x561C

Reset Value: 0x00000000

Reserved

PWM_SELL2

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM2_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM2 issynchronized with

7..1

PWM_SELL2

RW

0x00

0x0:

is not synchronized with ADs

0x1:

is synchronized with HPADC00x2:

is synchronized with HPADC1

0x3:

is synchronized with LPADC in

operation
0x4:

is synchronized with LPADC0

0x5:

is synchronized with LPADC1

0x6:

is synchronized with LPADC2

0x7:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM2
is synchronized with
Controls the permission/stop of the PWM’soperation.
The operation is permitted by writing “1”.
0

PWM2_ENRW

0x0

The operation is suspended by writing “0”.
Written values can always be read out.
Changed contents are reflected to the HW bywriting “1” in PWM2_UPDATE.

－516/1293－

CXD5602 User Manual

3.9.12.3.162{0x5620} PWM2_UPDATE Details
Table SCU (Sensor Control Unit)-314
Register Type: RW (read/write)

Local Address: 0x5620

Reset Value: 0x00000000

PWM2_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM2_UPDATE

WO

0x0

3.9.12.3.163

Reflects a set value in PWM2’s operation by
writing “1” on this register.

{0x5624} PWM3_PARAM Details
Table SCU (Sensor Control Unit)-315
Register Type: RW (read/write)

Local Address: 0x5624

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM3_THRESH

PWM3_CYCLE

Bits

Name

Type Reset Value

Description

31..16

PWM3_THRESH

RW

0x0000

Sets the duty of PWM3 output

15..0

PWM3_CYCLE

RW

0x0000

Sets the output cycle of PWM3

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and as for the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－517/1293－

CXD5602 User Manual

3.9.12.3.164{0x5628} PWM3_EN Details
Table SCU (Sensor Control Unit)-316
Register Type: RW (read/write)

Local Address: 0x5628

Reset Value: 0x00000000

Reserved

PWM_SELL3

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM3_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM3 issynchronized with

7..1

PWM_SELL3

RW

0x00

0x0:

is not synchronized with ADs

0x1:

is synchronized with HPADC00x2:

is synchronized with HPADC1

0x3:

is synchronized with LPADC in

operation
0x4:

is synchronized with LPADC0

0x5:

is synchronized with LPADC1

0x6:

is synchronized with LPADC2

0x7:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM3
is synchronized with
Controls the permission/stop of the PWM’soperation.
The operation is permitted by writing “1”.
0

PWM3_ENRW

0x0

The operation is suspended by writing “0”.
Written values can always be read out.
Changed contents are reflected to the HW bywriting “1” in PWM3_UPDATE.

－518/1293－

CXD5602 User Manual

3.9.12.3.165{0x562C} PWM3_UPDATE Details
Table SCU (Sensor Control Unit)-317
Register Type: RW (read/write)

Local Address: 0x562C

Reset Value: 0x00000000

PWM3_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM3_UPDATE

WO

0x0

Reflects a set value in PWM3’s operation by
writing “1” on this register.

－519/1293－

CXD5602 User Manual

3.9.12.3.166{0x5630} PWM_PASE0 Details
Table SCU (Sensor Control Unit)-318
Register Type: RW (read/write)

Local Address: 0x5630

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_CNTEN0
Bits

Name

PWM_DELAY0
Type Reset Value Description[19:16]: Sets the PWM prescale
0x0: 1/1
0x1: 1/2
0x2: 1/4
0x3: 1/8
0x4: 1/16
0x5: 1/32

31..16 PWM_CNTEN0

RW

0x0000

0x6: 1/64
0x7: 1/128
0x8: 1/256[23:20]: The number of AD capturing based on the PWM(from 1 to 15 available)[31:24]: Positioning for capturing AD based on the PWM(step is SCU_CK unit)(from 3 to 255 available)

15..0

PWM_DELAY0

RW

0x0000Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－520/1293－

CXD5602 User Manual

3.9.12.3.167{0x5634} PWM_PASE1 Details
Table SCU (Sensor Control Unit)-319
Register Type: RW (read/write)

Local Address: 0x5634

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_CNTEN1

PWM_DELAY1

Bits

Name

Type Reset Value

31..16

PWM_CNTEN1

RW

0x0000

15..0

PWM_DELAY1

RW

0x0000Description
PWM1 setting
for the control specification, refer to PWM_CNTEN0
Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－521/1293－

CXD5602 User Manual

3.9.12.3.168{0x5638} PWM_PASE2 Details
Table SCU (Sensor Control Unit)-320
Register Type: RW (read/write)

Local Address: 0x5638

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_CNTEN2
Bits

PWM_DELAY2

Name

Type

Reset Value

31..16 PWM_CNTEN2

RW

0x000015..0RW

0x0000PWM_DELAY2

Description
PWM2 setting
for the control specification, refer to PWM_CNTEN0
Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－522/1293－

CXD5602 User Manual

3.9.12.3.169{0x563C} PWM_PASE3 Details
Table SCU (Sensor Control Unit)-321
Register Type: RW (read/write)

Local Address: 0x563C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_CNTEN3

PWM_DELAY3

Bits

Name

Type Reset Value

31..16

PWM_CNTEN3

RW

0x0000

15..0

PWM_DELAY3

RW

0x0000Description
PWM3 setting
for the control specification, refer to PWM_CNTEN0
Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－523/1293－

CXD5602 User Manual

3.9.12.3.170{0x5640} PWM4_PARM Details
Table SCU (Sensor Control Unit)-322
Register Type: RW (read/write)

Local Address: 0x5640

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM4_THRESH

PWM4_CYCLE

Bits

Name

Type Reset Value

Description

31..16

PWM4_THRESH

RW

0x0000

Sets the duty of PWM4 output

15..0

PWM4_CYCLE

RW

0x0000

Sets the output cycle of PWM4

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and as for the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－524/1293－

CXD5602 User Manual

3.9.12.3.171{0x5644} PWM4_EN Details

100：LPADC0 101:LPADC1 110:LPADC2 111:LPADC3
Table SCU (Sensor Control Unit)-323
Register Type: RW (read/write)

Local Address: 0x5644

Reset Value: 0x00000000

Reserved

PWM_SELL4

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM4_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM4 issynchronized with

7..1

PWM_SELL4

RW

0x00

0x0:

is not synchronized with ADs

0x1:

is synchronized with HPADC00x2:

is synchronized with HPADC1

0x3:

is synchronized with LPADC in

operation
0x4:

is synchronized with LPADC0

0x5:

is synchronized with LPADC1

0x6:

is synchronized with LPADC2

0x7:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM4
is synchronized with
Controls the permission/stop of the PWM’soperation.
0

PWM4_ENRW

0x0

The operation is permitted by writing “1”.
The operation is suspended by writing “0”.
Changed contents are reflected to the HW bywriting “1” in PWM4_UPDATE.

－525/1293－

CXD5602 User Manual

3.9.12.3.172{0x5648} PWM4_UPDATE Details
Table SCU (Sensor Control Unit)-324
Register Type: RW (read/write)

Local Address: 0x5648

Reset Value: 0x00000000

PWM4_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM4_UPDATE

WO

0x0

Reflects a set value in PWM4’s operation by
writing “1” on this register.

－526/1293－

CXD5602 User Manual

3.9.12.3.173{0x564C} PWM5_PARAM Details
Table SCU (Sensor Control Unit)-325
Register Type: RW (read/write)

Local Address: 0x564C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM5_THRESH

PWM5_CYCLE

Bits

Name

Type Reset Value

Description

31..16

PWM5_THRESH

RW

0x0000

Sets the duty of PWM5 output

15..0

PWM5_CYCLE

RW

0x0000

Sets the output cycle of PWM5

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and as for the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－527/1293－

CXD5602 User Manual

3.9.12.3.174{0x5650} PWM5_EN Details
Table SCU (Sensor Control Unit)-326
Register Type: RW (read/write)

Local Address: 0x5650

Reset Value: 0x00000000

Reserved

PWM_SELL5

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM5_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM5 issynchronized with

7..1

PWM_SELL5

RW

0x00

000:

is not synchronized with ADs

001:

is synchronized with HPADC0002:

is synchronized with HPADC1003:

is synchronized with LPADC in

operation004:

is synchronized with LPADC0005:

is synchronized with LPADC1006:

is synchronized with LPADC2

007:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM5
is synchronized with
Controls the permission/stop of the PWM’soperation.
The operation is permitted by writing “1”.
0

PWM5_ENRW

0x0

The operation is suspended by writing “0”.
Written values can always be read out.
Changed contents are reflected to the HW bywriting “1” in PWM5_UPDATE.

－528/1293－

CXD5602 User Manual

3.9.12.3.175{0x5654} PWM5_UPDATE Details
Table SCU (Sensor Control Unit)-327
Register Type: RW (read/write)

Local Address: 0x5654

Reset Value: 0x00000000

PWM5_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM5_UPDATE

WO

0x0

Reflects a set value in PWM5’s operation by
writing “1” on this register.

－529/1293－

CXD5602 User Manual

3.9.12.3.176{0x5658} PWM6_PARAM Details
Table SCU (Sensor Control Unit)-328
Register Type: RW (read/write)

Local Address: 0x5658

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM6_THRESH

PWM6_CYCLE

Bits

Name

Type Reset Value

Description

31..16PWM6_THRESH

RW

0x0000

Sets the duty of PWM6 output

15..0

PWM6_CYCLE

RW

0x0000

Sets the output cycle of PWM6

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and as for the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－530/1293－

CXD5602 User Manual

3.9.12.3.177{0x565C} PWM6_EN Details
Table SCU (Sensor Control Unit)-329
Register Type: RW (read/write)

Local Address: 0x565C

Reset Value: 0x00000000

Reserved

PWM_SELL6

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM6_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM6 issynchronized with

7..1

PWM_SELL6

RW

0x00

000:

is not synchronized with ADs

001:

is synchronized with HPADC0002:

is synchronized with HPADC1003:

is synchronized with LPADC in

operation004:

is synchronized with LPADC0005:

is synchronized with LPADC1006:

is synchronized with LPADC2

007:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM6
is synchronized with
Controls the permission/stop of the PWM’soperation.
The operation is permitted by writing “1”.
0

PWM6_ENRW

0x0

The operation is suspended by writing “0”.
Written values can always be read out.
Changed contents are reflected to the HW bywriting “1” in PWM6_UPDATE.

－531/1293－

CXD5602 User Manual

3.9.12.3.178{0x5660} PWM6_UPDATE Details
Table SCU (Sensor Control Unit)-330
Register Type: RW (read/write)

Local Address: 0x5660

Reset Value: 0x00000000

PWM6_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM6_UPDATE

WO

0x0

Reflects a set value in PWM6’s operation by
writing “1” on this register.

－532/1293－

CXD5602 User Manual

3.9.12.3.179{0x5664} PWM7_PARAM Details
Table SCU (Sensor Control Unit)-331
Register Type: RW (read/write)

Local Address: 0x5664

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM7_THRESH

PWM7_CYCLE

Bits

Name

Type Reset Value

Description

31..16

PWM7_THRESH

RW

0x0000

Sets the duty of PWM7 output

15..0

PWM7_CYCLE

RW

0x0000

Sets the output cycle of PWM7

For formulas of the cycle and the DUTY, refer to the below.
As for the formula of the PWM cycle, refer to Section 3.9.11.2.1, and as for the formula of the DUTY (period of
HIGH/cycle) of the PWM output, refer to Section 3.9.11.2.2.

－533/1293－

CXD5602 User Manual

3.9.12.3.180{0x5668} PWM7_EN Details
Table SCU (Sensor Control Unit)-332
Register Type: RW (read/write)

Local Address: 0x5668

Reset Value: 0x00000000

Reserved

PWM_SELL7

Bits

Name

Type Reset Value

Description

31..8

ReservedRO

Reserved

0x000000

PWM7_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0[3:1]: Selects a target AD which the PWM7 issynchronized with

7..1

PWM_SELL7

RW

0x00

000:

is not synchronized with ADs

001:

is synchronized with HPADC0002:

is synchronized with HPADC1003:

is synchronized with LPADC in

operation004:

is synchronized with LPADC0005:

is synchronized with LPADC1006:

is synchronized with LPADC2

007:

is synchronized with LPADC3[6:4]: Selects a target PWM which the PWM7
is synchronized with
Controls the permission/stop of the PWM’soperation.
The operation is permitted by writing “1”.
0

PWM7_ENRW

0x0

The operation is suspended by writing “0”.
Written values can always be read out.
Changed contents are reflected to the HW bywriting “1” in PWM7_UPDATE.

－534/1293－

CXD5602 User Manual

3.9.12.3.181{0x566C} PWM7_UPDATE Details
Table SCU (Sensor Control Unit)-333
Register Type: RW (read/write)

Local Address: 0x566C

Reset Value: 0x00000000

PWM7_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

PWM7_UPDATE

WO

0x0

Reflects a set value in PWM7’s operation by
writing “1” on this register.

－535/1293－

CXD5602 User Manual

3.9.12.3.182{0x5670} PWM_PASE4 Details
Table SCU (Sensor Control Unit)-334
Register Type: RW (read/write)

Local Address: 0x5670

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_CNTEN4
Bits

Name

PWM_DELAY4
Type Reset Value

31..16 PWM_CNTEN4

RW

0x000015..0RW

0x0000PWM_DELAY4

Description
PWM4 setting
for the control specification, refer to PWM_CNTEN0
Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－536/1293－

CXD5602 User Manual

3.9.12.3.183{0x5674} PWM_PASE5 Details
Table SCU (Sensor Control Unit)-335
Register Type: RW (read/write)

Local Address: 0x5674

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM_CNTEN5

Bits

Name

PWM_DELAY5Type Reset Value

31..16 PWM_CNTEN5

RW

0x000015..0RW

0x0000PWM_DELAY5

Description
PWM5 setting
for the control specification, refer to PWM_CNTEN0
Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－537/1293－

CXD5602 User Manual

3.9.12.3.184{0x5678} PWM_PASE6 Details
Table SCU (Sensor Control Unit)-336
Register Type: RW (read/write)

Local Address: 0x5678

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM_CNTEN6

Bits

Name

PWM_DELAY6

Type Reset Value

31..16 PWM_CNTEN6

RW

0x000015..0RW

0x0000PWM_DELAY6

Description
PWM6 setting
for the control specification, refer to PWM_CNTEN0
Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－538/1293－

CXD5602 User Manual

3.9.12.3.185{0x567C} PWM_PASE7 Details
Table SCU (Sensor Control Unit)-337
Register Type: RW (read/write)

Local Address: 0x567C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_CNTEN7
Bits

Name

PWM_DELAY7
Type Reset Value

31..16 PWM_CNTEN7

RW

0x000015..0RW

0x0000PWM_DELAY7

Description
PWM7 setting
for the control specification, refer to PWM_CNTEN0
Adjusts phases for the timing of AD data capturing(to SCU unit 0-65535 clock)－539/1293－

CXD5602 User Manual

3.9.12.3.186{0x5680} PWM_TIMER01 details

When the PWM is not used, PWM generator can be used as a timer. In this case, counter values within the timer
can be read.
Table SCU (Sensor Control Unit)-338
Register Type: RO (read only)

Local Address: 0x5680

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER1TIMER0

Bits

Name

Type Reset Value

Description

31..16

TIMER1

RO

0x0000Counter value of PWM1

15..0

TIMER0RO

0x00003.9.12.3.187

Counter value of PWM0{0x5684} PWM_TIMER23 Details

When the PWM is not used, PWM generator can be used as a timer. In this case, counter values within the timer
can be read.
Table SCU (Sensor Control Unit)-339
Register Type: RO (read only)

Local Address: 0x5684

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER3

TIMER2Bits

Name

Type Reset Value

Description

31..16

TIMER3

RO

0x0000Counter value of PWM3

15..0

TIMER2

RO

0x0000Counter value of PWM2

－540/1293－

CXD5602 User Manual

3.9.12.3.188{0x5688} PWM_TIMER45 Details

When the PWM is not used, PWM generator can be used as a timer. In this case, counter values within the timer
can be read.
Table SCU (Sensor Control Unit)-340
Register Type: RO (read only)

Local Address: 0x5688

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER5

TIMER4Bits

Name

Type Reset Value

Description

31..16

TIMER5RO

0x0000Counter value of PWM5

15..0

TIMER4

RO

0x0000Counter value of PWM4

3.9.12.3.189{0x568C} PWM_TIMER67 Details

When the PWM is not used, PWM generator can be used as a timer. In this case, counter values within the timer
can be read.
Table SCU (Sensor Control Unit)-341
Register Type: RO (read only)

Local Address: 0x568C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER7

TIMER6Bits

Name

Type Reset Value

Description

31..16

TIMER7RO

0x0000Counter value of PWM7

15..0

TIMER6

RO

0x0000Counter value of PWM6

－541/1293－

CXD5602 User Manual

3.9.12.3.190{0x5690} PWM_FUNCSEL0 Details

When synthesizing the PWM, you can designate the polarity of the source PWM (for PWM0-3).
Table SCU (Sensor Control Unit)-342
Register Type: RW (read/write)

Local Address: 0x5690

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_SEL_INV3

PWM_SEL_INV2

PWM_SEL_INV1

Bits

Name

Type Reset Value

31..24PWM_SEL_INV3

RW

0x00

23..16PWM_SEL_INV2

RW

0x00

15..8

PWM_SEL_INV1

RW

0x00

7..0

PWM_SEL_INV0

RW

0x00

3.9.12.3.191

PWM_SEL_INV0

Description{0x5694} PWM_FUNC1 Details

When synthesizing the PWM, you can designate the polarity of the source PWM (for PWM4-7).
Table SCU (Sensor Control Unit)-343
Register Type: RW (read/write)

Local Address: 0x5694

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM_SEL_INV7

PWM_SEL_INV6

PWM_SEL_INV5

Bits

Name

Type Reset Value

31..24PWM_SEL_INV7

RW

0x00

23..16PWM_SEL_INV6

RW

0x00

15..8

PWM_SEL_INV5

RW

0x00

7..0

PWM_SEL_INV4

RW

0x00

Description－542/1293－

PWM_SEL_INV4

CXD5602 User Manual

3.9.12.3.192{0x5698} PWM_FUCN2 Details

When synthesizing the PWM, you can designate whether to use the PWM or not (for PWM0-3).
Table SCU (Sensor Control Unit)-344
Register Type: RW (read/write)

Local Address: 0x5698

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM_SEL_DIS3

PWM_SEL_DIS2

PWM_SEL_DIS1

Bits

Name

Type Reset Value

31..24PWM_SEL_DIS3

RW

0x00

23..16PWM_SEL_DIS2

RW

0x00

15..8

PWM_SEL_DIS1

RW

0x00

7..0

PWM_SEL_DIS0

RW

0x00

3.9.12.3.193

PWM_SEL_DIS0

Description{0x569C} PWM_FUNC3 Details

When synthesizing the PWM, you can designate whether to use the PWM or not (for PWM4-7).
Table SCU (Sensor Control Unit)-345
Register Type: RW (read/write)

Local Address: 0x569C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM_SEL_DIS7

PWM_SEL_DIS6

PWM_SEL_DIS5

PWM_SEL_DIS4

Bits

Name

Type Reset Value

Description

31..24PWM_SEL_DIS7

RW

0x00

Invalid because the HWdoes not exist

23..16PWM_SEL_DIS6

RW

0x00

Invalid because the HWdoes not exist

15..8

PWM_SEL_DIS5

RW

0x00

Invalid because the HWdoes not exist

7..0

PWM_SEL_DIS4

RW

0x00

Invalid because the HWdoes not exist－543/1293－

CXD5602 User Manual

3.9.12.3.194{0x56A0} PWM_FUNC4 Details

You can select synthesis by ANDing or ORing PWMs (0: AND, 1: OR)
Table SCU (Sensor Control Unit)-346
Register Type: RW (read/write)

Local Address: 0x56A0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM_SEL7 PWM_SEL6 PWM_SEL5 PWM_SEL4 PWM_SEL3 PWM_SEL2 PWM_SEL1 PWM_SEL0

Bits

Name

Type Reset Value

Description

31..28PWM_SEL7RW

0x0

Invalid setting

27..24PWM_SEL6RW

0x0

Invalid setting

23..20PWM_SEL5RW

0x0

Invalid setting

19..16PWM_SEL4RW

0x0

Invalid setting

15..12PWM_SEL3

RW

0x0

For PWM3 unit

11..8

PWM_SEL2

RW

0x0

For PWM2 unit

7..4

PWM_SEL1

RW

0x0

For PWM1 unit

3..0

PWM_SEL0RW

0x0

For PWM0 unit

－544/1293－

CXD5602 User Manual

3.9.12.3.195{0x56A4} POWER_EN Details

Prohibited setting
Table SCU (Sensor Control Unit)-347
Register Type: RW (read/write)

Local Address: 0x56A4

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

POWER_EN

Bits

Name

Type Reset Value

Description

31..16

Reserved

RO

0x0000Reserved

15..0

POWER_EN

RW

0xFFFF

Prohibited setting－545/1293－

CXD5602 User Manual

3.9.12.3.196{0x0 .. 0x3FFC} SEQ_IRAM Details

Instruction RAM array for internal sequencer
Refer to Section 3.9.12.11.
Table SCU (Sensor Control Unit)-348
Memory Type: RW (read/write)

Local Address: 0x0

Reset Value: 0xxxxxxxxx

Bits

Name

Type Reset Value

Description

31..0

SEQ_IRAM

RW

Instruction RAM array for internal sequencer

3.9.12.3.197

0xxxxxxxxx{0x4000 .. 0x4FFC} SEQ_DRAM Details

Data Ram array for internal sequencer
Table SCU (Sensor Control Unit)-349
Memory Type: RW (read/write)

Local Address: 0x4000

Reset Value: 0xxxxxxxxx

Bits

Name

Type Reset Value

Description

31..0

SEQ_DRAM

RW

Data Ram array for internal sequencer

0xxxxxxxxx－546/1293－

CXD5602 User Manual

3.9.12.4

SCU_ADCIF_REG Register List

The following describes 32 bit address offset from the CPU. For calculating the address from the CPU, add thisaddress to each offset in the table.
Offset:0x0018dc00 (Mirror:0x0418dc00)
For the offset Address from 0x0200 to 0x03D4 of the ADCIF control registers, refer to Chapter of ADC (3.21).

3.9.12.5

SCU_MATH_PROC_REG Overview

Only sequencers in the SCU can access this register.
The following describes 32 bit address offsets which can be seen from the sequencers in the SCU. For calculating
the address to access from the sequencer in the CPU, add this address to each offset in the table.
Offset:0x0000e000

3.9.12.6

SCU_MATH_PROC_REG Register List
Table SCU (Sensor Control Unit)-350

OffsetAddress

Name

Type

Size (bits)

Description

Reset Value

0x0

MATH_PROC_EXE

RO

32

0x00000000

0x4

WRITE_DATA_SET0

RW

320x00000000

0x8

WRITE_DATA_SET1

RW

320x00000000

0xC

WRITE_DATA_SET2

RW

320x00000000

0x10

WRITE_DATA_SET3

RW

320x00000000

0x14

WRITE_DATA_SET4

RW

320x00000000

0x18

WRITE_DATA_SET5RW

320x00000000

0x80

READ_DATA_SET0RO

320x00000000

0x84

READ_DATA_SET1

RO

320x00000000

0x88

READ_DATA_SET2

WO

320x00000000(Transaction Port)－547/1293－

CXD5602 User Manual

3.9.12.6.1{0x0} MATH_PROC_EXE Details
Table SCU (Sensor Control Unit)-351
Register Type: RO (read only)

Local Address: 0x0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

Bits

Name

31..16 Reserved

MATH_PROC_EXE

Type
RO

Reset
Value

Description

0x0000 Reserved
This is a flag of determining whether MATH_PROC should beexecuted or not.
1: Performs MATH_PROC processing
0, 4, 8 to 15 bit only: valid
The following describes the conditions that the value of
MATH_PROC_EXE becomes “1”.
0, 4 bit: When if any of the following (1), (2), and (3) are true
(1) When OFST_GAIN_EN{0x5070} of MATHID which you use
is “1”

15..0

MATH_PRO
C_EXE

RO

0x0000(2) When MATHFUNC_SEL{0x508c} of MATHID which you
use is set(3) When the set value for DECIMATION_PARAM0/1{0x5084/0x5088} of MATHID which you use is ’d9 or less
8 to 15 bit: When if any of the following (1) and (2) are true
(1) When OFST_GAIN_EN{0x5070} of MATHID which you use
is “1”(2) When MATHFUNC_SEL{0x508c} of MATHID which you
use is set
Refer to Section 3.9.9.9.

－548/1293－

CXD5602 User Manual

3.9.12.6.2{0x4} WRITE_DATA_SET0 Details
Table SCU (Sensor Control Unit)-352
Register Type: RW (read/write)

Local Address: 0x4

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value Description

31..16

DATA_X

RW

0x000015..10Reserved

RO

0x00

Reserved

FIFO_W_ID

DATA_XVEC_ELE_NUM

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Vector element X of the target data for processing
requestReserved
The number of Vector element X of the target data

9..8

VEC_ELE_NUM

RW

0x0

for processing request“0” is equivalent to “1” element.
You can select one integer from 1, 2, and 3.

7..4

Reserved

RO

0x0

3..0

FIFO_W_ID

RW

0x0

Reserved
You can select one integer for MATH ID forprocessing request from 0, 4, 8 to 15.

－549/1293－

CXD5602 User Manual

3.9.12.6.3{0x8} WRITE_DATA_SET1 Details
Table SCU (Sensor Control Unit)-353
Register Type: RW (read/write)

Local Address: 0x8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_Z

DATA_Y

Bits

NameType Reset Value

31..16

DATA_Z

RW

0x000015..0

DATA_Y

RW

0x00003.9.12.6.4

Description{0xC} WRITE_DATA_SET2 Details
Table SCU (Sensor Control Unit)-354
Register Type: RW (read/write)

Local Address: 0xC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GAIN_XOFST_X

Bits

Name

Type Reset Value

31..16

GAIN_X

RW

0x0000

15..0

OFST_X

RW

0x0000Description－550/1293－

CXD5602 User Manual

3.9.12.6.5{0x10} WRITE_DATA_SET3 Details
Table SCU (Sensor Control Unit)-355
Register Type: RW (read/write)

Local Address: 0x10

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GAIN_Y

OFST_Y

Bits

NameType Reset Value

31..16

GAIN_Y

RW

0x0000

15..0

OFST_Y

RW

0x00003.9.12.6.6

Description{0x14} WRITE_DATA_SET4 Details
Table SCU (Sensor Control Unit)-356
Register Type: RW (read/write)

Local Address: 0x14

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GAIN_Z

OFST_Z

Bits

Name

Type Reset Value

31..16

GAIN_Z

RW

0x0000

15..0

OFST_Z

RW

0x0000Description－551/1293－

CXD5602 User Manual

3.9.12.6.7{0x18} WRITE_DATA_SET5 Details
Table SCU (Sensor Control Unit)-357
Register Type: RW (read/write)

Local Address: 0x18

Reset Value: 0x00000000

DATA_UPDATE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type

Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved
This can be set if some changes need to be made0

DATA_UPDATE

RW

0x0

between

WRITE_DATA_SET0

WRITE_DATA_SET5, or if MATH is executed.

－552/1293－

andCXD5602 User Manual

3.9.12.6.8{0x80} READ_DATA_SET0 Details
Table SCU (Sensor Control Unit)-358
Register Type: RO (read only)

Local Address: 0x80

Reset Value: 0x00000000

Bits

Name

Reserved

Type

Reset Value Description

31..16 DATA_X

RO

0x000015..10 Reserved

RO

0x00

9..8

VEC_ELE_NUM RO

0x0

7..4

Reserved

0x0

RO

Reserved

FIFO_W_ID

DATA_XVEC_ELE_NUM

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reserved
MATH ID (from 0 to 15) which is requested to process

3..0

FIFO_W_ID

RO0x0

is output.
The order in which the MATH ID is output is not thesame as the order of the input.

－553/1293－

CXD5602 User Manual

3.9.12.6.9{0x84} READ_DATA_SET1 Details
Table SCU (Sensor Control Unit)-359
Register Type: RO (read only)

Local Address: 0x84

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_Z

DATA_Y

Bits

NameType Reset Value

31..16

DATA_ZRO

0x000015..0

DATA_YRO

0x00003.9.12.6.10

Description{0x88} READ_DATA_SET2 Details
Table SCU (Sensor Control Unit)-360
Register Type: WO (write only)

Local Address: 0x88

Reset Value: 0x00000000

DATA_READ_DONE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

WO

Reserved0

DATA_READ_DONE WO

0x00000000
0x0－554/1293－

CXD5602 User Manual

3.9.12.7

SCU_SEQ_REG Overview

Only sequencers in the SCU can access these registers.
The following describes 32 bit address offset which can be seen from the sequencer in the SCU. For calculating
the address to access from the sequencer in the SCU, add this Offset: 0x0000e400 to each Offset Address(Transaction Port) in the table.
Offset: 0x0000e400

3.9.12.8

SCU_SEQ_REG Register List
Table SCU (Sensor Control Unit)-361

OffsetAddress

Name

Type

Size (bits)

Description

Reset Value

0x0

EXTERNAL_STT0

RO

320x00000000

0x4

EXTERNAL_STT1

RO

32

0x00000000

0x8

START_CTRL

WO

320x00000000

0x10

ISOPSTT

RW

32

0x00000000

0x14

ISOPINT

RW

320x00000000

0x18

POWER_CTRL

RW

320x00000000

0x20

TIME_STAMP_MSB

RO

32

0x00000000

0x24

TIME_STAMP_LSB

RO

320x00000000

0x40

ISOPMONOUT

RW

320x00000000

0x44

SCU_ISOP_POWER

RW

32(Transaction Port)

0: CK_SCU

0x00000000

1: CK_SPI
2: CK_I2C0
3: CK_I2C1
0x190

TIMER_SEL

RW

32－555/1293－

0x00000000

CXD5602 User Manual

3.9.12.8.1{0x0} EXTERNAL_STT0 Details
Table SCU (Sensor Control Unit)-362
Register Type: RO (read only)

Local Address: 0x0

Reset Value: 0x00000000

Bits

Name

Type

Reset Value Description

31

TIMER_INT2

RO

0x0

30

TIMER_INT1

RO

0x0

29

TIMER_INT0

RO

0x0

28

FIFO1_ALL_ON_STT

RO

0x0

27

FIFO0_ALL_ON_STT

RO

0x0

RO

0x0

RO

0x0

26

25

MATH_PROC_READ_DATA_R
EADY
MATH_PROC_WRITE_DATA_
READY

24

HPADC1_NOT_EMPTY

RO

0x0

23

HPADC0_NOT_EMPTY

RO

0x0

22

LPADC_NOT_EMPTY3

RO

0x0

21

LPADC_NOT_EMPTY2

RO

0x0

APB_ACCESS_INHIBITPWD_SPI_ON_STT

PWD_I2C_ON_STT

I2C0_RX_ALMOST_FULL

I2C0_MASTER_ON_HOLD

I2C0_ACTIVE

I2C1_RX_ALMOST_FULL

I2C1_MASTER_ON_HOLD

I2C1_ACTIVE

LPADC_NOT_EMPTY0

LPADC_NOT_EMPTY1

LPADC_NOT_EMPTY2

LPADC_NOT_EMPTY3HPADC0_NOT_EMPTY

HPADC1_NOT_EMPTY

MATH_PROC_WRITE_DATA_READY

MATH_PROC_READ_DATA_READY

FIFO0_ALL_ON_STT

FIFO1_ALL_ON_STTTIMER_INT0

TIMER_INT1

TIMER_INT2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7 6

5

4

3

2

1

0

EXE_REQ_STT

Indicates that the power supply state of FIFO SRAM
32KByte region is All On
Indicates that the power supply state of FIFO SRAM
8KByte region is All On.
Indicates the status that the readout from MATH_PROC
is possible
Indicates the status that the write to MATH_PROC ispossible
Indicates that one or more data exist in the FIFO for
HPADC1
Indicates that one or more data exist in the FIFO for
HPADC0Indicates that one or more data exist in the FIFO for
LPADC
Indicates that one or more data exist in the FIFO for
LPADC－556/1293－

CXD5602 User Manual

Indicates that one or more data exist in the FIFO for20

LPADC_NOT_EMPTY1

RO

0x0

19

LPADC_NOT_EMPTY0

RO

0x0

18

I2C1_ACTIVE

RO

0x0

17

I2C1_MASTER_ON_HOLD

RO

0x0

16

I2C1_RX_ALMOST_FULL

RO

0x0

15

I2C0_ACTIVE

RO

0x0

14

I2C0_MASTER_ON_HOLD

RO

0x0

13

I2C0_RX_ALMOST_FULL

RO

0x0

12

PWD_I2C_ON_STT

RO

0x0

Power supply status of PWD_I2C

11

PWD_SPI_ON_STT

RO

0x0

Power supply status of PWD_ SPI

10

APB_ACCESS_INHIBIT

RO

0x0

ORed signal of ACCESS_INHIBIT

9..0

EXE_REQ_STT

RO

0x000

Execution request to each sequencer

LPADC
Indicates that one or more data exist in the FIFO for
LPADC
Indicates the operation active status of I2C1
Indicates that the status is I2C1 TX_FIFO Empty, but a
STOP command has not been issued
Indicates that more data than designated exist in the RX
FIFO of I2C1
Indicates the operation active status of I2C0
Indicates that the status is I2C0 TX_FIFO Empty, but a
STOP command has not been issued
Indicates that more data than designated exist in the RX
FIFO of I2C0－557/1293－

CXD5602 User Manual

3.9.12.8.2{0x4} EXTERNAL_STT1 Details
Table SCU (Sensor Control Unit)-363
Register Type: RO (read only)

Local Address: 0x4

Reset Value: 0x00000000

Reset

SPI_ACCESS_INHIBITHPADC1_ACCESS_INHIBITHPADC0_ACCESS_INHIBITLPADC_ACCESS_INHIBIT
I2C1_ACCESS_INHIBIT
I2C0_ACCESS_INHIBIT

Reserved

APB_ACCESS_ERR
DRAM_ALL_ON_STT

MATH_EVENT_R

MATH_EVENT_F

I2C0_FSM_STATUS

Reserved

I2C1_FSM_STATUS

LPADC_ACCESS_INHIBIT3
LPADC_ACCESS_INHIBIT2LPADC_ACCESS_INHIBIT1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bits

Name

Type

31

LPADC_ACCESS_INHIBIT3

RO

0x0

30

LPADC_ACCESS_INHIBIT2

RO

0x0

29

LPADC_ACCESS_INHIBIT1

RO

0x0

28..24 I2C1_FSM_STATUS

RO

0x00

FSM status of I2C1

23..21 Reserved

RO

0x0

Reserved

20..16 I2C0_FSM_STATUS

RO

0x00

FSM status of I2C0

15..13 MATH_EVENT_F

RO

0x0

The status of Math Function interrupt to the CPU

12..10 MATH_EVENT_R

RO

0x0

The status of Math Function interrupt to the CPU9

APB_ACCESS_ERR

RO

0x0

Indicates “1” when APB error occurs

8

DRAM_ALL_ON_STT

RO

0x0

7..6

Reserved

RO

0x0

5

HPADC1_ACCESS_INHIBIT

RO

0x0

4

HPADC0_ACCESS_INHIBIT

RO

0x0

Refer to HPADC1_ACCESS_INHIBIT3

LPADC_ACCESS_INHIBIT

RO

0x0

Refer to HPADC1_ACCESS_INHIBIT2

I2C1_ACCESS_INHIBIT

RO

0x0

Refer to HPADC1_ACCESS_INHIBIT1

I2C0_ACCESS_INHIBIT

RO

0x0

Refer to HPADC1_ACCESS_INHIBIT0

SPI_ACCESS_INHIBIT

RO

0x0

Refer to HPADC1_ACCESS_INHIBIT

Value

Description

Indicates the power supply status of the internalsequencer SEQ_DRAM
Reserved
Indicates that the sequencer is inhibited fromaccessing the target APB Slave－558/1293－

CXD5602 User Manual

3.9.12.8.3{0x8} START_CTRL Details
Table SCU (Sensor Control Unit)-364
Register Type: WO (write only)

Local Address: 0x8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

EXE_ERR

Reserved

Bits

Name

Type Reset Value

Description

31..26

Reserved

WO

0x00

Reserved

25..16

EXE_ERR

WO

0x000

15..10Reserved

WO

0x00

9..0

EXE_DONE

WO

0x000

EXE_DONE

Indicates error notification of each sequencer
when executed
Reserved
Indicates execution-completed notification ofeach sequencer－559/1293－

CXD5602 User Manual

3.9.12.8.4{0x10} ISOPSTT Details
Table SCU (Sensor Control Unit)-365
Register Type: RW (read/write)

Local Address: 0x10

Reset Value: 0x00000000

Reserved

Reset

Bits

Name

Type

31

LPADC_ACCESS_INHIBIT_ACK3

RW

0x0

30

LPADC_ACCESS_INHIBIT_ACK2

RW

0x0

29

LPADC_ACCESS_INHIBIT_ACK1

RW

0x0

28..17 Reserved

RO

0x000 Reserved

16

ISOP_READY

RW

0x0

15..6

Reserved

RO

0x000 Reserved

5

HPADC1_ACCESS_INHIBIT_ACK

RW

0x0

4

HPADC0_ACCESS_INHIBIT_ACK

RW

0x0

3

LPADC_ACCESS_INHIBIT_ACK

RW

0x0

2

I2C1_ACCESS_INHIBIT_ACK

RW

0x0

1

I2C0_ACCESS_INHIBIT_ACK

RW

0x0

0

SPI_ACCESS_INHIBIT_ACK

RW

0x0

Value

－560/1293－

SPI_ACCESS_INHIBIT_ACK

HPADC1_ACCESS_INHIBIT_ACK
HPADC0_ACCESS_INHIBIT_ACK
LPADC_ACCESS_INHIBIT_ACK
I2C1_ACCESS_INHIBIT_ACK
I2C0_ACCESS_INHIBIT_ACK

Reserved
ISOP_READYLPADC_ACCESS_INHIBIT_ACK3
LPADC_ACCESS_INHIBIT_ACK2
LPADC_ACCESS_INHIBIT_ACK1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description

Indicates “1” when the boot of theinternal sequencer has been completed
ACK output in response to the INHIBIT
requestRefer

to

HPADC1_ACCESS_INHIBIT_ACK
Refer

to

HPADC1_ACCESS_INHIBIT_ACK
Refer

to

HPADC1_ACCESS_INHIBIT_ACK
Refer

to

HPADC1_ACCESS_INHIBIT_ACK
Refer
HPADC1_ACCESS_INHIBIT_ACKtoCXD5602 User Manual

3.9.12.8.5{0x14} ISOPINT Details
Table SCU (Sensor Control Unit)-366
Register Type: RW (read/write)

Local Address: 0x14

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

ISOP_INT

Bits

Name

Type

Reset Value

Description

31..4

Reserved

RO

0x0000000

Reserved

3..0

ISOP_INT

RW

0x0

Information interrupt output to the CPU (used for SW
definition)－561/1293－

CXD5602 User Manual

3.9.12.8.6{0x18} POWER_CTRL Details
Table SCU (Sensor Control Unit)-367
Register Type: RW (read/write)

Local Address: 0x18

Reset Value: 0x00000000

Bits

Reserved

Name

Type

Value

RO

0x00

24

WO

0x0

RO

0x00

17

FIFO1_RETENTION_REQ RW

0x0

16

FIFO0_RETENTION_REQ RW

0x0

APB_ACCESS_ERR_CLR

23..18 Reserved

Reserved

Reset

31..25 Reserved

15..10 Reserved

RO

0x00

9

FIFO1_ALL_ON_REQ

RW

0x0

8

FIFO0_ALL_ON_REQ

RW

0x0

7..0

Reserved

RO

0x00

FIFO1_ALL_ON_REQ
FIFO0_ALL_ON_REQ

FIFO1_RETENTION_REQ
FIFO0_RETENTION_REQ

Reserved

APB_ACCESS_ERR_CLR

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Description
Reserved
Clear

the

APB_ACCESS_ERR

in

EXTERNAL_STT1
Reserved
Requests for the retention of the power supply
status of FIFO SRAM 32 KByte region
Requests for the retention of the power supply
status of FIFO SRAM 8 KByte region
Reserved
Requests that the power supply status of FIFOSRAM 34 KByte region turn All On
Requests that the power supply status of FIFOSRAM 6 KByte region turn All On
Reserved－562/1293－

CXD5602 User Manual

3.9.12.8.7{0x20} TIME_STAMP_MSB Details
Table SCU (Sensor Control Unit)-368
Register Type: RO (read only)

Local Address: 0x20

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIME_STAMP_46_15

Bits

Name

Type Reset Value

31..0

TIME_STAMP_46_15

RO

3.9.12.8.8

0x00000000

Description
Time stamp information with 47 bit data width
on the MSB side

{0x24} TIME_STAMP_LSB Details
Table SCU (Sensor Control Unit)-369
Register Type: RO (read only)

Local Address: 0x24

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME_STAMP_31_0
Bits

Name

Type Reset Value

31..0

TIME_STAMP_31_0 RO

0x00000000

Description
Time stamp information with 47 bit data width
on the LSB side－563/1293－

CXD5602 User Manual

3.9.12.8.9{0x40} ISOPMONOUT Details
Table SCU (Sensor Control Unit)-370
Register Type: RW (read/write)

Local Address: 0x40

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

MON1

Reserved

Bits

Name

Type Reset Value

Description

31..26

Reserved

RO

0x00

Reserved

25..16

MON1

RW

0x000

15..10Reserved

RO

0x00

9..0

MON0

RW

0x000

MON0

Indicates debug monitor output for theexternal pin output
Reserved
Indicates debug monitor output for theexternal pin output－564/1293－

CXD5602 User Manual

3.9.12.8.10{0x44} SCU_ISOP_POWER Details

0: CK_SCU 1: CK_SPI 2: CK_I2C0 3: CK_I2C1
Table SCU (Sensor Control Unit)-371
Register Type: RW (read/write)

Local Address: 0x44

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

CLK_EN

Bits

Name

Type Reset Value

Description

31..5

Reserved

RO

0x0000000

Reserved

4..0

CLK_EN

RW

0x00

3.9.12.8.11{0x190} TIMER_SEL Details
Table SCU (Sensor Control Unit)-372
Register Type: RW (read/write)

Local Address: 0x190

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TIMWE_SEL2

TIMWE_SEL1

Bits

Name

Type Reset Value

Description

31..24

Reserved

RO

0x00

Reserved

23..16TIMWE_SEL2

RW

0x00

15..8

TIMWE_SEL1

RW

0x00

7..0

TIMWE_SEL0

RW

0x00

－565/1293－

TIMWE_SEL0

CXD5602 User Manual

3.9.12.9

SCU_FIFO_REG Overview

Offset:0x00180000 (Mirror:0x04180000)
The following describes 32 bit address offset from the CPU. For calculating the address from the CPU, add this
Offset: 0x0000e400 to each Offset Address (Transaction Port) in the table.
Offset: 0x0000e400

3.9.12.10

SCU_FIFO_REG Register List
Table SCU (Sensor Control Unit)-373 SCU_FIFO_REG Register List

OffsetAddress

Name

Type

Size (bits)

Description

Reset Value

0x0

D0_W0_S_CTRL0RW

32

0xA0000000

0x4

D0_W0_S_CTRL1

RW

320x00000000

0x8

D0_W0_S_STATUS

RO

320x00000000

0xC

D0_W0_S_TIMSTAMP0RO

320x00000000

0x10

D0_W0_S_TIMSTAMP1

RO

320x00000000

0x20

D0_W1_S_CTRL0RW

32

0xA0000000

0x24

D0_W1_S_CTRL1

RW

320x00000000

0x28

D0_W1_S_STATUS

RO

320x00000000

0x2C

D0_W1_S_TIMSTAMP0RO

320x00000000

0x30

D0_W1_S_TIMSTAMP1

RO

320x00000000

0x40

D0_W2_S_CTRL0RW

32

0xA0000000

0x44

D0_W2_S_CTRL1

RW

320x00000000

0x48

D0_W2_S_STATUS

RO

320x00000000

0x4C

D0_W2_S_TIMSTAMP0RO

320x00000000

0x50

D0_W2_S_TIMSTAMP1

RO

320x00000000

0x60

D0_W3_S_CTRL0RW

32

0xA0000000

0x64

D0_W3_S_CTRL1

RW

320x00000000

0x68

D0_W3_S_STATUS

RO

320x00000000

0x6C

D0_W3_S_TIMSTAMP0RO

320x00000000

0x70

D0_W3_S_TIMSTAMP1

RO

320x00000000

0x80

D1_W0_S_CTRL0RW

32

0xA0000000

0x84

D1_W0_S_CTRL1

RW

320x00000000

0x88

D1_W0_S_STATUS

RO

320x00000000

0x8C

D1_W0_S_TIMSTAMP0RO

320x00000000(Transaction
Port)－566/1293－

CXD5602 User Manual

0x90

D1_W0_S_TIMSTAMP1

RO

320x00000000

0xA0

D1_W1_S_CTRL0RW

32

0xA0000000

0xA4

D1_W1_S_CTRL1

RW

320x00000000

0xA8

D1_W1_S_STATUS

RO

320x00000000

0xAC

D1_W1_S_TIMSTAMP0RO

320x00000000

0xB0

D1_W1_S_TIMSTAMP1

RO

320x00000000

0xC0

D1_W2_S_CTRL0RW

32

0xA0000000

0xC4

D1_W2_S_CTRL1

RW

320x00000000

0xC8

D1_W2_S_STATUS

RO

320x00000000

0xCC

D1_W2_S_TIMSTAMP0RO

320x00000000

0xD0

D1_W2_S_TIMSTAMP1

RO

320x00000000

0xE0

D1_W3_S_CTRL0RW

32

0xA0000000

0xE4

D1_W3_S_CTRL1

RW

320x00000000

0xE8

D1_W3_S_STATUS

RO

320x00000000

0xEC

D1_W3_S_TIMSTAMP0RO

320x00000000

0xF0

D1_W3_S_TIMSTAMP1

RO

320x00000000

0x100

N0_W_S_CTRL0RW

32

0xA0000000

0x104

N0_W_S_CTRL1

RW

320x00000000

0x108

N0_W_S_STATUS

RO

320x00000000

0x10C

N0_W_S_TIMSTAMP0RO

320x00000000

0x110

N0_W_S_TIMSTAMP1

RO

320x00000000

0x120

N1_W_S_CTRL0RW

32

0xA0000000

0x124

N1_W_S_CTRL1

RW

320x00000000

0x128

N1_W_S_STATUS

RO

320x00000000

0x12C

N1_W_S_TIMSTAMP0RO

320x00000000

0x130

N1_W_S_TIMSTAMP1

RO

320x00000000

0x140

N2_W_S_CTRL0RW

32

0xA0000000

0x144

N2_W_S_CTRL1

RW

320x00000000

0x148

N2_W_S_STATUS

RO

320x00000000

0x14C

N2_W_S_TIMSTAMP0RO

320x00000000

0x150

N2_W_S_TIMSTAMP1

RO

320x00000000

0x160

N3_W_S_CTRL0RW

32

0xA0000000

0x164

N3_W_S_CTRL1

RW

320x00000000

0x168

N3_W_S_STATUS

RO

320x00000000

0x16C

N3_W_S_TIMSTAMP0RO

320x00000000

0x170

N3_W_S_TIMSTAMP1

RO

320x00000000

0x180

N4_W_S_CTRL0RW

32

0xA0000000

0x184

N4_W_S_CTRL1

RW

320x00000000－567/1293－

CXD5602 User Manual

0x188

N4_W_S_STATUS

RO

320x00000000

0x18C

N4_W_S_TIMSTAMP0RO

320x00000000

0x190

N4_W_S_TIMSTAMP1

RO

320x00000000

0x1A0

N5_W_S_CTRL0RW

32

0xA0000000

0x1A4

N5_W_S_CTRL1

RW

320x00000000

0x1A8

N5_W_S_STATUS

RO

320x00000000

0x1AC

N5_W_S_TIMSTAMP0RO

320x00000000

0x1B0

N5_W_S_TIMSTAMP1

RO

320x00000000

0x1C0

N6_W_S_CTRL0RW

32

0xA0000000

0x1C4

N6_W_S_CTRL1

RW

320x00000000

0x1C8

N6_W_S_STATUS

RO

320x00000000

0x1CC

N6_W_S_TIMSTAMP0RO

320x00000000

0x1D0

N6_W_S_TIMSTAMP1

RO

320x00000000

0x1E0

N7_W_S_CTRL0RW

32

0xA0000000

0x1E4

N7_W_S_CTRL1

RW

320x00000000

0x1E8

N7_W_S_STATUS

RO

320x00000000

0x1EC

N7_W_S_TIMSTAMP0RO

320x00000000

0x1F0

N7_W_S_TIMSTAMP1

RO

320x00000000

0x200

V0_W_C_CTRL0RW

32

0xA0000000

0x204

V0_W_C_CTRL1

RW

320x00000000

0x208

V0_W_C_STATUS

RO

320x00000000

0x20C

V0_W_C_TIMSTAMP0RO

320x00000000

0x210

V0_W_C_TIMSTAMP1

RO

320x00000000

0x214

V0_W_C_TIMSTAMP_SET0

RW

320x00000000

0x218

V0_W_C_TIMSTAMP_SET1

RW

320x00000000

0x220

V1_W_C_CTRL0RW

32

0xA0000000

0x224

V1_W_C_CTRL1

RW

320x00000000

0x228

V1_W_C_STATUS

RO

320x00000000

0x22C

V1_W_C_TIMSTAMP0RO

320x00000000

0x230

V1_W_C_TIMSTAMP1

RO

320x00000000

0x234

V1_W_C_TIMSTAMP_SET0

RW

320x00000000

0x238

V1_W_C_TIMSTAMP_SET1

RW

320x00000000

0x240

V2_W_C_CTRL0RW

32

0xA0000000

0x244

V2_W_C_CTRL1

RW

320x00000000

0x248

V2_W_C_STATUS

RO

320x00000000

0x24C

V2_W_C_TIMSTAMP0RO

320x00000000

0x250

V2_W_C_TIMSTAMP1

RO

320x00000000

0x254

V2_W_C_TIMSTAMP_SET0

RW

320x00000000－568/1293－

CXD5602 User Manual

0x258

V2_W_C_TIMSTAMP_SET1

RW

320x00000000

0x260

V3_W_C_CTRL0RW

32

0xA0000000

0x264

V3_W_C_CTRL1

RW

320x00000000

0x268

V3_W_C_STATUS

RO

320x00000000

0x26C

V3_W_C_TIMSTAMP0RO

320x00000000

0x270

V3_W_C_TIMSTAMP1

RO

320x00000000

0x274

V3_W_C_TIMSTAMP_SET0

RW

320x00000000

0x278

V3_W_C_TIMSTAMP_SET1

RW

320x00000000

0x280

V4_W_C_CTRL0RW

32

0xA0000000

0x284

V4_W_C_CTRL1

RW

320x00000000

0x288

V4_W_C_STATUS

RO

320x00000000

0x28C

V4_W_C_TIMSTAMP0RO

320x00000000

0x290

V4_W_C_TIMSTAMP1

RO

320x00000000

0x294

V4_W_C_TIMSTAMP_SET0

RW

320x00000000

0x298

V4_W_C_TIMSTAMP_SET1

RW

320x00000000

0x2A0

V5_W_C_CTRL0RW

32

0xA0000000

0x2A4

V5_W_C_CTRL1

RW

320x00000000

0x2A8

V5_W_C_STATUS

RO

320x00000000

0x2AC

V5_W_C_TIMSTAMP0RO

320x00000000

0x2B0

V5_W_C_TIMSTAMP1

RO

320x00000000

0x2B4

V5_W_C_TIMSTAMP_SET0

RW

320x00000000

0x2B8

V5_W_C_TIMSTAMP_SET1

RW

320x00000000

0x2C0

V6_W_C_CTRL0RW

32

0xA0000000

0x2C4

V6_W_C_CTRL1

RW

320x00000000

0x2C8

V6_W_C_STATUS

RO

320x00000000

0x2CC

V6_W_C_TIMSTAMP0RO

320x00000000

0x2D0

V6_W_C_TIMSTAMP1

RO

320x00000000

0x2D4

V6_W_C_TIMSTAMP_SET0

RW

320x00000000

0x2D8

V6_W_C_TIMSTAMP_SET1

RW

320x00000000

0x2E0

V7_W_C_CTRL0RW

32

0xA0000000

0x2E4

V7_W_C_CTRL1

RW

320x00000000

0x2E8

V7_W_C_STATUS

RO

320x00000000

0x2EC

V7_W_C_TIMSTAMP0RO

320x00000000

0x2F0

V7_W_C_TIMSTAMP1

RO

320x00000000

0x2F4

V7_W_C_TIMSTAMP_SET0

RW

320x00000000

0x2F8

V7_W_C_TIMSTAMP_SET1

RW

320x00000000

0x300

V8_W_C_CTRL0RW

32

0xA0000000

0x304

V8_W_C_CTRL1

RW

320x00000000－569/1293－

CXD5602 User Manual

0x308

V8_W_C_STATUS

RO

320x00000000

0x30C

V8_W_C_TIMSTAMP0RO

320x00000000

0x310

V8_W_C_TIMSTAMP1

RO

320x00000000

0x314

V8_W_C_TIMSTAMP_SET0

RW

320x00000000

0x318

V8_W_C_TIMSTAMP_SET1

RW

320x00000000

0x320

V9_W_C_CTRL0RW

32

0xA0000000

0x324

V9_W_C_CTRL1

RW

320x00000000

0x328

V9_W_C_STATUS

RO

320x00000000

0x32C

V9_W_C_TIMSTAMP0RO

320x00000000

0x330

V9_W_C_TIMSTAMP1

RO

320x00000000

0x334

V9_W_C_TIMSTAMP_SET0

RW

320x00000000

0x338

V9_W_C_TIMSTAMP_SET1

RW

320x00000000

0x1000D0_R1_C_CTRL0

RW

320x0000FFFF

0x1004

D0_R1_C_CTRL1

RW

320x00000000

0x1008

D0_R1_C_STATUS0RO

320x00000000

0x100C

D0_R1_C_STATUS1

RO

32

0x00000000

0x1010D0_R1_C_TIMSTAMP0RO

320x00000000

0x1014

D0_R1_C_TIMSTAMP1

RO

320x00000000

0x1020D0_R2_C_CTRL0

RW

320x0000FFFF

0x1024

D0_R2_C_CTRL1

RW

320x00000000

0x1028

D0_R2_C_STATUS0RO

320x00000000

0x102C

D0_R2_C_STATUS1

RO

32

0x00000000

0x1030D0_R2_C_TIMSTAMP0RO

320x00000000

0x1034

D0_R2_C_TIMSTAMP1

RO

320x00000000

0x1040

D1_R1_C_CTRL0

RW

320x0000FFFF

0x1044

D1_R1_C_CTRL1

RW

320x00000000

0x1048

D1_R1_C_STATUS0RO

320x00000000

0x104C

D1_R1_C_STATUS1

RO

32

0x00000000

0x1050

D1_R1_C_TIMSTAMP0RO

320x00000000

0x1054

D1_R1_C_TIMSTAMP1

RO

320x00000000

0x1060

D1_R2_C_CTRL0

RW

320x0000FFFF

0x1064

D1_R2_C_CTRL1

RW

320x00000000

0x1068

D1_R2_C_STATUS0RO

320x00000000

0x106C

D1_R2_C_STATUS1

RO

32

0x00000000

0x1070

D1_R2_C_TIMSTAMP0RO

320x00000000

0x1074

D1_R2_C_TIMSTAMP1

RO

320x00000000

0x1080N0_R1_C_CTRL0

RW

320x0000FFFF

0x1084

N0_R1_C_CTRL1

RW

320x00000000－570/1293－

CXD5602 User Manual

0x1088

N0_R1_C_STATUS0RO

320x00000000

0x108C

N0_R1_C_STATUS1

RO

32

0x00000000

0x1090N0_R1_C_TIMSTAMP0RO

320x00000000

0x1094

N0_R1_C_TIMSTAMP1

RO

320x00000000

0x10A0

N1_R1_C_CTRL0

RW

320x0000FFFF

0x10A4

N1_R1_C_CTRL1

RW

320x00000000

0x10A8

N1_R1_C_STATUS0RO

320x00000000

0x10AC

N1_R1_C_STATUS1

RO

32

0x00000000

0x10B0

N1_R1_C_TIMSTAMP0RO

320x00000000

0x10B4

N1_R1_C_TIMSTAMP1

RO

320x00000000

0x10C0

N2_R1_C_CTRL0

RW

320x0000FFFF

0x10C4

N2_R1_C_CTRL1

RW

320x00000000

0x10C8N2_R1_C_STATUS0RO

320x00000000

0x10CCN2_R1_C_STATUS1

RO

32

0x00000000

0x10D0

N2_R1_C_TIMSTAMP0RO

320x00000000

0x10D4

N2_R1_C_TIMSTAMP1

RO

320x00000000

0x10E0

N3_R1_C_CTRL0

RW

320x0000FFFF

0x10E4

N3_R1_C_CTRL1

RW

320x00000000

0x10E8N3_R1_C_STATUS0RO

320x00000000

0x10EC

N3_R1_C_STATUS1

RO

32

0x00000000

0x10F0

N3_R1_C_TIMSTAMP0RO

320x00000000

0x10F4

N3_R1_C_TIMSTAMP1

RO

320x00000000

0x1100

N4_R1_C_CTRL0

RW

320x0000FFFF

0x1104N4_R1_C_CTRL1

RW

320x00000000

0x1108N4_R1_C_STATUS0RO

320x00000000

0x110C

N4_R1_C_STATUS1

RO

32

0x00000000

0x1110

N4_R1_C_TIMSTAMP0RO

320x00000000

0x1114N4_R1_C_TIMSTAMP1

RO

320x00000000

0x1120

N5_R1_C_CTRL0

RW

320x0000FFFF

0x1124

N5_R1_C_CTRL1

RW

320x00000000

0x1128N5_R1_C_STATUS0RO

320x00000000

0x112C

N5_R1_C_STATUS1

RO

32

0x00000000

0x1130

N5_R1_C_TIMSTAMP0RO

320x00000000

0x1134

N5_R1_C_TIMSTAMP1

RO

320x00000000

0x1140

N6_R1_C_CTRL0

RW

320x0000FFFF

0x1144

N6_R1_C_CTRL1

RW

320x00000000

0x1148N6_R1_C_STATUS0RO

320x00000000

0x114C

N6_R1_C_STATUS1

RO

32

0x00000000－571/1293－

CXD5602 User Manual

0x1150

N6_R1_C_TIMSTAMP0RO

320x00000000

0x1154

N6_R1_C_TIMSTAMP1

RO

320x00000000

0x1160

N7_R1_C_CTRL0

RW

320x0000FFFF

0x1164

N7_R1_C_CTRL1

RW

320x00000000

0x1168N7_R1_C_STATUS0RO

320x00000000

0x116C

N7_R1_C_STATUS1

RO

32

0x00000000

0x1170

N7_R1_C_TIMSTAMP0RO

320x00000000

0x1174

N7_R1_C_TIMSTAMP1

RO

320x00000000

0x1180D0_R3_CH_CTRL0

RW

320x0000FFFF

0x1184

D0_R3_CH_CTRL1

RW

320x00000000

0x1188

D0_R3_CH_STATUS0RO

320x00000000

0x118C

D0_R3_CH_STATUS1

RO

32

0x00000000

0x1190D0_R3_CH_TIMSTAMP0RO

320x00000000

0x1194

D0_R3_CH_TIMSTAMP1

RO

320x00000000

0x11A0

D1_R3_CH_CTRL0

RW

320x0000FFFF

0x11A4

D1_R3_CH_CTRL1

RW

320x00000000

0x11A8

D1_R3_CH_STATUS0RO

320x00000000

0x11AC

D1_R3_CH_STATUS1

RO

32

0x00000000

0x11B0

D1_R3_CH_TIMSTAMP0RO

320x00000000

0x11B4

D1_R3_CH_TIMSTAMP1

RO

320x00000000

0x11C0

D0_R0_H_CTRL0

RW

320x0000FFFF

0x11C4

D0_R0_H_CTRL1

RW

320x00000000

0x11C8

D0_R0_H_STATUS0RO

320x00000000

0x11CC

D0_R0_H_STATUS1

RO

32

0x00000000

0x11D0

D0_R0_H_TIMSTAMP0RO

320x00000000

0x11D4

D0_R0_H_TIMSTAMP1

RO

320x00000000

0x11E0

D1_R0_H_CTRL0

RW

320x0000FFFF

0x11E4

D1_R0_H_CTRL1

RW

320x00000000

0x11E8

D1_R0_H_STATUS0RO

320x00000000

0x11EC

D1_R0_H_STATUS1

RO

32

0x00000000

0x11F0

D1_R0_H_TIMSTAMP0RO

320x00000000

0x11F4

D1_R0_H_TIMSTAMP1

RO

320x00000000

0x1200N0_R0_H_CTRL0

RW

320x0000FFFF

0x1204

N0_R0_H_CTRL1

RW

320x00000000

0x1208N0_R0_H_STATUS0RO

320x00000000

0x120C

N0_R0_H_STATUS1

RO

32

0x00000000

0x1210N0_R0_H_TIMSTAMP0RO

320x00000000

0x1214

N0_R0_H_TIMSTAMP1

RO

320x00000000－572/1293－

CXD5602 User Manual

0x1220

N1_R0_H_CTRL0

RW

320x0000FFFF

0x1224

N1_R0_H_CTRL1

RW

320x00000000

0x1228

N1_R0_H_STATUS0RO

320x00000000

0x122C

N1_R0_H_STATUS1

RO

32

0x00000000

0x1230

N1_R0_H_TIMSTAMP0RO

320x00000000

0x1234

N1_R0_H_TIMSTAMP1

RO

320x00000000

0x1240

N2_R0_H_CTRL0

RW

320x0000FFFF

0x1244

N2_R0_H_CTRL1

RW

320x00000000

0x1248N2_R0_H_STATUS0RO

320x00000000

0x124C

N2_R0_H_STATUS1

RO

32

0x00000000

0x1250

N2_R0_H_TIMSTAMP0RO

320x00000000

0x1254

N2_R0_H_TIMSTAMP1

RO

320x00000000

0x1260

N3_R0_H_CTRL0

RW

320x0000FFFF

0x1264

N3_R0_H_CTRL1

RW

320x00000000

0x1268N3_R0_H_STATUS0RO

320x00000000

0x126C

N3_R0_H_STATUS1

RO

32

0x00000000

0x1270

N3_R0_H_TIMSTAMP0RO

320x00000000

0x1274

N3_R0_H_TIMSTAMP1

RO

320x00000000

0x1280

N4_R0_H_CTRL0

RW

320x0000FFFF

0x1284N4_R0_H_CTRL1

RW

320x00000000

0x1288N4_R0_H_STATUS0RO

320x00000000

0x128C

N4_R0_H_STATUS1

RO

32

0x00000000

0x1290

N4_R0_H_TIMSTAMP0RO

320x00000000

0x1294N4_R0_H_TIMSTAMP1

RO

320x00000000

0x12A0

N5_R0_H_CTRL0

RW

320x0000FFFF

0x12A4

N5_R0_H_CTRL1

RW

320x00000000

0x12A8N5_R0_H_STATUS0RO

320x00000000

0x12AC

N5_R0_H_STATUS1

RO

32

0x00000000

0x12B0

N5_R0_H_TIMSTAMP0RO

320x00000000

0x12B4

N5_R0_H_TIMSTAMP1

RO

320x00000000

0x12C0

N6_R0_H_CTRL0

RW

320x0000FFFF

0x12C4

N6_R0_H_CTRL1

RW

320x00000000

0x12C8N6_R0_H_STATUS0RO

320x00000000

0x12CC

N6_R0_H_STATUS1

RO

32

0x00000000

0x12D0

N6_R0_H_TIMSTAMP0RO

320x00000000

0x12D4

N6_R0_H_TIMSTAMP1

RO

320x00000000

0x12E0

N7_R0_H_CTRL0

RW

320x0000FFFF

0x12E4

N7_R0_H_CTRL1

RW

320x00000000－573/1293－

CXD5602 User Manual

0x12E8N7_R0_H_STATUS0RO

320x00000000

0x12EC

N7_R0_H_STATUS1

RO

32

0x00000000

0x12F0

N7_R0_H_TIMSTAMP0RO

320x00000000

0x12F4

N7_R0_H_TIMSTAMP1

RO

320x00000000

0x1300V0_R_H_CTRL0

RW

320x0000FFFF

0x1304

V0_R_H_CTRL1

RW

320x00000000

0x1308V0_R_H_STATUS0RO

320x00000000

0x130C

V0_R_H_STATUS1

RO

32

0x00000000

0x1310V0_R_H_TIMSTAMP0RO

320x00000000

0x1314

V0_R_H_TIMSTAMP1

RO

320x00000000

0x1320

V1_R_H_CTRL0

RW

320x0000FFFF

0x1324

V1_R_H_CTRL1

RW

320x00000000

0x1328

V1_R_H_STATUS0RO

320x00000000

0x132C

V1_R_H_STATUS1

RO

32

0x00000000

0x1330

V1_R_H_TIMSTAMP0RO

320x00000000

0x1334

V1_R_H_TIMSTAMP1

RO

320x00000000

0x1340V2_R_H_CTRL0

RW

320x0000FFFF

0x1344

V2_R_H_CTRL1

RW

320x00000000

0x1348V2_R_H_STATUS0RO

320x00000000

0x134C

V2_R_H_STATUS1

RO

32

0x00000000

0x1350V2_R_H_TIMSTAMP0RO

320x00000000

0x1354

V2_R_H_TIMSTAMP1

RO

320x00000000

0x1360V3_R_H_CTRL0

RW

320x0000FFFF

0x1364

V3_R_H_CTRL1

RW

320x00000000

0x1368V3_R_H_STATUS0RO

320x00000000

0x136C

V3_R_H_STATUS1

RO

32

0x00000000

0x1370V3_R_H_TIMSTAMP0RO

320x00000000

0x1374

V3_R_H_TIMSTAMP1

RO

320x00000000

0x1380

V4_R_H_CTRL0

RW

320x0000FFFF

0x1384V4_R_H_CTRL1

RW

320x00000000

0x1388V4_R_H_STATUS0RO

320x00000000

0x138C

V4_R_H_STATUS1

RO

32

0x00000000

0x1390

V4_R_H_TIMSTAMP0RO

320x00000000

0x1394V4_R_H_TIMSTAMP1

RO

320x00000000

0x13A0V5_R_H_CTRL0

RW

320x0000FFFF

0x13A4

V5_R_H_CTRL1

RW

320x00000000

0x13A8V5_R_H_STATUS0RO

320x00000000

0x13AC

V5_R_H_STATUS1

RO

32

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CXD5602 User Manual

0x13B0V5_R_H_TIMSTAMP0RO

320x00000000

0x13B4

V5_R_H_TIMSTAMP1

RO

320x00000000

0x13C0V6_R_H_CTRL0

RW

320x0000FFFF

0x13C4

V6_R_H_CTRL1

RW

320x00000000

0x13C8V6_R_H_STATUS0RO

320x00000000

0x13CC

V6_R_H_STATUS1

RO

32

0x00000000

0x13D0V6_R_H_TIMSTAMP0RO

320x00000000

0x13D4

V6_R_H_TIMSTAMP1

RO

320x00000000

0x13E0

V7_R_H_CTRL0

RW

320x0000FFFF

0x13E4

V7_R_H_CTRL1

RW

320x00000000

0x13E8V7_R_H_STATUS0RO

320x00000000

0x13EC

V7_R_H_STATUS1

RO

32

0x00000000

0x13F0

V7_R_H_TIMSTAMP0RO

320x00000000

0x13F4

V7_R_H_TIMSTAMP1

RO

320x00000000

0x1400

V8_R_H_CTRL0

RW

320x0000FFFF

0x1404

V8_R_H_CTRL1

RW

320x00000000

0x1408V8_R_H_STATUS0RO

320x00000000

0x140C

V8_R_H_STATUS1

RO

32

0x00000000

0x1410

V8_R_H_TIMSTAMP0RO

320x00000000

0x1414

V8_R_H_TIMSTAMP1

RO

320x00000000

0x1420V9_R_H_CTRL0

RW

320x0000FFFF

0x1424

V9_R_H_CTRL1

RW

320x00000000

0x1428V9_R_H_STATUS0RO

320x00000000

0x142C

V9_R_H_STATUS1

RO

32

0x00000000

0x1430V9_R_H_TIMSTAMP0RO

320x00000000

0x1434

V9_R_H_TIMSTAMP1

RO

320x00000000

0x1C00

DECI_PARTITION_SEL

RW

32

0x00000000－575/1293－

CXD5602 User Manual

3.9.12.10.1{0x0} D0_W0_S_CTRL0 Details
Table SCU (Sensor Control Unit)-374
Register Type: RW (read/write)

Local Address: 0x0

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits
31..16

15..0

Name
FIFO_START_OFSTFIFO_PARTITI
ON_SIZEFIFO_PARTITION_SIZE

TypeReset Value Description
Start address offset

RW

0xA000Means the start address offset of the RAM for the FIFO
(by Byte unit)
Partition size -1

RW

0x0000

Sets partition size minus 1.
(by Sample unit)－576/1293－

CXD5602 User Manual

3.9.12.10.2{0x4} D0_W0_S_CTRL1 Details
Table SCU (Sensor Control Unit)-375
Register Type: RW (read/write)

Local Address: 0x4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description

31..17 Reserved

RO

0x0000 Reserved

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

ENABLE_ADC_
INTERVAL

Reset of the FIFO
Clears the writing pointer to “0”

When
11..8

ADC_INTERVA
L

RW

0x0

ENABLE_ADC_INTERVALis

ADC_INTERVAL is used as a sampling interval instead of
PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

7..5

ReservedRO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

“1”,

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－577/1293－

CXD5602 User Manual

3.9.12.10.3{0x8} D0_W0_S_STATUS Details
Table SCU (Sensor Control Unit)-376
Register Type: RO (read only)

Local Address: 0x8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－578/1293－

CXD5602 User Manual

3.9.12.10.4{0xC} D0_W0_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-377
Register Type: RO (read only)

Local Address: 0xC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LATEST_TIMESTAMP_MSB
Bits
31..0

Name

Type

LATEST_TIMESTAMP_
MSB

3.9.12.10.5

Reset Value

Description
Latest time stamp (integer part of second)RO

0x00000000

Time stamp which supports the newest data in
the FIFO by second unit

{0x10} D0_W0_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-378
Register Type: RO (read only)

Local Address: 0x10

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－579/1293－

CXD5602 User Manual

3.9.12.10.6{0x20} D0_W1_S_CTRL0 Details
Table SCU (Sensor Control Unit)-379
Register Type: RW (read/write)

Local Address: 0x20

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for the
FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－580/1293－

CXD5602 User Manual

3.9.12.10.7{0x24} D0_W1_S_CTRL1 Details
Table SCU (Sensor Control Unit)-380
Register Type: RW (read/write)

Local Address: 0x24

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..17

Reserved

RO

0x0000Reserved

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF_F
ULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_SIZ
E

Number of Byte per Sample – 1
RW

0x0

Sets data length per Sample in the FIFO by
Byte unit－581/1293－

CXD5602 User Manual

3.9.12.10.8{0x28} D0_W1_S_STATUS Details
Table SCU (Sensor Control Unit)-381
Register Type: RO (read only)

Local Address: 0x28

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset Value Description
Writing pointer address of the FIFO

RO

0x0000The start address where the next data is written by Byte
unit

RO

0x000

Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－582/1293－

CXD5602 User Manual

3.9.12.10.9{0x2C} D0_W1_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-382
Register Type: RO (read only)

Local Address: 0x2C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.10{0x30} D0_W1_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-383
Register Type: RO (read only)

Local Address: 0x30

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－583/1293－

CXD5602 User Manual

3.9.12.10.11{0x40} D0_W2_S_CTRL0 Details
Table SCU (Sensor Control Unit)-384
Register Type: RW (read/write)

Local Address: 0x40

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－584/1293－

CXD5602 User Manual

3.9.12.10.12{0x44} D0_W2_S_CTRL1 Details
Table SCU (Sensor Control Unit)-385
Register Type: RW (read/write)

Local Address: 0x44

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..17

Reserved

RO

0x0000Reserved

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF_F
ULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_SIZ
E

Number of Byte per Sample – 1
RW

0x0

Sets data length per Sample in the FIFO by
Byte unit－585/1293－

CXD5602 User Manual

3.9.12.10.13{0x48} D0_W2_S_STATUS Details
Table SCU (Sensor Control Unit)-386
Register Type: RO (read only)

Local Address: 0x48

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits

31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

Description
Writing pointer address of the FIFO

RO

0x0000The start address where the next data is written
by Byte unit

RO

0x000

Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－586/1293－

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.14{0x4C} D0_W2_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-387
Register Type: RO (read only)

Local Address: 0x4C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.15{0x50} D0_W2_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-388
Register Type: RO (read only)

Local Address: 0x50

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point
The start address where the next data is written
by Byte unit

－587/1293－

CXD5602 User Manual

3.9.12.10.16{0x60} D0_W3_S_CTRL0 Details
Table SCU (Sensor Control Unit)-389
Register Type: RW (read/write)

Local Address: 0x60

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－588/1293－

CXD5602 User Manual

3.9.12.10.17{0x64} D0_W3_S_CTRL1 Details
Table SCU (Sensor Control Unit)-390
Register Type: RW (read/write)

Local Address: 0x64

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..17

Reserved

RO

0x0000Reserved

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF_F
ULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_SIZ
E

Number of Byte per Sample – 1
RW

0x0

Sets data length per Sample in the FIFO by
Byte unit－589/1293－

CXD5602 User Manual

3.9.12.10.18{0x68} D0_W3_S_STATUS Details
Table SCU (Sensor Control Unit)-391
Register Type: RO (read only)

Local Address: 0x68

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－590/1293－

CXD5602 User Manual

3.9.12.10.19{0x6C} D0_W3_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-392
Register Type: RO (read only)

Local Address: 0x6C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.20{0x70} D0_W3_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-393
Register Type: RO (read only)

Local Address: 0x70

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－591/1293－

CXD5602 User Manual

3.9.12.10.21{0x80} D1_W0_S_CTRL0 Details
Table SCU (Sensor Control Unit)-394
Register Type: RW (read/write)

Local Address: 0x80

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－592/1293－

CXD5602 User Manual

3.9.12.10.22{0x84} D1_W0_S_CTRL1 Details
Table SCU (Sensor Control Unit)-395
Register Type: RW (read/write)

Local Address: 0x84

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－593/1293－

CXD5602 User Manual

3.9.12.10.23{0x88} D1_W0_S_STATUS Details
Table SCU (Sensor Control Unit)-396
Register Type: RO (read only)

Local Address: 0x88

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－594/1293－

CXD5602 User Manual

3.9.12.10.24{0x8C} D1_W0_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-397
Register Type: RO (read only)

Local Address: 0x8C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.25{0x90} D1_W0_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-398
Register Type: RO (read only)

Local Address: 0x90

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－595/1293－

CXD5602 User Manual

3.9.12.10.26{0xA0} D1_W1_S_CTRL0 Details
Table SCU (Sensor Control Unit)-399
Register Type: RW (read/write)

Local Address: 0xA0Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－596/1293－

CXD5602 User Manual

3.9.12.10.27{0xA4} D1_W1_S_CTRL1 Details
Table SCU (Sensor Control Unit)-400
Register Type: RW (read/write)

Local Address: 0xA4

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..17

Reserved

RO

0x0000Reserved

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF_F
ULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_SIZ
E

Number of Byte per Sample – 1
RW

0x0

Sets data length per Sample in the FIFO by
Byte unit－597/1293－

CXD5602 User Manual

3.9.12.10.28{0xA8} D1_W1_S_STATUS Details
Table SCU (Sensor Control Unit)-401
Register Type: RO (read only)

Local Address: 0xA8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－598/1293－

CXD5602 User Manual

3.9.12.10.29{0xAC} D1_W1_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-402
Register Type: RO (read only)

Local Address: 0xAC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.30{0xB0} D1_W1_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-403
Register Type: RO (read only)

Local Address: 0xB0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－599/1293－

CXD5602 User Manual

3.9.12.10.31{0xC0} D1_W2_S_CTRL0 Details
Table SCU (Sensor Control Unit)-404
Register Type: RW (read/write)

Local Address: 0xC0Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－600/1293－

CXD5602 User Manual

3.9.12.10.32{0xC4} D1_W2_S_CTRL1 Details
Table SCU (Sensor Control Unit)-405
Register Type: RW (read/write)

Local Address: 0xC4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－601/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.33{0xC8} D1_W2_S_STATUS Details
Table SCU (Sensor Control Unit)-406
Register Type: RO (read only)

Local Address: 0xC8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－602/1293－

CXD5602 User Manual

3.9.12.10.34{0xCC} D1_W2_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-407
Register Type: RO (read only)

Local Address: 0xCC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.35{0xD0} D1_W2_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-408
Register Type: RO (read only)

Local Address: 0xD0Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－603/1293－

CXD5602 User Manual

3.9.12.10.36{0xE0} D1_W3_S_CTRL0 Details
Table SCU (Sensor Control Unit)-409
Register Type: RW (read/write)

Local Address: 0xE0

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－604/1293－

CXD5602 User Manual

3.9.12.10.37{0xE4} D1_W3_S_CTRL1 Details
Table SCU (Sensor Control Unit)-410
Register Type: RW (read/write)

Local Address: 0xE4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－605/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.38{0xE8} D1_W3_S_STATUS Details
Table SCU (Sensor Control Unit)-411
Register Type: RO (read only)

Local Address: 0xE8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－606/1293－

CXD5602 User Manual

3.9.12.10.39{0xEC} D1_W3_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-412
Register Type: RO (read only)

Local Address: 0xEC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.40{0xF0} D1_W3_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-413
Register Type: RO (read only)

Local Address: 0xF0Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－607/1293－

CXD5602 User Manual

3.9.12.10.41{0x100} N0_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-414
Register Type: RW (read/write)

Local Address: 0x100

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－608/1293－

CXD5602 User Manual

3.9.12.10.42{0x104} N0_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-415
Register Type: RW (read/write)

Local Address: 0x104

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－609/1293－

CXD5602 User Manual

3.9.12.10.43{0x108} N0_W_S_STATUS Details
Table SCU (Sensor Control Unit)-416
Register Type: RO (read only)

Local Address: 0x108

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－610/1293－

CXD5602 User Manual

3.9.12.10.44{0x10C} N0_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-417
Register Type: RO (read only)

Local Address: 0x10C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.45{0x110} N0_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-418
Register Type: RO (read only)

Local Address: 0x110

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－611/1293－

CXD5602 User Manual

3.9.12.10.46{0x120} N1_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-419
Register Type: RW (read/write)

Local Address: 0x120

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－612/1293－

CXD5602 User Manual

3.9.12.10.47{0x124} N1_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-420
Register Type: RW (read/write)

Local Address: 0x124

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－613/1293－

CXD5602 User Manual

3.9.12.10.48{0x128} N1_W_S_STATUS Details
Table SCU (Sensor Control Unit)-421
Register Type: RO (read only)

Local Address: 0x128

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits

Name

Reserved

Type Reset ValueFIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Writing pointer address of the FIFO

31..16

FIFO_WRITE_PTR RO

0x0000The start address where the next data is written
by Byte unit

15..4

Reserved

RO

0x000

Reserved
Write phase of the data in the FIFO
The data position in a sample data stored in the

3..0

FIFO_WRITE_PHAS
E

RO

0x0

FIFO
(by Byte unit)“0” indicates that it is delimited of the sample
data.

－614/1293－

CXD5602 User Manual

3.9.12.10.49{0x12C} N1_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-422
Register Type: RO (read only)

Local Address: 0x12C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.50{0x130} N1_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-423
Register Type: RO (read only)

Local Address: 0x130

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－615/1293－

CXD5602 User Manual

3.9.12.10.51{0x140} N2_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-424
Register Type: RW (read/write)

Local Address: 0x140

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－616/1293－

CXD5602 User Manual

3.9.12.10.52{0x144} N2_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-425
Register Type: RW (read/write)

Local Address: 0x144

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－617/1293－

CXD5602 User Manual

3.9.12.10.53{0x148} N2_W_S_STATUS Details
Table SCU (Sensor Control Unit)-426
Register Type: RO (read only)

Local Address: 0x148

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－618/1293－

CXD5602 User Manual

3.9.12.10.54{0x14C} N2_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-427
Register Type: RO (read only)

Local Address: 0x14C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.55{0x150} N2_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-428
Register Type: RO (read only)

Local Address: 0x150

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－619/1293－

CXD5602 User Manual

3.9.12.10.56{0x160} N3_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-429
Register Type: RW (read/write)

Local Address: 0x160

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－620/1293－

CXD5602 User Manual

3.9.12.10.57{0x164} N3_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-430
Register Type: RW (read/write)

Local Address: 0x164

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－621/1293－

CXD5602 User Manual

3.9.12.10.58{0x168} N3_W_S_STATUS Details
Table SCU (Sensor Control Unit)-431
Register Type: RO (read only)

Local Address: 0x168

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－622/1293－

CXD5602 User Manual

3.9.12.10.59{0x16C} N3_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-432
Register Type: RO (read only)

Local Address: 0x16C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.60{0x170} N3_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-433
Register Type: RO (read only)

Local Address: 0x170

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－623/1293－

CXD5602 User Manual

3.9.12.10.61{0x180} N4_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-434
Register Type: RW (read/write)

Local Address: 0x180

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－624/1293－

CXD5602 User Manual

3.9.12.10.62{0x184} N4_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-435
Register Type: RW (read/write)

Local Address: 0x184

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－625/1293－

CXD5602 User Manual

3.9.12.10.63{0x188} N4_W_S_STATUS Details
Table SCU (Sensor Control Unit)-436
Register Type: RO (read only)

Local Address: 0x188

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－626/1293－

CXD5602 User Manual

3.9.12.10.64{0x18C} N4_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-437
Register Type: RO (read only)

Local Address: 0x18C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.65{0x190} N4_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-438
Register Type: RO (read only)

Local Address: 0x190

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－627/1293－

CXD5602 User Manual

3.9.12.10.66{0x1A0} N5_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-439
Register Type: RW (read/write)

Local Address: 0x1A0

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－628/1293－

CXD5602 User Manual

3.9.12.10.67{0x1A4} N5_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-440
Register Type: RW (read/write)

Local Address: 0x1A4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－629/1293－

CXD5602 User Manual

3.9.12.10.68{0x1A8} N5_W_S_STATUS Details
Table SCU (Sensor Control Unit)-441
Register Type: RO (read only)

Local Address: 0x1A8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－630/1293－

CXD5602 User Manual

3.9.12.10.69{0x1AC} N5_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-442
Register Type: RO (read only)

Local Address: 0x1AC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.70{0x1B0} N5_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-443
Register Type: RO (read only)

Local Address: 0x1B0Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－631/1293－

CXD5602 User Manual

3.9.12.10.71{0x1C0} N6_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-444
Register Type: RW (read/write)

Local Address: 0x1C0

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－632/1293－

CXD5602 User Manual

3.9.12.10.72{0x1C4} N6_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-445
Register Type: RW (read/write)

Local Address: 0x1C4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－633/1293－

CXD5602 User Manual

3.9.12.10.73{0x1C8} N6_W_S_STATUS Details
Table SCU (Sensor Control Unit)-446
Register Type: RO (read only)

Local Address: 0x1C8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset Value Description
Writing pointer address of the FIFO

RO

0x0000The start address where the next data is written by Byte
unit

RO

0x000

Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－634/1293－

CXD5602 User Manual

3.9.12.10.74{0x1CC} N6_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-447
Register Type: RO (read only)

Local Address: 0x1CC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.75{0x1D0} N6_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-448
Register Type: RO (read only)

Local Address: 0x1D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－635/1293－

CXD5602 User Manual

3.9.12.10.76{0x1E0} N7_W_S_CTRL0 Details
Table SCU (Sensor Control Unit)-449
Register Type: RW (read/write)

Local Address: 0x1E0

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－636/1293－

CXD5602 User Manual

3.9.12.10.77{0x1E4} N7_W_S_CTRL1 Details
Table SCU (Sensor Control Unit)-450
Register Type: RW (read/write)

Local Address: 0x1E4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

Description

31..17 Reserved

RO

0x0000

16

WO

0x0

RO

0x0

Reserved

RW

0x0

Uses ADC_INTERVAL instead of PRE_DIVIDERFIFO_RESET

15..13 Reserved
12

11..8
7..5

ENABLE_ADC_
INTERVAL
ADC_INTERVA
L
Reserved

FIFO_SAMPLE_SIZEOVERWRITE_IF_FULL

Reserved

ADC_INTERVAL

Reserved

FIFO_RESET

Reserved

ENABLE_ADC_INTERVAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Reset of the FIFO
Clears the writing pointer to “0”ADC_INTERVAL is used as a sampling interval instead of
RW

0x0

PRE_DIVIDER.
Note: ADC_INTERVAL must be bigger than 1.

RO

0x0

Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－637/1293－

CXD5602 User Manual

3.9.12.10.78{0x1E8} N7_W_S_STATUS Details
Table SCU (Sensor Control Unit)-451
Register Type: RO (read only)

Local Address: 0x1E8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－638/1293－

CXD5602 User Manual

3.9.12.10.79{0x1EC} N7_W_S_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-452
Register Type: RO (read only)

Local Address: 0x1EC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.80{0x1F0} N7_W_S_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-453
Register Type: RO (read only)

Local Address: 0x1F0Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－639/1293－

CXD5602 User Manual

3.9.12.10.81{0x200} V0_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-454
Register Type: RW (read/write)

Local Address: 0x200

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－640/1293－

CXD5602 User Manual

3.9.12.10.82{0x204} V0_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-455
Register Type: RW (read/write)

Local Address: 0x204

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－641/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.83{0x208} V0_W_C_STATUS Details
Table SCU (Sensor Control Unit)-456
Register Type: RO (read only)

Local Address: 0x208

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－642/1293－

CXD5602 User Manual

3.9.12.10.84{0x20C} V0_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-457
Register Type: RO (read only)

Local Address: 0x20C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.85{0x210} V0_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-458
Register Type: RO (read only)

Local Address: 0x210

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－643/1293－

CXD5602 User Manual

3.9.12.10.86{0x214} V0_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-459
Register Type: RW (read/write)

Local Address: 0x214

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.87

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x218} V0_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-460
Register Type: RW (read/write)

Local Address: 0x218

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_INT
ERVAL

TIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_TIMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－644/1293－

CXD5602 User Manual

3.9.12.10.88{0x220} V1_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-461
Register Type: RW (read/write)

Local Address: 0x220

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－645/1293－

CXD5602 User Manual

3.9.12.10.89{0x224} V1_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-462
Register Type: RW (read/write)

Local Address: 0x224

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－646/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.90{0x228} V1_W_C_STATUS Details
Table SCU (Sensor Control Unit)-463
Register Type: RO (read only)

Local Address: 0x228

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－647/1293－

CXD5602 User Manual

3.9.12.10.91{0x22C} V1_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-464
Register Type: RO (read only)

Local Address: 0x22C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.92{0x230} V1_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-465
Register Type: RO (read only)

Local Address: 0x230

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－648/1293－

CXD5602 User Manual

3.9.12.10.93{0x234} V1_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-466
Register Type: RW (read/write)

Local Address: 0x234

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.94

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x238} V1_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-467
Register Type: RW (read/write)

Local Address: 0x238

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_INT
ERVAL

TIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_TIMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－649/1293－

CXD5602 User Manual

3.9.12.10.95{0x240} V2_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-468
Register Type: RW (read/write)

Local Address: 0x240

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

31..16

15..0

Name
FIFO_START_OFSTFIFO_PARTITI
ON_SIZEFIFO_PARTITION_SIZE

Type

Reset
Value

Description
Start address offset

RW

0xA000 Means the start address offset of the RAM for the FIFO
(by Byte unit)
Partition size -1

RW

0x0000

Sets partition size minus 1.
(by Sample unit)－650/1293－

CXD5602 User Manual

3.9.12.10.96{0x244} V2_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-469
Register Type: RW (read/write)

Local Address: 0x244

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－651/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.97{0x248} V2_W_C_STATUS Details
Table SCU (Sensor Control Unit)-470
Register Type: RO (read only)

Local Address: 0x248

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－652/1293－

CXD5602 User Manual

3.9.12.10.98{0x24C} V2_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-471
Register Type: RO (read only)

Local Address: 0x24C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.99{0x250} V2_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-472
Register Type: RO (read only)

Local Address: 0x250

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－653/1293－

CXD5602 User Manual

3.9.12.10.100{0x254} V2_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-473
Register Type: RW (read/write)

Local Address: 0x254

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.101

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x258} V2_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-474
Register Type: RW (read/write)

Local Address: 0x258

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_IN
TERVALTIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_T
IMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－654/1293－

CXD5602 User Manual

3.9.12.10.102{0x260} V3_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-475
Register Type: RW (read/write)

Local Address: 0x260

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－655/1293－

CXD5602 User Manual

3.9.12.10.103{0x264} V3_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-476
Register Type: RW (read/write)

Local Address: 0x264

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－656/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.104{0x268} V3_W_C_STATUS Details
Table SCU (Sensor Control Unit)-477
Register Type: RO (read only)

Local Address: 0x268

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－657/1293－

CXD5602 User Manual

3.9.12.10.105{0x26C} V3_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-478
Register Type: RO (read only)

Local Address: 0x26C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.106{0x270} V3_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-479
Register Type: RO (read only)

Local Address: 0x270

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－658/1293－

CXD5602 User Manual

3.9.12.10.107{0x274} V3_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-480
Register Type: RW (read/write)

Local Address: 0x274

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.108

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x278} V3_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-481
Register Type: RW (read/write)

Local Address: 0x278

Reset Value: 0x00000000

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME_STAMP_INTERVAL

Bits

Name

Type

31

Reserved

RO

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_INT
ERVAL

TIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_TIMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－659/1293－

CXD5602 User Manual

3.9.12.10.109{0x280} V4_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-482
Register Type: RW (read/write)

Local Address: 0x280

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

31..16

15..0

Name
FIFO_START_OFSTFIFO_PARTITI
ON_SIZEFIFO_PARTITION_SIZE

Type

Reset
Value

Description
Start address offset

RW

0xA000 Means the start address offset of the RAM for the FIFO
(by Byte unit)
Partition size -1

RW

0x0000

Sets partition size minus 1.
(by Sample unit)－660/1293－

CXD5602 User Manual

3.9.12.10.110{0x284} V4_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-483
Register Type: RW (read/write)

Local Address: 0x284

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－661/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.111{0x288} V4_W_C_STATUS Details
Table SCU (Sensor Control Unit)-484
Register Type: RO (read only)

Local Address: 0x288

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－662/1293－

CXD5602 User Manual

3.9.12.10.112{0x28C} V4_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-485
Register Type: RO (read only)

Local Address: 0x28C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.113{0x290} V4_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-486
Register Type: RO (read only)

Local Address: 0x290

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－663/1293－

CXD5602 User Manual

3.9.12.10.114{0x294} V4_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-487
Register Type: RW (read/write)

Local Address: 0x294

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.115

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x298} V4_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-488
Register Type: RW (read/write)

Local Address: 0x298

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_IN
TERVALTIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_T
IMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－664/1293－

CXD5602 User Manual

3.9.12.10.116{0x2A0} V5_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-489
Register Type: RW (read/write)

Local Address: 0x2A0

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO_START_OFST
Bits

Name

FIFO_PARTITION_SIZE
Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－665/1293－

CXD5602 User Manual

3.9.12.10.117{0x2A4} V5_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-490
Register Type: RW (read/write)

Local Address: 0x2A4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－666/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.118{0x2A8} V5_W_C_STATUS Details
Table SCU (Sensor Control Unit)-491
Register Type: RO (read only)

Local Address: 0x2A8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－667/1293－

CXD5602 User Manual

3.9.12.10.119{0x2AC} V5_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-492
Register Type: RO (read only)

Local Address: 0x2AC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.120{0x2B0} V5_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-493
Register Type: RO (read only)

Local Address: 0x2B0Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－668/1293－

CXD5602 User Manual

3.9.12.10.121{0x2B4} V5_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-494
Register Type: RW (read/write)

Local Address: 0x2B4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.122

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x2B8} V5_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-495
Register Type: RW (read/write)

Local Address: 0x2B8

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_IN
TERVALTIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_T
IMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－669/1293－

CXD5602 User Manual

3.9.12.10.123{0x2C0} V6_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-496
Register Type: RW (read/write)

Local Address: 0x2C0

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－670/1293－

CXD5602 User Manual

3.9.12.10.124{0x2C4} V6_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-497
Register Type: RW (read/write)

Local Address: 0x2C4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－671/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.125{0x2C8} V6_W_C_STATUS Details
Table SCU (Sensor Control Unit)-498
Register Type: RO (read only)

Local Address: 0x2C8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－672/1293－

CXD5602 User Manual

3.9.12.10.126{0x2CC} V6_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-499
Register Type: RO (read only)

Local Address: 0x2CC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.127{0x2D0} V6_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-500
Register Type: RO (read only)

Local Address: 0x2D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－673/1293－

CXD5602 User Manual

3.9.12.10.128{0x2D4} V6_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-501
Register Type: RW (read/write)

Local Address: 0x2D4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.129

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x2D8} V6_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-502
Register Type: RW (read/write)

Local Address: 0x2D8

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_INT
ERVAL

TIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_TIMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－674/1293－

CXD5602 User Manual

3.9.12.10.130{0x2E0} V7_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-503
Register Type: RW (read/write)

Local Address: 0x2E0Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－675/1293－

CXD5602 User Manual

3.9.12.10.131{0x2E4} V7_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-504
Register Type: RW (read/write)

Local Address: 0x2E4

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－676/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.132{0x2E8} V7_W_C_STATUS Details
Table SCU (Sensor Control Unit)-505
Register Type: RO (read only)

Local Address: 0x2E8

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－677/1293－

CXD5602 User Manual

3.9.12.10.133{0x2EC} V7_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-506
Register Type: RO (read only)

Local Address: 0x2EC

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.134{0x2F0} V7_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-507
Register Type: RO (read only)

Local Address: 0x2F0Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－678/1293－

CXD5602 User Manual

3.9.12.10.135{0x2F4} V7_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-508
Register Type: RW (read/write)

Local Address: 0x2F4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.136

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x2F8} V7_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-509
Register Type: RW (read/write)

Local Address: 0x2F8

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_IN
TERVALTIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_T
IMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－679/1293－

CXD5602 User Manual

3.9.12.10.137{0x300} V8_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-510
Register Type: RW (read/write)

Local Address: 0x300

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－680/1293－

CXD5602 User Manual

3.9.12.10.138{0x304} V8_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-511
Register Type: RW (read/write)

Local Address: 0x304

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_
IF_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE
_SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－681/1293－

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CXD5602 User Manual

3.9.12.10.139{0x308} V8_W_C_STATUS Details
Table SCU (Sensor Control Unit)-512
Register Type: RO (read only)

Local Address: 0x308

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－682/1293－

CXD5602 User Manual

3.9.12.10.140{0x30C} V8_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-513
Register Type: RO (read only)

Local Address: 0x30C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.141{0x310} V8_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-514
Register Type: RO (read only)

Local Address: 0x310

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－683/1293－

CXD5602 User Manual

3.9.12.10.142{0x314} V8_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-515
Register Type: RW (read/write)

Local Address: 0x314

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.143

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x318} V8_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-516
Register Type: RW (read/write)

Local Address: 0x318

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_IN
TERVALTIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_T
IMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－684/1293－

CXD5602 User Manual

3.9.12.10.144{0x320} V9_W_C_CTRL0 Details
Table SCU (Sensor Control Unit)-517
Register Type: RW (read/write)

Local Address: 0x320

Reset Value: 0xA0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIFO_START_OFST

Bits

Name

FIFO_PARTITION_SIZE

Type Reset Value

Description
Start address offset

31..16

FIFO_START_OFST RW

0xA000Means the start address offset of the RAM for
the FIFO(by Byte unit)

15..0

FIFO_PARTITION_
SIZEPartition size -1
RW

0x0000

Sets partition size minus 1.
(by Sample unit)－685/1293－

CXD5602 User Manual

3.9.12.10.145{0x324} V9_W_C_CTRL1 Details
Table SCU (Sensor Control Unit)-518
Register Type: RW (read/write)

Local Address: 0x324

Reset Value: 0x00000000

Bits

Name

Type

Reset
Value

31..17 Reserved

RO

0x0000

16

FIFO_RESET

WO

0x0

15..5

Reserved

RO

0x000

Reserved

FIFO_SAMPLE_SIZEFIFO_RESET

Reserved

OVERWRITE_IF_FULL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Reset of the FIFO
Clears the writing pointer to “0”Reserved
OVERWRITE_IF_FULL overview

4

OVERWRITE_IF
_FULL

RW

0x0

Sets whether to overwrite or not at FIFO Full
0: does not overwrite
1: overwrites

3..0

FIFO_SAMPLE_
SIZE

RW

0x0

Number of Byte per Sample – 1
Sets data length per Sample in the FIFO by Byte unit

－686/1293－

CXD5602 User Manual

3.9.12.10.146{0x328} V9_W_C_STATUS Details
Table SCU (Sensor Control Unit)-519
Register Type: RO (read only)

Local Address: 0x328

Reset Value: 0x00000000

FIFO_WRITE_PTR

Bits
31..16
15..4

Name
FIFO_WRITE_
PTR
Reserved

Reserved

Type

Reset
Value

RO

0x0000RO

0x000

Description
Writing pointer address of the FIFO
The start address where the next data is written by Byte unit
Reserved
Write phase of the data in the FIFO

3..0

FIFO_WRITE_
PHASE

RO

0x0

FIFO_WRITE_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

－687/1293－

CXD5602 User Manual

3.9.12.10.147{0x32C} V9_W_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-520
Register Type: RO (read only)

Local Address: 0x32C

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_TIMESTAMP_MSB

Bits

Name

Type Reset Value

Description
Latest time stamp (integer part of second)

31..0

LATEST_TIMESTA
MP_MSB

RO

0x00000000

Time stamp which supports the newest data in
the FIFO
Second unit

3.9.12.10.148{0x330} V9_W_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-521
Register Type: RO (read only)

Local Address: 0x330

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedLATEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Latest time stamp (second after the decimal
14..0

LATEST_TIMESTA
MP_LSB

RO

0x0000point)The start address where the next data is written
by Byte unit

－688/1293－

CXD5602 User Manual

3.9.12.10.149{0x334} V9_W_C_TIMSTAMP_SET0 Details
Table SCU (Sensor Control Unit)-522
Register Type: RW (read/write)

Local Address: 0x334

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LATEST_BASE_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueLATEST_BASE_TIMESTAMP_MSB

3.9.12.10.150

RW

Description
Reference time stamp value (integer part of

0x00000000

second){0x338} V9_W_C_TIMSTAMP_SET1 Details
Table SCU (Sensor Control Unit)-523
Register Type: RW (read/write)

Local Address: 0x338

Reset Value: 0x00000000

TIME_STAMP_INTERVAL

Bits

Name

Type

31

ReservedRO

Reserved

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset
Value
0x0

LATEST_BASE_TIMESTAMP_LSB

Description
Reserved
Time stamp interval (virtual sensor partition only)

30..16

TIME_STAMP_IN
TERVALTIME_STAMP_INTERVAL only exists in the control
RW

0x0000registers for the virtual sensor partition.
Every writing to FIFO_WRITE_REG, the value isaccumulated to LATEST_TIME_STAMP.

15
14..0

ReservedLATEST_BASE_T
IMESTAMP_LSB

RO

0x0

RW

0x0000Reserved
Reference time stamp value (second after the decimal
point)－689/1293－

CXD5602 User Manual

3.9.12.10.151{0x1000} D0_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-524
Register Type: RW (read/write)

Local Address: 0x1000

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Bits

Name

31..16 Reserved

WATER_MARK
Type

Reset Value

Description

RO

0x0000Reserved
Watermark value (sample unit) for interrupt/DMA control
When the number of valid data in the FIFO is the same as the

15..0

WATER_MARK

RW

0xFFFFvalue or more, an interrupt occurs/a request for DMA transfer
begins.
The interrupt request only occurs when the corresponding
register in INT_ENABLE_MAIN is set to “1”.

－690/1293－

CXD5602 User Manual

3.9.12.10.152{0x1004} D0_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-525
Register Type: RW (read/write)

Local Address: 0x1004

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_ENABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENAB
LE

RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET WO

0x0

The value of the readout pointer is forced to set the same value ofthe writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_RESET
Reserved
FIFO_UNDE
R_RUN_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced to
set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of the
FIFO is “0”－691/1293－

CXD5602 User Manual

0

FIFO_OVER_
RUN_CLR

3.9.12.10.153

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1008} D0_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-526
Register Type: RO (read only)

Local Address: 0x1008

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

31..16 Reserved
15..0

FIFO_AVAIABLE_
DATA_NUM

FIFO_AVAIABLE_DATA_NUM

Type

Reset
Value

RO

0x0000RO

0x0000Description
Reserved
The number of data stored in the FIFO
Number of sample unit

－692/1293－

CXD5602 User Manual

3.9.12.10.154{0x100C} D0_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-527
Register Type: RO (read only)

Local Address: 0x100C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full－693/1293－

CXD5602 User Manual

3.9.12.10.155{0x1010} D0_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-528
Register Type: RO (read only)

Local Address: 0x1010

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset Value Description

OLDEST_TIMESTAM
P_MSB

3.9.12.10.156

Earliest time stamp (integer part of second)RO

0x00000000 Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1014} D0_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-529
Register Type: RO (read only)

Local Address: 0x1014

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－694/1293－

CXD5602 User Manual

3.9.12.10.157{0x1020} D0_R2_C_CTRL0 Details
Table SCU (Sensor Control Unit)-530
Register Type: RW (read/write)

Local Address: 0x1020

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－695/1293－

in

CXD5602 User Manual

3.9.12.10.158{0x1024} D0_R2_C_CTRL1 Details
Table SCU (Sensor Control Unit)-531
Register Type: RW (read/write)

Local Address: 0x1024

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_ENABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENAB
LE

RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET WO

0x0

The value of the readout pointer is forced to set the same value ofthe writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_RESET
Reserved
FIFO_UNDE
R_RUN_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced to
set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of the
FIFO is “0”－696/1293－

CXD5602 User Manual

0

FIFO_OVER_
RUN_CLR

3.9.12.10.159

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1028} D0_R2_C_STATUS0 Details
Table SCU (Sensor Control Unit)-532
Register Type: RO (read only)

Local Address: 0x1028

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－697/1293－

CXD5602 User Manual

3.9.12.10.160{0x102C} D0_R2_C_STATUS1 Details
Table SCU (Sensor Control Unit)-533
Register Type: RO (read only)

Local Address: 0x102C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the FIFO
is “0”
Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full－698/1293－

CXD5602 User Manual

3.9.12.10.161{0x1030} D0_R2_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-534
Register Type: RO (read only)

Local Address: 0x1030

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset Value Description

OLDEST_TIMESTAM
P_MSB

3.9.12.10.162

Earliest time stamp (integer part of second)RO

0x00000000 Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1034} D0_R2_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-535
Register Type: RO (read only)

Local Address: 0x1034

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－699/1293－

CXD5602 User Manual

3.9.12.10.163{0x1040} D1_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-536
Register Type: RW (read/write)

Local Address: 0x1040

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－700/1293－

in

CXD5602 User Manual

3.9.12.10.164{0x1044} D1_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-537
Register Type: RW (read/write)

Local Address: 0x1044

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_ENABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENAB
LE

RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET WO

0x0

The value of the readout pointer is forced to set the same value ofthe writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_RESET
Reserved
FIFO_UNDE
R_RUN_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced to
set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of the
FIFO is “0”－701/1293－

CXD5602 User Manual

0

FIFO_OVER_
RUN_CLR

3.9.12.10.165

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1048} D1_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-538
Register Type: RO (read only)

Local Address: 0x1048

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－702/1293－

CXD5602 User Manual

3.9.12.10.166{0x104C} D1_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-539
Register Type: RO (read only)

Local Address: 0x104C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－703/1293－

CXD5602 User Manual

3.9.12.10.167{0x1050} D1_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-540
Register Type: RO (read only)

Local Address: 0x1050

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset Value Description

OLDEST_TIMESTAM
P_MSB

3.9.12.10.168

Earliest time stamp (integer part of second)RO

0x00000000 Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1054} D1_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-541
Register Type: RO (read only)

Local Address: 0x1054

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－704/1293－

CXD5602 User Manual

3.9.12.10.169{0x1060} D1_R2_C_CTRL0 Details
Table SCU (Sensor Control Unit)-542
Register Type: RW (read/write)

Local Address: 0x1060

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－705/1293－

in

CXD5602 User Manual

3.9.12.10.170{0x1064} D1_R2_C_CTRL1 Details
Table SCU (Sensor Control Unit)-543
Register Type: RW (read/write)

Local Address: 0x1064

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_ENABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENAB
LE

RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET WO

0x0

The value of the readout pointer is forced to set the same value ofthe writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_RESET
Reserved
FIFO_UNDE
R_RUN_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced to
set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of the
FIFO is “0”－706/1293－

CXD5602 User Manual

0

FIFO_OVER_
RUN_CLR

3.9.12.10.171

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1068} D1_R2_C_STATUS0 Details
Table SCU (Sensor Control Unit)-544
Register Type: RO (read only)

Local Address: 0x1068

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－707/1293－

CXD5602 User Manual

3.9.12.10.172{0x106C} D1_R2_C_STATUS1 Details
Table SCU (Sensor Control Unit)-545
Register Type: RO (read only)

Local Address: 0x106C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－708/1293－

CXD5602 User Manual

3.9.12.10.173{0x1070} D1_R2_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-546
Register Type: RO (read only)

Local Address: 0x1070

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset Value Description

OLDEST_TIMESTAM
P_MSB

3.9.12.10.174

Earliest time stamp (integer part of second)RO

0x00000000 Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1074} D1_R2_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-547
Register Type: RO (read only)

Local Address: 0x1074

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－709/1293－

CXD5602 User Manual

3.9.12.10.175{0x1080} N0_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-548
Register Type: RW (read/write)

Local Address: 0x1080

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type

Reset Value

Description

31..16

Reserved

RO

0x0000Reserved
Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－710/1293－

in

CXD5602 User Manual

3.9.12.10.176{0x1084} N0_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-549
Register Type: RW (read/write)

Local Address: 0x1084

Reset Value: 0x00000000

Bits

Name

Type

31..26

Reserved

RO

Reset
Value
0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESETFIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_ENA
BLE

RW

0x0

When the value is "1", the DMA control signal is permitted
to output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE

RW

0x0

“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17

Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_RE
SET
Reserved
FIFO_UNDER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”－711/1293－

CXD5602 User Manual

0

FIFO_OVER_RUN_CLR

3.9.12.10.177

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1088} N0_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-550
Register Type: RO (read only)

Local Address: 0x1088

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type

31..16

Reserved

RO

15..0

FIFO_AVAIABLE_
DATA_NUM

Reset
Value
0x0000Description
Reserved
The number of data stored in the FIFO

RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－712/1293－

CXD5602 User Manual

3.9.12.10.178{0x108C} N0_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-551
Register Type: RO (read only)

Local Address: 0x108C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－713/1293－

CXD5602 User Manual

3.9.12.10.179{0x1090} N0_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-552
Register Type: RO (read only)

Local Address: 0x1090

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.180

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1094} N0_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-553
Register Type: RO (read only)

Local Address: 0x1094

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

31..15 Reserved
14..0

OLDEST_TIME
STAMP_LSB

OLDEST_TIMESTAMP_LSB

TypeReset Value

Description

RO

0x00000

Reserved
Earliest time stamp (second after the decimal point)RO

0x0000Time stamp supporting the earliest data in the FIFO
1/32768 second unit

－714/1293－

CXD5602 User Manual

3.9.12.10.181{0x10A0} N1_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-554
Register Type: RW (read/write)

Local Address: 0x10A0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－715/1293－

in

CXD5602 User Manual

3.9.12.10.182{0x10A4} N1_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-555
Register Type: RW (read/write)

Local Address: 0x10A4

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”－716/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.183

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x10A8} N1_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-556
Register Type: RO (read only)

Local Address: 0x10A8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－717/1293－

CXD5602 User Manual

3.9.12.10.184{0x10AC} N1_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-557
Register Type: RO (read only)

Local Address: 0x10AC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO
is "0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－718/1293－

CXD5602 User Manual

3.9.12.10.185{0x10B0} N1_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-558
Register Type: RO (read only)

Local Address: 0x10B0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.186

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x10B4} N1_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-559
Register Type: RO (read only)

Local Address: 0x10B4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

31..15 Reserved
14..0

OLDEST_TIME
STAMP_LSB

OLDEST_TIMESTAMP_LSB

TypeReset Value

Description

RO

0x00000

Reserved
Earliest time stamp (second after the decimal point)RO

0x0000Time stamp supporting the earliest data in the FIFO
1/32768 second unit

－719/1293－

CXD5602 User Manual

3.9.12.10.187{0x10C0} N2_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-560
Register Type: RW (read/write)

Local Address: 0x10C0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－720/1293－

in

CXD5602 User Manual

3.9.12.10.188{0x10C4} N2_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-561
Register Type: RW (read/write)

Local Address: 0x10C4

Reset Value: 0x00000000

Bits

Name

Type

31..26

Reserved

RO

Reset
Value
0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESETFIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is "1", the DMA control signal is permitted
to output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0”is indicated, the function operates in a way that the readoutside does not recognize that data is written to the FIFO.

23..17

Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”－721/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.189

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x10C8} N2_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-562
Register Type: RO (read only)

Local Address: 0x10C8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－722/1293－

CXD5602 User Manual

3.9.12.10.190{0x10CC} N2_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-563
Register Type: RO (read only)

Local Address: 0x10CC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－723/1293－

CXD5602 User Manual

3.9.12.10.191{0x10D0} N2_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-564
Register Type: RO (read only)

Local Address: 0x10D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.192

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x10D4} N2_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-565
Register Type: RO (read only)

Local Address: 0x10D4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－724/1293－

CXD5602 User Manual

3.9.12.10.193{0x10E0} N3_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-566
Register Type: RW (read/write)

Local Address: 0x10E0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－725/1293－

in

CXD5602 User Manual

3.9.12.10.194{0x10E4} N3_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-567
Register Type: RW (read/write)

Local Address: 0x10E4

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”－726/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.195

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x10E8} N3_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-568
Register Type: RO (read only)

Local Address: 0x10E8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－727/1293－

CXD5602 User Manual

3.9.12.10.196{0x10EC} N3_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-569
Register Type: RO (read only)

Local Address: 0x10EC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－728/1293－

CXD5602 User Manual

3.9.12.10.197{0x10F0} N3_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-570
Register Type: RO (read only)

Local Address: 0x10F0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.198

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x10F4} N3_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-571
Register Type: RO (read only)

Local Address: 0x10F4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－729/1293－

CXD5602 User Manual

3.9.12.10.199{0x1100} N4_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-572
Register Type: RW (read/write)

Local Address: 0x1100

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－730/1293－

in

CXD5602 User Manual

3.9.12.10.200{0x1104} N4_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-573
Register Type: RW (read/write)

Local Address: 0x1104

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”－731/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.201

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1108} N4_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-574
Register Type: RO (read only)

Local Address: 0x1108

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－732/1293－

CXD5602 User Manual

3.9.12.10.202{0x110C} N4_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-575
Register Type: RO (read only)

Local Address: 0x110C

Reset Value: 0x00000000

Bits

31..16
15..12Name
FIFO_READ_
PTR
Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000 Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full－733/1293－

CXD5602 User Manual

3.9.12.10.203{0x1110} N4_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-576
Register Type: RO (read only)

Local Address: 0x1110

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.204

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1114} N4_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-577
Register Type: RO (read only)

Local Address: 0x1114

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－734/1293－

CXD5602 User Manual

3.9.12.10.205{0x1120} N5_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-578
Register Type: RW (read/write)

Local Address: 0x1120

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－735/1293－

in

CXD5602 User Manual

3.9.12.10.206{0x1124} N5_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-579
Register Type: RW (read/write)

Local Address: 0x1124

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is "1", the DMA control signal is permitted to
output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”－736/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.207

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1128} N5_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-580
Register Type: RO (read only)

Local Address: 0x1128

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－737/1293－

CXD5602 User Manual

3.9.12.10.208{0x112C} N5_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-581
Register Type: RO (read only)

Local Address: 0x112C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full－738/1293－

CXD5602 User Manual

3.9.12.10.209{0x1130} N5_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-582
Register Type: RO (read only)

Local Address: 0x1130

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.210

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1134} N5_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-583
Register Type: RO (read only)

Local Address: 0x1134

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－739/1293－

CXD5602 User Manual

3.9.12.10.211{0x1140} N6_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-584
Register Type: RW (read/write)

Local Address: 0x1140

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－740/1293－

in

CXD5602 User Manual

3.9.12.10.212{0x1144} N6_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-585
Register Type: RW (read/write)

Local Address: 0x1144

Reset Value: 0x00000000

Bits

Name

Type

31..26

Reserved

RO

Reset
Value
0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESETFIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is "1", the DMA control signal is permitted
to output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0”is indicated, the function operates in a way that the readoutside does not recognize that data is written to the FIFO.

23..17

Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”－741/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.213

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1148} N6_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-586
Register Type: RO (read only)

Local Address: 0x1148

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－742/1293－

CXD5602 User Manual

3.9.12.10.214{0x114C} N6_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-587
Register Type: RO (read only)

Local Address: 0x114C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－743/1293－

CXD5602 User Manual

3.9.12.10.215{0x1150} N6_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-588
Register Type: RO (read only)

Local Address: 0x1150

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.216

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1154} N6_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-589
Register Type: RO (read only)

Local Address: 0x1154

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－744/1293－

CXD5602 User Manual

3.9.12.10.217{0x1160} N7_R1_C_CTRL0 Details
Table SCU (Sensor Control Unit)-590
Register Type: RW (read/write)

Local Address: 0x1160

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”.

－745/1293－

in

CXD5602 User Manual

3.9.12.10.218{0x1164} N7_R1_C_CTRL1 Details
Table SCU (Sensor Control Unit)-591
Register Type: RW (read/write)

Local Address: 0x1164

Reset Value: 0x00000000

Bits

Name

Type

31..26

Reserved

RO

Reset
Value
0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESETFIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is "1", the DMA control signal is permitted
to output.
When "0", the output is fixed to "0".
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0”is indicated, the function operates in a way that the readoutside does not recognize that data is written to the FIFO.

23..17

Reserved

RO

0x00

Reserved
Reset of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the read out error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”－746/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.219

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1168} N7_R1_C_STATUS0 Details
Table SCU (Sensor Control Unit)-592
Register Type: RO (read only)

Local Address: 0x1168

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－747/1293－

CXD5602 User Manual

3.9.12.10.220{0x116C} N7_R1_C_STATUS1 Details
Table SCU (Sensor Control Unit)-593
Register Type: RO (read only)

Local Address: 0x116C

Reset Value: 0x00000000

Bits

31..16
15..12Name
FIFO_READ_
PTR
Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000 Start address that is read out as the next data
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates "1", when the number of the valid data in the FIFO is"0" and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－748/1293－

CXD5602 User Manual

3.9.12.10.221{0x1170} N7_R1_C_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-594
Register Type: RO (read only)

Local Address: 0x1170

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.222

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1174} N7_R1_C_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-595
Register Type: RO (read only)

Local Address: 0x1174

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－749/1293－

CXD5602 User Manual

3.9.12.10.223{0x1180} D0_R3_CH_CTRL0 Details
Table SCU (Sensor Control Unit)-596
Register Type: RW (read/write)

Local Address: 0x1180

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－750/1293－

in

CXD5602 User Manual

3.9.12.10.224{0x1184} D0_R3_CH_CTRL1 Details
Table SCU (Sensor Control Unit)-597
Register Type: RW (read/write)

Local Address: 0x1184

Reset Value: 0x00000000

Bits

Name

Type

31..26

Reserved

RO

Reset
Value
0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESETFIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is “1”, the DMA control signal is permitted
to output.
When “0”, the output is fixed to “0”.
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0”is indicated, the function operates in a way that the readoutside does not recognize that data is written to the FIFO.

23..17

Reserved

RO

0x00

Reserved
Reset the readout pointer for the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”－751/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.225

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x1188} D0_R3_CH_STATUS0 Details
Table SCU (Sensor Control Unit)-598
Register Type: RO (read only)

Local Address: 0x1188

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－752/1293－

CXD5602 User Manual

3.9.12.10.226{0x118C} D0_R3_CH_STATUS1 Details
Table SCU (Sensor Control Unit)-599
Register Type: RO (read only)

Local Address: 0x118C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－753/1293－

CXD5602 User Manual

3.9.12.10.227{0x1190} D0_R3_CH_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-600
Register Type: RO (read only)

Local Address: 0x1190

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.228

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1194} D0_R3_CH_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-601
Register Type: RO (read only)

Local Address: 0x1194

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－754/1293－

CXD5602 User Manual

3.9.12.10.229{0x11A0} D1_R3_CH_CTRL0 Details
Table SCU (Sensor Control Unit)-602
Register Type: RW (read/write)

Local Address: 0x11A0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－755/1293－

in

CXD5602 User Manual

3.9.12.10.230{0x11A4} D1_R3_CH_CTRL1 Details
Table SCU (Sensor Control Unit)-603
Register Type: RW (read/write)

Local Address: 0x11A4

Reset Value: 0x00000000

Bits

Name

31..26 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_DMA_ENABLE
FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Output permission of the DMA control signal

25

FIFO_DMA_EN
ABLE

RW

0x0

When the value is “1”, the DMA control signal is permitted to
output.
When “0”, the output is fixed to “0”.
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset the readout pointer for the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”－756/1293－

CXD5602 User Manual

0

FIFO_OVER_RU
N_CLR

3.9.12.10.231

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

{0x11A8} D1_R3_CH_STATUS0 Details
Table SCU (Sensor Control Unit)-604
Register Type: RO (read only)

Local Address: 0x11A8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－757/1293－

CXD5602 User Manual

3.9.12.10.232{0x11AC} D1_R3_CH_STATUS1 Details
Table SCU (Sensor Control Unit)-605
Register Type: RO (read only)

Local Address: 0x11AC

Reset Value: 0x00000000

Bits

31..16
15..12Name
FIFO_READ_
PTR
Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000 The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－758/1293－

CXD5602 User Manual

3.9.12.10.233{0x11B0} D1_R3_CH_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-606
Register Type: RO (read only)

Local Address: 0x11B0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.234

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x11B4} D1_R3_CH_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-607
Register Type: RO (read only)

Local Address: 0x11B4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－759/1293－

CXD5602 User Manual

3.9.12.10.235{0x11C0} D0_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-608
Register Type: RW (read/write)

Local Address: 0x11C0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－760/1293－

in

CXD5602 User Manual

3.9.12.10.236{0x11C4} D0_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-609
Register Type: RW (read/write)

Local Address: 0x11C4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset the readout pointer for the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the same valueof the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_
RESETReserved
FIFO_UNDER_
RUN_CLR
FIFO_OVER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－761/1293－

CXD5602 User Manual

3.9.12.10.237{0x11C8} D0_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-610
Register Type: RO (read only)

Local Address: 0x11C8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－762/1293－

CXD5602 User Manual

3.9.12.10.238{0x11CC} D0_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-611
Register Type: RO (read only)

Local Address: 0x11CC

Reset Value: 0x00000000

Bits

31..16
15..12Name
FIFO_READ_
PTR
Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－763/1293－

CXD5602 User Manual

3.9.12.10.239{0x11D0} D0_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-612
Register Type: RO (read only)

Local Address: 0x11D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.240

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x11D4} D0_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-613
Register Type: RO (read only)

Local Address: 0x11D4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－764/1293－

CXD5602 User Manual

3.9.12.10.241{0x11E0} D1_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-614
Register Type: RW (read/write)

Local Address: 0x11E0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－765/1293－

in

CXD5602 User Manual

3.9.12.10.242{0x11E4} D1_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-615
Register Type: RW (read/write)

Local Address: 0x11E4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value

Description

RO

0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE RW

0x0“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17 Reserved

RO

0x00

Reserved
Reset the readout pointer for the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_
RESETReserved
FIFO_UNDER_
RUN_CLR
FIFO_OVER_R
UN_CLRRO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－766/1293－

CXD5602 User Manual

3.9.12.10.243{0x11E8} D1_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-616
Register Type: RO (read only)

Local Address: 0x11E8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－767/1293－

CXD5602 User Manual

3.9.12.10.244{0x11EC} D1_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-617
Register Type: RO (read only)

Local Address: 0x11EC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－768/1293－

CXD5602 User Manual

3.9.12.10.245{0x11F0} D1_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-618
Register Type: RO (read only)

Local Address: 0x11F0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.246

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x11F4} D1_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-619
Register Type: RO (read only)

Local Address: 0x11F4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－769/1293－

CXD5602 User Manual

3.9.12.10.247{0x1200} N0_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-620
Register Type: RW (read/write)

Local Address: 0x1200

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－770/1293－

in

CXD5602 User Manual

3.9.12.10.248{0x1204} N0_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-621
Register Type: RW (read/write)

Local Address: 0x1204

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the same valueof the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－771/1293－

CXD5602 User Manual

3.9.12.10.249{0x1208} N0_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-622
Register Type: RO (read only)

Local Address: 0x1208

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－772/1293－

CXD5602 User Manual

3.9.12.10.250{0x120C} N0_R0_H_STATUS1 details
Table SCU (Sensor Control Unit)-623
Register Type: RO (read only)

Local Address: 0x120C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1
0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO fullIndicates “1” if the write occurs in the FIFO when FIFO is full

－773/1293－

CXD5602 User Manual

3.9.12.10.251{0x1210} N0_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-624
Register Type: RO (read only)

Local Address: 0x1210

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueOLDEST_TIME
STAMP_MSB

3.9.12.10.252

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1214} N0_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-625
Register Type: RO (read only)

Local Address: 0x1214

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－774/1293－

CXD5602 User Manual

3.9.12.10.253{0x1220} N1_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-626
Register Type: RW (read/write)

Local Address: 0x1220

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－775/1293－

in

CXD5602 User Manual

3.9.12.10.254{0x1224} N1_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-627
Register Type: RW (read/write)

Local Address: 0x1224

Reset Value: 0x00000000

Bits

Name

Type

31..25Reserved

RO

Reset
Value
0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_RESETFIFO_ENABLE

Reserved

FIFO_PHASE_RESET

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0”is indicated, the function operates in a way that the readoutside does not recognize that data is written to the FIFO.

23..17

Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－776/1293－

CXD5602 User Manual

3.9.12.10.255{0x1228} N1_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-628
Register Type: RO (read only)

Local Address: 0x1228

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－777/1293－

CXD5602 User Manual

3.9.12.10.256{0x122C} N1_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-629
Register Type: RO (read only)

Local Address: 0x122C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－778/1293－

CXD5602 User Manual

3.9.12.10.257{0x1230} N1_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-630
Register Type: RO (read only)

Local Address: 0x1230

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.258

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1234} N1_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-631
Register Type: RO (read only)

Local Address: 0x1234

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－779/1293－

CXD5602 User Manual

3.9.12.10.259{0x1240} N2_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-632
Register Type: RW (read/write)

Local Address: 0x1240

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－780/1293－

in

CXD5602 User Manual

3.9.12.10.260{0x1244} N2_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-633
Register Type: RW (read/write)

Local Address: 0x1244

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－781/1293－

CXD5602 User Manual

3.9.12.10.261{0x1248} N2_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-634
Register Type: RO (read only)

Local Address: 0x1248

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－782/1293－

CXD5602 User Manual

3.9.12.10.262{0x124C} N2_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-635
Register Type: RO (read only)

Local Address: 0x124C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－783/1293－

CXD5602 User Manual

3.9.12.10.263{0x1250} N2_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-636
Register Type: RO (read only)

Local Address: 0x1250

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.264

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1254} N2_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-637
Register Type: RO (read only)

Local Address: 0x1254

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－784/1293－

CXD5602 User Manual

3.9.12.10.265{0x1260} N3_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-638
Register Type: RW (read/write)

Local Address: 0x1260

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－785/1293－

in

CXD5602 User Manual

3.9.12.10.266{0x1264} N3_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-639
Register Type: RW (read/write)

Local Address: 0x1264

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value Description

RO

0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE RW

0x0“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－786/1293－

CXD5602 User Manual

3.9.12.10.267{0x1268} N3_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-640
Register Type: RO (read only)

Local Address: 0x1268

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－787/1293－

CXD5602 User Manual

3.9.12.10.268{0x126C} N3_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-641
Register Type: RO (read only)

Local Address: 0x126C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－788/1293－

CXD5602 User Manual

3.9.12.10.269{0x1270} N3_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-642
Register Type: RO (read only)

Local Address: 0x1270

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.270

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1274} N3_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-643
Register Type: RO (read only)

Local Address: 0x1274

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－789/1293－

CXD5602 User Manual

3.9.12.10.271{0x1280} N4_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-644
Register Type: RW (read/write)

Local Address: 0x1280

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－790/1293－

in

CXD5602 User Manual

3.9.12.10.272{0x1284} N4_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-645
Register Type: RW (read/write)

Local Address: 0x1284

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Type Reset Value Description
RO

0x00

Reserved
Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE RW

0x0“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－791/1293－

CXD5602 User Manual

3.9.12.10.273{0x1288} N4_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-646
Register Type: RO (read only)

Local Address: 0x1288

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－792/1293－

CXD5602 User Manual

3.9.12.10.274{0x128C} N4_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-647
Register Type: RO (read only)

Local Address: 0x128C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－793/1293－

CXD5602 User Manual

3.9.12.10.275{0x1290} N4_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-648
Register Type: RO (read only)

Local Address: 0x1290

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.276

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1294} N4_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-649
Register Type: RO (read only)

Local Address: 0x1294

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－794/1293－

CXD5602 User Manual

3.9.12.10.277{0x12A0} N5_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-650
Register Type: RW (read/write)

Local Address: 0x12A0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－795/1293－

in

CXD5602 User Manual

3.9.12.10.278{0x12A4} N5_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-651
Register Type: RW (read/write)

Local Address: 0x12A4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value

Description

RO

0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted.
24

FIFO_ENABLE

RW

0x0

When “0” is indicated, the function operates in a waythat the readout side does not recognize that data is
written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set thesame value of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_RE
SET
Reserved
FIFO_UNDER_RU
N_CLR
FIFO_OVER_RUN
_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it
is forced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number ofvalid data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－796/1293－

CXD5602 User Manual

3.9.12.10.279{0x12A8} N5_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-652
Register Type: RO (read only)

Local Address: 0x12A8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－797/1293－

CXD5602 User Manual

3.9.12.10.280{0x12AC} N5_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-653
Register Type: RO (read only)

Local Address: 0x12AC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the FIFO
is “0”
Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－798/1293－

CXD5602 User Manual

3.9.12.10.281{0x12B0} N5_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-654
Register Type: RO (read only)

Local Address: 0x12B0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.282

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x12B4} N5_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-655
Register Type: RO (read only)

Local Address: 0x12B4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－799/1293－

CXD5602 User Manual

3.9.12.10.283{0x12C0} N6_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-656
Register Type: RW (read/write)

Local Address: 0x12C0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－800/1293－

in

CXD5602 User Manual

3.9.12.10.284{0x12C4} N6_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-657
Register Type: RW (read/write)

Local Address: 0x12C4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value

Description

RO

0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted.
24

FIFO_ENABLE RW

0x0

When “0” is indicated, the function operates in a waythat the readout side does not recognize that data is
written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set thesame value of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－801/1293－

CXD5602 User Manual

3.9.12.10.285{0x12C8} N6_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-658
Register Type: RO (read only)

Local Address: 0x12C8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－802/1293－

CXD5602 User Manual

3.9.12.10.286{0x12CC} N6_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-659
Register Type: RO (read only)

Local Address: 0x12CC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the FIFO
is “0”
Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－803/1293－

CXD5602 User Manual

3.9.12.10.287{0x12D0} N6_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-660
Register Type: RO (read only)

Local Address: 0x12D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueOLDEST_TIMESTA
MP_MSB

3.9.12.10.288

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x12D4} N6_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-661
Register Type: RO (read only)

Local Address: 0x12D4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－804/1293－

CXD5602 User Manual

3.9.12.10.289{0x12E0} N7_R0_H_CTRL0 Details
Table SCU (Sensor Control Unit)-662
Register Type: RW (read/write)

Local Address: 0x12E0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－805/1293－

in

CXD5602 User Manual

3.9.12.10.290{0x12E4} N7_R0_H_CTRL1 Details
Table SCU (Sensor Control Unit)-663
Register Type: RW (read/write)

Local Address: 0x12E4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value

Description

RO

0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted.
24

FIFO_ENABLE RW

0x0

When “0” is indicated, the function operates in a waythat the readout side does not recognize that data is
written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set thesame value of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－806/1293－

CXD5602 User Manual

3.9.12.10.291{0x12E8} N7_R0_H_STATUS0 Details
Table SCU (Sensor Control Unit)-664
Register Type: RO (read only)

Local Address: 0x12E8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－807/1293－

CXD5602 User Manual

3.9.12.10.292{0x12EC} N7_R0_H_STATUS1 Details
Table SCU (Sensor Control Unit)-665
Register Type: RO (read only)

Local Address: 0x12EC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the FIFO
is “0”
Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－808/1293－

CXD5602 User Manual

3.9.12.10.293{0x12F0} N7_R0_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-666
Register Type: RO (read only)

Local Address: 0x12F0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.294

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x12F4} N7_R0_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-667
Register Type: RO (read only)

Local Address: 0x12F4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－809/1293－

CXD5602 User Manual

3.9.12.10.295{0x1300} V0_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-668
Register Type: RW (read/write)

Local Address: 0x1300

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－810/1293－

in

CXD5602 User Manual

3.9.12.10.296{0x1304} V0_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-669
Register Type: RW (read/write)

Local Address: 0x1304

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value

Description

RO

0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted.
24

FIFO_ENABLE RW

0x0

When “0” is indicated, the function operates in a waythat the readout side does not recognize that data is
written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set thesame value of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－811/1293－

CXD5602 User Manual

3.9.12.10.297{0x1308} V0_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-670
Register Type: RO (read only)

Local Address: 0x1308

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－812/1293－

CXD5602 User Manual

3.9.12.10.298{0x130C} V0_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-671
Register Type: RO (read only)

Local Address: 0x130C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the FIFO
is “0”
Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－813/1293－

CXD5602 User Manual

3.9.12.10.299{0x1310} V0_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-672
Register Type: RO (read only)

Local Address: 0x1310

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.300

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1314} V0_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-673
Register Type: RO (read only)

Local Address: 0x1314

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－814/1293－

CXD5602 User Manual

3.9.12.10.301{0x1320} V1_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-674
Register Type: RW (read/write)

Local Address: 0x1320

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－815/1293－

in

CXD5602 User Manual

3.9.12.10.302{0x1324} V1_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-675
Register Type: RW (read/write)

Local Address: 0x1324

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value Description

RO

0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE RW

0x0“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－816/1293－

CXD5602 User Manual

3.9.12.10.303{0x1328} V1_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-676
Register Type: RO (read only)

Local Address: 0x1328

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－817/1293－

CXD5602 User Manual

3.9.12.10.304{0x132C} V1_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-677
Register Type: RO (read only)

Local Address: 0x132C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－818/1293－

CXD5602 User Manual

3.9.12.10.305{0x1330} V1_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-678
Register Type: RO (read only)

Local Address: 0x1330

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueOLDEST_TIMESTA
MP_MSB

3.9.12.10.306

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1334} V1_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-679
Register Type: RO (read only)

Local Address: 0x1334

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－819/1293－

CXD5602 User Manual

3.9.12.10.307{0x1340} V2_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-680
Register Type: RW (read/write)

Local Address: 0x1340

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－820/1293－

in

CXD5602 User Manual

3.9.12.10.308{0x1344} V2_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-681
Register Type: RW (read/write)

Local Address: 0x1344

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value Description

RO

0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved
Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE RW

0x0“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－821/1293－

CXD5602 User Manual

3.9.12.10.309{0x1348} V2_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-682
Register Type: RO (read only)

Local Address: 0x1348

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－822/1293－

CXD5602 User Manual

3.9.12.10.310{0x134C} V2_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-683
Register Type: RO (read only)

Local Address: 0x134C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－823/1293－

CXD5602 User Manual

3.9.12.10.311{0x1350} V2_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-684
Register Type: RO (read only)

Local Address: 0x1350

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.312

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1354} V2_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-685
Register Type: RO (read only)

Local Address: 0x1354

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－824/1293－

CXD5602 User Manual

3.9.12.10.313{0x1360} V3_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-686
Register Type: RW (read/write)

Local Address: 0x1360

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－825/1293－

in

CXD5602 User Manual

3.9.12.10.314{0x1364} V3_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-687
Register Type: RW (read/write)

Local Address: 0x1364

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Type Reset Value Description
RO

0x00

Reserved
Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE RW

0x0“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－826/1293－

CXD5602 User Manual

3.9.12.10.315{0x1368} V3_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-688
Register Type: RO (read only)

Local Address: 0x1368

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－827/1293－

CXD5602 User Manual

3.9.12.10.316{0x136C} V3_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-689
Register Type: RO (read only)

Local Address: 0x136C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－828/1293－

CXD5602 User Manual

3.9.12.10.317{0x1370} V3_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-690
Register Type: RO (read only)

Local Address: 0x1370

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.318

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1374} V3_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-691
Register Type: RO (read only)

Local Address: 0x1374

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－829/1293－

CXD5602 User Manual

3.9.12.10.319{0x1380} V4_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-692
Register Type: RW (read/write)

Local Address: 0x1380

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－830/1293－

in

CXD5602 User Manual

3.9.12.10.320{0x1384} V4_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-693
Register Type: RW (read/write)

Local Address: 0x1384

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type

Reset Value

Description

RO

0x00

Reserved

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted.
24

FIFO_ENABLE RW

0x0

When “0” is indicated, the function operates in a waythat the readout side does not recognize that data is
written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set thesame value of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－831/1293－

CXD5602 User Manual

3.9.12.10.321{0x1388} V4_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-694
Register Type: RO (read only)

Local Address: 0x1388

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－832/1293－

CXD5602 User Manual

3.9.12.10.322{0x138C} V4_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-695
Register Type: RO (read only)

Local Address: 0x138C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the FIFO
is “0”
Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－833/1293－

CXD5602 User Manual

3.9.12.10.323{0x1390} V4_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-696
Register Type: RO (read only)

Local Address: 0x1390

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.324

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1394} V4_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-697
Register Type: RO (read only)

Local Address: 0x1394

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－834/1293－

CXD5602 User Manual

3.9.12.10.325{0x13A0} V5_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-698
Register Type: RW (read/write)

Local Address: 0x13A0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－835/1293－

in

CXD5602 User Manual

3.9.12.10.326{0x13A4} V5_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-699
Register Type: RW (read/write)

Local Address: 0x13A4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－836/1293－

CXD5602 User Manual

3.9.12.10.327{0x13A8} V5_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-700
Register Type: RO (read only)

Local Address: 0x13A8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－837/1293－

CXD5602 User Manual

3.9.12.10.328{0x13AC} V5_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-701
Register Type: RO (read only)

Local Address: 0x13AC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－838/1293－

CXD5602 User Manual

3.9.12.10.329{0x13B0} V5_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-702
Register Type: RO (read only)

Local Address: 0x13B0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.330

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x13B4} V5_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-703
Register Type: RO (read only)

Local Address: 0x13B4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－839/1293－

CXD5602 User Manual

3.9.12.10.331{0x13C0} V6_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-704
Register Type: RW (read/write)

Local Address: 0x13C0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－840/1293－

in

CXD5602 User Manual

3.9.12.10.332{0x13C4} V6_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-705
Register Type: RW (read/write)

Local Address: 0x13C4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－841/1293－

CXD5602 User Manual

3.9.12.10.333{0x13C8} V6_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-706
Register Type: RO (read only)

Local Address: 0x13C8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－842/1293－

CXD5602 User Manual

3.9.12.10.334{0x13CC} V6_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-707
Register Type: RO (read only)

Local Address: 0x13CC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－843/1293－

CXD5602 User Manual

3.9.12.10.335{0x13D0} V6_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-708
Register Type: RO (read only)

Local Address: 0x13D0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type Reset ValueOLDEST_TIMESTA
MP_MSB

3.9.12.10.336

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x13D4} V6_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-709
Register Type: RO (read only)

Local Address: 0x13D4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－844/1293－

CXD5602 User Manual

3.9.12.10.337{0x13E0} V7_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-710
Register Type: RW (read/write)

Local Address: 0x13E0

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－845/1293－

in

CXD5602 User Manual

3.9.12.10.338{0x13E4} V7_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-711
Register Type: RW (read/write)

Local Address: 0x13E4

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE

RW

0x0

When “1” is indicated, the operation is permitted. When “0”is indicated, the function operates in a way that the readoutside does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_RE
SET
Reserved
FIFO_UNDER_RU
N_CLR
FIFO_OVER_RUN
_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid dataof the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－846/1293－

CXD5602 User Manual

3.9.12.10.339{0x13E8} V7_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-712
Register Type: RO (read only)

Local Address: 0x13E8

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－847/1293－

CXD5602 User Manual

3.9.12.10.340{0x13EC} V7_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-713
Register Type: RO (read only)

Local Address: 0x13EC

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－848/1293－

CXD5602 User Manual

3.9.12.10.341{0x13F0} V7_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-714
Register Type: RO (read only)

Local Address: 0x13F0

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.342

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x13F4} V7_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-715
Register Type: RO (read only)

Local Address: 0x13F4

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－849/1293－

CXD5602 User Manual

3.9.12.10.343{0x1400} V8_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-716
Register Type: RW (read/write)

Local Address: 0x1400

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－850/1293－

in

CXD5602 User Manual

3.9.12.10.344{0x1404} V8_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-717
Register Type: RW (read/write)

Local Address: 0x1404

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type Reset Value

Description

RO

Reserved

0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operation permission of the FIFO readout function
When “1” is indicated, the operation is permitted. When24

FIFO_ENABLE RW

0x0“0” is indicated, the function operates in a way that thereadout side does not recognize that data is written to the
FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it isforced to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid
data of the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－851/1293－

CXD5602 User Manual

3.9.12.10.345{0x1408} V8_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-718
Register Type: RO (read only)

Local Address: 0x1408

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－852/1293－

CXD5602 User Manual

3.9.12.10.346{0x140C} V8_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-719
Register Type: RO (read only)

Local Address: 0x140C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－853/1293－

CXD5602 User Manual

3.9.12.10.347{0x1410} V8_R_H_TIMSTAMP0 Details
Table SCU (Sensor Control Unit)-720
Register Type: RO (read only)

Local Address: 0x1410

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OLDEST_TIMESTAMP_MSB

Bits
31..0

Name

Type

OLDEST_TIME
STAMP_MSB

3.9.12.10.348

Reset Value

Description
Earliest time stamp (integer part of second)RO

0x00000000

Register for reading out the data in the FIFO
Can read out the earliest data in the FIFO

{0x1414} V8_R_H_TIMSTAMP1 Details
Table SCU (Sensor Control Unit)-721
Register Type: RO (read only)

Local Address: 0x1414

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

OLDEST_TIMESTAMP_LSB

Bits

Name

Type Reset Value

Description

31..15ReservedRO

Reserved

0x00000

Earliest time stamp (second after the decimal
14..0

OLDEST_TIMESTA
MP_LSB

point)
RO

0x0000Time stamp supporting the earliest data in the
FIFO
1/32768 second unit

－854/1293－

CXD5602 User Manual

3.9.12.10.349{0x1420} V9_R_H_CTRL0 Details
Table SCU (Sensor Control Unit)-722
Register Type: RW (read/write)

Local Address: 0x1420

Reset Value: 0x0000FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

WATER_MARK

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

0x0000

Watermarkvalue(sample

unit)

for

interrupt/DMA control
When the number of valid data in the FIFO is
15..0

WATER_MARK

RW

0xFFFFthe same as the value or more, an interrupt
occurs/a request for DMA transfer begins.
The interrupt request only occurs when thecorresponding

register

INT_ENABLE_MAIN is set to “1”－855/1293－

in

CXD5602 User Manual

3.9.12.10.350{0x1424} V9_R_H_CTRL1 Details
Table SCU (Sensor Control Unit)-723
Register Type: RW (read/write)

Local Address: 0x1424

Reset Value: 0x00000000

Bits

Name

31..25 Reserved

Type
RO

Reset
Value
0x00

FIFO_OVER_RUN_CLR

Reserved

FIFO_UNDER_RUN_CLR

Reserved

FIFO_PHASE_RESET

Reserved

FIFO_RESET

Reserved

FIFO_ENABLE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Reserved
Operation permission of the FIFO readout function

24

FIFO_ENABLE RW

0x0

When “1” is indicated, the operation is permitted. When “0” isindicated, the function operates in a way that the readout side
does not recognize that data is written to the FIFO.

23..17 Reserved

RO

0x00

Reserved
Clear of the FIFO

16

FIFO_RESET

WO

0x0

The value of the readout pointer is forced to set the samevalue of the writing pointer.

15..9
8
7..2
1

0

Reserved
FIFO_PHASE_R
ESET
Reserved
FIFO_UNDER_R
UN_CLR
FIFO_OVER_RU
N_CLR

RO

0x00

Reserved
Reset of the readout pointer for the FIFO

WO

0x0

If the readout pointer is in the process of sampling, it is forced
to set at the head of the next sample.

RO

0x00

Reserved
Clearing of the readout error at FIFO empty

WO

0x0

Clears bits which are read out that the number of valid data of
the FIFO is “0”

WO

0x0

Clearing of the write error at FIFO full
Clears an error occurred by writing at FIFO full

－856/1293－

CXD5602 User Manual

3.9.12.10.351{0x1428} V9_R_H_STATUS0 Details
Table SCU (Sensor Control Unit)-724
Register Type: RO (read only)

Local Address: 0x1428

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FIFO_AVAIABLE_DATA_NUM

Bits

Name

Type Reset Value

Description

31..16

ReservedRO

Reserved

15..0

FIFO_AVAIABLE_
DATA_NUM

0x0000The number of data stored in the FIFO
RO

0x0000The number of data remaining in the FIFO
Number of sample unit

－857/1293－

CXD5602 User Manual

3.9.12.10.352{0x142C} V9_R_H_STATUS1 Details
Table SCU (Sensor Control Unit)-725
Register Type: RO (read only)

Local Address: 0x142C

Reset Value: 0x00000000

Bits

31..16Name
FIFO_READ_
PTR

15..12 Reserved

Type

Reset
Value

FIFO_OVER_RUN

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_FULLFIFO_ALMOST_FULL
FIFO_UNDER_RUN

Reserved

Reserved

FIFO_READ_PTR

FIFO_READ_PHASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Description
Readout pointer address in the FIFO

RO

0x0000The next data is read out on the start address
Byte unit

RO

0x0

Reserved
Readout phase of the data in the FIFO

11..8

FIFO_READ_
PHASE

RO

0x0

The data position in a sample data stored in the FIFO
(by Byte unit)“0” indicates that it is delimited of the sample data.

7..6
5
4
3
2
1

0

Reserved

RO

0x0

RO

0x0

RO

0x0

FIFO_FULL RO

0x0

FIFO_EMPTY_BYTE
FIFO_EMPTY_SAMPLE
FIFO_ALMOST_FULL
FIFO_UNDE
R_RUN
FIFO_OVER_
RUN

RO

0x0

RO

0x0

Reserved
Indicates “1” when the number of the valid data byte in the
FIFO is “0”Indicates “1” when the number of the valid data sample in the
FIFO is “0”Indicates “1” when the FIFO is fullIndicates “1” when the number of the valid data in the FIFO is
WATER_MARK or more
Indicates “1”, when the number of the valid data in the FIFO is“0” and the FIFO data is read out.
Indicates that the write occurs at FIFO full

RO

0x0

Indicates “1” if the write occurs in the FIFO when the FIFO is
full－858/1293－

CXD5602 User Manual

3.9.12.11

SCU_RAM Parameters

The following table shows the parameters within the SCU_RAM. Since these parameters are within thememory, they are undefined after a reset is performed, and therefore, their initial values must be set from the CPUor the internal sequencer. When Reserved regions are not initialized by the CPU, undefined values are read out.
The SCU_RAM parameters are used to run the firmware that controls the sequencers.
Table SCU (Sensor Control Unit)-726 SCU_RAM Parameters
Parameter Name

Address Offset

RW

Description

SCU_SW_REVISION_DATE

0x0000RO

Year, month, date that the SCU SW was built

SCU_SW_REVISION_TIME

0x0004

RO

Time that the SCU SW was built

SCU_SW_REVISION_GIT_HASH

0x0008RO

Configuration management data of the SCU SW

SEQ_SRC_SEL

0x000c

RW

Source setting of the sequencer

Reserved

0x0010Reserved

Reserved

0x0014 to 0x001c

Reserved

SEQ_PROPERTY_n

0x0020 + n x 0x20

RW

Attribute settings of sequencer n (n = 0, …, 9)

SEQ_OUT_FORMAT_n0x0024 + n x 0x20

RW

Output format setting of sequencer n (n = 0, …, 9)

SEQ_MATH_PROC_OFST_GAIN_n

0x0028 + n x 0x04

RW

Offset value and gain value of vector element n of_m

+ m x 0x20

sequencer m (n = 0, …, 2, m = 0, …, 9)
Corresponds to n = 0: X value, n = 1: Y value, n = 2: Z
value

Reserved

0x0034 + n x 0x20

Reserved (n = 0, …, 9)

to0x003c + n x 0x20
SEQ_INSTRUCTION_n0x0160 + n x 0x04

RW

Sequencer n instructions (n = 0, …, 127)

ADC_PROPERTY

0x0260RW

Attribute settings of ADC

ADC_MATH_PROC_OFST_GAIN_n

0x0264 + n x 0x04

RW

Offset value and gain value of ADC (n = 0, …, 6)

FIFO_WRITE_EVENT_CTRL_n0x0280 + n x 0x04

RW

Event control setting of FIFO (n = 0, …, 14)

FIFO_SRAM_POWER_CTRL

0x02c0RW

Power supply control setting of SRAM for FIFOSYNCHRO_CPU2iSoP

0x02c4

RW

Sequencer ID that issues interrupt upon completion orsuspension

SYNCHRO_iSoP2CPU

0x02c8RW

After the sequencer ID suspend interrupt, if the sequencer is
executed, the error is notified

Reserved

0x02c4 to 0x02c8

SEQ_RAM_OUT_n_READ_DATA_

0x02cc + n x 0x20m

+ m x 0x04

SCU_SW_STATUS

0x02fc to 0x310

Reserved
RW

Data read out from sensor by One-shot Sequencer (n = 0,…, 2, m = 0, …, 3)

RO－859/1293－

Status flag of firmware of SCU internal sequencer

CXD5602 User ManualFor debugging
SCU_FIFO_COPY_INFO_n

0x0314 + n x 0x04

RW

Copy enable flag and copy destination Write FIFO ID ofwrite partition

3.9.12.11.1 SCU_SW_REVISION_DATE
Table SCU (Sensor Control Unit)-727
OFFSET: 0x0000
NAME

Field NameSCU_SW_REVISION_DATE

Bit

RW

Description[31:0]RO

Year, month, and date that SCU SW was built. TheYYYYMMDD can be obtained on hexadecimal. (E.g.
20140819)

This parameter must be written during startup of the internal sequencer and cannot be updated later.

3.9.12.11.2 SCU_SW_REVISION_TIME
Table SCU (Sensor Control Unit)-728
OFFSET: 0x0004
NAME

Field Name

Bit

SCU_SW_REVISION_TIME

Reserved[31:24][23:0]

RW

Description
Reserved

RO

Time that the SCU SW was built. The HHMMSS canbe obtained in hexadecimal. (E.g. 100615)

This parameter must be written during startup of the internal sequencer and cannot be updated later.

3.9.12.11.3 SCU_SW_REVISION_GIT_HASH
Table SCU (Sensor Control Unit)-729
OFFSET: 0x0008
NAME

Field Name

Bit

SCU_SW_REVISION_GIT_HASHReserved[31:28][27:0]

RW

Description
Reserved

RO

Configuration management information of the SCU
SW. The leading seven characters of the git hash value
can be obtained in hexadecimal. (E.g. 8b447cd)

This parameter must be written during startup of the internal sequencer and cannot be updated later.

－860/1293－

CXD5602 User Manual

3.9.12.11.4 SEQ_SRC_SEL
Table SCU (Sensor Control Unit)-730
OFFSET: 0x000c
NAME

Field Name

Bit

RW

SEQ_SRC_SEL

Reserved[31:30]I2C1_SRC_SEL[29:20]Description
Reserved

RW

Selects the I2C1 sequencer using each bit. (When the
I2C1 sequencer is 4 or 6, select 0x50)

I2C0_SRC_SEL[19:10]

RW

Selects the I2C0 sequencer using each bit. (When the
I2C0 sequencer is 3 or 5, select 0x28)

SPI_SRC_SEL

[9:0]

RW

Selects the SPI sequencer using each bit. (When the SPI
sequencer is 0,1, or 2, select 0x07)

Each bit of this parameter cannot be written when the corresponding sequencer is in operation.

3.9.12.11.5 SEQ_PROPERTY_n
Table SCU (Sensor Control Unit)-731
OFFSET: 0x0020 + n x 0x20 (n = 0, ..., 9)
NAME

Field Name

Bit

SEQ_PROPERTY_

Reserved[31:29]n

INST_LEN[28:24]RW

Description
Reserved

RW

Sets the number of sequence commands of the sequencer. “0”corresponds to 1 command. (0 to 31)

INST_OFST[22:16]

RW

Sets the start offset of the sequence command of the sequencer. “0”corresponds to no offset. (0 to 127)

SEQ_OUT_SEL[13:12]

RW

Sets the writing destination of the data read out from the sensor.
0: FIFO
1: SEQ_RAM_OUT_0
2: SEQ_RAM_OUT_1
3: SEQ_RAM_OUT_2

SEQ_SRC_SEL_
SUB[10:0]

RW

Sets the supplementary information of the data source of thesequencer.
When SRC_SEL_0 is “0”: SPI SlaveSelect ID(0 to 2)
When SRC_SEL_1 is “1” or “2”: I2C SlaveAddressThis parameter cannot be rewritten when the corresponding sequencer n is in operation.

－861/1293－

CXD5602 User Manual

3.9.12.11.6 SEQ_OUT_FORMAT_n
Table SCU (Sensor Control Unit)-732
OFFSET: 0x0024 + n x 0x20 (n = 0, ..., 9)
NAME

Field Name

Bit

SEQ_OUT_FORMAT_

Reserved[31:30]n

MATH_WRITE_VEC_[29:28]RW

Description
Reserved

RW

ELE_NUM

Format for writing to the MATH_PROC. Number of vector
elements. “0” corresponds to one element. Set this from “0”
to “2”.

MATH_WRITE_STAR[26:24]RW

T_OFST

Format for writing to the MATH_PROC. The data toprocess is selected using the number of Bytes from the startof the reading buffer. “0” corresponds to no offset. (0 to 7)

Reserved[23]

MATH_WRITE_SHIF[22:20]Reserved
RW

Format for writing to the MATH_PROC. Selects theamount of left bit shift of the 16 bit data. “1” corresponds to

T_SIZE

1 bit shift (0 to 7)
Reserved[19:15]

MATH_WRITE_BYTE[16]

Reserved
RW_SWAPT

Format for writing to the MATH_PROC. Set to “1” whenswapping 8 bit 2 Byte data to 16 bits

Reserved[15:8]

FIFO_WRITE_LEN[7:4]

Reserved
RW

Selects how many Bytes of data read out from the sensor towrite to the FIFO. “0” means 1 Byte (0 to 15)

FIFO_WRITE_START

[3:0]

RW

_OFST

Selects from which Byte of data read out from the sensor tostart writing to the FIFO. “0” means 1 Byte (0 to 15)

Each bit of this parameter cannot be rewritten when the corresponding sequencer n is in operation.

3.9.12.11.7 SEQ_MATH_PROC_OFST_GAIN_n_m
Table SCU (Sensor Control Unit)-733
OFFSET: 0x0028 + n x 0x04 + m x 0x20
NAME

Field Name

Bit

RW

Description

SEQ_MATH_PROC_OFST_GAIN_n_m

GAIN_n[31:16]RW

Gain value of vector n of sequencer m (n =0, …, 2, m = 0, …, 9)

OFST_n[15:0]

RW

Offset value of vector n of sequencer m (n =0, …, 2, m = 0, …, 9)

Each bit of this parameter can be rewritten when its corresponding sequencer m is in operation.

－862/1293－

CXD5602 User Manual

3.9.12.11.8 SEQ_INSTRUCTION_n
Table SCU (Sensor Control Unit)-734)
OFFSET: 0x0264 + n x 0x02 (n = 0, …, 127)
NAME

Field Name

Bit

RW

Description

SEQ_INSTRUCTION_n

INSTRUCTION[15:0]

RW

Sequencer instructions

This parameter cannot be rewritten when the corresponding sequencer is in operation.
The following table shows the instruction formats.
(the value in the first row indicates the bit position)
Table SCU (Sensor Control Unit)-735 Sequencer Instruction Formats
INST.

15

14

13

12

0

REPEAT_COUNT

11

10

9

8

7

6

5

TERMIN

RESTA

STOP

IS_READ

WDATA

ATE

RT

4

3

2

1

NAME
TX_RX

I2C_SLAVE

100

IS_10_BITS

WAIT

1

1

0

0

RESERVED

1

1

1

Reserved

0

SLAVE_ADDRESSWAIT_COUNT

TX_RXInstructions for Tx or Rx transfer


REPEAT_COUNT is the number of times the instruction is repeated. The actual number of repeats - 1 isset.

When TERMINATE is “1”, the sequencer is completed within the main loop being executed after thedata transfer has been completed. After confirming the data, the sequencer executes instructions fromthe next instruction after TERMINATE during the next execution.
[Caution]When I2C command is executed only writing or the last command of I2C command strings is“write”, you cannot set TERMINATE to “1”.

When RESTART is “1”, the transfer starts by the RESTART condition (this is ignored in SPI transfers).

When STOP is “1”, STOP of I2C is executed after the transfer (this is ignored in SPI transfers).

When RESTART and STOP are both “1”, the transfer starts at RESTART and completes at STOP.

When IS_READ is “1”, this indicates Rx transfer, when “0”, it indicates Tx transfer.



WDATA is writing data.

I2C_SLAVE
Instructions that set the I2C slave address (this is ignored in SPI transfers).
When IS_10_BITS is “1”, this indicates the 10 bit addressing mode.

－863/1293－

0

CXD5602 User Manual

SLAVE_ADDRESS is the slave address.

WAIT
Instruction to insert WAITThe sequencer waits for the number of main loops which is set to WAIT_COUNT and then executes the
instruction. Set the actual number of waits – 1.

RESERVED
The values written to Reserved are ignored.

3.9.12.11.9 ADC_PROPERTY
Table SCU (Sensor Control Unit)-736
OFFSET:0x0260
NAME

Field Name

Bit

ADC_PROPERTY

Reserved[31:30]HPADC1_ENABLE

[29]

RW

Description
Reserved

RW

When using the sequencer to read out values fromthe HPADC1, this is “1”.

HPADC0_ENABLE

[28]

RW

When using the sequencer to read out values fromthe HPADC0, this is “1”.

LPADC3_ENABLE

[27]

RW

When using the sequencer to read out values fromthe LPADC3, this is “1”.

LPADC2_ENABLE

[26]

RW

When using the sequencer to read out values fromthe LPADC2, this is “1”.

LPADC1_ENABLE*1

[25]

RW

When using the sequencer to read out values fromthe LPADC1, this is “1”.

LPADC0_ENABLE

[24]

RW

When using the sequencer to read out values fromthe LPADC0, this is “1”.

HPADC1_FIFO_WRITE_ID[23:20]

RW

Selects the FIFO_ID (0 to 15) to which data readout from the HPADC1 is written

HPADC0_FIFO_WRITE_ID[19:16]RW

Selects the FIFO_ID (0 to 15) to which data readout from the HPADC0 is written

LPADC3_FIFO_WRITE_ID[15:12]

RW

Selects the FIFO_ID (0 to 15) to which data readout from the LPADC3 is written

LPADC2_FIFO_WRITE_ID[11:8]

RW

Selects the FIFO_ID (0 to 15) to which data readout from the LPADC2 is written

LPADC1_FIFO_WRITE_ID

[7:4]

RW

Selects the FIFO_ID (0 to 15) to which data readout from the LPADC1 is written

LPADC0_FIFO_WRITE_ID

[3:0]

RW

Selects the FIFO_ID (0 to 15) to which data readout from the LPADC0 is written－864/1293－

CXD5602 User Manual

Only *_ENABLE of this parameter can be rewritten during operation of the ADC. To rewrite only*_ENABLE, Read/Modify/Write access is required.
The following tables shows the FIFO_IDs and the FIFOs linked to FIFO_ID.
Table SCU (Sensor Control Unit)-737 FIFO_IDs and the FIFOs linked to FIFO_ID
FIFO_ID

FIFO

0

D0_W0_S

1

D0_W1_S

Prohibited setting at ADC_PRIORITY2

D0_W2_S

Prohibited setting at ADC_PRIORITY3

D0_W3_S

Prohibited setting at ADC_PRIORITY

4

D1_W0_S

5

D1_W1_S

Prohibited setting at ADC_PRIORITY

6

D1_W2_S

Prohibited setting at ADC_PRIORITY

7

D1_W3_S

Prohibited setting at ADC_PRIORITY

8

N0_W_S

9

N1_W_S10

N2_W_S

11

N3_W_S

12

N4_W_S

13

N5_W_S

14

N6_W_S

15

N7_W_S

3.9.12.11.10 ADC_MATH_PROC_OFST_GAIN_n
Table SCU (Sensor Control Unit)-738
OFFSET: 0x0264 + n x 0x04 (n = 0, ..., 6)
NAME

Field Name

Bit

RW

Description

ADC_MATH_PROC_OFST_GAIN_n

GAIN[31:30]RW

n = 0: LPADC0 gain value (X)n = 1: LPADC1 gain value (X)n = 2: LPADC2 gain value (X)n = 3: LPADC3 gain value (X)n = 4: HPADC0 gain value (X)n = 5: HPADC0 gain value (Y)n = 6: HPADC1 gain value (X)－865/1293－

CXD5602 User Manual

OFST[29:20]RW

n =0: LPADC0 offset value (X)n = 1: LPADC1 offset value (X)n = 2: LPADC2 offset value (X)n = 3: LPADC3 offset value (X)n = 4: HPADC0 offset value (X)n = 5: HPADC0 offset value (Y)n = 6: HPADC1 offset value (X)Each bit of this parameter can be rewritten when the ADC is in operation.

3.9.12.11.11 FIFO_WRITE_EVENT_CTRL_n
Table SCU (Sensor Control Unit)-739
OFFSET: 0x0280 + n x 0x04 (n = 0, ..., 14)
NAME

Field Name

Bit

RW

FIFO_WRITE_

Reserved[31:25]EVENT_CTRL

OUTPUT_8BITS[24]

Description
Reserved

RW_n

Set to “1” when writing only the upper 8 bits of the resultsfrom the Math Function to the FIFO.

Reserved[23:20]WRITE_SAMPLE_NUM[19:8]

Reserved
RW

When WRITE_CTRL is “2”, if selected condition issatisfied, the number of samples selected here are written to
the FIFO. “0” means one time. (0 to 4095)

Reserved[7:6]

Reserved

EVENT_ID[5:4]

When WRITE_CTRL is “1” or “2”, the condition ID
selected here is referenced. Select from 0 to 2.

Reserved[3:2]

Reserved

WRITE_CTRL[1:0]

0: Always writes.
1: Does not write until the condition selected by the
EVENT_ID is satisfied, and starts writing after thecondition is satisfied.
2: Writes until the condition selected by the EVENT_ID issatisfied, and after the condition is satisfied, writes thenumber of samples selected by WRITE_SAMPLE_NUM.
3: Never writes (assumes use only for conditional
statement)

Each bit of this parameter cannot be rewritten when the corresponding sequencer n is in operation.

－866/1293－

CXD5602 User Manualn corresponds to the following Write FIFOs.
n = 0, 1, 2, 3

D0_W0_S, D0_W1_S, D0_W2_S, D0_W3_S

n = 4 , 5, 6, 7

D1_W0_S, D1_W1_S, D1_W2_S, D1_W3_S

n = 8, 9, 10, 11, 12, 13, 14, 15

N0_W_S, N1_W_S, N2_W_S, N3_W_S, N4_W_S, N5_W_S, N6_W_S,

N7_W_S

3.9.12.11.12 FIFO_SRAM_POWER_CTRL
Table SCU (Sensor Control Unit)-740
OFFSET: 0x02c0
NAME

Field Name

Bit

RW

FIFO_SRAM_PO

Reserved[31:25]

WER_CTRLPW_STT_IGNORE1[24]

Description
Reserved

RW

When writing data to the FIFO, SEQ ignores the power supply
status of the later-half 32 Kbytes of FIFO SRAM.

Reserved[23:17]

PW_STT_IGNORE0[16]

Reserved
RW

When writing data to the FIFO, SEQ ignores the power supply
status of the first-half 8 KBytes of FIFO SRAM.

Reserved[15:9]

PW_CTRL_EN1[8]

Reserved
RW

Performs power down control of the later-half 32 KBytes
region of the FIFO SRAM.
Turns ON the SRAM when any of the sequencers within the
SCU starts up, and switches to the low power mode whichholds values of SRAM when writing to the FIFO is completed.

Reserved[7:1]

PW_CTRL_EN0[0]

Reserved
RW

Performs power down control of the first-half 8 KBytes regionof the FIFO SRAM.
Turns ON the SRAM when any of the sequencers within the
SCU starts up, and switches to the low power mode whichholds values of SRAM when writing to the FIFO is completed.

Power supply control of the FIFO by the SCU is not supported. Neither turn OFF nor set the FIFO power supply
to retention during operation of the SCU.

3.9.12.11.13 SEQ_RAM_OUT_n_READ_DATA_m
Table SCU (Sensor Control Unit)-741
OFFSET: 0x02cc + n x 0x20 + m x 0x040 (n = 0, …, 2, m = 0, …, 3)
NAME

Field Name

Bit

RW

Description－867/1293－

CXD5602 User Manual

SEQ_RAM_OUT_n_

DATA3[31:24]RO

The (m x 4 + 4) th Byte of the data read out from the One-shot Sequencer

READ_DATA_m

n
DATA2

[23:16]RO

The (m x 4 + 3) th Byte of the data read out from the One-shot Sequencer
n

DATA1

[15:8]RO

The (m x 4 + 2) th Byte of the data read out from the One-shot Sequencer
n

DATA0

[7:0]

RO

The (m x 4 + 1) th Byte of the data read out from the One-shot Sequencernn corresponds to the channel of the One-shot Sequencer, and three channels of One-shot Sequencer can be used.

3.9.12.11.14 SYNCHRO_CPU2iSoP
Table SCU (Sensor Control Unit)-742
OFFSET:0x02c4
NAME

Field Name

Bit

SYNCHRO_CPU2iSoP

Reserved[31:4]

SEQ_ID[3:0]

RW

Description
Reserved

RW

The sequencer ID that raises an interrupt at completion orsuspension

The following describes the procedures of sequencer complete interrupt request.
(1) Sequencer completion request (change the bit of the corresponding sequencer of START_MODE0 within
SCU_REG from “1” to “0”)(2) Check that Sleep setting is released. If not released, set HPADC0_ACCESS_INHIBIT_REQ within
SCU_REG to “1” (SLEEP release and prohibition)(3) Clear the SCU interrupt factor(4) Disable the iSoP3 IRQ interrupt mask
(5) Set the complete/suspend request sequencer number to the SYNCHRO_CPU2iSoP(6) Set LPADC_ACCESS_INHIBIT_REQ within the SCU_REG to “1” (complete interrupt request)(7) Wait for the interrupt(8) Within the following interrupt context:(i) Set LPADC_ACCESS_INHIBIT_REQ to “0” (release the complete interrupt request)(ii) Set the iSoP3 IRQ interrupt mask(iii) Clear the interrupt factor(9)When SLEEP needs to be enabled, set HPADC0_ACCESS_INHIBIT_REQ to “0” (SLEEP enable)(10) End of procedure
The following describes the procedures of sequencer suspend interrupts.

－868/1293－

CXD5602 User Manual(1) Set the HPADC0_ACCESS_INHIBIT_REQ to “1” (SCU SLEEP release and prohibition)(2) Clear the SCU interrupt factor(3) Disable the iSoP3 IRQ interrupt mask
(4) Set the complete/suspend request sequencer number to the SYNCHRO_CPU2iSoP(5) Set the HPADC1_ACCESS_INHIBIT_REQ to “1” (suspend interrupt request)(6) Wait for the interrupt(7) Within the following interrupt context:(i) Update the MATH_PROC setting (when required)(ii) Set HPADC1_ACCESS_INHIBIT_REQ to “0”(iii) Set the iSoP3 IRQ interrupt mask(iv) Interrupt factor clear(8) Check whether there is “1” in sample data loss flag (SCU_RAM internal parameter SYNCHRO_iSoP2CPU(refer to Section 3.9.12.11)). if there is “1”, there may be sample data loss. Perform readout twice, and after
checking, clear the sample data loss flag to "0".
(9) Set HPADC0_ACCESS_INHIBIT_REQ to “0” (SLEEP enable)(10) End of the procedure

3.9.12.11.15 SYNCHRO_iSoP2CPU
Table SCU (Sensor Control Unit)-743
OFFSET: 0x02c8
NAME

Field Name

Bit

SYNCHRO_iSoP2CPU

Reserved[31:30]

SEQ_ID[0]

RW

Description
Reserved

RW

After the sequencer ID suspend interrupt, if the sequencer is
executed, the error is notified“1” means an error
The internal sequencer sets “1” when an error is detected but
does not return this to “0” (the CPU needs to return it to “0”)Follow the description in Section 3.9.12.11.14 and perform readout and clear according to the procedure.

3.9.12.11.16 SCU_FIFO_COPY_INFO_n
OFFSET: 0x0314 + n x 0x04 (n = 0, 1, ..., 9)
NAME

Field Name

Bit

SCU_FIFO_COPY

Reserved[31:6]_INFO_n

COPY_ID[5:1]

RW

Description
Reserved

RW

The copy destination FIFO_ID (ignored when the enable flag of the
0th bit is negated) of the write partition of sequencer n－869/1293－

CXD5602 User Manual

COPY_ENABLE

[0]

RW

The copy enable flag of the write partition of sequencer nEach bit of this parameter can be rewritten when the corresponding sequencer n is in operation.

3.9.13SCU Control Sequence

The following describes the control sequence. For details on the control, refer to Section 3.9.13.6.

3.9.13.1

Power Supply Startup to Initialization

Power supply startup to initialization is performed by the following procedure.
(1) PWD_SCU power supply On(2) XOSC power supply On(3) RCOSC power supply On(4) LPADC, HPADC power supply On(5) PWD_SCU reset release(6) LPADC functional block reset release(7) HPADC functional block reset release(8) XOSC, RCOSC clock set(9) PWD_SCU clock set(10) SPI clock supply start(11 )I2C0, I2C1 clock supply start(12) LPADC clock supply start(13) HPADC clock supply start(14) LPADC, HPADC operation enable(15) Sensor interrupt input terminal set(16) SPI terminal set(17) I2C0 terminal set(18) I2C1 terminal set(19) LPADC, HPADC terminal set(20) PWM terminal set(21) SCU_REG sequencer-related set(22) Program download to SEQ_IRAM(23) SEQ_DRAM sequencer-related set(24) SCU_FIFO initialization(25) SPI sequencer operation initial value set(26) I2C0 sequencer operation initial value set(27) I2C1 sequencer operation initial value set－870/1293－

CXD5602 User Manual(28) LPADC0 data rate set(29) LPADC1 data rate set(30) LPADC2 data rate set(31)LPADC3 data rate set(32)HPADC0 data rate set(33)HPADC1 data rate set(34)Sequencer boot wait(35)Sequencer startup(36)LPADC data output enable(37)HPADC0 data output enable(38)HPADC1 data output enable

3.9.13.2

Power Source Turn OFF

Power supply turn OFF is performed by the following procedures.
(1) LPADC data output disable(2) HPADC0 data output disable(3) HPADC1 data output disable(4) Sequencer suspend(5) Sequencer reset(6) LPADC, HPADC operation suspend(7) RCOSC, XOSC clock supply stop
(8) LPADC clock supply stop(9) HPADC clock supply stop(10) I2C clock supply stop(11) SPI clock supply stop(12) SCU clock supply stop(13) HPADC power supply stop(14) LPADC power supply stop(15) PWD_SCU power supply stop

3.9.13.3

Sequencer Initialization

Sequencer initialization is performed by the following procedures.
(1) Sequencer, SEQ_IRAM, SEQ_DRAM power supply(2) Sequencer reset(3) FIFO initialization(4) START_CTRL related register set(5) MATH_PROC related register set－871/1293－

CXD5602 User Manual(6) Writing program to SEQ_IRAM(7) Writing setting and initial value to SEQ_DRAM(8) Sequencer clock stop(9) Sequencer reset release(10) Sequencer clock supply start(11) SPI sequencer operation initial value set(12) I2C0 sequencer operation initial value set(13) I2C1 sequencer operation initial value set(14) Sequencer boot completion wait (optional)(15) Sequencer startup(16) LPADC operation start(17) HPADC0 operation start(18 )HPADC1 operation start

3.9.13.4

SPI/I2C/ADC Control

For the settings of SPI, I2C0, I2C1, LPADC, HPADC0, and HPADC1, refer to the following Sections.


SPI sequencer operation initial settings: Section 3.9.13.6.3



I2C0 sequencer operation initial settings: Section 3.9.13.6.5



I2C1 sequencer operation initial settings: Section 3.9.13.6.5



LPADC operation parameter settings: Section 3.9.13.6.6



LPADC data output start: Section 3.9.13.6.6



LPADC conversion settings: Section 3.9.13.6.6



HPADC0 operation parameter settings: Section 3.9.13.6.7



HPADC0 data output start: Section 3.9.13.6.7



HPADC1 operation parameter settings: Section 3.9.13.6.8



HPADC1 data output start settings: Section 3.9.13.6.8

3.9.13.5

FIFO Control

For the following FIFO control procedures, refer to Section 3.9.13.6.9.
Writing side initial settings

Readout side initial settings

FIFO writing process

FIFO readout processTransition process to FIFO (8 KByte) Retention

Transition process to FIFO (8 KByte) All OnTransition process to FIFO (8 KByte) All OffTransition process to FIFO (32 KByte) Retention－872/1293－

CXD5602 User ManualTransition process to FIFO (32 KByte) All OnTransition process to FIFO (32 KByte) All Off

3.9.13.6

Control Setting Details by Function

The following describes the control setting details by function.

3.9.13.6.1

Power Supply Control Power ON
Table SCU (Sensor Control Unit)-744

Event

Control

Addressbit

Name

Power Supply Control Power ON
Setting

Register

Descriptions

Value

LocationPWD_SCU

---

---

---

---

---

Refer to the PMU Chapter (3.4)

TOPREG

0x0008[25]

ON_XO_OSC_

1'b0

The setting parameters differ depending on thePower ONON
XOSC

XOSC operation mode (internal oscillation

EN_SETPower ON

[24]

OFF_XO_OSC

1'b0shows the setting for external clock mode

_EN_CLR[20]

ON_XO_OSCO

1'b0

OFF_XO_OSC

1'b0

ON_XO_EXT_

1'b1

OFF_XO_EXT

OFF_XO_OSC_EN_CLR,
ON_XO_OSCOUT_EN_SET,

EN_SET[17]

configuration using crystal oscillator), set
ON_XO_OSC_EN_SET,OUT_EN_CLR[18](system configuration using TCXO).
For the internal oscillation mode (system

UT_EN_SET[19]

mode or external clock mode). The setting here

1'b1

OFF_XO_OSCOUT_EN_CLR to “1'b1”,
and_EN_CLR

andset

ON_XO_EXT_EN_SET

and

OFF_XO_EXT_EN_CLR to “1'b0”.
0x0584[23:16

IXO_LV_I_VA]

L3[15:8]

IXO_LV_I_VA

8'd0

The setting value is differs depending on theoscillation frequency of the crystal oscillator.

8'd0

For external clock mode, set each to “8'd0”.

L10x0004RSOSC
Power ON

TOPREG

0x0004[17]

WEN_XOSC

1'b1

XOSC power supply control Write Enable

[1]

XOSC

1'b1

XOSC power ON[16]

WEN_RCOSC

1'b1

RCOSC power supply control Write Enable

[0]

RCOSC

1'b1

RSOSC Power ON－873/1293－

CXD5602 User Manual

LPADC,SCU.AD

0x0018d

HPADC

CIF

e40

[0]

LV_CLK_OSC-->

The clock source selection setting during thehigh speed sampling mode

_SEL

0: XOSC, 1: RCOSC

Power ON
[5:4]

LV_CLK_XOS-->

The frequency division setting during the useof the XOSC as clock source

C_DIV

0: divided by 2
1: divided by 3
2: divided by 4
3: divided by 6
0x0018d[0]

LV_BGR_EN

1'b1

LV BGR circuit enable[0]

VECTOR_SEL-->

Enable/disable of two element vector[0]

LV_CLK_U32_-->

Clock selection

e440x0018de500x0018de80

0: High-speed clock

SEL0

1: Low-speed clock
0x0018d[0]

ec0

LV_CLK_U32_-->

Clock selection
0: High-speed clock

SEL1

1: Low-speed clock
0x0018d[0]f80

LV_ADC0_SE

1'b0

ADC0 stage selection

4'b1100

ADC0 internal clock delay amount adjustment

LSTAGE[7:4]

LV_ADC0_DE
LAYADJUST

0x0018d[0]

fc0

LV_ADC1_SE

signal1'b0

ADC0 stage selection

4'b1100

ADC0 internal clock delay amount adjustment

LSTAGE[7:4]

LV_ADC1_DE
LAYADJUST

0x0018dsignal[7:0]

LV_RSV

8'h04[0]

LV_SELSTAG

1'b0

Stage selection

f04
0x0018df00
TOPREG

0x0004

E[29]

WEN_LPADC

1'b1

LPADC power supply control Write Enable

[13]

LPADC

1'b1

LPADC power ON[28]

WEN_HPADC

1'b1

HPADC power supply control Write Enable

[12]

HPADC

1'b1

HPADC power ON－874/1293－

CXD5602 User Manual

Power ON

TOPREG

0x0048[11:0]

CLR|=12'h00D

Sets the following bits to “1”. RMW (OR)Common(Read[3] I2C interrupt during power supply control

Setting

Modify[2] Timeout error occurrence interrupt during

Write

0x004C[11:0]

MSK

power supply control(OR))[0] Power supply control completion interrupt&=12'hFF2

Sets the following bits to “0”. RMW (AND)(Read[3] I2C communication error interrupt during

Modifypower supply control

Write[2] Timeout error occurrence interrupt during(AND))

power supply control[0] Power supply control completion interrupt

0x0030[0]

POWER_CTRL

1'b1

Power supply control execution
note: SRAM for SCU starts operation when_ON

power supply for PWD_SCU is turned ON.
PMU

---

---

---

---

---

Interrupt

Waits for a power supply control completioninterrupt from the PMU

WaitInterrupt

TOPREG

0x0040[11:0]STAT

Confirmati(&=12'h00DInterrupt Confirmation: Check that only [0])==1

DONE is “1”|= 12'h00DSets the following bits to “1”. RMW (OR)on
PWD_SCU

TOPREG

0x0048[11:0]

CLR

Power ON[3] I2C communication error interrupt during

Wait

power supply control

RCOSC,[2] Timeout error occurrence interrupt during

XOSC,
LPADC,

power supply control
0x004C[11:0]

MSK&=12'hFF2

Sets the following bits to “0”. RMW (AND)HPADC[3] I2C communication error interrupt during

Power ONpower supply control[2] Timeout error occurrence interrupt during
power supply control[0] Power supply control completion interrupt
0x009C[0]

POWER_CTRL

1'b1

_ON

Power supply control execution (All SRAMs
start from ON when the PWD_SCU starts up)

Note 1: The setting parameters differ depending on the XOSC operation mode (internal oscillation mode or
external clock mode). The ones shown here are the settings of the external clock mode (configuration using
TCXO), which are the initial values of the TOPREG.
For the internal oscillation mode (configuration using a crystal oscillator), set ON_XO_OSC_EN_SET,
OFF_XO_OSC_EN_CLR, ON_XO_OSCOUT_EN_SET, and OFF_XO_OSCOUT_EN_CLR to “1'b1”, and set
ON_XO_EXT_EN_SET, and OFF_XO_EXT_EN_CLR to “1'b0”.

－875/1293－

CXD5602 User Manual

Caution: The frequencies supported for internal oscillation mode is 26 MHz.
The frequencies supported for external clock mode is 26 MHz.
Note 2: The settings differ for each crystal oscillator frequency. The IXO_LV_I_VAL1 (before oscillation starts)and IXO_LV_I_VAL3 (after changing the current setting) parameter values are tentative values. During external
clock mode, set to “8'd0”.
Table SCU (Sensor Control Unit)-745 Main Reset Control
Event

Control

Addressbit

Name

Register

Setting

Descriptions

Value

LocationPWD_SCU

Reset

TOPREG

0x0060[16]

WEN_PWD_SCU

1'b1

PWD_SCU

Releasereset

control

Write Enable[0]

PWD_SCU

1'b1

PWD_SCU reset release

LPADC Reset Release

TOPREG

0x0704[4]

XRST_SCU_LPADC

1'b1

LPADC reset release

HPADC Reset Release

TOPREG

0x0704[2]

XRST_SCU_HPADC

1'b1

LPADC reset release

For clock control refer to the PMU (3.4) Chapter.
Table SCU (Sensor Control Unit)-746 Sub Reset Control
Event

Control

Addressbit

Name

Register

Setting

Descriptions

Value

LocationLPADC

SCU.ADC0x0018de00[0]

LV_ADC_EN

1'b1

LPADC operation enable

OperationIF

0x0018de10[0]

SW_RESET

1'b1

FIFO reset

HPADC0SCU.ADC0x0018de84[0]

LV_ADC0_EN

1'b1

HPADC0 operation

Operation

IF

Enablepermission /stop

EnableHPADC1

SCU.ADC

OperationIF[1]

LV_ADC0_REF_EN

1'b1

LPF0 Enable control terminal.

[2]

LV_LPF0_EN

1'b1

ADC0 REF circuit enable

0x0018de88[0]

LV_CLKOUT0_EN

1'b1

ADC0 clock output enable

0x0018de90[0]

SW_RESET

1'b1

FIFO reset

0x0018dec4[0]

LV_ADC0_EN

1'b1

HPADC1 operation
permission/stop

EnableReset

SCU.ADC[1]

LV_ADC0_REF_EN

1'b1

LPF1 enable control terminal[2]

LV_LPF0_EN

1'b1

ADC1 REF circuit enable

0x0018dec8[0]

LV_CLKOUT0_EN

1'b1

ADC1 clock output enable

0x0018ded0[0]

SW_RESET

1'b1

FIFO reset

0x0018de10[0]

SW_RESET==0

Confirms whether turns to “0”－876/1293－

CXD5602 User Manual

Confirmati
onIF

0x0018de90[0]

SW_RESET==0

Confirms whether turns to “0”0x0018ded0[0]

SW_RESET==0

Confirms whether turns to “0”－877/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-747 AD Conversion Settings
Control

Register

Addressbit

Name

Setting

Location
SCU.ADCIF

Descriptions

Value
0x0018de04[9:8]

LV_CH_SEL_INV-->ADCH selector for GNSS (set for only the

Refer tofollowing operating channels)

descripti

2'b00 CH0ons

2'b01 CH1
2'b10 CH2
2'b11 CH3

[2:0]

LV_CH_SEL_MODE-->

LPADC channel switching mode

Refer to3'b000 CH0descripti

3'b001 CH1

ons

3'b010 CH2
3'b011 CH3
3'b100 CH0 ==>CH1
3'b101 CH0 ==>CH1==>CH2==>CH3

Table SCU (Sensor Control Unit)-748 Startup Settings
EventControl

Addressbit

Name

Setting Value

Descriptions

---

---

---

---

Follow the API

---

---

---

---

Follow the API

---

---

---

---

Follow the API

0x04EC[21:0]

CLR|= 22'h002000

Sets the following bit to “1”Register
Location
Sequencer

SCU.SCU

Operation_REG

Parameter
Settings
Sequencer

SCU.SCU

Program_REG

Download
Sequencer

SCU.SCU

Operation_REG

Parameter Setting
Interrupt Clear

TOPREG

RMW (OR)[13]:CK_SCU_SEQ On/Off
Interrupt Mask

TOPREG

0x04F0[21:0]

MSK&=

Sets the following bit to “0”22'h3FDFFF

RMW (AND)[13]:CK_SCU_SEQ On/Off－878/1293－

CXD5602 User Manual

Sequencer Clock

TOPREG

0x071C[4]

SCU_REQ

1'b0

Stop
CRG

PWD_SCU sequencer clock enable(CK_SCU_SEQ)

Interrupt

---

---

---

---

---

Wait

Waits for the clock enable completioninterrupt

from

the

Clock

Reset

Generator (CRG)
Interrupt

TOPREG

0x04F4[21:0]STAT

Confirmation

Interrupt Clear

TOPREG

0x04EC[21:0]

CLR(&=

Interrupt confirmation: Confirms that

22'h002000) !

the following bit turns to “1”=0[13]: CK_SCU_SEQ On/Off|= 22'h002000

Sets the following bit to “1”
RMW (OR)[13]: CK_SCU_SEQ On/Off

Reset Release

TOPREG

0x0704[7]

XRST_SCU

1'b1

_ISOP
Interrupt Mask

TOPREG

0x04F0[21:0]

MSK&=

Sets the following bit to “0”22'h3FDFFF

RMW (AND)[13]: CK_SCU_SEQ On/Off

Clock Supply

TOPREG

0x071C[4]

SCU_REQ

1'b1

PWD_SCU sequencer clock enable(CK_SCU_SEQ)

CRG

Interrupt

---

---

---

---

---

Wait

Waits for the clock enable completioninterrupt from the CRG

Interrupt

TOPREG

0x04F4[21:0]STAT

Confirmation

Interrupt Clear

TOPREG

0x04EC[21:0]

CLR(&=

Interrupt confirmation: confirms that the

22'h002000)

following bit turns to “1”!= 0[13]: CK_SCU_SEQ On/Off|= 22'h002000

Sets the following bit to “1”
RMW (OR)[13]: CK_SCU_SEQ On/Off

FIFO

Partition

Setting

SCU.FIF

---

---

---

---

Refer

to

Table

SCU

(SensorControl Unit)-757, Table SCU

O_REG(Sensor Control Unit)-758, Table
SCU (Sensor Control Unit)-759,
Table

SCU

(Sensor

Unit)-760
SPI Initial Setting

SCU.SPI

---

---

---

---

Refer to the SPI (3.10) Chapter

I2C0

InitialSCU.I2C0

---

---

---

---

Refer to the I2C (3.7) Chapter

InitialSCU.I2C1

---

---

---

---

Refer to the I2C (3.7) Chapter

Settings
I2C1
Settings－879/1293－

ControlCXD5602 User Manual

LPADC

SCU.ADC0x0018dOperationIF

e14

Parameter[3:0]

FIFO_WAT

4'd8

LPADC FIFO Watermark

1'b0

LPADC

ERMARK[5]

Settings

DMA_HS_EN[11:8]

SAMP_RASCU.ADC0x0018dOperationIF

e1c

Parameter[3:0]

FIFO_WAT

Settings-->[11:8]

4'd8

LPADC FIFO Watermark

DMA_HS_

1'b0

LPADC

SAMP_RAOperation

IF

e20

Parameter[3:0]

FIFO_WAT

Settings-->[11:8]

OperationIF

e24

Parameter[3:0]

LPADC FIFO Watermark

DMA_HS_

1'b0

LPADC

SAMP_RAFIFO_WAT

Settings[11:8]-->

Operation

IF

e94

Parameter[4:0]

Settings

4'd8

LPADC FIFO Watermark

DMA_HS_

1'b0

LPADC

SAMP_RAFIFO_WAT[10:8]-->

HPADC0IF

ed4

Operation[4:0]

Parameter

HPADC0 FIFO Watermark

DMA_HS_

1'b0

HPADC0

DECI_RATFIFO_WAT[10:8]

Confirmation

SCU.SCU

0x00195

_REG

020

DMA

signalusage

enable/disable
3'd7

HPADC0 decimation ratio selection(0: bypass, 0: 1/2, -, 7: 1/128)

5'd16

HPADC1 FIFO Watermark

DMA_HS_

1'b0

HPADC1EN

Boot

LPADC sampling ratio selection

5'd16

DECI_RAT[1]

ENABLE_

DMA

signalusage

enable/disable
3'd7

HPADC1 decimation ratio selection(0: bypass, 0: 1/2, -, 7: 1/128)

IO
Sequencer

usage

ERMARK[5]

Settings

signal(0: bypass, 1:1/2, -, 15:1/32768)

IO
0x0018d

DMA

enable/disable

EN

SCU.ADCLPADC sampling ratio selection

ERMARK[5]

HPADC1usage(0: bypass, 1: 1/2, -, 15: 1/32768)

TIO
0x0018dsignalenable/disable

EN

SCU.ADCDMA

ERMARK[5]

HPADC0

LPADC sampling ratio selection

4'd8

TIO
0x0018dusage(0: bypass, 1: 1/2, -, 15: 1/32768)

EN

SCU.ADCsignalERMARK
[5]

LPADC

DMA

enable/disable

TIO
0x0018d

LPADC sampling ratio selection(0: bypass, 1: 1/2, -, 15: 1/32768)

EN

SCU.ADC

usage

ERMARK[5]

LPADC

Signalenable/disable

TIO
LPADC

DMA

(&= 2) != 0

READY

－880/1293－

Confirm that the following bit turns to“1”

CXD5602 User Manual[1]: ENABLE_READY (Read Only)
Setting for whole

SCU.SCU

0x00195

Sequencers

_REG

020

[0]

ENABLE_

1'b1

sequencers operations, which can be

ALL_SEQ

collectively controlled by this bit

operation control
LPADC

Permission/prohibition setting for whole

Data

Output Start

SCU.ADC0x0018d

IF

e18

[3:0]

FIFO_EN

arbitrary

Data output start(Sets “1” in the bit of the required
LPADC)

HPADC0Data

Output Start
HPADC1

Data

Output Start

3.9.13.6.2

SCU.ADC0x0018dIF

e98

SCU.ADC0x0018d

IF

ed8

[0]

DECIFIFO_

1'b1

Data output start

1'b1Data output startEN[0]

DECIFIFO_
EN

Power Supply Control Power OFF
Table SCU (Sensor Control Unit)-749 Output Disable Settings

EventControl

Addressbit

Name

Register

Setting
Value

Descriptions

Location
LPADC Output Disable

SCU.ADCIF

0x0018de18[3:0]

FIFO_EN

4'h0

Refer to Table SCU(SensorControlUnit)-744
HPADC0

OutputSCU.ADCIF

0x0018de98[0]

DECIFIFO_EN

1'b0

Same as above

OutputSCU.ADCIF

0x0018ded8[0]

DECIFIFO_EN

1'b0

Same as above

SCU.SCU_R

0x00195020[0]ENABLE_ALL_SEQ

1'b0

Same as above

---

---

---

---

Waits

DisableHPADC1DisableSequencer Suspend

EG
wait

---

for

sequencer

suspend
Sequencer Reset

TOPREG

0x1028[7]

XRST_SCU_ISOP

1'b0

Refer to Table SCU(Sensor
Unit)-744
LPADC

Operation

SCU.ADCIF

0x0018de00[0]

LV_ADC_EN

1'b0

Same as above

Operation

SCU.ADCIF

0x0018de84[0]

LV_ADC0_EN

1'b0Same as above[1]

LV_ADC0_REF_EN

1'b0

Same as above[2]

LV_LPF0_EN

1'b0Same as above[0]

LV_CLKOUT0_EN

1'b0

Same as above

Suspend
HPADC0
Suspend0x0018de88－881/1293－

ControlCXD5602 User Manual

HPADC1

Operation

SCU.ADCIF

0x0018dec4

Suspend0x0018dec8[0]

LV_ADC1_EN

1'b0

Same as above[1]

LV_ADC1_REF_EN

1'b0

Same as above[2]

LV_LPF1_EN

1'b0

Same as above[0]

LV_CLKOUT1_EN

1'b0

Same as above

For clock control during Power OFF or Power OFF control, refer to the PMU Chapter (3.4).

3.9.13.6.3

Sequencer
Table SCU (Sensor Control Unit)-750 Sequencer Startup Settings

EventControl

Addressbit

Name

Register

Setting

Descriptions

Value

Location
Power Supply

---

---

---

---

---

SRAM power supply
Refer to the PMU
Chapter (3.4)

Sequencer

TOPREG

0x0704[7]

XRST_SCU_ISOP

1'b1

---

---

---

---

---

Reset
FIFO

Refer to Table SCU(SensorInitialization

ControlUnit)-757
START_CTR
L

RelatedSCU.SCU

0x001950---

START_CTRL_COMMON

---

28

Register

0x001950

Settings

2c0x001950---

START_MODE0---

START_MODE10 (e.g.)---

START_INTERVAL3_0---

START_INTERVAL7_4---

START_INTERVAL9_8

3c0x001950

0 (e.g.)

to

Refer

to

---

START_PHASE1_0

0x5432Refer(e.g.)

3.9.12.3.8

0x9876

Refer(e.g.)

3.9.12.3.9

0x0099Refer(e.g.)

3.9.12.3.10

0x00040002

Refer

40
0x001950

Refer

SectionSection

3.9.12.3.7

380x001950

Section

3.9.12.3.6

340x001950

to3.9.12.3.5300x001950

Refer

to

to

to

to

SectionSectionSectionSection

3.9.12.3.11---

START_PHASE3_2

440x00100008

Refer

to

3.9.12.3.12－882/1293－

SectionCXD5602 User Manual

0x001950---

START_PHASE5_4

0x00400020

48
0x001950---

START_PHASE7_6

0x01000080

C

RelatedSCU.SCU

0x001950---

START_PHASE9_8

0x001950

Settings

74
0x001950---

OFST_GAIN_EN

---

---

UNSIGNED_TO_SIGNED

DEC_CLR780x001950

0x01000100---

MATHFUNC_CLR---

DECIMATION_PARAM0---

DECIMATION_PARAM1

880x001950

3.9.12.3.20

0x00000300

Refer(e.g.)

3.9.12.3.210x000000F

Refer

F

3.9.12.3.22

0x00000007

Refer

---

---

---

---

b8

SectionSection

MATHFUNC_SEL

to

3.9.12.3.25

0x0F0F0F0

Refer

0 (e.g.)3.9.12.3.26

0 (e.g.)

Refer

to

to

SectionSectionSection

MATHFUNC_POS00 (e.g.)

Refer

to

Section

MATHFUNC_POS1

0 (e.g.)

Refer

to

Section

MATHFUNC_POS2

0 (e.g.)

Refer

to

Section

3.9.12.3.30---

MATHFUNC_PARAM_0_0

0 (e.g.)

Refer

to

Section

3.9.12.3.31---

MATHFUNC_PARAM_C0_0_0_

0 (e.g.)MSB---

MATHFUNC_PARAM_C0_0_0_L---

0 (e.g.)

MATHFUNC_PARAM_C1_0_0_

0 (e.g.)SectionRefer

toSection

MATHFUNC_PARAM_C1_0_0_L

Refer

to

Section

3.9.12.3.34
0 (e.g.)

SB
---

to

3.9.12.3.33

MSB
---

Refer

3.9.12.3.32

SBb40x001950

Section

3.9.12.3.29

b00x001950

toSection

3.9.12.3.28

a80x001950

Section

3.9.12.3.27

a40x001950

to0 (e.g.)a00x001950

to

Refer

98
0x001950

to0x0F0F0F094
0x001950

to(e.g.)

90
0x001950

Refer

Refer

8c
0x001950

Section

3.9.12.3.23

840x001950

to0x00000311

7c
0x001950

Refer

3.9.12.3.15

70

Register

Section

3.9.12.3.14

50
MATH_PROto

3.9.12.3.13

4c0x001950

Refer

Refer

to

Section

3.9.12.3.35

MATHFUNC_PARAM_C2_0_0_
MSB－883/1293－

0 (e.g.)

Refer

to

3.9.12.3.36

SectionCXD5602 User Manual

0x001950---bc
0x001950

---

---

d8
0x001950

0 (e.g.)---

MATHFUNC_PARAM_C3_0_0_L

0 (e.g.)

MATHFUNC_PARAM_C4_0_0_

0 (e.g.)---

MATHFUNC_PARAM_C4_0_0_L

0 (e.g.)---

MATHFUNC_PARAM_0_1

0 (e.g.)

---

---

---

---

---

---

---

0 (e.g.)

MATHFUNC_PARAM_C1_0_1_L

0 (e.g.)---

MATHFUNC_PARAM_C2_0_1_

0 (e.g.)

14

toSectionRefer

toSectionRefer

toSection

---

Refer

to

SectionRefer

toSectionRefer

toSectionRefer

toSection

MATHFUNC_PARAM_C2_0_1_L

Refer

to

Section

3.9.12.3.47
0 (e.g.)

Refer

to

Section

3.9.12.3.48

MATHFUNC_PARAM_C3_0_1_

0 (e.g.)

MATHFUNC_PARAM_C3_0_1_L

Refer

to

Section

3.9.12.3.49
0 (e.g.)

Refer

to

Section

3.9.12.3.50

MATHFUNC_PARAM_C4_0_1_

0 (e.g.)

MATHFUNC_PARAM_C4_0_1_L

Refer

to

Section

3.9.12.3.51
0 (e.g.)

SB

Refer

to

Section

3.9.12.3.52

MATHFUNC_PARAM_1_0

0 (e.g.)

Refer

to

Section

3.9.12.3.53---

100x001951

Refer

3.9.12.3.46

0c0x001951

Section

3.9.12.3.45MSB

080x001951

MATHFUNC_PARAM_C1_0_1_

SB040x001951

to3.9.12.3.44

MSB00
0x001951

0 (e.g.)SBfc
0x001951

MATHFUNC_PARAM_C0_0_1_L

MSB

f8
0x001950

Refer

3.9.12.3.43SBf40x001950

0 (e.g.)MSB

f00x001950

MATHFUNC_PARAM_C0_0_1_

SBec0x001950

Section

3.9.12.3.41MSB

e80x001950

to3.9.12.3.42

e40x001950

Refer

3.9.12.3.40

e00x001950

Section

3.9.12.3.39

SB
---

to

3.9.12.3.38

MSBdc
0x001950

MATHFUNC_PARAM_C3_0_0_

SB
---

Refer

3.9.12.3.37MSB

d40x001950

0 (e.g.)SB

d00x001950

MATHFUNC_PARAM_C2_0_0_L

MATHFUNC_PARAM_C0_1_0_

0 (e.g.)MSB---

MATHFUNC_PARAM_C0_1_0_L
SB

Refer

to

3.9.12.3.54
0 (e.g.)

Refer

to

3.9.12.3.55－884/1293－

SectionSectionCXD5602 User Manual

0x001951---

180x001951

---

---

---

---

2c
0x001951------

MATHFUNC_PARAM_C2_1_0_L

0 (e.g.)

MATHFUNC_PARAM_C3_1_0_

0 (e.g.)---

MATHFUNC_PARAM_C3_1_0_L

0 (e.g.)---

MATHFUNC_PARAM_C4_1_0_

0 (e.g.)---

MATHFUNC_PARAM_C4_1_0_L

0 (e.g.)---

MATHFUNC_PARAM_1_1

0 (e.g.)

---

---

---

---

60

0 (e.g.)toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSection---

MATHFUNC_PARAM_C1_1_1_

0 (e.g.)toSectionRefer

toSection

MATHFUNC_PARAM_C1_1_1_L

Refer

to

Section

3.9.12.3.67
0 (e.g.)

Refer

to

Section

3.9.12.3.68

MATHFUNC_PARAM_C2_1_1_

0 (e.g.)

MATHFUNC_PARAM_C2_1_1_L

Refer

to

Section

3.9.12.3.69
0 (e.g.)

Refer

to

Section

3.9.12.3.70

MATHFUNC_PARAM_C3_1_1_

0 (e.g.)

MATHFUNC_PARAM_C3_1_1_L

Refer

to

Section

3.9.12.3.71
0 (e.g.)

Refer

to

Section

3.9.12.3.72

MATHFUNC_PARAM_C4_1_1_

0 (e.g.)

MSB
---

Refer

3.9.12.3.66SB5c0x001951

MATHFUNC_PARAM_C0_1_1_L

MSB

58
0x001951

Refer

3.9.12.3.65SB540x001951

0 (e.g.)MSB

500x001951

MATHFUNC_PARAM_C0_1_1_

SB4c0x001951

Section

3.9.12.3.63MSB

480x001951

to3.9.12.3.62SB

440x001951

Refer

3.9.12.3.61

MSB

400x001951

Section

3.9.12.3.64

3c0x001951

to3.9.12.3.60

380x001951

Refer

3.9.12.3.59

SB---

Section

3.9.12.3.58

MSB

34
0x001951

0 (e.g.)SB

300x001951

MATHFUNC_PARAM_C2_1_0_

MSB
---

to

3.9.12.3.57SB

280x001951

0 (e.g.)MSB

240x001951

MATHFUNC_PARAM_C1_1_0_L

Refer

3.9.12.3.56SB

200x001951

0 (e.g.)MSB

1c0x001951

MATHFUNC_PARAM_C1_1_0_

MATHFUNC_PARAM_C4_1_1_L
SB

Refer

to

3.9.12.3.73
0 (e.g.)

Refer

to

3.9.12.3.74－885/1293－

SectionSectionCXD5602 User Manual

0x001951---

MATHFUNC_PARAM_2_0

0 (e.g.)64
0x001951

---

---

---

---

---

---

---

84
0x001951------

MATHFUNC_PARAM_C1_2_0_L

0 (e.g.)

MATHFUNC_PARAM_C2_2_0_

0 (e.g.)---

MATHFUNC_PARAM_C2_2_0_L

0 (e.g.)---

MATHFUNC_PARAM_C3_2_0_

0 (e.g.)---

MATHFUNC_PARAM_C3_2_0_L

0 (e.g.)---

MATHFUNC_PARAM_C4_2_0_

0 (e.g.)---

MATHFUNC_PARAM_C4_2_0_L

0 (e.g.)

ac

Refer

to

SectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSection

3.9.12.3.85

MATHFUNC_PARAM_2_1

0 (e.g.)

MATHFUNC_PARAM_C0_2_1_

0 (e.g.)

Refer

to

Section

MATHFUNC_PARAM_C0_2_1_L---

0 (e.g.)toSectionRefer

toSection

3.9.12.3.88

MATHFUNC_PARAM_C1_2_1_

0 (e.g.)

MATHFUNC_PARAM_C1_2_1_L

Refer

to

Section

3.9.12.3.89
0 (e.g.)

Refer

to

Section

3.9.12.3.90

MATHFUNC_PARAM_C2_2_1_

0 (e.g.)

MATHFUNC_PARAM_C2_2_1_L

Refer

to

Section

3.9.12.3.91
0 (e.g.)

SB
---

Refer

3.9.12.3.87

MSB

a80x001951

Section

3.9.12.3.84

SBa40x001951

to3.9.12.3.83

MSB

a00x001951

Refer

3.9.12.3.82SB9c0x001951

Section

3.9.12.3.81

MSB

980x001951

to3.9.12.3.86

940x001951

Refer

3.9.12.3.80900x001951

Section

3.9.12.3.79

SB
---

to

3.9.12.3.78MSB

8c0x001951

0 (e.g.)SB

880x001951

MATHFUNC_PARAM_C1_2_0_

MSB
---

Refer

3.9.12.3.77SB800x001951

0 (e.g.)MSB

7c0x001951

MATHFUNC_PARAM_C0_2_0_L

SB780x001951

Section

3.9.12.3.76MSB740x001951

0 (e.g.)SB

700x001951

MATHFUNC_PARAM_C0_2_0_MSB6c0x001951

to3.9.12.3.75

680x001951

Refer

Refer

to

Section

3.9.12.3.92

MATHFUNC_PARAM_C3_2_1_
MSB－886/1293－

0 (e.g.)

Refer

to

3.9.12.3.93

SectionCXD5602 User Manual

0x001951---

b00x001951------

MATHFUNC_PARAM_C4_2_1_

0 (e.g.)

MATHFUNC_PARAM_C4_2_1_L

0 (e.g.)

EVENT_PARAM0_THRESH

0 (e.g.)---

EVENT_PARAM0_COUNT00 (e.g.)---

EVENT_PARAM0_COUNT10 (e.g.)---

EVENT_PARAM0_COUNT20 (e.g.)---

EVENT_PARAM1_THRESH

0 (e.g.)---

EVENT_PARAM1_COUNT00 (e.g.)---

EVENT_PARAM1_COUNT10 (e.g.)---

EVENT_PARAM1_COUNT20 (e.g.)---

EVENT_PARAM2_THRESH

0 (e.g.)---

EVENT_PARAM2_COUNT00 (e.g.)---

EVENT_PARAM2_COUNT10 (e.g.)

TOPREG

0x0214toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSectionRefer

toSection

3.9.12.3.107---

EVENT_PARAM2_COUNT20 (e.g.)e8
Power Supply

Refer

3.9.12.3.106e40x001951

Section

3.9.12.3.105

e00x001951

to3.9.12.3.104dc
0x001951

Refer

3.9.12.3.103d80x001951

Section

3.9.12.3.102d40x001951

to3.9.12.3.101d00x001951

Refer

3.9.12.3.100

cc
0x001951

Section

3.9.12.3.99c80x001951

to3.9.12.3.98

c40x001951

Refer

3.9.12.3.97

c00x001951

Section

3.9.12.3.96

bc0x001951

to3.9.12.3.95

SB
---

Refer

3.9.12.3.94MSBb80x001951

0 (e.g.)SBb40x001951

MATHFUNC_PARAM_C3_2_1_L

Refer

to

Section

3.9.12.3.108[5:4]

SCUSEQ

2'd3(Read Only)

Confirmation

optional
Confirms 2'd3of SRAM for
Sequencer
Write
ProgramSCU.SCU

---

---

---

---

to

Writes 8 KBytes ofdata
Refer to Figure SCU

SEQ_IRAM(Sensor－887/1293－

ControlCXD5602 User ManualUnit)-80
Write Setting
and

SCU.SCU

---

---

---

---

InitialValuesWrites 512Byte + α.
For the address, refertotoFigure(SensorSEQ_DRAM

SCU
ControlUnit)-80.
Clock Stop

TOPREG

0x071c[5]

SCU_SEQ

1'b0

Reset Release

TOPREG

0x0704[7]

XRST_SCU_ISOP

1'b1

Clock Supply

TOPREG

0x071c[5]

SCU_SEQ

1'b1

InitialSCU.SPI

---

---

---

---

Settings

for

Refer

to

Section

3.9.13.6.4

SPI
Sequencer
Operation
InitialSCU.I2C0

Settings

---

---

---

---

for

Refer

to

Section

3.9.13.6.5

I2C0
Sequencer
Operation
Initial Setting
for

SCU.I2C1

---

---

---

---

I2C1

Refer

to

Section

3.9.13.6.5

Sequencer
Operation
Boot

SCU.SCU

Completion

0x001950[1]

ENABLE_READY

1'b1(Read Only)

20

optional
Confirms “1'b1”

Wait
Sequencer

SCU.SCU

Startup

0x001950[0]

ENABLE_ALL_SEQ

1'b1

---

---

---

20

LPADC

SCU.ADC

Operation

IF

---

Refer

to

Section

3.9.13.6.6

Start
HPADC0SCU.ADC

Operation

IF

---

---

---

---

Refer

to

Section

3.9.13.6.7

Start
HPADC1

SCU.ADC

Operation

IF

---

---

---

---

Refer

to

3.9.13.6.8

Start－888/1293－

SectionCXD5602 User Manual

Table SCU (Sensor Control Unit)-751 SPI Direct Control from CPU during Sequencer Operation
Event

Control

Addressbit

Name

Register

Setting

Descriptions

ValuesLocation
Inhibit Request

SCU.SCU

0x00195024[0]

SPI_ACCESS_INHIBIT_REQ

1'b1

Request Acceptance

SCU.SCU

0x00195024[8]

SPI_ACCESS_INHIBIT_ACK

1'b1

Confirmation(Read Only)

SPI Register Setting

SPI

Sequencer

Operation

SCU.SPI

SCU.SPI

---

---

---

---

---

---

Confirms that it is“1'b1”

as

Refer to Section

necessary

3.9.13.6.4---

Refer to Section

Initial3.9.13.6.4

Setting
Inhibit

RequestSCU.SCU

0x00195024[0]

SPI_ACCESS_INHIBIT_REQ

1'b0

ReleaseTable SCU (Sensor Control Unit)-752 I2C0 Direct Control from CPU during Sequencer Operation
Event

Control

Addressbit

Name

Register

Setting

Descriptions

ValuesLocation
Inhibit Request

SCU.SCU

0x00195024[1]

I2C0_ACCESS_INHIBIT_REQ

1'b1

Request Acceptance

SCU.SCU

0x00195024[9]

I2C0_ACCESS_INHIBIT_ACK

1'b1

Confirmation
I2C0(Read Only)

Register

SCU.SPI

---

---

---

Setting
I2C0

Sequencer

Operation

SCU.SPI

---

---

---

Confirm that it is“1'b1”

as

Refer to Section

necessary

3.9.13.6.5---

Refer to Section

Initial3.9.13.6.5

Setting
Inhibit

RequestSCU.SCU

0x00195024[1]

I2C0_ACCESS_INHIBIT_REQ

1'b0

ReleaseTable SCU (Sensor Control Unit)-753 I2C1 Direct Control from CPU during Sequencer Operation
Event

Control

Addressbit

Name

Register

Setting

Descriptions

ValuesLocation
Inhibit Request

SCU.SCU

0x00195024[2]

I2C1_ACCESS_INHIBIT_REQ

1'b1

Request Acceptance

SCU.SCU

0x00195024[10]

I2C1_ACCESS_INHIBIT_ACK

1'b1

Confirmation
I2C1

Register(Read Only)
SCU.SPI

---

---

---

－889/1293－

Confirm that it is“1'b1”

as

Refer to SectionCXD5602 User Manual

Setting
I2C1

Sequencer

Operation

SCU.SPI

---

---

---

necessary

3.9.13.6.5---

Refer to Section

Initial3.9.13.6.5

Setting
Inhibit

RequestSCU.SCU

0x00195024[2]

I2C1_ACCESS_INHIBIT_REQ

Release－890/1293－

1'b0

CXD5602 User Manual

3.9.13.6.4

SPI Operation Initial Settings

Refer to the SPI Chapter (3.10).

3.9.13.6.5

I2C Operation Initial Settings

For the I2C0 and I2C1 settings, refer to the I2C Chapter (3.7).

3.9.13.6.6

LPADC Settings

For the control register specifications, also refer to the ADC Chapter (3.21).
Table SCU (Sensor Control Unit)-754 LPADC Operation Initial Settings
Addressbit

Name

Setting

Description

Values0x0018d[3:0]

FIFO_WATERMARK-->LPADC FIFO Watermark

e14

[5]

DMA_HS_EN-->

LPADC DMA signal usage enable/disable[11:8]

SAMP_RATIO-->LPADC sampling ratio selection(0: bypass, 1: 1/2, -, 15: 1/32768)

0x0018d[3:0]

FIFO_WATERMARK-->LPADC FIFO Watermark

e1c

[5]

DMA_HS_EN-->

LPADC DMA signal usage enable/disable[11:8]

SAMP_RATIO-->LPADC sampling ratio selection(0: bypass, 1: 1/2, -, 15: 1/32768)

0x0018d[3:0]

FIFO_WATERMARK-->LPADC FIFO Watermark[5]

DMA_HS_EN-->

LPADC DMA signal usage enable/disable[11:8]

SAMP_RATIO-->LPADC sampling ratio selection

e20(0: bypass, 1: 1/2, -, 15: 1/32768)
0x0018d[3:0]

FIFO_WATERMARK-->LPADC FIFO Watermark

e24

[5]

DMA_HS_EN-->

LPADC DMA signal usage enable/disable[11:8]

SAMP_RATIO-->LPADC sampling ratio selection(0: bypass, 1: 1/2, -, 15: 1/32768)

0x0018d[3:0]

FIFO_EN-->

LPADC FIFO operation enable/disable

e18－891/1293－

CXD5602 User Manual

0x0018d[9:8]

LV_CH_SEL_INV-->ADCH selector for GNSS (set for only the following
operating channels)

e04

2'b00: CH0
2'b01: CH1
2'b10: CH2
2'b11: CH3[2:0]

LV_CH_SEL_MODE-->

LPADC channel switching mode
3'b000: CH0
3'b001: CH1
3'b010: CH2
3'b011: CH3
3'b100: CH0 ==>CH1
3'b101: CH0 ==>CH1==>CH2==>CH3

3.9.13.6.7

HPADC0 Operation Settings

For the control register specifications, refer to the ADC Chapter (3.21).
Table SCU (Sensor Control Unit)-755 HPADC0 Operation Initial Settings
Addressbit

Name

Setting

Descriptions

Values0x0018de94[4:0]

FIFO_WATERMARK-->HPADC0 FIFO Watermark[5]

DMA_HS_EN-->

HPADC0 DMA signal usage enable/disable[10:8]

DECI_RATIO-->

HPADC0 decimation ratio selection(0: bypass, 1: 1/2, -, 7: 1/128)

0x0018de98[0]

DECIFIFO_EN

1

HPADC0Decimation,

FIFO

operation

enable/disable

3.9.13.6.8

HPADC1 Operation Settings

For the control register specifications, refer to the ADC Chapter (3.21).
Table SCU (Sensor Control Unit)-756 HPADC1 Operation Initial Settings
Addressbit

Name

Setting

Descriptions

Values0x0018ded4[4:0]

FIFO_WATERMARK-->HPADC1 FIFO Watermark[5]

DMA_HS_EN-->

HPADC1 DMA signal usage enable/disable[10:8]

DECI_RATIO-->

HPADC1 decimation ratio selection(0: bypass, 1: 1/2, -, 7: 1/128)

0x0018de98[0]

DECIFIFO_EN

1

HPADC1－892/1293－

Decimation,

FIFO

operationCXD5602 User Manualenable/disable－893/1293－

CXD5602 User Manual

3.9.13.6.9

FIFO Settings

For details on the control registers, refer to Section 3.9.12.10.
Table SCU (Sensor Control Unit)-757 FIFO Writing Side Initial Settings
FIFO

Addressbit

Name

Setting

Partitio

Descriptions

ValuesnD0_W00x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

0000

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per samples

0004

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO fullSets {STOP_WRITING, OVER_WRITE}[16]

FIFO_RESET

1

Resets the FIFO writing side

D0_W1

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

0020

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0024

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

D0_W2

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

0040

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0044

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

D0_W3

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

0060

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per samples

0064

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

D1_W00x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

0080

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0084

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

D1_W1

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

00a0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

00a4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full

－894/1293－

CXD5602 User Manual[16]

FIFO_RESET

1

Resets the FIFO writing side

D1_W2

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

00c0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

00c4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

D1_W3

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

_S

00e0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

00e4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N0_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

0100

[15:0]

FIFO_PARTITION_SIZE

Selects the partition start address

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0104

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N1_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

0120

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0124

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N2_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

0140

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0144

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N3_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

0160

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0164

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N4_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

0180

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0184

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N5_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

01a0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

－895/1293－

CXD5602 User Manual

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

01a4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N6_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

01c0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

01c4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

N7_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

S

01e0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

01e4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET

1

Resets the FIFO writing side

V0_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

0200

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0204

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition)

0x00180218

1

Resets the FIFO writing side

This

value

is

added

to

the

LATEST_TIME_STAMP each time writing to
the FIFO_WRITE_REG is performed.
V1_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

0220

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0224

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition).

0x00180238

1

Resets the FIFO writing side

V2_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

0240

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0244

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition).

FIFO_START_OFST

Selects the partition start address

0x00180258
V3_W_

0x0018[31:16]1－896/1293－

Resets the FIFO writing sideCXD5602 User Manual

C

0260

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0264

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIGI full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition)

0x00180278

1

Resets the FIFO writing side

V4_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

0280

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0284

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition)

0x00180298

1

Resets the FIFO writing side

V5_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

02a0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

02a4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition)

0x001802b8

1

Resets the FIFO writing side

V6_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

02c0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

02c4

[4]

OVERWRITE_IF_FULL

Selects the operation during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition)

0x001802d8

1

Resets the FIFO writing side

V7_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

02e0

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

02e4

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition)

0x001802f81

Resets the FIFO writing side

V8_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

0300

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0304

[4]

OVERWRITE_IF_FULL

Selects operation mode during FIFO full

－897/1293－

CXD5602 User Manual

0x0018[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition)

0318

1

Resets the FIFO writing side

V9_W_

0x0018[31:16]

FIFO_START_OFST

Selects the partition start address

C

0320

[15:0]

FIFO_PARTITION_SIZE

Selects the partition size

0x0018[3:0]

FIFO_SAMPLE_SIZE

Selects the number of Bytes per sample

0324

[4]

OVERWRITE_IF_FULL

Selects the operation mode during FIFO full[16]

FIFO_RESET[30:16]

TIME_STAMP_INTERVSets the intervals of FIFO writing (only forALvirtual sensor partition).

0x00180338

1

Resets the FIFO writing side

Table SCU (Sensor Control Unit)-758 FIFO Readout Side Initial Settings
FIFO

Addressbit

Name

Setting

Partition---

Descriptions

Values0x00195400[22:9]ALMOST_FULL

1

Almost Full Interrupt Permission (optional)[9]D0_R1_C[10]D0_R2_C[11]D1_R1_C[12]D1_R2_C[13]N0_R1_C[14]N1_R1_C[15]N2_R1_C[16]N3_R1_C[17]N4_R1_C[18]N5_R1_C[19]N6_R1_C[20]N7_R1_C[21]D0_R3_CH [22]D1_R3_CH---

0x00195420[22:9]

OVER_RUN

1

Enables writing occurrence error interrupt
during Full (optional)
For bit assignment, refer to ALMOST_FULL---

0x00195440[22:9]UNDER_RUN

1

Enables readout occurrence error interrupt
during Empty (optional)
For bit assignment, refer to ALMOST_FULL

D0_R1_

0x00181000[15:0]WATER_MARK

Sets Watermark

C

0x00181004[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal0: disable 1: enable[24]

FIFO_ENABLE

1

Readout side FIFO operation permission
0: disable 1: enable[16]

FIFO_RESET

1

Resets the readout side FIFO

D0_R2_

0x00181020[15:0]WATER_MARK

Sets Watermark

C

0x00181024[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

－898/1293－

CXD5602 User Manual

D1_R1_

0x00181040[15:0]WATER_MARK

Sets Watermark

C

0x00181044[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

D1_R2_

0x00181060[15:0]WATER_MARK

Sets Watermark

C

0x00181064[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N0_R1_

0x00181080[15:0]WATER_MARK

Sets Watermark

C

0x00181084[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N1_R1_

0x001810a0[15:0]WATER_MARK

Sets Watermark

C

0x001810a4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N2_R1_

0x001810c0[15:0]WATER_MARK

Sets Watermark

C

0x001810c4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N3_R1_

0x001810e0[15:0]WATER_MARK

Sets Watermark

C

0x001810e4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N4_R1_

0x00181100[15:0]WATER_MARK

Sets Watermark

C

0x00181104[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N5_R1_

0x00181120[15:0]WATER_MARK

Sets Watermark

C

0x00181124[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal－899/1293－

CXD5602 User Manual[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N6_R1_

0x00181140[15:0]WATER_MARK

Sets Watermark

C

0x00181144[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N7_R1_

0x00181160[15:0]WATER_MARK

Sets Watermark

C

0x00181164[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

D0_R3_

0x00181180[15:0]WATER_MARK

Sets Watermark

CH

0x00181184[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

D1_R3_

0x001811a0[15:0]WATER_MARK

Sets Watermark

CH

0x001811a4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

D0_R0_

0x001811c0[15:0]WATER_MARK

Sets Watermark

H

0x001811c4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

D1_R0_

0x001811e0[15:0]WATER_MARK

Sets Watermark

H

0x001811e4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N0_R0_

0x00181200[15:0]WATER_MARK

Sets Watermark

H

0x00181204[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal

N1_R0_

0x00181220[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

[15:0]WATER_MARK

Sets Watermark－900/1293－

CXD5602 User ManualH

0x00181224[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N2_R0_

0x00181240[15:0]WATER_MARK

Sets Watermark

H

0x00181244[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N3_R0_

0x00181260[15:0]WATER_MARK

Sets Watermark

H

0x00181264[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N4_R0_

0x00181280[15:0]WATER_MARK

Sets Watermark

H

0x00181284[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N5_R0_

0x001812a0[15:0]WATER_MARK

Sets Watermark

H

0x001812a4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N6_R0_

0x001812c0[15:0]WATER_MARK

Sets Watermark

H

0x001812c4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

N7_R0_

0x001812e0[15:0]WATER_MARK

Sets Watermark

H

0x001812e4[25]

FIFO_DMA_ENAB

Sets output permission of DMA handshakeLEsignal

V0_R_H

V1_R_H[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x00181300[15:0]WATER_MARK

0x00181304[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

[15:0]WATER_MARK

0x00181320

Sets Watermark

Sets Watermark－901/1293－

CXD5602 User Manual

0x00181324

V2_R_H

V3_R_H

V4_R_H

V5_R_H

V6_R_H

V7_R_H

V8_R_H

V9_R_H[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x00181340[15:0]WATER_MARK

0x00181344[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x00181360[15:0]WATER_MARK

0x00181364[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x00181380[15:0]WATER_MARK

0x00181384[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x001813a0[15:0]WATER_MARK

0x001813a4[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x001813c0[15:0]WATER_MARK

0x001813c4[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x001813e0[15:0]WATER_MARK

0x001813e4[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x00181400[15:0]WATER_MARK

0x00181404[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

0x00181420[15:0]WATER_MARK

0x00181404[24]

FIFO_ENABLE

1

Readout side FIFO operation permission[16]

FIFO_RESET

1

Resets the readout side FIFO

Sets Watermark

Sets Watermark

Sets Watermark

Sets Watermark

Sets Watermark

Sets Watermark

Sets Watermark

Sets Watermark

Table SCU (Sensor Control Unit)-759 FIFO Write Processing
FIFO

Addressbit

Name

Setting

Partition
V0_W_C

Descriptions

Values0x00180214

0x00180218[31:0][14:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

STAMP_LSB
0x00180208[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

---

---

---

---

－902/1293－

FIFO data writeCXD5602 User Manual

V1_W_C0x00180234

0x00180238[31:0][14:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

STAMP_LSB
0x00180228[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V2_W_C

---

---

---

0x00180254[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

0x00180258[14:0]---FIFO data write

STAMP_LSB
0x00180248[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V3_W_C

---

---

---

0x00180274[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

0x00180278[14:0]---FIFO data write

STAMP_LSB
0x00180268[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V4_W_C

---

---

---

0x00180294[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

0x00180298[14:0]---FIFO data write

STAMP_LSB
0x00180288[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V5_W_C

---

---

---

0x001802b4[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

0x001802b8[14:0]---FIFO data write

STAMP_LSB
0x001802a8[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V6_W_C

---

---

---

---

0x001802d4[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is－903/1293－

FIFO data writeCXD5602 User Manual

0x001802d8[14:0]LATEST_BASE_TIME

optional)

STAMP_LSB
0x001802c8[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V7_W_C

---

---

---

0x001802f4[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

0x001802f8[14:0]---FIFO data write

STAMP_LSB
0x001802e8[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V8_W_C

---

---

---

0x00180314[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

0x00180318[14:0]---FIFO data write

STAMP_LSB
0x00180308[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

V9_W_C

---

---

---

0x00180334[31:0]LATEST_BASE_TIME

Writes the reference time stamp

STAMP_MSB(1st time is mandatory, 2nd time on is

LATEST_BASE_TIME

optional)

0x00180338[14:0]---FIFO data write

STAMP_LSB
0x00180328[3:0]

FIFO_WRITE_PHASE

Confirmation (optional) and readout of thewriting phase

---

---

---

---

FIFO data write

Table SCU (Sensor Control Unit)-760 FIFO Readout Processing
FIFO

Addressbit

Name

Setting

PartitDescriptions

Values

ion
D0_

---

---

---

R1_

0x00181010[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181014[14:0]OLDEST_TIMESTAMP_LSB

0x0018100c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181004[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018100c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)－904/1293－

FIFO data readout
Time stamp readout (optional)

occurrence

factorCXD5602 User Manual

0x00181004[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

D0_

---

R2_

0x00181030[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181034[14:0]OLDEST_TIMESTAMP_LSB

0x0018102c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181024[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018102c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181024

---

---

Time stamp readout (optional)---

occurrence

factor

D1_

---

R1_

0x00181050[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181054[14:0]OLDEST_TIMESTAMP_LSB

0x0018104c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181044[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018104c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181044---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

D1_

---

R2_

0x00181070[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181074[14:0]OLDEST_TIMESTAMP_LSB

0x0018106c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181064[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018106c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181064---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

N0_

---

R1_

0x00181090[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181094[14:0]OLDEST_TIMESTAMP_LSB

0x0018108c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181084[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018108c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181084---

FIFO data readout－905/1293－

FIFO data readout
Time stamp readout (optional)

occurrence

factorCXD5602 User Manual

N1_

---

R1_

0x001810b0[31:0]OLDEST_TIMESTAMP_MSB

C

0x001810b4[14:0]OLDEST_TIMESTAMP_LSB

0x001810ac[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001810a4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001810ac[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001810a4

---

---

Time stamp readout (optional)---

occurrence

factor

N2_

---

R1_

0x001810d0[31:0]OLDEST_TIMESTAMP_MSB

C

0x001810d4[14:0]OLDEST_TIMESTAMP_LSB

0x001810cc[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001810c4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001810cc[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001810c4---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

N3_

---

R1_

0x001810f0[31:0]OLDEST_TIMESTAMP_MSB

C

0x001810f4[14:0]OLDEST_TIMESTAMP_LSB

0x001810ec[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001810e4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001810ec[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001810e4---

FIFO data readout

Time stamp readout (optional)

factor

---R1_

0x00181110[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181114[14:0]OLDEST_TIMESTAMP_LSB

0x0018110c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181104[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018110c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

N5_

---

R1_

0x00181130---

occurrenceN4_0x00181104---

FIFO data readout--[31:0]

FIFO data readout
Time stamp readout (optional)---

OLDEST_TIMESTAMP_MSB－906/1293－

occurrence

FIFO data readout
Time stamp readout (optional)

factorCXD5602 User ManualC

0x00181134[14:0]OLDEST_TIMESTAMP_LSB

0x0018112c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181124[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018112c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181124---

factor

N6_

---

R1_

0x00181150[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181154[14:0]OLDEST_TIMESTAMP_LSB

0x0018114c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181144[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018114c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181144---

occurrenceTime stamp readout (optional)---

occurrence

factor

N7_

---

R1_

0x00181170[31:0]OLDEST_TIMESTAMP_MSB

C

0x00181174[14:0]OLDEST_TIMESTAMP_LSB

0x0018116c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181164[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018116c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181164---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

D0_

---

R3_

0x00181190[31:0]OLDEST_TIMESTAMP_MSB

CH

0x00181194[14:0]OLDEST_TIMESTAMP_LSB

0x0018118c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181184[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018118c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181184---

FIFO data readout

D1_

---

---

R3_

0x001811b0[31:0]OLDEST_TIMESTAMP_MSB

CH

0x001811b4[14:0]OLDEST_TIMESTAMP_LSB

0x001811ac[11:8]

FIFO_READ_PHASE

FIFO data readout
Time stamp readout (optional)---

occurrence

factorFIFO data readout
Time stamp readout (optional)

Readout phase confirmation (optional)－907/1293－

CXD5602 User Manual

0x001811a4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001811ac[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001811a4---

factor

D0_

---

R0_

0x001811d0[31:0]OLDEST_TIMESTAMP_MSB

H

0x001811d4[14:0]OLDEST_TIMESTAMP_LSB

0x001811cc[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001811c4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001811cc[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001811c4---

occurrenceTime stamp readout (optional)---

occurrence

factor

D1_

---

R0_

0x001811f0[31:0]OLDEST_TIMESTAMP_MSB

H

0x001811f4[14:0]OLDEST_TIMESTAMP_LSB

0x001811ec[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001811e4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001811ec[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001811e4---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

N0_

---

R0_

0x00181210[31:0]OLDEST_TIMESTAMP_MSB

H

0x00181214[14:0]OLDEST_TIMESTAMP_LSB

0x0018120c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181204[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018120c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181204---

FIFO data readout---

FIFO data readout
Time stamp readout (optional)---

occurrence

factor

N1_

---

R0_

0x00181230[31:0]OLDEST_TIMESTAMP_MSB

H

0x00181234[14:0]OLDEST_TIMESTAMP_LSB

0x0018122c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181224[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018122c[0]

FIFO_OVER_RUN

Abnormality－908/1293－

FIFO data readout
Time stamp readout (optional)

occurrence

factorCXD5602 User Manual

0x00181224[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

N2_

---

R0_

0x00181250[31:0]OLDEST_TIMESTAMP_MSB

H

0x00181254[14:0]OLDEST_TIMESTAMP_LSB

0x0018124c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181244[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018124c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181244

---

---

Time stamp readout (optional)---

occurrence

factor

N3_

---

R0_

0x00181270[31:0]OLDEST_TIMESTAMP_MSB

H

0x00181274[14:0]OLDEST_TIMESTAMP_LSB

0x0018126c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181264[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018126c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181264---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

N4_

---

R0_

0x00181290[31:0]OLDEST_TIMESTAMP_MSB

H

0x00181294[14:0]OLDEST_TIMESTAMP_LSB

0x0018128c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181284[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018128c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181284---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

N5_

---

R0_

0x001812b0[31:0]OLDEST_TIMESTAMP_MSB

H

0x001812b4[14:0]OLDEST_TIMESTAMP_LSB

0x001812ac[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001812a4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001812ac[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear

0x001812a4---

FIFO data readout－909/1293－

FIFO data readout
Time stamp readout (optional)

occurrence

factorCXD5602 User Manual[1]

FIFO_UNDER_RUN_CLR

N6_

---

R0_

0x001812d0[31:0]OLDEST_TIMESTAMP_MSB

H

0x001812d4[14:0]OLDEST_TIMESTAMP_LSB

0x001812cc[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001812c4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001812cc[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001812c4---(optional)---

Time stamp readout (optional)---

occurrence

factor

N7_

---

R0_

0x001812f0[31:0]OLDEST_TIMESTAMP_MSB

H

0x001812f4[14:0]OLDEST_TIMESTAMP_LSB

0x001812ec[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001812e4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001812ec[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001812e4---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

V0_

---

R_H

0x00181310[31:0]OLDEST_TIMESTAMP_MSB

0x00181314[14:0]OLDEST_TIMESTAMP_LSB

0x0018130c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181304[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018130c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181304---

FIFO data readout

Time stamp readout (optional)

factor---R_H

0x00181330[31:0]OLDEST_TIMESTAMP_MSB

0x00181334[14:0]OLDEST_TIMESTAMP_LSB

0x0018132c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181324[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018132c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

V2_

---

---

---

occurrence

V1_0x00181324---

FIFO data readout

FIFO data readout
Time stamp readout (optional)---－910/1293－

occurrence

FIFO data readout

factorCXD5602 User Manual

R_H

0x00181350[31:0]OLDEST_TIMESTAMP_MSB

0x00181354[14:0]OLDEST_TIMESTAMP_LSB

0x0018134c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181344[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018134c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181344---

occurrence

factor

V3_

---

R_H

0x00181370[31:0]OLDEST_TIMESTAMP_MSB

0x00181374[14:0]OLDEST_TIMESTAMP_LSB

0x0018136c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181364[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018136c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181364---

Time stamp readout (optional)

Time stamp readout (optional)---

occurrence

factor

V4_

---

R_H

0x00181390[31:0]OLDEST_TIMESTAMP_MSB

0x00181394[14:0]OLDEST_TIMESTAMP_LSB

0x0018138c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181384[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018138c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181384---

FIFO data readout

Time stamp readout (optional)---

occurrence

factor

V5_

---

R_H

0x001813b0[31:0]OLDEST_TIMESTAMP_MSB

0x001813b4[14:0]OLDEST_TIMESTAMP_LSB

0x001813ac[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001813a4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001813ac[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001813a4---

FIFO data readout

V6_

---

---

R_H

0x001813d0[31:0]OLDEST_TIMESTAMP_MSB

0x001813d4[14:0]OLDEST_TIMESTAMP_LSB

FIFO data readout
Time stamp readout (optional)---－911/1293－

occurrence

FIFO data readout
Time stamp readout (optional)

factorCXD5602 User Manual

0x001813cc[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001813c4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001813cc[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001813c4---

factor

V7_

---

R_H

0x001813f0[31:0]OLDEST_TIMESTAMP_MSB

0x001813f4[14:0]OLDEST_TIMESTAMP_LSB

0x001813ec[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x001813e4[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x001813ec[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x001813e4---

occurrence---

FIFO data readout
Time stamp readout (optional)

factor

V8_

---

R_H

0x00181410[31:0]OLDEST_TIMESTAMP_MSB

0x00181414[14:0]OLDEST_TIMESTAMP_LSB

0x0018140c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181404[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018140c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181404---

occurrence---

FIFO data readout
Time stamp readout (optional)

factor

V9_

---

R_H

0x00181430[31:0]OLDEST_TIMESTAMP_MSB

0x00181434[14:0]OLDEST_TIMESTAMP_LSB

0x0018142c[11:8]

FIFO_READ_PHASE

Readout phase confirmation (optional)

0x00181424[8]

FIFO_PHASE_RESET

Readout phase reset (optional)

0x0018142c[0]

FIFO_OVER_RUN

Abnormality[1]

FIFO_UNDER_RUN

confirmation (optional)[0]

FIFO_OVER_RUN_CLR

Abnormality occurrence factor clear[1]

FIFO_UNDER_RUN_CLR(optional)

0x00181424---

occurrence

FIFO data readout
Time stamp readout (optional)

occurrence

factorTable SCU (Sensor Control Unit)-761 Transition Process to FIFO (8 KByte) Retention
Control
Register

Addressbit

Name

Setting
ValuesLocation－912/1293－

DescriptionsCXD5602 User Manual

TOPREG

0x0018[1:0]

SCU_FIFO0

1

Table SCU (Sensor Control Unit)-762 Transition Process to FIFO (8 KByte) All ON
Control

Addressbit

Name

Register

Setting

Descriptions

ValuesLocation
TOPREG

0x0018[1:0]

SCU_FIFO0

30x0214[1:0]

SCU_FIFO0---

Status confirmation
11: Normal 10: Prohibited Setting 01: SRAM off 00:
Shut Down

Table SCU (Sensor Control Unit)-763 Transition Process to FIFO (8 KByte) ALL OFF
Control

Addressbit

Name

Setting

Register

Descriptions

ValuesLocation
TOPREG

0x0018[1:0]

SCU_FIFO00

Table SCU (Sensor Control Unit)-764 Transition Process to FIFO (32 KByte) Retention
Control

Addressbit

Name

Setting

Register

Descriptions

ValuesLocation
TOPREG

0x0018[3:2]

SCU_FIFO1

1

Table SCU (Sensor Control Unit)-765 Transition Process to FIFO (8 KByte) All ON
Control

Addressbit

Name

Register

Setting

Descriptions

ValuesLocation
TOPREG

0x0018[3:2]

SCU_FIFO1

3

0x0214[3:2]

SCU_FIFO1---

Status confirmation
11: Normal 10: Prohibited Setting 01: SRAM off 00:
Shut Down

Table SCU (Sensor Control Unit)-766 Transition Process to FIFO (8 KByte) ALL OFF
Control

Addressbit

Name

Register

Setting
ValuesLocation
TOPREG

0x0018[3:2]

SCU_FIFO1

0－913/1293－

DescriptionsCXD5602 User Manual

3.9.14

Error Handling

The following table shows the SCU errors and the way they should be handled
Table SCU (Sensor Control Unit)-767 Errors and their HandlingResource

Cause

Notification Method

How to handle on CPU

SPI

SPI transfer timeout (650240 SCU

EXE_ERR interrupt (1 bit

Check the SPI setting and choose a setting thatclock cycles elapsed when reading

per each sequencer)

does not cause timeout.

A Master On Hold error was returned

EXE_ERR interrupt (1 bit

Check the slave address of the target andfrom the I2C functional block

per each sequencer)

perform the transfer again. The I2C functionalout data from the FIFO)
I2C

block is disabled by the firmware of the SCU
internal sequencer
Sequencer

ADCIF

ADCIF

ADCIF

Withdrawal of the suspend interrupt

Within the SCU_RAM

None. When sample data loss occurs, this canrequest was not in time by the next

SYNCHRO_iSoP2CPU

be known by the time stamp shift.

execution of the MATH_PROC

parameter

The FIFO for the LPADC ch.n within

LPADC_OVER_RUNn

the ADCIF has overflowed(n = 0, ..., 3)

The FIFO for the HPADC ch.n within

HPADCn_OVER_RUN

the ADCIF has overflowed(n = 1, 2)

An abnormal readout from the FIFOADCIF_READ_ERR

None

The FIFO partition D0_Rn has

D0_Rn_C_OVER_RUN

None

overflowed(n= 1, 2)

The FIFO partition D1_Rn has

D1_Rn_C_OVER_RUN

overflowed(n = 1, 2)

The FIFO partition Nn_R1 has

Nn_R1_C_OVER_RUN

overflowed(n = 0, ..., 7)

The FIFO partition Dn_R3 has

Dn_R3_CH_OVER_RUN

overflowed(n = 0, 1)

The FIFO for the LPADC ch.n within

LPADC_UNDER_RUNn

the ADCIF was empty but read out(n = 0, ..., 3)

The FIFO for the HPADC ch.n within

HPADCn_UNDER_RUN

the ADCIF was empty but read out(n = 1, 2)

The FIFO partition D0_Rn was

D0_Rn_C_UNDER_RUN

empty but read out(n = 1, 2)

The FIFO partition D1_Rn was

D1_Rn_C_UNDER_RUN

empty but read out(n = 1, 2)

None

None

within the ADCIF has occurred
ADCIF

ADCIF

ADCIF

ADCIF

ADCIF

ADCIF

ADCIF

ADCIF

－914/1293－

None

None

None

None

None

None

None

CXD5602 User Manual

ADCIF

ADCIF

The FIFO partition Nn_R1 was

Nn_R1_C_UNDER_RUN

empty but read out(n = 0, ..., 7)

The FIFO partition Dn_R3 was

Dn_R3_CH_UNDER_RUN

empty but read out(n = 0, 1)

3.9.153.9.15.1


None

None

Restrictions
Parameter Initialization and Change Timing

Overall SCU_RAM

The SCU_RAM must be initialized before releasing the reset of the internal sequencer.

In general, the parameters within the SCU_RAM can only be changed when the functions of the related
internal sequencers are stopped.

For the restrictions on each parameter, refer to the descriptions in Section 3.9.12.11.


ADC_PROPERTY.*_ENABLE
Set ADC_PROPERTY.*_ENABLE to enable before enabling the *_D2.*_EN within the
SCU_ADCIF_REG.
The SCU_RAM cannot be accessed during SLEEP.

3.9.15.2

Decimation Partition Input Data

The data input to the decimation partition (all paths to the Write FIFOs) must be Calculation Operable Type.
This restriction is the same during FORTH_THROUGH mode and when the decimation ratio is 1.

3.9.15.3

Preprocessing of MATH_PROC

During preprocessing of the MATH_PROC, when the flag to convert from Unsigned to Signed is ON, the input
performs conversion to 2’s complement format as offset binary (the offset is equal to (input value binary
maximum value + 1)/2).
The following table shows conversion examples to 2’s complement format when 4 bits.

－915/1293－

CXD5602 User Manual

Table SCU (Sensor Control Unit)-768 Conversion to 2’s Complement Format (e.g. four bit width)
Decimal

Offset Binary

2's complement(Binary)(Binary)->

Decimal

0

000

1

001

2

010

3

011

4

100

5

101

6

110

7

111

3.9.15.4

MATH_PROC Parameter Dynamic Change

->
->
->
->
->
->
->

100

-4

101

-3

110

-2

111

-1

000

0

001

1

010

2

011

3

Some of the MATH_PROC parameters cannot be dynamically changed (when the data is being input/output
to/from the MATH_PROC corresponding to the parameter change). Update is possible only when the operation of
the corresponding MATH_PROC is suspended (the states other than from when “the data is input to the
MATH_PROC to the completion of preparing the data for output”).
The following shows the registers that cannot be dynamically changed.
Table SCU (Sensor Control Unit)-769 MATH_PROC Registers that cannot be Dynamically Changed
Register

Bit Field

Description

Effect of Changing Dynamically

DEC_CLR

DEC0_COMM

Register Clear of DEC0 integrator

The integrator cannot be reset because the initial state

ON_CLR
DEC1_COMM

of the integrator’s counter is enforced
Register Clear of DEC1 integrator

Same as above

ON_CLR
DECIMAT

N1

Decimation ratio

The decimation ratio cannot be dynamically changed

ION_PAR

FORCE_THR

When set to “1”, regardless of the N1 value,

since the data output is sometimes delayed. Also,

AM0

OUGH1

bypass is enforced with no sample delay

decimation cannot be turned ON from bypass mode.

N2

Decimation ratio

Same as above－916/1293－

CXD5602 User Manual

FORCE_THR

When set to “1”, regardless of the N1 value,

OUGH2

bypass is enforced with no sample delay

N3

Decimation ratio

FORCE_THR

When set to “1”, regardless of the N1 value,

OUGH3

bypass is enforced with no sample delay

DECIMAT

N5

Decimation ratio

The decimation ratio cannot be dynamically changed

ION_PAR

FORCE_THR

When set to “1”, regardless of the N1 value,

since the data output is sometimes delayed. Also,

AM1

OUGH5

bypass is enforced with no sample delay

decimation cannot be turned ON from bypass mode.

N6

Decimation ratio

Same as above

FORCE_THR

When set to “1”, regardless of the N1 value,

OUGH6

bypass is enforced with no sample delay

N7

Decimation ratio

FORCE_THR

When set to “1”, regardless of the N1 value,

OUGH7

bypass is enforced with no sample delay

WID0

The FIFO Partition ID assigned to Math

The MATH_FUNCTION cannot be turned ON

Function 0

dynamically since the calculation results sometimes

MATHFU
NC_SEL

Same as above

Same as above

are not output
MATHF_EN0

Operation permission of Math Function 0

WID1

The FIFO Partition ID assigned to MathSame as above

Function 1
MATHF_EN1

Operation permission of Math Function 1

WID2

The FIFO Partition ID assigned to MathSame as above

Function 2
MATHF_EN2

Operation permission of Math Function 2

The change of parameters that cannot be dynamically changed must be completed during the period that the
MATH_PROC is not operating using SCU-CPU synchronized communication (Section 3.9.9.12).
Also, to change the MATH_PROC settings, the MATH_PROC must be executed at least one more time after once
performing rewrite.

3.9.15.5

Using the Decimation Filter in MATH_PROC processing

The decimation filters (two-stage CIC Filter) that can be used for MATH_PROC processing can be applied tothe sensor data captured by sequencers SEQ0 and SEQ1.

3.9.15.6

Excess Detection of MATH_PROC Processing

Do not enter a negative value into the excess detector. The detection result will be incorrect. Take measures－917/1293－

CXD5602 User Manualsuch as using the MATHFUNC_SEL register (Section 3.9.12.3.27) to perform normalization processing as apreprocess.

3.9.15.7

Caution upon Directly Controlling the I2C Block from the CPU

The I2C block equipped on the SCU requires an idle time from when Enable is set to the time when the internal
state becomes Active. This is done by setting by IC_ENABLE[0] to “1”. During this idle period, master operation
will not begin even when data is written to the IC_DATA_CMD. To avoid this, check TX_EMPTY by readingout the register or stop the functional block (set IC_ENABLE[0] to “0”) after checking whether the
MST_ACTIVITY changes from “0” to “1”. See the following flowchart for the procedures.

Write 0 to
IC_ENABLE todisableDW_apb_i2c

Write 1 to
IC_ENABLE toenableDW_apb_i2c

Program IC_CON register fields as
required:

1. Set IC_SLAVE_DISABLE to 1 Slave disabled
2. Set IC_RESTART_EN to 1 Enable restart mode
3. Set IC_10BITADDR_MASTER to 0 7-bit addressing
4. Set IC_10BITADDR_SLAVE to 0 7-bit addressing
5. Set IC_MAX_SPEED_MODE to 1 Standard mode
6. Set IC_MASTER_MODE to 1 MasterWrite to IC_DATA_CMD to push
Write command and write data
or Read command Tx FIFO

Set address of target
Slave by writing it to TAR

Command is
Write?
Yes

Write to IC_SS_HCNT to
set HIGH period of SCL

TX_EMPTY
interrupt
asserted?

Write to IC_SS_LCNT to
set LOW period of SCL

Yes
Yes

Write to IC_INTR_MASK
to enable all interrupts
Write to IC_RX_TL to set
Rx FIFO threshold level
Write to IC_TX_TL to set
Tx FIFO threshold level

Morecommands tosend?

It is necessary to check MST_ACTIVITY
before stopping the I2C macro.
But if confirmation of the TX_EMPTY interrupt
is omitted,there is a need to comfirm
a transition of 0→1→0 about MST_ACTIVITY.

No

RX_FULL
interrupt
asserted?
Yes

Read
IC_DATA_CMD[7:0] toretrieve received byteNo

Is IC_STATUS[5](MST_ACTIVITY) =0?
Yes

Write 0 to
IC_ENABLE todisableDW_apb_i2c

Figure SCU (Sensor Control Unit)-116 I2C Master Control (Example)

3.9.15.8

Sequencer Startup Delay

When the sequencer is first started up by periodic startup, a delay as much as one cycle of the selected startup
period occurs until the first startup. In the same way, the time stamp also delays.
When the periodic startup by the timer is set to MODE1 and the following equation is “true”, the START_CTRL
block issues an interrupt to the internal sequencer.

－918/1293－

CXD5602 User Manual

ICOUNT2 & (2^ (START_INTEVALn + 1) - 1)==START_PHASEn & (2 ^(START_INTERVALn + 1) - 1)
(n is the sequencer number, n = 0, …, 9)
The ICOUNT2 is a nine bit internal counter that counts up by a clock obtained by frequency dividing(2^PRE_DIVIDER) of 32 kHz clock. This counter is reset when the SEQ_ENABLE_ALL is “0”.
The internal sequencer exits the SLEEP state by an interrupt and executes the processes of each sequencer in order
within the main loop.
Figure SCU (Sensor Control Unit)-117 shows the basic startup timing.
RTC
the lower 9 bits
ICOUNT2

5

6

7

8

0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

SEQ_ENABLE_ALL
SEQ_ENABLE0
PRE_DIVIDER

0START_PHASE0

5START_
INTERVAL03

SEQ_EXE0

Figure SCU (Sensor Control Unit)-117 Basic Startup Timing
Figure SCU (Sensor Control Unit)-118 shows an example of when the startup delays. The delay of sampling
start (Td in the below Figure) cannot be known from the outside (CPU) because it depends on the relation
between the startup timing, the START_PHASEn, and the ICOUNT2.
For example, if startup is performed by START_PHASEn=0 immediately after ICOUNT2 has started counting,the ICOUNT2=0 state has already finished and a startup delay of approximately one cycle occurs.

ICOUNT2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

SEQ_ENABLE_ALL
SEQ_ENABLE0/1/2
SEQ_EXE0(8kHz)(START_INTERVAL0=1,START_PHASE0=1)
SEQ_EXE1(4kHz)(START_INTERVAL1=2,START_PHASE1=1)
SEQ_EXE2(2kHz)(START_INTERVAL2=3,START_PHASE2=1)
TdboottimingFigure SCU (Sensor Control Unit)-118 Delay at Start (Example)－919/1293－

14

15

16

17

18

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3.9.15.9

OLDEST Time Stamp Restriction

The OLDEST time stamp calculated by the hardware has the following restrictions. These restrictions can be
avoided by using the LATEST time stamp.
・When FORCE_THROUGH within the SCU_REG is set to “1” at the Decimation partition, the decimation ratio
must be calculated using “1” but when the decimation ratio of the CIC filter is nine or smaller, that value is used.
・When the XOSC is used at the HPADC, and the sampling frequency is not a power of 2, the time stamp

cannotbe accurately calculated. This is because the corresponding arithmetic circuit within the hardware is comprised ofa bit shift circuit.
・If the One-shot Operation is performed by the sequencer with the same ID as ID assigned for the ADC readout,
the time stamp of the ADC will be incorrect. This is because 0xA must be set in the START_INTERVALn fieldof the START_INTERVAL register within the SCU_REG when using the One-shot Sequencer.

3.9.15.10

Converting the LATEST Time Stamp to the OLDEST Time Stamp

The LATEST_TIMESTAMP can be converted to the OLDEST_TIMESTAMP.
Due to the restrictions of the OLDEST_TIMESTAMP (refer to Section 3.9.15.9), there are cases where you willneed to convert the LATEST_TIMESTAMP to the OLDEST_TIMESTAMP.
This can be done by the following equation.
OLDEST_TIMESTAMP = LATEST_TIMESTAMP - INTERVAL x remaining FIFOs(For the LATEST_TIMESTAMP and the remaining number of data, the ones read out after data transfer are used.
In the case that readout is performed before the transfer, errors will occur due to writing data during thesubsequent data readouts.)
The calculation for INTERVAL will be described later.

The following is an example of pseudo code for LATEST to OLDEST conversion.

3.9.15.11

INTERVAL Calculation Method

The INTERVAL is the value of “How many times data is input to the FIFO per the number of counts of the32768 Hz counter”.
For example, the INTERVAL is 32768/64 = 512 when data sampled at 64 Hz is input as-is. The dimension is“time” and the unit is 1/32768 (seconds).
The INTERVAL is used within the hardware for calculating the OLDEST_TIMESTAMP.

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The following describes how to calculate the INTERVAL, which is necessary to obtain the
OLDEST_TIMESTAMP data by calculating.
LPADC
Obtains the values from the following related registers.


32 kHz frequency division setting of TOPREG: CKDIV_SCU.SCU_U32KL(@0x4E4+TOPREG region)

Channel select mode of SCU_ADCIF: LPADC_A1.LV_CH_SEL_MODE(@0x0204+PWD_SCU region)
Set the SEL_DIV as follows according to the CH_SEL_MODE value (the intermediate parameter used here)In the case of 4 (two channel mode)

SEL_DIV = 1

In the case of 5 (four channel mode)

SEL_DIV = 2

Other

SEL_DIV = 0

32 kHz frequency division setting register of SCU_ADCIFLPADC_D1.SAMP_RATIO(@0x0214 + PWD_SCU region)(for LPADC0)

LPADC_D4.SAMP_RATIO(@0x021C + PWD_SCU region)(for LPADC1)

LPADC_D5.SAMP_RATIO(@0x0220 + PWD_SCU region)(for LPADC2)

LPADC_D6.SAMP_RATIO(@0x0224 + PWD_SCU region)(for LPADC3)

Pick up the decimation ratio of CIC filter within MATH_PROC which is used

DECIMATION_PARAM0. N1 or N2 or N3(0x5084 PWD_SCU region)or

DECIMATION_PARAM0. N4 or N5 or N6(0x5088 PWD_SCU region)

Set this to “0” when not using decimation.
Calculation Equation
Sampling frequency
FREQ_LPADC = 32768/(2^SCU_U32KL)/(2^SAMP_RATIO)/(2^SEL_DIV)/(2^(one of N1 to N6))INTERVAL = 32768/FREQ_LPADC
Calculation Equation
Sampling frequency:
FREQ_LPADC = 32768/(2^SCU_U32KL)/(2^SAMP_RATIO)/(2^SEL_DIV)/(2^(one of N1 to N6))INTERVAL = 32768/FREQ_LPADC

HPADCObtains the values from the following related registers.


32 kHz frequency division setting of TOPREG: CKDIV_SCU.SCU_U32KH(@0x4E4 ＋ TOPREG region)



XOSC frequency division register of SCU_ADCIF, common to the two HPADCs


HPADC_AC0.LV_CLK_XOSC_DIV(@0x0240 + PWD_SCU region)When LV_CLK_XOSC_DIV == 0, XOSC_DIV = 2

When LV_CLK_XOSC_DIV == 1, XOSC_DIV = 3

When LV_CLK_XOSC_DIV == 2, XOSC_DIV = 4－921/1293－

CXD5602 User Manual








When LV_CLK_XOSC_DIV == 3, XOSC_DIV = 6

Sets whether to use XOSC/RCOSC of SCU_ADCIF or 32 kHz input, for each HPADC


HPADC0_A0.LV_CLK_U32_SEL0(@0x0280 + PWD_SCU region)



HPADC1_A0.LV_CLK_U32_SEL1(@0x02C0 + PWD_SCU region)

Decimation ratio of CIC filter, for each HPADC


HPADC0_D1.DECI_RATIO(@0x0294 + PWD_SCU region)



HPADC1_D1.DECI_RATIO(@0x02D4 + PWD_SCU region)

Pick up the decimation ratio of CIC filter within MATH_PROC which is used

DECIMATION_PARAM0. N1 or N2 or N3(0x5084 PWD_SCU region)or

DECIMATION_PARAM0. N4 or N5 or N6(0x5088 PWD_SCU region)

Set this to “0” when not using decimation

Calculation Equation
When LV_CLK_U32_SEL0/1 == 1
Sampling frequency:
FREQ_HPADC = 32768/(2^SCU_U32KH)/(2^DECI_RATIO)/(2^(one of N1 to N6))
When LV_CLK_U32_SEL0/1 == 0
When LV_CLK_OSC_SEL0 == 0 (XOSC is selected)
Sampling frequency:
FREQ_HPADC = XOSC frequency/XOSC_DIV/(2^DECI_RATIO)/4/(2^(one of N1 to N6))
When LV_CLK_OSC_SEL0 == 1 (RCOSC is selected)
Sampling frequency: FREQ_HPADC = RCOSC frequency/(2^DECI_RATIO)/4/(2^(one of N1 to N6))INTERVAL = 32768/FREQ_LPADC
Sequencer
Obtains the values from the following related registers.
Frequency division of 32768 Hz that is common to all sequencers
START_CTRL_COMMON.PRE_DIVIDER(@0x5028 PWD_SCU region)

START_INTERVAL of each sequencer


START_INTERVAL3_0.START_INTERVAL0, or 1, or 2, or 3(@0x5034 PWD_SCU region)



START_INTERVAL7_4.START_INTERVAL4, or 5, or 6, or 7(@0x5038 PWD_SCU region)



START_INTERVAL9_8.START_INTERVAL8, or 9(@0x503c PWD_SCU region)

Decimation ratio of CIC filter within MATH_PROC

DECIMATION_PARAM0.N1, or N2, or N3(0x5084 PWD_SCU region)

DECIMATION_PARAM0.N4, or N5, or N6(0x5088 PWD_SCU region)

Set this to “0” when not using decimation

Calculation Equation－922/1293－

CXD5602 User ManualSampling frequency:
FREQ_SEQ = 32768/(PRE_DIVIDER+1)/(2^START_INTERVAL0, or 1, or 2, or 3, or 4, or 5, or 6, or
7, or 8, or 9)/(2^(one of N1 to N6))INTERVAL = 32768/FREQ_LPADC

3.9.15.12

Time Stamp Fluctuation

The fluctuation of time stamps depends on the execution time of each task. When tasks that were not executedin the main loop are executed, or when tasks that were executed are not executed, the time stamps fluctuate. Table
SCU (Sensor Control Unit)-770 shows the approximate execution times of tasks.
Table SCU (Sensor Control Unit)-770 Approximate Execution Times of Tasks
Task

NumberofProcessing Clocks

Time Stamp Fluctuation
Number

of

32

kHz

counts(1/32768 seconds)
When Main Loop Idles

720

3

HPADC 8 Sample Processing

1550

7

SPI 6 Byte (3-axis sensor) Processing370

2

I2C 6 Byte (3-axis sensor) Processing

1100

5

LPADC 1 Sample Processing

1260

6

(The number of 32 kHz counts is the value when the main clock of the SCU is 8.192 MHz)The following table shows the estimated values of time stamp fluctuation (maximum) when a task’s execution
start time is affected by the presence of a different task. (in this table, the SCU clock is RCOSC 8.192 MHz)
Table SCU (Sensor Control Unit)-771 Time Stamp Fluctuation Estimated Values
Task

Number of Fluctuation Clocks

Time Stamp Fluctuation (maximum)(1/32768 seconds)

HPADC

2737

11

LPADC

3907

16

SPI

3794

16

I2C

4259

18

Figure SCU (Sensor Control Unit)-119 shows a case when fluctuation is caused by the effects of HPADC. In
this example, the fluctuation is approximately 7 (32 kHz count) in Table SCU (Sensor Control Unit)-770. Notethat in the below Figure, the fluctuation of the sequencer start time is not considered.

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CXD5602 User Manual

the case of fetching
HPADC data

HPADC

the case of not
fetching HPADC data

SPI

SPI

I2C0

I2C1

I2C0

I2C1

LPADC

LPADC

the variation oftime stamp for SPI

Figure SCU (Sensor Control Unit)-119 Time Stamp Fluctuation by the Presence/Absence of HPADC Execution

3.9.15.13

Time Stamp Readout Restrictions

The time stamp within the SCU is comprised of MSB 32 bits (the seconds digits) and LSB 15 bits (the seconds
and smaller than seconds digits). However, atomic access is not supported during readout from the APB.
Therefore, when readout is performed by APB access two times, the time stamp readout value may shift by amaximum of ±1 seconds.
Within the hardware, “LSB and MSB, and remaining number of FIFO data update are atomic” is compensated for.
Therefore, the only problem is when update occurs during two bus accesses, which can be avoided by performing
two continuous readouts (four APB accesses).
The following is an example pseudo code of reading out the OLDEST_TIMESTAMP two times. Using thechange of the MSB, the carry of the MSB during the two bus accesses is detected.

Also, the following is an example pseudo code of reading out the LATEST_TIMESTAMP. Using theremaining number of FIFOs (PreAvail/PostAvail), the carry of the MSB during the two readouts is detected. (Inthe readout of the LATEST_TIMESTAMP, the remaining number of FIFOs must be read out for the
LATEST_TIMESTAMP to the OLDEST_TIMESTAMP conversion, and because of this, detection is performedby the readout of the remaining number of FIFOs.)

3.9.15.14

LPADC Sample Decimation Parameter Dynamic Change

When converting the sampling rate using the LPADC sample decimation function within the ADCIF, amaximum delay equal to the [original sampling period of the LPADC analog region] x 32768 will occur when thesampling rate is dynamically changed (with the sampling input of the FIFO inside the ADCIF kept ON) to ahigher rate than the one currently in use.
The sample decimation circuit of the LPADC is controlled by the counter (the output value is cnt_out) which
increments each time data is output from the LPADC.

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The counter operates at a clock of 32 kHz, and countup is performed at the timing that data is output from the
LPADC (the LPADC_DATAEN in Figure SCU (Sensor Control Unit)-120).

When cnt_out == 2^SAMP_RATIO-1, the value of the cnt_out is reset to “0” (comparison is always
performed in 16 bit).



Data is input to the FIFO when cnt_out is reset.



E.g.: When SAMP_RATIO = 2, reset is performed at cnt_out == 3, which results in 0-1-2-3-0-1-2-3-, …, andsampling is performed to the FIFO at a rate of 1/4 (Figure SCU (Sensor Control Unit)-120).

The maximum value of cnt_out is 32767(2^15-1).

Since the SAMP_RATIO is directly connected from the register to the comparator for comparing the countervalue, when the software is changed, it is immediately reflected.

Counter reset is common to all four channels (reset cannot be done on a counter basis).
Dynamic update of the SAMP_RATIO is not considered (the specification is such that parameters are updated

when the internal counter is reset).

cnt_out

0

1

2

1

0

3

2

3

0

1

2

LPADC_DATAEN
2

SAMP_RATIOLPADC_DATAEN_SMP

Figure SCU (Sensor Control Unit)-120 Counter Basic Operation
When a reset of the internal counter is not performed, and the sampling frequency is changed from low to high, alarge delay may occur.
The delay until the first datum can be extracted is as follows:When the first time each channel of LPADC is started up
1/RPOST(RPOST = RPRE) [seconds]

E.g.: When 256 Hz, approximately 3.9 msAfter the LPADC stops, startup with sampling frequency changed, not resetting the LPADC
In the case of sampling frequency change (High => Low) (SAMP_RATIO Low => High)Maximum
1/RPOST[seconds]

Minimum
1/RPOST – 1/RPRE + 1/RADC[seconds]

In the case of sampling frequency change (Low => High) (SAMP_RATIO High => Low)
Minimum
1/RADC[seconds]

Maximum－925/1293－

CXD5602 User Manual

32768/RADC[seconds]

E.g.: when 256 Hz, 128s
Here,
RADC: Sampling rate of LPADC (Hz)RPRE: Sampling rate after decimation before change (Hz)RPOST: Sampling rate after decimation after change (Hz)Also, the possibility of a large delay longer than the sampling period is:
Condition:
Sampling frequency change (Low => High) (SAMP_RATIO High => Low)
The current count value Count value at register change > (2^RPOST-1)
Possibility of occurrence:
1-1/(RPRE/RPOST)

3.9.15.15

HPADC CIC Filter Parameter Dynamic Change

When performing sampling rate conversion using the CIC filter within the ADCIF, a maximum delay equal to
the [original sampling period of the HPADC analog region] x 256 will occur when the sampling rate is
dynamically changed to a higher rate than the one currently in use.
This is because the CIC filter uses the same counter circuit as the sample decimation circuit of the LPADC(Section 3.9.15.14).

3.9.15.16
Decimation Partition Write FIFO and Read FIFO Connection
Combinations
In principle, the Write FIFOs and Read FIFOs of the decimation partition must be connected in a one-to-one
relation as shown in the example in Figure SCU (Sensor Control Unit)-121.
One-to-N connections as shown in Figure SCU (Sensor Control Unit)-122 are functionally capable of realizing
equivalent processing by one-to-one connections but they are normally not used.

SEQ0

SEQ0

D0_W0_S

D0_R0_H

Decimation

D0_W1_S

D0_R1_C

D0_R2_C

Decimation

D0_W2_S

D0_R2_C

D0_R3_CH

Decimation

D0_W3_S

D0_R3_CH

D0_W0_S

D0_R0_H

Decimation

D0_W1_S

D0_R1_C

Decimation

D0_W2_S

Decimation

D0_W3_S

Figure SCU (Sensor Control Unit)-121 1 One-to-One Connection (Example)－926/1293－

CXD5602 User Manual

SEQ0

D0_W0_S

D0_R0_H

Decimation

D0_W1_S

D0_R1_C

Decimation

D0_W2_S

D0_R2_C

Decimation

D0_W3_S

D0_R3_CH

Figure SCU (Sensor Control Unit)-122 One-to-N Connection (Example)

3.9.15.17

One-shot Sequencer Parameter Restrictions

When using the One-shot Sequencer, 0xA must be set in the corresponding START_INTERVALn (n is thesequencer number) fields of the START_INTERVAL3_0, START_INTERVAL7_4, andSTART_INTERVAL9_8 registers within the SCU_REG.
When this setting has been made, the OLDEST_TIMESTAMP cannot be used because its value cannot becorrectly calculated by the sequencer using the same Write FIFO number as the ADC.
(refer to Section 3.9.15.9)
With the One-shot Sequencer, captured data cannot be passed through the MATH_PROC.

3.9.15.18

FIFO Points of Attention

3.9.15.18.1 FIFO Initialization
Initialization of the Write FIFO and Read FIFO have the following restrictions in terms of their order.
Make sure to perform reset (*_R*_*_CTRL1.FIFO_RESET) of the readout side FIFO after initializing thewriting side FIFO.
Before performing reset of the readout side, the initial setting of the Write FIFO must be completed because thehardware uses the reset of the readout side FIFO as the trigger to copy the pointer of the writing side FIFO to thereadout side. Initialization of the writing side FIFO means the below sequences.
Table SCU (Sensor Control Unit)-772 Write FIFO Initialization (excluding virtual partition)
Order

Initialization Process

Register(FIFO_REG)

1

Partition start address selection*_W*_*_CTRL0.START_OFFSET

2

Partition size selection*_W*_*_CTRL0.PARTITION_SIZE

3

Selection of number of bytes per sample*_W*_*_CTRL1.FIFO_SAMPLE_SIZE

4

Selection of operation mode during FIFO full*_W*_*_CTRL1.OVERWRITE_IF_FULL－927/1293－

CXD5602 User Manual

5

FIFO writing side reset*_W*_*_CTRL1.FIFO_RESET

Make the Read FIFO initial settings in the following order.
Table SCU (Sensor Control Unit)-773 Read FIFO Initialization
Order

Initialization Process

Register

1

Watermark setting*_R*_*_CTRL0.WATER_MARK

2

Writing side FIFO reset*_R*_*_CTRL1.FIFO_RESET(Simultaneously)

DMA handshake signal output permission*_R*_*_CTRL1.FIFO_DMA_ENABLE

setting
Readout side FIFO operation permission*_R*_*_CTRL1.FIFO_ENABLE

For FIFO restrictions, also refer to Section 3.9.8.10.

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CXD5602 User Manual

3.9.15.19

Register and SCU_RAM Reading and Writing

When the internal sequencer is in SLEEP, you cannot read or write from/to the control registers or SCU_RAM.
Recover the internal sequencer from SLEEP before reading or writing from/to the control registers or SCU_RAM.

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3.10 SPI
3.10.1

Overview and Features

The SPI of this LSI equips the PrimeCell® Synchronous Serial Port (PL022) from ARM Limited.
The SPI0 and SPI3 offer additional functions to the Chip Select control. For details, refer to the PrimeCell®
Synchronous Serial Port (PL022) Technical Reference Manual.
Features•

Support only Master operation.

•

Programmable clock bit rate and prescale.

•

Separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8 locations deep.

•

Programmable choice of interface operation, SPI, Microwire, or TI synchronous serial.

•

Programmable data frame size from 4 to 16 bits.

•

Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts.

•

Internal loopback test mode available.

•

Support for Direct Memory Access (DMA).

SPI List

SPI0 (Power domain: PWD_SYSIOP_SUB)
Supports only the master mode.
There is only one line of Chip Select.
This is used for data transmit/receive (Tx&Rx mode).



SPI3 (Power domain: PWD_SCU)
Supports only the master mode. Since it has three lines of Chip Select, it can connect a maximum of
three sensors to the SPI bus. SPI is usually controlled from the SCU sequencer. When the SCU
sequencer is not used, communication can be performed via the SPI bus by directly controlling theregisters of the SPI from the SYSCPU. Since control from the sequencer and control from the SYSCPU
are exclusive, they cannot be performed simultaneously.
This is used for data transmit/receive (Tx&Rx mode).



SPI4 (Power domain: PWD_APP_SUB)
Supports only the master mode.
There is only one line of Chip Select.
This is used for data transmit/receive (Tx&Rx mode) or data transmit (Tx mode) only.



SPI5 (Power domain: PWD_APP_SUB)
Supports only the master mode.

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CXD5602 User Manual

There is only one line of Chip Select.
This is used for data transmit/receive (Tx&Rx mode)
Table SPI-774 SPI List
SPI
channel
SPI0

Base Address

Power Domain

Description

0x041AB000

PWD_SYSIOP_SUB

SPI30x0418D000

PWD_SCU

SPI4

0x4E103400

PWD_APP_SUB

SPI5

0x4E103C00

PWD_APP_SUBSPI0 is used to communicate with a general SPI device
from the Application CPU. However, this SPI0 pins are
exclusive with UART1, which is normally used for theserial terminal.
SPI3 is used to communicate with the general SPI devices
like as sensor from the Application CPU.
SPI4 is used to communicate with a general SPI device likeas LCD from the Application CPU.
SPI5 is used to communicate with a general SPI device
from the Application CPU.

Additional functions
The SPI0 and SPI3 offer the following additional functions to the PrimeCell® Synchronous Serial Port (PL022).
Additional functions
Chip Select function (SPI3)
By the addition of two lines of Chip Select signals, one Chip Select signal can be selected from thetotal of three Chip Select signals. The selection of the Chip Select signal is done through exclusive
control.

Switching between the function for fixed-value output and function for control of the PL022
A function has been added to set the Chip Select signal (High/Low) by register control. You canswitch between Chip Select control by the register and Chip Select control by the PL022.
In Chip Select control by the register, the Chip Select does not change every 8 bits or 16 bits
during the communication, and fixed values can be output during the communication.

Transfer Rate
The maximum transfer rate of the SPI is determined by the combination of the clock selected as the clock source(SYSPLL, XOSC, RCOSC, or RTC), the X'tal Oscillator clock, and the voltage mode (High Performance mode/
Low Power mode). The following tables show each combination and the maximum transfer rates.
Table SPI-775 XOSC (26 MHz), High Performance Mode

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CXD5602 User Manual

Clock source
frequency
M Hz
SYSIOP (ck_ahb_gear,ck_com_gear) M Hz
S PI0 S CK(Tx&Rx mode)
M bps
SCU (ck_scu_pre)
M Hz
S PI3 S CK(Tx&Rx mode)
M bps
APP (CK_APP)
M Hz
S PI4 S CK(Tx&Rx mode)
M bps
S PI4 S CK(Tx mode)
M bps
S PI5 S CK(Tx&Rx mode)
M bps

SYSPLL
195.000
156.000
48.75039.00012.1889.750
97.500156.000
9.750
9.750
48.75039.00012.18813.000

XOSC
26.00026.0006.500
13.0006.500
26.00013.00013.00013.000

RCOSC
8.192
8.192
4.096
8.192
4.096
8.192
4.096
4.096
4.096

RTC
0.032768
0.032768
0.016384
0.032768
0.016384
0.032768
0.016384
0.016384
0.016384

RCOSC
8.192
8.192
4.096
8.192
4.096
8.192
4.096
4.096
4.096

RTC
0.032768
0.032768
0.016384
0.032768
0.016384
0.032768
0.016384
0.016384
0.016384

Table SPI-776 XOSC (26 MHz), Low Power Mode
Clock source
frequency
M Hz
SYSIOP (ck_ahb_gear,ck_com_gear) M Hz
S PI0 S CK(Tx&Rx mode)
M bps
SCU (ck_scu_pre)
M Hz
S PI3 S CK(Tx&Rx mode)
M bps
APP (CK_APP)
M Hz
S PI4 S CK(Tx&Rx mode)
M bps
S PI4 S CK(Tx mode)
M bps
S PI5 S CK(Tx&Rx mode)
M bps

3.10.2
3.10.2.1

SYSPLL
195.000
156.000
32.50031.2008.125
7.800
39.00039.000
6.500
6.500
9.750
9.750
6.500
6.500

XOSC
26.00026.0006.500
13.0006.500
26.0006.500
13.0006.500

SPI0
Clock and Reset

Figure SPI-123 shows the clock and reset system diagram of the SPI0.
To access the SPI0 register, supply the clock to the AHB/APB Bus Bridge.

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CXD5602 User Manual

RCOSC

ck_rf_pll_1

RTC_CLK_IN(32.768kHz)XOSC

SYSPLLck_cpu_bus

1/M

ck_co m_gear

CK
GATE

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

SPI0

SSPCLKPCLKnSSPRSTPRESETn

0
1

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4

CKDIV_COM.CK_COM
SYSIOP_SUB_CKEN.SPIMSYSIOP_SUB_CKEN.COM_BRG

CK
GATE

1/M

1/M

ck_ahb_gear

CK
GATE

CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_BRG_COMIF
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
SWRESET_BUS.XRST_SPIM

Figure SPI-123 SPI0 Clock and Reset System

3.10.2.2

Clock Supply Start and Stop

3.10.2.2.1

Clock Supply Start

Perform the following control to start supplying the SSPCLK clock and PCLK clock to the SPI0.
1. Clock supply start to the AHB/APB Bus Bridge
SYSIOP_SUB_CKEN.COM_BRG = 1'b1
SYSIOP_SUB_CKEN.AHB_BRG_COMIF = 1'b1
2. Reset release
SWRESET_BUS.XRST_SPIM=1'b1
3. Clock supply start
SYSIOP_SUB_CKEN.SPIM=1'b1

3.10.2.2.2

Clock Supply Stop

Perform the following control to stop supplying the SSPCLK clock and PCLK clock to the SPI0.
1. Clock supply stop
SYSIOP_SUB_CKEN.SPIM=1'b0

3.10.33.10.3.1

SPI3
Clock and Reset－933/1293－

AHB/APB
BusBridge

CXD5602 User Manual

Figure SPI-124 shows the clock and reset system diagram of the SPI3.
When accessing the SPI3 register, set SCU_CKEN.SCU=1'b1 beforehand.

RCOSC
RTC_CLK_IN(32.768kHz)

1/250

0
1

0
1
2
3

Reserved

CKSEL_SCU.SEL_SCU_32K

ck_scu_pre

SCU_CKEN.SCU_SPI

CK
GATE

SPI3

SSPCLKPCLKnSSPRSTPRESETn

XOSC

1/2
1/3
1/4

0
1
2
3

CKSEL_SCU.SEL_SCU_XTALCKSEL_SCU.SEL_SCU

PWD_RESET0.PWD_SCU
SWRESET_SCU.XRST_SCU_SPI

Figure SPI-124 SPI3 Clock and Reset System

3.10.3.2

Clock Supply Start and Stop

3.10.3.2.1

Clock Supply Start

Perform the following control to start supplying the SSPCLK clock and PCLK clock to the SPI3.
1. Reset release
SWRESET_SCU.XRST_SCU_SPI=1'b1
2. Clock supply start
SCU_CKEN.SCU_SPI=1'b1

3.10.3.2.2

Clock Supply Stop

Perform the following control to stop supplying the SSPCLK clock and PCLK clock to the SPI3.
1. Clock supply stop
SCU_CKEN.SCU_SPI=1'b0

3.10.43.10.4.1

SPI4
Clock and Reset

Figure SPI-125 shows the clock and reset system diagram of the SPI4.

－934/1293－

CXD5602 User Manual

RCOSC
RTC_CLK_IN(32.768kHz)SYSPLL

0
1
2
3

XOSC

CK_APP

N/M

CK
GATE

GEAR_AHB.gear_m_ahb
GEAR_AHB.gear_n_ahb
CK_GATE_AHB.ck_gate_img

0
1
2
3

1/2
1/3
1/4
1/5

CK
GATE

1/M

0
1

SPI4

CK
GATE

SSPCLK
PCLK

GEAR_IMG_SPI.gear_m_spi
GEAR_IMG_SPI.gear_n_spi

APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP

nSSPRSTPRESETn

1/M

SPI5

CK
GATE

SSPCLK
PCLK

GEAR_IMG_WSPI.gear_m_img_wspi
GEAR_IMG_WSPI.gear_n_img_wspi

nSSPRSTPRESETn

1/M

UART2

CK
GATE

UARTCLK
PCLK

GEAR_IMG_UART.gear_m_uart
GEAR_IMG_UART.gear_n_uart

Figure SPI-125 SPI4 Clock and Reset System

3.10.4.2

Clock Supply Start and Stop

3.10.4.2.1

Clock Supply Start

Perform the following control to start supplying the SSPCLK clock and PCLK clock to the SPI4.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_img=1'b1
2. Supply the CK_APP (For details, refer to the APP Section (3.13))
3. Clock supply for the SPI4 register and division ratio setting
GEAR_AHB.gear_m_ahb=(arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb=(arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_img=1'b1
4. SPI4 control clock supply and division ratio setting
GEAR_IMG_SPI.gear_m_spi=(arbitrary: denominator setting of the division ratio)
GEAR_IMG_SPI.gear_n_spi=1'b1

3.10.4.2.2

Clock Supply Stop

Perform the following control to stop supplying the SSPCLK clock and PCLK clock to the SPI4.
1. SPI4 control clock stop
GEAR_IMG_SPI.gear_n_spi=1'b0
2. SPI4 register’s clock stop
CK_GATE_AHB.ck_gate_img=1'b0－935/1293－

PRESETn

IMG_RST_X

RESET.xrs_img
PWD_RESET0.PWD_APPnUARTRSTCXD5602 User Manual

3.10.53.10.5.1

SPI5
Clock and Reset

Figure SPI-126 shows the clock and reset system diagram of the SPI5.
RCOSC
XOSC

RTC_CLK_IN(32.768kHz)SYSPLLCKGATE

CK_APP

N/M

CK
GATE

GEAR_AHB.gear_m_ahb
GEAR_AHB.gear_n_ahb
CK_GATE_AHB.ck_gate_img

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

1/M

0
1

SPI4

CK
GATE

SSPCLK
PCLK

GEAR_IMG_SPI.gear_m_spi
GEAR_IMG_SPI.gear_n_spi

APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP

nSSPRSTPRESETn

1/M

SPI5

CK
GATE

SSPCLK
PCLK

GEAR_IMG_WSPI.gear_m_img_wspi
GEAR_IMG_WSPI.gear_n_img_wspi

nSSPRSTPRESETn

1/M

UART2

CK
GATE

UARTCLK
PCLK

GEAR_IMG_UART.gear_m_uart
GEAR_IMG_UART.gear_n_uart

Figure SPI-126 SPI5 Clock and Reset System

3.10.5.2

Clock Supply Start and Stop

3.10.5.2.1

Clock Supply Start

Perform the following control to start supplying the SSPCLK clock and PCLK clock to the SPI5.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_img=1'b1
2. Supply the CK_APP (For details, refer to the APP Section (3.13))
3. Clock supply for SPI5 register and division ratio setting
GEAR_AHB.gear_m_ahb=(arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb=(arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_img=1'b1
4. SPI5 control clock supply and division ratio setting
GEAR_IMG_WSPI.gear_m_wspi=(arbitrary: denominator setting of the division ratio)
GEAR_IMG_WSPI.gear_n_wspi=1'b1－936/1293－

PRESETn

IMG_RST_X

RESET.xrs_img
PWD_RESET0.PWD_APPnUARTRSTCXD5602 User Manual

3.10.5.2.2

Clock Supply Stop

Perform the following control to stop supplying the SSPCLK clock and PCLK clock to the SPI5.
1. SPI5 control clock stop
GEAR_IMG_WSPI.gear_n_wspi=1'b0
2. SPI5 register’s clock stop
CK_GATE_AHB.ck_gate_img=1'b0

3.10.6

List of Registers

3.10.6.1

Register Map

OffsetName

Description

0x000

SSPCR0Control register0

0x004

SSPCR1

Control register1

0x008

SSPDR

Data register

0x00C

SSPSR

Status register

0x010

SSPCPSRClock prescale register

0x014

SSPIMSCInterrupt mask set or clear register

0x018

SSPRIS

Raw interrupt status register

0x01C

SSPMIS

Masked interrupt status register

0x020

SSPICRInterrupt clear register

0x024

SSPDMACRDMA control register

0x090

CS_MODE

Chip Select (Only for SPI0 and SPI3)

0x094

SSP_CS

Chip Select setting (Only for SPI0 and SPI3)0x98

SLAVE_TYPE

Chip Select selection (Only for SPI3)

3.10.6.2

Registers and Field Descriptions

3.10.6.2.1

SSPCR0 (0x000)

Description: SSPCR0 is control register 0 and contains five bit fields that control various functions within thePrimeCell SSP.

The SSPCR0 register is used to:•program the serial clock rate•

select one of the three protocols•

select the data word size, where applicable.

The Serial Clock Rate (SCR) value, in conjunction with the SSPCPSR clock prescale divisor value, CPSDVSR, is－937/1293－

CXD5602 User Manualused to derive the PrimeCell SSP transmit and receive bit rate from the external SSPCLK.
The frame format is programmed through the FRF bits, and the data word size through the DSS bits.
Bit phase and polarity, applicable to Motorola SPI format only, are programmed through the SPH and SPO bits.
Table SPI-777 SSPCR0 Register
Bit Field

Type

Bit

InitialDescription

SCR

R/W

[15:8]

0

Serial clock rate. The value SCR is used to generate the transmit and receive
bit rate of the PrimeCell SSP. The bit rate is:
FSSPCLK / {CPSDVR x (1+SCR)}

SPH

R/W

[7:7]

0

where CPSDVSR is an even value from 2-254, programmed through the
SSPCPSR register and SCR is a value from 0-255.
SSPCLKOUT phase, applicable to Motorola SPI frame format only.

SPO

R/W

[6:6]

0

SSPCLKOUT polarity, applicable to Motorola SPI frame format only.

FRF

R/W

[5:4]

0

Frame format:
00
Motorola SPI frame format.
01
TI synchronous serial frame format.
10
National Microwire frame format.
11
Reserved, undefined operation.

DSS

R/W

[3:0]

0

Data Size Select:
0000

Reserved, undefined operation.

0001

Reserved, undefined operation.

0010

Reserved, undefined operation.

0011

4-bit data.

0100

5-bit data.

0101

6-bit data.

0110

7-bit data.

0111

8-bit data.

1000

9-bit data.

1001

10-bit data.

1010

11-bit data.

1011

12-bit data.

1100

13-bit data.

1101

14-bit data.

1110

15-bit data.

1111

16-bit data.

Bit rate generation
The serial bit rate is derived by dividing down the input clock, SSPCLK. The clock is first divided by an evenprescale value CPSDVSR in the range 2-254, and is programmed in SSPCPSR. The clock is divided again by avalue in the range 1-256, that is 1 + SCR, where SCR is the value programmed in SSPCR0.
The following equation defines the frequency of the output signal bit clock, SSPCLKOUT:FSSPCLKFSSPCLKOUT =CPSDVR x (1+SCR)－938/1293－

CXD5602 User ManualFor example, if SSPCLK is 3.6864MHz, and CPSDVSR = 2, then SSPCLKOUT has a frequency range from
7.2kHz-1.8432MHz.
Motorola SPI frame format
The Motorola SPI interface is a four-wire interface where the SSPFSSOUT signal behaves as a slave select. The
main feature of the Motorola SPI format is that you can program the inactive state and phase of the SSPCLKOUT
signal using the SPO and SPH bits of the SSPSCR0 control register.
•

SPO, clock polarity
When the SPO clock polarity control bit is LOW, it produces a steady state LOW value on the SSPCLKOUT
pin. If the SPO clock polarity control bit is HIGH, a steady state HIGH value is placed on the SSPCLKOUT
pin when data is not being transferred.

•

SPH, clock phase
The SPH control bit selects the clock edge that captures data and enables it to change state. It has the mostimpact on the first bit transmitted by either permitting or not permitting a clock transition before the first data
capture edge.
When the SPH phase control bit is LOW, data is captured on the first clock edge transition.
When the SPH clock phase control bit is HIGH, data is captured on the second clock edge transition.

Motorola SPI Format with SPO=0, SPH=0 (Mode0)This figure shows a single transmission signal sequence for Motorola SPI frame format with SPO=0, SPH=0.

Figure SPI-127 Mode0, single transfer
This figure shows a continuous transmission signal sequence for Motorola SPI frame format with SPO=0, SPH=0.

Figure SPI-128 Mode0, continuous transfer－939/1293－

CXD5602 User Manual

In this configuration, during idle periods:•

the SSPCLKOUT signal is forced LOW•

the SSPFSSOUT signal is forced HIGH•

the transmit data line SSPTXD is arbitrarily forced LOW•

the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance•

when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the
SSPCLKOUT pad, active-LOW enable•

when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the
SSPCLKOUT pad, active-LOW enable.

If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission issignified by the SSPFSSOUT master signal being driven LOW. This causes slave data to be enabled onto the
SSPRXD input line of the master. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad.
One half SSPCLKOUT period later, valid master data is transferred to the SSPTXD pin. Now that both the masterand slave data have been set, the SSPCLKOUT master clock pin goes HIGH after one additional half
SSPCLKOUT period.
The data is now captured on the rising and propagated on the falling edges of the SSPCLKOUT signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the SSPFSSOUT
line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must be pulsed HIGH
between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral
register and does not permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the
SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period
after the last bit has been captured.
Motorola SPI Format with SPO=0, SPH=1 (Mode1)
This figure shows the transfer signal sequence for Motorola SPI format with SPO=0, SPH=1, and it covers both
single and continuous transfers.

Figure SPI-129 Mode1, single and continuous transfers
In this configuration, during idle periods:•

the SSPCLKOUT signal is forced LOW－940/1293－

CXD5602 User Manual•

The SSPFSSOUT signal is forced HIGH•

the transmit data line SSPTXD is arbitrarily forced LOW•

the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance•

when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the
SSPCLKOUT pad, active-LOW enable•

when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the
SSPCLKOUT pad, active-LOW enable.

If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission issignified by the SSPFSSOUT master signal being driven LOW. The nSSPOE line is driven LOW, enabling themaster SSPTXD output pad. After an additional one half SSPCLKOUT period, both master and slave valid data isenabled onto their respective transmission lines. At the same time, the SSPCLKOUT is enabled with a rising edgetransition.
Data is then captured on the falling edges and propagated on the rising edges of the SSPCLKOUT signal.
In the case of a single word transfer, after all bits have been transferred, the SSPFSSOUT line is returned to its
idle HIGH state one SSPCLKOUT period after the last bit has been captured.
For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive data words andtermination is the same as that of the single word transfer.
Motorola SPI Format with SPO=1, SPH=0 (Mode2)
This figure shows a single transmission signal sequence for Motorola SPI format with SPO=1, SPH=0.

Figure SPI-130 Mode2, single transfer
This figure shows a continuous transmission signal sequence for Motorola SPI format with SPO=1, SPH=0.

Figure SPI-131 Mode2, continuous transfer－941/1293－

CXD5602 User Manual

In this configuration, during idle periods:•

the SSPCLKOUT signal is forced HIGH•

the SSPFSSOUT signal is forced HIGH•

the transmit data line SSPTXD is arbitrarily forced LOW•

the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance•

when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the
SSPCLKOUT pad, active-LOW enable•

when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the
SSPCLKOUT pad, active-LOW enable.

If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission issignified by the SSPFSSOUT master signal being driven LOW, and this causes slave data to be immediatelytransferred onto the SSPRXD line of the master. The nSSPOE line is driven LOW, enabling the master SSPTXD
output pad.
One half period later, valid master data is transferred to the SSPTXD line. Now that both the master and slave data
have been set, the SSPCLKOUT master clock pin becomes LOW after one additional half SSPCLKOUT period.
This means that data is captured on the falling edges and be propagated on the rising edges of the SSPCLKOUT
signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSPFSSOUT line isreturned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must be pulsed HIGH
between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral
register and does not permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the
SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period
after the last bit has been captured.
Motorola SPI Format with SPO=1, SPH=1 (Mode3)
This figure shows the transfer signal sequence for Motorola SPI format with SPO=1, SPH=1, and it covers both
single and continuous transfers.

Figure SPI-132 Mode3, single and continuous transfers－942/1293－

CXD5602 User Manual

In this configuration, during idle periods:•

the SSPCLKOUT signal is forced HIGH•

the SSPFSSOUT signal is forced HIGH•

the transmit data line SSPTXD is arbitrarily forced LOW•

the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance•

when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the
SSPCLKOUT pad, active-LOW enable•

when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the
SSPCLKOUT pad, active-LOW enable.

If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission issignified by the SSPFSSOUT master signal being driven LOW. The nSSPOE line is driven LOW, enabling themaster SSPTXD output pad. After an additional one half SSPCLKOUT period, both master and slave data areenabled onto their respective transmission lines. At the same time, the SSPCLKOUT is enabled with a fallingedge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSPCLKOUT
signal.
After all bits have been transferred, in the case of a single word transmission, the SSPFSSOUT line is returned to
its idle HIGH state one SSPCLKOUT period after the last bit has been captured.
For continuous back-to-back transmissions, the SSPFSSOUT pin remains in its active-LOW state, until the final
bit of the last word has been captured, and then returns to its idle state as the previous section describes.
For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive data words andtermination is the same as that of the single word transfer.

3.10.6.2.2

SSPCR1 (0x004)

Description: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions
within the PrimeCell SSP.

The SSPCR1 register is used to:•

select master or slave mode•

enable a loop back test feature•enable the PrimeCell SSP peripheral.

To configure the PrimeCell SSP as a master, clear the SSPCR1 register master or slave selection bit, MS, to 0.
This is the default value on reset.
Setting the SSPCR1 register MS bit to 1 configures the PrimeCell SSP as a slave. When configured as a slave,enabling or disabling of the PrimeCell SSP SSPTXD signal is provided through the SSPCR1 slave mode SSPTXD
output disable bit, SOD. You can use this in some multi-slave environments where masters might parallel
broadcast.
To enable the operation of the PrimeCell SSP, set the Synchronous Serial Port Enable (SSE) bit to 1.
Table SPI-778 SSPCR1 Register－943/1293－

CXD5602 User Manual

Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:4]-

Reserved

SOD

R/W

[3:3]

0

Slave-mode output disable. This bit is relevant only in the slave mode, MS=1.
In multiple-slave systems, it is possible for an PrimeCell SSP master tobroadcast a message to all slaves in the system while ensuring that only one
slave drives data onto its serial output line. In such systems the RXD lines
from multiple slaves could be tied together.
To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave
is not supposed to drive the SSPTXD line:
0

SSP can drive the SSPTXD output in slave mode.
1

mode.
MS

R/W

[2:2]

0

SSP must not drive the SSPTXD output in slave

Master or slave mode select.
This bit can be modified only when the PrimeCell SSP is disabled, SSE=0:0

Device configured as master, default.
1

SSE

R/W

[1:1]

0

Synchronous serial port enable:
0

SSP operation disabled.
1

LBM

R/W

[0:0]

Device configured as slave.

0

SSP operation enabled.

Loop back mode:0

Normal serial port operation enabled.
1
Output of transmit serial shifter is connected to inputof receive serial shifter internally.

3.10.6.2.3

SSPDR (0x008)

Description: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO,
pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic
from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write
pointer.
When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are
removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter,then serially shifted out onto the SSPTXD pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The
transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive
buffer.

Table SPI-779 SSPDR Register
Bit Field

Type

Bit

InitialDescription－944/1293－

CXD5602 User Manual

DATA

R/W

[15:0]-

Transmit/Receive FIFO:
Read

Receive FIFO.

WriteTransmit FIFO.

You must right-justify data when the PrimeCell SSP is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by transmit
logic. The receive logic automatically right-justifies.

3.10.6.2.4

SSPSR (0x00C)

Description: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP
busy status.

Table SPI-780 SSPSR Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:5]-

Reserved

BSY

RO

[4:4]

0

PrimeCell SSP busy flag, RO:0

SSP is idle.
1
SSP is currently transmitting and/or receiving a frameor the transmit FIFO is not empty.

RFF

RO

[3:3]

0

Receive FIFO full, RO:
0

Receive FIFO is not full.
1

RNE

RO

[2:2]

0

Receive FIFO not empty, RO:
0

Receive FIFO is empty.
1

TNF

RO

[1:1]

1

Transmit FIFO is full.
1

3.10.6.2.5

RO

[0:0]

Receive FIFO is not empty.

Transmit FIFO not full, RO:
0

TFE

Receive FIFO is full.

1

Transmit FIFO is not full.

Transmit FIFO empty, RO:
0

Transmit FIFO is not empty.

1

Transmit FIFO is empty.

SSPCPSR (0x010)

Description: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK
must be internally divided before further use.
The value programmed into this register must be an even number between 2-254. The least significant bit of the
programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this registerhas the least significant bit as zero.

Table SPI-781 SSPCPSR Register
Bit Field

Type

Bit

InitialDescription－945/1293－

CXD5602 User Manual

Reserved

N/A[15:8]-

Reserved

CPSDVSR

R/W

[7:0]

0

Clock prescale divisor. Must be an even number from 2-254, depending on
the frequency of SSPCLK. The least significant bit always returns zero on
reads.

3.10.6.2.6

SSPIMSC (0x014)

Description: The SSPIMSC register is the interrupt mask set or clear register.
On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets
the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask.

Table SPI-782 SSPIMSC Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:4]-

Reserved

TXIM

R/W

[3:3]

0

Transmit FIFO interrupt mask:

RXIM

R/W

[2:2]

0

0

Transmit FIFO half empty or less condition interrupt is masked.

1

Transmit FIFO half empty or less condition interrupt is notmasked.

Receive FIFO interrupt mask:
Receive FIFO half full or less condition interrupt is masked.

01
Receive FIFO half full or less condition interrupt is
not masked.

RTIM

RORIM

3.10.6.2.7

R/W

R/W

[1:1]

[0:0]

0

Receive timeout interrupt mask:

00Receive FIFO not empty and no read prior to timeout periodinterrupt is masked.

1

Receive FIFO not empty and no read prior to timeout periodinterrupt is not masked.

Receive overrun interrupt mask:
0

Receive FIFO written to while full condition interrupt is masked.

1

Receive FIFO written to while full condition interrupt is notmasked.

SSPRIS (0x018)

Description: The SSPRIS register is the raw interrupt status register.
On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has noeffect.

Table SPI-783 SSPRIS Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:4]-

Reserved

TXRIS

RO

[3:3]

1

Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt

RXRIS

RO

[2:2]

0

Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt

RTRIS

RO

[1:1]

0

Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt－946/1293－

CXD5602 User Manual

RORRIS

RO

[0:0]

0

3.10.6.2.8

SSPMIS (0x01C)

Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt

Description: The SSPMIS register is the masked interrupt status register. On a read this register gives the current
masked status value of the corresponding interrupt. A write has no effect.

Table SPI-784 SSPMIS Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:4]-

Reserved

TXMIS

RO

[3:3]

0

Gives the transmit FIFO masked interrupt state, after masking, of the
SSPTXINTR interrupt

RXMIS

RO

[2:2]

0

Gives the receive FIFO masked interrupt state, after masking, of the
SSPRXINTR interrupt

RTMIS

RO

[1:1]

0

Gives the receive timeout masked interrupt state, after masking, of the
SSPRTINTR interrupt

RORMIS

RO

[0:0]

0

Gives the receive over run masked interrupt status, after masking, of the
SSPRORINTR interrupt

3.10.6.2.9

SSPICR (0x020)

Description: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding
interrupt is cleared. A write of 0 has no effect.

Table SPI-785 SSICR Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:2]-

Reserved

RTIC

WO

[1:1]

-

Clears the SSPRTINTR interrupt

RORIC

WO

[0:0]

-

Clears the SSPRORINTR interrupt

3.10.6.2.10

SSPIDMACR (0x024)

Description: The SSPDMACR register is the DMA control register.
Table SPI-786 SSPIDMACR Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:2]-

Reserved

TXDMAE

R/W

[1:1]

0

Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO isenabled.

RXDMAE

R/W

[0:0]

0

Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO isenabled.

－947/1293－

CXD5602 User Manual

3.10.6.2.11

CS_MODE (0x090)

Description: The CS_MODE is the register for switching Chip Select (CS) control.
This is supported only for SPI0 and SPI3.
Table SPI-787 CS_MODE Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:1]-

Reserved

cs_mode

R/W

[0:0]

0

Chip Select (CS)

3.10.6.2.12

0

CS is automaticaly controlled by PL022

1

CS is manually controlled by SSP_CS register.

SSP_CS (0x094)

Description: The SSP_CS register is the Chip Select (CS) control register.
This is supported only for SPI0 and SPI3.
Table SPI-788 SSP_CS Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:1]-

Reserved

ssp_cs

R/W

[0:0]

0

Chip Select setting

3.10.6.2.13

0

SPI communication active

1

SPI communication inactive

SLAVE_TYPE (0x098)

Description: The SLAVE_TYPE register determines the Chip Select (CS) pin.
This is supported only for SPI3.

Table SPI-789 SLAVE_TYPE Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:2]-

Reserved

slave_type

R/W

[1:0]

0

Chip Select setting
0

SPI3_CS0_X

1

SPI3_CS1_X

2

SPI3_CS2_X

3

SPI3_CS0_X－948/1293－

CXD5602 User Manual

3.11 UART
3.11.1

Overview and Features

The UART of this LSI equips the PrimeCell® UART (PL011) from ARM Limited.
It has an independent transmitter and independent receiver built in and allows full-duplex transmission. There isalso a dedicated baud rate generator built in, which enables transmissions of a wide range of baud rates. For
details, refer to the PrimeCell® UART (PL011) Technical Reference Manual.
Features

Separate 32×8 transmit and 32×12 receive First-In, First-Out (FIFO) memory buffers to reduce CPUinterrupts.

Programmable FIFO disabling for 1-byte depth.

Programmable baud rate generator. This enables division of the reference clock by (1×16) to (65535×16) andgenerates an internal ×16 clock. The divisor can be a fractional number enabling you to use any clock with afrequency >3.6864MHz as the reference clock.

Standard asynchronous communication bits (start, stop and parity). These are added prior to transmission andremoved on reception.



Independent masking of transmit FIFO, receive FIFO, receive timeout, modem status, and error conditioninterrupts.

Support for Direct Memory Access (DMA).



False start bit detection.

Line break generation and detection.

Support of the modem control functions CTS, DCD, DSR, RTS, DTR, and RI.

Programmable hardware flow control.

Fully-programmable serial interface characteristics:
data can be 5, 6, 7, or 8 bits

even, odd, stick, or no-parity bit generation and detection

1 or 2 stop bit generation

baud rate generation, dc up to UARTCLK/16
Table UART-790 UART List
UART
channelBase Address

Power Domain

Description－949/1293－

CXD5602 User Manual

UART00x041A9000

PWD_SYSIOP

UART1

0x041AC000

PWD_SYSIOP_SUB

UART2

0x4E103000

PWD_APP_SUB

UART0 is not memory-mapped to the Application CPU,and so the CPU cannot access UART0 directly. It isprovided a UART0 driver to control via System CPU, but it
behaves synchronously, not asynchronously. So then, it isrecommended that it is used with hardware flow control.
UART1 is typically used as a serial console from theApplication CPU.
UART2 is used as a general serial device from theApplication CPU.

Transfer Rate
The maximum baud rate of the UART is determined by the combination of the clock selected as the clock source(SYSPLL, XOSC, RCOSC, or RTC), the X'tal Oscillator clock, and the voltage mode (High Performance mode/
Low Power mode). The following table shows each combination and the maximum transfer rates.
Table UART-791 XOSC (26 MHz), High Performance Mode
Clock source
frequency
SYSIOP (ck_host_gear)

SYSPLL
MHz

195.000

156.000

XOSC

RCOSC

RTC

26.0008.192

0.032768MHz

48.75039.00026.0008.192

0.032768

UART0 baudratebps

3046875

2437500

1625000

5120002048

SYSIOP (ck_ahb_gear, ck_com_gear)MHz

48.75039.00026.0008.192

0.032768

UART1 baudratebps

3046875

2437500

1625000

5120002048

APP (CK_APP, GEAR_IMG_UART)

MHz

48.75039.00026.0008.192

0.032768

UART2 baudratebps

3046875

2437500

1625000

5120002048

Table UART-792 XOSC (26 MHz), Low Power Mode
Clock source
frequency

3.11.2.1

XOSC

RCOSC

RTC

MHz

195.000

156.000

26.0008.192

0.032768MHz

32.50031.20026.0008.192

0.032768

UART0 baudratebps

2031250

1950000

1625000

5120002048

SYSIOP (ck_ahb_gear, ck_com_gear)MHz

32.50031.20026.0008.192

0.032768

SYSIOP (ck_host_gear)

3.11.2

SYSPLLUART1 baudratebps

2031250

1950000

1625000

5120002048

APP (CK_APP, GEAR_IMG_UART)

MHz

39.00039.00026.0008.192

0.032768

UART2 baudratebps2437500

2437500

1625000

5120002048

UART1Clock and Reset

Figure UART-133 UART1 Clock and Reset System shows the clock and reset system diagram of the UART1.
To access the UART1 register, supply the clock to the AHB/APB Bus Bridge.

－950/1293－

CXD5602 User Manual

RCOSC

ck_rf_pll_1

RTC_CLK_IN(32.768kHz)XOSC

SYSPLLck_cpu_bus

1/M

ck_co m_gear
CK
GATE

CK_COM_BRG

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

CK
GATE

UART1

UARTCLKPCLKnUARTRSTPRESETn

0
1

CK
GATE

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4

CKDIV_COM.CK_COM
SYSIOP_SUB_CKEN.COM_BRG
SYSIOP_SUB_CKEN.UART1SYSIOP_SUB_CKEN.COM_UART_PCLK

AHB/APB
BusBridge
1/M

1/M

ck_ahb_gear

CK
GATE

CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_BRG_COMIF
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
SWRESET_BUS.XRST_UART1

Figure UART-133 UART1 Clock and Reset System

3.11.2.2

Clock supply Start and Stop

3.11.2.2.1

Clock Supply Start

Perform the following control to start supplying the UARTCLK clock and PCLK clock to the UART1.
1.

Clock supply start to the AHB/APB Bus Bridge
SYSIOP_SUB_CKEN.COM_BRG=1'b1
SYSIOP_SUB_CKEN.AHB_BRG_COMIF=1'b1

2. Reset release
SWRESET_BUS.XRST_UART1=1'b1
3. Clock supply start
SYSIOP_SUB_CKEN.COM_UART_PCLK=1'b1
SYSIOP_SUB_CKEN.UART1=1'b1

3.11.2.2.2

Clock Supply Stop

Perform the following control to stop supplying the UARTCLK clock and PCLK clock to the UART1.
1. Clock supply stop
SYSIOP_SUB_CKEN.COM_UART_PCLK=1'b0
SYSIOP_SUB_CKEN.UART1=1'b0－951/1293－

CXD5602 User Manual

3.11.33.11.3.1

UART2
Clock and Reset

Figure UART-134 UART2 Clock and Reset System shows the clock and reset system diagram of the UART2.
RCOSC
XOSC

RTC_CLK_IN(32.768kHz)SYSPLLCKGATE

CK_APP

N/M

CK
GATE

GEAR_AHB.gear_m_ahb
GEAR_AHB.gear_n_ahb
CK_GATE_AHB.ck_gate_img

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

1/M

0
1

SPI4

CK
GATE

SSPCLK
PCLK

GEAR_IMG_SPI.gear_m_spi
GEAR_IMG_SPI.gear_n_spi

APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP

nSSPRSTPRESETn

1/M

SPI5

CK
GATE

SSPCLK
PCLK

GEAR_IMG_WSPI.gear_m_img_wspi
GEAR_IMG_WSPI.gear_n_img_wspi

nSSPRSTPRESETn

1/M

UART2

CK
GATE

UARTCLK
PCLK

GEAR_IMG_UART.gear_m_uart
GEAR_IMG_UART.gear_n_uart

PRESETn

IMG_RST_X

RESET.xrs_img
PWD_RESET0.PWD_APPnUARTRST

Figure UART-134 UART2 Clock and Reset System

3.11.3.2

Clock Supply Start and Stop

3.11.3.2.1

Clock Supply Start

Perform the following control to start supplying the UARTCLK clock and PCLK clock to the UART2.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_img=1'b1
2. Supply the CK_APP (For details, refer to the APP Section (3.13))
3. Clock supply for the UART2 register and division ratio setting
GEAR_AHB.gear_m_ahb=(arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb=(arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_img=1'b1
4. UART2 control clock supply and division ratio setting
GEAR_IMG_UART.gear_m_uart=(arbitrary: denominator setting of the division ratio)
GEAR_IMG_UART.gear_n_uart=1'b1－952/1293－

CXD5602 User Manual

3.11.3.2.2

Clock Supply Stop

Perform the following control to stop supplying the UARTCLK clock and PCLK clock to the UART2.
1. UART2 control clock stop
GEAR_IMG_UART.gear_n_uart=1'b0
2. UART2 register’s clock stop
CK_GATE_AHB.ck_gate_img=1'b0

3.11.4

List of Registers

3.11.4.1

Register Map

OffsetName

Description

0x000

UARTDR

Data Register

0x004

UARTRSR/UARTECR

Receive Status Register/Error Clear Register

0x018

UARTFR

Flag Register

0x020

UARTILPR

IrDA Low-Power Counter Register

0x024

UARTIBRD

Integer Baud Rate Register

0x028

UARTFBRD

Fractional Baud Rate Register

0x02C

UARTLCR_H

Line Control Register

0x030

UARTCR

Control Register

0x034

UARTIFLS

Interrupt FIFO Level Select Register

0x038

UARTIMSC

Interrupt Mask Set/Clear Register

0x03C

UARTRISRaw Interrupt Status Register

0x040

UARTMIS

Masked Interrupt Status Register

0x044

UARTICR

Interrupt Clear Register

0x048

UARTDMACRDMA Control Register

3.11.4.1

Registers and Field Descriptions

3.11.4.1.1

UARTDR (0x000)

Description: The UARTDR Register is the data register.
For words to be transmitted:▪

if the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO▪

if the FIFOs are not enabled, data is stored in the transmitter holding register (the bottom word of thetransmit FIFO).

The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the－953/1293－

CXD5602 User Manualappropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted.
For received words:▪

if the FIFOs are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed
onto the 12-bit wide receive FIFO▪

if the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (thebottom word of the receive FIFO).

The received data byte is read by performing reads from the UARTDR Register along with the corresponding
status information. The status information can also be read by a read of the UARTRSR/UARTECR Register.
Table UART-793 UARTDR Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:12]-

Reserved

OE

R/W[11:11]0Overrun error. This bit is set to 1 if data is received and the receive FIFO isalready full.

BE

PE

FE

R/W

R/W

R/W

[10:10]

[9:9]

[8:8]

0

0

0

This is cleared to 0 once there is an empty space in the FIFO and a new
character can be written to it.
Break error. This bit is set to 1 if a break condition was detected, indicatingthat the received data input was held LOW for longer than a full-wordtransmission time (defined as start, data, parity and stop bits).
In FIFO mode, this error is associated with the character at the top of the
FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The
next character is only enabled after the receive data input goes to a 1(marking state), and the next valid start bit is received.
Parity error. When set to 1, it indicates that the parity of the received datacharacter does not match the parity that the EPS and SPS bits in the Line
Control Register, UARTLCR_H.
In FIFO mode, this error is associated with the character at the top of the
FIFO.
Framing error. When set to 1, it indicates that the received character did nothave a valid stop bit (a valid stop bit is 1).
In FIFO mode, this error is associated with the character at the top of the
FIFO.

DATA

R/W

[7:0]

0

Receive (read) data character.
Transmit (write) data character.

3.11.4.1.2

UARTRSR/UARTECR (0x004)

Description: The UARTRSR/UARTECR Register is the receive status register/error clear register.
Receive status can also be read from the UARTRSR Register. If the status is read from this register, then thestatus information for break, framing and parity corresponds to the data character read from the Data Register,UARTDR prior to reading the UARTRSR Register. The status information for overrun is set immediately whenan overrun condition occurs.
A write to the UARTECR Register clears the framing, parity, break, and overrun errors.
The received data character must be read first from the Data Register, UARTDR before reading the error status－954/1293－

CXD5602 User Manual

associated with that data character from the UARTRSR Register. This read sequence cannot be reversed, because
the UARTRSR Register is updated only when a read occurs from the UARTDR Register. However, the status
information can also be obtained by reading the UARTDR Register.
Table UART-794 UARTRSR/UARTECR Register
Bit Field

Type

Bit

InitialDescription

-

R/W

[7:0]

-

Reserved

N/A

[7:4]

-

A write to this register clears the framing, parity, break, and overrun errors.
The data value is not important.
Reserved

OE

R/W

[3:3]

0

Overrun error. This bit is set to 1 if data is received and the FIFO is alreadyfull.
This bit is cleared to 0 by a write to UARTECR.

BE

R/W

[2:2]

0

PE

R/W

[1:1]

0

The FIFO contents remain valid because no more data is written when the
FIFO is full, only the contents of the shift register are overwritten. The CPU
must now read the data, to empty the FIFO.
Break error. This bit is set to 1 if a break condition was detected, indicatingthat the received data input was held LOW for longer than a full-wordtransmission time (defined as start, data, parity, and stop bits). This bit iscleared to 0 after a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the
FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The
next character is only enabled after the receive data input goes to a 1(marking state) and the next valid start bit is received.
Parity error. When set to 1, it indicates that the parity of the received datacharacter does not match the parity that the EPS and SPS bits in the Line
Control Register, UARTLCR_H.
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the
FIFO.

FE

R/W

[0:0]

0

Framing error. When set to 1, it indicates that the received character did nothave a valid stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the
FIFO.

3.11.4.1.3

UARTFR (0x018)

Description: The UARTFR Register is the flag register.
Table UART-795 UARTFR Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:9]-

Reserved

RI

RO

[8:8]

0

Ring indicator. This bit is the complement of the UART ring indicator,
nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is
LOW－955/1293－

CXD5602 User Manual

TXFE

RO

[7:7]

1

Transmit FIFO empty. The meaning of this bit depends on the state of the
FEN bit in the Line Control Register, UARTLCR_H.
If the FIFO is disabled, this bit is set when the transmit holding register is
empty.
If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty.
This bit does not indicate if there is data in the transmit shift register.

RXFF

RO

[6:6]

0

Receive FIFO full. The meaning of this bit depends on the state of the FEN
bit in the UARTLCR_H Register.
If the FIFO is disabled, this bit is set when the receive holding register is full.
If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.

TXFF

RO

[5:5]

0

Transmit FIFO full. The meaning of this bit depends on the state of the FEN
bit in the UARTLCR_H Register.
If the FIFO is disabled, this bit is set when the transmit holding register isfull.
If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.

RXFE

RO

[4:4]

1

Receive FIFO empty. The meaning of this bit depends on the state of the FEN
bit in the UARTLCR_H Register.
If the FIFO is disabled, this bit is set when the receive holding register is
empty.
If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.

BUSY

RO

[3:3]

0

UART busy. If this bit is set to 1, the UART is busy transmitting data. Thisbit remains set until the complete byte, including all the stop bits, has been
sent from the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty, regardless ofwhether the UART is enabled or not.

DCD

RO

[2:2]

0

Data carrier detect. This bit is the complement of the UART data carrier
detect, nUARTDCD, modem status input. That is, the bit is 1 whennUARTDCD is LOW.

DSR

RO

[1:1]

0

Data set ready. This bit is the complement of the UART data set ready,nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is
LOW.

CTS

RO

[0:0]

0

Clear to send. This bit is the complement of the UART clear to send,
nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is
LOW.

3.11.4.1.4

UARTILPR (0x020)

Description: The UARTILPR Register is the IrDA low-power counter register.
This is an 8-bit read/write register that stores the low-power counter divisor value used to generate the
IrLPBaud16 signal by dividing down of UARTCLK.
Table UART-796 UARTILPR Register
Bit Field

Type

Bit

InitialDescription

ILPDVSR

R/W

[7:0]

0

8-bit low-power divisor value. These bits are cleared to 0 at reset.

3.11.4.1.5

UARTIBRD (0x024)

Description: The UARTIBRD Register is the integer part of the baud rate divisor value.

－956/1293－

CXD5602 User Manual

Table UART-797 UARTIBRD Register
Bit Field

Type

Bit

InitialDescription

BAUD DIVINT

R/W[15:0]

0

The integer baud rate divisor.

3.11.4.1.6

UARTFBRD (0x028)

Description: The UARTFBRD Register is the fractional part of the baud rate divisor value.
The baud rate divisor is calculated as follows:•

Baud rate divisor BAUDDIV = (FUARTCLK / (16×Baud rate))
where FUARTCLK is the UART reference clock frequency.

The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD DIVFRAC).
•

The contents of the UARTIBRD and UARTFBRD registers are not updated until transmission or receptionof the current character is complete.

•

The minimum divide ratio possible is 1 and the maximum is 65535(216 - 1). That is, UARTIBRD = 0 isinvalid and UARTFBRD is ignored when this is the case.

•

Similarly, when UARTIBRD = 65535 (that is 0xFFFF), then UARTFBRD must not be greater than zero. If
this is exceeded, it results in an aborted transmission or reception.
Table UART-798 UARTFBRD Register
Bit Field

Type

Bit

InitialDescription

BAUD DIVFRAC

R/W

[5:0]

0

The fractional baud rate divisor.

3.11.4.1.7

UARTLCR_H (0x02C)

Description: The UARTLCR_H Register is the line control register.
This register accesses bits 29 to 22 of the UART Line Control Register, UARTLCR. The UARTLCR_H,
UARTIBRD, and UARTFBRD registers form the single 30-bit wide UARTLCR Register that is updated on asingle write strobe generated by a UARTLCR_H write. So, to internally update the contents of UARTIBRD or
UARTFBRD, a UARTLCR_H write must always be performed at the end.
Table UART-799 UARTLCR_H Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:8]-

Reserved－957/1293－

CXD5602 User Manual

SPS

R/W

[7:7]

0

Stick parity select.
0 = stick parity is disabled
1 = either•

if the EPS bit is 0 then the parity bit is transmitted and checked as a 1•

if the EPS bit is 1 then the parity bit is transmitted and checked as a 0.

This bit has no effect when the PEN bit disables parity checking andgeneration.
WLEN

N/A

[6:5]

0

Word length. These bits indicate the number of data bits transmitted or
received in a frame as follows:
b11 = 8 bits
b10 = 7 bits
b01 = 6 bits
b00 = 5 bits.

FEN

R/W

[4:4]

0

Enable FIFOs:
0 = FIFOs are disabled (character mode) that is, the FIFOs become
1-byte-deep holding registers
1 = transmit and receive FIFO buffers are enabled (FIFO mode).

STP2

R/W

[3:3]

0

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at theend of the frame. The receive logic does not check for two stop bits being
received.

EPS

R/W

[2:2]

0

Even parity select. Controls the type of parity the UART uses duringtransmission and reception:= odd parity. The UART generates or checks for an odd number of 1s in thedata and parity bits.
= even parity. The UART generates or checks for an even number of 1s in thedata and parity bits.
This bit has no effect when the PEN bit disables parity checking andgeneration.

PEN

R/W

[1:1]

0

Parity enable:
0 = parity is disable and no parity bit added to the data frame
1 = parity checking and generation is enabled.

BRK

R/W

[0:0]

0

PEN

EPS

SPS Parity bit (transmitted or checked)

0

x

x

Not transmitted or checked

1

1

0

Even parity

1

0

0

Odd parity

1

0

1

1

1

1

1

0

Send break. If this bit is set to 1, a low-level is continually output on the
UARTTXD output, after completing transmission of the current character.
For the proper execution of the break command, the software must set this bit
for at least two complete frames.
For normal use, this bit must be cleared to 0.

3.11.4.1.8

UARTCR (0x030)

Description: The UARTCR Register is the control register.
Program the control registers as follows:
1. Disable the UART.

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2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by setting the FEN bit to 0 in the Line Control Register, UARTLCR_H.
4. Reprogram the UARTCR Register.
5. Enable the UART.
Table UART-800 UARTCR Register
Bit Field

Type

Bit

InitialDescription

CTSEn

R/W

[15:15]

0

RTSEn

R/W

[14:14]0

CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow
control is enabled. Data is only transmitted when the nUARTCTS signal isasserted.
RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow
control is enabled. Data is only requested when there is space in the receive
FIFO for it to be received.

Out2

R/W

[13:13]0This bit is the complement of the UART Out2 (nUARTOut2) modem status
output. That is, when the bit is programmed to a 1, the output is 0. For DTE
this can be used as Ring Indicator (RI).

Out1

R/W

[12:12]0This bit is the complement of the UART Out1 (nUARTOut1) modem status
output. That is, when the bit is programmed to a 1 the output is 0. For DTE
this can be used as Data Carrier Detect (DCD).

RTS

R/W

[11:11]0

Request to send. This bit is the complement of the UART request to send,
nUARTRTS, modem status output. That is, when the bit is programmed to a
1 then nUARTRTS is LOW.

DTR

R/W

[10:10]

0

RXE

R/W

[9:9]

1

TXE

R/W

[8:8]

1

Data transmit ready. This bit is the complement of the UART data transmit
ready, nUARTDTR, modem status output. That is, when the bit isprogrammed to a 1 then nUARTDTR is LOW.
Receive enable. If this bit is set to 1, the receive section of the UART isenabled. Data reception occurs for either UART signals or SIR signals
depending on the setting of the SIREN bit. When the UART is disabled in the
middle of reception, it completes the current character before stopping.
Transmit enable. If this bit is set to 1, the transmit section of the UART isenabled. Data transmission occurs for either UART signals, or SIR signals
depending on the setting of the SIREN bit. When the UART is disabled in the
middle of transmission, it completes the current character before stopping.

LBE

R/W

[7:7]

0

Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the
SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then thenSIROUT path is inverted, and fed through to the SIRIN path. The
SIRTEST bit in the test register must be set to 1 to override the normal
half-duplex SIR operation. This must be the requirement for accessing the test
registers during normal operation, and SIRTEST must be cleared to 0 whenloopback testing is finished. This feature reduces the amount of external
coupling required during system test.
If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path isfed through to the
UARTRXD path.
In either SIR mode or UART mode, when this bit is set, the modem outputs
are also fed through to the modem inputs.
This bit is cleared to 0 on reset, to disable loopback.

Reserved

N/A

[6:3]

-

Reserved－959/1293－

CXD5602 User Manual

SIRLP

R/W

[2:2]

0

SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this
bit is cleared to 0, low-level bits are transmitted as an active high pulse with awidth of 1/16 of the bit period. If this bit is set to 1, low-level bits aretransmitted with a pulse width that is 3 times the period of the IrLPBaud16
input signal, regardless of the selected bit rate. Setting this bit uses lesspower, but might reduce transmission distances.

SIREN

R/W

[1:1]

0

SIR enable:
0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse
generated), and signal transitions on SIRIN have no effect.
1 = IrDA SIR ENDEC is enabled. Data is transmitted and received onnSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state.
Signal transitions on UARTRXD or modem status inputs have no effect.
This bit has no effect if the UARTEN bit disables the UART.

UARTEN

R/W

[0:0]

0

UART enable:
0 = UART is disabled. If the UART is disabled in the middle of transmission
or reception, it completes the current character before stopping.
1 = the UART is enabled. Data transmission and reception occurs for either
UART signals or SIR signals depending on the setting of the SIREN bit.

To enable transmission, the TXE bit and UARTEN bit must be set to
1. Similarly, to enable reception, the RXE bit and UARTEN bit, must
be set to 1.

3.11.4.1.9

UARTIFLS (0x034)

Description: The UARTIFLS Register is the interrupt FIFO level select register.
You can use this register to define the FIFO level that triggers the assertion of UARTTXINTR andUARTRXINTR.
The interrupts are generated based on a transition through a level rather than being based on the level. That is, theinterrupts are generated when the fill level progresses through the trigger level.
The bits are reset so that the trigger level is when the FIFOs are at the half-way mark.

Table UART-801 UARTIFLS Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:6]-

Reserved

RXIFLSEL

R/W

[5:3]

0x2

Receive interrupt FIFO level select. The trigger points for the receive
interrupt are as follows:b000 = Receive FIFO becomes ≥ 1/8 fullb001 = Receive FIFO becomes ≥ 1/4 fullb010 = Receive FIFO becomes ≥ 1/2 fullb011 = Receive FIFO becomes ≥ 3/4 fullb100 = Receive FIFO becomes ≥ 7/8 fullb101-b111 = reserved.

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TXIFLSEL

R/W

[2:0]

0x2

Transmit interrupt FIFO level select. The trigger points for the transmit
interrupt are as follows:b000 = Transmit FIFO becomes ≤ 1/8 fullb001 = Transmit FIFO becomes ≤ 1/4 fullb010 = Transmit FIFO becomes ≤ 1/2 fullb011 = Transmit FIFO becomes ≤ 3/4 fullb100 = Transmit FIFO becomes ≤ 7/8 fullb101-b111 = reserved.

3.11.4.1.10

UARTIMSC (0x038)

Description: The UARTIMSC Register is the interrupt mask set/clear register.
On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to theparticular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask.

Table UART-802 UARTIMSC Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:11]-

Reserved

OEIM

R/W

[10:10]0Overrun error interrupt mask. A read returns the current mask for the
UARTOEINTR interrupt.

BEIM

R/W

[9:9]

0

PEIM

R/W

[8:8]

0

On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0
clears the mask.
Break error interrupt mask. A read returns the current mask for the
UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR
interrupt is set. A write of 0 clears the mask.
Parity error interrupt mask. A read returns the current mask for the
UARTPEINTR interrupt.
On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0
clears the mask.

FEIM

R/W

[7:7]

0

Framing error interrupt mask. A read returns the current mask for the
UARTFEINTR interrupt.
On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0
clears the mask.

RTIM

R/W

[6:6]

0

Receive timeout interrupt mask. A read returns the current mask for the
UARTRTINTR interrupt.
On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0
clears the mask.

TXIM

R/W

[5:5]

0

Transmit interrupt mask. A read returns the current mask for the
UARTTXINTR interrupt.
On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0
clears the mask.

RXIM

R/W

[4:4]

0

Receive interrupt mask. A read returns the current mask for the
UARTRXINTR interrupt.
On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0
clears the mask.

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CXD5602 User Manual

DSRMIM

R/W

[3:3]

0

nUARTDSR modem interrupt mask. A read returns the current mask for the
UARTDSRINTR interrupt.
On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of
0 clears the mask.

DCDMIM

R/W

[2:2]

0

nUARTDCD modem interrupt mask. A read returns the current mask for the
UARTDCDINTR interrupt.
On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of
0 clears the mask.

CTSMIM

R/W

[1:1]

0

nUARTCTS modem interrupt mask. A read returns the current mask for the
UARTCTSINTR interrupt.
On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of
0 clears the mask.

RIMIM

R/W

[0:0]

0

nUARTRI modem interrupt mask. A read returns the current mask for the
UARTRIINTR interrupt.
On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0
clears the mask.

3.11.4.1.11

UARTRIS (0x03C)

Description: The UARTRIS Register is the raw interrupt status register.
This register returns the current raw status value, prior to masking, of the corresponding interrupt. A write has noeffect.
Table UART-803 UARTRIS Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:11]-

Reserved

OERIS

RO

[10:10]0Overrun error interrupt status. Returns the raw interrupt state of the
UARTOEINTR interrupt.

BERIS

RO

[9:9]

0

PERIS

RO

[8:8]

0

Parity error interrupt status. Returns the raw interrupt state of the
UARTPEINTR interrupt.

FERIS

RO

[7:7]

0

Framing error interrupt status. Returns the raw interrupt state of the
UARTFEINTR interrupt.

RTRIS

RO

[6:6]

0

Receive timeout interrupt status. Returns the raw interrupt state of the
UARTRTINTR interrupt.

TXRIS

RO

[5:5]

0

Transmit interrupt status. Returns the raw interrupt state of the
UARTTXINTR interrupt.

RXRIS

RO

[4:4]

0

Receive interrupt status. Returns the raw interrupt state of the
UARTRXINTR interrupt.

DSRRIS

RO

[3:3]

-

nUARTDSR modem interrupt status. Returns the raw interrupt state of theUARTDSRINTR interrupt.

DCDRMIS

RO

[2:2]

-

nUARTDCD modem interrupt status. Returns the raw interrupt state of theUARTDCDINTR interrupt.

CTSRMIS

RO

[1:1]

-

nUARTCTS modem interrupt status. Returns the raw interrupt state of the
UARTCTSINTR interrupt.

RIRMIS

RO

[0:0]

-

nUARTRI modem interrupt status. Returns the raw interrupt state of the
UARTRIINTR interrupt.

Break error interrupt status. Returns the raw interrupt state of theUARTBEINTR interrupt.

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CXD5602 User Manual

3.11.4.1.12

UARTMIS (0x040)

Description: The UARTMIS Register is the masked interrupt status register.
This register returns the current masked status value of the corresponding interrupt. A write has no effect.
All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when reset. The modem statusinterrupt bits are undefined after reset.
Table UART-804 UARTMIS Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:11]-

Reserved

OEMIS

RO

[10:10]0Overrun error masked interrupt status. Returns the masked interrupt state of
the UARTOEINTR interrupt.

BEMIS

RO

[9:9]

0

PEMIS

RO

[8:8]

0

Parity error masked interrupt status. Returns the masked interrupt state of the
UARTPEINTR interrupt.

FEMIS

RO

[7:7]

0

Framing error masked interrupt status. Returns the masked interrupt state of
the UARTFEINTR interrupt.

RTMIS

RO

[6:6]

0

Receive timeout masked interrupt status. Returns the masked interrupt state of
the UARTRTINTR interrupt.

TXMIS

RO

[5:5]

0

Transmit masked interrupt status. Returns the masked interrupt state of the
UARTTXINTR interrupt.

RXMIS

RO

[4:4]

0

Receive masked interrupt status. Returns the masked interrupt state of the
UARTRXINTR interrupt.

DSRMMIS

RO

[3:3]

-

nUARTDSR modem masked interrupt status. Returns the masked interrupt
state of the UARTDSRINTR interrupt.

DCDMMIS

RO

[2:2]

-

nUARTDCD modem masked interrupt status. Returns the masked interrupt
state of the UARTDCDINTR interrupt.

CTSMMIS

RO

[1:1]

-

nUARTCTS modem masked interrupt status. Returns the masked interrupt
state of the UARTCTSINTR interrupt.

RIMMIS

RO

[0:0]

-

nUARTRI modem masked interrupt status. Returns the masked interrupt
state of the UARTRIINTR interrupt.

3.11.4.1.13

UARTICR (0x044)

Break error masked interrupt status. Returns the masked interrupt state of theUARTBEINTR interrupt.

Description: The UARTICR Register is the interrupt clear register and is write-only.
On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

Table UART-805 UARTICR Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:11]-

Reserved

OEIC

WO[10:10]-Overrun error interrupt clear. Clears the UARTOEINTR interrupt.

BEIC

WO

[9:9]

-

Break error interrupt clear. Clears the UARTBEINTR interrupt.

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CXD5602 User Manual

PEIC

WO

[8:8]

-

Parity error interrupt clear. Clears the UARTPEINTR interrupt.

FEIC

WO

[7:7]

-

Framing error interrupt clear. Clears the UARTFEINTR interrupt.

RTIC

WO

[6:6]

-

Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.

TXIC

WO

[5:5]

-

Transmit interrupt clear. Clears the UARTTXINTR interrupt.

RXIC

WO

[4:4]

-

Receive interrupt clear. Clears the UARTRXINTR interrupt.

DSRMIC

WO

[3:3]

-

nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

DCDMIC

WO

[2:2]

-

nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

CTSMIC

WO

[1:1]

-

nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

RIMIC

WO

[0:0]

-

nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

3.11.4.1.14

UARTDMACR (0x048)

Description: The UARTDMACR Register is the DMA control register.
Table UART-806 UARTDMACR Register
Bit Field

Type

Bit

InitialDescription

Reserved

N/A[15:3]-

Reserved

DMAONERR

R/W

[2:2]

0

DMA on error. If this bit is set to 1, the DMA receive request outputs,
UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the
UART error interrupt is asserted.

TXDMAE

R/W

[1:1]

0

Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO isenabled.

RXDMAE

R/W

[0:0]

0

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO isenabled.

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CXD5602 User Manual

3.12 GNSS
Multi-GNSS receiver
The features are:

Multiple Constellation compatibility-

GPS (L1 C/A)-

GLONASS (L1OF)

Position Accuracy

Item

GPS

GPS &
GLONASS

RemarkUnit

Signal strength is -130 dBm
2DRMS

2.5

2.5

m

Test circuit as shown in the figure
below

Time-To-First-Fix (TTFF)

GPS &

Item

GPS

Cold Start

35

35

s

Hot Start

2

2

s



GLONASS

RemarkUnit

Signal strength is -130 dBm
Test circuit as shown in the figure
below

Sensitivity

GPS &RemarkItemGPS

Cold Start

-147

-147

dBm

Test circuit as shown in the figure

Hot Start

-160

-160

dBm

below

Tracking

-161

-161

dBm



GLONASS

Unit

Test Circuit－965/1293－

CXD5602 User Manual

Noise Filter

An embedded noise filter for GNSS signals. It is automatically enabled at the optimum settings for the input noise.


RF Performance

Item

Min.

Typ.

Max.

Unit

Total NF

-

3

-

db

－966/1293－

CXD5602 User Manual

3.13 APP
3.13.1

Function Overview

The Application Domain is responsible for a variety of application software of the CXD5602. Centered around themulti core CPU system of the Arm® Cortex®-M4 processor with FPU, it equips high speed interface processing
block such as USB and eMMC, Audio, and Imaging multimedia processing.
The following describes the Application Domain’s features.
Depending on the combination of X'tal Oscillator clock frequencies and voltage modes (High Performancemode/Low Power mode), the performance such as transfer rate varies. This section explains the performances
when 26 MHz is selected as the X'tal Oscillator clock frequency. Overview of APP Maximum Frequency andsections of each function, for example, for SPI, refer to the Section of SPI (0).
Application Processor
The application processor integrates six Cortex®-M4 processors with FPU (ADSP) to meet the requirements ofwearable and IoT devices, which demand operation in low power and performance-optimized consumer
applications with the ability to scale in speed up to 156.0 MHz, the Arm® Cortex®-M4 Processor.
The key features include:Arm® Cortex®-M4 processor with FPUISA Support: Thumb®/Thumb®-2 technology



DSP Extension: Single cycle 16/32 bit MAC, Single cycle dual 16 bit MAC, 8/16 bit SIMD arithmetic,
Hardware Divide (2-12 Cycles)

Floating Point Unit: Single precision floating point unit, IEEE 754 compliant

Processor system peripherals
Programmable Interrupts Controller

128 channel peripheral Interrupt support for each processor

Timer


AMBA® Design Kit (ADK) SP804



Two-channel support



One Timer module for each processor (Total: Six Timers)

Watchdog Timer

AMBA® Design Kit (ADK) SP805



One channel for each processor (Total: Six Watchdog Timers)

Crypto Engine in Application Domain
The key features include:－967/1293－

CXD5602 User Manual

AES Encryption/Decryption

ECB, CBC, CTR, OFB, and CFB and CMAC chaining algorithms, 128, 192 or 256 bit key

Key generationUp to 128 bit

Embedded Application Memory
The key features include:

1.5 MByte SRAM



operating frequency
High Performance mode: Up to 156.0 MHz



Low Power mode: Up to 39.0 MHz

Image and Display Processing Domain
The key features Domain include:

8 bit parallel Camera Interface input

8 bit ITU-R BT.601/656 Mode

compressed data like JPEG supported

supports Y/C, JPEG and JPEG+Y/C Interleave formats

Programmable polarity of video sync signal

Capture frame control supported



Input image size

JPEG Only: up to 5 M pixels



Y/C Only: up to 480 x 360



JPEG+Y/C: 2 M + WQVGA (JPEG High Quality mode)
5 M + WQVGA (JPEG Normal Quality mode)

Parallel Input rate: Up to 54 MHz

SPI Interface for external display
PrimeCell® Synchronous Serial Port (PL022)



Display resolutionHigh Performance mode: Up to 320 240 15 fps 24 bit RGB

Low Power Mode: Up to 176 x 144, 15 fps 24 bit RGB

Communication at speedsHigh Performance mode:

Master Half duplex mode: up to 39 Mbit/s (transmit only)

Master Full duplex mode: up to 9.75 Mbit/s

Low Power mode:

Master Half duplex mode: up to 9.75 Mbit/s (transmit only)

Master Full duplex mode: up to 6.5 Mbit/s

SPI Interface for Wi-Fi－968/1293－

CXD5602 User Manual

PrimeCell® Synchronous Serial Port (PL022)



Communication at speeds
High Performance mode: up to 13.00 Mbit/s

Low Power mode: up to 6.5 Mbit/s

2D Graphics Accelerator


Bit Block Transfer



RotatorSupported image format: YCbCr422, RGB565

Supported rotate degree:0, 90, 180, 270



3-operand raster operation (ROP3)



Alpha blendingScalingHorizontal direction: x1/64 to x64, Vertical direction: x1/64 to x64
Maximum source input 2880x2160, maximum destination output 768x1024



YCbCr 422 16 bpp format

Connectivity and Storage Domain
The key features are:

USB 2.0 DeviceComplies with USB 2.0 Specification High-speed up to 480 Mbps


On-chip USB PHY transceiverSupports MSC, MTP, CDC, PTP, ACM, and HID class

Multi-function








Not supported at Low Power mode:

Interface: #0/#1/#2

SD Host Controller InterfaceSD Memory Card Protocol version 3.0 compatible



8 KByte (32 bit x 2048 word) x2 FIFOs for Tx/Rx

Communication speeds
High Performance mode: Up to 39.000 MHz



Low Power mode: Up to 24.552 MHz

eMMC Interface
eMMC 4.41 Protocol compatible



1 KByte (32 bit x 256 word) x2 FIFOs for Tx/Rx

Communication speeds
High Performance mode: Up to 39.000 MHz



Low Power mode: Up to 24.552 MHzUART interfaces for external Wi-Fi and Bluetooth devices:－969/1293－

CXD5602 User Manual

PrimeCell® UART (PL011)



Communication speeds
High Performance mode: up to 3 Mbit/s

Low Power mode: up to 2 Mbit/s

DMAC


ADMAC (PL081) supports for memory to memory



IDMAC (like PL080) supports for SPI for display and UART for BT, BLE, Wi-Fi

Audio Codec Domain
The key features are:

I2S Bus Interface supports:

Two I2S-bus for audio-codec interface with DMA-based operation



16/24 bit per channel data transfers



I2S, Left-justified data format



Various bit clock frequency and codec clock frequency support

Master clock:High Performance mode: 256fs, 128fs, 64fs of bit clock frequency

Low power mode: 128fs, 64fs of bit clock frequency

Slave clock:High Performance mode: 256fs, 128fs, 64fs of bit clock frequency

Low power mode: 128fs, 64fs of bit clock frequency

Sampling rate







High Performance mode

Master mode: 192 kHz, 96 kHz, 48 kHz

Slave mode: 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 16 kHz, 8 kHz

Low Power mode

Master mode: 96 kHz, 48 kHz

Slave mode: 96 kHz, 48 kHz, 44.1 kHz, 16 kHz, 8 kHz

Two channels each I2S interface

Unique Audio Data Format (Pulse Density Modulation) between CXD5602GF/GG and CXD5247GF

This part mainly explains the Application Processor and application memory. For explanations of other separate
functional blocks, refer to other sections.

3.13.2

Power Supply Control

The Application Domain is divided into four power domains: the PWD_APP, PWD_APP_DSP, PWD_APP_SUB,－970/1293－

CXD5602 User Manualand PWD_APP_AUD. The following describes each functional block of the Application Domain and thecorresponding power domains.


PWD_APPAll components of Application Domain

Including 1.5 MByte SRAM in Application memory and Application Multi-layer Bus

PWD_APP_DSPApplication & DSP processors



ADMAC

PWD_APP_SUBConnectivity, Storage I/F and Camera, Display Interface in Application Domain

PWD_APP_AUD


Audio Codec

3.13.33.13.3.1

Clock Reset Control
Overview of APP Maximum Frequency

The following tables describe the APP maximum operating frequencies of the APP MAIN Bus and the APP SUB
Bus to which main functional blocks of the Application Domain are connected. Each has a different maximum
operating frequency depending on the supported XOSC frequency and the SYSPLL oscillating frequency. In
addition, element circuits such as AudioCodec, USB, eMMC, that are connected to the APP SUB Bus, have thesame maximum frequencies as the APP MAIN Bus.
For the maximum operating frequencies of external communication interfaces, refer to separate sections.
Table APP-807 XOSC (26 MHz), High Performance Mode
Clock source
frequency
APP M AIN Bus/APP SUB Bus

M Hz
M Hz

SYSPLL
195.000
156.000
97.500156.000

XOSC
26.00026.000

RCOSC
8.192
8.192

RTC
0.032768
0.032768

RCOSC
8.192
8.192

RTC
0.032768
0.032768

Table APP-808 XOSC (26 MHz), Low Power Mode
Clock source
frequency
APP M AIN Bus/APP SUB Bus

M Hz
M Hz

SYSPLL
195.000
156.000
39.00039.000－971/1293－

XOSC
26.00026.000CXD5602 User Manual

3.13.3.2

Clock Reset Generator

The following shows the clock system diagram.

RCOSC
XOSC
SYSPLL
RTC_CLK_IN(32.768kHz)
0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

0
1

CK
GATE

CK_APP

APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP

GEAR_AHB

0
1
2
3

1/2
1/3
1/4
1/5

0
1
2
3

0
1

N/M

ck_cpu_bus

1/M

ck_ahb_gear

1/M

CK
GATE

CK_APP_AHB

CK
GATE

CK_GATE_AHB.ck_gate_aud

CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4

CK_APP_MCLKCKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
APP_CKEN.AHB
P1x_00(MCLK)

1/M
Reserved

0
1
2
3

ADSP

CK
CK
CK
GATE
CK
GATE
CK
GATE
CK
GATE
GATE
GATE

CK_GATE_AHB.ck_gate_dsp0-5

CK
GATE

APP_DIV.AU_MCLKAPP_CKSEL.AU_MCK
APP_CKEN.MCLK

AUDIO

CLK_AHBMCLKCK_GATE_AHB.ck_gate_dmac

CK
GATE

CK_GATE_AHB.ck_gate_sake

CK
GATE

CK_GATE_AHB.ck_gate_kaki

CK
GATE

CK_GATE_AHB.ck_gate_img

CK
GATE

ADMAC

HCLK

CryptoCIS I/F
CLK_AHB/APB

2D Graphics
IMG_CLK_AHB

GEAR_IMG_UART.gear_m_uart
GEAR_IMG_UART.gear_n_uart
GEAR_IMG_SPI.gear_m_spi
GEAR_IMG_SPI.gear_n_spi
GEAR_IMG_WSPI.gear_m_wspi
GEAR_IMG_WSPI.gear_n_wspi

1/M

1/M

1/M

PCLK

CK
GATE

UART

UARTCLK

PCLK

CK
GATE

SPI4

SSPCLK

PCLK

CK
GATE

SPI5

SSPCLK

IDMAC

GEAR_M_IMG_VENB
GEAR_N_IMG_VENB

HCLK

N/M

Pulse w idth
co nversio n

CK
GATE

CK_GATE_AHB.ck_gate_mmc

CK_GATE_AHB.ck_gate_sdio
GEAR_PER_SDIO.gear_m_sdio
GEAR_PER_SDIO.gear_n_sdio
CK_GATE_AHB.ck_gate_usb
GEAR_PER_USB.gear_n_usb
GEAR_PER_USB.gear_n_usb

Figure APP-135 Application Domain Clock System－972/1293－

VideoTG

CK
GATE

1/M

CK
GATE

CK
GATE

HCLK

SDIO

CLK_IN
CK
GATE

1/M

eMMC

MMC_I_HCLK

1/2

USB

USBD_SYS_CLK_I
USBD_CLK_32K_I

CXD5602 User Manual

The following shows the reset system diagram.

RESET.xrs_dsp0-5

ADSP

RESET.xrs_aud

AUDIO

XRST

RESET.xrs_dsp_gen

ADMAC

HRESETn

CryptoXRSTSXRSTKRESET.xrs_img

CIS I/FXRST

2D Graphics

IMG_RST_X

UARTPRESETnnUARTRSTSPI4PRESETnnSSPRSTSPI5PRESETnnSSPRSTIDMAC

HRESETnRESET.xrs_mmc

eMMC

MMC_I_RST_N

RESET.xrs_mmc_crg
XRST

RESET.xrs_sdio

SDIO

HRESETNRESET.xrs_usb

USB

USBD_SYS_RST_N_I

PWD_RESET0.PWD_APP

Figure APP-136 Application Domain Reset System－973/1293－

CXD5602 User Manual

3.13.3.3

Register Descriptions

The following describes setting registers for clock and reset.
Clock division ratio setting and clock switching registers are controlled by the API. The clock setting can be
confirmed with the registers described in Table APP-809 and Table APP-810. Make sure to use them as RO
registers.
Table APP-809Clock Division Ratio Setting Registers
Address

Register Name

Bit Field

Type

Bit

Name
0x0410341C

APP_DIV

InitialDescription

Value

ReservedRO[31:3]

0Reserved

AU_MCLK

RW

[2:0]

0

AUDIO XOSC division ratio setting
0: clock not divided
1: clock divided by 2
2: clock divided by 3
3: clock divided by 4
4: clock divided by 5
5: clock divided by 6
6: clock divided by 7
7: clock divided by 8

Table APP-810 Clock Switching Registers
Address

0x04103418

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

APP_CKSEL

ReservedRO[31:18]0Reserved

AU_MCLK

RW[17:16]

2'b00

Clock source switching for AUDIO

Value

2'b00: External MCLK
2'b01: XOSC divided clock selected by
APP_DIV.AU_MCLK
2'b10: RCOSC
2'b11: Prohibited setting
ReservedRO[15:12]－974/1293－

0ReservedCXD5602 User Manual

STAT_SP_C

RO[11:10]2'b00

Frequency division setting status for
CK_APP SYSPLLLK_SEL4

2'b00: clock not divided
2'b01: divided by 2
2'b10: divided by 3
2'b11: divided by 4 or 5 (depending on
APP_CKSEL.APP_PLL_DIV5)
STAT_APP_

RO

[9:8]

2'b00

Clock source switching status for
CK_APP

CLK_SEL42'b00: RCOSC
2'b01: SYSPLL divided clock selected
by
APP_CKSEL.STAT_SP_CLK_SEL4
2'b10: XOSC
2'b11: RTC Clock
APP_PLL_DI

RW

[7]

0

V5

Clock divided by 4 or 5 for CK_APP
SYSPLL
0: clock divided by 4
1: clock divided by 5

Reserved

RW

[6:0]

0

Reserved

Table APP-811 Clock Enable Registers
Address

Register Name

Bit Field

Type

Bit

Name
0x04103414

APP_CKEN

InitialDescription

Value

ReservedRO[31:4]

0Reserved

AHB

RW

[3]

0

Clock Enable of CK_APP_AHB
0: Clock stopped
1: Clock supplied

Reserved

RO

[2]

0

Reserved

MCLK

RW

[1]

0

Clock Enable of CK_APP_MCLK
0: Clock stopped
1: Clock supplied

APP

RW

[0]

0

Clock Enable of CK_APP
0: Clock stopped
1: Clock supplied－975/1293－

CXD5602 User Manual

Table APP-812 Clock Reset Generator Registers
Address

Register Name

Bit Field

Type

Bit

Name
0x0E011000

GEAR_AHB

InitialDescription

Value

ReservedRO[31:23]0Reserved

gear_n_ahb

RW[22:16]

7'h1

Division ratio setting of AHB bus clock(numerator)“0” must not be written (because “0”will be overwritten to “1”)ReservedRO[15:7]

0Reserved

gear_m_ahb

RW

[6:0]

7'h2

Division ratio setting of AHB bus clock(denominator) “0” or values which areapplicable to the formula “gear_n_ahb >gear_m_ahb” must not be written.
(If that is done, gear_n_ahb will beoverwritten to 7'h7f, andgear_m_ahb, to 7'h7f. (Operationally,
it means 1/1.)

0x0E011004

GEAR_IMG_UART

ReservedRO[31:17]

0

Reserved

gear_n_uart

RW

[16]

0

UART2 Clock Enable
0: Clock stopped
1: Clock supplied

ReservedRO[15:7]

0Reserved

gear_m_uart

RW

[6:0]

7'h4

Division ratio setting of UART2 clock(denominator)“0” must not be written.

0x0E011008

GEAR_IMG_SPI

ReservedRO[31:17]

0

Reserved

gear_n_spi

RW

[16]

0

SPI4 Clock Enable
0: Clock stopped
1: Clock supplied

ReservedRO[15:7]

0Reserved

gear_m_spi

RW

[6:0]

7'h4

Division ratio setting of SPI4 clock(denominator)“0” must not be written.

0x0E01100C

GEAR_PER_SDIO

ReservedRO[31:17]－976/1293－

0ReservedCXD5602 User Manualgear_n_sdio

RW

[16]

0

SDIO Clock Enable
0: Clock stopped
1: Clock supplied

ReservedRO[15:2]

0Reserved

gear_m_sdio

RW

[1:0]

2'h2

Division ratio setting of SDIO Clock(denominator)“0” must not be written.

0x0E011010

GEAR_PER_USB

ReservedRO[31:17]

0

Reserved

gear_n_usb

RW

[16]

0

Division ratio setting of USB Clock(numerator)
0: Clock stopped
Clock is output when
RESET.xrs_usb equals 1'b1.

ReservedRO[15:12]0

Reserved

gear_m_usb

RW[11:0]

12'h2

Division ratio setting of USB clock(denominator)“0” must not be written.

0x0E011014

GEAR_M_IMG_VENB

gear_m_img_

RW[31:0]

0

venb

Division ratio setting of VideoTG(denominator)
Set values are not reflected until they
are written in
GEAR_N_IMG_VENB.
“0” or values which are applicable tothe formula “GEAR_N_IMG_VENB >GEAR_M_IMG_VENB” must not be
written.

0x0E011018

GEAR_N_IMG_VENB

gear_n_img_v

RW[31:0]

0

Division ratio setting of VideoTG(numerator)enb

0: Clock stopped
VideoTG is output when
RESET.xrs_img equals 1'b1.
Values of GEAR_M_IMG_VENB and
GEAR_N_IMG_VENB are reflected individer circuits by writing them in thisregister.
0x0E01101C

GEAR_IMG_WSPIReservedRO[31:17]－977/1293－

0ReservedCXD5602 User Manualgear_n_img_

RW

[16]

0

Division ratio setting of SPI5 clock(numerator)

wspi

0: Clock stopped
1: Clock supplied
ReservedRO[15:4]

0Reserved

gear_m_img_

RW

[3:0]

4'h4

Division ratio setting of SPI5 clock

wspi(denominator)“0” must not be written.

0x0E011020

CKEN_EMMC

ReservedRO[31:3]

0Reserved

cken_emmc_s

RW

[2]

0

eMMC Sample Clock Enabler

mp

0: Clock stopped
1: Clock supplied

cken_emmc_d

RW

[1]

0

rv

eMMC DRV Clock Enabler
0: Clock stopped
1: Clock supplied

cken_emmc_c

RW

[0]

0

lkin

eMMC Clock Enabler
0: Clock stopped
1: Clock supplied

0x0E011030

RESET

ReservedRO[31:23]0Reserved

xrs_dsp_gen

RW

[22]

0

DSP GENERAL/Reset Register
0: Reset assert
1: Reset release

xrs_dsp5

RW

[21]

0

Reset Register for ADSP5
0: Reset assert
1: Reset release

xrs_dsp4

RW

[20]

0

Reset Register for ADSP4
0: Reset assert
1: Reset release

xrs_dsp3

RW

[19]

0

Reset Register for ADSP3
0: Reset assert
1: Reset release

xrs_dsp2

RW

[18]

0

Reset Register for ADSP2
0: Reset assert
1: Reset release

xrs_dsp1

RW

[17]

0

Reset Register for ADSP1
0: Reset assert
1: Reset release－978/1293－

CXD5602 User Manual

xrs_dsp0

RW

[16]

0

Reset Register for ADSP0
0: Reset assert
1: Reset release

ReservedRO[15:12]0

Reserved

xrs_mmc_crg

RW

[11]

0

eMMC CRG Reset Register
0: Reset assert
1: Reset release

xrs_mmc

RW

[10]

0

eMMC Reset Register
0: Reset assert
1: Reset release

xrs_sdio

RW

[9]

0

SDIO Reset Register
0: Reset assert
1: Reset release

xrs_usb

RW

[8]

0

USB Reset Register
0: Reset assert
1: Reset release

Reserved

RO

[7:5]

0

Reserved

xrs_img

RW

[4]

0

Image Reset Register
0: Reset assert
1: Reset release

Reserved

RO

[3:1]

0

Reserved

xrs_aud

RW

[0]

0

PWD_AUD/Reset Register
0: Reset assert
1: Reset release

0x0E011040

CK_GATE_AHB

ReservedRO[31:29]0Reserved

ck_gate_dmac

RW

[28]

0

ADMAC ClockGate Register0: Clock stopped
1: Clock supplied

ReservedRO[27:22]0

Reserved

ck_gate_dsp5

RW

[21]

0

ADSP5 ClockGate Register0: Clock stopped
1: Clock supplied

ck_gate_dsp4

RW

[20]

0

ADSP4 ClockGate Register0: Clock stopped
1: Clock supplied

ck_gate_dsp3

RW

[19]

0

ADSP3 ClockGate Register0: Clock stopped
1: Clock supplied－979/1293－

CXD5602 User Manual

ck_gate_dsp2

RW

[18]

0

ADSP2 ClockGate Register0: Clock stopped
1: Clock supplied

ck_gate_dsp1

RW

[17]

0

ADSP1 ClockGate Register0: Clock stopped
1: Clock supplied

ck_gate_dsp0

RW

[16]

0

ADSP0 ClockGate Register0: Clock stopped
1: Clock supplied

ReservedRO[15:11]

0

Reserved

ck_gate_mmc

RW

[10]

0

eMMC (AHB Bus) ClockGate Register0: Clock stopped
1: Clock supplied

ck_gate_sdio

RW

[9]

0

SDIO (AHB Bus) ClockGate Register0: Clock stopped
1: Clock supplied

ck_gate_usb

RW

[8]

0

USB (AHB Bus) ClockGate Register0: Clock stopped
1: Clock supplied

Reserved

RO

[7:5]

0

Reserved

ck_gate_img

RW

[4]

0

Image (AHB Bus) ClockGate Register0: Clock stopped
1: Clock supplied

Reserved

RO

[3:1]

0

Reserved

ck_gate_aud

RW

[0]

0

Audio (AHB Bus) ClockGate Register0: Clock stopped
1: Clock supplied

Table APP-813 APP SRAM Tile Clock Gating Registers
Address

Register Name

Bit Field

Type

Bit

Name
0x0E001084

InitialDescription

Value

APP_TILE_CLK_GATI

ReservedRO[31:12]0

Reserved

NG_ENB

tile11_clk_gat

RW

[11]

0

APP SRAM Tile 11 ClockGate

ing_enb

0: Clock stopped
1: Clock supplied

tile10_clk_gat

RW

[10]

0

APP SRAM Tile 10 ClockGate
0: Clock stopped

ing_enb

1: Clock supplied－980/1293－

CXD5602 User Manual

tile9_clk_gati

RW

[9]

0

ng_enbAPP SRAM Tile 9 ClockGate
0: Clock stopped
1: Clock supplied

tile8_clk_gati

RW

[8]

0

ng_enbAPP SRAM Tile 8 ClockGate
0: Clock stopped
1: Clock supplied

tile7_clk_gati

RW

[7]

0

ng_enbAPP SRAM Tile 7 ClockGate
0: Clock stopped
1: Clock supplied

tile6_clk_gati

RW

[6]

0

ng_enbAPP SRAM Tile 6 ClockGate
0: Clock stopped
1: Clock supplied

tile5_clk_gati

RW

[5]

0

ng_enbAPP SRAM Tile 5 ClockGate
0: Clock stopped
1: Clock supplied

tile4_clk_gati

RW

[4]

0

ng_enbAPP SRAM Tile 4 ClockGate
0: Clock stopped
1: Clock supplied

tile3_clk_gati

RW

[3]

0

ng_enbAPP SRAM Tile 3 ClockGate
0: Clock stopped
1: Clock supplied

tile2_clk_gati

RW

[2]

0

ng_enbAPP SRAM Tile 2 ClockGate
0: Clock stopped
1: Clock supplied

tile1_clk_gati

RW

[1]

0

ng_enbAPP SRAM Tile 1 ClockGate
0: Clock stopped
1: Clock supplied

tile0_clk_gati

RW

[0]

ng_enb0

APP SRAM Tile 0 ClockGate
0: Clock stopped
1: Clock supplied－981/1293－

CXD5602 User Manual

Table APP-814 Reset Control Registers
Address

Register Name

Bit Field

Type

Bit

Name
0x04103408

3.13.43.13.4.1

SWRESET_APP

InitialDescription

Value

ReservedRO[31:1]

0Reserved

APP_DBG

RW

[0]

0

Debug Reset of ADSP

Description of APP_DSP Function
Overview and Features

The APP_DSP is a sub block in the Application Domain. It consists of the following:
1. six Cortex®-M4 processors with FPU
2. 1.5 Mbyte of SRAM
3. Audio and Imaging (2D Graphics, CIF I/F)
4. Storage (eMMC, USB)
5. buses to connect 1 to 5 functional blocks above.
The APP_DSP is mainly used for executing Main program and controlling other sub blocks.

－982/1293－

CXD5602 User Manual

Debug

APP_DSP
Application Processor

ADSP0
FPU

NVIC

WIC

Interrupt
Input
Controller
Watch Dog
Timer

MPU
D

PID3-7

ITM DAP CTI

Cortex-M4
Core
SysTickI

ADSP1-5

async
bridge

PID2

Timer

S

BUS

ADMAC

Clock
Reset
Generator

Crypto(AES)

GeneralPurposeRegisters

GeneralPurposeRegisters

Bus Exclusive LD/ST
disablePID
Sleep Monitor
Watch Dog reset
Ored

Address Converter
Bus Error
Cause
Registers

Protction
Setting
Registers

AHB to APB

APP MAIN Bus : 32b Multi-Layer AHB

protection(MID+power)

AHB to APB

protection(MID)

APP SUB Bus : 32b Multi-Layer AHB

Exclusive Load/StoreAPP SRAM

protection(MID+power)

AHB toAHB

protection(MID+power)

protection(MID+power)

protection(MID+power)

protection(MID+power)

protection protection(MID+po (MID+po
wer)
wer)

protection(MID+power)

protection(MID+power)

protection(MID+power)

protection
setting reg

protection(MID+power)

protection(MID+po
wer)

SRAM
0
128KB

SRAM
1
128KB

・・・SRAM2 - SRAM9・・・

protection(MID+power)

protection(MID+po
wer)

SRAM
10
128KB

SRAM
11
128KB

async
bridgeSYSIOP Bus

Audio

Imaging / 2D

Figure APP-137 APP_DSP Block Diagram－983/1293－

Storage/Connectivity

CXD5602 User Manual

3.13.4.2

Function List

Table APP-815 shows the functions of the APP_DSP.
Table APP-815 APP_DSP Function List
No

Function Name

Description

1

Cortex®-M4 processor with FPU

The APP_DSP equips six Cortex®-M4 processors with FPU in total.

2

Processor ID

The APP_DSP has unique ID for each processor. Slave access control can be set for

ADSP

each ID. The ID of each processor can be confirmed by reading registers.
3

Interrupt Controller

This function controls interrupts which are input to each processor via Private
Peripheral Bus of Cortex®-M4 processors with FPU.

4

Timer

The Timer is used for general purpose, with two input ports, and can be controlled
via Private Peripheral Bus of the Cortex®-M4 processor with FPU

5Watchdog Timer

The Watchdog Timer can be controlled via Private Peripheral Bus of the Cortex®-M4
processor with FPU.

6SLEEPING Signal Monitor

This function enables to confirm the SLEEPING signal status of each processor byreading registers.

7

Debug Function

The APP_DSP has the debug block which offers SWD, Trace, and Cross-Trigger
functions.

8

I/D Multiplexor

This function multiplexes ICode bus and DCode bus of the Cortex®-M4 processor
with FPU in order of fixed priority (DCode has a higher priority than ICode).

BUS
9

Address Map

The Address Map enables to access memories and control a variety of programablefunctions via buses.

10Address Converter

This function converts addresses of virtual memory space for every 64 Kbyte logical
area.

11

Bus Matrix

The Bus Matrix includes multi-layer matrix in the sub block based on the AMBA® 3
AHB-Lite protocol and bridges which connect AHBs between the blocks.

12

Exclusive Load/StoreThis function performs monitoring and controlling of exclusive accesses to a specific
SRAM Tile.

13

Protection and Error Information

This function blocks accesses from unprivileged bus masters to a specific bus slave,

Registeror a bus slave which is in the status that the power is turned off. The function has aregister to hold access error information when an unprivileged access occurs.

14

SYSIOP Bridge

Bus Matrix of the APP SUB Bus connects to the upper-layer SYSIOP bus of the
APP_DSP block via the asynchronous bridge.

15

ADMAC

Refer to the Section of the DMAC (3.8).

－984/1293－

CXD5602 User Manual

Memory16

SRAM with protection feature

The SRAM module consists of 128 KByte Logic Tile units, holding access control
function for each tile, and AHB slave interface.

Clock Reset
17

Clock Reset Generator

The Clock Reset Generator generates clocks and resets required for the sub block in
the Application Domain.

Other
18

Interrupt Output

For the main purpose of debugging, this function outputs interrupts which occur in
the APP_DSP block for the processors in the SYSIOP block and the GNSS block.

3.13.4.3

Register List
Table APP-816 APP_DSP Register List

Address

Register NameType

Description

Initial Value

0x0E002040

PID

RO

Processor ID-

0x0E002044

DSP_SLEEPINGROSLEEPING Signal Monitor0

0x0E002048

WD_TIM_RES

RO

Watchdog Timer Status0

0x0E010000

BUS_ERROR0WO

BUS ERROR Clear Register0

0x0E010004

BUS_ERROR1RO

BUS ERROR Cause Register (Error Type)00x0E010008

BUS_ERROR2RO

BUS ERROR Cause Register (Master ID)

0

0x0E012004

ACNV_P0_DST_{0-7}

RW

Address Converter (ADSP0)-

ACNV_P1_DST_{0-7}

RW

Address Converter (ADSP1)-

ACNV_P2_DST_{0-7}

RW

Address Converter (ADSP2)-

ACNV_P3_DST_{0-7}

RW

Address Converter (ADSP3)-

ACNV_P4_DST_{0-7}

RW

Address Converter (ADSP4)-

ACNV_P5_DST_{0-7}

RW

Address Converter (ADSP5)-|
0x0E012020
0x0E012024|
0x0E012040
0x0E012044|
0x0E012060
0x0E012064|
0x0E012080
0x0E012084|
0x0E0120A0
0x0E0120A4|
0x0E0120C0－985/1293－

CXD5602 User Manual

0x0E013000

BUS_SNOOP_DISABLE

RW

Exclusive Access Control

1

0xE0043000

Timer

RW

Refer to Section 3.13.4.7-

0xE0044000

Watchdog Timer

RW

Refer to Section 3.13.4.8-

0xE0045000

Interrupt controller

RW

Refer to Section 3.13.4.6-

For details, refer to Section of the Interrupt (3.3).

－986/1293－

CXD5602 User Manual

3.13.4.4

Cortex®-M4 processor with FPU

The APP_DSP equips six Cortex®-M4 processors with FPU. On the APP_DSP Bus Matrix, regardless of theendianness of the processor, byte lanes in the little endian are used.
Table APP-817 describes the functions of the Cortex®-M4 processor with FPU.
Table APP-817 Cortex®-M4 processor with FPU Function List
Function

Description

Memory Protection Unit (MPU)

Memory Protection Unit is equipped. It can control eight independent areas.

Floating Point Unit (FPU)

A calculation function of single precision floating point number is supported.

Nested Vectored Interrupt Controller (NVIC)

The NVIC supports 128 interrupts.
The priority of each interrupt can be set in 256 steps.

Wakeup Interrupt Controller (WIC)

Wakeup Interrupt Controller (WIC) is equipped.

WIC Support Signal

The WIC interface uses NMI, EDBGRQ, RXEV, and IRQ[127:0] to detect
Wakeup Interrupts.

Trace Support Level

The ITM, TPIU, DWT trigger, and counter are supported. The ETM andHTM are not supported.

Debug Support Level

All debug functions except for data matching are supported.

Bit-bandA bit-band function is not supported in this system.

For Intellectual Property cores (IP cores) offered by ARM Limited, refer to the following references.
Arm® Cortex®-M4 Processor Technical Reference Manual

Cortex®-M4 Devices Generic User Guide



ARMv7-M Architecture Reference Manual－987/1293－

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3.13.4.5

Processor ID

Processor ID register is used for each processor to recognize its own ID. Each processor can obtain its own ID byaccessing the address, which can be seen the same from each processor, to read the register. (Each processor
cannot access the ID of other processors.)
Table 3.31 20 shows Processor ID registers which can be seen from each processor.
Table APP-818 Register List
Address

Register Name

Bit Field

Type

Bit

Name
0x0E002040

PID

PID

InitialDescription

Value
RO

[3:0]

（1*）

Processor ID（1*）

Each processor can read the value which areindicated in Table APP-819.

Table APP-819 Processor List
Processor Name

Processor ID

ADSP0

2

ADSP1

3

ADSP2

4

ADSP3

5

ADSP4

6

ADSP5

7

3.13.4.6

Interrupt Controller

The 128 bit interrupt signals are connected to each processor. By using the interrupt controller, confirmation of
the interrupt state, interrupt enable or disable, and the polarity reverse of the interrupt can be performed.
Since the control registers of the interrupt controller for each processor are in the Private Peripheral Bus area, they
can be accessed in Privileged Mode only. For details, refer to Section of Interrupt (3.3).

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3.13.4.7

Timer

As general-purpose timers, Dual input Timers of AMBA® Design Kit Technical Reference Manual are equipped.
One timer for every processor, six timers in total are equipped. Since the control registers of the timer for eachprocessor are in the Private Peripheral Bus area, they can be accessed in Privileged Mode only.
For detailed control method, refer to AMBA® Design Kit Technical Reference Manual.
The base address of the control register is 0xE0043000. Each control register can be accessed with the same
address from each processor.

3.13.4.8

Watchdog Timer

As Watchdog Timers, Watchdog units of AMBA® Design Kit Technical Reference Manual are equipped.
One timer for every processor, six timers in total are equipped. Since the registers of the Watchdog Timer for eachprocessor are in the Private Peripheral Bus area, they can be accessed in Privileged Mode only.
For detailed control method, refer to AMBA® Design Kit Technical Reference Manual.
The base address of the control register is 0xE0044000. Each control register can be accessed with the same
address from each processor.
WDTRES signals of each Watchdog Timer are not connected to the reset signals of the corresponding processor,
but to the NMI. (Enable control of the WDTRES signals can be performed.)
Furthermore, 1 bit signal which is ORed among all WDTRES signals of the ADSP are connected to the WIC of
the ADSP through the interrupt controller of each ADSP. The same 1 bit signal is also connected to the System
and I/O Processor.

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Application Processor
ADSP0
WDT

WDTINTInterrupt input
Register

128

NMI

WDTRESADSP1
WDT

WDTINTInterrupt input
Register

128

ADSP2
WDTINTInterrupt input
Register

128

ADSP3
WDTINTInterrupt input
Register

128

ADSP4
WDTINTInterrupt input
Register

128

ADSP5
WDTINT

Cortex-M4(PID6)IRQ
NMI

WDTRES

WDT

Cortex-M4(PID5)IRQ
NMI

WDTRES

WDT

Cortex-M4(PID4)IRQ
NMI

WDTRES

WDT

Cortex-M4(PID3)IRQ
NMI

WDTRES

WDT

Cortex-M4(PID2)
IRQ

Interrupt input
Register

128

Cortex-M4(PID7)IRQ
NMI

WDTRES

to System and I/O Processor
WD_TIM_RES[5:0]

Figure APP-138 WDTRES Connection
All the WDTRES signal status of the ADSP can be confirmed by reading the registers.

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Table APP-820 WDTRES Register List
Address

Register Name

Bit Field

Type

Bit

InitialName
0x0E002048

3.13.4.9

WD_TIM_RES

Description

Value

ReservedRO[31:6]

0Reserved

wd_tim_res_5

RO

[5]

0

Reset status of Watchdog Timer of ADSP5

wd_tim_res_4

RO

[4]

0

Reset status of Watchdog Timer of ADSP4

wd_tim_res_3

RO

[3]

0

Reset status of Watchdog Timer of ADSP3

wd_tim_res_2

RO

[2]

0

Reset status of Watchdog Timer of ADSP2

wd_tim_res_1

RO

[1]

0

Reset status of Watchdog Timer of ADSP1

wd_tim_res_0

RO

[0]

0

Reset status of Watchdog Timer of ADSP0SLEEPING Signal Monitor

You can confirm whether each ADSP is in stopped state (Sleep-now or Sleep-on-exit mode) or not by reading
registers shown below.
Table APP-821 SLEEPING Signal Register List
Address

Register Name

Bit Field

Type

Bit

Name
0x0E002044

DSP_SLEEPING

InitialDescription

Value

ReservedRO[31:6]

0Reserved

dsp_sleeping_5

RO

[5]

0

Stopped state of ADSP5

dsp_sleeping_4

RO

[4]

0

Stopped state of ADSP4

dsp_sleeping_3

RO

[3]

0

Stopped state of ADSP3

dsp_sleeping_2

RO

[2]

0

Stopped state of ADSP2

dsp_sleeping_1

RO

[1]

0

Stopped state of ADSP1

dsp_sleeping_0

RO

[0]

0

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3.13.4.10

Debug Function

For debugging of each ADSP, Serial Wire Debug (two-wire protocol) can be used. It supports the following
functions.
Table APP-822 Debug Function List
Function Name

Description

Multi-Core-Debug

Embedded multi-core debug function is supported.

System-Debug

System debug function is supported. Without halting the ADSP, debug access to the memories is possible.

Debugger

AS Integrated Development Environment of Embedded multi-core,
YDC advice LUNA II (customized for CXD5602) environment can be used.
Arm® DS-5 environment and DSTREAM as debug adaptor are supported. (The number of processors
which can be debugged simultaneously is limited.)

FPB

Eight-breakpoint function is equipped including FPB (4K) in the configuration of Cortex®-M4 processor
with FPU. FPB unit contains the following components:
・Two literal comparators
Two literal comparators for matching against literal loads from Code space, and remapping to acorresponding area in System space.
・Six instruction comparators
Six instruction comparators for matching against instruction fetches from Code space, and remapping to acorresponding area in System space. Alternatively, you can configure the comparators individually toreturn a Breakpoint Instruction (BKPT) to the processor core on a match, to provide hardware breakpoint
capability.

DWT

Four-watchpoint function is supported including a reduced DWT (7K) to the configuration of Cortex®-M4
processor with FPU.

ITM

Instrumentation Trace Macrocell (ITM) function in Cortex®-M4 processor with FPU is supported.

TRACE

Data tracing and software tracing functions using ITM/DWT features of Cortex®-M4 processor with FPU
are supported. Clock synchronized signals are output from Tracedata.

AUTH

Debug I/F Authentication function is supported.

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3.13.4.11

I/D Multiplexor

Master ports of the ICode and DCode of each ADSP are connected to a master port.
When the ICode and the DCode access the master port simultaneously, DCode has a higher priority than ICode.

3.13.4.12

Address Map

Figure APP-139 shows a map showing how to access resource of the APP_DSP via buses.
For external access of each ADSP, there are three AHP Lite master ports, which can be seen as the Application
Processor View. ICode bus is used for instruction fetch of the code memory region (0x00000000 - 0x1FFFFFFC),
DCode bus is used for data and the debug access of the code memory region (0x00000000 - 0x1FFFFFFF), andSystem bus is used for instruction fetch, data, and the debug access of the address regions (0x20000000 0xDFFFFFFF and 0xE0100000 - 0xFFFFFFFF). Please note that 0x22000000 - 0x23FFFFFF region and
0x42000000 - 0x43FFFFFF region of the Application Processor View cannot be accessed.
The Application Processor View’s three regions: 0x0000000 - 0x0FFFFFFF region, 0x2000000 - 0x2FFFFFFF
region, and 0x4000000 - 0x4FFFFFFF region are mapped in 0x0000000 - 0x0FFFFFFF region. Then, using
address converter, the 0x00000000 - 0x000FFFFF region can be remapped, being controlled by the program, as
the APP Window, GNSS Window, and SYS Window.

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Application Processor
View

APP View

0xFFFFFFFF

0xFFFFFFFF

PhysicalDestination

CPU Internal(511MB)
0xE0045000

0xE0010000
0xE0000000
0x90000000

0x80000000

0xE0044000
PPB(1MB)

0xE0043000

0x0FFFFFFF

Reserved

Interrupt Controller(4KB)

Reserved

Watch Dog Timer（4KB）

0x0E305000

0x0E300000

Timer
(4KB)

SPI-Flash(256 MB)0x80000000

SPI-Flash(256 MB)

0x0E203000
0x0E202000
0x0E201000
0x0E200000

SDIO
eMMC
USB
Reserved

0x0E103000
0x0E102000
0x0E101000
0x0E100000

0x60000000

IMG_PERIIDMAC
2D Graphics
CIS I/F
Reserved

0x0E025000
0x0E024000

0x50000000

System bus Strictly Ordered(256MB)
0x40000000

0x20000000

Audio(20KB)
Reserved

0x90000000

0x0E105000

0x30000000

PhysicalDestination

0x0E021000
0x0E020000

System bus(256MB)

Crypto(AES)
Crypto(AES)(12KB)ADMAC
Reserved(48KB)

Reserved
0x0E014000
0x0E013000
0x0E012000
0x0E011000
0x0E010000

SMP_GEN_REG
SMP_ADR_CONVSMP_CRG
SMP_BUSERR_REG
Reserved(52KB)

0x0E003000
0x0E002000
0x0E001000
0x0E000000
0x10000000

0x10000000

0x0C000000

ICode bus / DCode bus(256MB)

0x08000000

0x04000000
0x00100000
0x00000000

0x00000000

Reserved

0x10000000
APP Window(64MB)GNSS Window(64MB)SYS Window(64MB)

0x0C000000

0x08000000

0x04000000

area 15 (64KB)...
area 1 (64KB)
area 0 (64KB)

Address Converter
programmable to
SYS Window/
GNS Window/
APP Window
area

SMP_UNPROT_GEN_REG
SMP_RAM_CTRL
SMP_PROT_REG

APP Window(64MB)GNSS Window(64MB)SYS Window(64MB)

0x0D180000
0x0D160000
0x0D140000
0x0D120000
0x0D100000
0x0D0e0000
0x0D0c0000

Reserved

0x0D0a0000
0x0D080000
0x0D060000
0x0D040000
0x0D020000
0x0D000000

SMP_RAM11(128KB)
SMP_RAM10(128KB)
SMP_RAM09(128KB)
SMP_RAM08(128KB)
SMP_RAM07(128KB)
SMP_RAM06(128KB)
SMP_RAM05(128KB)
SMP_RAM04(128KB)
SMP_RAM03(128KB)
SMP_RAM02(128KB)
SMP_RAM01(128KB)
SMP_RAM00(128KB)
Reserved

0x0C000000

Figure APP-139 Address Map－994/1293－

CXD5602 User Manual

3.13.4.13

Address Converter

Address converter offers the function that converts address signals from each ADSP into 96 MByte of region in
total, when the address signals are within 1 MByte of region from 0x00000000 to 0x000FFFFF. The remapped
regions are from 0x04000000 to 0x05FFFFFF, from 0x08000000 to 0x09FFFFFF, and from 0x0C000000 to
0x0DFFFFFF, which are 32 MByte individually.

0x10000000
32MB

APP Window
32MB
0x0C000000
32MB

GNS Window
32MB
0x08000000
32MB

SYS Window
32MB
0x04000000

Reserved
0x00000000 – 0x000FFFFF 1MB

virtual region
input address

0x00000000

output address

Figure APP-140 Input-Output Addresses of Address Converter
Address converter can be set on each ADSP, furthermore, on 16 areas of each 64 Kbyte individually. As Figure
APP-141 indicates, address converter realizes the above conversion function that identifies areas by using input
address bit [19:16] and replaces output address bits [27:26] and [24:16] with set values against the areas. As theconversion is performed by every 64 Kbyte, an input address less than 64 Kbyte corresponding to the input
address bit [15:0] becomes to be an output address without conversion. In addition, address signals are transferredwith no latency from input to output.

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Input Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0

0

0

0

0

0

0

0

0

0

0

0

8

7

6

5

4

3

2

1

0

2

1

0

Area SelectConversion enabled when theaddress is 1MB from the
beginning.

Area
SelectConversion Setting Registers

0x0

Value for Area0

0x1

Value for Area1

0xF

Value for AreaF
10 9

bit

Output Address

Address[15:0]

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 900

00：Reserved
01：SYS Window
10：GNS Window
11：APP Window

0

0

8

7

6

5

4

3

0

Start Window 32MB Area

Figure APP-141 Address Conversion Operation Scheme
Timing control function of reflecting the address converter setting is not equipped. For this reason, set valuechange must be performed during the period that there are no bus transactions of the target ADSP between theaddress area before conversion and the address area after conversion. Any accesses to undefined addresses areprohibited.
Table APP-823 shows address conversion registers.

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Table APP-823 Address Conversion Registers
Address

Register Name

Bit Field

Type

Bit

Name
0x0E012004

ACNV_P<N>_DST_0

AREA_1

InitialDescription

Value
RW

[26:16]0x001+<N>*0x020

Destination address after conversion of
ADSP<N> area 1 (64 – 128 KByte address
area)

AREA_0RW[10:0]

0x000

Destination address after conversion of
ADSP<N> area 0 (0 – 64 KByte address
area)

0x0E012008

ACNV_P<N>_DST_1

AREA_3RW[26:16]0x003+<N>*0x020

Destination address after conversion of
ADSP<N> area 3 (192 - 256 KByte address
area)

AREA_2RW[10:0]

0x002

Destination address after conversion of
ADSP<N> area 2 (128 - 192 KByte address
area)

0x0E01200C

ACNV_P<N>_DST_2

AREA_5RW[26:16]0x005+<N>*0x020

Destination address after conversion of
ADSP<N> area 5 (320 - 384 KByte address
area)

AREA_4RW[10:0]

0x004

Destination address after conversion of
ADSP<N> area 4 (256 - 320 KByte addressarea)

0x02012010

ACNV_P<N>_DST_3

AREA_7RW[26:16]0x007+<N>*0x020

Destination address after conversion of
ADSP<N> area 7 (448 - 512 KByte address
area)

AREA_6RW[10:0]

0x006

Destination address after conversion of
ADSP<N> area 6 (384 - 448 KByte address
area)

0x0E012014

ACNV_P<N>_DST_4

AREA_9RW[26:16]0x009+<N>*0x020

Destination address after conversion of
ADSP<N> area 9 (576 - 640 KByte address
area)

AREA_8RW[10:0]

0x008

Destination address after conversion of
ADSP<N> area 8 (512 - 576 KByte address
area)

0x0E012018

ACNV_P<N>_DST_5

AREA_B

RW[26:16]+<N>*0x020

0x00B

Destination address after conversion of
ADSP<N> area B (704 - 768 KByte addressarea)－997/1293－

CXD5602 User Manual

AREA_A

RW[10:0]

0x00A

Destination address after conversion of
ADSP<N> area A (640 - 704 KByte address
area)

0x0E01201C

ACNV_P<N>_DST_6

AREA_D

RW[26:16]0x00D+<N>*0x020

Destination address after conversion of
ADSP<N> area D (832 - 896 KByte address
area)

AREA_C

RW[10:0]

0x00C

Destination address after conversion of
ADSP<N> area C (768 - 832 KByte address
area)

0x0E012020

ACNV_P<N>_DST_7

AREA_F

RW[26:16]0x00F+<N>*0x020

Destination address after conversion of
ADSP<N> area F (960 - 1024 KByte
address area)

AREA_ERW[10:0]

0x00E

Destination address after conversion of
ADSP<N> area E (896 - 960 KByte address
area)

Note: about <N>
E.g., ADSP0 means that N = 0, ADSP1 means that N = 1, in the same way, ADSP5 means that N = 5.
Examples of Address Conversion
Below are setting examples showing conversion from 0x00000000 - 0x0001FFFF region into 0x0D000000 0x0D01FFFF region which is seen from ADSP0, and conversion from 0x00000000 - 0x0001FFFF region into
0x0D020000 - 0x0D03FFFF region which is seen from ADSP1.
ACNV_P0_DST_0 = 0x07010700
ACNV_P1_DST_0 = 0x07030702
Figure APP-142 and Figure APP-143 show these conversion schemes.

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Input Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0 0 0 00 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1

8

7

6

5

4

3

2

1

0

2

1

0

0x00000x0001

Area
SelectConversion Setting Registers

0x0 1

1

1

0

0

0

0

0

0

0

0

0x1 1

1

1

0

0

0

0

0

0

0

1

10 9

8

7

6

5

4

3

2

1

0

Address[15:0]

ACNV_P0_DST_0.AREA_0 = 0x700
ACNV_P0_DST_0.AREA_1 = 0x701
bit

Output Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
1 1
1 0 0 0 0 0 0 0 0
0 0 0 00
1 1
1 0 0 0 0 0 0 0 1

8

7

6

5

4

3

0x0D00
0x0D01Figure APP-142 Example of Address Conversion: Conversion of Bit Assignment for ADSP0

APP Window

0x0D020000
0x0D010000
0x0D000000

APP Window
0x0D040000
0x0D030000
0x0D020000

64KB
64KB

0x0C000000

0x0C000000

0x00010000
0x00000000

64KB
64KB
ADSP0
input address

0x00000000

64KB
64KB

ADSP0
output address

0x00010000
0x00000000

64KB
64KB
ADSP1
input address

0x00000000

ADSP1
output address

Figure APP-143 Example of Address Conversion: Conversion Address Map for ADSP0 and ADSP1－999/1293－

CXD5602 User Manual

3.13.4.14

Bus Matrix

APP_DSP has two multi-layer AHB matrixes. APP MAIN Bus matrix uses a processor as a master, and has
SRAM with protection features as a slave. APP SUB Bus matrix has a connection interface for three sub blocks:
PWD_APP_AUD, APP_IMG, and APP_PER mainly used for PWD_APP, and has data of each functional block
inside APP_DSP and control interface. Figure APP-137 shows the connection overview.
Only when simultaneous accesses to a single slave occurs, arbitration operates according to the multi-layer AHB
matrix. The algorithm of the arbitration is round-robin.

3.13.4.15

Exclusive Load/Store

Monitoring and controlling of exclusive accesses to slaves are performed.
One monitoring of access per APP SRAM tile (12 in total) and one monitoring of access from APP MAIN Bus to
APP SUB Bus are performed.
By setting the register, this function can be enabled or disabled.
When BUS_SNOOP_DISABLE.bus_snoop_disable = 1'b1, all accesses receive “success” response.
Switch BUS_SNOOP_DISABLE at the timing when LDREX/STREX is ensured not to be issued. In the casethat it was switched while LDREX or STREX are in use, the snooping of the Bus will be finished.
When BUS_SNOOP_DISABLE.bus_snoop_disable = 1'b1, Bus Snooper is reset. Held status is cleared. (Onlyinternal flag is cleared.)
Table APP-824 Exclusive Access Register
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x0E013000

BUS_SNOOP_DIS

bus_snoop_disable

RW

[0]

1

Exclusive Load/Store Disable register
1: Disable

ABLE

0: Enable

3.13.4.15.1

Monitoring Exclusive Accesses to SRAM

The following shows the features of monitoring exclusive accesses to SRAM.
In the case that there is an exclusive read (ExR), the address will be snooped.

Only first address per APP SRAM tile can be snooped. Until the snooping of the first address is released, thesecond and subsequent exclusive reads (ExRs) are ignored. In addition, only one master can obtain the
exclusive access right.



The target address of monitoring must be Word address. When monitoring an exclusive access, the data
monitor size is word even if the data access size is any of byte, halfword, or word.

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In the case that “failure” has been retuned as a result of exclusive access, write to the slave has not been
performed.

Success case of exclusive access

The snooping is released after an exclusive write (ExW) is issued from the master obtaining exclusive accessright to the target address to snoop. At this time, if exclusion process to the target address to snoop has beensuccessful, “success” will be returned. (refer to Figure APP-144)



An exclusive read access always receives “success” response. That is, “success” is returned even during one
exclusive read access’s snooping, another exclusive read access has occurred. After the other exclusive readaccess’s occurrence, “success” is returned to the exclusive write access to the target address to snoop, issued
from the master obtaining exclusive access right. (refer to Figure APP-145)

APP SRAM N

Access phase

ExW
A0
MID0

ExR
A0
MID0

Respons phase

D0

D1

success

success

snoop_mid

MID0snoop_addr

A0snoop_flag
exfail_flag

Figure APP-144 Success Case 1 of Exclusive Access

APP SRAM N

Access phase

ExR
A0
MID0

Respons phase

ExR
A1
MID0
D0

success

ExW
A0
MID0
D0

success

snoop_mid

MID0snoop_addr

A0

D1

success

snoop_flag
exfail_flag

Figure APP-145 Success Case 2 of Exclusive AccessFailure case of exclusive access

In the case that a usual write access (not an exclusive write access) occurs to a target address to snoop,
exclusive access processing is failed and the exclusive write access is blocked.
“Failure” will be returned at the timing of an exclusive write access from the master with the exclusive
access right. (refer to Figure APP-146)



In the case that an exclusive write access (ExW) occurs from the master without the exclusive access right to－1001/1293－

CXD5602 User Manuala target address, “failure” will be returned. (refer to Figure APP-147)
In the case that an exclusive write access (ExW) occurs to an address that is not a target to snoop, “failure”
will be returned at the timing of an exclusive write access from the master with the exclusive access right.
(refer to Figure APP-148)

For all failure cases, write to the slave is not performed.

Write invalid

APP SRAM N

Access phase
Respons phase

W
A0
MID1

ExR
A0
MID0
D0

ExW
A0
MID0
D2

D1

success

failsuccess

snoop_mid

MID0snoop_addr

A0snoop_flag
exfail_flag

Figure APP-146 Failure Case 1 of Exclusive Access

Write invalid

APP SRAM N

Access phase
Respons phase

ExR
A0
MID1

ExW
A0
MID0

ExR
A0
MID0
D0

success

D0

ExW
A0
MID1
D1

D2

fail

success

snoop_mid

MID1

snoop_addr

A0

success

snoop_flag
exfail_flag

Figure APP-147 Failure Case 2 of Exclusive Access

Write invalid

APP SRAM N

Access phase
Respons phase

ExW
A1
MID0

ExR
A0
MID1
D0

D1

fail

success

snoop_mid

MID1

snoop_addr

A0snoop_flag
exfail_flag

Figure APP-148 Failure Case 3 of Exclusive Access－1002/1293－

CXD5602 User Manual

3.13.4.15.2

Monitoring Exclusive Accesses to APP SUB Bus

The following shows the features of monitoring of exclusive accesses to APP SUB Bus.


“Failure”

will

be

returnedtotheexclusive

write(ExW).

However,

in

the

case

that

BUS_SNOOP_DISABLE.bus_snoop_disable=1'b1, “success” will be returned. Even if for failure cases,
write to the slave is performed.
“Success” will be returned to the exclusive read (ExR).

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CXD5602 User Manual

3.13.4.16

Start and Stop Sequence of ADSPThis section explains power supply, clock, and ADSP’s recommended start and stop sequence including reset
control.
Precaution:
Cortex®-M4 processor with FPU has multiple clocks and resets. In this section, when without specific description
hereinafter, “clock” and “reset” means clock and reset of Cortex®-M4 processor with FPU core.
Read-modify-write operation to registers is needed so that bits other than designated bits of the write register will
not be changed.
Perform ADSP’s start control in the following order.
step1

Turn ON the power domain PWD_APP or supply clocks if

For power supply control, refer to the PMU chapter.

required.
step2

Turn ON the power domain PWD_APP if required.

Refer to 3.13.4.16.2 section.

step3

Start the ADSP.

Refer to 3.13.4.16.3 section.

Perform the ADSP’s stop control in the following order.
step1

Stop the ADSP.

Refer to 3.13.4.16.6 section.

step2

Turn OFF the power domain PWD_APP_DSP if required.

Refer to 3.13.4.16.7 section.

step3

Stop the clock, turn OFF the power domain PWD_APP if

For power supply control, refer to the PMU chapter

required.

3.4.

3.13.4.16.1

Start of Clock Supply for APP

Control the clock supply using System and I/O Processor.


Precondition
The power supply of the power domain PWD_APP must be ON. (For power supply control, refer to the
PMU chapter 3.4.)

1. Clock supply setting for APP
Control clock division ratio and clock source using the API.
2. Start of clock supply
APP_CKEN.APP=1 (CK_APP supply starts)
APP_CKEN.AHB=1 (CK_APP_AHB supply starts)
APP_CKEN.MCLK=1 (CK_APP_MCLK supply starts (only when AUDIO is used))－1004/1293－

CXD5602 User Manual

3.13.4.16.2

Power Supply ON for PWD_APP_DSP

For power supply control, refer to the PMU chapter 3.4.

3.13.4.16.3

ADSP Startup

Control the ADSP startup using System and I/O Processor or ADSP other than the target ADSP.
Note: about <N>
E.g., ADSP0 means that N = 0, ADSP1 means that N = 1, in the same way, ADSP5 means that N = 5.
Precondition
The power supply of the power domain PWD_APP and PWD_APP_DSP must be ON. (For power
supply control, refer to the PMU chapter 3.4.)

1. Clock division ratio setting
GEAR_AHB.gear_m_ahb= arbitrary (division ratio denominator write)
GEAR_AHB.gear_n_ahb= arbitrary (division ratio numerator write)
2. Clock supply (Initialization of internal circuit)
CK_GATE_AHB.ck_gate_dsp<N>=1
3. Clock stop
CK_GATE_AHB.ck_gate_dsp<N>=0
4. ADSP start preparation
Transfer the program codes to the APP SRAM, and do the address converter setting.
(For address converter, refer to 3.13.4.13 section.)
5. Reset release
RESET.xrs_dsp<N>=1
6. Clock supply
CK_GATE_AHB.ck_gate_dsp<N>=1

3.13.4.16.4

Clock Frequency Change

1. Clock division ratio setting
GEAR_AHB.gear_m_ahb= (division ratio denominator)
GEAR_AHB.gear_n_ahb= (division ratio numerator)－1005/1293－

CXD5602 User Manual

3.13.4.16.5

Reset Assert and Release

Control Reset Enable and Release using System and I/O Processor or ADSP other than the target ADSP processor.
Note: about <N>
E.g., ADSP0 means that N = 0, ADSP1 means that N = 1, in the same way, ADSP5 means that N = 5.
Precondition
The ADSP must be in SLEEPING state so that uncompleted accesses will not remain in buses. (Refer tothe PMU chapter 3.4 and 3.13.4.9 section.)

1. Reset assert
RESET.xrs_dsp<N>=0
2. Clock stop
CK_GATE_AHB.ck_gate_dsp<N>=0
3. Reset release
RESET.xrs_dsp<N>=1
4. Clock supply
CK_GATE_AHB.ck_gate_dsp<N>=1

3.13.4.16.6

ADSP Stop

Control ADSP stop using System and I/O Processor or ADSP other than the target ADSP.
Note: about <N>
E.g., ADSP0 means that N = 0, ADSP1 means that N = 1, in the same way, ADSP5 means that N = 5.
Precondition
The ADSP must be in SLEEPING state so that uncompleted accesses will not remain in buses. (Refer to the PMU
chapter 3.4 and 3.13.4.9 section.)
1. Reset assert
RESET.xrs_dsp<N>=0
2. Clock stop
CK_GATE_AHB.ck_gate_dsp<N>=0

3.13.4.16.7

PWD_APP_DSP Power Supply OFF

For power supply control, refer to the PMU chapter 3.4.

－1006/1293－

CXD5602 User Manual

3.14 SYSIOP Clock and Reset Control
3.14.1

Function Overiew

The System and IOP Domain (referred to as “SYSIOP” hereinafter) is responsible for overall system control.
Centered around the Arm® Cortex®-M0+, it equips IO Configuration, DMAC, RTC, a common communication
I/F that supports I2C/SPI/UART, and the HOSTIFC, etc. for communication with the external host. These areconnected together via the SYSTEM Bus.
The performance such as the transfer rate depends on the combination of the X'tal Oscillator clock frequency andvoltage mode (High Performance mode/Low Power mode). The following describes a function overview using the
X'tal Oscillator clock frequency operating at 26 MHz as an example.
The SYSIOP offers the following functions.
System and I/O Processor
This is the processor block (referred to as “SYSCPU” hereinafter) that is centered around the Arm® Cortex®-M0+.
The following functions are equipped.
Arm® Cortex®-M0+

The communication unit that performs communication between the Application Processor and CPU,and between the GNSS DSP and CPU

Interrupt input register



Timer





AMBA® Design Kit (ADK) SP804



Two channel support



One Timer module for each processor (Total: Six Timers)

Watchdog Timer

AMBA® Design Kit (ADK) SP805



One channel for each processor (Total: Six Watchdog Timers)

System and I/O Processor Memory

256 KByte SRAM



operating frequency
High Performance mode: Up to 97.5 MHz



Low Power mode: Up to 32.5 MHz

SYSTEM Bus
A 32 bit multi-layer AHB bus matrix. Connects the blocks within the SYSIOP to each other and other Domains.

－1007/1293－

CXD5602 User Manual

Equips an HW protection function that uses a master ID, and an access detection (error response) function to thepower supply OFF area.
I/O Configuration
An I/O terminal control function. For details, refer to Section 3.1.
GPIO
Performs GPIO control of pins and selection/detection control of pins used for interrupts. The following functions
are equipped.


GPIO control

Pin selectionExternal interrupt selectionEvent detection control

For details, refer to Section 3.2.
DMAC
Equips the four following DMACs that are used according to the application.
SYDMAC: memory to memory transfer and Crypto-engine

SYSUBDMAC: Crypto-engine, SPI-FLASH Interface and Configurable I/O

SDMAC: Sensor Engine

HDMAC: Host Interface

RTC
The timer block that counts the time using the RTC clock. For details, see Section 3.6.
COMMIFHas each of the interface circuits of the I2C/SPI/UART.
I2C Interface for Configurable I/OCommunication speeds
High Performance mode: up to 400 Kbit/s

Low Power mode: up to 400 Kbit/s

SPI Interface for Configurable I/OArm® PrimeCell® Synchronous Serial Port (PL022)



Communication speeds
High Performance mode: up to 9.750 Mbit/s

Low Power mode: up to 7.8 Mbit/s

UART interfaces for Configurable I/OPrimeCell® UART (PL011)



Communication speeds－1008/1293－

CXD5602 User ManualHigh Performance mode: up to 3 Mbit/s

Low Power mode: up to 2 Mbit/s

SPI Flash Controller
The main memory interface that supports the Quad SPI FLASH. For details, refer to Section 0.
HOSTIFC
The I/F block for communication with the CXD5602’s external host. In addition to supporting the I2C/UART/SPI
communication I/F, sequential control is also possible for reduced power consumption.
Debugger I/F
A debugger interface circuit. It has a user authentication function that uses a debug path.

－1009/1293－

CXD5602 User Manual

3.14.2

Power Supply Control

The SYSIOP block is divided into the three power domains of PWD_CORE, PWD_SYSIOP, andPWD_SYSIOP_SUB. The power supply domains that correspond to each function block of the SYSIOP are as
follows:

PWD_CORE

256 KByte SRAM in System Control and I/O Processor Memory

PWD_SYSIOP

System and I/O Processor



DMAC (SYDMAC, HDMAC, SDMAC)HOSTIFC

Debugger I/F

FREQDISCRTC

PWD_SYSIOP_SUBCOMMIF Block

SPI-FLASH Interface



128 KByte ROM in System Control and I/O Processor Memory

Crypto Engine in System Control and I/O Domain

SYSUBDMAC－1010/1293－

CXD5602 User Manual

3.14.3Clock and Reset Control

Using clock control, clock switching, frequency control by frequency division switching, and clock supply/stop
can be performed. Using reset control, reset assert/release of each block can be performed. The API is used for thecontrol.

3.14.3.1

SYSIOP Clock Configuration Diagram

Figure SYSIOP Clock and Reset Control-149 shows the SYSIOP clock configuration diagram. Within the figure,the SEL(number), DIV(number), and CG(SYS/SUB number) are linked to the numbers within Table SYSIOPClock and Reset Control-827, Table SYSIOP Clock and Reset Control-832, and Table SYSIOP Clock and ResetControl-833. For areas where the register names are directly indicated in the figure, refer to the descriptions ineach corresponding Section.

－1011/1293－

CXD5602 User Manual

RCOSC
XOSC
SYSPLL

0
1
2
3

1/2
1/3
1/4
1/5

ck_rf_pll_1

0
1

CKSEL_ROOT.CPU_PLL_DIV5(Refer to GNSS)

0
1
2
3

CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4

RTC_CLK_IN(32.768kHz)
RF_CLK_IN

ck_cpu_bus

1/M

ck_cpu_bus_gear_1

DCLK
SCLK
FCLK

CKSEL_ROOT.STAT_CLK_SEL4L

0
1

System andI/O Processor

HCLK

DIV(0)CKSEL_ROOT.SEL_RF_PLL_0

1/M

SYSTEM Bus

ck_ahb_gear

HCLK

DIV(1)

1/M

ck_co m_gear

CG(SUB04)

DIV(4)

CG(SUB1)CKGATECG(SUB03)
CG(SUB10)

CG(SUB05)

CG(SUB00)

CG(SYS05)

CG(SYS06)

CG(SYS07)

CG(SUB02)

0
1
2
3

1/2
1/3
1/4

1/M
ck_scu_xtal

1/2

DIV(3)CKSEL_SCU.SEL_SCU_XTAL

1/250

0
1

ck_32k_preReserved

CG(SUB07)

ck_sf c_sf clk_gear

0
1
2
3

ck_sf c_hclk_lo w_gear

CG(SUB08)
CG(SUB09)

CG(SYS14)

CG(SUB06)

1/250

1/M

UART1
UARTCLK

CK
GATE

PCLK

CK
GATE

I2CCLK

I2C2
PCLK

AHB/APB
BusBridge

CK_AHB_BRG_COMIF
CK
GATE

SDMAC

CK
GATE

HCLK

CK
GATE

HCLK

CK
GATE

HCLK

CK
GATE

HCLK

CK
GATE

HCLK

CK
GATE

SFCLK

CK
GATE

SFC_HCLKHDMACSYDMACSYSUBDMACSPI Flash Controller

CK
GATE

CK_BRG_SCU

Crypto

CK
GATE

HCLK

ck_ho st_gear

SPI2

DIV(5)

SEL(0)PCLKCKSEL_SCU.SEL_SCU

CKSEL_SCU.SEL_SCU_32K

ck_hostSSPCLKCKGATE

AHB/AHBBusBridge
ck_scu_pre

SPI2_SCK
0
1
2
3

SPI0

CK
GATE

0
1
SEL(1)

SSPCLK

ck_ho st2CG(SYS02)

ReservedCK
GATE

CG(SYS17)01
23

CG(SYS03)

SEL(3)CG(SYS16)
0
1

CG(SYS00)

SEL(2)CG(SYS01)

CG(SYS15)

CK
GATE

PCLK

CK
GATE

I2CCLK

CK
GATE

PCLK

CK
GATE

UARTCLK

CK
GATE

PCLK

CK
GATE

SEQ_CLK

I2C3

UART0

SEQ

PCLK
PCLK_CGCG(SYS04)
AP_CLK_IN

1/M

1/2
1/4
SEL(5)

0
1
2
3

Reserved

01
2
3

ck_apb_gear

CG(SYS08)

DIV(2)

ck_freqdis_pre

CG(SYS09)
CG(SYS10)CG(SYS11)

SEL(4)CG(SYS12)CKGATE

CK_BRG_HOST

CK
GATE

CK_APB

AHB/APB
BusBridge

FreqDisc
PCLK

CK
GATE

CK_REFCKGATEISI G[0]CKGATEISI G[2]CKGATEISI G[1]ISI G[6]

RTC0
1/250
Reserved01
2
3Register
ck_rtc_pre

CG(SYS13)

PCLK

CK
GATE

CK_RTCCK_RTCCKSEL_ROOT.PMU_STAT_CLK_SEL4

CK_RTC_INV

RTC1Register
PCLK
CK_RTCCK_RTCCK_RTC_INV

AHB/APB
BusBridge

Figure SYSIOP Clock and Reset Control-149 SYSIOP Clock Configuration Diagram

3.14.3.2

Overview of SYSIOP Maximum Frequency

The following tables describe the maximum operating frequencies of the System and I/O Processor and the
SYSTEM Bus – the main function blocks of the SYSIOP. Each has a different maximum operating frequency
depending on the supported XOSC frequency and the SYSPLL oscillating frequency. The SYS SRAM within the
SYSIOP has the same operating frequency as the System and I/O Processor. The element circuits (BackUp SRAM,
DMAC, Crypto…) directly connected to the SYSTEM Bus or via a synchronous bridge basically have the same
maximum frequencies as the SYSTEM Bus.
For the maximum operating frequencies of external communication interfaces, refer to each respective Part. For
the XOSC and SYSPLL frequency settings, refer to Section 3.5.
Table SYSIOP Clock and Reset Control-825 XOSC (26 MHz), High Performance Mode
Clock source
frequency
System and I/O Processor
System Bus

M Hz
M Hz
M Hz

SYSPLL
195.000
156.000
97.50078.00048.75039.000－1012/1293－

XOSC
26.00026.00026.000

RCOSC
8.192
8.192
8.192

RTC
0.032768
0.032768
0.032768

CXD5602 User Manual

Table SYSIOP Clock and Reset Control-826 XOSC (26 MHz), Low Power Mode
Clock source
frequency
System and I/O Processor
System Bus

M Hz
M Hz
M Hz

SYSPLL
195.000
156.000
32.50031.20032.50031.2003.14.3.3

Clock Switching Confirmation

3.14.3.3.1

Function Details

XOSC
26.00026.00026.000

RCOSC
8.192
8.192
8.192

RTC
0.032768
0.032768
0.032768

The clock source of the clock supplied to each block can be changed using the API. The selected clock can be
confirmed by reading the register.

－1013/1293－

CXD5602 User Manual

3.14.3.3.2

Register Descriptions

Table SYSIOP Clock and Reset Control-827 shows the clock switching status registers. Make sure to use RW
registers as RO registers.
Table SYSIOP Clock and Reset Control-827 Clock Switching Status Registers
Address

0x041004CC

Register

Bit Field

Type

Bit

InitialDescription

Name

Name

CKSEL_S

ReservedRO[31:22]0

ReservedYSIOP

SEL_FD_PLL

RW[21:20]

2'b00

Indicated as SEL(5) in Figure SYSIOP Clock and

Value

Reset Control-149
FREQDISC clock source switching
2'b00: SYSPLL clock not divided
2'b01: SYSPLL clock divided by 2
2'b10: SYSPLL clock divided by 4
2'b11: SYSPLL clock divided by 4
ReservedRO[19:18]0Reserved

SEL_FREQD

RW[17:16]

2'b00

Indicated as SEL(4) in Figure SYSIOP Clock andReset Control-149

IS

FREQDISC clock source switching
2'b00: RCOSC
2'b01: XOSC
2'b10: The frequency divided clock selected by
CKSEL_SYSIOP.SEL_FD_PLL
2'b11: Prohibited setting
ReservedRO[15:14]0Reserved

SEL_I2CS

RW[13:12]

2'b00

Indicated as SEL(3) in Figure SYSIOP Clock andReset Control-149
I2C3 clock source switching
2'b00: The clock selected by
CKSEL_SYSIOP.SEL_HOST2
2'b01: The frequency divided clock selected by
CKSEL_SCU.SEL_SCU_XTAL
2'b10: SYSPLL
2'b11: Prohibited setting
ReservedRO[11:9]

0－1014/1293－

ReservedCXD5602 User Manual

SEL_UART0

RW

[8]

0

Indicated as SEL(2) in Figure SYSIOP Clock andReset Control-149
UART0 clock source switching
0: The clock selected by
CKSEL_SYSIOP.SEL_HOST2
1: Reserved
Reserved

RO

[7:3]

0

Reserved

SEL_HOST2

RW

[2]

0

Indicated as SEL(1) in Figure SYSIOP Clock andReset Control-149
HOSTIFC clock source switching
0:

The

clock

selectedby

CKSEL_SYSIOP.SEL_HOST
1: XOSC
SEL_HOST

RW

[1:0]

2'b00

Indicated as SEL(0) in Figure SYSIOP Clock andReset Control-149
HOSTIFC clock source switching
2'b00: RCOSC
2'b01: RCRTC (RCOSC frequency divided by 250)
2'b10:

The

clock

selectedby

CKSEL_ROOT.SEL_RF_PLL_1_DIV
2'b11: RTC Clock0x041004D0

CKSEL_S

ReservedRO[31:1]

0ReservedYSIOP_S

SEL_UART1

RW

[0]

0

Indicated as SEL(6) in Figure SYSIOP Clock andReset Control-149

UB

UART1 clock source switching
1: Reserved
0: The clock selected by CKDIV_COM.CK_COM

3.14.3.4

Clock Frequency Division Switching Confirmation

3.14.3.4.1

Function Details

Using the API, the frequency division ratio of the target clock can be changed. You can confirm the currently
selected frequency division ratio from the register.
Clock Frequency Division for the System and I/O Processor, AHB, and APB
The clock (ck_cpu_bus_gear_1) for the System and I/O Processor, the AHB clock (ck_ahb_gear), and the APB
clock (ck_apb_gear) are frequency divided clocks of the ck_cpu_bus. The frequency division of the ck_cpu_bus isdescribed by the following equations.

－1015/1293－

CXD5602 User ManualFrequency division of ck_cpu_bus


ck_cpu_bus_gear_1= frequency division (A)

ck_ahb_gear= frequency division (A) x frequency division (B)

ck_apb_gear= frequency division (A) x frequency division (B) x frequency division

(C)
Note:
Refer to Table SYSIOP Clock and Reset Control-828 for frequency division (A), Table SYSIOP Clockand Reset Control-829 for frequency division (B), and Table SYSIOP Clock and Reset Control-830 for
frequency division (C).
Table SYSIOP Clock and Reset Control-828 System and I/O Processor Frequency Division Setting
CKDIV_CPU_DSP_BUS.CK_M0

Frequency Division(A)

0

1

1

2

2

3

3

4

...

Register value + 1

28

29

29

30

30

31

31

32

Table SYSIOP Clock and Reset Control-829 AHB Clock Frequency Division Setting
CKDIV_CPU_DSP_BUS.CK_AHB

Frequency Division(B)

0

1

1

2

2

4

3

8

4

16

5

Prohibited setting

6
7

Table SYSIOP Clock and Reset Control-830 APB Clock Frequency Division Setting
CKDIV_CPU_DSP_BUS.CK_APB

Frequency Division(C)

0

1

1

2

2

4

－1016/1293－

CXD5602 User Manual3

8Clock Frequency Division for SPI Flash Controller
The frequency of the clock for the SPI Flash Controller is determined by the ck_cpu_bus frequency and theregister setting value. The following equations show the frequency division of the clock for the SPI Flash
Controller.
Frequency division of the clock for the SPI Flash Controller based on the ck_cpu_bus



ck_sfc_sfclk_gear= frequency division(D)

ck_sfc_hclk_low_gear= frequency division(D) x 2

Note:
Refer to Table SYSIOP Clock and Reset Control-831 for the frequency division(D).
Table SYSIOP Clock and Reset Control-831 Frequency Division Setting of Clock for the SPI Flash Controller
CKDIV_CPU_DSP_BUS.SFC_HCLK_LOW

Frequency
Division(D)

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

16

11

32

12

64

13

128

14

256

15

512

Caution upon Setting the Frequency Division
When the SPI Flash Controller is not used, set CKDIV_CPU_DSP_BUS.SFC_HCLK_LOW to “0”.

－1017/1293－

CXD5602 User Manual

3.14.3.4.2

Register Descriptions

Table SYSIOP Clock and Reset Control-832 shows the frequency division setting status registers of each clock.
Make sure to use the RW registers as RO registers.
Table SYSIOP Clock and Reset Control-832 Frequency Division Setting Status Registers
Address

Register Name

Bit Field

Type

Bit

Name
0x041004D8

CKDIV_CPU_

SFC_HCL

DSP_BUSK_LOW

InitialDescription

Value
RW

[31:28]0

Indicated as DIV(3) in Figure SYSIOP Clock andReset Control-149
Frequency division setting (ratio against System andI/O Processor clock) of ck_sfc_sfclk_gear

0: divided by 1
1: divided by 2
2: divided by 3
3: divided by 4
4: divided by 5
5: divided by 6
6: divided by 7
7: divided by 8
8: divided by 9
9: divided by 10
10: divided by 16
11: divided by 32
12: divided by 64
13: divided by 128
14: divided by 256
15: divided by 512
CK_SFC_HCLK_LOW

isalwaysCK_SFC_SFCLK frequency divided by 2.
E.g.
0: CK_SFC_SFCLK (divided by 1)
CK_SFC_HCLK_LOW(divided by 2)
3： CK_SFC_SFCLK(divided by 4)
CK_SFC_HCLK_LOW(divided by 8)
ReservedRO[27:26]0－1018/1293－

ReservedtheCXD5602 User Manual

CK_APB

RW[25:24]2'b00

Indicated as DIV(2) in Figure SYSIOP Clock andReset Control-149
Frequency division setting (ratio against AHB clock)of APB clock
0: divided by 1
1: divided by 2
2: divided by 4
4: divided by 8
ReservedRO[23:19]0Reserved

CK_AHB

RW[18:16]0

Indicated as DIV(1) in Figure SYSIOP Clock andReset Control-149
Frequency division setting (ratio against CPU clock)of AHB clock
0: divided by 1
1: divided by 2
2: divided by 4
3: divided by 8
4: divided by 6
5, 6, 7: Prohibited settings
ReservedRO[15:5]

0Reserved

CK_M0

RW

[4:0]

0

Indicated as DIV(0) in Figure SYSIOP Clock andReset Control-149
Frequency division setting (ratioagainst ck_cpu_bus)
of System and I/O Processor
0: divided by 1
1: divided by 2…
30: divided by 31
31: divided by 32
0x041004DCCKDIV_COM

ReservedRO[31:5]

0－1019/1293－

ReservedCXD5602 User Manual

CK_COM

RW

[4:0]

0

Indicated as DIV(4) in Figure SYSIOP Clock andReset Control-149
Frequency division setting (ratio against ck_cpu_bus)
of SYSIOP_SUB communication system
0: divided by 1
1: divided by 2
2: divided by 3…
29: divided by 30
30: divided by 31
31: divided by 32
0x041004E0

CKDIV_HOS

ReservedRO[31:5]

0Reserved

TIFC

CK_HOS

RW

[4:0]

0

Indicated as DIV(5) in Figure SYSIOP Clock andReset Control-149

TIFC

HOSTIFC frequency switching setting
0: divided by 1
1: divided by 2…
30: divided by 31
31: divided by 32
0x04100518

GEAR_STAT

ReservedRO[31:3]

0Reserved

SFC_STA

RO

[2]

0

Indicated as DIV(3) in Figure SYSIOP Clock andReset Control-149

T

Updatestatusof

CKDIV_CPU_DSP_BUS.SFC_HCLK_LOW
setting value
0: Update completed
1: Update in progress
AHB_STRO[1]

0

Indicated as DIV(1) in Figure SYSIOP Clock andReset Control-149

AT

UpdatestatusCKDIV_CPU_DSP_BUS.CK_AHB setting value
0: Update completed
1: Update in progress－1020/1293－

ofCXD5602 User Manual

CPU_STRO[0]

0

Indicated as DIV(0) in Figure SYSIOP Clock andReset Control-149

AT

Update status of CKDIV_CPU_DSP_BUS.CK_M0
setting value
0: Update completed
1: Update in progress

3.14.3.5

Clock Enable Confirmation

3.14.3.5.1

Function Details

Using the API, supply/stop control of the clocks supplied to each block can be performed.

－1021/1293－

CXD5602 User Manual

3.14.3.5.2

Register Descriptions

Table SYSIOP Clock and Reset Control-833 shows the clock enable status registers. Make sure to use the RW
registers as RO registers.
Table SYSIOP Clock and Reset Control-833 Clock Enable Status Registers
Address

Register Name

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100714

SYSIOP_CKENReserved

RW[31:18]0Reserved

HOSSPI

RW

[17]

0

Indicated as CG(SYS17) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for SPI2
HOSI2C

RW

[16]

0

Indicated as CG(SYS16) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for I2C3
HOSTIFC_SEQ

RW

[15]

0

Indicated as CG(SYS15) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for HOSTIFC processor
BRG_SCU

RW

[14]

0

Indicated as CG(SYS14) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for AHB-APB bridge
between PWD_SYSIOP and PWD_SCUSYSIOP_RTC

RW

[13]

1

Indicated as CG(SYS13) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for RTC1 and APB
RCOSC_OUT

RW

[12]

0

Indicated as CG(SYS12) in Figure

SYSIOP

Clock

and

Reset

referenceclock

Control-149
Clockenablefor(RCOSC) of FREQDISC－1022/1293－

CXD5602 User Manual

AP_CLK

RW

[11]

0

Indicated as CG(SYS11) in Figure

SYSIOP

Clock

and

Reset

referenceclock

Control-149
Clockenablefor(AP_CLK) of FREQDISC
RTC_ORG

RW

[10]

0

Indicated as CG(SYS10) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for reference clock (RTC
Clock) of FREQDISC
FREQDIS

RW

[9]

0

Indicated as CG(SYS09) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for measurement target
clock of FREQDISC
APB

RW

[8]

1

Indicated as CG(SYS08) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clockenable

for

the

APB

withinPWD_SYSIOPAHB_DMAC2

RW

[7]

0

Indicated as CG(SYS07) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for SYDMAC
AHB_DMAC1

RW

[6]

0

Indicated as CG(SYS06) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for HDMAC
AHB_DMAC0

RW

[5]

0

Indicated as CG(SYS05) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for SDMAC
BRG_HOST

RW

[4]

0

Indicated as CG(SYS04) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for the AHBAPB bridge thatconnects the MainAHB Bus and APB
module of the HOSTIF－1023/1293－

CXD5602 User Manual

I2CS

RW

[3]

0

Indicated as CG(SYS03) in Figure

SYSIOP

Clock

and

Reset

HOSTIFC

I2C3

Control-149
Clockenableforcommunication
PCLK_HOSTIFC

RW

[2]

0

Indicated as CG(SYS02) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for the APB of SPI2 and
I2C3
PCLK_UART0

RW

[1]

0

Indicated as CG(SYS01) in Figure

SYSIOP

Clock

and

Reset

Control-149
UART0 APB clock enable
UART0

RW

[0]

0

Indicated as CG(SYS00) in Figure

SYSIOP

Clock

and

Reset

Control-149
UART0 communication clock enable
0x04103420

SYSIOP_SUB_C

ReservedRO[31:17]

0

ReservedKEN

COM_UART_PC

RW

[16]

0

Indicated as CG(SUB10) in Figure

SYSIOP

LK

Clock

and

Reset

Control-149
Clock enable for APB of UART1ReservedRO[15:10]0Reserved

SFC_HCLK_LO

RW

[9]

1

Indicated as CG(SUB09) in Figure

SYSIOP

W

Clock

and

Reset

Control-149
Clock enable for AHB of SPI Flash
Controller
SFC_SFCLK

RW

[8]

1

Indicated as CG(SUB08) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for clock generation of SPI
Flash Controller－1024/1293－

CXD5602 User Manual

SFC_HCLK

RW

[7]

1

Indicated as CG(SUB07) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for AHB synchronous
bridge between SYSTEM Bus and SPI
Flash Controller
Reserved

RW

[6]

0

Reserved

I2CM_SUB

RW

[5]

0

Indicated as CG(SUB05) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for I2C2
SPIM

RW

[4]

0

Indicated as CG(SUB04) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for SPI0
UART1

RW

[3]

0

Indicated as CG(SUB03) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for UART1
AHB_DMAC3

RW

[2]

0

Indicated as CG(SUB02) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for SYSUBDMAC
COM_BRG

RW

[1]

0

Indicated as CG(SUB01) in Figure

SYSIOP

Clock

and

Reset

Control-149
Clock enable for AHB asynchronous
bridge master of I2C2, UART1, and SPI0
AHB_BRG_COM

RW

[0]

0

Indicated as CG(SUB00) in Figure

SYSIOP

IF

Clock

and

Reset

Control-149
Clock enable for AHB asynchronous
bridge slave of I2C2, UART1, and SPI0

3.14.3.6

Reset and Control

3.14.3.6.1

SYSIOP Reset Configuration Diagram

Figure SYSIOP Clock and Reset Control-150 SYSIOP Reset Configuration Diagramshows the reset configuration
diagram of SYSIOP.

－1025/1293－

CXD5602 User Manual

Auto(PWD_SYSIOP Power Domain ON)

System andI/O Processor

RST_CPU_P0_X

RST_CPU_SYS_XSYSIOP_MAIN_BUS
HRESTnAuto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
RST(0)SPI0NSSPRST
PRESTnUART1nUARTRST

RST(3)PRESETn

I2C2
PRESETn

RST(8)

AHB/APB
BusBridge
PWD_RESET0.PWD_SYSIOP_SUB

SDMAC
HRESETn

HDMAC
HRESETn

SYDMACHRESETn

SYSUBDMAC
HRESETn

SPI Flash Controller
HRESETn

RST(1)

AHB/AHBBusBridge

CryptoXRST_SK

RST(2)SPI2
RST(5)PRESTn

I2C3
PRESETn

UART0
RST(7)nUARTRSTPRESETn

SEQ
RST(6)XRST_HOS_SEQ
PRESETn

AHB/APB
BusBridge

FreqDisc
PRESETn

RTC0
PRESETn

RTC1
PRESETn

AHB/APB
BusBridge

Figure SYSIOP Clock and Reset Control-150 SYSIOP Reset Configuration Diagram－1026/1293－

CXD5602 User Manual

3.14.3.6.2

Register Descriptions

The reset of each block can be controlled using the registers. Since the control flow varies according to thefunction block, refer to each block’s Section. Table SYSIOP Clock and Reset Control-834 shows the reset control
registers.
Table SYSIOP Clock and Reset Control-834 Reset Control Registers
Address

Register

Bit Field Name

Type

Bit

InitialDescription

Value
0x04100700

SWRESET_BUS

ReservedRO[31:17]

0

Reserved

XRST_PMU_I2C

RW

[16]

1

Indicated as RST(9) in Figure SYSIOPClock and Reset Control-150

M

Reset for I2C40 Reset is performed
1: Reset release
ReservedRO[15:12]0

Reserved

XRST_I2CM_SU

RW

[11]

0

Indicated as RST(8) in Figure SYSIOPClock and Reset Control-150

B

Reset for I2C2
XRST_UART0

RW

[10]

0

Indicated as RST(7) in Figure SYSIOPClock and Reset Control-150
Reset for UART0
XRST_HOSTIFC

RW

[9]

0

Indicated as RST(6) in Figure SYSIOPClock and Reset Control-150_ISOP

Reset for HOSTIFC Sequencer
XRST_HOSTIFC

RW

[8]

0

Indicated as RST(5) in Figure SYSIOPClock and Reset Control-150
Reset for HOSTIFC
Reserved

RO

[7:6]

0

Reserved

XRST_UART1

RW

[5]

0

Indicated as RST(3) in Figure SYSIOPClock and Reset Control-150
Reset for UART1Reserved

RO

[4:3]

0

Reserved

XRST_SAKE

RW

[2]

0

Indicated as RST(2) in Figure SYSIOPClock and Reset Control-150
Reset for Crypto(Clefia)－1027/1293－

CXD5602 User Manual

XRST_SFC

RW

[1]

1

Indicated as RST(1) in Figure SYSIOPClock and Reset Control-150
Reset for SPI Flash Controller
XRST_SPIM

RW

[0]

0

Indicated as RST(0) in Figure SYSIOPClock and Reset Control-150
Reset for SPI0－1028/1293－

CXD5602 User Manual

3.15 Audio Codec
3.15.1

Audio Codec Overview and Features

The Audio Codec, when combined with the CXD5247, realizes Audio Codec functions.
The following is an overview of its functions.


Audio Mic input

Direct connection to CXD5602


Via CXD5247


two channel digital microphone input (only if CXD5247 is not used).
four channel analogue microphones or eight channel digital microphone

Digital audio amplifierEquips the ΔΣ modulator of the S-Master to output noise-shaped audio signals

Combined with the S-Master Modulator of the CXD5247, it comprises an audio digital amplifier circuit

512fs/1024fs support

I2S I/F

Equips two independent sets of I2S I/F (I2S0, I2S1)

Supports Master/Slave modes. When the CXD5602 is the Slave, the signal data can be transferred fromthe external clock domain to the system clock domain of the CXD5602 using the SRC (Sampling Rate
Converter) inside the Audio Codec

CXD5247 I/F

Audio digital amplifier (512fs) mode: two channels of 16fs 6 bit ΔΣ modulator output are converted
from parallel to serial by the serializer circuit, and output as 1 bit serial data

Audio digital amplifier (1024fs) mode: two channels of 32fs 6 bit ΔΣ modulator output are converted
from parallel to serial by the serializer circuit, and output as 1 bit serial data

Outputs the PDM _CLK (64fs) as the frame signal of the the PDM data input (PDM_IN) and ΔΣ
modulator output (PDM_OUT)

By switching the mode, the I/F pin with the CXD5247 can be switched to Digital Mic I/F (twochannels)

AHB I/F

Equips a total of three AHB master side I/Fs that connect to the AHB bus slave, which are used for theI2S I/F and Mic I/F

Equips a DMAC that performs single transfer of audio dataEquips two sets of DMAC for Reading and Writing for the AHB for the I2S I/F

Equips a DMAC for Writing within the Mic I/F AHB－1029/1293－

CXD5602 User Manual

3.15.2

Audio Codec Block Diagram

Figure 3.15-1 Audio Codec Block Diagram－1030/1293－

CXD5602 User Manual

3.15.2.1

I2S Signal Path

in

Codec
DSP
in

IO

I2S Data IN

I2S Data OUT

L/R

in

I2S I/F
SRC-1
out

out

in

in

L/R

out

Pre
FilterIO

IO

I2S Data OUT

I2S Data IN

in

I2S I/Fout SRC-2

out

in

L/R

L/R

out

in

BUS
Master(I2S0)

BUS
MasterAHB-BUS

IO

BLEND
DNC

(I2S0)

Figure 3.15-2 I2S Signal Path
The two lines of I2S input signals are re-sampled to the Audio Codec’s system clock at the I2S I/F and SRC
circuits. After processing the signals by the Codec DSP, and the signals are passed to CXD5247 (the Speaker
output path). For the input of the Codec DSP, either the I2S I/F, SRC output, or the signal processed on the ADSP
can be selected. The I2S I/F and SRC outputs can also be used for audio signal processing that uses the ADSP bywriting them to the SRAM on the AHB BUS via the BUS master. Via the BUS master, the signals processed by
the ADSP are subject to bandwidth limitation by the Pre Filter (BLF) and then re-sampled to the BCK/LRCK of
the I2S at the SRC circuit, and output from the terminals as I2S output signals.
I2S I/F, SRC
The I2S I/F converts the I2S format input and output signals into the format required for processing them at the
Audio Codec. The SRC converts the data rate in cases when the data rates inside the Audio Codec and I2S format
signal are asynchronous. The I2S I/F has two operations modes, namely the Master Mode and Slave Mode. In the
Master Mode, the I2S input and output are synchronized with the system clock of the Audio Codec. In Slave
Mode, the I2S input and output and the system clock operate asynchronously. For details, refer to Section
3.15.6.8and Section 3.15.6.8.2.
Pre Filter
This Pre Filter is used for cases when the Audio Codec signal is output in the I2S format. The operation of the Pre－1031/1293－

CXD5602 User Manual

Filted changes according to the format conversion operation of the I2S I/F and SRC. For details, refer to Section
3.15.6.10.
Codec DSP
Two signal lines from the I2S I/F, the SRC, or the I2S_BUS_IF processed at the ADSP are selected and input. At
the Codec DSP, signal processing such as volume control, EQ control, and Clear Stereo are performed. For details,
refer to Section 3.15.6.11.

3.15.2.2

Mic Signal Path

Figure 3.15-3 Mic Signal Path
The multiplexed and serialized Mic input signal transferred from the CXD5247 is divided into a maximum ofeight channels (four channels of L/R) of 1 bit signals at the deserialization circuit. The signals are processed at the
Cascade integrator-comb (CIC) Filter circuit and converted into linear PCM signals, and the outputs of CIC filters{1,2} is output

from the CXD5247 as Speaker (SP) signals.

On the other hand, the CIC filter {1,2,3,4} output signals are processed at the Decimation Filter circuit and written
to the SRAM via the Mic signal BUS Master and used for audio signal processing at the ADSP as well. The
signals processed at the ADSP are processed at the Pre Filter (BLF) via the BUS Master, and then re-sampled to
the BCK clock domain of the I2S at the I2S I/F, SRC circuits for output from the terminal as I2S outputs signals.
When directly using a two-channel Digital Mic without use of the CXD5247, the signals are input to the CIC
filters {3, 4} from the PDM_IN via the DMIC I/F. The signals from the Decimation Filter circuit can be output in
the I2S format via the I2S I/F, SRC circuit. For details on controlling the Mic input block, refer to Section3.15.6.6
and Section 3.15.6.7.
Deserialization－1032/1293－

CXD5602 User ManualThis circuit deserializes the Mic input signal transferred from the CXD5247 and divides it into a maximum ofeight channels. There are two operation modes for the Mic input signal, namely 64fs (eight Mics) and 128fs (fourMics), and all transfer channels can be separately routed to the deserialized output. The output is a 1 bit PDM
signal.
DMIC I/F
When operating the Audio Codec with only the CXD5602 and without using the CXD5247, the Digital Mic(DMIC) can be used as a means to input the audio signal. The DMIC I/F is a circuit that divides the signal fromthe external DMIC that changes with both edges of the MCK_DMIC clock into the L/R signals in which the datachange at the rising edge of MCK_DMIC Also, to operate the DMIC, the MCK_DMIC output of the Audio Codec
must be sent outside the CXD5602. The PDM_CLK and MCK_DMIC are exclusive output. For details, refer to
Section 3.15.5.3.
CIC filter
A three-stage CIC filter in the CXD5602 converts the 1 bit ΔΣ modulated Mic signal that is output from the
CXD5247 to a 24 bit linear PCM signal. Using one circuit, the L/R signals are processed, where the input rate is
selectable from 64fs/128fs and output rate is selectable from 4fs/8fs. The CIC filters {3, 4} can select the DMIC
signal from the DMIC I/F.
Decimation Filter
The output of the CIC filter circuit allows selection between 4fs/8fs, but the Decimation Filter circuit is for
reducing this output rate further. Comprised of a three-stage CIC filter, the output is selectable from 4fs, 2fs, and1fs. It equips two circuits, each of which processes four channels. For details, refer to Section 3.15.6.12.

3.15.2.3

Speaker Output Path

The speaker output path is designed to provide a stereo audio digital output which is converted to an analogue
output by the CXD5247.

－1033/1293－

CXD5602 User Manual

Figure 3.15-4 SP Signal Path
Using the BLEND circuit, the DNC output (two lines) is subtracted from the Codec DSP output, and via the
Digital Amplifer Pre-Process circuit followed by the serialization circuit, the PDM signal is transferred to the
CXD5247.
BLEND (Mixer) /Beep
The BLEND (Mixer) circuit combines the Codec DSP output and Mic input together. In addition to ordinarytransfer of the L channel and R channel, transfer of (L+R)/2 and (L-R)/2 can be selected. For details on the BEEP
function, refer to Section 3.15.6.11.5.
Digital Amplifier Pre-Process circuit
In combination with the Digital Amplifier Post-Process circuit equipped on the CXD5247, the Amplifier circuit
comprises the Digital Amplifier Post-Process circuit. For details, refer to Section 3.15.6.13.

Serialization
The Serialization circuit converts the 6 bit PDM signal to the 1 bit signal that is transferred to the CXD5247. The
output signal has the two operation modes of 16fs/32fs.
Starting from the rising edge of the PDM_CLK (64fs) that is transferred together, the first 2 bits are the ID, whichin the 16fs transfer mode, change as 11=>00=>00=>00=>10=>00=>00=>00=>11, where the remaining 6 bits of
the 1 PDM_CLK cycle are used for L/R transfer. In the 32fs transfer mode, the ID changes as11=>00=>10=>00=>11. These two transfer modes are determined by the Digital Amplifier Pre-Process setting.

－1034/1293－

CXD5602 User Manual

512fs = 24.576 MHz

MCLK
64fs (3.072 MHz)PDM_CLKRch Data

Lch Data

16fs Mode

0

0

0

ID

ID

PDM_OUT
Lch

32fs Mode

0

0

0

ID

0

0

0

0

0

0

0

0

0

ID

32fs (1536 kHz)

0

0

0

0

0

0

0 D5 D4 D3 D2 D1 D0 0

1

ID

0 D5 D4 D3 D2 D1 D0 0
ID

ID

0

0

0

0

0

0

0

0

0

ID

0

0

0

0

0

0

1

1
ID

ID

16fs (768 kHz)
Rch

ID

ID

ID

ID

ID

ID

1

0 D5 D4 D3 D2 D1 D0 1

0 D5 D4 D3 D2 D1 D0 0

0 D5 D4 D3 D2 D1 D0 1

1 D5 D4 D3 D2 D1 D0 0

0 D5 D4 D3 D2 D1 D0 1

0 D5 D4 D3 D2 D1 D0 0

0 D5 D4 D3 D2 D1 D0 1

1 D5 D4 D3 D2 D1 D0 0

1

8fs (384 kHz)

16fs (768 kHz)

0 D5 D4 D3 D2 D1 D0 0

1 D5 D4 D3 D2 D1 D0 0

1

ID

ID

Figure 3.15-5 Serializer Timing Chart

3.15.3Clock Supply

3.15.3.1

Application with the CXD5247

The Audio Codec block assumes the supply of a 24.576 MHz system clock from the CXD5247. However, inthe case that the function limitations described in Section 3.15.4 are permissible, the Audio Codec can be used by
the CXD5602 alone. In this case, make sure to supply a 24.576 MHz system clock from a X'tal oscillator, etc.
Refer to Chapter *** for the clock setting.

3.15.4Standalone Operation (without the CXD5247)

The Audio Codec block offers its full set of functions in conjuction with the CXD5247, but also supports
standalone use by the CXD5602 without the CXD5247. When using the CXD5602 alone, be cautious of thefollowing points.

3.15.4.1

Function Limitations upon Standalone Use

The following table shows the function limitions when using the CXD5602 alone.

Table 3.15-1

Function Limitations upon Standalone UseFunctionCXD5602+CXD5247

CXD5602 only

Mic input

Digital Mic eight channels or,Digital Mic two channels

Analog Mic four channels
Speaker/

Speaker two channels output

Headphone output

Output is not possible due toproprietary interface

For the Digital Mic connections when using the CXD5602 alone, refer to Section 3.15.5.3.
Whether or not to be able to use I2S I/F is not relevant to using CXD5247.

－1035/1293－

CXD5602 User Manual

3.15.4.2

Clock Supply

The Audio Codec block assumes the supply of a system clock from the CXD5247. However, when the
CXD5602 is used alone, make sure to supply a 24.576 MHz system clock from a X'tal oscillator, etc. which would
have otherwise been supplied from the CXD5247.
For the setting of clock supply, refer to Chapter ***.

3.15.5External Interfaces

3.15.5.1

I2S Interface

3.15.5.1.1

I2S Interface Specifications

Table 3.15-2 I2S Interface Specifications
mode

item

specifications

memo

master mode

Sampling frequency [kHz]48, 96, 192

Synchronzied with CXD5602 internal clock

Bit clock frequency(Sampling frequency) x 64

max: 12.288 MHz

Data format

Left Justified, I2S format

Data bit width [bit]24

In the case of 16 bit, 0 aligned to the lowerbitslave mode

Sampling frequency [kHz]8, 16, 44.1, 48, 96, 192

Not synchronized with CXD5602 internal
clock
Requires setting according to the input
signal frequency range(refer to Section 3.15.6.8)

3.15.5.1.2

Bit clock frequency(Sampling frequency) x 64

Data format

Left Justified, I2S format

Data bit width [bit]24

max: 12.288 MHz

In the case of 16 bit, 0 aligned to lower bit

I2S Timing Chart

BCK
LRCK
DATA

32CLK(@BCK)

32CLK(BCK)

0 [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0

0

0

0

0

0

0

0 [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0

Lch 24bit

Rch 24bit

Figure 3.15-6 I2S Format 24bit－1036/1293－

0

0

0

0

0

0

CXD5602 User Manual

BCK
LRCK

32CLK(BCK)

32CLK(@BCK)

DATA[23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0

0

0

0

0

0

0

0

0 [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0

0

0

0

0

0

0

Rch 24bit

Lch 24bit

Figure 3.15-7 Left Justified 24bit
For details on I2S interface control, refer to Section 3.15.6.8.

3.15.5.2

CXD5247 Interface

3.15.5.2.1

Function Details

The CXD5602 transfers signals between the CXD5247 using a dedicated format. From the CXD5247, the Mic
signals are input, and to the CXD5247, signals for speaker output or headphone output are output. The signals forspeaker output or headphone output can be transferred in either 16fs or 32fs mode, while the Mic input signals canbe transferred in either 64fs (eight Mics) or 128fs (four Mics) mode.

3.15.5.2.2

CXD5247 Interface Timing Chart
512fs = 24.576 MHz

MCLK
64fs (3.072 MHz)PDM_CLKRch Data

Lch Data

16fs Mode

0

0

0

ID

ID

PDM_OUT
Lch

32fs Mode

0

0

0

ID

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0 D5 D4 D3 D2 D1 D0 0

1

ID

0 D5 D4 D3 D2 D1 D0 0
ID

ID

0

0

0

0

0

0

0

0

0

ID

0

0

0

0

0

0

1

1
ID

ID

16fs (768 kHz)
Rch
ID

ID

ID

ID

ID

1

0 D5 D4 D3 D2 D1 D0 1

0 D5 D4 D3 D2 D1 D0 0

0 D5 D4 D3 D2 D1 D0 1

1 D5 D4 D3 D2 D1 D0 0

0 D5 D4 D3 D2 D1 D0 1

0 D5 D4 D3 D2 D1 D0 0

0 D5 D4 D3 D2 D1 D0 1
ID

0

ID

32fs (1536 kHz)1 D5 D4 D3 D2 D1 D0 0

1

8fs (384 kHz)

16fs (768 kHz)

0 D5 D4 D3 D2 D1 D0 0

1 D5 D4 D3 D2 D1 D0 0

1

ID

ID

64fs (3.072 MHz)
64fs Mode

6ch 7ch 8ch 1ch 2ch 3ch 4ch 5ch 6ch 7ch 8ch 1ch 2ch 3ch 4ch 5ch 6ch 7ch 8ch 1ch 2ch 3ch 4ch 5ch 6ch 7ch 8ch

128fs(6.144MHz)

PDM_IN
128fs Mode2ch 3ch 4ch 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch

Figure 3.15-8 CXD5247 Interface (SP) (MIC)
For details on control of the connection interface with the CXD5247, refer to Section 3.15.6.5.

3.15.5.3

Digital Mic Interface

When using the CXD5602 alone, you can connect the Digital Mic via the port that is used as the interface with the
CXD5247. The signal from the Digital Mic interface is selected using CIC3IN_SEL and CIC4IN_SEL. For details,
refer to Section 3.15.6.7.

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Clock forDigital Mic

Audio Codec
L
R

DigitalMic(L)DMIC
I/F

DigitalMic(R)

Digital Mic
signal(OR)

OR

L0

R0

L1

R1

L2

R2

dmic_if
Lch

L0

L1

L2

dmic_if
Rch

R0

R1

R2

Figure 3.15-9 DMIC Timing

3.15.6

Details of Audio Codec Control Registers

3.15.6.1

Address Map

Table 3.15-3 Audio Codec Address Map
offset addressfrom

0x0100to

0x0FFF

Size

Name

comment

4 KByteREG_IF

Control Register(Area 1)

Area

Audio

Codec
Processing
from

0x1000to

0x11FFfrom

0x1200to

0x17FF

0.5 KByte

1.5 KByte

BUS_CTRL_A

Control Register

HB

for DMAC

AHBMSTR_MI

BUS

C

configuration for

I/F

Mic
from

0x1800to

0x1FFF

2 KByteAHBMSTR_I2S

BUS

I/F

0

configuration for
I2S0

from

0x2000to

0x27FF

2 KByteAHBMSTR_I2S

BUS

I/F

1

configuration for
I2S1

from

0x2800to

0x2FFFfrom

0x3000to

0x4FFF

2 KByte------

8 KByteREG_IF

SRAM Area(Area 2)

The 32 bit address offset from the CPU is as follows. To calculate the address from the CPU, add this address
to the offset shown in the table.

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CXD5602 User Manual

Offset: 0x02300000 (Mirror: 0x0E300000)

3.15.6.2

Register Map

Refer to Section 3.15.9.

3.15.6.3

Clock Control

The clock supplied within the Audio Codec can be controlled. The supply of unnecessary clocks will not affectthe operation, but the power consumption will increase. Table 3.15-4 shows a list of the clock supply settings.
Note the following:
1'b0: Clock supply start
1'b1: Clock supply stop (Power Down)
Also, the initial values are all “1'b1”.

Table 3.15-4 Clock Supply Settings
offset addressbitparameter Neme

Block

0x0100[23]

PDN_DSPC

Codec DSP[22]

PDN_DSPS1

SRC 1

[21]

PDN_DSPS2

SRC 2

[20]

PDN_SMSTR

Noise Shaper[16]

PDN_DSPB

Output Filter for SRC1 & SRC2[15]

PDN_DMIC

Digital Mic I/F (without CXD5247)[6]

PDN_AMIC2

CIC filter 1[5]

PDN_AMIC1

CIC filter 2[4]

PDN_AMICEXT

CIC filter 3 and CIC filter 4

MCK_AHBMSTR_EN (offset 0x0104 bit[19]) must be set when transferring the Audio data to the SRAM on
the AHB or when reading out the data from the SRAM on the AHB.
1'b0: AHB I/F for Audio Data disable
1'b1: AHB I/F for Audio Data enable
These settings do not affect the AHB I/F for control.
Regarding the offset 0x0100 bit[10] PDN_MIC, bit[9] PDN_LINEIN, and bit[8] PDN_DAC, use them with
1'b1.
Regarding the Enable/Disable of each function block, refer to the control of each function block that follows.
HALT_INHIBIT (offset 0x0400 bit[19]) can stop the supplied clock when the Codec DSP or SRC terminates－1039/1293－

CXD5602 User Manual

calculation, and when waiting for the subsequent processes.
1'b0: Clock stops during processing wait
1'b1: Clock is always supplied

3.15.6.4

from
CXD5247

Internal Signal Selection
COD_INSEL1
MIC1

MIC2
SERIAL to
MIC3
PARALLEL
MIC4
COD_INSEL2

I2S0

SRC1
(input side)

I2S1

Codec
DSP

SRC2
(input side)

AU_DAT_SEL1
to S-MasterModule
Digital Amplifer
Mod.

Decimation
Filter
COD_INSEL3AHB

BUS I/F
I2S0

BUS I/F
I2S1

SRC1(output side)
AU_DAT_SEL2

BLF

I2S0

I2S1
SRC2
(output side)

Figure 3.15-10 Internal Signal Selector Overview Diagram
By controlling the offset 0x0108 bit[29:28] COD_INSEL1, the Mic signal input to the Codec DSP can beselected. The Mic signal outputs obtained from the connection I/F with CXD5247 are referred to as MIC1, MIC2,
MIC3, and MIC4 hereinafter. Each Mic signal contains two channels for L/R. Regarding the application of MIC1,
MIC2, MIC3, and MIC4, also refer to Section 3.15.6.6.
COD_INSEL1 (offset 0x0108 bit[29:28])
2'b00: Supplies MIC 1 to the Codec DSP
2'b01: Supplies MIC 2 to the Codec DSP
2'b10: Supplies MIC 3 to the Codec DSP
2'b11: Supplies MIC 4 to the Codec DSP－1040/1293－

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By controlling the offset 0x0108 bit[27:26] COD_INSEL2, the signal input to the Codec DSP can be selected.
The input level of the signal selected by COD_INSEL2 can be controlled by the SDIN1_VOL. For information on
the SDIN1_VOL, refer to Section 3.15.6.11.2.
COD_INSEL2 (offset 0x0108 bit[27:26])
2'b00: Selects the SRC1 output
2'b01: Selects the SRC2 output
2'b10: Selects the output selected by AU_DAT_SEL1
2'b11: Selects the output selected by AU_DAT_SEL2
By controlling the offset 0x0108 bit[25:24] COD_INSEL3, the signal input to the Codec DSP can be selected.
The input level of the signal selected by COD_INSEL3 can be controlled by the SDIN2_VOL. For information on
the SDIN2_VOL, refer to Section 3.15.6.11.2.
COD_INSEL3 (offset 0x0108 bit[25:24])
2'b00: Selects the SRC1 output
2'b01: Selects the SRC2 output
2'b10: Selects the output selected by AU_DAT_SEL1
2'b11: Selects the output selected by AU_DAT_SEL2
By controlling the offset 0x0108 bit[22:20] AU_DAT_SEL1, the signal to input to the Codec DSP when the
COD_INSEL2 and COD_INSEL3 are set to “2'b10” can be selected. The output selected by AU_DAT_SEL1 canseparately be used as the I2S output. For information on the I2S output, refer to Section 3.15.6.8.2.
AU_DAT_SEL1 (offset 0x0108 bit[22:20])
3'b000: Selects the MIC1 signal to which the Decimation Filter process is applied
3'b001: Selects the MIC2 signal to which the Decimation Filter process is applied
3'b010: Selects the MIC3 signal to which the Decimation Filter process is applied
3'b011: Selects the MIC4 signal to which the Decimation Filter process is applied
3'b1xx: Selects the BUS I/F1 signal
By controlling the offset 0x0108 bit[22:20] AU_DAT_SEL2, the signal to input to the Codec DSP when the
COD_INSEL2 and COD_INSEL3 are set to “1'b11” can be selected. The output selected by AU_DAT_SEL2 canseparately be used as the I2S output. For information on the I2S output, refer to Section 3.15.6.8.2.
AU_DAT_SEL2 (offset 0x0108 bit[22:20])
3'b000: Selects the MIC1 signal to which the Decimation Filter process is applied
3'b001: Selects the MIC2 signal to which the Decimation Filter process is applied－1041/1293－

CXD5602 User Manual

3'b010: Selects the MIC3 signal to which the Decimation Filter process is applied
3'b011: Selects the MIC4 signal to which the Decimation Filter process is applied
3'b1xx: Selects the BUS I/F2 signal

3.15.6.5

Setting the Connection I/F Setting with the CXD5247

SDES_EN (offset 0x0104 bit[18]) controls the clock supplied to the block that converts SERIAL signals
from the CXD5247 to PARALLEL signals and the block that converts PARALLEL signals to SERIAL signals to
the CXD5247.
SDES_EN (offset 0x0104 bit[18])1'b0: Conversion Function block inactive
1'b1: Conversion Function block active
To use the audio interface for the CXD5247 as a Digital Mic I/F, set this to “1'b0”.
When the audio interface for the CXD5247 is used as a Digital Mic I/F and the SDES_EN is set to “1'b1”, theDigital Mic I/F will operate properly but power for the I/F circuit with the CXD5247 will still be consumed.
FS_CLK_EN (offset 0x0500 bit[24]) sets the output of the PDM_CLK.
FS_CLK_EN (offset 0x0500 bit[24])1'b0: output disable (fixed Low)
1'b1: output enable
PDM_OUT_EN (offset 0x0500 bit[16]) sets the output of the PDM_OUT.
PDM_OUT_EN (offset 0x0500 bit[16])1'b0: output disable (fixed Low)
1'b1: output enable
For the specifications and timing chart of the I/F with the CXD5247, refer to Section 3.15.5.2.

3.15.6.6

Mic Signal Input Block Control

3.15.6.6.1

Reset during setting changes

The settings of the Mic signal input block can be changed as required. Also, there is no need to perform a reset
after making such changes. However, noise may be output during the setting changes. Mute the noise in a
subsequent stage as necessary.

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3.15.6.6.2

Setting the connection I/F with the CXD5247

FS_FS (offset 0x0104 bit[0]) sets the transfer rate of the Mic signals from the CXD5247.
Make sure that this matches the CXD5247 output setting.
FS_FS (offset 0x0104 bit[0])1'b0: 128fs/4 channels
1'b1: 64fs/8 channels
SER_MODE (offset 0x0500 bit[0]) sets the transmission channels of the Mic signals from the CXD5247.
Make sure that this matches the CXD5247 output setting.
SER_MODE (offset 0x0500 bit[0])1'b0: eight channel transmission
1'b1: four channel transmission
The number of transmission channels is uniquely determined by the setting of the transmission rate by the FS_FS.
Set the SER_MODE accordingly.
ADC_FS (offset 0x0204 bit[29:28]) sets the transmission rate of the Mic signals from the CXD5247.
Make sure that this matches the CXD5247 output setting.
ADC_FS (offset 0x0204 bit[29:28])
2'b00: 64fs
2'b01: 128fs
2'b1x: Prohibited setting
Set the ADC_FS in accordance with the transmission rate setting of the FS_FS. For example, when the FS_FS is“1'b0”, set ADC_FS: 2'b01 (128fs).
The following table summarizes the settings.

Table 3.15-5 Mic Mode Settings
Mic Mode

SER_MO

FS_FS

ADC_FS

SEL_OUTx_L/R[2:0]Remarks

DE
64fs (eight Mics)

0

1

0

0-7

Selects one channel from channels 1 to 8

128fs (four Mics)

1

0

1

0-3

Selects one channel from channels 1 to 4.

3.15.6.7

Details of Mic Input Block Control－1043/1293－

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DCMFS (offset 0x0308 bit[31:30]) sets the data rate when the MIC1 and MIC2 input signals are internallyhandled.
DCMFS (offset 0x0308 bit[31:30])
2'b00: Prohibited setting
2'b01: 4fs (192 kHz)
2'b10: 8fs (384 kHz)
2'b11: Prohibited setting
When the DCMFS is set to “2'b10”, the ADC_FS must also be set to “2'b01”.
When the DCMFS is set to “2'b10” and transmitting the Mic data to the AHB, the data rate must be reduced to 4fs
by the Decimation Filter described later in this document.
DCMFS_34 (offset 0x0308 bit[23:22]) sets the data rate when the MIC3 and MIC4 input signals are internallyhandled. The control specifications conform to the DCMFS.
The use of the DCMFS and DCMFS_34 assume the same setting value.
The Mic signals can be selected using the control register of the offset 0x0504.
SEL_OUT1_L (bit[30:28]): Selects the L channel output of the MIC1 signal.
SEL_OUT1_R (bit[26:24]): Selects the R channel output of the MIC1 signal.
SEL_OUT2_L (bit[22:20]): Selects the L channel output of the MIC2 signal.
SEL_OUT2_R (bit[18:16]): Selects the R channel output of the MIC2 signal.
SEL_OUT3_L (bit[14:12]): Selects the L channel output of the MIC3 signal.
SEL_OUT3_R (bit[10:8]): Selects the R channel output of the MIC3 signal.
SEL_OUT4_L (bit[6:4]): Selects the L channel output of the MIC4 signal.
SEL_OUT4_R (bit[2:0]): Selects the R channel output of the MIC4 signal.
The control specifications are as follows. To apply channels 1 to 8, refer toFigure 3.15-8.
offset 0x0504
SEL_OUT1_L (bit[30:28]) , SEL_OUT1_R (bit[26:24]) , SEL_OUT2_L (bit[22:20]),
SEL_OUT2_R (bit[18:16]) , SEL_OUT3_L (bit[14:12]) , SEL_OUT3_R (bit[10:8]),
SEL_OUT4_L (bit[6:4]) , SEL_OUT4_R (bit[2:0])
3'b000: Selects channel 1
3'b001: Selects channel 2:
3'b110: Selects channel 7
3'b111: Selects channel 8－1044/1293－

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INV_AMIC1R (offset 0x0204 bit[31]) and INV_AMIC1L (offset 0x0204 bit[30])
The MIC1 signal can be inverted. INV_AMIC1R inverts the R channel of MIC1 and INV_AMIC1L inverts the L
channel of MIC1.
offset 0x0204
INV_AMIC1R (bit[31]) , INV_AMIC1L (bit[30])1'b0: Not inverted
1'b1: Inverted
INV_AMIC2R (offset 0x0204 bit[15]) and INV_AMIC2L (offset 0x0204 bit[14]) control MIC2,
INV_AMIC3R (offset 0x0208 bit[31]) and INV_AMIC3L (offset 0x0208 bit[30]) control MIC3, and
INV_AMIC4R (offset 0x0208 bit[15]) and INV_AMIC4L (offset 0x0204 bit[14]) control MIC4.
The control specifications are the same as INV_AMIC1R, INV_AMIC1L.
Set the offset 0x0204 bit[26], offset 0x0204 bit[10], offset 0x0208 bit[26], and offset 0x0208 bit[10] each to“1'b0”. Setting them to “1'b1” is prohibited.
CIC1IN_SEL (offset 0x0204 bit[25])1'b0: Normal Setting
1'b1: fixed Low
When CIC1IN_SEL is set to “1'b1”, the signal supplied to MIC1 is fixed to Low.
The specifications of CIC2IN_SEL (offset 0x0204 bit[9]) are the same as CIC1IN_SEL.
CIC3IN_SEL (offset 0x0208 bit[25])1'b0: with CXD5247
1'b1: without CXD5247
When directly connecting the Digital Mic without using the CXD5247, set CIC3IN_SEL (offset 0x0208 bit[25])to “1'b1”. The data of the Digital Mic is supplied as MIC3.
CIC4IN_SEL (offset 0x0208 bit[9])1'b0: with CXD5247
1'b1: without CXD5247
When directly connecting the Digital Mic without using the CXD5247, set CIC4IN_SEL (offset 0x0208 bit[9]) to“1'b1”. The data of the Digital Mic is supplied as MIC4.
When setting CIC3IN_SEL and CIC4IN_SEL to “1'b1” and directly connecting the Digital Mic without using the
CXD5247, the same signal is supplied to MIC3 and MIC4.

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CIC1_GAIN_MODE (offset 0x0204 bit[24]) can switch the gain control register of the MIC input.
CIC1_GAIN_MODE (offset 0x0204 bit[24])1'b0 : controlled by ADC1L_VOL (offset 0x0240 bit[6:0]) and ADC1R_VOL (offset 0x0240 bit[14:8])
1'b1 : controlled by CIC1_LGAIN (offset 0x020C bit[31:16]) and CIC1_RGAIN (offset 0x020C bit[15:0])
CIC2_GAIN_MODE (offset 0x0204 bit[8]) performs control of MIC2.
The control specifications are the same as CIC1_GAIN_MODE. For the addresses of registers that will comeunder control, refer to the descriptions below.
Gain control of MIC3 can be done only by CIC3_LGAIN and CIC3_RGAIN.
Gain control of MIC4 can be done only by CIC4_LGAIN and CIC4_RGAIN.
ADC1L_VOL (offset 0x0240 bit[6:0]) controls the L channel output gain of MIC1 when CIC1_GAIN_MODE is
set to “1'b0”.
ADC1L_VOL (offset 0x0240 bit[6:0])
7'h00: 0dB
7'h3F: -0.05dB
7'h3E: -0.10dB:
7'h03: -6.25dB
7'h02: -6.30dB
7'h01: mute
ADC1R_VOL (offset 0x0240 bit[14:8]) controls the R channel output gain of MIC1 when CIC1_GAIN_MODE
is set to “1'b0”. The control specifications are the same as ADC1L_VOL.
ADC2L_VOL (offset 0x0240 bit[22:16]) controls the L channel output gain of MIC2 when CIC2_GAIN_MODE
is set to “1'b0”. The control specifications are the same as ADC1L_VOL.
ADC2R_VOL (offset 0x0240 bit[30:24]) controls the R channel output gain of MIC2 when CIC2_GAIN_MODE
is set to “1'b0”. The control specifications are the same as ADC1L_VOL.
CIC1_LGAIN (offset 0x020C bit[31:16]) controls the L channel output gain of MIC1 when CIC1_GAIN_MODE
is set to “1'b1”.
The Gain is specified by 20log((CIC1_LGAIN x 2 - 32768) / 32768) (dB).
[Caution] Make sure to use a setting value from 16'h4000 (mute) to 16'h8000 (0dB).
CIC1_RGAIN (offset 0x020C bit[15:0]) controls the R channel output gain of MIC1 when CIC1_GAIN_MODE
is set to “1'b1”.
CIC2_LGAIN (offset 0x0210 bit[31:15]) controls the L channel output gain of MIC2 when CIC2_GAIN_MODE－1046/1293－

CXD5602 User Manualis set to “1'b1”.
CIC2_RGAIN (offset 0x0210 bit[15:0]) controls the R channel output gain of MIC2 when CIC2_GAIN_MODE
is set to “1'b1”.
CIC3_LGAIN (offset 0x0214 bit[31:15]) controls the L channel output gain of MIC3,CIC3_RGAIN (offset 0x0214 bit[15:0]) controls the R channel output gain of MIC3,
CIC4_LGAIN (offset 0x0218 bit[31:15]) controls the L channel output gain of MIC4, and
CIC4_RGAIN (offset 0x0218 bit[15:0]) controls the L channel output gain of MIC4.
The control specifications are the same as CIC1_LGAIN.
Set the following to “1'b0”.
INV_DMIC1L (offset 0x0204 bit[22]) , INV_DMIC1R (offset 0x0204 bit[23]),
INV_DMIC2L (offset 0x0204 bit[6]) , INV_DMIC2R (offset 0x0204 bit[7])INV_DMIC3L (offset 0x0208 bit[22]) can invert the L channel output of MIC3 when not using the CXD5247 anddirectly connecting the Digital Mic.
INV_DMIC3L (offset 0x0208 bit[22])1'b0: Do not invert
1'b1: Invert
INV_DMIC3R (offset 0x0208 bit[23]) can invert the R channel output of MIC3,
INV_DMIC4L (offset 0x0208 bit[14]) can invert the L channel output of MIC4, and
INV_DMIC4R (offset 0x0208 bit[15]) can invert the R channel output of MIC4.
The control specifications are the same as INV_DMIC3L.
CIC1IN_SWAP (offset 0x0204 bit[21]) can swap the L channel and R channel of MIC1.
CIC1IN_SWAP (offset 0x0204 bit[21])1'b0: Normal operation
1'b1: Swaps the L channel and R channel
CIC2IN_SWAP (offset 0x0204 bit[5]) can swap the L channel and R channel of MIC2,CIC3IN_SWAP (offset 0x0208 bit[21]) can swap the L channel and R channel of MIC3, and
CIC4IN_SWAP (offset 0x0208 bit[5]) can swap the L channel and R channel of MIC4.
HPF1_MODE (offset 0x0204 bit[17:16]) can apply an HPF to the MIC1 signal,
HPF2_MODE (offset 0x0204 bit[1:0]) can apply an HPF to the MIC2 signal,
HPF3_MODE (offset 0x0208 bit[17:16]) can apply an HPF to the MIC3 signal, and
HPF4_MODE (offset 0x0208 bit[1:0]) can apply an HPF to the MIC4 signal.

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HPF1_MODE (offset 0x0204 bit[17:16]) , HPF2_MODE (offset 0x0204 bit[1:0]),
HPF3_MODE (offset 0x0208 bit[17:16]) , HPF4_MODE (offset 0x0208 bit[1:0])
2'b00: HPF OFF
2'b01: HPF Cut Off Frequency Low
2'b10: HPF Cut Off Frequency Mid
2'b11: HPF Cut Off Frequency High3.15.6.8

I2S Input/Output Settings

3.15.6.8.1

I2S I/F Settings

SDCK_OUTENX (offset 0x0200 bit[30]) controls the BCK and LRCK outputs when I2S is set to master mode.
SDCK_OUTENX (offset 0x0200 bit[30])1'b0: BCK, LRCK output enable
1'b1: BCK, LRCK output disable
Regarding enable/disable of the outputs, the two lines of I2S cannot be controlled separately.
SD1MASTER (offset 0x0200 bit[29]) sets the mode of the I2S input/output of SRC1.
SD1MASTER (offset 0x0200 bit[29])1'b0: I2S slave mode
1'b1: I2S master mode
SD2MASTER (offset 0x0200 bit[28]) sets the mode of the I2S input/output of SRC2.
The control specifications conform to the SD1MASTER.
DIF1 (offset 0x0200 bit[27]) sets the mode of the I2S input/output of SRC1.
DIF1 (offset 0x0200 bit[27])1'b0: I2S mode
1'b1: Left Justfied mode
[Caution] When DIF1 is set to “1'b1” and used in Left Justified mode, LR_SWAP1 (offset 0x0678 bit[0]) must be
set to “1'b1”.
DIF2 (offset 0x0200 bit[26]) sets the mode of the I2S input/output of SRC2.
The control specifications conform to DIF1.
[Caution] When DIF2 is set to “1'b1” and used in Left Justified mode, LR_SWAP2 (offset 0x0678 bit[1]) must be－1048/1293－

CXD5602 User Manual

set to “1'b1”.
SDOUT1_EN (offset 0x022C bit[2]) controls the I2S Data output of SRC1.
SDOUT1_EN (offset 0x022C bit[2])1'b0: I2S Data output disable
1'b1: I2S Data output enable
SDOUT2_EN (offset 0x022C bit[3] controls the I2S Data output of SRC2.
The control specifications conform to SDOUT1_EN.
SDIN1_EN (offset 0x022C bit[0]) controls the I2S Data input of SRC1.
SDIN1_EN (offset 0x022C bit[0])1'b0: I2S Data input disable
1'b1: I2S Data input enable
SDIN2_EN(offset 0x022C bit[1]) controls the I2S Data input of SRC2.
The control specifications conform to SDIN1_EN.
INV_ASP1L (offset 0x0220 bit[19]) inverts the L channel signal of SRC1.
INV_ASP1L (offset 0x0220 bit[19])1'b0: invert disable
1'b1: invert enable
INV_ASP1R (offset 0x0220 bit[18]) inverts the R channel signal of SRC1.
The control specifications conform to INV_ASP1L.
INV_ASP2L (offset 0x0220 bit[17]) inverts the L channel signal of SRC2.
The control specifications conform to INV_ASP1L.
INV_ASP2R (offset 0x0220 bit[16]) inverts the R channel signal of SRC2.
The control specifications conform to INV_ASP1L.

3.15.6.8.2

I2S SRC Settings

SRC1IN_SEL (offset 0x0200 bit[19:18]) selects the output signal of SRC1.
SRC1IN_SEL (offset 0x0200 bit[19:18])－1049/1293－

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2'b00: Outputs the selection results of AU_DAT_SEL1
2'b01: Outputs the selection results of AU_DAT_SEL2
2'b10: Outputs the Mic signal via the Codec DSP
2'b11 : Outputs the MIX signal via the Codec DSP
Regarding the signal supplied from the Codec DSP, refer to Figure 3.15-10 and Figure 3.15-13.
SRC2IN_SEL (offset 0x0200 bit[23:22]) selects the output signal of SRC2.
The control specifications are the same as SRC1IN_SEL.
SRC1 (offset 0x0200 bit[17:16]) determines the BCK frequency of the SRC1 of I2S.
(1) When SD1MASTER:1'b0 (I2S slave mode):

Table 3.15-6 BCK Support Range by SRC1 (I2S slave mode)
SRC1

BCK Support Range*

LRCK Support Range*

2'b00

Prohibited setting

Prohibited setting

2'b01

512 kHz to 3.072 MHz

8 kHz to 48 kHz

2'b10

3.07 2 MHz (not including) to 6.144 MHz

48 kHz (not including) to 96 kHz

2'b11

6.144 MHz (not including) to 12.288 MHz

96 kHz (not including) to 192 kHz* The frequencies in the above table are center values. As for the specifications of the I2S, the permissible range is
BCK ± 10%. For example, if the center frequency is 3.072 MHz at 2'b01, the upper frequency limit of the input ispermissible up to 3.072 MHz x 1.1 = 3.3792 MHz. As for the lower frequency limit, make sure to observe thevalues in the table.
(2) When SD1MASTER: 1'b1 (I2S master mode):

Table 3.15-7 BCK Output Frequency by SRC1 (I2S master mode)
SRC1

BCK Output Frequency

LRCK Output Frequency

2'b00

Prohibited setting

Prohibited setting

2'b01

3.072 MHz48 kHz2'b10

6.144 MHz

96 kHz2'b11

12.288 MHz

192 kHz

SRC2 (offset 0x0200 bit[21:20]) determines the BCK frequency of the SRC2 of I2S. The behavior changes
according to the SD2MASTER setting, but the control specifications are the same as SRC1.
When the internal signal processing is set to fs = 48 kHz, the SRC1/SRC2 can only be set to “2'b01”. Other
setting values are prohibited. When the internal signal processing is set to fs = 192 kHz, the SRC1/SRC2 canbe set to “2'b01”, “2'b10”, or “2'b11”.
For the settings of the internal signal processing rate, refer to HI_RES_MODE (Section 3.15.6.11).

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To set the I2S output, but not via the SRC, set TEST_IN_089 (offset 0x0400 bit[2:1]).
Filter control of the TEST_IN_089[0]: SRC1 output and filter control of the TEST_IN_089[1] : SRC2 output isperformed.
TEST_IN_089 (offset 0x0400 bit[2:1])
2'b00: Normal Operation (SRC1 and SRC2 Enable)
2'b01: SRC1 Disable (Filter bypass) , SRC2 Enable
2'b10: SRC1 Enable , Disable (Filter bypass)
2'b11: SRC1 Disable (Filter bypass) , SRC2 Disable (Filter bypass)
When not using the SRC function due to the TEST_IN_089 setting, the I2S I/F is used only in Master Mode. Also,
the transfer rate becomes 48 kHz or 192 kHz as designated in the HI_RES_MODE. The transfer rate of 96 kHz is
not available for the output.
Note that TEST_OUT_SIF (offset 0x0400 bit[5:4]) must be set to “2'b00”.
Also, make sure to set MONSEL (offset 0x0400 bit[3:0]) to “4'h0”.

3.15.6.9

Internal SRAM Data Output Mode

For debugging purposes during program development, the SRAM data on the AHB can be output.
By referring to Section 3.15.6.4, make sure to set the SRAM data output as follows with the internal selectors
properly set.


Set HI_RES_MODE to “1'b1”.

In accordance with the I/F of the I2S you use, set the SRC1 or SRC2 to “2'b11”, and further set the I2S I/F to
Master Mode.



Set test_out_sel[1:0] as appropriate.
The settings of test_out_sel (offset 0x0400 bit[7:6]) are as follows:

test_out_sel (offset 0x0400 bit[7:6])
2'b00: Normally used
2'b01: The I2S0 (SRC1) output is internal SRAM data output
2'b10: The I2S1 (SRC2) output is internal SRAM data output
2'b11: The I2S0 and I2S1 outputs are internal SRAM data output
At this time, the SRAM data is output at a 192 kHz data rate from the I2S I/F used.
The SRAM data that can be output is limited to the area accessible by the Audio Codec. For the SRAM area

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accessible by the Audio Codec, refer to the APP Chapter.

3.15.6.10

BLF Settings

When outputting data to the I2S I/F using a data rate lower than the internal processing rate (determined by
HI_RES_MODE), the internal BLF (Band Limiting Filter) block must be used to avoid aliasing.
BLF_EN controls the clock supply to the BLF block.
BLF_EN (offset 0x022C bit[5])1'b0: BLF block clock supply OFF
1'b1: BLF block clock supply ON
When performing I2S output, set BLF_EN to “1'b1”. When set to “1'b0”, the I2S output signal cannot be obtained.
In the case of I2S input only, BLF_EN can be set to “1'b0”.
The band limiting filter behaves as follows:(1) When HI_RES_MODE: 1'b1
Note that the band limiting filter is effective only when the internal processing is performed in Hi-Res Mode andthe BCK of the I2S output is set to 48 kHz or 96 kHz.

Table 3.15-8 Bandwidth limitation by BLF (HI_RES_MODE:1'b1)
SRC{1,2}

Data Bandwidth

2'b00

Prohibited setting

2'b01

24 kHz

2'b10

48 kHz2'b11

Filter OFF (bypass)For example, when SRC1 is set to “2'b10” and the data is read out in the Slave Mode with the LRCK at 88.2
kHz (twice times 44.1 kHz), aliasing is caused by the audio data from 44.1 kHz to 48 kHz. To avoid this, thebandwidth must be limited using software processing by the ADSP.
As this example shows, the Audio Codec does not have an internal band limiting filter for I2S output frequencies
under 24 kHz, so when using transfer rates below 48 kHz, the bandwidth must be limited using software
processing by the ADSP.
(2) When HI_RES_MODE: 1'b0

Table 3.15-9 Bandwidth limitation by BLF (HI_RES_MODE:1'b0)
SRC{1,2}

Data Bandwidth

2'b00

Prohibited setting

2'b01

96 kHz

2'b10

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2'b11Prohibited setting

When HI_RES_MODE is set to “1'b0”, the BLF does not operate as a band limiting filter; instead, it peforms
up-sampling from fs = 48 kHz to fs = 192 kHz. The SRC1 and SRC2 then receive the data that was up-sampled by
192 kHz, and perform output of the I2S format according to the data rate setting.
The limitations due to the absence of an internal band limiting filter for frequencies under 24 kHz are the sameeven when HI_RES_MODE is set to “1'b0”.
The following shows the characterstics of the band limiting filter

1.00E+01
0.00E+00-1.00E+01-2.00E+01

Gain(dB)-3.00E+01-4.00E+01-5.00E+01-6.00E+01-7.00E+01-8.00E+01-9.00E+01-1.00E+02-1.10E+02-1.20E+02

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Normalized Frequency(fs=192kHz)

Figure 3.15-11 Characterstics of the Band Limiting Filter (HI_RES_MODE:1'b1, SRC{1,2}:2'b10)
1.00E+01
0.00E+00-1.00E+01

Gain(dB)-2.00E+01-3.00E+01-4.00E+01-5.00E+01-6.00E+01-7.00E+01-8.00E+01

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Normalized Frequency(fs=192kHz)－1053/1293－

0.4

0.45

0.5

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Figure 3.15-12 Characterstics of the Band Limiting Filter (HI_RES_MODE:1'b1, SRC{1,2}:2'b01)[Caution] When HI_RES_MODE:1'b0 (internal processing rate 48 kHz) and SRC{1, 2} is set to “2'b01”, keep
the I2S output within 90% of the D Range. For example:(1) For the Mic input, set the gain to -1 dB using ADC1L_VOL, or CIC1_LGAIN, etc.
(2) When the signal processed by the ADSP is received by the Audio Codec, perform the processing within the
ADSP and clip the signal by -1 dB of the D Range.

3.15.6.11

Codec DSP Setting

3.15.6.11.1

Internal Signal Processsing Rate Setting

HI_RES_MODE (offset 0x0200 bit[31]) determines the internal signal processing rate.
HI_RES_MODE (offset 0x0200 bit[31])1'b0: Normal Mode (fs = 48 kHz)
1'b1: Hi-Res Mode (fs = 192 kHz)When this is set to “1'b0”, the settings of SRC1/SRC2 are limited. Refer to Section 3.15.6.8.2.

3.15.6.11.2

Volume Control

The following diagram shows an overview of volume control.

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Figure 3.15-13 Volume Control Overview Diagram
MUTE_B (offset 0x022C bit[4]) mutes the Digital Amplipfer input signal.
MUTE_B (offset 0x022C bit[4])1'b0: mute disable
1'b1: mute enable
SDIN1_VOL (offset 0x0228 bit[31:24]) , SDIN2_VOL (offset 0x0228 bit[23:16]) , SDOUT_VOL (offset 0x0228
bit[15:8]) , LINEIN_VOL (offset 0x022C bit[23:16]) , DAC_VOL (offset 0x022C bit[15:7])
8'h18: +12 dB:
8'h00: 0 dB
8'hFF: -0.5 dB
8'hFE: -1.0 dB:
8'h34: -102 dB
8'h33: mute
8'h34 ~ 8'h19: Prohibited setting
DIGSFT (offset 0x0200 bit[12]) is a function that ultimately reaches the desired value in predetermined stepchanges when the above Volume Control value is changed. This is used to cope with so-called “pop noise” that
occurs when the Volume Control is changed.
DIGSFT (offset 0x0200 bit[12])1'b0: Soft Control function disable
1'b1: Soft Control function enable
DSR_RATE (offset 0x0200 bit[2:0]) controls the steps of the control value changes when DIGSFT is set to “1'b1”.
DSR_RATE (offset 0x0200 bit[2:0])
3'h0: 1STEP up/down per clock
3'h1: 1STEP up/down per every other cycle
3'h2: 1STEP up/down per each 3 cycles
3'h3: 1STEP up/down per each 5 cycles
3'h4: 1STEP up/down per each 7 cycles
3'h5: 1STEP up/down per each 10 cycles
3'h6: 1STEP up/down per each 11 cycles
3'h7: 1STEP up/down per each 15 cycles－1055/1293－

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3.15.6.11.3

ALC, SPC

The ALC (Automatic Level Control) function can be controlled.
ALC_EN (offset 0x021C bit[31])1'b0: ALC OFF
1'b1: ALC ON
ALC_REC (offset 0x021C bit[30]) selects the path to activate ALC.
ALC_REC (offset 0x021C bit[30])1'b0: Play1'b1: RecFor the order of the processing of ALC, SPC, etc., refer to Section 3.15.6.11.4.
ALC_TARGET (offset 0x021C bit[29:24]) sets the convergence level when the ALC operates.
ALC_TARGET (offset 0x021C bit[29:24])
6'h00: 0dB
6'h01: -1dB:
6'h3E: -62dB
6'h3F: -63dB

6'h00

output

0dB

6'h06

-6dB

input

-6dB 0dB

Figure 3.15-14 Example of ALC_TARGET Control (ALC_KNEE:7'h00)
ALC_KNEE (offset 0x021C bit[22:16]) sets the KNEE point of ALC.

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ALC_KNEE (offset 0x021C bit[22:16])
7'h00: 0dB
7'h01: -0.5dB:
7'h3E: -63dB
7'h3F: -63.5dB

7'h0C
7'h00

output

0dB
-6dB

input

-6dB 0dB

Figure 3.15-15 Example of ALC_KNEE Control (ALC_TARGET:6'h00)
Note that the KNEE slope cannot be controlled.
ALC_ALG (offset 0x0404 bit[15]) selects the control algorithm of ALC.
ALC_ALG (offset 0x0404 bit[15])1'b0: Operates the ALC using the smoothing results of the input signal power.
1'b1: Compares the momentary power and smoothing results of the input signal, and operates the ALC using
the data that is larger.
ALC_DELAY (offset 0x0404 bit[14:8]) inserts a delay to the input signal.
ALC_DELAY (offset 0x0404 bit[14:8])
7'h00: 0 sample delay:
7'h7F: 127 sample delay
ALC_LPF (offset 0x0410 bit[23:0]) calculates the power of input signal and sets the LPF used for smoothing.
The LPF cut off frequency is obtained by the following equation:－1057/1293－

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In this equation, ln is natural logarithm using base e, and fs is the audio data rate (48 kHz or 192 kHz) that is set
by HI_RES_MODE.
[Caution] Do not use ALC_LPF set at “24'h000000”. Also, do not make a setting higher than “24'h400000”.
When ALC_LPF is set to “24'h400000”, the LPF turns OFF (bypass).
SPC_ALC_ATTACK (offset 0x0408 bit[23:0]) sets the ATTACK time of ALC and SPC_ALC_RELEASE(offset 0x040C bit[23:0]) sets the RELEASE time of ALC. These registers are shared with the SPC function
described later. Simultaneous use of SPC and ALC is not assumed.
The ATTACK time and RELEASE time are obtained by the following equations.
When HI_RES_MODE:1'b0 (Audio data rate 48 kHz):When HI_RES_MODE:1'b1 (Audio data rate192 kHz):In these equations, ‘setting Data’ is the setting data of SPC_ALC_ATTACK or SPC_ALC_RELEASE.
[Caution] Do not use SPC_ALC_ATTACK set to “24'h000000”. Also, do not make a setting higher than
“24'h400000”. When SPC_ALC_ATTACK is set to “24'h400000”, the ALC response becomes immediate.
The following shows an example of the response to the ALC function. Here, the ALC_TARGET is set to “-6dB” and the ALC_KNEE is set to “-26 dB”. The input signal is a 1 kHz burst signal that changes amplitude from
-6 dB to -26 dB every 1000 cycles, and the HD output of the CXD5247 is being observed.

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Figure 3.15-16 The HP Output Signal in Normal Mode (fs = 48 kHz) with ALC function OFF and
Input Signal Level: -6 dB/-26 dB

Figure 3.15-17 The HP Output Signal in Normal Mode (fs = 48 kHz) with ALC function ON,
SPC_ALC_RELEASE = 0x000100, ALC_ALG = 1'b0, and Input Signal Level -6 dB/-26 dB
SPC_EN (offset 0x021C bit[15]) can enable the SPC (Sound Pressure Control).
SPC_EN (offset 0x021C bit[15])1'b0: SPC disable
1'b1: SPC enable
For the order of processing of ALC, SPC, etc., refer to Section 3.15.6.11.4.
SPC_LIMIT (offset 0x021C bit[14:8]) determines the Limit value of SPC.
SPC_LIMIT (offset 0x021C bit[14:8])
7'h00: 0dB
7'h01: -0.5dB:
7'h31: -24.5dB
7'h32: -25dB
Do not use with a setting value higher than “7'h32”.
The response speed of SPC is set using SPC_ALC_ATTACK and SPC_ALC_RELEASE. For details, refer to the－1059/1293－

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ALC item. Also, simultaneous use of SPC and ALC is not assumed.
The following shows an example of response of the SPC function. In this example, SPC_LIMIT is set to “-12dB”. The input signal is a 1 kHz burst signal that changes amplitude from -6 dB to -26 dB every 1000 cycles, andSpeaker output is being observed.

Figure 3.15-18 The HP Output Signal in Normal Mode (fs = 48 kHz) with SPC function ON,
SPC_ALC_ATTACK = 0x000100, and Input Signal Level -6 dB/-26 dB
SPC_AWEIGHT (offset 0x0404 bit[23])1'b0: AWEIGHT filter OFF (bypass)
1'b1: AWEIGHT filter ON
The following shows the filter characteristics.
(Settings: SPC_LIMIT: 0x32, SPC_ALC_ATTACK: 0x400000, and SPC_ALC_RELEASE: 0x000100)－1060/1293－

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AWEIGHT:1'b1

AWEIGHT:1'b0

Figure 3.15-19 AWEIGHT Filter Characteristics (Hi-Res Mode)
The gain drop in the high frequency area is caused by the influence of the SRC filter and observing the I2S output

AWEIGHT:1'b1

AWEIGHT:1'b0

Figure 3.15-20 AWEIGHT Filter Chracteristics (Normal Mode)

3.15.6.11.4

SPC, and ALC Order of Processing

The following shows the order of processing ALC.

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CXD5602 User Manual(1-1) When HI_RES_MODE:1'b1, ALC_REC: 1'b0 (Play)

Figure 3.15-21 Order of Processing ALC (HI_RES_MODE:1'b1, ALC_REC:1'b0)(1-2) When HI_RES_MODE:1'b1, ALC_REC: 1'b1 (Rec)

Figure 3.15-22 Order of Processing ALC (HI_RES_MODE:1'b1, ALC_REC:1'b1)(2-1) When HI_RES_MODE:1'b0, ALC_REC: 1'b0 (Play)

Figure 3.15-23 Order of Processing ALC (HI_RES_MODE:1'b0, ALC_REC:1'b0)(2-2) When HI_RES_MODE:1'b0, ALC_REC: 1'b1 (Rec)－1062/1293－

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Figure 3.15-24 Order of Processing ALC (HI_RES_MODE:1'b0, ALC_REC:1'b1)
The following shows the order of processing SPC.

Figure 3.15-25 Order of Processing SPC
3.15.6.11.5

BEEP

BEEP_ON (offset 0x0230 bit[31]) allows the output of a BEEP sound.
BEEP_ON (offset 0x0230 bit[31])1'b0: OFF
1'b1: ON
BEEP_FREQ (offset 0x0230 bit[29:24]) controls the output frequency of the BEEP sound.

BEEP_VOL (offset 0x0230 bit[20:16]) controls the volume of the BEEP sound.
BEEP_VOL (offset 0x0230 bit[20:16])
5'h00: Volume min.
5'h1F: Volume max.

3.15.6.12

Decimation Filter

The Decimation Filter can be used to restrict bandwidth when the audio data rate written to the SRAM on the－1063/1293－

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AHB is lower than the audio data rate of internal processing.

from
CXD5247SERIAL to
PARALLEL

Decimation
BUS I/F
Filter
MIC1_A(L/R)
MIC1(L/R)
MIC2(L/R)

MIC2_A(L/R)

MIC3(L/R)

MIC1_B(L/R)

MIC4(L/R)

MIC2_B(L/R)

Figure 3.15-26 Decimation Filter Peripheral Overview
The MIC1 signals (L channel, R channel) passed through the Decimation Filter are called signal MIC1L_A and
MIC1R_A. In the same way, the MIC2 signals are called signal MIC2L_A and MIC2R_A, the MIC3 signals arecalled signal MIC1L_B and MIC1R_B, and finally, the MIC4 signals are called signal MIC2L_B and MIC2R_B.
DECIM_EN (offset 0x0104 bit[16]) controls ON/OFF of the Decimation Filter block.
DECIM_EN (offset 0x0104 bit[16])1'b0: Decimation Filter Block inactive
1'b1: Decimation Filter Block active
When sending the signal through the Decimation Filter block, set this to “1'b1”, regardless of using or not using
the Filter function.
SEL_DECIM (offset 0x0304 bit[24]) controls ON/OFF of the Decimation Filter.
SEL_DECIM (offset 0x0304 bit[24])1'b0: bypass
1'b1: Decimation Enable
SEL_INF (offset 0x0304 bit[20]) sets the audio data rate of the input.
SEL_INF (offset 0x0304 bit[20])1'b0: 4fs
1'b1: 8fs
Match the data rate that you set by SEL_INF with the data rate that you set by DCMFS and DCMFS_34 (Refer to
Section 3.15.6.7).
SEL_OUTF (offset 0x0304 bit[17:16]) sets the audio data rate written to the SRAM on the AHB.

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SEL_OUTF (offset 0x0304 bit[17:16])
2'b00: 1fs
2'b01: 2fs
2'b10: 4fs
2'b11: Prohibited setting
You cannot write data to the SRAM on the AHB at a data rate of 8fs.
The following shows the characteristics of the Decimation Filter.
(1) 1/2-band limiting (input 4fs => output 2fs or input 8fs => output 4fs)

0
-10
-20
-30

Gain(dB)

-40
-50
-60
-70
-80
-90
-100

0

0.06250.125

0.18750.25

0.31250.375

0.43750.5

Normalized Frequency(denominator : input frequency)

Figure 3.15-27 Characteristics of 1/2-band Decimation Filter(2) 1/4-band limiting (input 4fs => output 1fs or input 8fs => output 2fs)

0
-10
-20
-30

Gain(dB)

-40
-50
-60
-70
-80
-90
-100

0

0.06250.125

0.18750.25

0.31250.375

0.43750.5

Normalized Frequency(denominator : input frequency)－1065/1293－

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Figure 3.15-28 Characteristics of 1/4-band Decimation Filter(3) 1/8-band limiting (input 8fs => output 1fs)

0
-10
-20
-30

Gain(dB)

-40
-50
-60
-70
-80
-90
-100

0

0.06250.125

0.18750.25

0.31250.375

0.43750.5

Normalized Frequency(denominator : input frequency)

Figure 3.15-29 Characteristics of 1/8-band Decimation Filter
The input and output frequencies can also be set to 4fs, but in this case, it is recommended to set SEL_DECIM
to “1'b0” (bypass).
The following shows some setting examples.

Table 3.15-10 Settings by Input and Output Rate
Input Rate

Output Rate

SEL_DECIM

SEL_INF

SEL_OUTF[1:0]

Decimation Filter

4fs

1fs

1

0

0

1/4 Decimation

4fs

2fs(1*)

1

0

1

1/2 Decimation

4fs

4fs

0

-

-

Bypass

8fs

1fs

1

1

0

1/8 Decimation

8fs

2fs(1*)

1

1

1

1/4 Decimation

8fs

4fs

1

1

2

1/2 Decimation

1* When the output rate is set to 2fs and the signal is returned to the Audio Codec after processing at the ADSP, a

1/2-Decimation process must be applied at the ADSP to obtain a 1fs rate.
The outputs of the Decimation Filter can be separately controlled.
OUTEN_MIC1L_A (offset 0x0580 bit[4]) can control the output of the MIC1L_A signal.
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1'b0: output disable
1'b1: output enable
OUTEN_MIC1R_A (offset 0x0580 bit[5]) can control the output of the MIC1R_A signal. The control
specifications conform to OUTEN_MIC1L_A.
OUTEN_MIC2L_A (offset 0x0580 bit[6]) can control the output of the MIC2L_A signal. The control
specifications conform to OUTEN_MIC1L_A.
OUTEN_MIC2R_A (offset 0x0580 bit[7]) can control the output of the MIC2R_A signal. The control
specifications conform to OUTEN_MIC1L_A.
OUTEN_MIC1L_B (offset 0x0580 bit[0]) can control the output of the MIC1L_B signal. The control
specifications conform to OUTEN_MIC1L_A.
OUTEN_MIC1R_B (offset 0x0580 bit[1]) can control the output of the MIC1R_B signal. The control
specifications conform to OUTEN_MIC1L_A.
OUTEN_MIC2L_B (offset 0x0580 bit[2]) can control the output of the MIC2L_B signal. The control
specifications conform to OUTEN_MIC1L_A.
OUTEN_MIC2R_B (offset 0x0580 bit[3]) can control the output of the MIC2R_B signal. The control
specifications conform to OUTEN_MIC1L_A.

3.15.6.13

Digital Ampliper Setting

NSPMUTE (offset 0x0340 bit[31]) can mute the Digital Ampliipfer output.
NSPMUTE (offset 0x0340 bit[31])1'b0: Normal Operation
1'b1: Mute
When muting, “0” is output from the Digital Ampliipfer output. It is not fixed to Low.
The “0” output of the Digital Ampliipfer output ultimately becomes a pulse of Duty 50% at the CXD5247 output.
Switch the NSX2 (offset 0x0340 bit[30]) according to the operating frequency of the subsequent CXD5247.
NSX2 (offset 0x0340 bit[30])1'b0: CXD5247 operating frequency

24.576 MHz

1'b1: CXD5247 operating frequency

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Table 3.15-11 Settings According to the Transfer Mode
Transfer Mode

NSX2

Serialized Output

CXD5247 Operation Clock

16fs

0

16fs

24.576 MHz

32fs

1

32fs

49.152 MHz

Note: The Audio Codec block is always operated by 24.576 MHz clock.
When setting TRANS_MODE (offset 0x022C bit[6])=1, the normal transmissions of the L channel and R
channel are switched to (L+R) /2 transmission and (L-R) /2 transmission. The (L+R) /2 is sent to the L channel
and the (L-R) /2 signal is sent to the R channel.
NSADJON (offset 0x0340 bit[29]) switches enable/disable of the NSADJ setting described later.
NSADJON (offset 0x0340 bit[29])1'b0: NSADJ setting disable
1'b1: NSADJ setting enable
NSADJ (offset 0x034C bit[23:16]) can change the zero point setting of the Noise Shaper.
NSDD (offset 0x0344 bit[19:0]) can change the DC dither level.
BPON (offset 0x0340 bit[23]) can output a BEEP sound.
This function is diffrent from the function which is operated in the Codec DSP.
(refer to Section 3.15.6.11.5).
BPON (offset 0x0340 bit[23])1'b0: BEEP OFF
1'b1: BEEP ON
BPSEL (offset 0x0340 bit[19:16]) can control the frequency of the BEEP sound.
BPSEL (offset 0x0340 bit[19:16])
4'h0: lowest frequency
4'hF: highest frequency
BPGAIN (offset 0x0340 bit[15:8]) can control the output level of the BEEP sound.
BPGAIN (offset 0x0340 bit[15:8])
8'h00: highest BEEP level－1068/1293－

CXD5602 User Manual

8'hFF: lowest BEEP level
By further adding a comb filter to the Noise Shaper output, the NS_AMMD (offset 0x340 bit[3:0]) can reduce
the effects on signal detection when receiving FM signals. The frequencies for the comb filter are defined asfollows:
fcomb = 16 x fs/2/NS_AMMD x (2n + 1) (n = 0, 1, 2, 3, 4, ...)
When NS_AMMD is set to “4'h0”, the Filter turns OFF (bypass).
[Caution] Note that there are limitations for the PWMMD setting on the CXD5247 side when using a comb
filter by the NS_AMMD.
Specifically, the PWMMD of the CXD5247 must be set to “2'b00” (Single sideband modulation mode).

3.15.6.14

Other Control Registers (Signal Processing)

3.15.6.14.1

Internal SRAM Clear

The SRC, BLF, and Codec DSP each have internal SRAM. When a system reset occurs upon supplying
power, etc., it is recommended to initialize the internal SRAM as well.
Initialization is performed when a change from “0” to “1” is detected in the selected register and the initialization
routine starts. The initialization takes about 21 us (512 cycles@24.576 MHz).
Note that the register value does not return to “0” automatically. After setting it to “1”, make sure to set it back to“0”.
DSPRAM1_CLR (offset 0x0400 bit[31]) initializes the internal SRAM of the SRC block.
DSPRAM1_CLR (offset 0x0400 bit[31])1'b0: Normal Operation
1'b1: SRAM Clear
DSPRAM2_CLR (offset 0x0400 bit[30]) initializes the internal SRAM of the Codec DSP block.
DSPRAM2_CLR (offset 0x0400 bit[30])1'b0: Normal Operation
1'b1: SRAM Clear
DSPRAM3_CLR (offset 0x0400 bit[29]) initializes the internal SRAM of the DNC block.
DSPRAM3_CLR (offset 0x0400 bit[29])1'b0: Normal Operation
1'b1: SRAM Clear[Caution] Since the instruction code for DNC is stored in the SRAM, initialization is also performed to the－1069/1293－

CXD5602 User Manual

Instruction Code area. After initialization, make sure to re-transfer the Instruction Code.
DSPRAM4_CLR (offset 0x0400 bit[28]) initializes the internal SRAM of the BLF block.
DSPRAM4_CLR (offset 0x0400 bit[28])1'b0: Normal Operation
1'b1: SRAM Clear

3.15.6.15

Reset Control

S_RESET (offset 0x0400 bit[16]) initializes the internal SRC and the FF of the Codec DSP block. Whenchanging the SRC transfer rate or the Slave/Master Mode, make sure to perform initialization using thisS_RESET.
S_RESET (offset 0x0400 bit[16])1'b0: Normal operation
1'b1: Initialization
Note that the register value does not return to “0” automatically. After setting it to “1”, make sure to set it back to“0”. The internal SRC and Codec DSP block will not operate properly if this setting is kept at “1”.

3.15.6.16

Clock Monitor

The Audio Codec, due to the specifications of the clock domain crossing circuit of its internal AHB, prohibits
access to the AHB Address assigned to the Audio Codec when the system clock supplied from the CXD5247
stops. It also monitors whether this system clock is supplied. In the system clock’s monitor circuit, the tresh(offset 0x11FC bit[7:0]) controls the time constant from when the system clock stops to the notification of thatstop to the upper layer.
tresh (offset 0x11FC bit[7:0]0x00: short time constant:
0xFF: long time constant

3.15.6.17

AHB I/F for SRAM Upload/Download

The Audio Codec has an AHB I/F for writing data to the SRAM on the AHB.
This assumes that writing to the SRAM on the AHB is controlled by the firmware that is operating on the ADSP.

－1070/1293－

CXD5602 User ManualFor data Upload (writing to the SRAM), there are the three lines of MIC, I2S0, and I2S1, while for Download(reading out from the SRAM), there are the two lines of I2S0 and I2S1.
The following is an overview of the functions.


Upload of eight channels of MIC data to the AHB (8 channels x 1 line)

1fs/4fs supportUpload of 24 bit Mic dataCombination of the higher-order 16 bits of two 24 bit Mic data and upload as one 32 bit datum. The
lower-order 8 bits are truncated.



Upload of the I2S I/F data to the AHB (2 channels x 2 lines)

1fs/4fs supportUpload of the 24 bit data of each channel input to the I2S I/FCombination of the higher-order 16 bits of each 24 bit channel input to the I2S I/F by line and upload asone 32 bit datum. The lower-order 8 bits are truncated.



Output of the data downloaded from the SRAM from the I2S I/F (2 channels x 2 lines)

1fs/4fs support

Download of the 24 bit data and output from the I2S I/F

Download of the 32 bit data and treat this as a pair of 16 bit data, which are distributed to the L channel
and R channel, and 0 align the lower-order 8 bits and output from the I2S I/F as 24 bit L and R channel
data.

3.15.6.17.1

BUS_Master (MIC)

transfer setting command

CH2

MIC2_L_IN

CH3

MIC2_R_IN

CH4

MIC1_L_IN

SEL

CH1

FIFO

MIC1_L_IN
MIC1_R_IN

CH5

MIC1_R_IN

CH6

MIC2_L_IN

CH7

MIC2_R_IN

CH8

Hand Shake

BUS Master(MIC)

Data EN

commandinterface

WDATA

DMAC
IP

AHB（ configuration for IP）

Figure 3.15-30 BUS MASTER(MIC) Block－1071/1293－

AHB-BUSCXD5602 User Manual

The eight MIC signals of the Decimation Filter output are written to the SRAM on the AHB at the BUS Master(MIC). The input signal is transferred to the AHB clock and passes the first stage of FIFO, and the selected signal
is transferred from the DMAC.
The selection of the transfer channels can be arbitrarily set.
There are two transfer modes - 24 bit and 16 bit mode. In the case of 24 bit transfer mode, a maximum of eightwords of a 1 word = 32 bit signal with lower-order bits set to “0” are transferred. In the case of 16 bit transfer
mode, the lower-order 8 bits of the 24 bit input signal of each L channel and R channel are truncated and amaximum of four words of a 1 word = 32 bit (16 bit + 16 bit) signal merged from the L channel and R channel aretransferred. Switching between 32 bit and 16 bit is performed at the bitwt_MIC. For details, refer to Section
3.15.6.19.1.

1word 32bit

31

8 7

0

data(24bit)

BITWT = 0
31

0

16 15

BITWT = 10data(16bit)Rchdata(16bit)Lch

Figure 3.15-31 Bit Configuration by Transfer Mode (when writing to the SRAM)
3.15.6.17.2

BUS Master (I2S)

transfer setting command

CH2

CH1
CH2

Hand
Shake

CH1

WDATA

Hand
Shake

SD1/2_R_OUT

SEL

SD1/2_L_OUT

FF

SRC1/2_R_IN

FIFO

FIFO

SRC1/2_L_IN

SEL

BUS Master(I2S0/1)

Data EN

RDATA

commandinterface

DMAC
IP

AHB（configuration for IP）

Figure 3.15-32 BUS MASTER (I2S0/I2S1) Block－1072/1293－

AHB-BUSCXD5602 User Manual

The signals from I2S I/F, SRC-1/ I2S I/F, and SRC-2 are written to the SRAM on the AHB by two independent
BUS Master (I2S0, I2S1). The input signal is transferred to the AHB clock and passes the first stage of FIFO, andthe selected signal is transferred by the DMAC.
The signal from the AHB-BUS passes the first stage of FIFO selected, then is transferred to the MCLK, and is
output as two independent signals. The selection of the transfer channel can be arbitrarily set for both directions.
Two BUS Master (I2S) are equipped, each supporting UP/DOWN for I2S I/F and SRC-1, and UP/DOWN for I2S
I/F and SRC-2.
There are two transfer modes - 24 bit and 16 bit mode. In the case of 24 bit transfer mode, a maximum of twowords of a 1 word = 32 bit signal with lower-order bits set to “0” are transferred. In the case of 16 bit transfer
mode, the lower-order 8 bits of the 24 bit input signal of each L channel and R channel are truncated and amaximum of one word of a 1 word = 32 bit (16 bit + 16 bit) signal merged from the L channel and R channel aretransferred.
In other words, when reading and writing the L channel and R channel from/to the SRAM, the transmission mustbe performed in two words for 24 bit mode and one word for 16 bit mode.
The control of 24 bit/16 bit is performed by bitwt_I2S{1,2}_UP or bitwt_I2S{1,2}_DOWN. For details, refer to
Section 3.15.6.19.1.

1word 32bit

31

8 7

data(24bit)

BITWT = 031

BITWT = 1

0

0
0

16 15

data(16bit)Lchdata(16bit)Rch

Figure 3.15-33 Bit Configuration by Transfer Mode (when writing to the SRAM)

1word 32bit

31
31

0

0

data (n) (24bit)

BITWT = 0
BITWT = 1

8 7

16 15

0

data (n+1) (16bit)

data (n) (16bit)

Figure 3.15-34 Bit Configuration by Transfer Mode (when reading from the SRAM)

3.15.6.18

AHB I/F Clock Control

The clock of the AHB I/F circuit can be controlled for each line. By performing ON/OFF control as necessary,
the power consumption can be reduced.

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CXD5602 User Manual

ahbmstr_mic_en (offset 0x11F0 bit[0]) controls the clock of the I/F circuit that performs upload/download of
the MIC signal.
ahbmstr_mic_en (offset 0x11F0 bit[0])1'b0: clock disable
1'b1: clock enableahbmstr_I2S0_en (offset 0x11F0 bit[1]) controls the clock of the I/F circuit that performs upload/download of
I2S0 (1st line of the I2S I/F signal).
ahbmstr_I2S0_en (offset 0x11F0 bit[1])1'b0: clock disable
1'b1: clock enableahbmstr_I2S1_en (offset 0x11F0 bit[2]) controls the clock of the I/F circuit that performs upload/download of
I2S1 (2nd line of the I2S I/F signal).
ahbmstr_I2S1_en (offset 0x11F0 bit[2])1'b0: clock disable
1'b1: clock enable
After setting the necessary clocks to enable, make the register settings according to the following Chapters.
For the order of making the settings, refer to Section 3.15.10.2.

3.15.6.19

AHB I/F Control Registers

3.15.6.19.1

Channel Settings (MIC)

bitwt_MIC (offset 0x100C bit[0]) controls the bit width when transferring the MIC input signal.
bitwt_MIC (offset 0x100C bit[0])0x0: 24bit x 1 data
0x1: 16bit x 2 data
ch1_sel_MIC (offset 0x1010 bit[31:28]) , ch2_sel_MIC (offset 0x1010 bit[27:24]) ,ch3_sel_MIC (offset 0x1010 bit[23:20]) , ch4_sel_MIC (offset 0x1010 bit[19:16]) ,Assigns the transfer channels to the data of the eight channels of MIC input.
For the transfer channels n (n = 1, 2, 3, 4), ch{n}_sel_MIC is:
When bitwt_MIC : 0x0
0x0: MIC1 L channel is selected－1074/1293－

CXD5602 User Manual

0x1: MIC1 R channel is selected
0x2: MIC2 L channel is selected:
0x6: MIC4 L channel is selected
0x7: MIC4 R channel is selected
0x8 and above: unselects as a transfer channel
When bitwt_MIC : 0x1
0x0: MIC1 L channel and R channel are selected
0x1: MIC2 L channel and R channel are selected
0x2: MIC3 L channel and R channel are selected
0x3: MIC4 L channel and R channel are selected
0x8 or above: unselected as a transfer channel
When bitwt_MIC: 0x1
0x4, 0x5, 0x6, and 0x7 are prohibited settings.
Make sure to use the transfer channels in order starting from channel 1. For example, do not unselect channel 1
and transfer the MIC1 data using channel 2.
ch5_sel_MIC (offset 0x1010 bit[15:12]), ch6_sel_MIC (offset 0x1010 bit[11:8]),ch7_sel_MIC (offset 0x1010 bit[7:4]), ch8_sel_MIC (offset 0x1010 bit[3:0])
Assigns the transfer channels to the data of the eight channels of MIC input.
For the transfer channels n (n = 5, 6, 7, 8), ch{n}_sel_MIC is:
When bitwt_MIC: 0x0
0x0: MIC1 L channel is selected
0x1: MIC1 R channel is selected
0x2: MIC2 L channel is selected:
0x6: MIC4 L channel is selected
0x7: MIC4 R channel is selected
0x8 and above: unselects as a transfer channel
Since selection is not possible when bitwt_MIC: 0x1, make sure to set a value of eight or higher.

Table 3.15-12 Transfer Channel Settings
bitwt_MIC

Transfer Channel

Setting ValueControl Register－1075/1293－

Signal TransferredCXD5602 User Manual0

ch1_sel_MIC

0

MIC1 L channel

ch2_sel_MIC

1

MIC1 R channel

ch3_sel_MIC

2

MIC2 L channel

ch4_sel_MIC

3

MIC2 R channel

ch5_sel_MIC

4

MIC3 L channel

5

MIC3 R channel

6

MIC4 L channel

7

MIC4 R channel

8, 9, 10, 11, 12, 13, 14, 15

Unselects (transfer channel is not used)

ch1_sel_MIC

0

MIC1 L channel and R channel

ch2_sel_MIC

1

MIC2 L channel and R channel

ch3_sel_MIC

2

MIC3 L channel and R channel

ch4_sel_MIC

3

MIC4 L channel and R channel

4, 5, 6, 7

Prohibited setting

8, 9, 10, 11, 12, 13, 14, 15

Unselects (transfer channel is not used)ch5_sel_MIC

0, 1, 2, 3, 4, 5, 6, 7

Prohibited setting

ch6_sel_MIC

8, 9, 10, 11, 12, 13, 14, 15

Unselects (transfer channel is not used)

ch6_sel_MIC
ch7_sel_MIC
ch8_sel_MIC

1

ch7_sel_MIC
ch8_sel_MIC

3.15.6.19.2

Channel Settings (I2S)

ensel (offset 0x1110 bit[0]) selects the audio data rate.
ensel (offset 0x1110 bit[0])0x0: data rate 48 kHz
0x1: data rate 192 kHz
Match ensel to the setting of HI_RES_MODE.
The ensel is valid for the data from I2S. The data rate of the MIC data is determined by the setting of the
CXD5247 I/F.
bitwt_I2S0_UP(offset 0x108C bit[0]) controls the bit width when the signal from I2S I/F is uploaded to the
SRAM on the AHB. The Audio Codec has two lines of BUS I/F for uploading data from the I2S, where each is
exclusively assigned to the two lines of I2S I/F 2 for independent control of each one.
bitwt_I2S0_UP(offset 0x108C bit[0])1'b0: 24bit x 1 data
1'b1: 16bit x 2 data

－1076/1293－

CXD5602 User Manualch1_sel_I2S0_UP (offset 0x1090 bit[5:4]) selects the signal when the signal from I2S I/F is uploaded to the
SRAM on the AHB.
ch1_sel_I2S0_UP (offset 0x1090 bit[5:4]) (when bitwt_I2S0_UP : 1'b0)
2'b00: selects the L channel of the I2S0 line
2'b01: selects the R channel of the I2S0 line
2'b1x: unselects as a transfer channel
Regardless of the ch1_sel_I2S0_UP setting, when bitwt_I2S0_UP : 1'b1, the L and R channels of the I2S0 line aretransferred as a pair (refer to Figure 3.15-33). They cannot be unselected as a transfer channel.
ch2_sel_I2S0_UP (offset 0x1090 bit[1:0])
Selects the signal when the signal from the I2S I/F is uploaded to the SRAM on the AHB.
ch2_sel_I2S0_UP (offset 0x1090 bit[1:0]) (when bitwt_I2S0_UP: 1'b0)
2'b00: selects the L channel of the I2S0 line
2'b01: selects the R channel of the I2S0 line
2'b1x: unselects as a transfer channel
Regardless of the ch2_sel_I2S0_UP setting, when bitwt_I2S0_UP: 1'b1, unselects as a transfer channel.
Make sure to use the transfer channels in order starting from channel 1. For example, do not unselect channel 1(ch1_sel_I2S0_UP: 2'b11) and transfer the data of the L channel using channel 2 (ch2_sel_I2S0_UP: 2'b01).
bitwt_I2S1_UP (offset 0x10AC bit[0]) controls the bit width when the signal from I2S I/F is uploaded to the
SRAM on the AHB. The Audio Codec has two lines of BUS I/F for uploading data from the I2S, where each is
exclusively assigned to the two lines of I2S I/F 2 for independent control of each one.
bitwt_I2S1_UP (offset 0x10AC bit[0])1'b0: 24bit x 1 data
1'b1: 16bit x 2 data
ch1_sel_I2S1_UP (offset 0x10B0 bit[5:4])
Selects the signal when the signal from the I2S I/F is uploaded to the SRAM on the AHB.
ch1_sel_I2S1_UP (offset 0x10B0 bit[5:4]) (when bitwt_I2S0_UP: 1'b0)
2'b00: selects the L channel of the I2S1 line
2'b01: selects the R channel of the I2S1 line
2'b1x: unselects as a transfer channel
Regardless of the ch1_sel_I2S1_UP setting, when bitwt_I2S1_UP: 1'b1, the L and R channels of the I2S1 line aretransferred as a pair (refer to Figure 3.15-33). They cannot be unselected as a transfer channel.

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CXD5602 User Manualch2_sel_I2S1_UP (offset 0x10B0 bit[1:0]) selects the signal when the signal from I2S I/F is uploaded to the
SRAM on the AHB.
ch2_sel_I2S1_UP (offset 0x10B0 bit[1:0]) (when bitwt_I2S1_UP: 1'b0)
2'b00: selects the L channel of the I2S1 line
2'b01: selects the R channel of the I2S1 line
2'b1x: unselects as a transfer channel
Regardless of the ch2_sel_I2S1_UP setting, when bitwt_I2S1_UP: 1'b1, unselects as a transfer channel.
Make sure to use the transfer channels in order starting from channel 1. For example, do not unselect channel 1(ch1_sel_I2S1_UP: 2'b11) and transfer the data of the L channel using channel 2 (ch2_sel_I2S1_UP: 2'b01).
bitwt_I2S0_DOWN (offset 0x10CC bit[0]) controls the bit width when downloading from the SRAM on AHB.
bitwt_I2S0_DOWN (offset 0x10CC bit[0])1'b0: 24bit x 1 data
1'b1: 16bit x 2 data
sd1_l_sel (offset 0x10D0 bit[5:4]) determines which channel’s data to send to through L channel output.
sd1_l_sel (offset 0x10D0 bit[5:4]) (when bitwt_I2S0_DOWN: 1'b0)
2'b00: selects channel 1
2'b01: selects channel 2
2'b1x: unselects as a transfer channel
sd1_l_sel (offset 0x10D0 bit[5:4]) (when bitwt_I2S0_DOWN: 1'b1)
2'b00: selects [31:16]
2'b01: selects [15:0]
2'b1x: unselects as a transfer channel
sd1_r_sel (offset 0x10D0 bit[1:0])
Determines which channel’s data to send through the R channel output.
sd1_r_sel (offset 0x10D0 bit[1:0]) (when bitwt_I2S0_DOWN: 1'b0)
2'b00: selects channel 1
2'b01: selects channel 2
2'b1x: unselects as a transfer channel－1078/1293－

CXD5602 User Manualsd1_r_sel (offset 0x10D0 bit[1:0]) (when bitwt_I2S0_DOWN: 1'b1)
2'b00: selects [31:16]
2'b01: selects [15:0]
2'b1x: unselects as a transfer channel
Make sure to use the transfer channels in order starting from channel 1. For example, it is not allowed that
sd1_r_sel is set to "2'b1x" and sd1_l_sel is set to "2'b01", nor it is not allowed that sd1_l_sel is set to "2'b1x" andsd1_r_sel is set to "2'b01". This constraint is valid regardless of the value bitwt_I2S0_DOWN.
bitwt_I2S1_DOWN(offset 0x10EC bit[0]) controls the bit width when downloading from the SRAM on AHB.
bitwt_I2S1_DOWN(offset 0x10EC bit[0])1'b0: 24bit x 1 data
1'b1: 16bit x 2 data
sd2_l_sel (offset 0x10F0 bit[5:4]) determines which channel’s data to send through the L channel output.
sd2_l_sel (offset 0x10F0 bit[5:4]) (when bitwt_I2S1_DOWN : 1'b0)
2'b00: selects channel 1
2'b01: selects channel 2
2'b1x: unselects as a transfer channel
Regardless of the sd2_l_sel setting, when bitwt_I2S1_DOWN: 1'b1, the L and R channels are transferred as a pair.
The sd2_r_sel (offset 0x10F0 bit[1:0]) determines which channel’s data to send through the R channel output.
sd2_r_sel (offset 0x10F0 bit[1:0]) (when bitwt_I2S1_DOWN: 1'b0)
2'b00: selects channel 1
2'b01: selects channel 2
2'b1x: unselects as a transfer channel
Regardless of the sd2_r_sel setting, when bitwt_I2S1_DOWN: 1'b1, unselects as a transfer channel.
Make sure to use the transfer channels in order starting from channel 1. For example, it is not allowed that
sd2_r_sel is set to "2'b1x" and sd2_l_sel is set to "2'b01", nor it is not allowed that sd2_l_sel is set to "2'b1x" andsd2_r_sel is set to "2'b01". This constraint is valid regardless of the value bitwt_I2S1_DOWN.

3.15.6.19.3

Command Write Overview

Each command processing I/F block employed for the signal processing of the MIC, I2S0, and I2S1 buffers up
to three transfer commands that are set, which are sent to the DMAC one at a time. In the case that more than
three transfer commands are written, the commands after the first three are ignored and not executed. For each－1079/1293－

CXD5602 User Manualtransfer command, the number of samples to process and the AHB access start address are separately stored.
In accordance with the execution statuses of the transfer commands, the command processing I/F block generates
a variety of status signals and interrupt signals. The generated status signals can be read out via the AHB.

3.15.6.19.4

Command Write (MIC)

By writing “2'b01” to the rtd_trg_MIC (offset 0x1008 bit[1:0]), the various settings when signals from the MIC
are written to the SRAM on the AHB, are written to the command buffers. Each time writing (the same value) is
performed, the setting is written to the command buffer. When writing “2'b00”, a STOP command is written to thecommand buffer, and the DMAC stops operation after executing all settings remaining in the command buffer.
Setting “2'b10” and “2'b11” is prohibited.
For the readout values of the rtd_trg_MIC, refer to Section 3.15.7.2.
start_adr_MIC(offset 0x1000 bit[31:2]) defines the start Byte address of the transfer destination memory whenwriting signals from the MIC to the SRAM on the AHB.
The sample_no_MIC(offset 0x1004 bit[31:0]) sets the value of subtracting 1 from the number of transfer
samples when writing signals from the MIC to the SRAM on the AHB.
nointr_MIC(offset 0x1008 bit[2]) also stores this data in the command buffer when writing to the rtd_trg_MIC.
nointr_MIC(offset 0x1008 bit[2])1'b0: outputs a completion interrupt when the process written to the buffer is executed.
1'b1: does not output a completion interrupt when the process written to the buffer is executed.
Since the nointr_MIC setting is stored in the command buffer, it can be defined for each command.

3.15.6.19.5

Command Write (I2C)

By writing “2'b01” to the rtd_trg_I2S0_UP (offset 0x1088 bit[1:0]), the various settings when writing from the
I2S0 line to the SRAM on the AHB are written to the command buffer. Each time writing (the same value) is
performed, the setting is written to the command buffer. When writing “2'b00”, a STOP command is written to thecommand buffer and the DMAC stops operation after executing all settings remaining in the command buffer.
Setting “2'b10” or “2'b11” is prohibited.
For the readout values of the rtd_trg_I2S0_UP, refer to Section 3.15.7.3.
start_adr_I2S0_UP (offset 0x1080 bit[31:2]) defines the start Byte address of the transfer destination memory
when writing from I2S0 line to the SRAM on the AHB.
sample_no_I2S0_UP (offset 0x1084 bit[31:0]) sets the value of subtracting 1 from the number of transfer samples
when writing from I2S0 line to the SRAM on the AHB.

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CXD5602 User Manual

nointr_I2S0_UP (offset 0x1088 bit[2]) also stores this data in the command buffer when writing to the
rtd_trg_I2S0_UP.
nointr_I2S0_UP (offset 0x1088 bit[2])1'b0: outputs a completion interrupt when the process written to the buffer is executed.
1'b1: does not output a completion interrupt when the process written to the buffer is executed.
Since the nointr_I2S0_UP setting is stored in the command buffer, it can be defined for each command.
By writing “2'b01” to the rtd_trg_I2S1_UP (offset 0x10A8 bit[1:0]), the various settings when writing from theI2S1 line to the SRAM on the AHB are written to the command buffer. Each time writing (the same value) is
performed, the setting is written to the command buffer. When writing “2'b00”, a STOP command is written to thecommand buffer and the DMAC stops operation after executing all settings remaining in the command buffer.
Setting “2'b10” or “2'b11” is prohibited.
For the readout values of the rtd_trg_I2S1_UP, refer to Section 3.15.7.4.
start_adr_I2S1_UP (offset 0x10A0 bit[31:2])
Defines the start Byte address of the transfer destination memory when writing from the I2S1 line to the SRAM
on the AHB.
sample_no_I2S1_UP(offset 0x10A4 bit[31:0])
Sets the value of subtracting 1 from the number of transfer samples when writing from the I2S1 line to the SRAM
on the AHB.
nointr_I2S1_UP (offset 0x10A8 bit[2]) also stores this data in the command buffer when writing to the
rtd_trg_I2S1_UP.
nointr_I2S1_UP (offset 0x10A8 bit[2])1'b0: outputs a completion interrupt when the process written to the buffer is executed.
1'b1: does not output a completion interrupt when the process written to the buffer is executed.
Since the nointr_I2S1_UP setting is stored in the command buffer, it can be defined for each command.
By writing “2'b01” to the rtd_trg_I2S0_DOWN (offset 0x10C8 bit[1:0]), the various settings for reading out
data from the SRAM on the AHB are written to the command buffer of the I2S0 line. Each time writing (the samevalue) is performed, the data is issued to the command buffer. When writing “2'b00”, a STOP command is written
to the command buffer and the DMAC stops operation after executing all settings remaining in the command
buffer.
Setting “2'b10” or “2'b11” is prohibited.
For the readout values of the rtd_trg_I2S0_DOWN, refer to Section 3.15.7.3.

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CXD5602 User Manual

Defines the start Byte address of the transfer source memory when reading out data from the SRAM on thestart_adr_I2S0_DOWN (offset 0x10C0 bit[31:2]) AHB. Used by the BUS I/F I2S0.
Sets the value of subtracting 1 from the number of transfer samples when reading data from the SRAM on thesample_no_I2S0_DOWN (offset 0x10C4 bit[31:0]) AHB.
This data is also stored in the command buffer when writing the nointr_I2S0_DOWN (offset 0x10C8 bit[2])rtd_trg_I2S0_DOWN.
nointr_I2S0_DOWN (offset 0x10C8 bit[2])1'b0: outputs a completion interrupt when the process written to the buffer is executed.
1'b1: does not output a completion interrupt when the process written to the buffer is executed.
Since the nointr_I2S0_DOWN setting is stored in the command buffer, it can be defined for each command.
By writing “2'b01” to the rtd_trg_I2S1_DOWN (offset 0x10E8 bit[1:0]), the various settings for reading out
data from the SRAM on the AHB are written to the command buffer of the I2S1 line. Each time writing (the samevalue) is performed, the data is written to the command buffer. When writing “2'b00”, a STOP command iswritten to the command buffer and the DMAC stops operation after executing all settings remaining in thecommand buffer.
Setting “2'b10” or “2'b11” is prohibited.
For the readout values of the rtd_trg_I2S1_DOWN, refer to Section 3.15.7.4.
start_adr_I2S1_DOWN (offset 0x10E0 bit[31:2])
Defines the start Byte address of the transfer source memory when reading out data from the SRAM on the AHB.
Used by the BUS I/F I2S1.
sample_no_I2S1_DOWN (offset 0x10E4 bit[31:0])
Sets the value of subtracting 1 from the number of transfer samples when reading out data from SRAM on the
AHB. Used by the BUS I/F I2S1.
nointr_I2S1_DOWN (offset 0x10E8 bit[2])This data is also stored in the command buffer when writing the rtd_trg_I2S1_DOWN.
1'b0: outputs a completion interrupt when the process written to the buffer is executed.
1'b1: does not output a completion interrupt when the process written to the buffer is executed.
Since the nointr_I2S1_DOWN setting is stored in the command buffer, it can be defined for each command.

3.15.6.19.6

Command Processing I/F Status Signal

Refer to Section 3.15.7.

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3.15.6.19.7

BUS ERROR Detection (MIC)

When you need to detect BUS ERRORs of MIC line transfers for debugging purposes upon developing
FIRMWARE, set the offset 0x1730 bit[31:0] to “0x00000303”. The change of this setting is prohibited during
DMAC transfers. Furthermore, by setting cmb_mic_MASK (offset 0x114C bit[3]) to “1'b0” , the BUS ERROR
interrupt mask is canceled, and for MIC signal upload, an interrupt will be issued when a BUS ERROR occurs.
If the cause of the interrupt is related to the MIC line, the readout value of cmb_mic (offset 0x1140 bit[3])becomes “1'b1”. The readout value of cmb_mic (offset 0x1140 bit[3]) can be cleared by setting “1'b1” to the
cmb_mic itself.

3.15.6.19.8

BUS ERROR Detection (I2S0, I2S1)

Regarding the I2S line, when a BUS ERROR is detected during transfer, make the settings shown below.

Table 3.15-13 I2S0, I2S1 Line BUS ERROR Detection SettingsLineaddress offset

Path desired to detect BUS ERROR

Setting Value

I2S0

0x1F30DOWN side (SRAM readout)

0x00000101

UP side (SRAM write)

0x00000202

Both Up and DOWN

0x00000303

DOWN side (SRAM readout)

0x00000101

UP side (SRAM write)

0x00000202

Both UP and DOWN

0x00000303

I2S1

0x2730After making the above setting, in the case that a BUS ERROR occurs in reading/writing data of I2S0 line,
under the condition that cmb_I2S0_MASK (offset 0x1150 bit[5]) is “1'b0”, the readout value of the cmb_I2S0(0x1144 bit[5]) becomes “1'b1”.
In the case that a BUS ERROR occurs in reading/writing data of I2S1 line, under the condition that
cmb_I2S1_MASK (offset 0x1154 bit[5]) is “1'b0”, the readout value of the cmb_I2S1 (0x1148 bit[5]) becomes“1'b1”.
The readout values of the cmb_I2S0 and cmb_I2S1 can be cleared by setting themselves to “1'b1”.
Note that when a BUS ERROR occurs, the DMAC error can only be canceled by system reset of the Audio Codec.

3.15.73.15.7.1

Status Register
Device ID, Revision ID

For the Device ID, the readout value of the offset 0x0000 bit[31:24] is set to “8'h01”. For the Revision ID, thereadout value of the offset 0x0000 bit[23:16] is set to “8'h10”.

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3.15.7.2

AHB I/F Control of DMAC Related to MIC Signal

3.15.7.2.1

Command Buffer Monitor

By reading the monbuf_MIC (offset 0x1014 bit[19:16]), the remaining amount of commands related to the MIC
signal can be monitored. Up to three commands can be stored in the command buffer.
When the command buffer becomes empty, the readout value of the rtd_trg_MIC[0] (offset 0x1008 bit[0])becomes “1'b0”. When the command buffer is not empty, the readout value of the rtd_trg_MIC[0] becomes “1'b1”.

3.15.7.2.2

Error Notification

error_setting2_MIC (offset 0x1014 bit[10])When the bitwt_MIC is set to “1'b1”, there are restrictions in the settings of ch{n}_sel_MIC (n = 5 to 8), andwhen an incorrect setting is made, the error_setting2_MIC becomes “1'b1”.
・When the bitwt_MIC is set to “1'b1”, ch5_sel_MIC, ch6_sel_MIC, ch7_sel_MIC, and ch8_sel_MIC cannot be
selected, and each setting must be set to 0x8 or higher (unselected as a transfer channel).
error_setting1_MIC (offset 0x1014 bit[9])When the bitwt_MIC is set to “1'b1”, there are restrictions in the settings of ch{n}_sel_MIC (n = 1 to 4), andwhen an incorrect setting is made, the error_setting1_MIC becomes “1'b1”.
・When bitwt_MIC is set to “1'b1”, ch1_sel_MIC, ch2_sel_MIC, ch3_sel_MIC, and ch4_sel_MIC must not be set
to 0x4, 0x05, 0x6, or 0x7.
error_setting0_MIC (offset 0x1014 bit[8])The ch{n}_sel_MIC (n=1 to 8) must be selected in order as transfer channels. When the number of required
transfer channels is less than eight, unselect the ones that are not used in the order of ch8_sel_MIC =>ch7_sel_MIC => ch6_sel_MIC.
In the case of violating these restrictions, the error_setting0_MIC becomes “1'b1”.
Also note that when all ch{n}_sel_MIC (n=1 to 8) are unselected, the error_setting0_MIC becomes “1'b1”.
In the case of starting the command that uploads/downloads the MIC signal when the error_setting0_MIC,
error_setting1_MIC, or error_setting2_MIC has been turned to “1'b1”, the internal DMAC block will hang
up. A hardware reset is required for restart.

3.15.7.2.3

Command Status

start_MIC (offset 0x1014 bit[0])When the START command written to the command buffer starts execution, the corresponding bit becomes “1”and then changes to “0” at completion. This is for the MIC signal processing.

3.15.7.3

AHB I/F Control of DMAC Related to I2S0 Signal

3.15.7.3.1

Command Buffer Monitor

At the monbuf_I2S0_UP (offset 0x1094 bit[19:16]) and the monbuf_I2S0_DOWN (offset 0x10D4 bit[19:16]),－1084/1293－

CXD5602 User Manual

the remaining amount of commands related to the I2S0 signal can be monitored. The UP side (upload from the
I2S0 to the SRAM on the AHB) is monbuf_I2S0_UP, and the DOWN side (download to the I2S0 from the SRAM
on the AHB) is monbuf_I2S0_DOWN. Up to three commands for each the UP side and DOWN side can be stored
in the command buffer.
When the command buffer of the UP side becomes empty, the readout value of the rtd_trg_I2S0_UP[0] (offset
0x1088 bit[0]) becomes “1'b0”. When the command buffer is not empty, the readout value of the
rtd_trg_I2S0_UP[0] becomes “1'b1”.
When the command buffer of the DOWN side becomes empty, the readout value of the rtd_trg_I2S0_DOWN[0](offset 0x10C8 bit[0]) becomes “1'b0”. When command buffer is not empty, the readout value of the
rtd_trg_I2S0_DOWN[0] becomes “1'b1”.

3.15.7.3.2

Error Notification

error_setting0_I2S0_UP (offset 0x1094 bit[8])When the bitwt_I2S0_UP is set to “1'b0”, the ch{n}_sel_I2S0 (n=1, 2) must be selected in order as transfer
channels. When the ch1_sel_I2S0_UP is unselected and a signal is selected for the ch2_sel_I2S0_UP, theerror_setting0_I2S0_UP becomes “1'b1”. Also, when both ch{n}_sel_I2S0 (n = 1, 2) are unselected, theerror_setting0_I2S0_UP becomes “1'b1”.
When the bitwt_I2S0_UP is set to “1'b1”, the transfer channel is uniquely determined, and since it cannot be
unselected, the error_setting0_I2S0_UP does not become “1'b1”.
In the case of starting the command that uploads the I2S0 signal when the error_setting0_I2S0_UP has
been turned to “1'b1”, the internal DMAC block will hang up. A hardware reset is required for restart.
error_setting0_I2S0_DOWN (offset 0x10D4 bit[8])When the bitwt_I2S0_DOWN is set to “1'b0”, the sd1_l_sel and sd1_r_sel must be selected in order as transfer
channels starting from channel 1.
When the sd1_l_sel is unselected and channel 2 is selected for the sd1_r_sel, the error_setting0_I2S0_DOWN
becomes “1'b1”.
Also, when both the sd1_l_sel and sd1_r_sel are unselected, the error_setting0_I2S0_DOWN becomes “1'b1”.
In

the

case

of

starting

thecommandthat

downloads

as

the

I2S0

signalwhen

theerror_setting0_I2S0_DOWN has been turned to “1'b1”, the internal DMAC block will hang up. A
hardware reset is required for restart.
When the bitwt_I2S0_DOWN is set to “1'b1”, the error_setting0_I2S0_DOWN does not become the value of“1'b1”.

3.15.7.3.3

Command Status

start_I2S0_UP (offset 0x1094 bit[0]) , start_I2S0_DOWN (offset 0x10D4 bit[0])－1085/1293－

CXD5602 User Manual

When the START command written to the command buffer starts execution, the start_I2S0_UP becomes “1” andthen changes to “0” at completion. This is for the I2S0 signal processing. The UP side is start_I2S0_UP and the
DOWN side is start_I2S0_DOWN.

3.15.7.4

AHB I/F Control of DMAC Related to I2S1 Signal

3.15.7.4.1

Command Buffer Monitor

At the monbuf_I2S1_UP (offset 0x10B4 bit[19:16]) and the monbuf_I2S1_DOWN (offset 0x10F4 bit[19:16]),
the remaining amount of commands related to the I2S1can be monitored. The UP side is monbuf_I2S1_UP, andthe DOWN side is monbuf_I2S1_DOWN. Up to three commands for each the UP side and DOWN side can be
stored in the command buffer.
When the command buffer of the UP side becomes empty, the readout value of the rtd_trg_I2S1_UP[0] (offset
0x10A8 bit[0]) becomes “1'b0”. When the command buffer is not empty, the readout value of the
rtd_trg_I2S1_UP[0] becomes “1'b1”.
When the command buffer of the DOWN side becomes empty, the readout value of the rtd_trg_I2S1_DOWN[0](offset 0x10E8 bit[0]) becomes “1'b0”. When command buffer is not empty, the readout value of the
rtd_trg_I2S1_DOWN[0] becomes “1'b1”.

3.15.7.4.2

Error Notification

error_setting0_I2S1_UP (offset 0x10B4 bit[8])When the bitwt_I2S1_UP is set to “1'b0”, the ch{n}_sel_I2S1 (n = 1, 2) must be selected in order as transfer
channels. When the ch1_sel_I2S1_UP is unselected and a signal is selected for the ch2_sel_I2S1_UP, theerror_setting0_I2S1 becomes “1'b1”. Also, when both ch{n}_sel_I2S1 (n = 1, 2) are unselected, theerror_setting0_I2S1 becomes “1'b1”.
When the bitwt_I2S1_UP is set to “1'b1”, the transfer channel is uniquely determined, and since it cannot be
unselected, the error_setting0_I2S1_UP does not become “1'b1”.
In the case of starting the command that uploads the I2S1 signal when the error_setting0_I2S1_UP has
been turned to “1'b1”, the internal DMAC block will hang up. A hardware reset is required for restart.
error_setting0_I2S1_DOWN (offset 0x10F4 bit[8])When the bitwt_I2S1_DOWN is set to “1'b0”, the sd2_l_sel and sd2_r_sel must be selected in order as transfer
channels starting from channel 1.
When the sd2_r_sel is unselected and channel 2 is selected for the sd2_l_sel, the error_setting0_I2S1_DOWN
becomes “1'b1”.
Also, when both the sd2_l_sel and sd2_r_sel are unselected, the error_setting0_I2S1_DOWN becomes “1'b1”.
In

the

case

of

starting

thecommandthat

downloads

as

the

I2S1

signalwhen

theerror_setting0_I2S1_DOWN has been turned to “1'b1”, the internal DMAC block will hang up. A
hardware reset is required for restart.

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CXD5602 User Manual

When the bitwt_I2S1_DOWN is set to “1'b1”, the error_setting0_I2S1_DOWN does not become the value of“1'b1”.

3.15.7.4.3

Command Status

start_I2S1_UP (offset 0x10B4 bit[0]) , start_I2S1_DOWN (offset 0x10F4 bit[0])When the START command written to the command buffer starts execution, start_I2S1_UP becomes “1” and thenchanges to “0” at completion. This is for the I2S1 signal processing. The UP side is start_I2S1_UP and the
DOWN side is start_I2S1_DOWN.

3.15.83.15.8.1

Interrupt Flag
Interrupt Status (Signal Processing)

When an interrupt occurs, the cause can be known by reading the status register of the offset 0x1160. When aninterrupt occurs, each status register of the offset 0x1160 becomes “1'b1”.

Table 3.15-14 Signal Processing Interrupt Status Registers (offset 0x1160)
bit

Register Name

Factor[18]

ovf_smasr

Digital Amplifer R channel output overflow[17]

ovf_smasl

Digital Amplifer L channel output oveflow[10]

anc_faint

DMC Analyze results changed[9]

I2s_bck_err2

I2S1 line LRCK violation (1*)[8]I2s_bck_err1

I2S0 line LRCK violation (2*)[0]hresp_err

AHB communication error

1* Valid only when the M_SPCLKERR2(offset 0x0234 bit[1]) is set to “1'b0”
2* Valid only when the M_SPCLKERR1(offset 0x0234 bit[0]) is set to “1'b0”

3.15.8.2

Interrupt Clear (Signal Processing)

When an interrupt occurs and its status becomes “1'b1”, the interrupt status can be cleared to “1'b0” by setting
the following registers to “1'b1”. The interrupt clear registers are automatically reset to “1'b0”.

Table 3.15-15 Signal Processing Interrupt Clear Registers (offset 0x115C)
bit

Register NameThe Interrupt Factor that is Cleared[18]

clr_ovf_smasr

ovf_smasr[17]

clr_ovf_smasl

ovf_smasl[10]

clr_anc_faintanc_faint－1087/1293－

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3.15.8.3[9]clr_I2s_bck_err2I2s_bck_err2[8]clr_I2s_bck_err1

I2s_bck_err1[0]clr_hresp_err

hresp_err

Interrupt Mask (Signal Processing)

The occurrence factor of the interrupt flag can be masked. The mask is valid only for the interrupt flag and theinterrupt status becomes “1'b1”.

Table 3.15-16 Signal Processing Interrupt Mask Registers (offset 0x1158)

3.15.8.4

bit

Register Name

Interrupt Factor that is Masked[18]

m_ovf_smasr

ovf_smasr[17]

m_ovf_smasl

ovf_smasl[10]

m_anc_faintanc_faint[9]

m_I2s_bck_err2I2s_bck_err2[8]m_I2s_bck_err1

I2s_bck_err1[0]m_hresp_err

hresp_err

Interrupt Status (for SRAM Transfer, AHB I/F)

The following shows the interrupt factors of the AHB I/F system used for SRAM transfers.

Table 3.15-17 AHB I/F Interrupt Status Registers (offset 0x1140)
bit

Register Name

Factor[3]

cmb_MICAHB BUS Error interrupt. Also refer to Section 3.15.6.19.

[2]

smp_MIC

Sampling interrupt. Occurs at the timing of each internal fs cycle.

[1]

err_MIC

Transfer error interrupt. Input sample data loss occurs due to transfer
command issuance delays or transfer delays.

[0]

done_MIC

Transfer command completion interrupt

The above registers change to “1'b1” when an interrupt factor occurs during data exchange with the SRAM on
the AHB by the DMAC of the MIC line.

Table 3.15-18 AHB I/F Interrupt Status Registers (offset 0x1144)
bit

Register Name

Factor[5]

cmb_I2S0

AHB BUS Error interrupt. Also refer to Section 3.15.6.19.

[4]smp_I2S0

Sampling interrupt. Occurs at the timing of each internal fs cycle.

[3]

err_I2S0I

Transfer error interrupt. Input sample data loss occurs due to transfer－1088/1293－

CXD5602 User Manualcommand issuance delays or transfer delays when transferring I2S0 line
data to the SRAM on the AHB.
[2]

done_I2S0I

Completion interrupt of the command that transfers I2S0 line data to the
SRAM on the AHB.

[1]

err_I2S0O

Transfer error interrupt. Input sample data loss occurs due to transfer
command issuance delays or transfer delays when transferring data in
the SRAM on the AHB as I2S0 line data.

[0]

done_I2S0O

Completion interrupt of the command that transfers data in the SRAM
on the AHB as I2S0 line data.

The above registers change to “1'b1” when an interrupt factor occurs during data exchange with the SRAM on
the AHB by the DMAC of the I2S0 line.

Table 3.15-19 AHB I/F Interrupt Status Registers (offset 0x1148)
bit

Register Name

Factor[5]

cmb_I2S1AHB BUS Error interrupt. Also refer to Section 3.15.6.19.

[4]smp_I2S1

Sampling interrupt. Occurs at the timing of each internal fs cycle.

[3]

err_I2S1I

Transfer error interrupt. Input sample data loss occurs due to transfer
command issuance delays or transfer delays when transferring I2S1 line
data to the SRAM on the AHB.

[2]

done_I2S1I

Completion interrupt of the command that transfers I2S1 line data to the
SRAM on the AHB.

[1]

err_I2S1O

Transfer error interrupt. Input sample data loss occurs due to transfer
command issuance delays or transfer delays when transferring data in
the SRAM on the AHB as I2S1 line data.

[0]

done_I2S1OCompletion interrupt of the command that transfers data in the SRAM
on the AHB as I2S1 line data.

The above registers change to “1'b1” when an interrupt factor occurs during data exchange with the SRAM on
the AHB by the DMAC of the I2S1 line.

3.15.8.5

Interrupt Clear (for SRAM Transfer, AHB I/F)

The registers listed on Table 3.15-17, Table 3.15-18, and Table 3.15-19 can be cleared to “1'b0” by writing“1'b1” to the registers themselves.

3.15.8.6

Interrupt Mask (AHB I/F)

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CXD5602 User Manual

The following shows the mask control signals for interrupts of the AHB I/F line used for SRAM transfers.

Table 3.15-20 AHB I/F Interrupt Mask Registers (offset 0x114C)
bit

Register Name

Interrupt Factor that is Masked[3]

cmb_MIC_MASK

cmb_MIC[2]

smp_MIC_MASK

smp_MIC[1]

err_MIC_MASK

err_MIC[0]done_MIC_MASK

done_MIC

Table 3.15-21 AHB I/F Interrupt Mask Registers (offset 0x1150)
bit

Register Name

Interrupt Factor that is Masked[5]cmb_I2S0_MASK

cmb_I2S0[4]

smp_I2S0_MASK

smp_I2S0[3]

err_I2S0I_MASK

err_I2S0I[2]done_I2S0I_MASK

done_I2S0I[1]

err_I2S0O_MASK

err_I2S0O[0]

done_I2S0O_MASK

done_I2S0O

Table 3.15-22 AHB I/F Interrupt Mask Registers (offset 0x1154)
bit

Register Name

Interrupt Factor that is Masked[5]cmb_I2S1_MASK

cmb_I2S1[4]

smp_I2S1_MASK

smp_I2S1[3]

err_I2S02_MASK

err_I2S1I[2]

done_I2S1I_MASK

done_I2S1I[1]

err_I2S1O_MASK

err_I2S1O[0]

done_I2S1O_MASK

done_I2S1O

By setting the above registers to “1'b1”, the interrupts can be masked.
Regarding cmb_MIC_MASK, cmb_I2S0_MASK, and cmb_I2S1_MASK, also refer to Section 3.15.6.19.
When set to “1'b1”, the CPU will not be interrupted even when an interrupt factor occurs, but the status register ofthe interrupt factor will change to “1'b1”.

3.15.9

Audio Codec Control Register List

The following is the 32 bit address offset from the CPU. To calculate the addresses from the CPU, add thisaddress to the offsets in the list.

－1090/1293－

CXD5602 User Manual

Offset:0x02300000 (Mirror:0x0E300000)

3.15.9.1

System Control Registers

Table 3.15-23 System Control Register List
offsetRegister

(Hex)

Name

0x0100

Audio_Codec_0100

0x0104

Audio_Codec_0104

Bit Field Name

Type

Bit

InitialDescription

Value
Reserved

RW[31:24]

PDN_DSPC

[23]

1'b1

refer

PDN_DSPS1

[22]

1'b1

3.15.6.3

PDN_DSPS2

[21]

1'b1

PDN_SMSTR

[20]

1'b1

PDN_DSPB

[16]

1'b1

PDN_DMIC

[15]

1'b1

Reserved[14:11]

PDN_MIC

[10]

1'b1

use initial setting

PDN_LINEIN

[9]

1'b1

use initial setting

PDN_DAC[8]

1'b1

use initial setting

Reserved[7]

PDN_AMIC2

[6]

1'b1

refer

PDN_AMIC1

[5]

1'b1

3.15.6.3

PDN_AMICEXT

[4]

1'b1

Reserved[3:0]

ReservedRW

MCK_AHBMSTR_E

toSectiontoSectiontoSectiontoSectiontoSectiontoSectiontoSection[31:20]
[19]

1'b0

refer
3.15.6.3

N
SDES_EN

[18]

1'b0

refer
3.15.6.5

Reserved[17]

DECIM_EN

[16]

1'b0

refer
3.15.6.12

Reserved[15:1]

FS_FS

[0]

1'b0

refer
3.15.6.60x0108

Audio_Codec_0108

Reserved

RW[31:30]refer

COD_INSEL1[29:28]2'h0

COD_INSEL2[27:26]2'h0－1091/1293－

3.15.6.4

CXD5602 User Manual

0x11FC

COD_INSEL3[25:24]

Reserved[23]

AU_DAT_SEL1[22:20]Reserved[19]

AU_DAT_SEL2[18:16]

Reserved[15:0]

Audio_Codec_11F

Reserved

C

tresh

RW

2'h0

3'h0

3'h0

[31:8]
[7:0]

8'h64

refer

to

Section

3.15.6.16

3.15.9.2

Codec DSP Control Registers

Table 3.15-24 Codec DSP Control Register List
offsetRegister

(Hex)

Name

0x0200

Audio_Codec

Bit Field Name

Type

Bit

InitialDescription

Value
HI_RES_MODE

RW

[31]

1'b0

_0200

refer

to

Section

3.15.6.11
SDCK_OUTENX

[30]

1'b0

refer

SD1MASTER

[29]

1'b0

3.15.6.8

SD2MASTER

[28]

1'b0

DIF1

[27]

1'b1

DIF2

[26]

1'b1

Reserved[25:24]SRC2IN_SEL[23:22]

2'h2

refer

SRC2

[21:20]2'h1

3.15.6.8.2

SRC1IN_SEL[19:18]

2'h2

SRC1

[17:16]2'd1

Reserved[15:13]

DIGSFT

[12]

1'b1

refer

to

SectiontoSectiontoSection

3.15.6.11
Reserved[11:3]

DSR_RATE

[2:0]

3'h0

refer

to

Section

3.15.6.110x0204

Audio_Codec

INV_AMIC1R

_0204

RW

[31]

1'b0

refer

INV_AMIC1L

[30]

1'b0

3.15.6.7

ADC_FS[29:28]2'h0

Reserved[27]－1092/1293－

toSectionCXD5602 User Manual

0x0208

ADC1_BOOST

[26]

1'b0

use initial setting

CIC1IN_SEL

[25]

1'b0

refer

CIC1_GAIN_MODE

[24]

1'b0

3.15.6.7

INV_DMIC1R

[23]

1'b0

INV_DMIC1L

[22]

1'b0

CIC1IN_SWAP

[21]

1'b0

Reserved[20:18]

HPF1_MODE[17:16]

2'd0

refer

INV_AMIC2R

[15]

1'b0

3.15.6.7

INV_AMIC2L

[14]

1'b0

Reserved[13:11]

ADC2_BOOST

[10]

1'b0

use initial setting

CIC2IN_SEL

[9]

1'b0

refer

CIC2_GAIN_MODE

[8]

1'b0

3.15.6.7

INV_DMIC2R

[7]

1'b0

INV_DMIC2L

[6]

1'b0

CIC2IN_SWAP

[5]

1'b0

Reserved[4:2]

HPF2_MODE

[1:0]

2'd0

refer

[31]

1'b0

3.15.6.7

1'b0

RW

to

SectiontoSectiontoSectiontoSectionAudio_Codec

INV_AMIC3R_0208

INV_AMIC3L[30]

Reserved[29:27]

ADC3_BOOST

[26]

1'b0

use initial setting

CIC3IN_SEL

[25]

1'b0

refer

to

SectiontoSectiontoSection

3.15.6.7
Reserved[24]

INV_DMIC3R

[23]

1'b0

refer

INV_DMIC3L

[22]

1'b0

3.15.6.7

CIC3IN_SWAP

[21]

1'b0

Reserved[20:18]

HPF3_MODE[17:16]

2'd0

refer

INV_AMIC4R

[15]

1'b0

3.15.6.7

INV_AMIC4L

[14]

1'b0

Reserved[13:11]

ADC4_BOOST

[10]

1'b0

use initial setting

CIC4IN_SEL

[9]

1'b0

refer
3.15.6.7

Reserved[8]－1093/1293－

toSectionCXD5602 User Manual

INV_DMIC4R

[7]

1'b0

refer

INV_DMIC4L

[6]

1'b0

3.15.6.7

CIC4IN_SWAP

[5]

1'b0

Reserved[4:2]

HPF4_MODE

[1:0]

2'd0

refer

to

SectiontoSection

3.15.6.7

Table 3.15-25 Codec DSP Control Register List
offsetRegister

(Hex)

Name

0x020C

0x02100x02140x02180x021C

0x02200x02240x0228Bit Field Name

Type

Bit

Initial Value

Description

Audio_Codec

CIC1_LGAIN

RW[31:16]

16'h4000

refer

_020C

CIC1_RGAIN[15:0]

16'h4000

3.15.6.7

Audio_Codec

CIC2_LGAIN[31:16]

16'h4000_0210

CIC2_RGAIN[15:0]

16'h4000

Audio_Codec

CIC3_LGAIN[31:16]

16'h4000_0214

CIC3_RGAIN[15:0]

16'h4000

Audio_Codec

CIC4_LGAIN[31:16]

16'h4000_0218

CIC4_RGAIN[15:0]

16'h4000

Audio_Codec

ALC_EN

[31]

1'b0

refer

_021C

ALC_REC

[30]

1'b1

3.15.6.11

ALC_TARGET[29:24]

6'h00

Reserved[23]

ALC_KNEE[22:16]

7'h08

refer

SPC_EN[15]

1'b0

3.15.6.11

SPC_LIMIT[14:8]

7'h00

Reserved

[7:0]

RW

RW

RW

RW

Audio_Codec

ARC

_0220

Reserved[28:20]

INV_ASP1L

to

SectiontoSectionuse initial setting

[19]

1'b0

refer

INV_ASP1R

[18]

1'b0

3.15.6.8

INV_ASP2L

[17]

1'b0

INV_ASP2R

[16]

1'b0

Reserved[15:0]

ARC_VOL_0224

Reserved

Audio_Codec

SDIN1_VOL_0228

SDIN2_VOL

RW[31:29]Section3'h4

Audio_Codec

RW

to[31:8]

toSection24'h800000

use initial setting[31:24]

8'h33

refer

[23:16]8'h33

3.15.6.11

[7:0]
RW

－1094/1293－

toSectionCXD5602 User Manual

SDOUT_VOL[15:8]

8'h33

CS_SIGN[7]

1'b0

CS_VOL

[6:0]

7'h00

Initial Value

Description

Table 3.15-26 Codec DSP Control Register List
offsetRegister

Bit Field Name

Type

Bit

(Hex)

Name

0x022C

Audio_Codec

Reserved

RW[31:24]_022C

LINEIN_VOL[23:16]

8'h33

refer

DAC_VOL[15:8]

8'h33

3.15.6.11

Reserved[7]

TRANS_MODE

[6]

1'b0

refer

to

to

SectionSection

3.15.6.13
BLF_EN

[5]

1'b0

refer

to

Section

3.15.6.10
MUTE_B

[4]

1'b0

refer

to

Section

3.15.6.11

0x02300x02340x0240SDOUT2_EN

[3]

1'b0

refer

SDOUT1_EN

[2]

1'b0

3.15.6.8

SDIN2_EN

[1]

1'b0

SDIN1_EN

[0]

1'b0

[31]

1'b0

Audio_Codec

BEEP_ON

RW_0230

Reserved[30]

BEEP_FREQ[29:24]

Reserved[23:21]

BEEP_VOL[20:16]

Reserved[15:0]
RW[31:2]

M_SPCLKERR2

[1]

1'b1

M_SPCLKERR1

[0]

1'b1

_0240

ADC2R_VOL[30:24]

Reserved[23]

ADC2L_VOL[22:16]

Reserved[15]

ADC1R_VOL[14:8]

Reserved[7]－1095/1293－

Section

5'h04

_0234

RW

to

6'h00

Reserved

Reserved

Section

3.15.6.11

Audio_Codec

Audio_Codec

refer

to

refer

[31]

7'h00

7'h00

SectiontoSection

3.15.8.1

refer
7'h00

to

3.15.6.7

CXD5602 User Manual

ADC1L_VOL

[6:0]

7'h00

Table 3.15-27 Codec DSP Control Register List
offsetRegister

Bit Field Name

Type

Bit

Initial Value

Description

(Hex)

Name

0x0400

Audio_Codec

DSPRAM1_CLR

RW

[31]

1'b0

refer

_0400

DSPRAM2_CLR

[30]

1'b0

3.15.6.14

DSPRAM3_CLR

[29]

1'b0

DSPRAM4_CLR

[28]

1'b0

Reserved[27:24]

ARWPHSET

[23]

1'b0

use initial setting

BEEP_TEST

[22]

1'b0

use initial setting

FSRDBGMD

[21]

1'b0

use initial setting

Reserved[20]

HALT_INHIBIT

[19]

1'b1

refer

to

SectiontoSectiontoSection

3.15.6.3
Reserved[18:17]

S_RESET

[16]

1'b0

refer

3.15.6.15

0x0404

TEST_IN[15:8]

8'h00

use initial setting

TEST_OUT

[7:0]

8'h00

use initial setting

1'b1

refer

Audio_Codec

Reserved_0404

SPC_AWEIGHT

RW[31:24][23]

toSection

3.15.6.110x04080x040C

0x0410Reserved[22]

ARC_DELAY[21:20]

2'b10

use initial setting

ARC_TIMER[19:16]

4'h0

use initial setting

ALC_ALG

[15]

1'b0

refer

ALC_DELAY[14:8]

7'h10

3.15.6.11

Reserved[7:0]

Audio_Codec

Reserved

RW

_0408

SPC_ALC_ATTACK

Audio_Codec

Reserved_040C

SPC_ALC_RELEASE

Audio_Codec

Reserved_0410

ALC_LPF[31:24][23:0]

RW

24'h000100

SectiontoSection

3.15.6.11
refer

24'h0141B3

toSection

3.15.6.11
refer[31:24][23:0]－1096/1293－

24'h400000[31:24][23:0]

RW

refer

to

to

3.15.6.11

SectionCXD5602 User Manual

3.15.9.3

Digital Amplifer Control Registers

Table 3.15-28 DNC, S-Master Control Register List
offsetRegister

(Hex)

Name

0x03000x0308Bit Field Name

Type

Bit

Audio_Codec

Reserved

RW[31:8]_0300

SMS_INTIM

Audio_Codec

DCMFS

RW

Initial Value

[7:0]

8'd0

[31:30]

2'b01

_0308

Description

refer

to

SectiontoSectiontoSection

3.15.6.7
Reserved[28:24]

DCMFS_34[23:22]

2'b01

refer
3.15.6.7

0x0340

Audio_Codec

Reserved[21:17]

Reserved[15:0]NSPMUTE

RW

[31]

1'b1

_0340

refer

3.15.6.13
NSX2

[30]

1'b0

refer

to

Section

3.15.6.13
NSADJON

[29]

refer

to

Section

3.15.6.13
Reserved

[28]

CHSEL

[27]

1'b0

NSMS

[26:24]

3'd2

BPON

[23]

1'b0

refer

to

Section

3.15.6.13
NSII

[22]

1'b0

NSDI

[21]

1'b0

Reserved

[20]

BPSEL

[19:16]

4'd0

refer

to

Section

3.15.6.13
BPGAIN[15:8]

8'hFF

refer

to

Section

3.15.6.13
Reserved[7:4]

NS_AMMD

[3:0]

4'd0

refer

to

3.15.6.13
0x0344

Audio_Codec

Reserved

RW[31:24]－1097/1293－

SectionCXD5602 User Manual_0344

OUT2DLY[23:20]

4'd0

NSDD

[19:0]

20'd0

refer

to

Section

3.15.6.13
0x0348

Audio_Codec

Reserved

RW[31:24]

_0348

NSAS

[23:22]

2'b00

PWMMD

[21:20]

2'b01

refer

to

Section

3.15.6.13
NSAD
0x034

Audio_Codec

VCONT

C

_034C

NSADJ

RW

[19:0]

20'd0[31:24]

8'd0[23:16]

8'd0

refer

to

Section

3.15.6.13
Reserved

3.15.9.4[15:0]CXD5247 I/F Control Registers

Table 3.15-29 CXD5247 I/F Control Register List
offsetRegister

Bit Field Name

Type

Bit

(Hex)

Name

0x0500

Audio_Codec

Reserved

RW[31:25]_0500

FS_CLK_EN[24]

Initial Value

Description

1'b0

refer

to

SectiontoSectiontoSectiontoSection

3.15.6.5
Reserved[23:17]

PDM_OUT_EN

[16]

1'b0

refer
3.15.6.5

Reserved[15:1]

SER_MODE

[0]

1'b0

refer
3.15.6.6

0x0504

Audio_Codec

Reserved

RW

[31]

_0504

SEL_OUT1_L[30:28]Reserved[27]

SEL_OUT1_R[26:24]

Reserved[23]

SEL_OUT2_L[22:20]Reserved[19]

SEL_OUT2_R[18:16]

Reserved[15]

SEL_OUT3_L[14:12]－1098/1293－

refer
3'h0

3'h1

3'h2

3'h3

3'h4

3.15.6.7

CXD5602 User Manual

0x06783.15.9.5

Reserved[11]

SEL_OUT3_R[10:8]

Reserved[7]

SEL_OUT4_L[6:4]

Reserved[3]

SEL_OUT4_R

[2:0]
RW

3'h5

3'h6

3'h7

Audio_Codec

Reserved[31:2]

refer

_0678

LR_SWAP2

[1]

1'b0

LR_SWAP1

[0]

1'b0

to

Section

3.15.6.8

Other Signal Processing Control Registers

Table 3.15-30 Decimation Filter Control Register List
offsetRegister

Bit Field Name

Type

Bit

(Hex)

Name

0x0580

Audio_Codec

Reserved

RW[31:25]_0580

SEL_DECIM[24]

Reserved[23:21]

SEL_INF[20]

Reserved[19:18]

SEL_OUTF[17:16]

Reserved[15:8]OUTEN_MIC2R_A

[7]

1'b0

OUTEN_MIC2L_A

[6]

1'b0

OUTEN_MIC1R_A

[5]

1'b0

OUTEN_MIC1L_A

[4]

1'b0

OUTEN_MIC2R_B

[3]

1'b0

OUTEN_MIC2L_B

[2]

1'b0

OUTEN_MIC1R_B

[1]

1'b0

OUTEN_MIC1L_B

[0]

1'b0

Table 3.15-31 DEQ Control Register List

3.15.9.6

SRAM Registers

Table 3.15-32 SRAM Register List

－1099/1293－

Initial Value

Description

refer
1'b0

1'b0

2'h0

3.15.6.12

toSectionCXD5602 User Manual

offsetRegister Name

Bit Field Name

Type

Bit

Audio_Codec_0780

Reserved

RW[31:1]

Initial Value

Description

(Hex)
0x078
0

RAM_RW_EN[0]refer to1'b0

Sectionエラー! 参照元が見つかりません。

3.15.9.7

AHB I/F Control Registers

Table 3.15-33 AHB I/F MIC Control Register List
offsetRegister Name

Bit Field Name

Type

Bit

Initial Value

Description

Audio_Codec_1000

start_adr_MIC

RW[31:2]

30'h00000000

refer to Section

(Hex)
0x100
0
0x100

Reserved
Audio_Codec_1004

3.15.6.19[1:0]

sample_no_MIC

RW[31:0]

32'h00000000

4
0x100

3.15.6.19
Audio_Codec_1008

8

0x100

Audio_Codec_100C

C
0x101

4

Reserved

RW

Audio_Codec_1010

Audio_Codec_1014[31:3]

refer to Section

nointr_MIC

[2]

1'b0

rtd_trg_MIC

[1:0]

2'b00

Reserved

RW[31:1]

3.15.6.19

refer to Section

[0]

1'b0

3.15.6.19[31:28]4'h0

refer to Section

ch2_sel_MIC[27:24]4'h0

3.15.6.19

ch3_sel_MIC[23:20]4'h0ch4_sel_MIC[19:16]4'h0

ch5_sel_MIC[15:12]4'h0

ch6_sel_MIC[11:8]

4'h0

ch7_sel_MIC

[7:4]

4'h0

ch8_sel_MIC

[3:0]

4'h0

bitwt_MIC

0

0x101

refer to Section

ch1_sel_MIC

RWReservedR[31:20]refer to Section

monbuf_MIC[19:16]3.15.7.2

Reserved[15:11]error_setting2_MIC[10]error_setting1_MIC[9]error_setting0_MIC[8]Reserved[7:1]

start_MIC[0]－1100/1293－

CXD5602 User Manual

Table 3.15-34 AHB I/F I2S0 (UP) Control Register List
offsetRegisterParameter Bit Field Name

Type

Bit

Initial Value

Description

(Hex)

Name

0x108

Audio_Codec

start_adr_I2S0_UP

RW[31:2]

30'h00000000

refer to Section

0

_1080

Reserved

0x108

Audio_Codec

sample_no_I2S0_UP

4

_1084

0x108

Audio_Codec

Reserved

8_1088

nointr_I2S0_UP

[2]

1'b0

rtd_trg_I2S0_UP

[1:0]

2'b00

3.15.6.19

[1:0]
RW

[31:0]

32'h00000000

refer to Section
3.15.6.19

RW

0x108

Audio_Codec

Reserved

C_108C

bitwt_I2S0_UP

0x109

Audio_Codec

Reserved

0_1090

ch1_sel_I2S0_UP[5:4]

Reserved[3:2]

ch2_sel_I2S0_UP

[1:0]

0x109

Audio_Codec

Reserved

4

_1094

RW

[31:3][31:1][0]

RW

R

refer to Section
3.15.6.19

refer to Section
1'b0[31:6]

3.15.6.19
refer to Section

2'b00

3.15.6.19

2'b00[31:20]refer to Section

monbuf_I2S0_UP[19:16]3.15.7.3

Reserved[15:9]

error_setting0_I2S0_UP[8]

Reserved[7:1]

start_I2S0_UP[0]

Table 3.15-35 AHB I/F I2S1 (UP) Control Register List
offsetRegister

Bit Field Name

Type

Bit

Initial Value

Description

(Hex)

Name

0x10A

Audio_Codec

start_adr_I2S1_UP

RW[31:2]

30'h00000000

refer

0

_10A0

Reserved

0x10A

Audio_Codec

sample_no_I2S1_UP

4

_10A4

0x10A

Audio_Codec

Reserved8_10A8

nointr_I2S1_UP

[2]

1'b0

rtd_trg_I2S1_UP

[1:0]

2'b00

[31:0]

Section

3.15.6.19

[1:0]
RW

to

32'h00000000

refer

to

Section

3.15.6.19

0x10A

Audio_Codec

ReservedC_10AC

bitwt_I2S1_UP

RW

RW[31:3][31:1][0]－1101/1293－

refer

to

Section

3.15.6.19

refer to Section エ
1'b0

ラー! 参照元がCXD5602 User Manual

見つかりません。
0x10B

Audio_Codec

Reserved0_10B0

ch1_sel_I2S1_UP[5:4]

Reserved[3:2]

ch2_sel_I2S1_UP

[1:0]

0x10B

Audio_Codec

Reserved

4

_10B4

RW

R

[31:6]

refer
2'b00

to

Section

3.15.6.19

2'b00[31:20]refer

tomonbuf_I2S1_UP[19:16]3.15.7.4

Reserved[15:9]

error_setting0_I2S1_UP[8]

Reserved[7:1]

start_I2S1_UP[0]

SectionTable 3.15-36 AHB I/F I2S0 (DOWN) Control Register List
offsetRegisterParameter Bit Field Name

Type

Bit

Initial Value

Description

(Hex)

Name

0x10C

Audio_Codec

start_adr_I2S0_DOWN

RW[31:2]

30'h00000000

refer to Section

0

_10C0

Reserved

0x10C

Audio_Codec

sample_no_I2S0_DOWN

4

_10C4

0x10C

Audio_Codec

Reserved

8_10C8

nointr_I2S0_DOWN

[2]

1'b0

rtd_trg_I2S0_DOWN

[1:0]

2'b00

3.15.6.19

[1:0]
RW

[31:0]

32'h00000000

refer to Section
3.15.6.19

RW

0x10C

Audio_Codec

ReservedC_10CC

bitwt_I2S0_DOWN

0x10D

Audio_Codec

Reserved0_10D0

sd1_l_sel[5:4]

Reserved[3:2]

sd1_r_sel

[1:0]

0x10D

Audio_Codec

Reserved

4

_10D4

RW

[31:3][31:1][0]

RW

R

refer to Section
3.15.6.19

refer to Section
1'b0[31:6]

3.15.6.19
refer to Section

2'b00

3.15.6.19

2'b00[31:20]refer to Section

monbuf_I2S0_DOWN[19:16]3.15.7.3

Reserved[15:9]

error_setting0_I2S0_DOWN[8]Reserved[7:1]

start_I2S0_DOWN[0]Table 3.15-37 AHB I/F I2S1 (DOWN) Control Register List

－1102/1293－

CXD5602 User Manual

offsetParameter Bit Field Name

Type

Bit

Initial Value

Description

RW[31:2]

30'h00000000

refer to Section

(Hex)
0x10E

Audio_Codec

start_adr_I2S1_DOWN

0

_10E0

Reserved

0x10E

Audio_Codec

sample_no_I2S1_DOWN

4

_10E4

0x10E

Audio_Codec

Reserved8_10E8

nointr_I2S1_DOWN

[2]

1'b0

rtd_trg_I2S1_DOWN

[1:0]

2'b00

3.15.6.19

[1:0]
RW

[31:0]

32'h00000000

refer to Section
3.15.6.19

RW

0x10E

Audio_Codec

ReservedC_10EC

bitwt_I2S1_DOWN

0x10F

Audio_Codec

Reserved0_10F0

sd2_l_sel[5:4]

Reserved[3:2]

sd2_r_sel

[1:0]

0x10F

Audio_Codec

Reserved

4

_10F4

RW

[31:3][31:1][0]

RW

R

refer to Section
3.15.6.19

refer to Section
1'b0[31:6]

3.15.6.19
refer to Section

2'b00

3.15.6.19

2'b00[31:20]refer to Section

monbuf_I2S1_DOWN[19:16]3.15.7.4

Reserved[15:9]

error_setting0_I2S1_DOWN[8]Reserved[7:1]

start_I2S1_DOWN[0]Table 3.15-38 AHB I/F Other Control Register List
offsetParameter Bit Field Name

Type

bit

Initial Value

RW[31:1]

Description

(Hex)
0x111

Audio_Codec

Reserved

0

_1110

ensel

0x11F

Audio_Codec

Reserved0_11F0

AHBMSTR_I2S1_EN

[2]

1'b0

AHBMSTR_I2S0_EN

[1]

1'b0

AHBMSTR_MIC_EN

[0]

1'b0

3.15.9.8

[0]
RW

refer
1'b0

[31:3]

to3.15.6.19
refer

to

3.15.6.19

Interrupt Control Registers

Table 3.15-39 AHB I/F Interrupt Control Register List
offset (Hex)Register Name

Bit Field Name

Type

－1103/1293－

Bit

Initial Value

SectionDescription

SectionCXD5602 User Manual

0x11400x11440x11480x114C0x1150

Audio_Codec_1140

Audio_Codec_1144

Audio_Codec_1148

Audio_Codec_114C

Audio_Codec_1150

Reserved

RW[31:4]

refer to Section

cmb_MIC[3]

1'b0

smp_MIC[2]

1'b0

err_MIC[1]

1'b0

done_MIC

[0]

1'b0

Reserved

RW[31:6]

refer to Section

cmb_I2S0

[5]

1'b0

smp_I2S0

[4]

1'b0

err_I2S0I

[3]

1'b0

done_I2S0I

[2]

1'b0

err_I2S0O

[1]

1'b0

done_I2S0O

[0]

1'b0

Reserved

RW

3.15.8.4[31:6]

3.15.8.4

refer to Section
3.15.8.4

cmb_I2S1

[5]

1'b0

smp_I2S1

[4]

1'b0

err_I2S1I

[3]

1'b0

done_I2S1I

[2]

1'b0

err_I2S1O

[1]

1'b0

done_I2S1O

[0]

1'b0

[31]

1'b0

use initial setting

nostpmask_MIC

[30]

1'b0

use initial setting

Reserved[29:4]

cmb_MIC_MASK

[3]

1'b1

refer to Section

smp_MIC_MASK

[2]

1'b1

3.15.8.6

err_MIC_MASK

[1]

1'b1

done_MIC_MASK

[0]

1'b1

[31]

1'b0

use initial setting

nostpmask_I2S0

[30]

1'b0

use initial setting

Reserved[29:6]

cmb_I2S0_MASK

[5]

1'b1

refer to Section

smp_I2S0_MASK

[4]

1'b1

3.15.8.6

err_I2S0I_MASK

[3]

1'b1

done_I2S0I_MASK

[2]

1'b1

err_I2S0O_MASK

[1]

1'b1

done_I2S0O_MAS

[0]

1'b1

[31]

1'b0

use initial setting

[30]

1'b0

use initial setting

srst_MIC

srst_I2S0

RW

RW

K
0x1154

Audio_Codec_1154

srst_I2S1

RW

nostpmask_I2S1－1104/1293－

CXD5602 User Manual

Reserved[29:6]

cmb_I2S1_MASK

[5]

1'b1

refer to Section

smp_I2S1_MASK

[4]

1'b1

3.15.8.6

err_I2S1I_MASK

[3]

1'b1

done_I2S1I_MASK

[2]

1'b1

err_I2S1O_MASK

[1]

1'b1

done_I2S1O_MAS

[0]

1'b1

K

Table 3.15-40 Signal Processing Interrupt Control Register List
offsetRegister

Bit Field Name

(Hex)

Name

0x115

Audio_Codec

Reserved

8

_1158

Type

Bit

InitialDescription

Value[31:25]refer to Section

Reserved[20:19]3.15.8.3

m_ovf_smasr

[18]

1'b1

m_ovf_smasl

[17]

1'b1

Reserved[16:11]m_anc_faint

[10]

1'b1

m_I2S0_bck_err2

[9]

1'b1

m_I2S0_bck_err1

[8]

1'b1

Reserved[7:1]

m_hresp_err

[0]

0x115

Audio_Codec

Reserved

C

_115C

RW

[31:25]refer to Section

Reserved[20:19]3.15.8.2

clr_ovf_smasr

[18]

1'b0

clr_ovf_smasl

[17]

1'b0

Reserved[16:11]

clr_anc_faint

[10]

1'b0

clr_I2S0_bck_err2

[9]

1'b0

clr_I2S0_bck_err1

[8]

1'b0

Reserved[7:1]

clr_hresp_err

[0]

0x116

Audio_Codec

Reserved

0

_1160

W

1'b1

R

1'b0

[31:25]refer to Section

Reserved[20:19]3.15.8.1

ovf_smasr[18]

ovf_smasl[17]

Reserved[16:11]－1105/1293－

CXD5602 User Manual

3.15.103.15.10.1

anc_faint[10]

I2S0_bck_err2[9]I2S0_bck_err1[8]

Reserved[7:1]

hresp_err[0]Control Sequence
Startup Control

The Audio Codec assumes startup by the below procedure.
(1) Power ON
Turn on the power.
(2) Asynchronous Reset Assert => Negate
Assert the asynchronous reset. This assumes that a clock is not supplied. Then, negate the asynchronous reset.
(3) Supply of Internal ClockSupply the internal clock.
(4) Setting of each Control Register, SRAM Initialization
Set each control register and initialize the SRAMs to be used.
Also refer to Section 3.15.6.14.1.
(5) Internal DSP Initialization
Using the control register, initialize the internal DSP. Also, wait for 20 ms after initialization until the mute isreleased.
(6) Perform VOL and other controls as necessary.

3.15.10.2

BUS I/F Control

3.15.10.2.1

SRAM Writing

The following is an example of the control routine when reading/writing data from/to the SRAM on the AHB
I/F.

－1106/1293－

CXD5602 User Manual

START

configure transfer mode
24bit/16bit

R/W

Addressbit

namewrite valueW

0x100C[0]

bitwt_MIC

any※During the DMA transfer,changing both the transfer mode setting and channel assign setting
is prohibited.

bitwt_MIC

interrupt about transfer
completion acceptedW

0x1140[0]done_MIC

1'b1

configure start addressW

0x1000[31:2]

start_adr_MIC

any

configure sample numberW

0x1004[31:0]

sample_no_MIC

any

Mask Interrupt

W

0x104C[1]

MSK_err_MIC

1'b1

SMP clearW

0x1140[2]

smp_MIC

1'b1

SMP status?

R

0x1140[2]

smp_MIC---W

0x1010[31:0]---

32'hFFFF_FFFF

W

0x1010[31:28]ch1_sel_MIC

any

W

0x1010[15:12]ch5_sel_MIC

any

W

0x1010[27:24]ch2_sel_MIC

any

W

0x1010[11:8]

ch6_sel_MIC

any

W

0x1010[23:20]ch3_sel_MIC

any

W

0x1010[7:4]

ch7_sel_MIC

any

W

0x1010[19:16]ch4_sel_MIC

any

W

0x1010[3:0]ch8_sel_MIC

any

done_MIC

start_adr_MIC

sample_no_MIC

MSK_err_MIC

smp_MIC

1'b0

smp_MIC

1'b1

ALL channels
invalidconfigurechannel assign※A done interrupt is generated
by the START command,so please abandon this doneinterrupt on this route.

start commandW

0x1008[2]

nointr_MIC

1'b0

W

0x1008[1:0]

rtd_trg_MIC

2'b01※If you do not issue an interrupt when command processing is complete,nointr_MIC is set to 1.

1'b1

err_MIC?

※During the DMA transfer,changing both the transfer mode setting and channel assign setting
is prohibited.

Interrupt Clear

1'b0

R

0x1140[1]

err_MIC---W

0x1140[1]

err_MIC

1'b1

W0x104C[1]

MSK_err_MIC

1'b0

R

0x1008[0]

rtd_trg_MIC---

R

0x1014[19:16]

monbuf_MIC---

err_MIC

Active Interrupt
MSK_err_MIC

command fifo
is full?

full(1'b0)

rtd_trg_MIC

vacant(1'b1)

monbuf_MIC== 3?

interrupt abouttransfer completion
acceptedNo

Yes

configure start
address※The sample number setting can be skipped
if you do not want to change it.

configuresample number

start command

command fifo
is full?

vacantfull

wait
interrupt

no interrupt

interrupt

interrupt?
transfercompletioninterrupt clear
done_MIC

Yes

err_MICInterrupt Clear
err_MICW

0x1140[1]

err_MIC

1'b1

W

0x1140[0]done_MIC

1'b1

W

0x1008[2]

nointr_MIC

1'b1

W

0x1008[1:0]

rtd_trg_MIC

2'b00

transfer
continued?
Nostop command

END－1107/1293－

CXD5602 User Manual

Figure 3.15-35 Mic Signal Upload Flow (Example)－1108/1293－

CXD5602 User Manual

START

R/W

Addressbit

nameinterrupt about transfer
completion acceptedW

0x1144[2]

done_I2S0I

1'b1

configure start addressW

0x1080[31:2]

start_adr_I2S0_UP

any

configure sample numberW

0x1084[31:0]

sample_no_I2S0_UP

any

configure transfer mode
set to 24bit

W

0x108C[0]

bitwt_I2S0_UP

1'b0

W

0x1144[4]smp_I2S0

1'b1

R0x1144[4]smp_I2S0---

write value

done_I2S0I

start_adr_I2S0_UP

sample_no_I2S0_UP

bitwt_I2S0_UP

SMP clear
smp_I2S0

1'b0

SMP status?
smp_I2S0

1'b1

ALL channels
invalidW

0x1090[5:4]

ch1_sel_I2S0_UP

2'b11

W

0x1090[1:0]

ch2_sel_I2S0_UP

2'b11※The bitwt_I2S0_UP setting can be skipped , if you want to set it to 1'b0.
W

configure transfer mode
24bit/16bit
bitwt_I2S0_UP

configurechannel assign※A done interrupt is generated
by the START command,so please abandon this doneinterrupt on this route.

start command

1'b0Interrupt Clear

command fifo
is full?

[0]

bitwt_I2S0_UP

any

any

W

0x1090[5:4]

ch1_sel_I2S0_UP

W

0x1090[1:0]

ch2_sel_I2S0_UP

anyW

0x1088[2]

nointr_I2S0_UP

1'b0

W

0x1088[1:0]

rtd_trg_I2S0_UP

2'b01※If you do not issue an interrupt when command processing is complete,nointr_MIC is set to 1.

1'b1

err_i2so1?

0x108C※During the DMA transfer,changing both the transfer mode setting and channel assign setting
is prohibited.

R

0x1144[4]

err_I2S0I---

W

0x1144[4]

err_I2S0I

1'b1

R

0x1088[0]

rtd_trg_I2S0_UP---

R

0x1094[19:16]

monbuf_I2S0_UP---

err_I2S0I

full(1'b0)

rtd_trg_I2S0_UP

vacant(1'b1)

monbuf_I2S0_UP== 3?

interrupt abouttransfer completion
acceptedNo

Yes

configure start
address※The sample number setting can be skipped
if you do not want to change it.

configuresample number

start command

command fifo
is full?

vacantfull

wait
interrupt

no interrupt

interrupt

interrupt?
transfercompletioninterrupt clear
done_I2S0I

Yes

err_I2S0I

Interrupt Clear
err_I2S0I

W

0x1144[3]

err_I2S0I

1'b1

W

0x1144[2]

done_I2S0I

1'b1

W

0x1088[2]

nointr_I2S0_UP

1'b1

W

0x1088[1:0]

rtd_trg_I2S0_UP

2'b00transfer
continued?
Nostop command

END

Figure 3.15-36 I2S0 Signal Upload Flow (Example)－1109/1293－

CXD5602 User ManualOnce the STOP command is processed, the completion interrupt is masked. After the START command iswritten, the mask is released. Although the above Figures show examples of writing to the SRAMs of the MIC
signal (Figure 3.15-35) and I2S0 signal (Figure 3.15-36), the flow for writing to the I2S1 signal is the same.

3.15.10.2.2

SRAM Readout

The following shows an example of the control routine for SRAM readout. Once the STOP command isprocessed, the completion interrupt is masked. After the START command is written, the mask is released.
Although the following Figure shows an example of reading the SRAM of the I2S0 signal, the flow for readingout the I2S1 signal is the same.

－1110/1293－

CXD5602 User Manual

START

configure transfer mode
24bit/16bit
bitwt_I2S0_DOWN

R/W

Addressbit

W

0x10CC[0]

namewrite value

bitwt_I2S0_DOWN

any※During the DMA transfer,changing both the transfer mode setting and channel assign setting
is prohibited.

interrupt about transfer
completion acceptedW

0x1144[0]

done_I2S0O

1'b1

start_adr_I2S0_DOWN

W

0x10C0[31:2]

start_adr_I2S0_DOWN

anyconfigure sample numberW

0x10C4[31:0]

sample_no_I2S0_DOWN

any

SMP clearW

0x1144[4]smp_I2S0

1'b1

R0x1144[4]smp_I2S0---

done_I2S0O

configure start address

sample_no_I2S0_DOWN

smp_I2S0

1'b0

SMP status?
smp_I2S0

1'b1

ALL channels
invalidW

0x10D0[5:4]

sd1_l_sel

2'b11

W

0x10D0[1:0]

sd1_r_sel

2'b11※During the DMA transfer,changing both the transfer mode setting and channel assign setting
is prohibited.

configurechannel assign※A done interrupt is generated
by the START command,so please abandon this doneinterrupt on this route.

start command

1'b0Interrupt Clear

command fifo
is full?

0x10D0[5:4]

sd1_l_sel

any

0x10D0[1:0]

sd1_l_sel

anyW

0x10C8[2]

nointr_I2S0_DOWN

1'b0

W

0x10C8[1:0]

rtd_trg_I2S0_DOWN

2'b01※If you do not issue an interrupt when command processing is complete,nointr_MIC is set to 1.

1'b1

err_I2S0O?

W
W

monbuf_I2S0_DO
WN
No
== 3?

vacant(1'b1)

interrupt abouttransfer completion
accepted

0x1144[1]

err_I2S0O---

W

0x1144[1]

err_I2S0O

1'b1

R

0x10C8[0]

rtd_trg_I2S0_DOWN---

R

0x10D4[19:16]

monbuf_I2S0_DOWN---

err_I2S0O

full(1'b0)

rtd_trg_I2S0_DOWN

R

Yes

configure start
address※The sample number setting can be skipped
if you do not want to change it.

configuresample number

start command

command fifo
is full?

vacantfull

wait
interrupt

no interrupt

interrupt

interrupt?
transfercompletioninterrupt clear
done_I2S0O

Yes

err_I2S0O

Interrupt Clear
err_I2S0O

W

0x1144[1]

err_I2S0O

1'b1

W

0x1144[0]

done_I2S0O

1'b1

transfer
continued?
Nostop commandW

0x10C8[2]

nointr_I2S0_DOWN

1'b1

W

0x10C8[1:0]

rtd_trg_I2S0_DOWN

2'b00

END

－1111/1293－

CXD5602 User Manual

3.16 SDIO

SD Host Controller InterfaceSD Memory Card Protocol version 3.0 compatible



8K-Byte(32bit x 512word) x2 FIFOs for Tx/Rx

Communication speeds
High Performance mode: up to 39.000MHz

Low Power mode: up to 24.552MHz

3.17 eMMC


eMMC Interface
eMMC 4.41 Protocol compatible

only SDR mode

1K-Byte(32bit x 256word) x2 FIFOs for Tx/Rx

Communication speeds
High Performance mode: up to 39.000MHz

Low Power mode: up to 24.552MHz

3.18 USB

USB 2.0 DeviceComplies with USB2.0 Specification High-speed up to 480 Mbps


Not supported at Low Power modeOn-chip USB PHY transceiverSupports MSC, MTP, CDC, PTP, ACM and HID class

Multi-functionInterface: #0/#1/#2－1112/1293－

CXD5602 User Manual

3.18.1

Overview

The USB block is the Synopsys’s USB Device Controller implemented with the HW configuration for CXD5602.
This description of the specifications is based on the reference: Synopsys d20ahb_databook(USB1.1 Release 2.11a,
USB2.0 AHB-VCI 2.45a/VCI 1.93a June 2009).

3.18.1.1

Features❖ Complies with USB 2.0 and USB 1.1 protocols
No support for Low Power mode (LPM)❖ Supports high-speed (480 MHz), full-speed (12 MHz) and low-speed (1.5 MHz) operations for UDC20, andsupports full-speed and low-speed operations for UDCVCI❖ Supports up to 16 IN and 16 OUT physical endpoints, which can be tied to different interfaces and configurations toachieve logical endpoints❖ Permits user control through memory-mapped control and status registers (CSRs)❖ Supports both DMA option and Slave-Only modes❖ Supports true scatter-gather DMA implementation❖ Supports descriptor-based memory structures in application memory when in DMA mode
❖ Supports adaptive buffering for efficient IN endpoint buffer management❖ Supports power management❖ In full and high speed operation, UDC-AHB subsystem is compatible with UTMI+ level 3 PHY❖ Supports the following UTMI data bus interfaces:✦ Unidirectional 8-bit interface

3.18.1.2

Hardware Overview

Figure USB-37 shows the UDC-AHB Subsystem architecture, both as a master on the AHB (in DMA mode), and as aslave on the AHB (in Slave-Only mode). In both Slave-Only and DMA modes, the subsystem acts as a Slave for CSR
access. In Slave-Only mode, the internal FIFOs are memory-mapped. Use DMA mode with applications that require
software controllability and throughput. Use Slave-Only mode with applications that do not depend on software and canbe functionally implemented in hardware. The architecture implements adaptive buffer sizes for each USB- IN endpoint.
This enables you to program the endpoint buffers sizes per your requirements. This is typically done when the USB hostchanges the interface or configuration settings of the device, and the various endpoints attached to that interface orconfiguration have different buffering requirements. In DMA mode, the subsystem acts as master on the AHB to read
and write the memory structures in the system memory. In Slave-Only mode, the subsystem responds to AHB
transactions from the application (the AHB master). Both of these modes are explained in detail in the following
sections. These modes are user-selectable when configuring the subsystem using the RapidScript configuration tools
provided with the subsystem. Additionally, RapidScript provides an option to choose FIFO depths. In the architecture
shown below, OUT transactions have a single FIFO that can hold all the OUT packets from the USB host. For IN
transactions, each endpoint has a FIFO associated with it. All these IN endpoint FIFOs are mapped to external RAM. A
FIFO for each IN endpoint is provided to avoid a deadlock situation in which the UDC offers a NAK handshake reply－1113/1293－

CXD5602 User Manual

to a USB host’s IN transaction, and the USB host (instead of retrying the same transaction) responds with a new IN
transaction to a different endpoint. Separate FIFOs for each of the IN endpoints also improves the throughput on theapplication bus (AHB in this case). USB 1.1/2.0 Device Subsystem-AHB/VCI handles all the standard device requests
except the following:❖ Get_Descriptor❖ Set_Descriptor❖ Synch_Frame, as well as class- and vendor-specific requests
UDC-AHB passes these requests to the application. Refer to Chapter 9 of the USB 2.0 specification for more
information on standard device requests.
UDC-AHB does not support interleaving control transfers with multiple control
endpoints

Note

3.18.1.3

Block Diagram

Figure USB-37 shows the UDC-AHB Subsystem architecture. The bold lines represent the data path, and the light lines
represent the control path.

Figure USB-37 UDC-AHB Subsystem Architecture－1114/1293－

CXD5602 User Manual

3.18.1.3.1

Block Descriptions

This section provides an overview of the blocks in Figure USB-37. Additional descriptions appear in 3.18.7
UDC
The UDC is Synopsys’s USB Device Controller (UDC20 or UDCVCI). For more information on these devices, refer totheir respective databooks. The UDC20 core connects to the USB cable either through the UTMI+ interface. The
UDCVCI core connects to the USB cable through the transceiver serial interface.
UTLIThe USB Transaction Layer Interface (UTLI) interfaces with the UDC and the FIFOs. For OUT transactions, the UTLI
writes data to the Receive FIFO; for IN transactions, the UTLI reads the addressed endpoint FIFO and provides the data
to the UDC. When the subsystem receives an OUT transaction, the UTLI checks if there is sufficient room in theaddressed endpoint’s FIFO. If there is not, the subsystem issues a NAK handshake. In high-speed operation, a NYET
handshake is generated if the Receive FIFO has space to take only one more packet for control and bulk endpoints. TheUTLI writes the received data into the Receive FIFO and sends a confirmation to the FIFO once the UDC performs astatus write with a good status. In Snoop mode, the packet is confirmed into the FIFO as soon as the UDC performs thestatus write. The UTLI also sends an interrupt to the application when there is an IN token and data is not available in
the appropriate endpoint FIFO.
Interrupt Manager
The Interrupt Manager controls interrupt generation to the application. This block also maintains the Interrupt registerand the Interrupt Mask registers, which are mapped into the CSR space.
Start-of-Frame (SOF) Tracker
The Start-of-Frame (SOF) Tracker checks for any missing SOF packets. If there is a missing SOF packet, this block
generates an event that is used by the ISO FIFOs to clear residual data from the previous frame.
Receive FIFO Controller
The RxFIFO offers more functionality than regular FIFOs. The RxFIFO provides the UTLI with enough space for the
UTLI to accept the packet or to send a NYET (UDC20 only) or NAK handshake. The RxFIFO also requires aconfirming signal when a packet is written to or read from it. This confirmation is used by the RxFIFO to propagate
pointer information from one domain to another to calculate different FIFO status signals. Any attempt to write to the
RxFIFO via the AHB interface results in an AHB error. A more detailed description of multiple RxFIFO controller
operations is provided in 3.18.13, “Multiple RxFIFO Controllers.”
Endpoint FIFO Controller (Transmit FIFO Controller)
This block manages the endpoint FIFO status of a specific IN endpoint; each IN endpoint has one of these blocks. These
blocks need the base address and buffer size for each endpoint to implement adaptive buffer management. Any attempt
to read from the TxFIFO via the AHB interface results in an AHB Error.

－1115/1293－

CXD5602 User ManualControl and Status Registers (CSRs)
The control and status registers provide a channel for exchanging control information with the application, and provide
a means for the application to control the subsystem. UDC CSRs are also mapped into this CSR address space.
AHB Slave-Only Interface
This module is active when the UDC-AHB Subsystem is configured as a slave on the AHB. All endpoint FIFOs are
mapped to the application memory, and the application writes the data directly to the endpoint FIFOs. Similarly, the
RxFIFO is also mapped to the system memory, and the application reads directly from the RxFIFO. A more detailed
description of the AHB Slave-Only interface is provided in 3.18.7, “Slave-Only Operation” and 3.18.9, “Application
Bus Protocol (Slave-Only Mode).”External RAM
The RAM is the buffer storage for endpoint FIFOs. Since the subsystem can use external RAM, the user has the choiceof using either external or embedded RAM. The user may also configure two different dual-port RAM access paths, one
for IN endpoints and one for OUT endpoints. This is shown in Figure USB-37 as:❖ External IN RAM (for all IN endpoints, 36 bits wide)❖ External OUT RAM (for all OUT endpoints, 32 bits wide)
Both RAM endpoints should have a dual-port interface (one Read and one Write address bus). The user can also
program the buffer storage used for each IN endpoint (adaptive buffering).
DMA (AHB Master Interface)This module enables the subsystem to become Master of the AHB. In this mode, the DMA block receives the required
data pointers from the values programmed in the CSRs and can transfer data to and from system memory. The DMA
supports a linked-list data structure in the system memory. A more detailed description of the DMA block is provided in
3.18.8, “DMA Operation.”
CSR Slave AccessThis block is active in DMA mode only and responds to any CSR access from the application (AHB master).

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3.18.1.4

Clock Boundary

The subsystem has a synchronization module ua_clksync that handles the synchronization of signals between two
different clock domains (phy_clk_i in UDC20, or dev_clk_i in UDC11 and HCLK clock domains) between the USB
Device Controller and the subsystem.

Figure USB-38 Clock Boundary－1117/1293－

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3.18.2

Configuration Parameters

This chapter describes all configuration parameters for the USB Device (Synopsys DWC_d20ahb) core.
However, these configuration parameters have already set for CXD5602.

3.18.2.1

Basic Configuration Parameters

Table USB-41 describes the basic configuration parameters.
The configuration parameter set in CXD5602 is shown in “Value” of the table. A value means 1: enable, 0:disable.
Table USB-41 Basic Configuration Parameters
OptionDefinition

Value

Does the UDC20 use ULPI

By default, the UDC20-AHB Subsystem is configured to support the0(UTMI+ Low Pin Interface)

UTMI. If this box is checked, either the ULPI (UTMI+ Low Pin

Would you prefer the DDR (y) or

By default, the UDC20-AHB Subsystem supports the ULPI’s 8-bit

the SDR (n) support

Single Data Rate (SDR) mode or the UTMI (in conjunction with theInterface) or UTMI (in conjunction with the ULPI) is supported.

0

ULPI). If this box is checked, the UDC20-AHB supports both the
ULPI’s 8-bit SDR mode and 4-bit Dual Data Rate (DDR) mode, andonly the ULPI is supported.

Should the UDC20 support UTMI in

By default, the UDC20-AHB Subsystem supports only the ULPI

conjunction with ULPI interface(SDR) interface. If this box is checked, the UDC20-AHB supports0both the ULPI (SDR) and UTMI (bidirectional data bus). When the
UDC20-AHB is configured to support both interfaces, during startup,
you can use the sideband signal, app_ulpi_sel, to select the ULPI or
UTMI.
Number of Logical Endpoints inThis parameter sets the number of logical endpoints (from Endpoint

Addition to Endpoint –0

1 through Endpoint 15) to be supported in addition to logical6

endpoint 0.
Number of Configurations in

The UDC20-AHB Subsystem supports 15 configurations. This

Addition to Configuration –0

parameter sets the number of configuration to be supported in1

addition to Configuration 0.
Total number of Physical Endpoints

This parameter sets the number of physical endpoints (UDC20
Endpoint registers) to be supported. The UDC20-AHB can support
16 logical endpoints (from 0 through 15). Each endpoint can bebidirectional (except Endpoint 0, where data transfers take place inboth directions and the endpoint is still treated as only one endpoint).
The UDC20-AHB extends the concept of the logical endpoints to thephysical endpoints. The number of physical endpoints in a device isbased on the information given to each endpoint descriptor used in
all configurations/interfaces/alternate setting values.

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3.18.2.2

UDC-AHB Subsystem Parameters

Table USB-42 describes the UDC-AHB subsystem configuration parameters.
Table USB-42 UDC-AHB Subsystem Configuration Parameters
OptionDefinition

Value

Support Multiple Receive FIFO

By default, only a single receive FIFO controller is implemented for all

1

OUT endpoints If this box is checked, multiple receive FIFO controllers
are implemented for OUT endpoints.
Receive (out) data FIFO depth

There are no endpoint-specific FIFOs in the OUT direction. All OUT

256

data goes through a receive FIFO. This parameter sets the depth(32-bit entry) of the RxFIFO. You must set the RxFIFO depth to atleast 128 words (512 bytes) available for bulk transactions and 16
words for control transactions. The minimum depth is 4 words (or 432-bit entries).
Note: You need to set the RxFIFO depth to at least 256 words (1024bytes) to minimize NYETs from the core for bulk OUT transactions.
Receive (out) address FIFO depthThis parameter sets the depth (32-bit entry) of the RxFIFO’s address

4

FIFO. An address FIFO is required for the RxFIFO to support
reception of multiple packets to different OUT endpoints. The
minimum address FIFO depth is 4. This parameter must be set to a
power of 2 (4, 8, 16, 32, and so forth). If multiple receive FIFO
controllers are supported, the maximum address FIFO depth is 4 andthe minimum address FIFO depth is 1. The parameter must be set to a
power of 2. All OUT endpoints must have the same Address FIFO
depth.
AHB Address Bits Required toThis parameter sets the number of bits (12 to 32) the UDC-AHB

Decode Slave Address

Subsystem uses to decode the address. All other valid address bits

16

must be used by the decoder to generate the proper HSEL, dependingon the address map. (In the CRV environment, there must be 31 or
fewer AHB address bits because the CRV environment uses one of
the bits for the internal RAM Manager. However, the UDC-AHB
Subsystem still supports up to 32 bits.)
Tx RAM Pointer Width

The maximum width for the Tx RAM pointer is based on the number ofTx Buffer Pointer Width

AHB address bits entered. The maximum Tx buffer pointer width is10

based on the Tx RAM pointer width entered.
Rx RAM Pointer Width

The maximum Rx RAM pointer width is also based on the number ofRx Buffer Pointer Width

AHB address bits entered. The maximum Rx buffer pointer width is10

also based on the Rx RAM pointer width entered.
UDC-AHB Subsystem Mode

Selecting “Slave-Only” generates source files for Slave-Only mode.

1

Selecting “DMA” generates source files for both DMA and Slave-Onlymodes.
UDC-AHB Subsystem Speed

Selecting “FS” defaults the speed field in the CSR (Device
Configuration register [1:0]) to Full Speed. If “HS” is selected, thespeed field is set to High.

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Table USB-43 UDC-AHB Subsystem Configuration Parameters (Continued)
OptionDefinition

Value

UDC-AHB Subsystem Default UTMI

Selecting “16-bit” defaults the UTMI PHY interface field in the CSR

1

PHY Interface(Device Configuration register [5]) to a 16-bit interface. If “8-bit” isselected, the UTMI PHY interface field is set to an 8-bit interface.

Support Test Mode

If this box is checked, the UDC20-AHB Subsystem is configured to0

support Test mode. In Test mode, the application can read from the
TxFIFO or write to the RxFIFO using the AHB. Test mode issupported only in Slave-Only mode of operation. By default, Test
mode is not supported.
Introduce Initial Wait States on AHB

This box should be checked if the application uses the AHB slave

Data Transfersinterface for accessing FIFOs, the subsystem must support more

0than 8 logical endpoints, and the AHB clock is 133 MHz.
Is Bi-direction UTMI Supported

If this box is checked, the UDC20-AHB Subsystem is configured to0

support the UTMI with a bidirectional data bus. Otherwise, the UTMI
is configured to support a unidirectional data bus.
Default UTMI PHY Direction

Selecting “bidirectional” defaults the UTMI PHY direction field in the1

CSR (Device Configuration register [6]) to a bidirectional interface. If“unidirectional” is selected, the UTMI PHY direction field is set to
unidirectional interface.
Mask Interrupts at power on reset

By default, all device and endpoint interrupts are not masked at

1

power-on reset. If this box is checked, these interrupts are masked
at power-on reset.
Do you want to enable Send Null

If this box is checked, the UDC20-AHB Subsystem is configured toenhancement?

support sending a NULL packet when no data is available in the

1

TxFIFO for an IN endpoint. Otherwise, sending a NULL packet is notsupported. (Refer to SEND NULL bit 10 of the Endpoint Control
register in Table USB-68 for more information.
Do you want to enable Close

If this box is checked, the UDC20-AHB Subsystem is configured to

Descriptor enhancement?

support closing a descriptor channel for an OUT endpoint.

1

Otherwise, closing a descriptor channel for an OUT endpoint is notsupported. (Refer to CLOSE DESC bit 11 of the Endpoint Control
register in Table USB-901 for more information.
Do you want an output port toEnabling this option creates an output port UDC_CSR_BUSY.

indicate internal register access

Assertion of this port indicates a RETRY response from the AHB

processing?

Slave for internal register access. The port is asserted as long as theinternal register access processing is completed to get an OKAY
response upon AHB Read. Disabling this option prevents creation of
the output port UDC_CSR_BUSY.

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Table USB-44 UDC-AHB Subsystem Configuration Parameters (Continued)
OptionDefinition

Value

Do you want the enhancement toEnabling this option allows the CNAK bit to be set, that is clearing

1

clear the NAK bit when the RxFIFO

NAK, even under the following conditions:is not empty?

• Single RxFIFO implementation–even when the RxFIFO is not
empty.
• Multiple RxFIFO implementation–even when the RxFIFO
corresponding to the same logical endpoint is not empty. Disabling
this option limits clearing of the NAK bit to the following conditions:• Single RxFIFO implementation—only when the RxFIFO is empty.
• Multiple RxFIFO implementation—only when the RxFIFO
corresponding to the same logical endpoint is empty. Enabling thisoption requires the new sideband strap signal
ss_clear_nak_nempty_en_i to be tied HIGH.

Do you want the enhancement toThis enhancement adds logic to ignore NAK bit set on the ISO OUT

ignore the NAK bit for ISO OUT

endpoint. If this enhancement is enabled in the RTL configuration

endpoints?

with the NAK for Isochronous OUT endpoint set, then the data out

1from the host can still be accepted, provided there is space in the
FIFO. Disabling this enhancement causes the NAK set on
Isochronous OUT endpoint to reject the Isochronous OUT data
packet. Enabling this option requires the new sideband strap signal
ss_dis_iso_out_nak_en_i to be tied HIGH.
Do you want the enhancement toEnabling this option allows the user to set the IN and OUT STALL bit

set the IN and OUT STALL bit (S)(S) when the RxFIFO is not empty (for single RxFIFO

when the RxFIFO is not empty?

1

implementation) or when the RxFIFO corresponding to the same
logical endpoint is not empty (Multiple RxFIFO implementation).
Disabling the option allows the user to set the IN and OUT STALL bit(S) only when the RxFIFO is empty (for single RxFIFO
implementation) or when the RxFIFO corresponding to the same
logical endpoint is empty (Multiple RxFIFO implementation).
Enabling this option requires the new sideband strap signal
ss_set_stall_nempty_en_i to be tied HIGH.

Do you want the enhancement toEnabling this option sets the UTMI OpMode to 2'b01(non-driving)set SD bit to 1 & UTMI OpMode to

and the Device Control Register[SD] bit to 1'b1 during

Non-driving during power-on-reset?

power-on-reset. After Power-on-reset, the software must clear the
SD bit to make the core come out of disconnect state. Enabling thisoption requires the new core I/O strap signal ss_set_opmode_por_i
to be tied HIGH.

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Table USB-45 UDC-AHB Subsystem Configuration Parameters (Continued)
OptionDefinition

Value

Do you want to enable theEnabling this option allows the ClearFeature(Halt) and1

ClearFeature and SetFeature

SetFeature(HALT) commands to be flow-controlled by theenhancement?

application. The application can now process the commands andtake any action necessary in the application logic before completingthe status phase of the commands. The core NAKs the Status Phase
until the application is done with the processing. Disabling this option
allows the core to respond to these commands without applicationintervention. The core operates the same as before thisenhancement. Enabling this option requires the core I/O strap signal
ss_set_clr_stall_ena_i to be tied HIGH.

Do you want to enable the Transmit

Enabling this option allows the application to detect the Transmit

FIFO empty interrupt enhancement?

FIFO empty condition. Once the Transmit FIFO goes from1

non-empty to empty condition, bit 24 [TXEMPTY] of Endpoint Status
Register is set. Additionally, the Endpoint interrupt bit is set for thecorresponding endpoint in the Endpoint Interrupt Register, and aninterrupt is generated. The application must clear the TXEMPTY bit
after servicing the interrupt. If this option is not enabled, the core
operates with no interrupts on a TX FIFO empty condition.
Do you want the enhancement toThis option allows user to choose whether the SNAK bit can be set

set SNAK bit even if the Tx FIFO iswhen the TxFIFO is non-empty. Enabling this option also creates the

non-empty?

new sideband strap signal ss_txfifo_snak_enh_en_i at the top-level1

that can be tied HIGH or LOW.
• Select: Set SNAK even if the Tx FIFO is non-empty.
• Deselect: Cannot set SNAK even when the Tx FIFO is non-empty.
Do you want to support

Enabling this feature will make all of the flip-flops in the design to be

Asynchronous Power-on-Reset?

asynchronously reset during power-on.

1• Select: Asynchronous reset on all flip-flops• Deselect: Synchronous reset on all flip-flops

Interfaces
Max Interfaces in Configuration 1:

This parameter sets the number of interfaces to be supported per

Max Interfaces in Configuration 15

configuration. The UDC20-AHB Subsystem can support a maximumof 15 interfaces per configuration. The UDC20-AHB Subsystem
issues a STALL handshake for command interfaces not supported in
Configuration 1. For example, if the device supports two interfaces,
the UDC20-AHB Subsystem responds to commands for interfaces 0
and 1, and issues a stall handshake for all other interfaces.
*1: Each setting value is as below
configuration1: 3, configuration2: 3, configuration3: 3,
configuration4: 5, configuration5: 5, configuration5: 5,
configuration7: 1, configuration8: 1, configuration9: 1,
configuration10: 1, configuration11: 1, configuration12: 1,
configuration13: 1, configuration14: 1, configuration15: 1－1122/1293－*1

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Table USB-46 UDC-AHB Subsystem Configuration Parameters (Continued)
OptionDefinition

Value

Alternate Setting 1
Max Alternate Setting in Interfaces 0

Max Alternate Setting in Interfaces 0 Configuration 1: Max Alternate

1

Configuration 1: Max Alternate

Setting in Interfaces 14 Configuration 1(everySetting in Interfaces 14

case)

Configuration 1

Endpoint Types
Endpoint Type for Logical Endpoint

This parameter sets the endpoint types for each logical endpoint

1:

supported. A bidirectional endpoint is a logical endpoint that can be

Endpoint Type for Logical Endpoint

used for both IN and OUT directions of the same logical endpoint

15

number. Two data toggle bits, two endpoint stalled bits, one TxFIFO*2controller, and one RxFIFO controller (for multiple RxFIFO
implementations) are created. An IN type endpoint is a logical
endpoint that can only be used for an IN direction. One data toggle
bit, one endpoint stalled bit, and one TxFIFO controller are created.
An OUT type endpoint is a logical endpoint that can only be used for
an OUT direction. One data toggle bit, one endpoint stalled bit, and
one RxFIFO controller (for multiple RxFIFO implementation) arecreated. A Control type endpoint is a logical endpoint that can beused for both IN and OUT directions of the same logical endpoint
number. One data toggle bit, one endpoint stalled bit, one TxFIFO
controller, and one RxFIFO controller (for multiple RxFIFO
implementations) are created.
*2: Each setting value is as below
Value: Control (1), IN (2), OUT (4), Bidirectional (3)EP1: 2, EP2: 4, EP3: 2, EP4: 2, EP5: 4,
EP6: 2, EP7: 3, EP8: 3, EP9: 3, EP10: 3,
EP11: 3, EP12: 3, EP13: 3, EP14: 3, EP15: 3

Low Power Management (LPM)
Do you want to enable the LPM

This parameter enables Link Power Management.

Support enhancement?

• If LPM support is enabled, then `define UDC20_LPM_EN controls
LPM support logic.
• If LPM support is enabled, then a CSR bit controls LPM support.
This ensures that an LPM-capable core has backward-compatibility
to work in a non-LPM environment.

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3.18.33.18.3.1

Theory of Operation
Overview

The UDC-AHB Subsystem supports two modes of operation. The first is a DMA-based implementation, in which thesubsystem can master AHB for data transfers. The second is a Slave-Only implementation, in which the subsystem isslaved to the application and the application bus master(s) reads data from, or writes data to, the memory-mappedsubsystem FIFOs. In both DMA and Slave-Only modes, all data transfers are interrupt-driven. In the UDC-AHB
Subsystem, there are two hosts: the USB host, which initiates USB traffic, and the application, which responds to USB
host commands from the device side. The UDC-AHB Subsystem can only be used in device-type applications. USB
host functionality is beyond the scope of this document.

3.18.4DMA Mode

In DMA mode, before the start of any action, the application must initialize the buffer descriptor chains for all active
endpoints, and must program the necessary CSRs in the UDC and subsystem during the USB reset.

3.18.4.1

DMA Mode IN

If the UDC receives an IN token for a non-isochronous endpoint, it checks the Transmit (IN) Data FIFO for data
availability. If data is available, the FIFO is read and the data is provided to the UDC. If the FIFO is empty, thesubsystem sends the application an interrupt, and the UDC sends the USB host a NAK handshake. On receiving theinterrupt, the application probes the Endpoint Interrupt register to determine which endpoint has requested the interrupt.
Having determined this endpoint, the application then probes the Endpoint Status register to determine the interrupt’s
cause. Upon notification that this is an IN token for a particular endpoint, the application updates the addressed
endpoint’s system memory buffer with data. It also indicates to the DMA the data’s availability by setting the Poll
Demand bit in the subsystem’s CSRs. (Each endpoint has a dedicated Poll Demand bit.) The DMA now transfers thedata from the system memory to the endpoint buffers (FIFOs). As shown in Figure USB-37, these endpoint buffers are
RAM-based implementations with programmable sizes. When the USB host retries with another IN token, thesubsystem provides the data to the UDC from the endpoint buffers for transmission. When the transmission is complete,status is written back into the buffer descriptor’s status quadlet. The subsystem clears the Poll Demand bit once thedescriptor chain reaches the last descriptor. The application can read the Poll Demand bit to determine if the descriptor
chain is serviced or not. The sequence of these events for a non-isochronous (bulk, interrupt, or control) IN endpoint isshown in Figure USB-39.

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Figure USB-39 IN Transaction Flow in DMA Mode

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CXD5602 User ManualIN transfers with isochronous endpoints are handled similarly. The transfer of IN data from the application memory to
the Endpoint FIFO is not initiated by request tokens from the USB Host; rather, the application sets the Poll Demand bit
when it has data available. The subsystem tags data for isochronous endpoints with a frame number. The UDC, which
maintains the Frame Counter, sends the isochronous data in the intended frame. The SOF (Start of Frame) Tracker
module tracks the incoming SOFs and their frame numbers. If the incoming frame number matches the frame number inthe buffer, the UDC transfers the frame from the appropriate data buffer. If the frame number in the SOF is greater than
the frame number in the Frame Counter, the DMA module skips the buffers to align to the correct frame number. If theframe number in the SOF is less than the subsystem’s frame number, the DMA waits for a few frames to align to thecorrect frame number. Hooks are provided for the application to flush the subsystem’s FIFOs in case of missing SOFs.

3.18.4.2

DMA Mode OUT

In the OUT direction, once the subsystem receives OUT or SETUP data from the USB host (that is, when a packet ofdata is completed or, if thresholding is enabled, a threshold is reached), it transfers the data to the buffers allocated tothe endpoint in application memory. Once the data is transferred, the subsystem updates the status of the received data
to the buffer’s status quadlet. SETUP data is transferred to a 16-byte SETUP buffer. The pointer for this buffer isindicated in the SETUP Buffer Pointer register. OUT data is transferred to the buffers indicated by the descriptor. The
pointer for these descriptors is programmed in the CSRs. Note that the SETUP data directly addresses the buffers, whileregular OUT data addresses the OUT data buffers indirectly. The transaction flow for all OUT endpoints is similar, theonly difference being that isochronous (ISO-OUT) data is tagged with the frame number in which the packet is received.
Refer to 3.18.7.5, “Transmit FIFO Controller” for more information on the confirmation mechanism. The transaction
flow of OUT data from the USB host to application memory is shown in Figure USB-40.

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Figure USB-40 OUT Transaction Flow in DMA Mode (Without Thresholding)－1127/1293－

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3.18.5

Slave-Only Mode

In Slave-Only implementation, the subsystem operates as a slave and the application bus master(s) reads data from orwrites data to the memory-mapped subsystem FIFOs. All data transfers are interrupt-driven, except ISO-IN andinterrupt-IN transfers, which are periodic. The USB host initiates USB traffic and the application responds to all theUSB host’s commands. In this mode, the UDC-AHB Subsystem can only be used in device-type applications, andbefore any operation, the application must completely program the necessary CSRs in the subsystem.

3.18.5.1

Slave-Only Mode IN

If the subsystem receives an IN token for a non-isochronous endpoint, it checks the Transmit (IN) Data FIFO for data
availability. If data is available, the UDC reads the data from the FIFO. If the FIFO does not contain data, the UDC
sends the application an interrupt, and the USB host retries the IN token. Upon receiving the interrupt, the application
probes the Endpoint Interrupt register to determine which endpoint requested the interrupt, and then probes the
Endpoint Status register to determine why the interrupt was requested. Once the application determines that an IN token
for the endpoint requested the interrupt, it writes the packet directly to the address where the TxFIFO is mapped. With
the packet data completely written to the FIFO, the application performs a single write to a predefined address (Offset
12’h01C + [endpoint number x 12’h020]) that indicates to the subsystem that the packet transfer is done. This write
confirms the packet in the endpoint Transmit FIFO. When the USB host retries the IN token, the subsystem provides the
Endpoint FIFO data to the UDC for transmission. The application receives no status update regarding the packet: thesubsystem must transmit this data. The application may flush the packet from the Transmit FIFO by setting the F bit in
the Endpoint Control register. The sequence of these events for a non-isochronous (interrupt, bulk, or control) endpointis shown in Figure USB-41. Isochronous-IN endpoints are handled similarly. The transfer of IN data from theapplication memory to the Endpoint FIFO is not initiated by USB host request tokens; rather, the application fills theTransmit FIFOs when it has available data. Isochronous endpoint data must be filled in the FIFO only if it is set for thecurrent frame, which the application can determine by reading the current active frame number from the CSR.

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Figure USB-41 IN Transaction Flow in Slave-Only Mode

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3.18.5.2

Slave-Only Mode OUT

When the subsystem receives OUT data from the USB host, it transfers the data to the Receive FIFO within thesubsystem, if it has space available for the packet. If no space is available, the packet is retried. SETUP OUT packets
are stored in a temporary subsystem register before being loaded to the Receive FIFO. Once the packet is transferred to
the Receive FIFO, the subsystem sends the application an interrupt for the received packet. The application reads theaddressed endpoint’s Interrupt and Status registers and determines the number of bytes received in the packet. The
application FIFO then reads the number of bytes received from the Receive FIFO. Note that the application reads fromthe address to which the Receive FIFO is mapped. The transaction flow of OUT data from the USB host to theapplication is shown in Figure USB-42.
Figure USB-42 OUT Transaction Flow in Slave-Only Mode－1130/1293－

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3.18.6
3.18.6.1

Control and Status Registers
Overview

The subsystem’s Control and Status Registers (CSRs) provide a high degree of control, making the subsystem bothconfigurable and scalable. These CSRs are divided into two basic categories: global CSRs, which are specific to theUSB device, and endpoint CSRs, which are specific to a particular endpoint. Each endpoint has a set of these
endpoint-specific CSRs. Interrupt bits in the interrupt registers are cleared on a write of 1’b1 to that bit. In the register
tables below, the following conventions are followed.
Register: The number of the register bit(s) in question.
Bit ID: The name of the bit.
Description: A brief description of the bit’s functionality.
Reset Value: The value that is required to reset the subject bit(s).
Read/Write: Describes the subject bit’s ability to be read from or written to.
The abbreviations used in this column are:
❖ RO Read-Only❖ RW Read/Write❖ R/WC Read/Write Clear
Note

R/WC behaves as RW; however, a write of 1 clears (sets to 0) the corresponding bit.

DMA/Slave Mode: “D” indicates that the bit’s functionality is supported in DMA mode, and “S” indicates thatthe bit’s functionality is supported in Slave mode.

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3.18.6.2

Global Command and Status Registers

3.18.6.2.1

Device Configuration Register

This register configures the device. It is only set during initial configuration or when there is a change in theconfiguration.
Table USB-47 Device Configuration Register
DMA/
Bit
31:22

Bit IDR

Description
Reserved

Reset
Value
--

Read/
Write
--

Slave
Mode
--

21

LPM_EN

Link Power Mode Enable

1’b0

RW

DS

The application sets or resets this bit to control
whether the core supports LPM features. This
allows optional backward compatibility forlegacy non-LPM environments while using acore capable of LPM.
The options for this field are:・1’b0: LPM features not enabled.
・1’b1: LPM features are enabled.
This bit drives the ss_lpm_enable_i input
internally to the VCI core.
Configuration: This field is implemented only
when LPM Support is selected in the HW
configuration.
When this field is not implemented, this field isreserved, and reads 1’b0.

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Table USB-48 Device Configuration Register (Continued)
DMA/
Bit

Bit ID

Description

Reset
Value

Read/
Write

Slave
Mode

20

LPM_AUTO

Link Power Mode Automatic

1’b0

RW

DS

1’b0

RW

DS

19

DDR

The application sets or resets this bit todetermine how the core responds to a LPM
transaction. The actual response is determinedby the values of field LPM_RESP, bits [21:20]
of this register.
The options for this field are:
The Enable LPM support is checked/ selectedin the HW configuration.
• 1’b0: Core response to LPM transaction isdetermined by field LPM_RESP.
• 1’b1: Core always issues an ACK for the
LPM transaction.
This bit drives the ss_lpm_auto_resp_i strap
input internally to the VCI core.
Dependencies: This field is valid only when
the following are true:• LPM_EN is set (1’b1).
• The Enable LPM support is checked/
selected in the HW configuration.
Configuration: This field is implemented only
when LPM Support is selected in the HW
configuration. When this field is not valid or not
implemented, this field is reserved, and reads
1’b0.
This bit indicates whether the ULPI PHY databus interface is in DDR (double data rate) or
SDR (single data rate) mode.
Options are:• 1’b0: SDR mode.
• 1’b1: DDR mode
Note: This bit is reserved if the UDC20-AHB
Subsystem is configured to support the UTMI
PHY interface. This bit is also reserved for the
UDC11-AHB Subsystem.
Dependencies: This bit is implemented only
when ULPI support is selected in the HW
configuration.

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Table USB-49 Device Configuration Register (Continued)

Bit

Bit ID

Description

18

SET_DESC17

CSR_PRG

16

HALT STATUS

Indicates that the device supports Set
Descriptor requests.
Options are:• 1’b0: The UDC-AHB Subsystem returns a
STALL handshake to the USB host.
• 1’b1: The SETUP packet for the Set
Descriptor request passes to theapplication.
Indicates that the device supports dynamic
UDC register programming.
The application can program the UDC
registers dynamically whenever it hasreceived an interrupt for either a Set
Configuration or a Set Interface request. If
this bit is enabled, the UDC-AHB Subsystem
returns a NAK handshake during the status
IN stage of both the Set Configuration and
Set Interface requests until the application
has written 1’b1 to the CSR_DONE bit 13 of
the Device Control Register.
This bit indicates whether the UDC-AHB
Subsystem must respond with a STALL or an
ACK handshake when the USB host has
issued a Clear_Feature (ENDPOINT_HALT)
request for Endpoint 0.
Options are:• 1’b0: ACK• 1’b1: STALL－1134/1293－

Reset
Value

Read/
Write

DMA/
Slave
Mode

1’b0

RW

DS

1’b0

RW

DS

1’b0

RW

DS

CXD5602 User Manual

Table USB-50 Device Configuration Register (Continued)

Bit
15:13

Bit ID
HS_TIMEOUT
CALIB

Description
These three bits indicate the number of PHY
clocks to the UDC20-AHB Subsystem’s
timeout counter. The application uses thesebits to increase the timeout value (736 to 848
bit times in high-speed operation), which
depends on the PHY’s delay in generating aline state condition. The default timeout value
is 736 bit times.

Reset
Value
3’b000

Read/
Write
RW

DMA/
Slave
Mode
DS

3’b000

RW

DS

1’b0

RW

DS

RW

DS

For example, using 30 MHz PHY clock, thetimeout time would be 736 + 48 = 784 bittimes. The value of 48 bit times comes fromthe 3 x 30 MHz PHY clock = 3 x [(33.3 ns x
3)/2.08]. Please note the bit times in thisexample are USB bit times.
These bits are reserved for the UDC11-AHB
Subsystem.
12:10

FS_TIMEOUT
CALIB

These three bits indicate the number of PHY
clocks to the UDC20-AHB Subsystem’s
timeout counter. The application uses thesebits to increase the timeout value (16 to 18 bittimes in full-speed operation), which depends
on the PHY’s delay in generating line state
condition. The default timeout value is 16 bittimes.
These bits are reserved for the UDC11-AHB
Subsystem.

9

PHY_ERROR
DETECT

If the application sets this bit, the device
detects the phy_rxvalid or phy_rxactive input
signal to be continuously asserted for 2 ms,
indicating PHY error.
This bit is reserved for the UDC11-AHB
Subsystem.

8

STATUS_1

This bit, together with STATUS Bit 7, provides
an option for the UDC-AHB Subsystem torespond to the USB host with a STALL or
ACK handshake if the USB host has issued anon-zero-length data packet during the
STATUS-OUT stage of a CONTROL transfer.
Refer to Table USB-919 for more information.

－1135/1293－

CXD5602 User Manual

Table USB-51 Device Configuration Register (Continued)

Bit
7

Bit IDSTATUS

4SS

Description
This bit, together with STATUS Bit 8, provides anoption for the UDC-AHB Subsystem to respond to
the USB host with a STALL or ACK handshake if
the USB host has issued a non-zero-length data
packet during the STATUS-OUT stage of a
CONTROL transfer. Refer to Table USB-919 formore information.
This bit indicates if the UTMI data bus interface has
to support a unidirectional or bidirectional interface.
Options are:・1’b0: Unidirectional interface
・1’b1: Bidirectional interface
Dependencies
・This bit is reserved if the UDC20-AHB
Subsystem is configured to support the UTMI
data interface for UTMI PHY with unidirectional
data bus only.
・If both the UTMI and ULPI PHY interface
configuration options are selected in the HW
configuration, and the app_ulpi_sel input signal istied high (ULPI), application software must set
this bit to 1’b0.
PHY interface. Indicates if the UTMI PHY must
support an 8-bit or 16-bit interface.
Options are:・1’b0: 16-bit
・1’b1: 8-bit. This is the default value.
Dependencies This bit is used only for the
UDC20-AHB Subsystem.
・If both the UTMI and ULPI PHY interface
configuration options are selected in
the HW configuration, and the app_ulpi_sel input
signal is tied high (ULPI), application softwaremust set this bit to 1’b1.
・If the ULPI PHY only interface configuration
option is selected, the default value is 1'b1.
Indicates that the device supports Sync Frame.

6

DIR

3

SP

Indicates that the device is self-powered.

5

PI－1136/1293－

Reset
Value

Read/
Write
RW

DMA/
Slave
Mode
DS

Based
on
RapidScript

RW

DS

RW

DS

1’b0

RW

DS

1’b0

RW

DS

or
coreConsu
lt-ant
input

Based
on
RapidScriptor
coreConsu
lt-antinput

CXD5602 User Manual

Table USB-52 Device Configuration Register (Continued)
DMA/
Bit

Bit ID

Description

2

RWKP

1:0

SPD

Indicates that the device is remote wake upcapable.
Device speed. This is the expected speed theapplication programs to the subsystem. The
actual speed the subsystem operates depends
on the enumeration speed (ENUM SPD) of theDevice Status register.
・2’b00: HS (PHY clock = 30 or 60 MHz)・2’b01: FS (PHY clock = 30 or 60 MHz)・2’b10: LS (PHY clock = 6 MHz)・2’b11: FS (PHY clock = 48 MHz)
Note: The UDC11-AHB Subsystem uses only
bit 0; bit 1 is a “don’t care” bit (2’bx0 = LS,
2’bx1 = FS).

－1137/1293－

Reset
Value

Read/
Write

Slave
Mode

1’b0

RW

DS

2’b00

RW

DS

CXD5602 User Manual

3.18.6.2.2

Device Control Register

This register is set at runtime and controls the device after device configuration
Table USB-53 Device Control Register
Read/
Write

DMA/
Slave
Mode

Bit

Bit ID

Description

Reset
Value

31:24

THLEN

Threshold Length

8’d0

RW

D

BRLEN

Indicates the number (THLEN + 1) of 32-bit
entries in the RxFIFO before the DMA can startdata transfer.
Burst Length

8’d0

RW

D

15

R

Indicates the length, in 32-bit transfers, of asingle burst on the AHB. The subsystem sends
number of 32-bit transfers equal to (BRLEN +1).
Reserved

-

-

-

14

SRX FLUSH

Receive FIFO Flush for Single Receive FIFO

1’b0

RW

DS

1’b0

W

DS

1’b0

RW

DS

23:16

13

CSR_DONE

12

DEVNAK

If The CNAK_CLR rnhancement option isenables in the HW configuration, theapplication enables to set the NAK bit when thereceive FIFO is not empty. When theapplication wants to flush the receive FIFO, it
must first set the DEVNAK bit in the Device
Control register. If the receive DMA is inprogress, then the core will finish the current
descriptor, terminate the DMA, and flush thedata in the receive FIFO and clear this bit. The
application must clear this bit after the receive
FIFO is empty, by checking the RXFIFOEMPTY bit in the Device Status register.
Note: This field is reserved in a multiple
receive FIFO configuration.
The application uses this bit to notify the UDCAHB Subsystem that the application has
completed programming all required UDC
registers, and the Subsystem can acknowledge
the current Set Configuration or Set Interface
command.
When the application sets this bit, theSubsystem core returns a NAK handshake to
all OUT endpoints.By writing 1’b1 to this bit, theapplication does not need to write 1’b1 to the
SNAK bit 7 of each Endpoint Control register.

－1138/1293－

CXD5602 User Manual

Table USB-54 Device Control Register (Continued)

Bit
11

Bit ID
SCALE

10

SD

9

MODE

8

BREN

7

THE

Description
Scale Down
This bit reduces the timer values inside the
UDC-AHB subsystem when running gate-level
simulation only. When this bit is set to 1’b1, timer
values are scaled down to reduce simulation time.
In Scale-Down mode, the UDC20-AHB detects a
USB reset within the following PHY clock cycles:• 60-MHz PHY clock, 8-bit UTMI: 150 PHY clock
cycles• 30-MHz PHY clock, 16-bit UTMI: 75 PHY clock
cyclesReset this bit to 1’b0 for normal operation.
Soft Disconnect
The application software uses this bit to signal the
UDC20 to soft-disconnect. When set to 1‘b1, thisbit causes the device to enter the disconnectedstate.
Note: When the enhancement to set SD bit to 1 &UTMI OpMode to Non-driving during
power-on-reset is enabled in the HW configuration,and the input signal (POR)is asserted HIGH, thenthe SD default power-on value will be 1'b1
(Disconnect ON). When this enhancement isenabled, the application has to clear this bit when it
is ready (after POR) to make the core come out of
disconnected state.
Enables the application to dictate the subsystem’s
operation in either DMA mode (1’b1) or Slave-Onlymode (1’b0) operation.
Dependencies:
If Slave-only mode is configured in the HW
configuration, this bit must be 1’b0.
Burst Enable
When this bit is set, transfers on the AHB are split
into bursts.
Threshold Enable
When this bit is set, a number of quadlets
equivalent to the threshold value is transferredfrom the RxFIFO to the memory.

－1139/1293－

Reset
Value
1’b0

Read/
Write
RW

DMA/
Slave
Mode
DS

1’b0

RW

DS

1’b0

RW

D

1’b0

RW

D

1’b0

RW

D

CXD5602 User Manual

Table USB-55 Device Control Register (Continued)

Bit
6

Bit ID
BF

Description
The DMA is in Buffer Fill mode and transfers data
into contiguous locations pointed to by the buffer
address.

5

BE

System Endianness Bit

Reset
Value
1’b0

Read/
Write
RW

DMA/
Slave
Mode
D

1’b0

RW

D

1’b0

RW

D

A value of 1’b1 indicates a big endian system.
4

DU

Descriptor Update
When this bit is set, the DMA updates the descriptor
at the end of each packet processed.

3

TDE

Transmit DMA is enabled.

1’b0

RW

D

2

RDE

Receive DMA is enabled.

1’b0

RW

D

1

R

Reserved

-

-

-

0

RES

Resuming Signaling on the USB

1’b0

RW

DS

To perform a remote wakeup resume—theapplication sets this bit to 1’b1, then resets it to 1’b0
after 1 ms. The UDC-AHB Subsystem signals theUSB host to resume the USB bus.
However:
・The application must first set RWKP bit 2 in the
Device Configuration Register, indicating that thesubsystem supports the Remote Wakeupfeature).
・The host must already have issued a Set Feature
request to enable the device Remote Wakeupfeature.
To resume from sleep—the application sets thisbit to 1'b1 when the sleep signal /the suspend
signal are asserted (active low) and resets this bit
after the sleep signal /the suspend signal are
de-asserted (active high).
However:
・The application must first set RWKP bit 2 inthe Device Configuration Register, indicatingthat the Subsystem supports the Remote Wakeupfeature.
・The host must indicate Device Remote Enable in
the LPM transaction.

－1140/1293－

CXD5602 User Manual

3.18.6.2.3

Device Status Register

This register reflects status information needed to service some of the interrupts. This is a read-only register.

Table USB-56 Device Status Register
DMA/
Bit
31:18

Bit IDTS17

RMTWKP
STATE

16

PHY
ERROR

Description
Frame number of the received SOF
For high-speed operation:• [31:21]: Millisecond frame number• [20:18]: Microframe number
For full-speed operation:• [31:29]: Reserved• [28:18]: Millisecond frame number
The state of Remote wakeup feature due to
Set/Clear Feature (Remotewakeup)command from the host. A value of 1
indicates a Set Feature (Remotewakeup) has
been received. A value of 0 indicates Clear
Feature (Remotewakeup) has been received.
Any change to this bit sets an interrupt inbit#7 of Device Interrupt register, if not
masked.
Note: This bit is valid only when the strap
signal input ss_setclr_rmtwkp_ena_i is tied
HIGH. When ss_setclr_rmtwkp_ena_i is nottied HIGH, this bit reads 1'b0.
Either the phy_rxvalid or phy_rxactive input
signal is detected to be continuously asserted
for 2 ms, indicating PHY error. The UDC20AHB Subsystem goes to the Suspend state
as a result.
When the application serves the earlysuspend interrupt (ES bit 2 of the Device
Interrupt register) it also must check this bit todetermine if the early suspend interrupt was
generated due to PHY error detection.
This bit is reserved for the UDC11-AHB
Subsystem.

－1141/1293－

Reset
Value
14’h0000

Read/
Write
RO

Slave
Mode
DS

1’b0

RO

DS

1’b0

RO

DS

CXD5602 User Manual

Table USB-57 Device Status Register (Continued)

Bit
15

Bit ID
RXFIFO
EMPTY

Description
This bit indicates Receive Address FIFO
empty status.

Reset
Value
1’b1

Read/
Write
RO

DMA/
Slave
Mode
DS

2’b00

RO

DS

1’b0

RO

DS

This bit is set after the DMA transfers data tosystem memory and there are no new
packets received.
This bit is cleared after receiving a goodpacket from the USB.
• 1’b1 RXFIFO is empty.
• 1’b0 RXFIFO is not empty.
14:13

ENUM SPD

Enumerated Speed. These bits hold the
speed at which the subsystem comes up after
the speed enumeration.
• If the expected speed (SPD of the Device
Configuration register) is high speed andthe subsystem connects to a 1.1 hostcontroller, then after Speed Enumeration,these bits indicate that the subsystem isoperating in full speed mode (2’b01 for
SPD = 2b’00).
• If the SPD is high speed and thesubsystem connects to a 2.0 hostcontroller, then after Speed Enumeration,these bits indicate that the subsystem isoperating in high speed mode (2’b00 for
SPD = 2’b00).
• If the speed is low speed or full speed andthe subsystem connects to either a 1.1 or a
2.0 host controller, then after Speed
Enumeration, these bits indicate that thesubsystem is operating in low speed mode
(2’b10 for SPD = 2’b10) or full speed mode
(2’b01 for SPD = 2’b01, and 2’b11 for SPD= 2’b11).
Possible options are:• 2’b00 HS• 2’b01 FS• 2’b10 LS• 2’b11 FS
Note: These bits are used only for the
UDC20-AHB Subsystem.

12

SUSP

Suspend status. This bit is set as long as a
Suspend condition is detected on the USB.

－1142/1293－

CXD5602 User Manual

Table USB-58 Device Status Register (Continued)

Bit
11:8

Bit ID
ALT

7:4

INTF

3:0

CFG

Description
This 4-bit field represents the alternate setting
to which the above interface is switched.
This 4-bit field reflects the interface set by the
SetInterface command.
This 4-bit field reflects the configuration set by
the SetConfiguration command.

－1143/1293－

Reset
Value
4’b0000

Read/
Write
RO

DMA/
Slave
Mode
DS

4’b0000

RODS

4’b0000RODS

CXD5602 User Manual

3.18.6.2.4

Device Interrupt Register

Device interrupts are set when there are system-level events. Interrupts are used by the application to make system-level
decisions. After checking the register, the application must clear the interrupt by writing a 1’b1 to the correct bit.
Table USB-59 Device Interrupt Register

Bit
31:11
10

Bit ID
R
EARLY
SLEEP

9

SLEEP

Description
Reserved
LPM Early Sleep
This bit is set through hardware by the controller
to indicate that the core has entered the early
USB Sleep state. This bit is set as a result of core
ACK-ing the LPM transaction and waiting for
Minimum TL1token retry time (9 us). If the core isoperating in HS, then it will switch to FS
terminations when early sleep is detected. The
application can reset this bit by writing 1’b1 to thisbit.
However the LPM is not selected in this HW
Configuration. this field is reserved, and reads
1’b0.
LPM Sleep
This bit is set through hardware by the controller
to indicate that the core has entered the USB
Sleep state. This bit is set as a result of either
udc20_sleepm_o or udc20_l1suspendm_o being
asserted (low) when the core transitions to L1(SLEEP) power state after ACK-ing the LPM
transaction and waiting for Minimum TL1token
retry time and Minimum TL1residency time (51us).
The application can reset this bit by writing a 1’b1
to this bit.
Note: For the UDC20-AHB subsystem, this LPM
sleep interrupt will not be generated if the PHY
clock is suspended/stopped immediately basedon the slee or suspend signal.
However the LPM is not selected in HW
Configuration. this field is reserved, and reads
1’b0.

－1144/1293－

Reset
Value
1’b0

Read/
Write
R/WC

DMA/
Slave
Mode
DS

1’b0

R/WC

DS

CXD5602 User Manual

Table USB-60 Device Interrupt Register (Continued)

Bit
8

Bit IDLPM_TKN

Description
LPM Transaction Received

7

RMTWKPSTATE INT

6ENUM

This bit is set through hardware by the controller
to indicate an LPM transaction has beenaddressed to this device. The application canreset this bit by setting this bit. This bit is not set
when successive LPM tokens are received andthe preceding one had NYET as the response.
However the LPM is not selected in this HW
Configuration. this field is reserved, and reads
1’b0.
A Set/Clear Feature (Remote Wakeup) is
received by the core. This bit is set by the corewhenever bit 17 of the Device Status Registerchanges: HIGH to LOW or LOW to HIGH.
Speed enumeration is complete.

5

SOF

Note: This bit is used only for the UDC20-AHB
Subsystem.
An SOF token is detected on the USB.

4

US

3

UR

2

ES

A suspend state is detected on the USB for aduration of 3 milliseconds, following the 3millisecond ES interrupt activity due to an idle
state.
Note: For the UDC20-AHB subsystem, there isno Suspend interrupt to the application if the PHY
clock is suspended via the suspendm signal
A reset is detected on the USB.
Note: If the application has not served thisinterrupt, the UDC Subsystem returns a NAK
handshake for all transactions except the 8
SETUP packet bytes from the USB host.
An idle state is detected on the USB for aduration of 3 milliseconds.
This interrupt bit is used for the application
firmware to finish its job before the subsystemgenerates a true suspend (US) interrupt (another3 milliseconds after the ES interrupt).

－1145/1293－

Reset
Value
1’b0

Read/
Write
R/WC

DMA/
Slave
Mode
DS

1’b0

R/WC

DS

1’b0

R/WC

DS

1’b0

R/WC

DS

1’b0

R/WC

DS

1’b0

R/WC

DS

1’b0

R/WC

DS

CXD5602 User Manual

Table USB-61 Device Interrupt Register (Continued)
DMA/
Bit

Bit ID

Description

1

SI

The device has received a Set_Interface
command.

Reset
Value

Read/
Write

Slave
Mode

1’b0

R/WC

DS

1’b0

R/WC

DS

Note: If the application has not served thisinterrupt, the subsystem returns a NAK
handshake to all transactions except the 8 SETUP
packet bytes coming from the USB host.
0SC

The device has received a Set_Configurationcommand.
Note: If the application has not served thisinterrupt, the subsystem returns a NAK
handshake to all transactions except the 8 SETUP
packet bytes coming from the USB host.

－1146/1293－

CXD5602 User Manual

3.18.6.2.5

Device Interrupt Mask Register

The device interrupt mask can be set for system-level interrupts using this register. Programming 1’b1 in theappropriate bit position in the Interrupt Mask register masks the designated interrupt. Once masked, an interrupt signal
does not reach the application, nor does its interrupt bit get set.
Table USB-62 Device Interrupt Mask Register

Bit
31:11
10

Bit ID
R
EARLY
SLEEP

9

SLEEP

8

LPM_
TKN

Reset
Value
1’b0

Description
Reserved
This bit is set or reset through the application. The
application masks the EARLY SLEEP interrupt by
setting this field to 1.
The options for this field are:• 1’b0: LPM_TKN Interrupt masked.
• 1’b1: LPM_TKN Interrupt masked.
When masked, an interrupt signal does not reach theapplication, nor does its interrupt bit get set.
Configuration: However the LPM is not selected inthis HW Configuration. this field is reserved, and reads
1’b0.
This bit is set or reset through the application. The
1’b0application masks the SLEEP interrupt by setting thisfield to 1.
The options for this field are:• 1’b0: LPM_TKN Interrupt masked.
• 1’b1: LPM_TKN Interrupt masked.
When masked, an interrupt signal does not reach theapplication, nor does its interrupt bit get set.
Configuration: However the LPM is not selected inthis HW Configuration. this field is reserved, and reads
1’b0.
This bit is set or reset through the application. The
1’b0application masks the LPM_TKN interrupt by setting
this field to 1.
The options for this field are:• 1’b0: LPM_TKN Interrupt masked.
• 1’b1: LPM_TKN Interrupt masked.
When masked, an interrupt signal does not reach theapplication, nor does its interrupt bit get set.
Configuration: However the LPM is not selected inthis HW Configuration. this field is reserved, and reads
1’b0.

－1147/1293－

Read/
Write
RW

DMA/
Slave
Mode
DS

RW

DS

RW

DS

CXD5602 User Manual

Table USB-63 Endpoint Interrupt Register
DMA/
Bit
7:0

Bit IDMASK

3.18.6.2.6

Description
Mask equivalent device interrupt bit. (HW
Configuration determines the reset value.)

Reset
Value
1’b0
or
1’b1

Read/
Write
R/W

Slave
Mode
DS

Endpoint Interrupt Register

The Endpoint Interrupt register is used to set endpoint-level interrupts. Since all 16 endpoints can be bidirectional, each
endpoint has two interrupt bits (one for each direction). The application needs to clear the interrupt by writing a 1’b1 tothe correct bit after checking the register.
Table USB-64 Endpoint Interrupt Register
DMA/
Bit
31:16

Bit IDOUT EP

15:0

IN EP

Description
One bit per OUT endpoint, set when there is an
event on that endpoint.
One bit per IN endpoint, set when there is an eventon that endpoint.

－1148/1293－

Reset
Value
1’b0

Read/
Write
RW

Slave
Mode
DS

1’b0

RW

DS

CXD5602 User Manual

3.18.6.2.7

Endpoint Interrupt Mask Register

This register is used to mask endpoint interrupts. A write of 1’b1 to any bit in this register masks the corresponding
endpoint for any possible interrupts. Once masked, an interrupt signal does not reach the application, nor does its
interrupt bit get set.
Table USB-65 Endpoint Interrupt Mask Register
DMA/
Bit
31:16

Bit IDOUT EP
MASK

15:0

IN EP
MASK

Description
Masks interrupts to the OUT endpoint equivalent tothis value. (HW Configuration determines the reset
value.)
Masks interrupts to the IN endpoint equivalent to this

Reset
Value
1’b0
or
1’b1
1’b0

value. (HW Configuration determines the reset
value.)

or1’b1－1149/1293－

Read/
Write
RW

Slave
Mode
DS

RW

DS

CXD5602 User Manual

3.18.6.3

Endpoint-Specific Command and Status Registers

3.18.6.3.1

Endpoint Control Register

This register is used to program the endpoints as required by the application. If the endpoint is bidirectional, there are
two such endpoint registers.
Table USB-66 Endpoint Control Register

Bit

Bit ID

Description

Reset
Value

31:13
12

R
MRX

Reserved
Receive FIFO Flush for Multiple Receive FIFO

1’b0

FLUSH

The core must be configured with the
UDC20AHB_CNAK_CLR_ENH_CC
enhancement to use this bit, as this will enable
the application to set the NAK bit when thereceive FIFO is not empty. When the application
wants to flush the endpoint receive FIFO, it mustfirst set the SNAK bit in the Endpoint Control
register. If the receive DMA is in progress, thenthe core will finish the current descriptor,
terminate the DMA, and flush the data in theendpoint receive FIFO and clear this bit. The
application must clear this bit after the EP receive
FIFO is empty, by checking the MRXFIFOEMPTY bit in the Endpoint Status register.
Note: This field is reserved for single receive
FIFO configurations.

－1150/1293－

Read/
Write

DMA/
Slave
Mode

RW

DS

CXD5602 User Manual

Table USB-67 Endpoint Control Register (Continued)

Bit

Bit ID

Description

Reset
Value

Read/
Write

DMA/
Slave
Mode

11

CLOSE

Close descriptor channel for this endpoint.

1’b0

RW

D

DESC

This bit applies only to OUT endpoints and isavailable only when the Close Descriptor Channel
option is selected through coreConsultant.
The application sets this bit to close the descriptor
channel, and the UDC Subsystem clears this bit
after the channel is closed.
This bit provides the application with a mechanism
to close the descriptors in cases where the USB
host does not indicate an end-of-transfer (byissuing a short packet to the USB device). To closethe descriptor channel for a particular endpoint, theapplication sets the CLOSE DESC bit in the
Endpoint Control register. When the channel isclosed, the UDC Subsystem clears this bit andgenerates an interrupt.
This bit must be used only for bulk and interrupt
OUT endpoints. In addition, before closing thedescriptor, software must ensure that the current
descriptor reachable by the DMA is active (buffer
status is Host Ready). When closed, the descriptor
is marked with the Last bit set. When the descriptor
is closed, it is assigned one of the following
descriptor statuses:•Buffer Fill mode: Accumulated byte count isavailable in the Rx Bytes field.
•Packet-Per-Buffer With Descriptor Update mode:
Current reachable descriptor is marked with theLast descriptor, and the Rx Bytes field is set to 0.
•Packet-Per-Buffer Without Descriptor Update
mode: Current reachable descriptor is marked with
the Last descriptor, and the accumulated byte
count is available in the Rx Bytes field.
When this bit is available, you can enable ordisable it using the strap signal,
ss_close_desc_ena_i.
Dependencies:
This bit is available only when the Close Descriptor
Enhancement option is enabled in the HW
configuration.

－1151/1293－

CXD5602 User Manual

Table USB-68 Endpoint Control Register (Continued)
DMA/
Reset

Read/

Slave

Bit

Bit ID

Description

Value

Write

Mode

10

SEND
NULL

Send NULL packet
This bit is available only when the Send NULL
option is selected through coreConsultant.
This bit provides the application with a mechanism
to instruct the UDC Subsystem to send a NULL
(zero-length) packet when no data is available in
the particular endpoint’s TxFIFO. If this bit is set,when no data is available in the endpoint’s TxFIFO,
the UDC Subsystem sends a NULL packet.
Dependencies

1’b0

RW

DS

1’b0

RW

D

9

RRDY

This bit is available only when the Send NULL
option is selected through the HW configuration.
Receive Ready
If this bit is set by the application, on receiving an
OUT packet, the DMA sends the packet to systemmemory. This bit is deasserted at the end of packet
if the Descriptor Update bit is set in the Device
Control register. This bit is deasserted at the end of
payload if the Descriptor Update bit is deasserted.
This bit can be set by the application at any time.
The application cannot clear this bit if the DMA isbusy transferring the data. If multiple receive FIFO
controllers is not implemented, this bit is reserved.
Dependencies
This bit is available only when the Multiple RX FIFO
option is enabled in the HW configuration.

－1152/1293－

CXD5602 User Manual

Table USB-69 Endpoint Control Register (Continued)

Bit

Bit ID

Description

8

CNAK

7

SNAK

Clear NAK
Used by the application to clear the NAK bit (bit 6,
below). After the subsystem sets bit 6 (NAK), theapplication must clear it with a write of 1 to the
CNAK bit. (For example, after the application has
decoded the SETUP packet and determined it is
not an invalid command, the application must set
the CNAK bit of the control endpoint to 1’b1 to clear
the NAK bit.)
The application also must clear the NAK bit
whenever the subsystem sets it. (The subsystemsets it due to the application setting the Stall bit.)
The application can clear this bit only when the
RxFIFO is empty (for single RxFIFO
implementation) or when the RxFIFO
corresponding to the same logical endpoint isempty (Multiple RxFIFO implementation).
Note: If the Clear NAK enhancement is enabled in
the RTL configuration, then the application canwrite CNAK any time without waiting for a RxFIFO
empty condition. The NAK bit is cleared
immediately upon write to CNAK bit. No polling isnecessary.
Set NAK
Used by the application to set the NAK bit (bit 6 ofthis register). The application must not set the NAK
bit for an IN endpoint until it has received an IN
token interrupt indicating that the TxFIFO is empty.

－1153/1293－

Reset
Value

Read/
Write

DMA/
Slave
Mode

1’b0

WO

DS

1’b0

WO

DS

CXD5602 User Manual

Table USB-70 Endpoint Control Register (Continued)

Reset

Read/

DMA/
Slave

Bit

Bit ID

Description

Value

Write

Mode

6

NAK

After a SETUP packet, which is decoded by theapplication, is received by the core, the core sets
the NAK bit for all control IN/OUT endpoints. NAK isalso set after a STALL response for the endpoint(the STALL bit is set in Endpoint Control register bit0).
• 1: The endpoint responds to the USB host with a
NAK handshake.
• 0: The endpoint responds normally.

1’b0

RO

DS

2’b00

RW

DS

1’b0

RW

DS

1’b0

RW

DS

5:4

ET

Note 1: A SETUP packet is sent to the application
regardless of whether the NAK bit is set.
Note 2: If the ignore NAK for ISO OUT
enhancement is enabled in the RTL configuration,and if the NAK for ISOC OUT endpoint is set, thenthe data out from the host is accepted, provided
there is space in the fifo. Without this enhancement
enabled, the NAK set on ISOC OUT endpoint
rejects the ISOC out data packet.
Endpoint Type (2-bit). The possible options are:• 2’b00: Control endpoint• 2’b01: Isochronous endpoint• 2’b10: Bulk endpoint• 2’b11: Interrupt endpoint

3

P

2

SN

Poll Demand
Poll demand from the application.
The application can set this bit after an IN token is
received from the endpoint. The application canalso set this bit before an IN token is received forthe endpoint, if it has the IN transfer data inadvance.
Note: After sending a zero-length or short packet,
the application must wait for the next
XFERDONE_TXEMPTY interrupt, before setting up
the P bit for the next transfer.
Configures the endpoint for Snoop mode. In thismode, the subsystem does not check thecorrectness of OUT packets before transferring
them to application memory. Reserved for IN
endpoints.

－1154/1293－

CXD5602 User Manual

Table USB-71 Endpoint Control Register (Continued)

Bit
1

Bit IDF

0S

Description
Flush the TxFIFO
Reserved for OUT endpoints.
The application firmware sets this bit to 1'b1 after it
has detected a disconnect/connect on the USB
cable, then waits for the IN token endpoint interrupt
before resetting this bit to 1'b0. This flushes thestale data out of the TxFIFO. This bit is cleared by
the core when TDC (Transmit DMA Complete)occurs on this endpoint.
STALL HandshakeOn successful reception of a SETUP packet(decoded by the application), the subsystem clears
both IN and OUT Stall bits, and sets both the IN andOUT NAK bits. The application must check for
RxFIFO emptiness before setting the IN and OUT
STALL bit.
For non-SETUP packets, the subsystem clears
either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets
the corresponding NAK bit. The subsystem returns
a STALL handshake for the subsequenttransactions of the stalled endpoint until the USB
host issues a Clear_Feature command to clear it.
Once this bit is set, if the subsystem has already
returned a STALL handshake to the USB host, theapplication firmware cannot clear the S bit to stop
the subsystem from sending the STALL handshakeon the endpoint. The host must instead send one of
the following commands to clear the endpoint Halt
status:• Clear Feature (Halt)• SetConfiguration• SetInterface.

－1155/1293－

Reset
Value
1’b0

Read/
Write
RW

DMA/
Slave
Mode
DS

1’b0

RW

DS

CXD5602 User Manual

3.18.6.3.2

Endpoint Status Register

The Endpoint Status register indicates the endpoint status.
Table USB-72 Endpoint Status Register
DMA/
Bit
31:29
28

Bit IDR
CDC Clear

Description
Reserved
This bit is valid only for OUT endpoints when
CLOSE_DESC feature is enabled. This bit will
be set by the core HW when CDC bit in the EP
Control register is cleared by the HWgenerating an interrupt. After servicing theinterrupt the application (SW) must clear this
bit.

Reset
Value
1’b0

Read/
Write
R/WC

Slave
Mode
D

Dependencies
This bit is available only when the Close
Descriptor Enhancement option is enabled in
the HW Configuration.
27

XFERDONETXEMPTY

Transfer Done/Transmit FIFO Empty.
This bit indicates that the TXFIFO is empty
after the DMA transfer has been completed.
The application can use this bit to set the poll
bit for the next transfer. The application mustfirst clear this bit after servicing the interrupt.

1’b0

R/WC

DS

26

RSS

Received Set Stall indication.
This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint.
To stall this endpoint, the application can set
the S bit in Endpoint Control Register. After
this, the application clears this RSS bit toacknowledge the reception of Set Feature stallcommand. Once this RSS bit is cleared, core
sends the zero-length packet for the Status IN
phase of Set Feature command.

1’b0

R/WC

DS

Received Set Stall indication is applicable onlyfor Bulk and Interrupt transactions, and only
when the "Set and Clear Featureenhancement" is enabled in coreConsultant.
Dependencies
This bit is applicable only when the Set andClear Feature enhancement is enabled in
the HW Configuration.

－1156/1293－

CXD5602 User Manual

Table USB-73 Endpoint Status Register (Continued)

Bit
25

24

23

Bit IDRCSTXEMPTY

ISO IN
DONE

Description
Received Clear Stall indication.
This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint.
To continue to stall the endpoint, the applicationmust set the S bit Endpoint Control Register.
After this, the application clears this RCS bit toacknowledge the reception of clear stallcommand. Once this bit is cleared, core sends
the zero-length packet for the Status IN phaseof clear stall command.
Received Clear Stall indication is applicable
only for Bulk and Interrupt transactions, andonly when the "Set and Clear Featureenhancement" is enabled in coreConsultant.
Dependencies
This bit is applicable only when "Set and Clear
Feature enhancement" is enabled in the HW
Configuration.
Transmit FIFO Empty detected.
This bit indicates that the Transmit FIFO Empty
condition is triggered. Application can use thisinformation to load the subsequent data into theTransmit FIFO. The application must clear thisbit after writing the data into the Transmit FIFO.
Note: This bit is not used for Isochronous
endpoints
Dependencies
This bit is available only when the TX FIFOEMPTY enhancement is enabled in HW
Configuration.
Isochronous IN transaction for the current
microframe is complete.
This bit indicates that the isochronous IN
transaction for this endpoint is complete. The
application can use this information to program
the isochronous IN data for the next
microframe. This bit is used only in Slave-Only
mode.
Note: This bit is reserved for the UDC11-AHB
Subsystem.

－1157/1293－

Reset
Value
1’b0

Read/
Write
R/WC

DMA/
Slave
Mode
DS

1’b0

R/WC

DS

1'b0

RW

S

CXD5602 User Manual

Table USB-74 Endpoint Status Register (Continued)
DMA/
Bit

Bit ID

Description

22:11

RX PKT
SIZE

10

TDC

9

HE

8

MRXFIFO
EMPTY

Receive Packet Size
Indicates the number of bytes in the current
receive packet the RxFIFO is receiving.
Because the USB host always sends 8 bytes of
SETUP data, these bits do not indicate thereceipt of 8 bytes of SETUP data for a SETUP
packet. Rather, these bits indicate theconfiguration status (Configuration number[22:19], Interface number [18:15], and Alternate
Setting number [14:11]). This field is used inslave mode only.
In DMA mode, the application must check thestatus from the endpoint data descriptor.
Transmit DMA Completion
Indicates the transmit DMA has completed
transferring a descriptor chain’s data to the Tx
FIFO. After servicing the interrupt, theapplication must clear this bit.
Error response on the host bus (AHB) when
doing a data transfer, descriptor fetch, or
descriptor update for this particular endpoint.
After servicing the interrupt, the applicationmust clear this bit.
Receive Address FIFO Empty Status
This bit indicates the empty status of theendpoint receive address FIFO. This bit is set
by the core after the DMA transfers data tosystem memory, and there are no new packets
received from the USB. This bit is cleared by
the core after receiving a valid packet from theUSB.
• 1’b1: EP RXFIFO is empty

Reset
Value

Read/
Write

Slave
Mode

12’h0000

RW

DS

1’b0

R/WC

D

1’b0

R/WC

DS

1’b1

RO

DS

1’b0

R/WC

D

• 1’b0: EP RXFIFO is not empty

7

BNA

Note: This field is reserved in single receive
FIFO configurations.
Buffer Not Available
The subsystem sets this bit when thedescriptor’s status is either Host Busy or DMA
Done to indicate that the descriptor was notready at the time the DMA tried to access it.
After servicing the interrupt, the applicationmust clear this bit.

－1158/1293－

CXD5602 User Manual

Table USB-75 Endpoint Status Register (Continued)
DMA/
Bit

Bit ID

Description

6

IN

5:4

OUT

3:0

R

An IN token has been received by this endpoint.
After servicing the interrupt, the application mustclear this bit. (Reserved for OUT endpoints.)
An OUT packet has been received by thisendpoint. The encoding of these two bits
indicates the type of data received.
The possible options are:・2’b00: None・2’b01: Received data
・2’b10: Received SETUP data (8 bytes)
・2’b11: Reserved(The application must write the same values toclear these bits.)
Note: In Slave mode, when the "Set and Clear
Feature enhancement" is enabled incoreConsultant, then the application must clear
these bits only after clearing the FIFO (in otherwords, only when the RXFIFO is empty).
Clearing these bits while FIFO is not empty
causes these bits to remain set until the FIFO iscleared. If by that time the Set/Clear Featurecommand referring to this endpoint is received,
then the Endpoint Status register shows both
OUT and RCS/RSS bits, which the application
might not be able to handle properly.
Reserved－1159/1293－

Reset
Value

Read/
Write

Slave
Mode

1'b0

R/WC

DS

2'b00

R/WC

DS

-

-

-

CXD5602 User Manual

3.18.6.3.3

Endpoint Buffer Size IN/Receive Packet Frame Number OUT Register

This dual-function register holds the endpoint buffer size when the endpoint is an IN endpoint. When the endpoint is an
OUT endpoint, the register contains the frame number in which the packet is received, updated in bits 15:0. This frame
number information is useful when handling isochronous traffic.
Table USB-76 Buffer Size/Frame Number Register
DMA/
Bit

Bit ID

Description

Reset
Value

Read/
Write

Slave
Mode

31:18

R

Reserved

-

-

-

17:16

ISO IN
PID

2'b00

RW

S

17:16

ISO OUT
PID

2'b00

RO

S

15:0

BUFF
SIZE

Initial data PID to be sent for a high-bandwidthisochronous IN transaction.
This field is used only in Slave-Only mode.
・2’b00: DATA0 PID is sent
・2’b01: DATA0 PID is sent
・2'b10: DATA1 PID is sent
・2'b11: DATA2 PID is sent
Note: These bits are reserved for the UDC11AHB Subsystem.
Data PID received for a high-bandwidthisochronous OUT transaction.
This field indicates that the data PID for thecurrent packet is available in the Receive FIFO.
This field is used only in Slave-Only mode.
・2'b00: DATA0 PID is received
・2'b01: DATA1 PID is received
・2'b10: DATA2 PID is received
・2'b11: MDATA PID is received
Note: These bits are reserved for the UDC11AHB Subsystem.
Buffer size required for this endpoint.
The application can program this field to makeeach endpoint’s buffers adaptive, providing
flexibility in buffer size when the interface orconfiguration is changed. This value is in 32-bit
words, and indicates the number of 32-bit word
entries in the Transmit FIFO.
(IN only)
Note: This value cannot be changed
dynamicallyduring operation.
Dependencies
The value in this field is determined by the TX
buffer pointer width. See “Tx Buffer PointerWidth”.

16’h0000

RW

DS－1160/1293－

CXD5602 User Manual

Table USB-77 Buffer Size/Frame Number Register (Continued)
DMA/
Bit

Bit ID

Description

Reset
Value

Read/
Write

Slave
Mode

15:0

FRAME

Frame number in which the packet is received.

14’h0000RODSNUMBERFor high-speed operation:
1. [15:14] Reserved
2. [13:3] Millisecond frame number
3. [2:0] Microframe number
For full-speed operation:
4. [15:11] Reserved
5. [10:0] Millisecond frame number

3.18.6.3.4

Endpoint Buffer Size OUT/Maximum Packet Size Register

This register holds the endpoint buffer size when the endpoint is an OUT endpoint. If Multiple Receive FIFO
Controllers is not implemented, these BUFF SIZE bits are reserved. This register also specifies the maximum packet
size an endpoint should support. This maximum size is used to calculate whether the Receive FIFO has sufficient space
to accept a packet. When changing the maximum packet size for a specific endpoint, the user must also program the
UDC register space.
Table USB-78 Endpoint Buffer Size OUT/Maximum Packet Size Register
DMA/
Bit
31:16

Bit ID
BUFF

Description
Buffer size required for this endpoint. The

SIZEapplication can program this field to make each
endpoint’s buffers adaptive, providing flexibility
in buffer size when the interface or configurationis changed. This value is in 32-bit words, andindicates the number of 32-bit word entries in
the Receive FIFO. If Multiple Receive FIFO
Controllers is not implemented, these bits arereserved.
Note: This value cannot be changed
dynamically during operation.
Dependencies• This field is applicable only when the Multiple
Receive FIFO Controllers enhancement isenabled in coreConsultant. See “Support
Multiple Receive FIFO” in Table USB-42.
• The value in this field is determined by the
RX buffer pointer width option in
coreConsultant. See “Rx Buffer PointerWidth” in Table USB-42.

－1161/1293－

Reset
Value
16’h0000

Read/
Write
RW

Slave
Mode
DS

CXD5602 User Manual

Table USB-79 Endpoint Buffer Size OUT/Maximum Packet Size Register (Continued)
DMA/
Bit

Bit ID

15:0

MAX PKT Maximum packet size for the
SIZE
endpoint. This is the value in bytes.
The maximum packet size must
equal the packet size being
programmed in the UDCVCI/UDC20
endpoint register.

3.18.6.3.5

Description

Reset
Value

Read/
Write

Slave
Mode

16’h0000_0000

RW

DS

Endpoint SETUP Buffer Pointer Register

Endpoint SETUP buffer pointers are used for SETUP commands. The Endpoint SETUP Buffer register tracks control
endpoint buffer registers; endpoint buffer registers for all other endpoint types are reserved. The Endpoint SETUP
Buffer Pointer register is used only in DMA mode. This register is read-and write-capable, with a reset value of
32’h0000_0000. This is applicable only to control endpoints. For all other endpoints this is reserved.
Table USB-80 Endpoint SETUP Buffer Pointer Register
DMA/
Bit

Bit ID

Description

Reset
Value

31:0

SUBPTRSETUP Buffer Pointer32’h0000_0000

3.18.6.3.6

Read/
Write

Slave
Mode

RW

D

Endpoint Data Descriptor Pointer Register

This register contains data descriptor pointers. Both IN and OUT endpoints have one data descriptor pointer each.
Table USB-81 Endpoint Data Descriptor Pointer Register
DMA/
Bit

Bit ID

Description

Reset
Value

Read/
Write

Slave
Mode

31:0

DESPTR

Descriptor Pointer32’h0000_0000

RW

D－1162/1293－

CXD5602 User Manual

3.18.6.4

Command and Status Register Memory Map

The endpoint-specific CSRs occupy the first 1024 bytes of the map. Each endpoint consumes 32 bytes ofmemory space in both the IN and OUT directions. All 16 endpoints are thus serviced by 512 bytes for eachdirection. The global CSRs, which serve the device, consume 32 bytes of memory space. The following tableshows the address allocation for the CSRs.
Table USB-82 CSR Memory Map
CSR

Offset Address

IN Endpoint-Specific Registers
Endpoint 0 Control register

000 h

Endpoint 0 Status register004 h

Endpoint 0 Buffer Size register008 hEndpoint 0 Maximum Packet Size register

00C h

Reserved

010 h

Endpoint 0 Data Descriptor Pointer register

014 hReserved

018 hEndpoint 0 Write Confirmation register (for Slave-Only mode)

01C h

Endpoint 1 registers

020 h–03C h

Endpoint 2 registers

040 h–05C h

Endpoint 3 registers

060 h–07C h

Endpoint 4 registers

080 h–09C h

Endpoint 5 registers

0A0 h–0BC h

Endpoint 6 registers

0C0 h–0DC h

Endpoint 7 registers

0E0 h–0FC h

Endpoint 8 registers

100 h–11C h

Endpoint 9 registers

120 h–13C h

Endpoint 10 registers

140 h–15C h

Endpoint 11 registers

160 h–17C h

Endpoint 12 registers

180 h–19C h

Endpoint 13 registers

1A0 h–1BC h

Endpoint 14 registers

1C0 h–1DC h

Endpoint 15 registers

1E0 h–1FC h

OUT Endpoint-Specific Registers
Endpoint 0 Control register

200 h－1163/1293－

CXD5602 User Manual

Table USB-83 CSR Memory Map (Continued)
CSR

Offset Address

Endpoint 0 Status register

204 hEndpoint 0 Packet Frame Number register

208 h

Endpoint 0 Buffer Size OUT/Maximum Packet Size register

20C h

Endpoint 0 SETUP Buffer Pointer register

210 h

Endpoint 0 Data Descriptor Pointer register

214 hReserved

218 hEndpoint 0 Read Confirmation register for zero-length OUT data (forSlave-Only mode)
Endpoint 1 registers

21C h

Endpoint 2 registers

240 h–25C h

Endpoint 3 registers

260 h–27C h

Endpoint 4 registers

280 h–29C h

Endpoint 5 registers

2A0 h–2BC h

Endpoint 6 registers

2C0 h–2DC h

Endpoint 7 registers

2E0 h–2FC h

Endpoint 8 registers

300 h–31C h

Endpoint 9 registers

320 h–33C h

Endpoint 10 registers

340 h–35C h

Endpoint 11 registers

360 h–37C h

Endpoint 12 registers

380 h–39C h

Endpoint 13 registers

3A0 h–3BC h

Endpoint 14 registers

3C0 h–3DC h

Endpoint 15 registers

3E0 h–3FC h

220 h–23C h

Global Registers
Device Configuration register

400 hDevice Control register404 hDevice Status register408 hDevice Interrupt register40C h

Device Interrupt Mask register

410 hEndpoint Interrupt register

414 h－1164/1293－

CXD5602 User Manual

Table USB-84 CSR Memory Map (Continued)
CSR

Offset Address

Endpoint Interrupt Mask register418 hTest Mode register. Reserved if Test mode is not supported.

41C h

Release number register. Reserved for UDC11-AHB.

420 h

LPM Control/Status register

424 hReserved

428 h–4FC h

UDC registers

500 h–7FC h

Apart from the subsystem CSRs, the UDC contains CSRs that require 768 bytes of memory space. These CSRs are
mapped to the 500h-7FCh address space. The SETUP command address pointer register (offset address 500h) is nolonger writable and returns 0 when read, because the SETUP command address pointer is already hardcoded to
16’hFFF0 in both the subsystem and the UDC core. The application must use an offset address, starting from 504h, then508h, and so on, to program the UDC core’s endpoint buffers. The subsystem maps these offset addresses in turn with
the UDC CSR addresses, starting from 4h, 8h, and so on. For more details on these CSRs, refer to 3.18.6.6 and 3.18.6.7.
Writing to the offset address (offset 12’h01c + [endpoint number x 12’h020]) (hexadecimal) confirms the IN data into
the TxFIFO. This is applicable only in the Slave-Only mode of operation. The data in the RxFIFO is mapped fromaddress 800h up to an address of the user’s design, which is followed by the address space of the TxFIFO.

－1165/1293－

CXD5602 User Manual

Figure USB-43 Memory Map (Processor Viewpoint)－1166/1293－

CXD5602 User Manual

3.18.6.5

Hand shake Response Options During a Control Command
Status-OUT StageNote

For a control command’s status-IN stage, the subsystem sends a zero-length
data packet by itself.

Table USB-85 Handshake Response Options During a Control Command’s Status-OUT Stage
Data Phase of
Status-OUT Stage

Control
Command

STATUS(Bit 7)STATUS_1(Bit 8)

Handshake Phaseof Status-OUT Stage

Zero-length packet

Internal:
Decodedby UDCAHB

1’b0
1’b1
1’b1

1’b0
1’b0
1’b1

The UDC-AHB sends the USB hostan ACK, and does not send theapplication a zero-length packet.

Zero-length packet

Internal:

1’b0

1’b1

Reserved for future use.

External:

1’b0

1’b0

The UDC-AHB sends the application

Decodedbyapplication

1’b1
1’b1

1’b0
1’b1

a zero-length packet and returns an
ACK handshake to the USB host
only if the NAK bit is cleared. If theapplication has set the S bit, the
UDC-AHB returns a STALL
handshake to the USB host, anddoes not send a zero-length packet
to the application.

Zero-length packet

External:
Decodedbyapplication

1’b0

1’b1

Reserved for future use.

Non-zero-lengthInternal:

1’b0

1’b0

The UDC-AHB sends the application

packetDecodedby UDCAHB

Non-zero-lengthInternal:

packetDecodedby UDC20

Non-zero-length
packetDecodedby UDCAHB
Zero-length packet

a non-zero-length packet and returns
an ACK handshake to the USB host
only if the NAK bit is cleared. If theapplication has set the S bit, the
UDC-AHB returns a STALL
handshake to the USB host, anddoes not send a non-zero-length
packet to the application.
1’b0

1’b1

Reserved for future use.

Internal:

1’b1

1’b0

The UDC20 sends the USB host a

Decodedby UDC20AHB

1’b1

1’b1

STALL, and does not send theapplication a non-zero-length packet.

－1167/1293－

CXD5602 User Manual

Table USB-86 Handshake Response Options During a Control Command’s Status-OUT Stage (Continued)
Data Phase of
Status-OUT Stage

Control
Command

STATUS(Bit 7)STATUS_1(Bit 8)

Handshake Phaseof Status-OUT Stage

Non-zero-length
packetExternal:
Decodedbyapplication

1’b0

1’b0

The UDC-AHB sends the applicationa non-zero-length packet and returns
an ACK handshake to the USB host
only if the NAK bit is cleared. If theapplication has set the S bit, the
UDC-AHB returns a STALL
handshake to the USB host, anddoes not send a non-zero-length
packet to the application.

Non-zero-length

External:

1’b0

1’b1

Reserved for future use.

packetDecodedbyapplication

Non-zero-length

External:

1’b1

1’b0

The UDC-AHB sends the application

packetDecodedbyapplication

Non-zero-length

External:

packetDecodedbyapplicationa non-zero-length packet and returns
an ACK handshake to the USB host
only if the NAK bit is cleared. If theapplication has set the S bit, the
UDC-AHB returns a STALL
handshake to the USB host, anddoes not send a non-zero-length
packet to the application
1’b1

1’b1

The UDC20 sends the USB host a
STALL, and does not send theapplication a non-zero-length packet.

－1168/1293－

CXD5602 User Manual

3.18.6.6

UDCVCI Endpoint Register

Table USB-87 UDCVCI Endpoint Register

Bit

Bit ID

Description

Reset
Value

Read/
Write

DMA/
Slave
Mode

ConfigParameter
Dependency

3:0-

Logical Endpoint Number

4’b0000

RW

DS

-

4

-

Endpoint direction. The possible
options are:・1’b0: OUT
・1’b1: IN

1’b0

RW

DS

-

6:5

-

Endpoint type. The possible options
are:・2’b00: Control
・2’b01: Isochronous・2’b10: Bulk
・2’b11: Interrupt

2’b00

RW

DS

-

10:7

-

Configuration number to which thisendpoint belongs.

4’b0000

RW

DS

-

14:11

-

Interface number to which thisendpoint belongs.

4’b0000

RW

DS

-

18:15

-

Alternate setting to which thisendpoint belongs.

4’b0000

RW

DS

-

28:19

-

Maximum packet size

10’h000

RW

DS

-

31:29

-

Reserved

-

-

-

-

－1169/1293－

CXD5602 User Manual

3.18.6.7

UDC20 Endpoint Register

Table USB-88 UDC20 Endpoint Register

Bit

Bit ID

Description

Reset
Value

Read/
Write

DMA/
Slave
Mode

ConfigParameter
Dependency

3:0-

Logical Endpoint Number

4’b0000

RW

DS

-

4

-

Endpoint direction. The possible
options are:・1’b0: OUT
・1’b1: IN

1’b0

RW

DS

-

6:5

-

Endpoint type. The possible options
are:・2’b00: Control
・2’b01: Isochronous・2’b10: Bulk
・2’b11: Interrupt

2’b00

RW

DS

-

10:7

-

Configuration number to which thisendpoint belongs.

4’b0000

RW

DS

-

14:11

-

Interface number to which thisendpoint belongs.

4’b0000

RW

DS

-

18:15

-

Alternate setting to which thisendpoint belongs.

4’b0000

RW

DS

-

29:19

-

Maximum packet size

11’h000

RW

DS

-

31:30

-

Reserved

-

-

-

-

Note

In full-speed mode operation, application firmware must program the maximum
packet size of default endpoint 0 in accordance with the value defined in USB
2.0 specification－1170/1293－

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3.18.6.8

Release Number Register

Table USB-89 Release Number Register

Bit

Bit ID

Description

Reset
Value

Read/
Write

DMA/
Slave
Mode

ConfigParameter
Dependency

31:0

RELEASENUMBER

Product release number.
This field indicates the four-digit
release number in hexadecimalformat. For example, 32_33_30_ 2A
represents 2.30* in ASCII character.
・[31:24]: 32 of 32_33_30_ 2A
・[23:16]: 33 of 32_33_30_ 2A
・[15:8]: 30 of 32_33_30_ 2A
・[7:0]: 2A of 32_33_30_ 2A

ReleasenumberRO

DS-

1. * is an alphabetic character (for example, a, b, or c) that represents a update to the release, which does not impact the
RTL source.

Example conversions from hex to ASCII character:
HEX

ASCII Character

30

0

31

1

32

2

33

3

34

4

2A

*

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3.18.73.18.7.1

Slave-Only Operation
Overview

This chapter explains the functionality of the UDC-AHB Subsystem in Slave-Only mode. The UDC-AHB Subsystem(Figure USB-44) is designed to be implemented in Slave-Only mode in applications with limited software complexity,
or when the subsystem has a dedicated master for data processing. In Slave-Only mode, the application initiates all datatransfers, and the subsystem acts as an AHB slave for both data and CSR transfers. The subsystem can respond to theapplication through an interrupt signal on a dedicated side band. In Slave-Only mode, the subsystem acts via thefollowing interfaces:❖ The AHB Slave-Only interface❖ The Transmit (IN) Data FIFO buffer❖ The Receive (OUT) Data FIFO buffer❖ The AHB Subsystem Command Status Register❖ The UDC Command Status Register－1172/1293－

CXD5602 User Manual

Figure USB-44 UDC-AHB Subsystem Architecture－1173/1293－

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3.18.7.2

USB Transaction Layer Interface

The USB Transaction Layer Interface (UTLI) is the first module to interface with the UDC during data reception andthe last to interface with it during transmission. UTLI has a major role in the UDC-AHB Subsystem, as this blockcontains most of the USB and the UDC Virtual Component Interface (VCI) logic. The UTLI:❖ Interfaces with the UDCVCI❖ Interfaces with endpoint-specific FIFOs when transmitting data in response to USB host IN requests❖ Interfaces with the Receive FIFO when receiving OUT data from the USB host❖ Works with the CSR block to maintain correct status and control❖ Works with the interrupt manager to generate proper interrupts to the application❖ Interfaces with the SOF tracker to ensure that isochronous data is transmitted in its intended frame
For both IN and OUT data, the UTLI sends a Confirm signal to the FIFOs to update the FIFO pointers. The UTLI
generates a Confirm signal only when the UDC indicates that the transaction has been successful on the USB.
For IN data, the UTLI reads from the Endpoint FIFOs and provides this data to the UDC, which then transmits the data
to the USB. If the data transfer is not successful, the data in the FIFOs is retained for retransmission on the next IN
request from the USB host. If the transfer is successful, the Confirm signal from the UTLI exports the Read pointers to
the Write domain.
For OUT data, received USB packets are written to the RxFIFO. If a packet is received without errors, the UTLI
generates a Confirm signal, enabling the Write pointers to be exported to the Read domain. If there are reception errors,
the pointers are rolled back to their previous values as though nothing had been written to the RxFIFO.

3.18.7.2.1

UTLI-to-TxFIFO Transaction

Upon receiving a command from the UDC, the UTLI initiates a transaction by signaling the Transmit FIFOs to read IN
data for different endpoints. The UTLI assumes that there is only one FIFO and reads from that FIFO for IN data. TheUTLI outputs the endpoint number for the IN data requested by the USB host.

3.18.7.2.2

UTLI-to-RxFIFO Transaction

When the UDC receives OUT data, it initiates an application bus (VCI) write sequence. This data is written to the
Receive FIFO if space is available. Since the UTLI can determine how much Receive FIFO space is available, it cansend acknowledgements to the USB host that are appropriate for different endpoint types.

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3.18.7.3

SOF Tracker

The USB host sends SOF packets every 1 ms for low-speed/full-speed (LS/FS) operation and every 125 μs forhigh-speed (HS) operation. This SOF token represents the start of every frame for isochronous data synchronization.
When an SOF packet is received from the host, the UDC captures its 11-bit frame number, and gives it to the back end
within a single clock pulse, indicating the reception of an SOF token. The SOF tracker module maintains an internalframe counter, which counts 1 ms for FS/LS and 125 μs for high-speed. If, after the frame counter expires, an SOF
token is still not received by a predefined delay (12042 full-speed bits for full-speed operation, 60096 high-speed bitsfor high-speed operation), the SOF Tracker indicates a missed SOF token. The subsystem moves to the next frame
number in the counter to provide isochronous data for any subsequent ISO requests from the USB host. In order toprovide backward-compatibility, in high-speed mode the frame number from the UDC does not change for 8
microframes. The SOF Tracker module generates the correct 14-bit microframe number by adding a 3-bit microframe
counter to the 11-bit frame number provided by the UDC. To summarize, the SOF Tracker:❖ Tracks incoming SOFs
❖ Generates an event when an SOF is received or missed❖ Generates a 14-bit microframe number in high-speed mode, based on the UDC’s 11-bit frame number
SOF Tracker Transactions
If the SOF Tracker detects a missing SOF packet, it increments its internal frame number to match the current USB
SOF token. It flushes the data associated with the missing SOF token, then sends the data to match the new frame
number. Since the isochronous-IN FIFOs can hold only one data packet (intended for the current frame) at a time, if IN
isochronous data is not transmitted in the intended frame, it is considered stale and the TxFIFO for that frame number ismade available for overwriting. In high-speed mode, the SOF tracker generates microframe numbers on it own. In thismode, the UDC does not increment the frame number upon receipt of every micro-SOF, because every frame tick lasts
only 125 μs. Maintaining backward compatibility with the 1 ms frame-tick of USB 1.1 requires the UDC to increment
the frame number once every eight microframes. By incrementing the microframe number every time it receives a
micro-SOF, the SOF tracker isolates the micro-SOFs from the rest of the logic.

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3.18.7.4

Interrupt Manager

The Interrupt Manager interfaces with different blocks and generates an interrupt to the processor when any of thefollowing events occurs:❖ Reception of an SOF token❖ Detection of a USB suspend❖ Detection of a USB reset❖ Reception of a SetInterface command❖ Reception of a SetConfiguration command
The above events are device events. The Interrupt Manager interfaces with the UTLI for information on these events.
An interrupt is also set when any of the following endpoint-related events occurs:❖ Reception of a request for IN data
❖ Reception of an OUT data packet❖ Reception of eight bytes of SETUP data packet❖ An application error resulting in an AHB Error response
The Interrupt Manager interfaces with the Transfer Engine to set the above interrupts. All the above interrupt bits arecleared by writing a 1’b1.

3.18.7.5

Transmit FIFO Controller

Transmit FIFO controllers are endpoint-specific blocks, and each IN endpoint must have a TxFIFO controller
instantiated for it. Each TxFIFO controller generates an address for its RAM and maintains its write and read pointers.
This address bounds a small address range within the RAM equal to the FIFO size programmed into the CSRs for theendpoint. Each FIFO controller’s base address is derived from the upper limit of the preceding FIFO controller. Ideally,for Endpoint 0 (the control endpoint) the base address is 0 (corresponding to the start of the RAM). The base address of
this FIFO controller, plus its FIFO size, is used by the succeeding FIFO controller as its base address. The FIFO size
programmed into the subsystem CSR must be word-aligned. The data width is 36 bits, of which 32 are for data, andfour are for the byte enable indication. The FIFO controller block also has a hard-coded endpoint number as an input toenable itself when it is addressed by the UTLI or the Transfer Engine.
To summarize, TxFIFO controllers:❖ Generate RAM addresses using the base address provided by the preceding TxFIFO controller❖ Maintain the TxFIFO status flags❖ Generate the base address for the next TxFIFO controller
When programming the FIFO size, the application must ensure that the FIFO sizes are integral multiples of the
maximum packet size supported by that endpoint. The signals to the external RAM with basic read/write transfer are
shown in Figure USB-45.

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Figure USB-45 External RAM Write/Read Transfer

TxFIFO Pointers
When the TxFIFOs are read or written, the FIFO pointers are not immediately exported to DMA or Slave-Only
controllers (for OUT transfers) or to the UTLI (for IN transfers). Before exporting the pointers, the FIFOs require a
confirmation signal and a signal indicating a successful transfer. If the transfer is not successful, the pointers are rolled
back. If the transfer is successful, the new pointers are exported to the other domain. Figure USB-46 shows the flow fora write transaction. The flow for a read transaction is similar.
Figure USB-46 FIFO Confirm Mechanism－1177/1293－

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3.18.7.6

Receive FIFO Controller

All endpoints share a common receive FIFO. The receive FIFO is built of two individual FIFOs, one for data andanother for addresses. Each entry in the address FIFO component corresponds to an OUT packet received. The address
FIFO entry has an endpoint number and a flag to differentiate regular data from the eight bytes of SETUP data. Upon
receiving this data, UTLI strobes the data into the data FIFO. Upon receiving the packet, the UDC sends a status bit
indicating whether or not the data was received without errors. If the data was received error-free, the UTLI confirms
the data in the receive FIFO by writing the endpoint number and data flag (data/SETUP) into the address FIFO. If thedata was received with errors, the RxFIFO controller rolls back the data FIFO pointers as if nothing had been received.
The data width is 32 bits (32 bits for the data). When the external AHB master tries to access the packet received for aparticular OUT endpoint, it must read the Endpoint Status register to determine the number of bytes to be transferred
and then initiate the appropriate AHB transfers with an appropriate HSIZE (i.e 32, 16, or 8). The data FIFO is
implemented as RAM whereas the address FIFO is implemented with registers, as shown in Figure USB-47. The
minimum depth of the address FIFO is four. A more detailed description of multiple RxFIFO controllers is provided in
3.18.13, “Multiple RxFIFO Controllers.”－1178/1293－

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Figure USB-47 RxFIFO Implementation－1179/1293－

CXD5602 User Manual

3.18.7.7

AHB Slave-Only Interface

Refer to 3.18.8.5.3, “AHB Interface” for more information on the AHB Slave BIU.

3.18.7.8

High-Bandwidth Isochronous Transfers

This section describes OUT and IN packets for high-bandwidth isochronous transfers in Slave-Only mode.

3.18.7.9

OUT Packet in Slave-Only Mode

The data PID received for a high-bandwidth transaction is available in the Endpoint Buffer Size IN/ Receive Packet
Frame Number OUT register. This field indicates the data PID for the current packet-available in the Receive FIFO. For
example, if the host sends three packets with a PID sequence of MDATA, MDATA, and DATA2, when the application
receives the interrupt for the first packet, this register indicates an MDATA PID. After the application reads out the firsttwo maximum-size packets, this register indicates DATA2.

3.18.7.9.1

IN Packet in Slave-Only Mode

The following example flow describes an IN packet.
1. Write the initial data PID (bits 17:16) in the Endpoint Buffer Size IN register. For example, to send three packets in a
microframe, write 2’b11 in the ISO IN PID field.
2. Write the data one maximum-size packet at a time. After writing one maximum-size packet, perform a confirm cycle.
3. Wait for the UDC Subsystem to send the ISO IN Done interrupt. Bit 23 in the Endpoint Status register is set after theentire high-bandwidth transaction is completed on the USB.
4. To change the packet number to be sent in the next microframe, the application can now modify the ISO IN PID fieldin the register.

3.18.7.9.2

Register Access in Slave-Only Mode

During FIFO access, the application must not access the UDC/Subsystem registers or vendor registers (forULPI mode). After starting to access a FIFO, the application must complete the transaction before accessing
the register.

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3.18.83.18.8.1

DMA Operation
Overview

This chapter explains the functionality of the UDC-AHB Subsystem in DMA mode. A major advantage of DMA-based
implementations is that they spare the main processor’s computing power from involvement in data movement tasks.
Use of a scatter-gather DMA helps applications make efficient and optimal use of system memory, a major design
constraint on portable systems. The DMA mode of implementation demands that data be presented in predefinedmemory structure formats. These memory structures are explained in detail in the following subtopics. In DMA mode,
the UDC-AHB Subsystem implements a true scatter-gather memory distribution, in which memory structures arescattered over the system memory. Each endpoint memory structure is implemented as a linked list, where each elementof the list is a data buffer of a predefined size. In addition to data, each buffer also has a status quadlet and a pointer tothe next buffer. The last element of such a linked list can point either to a null pointer, or, if the list is implemented as aring buffer, to the first element of the list. All the endpoints implement these structures in the memory, and apart fromthese structures, all control endpoints implement an additional 16-byte buffer to store SETUP data. The SETUP data
structure does not implement a linked-list structure. The descriptor memory structures are displayed in Figure USB-48..

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Figure USB-48 Descriptor Memory Structure－1182/1293－

CXD5602 User Manual

3.18.8.2

SETUP Data Memory Structure

Figure USB-49 shows the memory structure for SETUP data. Table USB-924 describes the SETUP Data Memory
Structure values. The subsystem receives SETUP data only from the USB host. The buffer size for SETUP data isalways 16 bytes. The SETUP buffer applies only to control endpoints. A “Host Busy” buffer status indicates that theapplication is accessing the location. DMA does not check the buffer status before transferring the 8-byte SETUP
packet. The application must always give highest priority to, and have the buffer ready for, a SETUP packet.
Figure USB-49 SETUP Data Memory Structure

Table USB-90 SETUP Data Memory Structure Values
Bit

Bit ID

Description

BS [1:0]

Buffer Status

Rx Sts [1:0]Receive
StatusStatus of the data buffer. The possible options are:・2’b00: Host ready・2’b01: DMA busy
・2’b10: DMA done
・2’b11: Host busy
Status of received SETUP data. This reflects whether the
SETUP data is received correctly or with errors. The possiblecombinations are:・2’b00: Success・2’b01: DESERR
・2’b10: Reserved
・2’b11: BUFERR
Status of the current configuration associated with the
SETUP packet for a control endpoint (endpoint type “00”,which is different from the default endpoint 0).
Configuration number [27:24]
Interface number [23:20]
Alternate setting number [19:16]
Reserved for future use.

Config Sts [27:16] Configuration
StatusR [15:0]

Reserved－1183/1293－

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3.18.8.3

OUT Data Memory Structure

All endpoints that support OUT direction transactions (endpoints that receive data from the USB host), must implement
a memory structure with the following characteristics:❖ Each data buffer must have a descriptor associated with it that provides the status of the buffer. The buffer itself
contains only raw data.
❖ Each buffer descriptor is 4 quadlets in length.
If the buffer status of the first descriptor is “Host Ready,” the DMA fetches and processes its data buffer; otherwise the
DMA skips to the next descriptor until it reaches the end of the descriptor chain. The buffers the descriptor points tohold packet data for non-isochronous endpoints and frame data for isochronous endpoints. Buffer fill mode does notsupport Isochronous OUT endpoints. Use packet-per-buffer mode instead. These features are discussed in 3.18.8.6.
“Host Ready” indicates that the descriptor is available for the DMA to process. “DMA Busy” indicates that the DMA isstill processing the descriptor. “DMA Done” indicates that the buffer data transfer is complete. “Host Busy” indicatesthat the application is processing the descriptor. A DESERR receive status indicates that the buffer status is somethingother than host ready (2’b00) during descriptor fetch.
The OUT data memory structure is shown in Figure USB-50.
Figure USB-50 OUT Data Memory Structure－1184/1293－

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Table USB-91 OUT Data Memory Structure Values
Bit

Bit ID

Description

BS [31:30]

BufferStatusThis 2-bit value describes the status of the data buffer. The
possible options are:・2’b00: Host ready・2’b01: DMA busy
・2’b10: DMA done
・2’b11: Host busy
This 2-bit value describes the status of the received data. This
reflects whether OUT data has been received correctly or witherrors. The possible combinations are:・2’b00: Success・2’b01: DESERR
・2’b10: Reserved
・2’b11: BUFERR

Rx Sts [29:28]

Receive
StatusL [27]

Last

When set, this bit indicates that this descriptor is the last oneof the chain.

Frame Number[26:16]
PID [15:14](ISO OUT)

Frame Number

The 11-bit frame number in which the current ISO-OUT
packet is received.
This field is for only high-speed isochronous transactions, andindicates the data PID for an isochronous receive packet.
・2'b00: The packet contained in this descriptor is received
with a data PID of DATA0.
・2'b01: The packet contained in this descriptor is received
with a data PID of DATA1.
・2'b10: The packet contained in this descriptor is received
with a data PID of DATA2.
・2'b11: The packet contained in this descriptor is received
with a data PID of MDATA.
Note: These PID bits are only used for database Release
2.20a and later, and cannot be applied to older releases. For
full-speed isochronous transactions, this is a “don’t care” field.

Rx Bytes [15:0](non-ISO OUT)

Receivednumber ofbytes

Rx Bytes [13:0](ISO OUT)

Receivednumber of
bytes

ISO
Received
Data PID

This 16-bit value can take values from 0 to 64K bytes*,depending on the packet size of data received from the USB
host.
*Note: Actual value is (64K – 1) bytes. Equivalent to ‘hFFFF.
This 14-bit value can take values from 0 to 16K bytes*,depending on the packet size of data received from the USB
host.
*Note: Actual value is (16K – 1) bytes. Equivalent to `h3FFF.

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3.18.8.4

IN Data Memory Structure

All endpoints that support IN direction transactions (transmitting data to the USB host) must implement the following
memory structure. Each buffer must have a descriptor associated with it. The application fills the data buffer, updates its
status in the descriptor, and sets the Poll Demand bit. The DMA fetches this descriptor and processes it, moving on inthis fashion until it reaches the end of the descriptor chain. The buffers the descriptor points to hold packet data for
non-isochronous endpoints and frame data for isochronous endpoints. The IN data memory structure is shown in FigureUSB-51.
Figure USB-51 IN Data Memory Structure

Table USB-92 IN Data Memory Structure Values
Bit

Bit ID

Description

BS [31:30]

Buffer Status

This 2-bit value describes the status of the data buffer. The
possible options are:・2’b00: Host ready・2’b01: DMA busy
・2’b10: DMA done
・2’b11: Host busy

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Table USB-93 IN Data Memory Structure Values
Bit

Bit ID

Description

Tx Sts [29:28]

Transmit Status

The status of the transmitted data. This reflects if the IN data
has been transmitted correctly or with errors. The possiblecombinations are:・2’b00: Success・2’b01: DESERR
・2’b10: Reserved
・2’b11: BUFERR

L [27]

Last

When set, this bit indicates that this descriptor is the last oneof the chain.

Frame Number[26:16]

Frame Number

Frame number in which the current packet must betransmitted.
・[26:19]: millisecond frame number
・[18:16]: microframe number

PID [15:14](ISO IN)

Number of
packets per
frameThis 2-bit value indicates the number of packets per µSOF
(microframe) for isochronous IN transfers during high-speed
operation. The application must program these bits in thedescriptor (these bits must be the same for all descriptorsof the same µSOF) such that the subsystem core returns an
isochronous packet with an appropriate data PID per frame.
These bits are reserved for full-speed operation
2’b00 and 2’b01: 1 packet per microframe・2’b10: 2 packets per microframe・2’b11: 3 packets per microframe
Note: These PID bits are only used for database Release
1.8b and later, and cannot be applied to older releases. For
full-speed transactions, these bits are reserved.

Tx bytes [15:0](non-ISO IN)

Number of byes
to be transmitted

Tx bytes [13:0](ISO IN)

Number of byes
to be transmittedThis 16-bit value can take values from 0 to 64K bytes*,
indicating the number of bytes of data to be transmitted to
the USB host.
*Note: Actual value is (64K – 1) bytes. Equivalent to‘hFFFF.
This 14-bit value can take values from 0 to 16K bytes*,
indicating the number of bytes of data to be transmitted to
the USB host.
*Note: Actual value is (16K – 1) bytes. Equivalent to‘h3FFF.

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3.18.8.5

Building Blocks

Refer to 3.18.7.1, “Overview” for all building blocks common to both Slave-Only and DMA mode. The DMA block,which is inactive in Slave-Only mode, is built of three basic components:❖ Transfer Engine - moves the actual data,❖ DMA Controller - controls the movement of the data
❖ AHB Interface- manages the flow of data between the DMA and AHB for both data transfer and CSR accesses
These three blocks are explained in greater detail in the following sections.

3.18.8.5.1

Transfer Engine

The Transfer Engine is slaved to the DMA Controller for the movement of data to and from system memory. When
there is a memory access, the Transfer Engine interfaces with the FIFOs and the AHB Interface module, and indicatesto the DMA whether or not the transfer was successful. If the transfer was unsuccessful, the Transfer Engine also
indicates how many bytes were successfully transferred to the destination, so that the DMA can decide whether to retry
the transaction. When transferring data from the FIFOs, the Transfer Engine depends on status signals from the FIFOs’
respective FIFO controllers. When transferring the data to system memory, the Transfer Engine registers the data, thenwaits for the request from the DMA Controller and decides on the direction of the transfer. It completes the transfer
whether the transaction is completed successfully or if there is an error during the data transfer.

3.18.8.5.2

DMA Controller

The DMA Controller controls data movement to and from system memory. It parses the descriptor structures andinstructs the other subsystem blocks to perform data transfers accordingly. The DMA Controller has two different
controllers, enabling it to control both Transmit (IN) and Receive (OUT) data simultaneously (although transmit andreceive functions cannot be performed simultaneously). The DMA Controller architecture has a descriptor buffer tostore descriptors fetched from memory.

3.18.8.5.3

AHB Interface

This block contains all the subsystem’s AHB protocol logic. This block has two functional states: it acts as a slave when
the application programs the subsystem’s or the UDC’s CSRs, and as master when the DMA performs data transfers.
When acting as AHB master, the subsystem accesses the application memory for descriptors and data buffers. When thesubsystem is in a non-DMA (Slave-Only) mode, the AHB Interface also acts as a slave. In this mode, all the FIFOs arememory-mapped, and the application writes directly to the FIFOs.

AHB Master BIU
The AHB master BIU breaks the transfer at the 1K-byte page boundary and then immediately starts a new transfer witha new incremented address without inserting any wait state. This block interfaces with the Transfer Engine andtranslates the Transfer Engine’s commands into appropriate AHB commands. This block also handles retry and split
responses from the AHB target. The AHB master BIU conveys only error response information to the Transfer Engine
and lets either the DMA or the Transfer Engine decide on the response. This block’s basic functionality block issummarized below.

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CXD5602 User Manual❖ Supports 8-, 16-, and 32-bit read/write access on the AHB❖ Supports both big and little endian FIFO data access (default is little endian)❖ Supports only little endian descriptor access❖ Supports HBURST values SINGLE, INCR, INCR 4/8/16 (WRAP 4/8/16 is not supported)❖ Accepts split, retry, and error responses❖ Cannot lock transactions
The AHB master BIU does not automatically align all transfers within a burst to an address boundary equal
to the size of the transfer. The application must perform this alignment. Descriptor information in systemmemory and buffer pointers must be word-aligned. Table USB-928 describes the HBURST generation by the
AHB master based on different conditions
Table USB-94 HBURST Generation
Descriptor
AccessRemaining Bytes

Burst Enable

Burst Length

HBURST

Yes

Don’t careNo

Don’t care

SINGLEYes

Don’t careYes

8’h00, 8’h01, or

INCR

8’h02
Yes

Don’t careYes

8’h03 or greater

INCR4

No

Don’t careNo

Don’t care

SINGLE/INCR

No< Burst length

YesDon’t care

SINGLE/INCR

No> or = Burst length

Yes

8’h00

SINGLENo> or = Burst length

Yes

8’h03

INCR4

No

> or = Burst length

Yes

8’h07

INCR8

No

> or = Burst length

Yes

8’h0f

INCR16No> or = Burst length

Yes

Other than 00,

INCR

03, 07, and 0f－1189/1293－

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AHB Slave BIU
The AHB slave BIU block acts as a slave on the AHB and responds to all subsystem CSR accesses from the AHB
master. The basic functionality of this block is summarized below.
❖ Supports 8-, 16-, and 32-bit read/write access on the AHB❖ Supports both big and little endian FIFO data access (default is little endian)❖ Supports only little endian CSR access❖ Supports retry and error responses❖ Does not support split transactions❖ Accepts single transfers using either an unspecified-length incrementing burst (INCR) with a burst length of one, or
HBURST=single with a burst length of one.
❖ Accepts HBURST values SINGLE, INCR, INCR 4/8/16 (except WRAP 4/8/16)❖ Generates an error response under the following conditions:✦ A wrap transfer is attempted.
✦ A read from the TxFIFO or write to the RxFIFO is attempted.
✦ A read from an empty RxFIFO is attempted.
✦ A read of excess data from the RxFIFO is attempted when the RxFIFO has run out of data.
✦ A write to a full TxFIFO is attempted.
✦ A transfer is attempted with a non-SINGLE or non-INCR (with one data beat) signal to the CSR.
✦ A transfer is attempted with an illegal HSIZE setting (other than 8, 16, or 32 bits).
❖ Does not support back-to-back transfers for two packets. For example, if there are two packets in the RxFIFO, after
the first is read, the second cannot be read back-to-back. The UDC-AHB Subsystem expects the application to wait
for the proper interrupt before reading data from the RxFIFO. This also applies to reads followed back-to-back by
writes.

3.18.8.6

Features

In all modes, an interrupt for an OUT transaction automatically disables the DMA Receive Engine, which must be
re-enabled by the application. This provides the application sufficient time to service the interrupt.

3.18.8.6.1

Packet-Per-Buffer ModeIn this mode, the DMA transfers packet by packet to various addresses as indicated by the descriptor. This is a true
scatter-gather mechanism. A descriptor update can either happen at the end of each packet transfer or only at the end of
the descriptor chain. The application may be interrupted after processing each descriptor or at the end of a descriptor
chain. Writing 1’b1 to the DU bit of the Device Control register enables descriptor updating and application interrupt tothe software at the end of each packet.
Descriptor Update Enable Operation
In this mode, the DMA updates the descriptor and interrupts the application after each packet is transferred, until itreaches the end of the descriptor chain.

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IN Transaction
Figure USB-52 and－1191/1293－

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Figure USB-53 show the DMA processing an IN token with and without descriptor update, respectively.
Figure USB-52 Control/Bulk-IN Transaction in Packet-Per-Buffer With Descriptor Update Mode

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Figure USB-53 Control/Bulk-IN Transaction in Packet-Per-Buffer Without Descriptor Update Mode

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OUT Transaction
Figure USB-54 and Figure USB-55 show the DMA processing an OUT token with and without descriptor update,respectively.
Figure USB-54 OUT Transaction in Packet-Per-Buffer Mode With Descriptor Update－1194/1293－

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Figure USB-55 OUT Transaction in Packet-Per-Buffer Mode Without Descriptor Update－1195/1293－

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3.18.8.6.2

Buffer Fill Mode（OUT Transfer）

In this mode of operation, the DMA transfers all packets to the large buffer whose address is indicated by the single out
data memory structure descriptor. The DMA Controller updates buffer status when a short packet is received, andsimultaneously sends an interrupt to the application. Buffer fill mode is enabled by writing 1’b1 to the BF bit of theDevice Control register. This mode of DMA operation requires fewer memory accesses than Packet-Per-Buffer With
Descriptor Update mode, increasing throughput. Figure USB-56 shows DMA operation in buffer fill mode for an OUT
transfer.
Figure USB-56 DMA Processing OUT Packets in Buffer Fill Mode

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3.18.8.6.3

Buffer Fill Mode（IN Transfer）

This mode of operation can be entered by using packet-per-buffer mode with only one descriptor indicating the systemmemory starting address, the number of bytes to be transferred to the USB host (Tx Bytes can be greater than a packet),and the “L” bit set in the status quadlet. The DMA Controller updates buffer status after all data has been transferred to
the TxFIFO. The Subsystem then sends the application an interrupt.

3.18.8.6.4

Threshold Enable

The threshold enable feature is used for transferring packets in the OUT direction and for DMA operation only. There isno threshold enable for the IN direction. In this context, “thresholding” means emptying the OUT RxFIFO as soon as it
receives a certain number (the threshold value) of 32-bit words. Thresholding is enabled by writing 1’b1 to the THE bit
in the Device Control register. The 8-bit threshold value is programmed by writing the THLEN bits in the Device
Control register. The threshold value is the number of 32-bit words (quadlets) that must be received by the RxFIFO
before the DMA can start the transfer. When thresholding is disabled, the DMA waits for the complete packet before
starting the data transfer. When thresholding is enabled, the transfer of the packet to host memory starts before thevalidity of the packet is assessed. If, at the end of the transfer, the packet is found to be corrupt, the descriptor is not
updated and the next clean packet overwrites the previous corrupt packet. This conceals the USB error from theapplication. Figure USB-57 shows DMA operation with thresholding enabled.

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Figure USB-57 DMA Processing OUT Packets in Packet-Per-Buffer With Descriptor Update Mode With
Threshold Enabled－1198/1293－

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3.18.8.6.5

Burst Split Enable

When Burst Split is enabled, all AHB transfers (transfers from the DMA to system memory and from system memory
to the TxFIFO) are split into bursts of a specified length. This mode can be enabled by writing 1’b1 to the BREN bit of
the Device Control register. Burst Length is programmed by writing the 8-bit value of the BRLEN to the Device
Control register. This field indicates the number of 32-bit transfers that should happen in a single burst.

3.18.8.6.6

Byte Ordering (Endianness)

System byte ordering can be changed from little endian (default) to big endian and vice versa by writing 1’b1 to the BE
bit in the Device Control register. This conversion is shown in Figure USB-58. Only data accesses are endian-sensitive(in both Slave-Only and DMA modes). Descriptor and CSR accesses are always in little endian mode

Figure USB-58 Byte Ordering (Endianness) Conversion－1199/1293－

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3.18.8.6.7

Relationship Between Threshold Length and Burst Length❖ Threshold length (THLEN) must be greater than (multiples of burst length) or equal to burst length(BRLEN).
THLEN+1 = N*(BRLEN+1)
Where N can be 1, 2, 3...
❖ Threshold length is used only to start the transfer. For example, if the threshold length is programmed as
7 and the total transfer size is 16 DWORDS, Receive DMA starts the transfer as soon as 8 DWORDS are
received from the USB. The AHB master introduces busy states on the AHB bus in case there is a data
underrun in the receive direction.
❖ BRLEN is used to make the AHB master transfer in chunks of BRLEN. If the burst length is 3, the AHB
master transfers 4 DWORDS at a time.
❖ If the threshold length is 8’h07 and the burst length is 8’h03, DMA transfer starts as soon as 8 DWORDS
are received from the USB. On the AHB side, data is transferred in chunks of 4 DWORDS.

3.18.8.7

High-Bandwidth Isochronous Transfers

This section describes OUT and IN packets for high-bandwidth isochronous transfers.

3.18.8.7.1

OUT Packet in DMA Mode

Each descriptor stores one maximum packet size of data. The data PID associated with the packet is available in the PID
field, bits [15:14]. If the microframe contains three packets, data and the corresponding data PID are stored in threedescriptors.

3.18.8.7.2

IN Packet in DMA Mode

The application creates data of one maximum packet size per descriptor. If the application must send three packets inthe microframe, the application must create three descriptors. Data PID information must be provided in the PID field,
bits [15:14].
Note

At low AHB frequencies, with multiple IN endpoint descriptors active, the core transmit
DMA engine may not get a chance to service some Isochronous IN endpoints on time.
This causes the device core to respond with zero-length packets to host.
This scenario is more likely with low AHB frequencies, and when the othernon-isochronous IN endpoints have large buffers allocated. This is because the TX DMA
controller services endpoints in a round-robin fashion, and gets out of the endpoint only
when the descriptor chain is empty, or the TXFIFO is full.
In certain cases, the TXFIFO for non-isochronous endpoints never becomes full, due todue to 2xmps of FIFO size, and slow AHB. The TX DMA is stuck with that endpoint as longthe host continues sending IN tokens for that endpoint.

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3.18.93.18.9.1

Application Bus Protocol (Slave-Only Mode)
Overview

The AMBA High-Performance Bus (AHB), defined by ARM, Ltd., is the application bus for the UDCAHB Subsystem.
This chapter describes possible scenarios on the AHB with the subsystem operating in Slave-Only mode.

3.18.9.2

IN Transaction: Slave-Only Mode

3.18.9.2.1

Basic IN Transaction

On the first IN token, the subsystem always responds to the USB host with a NAK, as it does not have data available in
the endpoint buffers. The subsystem then triggers an interrupt service routine (ISR), which fills the endpoint buffers.

3.18.9.2.2

IN Interrupt Service Routine

The IN interrupt service routine (ISR) is triggered on an IN interrupt. The subsystem sets an IN interrupt on thereception of an IN token from an IN endpoint only if the data buffers for that IN endpoint are empty.

3.18.9.2.3

IN Data Writes

The IN data is the transmission data for the subsystem. The AHB master writes the IN data to the IN endpoint buffers(FIFOs). Note that any transfer to an IN Data FIFO must be exactly 4 bytes; a transfer that is not 4 bytes can occur onlyat the end of the data packet.
If the AHB master tries to write data when the IN endpoint FIFO is full, the subsystem asserts a retry response on the
AHB. The application must choose the buffer sizes for IN endpoints so that the buffers can hold at least one maximum
packet size.

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3.18.9.3

OUT Transaction: Slave-Only Mode

3.18.9.3.1

Basic OUT Transaction

The subsystem accepts an OUT packet only if it has the space to take at least one packet. Each endpoint can be
programmed in the CSRs to have different maximum packet sizes. The subsystem responds with a NAK if it does nothave enough space to take a packet.

3.18.9.3.2

OUT Interrupt Service Routine

The subsystem generates an OUT interrupt when it accepts an OUT packet. The OUT ISR reads the packet from thememory-mapped RxFIFO.

3.18.9.3.3

OUT Data Reads

OUT data received from an OUT data packet resides in the memory-mapped RxFIFO. The application (AHB master)
can read the data from the RxFIFO as if it is reading from the memory. Note that the OUT data read from the FIFO
should always be 32 data bits. The only exception is at the end of the packet. If the packet is non-quadlet aligned, thelast bytes must be read by performing an incremental burst read of unspecified length with an HSIZE of 8.
When the AHB master reads more data than is available in the receive FIFO, the subsystem asserts an ERROR responseon the AHB.

3.18.9.3.4

UDC CSR Access

The UDC used in this subsystem has internal control and status registers independent of the subsystem’s CSR module.
These CSRs are memory-mapped, starting from the offset of 12’h500 to 12’h7fc, and can be accessed using 32-bit
accesses. Burst access is not allowed for CSR access. When the application is accessing the UDC register, a retry
response is returned if either the read or write access has not been performed inside the subsystem core.

3.18.9.3.5

Subsystem CSR AccessSubsystem CSRs can also be accessed similarly to the UDC CSRs.

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3.18.103.18.10.1

Application Bus Protocol (DMA Mode)
Overview

The AMBA High-Performance Bus (AHB), defined by ARM, Ltd., is the application bus for the UDCAHB Subsystem.
This chapter describes scenarios on the AHB with the subsystem operating in DMA mode.

3.18.10.2

IN Transaction: DMA Mode

3.18.10.2.1

Basic IN Transaction

The subsystem always responds to the USB host with a NAK on the first IN token, as it does not have data available in
the endpoint buffers. The subsystem then triggers an interrupt service routine (ISR) and sets the Poll Demand bit, andthe (Transmit) DMA transfers data from the system memory to the TxFIFOs. If the TxFIFO becomes full mid-transfer,the DMA engine stores the address of the next location and starts transferring as soon as the TxFIFO is empty.

3.18.10.2.2

Packet-Per-Buffer Mode

When the ISR receives a USB host IN token, it sets the Poll Demand bit. Once this bit is set, the DMA moves data fromsystem memory to the TxFIFO. In packet-per-buffer mode, the DMA can transfer data from non-contiguous address
locations (a true scatter-gather mechanism). The descriptor update and the transmission of an interrupt to the application
at the end of each packet transfer is shown.

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3.18.10.3

OUT Transaction: DMA Mode

3.18.10.3.1

Basic OUT Transaction

The subsystem accepts an OUT packet only if it has enough space in the RxFIFO to accommodate at least one packet.
Each endpoint can be programmed in the CSRs to have a different maximum packet size. The subsystem responds witha NAK if it does not have enough space to accommodate the whole packet.

3.18.10.3.2

Packet-Per-Buffer ModeIn packet-per-buffer mode, the DMA transfers data to non-contiguous address locations (a true scatter-gather
mechanism) in the system memory. As soon as it receives a packet from the USB host, the DMA moves the data fromthe RxFIFO to system memory. The descriptor update and the transmission of an interrupt to the application at the endof each packet transfer are shown.

3.18.10.3.3

Buffer Fill ModeIn buffer fill mode, the DMA transfers data to contiguous locations in the system memory from the RxFIFO.

3.18.10.3.4

Threshold Enable

When thresholding is enabled, the transfer starts early on the AHB. The number of quadlets (32-bit words) must be set
in the CSR before starting a transfer in threshold mode.

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3.18.113.18.11.1

Software Implementation Guidelines
Slave-Only Mode

This section describes proper software implementation for Slave-Only mode. It describes the basic test flow and theinterrupt service routine.

3.18.11.1.1

Test Flow

A basic test of the subsystem involves four steps:❖ Initialization❖ Configuration❖ USB traffic generation❖ Comparison of data transferred
During initialization, the test software must program the control and status registers inside both the UDC and the
UDC-AHB Subsystem. UDC Endpoint n registers must be programmed as described in either the USB 2.0 Device
Controller-VCI

Databook or the USB 1.1 Device Controller (UDCVCI) Databook. The UDC-AHB Subsystem’s

device registers and endpoint registers must also be programmed as described below.
The Device Configuration register must be programmed with the supported features of the device in mind. Specific bits
relevant to this task are described in 3.18.6, “Control and Status Registers.” If the Device Control register is to be tested
in Slave-Only mode, the Transmit DMA Enable and Receive DMA Enable bits must be off, and the Mode bit must be
set to 1’b0. The Device Interrupt Mask register and the Endpoint Interrupt Mask register may be set to 1 if the user
wants to mask out any interrupts; otherwise, they should also be reset to 0.
The appropriate endpoint-specific register set must be determined based on the active endpoint(s) to be used in the test.
The Endpoint Control register must be initialized with the correct endpoint type, while all other bits should be set tozero. The Endpoint Buffer Size register and Endpoint Maximum Packet Size register must both contain appropriate
values, as per the user configuration. Note that the Buffer Size register value is set in words (TxFIFO entries), while theMaximum Packet Size register is set in bytes.
After initialization is complete, the USB host must configure each subject endpoint by setting the device address, thenthat endpoint’s configuration, interface, and alternate setting. Configuration, interface, and alternate settings all default
to 0. Note also that Configuration 0 can only contain Interface 0 and Alternate Setting 0, and is used for the default
Endpoint 0.
USB traffic generation differs depending on the direction of transfer. In the case of IN direction transfers (transfers into
the USB host), the USB host sends an initial IN token. Since the software has not filled the transfer FIFO with any data,
the device returns a NAK response and sets an interrupt, at which point the interrupt service routine (ISR) begins to fill
the TxFIFO with the data to be transferred. When the TxFIFO is filled, additional IN tokens return ACK, and thesubsystem transfers the data from the TxFIFO to the USB host. (The ISR process is described in detail in 3.18.11.2.3.)
The test software should store the data transferred in a local buffer so that at the end of each transaction, it can compare
the contents of the local buffer with the data received by the USB host.
In OUT direction transfers (transfers from the USB host to the device), the USB host sends an OUT token and receives－1205/1293－

CXD5602 User Manualan ACK response from the device as long as there is room inside the receive FIFO (RxFIFO). Data must be loaded into
the USB host’s Transmit buffer before sending an OUT token.
It is important to note that there are separate RxFIFOs for data and addressing, and that if either of these is full, thedevice responds with a NAK and no data is transferred. For the remainder of this chapter, RxFIFO is used generically torefer to the Data RxFIFO. In high-speed operation, if there is no room in the RxFIFO for two maximum-sized packets,then the UDC returns a NYET response, but the data is still transferred to the RxFIFO. Once the data is transferred to
the RxFIFO, the subsystem sets an interrupt and the application reads the data from the RxFIFO as described in
3.18.11.1.2, “Interrupt Service Routine.”
The test software should store the data transferred in a local buffer so that at the end of the transaction, it can compare
the contents of the local buffer with the data transmitted by the USB host.

3.18.11.1.2

Interrupt Service Routine

The UDC-AHB Subsystem employs two different types of interrupt: device and endpoint. Device interrupts notify thesubsystem when one of five system-level interrupt conditions occur on the USB. As indicated in Table USB-893 theseare:❖ Set Configuration (SC)❖ Set Interface (SI)❖ USB Reset (UR)❖ USB Suspend (US)❖ Start of Frame token
Endpoint interrupts are used to control endpoint traffic. These interrupts are identifiable by endpoint and direction, witha maximum of 32 separate interrupts (16 IN, 16 OUT endpoints). Device interrupts must take precedence over endpointinterrupts. When it receives an interrupt, the ISR must check the Device Interrupt register to determine whether any
Device Interrupt register bits are set. If no bits are set, the ISR must check the Endpoint Interrupt register to determine
which endpoint generated the interrupt. If a device interrupt is set, the software must clear it by writing 1’b1 to theregister bit to be cleared. On receiving the SOF interrupt, the application must set up DMA descriptors forisochronous-IN endpoints. This is described 3.18.11.2, “DMA Mode.” The ISR is divided into two endpoint interrupt
sections, one each for IN and OUT endpoints. The subsystem only sends an interrupt in the IN direction if the USB hostsends it an IN token when the TxFIFO does not have data available. Upon checking the Endpoint Interrupt register forthe proper endpoint, the ISR must clear the interrupt by writing a 1’b1 to the correct Endpoint Interrupt register bit. The
ISR must then read the IN field of the Endpoint Status register and check that register to confirm that an IN token has
been received. The ISR must clear the IN token bit after it has been read by writing a 1’b1.
To finish, the ISR must write the data into the TxFIFO of the active endpoint. The mapping address can be one of theoffset addresses within the TxFIFO depth. In order to confirm that the data has been successfully transferred to the
TxFIFO, the software must perform a dummy write to address offset (12’h01C + [endpoint number x 12’h020]) to end
the data transfer.
In the OUT direction, the subsystem generates an interrupt after the data from the USB host has been placed in the
RxFIFO. Upon checking the Endpoint Interrupt register for the proper endpoint, the ISR must clear the interrupt by
writing a 1’b1 to the correct bit of the Endpoint Interrupt register. It must then read the Endpoint Status register and－1206/1293－

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check the 2-bit OUT field.
If the OUT field shows SETUP data was received, then the ISR reads the 8 bytes of SETUP data from the RxFIFO.
After it finishes reading, the software must reset the NAK bit in the Endpoint Control register, because the NAK bit isautomatically set after a SETUP transfer. If the software does not reset this bit, all subsequent transactions involving
this particular endpoint receive a NAK response.
If the OUT field shows non-SETUP data was received, then the ISR reads the data from the RxFIFO. The RxFIFO ismapped to a 32-bit-wide RAM address. The mapping address can be one of the offset addresses within the RxFIFO
depth. The size of the received packet can be determined by reading the Endpoint Status register’s RxPktSize field.
When reading data from the RxFIFO, the software must only read one packet at the time.
After the ISR reads the OUT field of the Endpoint Status register, it must clear the register by writing the same values to
the OUT field.
For zero-length OUT data, the application must perform a dummy read from address offset (12’h21C + [endpoint
number x 12’h020]). A zero-length packet can be determined by reading the Endpoint Status register’s “RxPktSize”
field.

3.18.11.2

DMA ModeThis section describes how software should be implemented in DMA mode. It describes:❖ How a test should be written❖ How to create a descriptor chain❖ How to write the interrupt service routine❖ Which modes of operation are available❖ How to decode and service error conditions

3.18.11.2.1

Test Flow

The test flow for a DMA mode test is similar to that of a test run in Slave-Only mode. During the initialization phase,
however, the Device Control register’s Receive DMA (RDMA) Enable and/or Transfer DMA (TDMA) Enable bits
must be set, as well as the Mode bit, indicating DMA mode. Additionally, the Threshold Enable, Burst Enable,
Threshold Length, and Burst Length fields may be set as required to meet the test’s objectives. Note that a
DMA-configured core can still use the Slave-Only path by programming the Device Control register accordingly, but a
Slave-Only-configured core is only capable of using the Slave-Only path. A DMA test must also set up necessary
descriptor chains.
A descriptor chain is required for DMA mode operation. The test software must program the Endpoint Data Descriptor
Pointer register with the address of the first descriptor in the chain. For SETUP packets, software must program the
Endpoint SETUP Buffer Pointer register instead.
The software must set the last bit in the descriptor status quadlet if that descriptor is the last one of the chain. Also, toprevent the DMA from accidentally overwriting data, the software must initially set the buffer status field of each
descriptor to “Host Busy.” After the complete descriptor chain is created, the software must set the buffer status field to“Host Ready.” The DMA engine only processes a descriptor if its field is set to “Host Ready.” If the buffer status field
is not set to “Host Ready,” the DMA engine skips the descriptor and the subsystem sets a buffer not available interrupt.

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Descriptors for isochronous-IN endpoints must also be programmed with a frame field. The frame number programmedin the frame field specifies the frame number on which that descriptor is to be transferred. If the frame field contains thevalue of 2, then the DMA waits until frame 1 to put the data pointed to by the descriptor into the TxFIFO, making thedata ready to be transferred on frame 2. If for some reason, the data isn’t put into the TxFIFO by frame 1, it can still be
put in on frame 2. After that, the descriptor is skipped, because it represents stale data. For isochronous-IN DMA
transfers, the TxFIFO implements double buffering in such a way that the next two frames of data are both written to
the TxFIFO. The software must program isochronous-IN endpoint TxFIFOs to be twice the maximum packet size.
For all IN endpoint tests, the software must set the Poll Demand bit in the Endpoint Control register to 1 in order toactivate the DMA. The DMA automatically clears this bit upon completing the descriptor chain. If multiple endpoints
have their Poll Demand bits set, they are served in a round-robin fashion.

3.18.11.2.2

Modes of Operation

The DMA has several modes of operation. There are two modes of operation in the IN direction: Packet- Per-BufferWith Descriptor Update (PPBDU), and Packet-Per-Buffer Without Descriptor Update (PPDNDU). Bothpacket-per-buffer modes are implemented such that only one maximum-sized packet is used per descriptor. There canbe a chain of descriptors for a transfer of several packets, but only the last one can be a short packet (a packet of lessthan the maximum packet size).
In PPBDU mode, each descriptor’s status is updated after completion of the transfer of the packet. In PPBNDU mode,
only the last descriptor in the chain’s status is updated. In descriptor update mode, the descriptor’s Tx Bytes fieldcontains the size of the packet transferred.
Thus, in PPBDU mode, the software can determine the status of each transferred packet, but in PPBNDU mode, only
the status of the entire chain can be determined. Updating each individual descriptor in PPBDU mode requires
additional cycles.
In the OUT direction, the DMA can operate in buffer fill mode in addition to the PPBDU and PPBNDU modes. Buffer
fill mode contains only one descriptor, which indicates a large buffer of many packets. A short or zero-length packet
signifies the last packet for the transfer. The subsystem generates an interrupt only at the end of the descriptor chain,
when it receives a short or zero-length packet. In PPBNDU mode, the subsystem generates an interrupt at the end of
descriptor chain, but for PPBDU mode, the subsystem generates an interrupt for each descriptor in the chain. The DMA
engine disables itself when the subsystem generates an interrupt, so that the application has ample time to collect thedata.
An advantage of packet-per-buffer mode over buffer fill mode is that the data buffers used may be scattered throughout
the system memory in maximum-packet-sized chunks. In buffer fill mode, the entire data buffer must be in contiguous
memory locations, which means there must be a large contiguous chunk of memory free. However, buffer fill mode
requires only one descriptor and is faster, as it need not fetch and process a descriptor for each transmitted packet.
These modes of operation are programmed through the Device Control register (see Table USB-887).

3.18.11.2.3

Interrupt Service Routine

The interrupt service routine for DMA mode is more complicated than that of Slave-Only mode. Device interrupts are
the same as for Slave-Only mode. An interrupt can be generated normally or by a error condition.

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Interrupt Service: Normal Conditions
When the ISR receives an IN interrupt, it must clear the interrupt and read the IN field of the Endpoint Status register toconfirm the reception of an IN token. The ISR must clear the IN field after the application reads it, by writing a 1’b1.
If a descriptor chain is not already set up, the software must set up the descriptor chain according to the above protocol,then set the Poll Demand bit to activate the DMA. Once the Poll Demand bit is set, the application’s role is finished,
and the DMA transfers the data from system memory to the TxFIFO.
When the ISR receives an OUT interrupt, it must clear the interrupt and read the Endpoint Status register’s OUT field todifferentiate regular data from SETUP data. The ISR clears the OUT field by writing 2’b11 to it.
In the case of OUT endpoints, the descriptor chain is already set up, and the DMA has already transferred the data tosystem memory. The DMA is also disabled to give enough time for the software to service the data. The ISR’s role inthis case is to read the data from system memory.
When it receives SETUP data, the ISR must determine the address in the system memory indicated by the SETUP
descriptor by reading the Endpoint SETUP Buffer Pointer register. Upon determining the system memory address, theISR can read the 8 bytes of SETUP data from the descriptor, and the ISR is finished. At this point, the ISR must either
create a new descriptor or reinitialize the existing descriptor by writing host ready to each descriptor’s buffer status field.
Then, the ISR must set the RDMA Enable bit in the Device Control register, re-enabling the DMA. The software mustalso clear the SetNak bit in the Endpoint Control register, because that bit is set by the device hardware after a SETUP
is received. Otherwise, all further transactions receive a NAK response.
If it receives non-SETUP data, the ISR must determine the address in the system memory indicated by the descriptor byreading the Endpoint Data Descriptor Pointer register. What happens next depends on the mode of operation the DMA
is in.
If the DMA is in Buffer Fill mode, the interrupt only arrives when the DMA receives a short- or zerolength packet,
signifying the end of the USB transfer. The application must read the Rx Bytes field to determine how much data toread and then read that amount of data from system memory. Note that the buffer status field of the descriptor must be
set to DMA done or the DMA continues to use the descriptor chain. Upon completion of processing the data in systemmemory, the ISR must create or reinitialize a descriptor chain and re-enable the DMA.
If the DMA is in Packet-Per-Buffer Without Descriptor Update (PPBNDU) mode, the ISR acts similarly to the buffer
fill mode, except it must traverse the entire descriptor chain in order to read all of the data transferred to system memory.
It does this by reading the next pointer of each descriptor until it reaches the last one (the last bit is set in the descriptor
status quadlet). In this mode, the last descriptor must have its buffer status field set to DMA done, and to collect the
total number of bytes transferred, the application must read the Rx Bytes field of the last descriptor as well. Eachdescriptor other than the last one is guaranteed to contain one maximum packet size, but the last one is always a short orzero-length packet.

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If the DMA is in Packet-Per-Buffer With Descriptor Update (PPBDU) mode, the ISR must respond to the addedcomplication of an interrupt generated each time a packet is transferred. The next pointer address of each descriptor
must thus be stored so that on each successive interrupt, the ISR can determine where to go to read the data transferred.
The buffer status field of each descriptor must be set to DMA done or the DMA continues to use the descriptor. EachRx Bytes field contains the amount of data transferred for that descriptor, which must equal the maximum packet size
unless there is a short or zero-length packet. On the last descriptor of the chain, the application must create orreinitialize a descriptor chain for use with the next transfer. The application must re-enable the DMA after the ISR
processes each descriptor.

Interrupt Service: Error Conditions
Error conditions can also generate interrupts. The following describes what is required of the ISR to service an error
interrupt.
After checking the Endpoint Interrupt register to determine the endpoint number that generated the interrupt, thesoftware’s ISR must check the Endpoint Status register to see if any error bits are set before checking the IN and OUT
fields as described in “Interrupt Service: Normal Conditions.” This is because errors have priority.
Two error bits, Host Error (HE) and Buffer Not Available (BNA), may be set. The subsystem sets the HE bit if an error
occurs on the AHB during DMA transfer, and sets the BNA bit if the descriptor is not ready when the DMA attempts toaccess it.
The HE bit can be set in each of the four stages of the DMA transfer: descriptor fetch, descriptor update after fetch, datatransfer, and descriptor update after data transfer. If there is an AHB error during descriptor fetch, the subsystem treats
the error as fatal, because the accuracy of the data in the descriptor is not guaranteed, and the DMA stops descriptor
chain processing. The subsystem sets an interrupt with the HE bit set in the Endpoint Status register.
If there is an AHB error during data transfer, the DMA by default treats it as non-fatal and moves on to the next
descriptor in the chain. However, if the error severity is set to Fatal, the DMA stops processing the chain. For non-fatal
errors, the Receive status is set to BUFERR, and an interrupt is set with the HE bit set in the Endpoint Status register.
The BNA bit can be set in the Endpoint Status register to indicate that the descriptor was not ready at the time the DMA
tried to access it. When the BNA bit is thus set, the Receive status is also set to DESERR.The DMA continues to thenext descriptor in the chain.
The application must reset the error bits (either HE or BNA) after reading the Endpoint Status register by writing a 1’b1
to the appropriate field.

－1210/1293－

CXD5602 User Manual

3.18.123.18.12.1

USB Programming
Overview

This appendix provides flow guidelines for various programming operations.

3.18.12.1.1

Device Initialization

This section describes the tasks required to initialize the device.

3.18.12.1.2

Programming Registers to Initialize the UDC11-/UDC20-AHB Subsystem

To initialize the UDC11-/UDC20-AHB Subsystem, application software must program the following registers:❖ Device Configuration register❖ Device Control register❖ Endpoint Control registers for Logical Endpoint 0, 1, 2, and so on❖ Endpoint Buffer Size registers for Logical Endpoint 0, 1, 2, and so on❖ Endpoint Max Packet Size registers for Logical Endpoint 0, 1, 2, and so on❖ Endpoint 0 Setup Buffer Pointer register❖ UDC11/UDC20 registers for Physical Endpoint 1, 2, and so on

3.18.12.1.3

Checking for a USB Reset Interrupt and the Enumerated Speed

After attaching the UDC11-/UDC20-AHB Subsystem to the USB host, application software can check for a USB reset
interrupt from the Device Interrupt register and the enumerated speed from the Device Status register.

3.18.12.1.4

Operating the UDC11-/UDC20-AHB Subsystem in DMA Mode

To operate the UDC11-/UDC20-AHB Subsystem in DMA mode, application software must do the following:
1. During device initialization, as described in 3.18.12.1.2, set the following Device Control register bits:✦ MODE (indicate DMA mode)✦ BREN (Burst Enable)✦ BRLEN (Burst Length)✦ DU (Descriptor Update)✦ If Threshold mode is supported for OUT data: THLEN (Threshold Enable) and THLEN(Threshold Length)
2. Set up the required descriptor chains for both IN and OUT packets by programming the Endpoint Data Descriptor
Pointer register with the address of the first descriptor in the chain. If that descriptor is also the last one of the chain,
set the last bit in the descriptor status quadlet.
3. To prevent the DMA from accidentally overwriting data, set the Buffer Status field of each descriptor to “HostBusy.”
After the complete descriptor chain is created, the software must set the Buffer Status field to “Host Ready.”
4. Set the P (Poll Demand) bit in the Endpoint Control register, then enable the transmit DMA and receive DMA by－1211/1293－

CXD5602 User Manual

setting the TDE and RDE bits, respectively, in the Device Control register.
The following flow is for dynamic UDC11/UDC20 registers programming. (The CSR_PRG bit in the Device
Configuration register is set during device initialization.)
Note

Step numbers are provided for reference purpose only.

USB Host
1.

Set_Interface or
Set_Configuration

2.

Subsystem Core

Application Software

→
←

3.

ACK
Sets device SI interrupt

4. IN Token

→

5.

←

6. IN Token

→

7.

←

8. ACK→→

NAK

・Status = Interface
or
configuration is switched・Programs the UDC, Buffer
Size, and Max Packet Sizeregisters

・Sets CSR_DONE bit
・Clears Device SI interrupt←

Zero-length packaet－1212/1293－

CXD5602 User Manual

3.18.12.2

Device Disconnection and Reconnection

This section describes the tasks required to physically disconnect and then reconnect the device for both the single
RxFIFO and multiple RxFIFO options.

3.18.12.2.1

Disconnect and Reconnect Flow – Single RxFIFO Implementation

The following flow is for physically disconnecting and then reconnecting the device, if the single RxFIFO option is
implemented.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

1.

Device is disconnected

2.

→

Flush the data inside the
TxFIFOs

3.

←
←

4.

Rx DMA writes OUT
Data to system memory
Device is reconnected

5.
6.
7.

Application Software→←
USB reset→－1213/1293－

Set the F bit to flush the stale
data for all IN endpoints.
Check RxFIFO EMPTY bit
before setting the RDE bit toflush the garbage data for all
OUT endpoints.
・If RxFIFO EMPTY = 1, does
not need to set the RDE bit
・If RxFIFO EMPTY = 0 and
RRDY bit = 0, prepares OUT
dummy descriptors and thensets the RDE bit.

Program all CSRs the same as
POR (power on reset)

CXD5602 User Manual

3.18.12.2.2

Disconnect and Reconnect Flow – Multiple RxFIFO Implementation

The following flow is for disconnecting and then reconnecting the device physically, if the multiple RxFIFO
option is implemented.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

1.

Device is disconnected

2.

Flush the data inside the
TxFIFOs

3.

←
←

4.

Rx DMA writes OUT
Data to system memory
Device is reconnected

5.
6.
7.

Application Software→←
USB reset→－1214/1293－

Set the F bit to flush the stale
data for all IN endpoints.
Check RxFIFO EMPTY bit
before setting the RRDY bit toflush the garbage data for all
OUT endpoints.
・If RxFIFO EMPTY = 1, does
not need to set the RRDY bit
・If RxFIFO EMPTY = 0 and
RRDY bit = 0, prepares OUT
dummy descriptors and thensets the RRDY bit.

Program all CSRs the same as
POR (power on reset)

CXD5602 User Manual

3.18.12.3

Detecting and Clearing the NAK Bit of a Stalled Endpoint

3.18.12.3.1

Clearing NAK for Stalled IN Endpoint

The following flow is for detecting and clearing the NAK bit of a stalled IN endpoint.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software

1.

2.

・Sets the S bit
・Polls the NAK bit
or・Sets the S bit and CNAK bit(if the NAK bit is set)
・Polls the NAK bit
IN Token

→

3.

←

STALL

4.

→

Clears S bit and sets
NAK bit5.

IN Token

→

6.
7.

STALL
Clear_Feature

8.
9.

←
IN Token

10.
11.

→

→
←

ACK

ACK
Data (available in
TxFIFO)→－1215/1293－→

Clears the NAK bit any timeafter detecting that the NAK bit
is setCXD5602 User Manual

3.18.12.3.2

Clearing NAK for Stalled OUT Endpoint

The following flow is for detecting and clearing the NAK bit of a stalled OUT endpoint.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software

1.

2.

・Sets the S bit
・Polls the NAK bit
or・Sets the S bit and CNAK bit(if the NAK bit is set)
・Polls the NAK bit
OUT Token

3.

→
←

4.

5.

Clears S bit and sets
NAK bitOUT Token

→

6.
7.

STALL

STALL
Clear_Feature

8.

→
←

ACK

9.

OUT Token→

10.

OUT Data→

Store in RxFIFO

←

ACK

11.

－1216/1293－→

Clears the NAK bit any timeafter detecting that the NAK bit
is setCXD5602 User Manual

3.18.12.4

Operational Models: DMA Mode

3.18.12.4.1

Control IN (Get_Descriptor) Transfer Flow

Control IN with Valid Data
The following flow is for a control IN (Get_Descriptor) transfer with valid Setup data.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software

1.

Prepares Setup descriptor
Enables Rx DMA

2.

SETUP

→

3.

Data

→

4.

←

5.

ACK
・Sets EP IN NAK・Sets EP OUT NAK・DMA writes Setup
data to systemmemory・Sets EP OUT
interrupt

6.

IN Token

7.

→
←

NAK

→

Clears EP OUT interrupt Status= Received Setup Data
Decodes Setup data => IN data←

Clears IN NAK bit→

8.

・Sets up descriptor chain

9.

・DMA reads IN datafrom system memory
・Sets EP IN interrupt forTransmit DMA
complete (TDC bit)←・Sets Poll Demand bit after→

・Clears Transmit DMA
interrupt
・Clears TDC bit

10.

IN Token

11.

→
←

12.

ACK

→

13.

OUT Token

→

14.

Data

→

Data

←

－1217/1293－

Clears OUT NAK bit

CXD5602 User Manual

USB Host
15.

Subsystem Core←

Application Software

NAK

16.

←

17.

OUT Token

→

18.

Data

→

19.

←

20.

Sets up OUT descriptor for
statusEnables Rx DMA

ACK・DMA writes zero
length packet tosystem memory
・Sets EP OUT
interrupt→

・Clears EP OUT interrupt
Status = Received Data
・Checks status data

Note: Application software receives three interrupts: Control EP Received Setup Data, Transmit DMA
Complete, and Status EP OUT data. For Packet-Per-Buffer mode (with or without descriptor update) and
Buffer Fill mode flow diagrams, see 3.18.8, “DMA Operation.”
Note

When the enhancement “Enabling this option allows the CNAK bit to be set, that isclearing NAK, even under the following conditions:” in Table USB-878 is enabled, theapplication must ensure the RXFIFO is empty before clearing the NAK bit of the EP0 IN
endpoint. In the event of back-to-back SETUP packets, the application must process thesecond SETUP, ignoring the first SETUP.

－1218/1293－

CXD5602 User ManualControl IN with Invalid Data
The following flow is for a control IN (Get_Descriptor) transfer with invalid Setup data.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software

1.

・Prepares Setup descriptor
・Enables Rx DMA

2.

SETUP

→

3.

Data

→

4.

←

5.

ACK
・Sets EP IN NAK・Sets EP OUT NAK・DMA writes Setup
data to systemmemory・Sets EP OUTInterrupt

6.

IN Token

→

7.

Data

←

NAK

→

Clears EP OUT interrupt
Status = Received Setup Data→

Decodes Setup Data => IN
data←

・Sets IN STALL
・Sets OUT STALL
・Prepares Setup descriptor
・Enables Rx DMA

8.

IN Token

9.
10.

→
←

SETUP

STALL

→

11.

－1219/1293－

CXD5602 User Manual

3.18.12.4.2

Control OUT (Set_Descriptor) Transfer Flow

Control OUT with Valid Data
The following flow is for a control OUT (Set_Descriptor) transfer with valid Setup data.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software

1.

・Prepares Setup descriptor
・Enables Rx DMA

2.

SETUP

→

3.

Data

→

4.

←

5.

ACK
・Sets EP IN NAK・Sets EP OUT NAK・DMA writes Setup
data to systemmemory・Sets EP OUTInterrupt

6.

OUT Token

→

7.

Data

→

8.

←

→

Clears EP OUT interrupt
Status = Received Setup Data
Decodes Setup Data => OUT
data

NAK

←

・Clears OUT NAK bit
・Sets up descriptor chain
・Enables Rx DMA

9.

OUT Token

→

10.

Data

→

11.

←

12.

13.

ACK
・DMA writes OUT data
to system memory
・Sets EP OUT
interrupt

IN Token

14.

←

NAK

Decodes received data←

IN Token

Clears EP OUT interrupt
Status = Received Data

→

15.
16.

→

→

－1220/1293－

Clears IN NAK bit

CXD5602 User Manual

USB Host
17.
18.

Subsystem Core←

ACK

Application Software

Zero-length packet→

Note: Application software receives two interrupts: Control EP Received Setup Data and Control EP OUT
Data Received. For Packet-Per-Buffer mode (with or without descriptor update) and Buffer Fill mode flow
diagrams, see 3.18.8, “DMA Operation.”Control OUT with Invalid Data
The following flow is for a control OUT (Set_Descriptor) transfer with invalid Setup data.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software

1.

・Prepares Setup descriptor
・Enables Rx DMA

2.

SETUP

→

3.

Data

→
←

4.
5.

ACK
・Sets EP IN NAK・Sets EP OUT NAK・DMA writes Setup
data to systemmemory・Sets EP OUTInterrupt

6.

OUT Token

→

7.

Data

→
←

8.

→

Clears EP OUT interrupt
Status = Received Setup Data
Decodes Setup Data => OUT
data

←

NAK

・Sets IN Stall bit
・Sets OUT Stall bit
・Prepares Setup descriptor
・Enables Rx DMA

9.

OUT Token

→

10.

Data

→
←

11.
12.

SETUP

STALL

→

13.

－1221/1293－

CXD5602 User Manual

3.18.12.4.3

Bulk/Interrupt IN Transfer Flow

The following flow is for a bulk/interrupt IN transfer.
Note

Step numbers are provided for reference purpose only.

USB Host
1.

IN Token

Subsystem Core

Application Software
Prepares isochronous IN
descriptor

→

2.

←

NAK

3.

→

Sets EP IN interrupt

→

4.

←

DMA reads IN data fromsystem memory
If Last bit is set, sets EP
IN interrupt for Transmit
DMA Completion (TDC bit)

←

5.
6.

IN Token

7.
8.

→
←

ACK

→

・Clears EP IN interrupt
Status = IN token bit
・Clears IN token bit
Sets Poll Demand bit
・Clears Transmit DMA
interrupt
・Clears TDC bit

Data

→

Note: Application software must service two interrupts (IN token and Transmit DMA complete). For
Packet-Per- Buffer mode (with or without descriptor update) and Buffer Fill mode flow diagrams, see 3.18.8,“DMA Operation.”－1222/1293－

CXD5602 User Manual

3.18.12.4.4

Isochronous IN Transfer Flow

The following flow is for an isochronous IN transfer.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core・Prepares isochronous IN

1.

descriptor
DMA reads IN data fromsystem memory forcurrent and next frame/µframe2.

3.

Application Software

IN Token→←

4.

・Sets Poll Demand bit

Data

5.
6.
7.

IN Token

→
←

Data

Note: Application software must service only IN token interrupt if there is no data available inside the transmit
FIFO during the time the USB host requests IN data. In this case, system core sends zero-length data packet.
For Packet-Per-Buffer mode (with or without descriptor update) and Buffer Fill mode flow diagrams, see
3.18.8, “DMA Operation.”－1223/1293－

CXD5602 User Manual

3.18.12.4.5

Bulk/Interrupt IN Transfer Flow

The following flow is for a bulk/interrupt IN transfer.
Note

Step numbers are provided for reference purpose only.

USB Host
1.

IN Token

Subsystem Core

Application Software
Prepares isochronous IN
descriptor

→

2.

←

NAK

3.

→

Sets EP IN interrupt

→

4.

←

DMA reads IN data fromsystem memory
If Last bit is set, sets EP
IN interrupt for Transmit
DMA Completion (TDC bit)

←

5.
6.

IN Token

7.
8.

→
←

ACK

→

・Clears EP IN interrupt
Status = IN token bit
・Clears IN token bit
Sets Poll Demand bit
・Clears Transmit DMA
interrupt
・Clears TDC bit

Data

→

Note: Application software must service two interrupts (IN token and Transmit DMA complete). For
Packet-Per- Buffer mode (with or without descriptor update) and Buffer Fill mode flow diagrams, see 3.18.8,“DMA Operation.”－1224/1293－

CXD5602 User Manual

3.18.12.4.6

Isochronous IN Transfer Flow

The following flow is for an isochronous IN transfer.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core・Prepares isochronous IN

1.

descriptor
DMA reads IN data fromsystem memory forcurrent and next frame/µframe2.

3.

Application Software

IN Token→←

4.

・Sets Poll Demand bit

Data

5.
6.
7.

IN Token

→
←

Data

Note: Application software must service only IN token interrupt if there is no data available inside the transmit
FIFO during the time the USB host requests IN data. In this case, system core sends zero-length data packet.
For Packet-Per-Buffer mode (with or without descriptor update) and Buffer Fill mode flow diagrams, see
3.18.8, “DMA Operation.”－1225/1293－

CXD5602 User Manual

3.18.12.4.7

Bulk/Interrupt OUT Transfer Flow

The following flow is for a bulk/interrupt OUT transfer.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software
Prepares bulk/interrupt OUT
descriptor

1.
2.

←

3.

OUT Token

→

4.

Data

→

5.

←

ACK
• DMA writes OUT data
to system memory
Descriptor Update ==Trueor
End of Descriptor Chain(short packed) == True
• Disables Rx DMA• Sets EP OUTInterrupt

6.

→
7.
8.

Enables Rx DMA

OUT Token

Status = Received Data→←

Clears EP OUT interrupt

NAK (RxFIFO is full)

Decodes data

9.

Reinitializes descriptor chain←

10.

Enables Rx DMA

Note: Application software must service only one interrupt (EP OUT interrupt):-During each descriptor for Packet-Per-Buffer mode with descriptor update-During the last descriptor of a chain for Packet-Per-Buffer mode without descriptor update-For Buffer Fill mode
For Packet-Per-Buffer mode with or without descriptor update and Buffer Fill mode flow diagrams,
see 3.18.8, “DMA Operation.”－1226/1293－

CXD5602 User Manual

3.18.12.4.8

Isochronous OUT Transfer Flow

The following flow is for an isochronous OUT transfer.
Note

Step numbers are provided for reference purpose only.

USB Host

Subsystem Core

Application Software
Prepares isochronous OUT

1.

descriptor

2.
3.

OUT Token

→

4.

Data

→

5.

←

Enables Rx DMA→• Clears EP OUT interrupt
Status = Received Data
• Checks ISO OUT PID(UDC20-AHB only) andFrame number in Endpoint
Buffer Size IN/Receive
Packet Frame Number OUT
register• Decodes data
• Reinitializes descriptor
chain• DMA writes OUT data
to system memory• Descriptor Update ==Trueor
End of Descriptor
Chain (short packaet)== True• Disables Rx DMA

6.

Sets EP OUT Interrupt

Note: Application software must service only one interrupt (EP OUT interrupt):-During each descriptor for Packet-Per-Buffer mode with descriptor update-During the last descriptor of a chain for Packet-Per-Buffer mode without descriptor update-For Buffer Fill mode
For Packet-Per-Buffer mode with or without descriptor update and Buffer Fill mode flow diagrams,
see 3.18.8, “DMA Operation.”－1227/1293－

CXD5602 User Manual

3.18.12.5

Set/Clear Feature (EP HALT) Enhancement

3.18.12.5.1

Clear_Feature Command Handling with the Set/Clear Feature

The following flow is for Clear_Feature (EP HALT) Command Handling when the Set/Clear Feature (EP HALT)
Enhancement is Enabled.
1. After receiving the Clear Feature (EP Halt) command, the core sets the Received Clear Stall (RCS) bit in the
Endpoint Status Register of the endpoint number referenced in the command. Meanwhile, the core continues to send
NAK response to the USB host for the Status IN command.
2. The core also sets the Endpoint Interrupt for the corresponding endpoint referenced in the command, and generates
the interrupt.
3. Software services this interrupt and decides whether to continue the stall condition or clear the stall condition.
✦ To continue the stall condition, the software must set the S bit in the Endpoint Status register.
✦ To clear the stall condition and accept the packet, the software must set the CNAK bit to clear the NAK
condition.
After sending the STALL response,
4. The core clears the S bit.
5. The core sets the NAK bit.
6. The software acknowledges the clear stall command reception by clearing the RCS bit in the Endpoint Status register.
7. The core always sends a zero-length response for the Status IN command.
Three examples follow.

－1228/1293－

CXD5602 User Manual

3.18.12.5.2

Set/Clear Feature Flow Examples

Note

Step numbers in the following examples are provided for reference purposes only.

Case 1
USB Host

Subsystem Core

1.
2.

Application Software
Set the S bit

Bulk OUT/IN

3.

→
←

4.

STALL
• Clear S bit• Set NAK bit

5.

Bulk OUT/IN

6.
7.

→
←

Clear Stall Setup

8.

STALL

→
←

9.

ACK
Set Received Clear Stall(RCS) bit

10.
11.

Generate Interrupt
Clear Stall Status In

12.

→
←

NAK

• Set CNAK bit for theendpoint to clear NAK• Clear S bit• Clear RCS bit

13.

Clear Stall Status IN

14.
15.
16.

→
←

Bulk OUT/IN

Zero-length packet

→
←

ACK

－1229/1293－

CXD5602 User Manual

Case 2
USB Host

Subsystem Core

1.
2.

Application Software
Set the S bit

Bulk OUT/IN

3.

→
←

4.

STALL
• Clear S bit• Set NAK bit

5.

Bulk OUT/IN

6.
7.

→
←

Clear Stall Setup

8.

STALL

→
←

ACK

9.

Set Received Clear Stall(RCS) bit

10.

Generate Interrupt

11.

Clear Stall Status In

12.

→
←

NAK

• Set S bit for the endpoint• Clear RCS bit

13.

Clear Stall Status IN

14.
15.

←
Bulk OUT/IN

16.
17.

Bulk OUT/IN

20.

STALL response→←

Clear Stall Setup

Zero-length packet

→
←

18.
19.

→

STALL response

→
←

ACK

21.

Set Reserved Clear Stall(RCS) bit

22.

Generate interrupt

23.
24.

Clear Stall Status IN

→
←

NAK
• Set CNAK bit for theendpoint to clear NAK

25.

• Clear S bit• Clear RCS bit－1230/1293－

CXD5602 User Manual

USB Host
26.

Clear Stall Status IN

27.
28.

Subsystem Core→←

Bulk OUT/IN

29.

Application Software

Zero-length packet

→
←

ACK

Case 3
USB Host
1.

Set Stall Setup

Set Stall Status IN

4.

Clear Stall Setup→

Set the S bit

Zero-length packet

→
←

5.

ACK

→
←

3.

Application Software

→
←

1.
2.

Subsystem Core

6.

ACK
Set Reserved Clear Stall(RCS) bit

←

7.
8.

Clear Stall Status IN

9.

Generate interrupt

→
←

NAK

10.

• Set CNAK bit for theendpoint to clear NAK• Clear S bit• Clear RCS bit

11.

Clear Stall Status IN

←

12.
13.
14.

→

Bulk OUT/IN

Zero-length packet

→
←

ACK

In this example, the S bit is not cleared by the core because the Bulk OUT packet is not received for that endpoint. This is the reason
to clear the S bit before clearing the RCS bit.

－1231/1293－

CXD5602 User ManualNote:

The core automatically sends a STALL response for the Clear_Feature (EP HALT)
command (in the status IN phase) when Clear Feature request references a featurethat:♦cannot be cleared.
♦
does not exist.
♦
references an interface or endpoint that does not exist in the core.
The application need not do anything. An interrupt is not generated.

－1232/1293－

CXD5602 User Manual

3.18.13Multiple RxFIFO Controllers

3.18.13.1

Multiple Receive FIFO Controllers

Multiple Receive FIFO controllers can be implemented in the UDC-AHB Subsystem through the HW design. Multiple
Receive FIFO controllers are endpoint-specific blocks, and each OUT endpoint has an RxFIFO controller associatedwith it. Each endpoint’s RxFIFO controller comprises two individual FIFOs, one for data and another for addresses.
Each entry in the address FIFO component corresponds to an OUT packet received for that endpoint. The address FIFO
entry has a flag to differentiate regular data from the eight bytes of SETUP data. UTLI provides the data, along with thebyte-enables, end-of-packet flag and the current endpoint number. Each RxFIFO controller generates an address for its
RAM and maintains its read and write pointers. This address bounds a small address range within the RAM equal to the
FIFO size programmed into the CSRs for the endpoint. RAM address generated by RxFIFO controller is similar to the
TxFIFO controller. The Data FIFO is implemented as RAM whereas the Address FIFO is implemented with registers.
Multiple data packets for each OUT endpoint are supported. The number of packets the address FIFO can store isdetermined in the HW design. The maximum value, however, is limited to 4 and the depth must be a power of 2. The
address FIFO depth is same for each address FIFO.

3.18.13.2

OUT Transfer Operation in DMA Mode

When the UDC receives an OUT token, it checks the corresponding Receive Data FIFO endpoint for available space. If
space is available, the packet is accepted and the data is written to the FIFO. If space is not available, the UDC sends
the USB host a NAK handshake. If the packet is received successfully or the threshold amount of data is available in the
FIFO, the DMA checks the received endpoint’s Receive Ready bit in the Endpoint Control register. If the application
has set the Receive Ready bit to 1’b1, the DMA transfers the data from the FIFO to the system memory. Aftertransmitting the packet, if the Descriptor Update bit is set to 1’b1, the Receive Ready bit is cleared to 1’b0. For the
DMA to transmit data for a subsequent packet, the application must set the Receive Ready bit again for the next
descriptor after serving the previous descriptor’s interrupt. If the Descriptor Update bit is not set to 1’b1, the Receive
Ready bit is cleared only at the end of payload (when either a short packet or zero-length packet is received, or when thelast bit of the descriptor’s status quadlet is set). Once the data is transferred, the subsystem updates the status of thereceived data to the buffer’s status quadlet. When the DMA is processing one endpoint’s packet, other endpoints’ OUT
data packets can be received and stored in the corresponding Receive Data FIFO. In this case, more than one packet
must be transferred (if the Receive Ready bit is set by the application for those endpoints) to the system memory.
Round-robin prioritization determines which endpoint’s packet is transferred next. SETUP data is transferred to a
16-byte SETUP Data memory structure. The pointer for this DMA descriptor is in the Endpoint SETUP Buffer Pointerregister (at offset 12’h210 + (endpoint number * 12’h020)). This DMA descriptor is updated with the 8 bytes of the
SETUP command received from the USB host. OUT data is transferred to the buffers indicated by the DMA descriptor.
The pointer for these descriptors is programmed in the CSRs. The transaction flow for all OUT endpoints is similar, theonly difference being that isochronous (ISO-OUT) data is tagged with the frame number in which the packet is received.
Figure USB-59 shows OUT transaction flow in DMA mode without thresholding enabled. In this case, the DMA
transfer starts only after the entire packet is received. Figure USB-60 shows OUT transaction flow with thresholding－1233/1293－

CXD5602 User Manualenabled, in which case, DMA transfer can start as soon as the threshold amount of data received from the USB host.

3.18.13.3

OUT Transfer Operation in Slave-Only Mode

When the subsystem receives OUT data from the USB host, it transfers the data to the endpoint’s Receive FIFO if space
is available for a packet. If space is not available, the UDC sends the USB host a NAK handshake. Once the packet istransferred to the Receive FIFO, the subsystem sends the application an interrupt for the received packet. The
application reads the addressed endpoint’s interrupt and Status registers and determines the number of bytes received in
the packet. The application must read all the data received for that packet: it cannot read partial data and return to readthe remaining data of the same packet after reading some other OUT endpoint’s Receive FIFO. If the application tries toread more than the byte count received, an AHB error response is provided. Note that the application reads from theaddress to which the endpoint’s Receive FIFO is mapped. Figure USB-61 shows the OUT transaction flow in
Slave-Only mode.

－1234/1293－

CXD5602 User Manual

Figure USB-59 OUT Transaction Flow in DMA Mode Without Thresholding Enabled－1235/1293－

CXD5602 User Manual

Figure USB-60 OUT Transaction Flow in DMA Mode With Thresholding Enabled－1236/1293－

CXD5602 User Manual

Figure USB-61 OUT Transaction Flow in Slave-Only Mode

－1237/1293－

CXD5602 User Manual

3.19 CIS I/F

8-bit parallel Camera Interface input

8-bit ITU-R BT 601 / 656 Mode

Compressed data like JPEG support

Supports Y/C, JPEG and JPEG+Y/C Interleave formats

Programmable polarity of video sync signal

Capture frame control supportInput image size

JPEG Only: up to 5M pixels



Y/C Only: up to 480x360



JPEG+Y/C: 2M + WQVGA (JPEG High Quality mode)
5M + WQVGA (JPEG Normal Quality mode)

Parallel Input rate: up to 54MHz

3.20 2D Graphics


2D Graphics accelerator


Bit Block Transfer



RotatorSupported image format: YCbCr422, RGB565

Supported rotate degree: 0, 90, 180, 270 degrees

Color space Conversion (YCbCr422<->RGB565)



3-operand raster operation (ROP3)



Alpha blendingScalingHorizontal direction: x1/64 to x64, Vertical direction: x1/64 to x64
Maximum source input 2880x2160, maximum destination output 768x1024



YCbCr 422 16 bpp format－1238/1293－

CXD5602 User Manual

3.21 ADC
3.21.1ADC Overview

Analog input function comprises the SCU_ADCIF module including a logic to control LPADC (4ch) and HPADC(2ch), and the SCU_ANALOG module including the ADC analog circuits and the peripheral circuits.
The ADCIF module distributes 10 bit A/D conversion data from the LPADC to four time-sharing lines and storesthem in the FIFO. In the meantime, the ADCIF module applies a decimation filter comprising the third order CIC
filter to two 10 bit A/D conversion data, which are from the individual two HPADCs separately. These data are
stored in the FIFO as 16 bit data. Regarding conversion data from the HPADC, two data-writing modes can beselected. One is a mode called vector mode (dual axis) that packs two A/D conversion data, and then writes themin the FIFO. The other is a mode that writes two A/D conversion data in the FIFO separately. These FIFOs which
are used only for the ADC in the ADCIF module are referred to as SCU_ADCIF_FIFOs in this manual. Fourchannels of 16 rows of SCU_ADCIF_FIFOs are prepared for the LPADC, and two channels of 32 rows areprepared for the HPADC. Each channel has an interface for DMA REQ/ACK signals to perform DMA processing,and for interrupt signals to perform Watermark Level detection.
Furthermore, the ADCIF module has a register block to control analog circuits, and the APB interface to exchange
data with the CPU and the SCU internal sequencer.
For data storage at the SCU and the FIFO control inside the SCU, refer to Chapter of the SCU (3.9).
The ADCIF module has two ports for GNSS, one is 10 bit A/D conversion data, and the other is the enable signal,
to directly output the values of a selected channel in the LPADC.

3.21.1.1

LPADC (Low Power ADC) Sampling Frequency

Table ADC-929 describes sampling frequencies supported by the LPADC. The maximum sampling rate isdependent on the number of active channels.
Table ADC-95 Sampling Rate Range Supported by the LPADC
Clock

Clock Frequency

Supported Sampling Rate Range vs number of active channels

CK_U32KL(Input to SCU)

1 channel

2 channels

4 channels

RCOSC

8.192 MHz

1 Hz to 32 kHz

1 Hz to 512 Hz

1 Hz to 256 Hz

RTC

32.768 kHz

1 Hz to 32 kHz

1 Hz to 512 Hz

1 Hz to 256 Hz

3.21.1.2

Sourceof

HPADC (High Performance ADC) Sampling Frequency－1239/1293－

CXD5602 User Manual

Table ADC-930 describes sampling frequencies supported by the HPADC
Table ADC-96 Sampling Rate Range Supported by the HPADC
Clock Source

Clock Frequency (Input toSupported Sampling Rate Range

Over Sampling Frequency

8.192 MHz

16 kHz to 32 kHz

2.048 MHz

1 Hz to 32.768 kHz

1 Hz to 32.768 kHz

None (actual rate conversion)

RTC

1 Hz to 32.768 kHz

1 Hz to 32.768 kHz

None (actual rate conversion)

XOSC

13 MHz16.927 kHz to 33.854 kHz

2.167 MHz

SCU)
RCOSC

3.21.2ADC Block Diagram

Figure 3.26-1 describes the block diagram of the ADCIF module and around ADC macro circuits.
for GNSSSCU

SCU_ANALOG
SCU_ADCIF_FIFOIFSCU_ANALOG
SEN_AIN2
1

LPADC_Wrapper

SEN_AIN3
1

LPAD_HV_AIN0
LPAD_HV_AIN1
LPAD_HV_AIN2
LPAD_HV_AIN3

SEN_AIN4
1
SEN_AIN5
1

LPAD_LV_CHSEL_OUT

LPAD_LV_DOUT

decimation

SCU_ADCIF_FIFO (L0)
16 words

decimation

SCU_ADCIF_FIFO (L1)
16 words

decimation

SCU_ADCIF_FIFO (L2)
16 words

decimation

SCU_ADCIF_FIFO (L3)
16 words

R

R

LPAD_LV_CHSEL
toggle data
( 0 <-> 1 )toggle data
( 0, 1, 2, 3 )SEN_AIN0
1
SEN_AIN1
1

HPAD_HV_AIN1

APB

APB

2's Comp.

HPADC_Wrapper
HPAD_HV_AIN0

SCU_ADCIF_MUX

HPAD_LV_DATA_EN0
HPAD_LV_DOUT0

2's Comp.

CIC3
FilterSCU_ADCIF_FIFO (H0)32 words

CIC3
FilterSCU_ADCIF_FIFO (H1)
32 words

HPAD_LV_DATA_EN1
HPAD_LV_DOUT1

2's Comp.

FIFO control
decimation control

SCU_ADCIF_REG

APB

LPADC control
HPADC control
interrupt
DMA_REQ / ACQ

SCU_PWM
LPADC_ENOAD_ENHPADC_EN

Figure ADC-62 Block Diagram ADCIF module and around ADC macro circuits

3.21.3

Memory Map

Figure ADC-63 describes a memory map inside the ADCIF.
For the memory map seen from the higher layers, refer to Chapter of the SCU (3.9).

－1240/1293－

CXD5602 User Manual

0x000

LPADC0 FIFO Read

0x004
0x008

LPADC2 FIFO Read

0x00C
0x080
0x084

0x000

LPADC1 FIFO ReadFIFO Read Port

0x200

LPADC3 FIFO Read

0x260

HPADC0 FIFO Read

0x2A0

HPADC1 FIFO Read

LPADC
HPADC Common

0x300
0x320

HPADC0HPADC1for Test

0x3FF

Figure ADC-63 Memory Map inside the ADCIF

3.21.4

Power Supply Control

The LPADC and the HPADC belong to power domain called PWD_SCU. Inside PWD_SCU, as lower level
power supply domains, there are module areas for power supply control shown below. Power supply control
registers for such areas are held in the TOPREG.
Table ADC-97 Power Supply Information
Targetfor

Power

SupplyAddress

Bit

OffsetBit

Name

Description(TOPREG)

Control
LPADC

0x0004[29]

WEN_LPADC

LPADC Power supply control Write
Enable0: Disable 1: Enable

[13]

LPADC

LPADC Power supply control
0: OFF 1: ON

HPADC

[28]

WEN_HPADC

HPADC Power supply control Write
Enable0: Disable 1: Enable

[12]

HPADC

HPADC Power supply control
0: OFF 1: ON

For control details, refer to Section of the SCU Control Sequence described in Chapter of the SCU (3.9).

－1241/1293－

CXD5602 User Manual

3.21.5Clock Control

3.21.5.1

Clock Summary
Table ADC-98 Clock Summary

Clock Name

Maximum

Maximum

Usage

Frequency (HV)

Frequency (LV)CK_SCU_SCU

13 MHz13 MHzSCU Main（1*）

CK_SCU_SCU_SC

13 MHz13 MHzControls SCU Main CPU only（1*）

CK_SCU_XOSC

13 MHz13 MHzFor HPADCCK_SCU_RC8M

8 MHz

8 MHz

For HPADCCK_SCU_U32KL

32 kHz32 kHzFor LPADCCK_SCU_U32KH

32 kHz32 kHzFor HPADCFor CK_SCU_SCU and CK_SCU_SCU_SC, refer to Section of the Clock Control described in Chapter of the（1*）

SCU (3.9).
The following describes the schematic diagram of the clock control.

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CXD5602 User Manual

RCRTC
RCOSC
8.192MHzCKDIV_SCU.SCU_32KH
0

1/250
RTC

CK_SCU_U32KH
CG

DIV

1

HPADC
HPAD_LV_CLK_U32

SCU_CKEN[7]CKSEL_SCU.SEL_SCU_32K

CK_SCU_RC8M
CK_SCU_XOSC

XOSCCKDIV_SCU.SCU_32KLDIV

CKSEL_SCU.SCU_XTAL"configure unavailable"

HPAD_LV_CLK_XOSC
DIV

LPADC
LPAD_LV_CLK

SCU_CKEN[6]

0
DIV

CG

CK_SCU_U32KL

HPAD_LV_CLK_RC8M

ADCIF

EN(1)

1

CG

2

CG

3

CK_SCU_SCU
CK_SCU_SCU_SC

EN(2)CKSEL_SCU.SEL_SCU
for GNSS TADC
for CK_SCU_SPICK_SCU_I2C0
etc..

Figure ADC-64 Schematic Diagram of the Clock Control
Clocks supplied to the HPADC and the LPADC are controlled by the following register.
Table ADC-99 Clock Control Register List
Control from

Block Name

Register Name

OffsetComment

CPU

TOPREGSCU_CKEN

0x071cTOPREG control area

For EN(1) and EN(2) in Figure ADC-64, and the summary of clock source selection, refer to Section of the ClockControl described in Chapter of the SCU (3.9).

3.21.5.2


Clock for the LPADCCK_SCU_U32KL

This is a clock to determine the sampling frequency of the LPADC.
CK_SCU_U32KL is generated in the CRG (Clock Reset Generator), and it is divided CK_SCU_32K (low speed
logic system clock) by 2^n (n = 0 to 15). For the range of the available sampling frequencies, refer to Table
ADC-929.

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CXD5602 User Manual

The API enables to select clock sources and to control selecting division ratio of CK_SCU_U32KL.

3.21.5.3

Clock for the HPADC

CK_SCU_XOSC



CK_SCU_RC8M



CK_SCU_U32KH

One of the above three clocks is used for the sampling frequency of the HPADC.
CK_U32KH is made, in the CRG outside the SCU, by dividing CK_SCU_32K (low speed logic system clock) by2^n (n = 0 to 15). The frequency division can be set independently from CK_SCU_U32KL of the clock for the
LPADC.
CK_SCU_XOSC is the oscillation clock of the crystal oscillator which is connected outside the LSI.
The oscillation clock of the RCOSC is input to CK_SCU_RC8M.
The API enables to select clock sources and to control selecting division ratio of CK_SCU_U32KH.
The ADCIF register actually controls to select which clock should be used for sampling frequency of the HPADC.
In addition, the frequency division of CK_SCU_XOSC and CK_SCU_RC8M can be set in the HPADC, and thesetting is controlled by the ADCIF register in the SCU as well.
The following describes the summary of input clock selection.
Table ADC-100 Input Clock Selection
Clock Source

Divider Circuit

Clock Port

Remarks

RCRTC (RCOSC divided

Select one number from 1, 2,

CK_SCU_32KL

For LPADC

by 250)4,

CK_SCU_32KH

For HPADC...,32768

todividefrequency
Select one number from 1, 2,
4,...,32768

todividefrequency
RCOSC

None

CK_SCU_RC8M

For HPADC

XOSC

None

CK_SCU_XOSC

For HPADC

3.21.5.4

Clock Control of the ADCIF

In the case that the HPADC in the SCU is not operated by the RCOSC while the RCOSC is ON, the power
consumption of the clock in the ADCIF can be reduced by writing “1” in RCOSC_CTRL1.
IRO_LV_SENSCLK_XEN, which is in 0x0590 region of the ADCIF.

3.21.5.5

CPU’s Clock Control to SCU－1244/1293－

CXD5602 User Manual

When you import the data for the ADC by using a sequencer inside the SCU, you must pay attention to the clock
supply to the SCU.
For details, refer to Section3.9.4.6 , Clock Control from Internal Sequencers described in Chapter of the CPU.

3.21.6

Reset Control

The following describes main reset control of the LPADC and the HPADC.
For Peripheral Name information, refer to Table Memory Mapping-2 of the section 2.6.1, Memory Map of eachblock.
Table ADC-101 Main Reset Control
TargetPeripheral Name

Address

bit

Name

Set

Remarks

Value
LPADC

PMU, CRG, GPIO, I/O Config

0x0704[4]

XRST_SCU_LPADC

1'b1

0: Reset

HPADC

PMU, CRG, GPIO, I/O Config

0x0704[2]

XRST_SCU_HPADC

1'b1

1: Reset release

3.21.7

Interrupt

The ADCIF is equipped in the SCU. For the details of the interrupt, refer to the chapter 3.3, Interrupt.

3.21.8

FIFO writing Process

The following describes the data flow.

LPADC0
LPADC1LPADC2ADCIF

MATH_PROC
Sequencer
Processing

LPADC3
HPADC0HPADC1Figure ADC-65 Data Flow of the ADC－1245/1293－

FIFO

CXD5602 User Manual

After being started, the ADC refers the status of the NOT_EMPTY interrupt from the ADCIF, then begins tomove. When the status is NOT_EMPTY, the ADC reads out the data and transfer them to the Write FIFO in the
SCU.
When the end of operation is notified (when a parameter ADC_PROPERTY.*_ENABLE in the SCU_RAM ischanged from “1” to “0”), the ADC reads out the corresponding data of SCU_ADCIF_FIFO until the FIFO
becomes EMPTY, then discards them. The function is prepared so that unnecessary data cannot be read out even
if the ADC is rebooted without resetting the SCU_ADCIF_FIFO.
The sample of the HPADC is processed every eight samples at a time. Accordingly, the time stamp per sample
cannot be recorded correctly. The fluctuation of the time stamp when eight samples are processed at a time can be
minimized by making the number of the DMA’s Watermark multiple of the eight samples. However, thefollowing fluctuation will occur if the samples are written during time stamp’s reading out even when making thenumber of the DMA’s Watermark multiple of the eight samples.
(The remaining number of the 8-FIFO data%8) × (INTERVAL[sec]－165/scu_clock_freq[Hz])In this formula, INTERVAL means sample’s interval (second).

3.21.93.21.9.1

Gain Control
Gain Control of the LPADC

The LPADC has a fixed voltage range, there is no gain control. Input the data with appropriate signal level basedon the LSI’s specifications, and perform appropriate signal processing after importing the data.

3.21.9.2

Gain Control of the HPADC

Gain control of the HPADC is performed in registers LV_LPFn_ATT_SEL, LV_LPFn_GAIN1ST, and
LV_LPFn_GAIN2ND (n = 0,1).
Table ADC-102 Gain Control of the HPADC
Function NameControl Register Name (n = 0, 1)

LPF

LV_LPFn_ATT_SEL

LV_LPFn_GAIN1ST

LV_LPFn_GAIN2ND

-6dB

2'b10

4'b0000

4'b0000

0dB

2'b00

4'b0000

4'b0000

6dB

2'b00

4'b0100

4'b0000

12dB

2'b00

4'b1100

4'b0000

14dB

2'b00

4'b0100

4'b1000

Gain setting－1246/1293－

CXD5602 User Manual

The combinations of setting other than the setting listed in Table ADC-936 are prohibited. Use the designatedcombinations of setting.
The following describes gain control overview.
ATT

Gain1st

HPAD_LV_LPFx_
ATT_SEL[1:0]HPAD_LV_LPFx_
GAIN1ST[3:0]Gain2nd

ATT
Attenuator

LPF and
Amplifier

LPF anddifferential
AmplifierAttenuator
Output

1st Amplifier
Outputdifferential
AmplifierOutput

-6dB

10bit
ADC

ADC output
Data
Dout

gain -6dB
setting(Total)1.6Vpp0.8Vpp0.8Vppgain 0dB
setting(Total)gain +6dB
setting(Total)gain +12dB
setting(Total)0.8Vpp0.8Vpp0.4VppDout

0.4Vpp0.8Vpp0.2Vppgain +14dB
setting(Total)Dout

0.2Vpp0.8Vpp+6dB
0.16Vpp

0.16Vpp0.32Vpp
0.8Vppd

Figure ADC-66 HPADC Gain Control Overview－1247/1293－

1023

0

0.8Vppd

+8dB

1023

0

0.8Vppd

+12dB

1023

0

0.8Vppd

+6dB

1023

0

0.8Vppd
Dout

0.8Vpp

10b

ADC

Vin

input signal
with full scale

HPADC

LPF

HPAD_LV_LPFx_
GAIN2ND[3:0]

Dout

1023

0

CXD5602 User Manual

3.21.10

Performance Estimation

The following describes the performance estimation of the maximum sampling frequency.
Table ADC-103 ADC Sampling Frequency Estimation
SCU

Main

Resource/ModeWith Sensor Operation

Without(Hz)

Operation (Hz)LPADC/1CH

25

27

LPADC/2CH

15

17

LPADC/4CH

8

9

HPADC

90

100

LPADC/1CH

5,500

6,500

LPADC/2CH

512

512

Clock(Hz)32,768

8,192,000

SensorRemarks

ADC

HW

performancebottleneck
LPADC/4CH

256

256

ADC

HW

performancebottleneck13,000,000

HPADC

22,00026,000

LPADC/1CH

9,500

11,000

LPADC/2CH

512

512

ADC

HW

performancebottleneck
LPADC/4CH

256

256

ADC

HW

performancebottleneck
HPADC



37,00041,000The following describes the sensor conditions with sensor operation.
・Six byte read transfer per event for each sensor (three axes are assumed)
・The total of the sampling frequencies of all SPI sensors is 820 Hz (1 Hz when the clock is 32 kHz)・The total of the sampling frequencies of all I2C sensors is 180 Hz (1 Hz when the clock is 32 kHz)・The SPI’s transfer rate is about 4 Mbps, and the I2C’s transfer rate is about 400 Kbps (The SPI’s isabout 16Kbps, and the I2C’s is about 1.4 Kbps, when the clock is 32 kHz)

Caution: When you use the XOSC for sampling clock of the ADC, set the decimation filter so that the frequencies
are less than the supported frequencies shown above.
In the meantime, the following describes the worst cases of the sensors estimated on the typical HPADC/LPADC
scenario.

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Table ADC-104 ADC Sensor Sampling Frequency Estimation
SCU Clock(Hz)HPADC(Hz)LPADC(Hz)SPI Sensor (Hz)I2C Sensor (Hz)32,768

0

0

16

0

8,192,000

16,384

250

1,500

500

13,000,000

16,384

250

3,500

1,000

The following describes the sensor conditions with sensor operation.
Six byte read transfer per event for each sensor (three axes are assumed)
The SPI’s transfer rate is about 4 Mbps, the I2C’s transfer rate is about 400 Kbps (The SPI’s is about 16
Kbps, the I2C’s is about 1.4 Kbps when the clock is 32 kHz.)3.21.113.21.11.1

Synchronization Function with PWM
PWM Output Based on ADC

The PWM output can be performed based on the AD data confirmation signals (synchronization signals) from the
ADC (LPADC/HPADC). For details, refer to Section 3.9.11, PWM Control described in Chapter of the SCU.

3.21.11.2

ADC Data Import Based on the PWM Output

Based on the rise of the PWM output, timing of importing the ADC data in the SCU can be controlled. For details,
refer to Section of PWM Control described in Chapter of the SCU (3.9).

3.21.123.21.12.1

ADC Control Register Details
SCU_ADCIF_REG

The following describes the 32 bit address offset. Add this address to the offset addresses in the table shown
below to calculate the address from the CPU.
Offset:0x0018dc00 (Mirror:0x0418dc00)－1249/1293－

CXD5602 User Manual

Table ADC-105 SCU_ADCIF_REG Register List
OffsetAddress

Name

Type

(Transaction Port)

Size

Description

Reset Value(bits)

0x200

LPADC_A0

RW

32

LPADC enable control

0x00000000

0x204

LPADC_A1

RW

32

LPADC channel switching control

0x00000000

0x210

LPADC_D0

RW

32

LPADC software reset

0x00000000

0x214

LPADC_D1

RW

32

LPADC basic setting

0x00000008

0x218

LPADC_D2

RW

32

Permission/prohibition of the LPADC

0x00000000

ADC data acceptance
0x21C

LPADC_D4

RW

32

LPADC basic setting

0x00000008

0x220

LPADC_D5

RW

32

LPADC basic setting

0x00000008

0x224

LPADC_D6

RW

32

LPADC basic setting

0x00000008

0x240

HPADC_AC0

RW

32

HPADC common clock control

0x00000000

0x244

HPADC_AC1

RW

32

HPADC common enable control

0x00000000

0x250

HPADC_DC

RW

32

Permission/prohibition of handling two

0x00000000

element vector
0x280

HPADC0_A0

RW

32

HPADC0 clock selection

0x00000000

0x284

HPADC0_A1

RW

32

HPADC0 enable control

0x00000000

0x288

HPADC0_A2

RW

32

HPADC0 clock enable control

0x00000000

0x28C

HPADC0_A3

RW

32

HPADC0 LPF control

0x00000100

0x290

HPADC0_D0

RW

32

HPADC0 software reset

0x00000000

0x294

HPADC0_D1

RW

32

HPADC0 basic setting

0x00000010

0x298

HPADC0_D2

RW

32

Permission/prohibition of the HPADC00x00000000

ADC data acceptance
0x2C0

HPADC1_A0

RW

32

HPADC1 clock selection

0x00000000

0x2C4

HPADC1_A1

RW

32

HPADC1 enable control

0x00000000

0x2C8

HPADC1_A2

RW

32

HPADC1 clock enable control

0x00000000

0x2CC

HPADC1_A3

RW

32

HPADC1 LPF control

0x00000100

0x2D0

HPADC1_D0

RW

32

HPADC1 software reset

0x00000000

0x2D4

HPADC1_D1

RW

32

HPADC1 basic setting

0x00000010

0x2D8

HPADC1_D2

RW

32

Permission/prohibition of the HPADC1

0x00000000

ADC data acceptance
0x3D0

ADCIF_DCT

RO

32

0x3D4

SCU_ADCIF_C

RW32

SCU_ADCIF register map revision code

0xADC1F000
0x00000001

KPOWER－1250/1293－

CXD5602 User Manual

3.21.12.1.1{0x200} LPADC_A0 Details

LPADC Enable Control
Table ADC-106
Register Type: RW (read/write)

Local Address: 0x200

Reset Value: 0x00000000

LV_ADC_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

ReservedRO

Reserved

0x00000000

Permission/prohibition of the LPADC operation0

LV_ADC_EN

RW

0x0

Switching between standby and move
1'b0: standby
1'b1: active (default)－1251/1293－

CXD5602 User Manual

3.21.12.1.2{0x204} LPADC_A1 Details

LPADC Channel Switching Control
Table ADC-107
Register Type: RW (read/write)

Local Address: 0x204

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..10ReservedRO

Reserved

0x000000Reserved

LV_CH_SEL_MODE

LV_CH_SEL_INV

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADCH selector for GNSS
(sets only a CH which are in operation shown
below)
9..8

LV_CH_SEL_INV

RW

0x0

2'b00 CH0
2'b01 CH1
2'b10 CH2
2'b11 CH3

7..3

Reserved

RO

0x00

Reserved
LPADC channel switching mode
3'b000 CH0
3'b001 CH1

2..0

LV_CH_SEL_MODE RW

0x0

3'b010 CH2
3'b011 CH3
3'b100 CH0 => CH1
3'b101 CH0 => CH1=> CH2=> CH3－1252/1293－

CXD5602 User Manual

3.21.12.1.3{0x210} LPADC_D0 Details

LPADC Software Reset
Table ADC-108
Register Type: RW (read/write)

Local Address: 0x210

Reset Value: 0x00000000

SW_RESET

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

SW_RESET

RW

0x0

LPADC software reset
common to each LPADC－1253/1293－

CXD5602 User Manual

3.21.12.1.4{0x214} LPADC_D1 Details

LPADC Basic Setting
Table ADC-109
Register Type: RW (read/write)

Local Address: 0x214

Reset Value: 0x00000008

Bits

Name

Type

Reset Value

Description

31..21

Reserved

RO

0x000

Reserved
Bit0

FIFO_WATERMARKDMA_HS_EN
Reserved

SAMP_RATIO2

Reserved

Reserved

SAMP_RATIO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Synchronization signal from the

PWM0 is enabled
Bit1

Synchronization signal from thePWM1 is enabled
Bit2

Synchronization signal from thePWM2 is enabled
Bit3

Synchronization signal from thePWM3 is enabled
20..12

SAMP_RATIO2

RW

0x000

Bit4

Synchronization signal from thePWM4 is enabled
Bit5

Synchronization signal from thePWM5 is enabled
Bit6

Synchronization signal from thePWM6 is enabled
Bit7

Synchronization signal from thePWM7 is enabled
Bit8

0: not synchronized

LPADC sampling ratio selection
11..8

SAMP_RATIO

RW

0x0

(0: No frequency division, 1: 1/2, ..., 15:
1/32768)

7..6

ReservedRO

0x0

Reserved－1254/1293－

CXD5602 User Manual

5

DMA_HS_EN

RW

0x0

4

Reserved

RO

0x0

3..0

FIFO_WATERMARK RW

0x8

3.21.12.1.5

Permission/prohibition of using LPADC DMA
signals
Reserved
LPADC FIFO Watermark
Determination of the DMA traffic{0x218} LPADC_D2 Details

Permission/Prohibition of the LPADC ADC Data Acceptance
Table ADC-110
Register Type: RW (read/write)

Local Address: 0x218

Reset Value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

FIFO_EN

Bits

Name

Type Reset Value

Description

31..4

Reserved

RO

0x0000000

Reserved

3..0

FIFO_EN

RW

0x0

Permission/prohibition of the LPADC FIFO
operation－1255/1293－

CXD5602 User Manual

3.21.12.1.6{0x21C} LPADC_D4 Details

LPADC Basic Setting
Table ADC-111
Register Type: RW (read/write)

Local Address: 0x21C

Reset Value: 0x00000008

Bits

Name

Type Reset Value

Description

31..21

ReservedRO

Reserved

0x000

Bit0

FIFO_WATERMARKDMA_HS_EN
Reserved

SAMP_RATIO2

Reserved

Reserved

SAMP_RATIO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Synchronization signal from the

PWM0 is enabled
Bit1

Synchronization signal from thePWM1 is enabled
Bit2

Synchronization signal from thePWM2 is enabled
Bit3

Synchronization signal from thePWM3 is enabled
20..12

SAMP_RATIO2

RW

0x000

Bit4

Synchronization signal from thePWM4 is enabled
Bit5

Synchronization signal from thePWM5 is enabled
Bit6

Synchronization signal from thePWM6 is enabled
Bit7

Synchronization signal from thePWM7 is enabled
Bit8

0: not synchronized

HPADC sampling ratio selection
11..8

SAMP_RATIO

RW

0x0

(0: No frequency division, 1: 1/2, -, 15:
1/32768)

7..6

ReservedRO

0x0

Reserved－1256/1293－

CXD5602 User Manual

5

DMA_HS_EN

RW

0x0

4

Reserved

RO

0x0

3..0

FIFO_WATERMARK RW

0x8

Permission/prohibition of using LPADC DMA
signals
Reserved
LPADC FIFO Watermark
Determination of the DMA traffic－1257/1293－

CXD5602 User Manual

3.21.12.1.7{0x220} LPADC_D5 Details

LPADC Basic Setting
Table ADC-112
Register Type: RW (read/write)

Local Address: 0x220

Reset Value: 0x00000008

Bits

Name

Type

Reset Value

Description

31..21

Reserved

RO

0x000

Reserved
Bit0

FIFO_WATERMARKDMA_HS_EN
Reserved

SAMP_RATIO2

Reserved

Reserved

SAMP_RATIO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Synchronization signal from the

PWM0 is enabled
Bit1

Synchronization signal from thePWM1 is enabled
Bit2

Synchronization signal from thePWM2 is enabled
Bit3

Synchronization signal from thePWM3 is enabled
20..12

SAMP_RATIO2

RW

0x000

Bit4

Synchronization signal from thePWM4 is enabled
Bit5

Synchronization signal from thePWM5 is enabled
Bit6

Synchronization signal from thePWM6 is enabled
Bit7

Synchronization signal from thePWM7 is enabled
Bit8

0: not synchronized

HPADC sampling ratio selection
11..8

SAMP_RATIO

RW

0x0

(0: No frequency division, 1: 1/2, -, 15:
1/32768)

7..6

ReservedRO

0x0

Reserved－1258/1293－

CXD5602 User Manual

5

DMA_HS_EN

RW

0x0

4

Reserved

RO

0x0

3..0

FIFO_WATERMARK RW

0x8

Permission/prohibition of using LPADC DMA
signals
Reserved
LPADC FIFO Watermark
Determination of the DMA traffic－1259/1293－

CXD5602 User Manual

3.21.12.1.8{0x224} LPADC_D6 Details

LPADC Basic Setting
Table ADC-113
Register Type: RW (read/write)

Local Address: 0x224

Reset Value: 0x00000008

Bits

Name

Type

Reset Value

Description

31..21

Reserved

RO

0x000

Reserved
Bit0

FIFO_WATERMARKDMA_HS_EN
Reserved

SAMP_RATIO2

Reserved

Reserved

SAMP_RATIO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Synchronization signal from the

PWM0 is enabled
Bit1

Synchronization signal from thePWM1 is enabled
Bit2

Synchronization signal from thePWM2 is enabled
Bit3

Synchronization signal from thePWM3 is enabled
20..12

SAMP_RATIO2

RW

0x000

Bit4

Synchronization signal from thePWM4 is enabled
Bit5

Synchronization signal from thePWM5 is enabled
Bit6

Synchronization signal from thePWM6 is enabled
Bit7

Synchronization signal from thePWM7 is enabled
Bit8

0: not synchronized

HPADC sampling ratio selection
11..8

SAMP_RATIO

RW

0x0

(0: No frequency division, 1: 1/2, -, 15:
1/32768)

7..6

ReservedRO

0x0

Reserved－1260/1293－

CXD5602 User Manual

5

DMA_HS_EN

RW

0x0

4

Reserved

RO

0x0

3..0

FIFO_WATERMARK RW

0x8

Permission/prohibition of using LPADC DMA
signals
Reserved
LPADC FIFO Watermark
Determination of the DMA traffic－1261/1293－

CXD5602 User Manual

3.21.12.1.9{0x240} HPADC_AC0 Details

Clock Control Common to the HPADC
Table ADC-114
Register Type: RW (read/write)

Local Address: 0x240

Reset Value: 0x00000000

Bits

Name

31..6 Reserved

LV_CLK_OSC_SEL

Reserved

Reserved

LV_CLK_XOSC_DIV

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Type Reset Value Description
RO

0x0000000 Reserved
Division ratio setting port when using the XOSC clock
0: clock divided by 2,

5..4

LV_CLK_XOSC_DIV RW

0x0

1: clock divided by 3
2: clock divided by 4
3: clock divided by 6

3..1

ReservedRO

0x0

Reserved
Clock selection port when performing high speed0

LV_CLK_OSC_SEL

RW

0x0

sampling
0: XOSC
1: RCOSC－1262/1293－

CXD5602 User Manual

3.21.12.1.10{0x244} HPADC_AC1 Details

Enable Control Common to the HPADC
Table ADC-115
Register Type: RW (read/write)

Local Address: 0x244

Reset Value: 0x00000000

LV_BGR_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

ReservedRO

Reserved

0x00000000

LV BGR Circuit Enable
0

LV_BGR_EN

RW

0x0

Switching between standby and move
1'b0: standby
1'b1: active (default)－1263/1293－

CXD5602 User Manual

3.21.12.1.11{0x250} HPADC_DC Details

Permission/Prohibition of Handling Two Element Vector
Table ADC-116
Register Type: RW (read/write)

Local Address: 0x250

Reset Value: 0x00000000

VECTOR_SEL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

VECTOR_SEL

RW

0x0

Permission/prohibition of handling two element
vector－1264/1293－

CXD5602 User Manual

3.21.12.1.12{0x280} HPADC0_A0 Details

HPADC0 Clock Selection
Table ADC-117
Register Type: RW (read/write)

Local Address: 0x280

Reset Value: 0x00000000

LV_CLK_U32_SEL0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

31..1 Reserved

Type Reset Value

Description

RO

Reserved

0x00000000

Clock selection port
0

LV_CLK_U32_SEL0 RW

0x0

0: high speed clock
1: low speed clock－1265/1293－

CXD5602 User Manual

3.21.12.1.13{0x284} HPADC0_A1 Details

HPADC0 Enable Control
Table ADC-118
Register Type: RW (read/write)

Local Address: 0x284

Reset Value: 0x00000000

Bits

Name

31..3 Reserved

Type Reset Value

Description

RO

Reserved

0x00000000

ADC0 REF circuit enable port
Setting for the ADC reference and operation mode
2

LV_ADC0_REF_EN RW

0x0

(0,0)

standby(0,1)

external enable(1,0)

active (default)(1,1)

active

LPF0 enable control port
1

LV_LPF0_EN

RW

0x0

(0,0)

standby(0,1)

standby(1,0)

active (default)(1,1)

prohibited setting

Permission/Prohibition of the HPADC0 operation0

LV_ADC0_EN

RW

0x0

1'b0: standby
1'b1: active (default)－1266/1293－

0

LV_ADC0_EN

Reserved

1

LV_LPF0_EN

LV_ADC0_REF_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

CXD5602 User Manual

3.21.12.1.14{0x288} HPADC0_A2 Details

HPADC0 Clock Enable Control
Table ADC-119
Register Type: RW (read/write)

Local Address: 0x288

Reset Value: 0x00000000

LV_CLKOUT0_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved0

LV_CLKOUT0_EN RW

0x0

ADC0 clock output enable port

－1267/1293－

CXD5602 User Manual

3.21.12.1.15{0x28C} HPADC0_A3 Details

HPADC0 ADC and LPF Control
Table ADC-120
Register Type: RW (read/write)

Local Address: 0x28C

Reset Value: 0x00000100

Bits

Name

31..26 Reserved

Type Reset Value

Description

RO

Reserved

0x00

LV_ADC0_PREAMPLP_EN

LV_ADC0_REFLP_EN

Reserved

LV_ADC0_REFCTRL

Reserved
LV_LPF0_XSTARTUP

LV_LPF0_FC

LV_LPF0_GAIN1ST

LV_LPF0_GAIN2ND

LV_LPF0_MODE

Reserved

Reserved

LV_LPF0_ATT_SEL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Attenuator gain switching at LPF input part
Refer to Section 3.21.9.1
25..24 LV_LPF0_ATT_SEL

RW

0x0

2'b00: x1 (default)
2'b01: x0.75
2'b10: x0.5
2'b11: x0.25 (prohibited setting)23

ReservedRO

0x0

Reserved
Switching port of the LPF current setting
Bias current value switching
3'b000: 0.4uA (default)
3'b001: 0.5uA

22..20 LV_LPF0_MODE

RW

0x0

3'b010: 0.6uA
3'b011: 0.7uA
3'b100: 0.8uA
3'b101: 0.1uA
3'b110: 0.2uA
3'b111: 0.3uA－1268/1293－

CXD5602 User Manual

LPF gain switching function (differential
amplifier)
Refer to Section 3.21.9.1.
4'b0000: x1 (default)
4'b0001: x1.08
4'b0010: x1.18
4'b0011: x1.29
4'b0100: x1.43
4'b0101: x1.6
19..16 LV_LPF0_GAIN2ND

RW

0x0

4'b0110: x1.82
4'b0111: x2.1
4'b1000: x2.5
4'b1001: x3.08
4'b1010: x4
4'b1011: x0.83
4'b1100: x0.71
4'b1101: x0.63
4'b1110: x0.56
4'b1111: x0.5
LPF gain switching function (first stage
amplifier)
Refer to Section 3.21.9.1.
4'b0000: x1 (default)

15..12 LV_LPF0_GAIN1ST

RW

0x0

4'b0001: x1.25
4'b0010: x1.5:
4'b1110: x4.5
4'b1111: x4.75
LPF frequency band switching function
2'b00: 75 kHz (default)

11..10 LV_LPF0_FC

RW

0x0

2'b01: 150 kHz
2'b10: 37.5 kHz
2'b11: No LPF, Amplifier only

9

ReservedRO

0x0

Reserved
LPF0 input common startup function

8

LV_LPF0_XSTARTUP RW

0x1

1'b0: startup enable
1'b1: startup disable (default)－1269/1293－

CXD5602 User Manual

REF voltage regulator port
Reference gm adjustment
4’b0000: ADC0 X1, ADC1 X1 (default)
4'b0001: X2, X1
4’b0010: X3, X1
4'b0011: X4, X2
4'b0100: X1, X2
4'b0101: X2, X2
7..4

LV_ADC0_REFCTRL

RW

0x0

4'b0110: X3, X2
4'b0111: X4, X2
4’b1000: X3, X1
4'b1001: X3, X2
4’b1010: X3, X3
4'b1011: X3, X4
4'b1100: X1, X4
4'b1101: X2, X4
4'b1110: X3, X4
4'b1111: X4, X4

3..2

ReservedRO

0x0

Reserved
Low power mode signal of the voltage
reference circuit

1

LV_ADC0_REFLP_EN RW

0x0

(0,0)

Standby(0,1)

Standby(1,0)

active (default)(1,1)

Prohibited setting

ADC0 PreAMP low power mode signal
0

LV_ADC0_PREAMPLP_EN

Control used when monitoring the ADC
RW

0x0

sampling clock via the ATB
1’b0: off (default)
1'b1: on－1270/1293－

CXD5602 User Manual

3.21.12.1.16{0x290} HPADC0_D0 Details

HPADC0 Software Reset
Table ADC-121
Register Type: RW (read/write)

Local Address: 0x290

Reset Value: 0x00000000

SW_RESET

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

SW_RESET

RW

0x0

HPADC0 software reset－1271/1293－

CXD5602 User Manual

3.21.12.1.17{0x294} HPADC0_D1 Details

HPADC0 Basic Setting
Table ADC-122
Register Type: RW (read/write)

Local Address: 0x294

Reset Value: 0x00000010

Bits

Name

Type Reset Value

Description

31..21

ReservedRO

Reserved

0x000

Bit0

FIFO_WATERMARKDMA_HS_EN

Reserved

DECI_RATIO2
Reserved

Reserved

DECI_RATIO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Synchronization signal from the

PWM0 is enabled
Bit1

Synchronization signal from thePWM1 is enabled
Bit2

Synchronization signal from thePWM2 is enabled
Bit3

Synchronization signal from thePWM3 is enabled
20..12

DECI_RATIO2

RW

0x000

Bit4

Synchronization signal from thePWM4 is enabled
Bit5

Synchronization signal from thePWM5 is enabled
Bit6

Synchronization signal from thePWM6 is enabled
Bit7

Synchronization signal from thePWM7 is enabled
Bit8
11

Reserved

RO

0x0

10..8

DECI_RATIO

RW

0x0

7..6

ReservedRO

0x0

0: not synchronized

Reserved
HPADC0 decimation ratio selection(0: No frequency division, 1: 1/2, ..., 7: 1/128)
Reserved－1272/1293－

CXD5602 User Manual

5

DMA_HS_EN

RW

0x0

4..0

FIFO_WATERMARK RW

0x10

3.21.12.1.18

Permission/prohibition of using HPADC0DMA signals
HPADC0 FIFO Watermark{0x298} HPADC0_D2 Details

Permission/Prohibition of the HPADC0 ADC Data Acceptance
Table ADC-123
Register Type: RW (read/write)

Local Address: 0x298

Reset Value: 0x00000000

DECIFIFO_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

DECIFIFO_EN

RW

0x0

Permission/prohibition

of

the

Decimation and FIFO operation－1273/1293－

HPADC0CXD5602 User Manual

3.21.12.1.19{0x2C0} HPADC1_A0 Details

HPADC1 Clock Selection
Table ADC-124
Register Type: RW (read/write)

Local Address: 0x2C0

Reset Value: 0x00000000

LV_CLK_U32_SEL1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

ReservedRO

Reserved0

LV_CLK_U32_SEL1 RW

0x00000000
0x0

Clock selection port
0: high speed clock, 1: low speed clock－1274/1293－

CXD5602 User Manual

3.21.12.1.20{0x2C4} HPADC1_A1 Details

HPADC1 Enable Control
Table ADC-125
Register Type: RW (read/write)

Local Address: 0x2C4

Reset Value: 0x00000000

Reserved

Bits

Name

Type Reset Value

Description

31..3

ReservedRO

Reserved

0x00000000

LV_ADC1_EN

LV_ADC1_REF_EN
LV_LPF1_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC1 REF circuit enable port
ADC reference operation mode setting
2

LV_ADC1_REF_EN RW

0x0

(0,0)

standby(0,1)

external enable(1,0)

active (default)(1,1)

activeLPF1 enable control port
1

LV_LPF1_EN

RW

0x0

(0,0)

standby(0,1)

standby(1,0)

active (default)(1,1)

prohibited setting

Permission/prohibition0

LV_ADC1_EN

RW

0x0

operation
1'b0: standby
1'b1: active (default)－1275/1293－

of

the

HPADC1CXD5602 User Manual

3.21.12.1.21{0x2C8} HPADC1_A2 Details

HPADC1 Clock Enable Control
Table ADC-126
Register Type: RW (read/write)

Local Address: 0x2C8

Reset Value: 0x00000000

LV_CLKOUT1_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved0

LV_CLKOUT1_EN RW

0x0

ADC1 clock output enable port

－1276/1293－

CXD5602 User Manual

3.21.12.1.22{0x2CC} HPADC1_A3 Details

HPADC1 LPF Control
Table ADC-127
Register Type: RW (read/write)

Local Address: 0x2CC

Reset Value: 0x00000100

Bits

Name

31..26 Reserved

Type Reset Value

Description

RO

Reserved

0x00

LV_ADC1_PREAMPLP_EN

LV_ADC1_REFLP_EN

Reserved

LV_ADC1_REFCTRL

Reserved
LV_LPF1_XSTARTUP

LV_LPF1_FC

LV_LPF1_GAIN1ST

LV_LPF1_GAIN2ND

LV_LPF1_MODE

Reserved

Reserved

LV_LPF1_ATT_SEL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Attenuator gain switching at LPF input part
Refer to Section 3.21.9.1
25..24 LV_LPF1_ATT_SEL

RW

0x0

2'b00: x1 (default)
2'b01: x0.75
2'b10: x0.5
2'b11: x0.25 (prohibited setting)23

ReservedRO

0x0

Reserved
Switching port of the LPF current setting
Bias current value switching
3'b000: 0.4uA (default)
3'b001: 0.5uA

22..20 LV_LPF1_MODE

RW

0x0

3'b010: 0.6uA
3'b011: 0.7uA
3'b100: 0.8uA
3'b101: 0.1uA
3'b110: 0.2uA
3'b111: 0.3uA－1277/1293－

CXD5602 User Manual

LPF gain switching function (differential
amplifier)
Refer to Section 3.21.9.1.
4'b0000: x1 (default)
4'b0001: x1.08
4'b0010: x1.18
4'b0011: x1.29
4'b0100: x1.43
4'b0101: x1.6
19..16 LV_LPF1_GAIN2ND

RW

0x0

4'b0110: x1.82
4'b0111: x2.1
4'b1000: x2.5
4'b1001: x3.08
4'b1010: x4
4'b1011: x0.83
4'b1100: x0.71
4'b1101: x0.63
4'b1110: x0.56
4'b1111: x0.5
LPF gain switching function (first stage
amplifier)
Refer to Section 3.21.9.1.
4'b0000: x1 (default)

15..12 LV_LPF1_GAIN1ST

RW

0x0

4'b0001: x1.25
4'b0010: x1.5:
4'b1110: x4.5
4'b1111: x4.75
LPF frequency band switching function
2'b00: 75 kHz (default)

11..10 LV_LPF1_FC

RW

0x0

2'b01: 150 kHz
2'b10: 37.5 kHz
2'b11: No LPF, Amplifier only

9

ReservedRO

0x0

Reserved
LPF input common startup function

8

LV_LPF1_XSTARTUP RW

0x1

1'b0: startup enable
1'b1: startup disable (default)－1278/1293－

CXD5602 User Manual

REF voltage regulator port
<3> reference destination switching
1’b0: internal 0.7 V system power supply(default)
1'b1: external enable power supply via theATB<2:0> BGR output voltage switching
7..4

LV_ADC1_REFCTRL

RW

0x0

3’b000: 700mV (default)
3'b001: 750mV
3’b010: 800mV
3'b011: 850mV
3'b100: 500mV
3'b101: 550mV
3'b110: 600mV
3'b111: 650mV

3..2

ReservedRO

0x0

Reserved
Low power mode signal of the REF circuit

1

LV_ADC1_REFLP_EN RW

0x0

(0,0)

standby(0,1)

standby(1,0)

active (default)(1,1)

prohibited setting

ADC1 PreAMP low power mode signal
0

LV_ADC1_PREAMPLP_EN

Control used when monitoring the ADC
RW

0x0

sampling clock via the ATB
1’b0: off (default)
1'b1: on－1279/1293－

CXD5602 User Manual

3.21.12.1.23{0x2D0} HPADC1_D0 Details

HPADC1 Software Reset
Table ADC-128
Register Type: RW (read/write)

Local Address: 0x2D0

Reset Value: 0x00000000

SW_RESET

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

SW_RESET

RW

0x0

HPADC1 software reset－1280/1293－

CXD5602 User Manual

3.21.12.1.24{0x2D4} HPADC1_D1 Details

HPADC1 Basic Setting
Table ADC-129
Register Type: RW (read/write)

Local Address: 0x2D4

Reset Value: 0x00000010

Bits

Name

Type

Reset Value

Description

31..21

Reserved

RO

0x000

Reserved
Bit0

FIFO_WATERMARKDMA_HS_EN

Reserved

DECI_RATIO2
Reserved

Reserved

DECI_RATIO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Synchronization signal from the

PWM0 is enabled
Bit1

Synchronization signal from thePWM1 is enabled
Bit2

Synchronization signal from thePWM2 is enabled
Bit3

Synchronization signal from thePWM3 is enabled
20..12

DECI_RATIO2

RW

0x000

Bit4

Synchronization signal from thePWM4 is enabled
Bit5

Synchronization signal from thePWM5 is enabled
Bit6

Synchronization signal from thePWM6 is enabled
Bit7

Synchronization signal from thePWM7 is enabled
Bit8
11

Reserved

RO

0x0

10..8

DECI_RATIO

RW

0x0

7..6

ReservedRO

0x0

0: not synchronized

Reserved
HPADC1 decimation ratio selection(0: No frequency division, 1: 1/2, ..., 7: 1/128)
Reserved－1281/1293－

CXD5602 User Manual

5

DMA_HS_EN

RW

0x0

4..0

FIFO_WATERMARK RW

0x10

Permission/prohibition of using HPADC1
DMA signals
HPADC1 FIFO Watermark－1282/1293－

CXD5602 User Manual

3.21.12.1.25{0x2D8} HPADC1_D2 Details

Permission/Prohibition of the HPADC1 ADC Data Acceptance
Table ADC-130
Register Type: RW (read/write)

Local Address: 0x2D8

Reset Value: 0x00000000

DECIFIFO_EN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

DECIFIFO_EN

RW

0x0

Permission/prohibition

of

the

Decimation and the FIFO operation－1283/1293－

HPADC1CXD5602 User Manual

3.21.12.1.26{0x3D0} ADCIF_DCT Details

SCU_ADCIF Register Map Revision Code
Table ADC-131
Register Type: RO (read only)

Local Address: 0x3D0

Reset Value: 0xADC1F000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_CODE
Bits

Name

Type Reset Value

Description
Revision code of the SCU_ADCIF register

31..0

REV_CODERO

0xADC1F000

map(revision of the last three digits)

3.21.12.1.27{0x3D4} SCU_ADCIF_CKPOWER Details
Table ADC-132
Register Type: RW (read/write)

Local Address: 0x3D4

Reset Value: 0x00000001

CK_POWEREN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits

Name

Type Reset Value

Description

31..1

Reserved

RO

0x00000000

Reserved

0

CK_POWEREN

RW

0x1

3.21.12.2

Default clock supply

SCU_RAM Parameter

For parameters in the SCU_RAM, refer to Chapter of the SCU.

－1284/1293－

CXD5602 User Manual

3.21.13ADC Control Sequence

For the ADC startup and the details of the data transfer, refer to Section 3.9.13 SCU Control Sequence describedin Chapter of the SCU.
In addition, for SCU sequencer to which the LPADC and the HPADC can connect, refer to Section ofConnectable Sequencer described in Chapter of the SCU (3.9).

3.21.13.1

Setting for transferring the data of the LPADC to the GNSS

The following describes the necessary settings.
{0x200} LPADC_A0

Select “1” when using the LPADC.

{0x204} LPADC_A1

Select the four-channel AD data to send the GNSS. Then select time shareprocessing.
Procedure:
When CK_SCU_SCU is OFF, turn it ON when setting registers.
Set the registers of the LPADC
If necessary, turn CK_SCU_SCU OFF after the setting is completed
Caution: CK_SCU_U32KL is the main clock of the LPADC, therefore, it cannot be stopped when using the
LPADC.

3.21.14
3.21.14.1

Restrictions
Delay at the LPADC Startup

When starting the LPADC up, there will be maximum one sampling period of delay until the first sample is taken.
The time stamp delays according to the delay of the first sample.

3.21.14.2

Delay at the HPADC Startup

When starting the HPADC up, there will be maximum one sampling period of delay until the first sample is taken.
The time stamp delays according to the delay of the first sample.

3.21.14.3

Other Restrictions

For sequencer, MATH_PROC, and the restrictions of the time stamp, refer to Chapter of the SCU (3.9).
－1285/1293－

CXD5602 User Manual

3.21.15

Error HandlingSome error interrupts for the ADC may occur. Refer to Section 3.9.14 of the Errror Handling described in Chapterof the SCU.

－1286/1293－

CXD5602 User Manual

4 Appendix
4.1

Words and Terms

4.1.1

Words and Terms Used in This User Manual

The following describes words and terms used in this user manual.
Table Words and Terms-133 Words and Terms Used in This User Manual
Abbreviation

Word and Terms

Explanation

ADSP

Application Processor

The ADSP is a group of processors equipped with six Cortex®-M4.
Each of the ADSP are explained in this manual with numbers referred to as fromADSP0 to ADSP5.
The ADSP contains Cortex®-M4, Interrupt input register, Timer, WDT,SLEEPING signal monitor, and Debug function.
The Tile address converter and the memory protection unit are equipped outside
the ADSP.

APP

Application Domain

The APP is the functional block of Imaging/2D, Storage/Connectivity, andAudio, equipped with six Arm® Cortex®-M4 processors with FPU 32 bit RISC,
indicated in Section 2.5.1.

APP_DSP---

The APP_DSP corresponds to the functional block of the Application Domain
excluding Imaging, Storage, and Audio.

APP MAIN Bus---

The APP MAIN Bus means the matrix bus which connects Application Processor
with the APP SRAM and the APP SUB Bus.

APP SRAM---The APP SRAM is 1.5 MByte of SRAM inside the Application Domain.

APP SUB Bus---

The APP SUB Bus is inside the APP.

CRG

Clock and Reset Generator

For details, refer to Chapter 3.5

DSP

---

The ADSP and the GDSP are collectively referred to as the DSP.

fs

---

“fs” means the sampling frequency of the audio data.
In this document, it means 48 kHz.

GDSPGNSS DSPThe GDSP means Cortex®-M4 inside the GNSS Domain.

GNSS

GNSS Domain

The GNSS is the GNSS functional block equipped with one Arm® Cortex®-M4
processor with FPU 32 bit RISC.

HPADC

High Performance A/D

The HPADC is the A/D Converter in the CXD5602.

Converter
HOST I/F

HOST Interface

The HOST I/F is the format to communicate with the external HOST CPU.

－1287/1293－

CXD5602 User Manual

Local AHB---

The Local AHB is the matrix bus which connects the System and I/O Processor
with the SYS SRAM and the SYSTEM Bus.

LPADC

Low Power A/D Converter

The LPADC is the A/D Converter in the CXD5602.

NVIC

Nested Vectored

For the NVIC, refer to the following URL.

Interrupt Controller

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/Cihcffda.html

Power Management IC

The PMIC is the IC to control power supply. As a companion chip for the

PMIC

CXD5602, the CXD5247 is prepared. In this document, the CXD5247 is assumed
as the PMIC.
PMU

Power Management Unit

The PMU is the block that performs overall power supply control of the
CXD5602. Refer to Chapter 3.4.

POR

Power On Reset

The POR is the reset that is enabled when power is supplied.

RCOSC

---

The RCOSC is the internal oscillator block.
Refer to Section 3.5.3.1.

RFRadio Frequency

The RF is the frequency band of the GNSS signal.

RTC

Real Time Clock

For the RTC, refer to Chapter 3.6

SCU

Sensor Domain

The SCU is a block which is equipped with the HPADC, LPADC, and theinterface to the external sensors. For details, refer to Chapter 3.9.

Sleep

---

Sleep is the status that any of the power domains of the CXD5602 becomes OFF,or any of the DSPs belonging to the power domains is not in operation.

SYSCPU

System and I/O Processor

The SYSCPU contains Cortex®-M0+, Interrupt input register, Timer, WDT,SLEEPING signal monitor, and Debug function (ITM).
The Tile address converter and the memory protection unit are equipped outside
the SYSCPU.

SYSIOP

System and IOP Domain

The SYSIOP is the functional block equipped with one Cortex®-M0+, to perform
a variety of controls of the CXD5602, indicated in Section 2.5.2.

SYSPLL---The SYSPLL is the internal PLL. Refer to Section 3.5.3.3.

SYSTEM Bus---

The SYSTEM Bus is the BUS inside the SYSIOP.

SYS SRAM---The SYS SRAM is 256 KByte of SRAM inside the System and IOP Domain.

WakeupWakeup is the status that the power domains of the CXD5602 becomes ON, or
the DSPs belonging to the power domains starts operations.

WDT

Watchdog Timer

The WDT is so called the Watch Dog Timer. It monitors the CPU’s operation.

WFI

Wait For Interrupt

The WFI is the status that the power domains of the CXD5602 is waiting for aninterrupt to enter into sleep mode.

XOSC

X'tal Oscillator

The XOSC is the internal oscillator block.
Refer to Section 3.5.3.2.

Processor---“Processor” means Cortex®-M0+ and Arm® Cortex®-M4 processor with FPU 32
bit RISC in the CXD5602.

－1288/1293－

CXD5602 User Manual

4.2

ReferencePrimeCell® µDMA Controller (PL230) Technical Reference ManualPrimeCell® DMA Controller (PL080) Technical Reference ManualPrimeCell® Single Master DMA Controller (PL081) Technical Reference ManualPrimeCell® Synchronous Serial Port (PL022) Technical Reference ManualPrimeCell® UART (PL011) Technical Reference ManualArm® Cortex®-M4 Processor Technical Reference ManualCortex®-M4 Devices Generic User Guide
ARMv7-M Architecture Reference Manual
AMBA® Design Kit Technical Reference Manual
Synopsys® DesignWare Cores USB 1.1/2.0 Device Subsystem-AHB/VCI databook (USB1.1 Release 2.11a, USB2.0
AHB-VCI 2.45a/VCI 1.93a June 2009)－1289/1293－

CXD5602 User Manual

Revision History
Date

Revision

Description

2019/07/05

1.0.0

Initial version.

2021/02/18

1.0.1

Fixed some link errors.

2022/10/24

1.1.0

Update I2C, SPI, UART, Audio and USB chapters.

－1290/1293－

CXD5602 User Manual

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UNLESS OTHERWISE NOTIFIED BY US IN WRITING, OTHERWISE AGREED BETWEEN THE
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THE PRODUCTS AND THE PRODUCT INFORMATION ARE PROVIDED BY SONY, ITS SUBSIDIARIESAND/OR THEIR AUTHORIZED REPRESENTATIVES "AS IS" AND WITHOUT WARRANTY OF ANY
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ANY WAY INCREASE THE SCOPE OF THIS WARRANTY.
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TO THE EXTENT PERMITTED BY LAW, SONY, ITS SUBSIDIARIES AND/OR THEIR AUTHORIZEDREPRESENTATIVES SHALL NOT BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL
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Compliance with Laws:
Customer shall comply with all applicable laws, ordinances, rules and regulations in connection with the usage of
the Products, including the export control laws or regulations of various countries and shall be fully responsible
for obtaining approvals in connection with the export of the Products in accordance with such said laws,
ordinances, rules and/or regulations.
Governing Law:
This specification and the terms and conditions contained herein shall be governed by and construed inaccordance with the laws of Japan, without reference to principles of conflict of laws or choice of laws. All
controversies and disputes arising out of or relating to this specification and the terms and conditions contained－1292/1293－

CXD5602 User Manual

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relating to the Products contained in this specification may be revised or updated by Sony at Sony’s sole
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－1293/1293－